opcodes/ChangeLog

   1 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
   2
   3         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
   4         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
   5         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
   6         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
   7         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
   8         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
   9         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
  10
  11 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
  12
  13         * disassemble.c (disassemble_init_for_target): Set
  14         created_styled_output for ARC based targets.
  15         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
  16         instead of fprintf_ftype throughout.
  17         (find_format): Likewise.
  18         (print_flags): Likewise.
  19         (print_insn_arc): Likewise.
  20
  21 2022-07-08  Nick Clifton  <nickc@redhat.com>
  22
  23         * 2.39 branch created.
  24
  25 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
  26
  27         * disassemble.c: (disassemble_init_for_target): Set
  28         created_styled_output for AVR based targets.
  29         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
  30         instead of fprintf_ftype throughout.
  31         (avr_operand): Pass in and fill disassembler_style when
  32         parsing operands.
  33
  34 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  35
  36         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
  37         table.
  38
  39 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
  40
  41         * configure.ac: Handle bfd_amdgcn_arch.
  42         * configure: Re-generate.
  43
  44 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
  45             Maciej W. Rozycki  <macro@orcam.me.uk>
  46
  47         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
  48         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
  49         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
  50         "bnez" instructions.
  51
  52 2022-02-17  Nick Clifton  <nickc@redhat.com>
  53
  54         * po/sr.po: Updated Serbian translation.
  55
  56 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
  57
  58         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
  59         * microblaze-opc.h: Follow 'fsqrt' rename.
  60
  61 2022-01-24  Nick Clifton  <nickc@redhat.com>
  62
  63         * po/ro.po: Updated Romanian translation.
  64         * po/uk.po: Updated Ukranian translation.
  65
  66 2022-01-22  Nick Clifton  <nickc@redhat.com>
  67
  68         * configure: Regenerate.
  69         * po/opcodes.pot: Regenerate.
  70
  71 2022-01-22  Nick Clifton  <nickc@redhat.com>
  72
  73         * 2.38 release branch created.
  74
  75 2022-01-17  Nick Clifton  <nickc@redhat.com>
  76
  77         * Makefile.in: Regenerate.
  78         * po/opcodes.pot: Regenerate.
  79
  80 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  81
  82         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  83         in insn_type on branching instructions.
  84
  85 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  86             Simon Cook  <simon.cook@embecosm.com>
  87
  88         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  89         (riscv_options): New static global.
  90         (disassembler_options_riscv): New function.
  91         (print_riscv_disassembler_options): Rewrite to use
  92         disassembler_options_riscv.
  93
  94 2021-11-25  Nick Clifton  <nickc@redhat.com>
  95
  96         PR 28614
  97         * aarch64-asm.c: Replace assert(0) with real code.
  98         * aarch64-dis.c: Likewise.
  99         * aarch64-opc.c: Likewise.
 100
 101 2021-11-25  Nick Clifton  <nickc@redhat.com>
 102
 103         * po/fr.po; Updated French translation.
 104
 105 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 106
 107         * Makefile.am: Remove obsolete comment.
 108         * configure.ac: Refer `libbfd.la' to link shared BFD library
 109         except for Cygwin.
 110         * Makefile.in: Regenerate.
 111         * configure: Regenerate.
 112
 113 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 114
 115         * configure: Regenerate.
 116
 117 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 118
 119         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 120         on POWER5 and later.
 121
 122 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 123
 124         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 125         before an unknown instruction, '%d' is replaced with the
 126         instruction length.
 127
 128 2021-09-02  Nick Clifton  <nickc@redhat.com>
 129
 130         PR 28292
 131         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 132         of BFD_RELOC_16.
 133
 134 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 135
 136         * arc-regs.h (DEF): Fix the register numbers.
 137
 138 2021-08-10  Nick Clifton  <nickc@redhat.com>
 139
 140         * po/sr.po: Updated Serbian translation.
 141
 142 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 143
 144         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 145
 146 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 147
 148         * s390-opc.txt: Add qpaci.
 149
 150 2021-07-03  Nick Clifton  <nickc@redhat.com>
 151
 152         * configure: Regenerate.
 153         * po/opcodes.pot: Regenerate.
 154
 155 2021-07-03  Nick Clifton  <nickc@redhat.com>
 156
 157         * 2.37 release branch created.
 158
 159 2021-07-02  Alan Modra  <amodra@gmail.com>
 160
 161         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 162         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 163         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 164         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 165         (nds32_keyword_gpr): Move declarations to..
 166         * nds32-asm.h: ..here, constifying to match definitions.
 167
 168 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 169
 170         * Makefile.am (GUILE): New variable.
 171         (CGEN): Use $(GUILE).
 172         * Makefile.in: Regenerate.
 173
 174 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 175
 176         * mep-asm.c (macros): Mark static & const.
 177         (lookup_macro): Change return & m to const.
 178         (expand_macro): Change mac to const.
 179         (expand_string): Change pmacro to const.
 180
 181 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 182
 183         * nds32-asm.c (operand_fields): Rename to ...
 184         (nds32_operand_fields): ... this.
 185         (keyword_gpr): Rename to ...
 186         (nds32_keyword_gpr): ... this.
 187         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 188         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 189         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 190         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 191         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 192         Mark static.
 193         (keywords): Rename to ...
 194         (nds32_keywords): ... this.
 195         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 196         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 197
 198 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 199
 200         * z80-dis.c (opc_ed): Make const.
 201         (pref_ed): Make p const.
 202
 203 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 204
 205         * microblaze-dis.c (get_field_special): Make op const.
 206         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 207         microblaze_opcodes.
 208         (print_insn_microblaze): Make op & pop const.
 209         (get_insn_microblaze): Make op const.  Rename opcodes to
 210         microblaze_opcodes.
 211         (microblaze_get_target_address): Likewise.
 212         * microblaze-opc.h (struct op_code_struct): Make const.
 213         Rename opcodes to microblaze_opcodes.
 214
 215 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 216
 217         * aarch64-gen.c (aarch64_opcode_table): Add const.
 218         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 219
 220 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 221
 222         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 223         available.
 224
 225 2021-06-22  Alan Modra  <amodra@gmail.com>
 226
 227         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 228         print separator for pcrel insns.
 229
 230 2021-06-19  Alan Modra  <amodra@gmail.com>
 231
 232         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 233
 234 2021-06-19  Alan Modra  <amodra@gmail.com>
 235
 236         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 237         entire buffer.
 238
 239 2021-06-17  Alan Modra  <amodra@gmail.com>
 240
 241         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 242         in table.
 243
 244 2021-06-03  Alan Modra  <amodra@gmail.com>
 245
 246         PR 1202
 247         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 248         Use unsigned int for inst.
 249
 250 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 251
 252         * arc-dis.c (arc_option_arg_t): New enumeration.
 253         (arc_options): New variable.
 254         (disassembler_options_arc): New function.
 255         (print_arc_disassembler_options): Reimplement in terms of
 256         "disassembler_options_arc".
 257
 258 2021-05-29  Alan Modra  <amodra@gmail.com>
 259
 260         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 261         Don't special case PPC_OPCODE_RAW.
 262         (lookup_prefix): Likewise.
 263         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 264         (print_insn_powerpc): ..update caller.
 265         * ppc-opc.c (EXT): Define.
 266         (powerpc_opcodes): Mark extended mnemonics with EXT.
 267         (prefix_opcodes, vle_opcodes): Likewise.
 268         (XISEL, XISEL_MASK): Add cr field and simplify.
 269         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 270         all isel variants to where the base mnemonic belongs.  Sort dstt,
 271         dststt and dssall.
 272
 273 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 274
 275         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 276         COP3 opcode instructions.
 277
 278 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 279
 280         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 281         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 282         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 283         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 284         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 285         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 286         "cop2", and "cop3" entries.
 287
 288 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 289
 290         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 291         entries and associated comments.
 292
 293 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 294
 295         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 296         of "c0".
 297
 298 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 299
 300         * mips-dis.c (mips_cp1_names_mips): New variable.
 301         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 302         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 303         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 304         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 305         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 306         "loongson2f".
 307
 308 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 309
 310         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 311         handling code over to...
 312         <OP_REG_CONTROL>: ... this new case.
 313         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 314         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 315         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 316         replacing the `G' operand code with `g'.  Update "cftc1" and
 317         "cftc2" entries replacing the `E' operand code with `y'.
 318         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 319         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 320         entries replacing the `G' operand code with `g'.
 321
 322 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 323
 324         * mips-dis.c (mips_cp0_names_r3900): New variable.
 325         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 326         for "r3900".
 327
 328 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 329
 330         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 331         and "mtthc2" to using the `G' rather than `g' operand code for
 332         the coprocessor control register referred.
 333
 334 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 335
 336         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 337         entries with each other.
 338
 339 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 340
 341         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 342
 343 2021-05-25  Alan Modra  <amodra@gmail.com>
 344
 345         * cris-desc.c: Regenerate.
 346         * cris-desc.h: Regenerate.
 347         * cris-opc.h: Regenerate.
 348         * po/POTFILES.in: Regenerate.
 349
 350 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 351
 352         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 353         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 354         (CGEN_CPUS): Add cris.
 355         (CRIS_DEPS): Define.
 356         (stamp-cris): New rule.
 357         * cgen.sh: Handle desc action.
 358         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 359         * Makefile.in, configure: Regenerate.
 360
 361 2021-05-18  Job Noorman  <mtvec@pm.me>
 362
 363         PR 27814
 364         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 365         the elf objects.
 366
 367 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 368
 369         * arm-dis.c (mve_opcodes): Fix disassembly of
 370         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 371         (is_mve_encoding_conflict): MVE vector loads should not match
 372         when P = W = 0.
 373         (is_mve_unpredictable): It's not unpredictable to use the same
 374         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 375
 376 2021-05-11  Nick Clifton  <nickc@redhat.com>
 377
 378         PR 27840
 379         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 380         the end of the code buffer.
 381
 382 2021-05-06  Stafford Horne  <shorne@gmail.com>
 383
 384         PR 21464
 385         * or1k-asm.c: Regenerate.
 386
 387 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 388
 389         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 390         info->insn_info_valid.
 391
 392 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-opc.tbl (lea): Add Optimize.
 395         * opcodes/i386-tbl.h: Re-generate.
 396
 397 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 398
 399         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 400         of l32r fetch and display referenced literal value.
 401
 402 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 403
 404         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 405         to 4 for literal disassembly.
 406
 407 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 408
 409         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 410         for TLBI instruction.
 411
 412 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 413
 414         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 415         DC instruction.
 416
 417 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 418
 419         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 420         "qualifier".
 421         (convert_mov_to_movewide): Add initializer for "value".
 422
 423 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 424
 425         * aarch64-opc.c: Add RME system registers.
 426
 427 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 428
 429         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 430         "addi d,CV,z" to "c.mv d,CV".
 431
 432 2021-04-12  Alan Modra  <amodra@gmail.com>
 433
 434         * configure.ac (--enable-checking): Add support.
 435         * config.in: Regenerate.
 436         * configure: Regenerate.
 437
 438 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 439
 440         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 441         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 442
 443 2021-04-09  Alan Modra  <amodra@gmail.com>
 444
 445         * ppc-dis.c (struct dis_private): Add "special".
 446         (POWERPC_DIALECT): Delete.  Replace uses with..
 447         (private_data): ..this.  New inline function.
 448         (disassemble_init_powerpc): Init "special" names.
 449         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 450         field of prefix instructions.
 451         (bsearch_reloc, print_got_plt): New functions.
 452         (print_insn_powerpc): For pcrel instructions, print target address
 453         and symbol if known, and decode plt and got loads too.
 454
 455 2021-04-08  Alan Modra  <amodra@gmail.com>
 456
 457         PR 27684
 458         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 459
 460 2021-04-08  Alan Modra  <amodra@gmail.com>
 461
 462         PR 27676
 463         * ppc-opc.c (DCBT_EO): Move earlier.
 464         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 465         (powerpc_operands): Add THCT and THDS entries.
 466         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 467
 468 2021-04-06  Alan Modra  <amodra@gmail.com>
 469
 470         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 471         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 472         symbol_at_address_func.
 473
 474 2021-04-05  Alan Modra  <amodra@gmail.com>
 475
 476         * configure.ac: Don't check for limits.h, string.h, strings.h or
 477         stdlib.h.
 478         (AC_ISC_POSIX): Don't invoke.
 479         * sysdep.h: Include stdlib.h and string.h unconditionally.
 480         * i386-opc.h: Include limits.h unconditionally.
 481         * wasm32-dis.c: Likewise.
 482         * cgen-opc.c: Don't include alloca-conf.h.
 483         * config.in: Regenerate.
 484         * configure: Regenerate.
 485
 486 2021-04-01  Martin Liska  <mliska@suse.cz>
 487
 488         * arm-dis.c (strneq): Remove strneq and use startswith.
 489         * cr16-dis.c (print_insn_cr16): Likewise.
 490         * score-dis.c (streq): Likewise.
 491         (strneq): Likewise.
 492         * score7-dis.c (strneq): Likewise.
 493
 494 2021-04-01  Alan Modra  <amodra@gmail.com>
 495
 496         PR 27675
 497         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 498
 499 2021-03-31  Alan Modra  <amodra@gmail.com>
 500
 501         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 502         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 503         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 504         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 505         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 506         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 507         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 508         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 509         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 510         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 511         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 512         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 513         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 514         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 515         and TRUE with true throughout.
 516
 517 2021-03-31  Alan Modra  <amodra@gmail.com>
 518
 519         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 520         * aarch64-dis.h: Likewise.
 521         * aarch64-opc.c: Likewise.
 522         * avr-dis.c: Likewise.
 523         * csky-dis.c: Likewise.
 524         * nds32-asm.c: Likewise.
 525         * nds32-dis.c: Likewise.
 526         * nfp-dis.c: Likewise.
 527         * riscv-dis.c: Likewise.
 528         * s12z-dis.c: Likewise.
 529         * wasm32-dis.c: Likewise.
 530
 531 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 532
 533         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 534         (i386_seg_prefixes): New.
 535         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 536         (i386_seg_prefixes): Declare.
 537
 538 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 541
 542 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 545         * i386-reg.tbl (st): Move down.
 546         (st(0)): Delete. Extend comment.
 547         * i386-tbl.h: Re-generate.
 548
 549 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 552         (cmpsd): Move next to cmps.
 553         (movsd): Move next to movs.
 554         (cmpxchg16b): Move to separate section.
 555         (fisttp, fisttpll): Likewise.
 556         (monitor, mwait): Likewise.
 557         * i386-tbl.h: Re-generate.
 558
 559 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 562         (vpsadbw): Add C.
 563         * i386-tbl.h: Re-generate.
 564
 565 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 568         pclmul, gfni): New templates. Use them wherever possible. Move
 569         SSE4.1 pextrw into respective section.
 570         * i386-tbl.h: Re-generate.
 571
 572 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 575         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 576         "length".
 577         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 578         Convert all of their uses to representation in opcode.
 579
 580 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 583         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 584         value of None. Shrink operands to 3 bits.
 585
 586 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-gen.c (process_i386_opcode_modifier): New parameter
 589         "space".
 590         (output_i386_opcode): New local variable "space". Adjust
 591         process_i386_opcode_modifier() invocation.
 592         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 593         invocation.
 594         * i386-tbl.h: Re-generate.
 595
 596 2021-03-29  Alan Modra  <amodra@gmail.com>
 597
 598         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 599         (fp_qualifier_p, get_data_pattern): Likewise.
 600         (aarch64_get_operand_modifier_from_value): Likewise.
 601         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 602         (operand_variant_qualifier_p): Likewise.
 603         (qualifier_value_in_range_constraint_p): Likewise.
 604         (aarch64_get_qualifier_esize): Likewise.
 605         (aarch64_get_qualifier_nelem): Likewise.
 606         (aarch64_get_qualifier_standard_value): Likewise.
 607         (get_lower_bound, get_upper_bound): Likewise.
 608         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 609         (aarch64_print_operand): Likewise.
 610         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 611         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 612         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 613         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 614         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 615         (print_insn_tic6x): Likewise.
 616
 617 2021-03-29  Alan Modra  <amodra@gmail.com>
 618
 619         * arc-dis.c (extract_operand_value): Correct NULL cast.
 620         * frv-opc.h: Regenerate.
 621
 622 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 623
 624         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 625         MMX form.
 626         * i386-tbl.h: Re-generate.
 627
 628 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 629
 630         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 631         immediate in br.n instruction.
 632
 633 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-dis.c (XMGatherD, VexGatherD): New.
 636         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 637         (print_insn): Check masking for S/G insns.
 638         (OP_E_memory): New local variable check_gather. Extend mandatory
 639         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 640         Extend check for disallowed 16-bit addressing.
 641         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 642         if()s to switch(). Check register conflicts for (VEX-encoded)
 643         gathers. Drop no longer reachable cases.
 644         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 645         vgatherdp*.
 646
 647 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 650         zeroing-masking without masking.
 651
 652 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 655         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 656         single-operand forms as deprecated.
 657         * i386-tbl.h: Re-generate.
 658
 659 2021-03-25  Alan Modra  <amodra@gmail.com>
 660
 661         PR 27647
 662         * ppc-opc.c (XLOCB_MASK): Delete.
 663         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 664         XLBH_MASK.
 665         (powerpc_opcodes): Accept a BH field on all extended forms of
 666         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 667
 668 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-gen.c (output_i386_opcode): Drop processing of
 671         opcode_length. Calculate length from base_opcode. Adjust prefix
 672         encoding determination.
 673         (process_i386_opcodes): Drop output of fake opcode_length.
 674         * i386-opc.h (struct insn_template): Drop opcode_length field.
 675         * i386-opc.tbl: Drop opcode length field from all templates.
 676         * i386-tbl.h: Re-generate.
 677
 678 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 681         parameter "prefix". Drop local variable "regular_encoding".
 682         Record prefix setting / check for consistency.
 683         (output_i386_opcode): Parse opcode_length and base_opcode
 684         earlier. Derive prefix encoding. Drop no longer applicable
 685         consistency checking. Adjust process_i386_opcode_modifier()
 686         invocation.
 687         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 688         invocation.
 689         * i386-tbl.h: Re-generate.
 690
 691 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 694         check.
 695         * i386-opc.h (Prefix_*): Move #define-s.
 696         * i386-opc.tbl: Move pseudo prefix enumerator values to
 697         extension opcode field. Introduce pseudopfx template.
 698         * i386-tbl.h: Re-generate.
 699
 700 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 703         comment.
 704         * i386-tbl.h: Re-generate.
 705
 706 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.h (struct insn_template): Move cpu_flags field past
 709         opcode_modifier one.
 710         * i386-tbl.h: Re-generate.
 711
 712 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 715         * i386-opc.h (OpcodeSpace): New enumerator.
 716         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 717         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 718         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 719         (struct i386_opcode_modifier): New field opcodespace. Shrink
 720         opcodeprefix field.
 721         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 722         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 723         OpcodePrefix uses.
 724         * i386-tbl.h: Re-generate.
 725
 726 2021-03-22  Martin Liska  <mliska@suse.cz>
 727
 728         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 729         * arc-dis.c (parse_option): Likewise.
 730         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 731         * cris-dis.c (print_with_operands): Likewise.
 732         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 733         * i386-dis.c (print_insn): Likewise.
 734         * ia64-gen.c (fetch_insn_class): Likewise.
 735         (parse_resource_users): Likewise.
 736         (in_iclass): Likewise.
 737         (lookup_specifier): Likewise.
 738         (insert_opcode_dependencies): Likewise.
 739         * mips-dis.c (parse_mips_ase_option): Likewise.
 740         (parse_mips_dis_option): Likewise.
 741         * s390-dis.c (disassemble_init_s390): Likewise.
 742         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 743
 744 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 745
 746         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 747
 748 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 749
 750         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 751         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 752
 753 2021-03-12  Alan Modra  <amodra@gmail.com>
 754
 755         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 756
 757 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 758
 759         * i386-dis.c (OP_XMM): Re-order checks.
 760
 761 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-dis.c (putop): Drop need_vex check when also checking
 764         vex.evex.
 765         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 766         checking vex.b.
 767
 768 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 771         checks. Move case label past broadcast check.
 772
 773 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 774
 775         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 776         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 777         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 778         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 779         EVEX_W_0F38C7_M_0_L_2): Delete.
 780         (REG_EVEX_0F38C7_M_0_L_2): New.
 781         (intel_operand_size): Handle VEX and EVEX the same for
 782         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 783         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 784         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 785         vex_vsib_q_w_d_mode uses.
 786         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 787         0F38A1, and 0F38A3 entries.
 788         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 789         entry.
 790         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 791         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 792         0F38A3 entries.
 793
 794 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 795
 796         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 797         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 798         MOD_VEX_0FXOP_09_12): Rename to ...
 799         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 800         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 801         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 802         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 803         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 804         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 805         (reg_table): Adjust comments.
 806         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 807         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 808         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 809         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 810         (vex_len_table): Adjust opcode 0A_12 entry.
 811         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 812         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 813         (rm_table): Move hreset entry.
 814
 815 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 816
 817         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 818         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 819         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 820         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 821         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 822         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 823         (get_valid_dis386): Also handle 512-bit vector length when
 824         vectoring into vex_len_table[].
 825         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 826         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 827         entries.
 828         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 829         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 830         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 831         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 832         entries.
 833
 834 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 835
 836         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 837         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 838         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 839         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 840         entries.
 841         * i386-dis-evex-len.h (evex_len_table): Likewise.
 842         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 843
 844 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 845
 846         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 847         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 848         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 849         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 850         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 851         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 852         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 853         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 854         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 855         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 856         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 857         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 858         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 859         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 860         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 861         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 862         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 863         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 864         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 865         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 866         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 867         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 868         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 869         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 870         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 871         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 872         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 873         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 874         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 875         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 876         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 877         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 878         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 879         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 880         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 881         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 882         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 883         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 884         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 885         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 886         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 887         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 888         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 889         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 890         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 891         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 892         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 893         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 894         EVEX_W_0F3A43_L_n): New.
 895         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 896         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 897         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 898         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 899         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 900         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 901         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 902         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 903         0F385B, 0F38C6, and 0F38C7 entries.
 904         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 905         0F38C6 and 0F38C7.
 906         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 907         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 908         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 909         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 910
 911 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 912
 913         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 914         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 915         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 916         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 917         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 918         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 919         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 920         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 921         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 922         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 923         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 924         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 925         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 926         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 927         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 928         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 929         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 930         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 931         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 932         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 933         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 934         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 935         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 936         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 937         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 938         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 939         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 940         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 941         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 942         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 943         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 944         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 945         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 946         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 947         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 948         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 949         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 950         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 951         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 952         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 953         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 954         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 955         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 956         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 957         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 958         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 959         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 960         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 961         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 962         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 963         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 964         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 965         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 966         VEX_W_0F99_P_2_LEN_0): Delete.
 967         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 968         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 969         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 970         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 971         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 972         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 973         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 974         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 975         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 976         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 977         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 978         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 979         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 980         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 981         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 982         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 983         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 984         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 985         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 986         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 987         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 988         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 989         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 990         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 991         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 992         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 993         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 994         (prefix_table): No longer link to vex_len_table[] for opcodes
 995         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 996         0F92, 0F93, 0F98, and 0F99.
 997         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 998         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 999         0F98, and 0F99.
1000         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1001         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1002         0F98, and 0F99.
1003         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1004         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1005         0F98, and 0F99.
1006         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1007         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1008         0F98, and 0F99.
1009
1010 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1011
1012         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1013         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1014         REG_VEX_0F73_M_0 respectively.
1015         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1016         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1017         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1018         MOD_VEX_0F73_REG_7): Delete.
1019         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1020         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1021         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1022         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1023         PREFIX_VEX_0F3AF0_L_0 respectively.
1024         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1025         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1026         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1027         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1028         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1029         VEX_LEN_0F38F7): New.
1030         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1031         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1032         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1033         0F38F3.
1034         (prefix_table): No longer link to vex_len_table[] for opcodes
1035         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1036         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1037         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1038         0F38F6, 0F38F7, and 0F3AF0.
1039         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1040         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1041         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1042         0F73.
1043
1044 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1045
1046         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1047         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1048         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1049         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1050         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1051         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1052         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1053         73.
1054         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1055         0F72, and 0F73.
1056         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1057         0F73.
1058
1059 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1060
1061         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1062         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1063         (reg_table): Don't link to mod_table[] where not needed. Add
1064         PREFIX_IGNORED to nop entries.
1065         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1066         (mod_table): Add nop entries next to prefetch ones. Drop
1067         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1068         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1069         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1070         PREFIX_OPCODE from endbr* entries.
1071         (get_valid_dis386): Also consider entry's name when zapping
1072         vindex.
1073         (print_insn): Handle PREFIX_IGNORED.
1074
1075 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1076
1077         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1078         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1079         element.
1080         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1081         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1082         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1083         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1084         (struct i386_opcode_modifier): Delete notrackprefixok,
1085         islockable, hleprefixok, and repprefixok fields. Add prefixok
1086         field.
1087         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1088         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1089         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1090         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1091         Replace HLEPrefixOk.
1092         * opcodes/i386-tbl.h: Re-generate.
1093
1094 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1095
1096         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1097         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1098         64-bit form.
1099         * opcodes/i386-tbl.h: Re-generate.
1100
1101 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1102
1103         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1104         for {} instead of {0}. Don't look for '0'.
1105         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1106         size specifiers.
1107
1108 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1109
1110         PR 27158
1111         * riscv-dis.c (print_insn_args): Updated encoding macros.
1112         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1113         (match_c_addi16sp): Updated encoding macros.
1114         (match_c_lui): Likewise.
1115         (match_c_lui_with_hint): Likewise.
1116         (match_c_addi4spn): Likewise.
1117         (match_c_slli): Likewise.
1118         (match_slli_as_c_slli): Likewise.
1119         (match_c_slli64): Likewise.
1120         (match_srxi_as_c_srxi): Likewise.
1121         (riscv_insn_types): Added .insn css/cl/cs.
1122
1123 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1124
1125         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1126         (default_priv_spec): Updated type to riscv_spec_class.
1127         (parse_riscv_dis_option): Updated.
1128         * riscv-opc.c: Moved stuff and make the file tidy.
1129
1130 2021-02-17  Alan Modra  <amodra@gmail.com>
1131
1132         * wasm32-dis.c: Include limits.h.
1133         (CHAR_BIT): Provide backup define.
1134         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1135         Correct signed overflow checking.
1136
1137 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1140         * i386-tbl.h: Re-generate.
1141
1142 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1143
1144         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1145         Oword.
1146         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1147
1148 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1149
1150         * s390-mkopc.c (main): Accept arch14 as cpu string.
1151         * s390-opc.txt: Add new arch14 instructions.
1152
1153 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1154
1155         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1156         favour of LIBINTL.
1157         * configure: Regenerated.
1158
1159 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1160
1161         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1162         * tic54x-opc.c (regs): Rename to ...
1163         (tic54x_regs): ... this.
1164         (mmregs): Rename to ...
1165         (tic54x_mmregs): ... this.
1166         (condition_codes): Rename to ...
1167         (tic54x_condition_codes): ... this.
1168         (cc2_codes): Rename to ...
1169         (tic54x_cc2_codes): ... this.
1170         (cc3_codes): Rename to ...
1171         (tic54x_cc3_codes): ... this.
1172         (status_bits): Rename to ...
1173         (tic54x_status_bits): ... this.
1174         (misc_symbols): Rename to ...
1175         (tic54x_misc_symbols): ... this.
1176
1177 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1178
1179         * riscv-opc.c (MASK_RVB_IMM): Removed.
1180         (riscv_opcodes): Removed zb* instructions.
1181         (riscv_ext_version_table): Removed versions for zb*.
1182
1183 2021-01-26  Alan Modra  <amodra@gmail.com>
1184
1185         * i386-gen.c (parse_template): Ensure entire template_instance
1186         is initialised.
1187
1188 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1189
1190         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1191         (riscv_fpr_names_abi): Likewise.
1192         (riscv_opcodes): Likewise.
1193         (riscv_insn_types): Likewise.
1194
1195 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1196
1197         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1198
1199 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1200
1201         * riscv-dis.c: Comments tidy and improvement.
1202         * riscv-opc.c: Likewise.
1203
1204 2021-01-13  Alan Modra  <amodra@gmail.com>
1205
1206         * Makefile.in: Regenerate.
1207
1208 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1209
1210         PR binutils/26792
1211         * configure.ac: Use GNU_MAKE_JOBSERVER.
1212         * aclocal.m4: Regenerated.
1213         * configure: Likewise.
1214
1215 2021-01-12  Nick Clifton  <nickc@redhat.com>
1216
1217         * po/sr.po: Updated Serbian translation.
1218
1219 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1220
1221         PR ld/27173
1222         * configure: Regenerated.
1223
1224 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1225
1226         * aarch64-asm-2.c: Regenerate.
1227         * aarch64-dis-2.c: Likewise.
1228         * aarch64-opc-2.c: Likewise.
1229         * aarch64-opc.c (aarch64_print_operand):
1230         Delete handling of AARCH64_OPND_CSRE_CSR.
1231         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1232         (CSRE): Likewise.
1233         (_CSRE_INSN): Likewise.
1234         (aarch64_opcode_table): Delete csr.
1235
1236 2021-01-11  Nick Clifton  <nickc@redhat.com>
1237
1238         * po/de.po: Updated German translation.
1239         * po/fr.po: Updated French translation.
1240         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1241         * po/sv.po: Updated Swedish translation.
1242         * po/uk.po: Updated Ukranian translation.
1243
1244 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1245
1246         * configure: Regenerated.
1247
1248 2021-01-09  Nick Clifton  <nickc@redhat.com>
1249
1250         * configure: Regenerate.
1251         * po/opcodes.pot: Regenerate.
1252
1253 2021-01-09  Nick Clifton  <nickc@redhat.com>
1254
1255         * 2.36 release branch crated.
1256
1257 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1258
1259         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1260         (DW, (XRC_MASK): Define.
1261         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1262
1263 2021-01-09  Alan Modra  <amodra@gmail.com>
1264
1265         * configure: Regenerate.
1266
1267 2021-01-08  Nick Clifton  <nickc@redhat.com>
1268
1269         * po/sv.po: Updated Swedish translation.
1270
1271 2021-01-08  Nick Clifton  <nickc@redhat.com>
1272
1273         PR 27129
1274         * aarch64-dis.c (determine_disassembling_preference): Move call to
1275         aarch64_match_operands_constraint outside of the assertion.
1276         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1277         Replace with a return of FALSE.
1278
1279         PR 27139
1280         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1281         core system register.
1282
1283 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1284
1285         * configure: Regenerate.
1286
1287 2021-01-07  Nick Clifton  <nickc@redhat.com>
1288
1289         * po/fr.po: Updated French translation.
1290
1291 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1292
1293         * m68k-opc.c (chkl): Change minimum architecture requirement to
1294         m68020.
1295
1296 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1297
1298         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1299
1300 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1301             Jim Wilson  <jimw@sifive.com>
1302             Andrew Waterman  <andrew@sifive.com>
1303             Maxim Blinov  <maxim.blinov@embecosm.com>
1304             Kito Cheng  <kito.cheng@sifive.com>
1305             Nelson Chu  <nelson.chu@sifive.com>
1306
1307         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1308         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1309
1310 2021-01-01  Alan Modra  <amodra@gmail.com>
1311
1312         Update year range in copyright notice of all files.
1313
1314 For older changes see ChangeLog-2020
1315 \f
1316 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1317
1318 Copying and distribution of this file, with or without modification,
1319 are permitted in any medium without royalty provided the copyright
1320 notice and this notice are preserved.
1321
1322 Local Variables:
1323 mode: change-log
1324 left-margin: 8
1325 fill-column: 74
1326 version-control: never
1327 End: