opcodes/ChangeLog

   1 2006-06-06  Paul Brook  <paul@codesourcery.com>
   2
   3         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
   4         instructions.
   5         (neon_opcodes): Add conditional execution specifiers.
   6         (thumb_opcodes): Ditto.
   7         (thumb32_opcodes): Ditto.
   8         (arm_conditional): Change 0xe to "al" and add "" to end.
   9         (ifthen_state, ifthen_next_state, ifthen_address): New.
  10         (IFTHEN_COND): Define.
  11         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
  12         (print_insn_arm): Change %c to use new values of arm_conditional.
  13         (print_insn_thumb16): Print thumb conditions.  Add %I.
  14         (print_insn_thumb32): Print thumb conditions.
  15         (find_ifthen_state): New function.
  16         (print_insn): Track IT block state.
  17
  18 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  19             Anton Blanchard  <anton@samba.org>
  20             Peter Bergner  <bergner@vnet.ibm.com>
  21
  22         * ppc-dis.c (powerpc_dialect): Handle power6 option.
  23         (print_ppc_disassembler_options): Mention power6.
  24
  25 2006-06-06  Thiemo Seufer  <ths@mips.com>
  26             Chao-ying Fu  <fu@mips.com>
  27
  28         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
  29         * mips-opc.c: Add DSP64 instructions.
  30
  31 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
  32
  33         * m68hc11-dis.c (print_insn): Warning fix.
  34
  35 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
  36
  37         * po/Make-in (top_builddir): Define.
  38
  39 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
  40
  41         * Makefile.am: Run "make dep-am".
  42         * Makefile.in: Regenerate.
  43         * config.in: Regenerate.
  44
  45 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
  46
  47         * Makefile.am (INCLUDES): Use @INCINTL@.
  48         * acinclude.m4: Include new gettext macros.
  49         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
  50         Remove local code for po/Makefile.
  51         * Makefile.in, aclocal.m4, configure: Regenerated.
  52
  53 2006-05-30  Nick Clifton  <nickc@redhat.com>
  54
  55         * po/es.po: Updated Spanish translation.
  56
  57 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  58
  59         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
  60         and fmovem entries.  Put register list entries before immediate
  61         mask entries.  Use "l" rather than "L" in the fmovem entries.
  62         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
  63         out from INFO.
  64         (m68k_scan_mask): New function, split out from...
  65         (print_insn_m68k): ...here.  If no architecture has been set,
  66         first try printing an m680x0 instruction, then try a Coldfire one.
  67
  68 2006-05-24  Nick Clifton  <nickc@redhat.com>
  69
  70         * po/ga.po: Updated Irish translation.
  71
  72 2006-05-22  Nick Clifton  <nickc@redhat.com>
  73
  74         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
  75
  76 2006-05-22  Nick Clifton  <nickc@redhat.com>
  77
  78         * po/nl.po: Updated translation.
  79
  80 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
  81
  82         * avr-dis.c: Formatting fix.
  83
  84 2006-05-14  Thiemo Seufer  <ths@mips.com>
  85
  86         * mips16-opc.c (I1, I32, I64): New shortcut defines.
  87         (mips16_opcodes): Change membership of instructions to their
  88         lowest baseline ISA.
  89
  90 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
  93
  94 2006-05-05  Julian Brown  <julian@codesourcery.com>
  95
  96         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
  97         vldm/vstm.
  98
  99 2006-05-05  Thiemo Seufer  <ths@mips.com>
 100             David Ung  <davidu@mips.com>
 101
 102         * mips-opc.c: Add macro for cache instruction.
 103
 104 2006-05-04  Thiemo Seufer  <ths@mips.com>
 105             Nigel Stephens  <nigel@mips.com>
 106             David Ung  <davidu@mips.com>
 107
 108         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 109         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 110         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 111         MIPS64R2.
 112         * mips-opc.c: fix random typos in comments.
 113         (INSN_SMARTMIPS): New defines.
 114         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 115         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 116         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 117         FP_S and FP_D flags to denote single and double register
 118         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 119         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 120         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 121         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 122         release 2 ISAs.
 123         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 124
 125 2006-05-03  Thiemo Seufer  <ths@mips.com>
 126
 127         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 128
 129 2006-05-02  Thiemo Seufer  <ths@mips.com>
 130             Nigel Stephens  <nigel@mips.com>
 131             David Ung  <davidu@mips.com>
 132
 133         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 134         (print_mips16_insn_arg): Force mips16 to odd addresses.
 135
 136 2006-04-30  Thiemo Seufer  <ths@mips.com>
 137             David Ung  <davidu@mips.com>
 138
 139         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 140         "udi0" to "udi15".
 141         * mips-dis.c (print_insn_args): Adds udi argument handling.
 142
 143 2006-04-28  James E Wilson  <wilson@specifix.com>
 144
 145         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 146         error message.
 147
 148 2006-04-28  Thiemo Seufer  <ths@mips.com>
 149             David Ung  <davidu@mips.com>
 150             Nigel Stephens  <nigel@mips.com>
 151
 152         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 153         names.
 154
 155 2006-04-28  Thiemo Seufer  <ths@mips.com>
 156             Nigel Stephens  <nigel@mips.com>
 157             David Ung  <davidu@mips.com>
 158
 159         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 160         (print_insn_mips):  Adjust print_insn_args call.
 161
 162 2006-04-28  Thiemo Seufer  <ths@mips.com>
 163             Nigel Stephens  <nigel@mips.com>
 164
 165         * mips-dis.c (print_insn_args): Print $fcc only for FP
 166         instructions, use $cc elsewise.
 167
 168 2006-04-28  Thiemo Seufer  <ths@mips.com>
 169             Nigel Stephens  <nigel@mips.com>
 170
 171         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 172         Map MIPS16 registers to O32 names.
 173         (print_mips16_insn_arg): Use mips16_reg_names.
 174
 175 2006-04-26  Julian Brown  <julian@codesourcery.com>
 176
 177         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 178         VMOV.
 179
 180 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 181             Julian Brown  <julian@codesourcery.com>
 182
 183         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 184         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 185         Add unified load/store instruction names.
 186         (neon_opcode_table): New.
 187         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 188         (arm_decode_bitfield): New.
 189         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 190         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 191         (print_insn_neon): New.
 192         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 193         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 194         (print_insn_thumb32): Likewise.
 195
 196 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 197
 198         * Makefile.am: Run "make dep-am".
 199         * Makefile.in: Regenerate.
 200
 201 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 202
 203         * avr-dis.c (avr_operand): Warning fix.
 204
 205         * configure: Regenerate.
 206
 207 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 208
 209         * po/POTFILES.in: Regenerated.
 210
 211 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 212
 213         PR binutils/2454
 214         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 215         the symolic form of an address, so that the output of objdump -d
 216         can be reassembled.
 217
 218 2006-04-10  DJ Delorie  <dj@redhat.com>
 219
 220         * m32c-asm.c: Regenerate.
 221
 222 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 223
 224         * Makefile.am: Add install-html target.
 225         * Makefile.in: Regenerate.
 226
 227 2006-04-06  Nick Clifton  <nickc@redhat.com>
 228
 229         * po/vi/po: Updated Vietnamese translation.
 230
 231 2006-03-31  Paul Koning  <ni1d@arrl.net>
 232
 233         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 234
 235 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 236
 237         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 238         logic to identify halfword shifts.
 239
 240 2006-03-16  Paul Brook  <paul@codesourcery.com>
 241
 242         * arm-dis.c (arm_opcodes): Rename swi to svc.
 243         (thumb_opcodes): Ditto.
 244
 245 2006-03-13  DJ Delorie  <dj@redhat.com>
 246
 247         * m32c-asm.c: Regenerate.
 248         * m32c-desc.c: Likewise.
 249         * m32c-desc.h: Likewise.
 250         * m32c-dis.c: Likewise.
 251         * m32c-ibld.c: Likewise.
 252         * m32c-opc.c: Likewise.
 253         * m32c-opc.h: Likewise.
 254
 255 2006-03-10  DJ Delorie  <dj@redhat.com>
 256
 257         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 258         * m32c-opc.c: Likewise.
 259         * m32c-opc.h: Likewise.
 260
 261
 262 2006-03-09  Nick Clifton  <nickc@redhat.com>
 263
 264         * po/sv.po: Updated Swedish translation.
 265
 266 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         PR binutils/2428
 269         * i386-dis.c (REP_Fixup): New function.
 270         (AL): Remove duplicate.
 271         (Xbr): New.
 272         (Xvr): Likewise.
 273         (Ybr): Likewise.
 274         (Yvr): Likewise.
 275         (indirDXr): Likewise.
 276         (ALr): Likewise.
 277         (eAXr): Likewise.
 278         (dis386): Updated entries of ins, outs, movs, lods and stos.
 279
 280 2006-03-05  Nick Clifton  <nickc@redhat.com>
 281
 282         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 283         signed 32-bit value into an unsigned 32-bit field when the host is
 284         a 64-bit machine.
 285         * fr30-ibld.c: Regenerate.
 286         * frv-ibld.c: Regenerate.
 287         * ip2k-ibld.c: Regenerate.
 288         * iq2000-asm.c: Regenerate.
 289         * iq2000-ibld.c: Regenerate.
 290         * m32c-ibld.c: Regenerate.
 291         * m32r-ibld.c: Regenerate.
 292         * openrisc-ibld.c: Regenerate.
 293         * xc16x-ibld.c: Regenerate.
 294         * xstormy16-ibld.c: Regenerate.
 295
 296 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 297
 298         * xc16x-asm.c: Regenerate.
 299         * xc16x-dis.c: Regenerate.
 300
 301 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 302
 303         * po/Make-in: Add html target.
 304
 305 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 306
 307         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 308         Intel Merom New Instructions.
 309         (THREE_BYTE_0): Likewise.
 310         (THREE_BYTE_1): Likewise.
 311         (three_byte_table): Likewise.
 312         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 313         THREE_BYTE_1 for entry 0x3a.
 314         (twobyte_has_modrm): Updated.
 315         (twobyte_uses_SSE_prefix): Likewise.
 316         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 317         Instructions.
 318
 319 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 320
 321         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 322         (v9_hpriv_reg_names): New table.
 323         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 324         New cases '$' and '%' for read/write hyperprivileged register.
 325         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 326         window handling and rdhpr/wrhpr instructions.
 327
 328 2006-02-24  DJ Delorie  <dj@redhat.com>
 329
 330         * m32c-desc.c: Regenerate with linker relaxation attributes.
 331         * m32c-desc.h: Likewise.
 332         * m32c-dis.c: Likewise.
 333         * m32c-opc.c: Likewise.
 334
 335 2006-02-24  Paul Brook  <paul@codesourcery.com>
 336
 337         * arm-dis.c (arm_opcodes): Add V7 instructions.
 338         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 339         (print_arm_address): New function.
 340         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 341         (psr_name): New function.
 342         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 343
 344 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 345
 346         * ia64-opc-i.c (bXc): New.
 347         (mXc): Likewise.
 348         (OpX2TaTbYaXcC): Likewise.
 349         (TF). Likewise.
 350         (TFCM). Likewise.
 351         (ia64_opcodes_i): Add instructions for tf.
 352
 353         * ia64-opc.h (IMMU5b): New.
 354
 355         * ia64-asmtab.c: Regenerated.
 356
 357 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * ia64-gen.c: Update copyright years.
 360         * ia64-opc-b.c: Likewise.
 361
 362 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         * ia64-gen.c (lookup_regindex): Handle ".vm".
 365         (print_dependency_table): Handle '\"'.
 366
 367         * ia64-ic.tbl: Updated from SDM 2.2.
 368         * ia64-raw.tbl: Likewise.
 369         * ia64-waw.tbl: Likewise.
 370         * ia64-asmtab.c: Regenerated.
 371
 372         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 373
 374 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 375             Anil Paranjape   <anilp1@kpitcummins.com>
 376             Shilin Shakti    <shilins@kpitcummins.com>
 377
 378         * xc16x-desc.h: New file
 379         * xc16x-desc.c: New file
 380         * xc16x-opc.h: New file
 381         * xc16x-opc.c: New file
 382         * xc16x-ibld.c: New file
 383         * xc16x-asm.c: New file
 384         * xc16x-dis.c: New file
 385         * Makefile.am: Entries for xc16x
 386         * Makefile.in: Regenerate
 387         * cofigure.in: Add xc16x target information.
 388         * configure: Regenerate.
 389         * disassemble.c: Add xc16x target information.
 390
 391 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 394         moves.
 395
 396 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         * i386-dis.c ('Z'): Add a new macro.
 399         (dis386_twobyte): Use "movZ" for control register moves.
 400
 401 2006-02-10  Nick Clifton  <nickc@redhat.com>
 402
 403         * iq2000-asm.c: Regenerate.
 404
 405 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 406
 407         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 408
 409 2006-01-26  David Ung  <davidu@mips.com>
 410
 411         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 412         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 413         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 414         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 415         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 416
 417 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 418
 419         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 420         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 421         disassembled.
 422         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 423         buffer overflows when disassembling instructions like
 424         ld (ix+123),0x23
 425         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 426         operand, if the offset is negative.
 427
 428 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 429
 430         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 431         unsigned char to hold data to be disassembled.
 432
 433 2006-01-17  Andreas Schwab  <schwab@suse.de>
 434
 435         PR binutils/1486
 436         * disassemble.c (disassemble_init_for_target): Set
 437         disassembler_needs_relocs for bfd_arch_arm.
 438
 439 2006-01-16  Paul Brook  <paul@codesourcery.com>
 440
 441         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 442         f?add?, and f?sub? instructions.
 443
 444 2006-01-16  Nick Clifton  <nickc@redhat.com>
 445
 446         * po/zh_CN.po: New Chinese (simplified) translation.
 447         * configure.in (ALL_LINGUAS): Add "zh_CH".
 448         * configure: Regenerate.
 449
 450 2006-01-05  Paul Brook  <paul@codesourcery.com>
 451
 452         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 453
 454 2006-01-06  DJ Delorie  <dj@redhat.com>
 455
 456         * m32c-desc.c: Regenerate.
 457         * m32c-opc.c: Regenerate.
 458         * m32c-opc.h: Regenerate.
 459
 460 2006-01-03  DJ Delorie  <dj@redhat.com>
 461
 462         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 463         * m32c-ibld.c: Regenerated.
 464
 465 For older changes see ChangeLog-2005
 466 \f
 467 Local Variables:
 468 mode: change-log
 469 left-margin: 8
 470 fill-column: 74
 471 version-control: never
 472 End: