opcodes/ChangeLog

   1 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   2
   3         * Makefile.am: Change dependencies and rule for
   4         $(srcdir)/i386-init.h.
   5         * Makefile.in: Re-generate.
   6         * i386-gen.c (process_i386_opcodes): New local variable
   7         "marker". Drop opening of input file. Recognize marker and line
   8         number directives.
   9         * i386-opc.tbl (OPCODE_I386_H): Define.
  10         (i386-opc.h): Include it.
  11         (None): Undefine.
  12
  13 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         PR gas/23418
  16         * i386-opc.h (Byte): Update comments.
  17         (Word): Likewise.
  18         (Dword): Likewise.
  19         (Fword): Likewise.
  20         (Qword): Likewise.
  21         (Tbyte): Likewise.
  22         (Xmmword): Likewise.
  23         (Ymmword): Likewise.
  24         (Zmmword): Likewise.
  25         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
  26         vcvttps2uqq.
  27         * i386-tbl.h: Regenerated.
  28
  29 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
  30
  31         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
  32         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
  33         * aarch64-asm-2.c: Regenerate.
  34         * aarch64-dis-2.c: Regenerate.
  35         * aarch64-opc-2.c: Regenerate.
  36
  37 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
  38
  39         PR binutils/23192
  40         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
  41         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
  42         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
  43         sqdmulh, sqrdmulh): Use Em16.
  44
  45 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
  46
  47         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
  48         csdb together with them.
  49         (thumb32_opcodes): Likewise.
  50
  51 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
  54         requiring 32-bit registers as operands 2 and 3. Improve
  55         comments.
  56         (mwait, mwaitx): Fold templates. Improve comments.
  57         OPERAND_TYPE_INOUTPORTREG.
  58         * i386-tbl.h: Re-generate.
  59
  60 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-gen.c (operand_type_init): Remove
  63         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
  64         OPERAND_TYPE_INOUTPORTREG.
  65         * i386-init.h: Re-generate.
  66
  67 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl (wrssd, wrussd): Add Dword.
  70         (wrssq, wrussq): Add Qword.
  71         * i386-tbl.h: Re-generate.
  72
  73 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-opc.h: Rename OTMax to OTNum.
  76         (OTNumOfUints): Adjust calculation.
  77         (OTUnused): Directly alias to OTNum.
  78
  79 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
  80
  81         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
  82         `reg_xys'.
  83         (lea_reg_xys): Likewise.
  84         (print_insn_loop_primitive): Rename `reg' local variable to
  85         `reg_dxy'.
  86
  87 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  88
  89         PR binutils/23242
  90         * aarch64-tbl.h (ldarh): Fix disassembly mask.
  91
  92 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  93
  94         PR binutils/23369
  95         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
  96         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
  97
  98 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
  99
 100         PR tdep/8282
 101         * mips-dis.c (mips_option_arg_t): New enumeration.
 102         (mips_options): New variable.
 103         (disassembler_options_mips): New function.
 104         (print_mips_disassembler_options): Reimplement in terms of
 105         `disassembler_options_mips'.
 106         * arm-dis.c (disassembler_options_arm): Adapt to using the
 107         `disasm_options_and_args_t' structure.
 108         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 109         * s390-dis.c (disassembler_options_s390): Likewise.
 110
 111 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 112
 113         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 114         expected result.
 115         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 116         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 117         * testsuite/ld-arm/tls-longplt.d: Likewise.
 118
 119 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 120
 121         PR binutils/23192
 122         * aarch64-asm-2.c: Regenerate.
 123         * aarch64-dis-2.c: Likewise.
 124         * aarch64-opc-2.c: Likewise.
 125         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 126         * aarch64-opc.c (operand_general_constraint_met_p,
 127         aarch64_print_operand): Likewise.
 128         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 129         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 130         fmlal2, fmlsl2.
 131         (AARCH64_OPERANDS): Add Em2.
 132
 133 2018-06-26  Nick Clifton  <nickc@redhat.com>
 134
 135         * po/uk.po: Updated Ukranian translation.
 136         * po/de.po: Updated German translation.
 137         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 138
 139 2018-06-26  Nick Clifton  <nickc@redhat.com>
 140
 141         * nfp-dis.c: Fix spelling mistake.
 142
 143 2018-06-24  Nick Clifton  <nickc@redhat.com>
 144
 145         * configure: Regenerate.
 146         * po/opcodes.pot: Regenerate.
 147
 148 2018-06-24  Nick Clifton  <nickc@redhat.com>
 149
 150         2.31 branch created.
 151
 152 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 153
 154         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 155         * aarch64-asm-2.c: Regenerate.
 156         * aarch64-dis-2.c: Likewise.
 157
 158 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 159
 160         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 161         `-M ginv' option description.
 162
 163 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 164
 165         PR gas/23305
 166         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 167         la and lla.
 168
 169 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 170
 171         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 172         * configure.ac: Remove AC_PREREQ.
 173         * Makefile.in: Re-generate.
 174         * aclocal.m4: Re-generate.
 175         * configure: Re-generate.
 176
 177 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 178
 179         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 180         mips64r6 descriptors.
 181         (parse_mips_ase_option): Handle -Mginv option.
 182         (print_mips_disassembler_options): Document -Mginv.
 183         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 184         (GINV): New macro.
 185         (mips_opcodes): Define ginvi and ginvt.
 186
 187 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 188             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 189
 190         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 191         * mips-opc.c (CRC, CRC64): New macros.
 192         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 193         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 194         crc32cd for CRC64.
 195
 196 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 197
 198         PR 20319
 199         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 200         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 201
 202 2018-06-06  Alan Modra  <amodra@gmail.com>
 203
 204         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 205         setjmp.  Move init for some other vars later too.
 206
 207 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 208
 209         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 210         (dis_private): Add new fields for property section tracking.
 211         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 212         (xtensa_instruction_fits): New functions.
 213         (fetch_data): Bump minimal fetch size to 4.
 214         (print_insn_xtensa): Make struct dis_private static.
 215         Load and prepare property table on section change.
 216         Don't disassemble literals. Don't disassemble instructions that
 217         cross property table boundaries.
 218
 219 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         * configure: Regenerated.
 222
 223 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 226         * i386-tbl.h: Re-generate.
 227
 228 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-opc.tbl (sldt, str): Add NoRex64.
 231         * i386-tbl.h: Re-generate.
 232
 233 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.tbl (invpcid): Add Oword.
 236         * i386-tbl.h: Re-generate.
 237
 238 2018-06-01  Alan Modra  <amodra@gmail.com>
 239
 240         * sysdep.h (_bfd_error_handler): Don't declare.
 241         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 242         * rl78-decode.opc: Likewise.
 243         * msp430-decode.c: Regenerate.
 244         * rl78-decode.c: Regenerate.
 245
 246 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 247
 248         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 249         * i386-init.h : Regenerated.
 250
 251 2018-05-25  Alan Modra  <amodra@gmail.com>
 252
 253         * Makefile.in: Regenerate.
 254         * po/POTFILES.in: Regenerate.
 255
 256 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 257
 258         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 259         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 260         (insert_bab, extract_bab, insert_btab, extract_btab,
 261         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 262         (BAT, BBA VBA RBS XB6S): Delete macros.
 263         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 264         (BB, BD, RBX, XC6): Update for new macros.
 265         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 266         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 267         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 268         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 269
 270 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 271
 272         * Makefile.am: Add support for s12z architecture.
 273         * configure.ac: Likewise.
 274         * disassemble.c: Likewise.
 275         * disassemble.h: Likewise.
 276         * Makefile.in: Regenerate.
 277         * configure: Regenerate.
 278         * s12z-dis.c: New file.
 279         * s12z.h: New file.
 280
 281 2018-05-18  Alan Modra  <amodra@gmail.com>
 282
 283         * nfp-dis.c: Don't #include libbfd.h.
 284         (init_nfp3200_priv): Use bfd_get_section_contents.
 285         (nit_nfp6000_mecsr_sec): Likewise.
 286
 287 2018-05-17  Nick Clifton  <nickc@redhat.com>
 288
 289         * po/zh_CN.po: Updated simplified Chinese translation.
 290
 291 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 292
 293         PR binutils/23109
 294         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 295         * aarch64-dis-2.c: Regenerate.
 296
 297 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 298
 299         PR binutils/21446
 300         * aarch64-asm.c (opintl.h): Include.
 301         (aarch64_ins_sysreg): Enforce read/write constraints.
 302         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 303         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 304         (F_REG_READ, F_REG_WRITE): New.
 305         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 306         AARCH64_OPND_SYSREG.
 307         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 308         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 309         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 310         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 311         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 312         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 313         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 314         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 315         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 316         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 317         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 318         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 319         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 320         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 321         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 322         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 323         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 324
 325 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 326
 327         PR binutils/21446
 328         * aarch64-dis.c (no_notes: New.
 329         (parse_aarch64_dis_option): Support notes.
 330         (aarch64_decode_insn, print_operands): Likewise.
 331         (print_aarch64_disassembler_options): Document notes.
 332         * aarch64-opc.c (aarch64_print_operand): Support notes.
 333
 334 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 335
 336         PR binutils/21446
 337         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 338         and take error struct.
 339         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 340         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 341         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 342         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 343         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 344         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 345         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 346         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 347         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 348         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 349         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 350         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 351         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 352         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 353         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 354         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 355         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 356         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 357         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 358         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 359         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 360         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 361         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 362         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 363         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 364         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 365         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 366         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 367         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 368         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 369         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 370         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 371         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 372         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 373         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 374         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 375         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 376         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 377         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 378         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 379         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 380         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 381         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 382         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 383         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 384         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 385         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 386         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 387         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 388         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 389         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 390         (determine_disassembling_preference, aarch64_decode_insn,
 391         print_insn_aarch64_word, print_insn_data): Take errors struct.
 392         (print_insn_aarch64): Use errors.
 393         * aarch64-asm-2.c: Regenerate.
 394         * aarch64-dis-2.c: Regenerate.
 395         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 396         boolean in aarch64_insert_operan.
 397         (print_operand_extractor): Likewise.
 398         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 399
 400 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 401
 402         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 403
 404 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 407
 408 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 409
 410         * cr16-opc.c (cr16_instruction): Comment typo fix.
 411         * hppa-dis.c (print_insn_hppa): Likewise.
 412
 413 2018-05-08  Jim Wilson  <jimw@sifive.com>
 414
 415         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 416         (match_c_slli64, match_srxi_as_c_srxi): New.
 417         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 418         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 419         <c.slli, c.srli, c.srai>: Use match_s_slli.
 420         <c.slli64, c.srli64, c.srai64>: New.
 421
 422 2018-05-08  Alan Modra  <amodra@gmail.com>
 423
 424         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 425         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 426         partition opcode space for index lookup.
 427
 428 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 429
 430         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 431         <insn_length>: ...with this.  Update usage.
 432         Remove duplicate call to *info->memory_error_func.
 433
 434 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 435             H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         * i386-dis.c (Gva): New.
 438         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 439         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 440         (prefix_table): New instructions (see prefix above).
 441         (mod_table): New instructions (see prefix above).
 442         (OP_G): Handle va_mode.
 443         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 444         CPU_MOVDIR64B_FLAGS.
 445         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 446         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 447         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 448         * i386-opc.tbl: Add movidir{i,64b}.
 449         * i386-init.h: Regenerated.
 450         * i386-tbl.h: Likewise.
 451
 452 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 455         AddrPrefixOpReg.
 456         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 457         (AddrPrefixOpReg): This.
 458         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 459         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 460
 461 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 462
 463         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 464         (vle_num_opcodes): Likewise.
 465         (spe2_num_opcodes): Likewise.
 466         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 467         initialization loop.
 468         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 469         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 470         only once.
 471
 472 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 473
 474         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 475
 476 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 477
 478         Makefile.am: Added nfp-dis.c.
 479         configure.ac: Added bfd_nfp_arch.
 480         disassemble.h: Added print_insn_nfp prototype.
 481         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 482         nfp-dis.c: New, for NFP support.
 483         po/POTFILES.in: Added nfp-dis.c to the list.
 484         Makefile.in: Regenerate.
 485         configure: Regenerate.
 486
 487 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 490         templates into their base ones.
 491         * i386-tlb.h: Re-generate.
 492
 493 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 496         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 497         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 498         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 499         * i386-init.h: Re-generate.
 500
 501 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 504         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 505         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 506         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 507         comment.
 508         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 509         and CpuRegMask.
 510         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 511         CpuRegMask: Delete.
 512         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 513         cpuregzmm, and cpuregmask.
 514         * i386-init.h: Re-generate.
 515         * i386-tbl.h: Re-generate.
 516
 517 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 520         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 521         * i386-init.h: Re-generate.
 522
 523 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-gen.c (VexImmExt): Delete.
 526         * i386-opc.h (VexImmExt, veximmext): Delete.
 527         * i386-opc.tbl: Drop all VexImmExt uses.
 528         * i386-tlb.h: Re-generate.
 529
 530 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 533         register-only forms.
 534         * i386-tlb.h: Re-generate.
 535
 536 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 537
 538         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 539
 540 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 541
 542         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 543         PREFIX_0F1C.
 544         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 545         (cpu_flags): Add CpuCLDEMOTE.
 546         * i386-init.h: Regenerate.
 547         * i386-opc.h (enum): Add CpuCLDEMOTE,
 548         (i386_cpu_flags): Add cpucldemote.
 549         * i386-opc.tbl: Add cldemote.
 550         * i386-tbl.h: Regenerate.
 551
 552 2018-04-16  Alan Modra  <amodra@gmail.com>
 553
 554         * Makefile.am: Remove sh5 and sh64 support.
 555         * configure.ac: Likewise.
 556         * disassemble.c: Likewise.
 557         * disassemble.h: Likewise.
 558         * sh-dis.c: Likewise.
 559         * sh64-dis.c: Delete.
 560         * sh64-opc.c: Delete.
 561         * sh64-opc.h: Delete.
 562         * Makefile.in: Regenerate.
 563         * configure: Regenerate.
 564         * po/POTFILES.in: Regenerate.
 565
 566 2018-04-16  Alan Modra  <amodra@gmail.com>
 567
 568         * Makefile.am: Remove w65 support.
 569         * configure.ac: Likewise.
 570         * disassemble.c: Likewise.
 571         * disassemble.h: Likewise.
 572         * w65-dis.c: Delete.
 573         * w65-opc.h: Delete.
 574         * Makefile.in: Regenerate.
 575         * configure: Regenerate.
 576         * po/POTFILES.in: Regenerate.
 577
 578 2018-04-16  Alan Modra  <amodra@gmail.com>
 579
 580         * configure.ac: Remove we32k support.
 581         * configure: Regenerate.
 582
 583 2018-04-16  Alan Modra  <amodra@gmail.com>
 584
 585         * Makefile.am: Remove m88k support.
 586         * configure.ac: Likewise.
 587         * disassemble.c: Likewise.
 588         * disassemble.h: Likewise.
 589         * m88k-dis.c: Delete.
 590         * Makefile.in: Regenerate.
 591         * configure: Regenerate.
 592         * po/POTFILES.in: Regenerate.
 593
 594 2018-04-16  Alan Modra  <amodra@gmail.com>
 595
 596         * Makefile.am: Remove i370 support.
 597         * configure.ac: Likewise.
 598         * disassemble.c: Likewise.
 599         * disassemble.h: Likewise.
 600         * i370-dis.c: Delete.
 601         * i370-opc.c: Delete.
 602         * Makefile.in: Regenerate.
 603         * configure: Regenerate.
 604         * po/POTFILES.in: Regenerate.
 605
 606 2018-04-16  Alan Modra  <amodra@gmail.com>
 607
 608         * Makefile.am: Remove h8500 support.
 609         * configure.ac: Likewise.
 610         * disassemble.c: Likewise.
 611         * disassemble.h: Likewise.
 612         * h8500-dis.c: Delete.
 613         * h8500-opc.h: Delete.
 614         * Makefile.in: Regenerate.
 615         * configure: Regenerate.
 616         * po/POTFILES.in: Regenerate.
 617
 618 2018-04-16  Alan Modra  <amodra@gmail.com>
 619
 620         * configure.ac: Remove tahoe support.
 621         * configure: Regenerate.
 622
 623 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 626         umwait.
 627         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 628         64-bit mode.
 629         * i386-tbl.h: Regenerated.
 630
 631 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 632
 633         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 634         PREFIX_MOD_1_0FAE_REG_6.
 635         (va_mode): New.
 636         (OP_E_register): Use va_mode.
 637         * i386-dis-evex.h (prefix_table):
 638         New instructions (see prefixes above).
 639         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 640         (cpu_flags): Likewise.
 641         * i386-opc.h (enum): Likewise.
 642         (i386_cpu_flags): Likewise.
 643         * i386-opc.tbl: Add umonitor, umwait, tpause.
 644         * i386-init.h: Regenerate.
 645         * i386-tbl.h: Likewise.
 646
 647 2018-04-11  Alan Modra  <amodra@gmail.com>
 648
 649         * opcodes/i860-dis.c: Delete.
 650         * opcodes/i960-dis.c: Delete.
 651         * Makefile.am: Remove i860 and i960 support.
 652         * configure.ac: Likewise.
 653         * disassemble.c: Likewise.
 654         * disassemble.h: Likewise.
 655         * Makefile.in: Regenerate.
 656         * configure: Regenerate.
 657         * po/POTFILES.in: Regenerate.
 658
 659 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 660
 661         PR binutils/23025
 662         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 663         to 0.
 664         (print_insn): Clear vex instead of vex.evex.
 665
 666 2018-04-04  Nick Clifton  <nickc@redhat.com>
 667
 668         * po/es.po: Updated Spanish translation.
 669
 670 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-gen.c (opcode_modifiers): Delete VecESize.
 673         * i386-opc.h (VecESize): Delete.
 674         (struct i386_opcode_modifier): Delete vecesize.
 675         * i386-opc.tbl: Drop VecESize.
 676         * i386-tlb.h: Re-generate.
 677
 678 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 681         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 682         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 683         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 684         * i386-tlb.h: Re-generate.
 685
 686 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 689         Fold AVX512 forms
 690         * i386-tlb.h: Re-generate.
 691
 692 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 695         (vex_len_table): Drop Y for vcvt*2si.
 696         (putop): Replace plain 'Y' handling by abort().
 697
 698 2018-03-28  Nick Clifton  <nickc@redhat.com>
 699
 700         PR 22988
 701         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 702         instructions with only a base address register.
 703         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 704         handle AARHC64_OPND_SVE_ADDR_R.
 705         (aarch64_print_operand): Likewise.
 706         * aarch64-asm-2.c: Regenerate.
 707         * aarch64_dis-2.c: Regenerate.
 708         * aarch64-opc-2.c: Regenerate.
 709
 710 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl: Drop VecESize from register only insn forms and
 713         memory forms not allowing broadcast.
 714         * i386-tlb.h: Re-generate.
 715
 716 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 719         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 720         sha256*): Drop Disp<N>.
 721
 722 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-dis.c (EbndS, bnd_swap_mode): New.
 725         (prefix_table): Use EbndS.
 726         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 727         * i386-opc.tbl (bndmov): Move misplaced Load.
 728         * i386-tlb.h: Re-generate.
 729
 730 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 733         templates allowing memory operands and folded ones for register
 734         only flavors.
 735         * i386-tlb.h: Re-generate.
 736
 737 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 740         256-bit templates. Drop redundant leftover Disp<N>.
 741         * i386-tlb.h: Re-generate.
 742
 743 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 744
 745         * riscv-opc.c (riscv_insn_types): New.
 746
 747 2018-03-13  Nick Clifton  <nickc@redhat.com>
 748
 749         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 750
 751 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * i386-opc.tbl: Add Optimize to clr.
 754         * i386-tbl.h: Regenerated.
 755
 756 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 759         * i386-opc.h (OldGcc): Removed.
 760         (i386_opcode_modifier): Remove oldgcc.
 761         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 762         instructions for old (<= 2.8.1) versions of gcc.
 763         * i386-tbl.h: Regenerated.
 764
 765 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.h (EVEXDYN): New.
 768         * i386-opc.tbl: Fold various AVX512VL templates.
 769         * i386-tlb.h: Re-generate.
 770
 771 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 774         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 775         vpexpandd, vpexpandq): Fold AFX512VF templates.
 776         * i386-tlb.h: Re-generate.
 777
 778 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 781         Fold 128- and 256-bit VEX-encoded templates.
 782         * i386-tlb.h: Re-generate.
 783
 784 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 785
 786         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 787         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 788         vpexpandd, vpexpandq): Fold AVX512F templates.
 789         * i386-tlb.h: Re-generate.
 790
 791 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 794         64-bit templates. Drop Disp<N>.
 795         * i386-tlb.h: Re-generate.
 796
 797 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 800         and 256-bit templates.
 801         * i386-tlb.h: Re-generate.
 802
 803 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 806         * i386-tlb.h: Re-generate.
 807
 808 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 811         Drop NoAVX.
 812         * i386-tlb.h: Re-generate.
 813
 814 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 817         * i386-tlb.h: Re-generate.
 818
 819 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-gen.c (opcode_modifiers): Delete FloatD.
 822         * i386-opc.h (FloatD): Delete.
 823         (struct i386_opcode_modifier): Delete floatd.
 824         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 825         FloatD by D.
 826         * i386-tlb.h: Re-generate.
 827
 828 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 831
 832 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 835         * i386-tlb.h: Re-generate.
 836
 837 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 840         forms.
 841         * i386-tlb.h: Re-generate.
 842
 843 2018-03-07  Alan Modra  <amodra@gmail.com>
 844
 845         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 846         bfd_arch_rs6000.
 847         * disassemble.h (print_insn_rs6000): Delete.
 848         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 849         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 850         (print_insn_rs6000): Delete.
 851
 852 2018-03-03  Alan Modra  <amodra@gmail.com>
 853
 854         * sysdep.h (opcodes_error_handler): Define.
 855         (_bfd_error_handler): Declare.
 856         * Makefile.am: Remove stray #.
 857         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 858         EDIT" comment.
 859         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 860         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 861         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 862         opcodes_error_handler to print errors.  Standardize error messages.
 863         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 864         and include opintl.h.
 865         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 866         * i386-gen.c: Standardize error messages.
 867         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 868         * Makefile.in: Regenerate.
 869         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 870         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 871         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 872         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 873         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 874         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 875         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 876         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 877         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 878         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 879         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 880         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 881         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 882
 883 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 886         vpsub[bwdq] instructions.
 887         * i386-tbl.h: Regenerated.
 888
 889 2018-03-01  Alan Modra  <amodra@gmail.com>
 890
 891         * configure.ac (ALL_LINGUAS): Sort.
 892         * configure: Regenerate.
 893
 894 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 895
 896         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 897         macro by assignements.
 898
 899 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         PR gas/22871
 902         * i386-gen.c (opcode_modifiers): Add Optimize.
 903         * i386-opc.h (Optimize): New enum.
 904         (i386_opcode_modifier): Add optimize.
 905         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 906         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 907         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 908         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 909         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 910         vpxord and vpxorq.
 911         * i386-tbl.h: Regenerated.
 912
 913 2018-02-26  Alan Modra  <amodra@gmail.com>
 914
 915         * crx-dis.c (getregliststring): Allocate a large enough buffer
 916         to silence false positive gcc8 warning.
 917
 918 2018-02-22  Shea Levy <shea@shealevy.com>
 919
 920         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 921
 922 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         * i386-opc.tbl: Add {rex},
 925         * i386-tbl.h: Regenerated.
 926
 927 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 928
 929         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 930         (mips16_opcodes): Replace `M' with `m' for "restore".
 931
 932 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 933
 934         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 935
 936 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 937
 938         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 939         variable to `function_index'.
 940
 941 2018-02-13  Nick Clifton  <nickc@redhat.com>
 942
 943         PR 22823
 944         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 945         about truncation of printing.
 946
 947 2018-02-12  Henry Wong <henry@stuffedcow.net>
 948
 949         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 950
 951 2018-02-05  Nick Clifton  <nickc@redhat.com>
 952
 953         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 954
 955 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 956
 957         * i386-dis.c (enum): Add pconfig.
 958         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 959         (cpu_flags): Add CpuPCONFIG.
 960         * i386-opc.h (enum): Add CpuPCONFIG.
 961         (i386_cpu_flags): Add cpupconfig.
 962         * i386-opc.tbl: Add PCONFIG instruction.
 963         * i386-init.h: Regenerate.
 964         * i386-tbl.h: Likewise.
 965
 966 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 967
 968         * i386-dis.c (enum): Add PREFIX_0F09.
 969         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 970         (cpu_flags): Add CpuWBNOINVD.
 971         * i386-opc.h (enum): Add CpuWBNOINVD.
 972         (i386_cpu_flags): Add cpuwbnoinvd.
 973         * i386-opc.tbl: Add WBNOINVD instruction.
 974         * i386-init.h: Regenerate.
 975         * i386-tbl.h: Likewise.
 976
 977 2018-01-17  Jim Wilson  <jimw@sifive.com>
 978
 979         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 980
 981 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 982
 983         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 984         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 985         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 986         (cpu_flags): Add CpuIBT, CpuSHSTK.
 987         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 988         (i386_cpu_flags): Add cpuibt, cpushstk.
 989         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 990         * i386-init.h: Regenerate.
 991         * i386-tbl.h: Likewise.
 992
 993 2018-01-16  Nick Clifton  <nickc@redhat.com>
 994
 995         * po/pt_BR.po: Updated Brazilian Portugese translation.
 996         * po/de.po: Updated German translation.
 997
 998 2018-01-15  Jim Wilson  <jimw@sifive.com>
 999
1000         * riscv-opc.c (match_c_nop): New.
1001         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1002
1003 2018-01-15  Nick Clifton  <nickc@redhat.com>
1004
1005         * po/uk.po: Updated Ukranian translation.
1006
1007 2018-01-13  Nick Clifton  <nickc@redhat.com>
1008
1009         * po/opcodes.pot: Regenerated.
1010
1011 2018-01-13  Nick Clifton  <nickc@redhat.com>
1012
1013         * configure: Regenerate.
1014
1015 2018-01-13  Nick Clifton  <nickc@redhat.com>
1016
1017         2.30 branch created.
1018
1019 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1020
1021         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1022         * i386-tbl.h: Regenerate.
1023
1024 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1027         * i386-tbl.h: Re-generate.
1028
1029 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1030
1031         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1032         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1033         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1034         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1035         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1036         Disp8MemShift of AVX512VL forms.
1037         * i386-tbl.h: Re-generate.
1038
1039 2018-01-09  Jim Wilson  <jimw@sifive.com>
1040
1041         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1042         then the hi_addr value is zero.
1043
1044 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1045
1046         * arm-dis.c (arm_opcodes): Add csdb.
1047         (thumb32_opcodes): Add csdb.
1048
1049 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1050
1051         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1052         * aarch64-asm-2.c: Regenerate.
1053         * aarch64-dis-2.c: Regenerate.
1054         * aarch64-opc-2.c: Regenerate.
1055
1056 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1057
1058         PR gas/22681
1059         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1060         Remove AVX512 vmovd with 64-bit operands.
1061         * i386-tbl.h: Regenerated.
1062
1063 2018-01-05  Jim Wilson  <jimw@sifive.com>
1064
1065         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1066         jalr.
1067
1068 2018-01-03  Alan Modra  <amodra@gmail.com>
1069
1070         Update year range in copyright notice of all files.
1071
1072 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1075         and OPERAND_TYPE_REGZMM entries.
1076
1077 For older changes see ChangeLog-2017
1078 \f
1079 Copyright (C) 2018 Free Software Foundation, Inc.
1080
1081 Copying and distribution of this file, with or without modification,
1082 are permitted in any medium without royalty provided the copyright
1083 notice and this notice are preserved.
1084
1085 Local Variables:
1086 mode: change-log
1087 left-margin: 8
1088 fill-column: 74
1089 version-control: never
1090 End: