opcodes/ChangeLog

   1 2021-04-09  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (struct dis_private): Add "special".
   4         (POWERPC_DIALECT): Delete.  Replace uses with..
   5         (private_data): ..this.  New inline function.
   6         (disassemble_init_powerpc): Init "special" names.
   7         (skip_optional_operands): Add is_pcrel arg, set when detecting R
   8         field of prefix instructions.
   9         (bsearch_reloc, print_got_plt): New functions.
  10         (print_insn_powerpc): For pcrel instructions, print target address
  11         and symbol if known, and decode plt and got loads too.
  12
  13 2021-04-08  Alan Modra  <amodra@gmail.com>
  14
  15         PR 27684
  16         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  17
  18 2021-04-08  Alan Modra  <amodra@gmail.com>
  19
  20         PR 27676
  21         * ppc-opc.c (DCBT_EO): Move earlier.
  22         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  23         (powerpc_operands): Add THCT and THDS entries.
  24         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  25
  26 2021-04-06  Alan Modra  <amodra@gmail.com>
  27
  28         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  29         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  30         symbol_at_address_func.
  31
  32 2021-04-05  Alan Modra  <amodra@gmail.com>
  33
  34         * configure.ac: Don't check for limits.h, string.h, strings.h or
  35         stdlib.h.
  36         (AC_ISC_POSIX): Don't invoke.
  37         * sysdep.h: Include stdlib.h and string.h unconditionally.
  38         * i386-opc.h: Include limits.h unconditionally.
  39         * wasm32-dis.c: Likewise.
  40         * cgen-opc.c: Don't include alloca-conf.h.
  41         * config.in: Regenerate.
  42         * configure: Regenerate.
  43
  44 2021-04-01  Martin Liska  <mliska@suse.cz>
  45
  46         * arm-dis.c (strneq): Remove strneq and use startswith.
  47         * cr16-dis.c (print_insn_cr16): Likewise.
  48         * score-dis.c (streq): Likewise.
  49         (strneq): Likewise.
  50         * score7-dis.c (strneq): Likewise.
  51
  52 2021-04-01  Alan Modra  <amodra@gmail.com>
  53
  54         PR 27675
  55         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  56
  57 2021-03-31  Alan Modra  <amodra@gmail.com>
  58
  59         * sysdep.h (POISON_BFD_BOOLEAN): Define.
  60         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  61         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  62         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  63         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
  64         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
  65         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  66         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  67         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  68         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
  69         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
  70         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
  71         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
  72         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
  73         and TRUE with true throughout.
  74
  75 2021-03-31  Alan Modra  <amodra@gmail.com>
  76
  77         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
  78         * aarch64-dis.h: Likewise.
  79         * aarch64-opc.c: Likewise.
  80         * avr-dis.c: Likewise.
  81         * csky-dis.c: Likewise.
  82         * nds32-asm.c: Likewise.
  83         * nds32-dis.c: Likewise.
  84         * nfp-dis.c: Likewise.
  85         * riscv-dis.c: Likewise.
  86         * s12z-dis.c: Likewise.
  87         * wasm32-dis.c: Likewise.
  88
  89 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  92         (i386_seg_prefixes): New.
  93         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  94         (i386_seg_prefixes): Declare.
  95
  96 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
  99
 100 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 103         * i386-reg.tbl (st): Move down.
 104         (st(0)): Delete. Extend comment.
 105         * i386-tbl.h: Re-generate.
 106
 107 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 110         (cmpsd): Move next to cmps.
 111         (movsd): Move next to movs.
 112         (cmpxchg16b): Move to separate section.
 113         (fisttp, fisttpll): Likewise.
 114         (monitor, mwait): Likewise.
 115         * i386-tbl.h: Re-generate.
 116
 117 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 120         (vpsadbw): Add C.
 121         * i386-tbl.h: Re-generate.
 122
 123 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 126         pclmul, gfni): New templates. Use them wherever possible. Move
 127         SSE4.1 pextrw into respective section.
 128         * i386-tbl.h: Re-generate.
 129
 130 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 133         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 134         "length".
 135         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 136         Convert all of their uses to representation in opcode.
 137
 138 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 141         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 142         value of None. Shrink operands to 3 bits.
 143
 144 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 145
 146         * i386-gen.c (process_i386_opcode_modifier): New parameter
 147         "space".
 148         (output_i386_opcode): New local variable "space". Adjust
 149         process_i386_opcode_modifier() invocation.
 150         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 151         invocation.
 152         * i386-tbl.h: Re-generate.
 153
 154 2021-03-29  Alan Modra  <amodra@gmail.com>
 155
 156         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 157         (fp_qualifier_p, get_data_pattern): Likewise.
 158         (aarch64_get_operand_modifier_from_value): Likewise.
 159         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 160         (operand_variant_qualifier_p): Likewise.
 161         (qualifier_value_in_range_constraint_p): Likewise.
 162         (aarch64_get_qualifier_esize): Likewise.
 163         (aarch64_get_qualifier_nelem): Likewise.
 164         (aarch64_get_qualifier_standard_value): Likewise.
 165         (get_lower_bound, get_upper_bound): Likewise.
 166         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 167         (aarch64_print_operand): Likewise.
 168         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 169         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 170         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 171         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 172         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 173         (print_insn_tic6x): Likewise.
 174
 175 2021-03-29  Alan Modra  <amodra@gmail.com>
 176
 177         * arc-dis.c (extract_operand_value): Correct NULL cast.
 178         * frv-opc.h: Regenerate.
 179
 180 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 183         MMX form.
 184         * i386-tbl.h: Re-generate.
 185
 186 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 187
 188         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 189         immediate in br.n instruction.
 190
 191 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (XMGatherD, VexGatherD): New.
 194         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 195         (print_insn): Check masking for S/G insns.
 196         (OP_E_memory): New local variable check_gather. Extend mandatory
 197         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 198         Extend check for disallowed 16-bit addressing.
 199         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 200         if()s to switch(). Check register conflicts for (VEX-encoded)
 201         gathers. Drop no longer reachable cases.
 202         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 203         vgatherdp*.
 204
 205 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 208         zeroing-masking without masking.
 209
 210 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 213         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 214         single-operand forms as deprecated.
 215         * i386-tbl.h: Re-generate.
 216
 217 2021-03-25  Alan Modra  <amodra@gmail.com>
 218
 219         PR 27647
 220         * ppc-opc.c (XLOCB_MASK): Delete.
 221         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 222         XLBH_MASK.
 223         (powerpc_opcodes): Accept a BH field on all extended forms of
 224         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 225
 226 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-gen.c (output_i386_opcode): Drop processing of
 229         opcode_length. Calculate length from base_opcode. Adjust prefix
 230         encoding determination.
 231         (process_i386_opcodes): Drop output of fake opcode_length.
 232         * i386-opc.h (struct insn_template): Drop opcode_length field.
 233         * i386-opc.tbl: Drop opcode length field from all templates.
 234         * i386-tbl.h: Re-generate.
 235
 236 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 239         parameter "prefix". Drop local variable "regular_encoding".
 240         Record prefix setting / check for consistency.
 241         (output_i386_opcode): Parse opcode_length and base_opcode
 242         earlier. Derive prefix encoding. Drop no longer applicable
 243         consistency checking. Adjust process_i386_opcode_modifier()
 244         invocation.
 245         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 246         invocation.
 247         * i386-tbl.h: Re-generate.
 248
 249 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 252         check.
 253         * i386-opc.h (Prefix_*): Move #define-s.
 254         * i386-opc.tbl: Move pseudo prefix enumerator values to
 255         extension opcode field. Introduce pseudopfx template.
 256         * i386-tbl.h: Re-generate.
 257
 258 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 261         comment.
 262         * i386-tbl.h: Re-generate.
 263
 264 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-opc.h (struct insn_template): Move cpu_flags field past
 267         opcode_modifier one.
 268         * i386-tbl.h: Re-generate.
 269
 270 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 273         * i386-opc.h (OpcodeSpace): New enumerator.
 274         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 275         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 276         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 277         (struct i386_opcode_modifier): New field opcodespace. Shrink
 278         opcodeprefix field.
 279         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 280         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 281         OpcodePrefix uses.
 282         * i386-tbl.h: Re-generate.
 283
 284 2021-03-22  Martin Liska  <mliska@suse.cz>
 285
 286         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 287         * arc-dis.c (parse_option): Likewise.
 288         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 289         * cris-dis.c (print_with_operands): Likewise.
 290         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 291         * i386-dis.c (print_insn): Likewise.
 292         * ia64-gen.c (fetch_insn_class): Likewise.
 293         (parse_resource_users): Likewise.
 294         (in_iclass): Likewise.
 295         (lookup_specifier): Likewise.
 296         (insert_opcode_dependencies): Likewise.
 297         * mips-dis.c (parse_mips_ase_option): Likewise.
 298         (parse_mips_dis_option): Likewise.
 299         * s390-dis.c (disassemble_init_s390): Likewise.
 300         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 301
 302 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 303
 304         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 305
 306 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 307
 308         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 309         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 310
 311 2021-03-12  Alan Modra  <amodra@gmail.com>
 312
 313         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 314
 315 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-dis.c (OP_XMM): Re-order checks.
 318
 319 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-dis.c (putop): Drop need_vex check when also checking
 322         vex.evex.
 323         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 324         checking vex.b.
 325
 326 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 329         checks. Move case label past broadcast check.
 330
 331 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 332
 333         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 334         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 335         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 336         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 337         EVEX_W_0F38C7_M_0_L_2): Delete.
 338         (REG_EVEX_0F38C7_M_0_L_2): New.
 339         (intel_operand_size): Handle VEX and EVEX the same for
 340         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 341         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 342         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 343         vex_vsib_q_w_d_mode uses.
 344         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 345         0F38A1, and 0F38A3 entries.
 346         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 347         entry.
 348         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 349         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 350         0F38A3 entries.
 351
 352 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 353
 354         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 355         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 356         MOD_VEX_0FXOP_09_12): Rename to ...
 357         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 358         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 359         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 360         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 361         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 362         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 363         (reg_table): Adjust comments.
 364         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 365         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 366         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 367         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 368         (vex_len_table): Adjust opcode 0A_12 entry.
 369         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 370         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 371         (rm_table): Move hreset entry.
 372
 373 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 374
 375         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 376         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 377         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 378         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 379         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 380         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 381         (get_valid_dis386): Also handle 512-bit vector length when
 382         vectoring into vex_len_table[].
 383         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 384         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 385         entries.
 386         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 387         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 388         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 389         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 390         entries.
 391
 392 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 393
 394         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 395         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 396         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 397         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 398         entries.
 399         * i386-dis-evex-len.h (evex_len_table): Likewise.
 400         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 401
 402 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 403
 404         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 405         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 406         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 407         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 408         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 409         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 410         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 411         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 412         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 413         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 414         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 415         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 416         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 417         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 418         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 419         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 420         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 421         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 422         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 423         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 424         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 425         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 426         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 427         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 428         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 429         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 430         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 431         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 432         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 433         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 434         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 435         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 436         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 437         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 438         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 439         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 440         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 441         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 442         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 443         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 444         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 445         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 446         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 447         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 448         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 449         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 450         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 451         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 452         EVEX_W_0F3A43_L_n): New.
 453         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 454         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 455         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 456         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 457         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 458         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 459         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 460         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 461         0F385B, 0F38C6, and 0F38C7 entries.
 462         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 463         0F38C6 and 0F38C7.
 464         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 465         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 466         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 467         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 468
 469 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 470
 471         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 472         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 473         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 474         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 475         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 476         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 477         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 478         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 479         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 480         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 481         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 482         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 483         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 484         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 485         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 486         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 487         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 488         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 489         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 490         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 491         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 492         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 493         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 494         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 495         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 496         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 497         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 498         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 499         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 500         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 501         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 502         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 503         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 504         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 505         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 506         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 507         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 508         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 509         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 510         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 511         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 512         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 513         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 514         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 515         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 516         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 517         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 518         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 519         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 520         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 521         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 522         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 523         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 524         VEX_W_0F99_P_2_LEN_0): Delete.
 525         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 526         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 527         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 528         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 529         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 530         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 531         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 532         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 533         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 534         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 535         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 536         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 537         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 538         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 539         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 540         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 541         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 542         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 543         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 544         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 545         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 546         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 547         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 548         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 549         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 550         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 551         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 552         (prefix_table): No longer link to vex_len_table[] for opcodes
 553         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 554         0F92, 0F93, 0F98, and 0F99.
 555         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 556         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 557         0F98, and 0F99.
 558         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 559         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 560         0F98, and 0F99.
 561         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 562         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 563         0F98, and 0F99.
 564         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 565         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 566         0F98, and 0F99.
 567
 568 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 569
 570         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 571         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 572         REG_VEX_0F73_M_0 respectively.
 573         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 574         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 575         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 576         MOD_VEX_0F73_REG_7): Delete.
 577         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 578         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 579         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 580         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 581         PREFIX_VEX_0F3AF0_L_0 respectively.
 582         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 583         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 584         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 585         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 586         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 587         VEX_LEN_0F38F7): New.
 588         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 589         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 590         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 591         0F38F3.
 592         (prefix_table): No longer link to vex_len_table[] for opcodes
 593         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 594         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 595         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 596         0F38F6, 0F38F7, and 0F3AF0.
 597         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 598         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 599         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 600         0F73.
 601
 602 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 603
 604         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 605         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 606         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 607         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 608         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 609         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 610         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 611         73.
 612         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 613         0F72, and 0F73.
 614         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 615         0F73.
 616
 617 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 618
 619         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 620         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 621         (reg_table): Don't link to mod_table[] where not needed. Add
 622         PREFIX_IGNORED to nop entries.
 623         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 624         (mod_table): Add nop entries next to prefetch ones. Drop
 625         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 626         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 627         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 628         PREFIX_OPCODE from endbr* entries.
 629         (get_valid_dis386): Also consider entry's name when zapping
 630         vindex.
 631         (print_insn): Handle PREFIX_IGNORED.
 632
 633 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 634
 635         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 636         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 637         element.
 638         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 639         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 640         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 641         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 642         (struct i386_opcode_modifier): Delete notrackprefixok,
 643         islockable, hleprefixok, and repprefixok fields. Add prefixok
 644         field.
 645         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 646         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 647         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 648         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 649         Replace HLEPrefixOk.
 650         * opcodes/i386-tbl.h: Re-generate.
 651
 652 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 653
 654         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 655         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 656         64-bit form.
 657         * opcodes/i386-tbl.h: Re-generate.
 658
 659 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 662         for {} instead of {0}. Don't look for '0'.
 663         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 664         size specifiers.
 665
 666 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 667
 668         PR 27158
 669         * riscv-dis.c (print_insn_args): Updated encoding macros.
 670         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 671         (match_c_addi16sp): Updated encoding macros.
 672         (match_c_lui): Likewise.
 673         (match_c_lui_with_hint): Likewise.
 674         (match_c_addi4spn): Likewise.
 675         (match_c_slli): Likewise.
 676         (match_slli_as_c_slli): Likewise.
 677         (match_c_slli64): Likewise.
 678         (match_srxi_as_c_srxi): Likewise.
 679         (riscv_insn_types): Added .insn css/cl/cs.
 680
 681 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 682
 683         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 684         (default_priv_spec): Updated type to riscv_spec_class.
 685         (parse_riscv_dis_option): Updated.
 686         * riscv-opc.c: Moved stuff and make the file tidy.
 687
 688 2021-02-17  Alan Modra  <amodra@gmail.com>
 689
 690         * wasm32-dis.c: Include limits.h.
 691         (CHAR_BIT): Provide backup define.
 692         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 693         Correct signed overflow checking.
 694
 695 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 698         * i386-tbl.h: Re-generate.
 699
 700 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 703         Oword.
 704         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 705
 706 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 707
 708         * s390-mkopc.c (main): Accept arch14 as cpu string.
 709         * s390-opc.txt: Add new arch14 instructions.
 710
 711 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 712
 713         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 714         favour of LIBINTL.
 715         * configure: Regenerated.
 716
 717 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 718
 719         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 720         * tic54x-opc.c (regs): Rename to ...
 721         (tic54x_regs): ... this.
 722         (mmregs): Rename to ...
 723         (tic54x_mmregs): ... this.
 724         (condition_codes): Rename to ...
 725         (tic54x_condition_codes): ... this.
 726         (cc2_codes): Rename to ...
 727         (tic54x_cc2_codes): ... this.
 728         (cc3_codes): Rename to ...
 729         (tic54x_cc3_codes): ... this.
 730         (status_bits): Rename to ...
 731         (tic54x_status_bits): ... this.
 732         (misc_symbols): Rename to ...
 733         (tic54x_misc_symbols): ... this.
 734
 735 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 736
 737         * riscv-opc.c (MASK_RVB_IMM): Removed.
 738         (riscv_opcodes): Removed zb* instructions.
 739         (riscv_ext_version_table): Removed versions for zb*.
 740
 741 2021-01-26  Alan Modra  <amodra@gmail.com>
 742
 743         * i386-gen.c (parse_template): Ensure entire template_instance
 744         is initialised.
 745
 746 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 747
 748         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 749         (riscv_fpr_names_abi): Likewise.
 750         (riscv_opcodes): Likewise.
 751         (riscv_insn_types): Likewise.
 752
 753 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 754
 755         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 756
 757 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 758
 759         * riscv-dis.c: Comments tidy and improvement.
 760         * riscv-opc.c: Likewise.
 761
 762 2021-01-13  Alan Modra  <amodra@gmail.com>
 763
 764         * Makefile.in: Regenerate.
 765
 766 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         PR binutils/26792
 769         * configure.ac: Use GNU_MAKE_JOBSERVER.
 770         * aclocal.m4: Regenerated.
 771         * configure: Likewise.
 772
 773 2021-01-12  Nick Clifton  <nickc@redhat.com>
 774
 775         * po/sr.po: Updated Serbian translation.
 776
 777 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         PR ld/27173
 780         * configure: Regenerated.
 781
 782 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 783
 784         * aarch64-asm-2.c: Regenerate.
 785         * aarch64-dis-2.c: Likewise.
 786         * aarch64-opc-2.c: Likewise.
 787         * aarch64-opc.c (aarch64_print_operand):
 788         Delete handling of AARCH64_OPND_CSRE_CSR.
 789         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 790         (CSRE): Likewise.
 791         (_CSRE_INSN): Likewise.
 792         (aarch64_opcode_table): Delete csr.
 793
 794 2021-01-11  Nick Clifton  <nickc@redhat.com>
 795
 796         * po/de.po: Updated German translation.
 797         * po/fr.po: Updated French translation.
 798         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 799         * po/sv.po: Updated Swedish translation.
 800         * po/uk.po: Updated Ukranian translation.
 801
 802 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 803
 804         * configure: Regenerated.
 805
 806 2021-01-09  Nick Clifton  <nickc@redhat.com>
 807
 808         * configure: Regenerate.
 809         * po/opcodes.pot: Regenerate.
 810
 811 2021-01-09  Nick Clifton  <nickc@redhat.com>
 812
 813         * 2.36 release branch crated.
 814
 815 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 816
 817         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 818         (DW, (XRC_MASK): Define.
 819         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 820
 821 2021-01-09  Alan Modra  <amodra@gmail.com>
 822
 823         * configure: Regenerate.
 824
 825 2021-01-08  Nick Clifton  <nickc@redhat.com>
 826
 827         * po/sv.po: Updated Swedish translation.
 828
 829 2021-01-08  Nick Clifton  <nickc@redhat.com>
 830
 831         PR 27129
 832         * aarch64-dis.c (determine_disassembling_preference): Move call to
 833         aarch64_match_operands_constraint outside of the assertion.
 834         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 835         Replace with a return of FALSE.
 836
 837         PR 27139
 838         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 839         core system register.
 840
 841 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 842
 843         * configure: Regenerate.
 844
 845 2021-01-07  Nick Clifton  <nickc@redhat.com>
 846
 847         * po/fr.po: Updated French translation.
 848
 849 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 850
 851         * m68k-opc.c (chkl): Change minimum architecture requirement to
 852         m68020.
 853
 854 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 855
 856         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 857
 858 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 859             Jim Wilson  <jimw@sifive.com>
 860             Andrew Waterman  <andrew@sifive.com>
 861             Maxim Blinov  <maxim.blinov@embecosm.com>
 862             Kito Cheng  <kito.cheng@sifive.com>
 863             Nelson Chu  <nelson.chu@sifive.com>
 864
 865         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 866         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 867
 868 2021-01-01  Alan Modra  <amodra@gmail.com>
 869
 870         Update year range in copyright notice of all files.
 871
 872 For older changes see ChangeLog-2020
 873 \f
 874 Copyright (C) 2021 Free Software Foundation, Inc.
 875
 876 Copying and distribution of this file, with or without modification,
 877 are permitted in any medium without royalty provided the copyright
 878 notice and this notice are preserved.
 879
 880 Local Variables:
 881 mode: change-log
 882 left-margin: 8
 883 fill-column: 74
 884 version-control: never
 885 End: