opcodes/ChangeLog

   1 2018-08-03  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_types): Remove Mem field.
   4         * i386-opc.h (union i386_operand_type): Remove mem field.
   5         * i386-init.h, i386-tbl.h: Re-generate.
   6
   7 2018-08-01  Alan Modra  <amodra@gmail.com>
   8
   9         * po/POTFILES.in: Regenerate.
  10
  11 2018-07-31  Nick Clifton  <nickc@redhat.com>
  12
  13         * po/sv.po: Updated Swedish translation.
  14
  15 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  18         * i386-init.h, i386-tbl.h: Re-generate.
  19
  20 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-opc.h (ZEROING_MASKING) Rename to ...
  23         (DYNAMIC_MASKING): ... this. Adjust comment.
  24         * i386-opc.tbl (MaskingMorZ): Define.
  25         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  26         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  27         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  28         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  29         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  30         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  31         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  32         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  33         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  34
  35 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-opc.tbl: Use element rather than vector size for AVX512*
  38         scatter/gather insns.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  44         (cpu_flags): Drop CpuVREX.
  45         * i386-opc.h (CpuVREX): Delete.
  46         (union i386_cpu_flags): Remove cpuvrex.
  47         * i386-init.h, i386-tbl.h: Re-generate.
  48
  49 2018-07-30  Jim Wilson  <jimw@sifive.com>
  50
  51         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  52         fields.
  53         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  54
  55 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  56
  57         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  58         * Makefile.in: Regenerated.
  59         * configure.ac: Add C-SKY.
  60         * configure: Regenerated.
  61         * csky-dis.c: New file.
  62         * csky-opc.h: New file.
  63         * disassemble.c (ARCH_csky): Define.
  64         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  65         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  66
  67 2018-07-27  Alan Modra  <amodra@gmail.com>
  68
  69         * ppc-opc.c (insert_sprbat): Correct function parameter and
  70         return type.
  71         (extract_sprbat): Likewise, variable too.
  72
  73 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  74             Alan Modra  <amodra@gmail.com>
  75
  76         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  77         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
  78         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
  79         support disjointed BAT.
  80         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
  81         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  82         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  83
  84 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  85             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  86
  87         * i386-gen.c (adjust_broadcast_modifier): New function.
  88         (process_i386_opcode_modifier): Add an argument for operands.
  89         Adjust the Broadcast value based on operands.
  90         (output_i386_opcode): Pass operand_types to
  91         process_i386_opcode_modifier.
  92         (process_i386_opcodes): Pass NULL as operands to
  93         process_i386_opcode_modifier.
  94         * i386-opc.h (BYTE_BROADCAST): New.
  95         (WORD_BROADCAST): Likewise.
  96         (DWORD_BROADCAST): Likewise.
  97         (QWORD_BROADCAST): Likewise.
  98         (i386_opcode_modifier): Expand broadcast to 3 bits.
  99         * i386-tbl.h: Regenerated.
 100
 101 2018-07-24  Alan Modra  <amodra@gmail.com>
 102
 103         PR 23430
 104         * or1k-desc.h: Regenerate.
 105
 106 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 109         vcvtusi2ss, and vcvtusi2sd.
 110         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 111         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 112         * i386-tbl.h: Re-generate.
 113
 114 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 115
 116         * arc-opc.c (extract_w6): Fix extending the sign.
 117
 118 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 119
 120         * arc-tbl.h (vewt): Allow it for ARC EM family.
 121
 122 2018-07-23  Alan Modra  <amodra@gmail.com>
 123
 124         PR 23419
 125         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 126         opcode variants for mtspr/mfspr encodings.
 127
 128 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 129             Maciej W. Rozycki  <macro@mips.com>
 130
 131         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 132         loongson3a descriptors.
 133         (parse_mips_ase_option): Handle -M loongson-mmi option.
 134         (print_mips_disassembler_options): Document -M loongson-mmi.
 135         * mips-opc.c (LMMI): New macro.
 136         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 137         instructions.
 138
 139 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 142         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 143         IgnoreSize and [XYZ]MMword where applicable.
 144         * i386-tbl.h: Re-generate.
 145
 146 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 149         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 150         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 151         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 152         * i386-tbl.h: Re-generate.
 153
 154 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 157         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 158         VPCLMULQDQ templates into their respective AVX512VL counterparts
 159         where possible, using Disp8ShiftVL and CheckRegSize instead of
 160         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 161         * i386-tbl.h: Re-generate.
 162
 163 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 166         AVX512VL counterparts where possible, using Disp8ShiftVL and
 167         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 168         IgnoreSize) as appropriate.
 169         * i386-tbl.h: Re-generate.
 170
 171 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl: Fold AVX512BW templates into their respective
 174         AVX512VL counterparts where possible, using Disp8ShiftVL and
 175         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 176         IgnoreSize) as appropriate.
 177         * i386-tbl.h: Re-generate.
 178
 179 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl: Fold AVX512CD templates into their respective
 182         AVX512VL counterparts where possible, using Disp8ShiftVL and
 183         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 184         IgnoreSize) as appropriate.
 185         * i386-tbl.h: Re-generate.
 186
 187 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-opc.h (DISP8_SHIFT_VL): New.
 190         * i386-opc.tbl (Disp8ShiftVL):  Define.
 191         (various): Fold AVX512VL templates into their respective
 192         AVX512F counterparts where possible, using Disp8ShiftVL and
 193         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 194         IgnoreSize) as appropriate.
 195         * i386-tbl.h: Re-generate.
 196
 197 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 198
 199         * Makefile.am: Change dependencies and rule for
 200         $(srcdir)/i386-init.h.
 201         * Makefile.in: Re-generate.
 202         * i386-gen.c (process_i386_opcodes): New local variable
 203         "marker". Drop opening of input file. Recognize marker and line
 204         number directives.
 205         * i386-opc.tbl (OPCODE_I386_H): Define.
 206         (i386-opc.h): Include it.
 207         (None): Undefine.
 208
 209 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 210
 211         PR gas/23418
 212         * i386-opc.h (Byte): Update comments.
 213         (Word): Likewise.
 214         (Dword): Likewise.
 215         (Fword): Likewise.
 216         (Qword): Likewise.
 217         (Tbyte): Likewise.
 218         (Xmmword): Likewise.
 219         (Ymmword): Likewise.
 220         (Zmmword): Likewise.
 221         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 222         vcvttps2uqq.
 223         * i386-tbl.h: Regenerated.
 224
 225 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 226
 227         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 228         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 229         * aarch64-asm-2.c: Regenerate.
 230         * aarch64-dis-2.c: Regenerate.
 231         * aarch64-opc-2.c: Regenerate.
 232
 233 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 234
 235         PR binutils/23192
 236         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 237         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 238         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 239         sqdmulh, sqrdmulh): Use Em16.
 240
 241 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 242
 243         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 244         csdb together with them.
 245         (thumb32_opcodes): Likewise.
 246
 247 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 250         requiring 32-bit registers as operands 2 and 3. Improve
 251         comments.
 252         (mwait, mwaitx): Fold templates. Improve comments.
 253         OPERAND_TYPE_INOUTPORTREG.
 254         * i386-tbl.h: Re-generate.
 255
 256 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-gen.c (operand_type_init): Remove
 259         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 260         OPERAND_TYPE_INOUTPORTREG.
 261         * i386-init.h: Re-generate.
 262
 263 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 266         (wrssq, wrussq): Add Qword.
 267         * i386-tbl.h: Re-generate.
 268
 269 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.h: Rename OTMax to OTNum.
 272         (OTNumOfUints): Adjust calculation.
 273         (OTUnused): Directly alias to OTNum.
 274
 275 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 276
 277         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 278         `reg_xys'.
 279         (lea_reg_xys): Likewise.
 280         (print_insn_loop_primitive): Rename `reg' local variable to
 281         `reg_dxy'.
 282
 283 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 284
 285         PR binutils/23242
 286         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 287
 288 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 289
 290         PR binutils/23369
 291         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 292         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 293
 294 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 295
 296         PR tdep/8282
 297         * mips-dis.c (mips_option_arg_t): New enumeration.
 298         (mips_options): New variable.
 299         (disassembler_options_mips): New function.
 300         (print_mips_disassembler_options): Reimplement in terms of
 301         `disassembler_options_mips'.
 302         * arm-dis.c (disassembler_options_arm): Adapt to using the
 303         `disasm_options_and_args_t' structure.
 304         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 305         * s390-dis.c (disassembler_options_s390): Likewise.
 306
 307 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 308
 309         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 310         expected result.
 311         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 312         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 313         * testsuite/ld-arm/tls-longplt.d: Likewise.
 314
 315 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 316
 317         PR binutils/23192
 318         * aarch64-asm-2.c: Regenerate.
 319         * aarch64-dis-2.c: Likewise.
 320         * aarch64-opc-2.c: Likewise.
 321         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 322         * aarch64-opc.c (operand_general_constraint_met_p,
 323         aarch64_print_operand): Likewise.
 324         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 325         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 326         fmlal2, fmlsl2.
 327         (AARCH64_OPERANDS): Add Em2.
 328
 329 2018-06-26  Nick Clifton  <nickc@redhat.com>
 330
 331         * po/uk.po: Updated Ukranian translation.
 332         * po/de.po: Updated German translation.
 333         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 334
 335 2018-06-26  Nick Clifton  <nickc@redhat.com>
 336
 337         * nfp-dis.c: Fix spelling mistake.
 338
 339 2018-06-24  Nick Clifton  <nickc@redhat.com>
 340
 341         * configure: Regenerate.
 342         * po/opcodes.pot: Regenerate.
 343
 344 2018-06-24  Nick Clifton  <nickc@redhat.com>
 345
 346         2.31 branch created.
 347
 348 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 349
 350         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 351         * aarch64-asm-2.c: Regenerate.
 352         * aarch64-dis-2.c: Likewise.
 353
 354 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 355
 356         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 357         `-M ginv' option description.
 358
 359 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 360
 361         PR gas/23305
 362         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 363         la and lla.
 364
 365 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 366
 367         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 368         * configure.ac: Remove AC_PREREQ.
 369         * Makefile.in: Re-generate.
 370         * aclocal.m4: Re-generate.
 371         * configure: Re-generate.
 372
 373 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 374
 375         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 376         mips64r6 descriptors.
 377         (parse_mips_ase_option): Handle -Mginv option.
 378         (print_mips_disassembler_options): Document -Mginv.
 379         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 380         (GINV): New macro.
 381         (mips_opcodes): Define ginvi and ginvt.
 382
 383 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 384             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 385
 386         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 387         * mips-opc.c (CRC, CRC64): New macros.
 388         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 389         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 390         crc32cd for CRC64.
 391
 392 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 393
 394         PR 20319
 395         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 396         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 397
 398 2018-06-06  Alan Modra  <amodra@gmail.com>
 399
 400         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 401         setjmp.  Move init for some other vars later too.
 402
 403 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 404
 405         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 406         (dis_private): Add new fields for property section tracking.
 407         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 408         (xtensa_instruction_fits): New functions.
 409         (fetch_data): Bump minimal fetch size to 4.
 410         (print_insn_xtensa): Make struct dis_private static.
 411         Load and prepare property table on section change.
 412         Don't disassemble literals. Don't disassemble instructions that
 413         cross property table boundaries.
 414
 415 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 416
 417         * configure: Regenerated.
 418
 419 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 422         * i386-tbl.h: Re-generate.
 423
 424 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-opc.tbl (sldt, str): Add NoRex64.
 427         * i386-tbl.h: Re-generate.
 428
 429 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 430
 431         * i386-opc.tbl (invpcid): Add Oword.
 432         * i386-tbl.h: Re-generate.
 433
 434 2018-06-01  Alan Modra  <amodra@gmail.com>
 435
 436         * sysdep.h (_bfd_error_handler): Don't declare.
 437         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 438         * rl78-decode.opc: Likewise.
 439         * msp430-decode.c: Regenerate.
 440         * rl78-decode.c: Regenerate.
 441
 442 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 443
 444         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 445         * i386-init.h : Regenerated.
 446
 447 2018-05-25  Alan Modra  <amodra@gmail.com>
 448
 449         * Makefile.in: Regenerate.
 450         * po/POTFILES.in: Regenerate.
 451
 452 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 453
 454         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 455         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 456         (insert_bab, extract_bab, insert_btab, extract_btab,
 457         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 458         (BAT, BBA VBA RBS XB6S): Delete macros.
 459         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 460         (BB, BD, RBX, XC6): Update for new macros.
 461         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 462         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 463         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 464         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 465
 466 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 467
 468         * Makefile.am: Add support for s12z architecture.
 469         * configure.ac: Likewise.
 470         * disassemble.c: Likewise.
 471         * disassemble.h: Likewise.
 472         * Makefile.in: Regenerate.
 473         * configure: Regenerate.
 474         * s12z-dis.c: New file.
 475         * s12z.h: New file.
 476
 477 2018-05-18  Alan Modra  <amodra@gmail.com>
 478
 479         * nfp-dis.c: Don't #include libbfd.h.
 480         (init_nfp3200_priv): Use bfd_get_section_contents.
 481         (nit_nfp6000_mecsr_sec): Likewise.
 482
 483 2018-05-17  Nick Clifton  <nickc@redhat.com>
 484
 485         * po/zh_CN.po: Updated simplified Chinese translation.
 486
 487 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 488
 489         PR binutils/23109
 490         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 491         * aarch64-dis-2.c: Regenerate.
 492
 493 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 494
 495         PR binutils/21446
 496         * aarch64-asm.c (opintl.h): Include.
 497         (aarch64_ins_sysreg): Enforce read/write constraints.
 498         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 499         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 500         (F_REG_READ, F_REG_WRITE): New.
 501         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 502         AARCH64_OPND_SYSREG.
 503         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 504         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 505         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 506         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 507         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 508         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 509         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 510         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 511         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 512         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 513         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 514         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 515         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 516         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 517         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 518         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 519         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 520
 521 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 522
 523         PR binutils/21446
 524         * aarch64-dis.c (no_notes: New.
 525         (parse_aarch64_dis_option): Support notes.
 526         (aarch64_decode_insn, print_operands): Likewise.
 527         (print_aarch64_disassembler_options): Document notes.
 528         * aarch64-opc.c (aarch64_print_operand): Support notes.
 529
 530 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 531
 532         PR binutils/21446
 533         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 534         and take error struct.
 535         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 536         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 537         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 538         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 539         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 540         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 541         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 542         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 543         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 544         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 545         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 546         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 547         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 548         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 549         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 550         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 551         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 552         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 553         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 554         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 555         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 556         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 557         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 558         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 559         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 560         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 561         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 562         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 563         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 564         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 565         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 566         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 567         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 568         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 569         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 570         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 571         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 572         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 573         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 574         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 575         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 576         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 577         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 578         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 579         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 580         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 581         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 582         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 583         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 584         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 585         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 586         (determine_disassembling_preference, aarch64_decode_insn,
 587         print_insn_aarch64_word, print_insn_data): Take errors struct.
 588         (print_insn_aarch64): Use errors.
 589         * aarch64-asm-2.c: Regenerate.
 590         * aarch64-dis-2.c: Regenerate.
 591         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 592         boolean in aarch64_insert_operan.
 593         (print_operand_extractor): Likewise.
 594         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 595
 596 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 597
 598         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 599
 600 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 603
 604 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 605
 606         * cr16-opc.c (cr16_instruction): Comment typo fix.
 607         * hppa-dis.c (print_insn_hppa): Likewise.
 608
 609 2018-05-08  Jim Wilson  <jimw@sifive.com>
 610
 611         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 612         (match_c_slli64, match_srxi_as_c_srxi): New.
 613         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 614         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 615         <c.slli, c.srli, c.srai>: Use match_s_slli.
 616         <c.slli64, c.srli64, c.srai64>: New.
 617
 618 2018-05-08  Alan Modra  <amodra@gmail.com>
 619
 620         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 621         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 622         partition opcode space for index lookup.
 623
 624 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 625
 626         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 627         <insn_length>: ...with this.  Update usage.
 628         Remove duplicate call to *info->memory_error_func.
 629
 630 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 631             H.J. Lu  <hongjiu.lu@intel.com>
 632
 633         * i386-dis.c (Gva): New.
 634         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 635         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 636         (prefix_table): New instructions (see prefix above).
 637         (mod_table): New instructions (see prefix above).
 638         (OP_G): Handle va_mode.
 639         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 640         CPU_MOVDIR64B_FLAGS.
 641         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 642         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 643         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 644         * i386-opc.tbl: Add movidir{i,64b}.
 645         * i386-init.h: Regenerated.
 646         * i386-tbl.h: Likewise.
 647
 648 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 651         AddrPrefixOpReg.
 652         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 653         (AddrPrefixOpReg): This.
 654         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 655         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 656
 657 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 658
 659         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 660         (vle_num_opcodes): Likewise.
 661         (spe2_num_opcodes): Likewise.
 662         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 663         initialization loop.
 664         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 665         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 666         only once.
 667
 668 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 669
 670         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 671
 672 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 673
 674         Makefile.am: Added nfp-dis.c.
 675         configure.ac: Added bfd_nfp_arch.
 676         disassemble.h: Added print_insn_nfp prototype.
 677         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 678         nfp-dis.c: New, for NFP support.
 679         po/POTFILES.in: Added nfp-dis.c to the list.
 680         Makefile.in: Regenerate.
 681         configure: Regenerate.
 682
 683 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 684
 685         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 686         templates into their base ones.
 687         * i386-tlb.h: Re-generate.
 688
 689 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 692         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 693         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 694         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 695         * i386-init.h: Re-generate.
 696
 697 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 700         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 701         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 702         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 703         comment.
 704         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 705         and CpuRegMask.
 706         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 707         CpuRegMask: Delete.
 708         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 709         cpuregzmm, and cpuregmask.
 710         * i386-init.h: Re-generate.
 711         * i386-tbl.h: Re-generate.
 712
 713 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 716         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 717         * i386-init.h: Re-generate.
 718
 719 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-gen.c (VexImmExt): Delete.
 722         * i386-opc.h (VexImmExt, veximmext): Delete.
 723         * i386-opc.tbl: Drop all VexImmExt uses.
 724         * i386-tlb.h: Re-generate.
 725
 726 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 729         register-only forms.
 730         * i386-tlb.h: Re-generate.
 731
 732 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 733
 734         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 735
 736 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 737
 738         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 739         PREFIX_0F1C.
 740         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 741         (cpu_flags): Add CpuCLDEMOTE.
 742         * i386-init.h: Regenerate.
 743         * i386-opc.h (enum): Add CpuCLDEMOTE,
 744         (i386_cpu_flags): Add cpucldemote.
 745         * i386-opc.tbl: Add cldemote.
 746         * i386-tbl.h: Regenerate.
 747
 748 2018-04-16  Alan Modra  <amodra@gmail.com>
 749
 750         * Makefile.am: Remove sh5 and sh64 support.
 751         * configure.ac: Likewise.
 752         * disassemble.c: Likewise.
 753         * disassemble.h: Likewise.
 754         * sh-dis.c: Likewise.
 755         * sh64-dis.c: Delete.
 756         * sh64-opc.c: Delete.
 757         * sh64-opc.h: Delete.
 758         * Makefile.in: Regenerate.
 759         * configure: Regenerate.
 760         * po/POTFILES.in: Regenerate.
 761
 762 2018-04-16  Alan Modra  <amodra@gmail.com>
 763
 764         * Makefile.am: Remove w65 support.
 765         * configure.ac: Likewise.
 766         * disassemble.c: Likewise.
 767         * disassemble.h: Likewise.
 768         * w65-dis.c: Delete.
 769         * w65-opc.h: Delete.
 770         * Makefile.in: Regenerate.
 771         * configure: Regenerate.
 772         * po/POTFILES.in: Regenerate.
 773
 774 2018-04-16  Alan Modra  <amodra@gmail.com>
 775
 776         * configure.ac: Remove we32k support.
 777         * configure: Regenerate.
 778
 779 2018-04-16  Alan Modra  <amodra@gmail.com>
 780
 781         * Makefile.am: Remove m88k support.
 782         * configure.ac: Likewise.
 783         * disassemble.c: Likewise.
 784         * disassemble.h: Likewise.
 785         * m88k-dis.c: Delete.
 786         * Makefile.in: Regenerate.
 787         * configure: Regenerate.
 788         * po/POTFILES.in: Regenerate.
 789
 790 2018-04-16  Alan Modra  <amodra@gmail.com>
 791
 792         * Makefile.am: Remove i370 support.
 793         * configure.ac: Likewise.
 794         * disassemble.c: Likewise.
 795         * disassemble.h: Likewise.
 796         * i370-dis.c: Delete.
 797         * i370-opc.c: Delete.
 798         * Makefile.in: Regenerate.
 799         * configure: Regenerate.
 800         * po/POTFILES.in: Regenerate.
 801
 802 2018-04-16  Alan Modra  <amodra@gmail.com>
 803
 804         * Makefile.am: Remove h8500 support.
 805         * configure.ac: Likewise.
 806         * disassemble.c: Likewise.
 807         * disassemble.h: Likewise.
 808         * h8500-dis.c: Delete.
 809         * h8500-opc.h: Delete.
 810         * Makefile.in: Regenerate.
 811         * configure: Regenerate.
 812         * po/POTFILES.in: Regenerate.
 813
 814 2018-04-16  Alan Modra  <amodra@gmail.com>
 815
 816         * configure.ac: Remove tahoe support.
 817         * configure: Regenerate.
 818
 819 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 820
 821         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 822         umwait.
 823         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 824         64-bit mode.
 825         * i386-tbl.h: Regenerated.
 826
 827 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 828
 829         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 830         PREFIX_MOD_1_0FAE_REG_6.
 831         (va_mode): New.
 832         (OP_E_register): Use va_mode.
 833         * i386-dis-evex.h (prefix_table):
 834         New instructions (see prefixes above).
 835         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 836         (cpu_flags): Likewise.
 837         * i386-opc.h (enum): Likewise.
 838         (i386_cpu_flags): Likewise.
 839         * i386-opc.tbl: Add umonitor, umwait, tpause.
 840         * i386-init.h: Regenerate.
 841         * i386-tbl.h: Likewise.
 842
 843 2018-04-11  Alan Modra  <amodra@gmail.com>
 844
 845         * opcodes/i860-dis.c: Delete.
 846         * opcodes/i960-dis.c: Delete.
 847         * Makefile.am: Remove i860 and i960 support.
 848         * configure.ac: Likewise.
 849         * disassemble.c: Likewise.
 850         * disassemble.h: Likewise.
 851         * Makefile.in: Regenerate.
 852         * configure: Regenerate.
 853         * po/POTFILES.in: Regenerate.
 854
 855 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         PR binutils/23025
 858         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 859         to 0.
 860         (print_insn): Clear vex instead of vex.evex.
 861
 862 2018-04-04  Nick Clifton  <nickc@redhat.com>
 863
 864         * po/es.po: Updated Spanish translation.
 865
 866 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-gen.c (opcode_modifiers): Delete VecESize.
 869         * i386-opc.h (VecESize): Delete.
 870         (struct i386_opcode_modifier): Delete vecesize.
 871         * i386-opc.tbl: Drop VecESize.
 872         * i386-tlb.h: Re-generate.
 873
 874 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 877         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 878         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 879         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 880         * i386-tlb.h: Re-generate.
 881
 882 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 885         Fold AVX512 forms
 886         * i386-tlb.h: Re-generate.
 887
 888 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 891         (vex_len_table): Drop Y for vcvt*2si.
 892         (putop): Replace plain 'Y' handling by abort().
 893
 894 2018-03-28  Nick Clifton  <nickc@redhat.com>
 895
 896         PR 22988
 897         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 898         instructions with only a base address register.
 899         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 900         handle AARHC64_OPND_SVE_ADDR_R.
 901         (aarch64_print_operand): Likewise.
 902         * aarch64-asm-2.c: Regenerate.
 903         * aarch64_dis-2.c: Regenerate.
 904         * aarch64-opc-2.c: Regenerate.
 905
 906 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-opc.tbl: Drop VecESize from register only insn forms and
 909         memory forms not allowing broadcast.
 910         * i386-tlb.h: Re-generate.
 911
 912 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 915         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 916         sha256*): Drop Disp<N>.
 917
 918 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-dis.c (EbndS, bnd_swap_mode): New.
 921         (prefix_table): Use EbndS.
 922         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 923         * i386-opc.tbl (bndmov): Move misplaced Load.
 924         * i386-tlb.h: Re-generate.
 925
 926 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 929         templates allowing memory operands and folded ones for register
 930         only flavors.
 931         * i386-tlb.h: Re-generate.
 932
 933 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 936         256-bit templates. Drop redundant leftover Disp<N>.
 937         * i386-tlb.h: Re-generate.
 938
 939 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 940
 941         * riscv-opc.c (riscv_insn_types): New.
 942
 943 2018-03-13  Nick Clifton  <nickc@redhat.com>
 944
 945         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 946
 947 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * i386-opc.tbl: Add Optimize to clr.
 950         * i386-tbl.h: Regenerated.
 951
 952 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 955         * i386-opc.h (OldGcc): Removed.
 956         (i386_opcode_modifier): Remove oldgcc.
 957         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 958         instructions for old (<= 2.8.1) versions of gcc.
 959         * i386-tbl.h: Regenerated.
 960
 961 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-opc.h (EVEXDYN): New.
 964         * i386-opc.tbl: Fold various AVX512VL templates.
 965         * i386-tlb.h: Re-generate.
 966
 967 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 968
 969         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 970         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 971         vpexpandd, vpexpandq): Fold AFX512VF templates.
 972         * i386-tlb.h: Re-generate.
 973
 974 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 977         Fold 128- and 256-bit VEX-encoded templates.
 978         * i386-tlb.h: Re-generate.
 979
 980 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 981
 982         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 983         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 984         vpexpandd, vpexpandq): Fold AVX512F templates.
 985         * i386-tlb.h: Re-generate.
 986
 987 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 990         64-bit templates. Drop Disp<N>.
 991         * i386-tlb.h: Re-generate.
 992
 993 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 994
 995         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 996         and 256-bit templates.
 997         * i386-tlb.h: Re-generate.
 998
 999 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1002         * i386-tlb.h: Re-generate.
1003
1004 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1007         Drop NoAVX.
1008         * i386-tlb.h: Re-generate.
1009
1010 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1013         * i386-tlb.h: Re-generate.
1014
1015 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-gen.c (opcode_modifiers): Delete FloatD.
1018         * i386-opc.h (FloatD): Delete.
1019         (struct i386_opcode_modifier): Delete floatd.
1020         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1021         FloatD by D.
1022         * i386-tlb.h: Re-generate.
1023
1024 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1027
1028 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1029
1030         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1031         * i386-tlb.h: Re-generate.
1032
1033 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1036         forms.
1037         * i386-tlb.h: Re-generate.
1038
1039 2018-03-07  Alan Modra  <amodra@gmail.com>
1040
1041         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1042         bfd_arch_rs6000.
1043         * disassemble.h (print_insn_rs6000): Delete.
1044         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1045         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1046         (print_insn_rs6000): Delete.
1047
1048 2018-03-03  Alan Modra  <amodra@gmail.com>
1049
1050         * sysdep.h (opcodes_error_handler): Define.
1051         (_bfd_error_handler): Declare.
1052         * Makefile.am: Remove stray #.
1053         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1054         EDIT" comment.
1055         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1056         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1057         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1058         opcodes_error_handler to print errors.  Standardize error messages.
1059         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1060         and include opintl.h.
1061         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1062         * i386-gen.c: Standardize error messages.
1063         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1064         * Makefile.in: Regenerate.
1065         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1066         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1067         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1068         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1069         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1070         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1071         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1072         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1073         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1074         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1075         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1076         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1077         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1078
1079 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1080
1081         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1082         vpsub[bwdq] instructions.
1083         * i386-tbl.h: Regenerated.
1084
1085 2018-03-01  Alan Modra  <amodra@gmail.com>
1086
1087         * configure.ac (ALL_LINGUAS): Sort.
1088         * configure: Regenerate.
1089
1090 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1091
1092         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1093         macro by assignements.
1094
1095 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1096
1097         PR gas/22871
1098         * i386-gen.c (opcode_modifiers): Add Optimize.
1099         * i386-opc.h (Optimize): New enum.
1100         (i386_opcode_modifier): Add optimize.
1101         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1102         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1103         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1104         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1105         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1106         vpxord and vpxorq.
1107         * i386-tbl.h: Regenerated.
1108
1109 2018-02-26  Alan Modra  <amodra@gmail.com>
1110
1111         * crx-dis.c (getregliststring): Allocate a large enough buffer
1112         to silence false positive gcc8 warning.
1113
1114 2018-02-22  Shea Levy <shea@shealevy.com>
1115
1116         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1117
1118 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         * i386-opc.tbl: Add {rex},
1121         * i386-tbl.h: Regenerated.
1122
1123 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1124
1125         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1126         (mips16_opcodes): Replace `M' with `m' for "restore".
1127
1128 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1129
1130         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1131
1132 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1133
1134         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1135         variable to `function_index'.
1136
1137 2018-02-13  Nick Clifton  <nickc@redhat.com>
1138
1139         PR 22823
1140         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1141         about truncation of printing.
1142
1143 2018-02-12  Henry Wong <henry@stuffedcow.net>
1144
1145         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1146
1147 2018-02-05  Nick Clifton  <nickc@redhat.com>
1148
1149         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1150
1151 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1152
1153         * i386-dis.c (enum): Add pconfig.
1154         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1155         (cpu_flags): Add CpuPCONFIG.
1156         * i386-opc.h (enum): Add CpuPCONFIG.
1157         (i386_cpu_flags): Add cpupconfig.
1158         * i386-opc.tbl: Add PCONFIG instruction.
1159         * i386-init.h: Regenerate.
1160         * i386-tbl.h: Likewise.
1161
1162 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1163
1164         * i386-dis.c (enum): Add PREFIX_0F09.
1165         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1166         (cpu_flags): Add CpuWBNOINVD.
1167         * i386-opc.h (enum): Add CpuWBNOINVD.
1168         (i386_cpu_flags): Add cpuwbnoinvd.
1169         * i386-opc.tbl: Add WBNOINVD instruction.
1170         * i386-init.h: Regenerate.
1171         * i386-tbl.h: Likewise.
1172
1173 2018-01-17  Jim Wilson  <jimw@sifive.com>
1174
1175         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1176
1177 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1178
1179         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1180         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1181         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1182         (cpu_flags): Add CpuIBT, CpuSHSTK.
1183         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1184         (i386_cpu_flags): Add cpuibt, cpushstk.
1185         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1186         * i386-init.h: Regenerate.
1187         * i386-tbl.h: Likewise.
1188
1189 2018-01-16  Nick Clifton  <nickc@redhat.com>
1190
1191         * po/pt_BR.po: Updated Brazilian Portugese translation.
1192         * po/de.po: Updated German translation.
1193
1194 2018-01-15  Jim Wilson  <jimw@sifive.com>
1195
1196         * riscv-opc.c (match_c_nop): New.
1197         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1198
1199 2018-01-15  Nick Clifton  <nickc@redhat.com>
1200
1201         * po/uk.po: Updated Ukranian translation.
1202
1203 2018-01-13  Nick Clifton  <nickc@redhat.com>
1204
1205         * po/opcodes.pot: Regenerated.
1206
1207 2018-01-13  Nick Clifton  <nickc@redhat.com>
1208
1209         * configure: Regenerate.
1210
1211 2018-01-13  Nick Clifton  <nickc@redhat.com>
1212
1213         2.30 branch created.
1214
1215 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1216
1217         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1218         * i386-tbl.h: Regenerate.
1219
1220 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1223         * i386-tbl.h: Re-generate.
1224
1225 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1228         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1229         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1230         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1231         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1232         Disp8MemShift of AVX512VL forms.
1233         * i386-tbl.h: Re-generate.
1234
1235 2018-01-09  Jim Wilson  <jimw@sifive.com>
1236
1237         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1238         then the hi_addr value is zero.
1239
1240 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1241
1242         * arm-dis.c (arm_opcodes): Add csdb.
1243         (thumb32_opcodes): Add csdb.
1244
1245 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1246
1247         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1248         * aarch64-asm-2.c: Regenerate.
1249         * aarch64-dis-2.c: Regenerate.
1250         * aarch64-opc-2.c: Regenerate.
1251
1252 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1253
1254         PR gas/22681
1255         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1256         Remove AVX512 vmovd with 64-bit operands.
1257         * i386-tbl.h: Regenerated.
1258
1259 2018-01-05  Jim Wilson  <jimw@sifive.com>
1260
1261         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1262         jalr.
1263
1264 2018-01-03  Alan Modra  <amodra@gmail.com>
1265
1266         Update year range in copyright notice of all files.
1267
1268 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1269
1270         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1271         and OPERAND_TYPE_REGZMM entries.
1272
1273 For older changes see ChangeLog-2017
1274 \f
1275 Copyright (C) 2018 Free Software Foundation, Inc.
1276
1277 Copying and distribution of this file, with or without modification,
1278 are permitted in any medium without royalty provided the copyright
1279 notice and this notice are preserved.
1280
1281 Local Variables:
1282 mode: change-log
1283 left-margin: 8
1284 fill-column: 74
1285 version-control: never
1286 End: