opcodes/ChangeLog

   1 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
   2
   3         PR binutils/3100
   4         * i386-dis.c (prefix_user_table): Fix the second operand of
   5         maskmovdqu instruction to allow only %xmm register instead of
   6         both %xmm register and memory.
   7
   8 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         PR binutils/3235
  11         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
  12         address size prefix.
  13
  14 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  15
  16         * score-dis.c: New file.
  17         * score-opc.h: New file.
  18         * Makefile.am: Add Score files.
  19         * Makefile.in: Regenerate.
  20         * configure.in: Add support for Score target.
  21         * configure: Regenerate.
  22         * disassemble.c: Add support for Score target.
  23
  24 2006-09-16  Nick Clifton  <nickc@redhat.com>
  25             Pedro Alves  <pedro_alves@portugalmail.pt>
  26
  27         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
  28         macros defined in bfd.h.
  29         * cris-dis.c: Likewise.
  30         * h8300-dis.c: Likewise.
  31         * i386-dis.c: Likewise.
  32         * ia64-gen.c: Likewise.
  33         * mips-dis: Likewise.
  34
  35 2006-09-04  Paul Brook  <paul@codesourcery.com>
  36
  37         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
  38
  39 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-dis.c (three_byte_table): Expand to 256 elements.
  42
  43 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  44
  45         PR binutils/3000
  46         * i386-dis.c (MXC,EMC): Define.
  47         (OP_MXC): New function to handle cvt* (convert instructions) between
  48         %xmm and %mm register correctly.
  49         (OP_EMC): ditto.
  50         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  51         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  52         with EMC/MXC.
  53
  54 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  55
  56         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  57         "fdaddl" entry.
  58
  59 2006-07-19  Paul Brook  <paul@codesourcery.com>
  60
  61         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  62
  63 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  66         "sldt", "str" and "smsw".
  67
  68 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  69
  70         PR binutils/2829
  71         * i386-dis.c (GRP11_C6): NEW.
  72         (GRP11_C7): Likewise.
  73         (GRP12): Updated.
  74         (GRP13): Likewise.
  75         (GRP14): Likewise.
  76         (GRP15): Likewise.
  77         (GRP16): Likewise.
  78         (GRPAMD): Likewise.
  79         (GRPPADLCK1): Likewise.
  80         (GRPPADLCK2): Likewise.
  81         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  82         respectively.
  83         (grps): Add entries for GRP11_C6 and GRP11_C7.
  84
  85 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  86            Michael Meissner             <michael.meissner@amd.com>
  87
  88         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  89         support for amdfam10 SSE4a/ABM instructions. Modify all
  90         initializer macros to have additional arguments. Disallow REP
  91         prefix for non-string instructions.
  92         (print_insn): Ditto.
  93
  94
  95 2006-07-05  Julian Brown  <julian@codesourcery.com>
  96
  97         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  98
  99 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 102         (twobyte_has_modrm): Set 1 for 0x1f.
 103
 104 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         * i386-dis.c (NOP_Fixup): Removed.
 107         (NOP_Fixup1): New.
 108         (NOP_Fixup2): Likewise.
 109         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 110
 111 2006-06-12  Julian Brown  <julian@codesourcery.com>
 112
 113         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 114         on 64-bit hosts.
 115
 116 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         * i386.c (GRP10): Renamed to ...
 119         (GRP12): This.
 120         (GRP11): Renamed to ...
 121         (GRP13): This.
 122         (GRP12): Renamed to ...
 123         (GRP14): This.
 124         (GRP13): Renamed to ...
 125         (GRP15): This.
 126         (GRP14): Renamed to ...
 127         (GRP16): This.
 128         (dis386_twobyte): Updated.
 129         (grps): Likewise.
 130
 131 2006-06-09  Nick Clifton  <nickc@redhat.com>
 132
 133         * po/fi.po: Updated Finnish translation.
 134
 135 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 136
 137         * po/Make-in (pdf, ps): New dummy targets.
 138
 139 2006-06-06  Paul Brook  <paul@codesourcery.com>
 140
 141         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 142         instructions.
 143         (neon_opcodes): Add conditional execution specifiers.
 144         (thumb_opcodes): Ditto.
 145         (thumb32_opcodes): Ditto.
 146         (arm_conditional): Change 0xe to "al" and add "" to end.
 147         (ifthen_state, ifthen_next_state, ifthen_address): New.
 148         (IFTHEN_COND): Define.
 149         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 150         (print_insn_arm): Change %c to use new values of arm_conditional.
 151         (print_insn_thumb16): Print thumb conditions.  Add %I.
 152         (print_insn_thumb32): Print thumb conditions.
 153         (find_ifthen_state): New function.
 154         (print_insn): Track IT block state.
 155
 156 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 157             Anton Blanchard  <anton@samba.org>
 158             Peter Bergner  <bergner@vnet.ibm.com>
 159
 160         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 161         (print_ppc_disassembler_options): Mention power6.
 162
 163 2006-06-06  Thiemo Seufer  <ths@mips.com>
 164             Chao-ying Fu  <fu@mips.com>
 165
 166         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 167         * mips-opc.c: Add DSP64 instructions.
 168
 169 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 170
 171         * m68hc11-dis.c (print_insn): Warning fix.
 172
 173 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 174
 175         * po/Make-in (top_builddir): Define.
 176
 177 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 178
 179         * Makefile.am: Run "make dep-am".
 180         * Makefile.in: Regenerate.
 181         * config.in: Regenerate.
 182
 183 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 184
 185         * Makefile.am (INCLUDES): Use @INCINTL@.
 186         * acinclude.m4: Include new gettext macros.
 187         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 188         Remove local code for po/Makefile.
 189         * Makefile.in, aclocal.m4, configure: Regenerated.
 190
 191 2006-05-30  Nick Clifton  <nickc@redhat.com>
 192
 193         * po/es.po: Updated Spanish translation.
 194
 195 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 196
 197         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 198         and fmovem entries.  Put register list entries before immediate
 199         mask entries.  Use "l" rather than "L" in the fmovem entries.
 200         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 201         out from INFO.
 202         (m68k_scan_mask): New function, split out from...
 203         (print_insn_m68k): ...here.  If no architecture has been set,
 204         first try printing an m680x0 instruction, then try a Coldfire one.
 205
 206 2006-05-24  Nick Clifton  <nickc@redhat.com>
 207
 208         * po/ga.po: Updated Irish translation.
 209
 210 2006-05-22  Nick Clifton  <nickc@redhat.com>
 211
 212         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 213
 214 2006-05-22  Nick Clifton  <nickc@redhat.com>
 215
 216         * po/nl.po: Updated translation.
 217
 218 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 219
 220         * avr-dis.c: Formatting fix.
 221
 222 2006-05-14  Thiemo Seufer  <ths@mips.com>
 223
 224         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 225         (mips16_opcodes): Change membership of instructions to their
 226         lowest baseline ISA.
 227
 228 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 231
 232 2006-05-05  Julian Brown  <julian@codesourcery.com>
 233
 234         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 235         vldm/vstm.
 236
 237 2006-05-05  Thiemo Seufer  <ths@mips.com>
 238             David Ung  <davidu@mips.com>
 239
 240         * mips-opc.c: Add macro for cache instruction.
 241
 242 2006-05-04  Thiemo Seufer  <ths@mips.com>
 243             Nigel Stephens  <nigel@mips.com>
 244             David Ung  <davidu@mips.com>
 245
 246         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 247         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 248         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 249         MIPS64R2.
 250         * mips-opc.c: fix random typos in comments.
 251         (INSN_SMARTMIPS): New defines.
 252         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 253         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 254         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 255         FP_S and FP_D flags to denote single and double register
 256         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 257         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 258         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 259         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 260         release 2 ISAs.
 261         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 262
 263 2006-05-03  Thiemo Seufer  <ths@mips.com>
 264
 265         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 266
 267 2006-05-02  Thiemo Seufer  <ths@mips.com>
 268             Nigel Stephens  <nigel@mips.com>
 269             David Ung  <davidu@mips.com>
 270
 271         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 272         (print_mips16_insn_arg): Force mips16 to odd addresses.
 273
 274 2006-04-30  Thiemo Seufer  <ths@mips.com>
 275             David Ung  <davidu@mips.com>
 276
 277         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 278         "udi0" to "udi15".
 279         * mips-dis.c (print_insn_args): Adds udi argument handling.
 280
 281 2006-04-28  James E Wilson  <wilson@specifix.com>
 282
 283         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 284         error message.
 285
 286 2006-04-28  Thiemo Seufer  <ths@mips.com>
 287             David Ung  <davidu@mips.com>
 288             Nigel Stephens  <nigel@mips.com>
 289
 290         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 291         names.
 292
 293 2006-04-28  Thiemo Seufer  <ths@mips.com>
 294             Nigel Stephens  <nigel@mips.com>
 295             David Ung  <davidu@mips.com>
 296
 297         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 298         (print_insn_mips):  Adjust print_insn_args call.
 299
 300 2006-04-28  Thiemo Seufer  <ths@mips.com>
 301             Nigel Stephens  <nigel@mips.com>
 302
 303         * mips-dis.c (print_insn_args): Print $fcc only for FP
 304         instructions, use $cc elsewise.
 305
 306 2006-04-28  Thiemo Seufer  <ths@mips.com>
 307             Nigel Stephens  <nigel@mips.com>
 308
 309         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 310         Map MIPS16 registers to O32 names.
 311         (print_mips16_insn_arg): Use mips16_reg_names.
 312
 313 2006-04-26  Julian Brown  <julian@codesourcery.com>
 314
 315         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 316         VMOV.
 317
 318 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 319             Julian Brown  <julian@codesourcery.com>
 320
 321         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 322         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 323         Add unified load/store instruction names.
 324         (neon_opcode_table): New.
 325         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 326         (arm_decode_bitfield): New.
 327         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 328         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 329         (print_insn_neon): New.
 330         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 331         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 332         (print_insn_thumb32): Likewise.
 333
 334 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 335
 336         * Makefile.am: Run "make dep-am".
 337         * Makefile.in: Regenerate.
 338
 339 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 340
 341         * avr-dis.c (avr_operand): Warning fix.
 342
 343         * configure: Regenerate.
 344
 345 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 346
 347         * po/POTFILES.in: Regenerated.
 348
 349 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 350
 351         PR binutils/2454
 352         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 353         the symolic form of an address, so that the output of objdump -d
 354         can be reassembled.
 355
 356 2006-04-10  DJ Delorie  <dj@redhat.com>
 357
 358         * m32c-asm.c: Regenerate.
 359
 360 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 361
 362         * Makefile.am: Add install-html target.
 363         * Makefile.in: Regenerate.
 364
 365 2006-04-06  Nick Clifton  <nickc@redhat.com>
 366
 367         * po/vi/po: Updated Vietnamese translation.
 368
 369 2006-03-31  Paul Koning  <ni1d@arrl.net>
 370
 371         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 372
 373 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 374
 375         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 376         logic to identify halfword shifts.
 377
 378 2006-03-16  Paul Brook  <paul@codesourcery.com>
 379
 380         * arm-dis.c (arm_opcodes): Rename swi to svc.
 381         (thumb_opcodes): Ditto.
 382
 383 2006-03-13  DJ Delorie  <dj@redhat.com>
 384
 385         * m32c-asm.c: Regenerate.
 386         * m32c-desc.c: Likewise.
 387         * m32c-desc.h: Likewise.
 388         * m32c-dis.c: Likewise.
 389         * m32c-ibld.c: Likewise.
 390         * m32c-opc.c: Likewise.
 391         * m32c-opc.h: Likewise.
 392
 393 2006-03-10  DJ Delorie  <dj@redhat.com>
 394
 395         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 396         * m32c-opc.c: Likewise.
 397         * m32c-opc.h: Likewise.
 398
 399
 400 2006-03-09  Nick Clifton  <nickc@redhat.com>
 401
 402         * po/sv.po: Updated Swedish translation.
 403
 404 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         PR binutils/2428
 407         * i386-dis.c (REP_Fixup): New function.
 408         (AL): Remove duplicate.
 409         (Xbr): New.
 410         (Xvr): Likewise.
 411         (Ybr): Likewise.
 412         (Yvr): Likewise.
 413         (indirDXr): Likewise.
 414         (ALr): Likewise.
 415         (eAXr): Likewise.
 416         (dis386): Updated entries of ins, outs, movs, lods and stos.
 417
 418 2006-03-05  Nick Clifton  <nickc@redhat.com>
 419
 420         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 421         signed 32-bit value into an unsigned 32-bit field when the host is
 422         a 64-bit machine.
 423         * fr30-ibld.c: Regenerate.
 424         * frv-ibld.c: Regenerate.
 425         * ip2k-ibld.c: Regenerate.
 426         * iq2000-asm.c: Regenerate.
 427         * iq2000-ibld.c: Regenerate.
 428         * m32c-ibld.c: Regenerate.
 429         * m32r-ibld.c: Regenerate.
 430         * openrisc-ibld.c: Regenerate.
 431         * xc16x-ibld.c: Regenerate.
 432         * xstormy16-ibld.c: Regenerate.
 433
 434 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 435
 436         * xc16x-asm.c: Regenerate.
 437         * xc16x-dis.c: Regenerate.
 438
 439 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 440
 441         * po/Make-in: Add html target.
 442
 443 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 446         Intel Merom New Instructions.
 447         (THREE_BYTE_0): Likewise.
 448         (THREE_BYTE_1): Likewise.
 449         (three_byte_table): Likewise.
 450         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 451         THREE_BYTE_1 for entry 0x3a.
 452         (twobyte_has_modrm): Updated.
 453         (twobyte_uses_SSE_prefix): Likewise.
 454         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 455         Instructions.
 456
 457 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 458
 459         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 460         (v9_hpriv_reg_names): New table.
 461         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 462         New cases '$' and '%' for read/write hyperprivileged register.
 463         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 464         window handling and rdhpr/wrhpr instructions.
 465
 466 2006-02-24  DJ Delorie  <dj@redhat.com>
 467
 468         * m32c-desc.c: Regenerate with linker relaxation attributes.
 469         * m32c-desc.h: Likewise.
 470         * m32c-dis.c: Likewise.
 471         * m32c-opc.c: Likewise.
 472
 473 2006-02-24  Paul Brook  <paul@codesourcery.com>
 474
 475         * arm-dis.c (arm_opcodes): Add V7 instructions.
 476         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 477         (print_arm_address): New function.
 478         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 479         (psr_name): New function.
 480         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 481
 482 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 483
 484         * ia64-opc-i.c (bXc): New.
 485         (mXc): Likewise.
 486         (OpX2TaTbYaXcC): Likewise.
 487         (TF). Likewise.
 488         (TFCM). Likewise.
 489         (ia64_opcodes_i): Add instructions for tf.
 490
 491         * ia64-opc.h (IMMU5b): New.
 492
 493         * ia64-asmtab.c: Regenerated.
 494
 495 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         * ia64-gen.c: Update copyright years.
 498         * ia64-opc-b.c: Likewise.
 499
 500 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 501
 502         * ia64-gen.c (lookup_regindex): Handle ".vm".
 503         (print_dependency_table): Handle '\"'.
 504
 505         * ia64-ic.tbl: Updated from SDM 2.2.
 506         * ia64-raw.tbl: Likewise.
 507         * ia64-waw.tbl: Likewise.
 508         * ia64-asmtab.c: Regenerated.
 509
 510         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 511
 512 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 513             Anil Paranjape   <anilp1@kpitcummins.com>
 514             Shilin Shakti    <shilins@kpitcummins.com>
 515
 516         * xc16x-desc.h: New file
 517         * xc16x-desc.c: New file
 518         * xc16x-opc.h: New file
 519         * xc16x-opc.c: New file
 520         * xc16x-ibld.c: New file
 521         * xc16x-asm.c: New file
 522         * xc16x-dis.c: New file
 523         * Makefile.am: Entries for xc16x
 524         * Makefile.in: Regenerate
 525         * cofigure.in: Add xc16x target information.
 526         * configure: Regenerate.
 527         * disassemble.c: Add xc16x target information.
 528
 529 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 532         moves.
 533
 534 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         * i386-dis.c ('Z'): Add a new macro.
 537         (dis386_twobyte): Use "movZ" for control register moves.
 538
 539 2006-02-10  Nick Clifton  <nickc@redhat.com>
 540
 541         * iq2000-asm.c: Regenerate.
 542
 543 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 544
 545         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 546
 547 2006-01-26  David Ung  <davidu@mips.com>
 548
 549         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 550         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 551         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 552         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 553         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 554
 555 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 556
 557         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 558         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 559         disassembled.
 560         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 561         buffer overflows when disassembling instructions like
 562         ld (ix+123),0x23
 563         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 564         operand, if the offset is negative.
 565
 566 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 567
 568         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 569         unsigned char to hold data to be disassembled.
 570
 571 2006-01-17  Andreas Schwab  <schwab@suse.de>
 572
 573         PR binutils/1486
 574         * disassemble.c (disassemble_init_for_target): Set
 575         disassembler_needs_relocs for bfd_arch_arm.
 576
 577 2006-01-16  Paul Brook  <paul@codesourcery.com>
 578
 579         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 580         f?add?, and f?sub? instructions.
 581
 582 2006-01-16  Nick Clifton  <nickc@redhat.com>
 583
 584         * po/zh_CN.po: New Chinese (simplified) translation.
 585         * configure.in (ALL_LINGUAS): Add "zh_CH".
 586         * configure: Regenerate.
 587
 588 2006-01-05  Paul Brook  <paul@codesourcery.com>
 589
 590         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 591
 592 2006-01-06  DJ Delorie  <dj@redhat.com>
 593
 594         * m32c-desc.c: Regenerate.
 595         * m32c-opc.c: Regenerate.
 596         * m32c-opc.h: Regenerate.
 597
 598 2006-01-03  DJ Delorie  <dj@redhat.com>
 599
 600         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 601         * m32c-ibld.c: Regenerated.
 602
 603 For older changes see ChangeLog-2005
 604 \f
 605 Local Variables:
 606 mode: change-log
 607 left-margin: 8
 608 fill-column: 74
 609 version-control: never
 610 End: