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Adds the speculation barrier instructions to the ARM assembler and disassembler.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
1 2018-07-11 Sudakshina Das <sudi.das@arm.com>
2
3 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
4 csdb together with them.
5 (thumb32_opcodes): Likewise.
6
7 2018-07-11 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
10 requiring 32-bit registers as operands 2 and 3. Improve
11 comments.
12 (mwait, mwaitx): Fold templates. Improve comments.
13 OPERAND_TYPE_INOUTPORTREG.
14 * i386-tbl.h: Re-generate.
15
16 2018-07-11 Jan Beulich <jbeulich@suse.com>
17
18 * i386-gen.c (operand_type_init): Remove
19 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
20 OPERAND_TYPE_INOUTPORTREG.
21 * i386-init.h: Re-generate.
22
23 2018-07-11 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.tbl (wrssd, wrussd): Add Dword.
26 (wrssq, wrussq): Add Qword.
27 * i386-tbl.h: Re-generate.
28
29 2018-07-11 Jan Beulich <jbeulich@suse.com>
30
31 * i386-opc.h: Rename OTMax to OTNum.
32 (OTNumOfUints): Adjust calculation.
33 (OTUnused): Directly alias to OTNum.
34
35 2018-07-09 Maciej W. Rozycki <macro@mips.com>
36
37 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
38 `reg_xys'.
39 (lea_reg_xys): Likewise.
40 (print_insn_loop_primitive): Rename `reg' local variable to
41 `reg_dxy'.
42
43 2018-07-06 Tamar Christina <tamar.christina@arm.com>
44
45 PR binutils/23242
46 * aarch64-tbl.h (ldarh): Fix disassembly mask.
47
48 2018-07-06 Tamar Christina <tamar.christina@arm.com>
49
50 PR binutils/23369
51 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
52 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
53
54 2018-07-02 Maciej W. Rozycki <macro@mips.com>
55
56 PR tdep/8282
57 * mips-dis.c (mips_option_arg_t): New enumeration.
58 (mips_options): New variable.
59 (disassembler_options_mips): New function.
60 (print_mips_disassembler_options): Reimplement in terms of
61 `disassembler_options_mips'.
62 * arm-dis.c (disassembler_options_arm): Adapt to using the
63 `disasm_options_and_args_t' structure.
64 * ppc-dis.c (disassembler_options_powerpc): Likewise.
65 * s390-dis.c (disassembler_options_s390): Likewise.
66
67 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
68
69 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
70 expected result.
71 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
72 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
73 * testsuite/ld-arm/tls-longplt.d: Likewise.
74
75 2018-06-29 Tamar Christina <tamar.christina@arm.com>
76
77 PR binutils/23192
78 * aarch64-asm-2.c: Regenerate.
79 * aarch64-dis-2.c: Likewise.
80 * aarch64-opc-2.c: Likewise.
81 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
82 * aarch64-opc.c (operand_general_constraint_met_p,
83 aarch64_print_operand): Likewise.
84 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
85 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
86 fmlal2, fmlsl2.
87 (AARCH64_OPERANDS): Add Em2.
88
89 2018-06-26 Nick Clifton <nickc@redhat.com>
90
91 * po/uk.po: Updated Ukranian translation.
92 * po/de.po: Updated German translation.
93 * po/pt_BR.po: Updated Brazilian Portuguese translation.
94
95 2018-06-26 Nick Clifton <nickc@redhat.com>
96
97 * nfp-dis.c: Fix spelling mistake.
98
99 2018-06-24 Nick Clifton <nickc@redhat.com>
100
101 * configure: Regenerate.
102 * po/opcodes.pot: Regenerate.
103
104 2018-06-24 Nick Clifton <nickc@redhat.com>
105
106 2.31 branch created.
107
108 2018-06-19 Tamar Christina <tamar.christina@arm.com>
109
110 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
111 * aarch64-asm-2.c: Regenerate.
112 * aarch64-dis-2.c: Likewise.
113
114 2018-06-21 Maciej W. Rozycki <macro@mips.com>
115
116 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
117 `-M ginv' option description.
118
119 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
120
121 PR gas/23305
122 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
123 la and lla.
124
125 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
126
127 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
128 * configure.ac: Remove AC_PREREQ.
129 * Makefile.in: Re-generate.
130 * aclocal.m4: Re-generate.
131 * configure: Re-generate.
132
133 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
134
135 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
136 mips64r6 descriptors.
137 (parse_mips_ase_option): Handle -Mginv option.
138 (print_mips_disassembler_options): Document -Mginv.
139 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
140 (GINV): New macro.
141 (mips_opcodes): Define ginvi and ginvt.
142
143 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
144 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
145
146 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
147 * mips-opc.c (CRC, CRC64): New macros.
148 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
149 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
150 crc32cd for CRC64.
151
152 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
153
154 PR 20319
155 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
156 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
157
158 2018-06-06 Alan Modra <amodra@gmail.com>
159
160 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
161 setjmp. Move init for some other vars later too.
162
163 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
164
165 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
166 (dis_private): Add new fields for property section tracking.
167 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
168 (xtensa_instruction_fits): New functions.
169 (fetch_data): Bump minimal fetch size to 4.
170 (print_insn_xtensa): Make struct dis_private static.
171 Load and prepare property table on section change.
172 Don't disassemble literals. Don't disassemble instructions that
173 cross property table boundaries.
174
175 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
176
177 * configure: Regenerated.
178
179 2018-06-01 Jan Beulich <jbeulich@suse.com>
180
181 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
182 * i386-tbl.h: Re-generate.
183
184 2018-06-01 Jan Beulich <jbeulich@suse.com>
185
186 * i386-opc.tbl (sldt, str): Add NoRex64.
187 * i386-tbl.h: Re-generate.
188
189 2018-06-01 Jan Beulich <jbeulich@suse.com>
190
191 * i386-opc.tbl (invpcid): Add Oword.
192 * i386-tbl.h: Re-generate.
193
194 2018-06-01 Alan Modra <amodra@gmail.com>
195
196 * sysdep.h (_bfd_error_handler): Don't declare.
197 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
198 * rl78-decode.opc: Likewise.
199 * msp430-decode.c: Regenerate.
200 * rl78-decode.c: Regenerate.
201
202 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
203
204 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
205 * i386-init.h : Regenerated.
206
207 2018-05-25 Alan Modra <amodra@gmail.com>
208
209 * Makefile.in: Regenerate.
210 * po/POTFILES.in: Regenerate.
211
212 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
213
214 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
215 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
216 (insert_bab, extract_bab, insert_btab, extract_btab,
217 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
218 (BAT, BBA VBA RBS XB6S): Delete macros.
219 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
220 (BB, BD, RBX, XC6): Update for new macros.
221 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
222 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
223 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
224 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
225
226 2018-05-18 John Darrington <john@darrington.wattle.id.au>
227
228 * Makefile.am: Add support for s12z architecture.
229 * configure.ac: Likewise.
230 * disassemble.c: Likewise.
231 * disassemble.h: Likewise.
232 * Makefile.in: Regenerate.
233 * configure: Regenerate.
234 * s12z-dis.c: New file.
235 * s12z.h: New file.
236
237 2018-05-18 Alan Modra <amodra@gmail.com>
238
239 * nfp-dis.c: Don't #include libbfd.h.
240 (init_nfp3200_priv): Use bfd_get_section_contents.
241 (nit_nfp6000_mecsr_sec): Likewise.
242
243 2018-05-17 Nick Clifton <nickc@redhat.com>
244
245 * po/zh_CN.po: Updated simplified Chinese translation.
246
247 2018-05-16 Tamar Christina <tamar.christina@arm.com>
248
249 PR binutils/23109
250 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
251 * aarch64-dis-2.c: Regenerate.
252
253 2018-05-15 Tamar Christina <tamar.christina@arm.com>
254
255 PR binutils/21446
256 * aarch64-asm.c (opintl.h): Include.
257 (aarch64_ins_sysreg): Enforce read/write constraints.
258 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
259 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
260 (F_REG_READ, F_REG_WRITE): New.
261 * aarch64-opc.c (aarch64_print_operand): Generate notes for
262 AARCH64_OPND_SYSREG.
263 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
264 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
265 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
266 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
267 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
268 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
269 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
270 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
271 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
272 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
273 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
274 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
275 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
276 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
277 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
278 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
279 msr (F_SYS_WRITE), mrs (F_SYS_READ).
280
281 2018-05-15 Tamar Christina <tamar.christina@arm.com>
282
283 PR binutils/21446
284 * aarch64-dis.c (no_notes: New.
285 (parse_aarch64_dis_option): Support notes.
286 (aarch64_decode_insn, print_operands): Likewise.
287 (print_aarch64_disassembler_options): Document notes.
288 * aarch64-opc.c (aarch64_print_operand): Support notes.
289
290 2018-05-15 Tamar Christina <tamar.christina@arm.com>
291
292 PR binutils/21446
293 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
294 and take error struct.
295 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
296 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
297 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
298 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
299 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
300 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
301 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
302 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
303 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
304 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
305 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
306 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
307 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
308 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
309 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
310 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
311 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
312 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
313 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
314 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
315 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
316 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
317 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
318 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
319 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
320 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
321 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
322 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
323 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
324 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
325 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
326 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
327 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
328 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
329 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
330 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
331 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
332 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
333 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
334 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
335 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
336 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
337 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
338 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
339 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
340 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
341 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
342 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
343 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
344 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
345 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
346 (determine_disassembling_preference, aarch64_decode_insn,
347 print_insn_aarch64_word, print_insn_data): Take errors struct.
348 (print_insn_aarch64): Use errors.
349 * aarch64-asm-2.c: Regenerate.
350 * aarch64-dis-2.c: Regenerate.
351 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
352 boolean in aarch64_insert_operan.
353 (print_operand_extractor): Likewise.
354 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
355
356 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
357
358 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
359
360 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
361
362 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
363
364 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
365
366 * cr16-opc.c (cr16_instruction): Comment typo fix.
367 * hppa-dis.c (print_insn_hppa): Likewise.
368
369 2018-05-08 Jim Wilson <jimw@sifive.com>
370
371 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
372 (match_c_slli64, match_srxi_as_c_srxi): New.
373 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
374 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
375 <c.slli, c.srli, c.srai>: Use match_s_slli.
376 <c.slli64, c.srli64, c.srai64>: New.
377
378 2018-05-08 Alan Modra <amodra@gmail.com>
379
380 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
381 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
382 partition opcode space for index lookup.
383
384 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
385
386 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
387 <insn_length>: ...with this. Update usage.
388 Remove duplicate call to *info->memory_error_func.
389
390 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
391 H.J. Lu <hongjiu.lu@intel.com>
392
393 * i386-dis.c (Gva): New.
394 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
395 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
396 (prefix_table): New instructions (see prefix above).
397 (mod_table): New instructions (see prefix above).
398 (OP_G): Handle va_mode.
399 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
400 CPU_MOVDIR64B_FLAGS.
401 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
402 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
403 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
404 * i386-opc.tbl: Add movidir{i,64b}.
405 * i386-init.h: Regenerated.
406 * i386-tbl.h: Likewise.
407
408 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
409
410 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
411 AddrPrefixOpReg.
412 * i386-opc.h (AddrPrefixOp0): Renamed to ...
413 (AddrPrefixOpReg): This.
414 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
415 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
416
417 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
418
419 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
420 (vle_num_opcodes): Likewise.
421 (spe2_num_opcodes): Likewise.
422 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
423 initialization loop.
424 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
425 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
426 only once.
427
428 2018-05-01 Tamar Christina <tamar.christina@arm.com>
429
430 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
431
432 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
433
434 Makefile.am: Added nfp-dis.c.
435 configure.ac: Added bfd_nfp_arch.
436 disassemble.h: Added print_insn_nfp prototype.
437 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
438 nfp-dis.c: New, for NFP support.
439 po/POTFILES.in: Added nfp-dis.c to the list.
440 Makefile.in: Regenerate.
441 configure: Regenerate.
442
443 2018-04-26 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.tbl: Fold various non-memory operand AVX512VL
446 templates into their base ones.
447 * i386-tlb.h: Re-generate.
448
449 2018-04-26 Jan Beulich <jbeulich@suse.com>
450
451 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
452 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
453 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
454 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
455 * i386-init.h: Re-generate.
456
457 2018-04-26 Jan Beulich <jbeulich@suse.com>
458
459 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
460 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
461 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
462 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
463 comment.
464 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
465 and CpuRegMask.
466 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
467 CpuRegMask: Delete.
468 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
469 cpuregzmm, and cpuregmask.
470 * i386-init.h: Re-generate.
471 * i386-tbl.h: Re-generate.
472
473 2018-04-26 Jan Beulich <jbeulich@suse.com>
474
475 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
476 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
477 * i386-init.h: Re-generate.
478
479 2018-04-26 Jan Beulich <jbeulich@suse.com>
480
481 * i386-gen.c (VexImmExt): Delete.
482 * i386-opc.h (VexImmExt, veximmext): Delete.
483 * i386-opc.tbl: Drop all VexImmExt uses.
484 * i386-tlb.h: Re-generate.
485
486 2018-04-25 Jan Beulich <jbeulich@suse.com>
487
488 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
489 register-only forms.
490 * i386-tlb.h: Re-generate.
491
492 2018-04-25 Tamar Christina <tamar.christina@arm.com>
493
494 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
495
496 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
497
498 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
499 PREFIX_0F1C.
500 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
501 (cpu_flags): Add CpuCLDEMOTE.
502 * i386-init.h: Regenerate.
503 * i386-opc.h (enum): Add CpuCLDEMOTE,
504 (i386_cpu_flags): Add cpucldemote.
505 * i386-opc.tbl: Add cldemote.
506 * i386-tbl.h: Regenerate.
507
508 2018-04-16 Alan Modra <amodra@gmail.com>
509
510 * Makefile.am: Remove sh5 and sh64 support.
511 * configure.ac: Likewise.
512 * disassemble.c: Likewise.
513 * disassemble.h: Likewise.
514 * sh-dis.c: Likewise.
515 * sh64-dis.c: Delete.
516 * sh64-opc.c: Delete.
517 * sh64-opc.h: Delete.
518 * Makefile.in: Regenerate.
519 * configure: Regenerate.
520 * po/POTFILES.in: Regenerate.
521
522 2018-04-16 Alan Modra <amodra@gmail.com>
523
524 * Makefile.am: Remove w65 support.
525 * configure.ac: Likewise.
526 * disassemble.c: Likewise.
527 * disassemble.h: Likewise.
528 * w65-dis.c: Delete.
529 * w65-opc.h: Delete.
530 * Makefile.in: Regenerate.
531 * configure: Regenerate.
532 * po/POTFILES.in: Regenerate.
533
534 2018-04-16 Alan Modra <amodra@gmail.com>
535
536 * configure.ac: Remove we32k support.
537 * configure: Regenerate.
538
539 2018-04-16 Alan Modra <amodra@gmail.com>
540
541 * Makefile.am: Remove m88k support.
542 * configure.ac: Likewise.
543 * disassemble.c: Likewise.
544 * disassemble.h: Likewise.
545 * m88k-dis.c: Delete.
546 * Makefile.in: Regenerate.
547 * configure: Regenerate.
548 * po/POTFILES.in: Regenerate.
549
550 2018-04-16 Alan Modra <amodra@gmail.com>
551
552 * Makefile.am: Remove i370 support.
553 * configure.ac: Likewise.
554 * disassemble.c: Likewise.
555 * disassemble.h: Likewise.
556 * i370-dis.c: Delete.
557 * i370-opc.c: Delete.
558 * Makefile.in: Regenerate.
559 * configure: Regenerate.
560 * po/POTFILES.in: Regenerate.
561
562 2018-04-16 Alan Modra <amodra@gmail.com>
563
564 * Makefile.am: Remove h8500 support.
565 * configure.ac: Likewise.
566 * disassemble.c: Likewise.
567 * disassemble.h: Likewise.
568 * h8500-dis.c: Delete.
569 * h8500-opc.h: Delete.
570 * Makefile.in: Regenerate.
571 * configure: Regenerate.
572 * po/POTFILES.in: Regenerate.
573
574 2018-04-16 Alan Modra <amodra@gmail.com>
575
576 * configure.ac: Remove tahoe support.
577 * configure: Regenerate.
578
579 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
580
581 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
582 umwait.
583 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
584 64-bit mode.
585 * i386-tbl.h: Regenerated.
586
587 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
588
589 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
590 PREFIX_MOD_1_0FAE_REG_6.
591 (va_mode): New.
592 (OP_E_register): Use va_mode.
593 * i386-dis-evex.h (prefix_table):
594 New instructions (see prefixes above).
595 * i386-gen.c (cpu_flag_init): Add WAITPKG.
596 (cpu_flags): Likewise.
597 * i386-opc.h (enum): Likewise.
598 (i386_cpu_flags): Likewise.
599 * i386-opc.tbl: Add umonitor, umwait, tpause.
600 * i386-init.h: Regenerate.
601 * i386-tbl.h: Likewise.
602
603 2018-04-11 Alan Modra <amodra@gmail.com>
604
605 * opcodes/i860-dis.c: Delete.
606 * opcodes/i960-dis.c: Delete.
607 * Makefile.am: Remove i860 and i960 support.
608 * configure.ac: Likewise.
609 * disassemble.c: Likewise.
610 * disassemble.h: Likewise.
611 * Makefile.in: Regenerate.
612 * configure: Regenerate.
613 * po/POTFILES.in: Regenerate.
614
615 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
616
617 PR binutils/23025
618 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
619 to 0.
620 (print_insn): Clear vex instead of vex.evex.
621
622 2018-04-04 Nick Clifton <nickc@redhat.com>
623
624 * po/es.po: Updated Spanish translation.
625
626 2018-03-28 Jan Beulich <jbeulich@suse.com>
627
628 * i386-gen.c (opcode_modifiers): Delete VecESize.
629 * i386-opc.h (VecESize): Delete.
630 (struct i386_opcode_modifier): Delete vecesize.
631 * i386-opc.tbl: Drop VecESize.
632 * i386-tlb.h: Re-generate.
633
634 2018-03-28 Jan Beulich <jbeulich@suse.com>
635
636 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
637 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
638 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
639 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
640 * i386-tlb.h: Re-generate.
641
642 2018-03-28 Jan Beulich <jbeulich@suse.com>
643
644 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
645 Fold AVX512 forms
646 * i386-tlb.h: Re-generate.
647
648 2018-03-28 Jan Beulich <jbeulich@suse.com>
649
650 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
651 (vex_len_table): Drop Y for vcvt*2si.
652 (putop): Replace plain 'Y' handling by abort().
653
654 2018-03-28 Nick Clifton <nickc@redhat.com>
655
656 PR 22988
657 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
658 instructions with only a base address register.
659 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
660 handle AARHC64_OPND_SVE_ADDR_R.
661 (aarch64_print_operand): Likewise.
662 * aarch64-asm-2.c: Regenerate.
663 * aarch64_dis-2.c: Regenerate.
664 * aarch64-opc-2.c: Regenerate.
665
666 2018-03-22 Jan Beulich <jbeulich@suse.com>
667
668 * i386-opc.tbl: Drop VecESize from register only insn forms and
669 memory forms not allowing broadcast.
670 * i386-tlb.h: Re-generate.
671
672 2018-03-22 Jan Beulich <jbeulich@suse.com>
673
674 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
675 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
676 sha256*): Drop Disp<N>.
677
678 2018-03-22 Jan Beulich <jbeulich@suse.com>
679
680 * i386-dis.c (EbndS, bnd_swap_mode): New.
681 (prefix_table): Use EbndS.
682 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
683 * i386-opc.tbl (bndmov): Move misplaced Load.
684 * i386-tlb.h: Re-generate.
685
686 2018-03-22 Jan Beulich <jbeulich@suse.com>
687
688 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
689 templates allowing memory operands and folded ones for register
690 only flavors.
691 * i386-tlb.h: Re-generate.
692
693 2018-03-22 Jan Beulich <jbeulich@suse.com>
694
695 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
696 256-bit templates. Drop redundant leftover Disp<N>.
697 * i386-tlb.h: Re-generate.
698
699 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
700
701 * riscv-opc.c (riscv_insn_types): New.
702
703 2018-03-13 Nick Clifton <nickc@redhat.com>
704
705 * po/pt_BR.po: Updated Brazilian Portuguese translation.
706
707 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
708
709 * i386-opc.tbl: Add Optimize to clr.
710 * i386-tbl.h: Regenerated.
711
712 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-gen.c (opcode_modifiers): Remove OldGcc.
715 * i386-opc.h (OldGcc): Removed.
716 (i386_opcode_modifier): Remove oldgcc.
717 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
718 instructions for old (<= 2.8.1) versions of gcc.
719 * i386-tbl.h: Regenerated.
720
721 2018-03-08 Jan Beulich <jbeulich@suse.com>
722
723 * i386-opc.h (EVEXDYN): New.
724 * i386-opc.tbl: Fold various AVX512VL templates.
725 * i386-tlb.h: Re-generate.
726
727 2018-03-08 Jan Beulich <jbeulich@suse.com>
728
729 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
730 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
731 vpexpandd, vpexpandq): Fold AFX512VF templates.
732 * i386-tlb.h: Re-generate.
733
734 2018-03-08 Jan Beulich <jbeulich@suse.com>
735
736 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
737 Fold 128- and 256-bit VEX-encoded templates.
738 * i386-tlb.h: Re-generate.
739
740 2018-03-08 Jan Beulich <jbeulich@suse.com>
741
742 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
743 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
744 vpexpandd, vpexpandq): Fold AVX512F templates.
745 * i386-tlb.h: Re-generate.
746
747 2018-03-08 Jan Beulich <jbeulich@suse.com>
748
749 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
750 64-bit templates. Drop Disp<N>.
751 * i386-tlb.h: Re-generate.
752
753 2018-03-08 Jan Beulich <jbeulich@suse.com>
754
755 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
756 and 256-bit templates.
757 * i386-tlb.h: Re-generate.
758
759 2018-03-08 Jan Beulich <jbeulich@suse.com>
760
761 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
762 * i386-tlb.h: Re-generate.
763
764 2018-03-08 Jan Beulich <jbeulich@suse.com>
765
766 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
767 Drop NoAVX.
768 * i386-tlb.h: Re-generate.
769
770 2018-03-08 Jan Beulich <jbeulich@suse.com>
771
772 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
773 * i386-tlb.h: Re-generate.
774
775 2018-03-08 Jan Beulich <jbeulich@suse.com>
776
777 * i386-gen.c (opcode_modifiers): Delete FloatD.
778 * i386-opc.h (FloatD): Delete.
779 (struct i386_opcode_modifier): Delete floatd.
780 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
781 FloatD by D.
782 * i386-tlb.h: Re-generate.
783
784 2018-03-08 Jan Beulich <jbeulich@suse.com>
785
786 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
787
788 2018-03-08 Jan Beulich <jbeulich@suse.com>
789
790 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
791 * i386-tlb.h: Re-generate.
792
793 2018-03-08 Jan Beulich <jbeulich@suse.com>
794
795 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
796 forms.
797 * i386-tlb.h: Re-generate.
798
799 2018-03-07 Alan Modra <amodra@gmail.com>
800
801 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
802 bfd_arch_rs6000.
803 * disassemble.h (print_insn_rs6000): Delete.
804 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
805 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
806 (print_insn_rs6000): Delete.
807
808 2018-03-03 Alan Modra <amodra@gmail.com>
809
810 * sysdep.h (opcodes_error_handler): Define.
811 (_bfd_error_handler): Declare.
812 * Makefile.am: Remove stray #.
813 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
814 EDIT" comment.
815 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
816 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
817 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
818 opcodes_error_handler to print errors. Standardize error messages.
819 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
820 and include opintl.h.
821 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
822 * i386-gen.c: Standardize error messages.
823 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
824 * Makefile.in: Regenerate.
825 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
826 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
827 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
828 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
829 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
830 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
831 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
832 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
833 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
834 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
835 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
836 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
837 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
838
839 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
840
841 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
842 vpsub[bwdq] instructions.
843 * i386-tbl.h: Regenerated.
844
845 2018-03-01 Alan Modra <amodra@gmail.com>
846
847 * configure.ac (ALL_LINGUAS): Sort.
848 * configure: Regenerate.
849
850 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
851
852 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
853 macro by assignements.
854
855 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
856
857 PR gas/22871
858 * i386-gen.c (opcode_modifiers): Add Optimize.
859 * i386-opc.h (Optimize): New enum.
860 (i386_opcode_modifier): Add optimize.
861 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
862 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
863 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
864 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
865 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
866 vpxord and vpxorq.
867 * i386-tbl.h: Regenerated.
868
869 2018-02-26 Alan Modra <amodra@gmail.com>
870
871 * crx-dis.c (getregliststring): Allocate a large enough buffer
872 to silence false positive gcc8 warning.
873
874 2018-02-22 Shea Levy <shea@shealevy.com>
875
876 * disassemble.c (ARCH_riscv): Define if ARCH_all.
877
878 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
879
880 * i386-opc.tbl: Add {rex},
881 * i386-tbl.h: Regenerated.
882
883 2018-02-20 Maciej W. Rozycki <macro@mips.com>
884
885 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
886 (mips16_opcodes): Replace `M' with `m' for "restore".
887
888 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
889
890 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
891
892 2018-02-13 Maciej W. Rozycki <macro@mips.com>
893
894 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
895 variable to `function_index'.
896
897 2018-02-13 Nick Clifton <nickc@redhat.com>
898
899 PR 22823
900 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
901 about truncation of printing.
902
903 2018-02-12 Henry Wong <henry@stuffedcow.net>
904
905 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
906
907 2018-02-05 Nick Clifton <nickc@redhat.com>
908
909 * po/pt_BR.po: Updated Brazilian Portuguese translation.
910
911 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
912
913 * i386-dis.c (enum): Add pconfig.
914 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
915 (cpu_flags): Add CpuPCONFIG.
916 * i386-opc.h (enum): Add CpuPCONFIG.
917 (i386_cpu_flags): Add cpupconfig.
918 * i386-opc.tbl: Add PCONFIG instruction.
919 * i386-init.h: Regenerate.
920 * i386-tbl.h: Likewise.
921
922 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
923
924 * i386-dis.c (enum): Add PREFIX_0F09.
925 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
926 (cpu_flags): Add CpuWBNOINVD.
927 * i386-opc.h (enum): Add CpuWBNOINVD.
928 (i386_cpu_flags): Add cpuwbnoinvd.
929 * i386-opc.tbl: Add WBNOINVD instruction.
930 * i386-init.h: Regenerate.
931 * i386-tbl.h: Likewise.
932
933 2018-01-17 Jim Wilson <jimw@sifive.com>
934
935 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
936
937 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
938
939 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
940 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
941 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
942 (cpu_flags): Add CpuIBT, CpuSHSTK.
943 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
944 (i386_cpu_flags): Add cpuibt, cpushstk.
945 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
946 * i386-init.h: Regenerate.
947 * i386-tbl.h: Likewise.
948
949 2018-01-16 Nick Clifton <nickc@redhat.com>
950
951 * po/pt_BR.po: Updated Brazilian Portugese translation.
952 * po/de.po: Updated German translation.
953
954 2018-01-15 Jim Wilson <jimw@sifive.com>
955
956 * riscv-opc.c (match_c_nop): New.
957 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
958
959 2018-01-15 Nick Clifton <nickc@redhat.com>
960
961 * po/uk.po: Updated Ukranian translation.
962
963 2018-01-13 Nick Clifton <nickc@redhat.com>
964
965 * po/opcodes.pot: Regenerated.
966
967 2018-01-13 Nick Clifton <nickc@redhat.com>
968
969 * configure: Regenerate.
970
971 2018-01-13 Nick Clifton <nickc@redhat.com>
972
973 2.30 branch created.
974
975 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
976
977 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
978 * i386-tbl.h: Regenerate.
979
980 2018-01-10 Jan Beulich <jbeulich@suse.com>
981
982 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
983 * i386-tbl.h: Re-generate.
984
985 2018-01-10 Jan Beulich <jbeulich@suse.com>
986
987 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
988 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
989 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
990 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
991 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
992 Disp8MemShift of AVX512VL forms.
993 * i386-tbl.h: Re-generate.
994
995 2018-01-09 Jim Wilson <jimw@sifive.com>
996
997 * riscv-dis.c (maybe_print_address): If base_reg is zero,
998 then the hi_addr value is zero.
999
1000 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1001
1002 * arm-dis.c (arm_opcodes): Add csdb.
1003 (thumb32_opcodes): Add csdb.
1004
1005 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1006
1007 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1008 * aarch64-asm-2.c: Regenerate.
1009 * aarch64-dis-2.c: Regenerate.
1010 * aarch64-opc-2.c: Regenerate.
1011
1012 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 PR gas/22681
1015 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1016 Remove AVX512 vmovd with 64-bit operands.
1017 * i386-tbl.h: Regenerated.
1018
1019 2018-01-05 Jim Wilson <jimw@sifive.com>
1020
1021 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1022 jalr.
1023
1024 2018-01-03 Alan Modra <amodra@gmail.com>
1025
1026 Update year range in copyright notice of all files.
1027
1028 2018-01-02 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1031 and OPERAND_TYPE_REGZMM entries.
1032
1033 For older changes see ChangeLog-2017
1034 \f
1035 Copyright (C) 2018 Free Software Foundation, Inc.
1036
1037 Copying and distribution of this file, with or without modification,
1038 are permitted in any medium without royalty provided the copyright
1039 notice and this notice are preserved.
1040
1041 Local Variables:
1042 mode: change-log
1043 left-margin: 8
1044 fill-column: 74
1045 version-control: never
1046 End: