]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - opcodes/ChangeLog
This patch adds support for the SSBB and PSSBB speculation barrier instructions to...
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
1 2018-07-12 Sudakshina Das <sudi.das@arm.com>
2
3 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
4 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
5 * aarch64-asm-2.c: Regenerate.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-opc-2.c: Regenerate.
8
9 2018-07-12 Tamar Christina <tamar.christina@arm.com>
10
11 PR binutils/23192
12 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
13 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
14 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
15 sqdmulh, sqrdmulh): Use Em16.
16
17 2018-07-11 Sudakshina Das <sudi.das@arm.com>
18
19 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
20 csdb together with them.
21 (thumb32_opcodes): Likewise.
22
23 2018-07-11 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
26 requiring 32-bit registers as operands 2 and 3. Improve
27 comments.
28 (mwait, mwaitx): Fold templates. Improve comments.
29 OPERAND_TYPE_INOUTPORTREG.
30 * i386-tbl.h: Re-generate.
31
32 2018-07-11 Jan Beulich <jbeulich@suse.com>
33
34 * i386-gen.c (operand_type_init): Remove
35 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
36 OPERAND_TYPE_INOUTPORTREG.
37 * i386-init.h: Re-generate.
38
39 2018-07-11 Jan Beulich <jbeulich@suse.com>
40
41 * i386-opc.tbl (wrssd, wrussd): Add Dword.
42 (wrssq, wrussq): Add Qword.
43 * i386-tbl.h: Re-generate.
44
45 2018-07-11 Jan Beulich <jbeulich@suse.com>
46
47 * i386-opc.h: Rename OTMax to OTNum.
48 (OTNumOfUints): Adjust calculation.
49 (OTUnused): Directly alias to OTNum.
50
51 2018-07-09 Maciej W. Rozycki <macro@mips.com>
52
53 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
54 `reg_xys'.
55 (lea_reg_xys): Likewise.
56 (print_insn_loop_primitive): Rename `reg' local variable to
57 `reg_dxy'.
58
59 2018-07-06 Tamar Christina <tamar.christina@arm.com>
60
61 PR binutils/23242
62 * aarch64-tbl.h (ldarh): Fix disassembly mask.
63
64 2018-07-06 Tamar Christina <tamar.christina@arm.com>
65
66 PR binutils/23369
67 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
68 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
69
70 2018-07-02 Maciej W. Rozycki <macro@mips.com>
71
72 PR tdep/8282
73 * mips-dis.c (mips_option_arg_t): New enumeration.
74 (mips_options): New variable.
75 (disassembler_options_mips): New function.
76 (print_mips_disassembler_options): Reimplement in terms of
77 `disassembler_options_mips'.
78 * arm-dis.c (disassembler_options_arm): Adapt to using the
79 `disasm_options_and_args_t' structure.
80 * ppc-dis.c (disassembler_options_powerpc): Likewise.
81 * s390-dis.c (disassembler_options_s390): Likewise.
82
83 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
84
85 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
86 expected result.
87 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
88 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
89 * testsuite/ld-arm/tls-longplt.d: Likewise.
90
91 2018-06-29 Tamar Christina <tamar.christina@arm.com>
92
93 PR binutils/23192
94 * aarch64-asm-2.c: Regenerate.
95 * aarch64-dis-2.c: Likewise.
96 * aarch64-opc-2.c: Likewise.
97 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
98 * aarch64-opc.c (operand_general_constraint_met_p,
99 aarch64_print_operand): Likewise.
100 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
101 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
102 fmlal2, fmlsl2.
103 (AARCH64_OPERANDS): Add Em2.
104
105 2018-06-26 Nick Clifton <nickc@redhat.com>
106
107 * po/uk.po: Updated Ukranian translation.
108 * po/de.po: Updated German translation.
109 * po/pt_BR.po: Updated Brazilian Portuguese translation.
110
111 2018-06-26 Nick Clifton <nickc@redhat.com>
112
113 * nfp-dis.c: Fix spelling mistake.
114
115 2018-06-24 Nick Clifton <nickc@redhat.com>
116
117 * configure: Regenerate.
118 * po/opcodes.pot: Regenerate.
119
120 2018-06-24 Nick Clifton <nickc@redhat.com>
121
122 2.31 branch created.
123
124 2018-06-19 Tamar Christina <tamar.christina@arm.com>
125
126 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
127 * aarch64-asm-2.c: Regenerate.
128 * aarch64-dis-2.c: Likewise.
129
130 2018-06-21 Maciej W. Rozycki <macro@mips.com>
131
132 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
133 `-M ginv' option description.
134
135 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
136
137 PR gas/23305
138 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
139 la and lla.
140
141 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
142
143 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
144 * configure.ac: Remove AC_PREREQ.
145 * Makefile.in: Re-generate.
146 * aclocal.m4: Re-generate.
147 * configure: Re-generate.
148
149 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
150
151 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
152 mips64r6 descriptors.
153 (parse_mips_ase_option): Handle -Mginv option.
154 (print_mips_disassembler_options): Document -Mginv.
155 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
156 (GINV): New macro.
157 (mips_opcodes): Define ginvi and ginvt.
158
159 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
160 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
161
162 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
163 * mips-opc.c (CRC, CRC64): New macros.
164 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
165 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
166 crc32cd for CRC64.
167
168 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
169
170 PR 20319
171 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
172 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
173
174 2018-06-06 Alan Modra <amodra@gmail.com>
175
176 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
177 setjmp. Move init for some other vars later too.
178
179 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
180
181 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
182 (dis_private): Add new fields for property section tracking.
183 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
184 (xtensa_instruction_fits): New functions.
185 (fetch_data): Bump minimal fetch size to 4.
186 (print_insn_xtensa): Make struct dis_private static.
187 Load and prepare property table on section change.
188 Don't disassemble literals. Don't disassemble instructions that
189 cross property table boundaries.
190
191 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
192
193 * configure: Regenerated.
194
195 2018-06-01 Jan Beulich <jbeulich@suse.com>
196
197 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
198 * i386-tbl.h: Re-generate.
199
200 2018-06-01 Jan Beulich <jbeulich@suse.com>
201
202 * i386-opc.tbl (sldt, str): Add NoRex64.
203 * i386-tbl.h: Re-generate.
204
205 2018-06-01 Jan Beulich <jbeulich@suse.com>
206
207 * i386-opc.tbl (invpcid): Add Oword.
208 * i386-tbl.h: Re-generate.
209
210 2018-06-01 Alan Modra <amodra@gmail.com>
211
212 * sysdep.h (_bfd_error_handler): Don't declare.
213 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
214 * rl78-decode.opc: Likewise.
215 * msp430-decode.c: Regenerate.
216 * rl78-decode.c: Regenerate.
217
218 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
219
220 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
221 * i386-init.h : Regenerated.
222
223 2018-05-25 Alan Modra <amodra@gmail.com>
224
225 * Makefile.in: Regenerate.
226 * po/POTFILES.in: Regenerate.
227
228 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
229
230 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
231 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
232 (insert_bab, extract_bab, insert_btab, extract_btab,
233 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
234 (BAT, BBA VBA RBS XB6S): Delete macros.
235 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
236 (BB, BD, RBX, XC6): Update for new macros.
237 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
238 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
239 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
240 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
241
242 2018-05-18 John Darrington <john@darrington.wattle.id.au>
243
244 * Makefile.am: Add support for s12z architecture.
245 * configure.ac: Likewise.
246 * disassemble.c: Likewise.
247 * disassemble.h: Likewise.
248 * Makefile.in: Regenerate.
249 * configure: Regenerate.
250 * s12z-dis.c: New file.
251 * s12z.h: New file.
252
253 2018-05-18 Alan Modra <amodra@gmail.com>
254
255 * nfp-dis.c: Don't #include libbfd.h.
256 (init_nfp3200_priv): Use bfd_get_section_contents.
257 (nit_nfp6000_mecsr_sec): Likewise.
258
259 2018-05-17 Nick Clifton <nickc@redhat.com>
260
261 * po/zh_CN.po: Updated simplified Chinese translation.
262
263 2018-05-16 Tamar Christina <tamar.christina@arm.com>
264
265 PR binutils/23109
266 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
267 * aarch64-dis-2.c: Regenerate.
268
269 2018-05-15 Tamar Christina <tamar.christina@arm.com>
270
271 PR binutils/21446
272 * aarch64-asm.c (opintl.h): Include.
273 (aarch64_ins_sysreg): Enforce read/write constraints.
274 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
275 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
276 (F_REG_READ, F_REG_WRITE): New.
277 * aarch64-opc.c (aarch64_print_operand): Generate notes for
278 AARCH64_OPND_SYSREG.
279 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
280 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
281 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
282 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
283 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
284 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
285 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
286 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
287 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
288 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
289 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
290 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
291 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
292 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
293 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
294 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
295 msr (F_SYS_WRITE), mrs (F_SYS_READ).
296
297 2018-05-15 Tamar Christina <tamar.christina@arm.com>
298
299 PR binutils/21446
300 * aarch64-dis.c (no_notes: New.
301 (parse_aarch64_dis_option): Support notes.
302 (aarch64_decode_insn, print_operands): Likewise.
303 (print_aarch64_disassembler_options): Document notes.
304 * aarch64-opc.c (aarch64_print_operand): Support notes.
305
306 2018-05-15 Tamar Christina <tamar.christina@arm.com>
307
308 PR binutils/21446
309 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
310 and take error struct.
311 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
312 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
313 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
314 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
315 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
316 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
317 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
318 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
319 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
320 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
321 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
322 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
323 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
324 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
325 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
326 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
327 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
328 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
329 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
330 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
331 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
332 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
333 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
334 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
335 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
336 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
337 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
338 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
339 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
340 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
341 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
342 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
343 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
344 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
345 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
346 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
347 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
348 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
349 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
350 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
351 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
352 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
353 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
354 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
355 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
356 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
357 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
358 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
359 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
360 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
361 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
362 (determine_disassembling_preference, aarch64_decode_insn,
363 print_insn_aarch64_word, print_insn_data): Take errors struct.
364 (print_insn_aarch64): Use errors.
365 * aarch64-asm-2.c: Regenerate.
366 * aarch64-dis-2.c: Regenerate.
367 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
368 boolean in aarch64_insert_operan.
369 (print_operand_extractor): Likewise.
370 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
371
372 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
373
374 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
375
376 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
377
378 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
379
380 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
381
382 * cr16-opc.c (cr16_instruction): Comment typo fix.
383 * hppa-dis.c (print_insn_hppa): Likewise.
384
385 2018-05-08 Jim Wilson <jimw@sifive.com>
386
387 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
388 (match_c_slli64, match_srxi_as_c_srxi): New.
389 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
390 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
391 <c.slli, c.srli, c.srai>: Use match_s_slli.
392 <c.slli64, c.srli64, c.srai64>: New.
393
394 2018-05-08 Alan Modra <amodra@gmail.com>
395
396 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
397 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
398 partition opcode space for index lookup.
399
400 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
401
402 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
403 <insn_length>: ...with this. Update usage.
404 Remove duplicate call to *info->memory_error_func.
405
406 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
407 H.J. Lu <hongjiu.lu@intel.com>
408
409 * i386-dis.c (Gva): New.
410 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
411 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
412 (prefix_table): New instructions (see prefix above).
413 (mod_table): New instructions (see prefix above).
414 (OP_G): Handle va_mode.
415 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
416 CPU_MOVDIR64B_FLAGS.
417 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
418 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
419 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
420 * i386-opc.tbl: Add movidir{i,64b}.
421 * i386-init.h: Regenerated.
422 * i386-tbl.h: Likewise.
423
424 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
425
426 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
427 AddrPrefixOpReg.
428 * i386-opc.h (AddrPrefixOp0): Renamed to ...
429 (AddrPrefixOpReg): This.
430 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
431 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
432
433 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
434
435 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
436 (vle_num_opcodes): Likewise.
437 (spe2_num_opcodes): Likewise.
438 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
439 initialization loop.
440 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
441 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
442 only once.
443
444 2018-05-01 Tamar Christina <tamar.christina@arm.com>
445
446 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
447
448 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
449
450 Makefile.am: Added nfp-dis.c.
451 configure.ac: Added bfd_nfp_arch.
452 disassemble.h: Added print_insn_nfp prototype.
453 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
454 nfp-dis.c: New, for NFP support.
455 po/POTFILES.in: Added nfp-dis.c to the list.
456 Makefile.in: Regenerate.
457 configure: Regenerate.
458
459 2018-04-26 Jan Beulich <jbeulich@suse.com>
460
461 * i386-opc.tbl: Fold various non-memory operand AVX512VL
462 templates into their base ones.
463 * i386-tlb.h: Re-generate.
464
465 2018-04-26 Jan Beulich <jbeulich@suse.com>
466
467 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
468 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
469 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
470 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
471 * i386-init.h: Re-generate.
472
473 2018-04-26 Jan Beulich <jbeulich@suse.com>
474
475 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
476 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
477 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
478 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
479 comment.
480 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
481 and CpuRegMask.
482 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
483 CpuRegMask: Delete.
484 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
485 cpuregzmm, and cpuregmask.
486 * i386-init.h: Re-generate.
487 * i386-tbl.h: Re-generate.
488
489 2018-04-26 Jan Beulich <jbeulich@suse.com>
490
491 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
492 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
493 * i386-init.h: Re-generate.
494
495 2018-04-26 Jan Beulich <jbeulich@suse.com>
496
497 * i386-gen.c (VexImmExt): Delete.
498 * i386-opc.h (VexImmExt, veximmext): Delete.
499 * i386-opc.tbl: Drop all VexImmExt uses.
500 * i386-tlb.h: Re-generate.
501
502 2018-04-25 Jan Beulich <jbeulich@suse.com>
503
504 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
505 register-only forms.
506 * i386-tlb.h: Re-generate.
507
508 2018-04-25 Tamar Christina <tamar.christina@arm.com>
509
510 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
511
512 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
513
514 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
515 PREFIX_0F1C.
516 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
517 (cpu_flags): Add CpuCLDEMOTE.
518 * i386-init.h: Regenerate.
519 * i386-opc.h (enum): Add CpuCLDEMOTE,
520 (i386_cpu_flags): Add cpucldemote.
521 * i386-opc.tbl: Add cldemote.
522 * i386-tbl.h: Regenerate.
523
524 2018-04-16 Alan Modra <amodra@gmail.com>
525
526 * Makefile.am: Remove sh5 and sh64 support.
527 * configure.ac: Likewise.
528 * disassemble.c: Likewise.
529 * disassemble.h: Likewise.
530 * sh-dis.c: Likewise.
531 * sh64-dis.c: Delete.
532 * sh64-opc.c: Delete.
533 * sh64-opc.h: Delete.
534 * Makefile.in: Regenerate.
535 * configure: Regenerate.
536 * po/POTFILES.in: Regenerate.
537
538 2018-04-16 Alan Modra <amodra@gmail.com>
539
540 * Makefile.am: Remove w65 support.
541 * configure.ac: Likewise.
542 * disassemble.c: Likewise.
543 * disassemble.h: Likewise.
544 * w65-dis.c: Delete.
545 * w65-opc.h: Delete.
546 * Makefile.in: Regenerate.
547 * configure: Regenerate.
548 * po/POTFILES.in: Regenerate.
549
550 2018-04-16 Alan Modra <amodra@gmail.com>
551
552 * configure.ac: Remove we32k support.
553 * configure: Regenerate.
554
555 2018-04-16 Alan Modra <amodra@gmail.com>
556
557 * Makefile.am: Remove m88k support.
558 * configure.ac: Likewise.
559 * disassemble.c: Likewise.
560 * disassemble.h: Likewise.
561 * m88k-dis.c: Delete.
562 * Makefile.in: Regenerate.
563 * configure: Regenerate.
564 * po/POTFILES.in: Regenerate.
565
566 2018-04-16 Alan Modra <amodra@gmail.com>
567
568 * Makefile.am: Remove i370 support.
569 * configure.ac: Likewise.
570 * disassemble.c: Likewise.
571 * disassemble.h: Likewise.
572 * i370-dis.c: Delete.
573 * i370-opc.c: Delete.
574 * Makefile.in: Regenerate.
575 * configure: Regenerate.
576 * po/POTFILES.in: Regenerate.
577
578 2018-04-16 Alan Modra <amodra@gmail.com>
579
580 * Makefile.am: Remove h8500 support.
581 * configure.ac: Likewise.
582 * disassemble.c: Likewise.
583 * disassemble.h: Likewise.
584 * h8500-dis.c: Delete.
585 * h8500-opc.h: Delete.
586 * Makefile.in: Regenerate.
587 * configure: Regenerate.
588 * po/POTFILES.in: Regenerate.
589
590 2018-04-16 Alan Modra <amodra@gmail.com>
591
592 * configure.ac: Remove tahoe support.
593 * configure: Regenerate.
594
595 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
596
597 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
598 umwait.
599 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
600 64-bit mode.
601 * i386-tbl.h: Regenerated.
602
603 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
604
605 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
606 PREFIX_MOD_1_0FAE_REG_6.
607 (va_mode): New.
608 (OP_E_register): Use va_mode.
609 * i386-dis-evex.h (prefix_table):
610 New instructions (see prefixes above).
611 * i386-gen.c (cpu_flag_init): Add WAITPKG.
612 (cpu_flags): Likewise.
613 * i386-opc.h (enum): Likewise.
614 (i386_cpu_flags): Likewise.
615 * i386-opc.tbl: Add umonitor, umwait, tpause.
616 * i386-init.h: Regenerate.
617 * i386-tbl.h: Likewise.
618
619 2018-04-11 Alan Modra <amodra@gmail.com>
620
621 * opcodes/i860-dis.c: Delete.
622 * opcodes/i960-dis.c: Delete.
623 * Makefile.am: Remove i860 and i960 support.
624 * configure.ac: Likewise.
625 * disassemble.c: Likewise.
626 * disassemble.h: Likewise.
627 * Makefile.in: Regenerate.
628 * configure: Regenerate.
629 * po/POTFILES.in: Regenerate.
630
631 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
632
633 PR binutils/23025
634 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
635 to 0.
636 (print_insn): Clear vex instead of vex.evex.
637
638 2018-04-04 Nick Clifton <nickc@redhat.com>
639
640 * po/es.po: Updated Spanish translation.
641
642 2018-03-28 Jan Beulich <jbeulich@suse.com>
643
644 * i386-gen.c (opcode_modifiers): Delete VecESize.
645 * i386-opc.h (VecESize): Delete.
646 (struct i386_opcode_modifier): Delete vecesize.
647 * i386-opc.tbl: Drop VecESize.
648 * i386-tlb.h: Re-generate.
649
650 2018-03-28 Jan Beulich <jbeulich@suse.com>
651
652 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
653 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
654 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
655 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
656 * i386-tlb.h: Re-generate.
657
658 2018-03-28 Jan Beulich <jbeulich@suse.com>
659
660 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
661 Fold AVX512 forms
662 * i386-tlb.h: Re-generate.
663
664 2018-03-28 Jan Beulich <jbeulich@suse.com>
665
666 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
667 (vex_len_table): Drop Y for vcvt*2si.
668 (putop): Replace plain 'Y' handling by abort().
669
670 2018-03-28 Nick Clifton <nickc@redhat.com>
671
672 PR 22988
673 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
674 instructions with only a base address register.
675 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
676 handle AARHC64_OPND_SVE_ADDR_R.
677 (aarch64_print_operand): Likewise.
678 * aarch64-asm-2.c: Regenerate.
679 * aarch64_dis-2.c: Regenerate.
680 * aarch64-opc-2.c: Regenerate.
681
682 2018-03-22 Jan Beulich <jbeulich@suse.com>
683
684 * i386-opc.tbl: Drop VecESize from register only insn forms and
685 memory forms not allowing broadcast.
686 * i386-tlb.h: Re-generate.
687
688 2018-03-22 Jan Beulich <jbeulich@suse.com>
689
690 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
691 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
692 sha256*): Drop Disp<N>.
693
694 2018-03-22 Jan Beulich <jbeulich@suse.com>
695
696 * i386-dis.c (EbndS, bnd_swap_mode): New.
697 (prefix_table): Use EbndS.
698 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
699 * i386-opc.tbl (bndmov): Move misplaced Load.
700 * i386-tlb.h: Re-generate.
701
702 2018-03-22 Jan Beulich <jbeulich@suse.com>
703
704 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
705 templates allowing memory operands and folded ones for register
706 only flavors.
707 * i386-tlb.h: Re-generate.
708
709 2018-03-22 Jan Beulich <jbeulich@suse.com>
710
711 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
712 256-bit templates. Drop redundant leftover Disp<N>.
713 * i386-tlb.h: Re-generate.
714
715 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
716
717 * riscv-opc.c (riscv_insn_types): New.
718
719 2018-03-13 Nick Clifton <nickc@redhat.com>
720
721 * po/pt_BR.po: Updated Brazilian Portuguese translation.
722
723 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
724
725 * i386-opc.tbl: Add Optimize to clr.
726 * i386-tbl.h: Regenerated.
727
728 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386-gen.c (opcode_modifiers): Remove OldGcc.
731 * i386-opc.h (OldGcc): Removed.
732 (i386_opcode_modifier): Remove oldgcc.
733 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
734 instructions for old (<= 2.8.1) versions of gcc.
735 * i386-tbl.h: Regenerated.
736
737 2018-03-08 Jan Beulich <jbeulich@suse.com>
738
739 * i386-opc.h (EVEXDYN): New.
740 * i386-opc.tbl: Fold various AVX512VL templates.
741 * i386-tlb.h: Re-generate.
742
743 2018-03-08 Jan Beulich <jbeulich@suse.com>
744
745 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
746 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
747 vpexpandd, vpexpandq): Fold AFX512VF templates.
748 * i386-tlb.h: Re-generate.
749
750 2018-03-08 Jan Beulich <jbeulich@suse.com>
751
752 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
753 Fold 128- and 256-bit VEX-encoded templates.
754 * i386-tlb.h: Re-generate.
755
756 2018-03-08 Jan Beulich <jbeulich@suse.com>
757
758 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
759 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
760 vpexpandd, vpexpandq): Fold AVX512F templates.
761 * i386-tlb.h: Re-generate.
762
763 2018-03-08 Jan Beulich <jbeulich@suse.com>
764
765 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
766 64-bit templates. Drop Disp<N>.
767 * i386-tlb.h: Re-generate.
768
769 2018-03-08 Jan Beulich <jbeulich@suse.com>
770
771 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
772 and 256-bit templates.
773 * i386-tlb.h: Re-generate.
774
775 2018-03-08 Jan Beulich <jbeulich@suse.com>
776
777 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
778 * i386-tlb.h: Re-generate.
779
780 2018-03-08 Jan Beulich <jbeulich@suse.com>
781
782 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
783 Drop NoAVX.
784 * i386-tlb.h: Re-generate.
785
786 2018-03-08 Jan Beulich <jbeulich@suse.com>
787
788 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
789 * i386-tlb.h: Re-generate.
790
791 2018-03-08 Jan Beulich <jbeulich@suse.com>
792
793 * i386-gen.c (opcode_modifiers): Delete FloatD.
794 * i386-opc.h (FloatD): Delete.
795 (struct i386_opcode_modifier): Delete floatd.
796 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
797 FloatD by D.
798 * i386-tlb.h: Re-generate.
799
800 2018-03-08 Jan Beulich <jbeulich@suse.com>
801
802 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
803
804 2018-03-08 Jan Beulich <jbeulich@suse.com>
805
806 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
807 * i386-tlb.h: Re-generate.
808
809 2018-03-08 Jan Beulich <jbeulich@suse.com>
810
811 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
812 forms.
813 * i386-tlb.h: Re-generate.
814
815 2018-03-07 Alan Modra <amodra@gmail.com>
816
817 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
818 bfd_arch_rs6000.
819 * disassemble.h (print_insn_rs6000): Delete.
820 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
821 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
822 (print_insn_rs6000): Delete.
823
824 2018-03-03 Alan Modra <amodra@gmail.com>
825
826 * sysdep.h (opcodes_error_handler): Define.
827 (_bfd_error_handler): Declare.
828 * Makefile.am: Remove stray #.
829 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
830 EDIT" comment.
831 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
832 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
833 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
834 opcodes_error_handler to print errors. Standardize error messages.
835 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
836 and include opintl.h.
837 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
838 * i386-gen.c: Standardize error messages.
839 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
840 * Makefile.in: Regenerate.
841 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
842 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
843 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
844 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
845 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
846 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
847 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
848 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
849 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
850 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
851 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
852 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
853 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
854
855 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
856
857 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
858 vpsub[bwdq] instructions.
859 * i386-tbl.h: Regenerated.
860
861 2018-03-01 Alan Modra <amodra@gmail.com>
862
863 * configure.ac (ALL_LINGUAS): Sort.
864 * configure: Regenerate.
865
866 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
867
868 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
869 macro by assignements.
870
871 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
872
873 PR gas/22871
874 * i386-gen.c (opcode_modifiers): Add Optimize.
875 * i386-opc.h (Optimize): New enum.
876 (i386_opcode_modifier): Add optimize.
877 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
878 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
879 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
880 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
881 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
882 vpxord and vpxorq.
883 * i386-tbl.h: Regenerated.
884
885 2018-02-26 Alan Modra <amodra@gmail.com>
886
887 * crx-dis.c (getregliststring): Allocate a large enough buffer
888 to silence false positive gcc8 warning.
889
890 2018-02-22 Shea Levy <shea@shealevy.com>
891
892 * disassemble.c (ARCH_riscv): Define if ARCH_all.
893
894 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
895
896 * i386-opc.tbl: Add {rex},
897 * i386-tbl.h: Regenerated.
898
899 2018-02-20 Maciej W. Rozycki <macro@mips.com>
900
901 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
902 (mips16_opcodes): Replace `M' with `m' for "restore".
903
904 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
905
906 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
907
908 2018-02-13 Maciej W. Rozycki <macro@mips.com>
909
910 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
911 variable to `function_index'.
912
913 2018-02-13 Nick Clifton <nickc@redhat.com>
914
915 PR 22823
916 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
917 about truncation of printing.
918
919 2018-02-12 Henry Wong <henry@stuffedcow.net>
920
921 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
922
923 2018-02-05 Nick Clifton <nickc@redhat.com>
924
925 * po/pt_BR.po: Updated Brazilian Portuguese translation.
926
927 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
928
929 * i386-dis.c (enum): Add pconfig.
930 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
931 (cpu_flags): Add CpuPCONFIG.
932 * i386-opc.h (enum): Add CpuPCONFIG.
933 (i386_cpu_flags): Add cpupconfig.
934 * i386-opc.tbl: Add PCONFIG instruction.
935 * i386-init.h: Regenerate.
936 * i386-tbl.h: Likewise.
937
938 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
939
940 * i386-dis.c (enum): Add PREFIX_0F09.
941 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
942 (cpu_flags): Add CpuWBNOINVD.
943 * i386-opc.h (enum): Add CpuWBNOINVD.
944 (i386_cpu_flags): Add cpuwbnoinvd.
945 * i386-opc.tbl: Add WBNOINVD instruction.
946 * i386-init.h: Regenerate.
947 * i386-tbl.h: Likewise.
948
949 2018-01-17 Jim Wilson <jimw@sifive.com>
950
951 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
952
953 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
954
955 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
956 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
957 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
958 (cpu_flags): Add CpuIBT, CpuSHSTK.
959 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
960 (i386_cpu_flags): Add cpuibt, cpushstk.
961 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
962 * i386-init.h: Regenerate.
963 * i386-tbl.h: Likewise.
964
965 2018-01-16 Nick Clifton <nickc@redhat.com>
966
967 * po/pt_BR.po: Updated Brazilian Portugese translation.
968 * po/de.po: Updated German translation.
969
970 2018-01-15 Jim Wilson <jimw@sifive.com>
971
972 * riscv-opc.c (match_c_nop): New.
973 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
974
975 2018-01-15 Nick Clifton <nickc@redhat.com>
976
977 * po/uk.po: Updated Ukranian translation.
978
979 2018-01-13 Nick Clifton <nickc@redhat.com>
980
981 * po/opcodes.pot: Regenerated.
982
983 2018-01-13 Nick Clifton <nickc@redhat.com>
984
985 * configure: Regenerate.
986
987 2018-01-13 Nick Clifton <nickc@redhat.com>
988
989 2.30 branch created.
990
991 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
992
993 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
994 * i386-tbl.h: Regenerate.
995
996 2018-01-10 Jan Beulich <jbeulich@suse.com>
997
998 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
999 * i386-tbl.h: Re-generate.
1000
1001 2018-01-10 Jan Beulich <jbeulich@suse.com>
1002
1003 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1004 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1005 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1006 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1007 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1008 Disp8MemShift of AVX512VL forms.
1009 * i386-tbl.h: Re-generate.
1010
1011 2018-01-09 Jim Wilson <jimw@sifive.com>
1012
1013 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1014 then the hi_addr value is zero.
1015
1016 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1017
1018 * arm-dis.c (arm_opcodes): Add csdb.
1019 (thumb32_opcodes): Add csdb.
1020
1021 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1022
1023 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1024 * aarch64-asm-2.c: Regenerate.
1025 * aarch64-dis-2.c: Regenerate.
1026 * aarch64-opc-2.c: Regenerate.
1027
1028 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1029
1030 PR gas/22681
1031 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1032 Remove AVX512 vmovd with 64-bit operands.
1033 * i386-tbl.h: Regenerated.
1034
1035 2018-01-05 Jim Wilson <jimw@sifive.com>
1036
1037 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1038 jalr.
1039
1040 2018-01-03 Alan Modra <amodra@gmail.com>
1041
1042 Update year range in copyright notice of all files.
1043
1044 2018-01-02 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1047 and OPERAND_TYPE_REGZMM entries.
1048
1049 For older changes see ChangeLog-2017
1050 \f
1051 Copyright (C) 2018 Free Software Foundation, Inc.
1052
1053 Copying and distribution of this file, with or without modification,
1054 are permitted in any medium without royalty provided the copyright
1055 notice and this notice are preserved.
1056
1057 Local Variables:
1058 mode: change-log
1059 left-margin: 8
1060 fill-column: 74
1061 version-control: never
1062 End: