opcodes/ChangeLog

   1 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Fold AVX512DQ templates into their respective
   4         AVX512VL counterparts where possible, using Disp8ShiftVL and
   5         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
   6         IgnoreSize) as appropriate.
   7         * i386-tbl.h: Re-generate.
   8
   9 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.tbl: Fold AVX512BW templates into their respective
  12         AVX512VL counterparts where possible, using Disp8ShiftVL and
  13         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  14         IgnoreSize) as appropriate.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl: Fold AVX512CD templates into their respective
  20         AVX512VL counterparts where possible, using Disp8ShiftVL and
  21         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  22         IgnoreSize) as appropriate.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.h (DISP8_SHIFT_VL): New.
  28         * i386-opc.tbl (Disp8ShiftVL):  Define.
  29         (various): Fold AVX512VL templates into their respective
  30         AVX512F counterparts where possible, using Disp8ShiftVL and
  31         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  32         IgnoreSize) as appropriate.
  33         * i386-tbl.h: Re-generate.
  34
  35 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  36
  37         * Makefile.am: Change dependencies and rule for
  38         $(srcdir)/i386-init.h.
  39         * Makefile.in: Re-generate.
  40         * i386-gen.c (process_i386_opcodes): New local variable
  41         "marker". Drop opening of input file. Recognize marker and line
  42         number directives.
  43         * i386-opc.tbl (OPCODE_I386_H): Define.
  44         (i386-opc.h): Include it.
  45         (None): Undefine.
  46
  47 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         PR gas/23418
  50         * i386-opc.h (Byte): Update comments.
  51         (Word): Likewise.
  52         (Dword): Likewise.
  53         (Fword): Likewise.
  54         (Qword): Likewise.
  55         (Tbyte): Likewise.
  56         (Xmmword): Likewise.
  57         (Ymmword): Likewise.
  58         (Zmmword): Likewise.
  59         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
  60         vcvttps2uqq.
  61         * i386-tbl.h: Regenerated.
  62
  63 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
  66         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
  67         * aarch64-asm-2.c: Regenerate.
  68         * aarch64-dis-2.c: Regenerate.
  69         * aarch64-opc-2.c: Regenerate.
  70
  71 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
  72
  73         PR binutils/23192
  74         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
  75         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
  76         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
  77         sqdmulh, sqrdmulh): Use Em16.
  78
  79 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
  80
  81         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
  82         csdb together with them.
  83         (thumb32_opcodes): Likewise.
  84
  85 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
  88         requiring 32-bit registers as operands 2 and 3. Improve
  89         comments.
  90         (mwait, mwaitx): Fold templates. Improve comments.
  91         OPERAND_TYPE_INOUTPORTREG.
  92         * i386-tbl.h: Re-generate.
  93
  94 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-gen.c (operand_type_init): Remove
  97         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
  98         OPERAND_TYPE_INOUTPORTREG.
  99         * i386-init.h: Re-generate.
 100
 101 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 104         (wrssq, wrussq): Add Qword.
 105         * i386-tbl.h: Re-generate.
 106
 107 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.h: Rename OTMax to OTNum.
 110         (OTNumOfUints): Adjust calculation.
 111         (OTUnused): Directly alias to OTNum.
 112
 113 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 114
 115         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 116         `reg_xys'.
 117         (lea_reg_xys): Likewise.
 118         (print_insn_loop_primitive): Rename `reg' local variable to
 119         `reg_dxy'.
 120
 121 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 122
 123         PR binutils/23242
 124         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 125
 126 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 127
 128         PR binutils/23369
 129         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 130         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 131
 132 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 133
 134         PR tdep/8282
 135         * mips-dis.c (mips_option_arg_t): New enumeration.
 136         (mips_options): New variable.
 137         (disassembler_options_mips): New function.
 138         (print_mips_disassembler_options): Reimplement in terms of
 139         `disassembler_options_mips'.
 140         * arm-dis.c (disassembler_options_arm): Adapt to using the
 141         `disasm_options_and_args_t' structure.
 142         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 143         * s390-dis.c (disassembler_options_s390): Likewise.
 144
 145 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 146
 147         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 148         expected result.
 149         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 150         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 151         * testsuite/ld-arm/tls-longplt.d: Likewise.
 152
 153 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 154
 155         PR binutils/23192
 156         * aarch64-asm-2.c: Regenerate.
 157         * aarch64-dis-2.c: Likewise.
 158         * aarch64-opc-2.c: Likewise.
 159         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 160         * aarch64-opc.c (operand_general_constraint_met_p,
 161         aarch64_print_operand): Likewise.
 162         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 163         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 164         fmlal2, fmlsl2.
 165         (AARCH64_OPERANDS): Add Em2.
 166
 167 2018-06-26  Nick Clifton  <nickc@redhat.com>
 168
 169         * po/uk.po: Updated Ukranian translation.
 170         * po/de.po: Updated German translation.
 171         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 172
 173 2018-06-26  Nick Clifton  <nickc@redhat.com>
 174
 175         * nfp-dis.c: Fix spelling mistake.
 176
 177 2018-06-24  Nick Clifton  <nickc@redhat.com>
 178
 179         * configure: Regenerate.
 180         * po/opcodes.pot: Regenerate.
 181
 182 2018-06-24  Nick Clifton  <nickc@redhat.com>
 183
 184         2.31 branch created.
 185
 186 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 187
 188         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 189         * aarch64-asm-2.c: Regenerate.
 190         * aarch64-dis-2.c: Likewise.
 191
 192 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 193
 194         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 195         `-M ginv' option description.
 196
 197 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 198
 199         PR gas/23305
 200         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 201         la and lla.
 202
 203 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 204
 205         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 206         * configure.ac: Remove AC_PREREQ.
 207         * Makefile.in: Re-generate.
 208         * aclocal.m4: Re-generate.
 209         * configure: Re-generate.
 210
 211 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 212
 213         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 214         mips64r6 descriptors.
 215         (parse_mips_ase_option): Handle -Mginv option.
 216         (print_mips_disassembler_options): Document -Mginv.
 217         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 218         (GINV): New macro.
 219         (mips_opcodes): Define ginvi and ginvt.
 220
 221 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 222             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 223
 224         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 225         * mips-opc.c (CRC, CRC64): New macros.
 226         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 227         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 228         crc32cd for CRC64.
 229
 230 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 231
 232         PR 20319
 233         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 234         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 235
 236 2018-06-06  Alan Modra  <amodra@gmail.com>
 237
 238         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 239         setjmp.  Move init for some other vars later too.
 240
 241 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 242
 243         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 244         (dis_private): Add new fields for property section tracking.
 245         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 246         (xtensa_instruction_fits): New functions.
 247         (fetch_data): Bump minimal fetch size to 4.
 248         (print_insn_xtensa): Make struct dis_private static.
 249         Load and prepare property table on section change.
 250         Don't disassemble literals. Don't disassemble instructions that
 251         cross property table boundaries.
 252
 253 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * configure: Regenerated.
 256
 257 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 260         * i386-tbl.h: Re-generate.
 261
 262 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-opc.tbl (sldt, str): Add NoRex64.
 265         * i386-tbl.h: Re-generate.
 266
 267 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-opc.tbl (invpcid): Add Oword.
 270         * i386-tbl.h: Re-generate.
 271
 272 2018-06-01  Alan Modra  <amodra@gmail.com>
 273
 274         * sysdep.h (_bfd_error_handler): Don't declare.
 275         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 276         * rl78-decode.opc: Likewise.
 277         * msp430-decode.c: Regenerate.
 278         * rl78-decode.c: Regenerate.
 279
 280 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 281
 282         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 283         * i386-init.h : Regenerated.
 284
 285 2018-05-25  Alan Modra  <amodra@gmail.com>
 286
 287         * Makefile.in: Regenerate.
 288         * po/POTFILES.in: Regenerate.
 289
 290 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 291
 292         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 293         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 294         (insert_bab, extract_bab, insert_btab, extract_btab,
 295         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 296         (BAT, BBA VBA RBS XB6S): Delete macros.
 297         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 298         (BB, BD, RBX, XC6): Update for new macros.
 299         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 300         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 301         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 302         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 303
 304 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 305
 306         * Makefile.am: Add support for s12z architecture.
 307         * configure.ac: Likewise.
 308         * disassemble.c: Likewise.
 309         * disassemble.h: Likewise.
 310         * Makefile.in: Regenerate.
 311         * configure: Regenerate.
 312         * s12z-dis.c: New file.
 313         * s12z.h: New file.
 314
 315 2018-05-18  Alan Modra  <amodra@gmail.com>
 316
 317         * nfp-dis.c: Don't #include libbfd.h.
 318         (init_nfp3200_priv): Use bfd_get_section_contents.
 319         (nit_nfp6000_mecsr_sec): Likewise.
 320
 321 2018-05-17  Nick Clifton  <nickc@redhat.com>
 322
 323         * po/zh_CN.po: Updated simplified Chinese translation.
 324
 325 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 326
 327         PR binutils/23109
 328         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 329         * aarch64-dis-2.c: Regenerate.
 330
 331 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 332
 333         PR binutils/21446
 334         * aarch64-asm.c (opintl.h): Include.
 335         (aarch64_ins_sysreg): Enforce read/write constraints.
 336         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 337         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 338         (F_REG_READ, F_REG_WRITE): New.
 339         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 340         AARCH64_OPND_SYSREG.
 341         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 342         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 343         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 344         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 345         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 346         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 347         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 348         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 349         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 350         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 351         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 352         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 353         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 354         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 355         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 356         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 357         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 358
 359 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 360
 361         PR binutils/21446
 362         * aarch64-dis.c (no_notes: New.
 363         (parse_aarch64_dis_option): Support notes.
 364         (aarch64_decode_insn, print_operands): Likewise.
 365         (print_aarch64_disassembler_options): Document notes.
 366         * aarch64-opc.c (aarch64_print_operand): Support notes.
 367
 368 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 369
 370         PR binutils/21446
 371         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 372         and take error struct.
 373         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 374         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 375         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 376         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 377         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 378         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 379         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 380         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 381         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 382         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 383         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 384         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 385         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 386         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 387         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 388         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 389         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 390         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 391         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 392         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 393         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 394         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 395         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 396         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 397         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 398         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 399         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 400         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 401         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 402         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 403         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 404         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 405         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 406         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 407         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 408         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 409         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 410         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 411         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 412         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 413         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 414         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 415         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 416         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 417         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 418         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 419         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 420         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 421         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 422         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 423         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 424         (determine_disassembling_preference, aarch64_decode_insn,
 425         print_insn_aarch64_word, print_insn_data): Take errors struct.
 426         (print_insn_aarch64): Use errors.
 427         * aarch64-asm-2.c: Regenerate.
 428         * aarch64-dis-2.c: Regenerate.
 429         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 430         boolean in aarch64_insert_operan.
 431         (print_operand_extractor): Likewise.
 432         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 433
 434 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 435
 436         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 437
 438 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 441
 442 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 443
 444         * cr16-opc.c (cr16_instruction): Comment typo fix.
 445         * hppa-dis.c (print_insn_hppa): Likewise.
 446
 447 2018-05-08  Jim Wilson  <jimw@sifive.com>
 448
 449         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 450         (match_c_slli64, match_srxi_as_c_srxi): New.
 451         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 452         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 453         <c.slli, c.srli, c.srai>: Use match_s_slli.
 454         <c.slli64, c.srli64, c.srai64>: New.
 455
 456 2018-05-08  Alan Modra  <amodra@gmail.com>
 457
 458         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 459         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 460         partition opcode space for index lookup.
 461
 462 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 463
 464         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 465         <insn_length>: ...with this.  Update usage.
 466         Remove duplicate call to *info->memory_error_func.
 467
 468 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 469             H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         * i386-dis.c (Gva): New.
 472         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 473         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 474         (prefix_table): New instructions (see prefix above).
 475         (mod_table): New instructions (see prefix above).
 476         (OP_G): Handle va_mode.
 477         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 478         CPU_MOVDIR64B_FLAGS.
 479         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 480         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 481         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 482         * i386-opc.tbl: Add movidir{i,64b}.
 483         * i386-init.h: Regenerated.
 484         * i386-tbl.h: Likewise.
 485
 486 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 489         AddrPrefixOpReg.
 490         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 491         (AddrPrefixOpReg): This.
 492         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 493         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 494
 495 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 496
 497         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 498         (vle_num_opcodes): Likewise.
 499         (spe2_num_opcodes): Likewise.
 500         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 501         initialization loop.
 502         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 503         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 504         only once.
 505
 506 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 507
 508         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 509
 510 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 511
 512         Makefile.am: Added nfp-dis.c.
 513         configure.ac: Added bfd_nfp_arch.
 514         disassemble.h: Added print_insn_nfp prototype.
 515         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 516         nfp-dis.c: New, for NFP support.
 517         po/POTFILES.in: Added nfp-dis.c to the list.
 518         Makefile.in: Regenerate.
 519         configure: Regenerate.
 520
 521 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 524         templates into their base ones.
 525         * i386-tlb.h: Re-generate.
 526
 527 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 530         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 531         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 532         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 533         * i386-init.h: Re-generate.
 534
 535 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 538         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 539         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 540         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 541         comment.
 542         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 543         and CpuRegMask.
 544         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 545         CpuRegMask: Delete.
 546         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 547         cpuregzmm, and cpuregmask.
 548         * i386-init.h: Re-generate.
 549         * i386-tbl.h: Re-generate.
 550
 551 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 554         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 555         * i386-init.h: Re-generate.
 556
 557 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-gen.c (VexImmExt): Delete.
 560         * i386-opc.h (VexImmExt, veximmext): Delete.
 561         * i386-opc.tbl: Drop all VexImmExt uses.
 562         * i386-tlb.h: Re-generate.
 563
 564 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 567         register-only forms.
 568         * i386-tlb.h: Re-generate.
 569
 570 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 571
 572         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 573
 574 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 575
 576         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 577         PREFIX_0F1C.
 578         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 579         (cpu_flags): Add CpuCLDEMOTE.
 580         * i386-init.h: Regenerate.
 581         * i386-opc.h (enum): Add CpuCLDEMOTE,
 582         (i386_cpu_flags): Add cpucldemote.
 583         * i386-opc.tbl: Add cldemote.
 584         * i386-tbl.h: Regenerate.
 585
 586 2018-04-16  Alan Modra  <amodra@gmail.com>
 587
 588         * Makefile.am: Remove sh5 and sh64 support.
 589         * configure.ac: Likewise.
 590         * disassemble.c: Likewise.
 591         * disassemble.h: Likewise.
 592         * sh-dis.c: Likewise.
 593         * sh64-dis.c: Delete.
 594         * sh64-opc.c: Delete.
 595         * sh64-opc.h: Delete.
 596         * Makefile.in: Regenerate.
 597         * configure: Regenerate.
 598         * po/POTFILES.in: Regenerate.
 599
 600 2018-04-16  Alan Modra  <amodra@gmail.com>
 601
 602         * Makefile.am: Remove w65 support.
 603         * configure.ac: Likewise.
 604         * disassemble.c: Likewise.
 605         * disassemble.h: Likewise.
 606         * w65-dis.c: Delete.
 607         * w65-opc.h: Delete.
 608         * Makefile.in: Regenerate.
 609         * configure: Regenerate.
 610         * po/POTFILES.in: Regenerate.
 611
 612 2018-04-16  Alan Modra  <amodra@gmail.com>
 613
 614         * configure.ac: Remove we32k support.
 615         * configure: Regenerate.
 616
 617 2018-04-16  Alan Modra  <amodra@gmail.com>
 618
 619         * Makefile.am: Remove m88k support.
 620         * configure.ac: Likewise.
 621         * disassemble.c: Likewise.
 622         * disassemble.h: Likewise.
 623         * m88k-dis.c: Delete.
 624         * Makefile.in: Regenerate.
 625         * configure: Regenerate.
 626         * po/POTFILES.in: Regenerate.
 627
 628 2018-04-16  Alan Modra  <amodra@gmail.com>
 629
 630         * Makefile.am: Remove i370 support.
 631         * configure.ac: Likewise.
 632         * disassemble.c: Likewise.
 633         * disassemble.h: Likewise.
 634         * i370-dis.c: Delete.
 635         * i370-opc.c: Delete.
 636         * Makefile.in: Regenerate.
 637         * configure: Regenerate.
 638         * po/POTFILES.in: Regenerate.
 639
 640 2018-04-16  Alan Modra  <amodra@gmail.com>
 641
 642         * Makefile.am: Remove h8500 support.
 643         * configure.ac: Likewise.
 644         * disassemble.c: Likewise.
 645         * disassemble.h: Likewise.
 646         * h8500-dis.c: Delete.
 647         * h8500-opc.h: Delete.
 648         * Makefile.in: Regenerate.
 649         * configure: Regenerate.
 650         * po/POTFILES.in: Regenerate.
 651
 652 2018-04-16  Alan Modra  <amodra@gmail.com>
 653
 654         * configure.ac: Remove tahoe support.
 655         * configure: Regenerate.
 656
 657 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 660         umwait.
 661         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 662         64-bit mode.
 663         * i386-tbl.h: Regenerated.
 664
 665 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 666
 667         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 668         PREFIX_MOD_1_0FAE_REG_6.
 669         (va_mode): New.
 670         (OP_E_register): Use va_mode.
 671         * i386-dis-evex.h (prefix_table):
 672         New instructions (see prefixes above).
 673         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 674         (cpu_flags): Likewise.
 675         * i386-opc.h (enum): Likewise.
 676         (i386_cpu_flags): Likewise.
 677         * i386-opc.tbl: Add umonitor, umwait, tpause.
 678         * i386-init.h: Regenerate.
 679         * i386-tbl.h: Likewise.
 680
 681 2018-04-11  Alan Modra  <amodra@gmail.com>
 682
 683         * opcodes/i860-dis.c: Delete.
 684         * opcodes/i960-dis.c: Delete.
 685         * Makefile.am: Remove i860 and i960 support.
 686         * configure.ac: Likewise.
 687         * disassemble.c: Likewise.
 688         * disassemble.h: Likewise.
 689         * Makefile.in: Regenerate.
 690         * configure: Regenerate.
 691         * po/POTFILES.in: Regenerate.
 692
 693 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 694
 695         PR binutils/23025
 696         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 697         to 0.
 698         (print_insn): Clear vex instead of vex.evex.
 699
 700 2018-04-04  Nick Clifton  <nickc@redhat.com>
 701
 702         * po/es.po: Updated Spanish translation.
 703
 704 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-gen.c (opcode_modifiers): Delete VecESize.
 707         * i386-opc.h (VecESize): Delete.
 708         (struct i386_opcode_modifier): Delete vecesize.
 709         * i386-opc.tbl: Drop VecESize.
 710         * i386-tlb.h: Re-generate.
 711
 712 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 715         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 716         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 717         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 718         * i386-tlb.h: Re-generate.
 719
 720 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 723         Fold AVX512 forms
 724         * i386-tlb.h: Re-generate.
 725
 726 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 729         (vex_len_table): Drop Y for vcvt*2si.
 730         (putop): Replace plain 'Y' handling by abort().
 731
 732 2018-03-28  Nick Clifton  <nickc@redhat.com>
 733
 734         PR 22988
 735         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 736         instructions with only a base address register.
 737         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 738         handle AARHC64_OPND_SVE_ADDR_R.
 739         (aarch64_print_operand): Likewise.
 740         * aarch64-asm-2.c: Regenerate.
 741         * aarch64_dis-2.c: Regenerate.
 742         * aarch64-opc-2.c: Regenerate.
 743
 744 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-opc.tbl: Drop VecESize from register only insn forms and
 747         memory forms not allowing broadcast.
 748         * i386-tlb.h: Re-generate.
 749
 750 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 753         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 754         sha256*): Drop Disp<N>.
 755
 756 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-dis.c (EbndS, bnd_swap_mode): New.
 759         (prefix_table): Use EbndS.
 760         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 761         * i386-opc.tbl (bndmov): Move misplaced Load.
 762         * i386-tlb.h: Re-generate.
 763
 764 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 767         templates allowing memory operands and folded ones for register
 768         only flavors.
 769         * i386-tlb.h: Re-generate.
 770
 771 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 774         256-bit templates. Drop redundant leftover Disp<N>.
 775         * i386-tlb.h: Re-generate.
 776
 777 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 778
 779         * riscv-opc.c (riscv_insn_types): New.
 780
 781 2018-03-13  Nick Clifton  <nickc@redhat.com>
 782
 783         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 784
 785 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * i386-opc.tbl: Add Optimize to clr.
 788         * i386-tbl.h: Regenerated.
 789
 790 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 793         * i386-opc.h (OldGcc): Removed.
 794         (i386_opcode_modifier): Remove oldgcc.
 795         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 796         instructions for old (<= 2.8.1) versions of gcc.
 797         * i386-tbl.h: Regenerated.
 798
 799 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.h (EVEXDYN): New.
 802         * i386-opc.tbl: Fold various AVX512VL templates.
 803         * i386-tlb.h: Re-generate.
 804
 805 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 808         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 809         vpexpandd, vpexpandq): Fold AFX512VF templates.
 810         * i386-tlb.h: Re-generate.
 811
 812 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 815         Fold 128- and 256-bit VEX-encoded templates.
 816         * i386-tlb.h: Re-generate.
 817
 818 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 821         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 822         vpexpandd, vpexpandq): Fold AVX512F templates.
 823         * i386-tlb.h: Re-generate.
 824
 825 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 828         64-bit templates. Drop Disp<N>.
 829         * i386-tlb.h: Re-generate.
 830
 831 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 834         and 256-bit templates.
 835         * i386-tlb.h: Re-generate.
 836
 837 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 840         * i386-tlb.h: Re-generate.
 841
 842 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 845         Drop NoAVX.
 846         * i386-tlb.h: Re-generate.
 847
 848 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 851         * i386-tlb.h: Re-generate.
 852
 853 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-gen.c (opcode_modifiers): Delete FloatD.
 856         * i386-opc.h (FloatD): Delete.
 857         (struct i386_opcode_modifier): Delete floatd.
 858         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 859         FloatD by D.
 860         * i386-tlb.h: Re-generate.
 861
 862 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 863
 864         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 865
 866 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 869         * i386-tlb.h: Re-generate.
 870
 871 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 874         forms.
 875         * i386-tlb.h: Re-generate.
 876
 877 2018-03-07  Alan Modra  <amodra@gmail.com>
 878
 879         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 880         bfd_arch_rs6000.
 881         * disassemble.h (print_insn_rs6000): Delete.
 882         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 883         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 884         (print_insn_rs6000): Delete.
 885
 886 2018-03-03  Alan Modra  <amodra@gmail.com>
 887
 888         * sysdep.h (opcodes_error_handler): Define.
 889         (_bfd_error_handler): Declare.
 890         * Makefile.am: Remove stray #.
 891         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 892         EDIT" comment.
 893         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 894         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 895         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 896         opcodes_error_handler to print errors.  Standardize error messages.
 897         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 898         and include opintl.h.
 899         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 900         * i386-gen.c: Standardize error messages.
 901         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 902         * Makefile.in: Regenerate.
 903         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 904         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 905         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 906         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 907         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 908         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 909         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 910         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 911         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 912         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 913         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 914         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 915         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 916
 917 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 920         vpsub[bwdq] instructions.
 921         * i386-tbl.h: Regenerated.
 922
 923 2018-03-01  Alan Modra  <amodra@gmail.com>
 924
 925         * configure.ac (ALL_LINGUAS): Sort.
 926         * configure: Regenerate.
 927
 928 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 929
 930         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 931         macro by assignements.
 932
 933 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 934
 935         PR gas/22871
 936         * i386-gen.c (opcode_modifiers): Add Optimize.
 937         * i386-opc.h (Optimize): New enum.
 938         (i386_opcode_modifier): Add optimize.
 939         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 940         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 941         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 942         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 943         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 944         vpxord and vpxorq.
 945         * i386-tbl.h: Regenerated.
 946
 947 2018-02-26  Alan Modra  <amodra@gmail.com>
 948
 949         * crx-dis.c (getregliststring): Allocate a large enough buffer
 950         to silence false positive gcc8 warning.
 951
 952 2018-02-22  Shea Levy <shea@shealevy.com>
 953
 954         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 955
 956 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         * i386-opc.tbl: Add {rex},
 959         * i386-tbl.h: Regenerated.
 960
 961 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 962
 963         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 964         (mips16_opcodes): Replace `M' with `m' for "restore".
 965
 966 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 967
 968         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 969
 970 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 971
 972         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 973         variable to `function_index'.
 974
 975 2018-02-13  Nick Clifton  <nickc@redhat.com>
 976
 977         PR 22823
 978         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 979         about truncation of printing.
 980
 981 2018-02-12  Henry Wong <henry@stuffedcow.net>
 982
 983         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 984
 985 2018-02-05  Nick Clifton  <nickc@redhat.com>
 986
 987         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 988
 989 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 990
 991         * i386-dis.c (enum): Add pconfig.
 992         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 993         (cpu_flags): Add CpuPCONFIG.
 994         * i386-opc.h (enum): Add CpuPCONFIG.
 995         (i386_cpu_flags): Add cpupconfig.
 996         * i386-opc.tbl: Add PCONFIG instruction.
 997         * i386-init.h: Regenerate.
 998         * i386-tbl.h: Likewise.
 999
1000 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1001
1002         * i386-dis.c (enum): Add PREFIX_0F09.
1003         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1004         (cpu_flags): Add CpuWBNOINVD.
1005         * i386-opc.h (enum): Add CpuWBNOINVD.
1006         (i386_cpu_flags): Add cpuwbnoinvd.
1007         * i386-opc.tbl: Add WBNOINVD instruction.
1008         * i386-init.h: Regenerate.
1009         * i386-tbl.h: Likewise.
1010
1011 2018-01-17  Jim Wilson  <jimw@sifive.com>
1012
1013         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1014
1015 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1016
1017         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1018         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1019         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1020         (cpu_flags): Add CpuIBT, CpuSHSTK.
1021         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1022         (i386_cpu_flags): Add cpuibt, cpushstk.
1023         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1024         * i386-init.h: Regenerate.
1025         * i386-tbl.h: Likewise.
1026
1027 2018-01-16  Nick Clifton  <nickc@redhat.com>
1028
1029         * po/pt_BR.po: Updated Brazilian Portugese translation.
1030         * po/de.po: Updated German translation.
1031
1032 2018-01-15  Jim Wilson  <jimw@sifive.com>
1033
1034         * riscv-opc.c (match_c_nop): New.
1035         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1036
1037 2018-01-15  Nick Clifton  <nickc@redhat.com>
1038
1039         * po/uk.po: Updated Ukranian translation.
1040
1041 2018-01-13  Nick Clifton  <nickc@redhat.com>
1042
1043         * po/opcodes.pot: Regenerated.
1044
1045 2018-01-13  Nick Clifton  <nickc@redhat.com>
1046
1047         * configure: Regenerate.
1048
1049 2018-01-13  Nick Clifton  <nickc@redhat.com>
1050
1051         2.30 branch created.
1052
1053 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1054
1055         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1056         * i386-tbl.h: Regenerate.
1057
1058 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1061         * i386-tbl.h: Re-generate.
1062
1063 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1066         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1067         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1068         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1069         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1070         Disp8MemShift of AVX512VL forms.
1071         * i386-tbl.h: Re-generate.
1072
1073 2018-01-09  Jim Wilson  <jimw@sifive.com>
1074
1075         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1076         then the hi_addr value is zero.
1077
1078 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1079
1080         * arm-dis.c (arm_opcodes): Add csdb.
1081         (thumb32_opcodes): Add csdb.
1082
1083 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1084
1085         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1086         * aarch64-asm-2.c: Regenerate.
1087         * aarch64-dis-2.c: Regenerate.
1088         * aarch64-opc-2.c: Regenerate.
1089
1090 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1091
1092         PR gas/22681
1093         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1094         Remove AVX512 vmovd with 64-bit operands.
1095         * i386-tbl.h: Regenerated.
1096
1097 2018-01-05  Jim Wilson  <jimw@sifive.com>
1098
1099         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1100         jalr.
1101
1102 2018-01-03  Alan Modra  <amodra@gmail.com>
1103
1104         Update year range in copyright notice of all files.
1105
1106 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1107
1108         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1109         and OPERAND_TYPE_REGZMM entries.
1110
1111 For older changes see ChangeLog-2017
1112 \f
1113 Copyright (C) 2018 Free Software Foundation, Inc.
1114
1115 Copying and distribution of this file, with or without modification,
1116 are permitted in any medium without royalty provided the copyright
1117 notice and this notice are preserved.
1118
1119 Local Variables:
1120 mode: change-log
1121 left-margin: 8
1122 fill-column: 74
1123 version-control: never
1124 End: