opcodes/ChangeLog

   1 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
   2
   3         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
   4         * configure.ac: Remove AC_PREREQ.
   5         * Makefile.in: Re-generate.
   6         * aclocal.m4: Re-generate.
   7         * configure: Re-generate.
   8
   9 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  10
  11         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
  12         mips64r6 descriptors.
  13         (parse_mips_ase_option): Handle -Mginv option.
  14         (print_mips_disassembler_options): Document -Mginv.
  15         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
  16         (GINV): New macro.
  17         (mips_opcodes): Define ginvi and ginvt.
  18
  19 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
  20             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  21
  22         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
  23         * mips-opc.c (CRC, CRC64): New macros.
  24         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
  25         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
  26         crc32cd for CRC64.
  27
  28 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
  29
  30         PR 20319
  31         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  32         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  33
  34 2018-06-06  Alan Modra  <amodra@gmail.com>
  35
  36         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
  37         setjmp.  Move init for some other vars later too.
  38
  39 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
  40
  41         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
  42         (dis_private): Add new fields for property section tracking.
  43         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
  44         (xtensa_instruction_fits): New functions.
  45         (fetch_data): Bump minimal fetch size to 4.
  46         (print_insn_xtensa): Make struct dis_private static.
  47         Load and prepare property table on section change.
  48         Don't disassemble literals. Don't disassemble instructions that
  49         cross property table boundaries.
  50
  51 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         * configure: Regenerated.
  54
  55 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
  58         * i386-tbl.h: Re-generate.
  59
  60 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-opc.tbl (sldt, str): Add NoRex64.
  63         * i386-tbl.h: Re-generate.
  64
  65 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl (invpcid): Add Oword.
  68         * i386-tbl.h: Re-generate.
  69
  70 2018-06-01  Alan Modra  <amodra@gmail.com>
  71
  72         * sysdep.h (_bfd_error_handler): Don't declare.
  73         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
  74         * rl78-decode.opc: Likewise.
  75         * msp430-decode.c: Regenerate.
  76         * rl78-decode.c: Regenerate.
  77
  78 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
  79
  80         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
  81         * i386-init.h : Regenerated.
  82
  83 2018-05-25  Alan Modra  <amodra@gmail.com>
  84
  85         * Makefile.in: Regenerate.
  86         * po/POTFILES.in: Regenerate.
  87
  88 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
  89
  90         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
  91         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
  92         (insert_bab, extract_bab, insert_btab, extract_btab,
  93         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
  94         (BAT, BBA VBA RBS XB6S): Delete macros.
  95         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
  96         (BB, BD, RBX, XC6): Update for new macros.
  97         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
  98         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
  99         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 100         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 101
 102 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 103
 104         * Makefile.am: Add support for s12z architecture.
 105         * configure.ac: Likewise.
 106         * disassemble.c: Likewise.
 107         * disassemble.h: Likewise.
 108         * Makefile.in: Regenerate.
 109         * configure: Regenerate.
 110         * s12z-dis.c: New file.
 111         * s12z.h: New file.
 112
 113 2018-05-18  Alan Modra  <amodra@gmail.com>
 114
 115         * nfp-dis.c: Don't #include libbfd.h.
 116         (init_nfp3200_priv): Use bfd_get_section_contents.
 117         (nit_nfp6000_mecsr_sec): Likewise.
 118
 119 2018-05-17  Nick Clifton  <nickc@redhat.com>
 120
 121         * po/zh_CN.po: Updated simplified Chinese translation.
 122
 123 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 124
 125         PR binutils/23109
 126         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 127         * aarch64-dis-2.c: Regenerate.
 128
 129 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 130
 131         PR binutils/21446
 132         * aarch64-asm.c (opintl.h): Include.
 133         (aarch64_ins_sysreg): Enforce read/write constraints.
 134         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 135         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 136         (F_REG_READ, F_REG_WRITE): New.
 137         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 138         AARCH64_OPND_SYSREG.
 139         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 140         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 141         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 142         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 143         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 144         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 145         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 146         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 147         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 148         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 149         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 150         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 151         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 152         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 153         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 154         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 155         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 156
 157 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 158
 159         PR binutils/21446
 160         * aarch64-dis.c (no_notes: New.
 161         (parse_aarch64_dis_option): Support notes.
 162         (aarch64_decode_insn, print_operands): Likewise.
 163         (print_aarch64_disassembler_options): Document notes.
 164         * aarch64-opc.c (aarch64_print_operand): Support notes.
 165
 166 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 167
 168         PR binutils/21446
 169         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 170         and take error struct.
 171         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 172         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 173         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 174         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 175         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 176         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 177         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 178         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 179         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 180         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 181         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 182         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 183         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 184         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 185         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 186         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 187         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 188         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 189         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 190         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 191         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 192         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 193         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 194         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 195         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 196         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 197         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 198         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 199         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 200         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 201         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 202         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 203         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 204         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 205         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 206         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 207         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 208         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 209         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 210         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 211         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 212         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 213         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 214         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 215         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 216         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 217         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 218         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 219         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 220         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 221         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 222         (determine_disassembling_preference, aarch64_decode_insn,
 223         print_insn_aarch64_word, print_insn_data): Take errors struct.
 224         (print_insn_aarch64): Use errors.
 225         * aarch64-asm-2.c: Regenerate.
 226         * aarch64-dis-2.c: Regenerate.
 227         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 228         boolean in aarch64_insert_operan.
 229         (print_operand_extractor): Likewise.
 230         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 231
 232 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 233
 234         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 235
 236 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 239
 240 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 241
 242         * cr16-opc.c (cr16_instruction): Comment typo fix.
 243         * hppa-dis.c (print_insn_hppa): Likewise.
 244
 245 2018-05-08  Jim Wilson  <jimw@sifive.com>
 246
 247         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 248         (match_c_slli64, match_srxi_as_c_srxi): New.
 249         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 250         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 251         <c.slli, c.srli, c.srai>: Use match_s_slli.
 252         <c.slli64, c.srli64, c.srai64>: New.
 253
 254 2018-05-08  Alan Modra  <amodra@gmail.com>
 255
 256         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 257         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 258         partition opcode space for index lookup.
 259
 260 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 261
 262         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 263         <insn_length>: ...with this.  Update usage.
 264         Remove duplicate call to *info->memory_error_func.
 265
 266 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 267             H.J. Lu  <hongjiu.lu@intel.com>
 268
 269         * i386-dis.c (Gva): New.
 270         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 271         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 272         (prefix_table): New instructions (see prefix above).
 273         (mod_table): New instructions (see prefix above).
 274         (OP_G): Handle va_mode.
 275         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 276         CPU_MOVDIR64B_FLAGS.
 277         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 278         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 279         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 280         * i386-opc.tbl: Add movidir{i,64b}.
 281         * i386-init.h: Regenerated.
 282         * i386-tbl.h: Likewise.
 283
 284 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 287         AddrPrefixOpReg.
 288         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 289         (AddrPrefixOpReg): This.
 290         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 291         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 292
 293 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 294
 295         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 296         (vle_num_opcodes): Likewise.
 297         (spe2_num_opcodes): Likewise.
 298         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 299         initialization loop.
 300         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 301         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 302         only once.
 303
 304 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 305
 306         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 307
 308 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 309
 310         Makefile.am: Added nfp-dis.c.
 311         configure.ac: Added bfd_nfp_arch.
 312         disassemble.h: Added print_insn_nfp prototype.
 313         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 314         nfp-dis.c: New, for NFP support.
 315         po/POTFILES.in: Added nfp-dis.c to the list.
 316         Makefile.in: Regenerate.
 317         configure: Regenerate.
 318
 319 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 322         templates into their base ones.
 323         * i386-tlb.h: Re-generate.
 324
 325 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 328         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 329         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 330         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 331         * i386-init.h: Re-generate.
 332
 333 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 336         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 337         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 338         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 339         comment.
 340         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 341         and CpuRegMask.
 342         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 343         CpuRegMask: Delete.
 344         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 345         cpuregzmm, and cpuregmask.
 346         * i386-init.h: Re-generate.
 347         * i386-tbl.h: Re-generate.
 348
 349 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 352         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 353         * i386-init.h: Re-generate.
 354
 355 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-gen.c (VexImmExt): Delete.
 358         * i386-opc.h (VexImmExt, veximmext): Delete.
 359         * i386-opc.tbl: Drop all VexImmExt uses.
 360         * i386-tlb.h: Re-generate.
 361
 362 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 365         register-only forms.
 366         * i386-tlb.h: Re-generate.
 367
 368 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 369
 370         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 371
 372 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 373
 374         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 375         PREFIX_0F1C.
 376         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 377         (cpu_flags): Add CpuCLDEMOTE.
 378         * i386-init.h: Regenerate.
 379         * i386-opc.h (enum): Add CpuCLDEMOTE,
 380         (i386_cpu_flags): Add cpucldemote.
 381         * i386-opc.tbl: Add cldemote.
 382         * i386-tbl.h: Regenerate.
 383
 384 2018-04-16  Alan Modra  <amodra@gmail.com>
 385
 386         * Makefile.am: Remove sh5 and sh64 support.
 387         * configure.ac: Likewise.
 388         * disassemble.c: Likewise.
 389         * disassemble.h: Likewise.
 390         * sh-dis.c: Likewise.
 391         * sh64-dis.c: Delete.
 392         * sh64-opc.c: Delete.
 393         * sh64-opc.h: Delete.
 394         * Makefile.in: Regenerate.
 395         * configure: Regenerate.
 396         * po/POTFILES.in: Regenerate.
 397
 398 2018-04-16  Alan Modra  <amodra@gmail.com>
 399
 400         * Makefile.am: Remove w65 support.
 401         * configure.ac: Likewise.
 402         * disassemble.c: Likewise.
 403         * disassemble.h: Likewise.
 404         * w65-dis.c: Delete.
 405         * w65-opc.h: Delete.
 406         * Makefile.in: Regenerate.
 407         * configure: Regenerate.
 408         * po/POTFILES.in: Regenerate.
 409
 410 2018-04-16  Alan Modra  <amodra@gmail.com>
 411
 412         * configure.ac: Remove we32k support.
 413         * configure: Regenerate.
 414
 415 2018-04-16  Alan Modra  <amodra@gmail.com>
 416
 417         * Makefile.am: Remove m88k support.
 418         * configure.ac: Likewise.
 419         * disassemble.c: Likewise.
 420         * disassemble.h: Likewise.
 421         * m88k-dis.c: Delete.
 422         * Makefile.in: Regenerate.
 423         * configure: Regenerate.
 424         * po/POTFILES.in: Regenerate.
 425
 426 2018-04-16  Alan Modra  <amodra@gmail.com>
 427
 428         * Makefile.am: Remove i370 support.
 429         * configure.ac: Likewise.
 430         * disassemble.c: Likewise.
 431         * disassemble.h: Likewise.
 432         * i370-dis.c: Delete.
 433         * i370-opc.c: Delete.
 434         * Makefile.in: Regenerate.
 435         * configure: Regenerate.
 436         * po/POTFILES.in: Regenerate.
 437
 438 2018-04-16  Alan Modra  <amodra@gmail.com>
 439
 440         * Makefile.am: Remove h8500 support.
 441         * configure.ac: Likewise.
 442         * disassemble.c: Likewise.
 443         * disassemble.h: Likewise.
 444         * h8500-dis.c: Delete.
 445         * h8500-opc.h: Delete.
 446         * Makefile.in: Regenerate.
 447         * configure: Regenerate.
 448         * po/POTFILES.in: Regenerate.
 449
 450 2018-04-16  Alan Modra  <amodra@gmail.com>
 451
 452         * configure.ac: Remove tahoe support.
 453         * configure: Regenerate.
 454
 455 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 458         umwait.
 459         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 460         64-bit mode.
 461         * i386-tbl.h: Regenerated.
 462
 463 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 464
 465         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 466         PREFIX_MOD_1_0FAE_REG_6.
 467         (va_mode): New.
 468         (OP_E_register): Use va_mode.
 469         * i386-dis-evex.h (prefix_table):
 470         New instructions (see prefixes above).
 471         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 472         (cpu_flags): Likewise.
 473         * i386-opc.h (enum): Likewise.
 474         (i386_cpu_flags): Likewise.
 475         * i386-opc.tbl: Add umonitor, umwait, tpause.
 476         * i386-init.h: Regenerate.
 477         * i386-tbl.h: Likewise.
 478
 479 2018-04-11  Alan Modra  <amodra@gmail.com>
 480
 481         * opcodes/i860-dis.c: Delete.
 482         * opcodes/i960-dis.c: Delete.
 483         * Makefile.am: Remove i860 and i960 support.
 484         * configure.ac: Likewise.
 485         * disassemble.c: Likewise.
 486         * disassemble.h: Likewise.
 487         * Makefile.in: Regenerate.
 488         * configure: Regenerate.
 489         * po/POTFILES.in: Regenerate.
 490
 491 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 492
 493         PR binutils/23025
 494         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 495         to 0.
 496         (print_insn): Clear vex instead of vex.evex.
 497
 498 2018-04-04  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/es.po: Updated Spanish translation.
 501
 502 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-gen.c (opcode_modifiers): Delete VecESize.
 505         * i386-opc.h (VecESize): Delete.
 506         (struct i386_opcode_modifier): Delete vecesize.
 507         * i386-opc.tbl: Drop VecESize.
 508         * i386-tlb.h: Re-generate.
 509
 510 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 513         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 514         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 515         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 516         * i386-tlb.h: Re-generate.
 517
 518 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 521         Fold AVX512 forms
 522         * i386-tlb.h: Re-generate.
 523
 524 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 527         (vex_len_table): Drop Y for vcvt*2si.
 528         (putop): Replace plain 'Y' handling by abort().
 529
 530 2018-03-28  Nick Clifton  <nickc@redhat.com>
 531
 532         PR 22988
 533         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 534         instructions with only a base address register.
 535         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 536         handle AARHC64_OPND_SVE_ADDR_R.
 537         (aarch64_print_operand): Likewise.
 538         * aarch64-asm-2.c: Regenerate.
 539         * aarch64_dis-2.c: Regenerate.
 540         * aarch64-opc-2.c: Regenerate.
 541
 542 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-opc.tbl: Drop VecESize from register only insn forms and
 545         memory forms not allowing broadcast.
 546         * i386-tlb.h: Re-generate.
 547
 548 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 551         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 552         sha256*): Drop Disp<N>.
 553
 554 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-dis.c (EbndS, bnd_swap_mode): New.
 557         (prefix_table): Use EbndS.
 558         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 559         * i386-opc.tbl (bndmov): Move misplaced Load.
 560         * i386-tlb.h: Re-generate.
 561
 562 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 565         templates allowing memory operands and folded ones for register
 566         only flavors.
 567         * i386-tlb.h: Re-generate.
 568
 569 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 572         256-bit templates. Drop redundant leftover Disp<N>.
 573         * i386-tlb.h: Re-generate.
 574
 575 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 576
 577         * riscv-opc.c (riscv_insn_types): New.
 578
 579 2018-03-13  Nick Clifton  <nickc@redhat.com>
 580
 581         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 582
 583 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         * i386-opc.tbl: Add Optimize to clr.
 586         * i386-tbl.h: Regenerated.
 587
 588 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 591         * i386-opc.h (OldGcc): Removed.
 592         (i386_opcode_modifier): Remove oldgcc.
 593         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 594         instructions for old (<= 2.8.1) versions of gcc.
 595         * i386-tbl.h: Regenerated.
 596
 597 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.h (EVEXDYN): New.
 600         * i386-opc.tbl: Fold various AVX512VL templates.
 601         * i386-tlb.h: Re-generate.
 602
 603 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 606         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 607         vpexpandd, vpexpandq): Fold AFX512VF templates.
 608         * i386-tlb.h: Re-generate.
 609
 610 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 613         Fold 128- and 256-bit VEX-encoded templates.
 614         * i386-tlb.h: Re-generate.
 615
 616 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 619         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 620         vpexpandd, vpexpandq): Fold AVX512F templates.
 621         * i386-tlb.h: Re-generate.
 622
 623 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 626         64-bit templates. Drop Disp<N>.
 627         * i386-tlb.h: Re-generate.
 628
 629 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 632         and 256-bit templates.
 633         * i386-tlb.h: Re-generate.
 634
 635 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 638         * i386-tlb.h: Re-generate.
 639
 640 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 643         Drop NoAVX.
 644         * i386-tlb.h: Re-generate.
 645
 646 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 649         * i386-tlb.h: Re-generate.
 650
 651 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-gen.c (opcode_modifiers): Delete FloatD.
 654         * i386-opc.h (FloatD): Delete.
 655         (struct i386_opcode_modifier): Delete floatd.
 656         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 657         FloatD by D.
 658         * i386-tlb.h: Re-generate.
 659
 660 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 663
 664 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 667         * i386-tlb.h: Re-generate.
 668
 669 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 670
 671         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 672         forms.
 673         * i386-tlb.h: Re-generate.
 674
 675 2018-03-07  Alan Modra  <amodra@gmail.com>
 676
 677         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 678         bfd_arch_rs6000.
 679         * disassemble.h (print_insn_rs6000): Delete.
 680         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 681         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 682         (print_insn_rs6000): Delete.
 683
 684 2018-03-03  Alan Modra  <amodra@gmail.com>
 685
 686         * sysdep.h (opcodes_error_handler): Define.
 687         (_bfd_error_handler): Declare.
 688         * Makefile.am: Remove stray #.
 689         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 690         EDIT" comment.
 691         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 692         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 693         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 694         opcodes_error_handler to print errors.  Standardize error messages.
 695         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 696         and include opintl.h.
 697         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 698         * i386-gen.c: Standardize error messages.
 699         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 700         * Makefile.in: Regenerate.
 701         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 702         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 703         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 704         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 705         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 706         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 707         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 708         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 709         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 710         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 711         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 712         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 713         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 714
 715 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 718         vpsub[bwdq] instructions.
 719         * i386-tbl.h: Regenerated.
 720
 721 2018-03-01  Alan Modra  <amodra@gmail.com>
 722
 723         * configure.ac (ALL_LINGUAS): Sort.
 724         * configure: Regenerate.
 725
 726 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 727
 728         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 729         macro by assignements.
 730
 731 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 732
 733         PR gas/22871
 734         * i386-gen.c (opcode_modifiers): Add Optimize.
 735         * i386-opc.h (Optimize): New enum.
 736         (i386_opcode_modifier): Add optimize.
 737         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 738         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 739         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 740         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 741         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 742         vpxord and vpxorq.
 743         * i386-tbl.h: Regenerated.
 744
 745 2018-02-26  Alan Modra  <amodra@gmail.com>
 746
 747         * crx-dis.c (getregliststring): Allocate a large enough buffer
 748         to silence false positive gcc8 warning.
 749
 750 2018-02-22  Shea Levy <shea@shealevy.com>
 751
 752         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 753
 754 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-opc.tbl: Add {rex},
 757         * i386-tbl.h: Regenerated.
 758
 759 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 760
 761         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 762         (mips16_opcodes): Replace `M' with `m' for "restore".
 763
 764 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 765
 766         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 767
 768 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 769
 770         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 771         variable to `function_index'.
 772
 773 2018-02-13  Nick Clifton  <nickc@redhat.com>
 774
 775         PR 22823
 776         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 777         about truncation of printing.
 778
 779 2018-02-12  Henry Wong <henry@stuffedcow.net>
 780
 781         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 782
 783 2018-02-05  Nick Clifton  <nickc@redhat.com>
 784
 785         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 786
 787 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 788
 789         * i386-dis.c (enum): Add pconfig.
 790         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 791         (cpu_flags): Add CpuPCONFIG.
 792         * i386-opc.h (enum): Add CpuPCONFIG.
 793         (i386_cpu_flags): Add cpupconfig.
 794         * i386-opc.tbl: Add PCONFIG instruction.
 795         * i386-init.h: Regenerate.
 796         * i386-tbl.h: Likewise.
 797
 798 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 799
 800         * i386-dis.c (enum): Add PREFIX_0F09.
 801         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 802         (cpu_flags): Add CpuWBNOINVD.
 803         * i386-opc.h (enum): Add CpuWBNOINVD.
 804         (i386_cpu_flags): Add cpuwbnoinvd.
 805         * i386-opc.tbl: Add WBNOINVD instruction.
 806         * i386-init.h: Regenerate.
 807         * i386-tbl.h: Likewise.
 808
 809 2018-01-17  Jim Wilson  <jimw@sifive.com>
 810
 811         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 812
 813 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 814
 815         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 816         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 817         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 818         (cpu_flags): Add CpuIBT, CpuSHSTK.
 819         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 820         (i386_cpu_flags): Add cpuibt, cpushstk.
 821         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 822         * i386-init.h: Regenerate.
 823         * i386-tbl.h: Likewise.
 824
 825 2018-01-16  Nick Clifton  <nickc@redhat.com>
 826
 827         * po/pt_BR.po: Updated Brazilian Portugese translation.
 828         * po/de.po: Updated German translation.
 829
 830 2018-01-15  Jim Wilson  <jimw@sifive.com>
 831
 832         * riscv-opc.c (match_c_nop): New.
 833         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 834
 835 2018-01-15  Nick Clifton  <nickc@redhat.com>
 836
 837         * po/uk.po: Updated Ukranian translation.
 838
 839 2018-01-13  Nick Clifton  <nickc@redhat.com>
 840
 841         * po/opcodes.pot: Regenerated.
 842
 843 2018-01-13  Nick Clifton  <nickc@redhat.com>
 844
 845         * configure: Regenerate.
 846
 847 2018-01-13  Nick Clifton  <nickc@redhat.com>
 848
 849         2.30 branch created.
 850
 851 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 852
 853         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 854         * i386-tbl.h: Regenerate.
 855
 856 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 859         * i386-tbl.h: Re-generate.
 860
 861 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 864         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 865         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 866         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 867         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 868         Disp8MemShift of AVX512VL forms.
 869         * i386-tbl.h: Re-generate.
 870
 871 2018-01-09  Jim Wilson  <jimw@sifive.com>
 872
 873         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 874         then the hi_addr value is zero.
 875
 876 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 877
 878         * arm-dis.c (arm_opcodes): Add csdb.
 879         (thumb32_opcodes): Add csdb.
 880
 881 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 882
 883         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 884         * aarch64-asm-2.c: Regenerate.
 885         * aarch64-dis-2.c: Regenerate.
 886         * aarch64-opc-2.c: Regenerate.
 887
 888 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 889
 890         PR gas/22681
 891         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 892         Remove AVX512 vmovd with 64-bit operands.
 893         * i386-tbl.h: Regenerated.
 894
 895 2018-01-05  Jim Wilson  <jimw@sifive.com>
 896
 897         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 898         jalr.
 899
 900 2018-01-03  Alan Modra  <amodra@gmail.com>
 901
 902         Update year range in copyright notice of all files.
 903
 904 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 907         and OPERAND_TYPE_REGZMM entries.
 908
 909 For older changes see ChangeLog-2017
 910 \f
 911 Copyright (C) 2018 Free Software Foundation, Inc.
 912
 913 Copying and distribution of this file, with or without modification,
 914 are permitted in any medium without royalty provided the copyright
 915 notice and this notice are preserved.
 916
 917 Local Variables:
 918 mode: change-log
 919 left-margin: 8
 920 fill-column: 74
 921 version-control: never
 922 End: