opcodes/ChangeLog

   1 2023-05-23  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/sv.po: Updated translation.
   4
   5 2023-04-21  Tom Tromey  <tromey@adacore.com>
   6
   7         * i386-dis.c (OP_J): Check result of get16.
   8
   9 2023-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
  10
  11         * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
  12         vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
  13         vsubs2h, and vsubs4h instructions.
  14
  15 2023-04-11  Nick Clifton  <nickc@redhat.com>
  16
  17         PR 30310
  18         * nfp-dis.c (init_nfp6000_priv): Check that the output section
  19         exists.
  20
  21 2023-03-15  Nick Clifton  <nickc@redhat.com>
  22
  23         PR 30231
  24         * mep-dis.c: Regenerate.
  25
  26 2023-03-15  Nick Clifton  <nickc@redhat.com>
  27
  28         PR 30230
  29         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
  30
  31 2023-02-28  Richard Ball  <richard.ball@arm.com>
  32
  33         * aarch64-opc.c: Add MEC system registers.
  34
  35 2023-01-03  Nick Clifton  <nickc@redhat.com>
  36
  37         * po/de.po: Updated German translation.
  38         * po/ro.po: Updated Romainian translation.
  39         * po/uk.po: Updated Ukrainian translation.
  40
  41 2022-12-31  Nick Clifton  <nickc@redhat.com>
  42
  43         * 2.40 branch created.
  44
  45 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
  46
  47         * arc-regs.h: Change isa_config address to 0xc1.
  48         isa_config exists for ARC700 and ARCV2 and not ARCALL.
  49
  50 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
  51
  52         * rx-decode.opc: Switch arguments of the MVTACGU insn.
  53         * rx-decode.c: Regenerate.
  54
  55 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
  56
  57         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
  58         Rm_BANK,Rn is always 1.
  59
  60 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
  61
  62         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
  63         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
  64         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
  65         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
  66         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
  67         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
  68         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
  69
  70 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
  71
  72         * disassemble.c (disassemble_init_for_target): Set
  73         created_styled_output for ARC based targets.
  74         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
  75         instead of fprintf_ftype throughout.
  76         (find_format): Likewise.
  77         (print_flags): Likewise.
  78         (print_insn_arc): Likewise.
  79
  80 2022-07-08  Nick Clifton  <nickc@redhat.com>
  81
  82         * 2.39 branch created.
  83
  84 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
  85
  86         * disassemble.c: (disassemble_init_for_target): Set
  87         created_styled_output for AVR based targets.
  88         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
  89         instead of fprintf_ftype throughout.
  90         (avr_operand): Pass in and fill disassembler_style when
  91         parsing operands.
  92
  93 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  94
  95         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
  96         table.
  97
  98 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
  99
 100         * configure.ac: Handle bfd_amdgcn_arch.
 101         * configure: Re-generate.
 102
 103 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
 104             Maciej W. Rozycki  <macro@orcam.me.uk>
 105
 106         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
 107         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
 108         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
 109         "bnez" instructions.
 110
 111 2022-02-17  Nick Clifton  <nickc@redhat.com>
 112
 113         * po/sr.po: Updated Serbian translation.
 114
 115 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
 116
 117         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
 118         * microblaze-opc.h: Follow 'fsqrt' rename.
 119
 120 2022-01-24  Nick Clifton  <nickc@redhat.com>
 121
 122         * po/ro.po: Updated Romanian translation.
 123         * po/uk.po: Updated Ukranian translation.
 124
 125 2022-01-22  Nick Clifton  <nickc@redhat.com>
 126
 127         * configure: Regenerate.
 128         * po/opcodes.pot: Regenerate.
 129
 130 2022-01-22  Nick Clifton  <nickc@redhat.com>
 131
 132         * 2.38 release branch created.
 133
 134 2022-01-17  Nick Clifton  <nickc@redhat.com>
 135
 136         * Makefile.in: Regenerate.
 137         * po/opcodes.pot: Regenerate.
 138
 139 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 140
 141         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 142         in insn_type on branching instructions.
 143
 144 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 145             Simon Cook  <simon.cook@embecosm.com>
 146
 147         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 148         (riscv_options): New static global.
 149         (disassembler_options_riscv): New function.
 150         (print_riscv_disassembler_options): Rewrite to use
 151         disassembler_options_riscv.
 152
 153 2021-11-25  Nick Clifton  <nickc@redhat.com>
 154
 155         PR 28614
 156         * aarch64-asm.c: Replace assert(0) with real code.
 157         * aarch64-dis.c: Likewise.
 158         * aarch64-opc.c: Likewise.
 159
 160 2021-11-25  Nick Clifton  <nickc@redhat.com>
 161
 162         * po/fr.po; Updated French translation.
 163
 164 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 165
 166         * Makefile.am: Remove obsolete comment.
 167         * configure.ac: Refer `libbfd.la' to link shared BFD library
 168         except for Cygwin.
 169         * Makefile.in: Regenerate.
 170         * configure: Regenerate.
 171
 172 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 173
 174         * configure: Regenerate.
 175
 176 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 177
 178         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 179         on POWER5 and later.
 180
 181 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 182
 183         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 184         before an unknown instruction, '%d' is replaced with the
 185         instruction length.
 186
 187 2021-09-02  Nick Clifton  <nickc@redhat.com>
 188
 189         PR 28292
 190         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 191         of BFD_RELOC_16.
 192
 193 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 194
 195         * arc-regs.h (DEF): Fix the register numbers.
 196
 197 2021-08-10  Nick Clifton  <nickc@redhat.com>
 198
 199         * po/sr.po: Updated Serbian translation.
 200
 201 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 202
 203         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 204
 205 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 206
 207         * s390-opc.txt: Add qpaci.
 208
 209 2021-07-03  Nick Clifton  <nickc@redhat.com>
 210
 211         * configure: Regenerate.
 212         * po/opcodes.pot: Regenerate.
 213
 214 2021-07-03  Nick Clifton  <nickc@redhat.com>
 215
 216         * 2.37 release branch created.
 217
 218 2021-07-02  Alan Modra  <amodra@gmail.com>
 219
 220         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 221         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 222         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 223         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 224         (nds32_keyword_gpr): Move declarations to..
 225         * nds32-asm.h: ..here, constifying to match definitions.
 226
 227 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 228
 229         * Makefile.am (GUILE): New variable.
 230         (CGEN): Use $(GUILE).
 231         * Makefile.in: Regenerate.
 232
 233 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 234
 235         * mep-asm.c (macros): Mark static & const.
 236         (lookup_macro): Change return & m to const.
 237         (expand_macro): Change mac to const.
 238         (expand_string): Change pmacro to const.
 239
 240 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 241
 242         * nds32-asm.c (operand_fields): Rename to ...
 243         (nds32_operand_fields): ... this.
 244         (keyword_gpr): Rename to ...
 245         (nds32_keyword_gpr): ... this.
 246         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 247         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 248         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 249         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 250         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 251         Mark static.
 252         (keywords): Rename to ...
 253         (nds32_keywords): ... this.
 254         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 255         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 256
 257 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 258
 259         * z80-dis.c (opc_ed): Make const.
 260         (pref_ed): Make p const.
 261
 262 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 263
 264         * microblaze-dis.c (get_field_special): Make op const.
 265         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 266         microblaze_opcodes.
 267         (print_insn_microblaze): Make op & pop const.
 268         (get_insn_microblaze): Make op const.  Rename opcodes to
 269         microblaze_opcodes.
 270         (microblaze_get_target_address): Likewise.
 271         * microblaze-opc.h (struct op_code_struct): Make const.
 272         Rename opcodes to microblaze_opcodes.
 273
 274 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 275
 276         * aarch64-gen.c (aarch64_opcode_table): Add const.
 277         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 278
 279 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 280
 281         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 282         available.
 283
 284 2021-06-22  Alan Modra  <amodra@gmail.com>
 285
 286         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 287         print separator for pcrel insns.
 288
 289 2021-06-19  Alan Modra  <amodra@gmail.com>
 290
 291         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 292
 293 2021-06-19  Alan Modra  <amodra@gmail.com>
 294
 295         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 296         entire buffer.
 297
 298 2021-06-17  Alan Modra  <amodra@gmail.com>
 299
 300         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 301         in table.
 302
 303 2021-06-03  Alan Modra  <amodra@gmail.com>
 304
 305         PR 1202
 306         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 307         Use unsigned int for inst.
 308
 309 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 310
 311         * arc-dis.c (arc_option_arg_t): New enumeration.
 312         (arc_options): New variable.
 313         (disassembler_options_arc): New function.
 314         (print_arc_disassembler_options): Reimplement in terms of
 315         "disassembler_options_arc".
 316
 317 2021-05-29  Alan Modra  <amodra@gmail.com>
 318
 319         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 320         Don't special case PPC_OPCODE_RAW.
 321         (lookup_prefix): Likewise.
 322         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 323         (print_insn_powerpc): ..update caller.
 324         * ppc-opc.c (EXT): Define.
 325         (powerpc_opcodes): Mark extended mnemonics with EXT.
 326         (prefix_opcodes, vle_opcodes): Likewise.
 327         (XISEL, XISEL_MASK): Add cr field and simplify.
 328         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 329         all isel variants to where the base mnemonic belongs.  Sort dstt,
 330         dststt and dssall.
 331
 332 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 333
 334         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 335         COP3 opcode instructions.
 336
 337 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 338
 339         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 340         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 341         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 342         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 343         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 344         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 345         "cop2", and "cop3" entries.
 346
 347 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 348
 349         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 350         entries and associated comments.
 351
 352 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 353
 354         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 355         of "c0".
 356
 357 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 358
 359         * mips-dis.c (mips_cp1_names_mips): New variable.
 360         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 361         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 362         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 363         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 364         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 365         "loongson2f".
 366
 367 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 368
 369         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 370         handling code over to...
 371         <OP_REG_CONTROL>: ... this new case.
 372         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 373         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 374         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 375         replacing the `G' operand code with `g'.  Update "cftc1" and
 376         "cftc2" entries replacing the `E' operand code with `y'.
 377         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 378         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 379         entries replacing the `G' operand code with `g'.
 380
 381 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 382
 383         * mips-dis.c (mips_cp0_names_r3900): New variable.
 384         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 385         for "r3900".
 386
 387 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 388
 389         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 390         and "mtthc2" to using the `G' rather than `g' operand code for
 391         the coprocessor control register referred.
 392
 393 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 394
 395         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 396         entries with each other.
 397
 398 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 399
 400         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 401
 402 2021-05-25  Alan Modra  <amodra@gmail.com>
 403
 404         * cris-desc.c: Regenerate.
 405         * cris-desc.h: Regenerate.
 406         * cris-opc.h: Regenerate.
 407         * po/POTFILES.in: Regenerate.
 408
 409 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 410
 411         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 412         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 413         (CGEN_CPUS): Add cris.
 414         (CRIS_DEPS): Define.
 415         (stamp-cris): New rule.
 416         * cgen.sh: Handle desc action.
 417         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 418         * Makefile.in, configure: Regenerate.
 419
 420 2021-05-18  Job Noorman  <mtvec@pm.me>
 421
 422         PR 27814
 423         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 424         the elf objects.
 425
 426 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 427
 428         * arm-dis.c (mve_opcodes): Fix disassembly of
 429         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 430         (is_mve_encoding_conflict): MVE vector loads should not match
 431         when P = W = 0.
 432         (is_mve_unpredictable): It's not unpredictable to use the same
 433         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 434
 435 2021-05-11  Nick Clifton  <nickc@redhat.com>
 436
 437         PR 27840
 438         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 439         the end of the code buffer.
 440
 441 2021-05-06  Stafford Horne  <shorne@gmail.com>
 442
 443         PR 21464
 444         * or1k-asm.c: Regenerate.
 445
 446 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 447
 448         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 449         info->insn_info_valid.
 450
 451 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-opc.tbl (lea): Add Optimize.
 454         * opcodes/i386-tbl.h: Re-generate.
 455
 456 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 457
 458         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 459         of l32r fetch and display referenced literal value.
 460
 461 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 462
 463         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 464         to 4 for literal disassembly.
 465
 466 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 467
 468         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 469         for TLBI instruction.
 470
 471 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 472
 473         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 474         DC instruction.
 475
 476 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 477
 478         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 479         "qualifier".
 480         (convert_mov_to_movewide): Add initializer for "value".
 481
 482 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 483
 484         * aarch64-opc.c: Add RME system registers.
 485
 486 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 487
 488         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 489         "addi d,CV,z" to "c.mv d,CV".
 490
 491 2021-04-12  Alan Modra  <amodra@gmail.com>
 492
 493         * configure.ac (--enable-checking): Add support.
 494         * config.in: Regenerate.
 495         * configure: Regenerate.
 496
 497 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 498
 499         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 500         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 501
 502 2021-04-09  Alan Modra  <amodra@gmail.com>
 503
 504         * ppc-dis.c (struct dis_private): Add "special".
 505         (POWERPC_DIALECT): Delete.  Replace uses with..
 506         (private_data): ..this.  New inline function.
 507         (disassemble_init_powerpc): Init "special" names.
 508         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 509         field of prefix instructions.
 510         (bsearch_reloc, print_got_plt): New functions.
 511         (print_insn_powerpc): For pcrel instructions, print target address
 512         and symbol if known, and decode plt and got loads too.
 513
 514 2021-04-08  Alan Modra  <amodra@gmail.com>
 515
 516         PR 27684
 517         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 518
 519 2021-04-08  Alan Modra  <amodra@gmail.com>
 520
 521         PR 27676
 522         * ppc-opc.c (DCBT_EO): Move earlier.
 523         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 524         (powerpc_operands): Add THCT and THDS entries.
 525         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 526
 527 2021-04-06  Alan Modra  <amodra@gmail.com>
 528
 529         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 530         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 531         symbol_at_address_func.
 532
 533 2021-04-05  Alan Modra  <amodra@gmail.com>
 534
 535         * configure.ac: Don't check for limits.h, string.h, strings.h or
 536         stdlib.h.
 537         (AC_ISC_POSIX): Don't invoke.
 538         * sysdep.h: Include stdlib.h and string.h unconditionally.
 539         * i386-opc.h: Include limits.h unconditionally.
 540         * wasm32-dis.c: Likewise.
 541         * cgen-opc.c: Don't include alloca-conf.h.
 542         * config.in: Regenerate.
 543         * configure: Regenerate.
 544
 545 2021-04-01  Martin Liska  <mliska@suse.cz>
 546
 547         * arm-dis.c (strneq): Remove strneq and use startswith.
 548         * cr16-dis.c (print_insn_cr16): Likewise.
 549         * score-dis.c (streq): Likewise.
 550         (strneq): Likewise.
 551         * score7-dis.c (strneq): Likewise.
 552
 553 2021-04-01  Alan Modra  <amodra@gmail.com>
 554
 555         PR 27675
 556         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 557
 558 2021-03-31  Alan Modra  <amodra@gmail.com>
 559
 560         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 561         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 562         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 563         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 564         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 565         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 566         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 567         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 568         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 569         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 570         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 571         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 572         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 573         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 574         and TRUE with true throughout.
 575
 576 2021-03-31  Alan Modra  <amodra@gmail.com>
 577
 578         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 579         * aarch64-dis.h: Likewise.
 580         * aarch64-opc.c: Likewise.
 581         * avr-dis.c: Likewise.
 582         * csky-dis.c: Likewise.
 583         * nds32-asm.c: Likewise.
 584         * nds32-dis.c: Likewise.
 585         * nfp-dis.c: Likewise.
 586         * riscv-dis.c: Likewise.
 587         * s12z-dis.c: Likewise.
 588         * wasm32-dis.c: Likewise.
 589
 590 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 593         (i386_seg_prefixes): New.
 594         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 595         (i386_seg_prefixes): Declare.
 596
 597 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 600
 601 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 604         * i386-reg.tbl (st): Move down.
 605         (st(0)): Delete. Extend comment.
 606         * i386-tbl.h: Re-generate.
 607
 608 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 611         (cmpsd): Move next to cmps.
 612         (movsd): Move next to movs.
 613         (cmpxchg16b): Move to separate section.
 614         (fisttp, fisttpll): Likewise.
 615         (monitor, mwait): Likewise.
 616         * i386-tbl.h: Re-generate.
 617
 618 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 621         (vpsadbw): Add C.
 622         * i386-tbl.h: Re-generate.
 623
 624 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 627         pclmul, gfni): New templates. Use them wherever possible. Move
 628         SSE4.1 pextrw into respective section.
 629         * i386-tbl.h: Re-generate.
 630
 631 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 634         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 635         "length".
 636         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 637         Convert all of their uses to representation in opcode.
 638
 639 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 640
 641         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 642         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 643         value of None. Shrink operands to 3 bits.
 644
 645 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-gen.c (process_i386_opcode_modifier): New parameter
 648         "space".
 649         (output_i386_opcode): New local variable "space". Adjust
 650         process_i386_opcode_modifier() invocation.
 651         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 652         invocation.
 653         * i386-tbl.h: Re-generate.
 654
 655 2021-03-29  Alan Modra  <amodra@gmail.com>
 656
 657         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 658         (fp_qualifier_p, get_data_pattern): Likewise.
 659         (aarch64_get_operand_modifier_from_value): Likewise.
 660         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 661         (operand_variant_qualifier_p): Likewise.
 662         (qualifier_value_in_range_constraint_p): Likewise.
 663         (aarch64_get_qualifier_esize): Likewise.
 664         (aarch64_get_qualifier_nelem): Likewise.
 665         (aarch64_get_qualifier_standard_value): Likewise.
 666         (get_lower_bound, get_upper_bound): Likewise.
 667         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 668         (aarch64_print_operand): Likewise.
 669         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 670         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 671         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 672         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 673         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 674         (print_insn_tic6x): Likewise.
 675
 676 2021-03-29  Alan Modra  <amodra@gmail.com>
 677
 678         * arc-dis.c (extract_operand_value): Correct NULL cast.
 679         * frv-opc.h: Regenerate.
 680
 681 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 684         MMX form.
 685         * i386-tbl.h: Re-generate.
 686
 687 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 688
 689         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 690         immediate in br.n instruction.
 691
 692 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-dis.c (XMGatherD, VexGatherD): New.
 695         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 696         (print_insn): Check masking for S/G insns.
 697         (OP_E_memory): New local variable check_gather. Extend mandatory
 698         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 699         Extend check for disallowed 16-bit addressing.
 700         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 701         if()s to switch(). Check register conflicts for (VEX-encoded)
 702         gathers. Drop no longer reachable cases.
 703         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 704         vgatherdp*.
 705
 706 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 709         zeroing-masking without masking.
 710
 711 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 714         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 715         single-operand forms as deprecated.
 716         * i386-tbl.h: Re-generate.
 717
 718 2021-03-25  Alan Modra  <amodra@gmail.com>
 719
 720         PR 27647
 721         * ppc-opc.c (XLOCB_MASK): Delete.
 722         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 723         XLBH_MASK.
 724         (powerpc_opcodes): Accept a BH field on all extended forms of
 725         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 726
 727 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 728
 729         * i386-gen.c (output_i386_opcode): Drop processing of
 730         opcode_length. Calculate length from base_opcode. Adjust prefix
 731         encoding determination.
 732         (process_i386_opcodes): Drop output of fake opcode_length.
 733         * i386-opc.h (struct insn_template): Drop opcode_length field.
 734         * i386-opc.tbl: Drop opcode length field from all templates.
 735         * i386-tbl.h: Re-generate.
 736
 737 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 740         parameter "prefix". Drop local variable "regular_encoding".
 741         Record prefix setting / check for consistency.
 742         (output_i386_opcode): Parse opcode_length and base_opcode
 743         earlier. Derive prefix encoding. Drop no longer applicable
 744         consistency checking. Adjust process_i386_opcode_modifier()
 745         invocation.
 746         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 747         invocation.
 748         * i386-tbl.h: Re-generate.
 749
 750 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 753         check.
 754         * i386-opc.h (Prefix_*): Move #define-s.
 755         * i386-opc.tbl: Move pseudo prefix enumerator values to
 756         extension opcode field. Introduce pseudopfx template.
 757         * i386-tbl.h: Re-generate.
 758
 759 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 762         comment.
 763         * i386-tbl.h: Re-generate.
 764
 765 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.h (struct insn_template): Move cpu_flags field past
 768         opcode_modifier one.
 769         * i386-tbl.h: Re-generate.
 770
 771 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 774         * i386-opc.h (OpcodeSpace): New enumerator.
 775         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 776         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 777         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 778         (struct i386_opcode_modifier): New field opcodespace. Shrink
 779         opcodeprefix field.
 780         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 781         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 782         OpcodePrefix uses.
 783         * i386-tbl.h: Re-generate.
 784
 785 2021-03-22  Martin Liska  <mliska@suse.cz>
 786
 787         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 788         * arc-dis.c (parse_option): Likewise.
 789         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 790         * cris-dis.c (print_with_operands): Likewise.
 791         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 792         * i386-dis.c (print_insn): Likewise.
 793         * ia64-gen.c (fetch_insn_class): Likewise.
 794         (parse_resource_users): Likewise.
 795         (in_iclass): Likewise.
 796         (lookup_specifier): Likewise.
 797         (insert_opcode_dependencies): Likewise.
 798         * mips-dis.c (parse_mips_ase_option): Likewise.
 799         (parse_mips_dis_option): Likewise.
 800         * s390-dis.c (disassemble_init_s390): Likewise.
 801         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 802
 803 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 804
 805         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 806
 807 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 808
 809         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 810         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 811
 812 2021-03-12  Alan Modra  <amodra@gmail.com>
 813
 814         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 815
 816 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-dis.c (OP_XMM): Re-order checks.
 819
 820 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-dis.c (putop): Drop need_vex check when also checking
 823         vex.evex.
 824         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 825         checking vex.b.
 826
 827 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 828
 829         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 830         checks. Move case label past broadcast check.
 831
 832 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 833
 834         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 835         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 836         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 837         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 838         EVEX_W_0F38C7_M_0_L_2): Delete.
 839         (REG_EVEX_0F38C7_M_0_L_2): New.
 840         (intel_operand_size): Handle VEX and EVEX the same for
 841         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 842         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 843         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 844         vex_vsib_q_w_d_mode uses.
 845         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 846         0F38A1, and 0F38A3 entries.
 847         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 848         entry.
 849         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 850         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 851         0F38A3 entries.
 852
 853 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 854
 855         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 856         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 857         MOD_VEX_0FXOP_09_12): Rename to ...
 858         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 859         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 860         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 861         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 862         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 863         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 864         (reg_table): Adjust comments.
 865         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 866         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 867         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 868         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 869         (vex_len_table): Adjust opcode 0A_12 entry.
 870         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 871         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 872         (rm_table): Move hreset entry.
 873
 874 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 875
 876         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 877         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 878         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 879         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 880         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 881         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 882         (get_valid_dis386): Also handle 512-bit vector length when
 883         vectoring into vex_len_table[].
 884         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 885         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 886         entries.
 887         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 888         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 889         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 890         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 891         entries.
 892
 893 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 894
 895         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 896         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 897         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 898         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 899         entries.
 900         * i386-dis-evex-len.h (evex_len_table): Likewise.
 901         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 902
 903 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 904
 905         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 906         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 907         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 908         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 909         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 910         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 911         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 912         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 913         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 914         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 915         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 916         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 917         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 918         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 919         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 920         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 921         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 922         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 923         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 924         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 925         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 926         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 927         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 928         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 929         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 930         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 931         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 932         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 933         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 934         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 935         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 936         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 937         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 938         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 939         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 940         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 941         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 942         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 943         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 944         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 945         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 946         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 947         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 948         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 949         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 950         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 951         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 952         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 953         EVEX_W_0F3A43_L_n): New.
 954         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 955         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 956         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 957         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 958         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 959         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 960         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 961         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 962         0F385B, 0F38C6, and 0F38C7 entries.
 963         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 964         0F38C6 and 0F38C7.
 965         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 966         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 967         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 968         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 969
 970 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 971
 972         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 973         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 974         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 975         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 976         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 977         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 978         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 979         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 980         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 981         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 982         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 983         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 984         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 985         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 986         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 987         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 988         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 989         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 990         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 991         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 992         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 993         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 994         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 995         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 996         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 997         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 998         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 999         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1000         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1001         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1002         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1003         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1004         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1005         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1006         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1007         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1008         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1009         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1010         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1011         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1012         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1013         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1014         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1015         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1016         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1017         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1018         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1019         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1020         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1021         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1022         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1023         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1024         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1025         VEX_W_0F99_P_2_LEN_0): Delete.
1026         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1027         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1028         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1029         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1030         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1031         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1032         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1033         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1034         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1035         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1036         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1037         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1038         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1039         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1040         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1041         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1042         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1043         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1044         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1045         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1046         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1047         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1048         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1049         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1050         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1051         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1052         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1053         (prefix_table): No longer link to vex_len_table[] for opcodes
1054         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1055         0F92, 0F93, 0F98, and 0F99.
1056         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1057         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1058         0F98, and 0F99.
1059         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1060         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1061         0F98, and 0F99.
1062         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1063         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1064         0F98, and 0F99.
1065         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1066         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1067         0F98, and 0F99.
1068
1069 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1070
1071         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1072         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1073         REG_VEX_0F73_M_0 respectively.
1074         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1075         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1076         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1077         MOD_VEX_0F73_REG_7): Delete.
1078         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1079         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1080         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1081         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1082         PREFIX_VEX_0F3AF0_L_0 respectively.
1083         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1084         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1085         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1086         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1087         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1088         VEX_LEN_0F38F7): New.
1089         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1090         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1091         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1092         0F38F3.
1093         (prefix_table): No longer link to vex_len_table[] for opcodes
1094         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1095         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1096         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1097         0F38F6, 0F38F7, and 0F3AF0.
1098         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1099         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1100         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1101         0F73.
1102
1103 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1104
1105         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1106         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1107         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1108         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1109         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1110         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1111         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1112         73.
1113         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1114         0F72, and 0F73.
1115         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1116         0F73.
1117
1118 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1119
1120         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1121         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1122         (reg_table): Don't link to mod_table[] where not needed. Add
1123         PREFIX_IGNORED to nop entries.
1124         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1125         (mod_table): Add nop entries next to prefetch ones. Drop
1126         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1127         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1128         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1129         PREFIX_OPCODE from endbr* entries.
1130         (get_valid_dis386): Also consider entry's name when zapping
1131         vindex.
1132         (print_insn): Handle PREFIX_IGNORED.
1133
1134 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1135
1136         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1137         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1138         element.
1139         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1140         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1141         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1142         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1143         (struct i386_opcode_modifier): Delete notrackprefixok,
1144         islockable, hleprefixok, and repprefixok fields. Add prefixok
1145         field.
1146         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1147         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1148         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1149         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1150         Replace HLEPrefixOk.
1151         * opcodes/i386-tbl.h: Re-generate.
1152
1153 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1154
1155         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1156         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1157         64-bit form.
1158         * opcodes/i386-tbl.h: Re-generate.
1159
1160 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1161
1162         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1163         for {} instead of {0}. Don't look for '0'.
1164         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1165         size specifiers.
1166
1167 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1168
1169         PR 27158
1170         * riscv-dis.c (print_insn_args): Updated encoding macros.
1171         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1172         (match_c_addi16sp): Updated encoding macros.
1173         (match_c_lui): Likewise.
1174         (match_c_lui_with_hint): Likewise.
1175         (match_c_addi4spn): Likewise.
1176         (match_c_slli): Likewise.
1177         (match_slli_as_c_slli): Likewise.
1178         (match_c_slli64): Likewise.
1179         (match_srxi_as_c_srxi): Likewise.
1180         (riscv_insn_types): Added .insn css/cl/cs.
1181
1182 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1183
1184         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1185         (default_priv_spec): Updated type to riscv_spec_class.
1186         (parse_riscv_dis_option): Updated.
1187         * riscv-opc.c: Moved stuff and make the file tidy.
1188
1189 2021-02-17  Alan Modra  <amodra@gmail.com>
1190
1191         * wasm32-dis.c: Include limits.h.
1192         (CHAR_BIT): Provide backup define.
1193         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1194         Correct signed overflow checking.
1195
1196 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1199         * i386-tbl.h: Re-generate.
1200
1201 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1204         Oword.
1205         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1206
1207 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1208
1209         * s390-mkopc.c (main): Accept arch14 as cpu string.
1210         * s390-opc.txt: Add new arch14 instructions.
1211
1212 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1213
1214         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1215         favour of LIBINTL.
1216         * configure: Regenerated.
1217
1218 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1219
1220         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1221         * tic54x-opc.c (regs): Rename to ...
1222         (tic54x_regs): ... this.
1223         (mmregs): Rename to ...
1224         (tic54x_mmregs): ... this.
1225         (condition_codes): Rename to ...
1226         (tic54x_condition_codes): ... this.
1227         (cc2_codes): Rename to ...
1228         (tic54x_cc2_codes): ... this.
1229         (cc3_codes): Rename to ...
1230         (tic54x_cc3_codes): ... this.
1231         (status_bits): Rename to ...
1232         (tic54x_status_bits): ... this.
1233         (misc_symbols): Rename to ...
1234         (tic54x_misc_symbols): ... this.
1235
1236 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1237
1238         * riscv-opc.c (MASK_RVB_IMM): Removed.
1239         (riscv_opcodes): Removed zb* instructions.
1240         (riscv_ext_version_table): Removed versions for zb*.
1241
1242 2021-01-26  Alan Modra  <amodra@gmail.com>
1243
1244         * i386-gen.c (parse_template): Ensure entire template_instance
1245         is initialised.
1246
1247 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1248
1249         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1250         (riscv_fpr_names_abi): Likewise.
1251         (riscv_opcodes): Likewise.
1252         (riscv_insn_types): Likewise.
1253
1254 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1255
1256         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1257
1258 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1259
1260         * riscv-dis.c: Comments tidy and improvement.
1261         * riscv-opc.c: Likewise.
1262
1263 2021-01-13  Alan Modra  <amodra@gmail.com>
1264
1265         * Makefile.in: Regenerate.
1266
1267 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         PR binutils/26792
1270         * configure.ac: Use GNU_MAKE_JOBSERVER.
1271         * aclocal.m4: Regenerated.
1272         * configure: Likewise.
1273
1274 2021-01-12  Nick Clifton  <nickc@redhat.com>
1275
1276         * po/sr.po: Updated Serbian translation.
1277
1278 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1279
1280         PR ld/27173
1281         * configure: Regenerated.
1282
1283 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1284
1285         * aarch64-asm-2.c: Regenerate.
1286         * aarch64-dis-2.c: Likewise.
1287         * aarch64-opc-2.c: Likewise.
1288         * aarch64-opc.c (aarch64_print_operand):
1289         Delete handling of AARCH64_OPND_CSRE_CSR.
1290         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1291         (CSRE): Likewise.
1292         (_CSRE_INSN): Likewise.
1293         (aarch64_opcode_table): Delete csr.
1294
1295 2021-01-11  Nick Clifton  <nickc@redhat.com>
1296
1297         * po/de.po: Updated German translation.
1298         * po/fr.po: Updated French translation.
1299         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1300         * po/sv.po: Updated Swedish translation.
1301         * po/uk.po: Updated Ukranian translation.
1302
1303 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1304
1305         * configure: Regenerated.
1306
1307 2021-01-09  Nick Clifton  <nickc@redhat.com>
1308
1309         * configure: Regenerate.
1310         * po/opcodes.pot: Regenerate.
1311
1312 2021-01-09  Nick Clifton  <nickc@redhat.com>
1313
1314         * 2.36 release branch crated.
1315
1316 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1317
1318         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1319         (DW, (XRC_MASK): Define.
1320         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1321
1322 2021-01-09  Alan Modra  <amodra@gmail.com>
1323
1324         * configure: Regenerate.
1325
1326 2021-01-08  Nick Clifton  <nickc@redhat.com>
1327
1328         * po/sv.po: Updated Swedish translation.
1329
1330 2021-01-08  Nick Clifton  <nickc@redhat.com>
1331
1332         PR 27129
1333         * aarch64-dis.c (determine_disassembling_preference): Move call to
1334         aarch64_match_operands_constraint outside of the assertion.
1335         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1336         Replace with a return of FALSE.
1337
1338         PR 27139
1339         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1340         core system register.
1341
1342 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1343
1344         * configure: Regenerate.
1345
1346 2021-01-07  Nick Clifton  <nickc@redhat.com>
1347
1348         * po/fr.po: Updated French translation.
1349
1350 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1351
1352         * m68k-opc.c (chkl): Change minimum architecture requirement to
1353         m68020.
1354
1355 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1356
1357         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1358
1359 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1360             Jim Wilson  <jimw@sifive.com>
1361             Andrew Waterman  <andrew@sifive.com>
1362             Maxim Blinov  <maxim.blinov@embecosm.com>
1363             Kito Cheng  <kito.cheng@sifive.com>
1364             Nelson Chu  <nelson.chu@sifive.com>
1365
1366         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1367         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1368
1369 2021-01-01  Alan Modra  <amodra@gmail.com>
1370
1371         Update year range in copyright notice of all files.
1372
1373 For older changes see ChangeLog-2020
1374 \f
1375 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1376
1377 Copying and distribution of this file, with or without modification,
1378 are permitted in any medium without royalty provided the copyright
1379 notice and this notice are preserved.
1380
1381 Local Variables:
1382 mode: change-log
1383 left-margin: 8
1384 fill-column: 74
1385 version-control: never
1386 End: