opcodes/ChangeLog

   1 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   2
   3         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
   4         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
   5         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
   6         (cpu_flags): Add CpuIBT, CpuSHSTK.
   7         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
   8         (i386_cpu_flags): Add cpuibt, cpushstk.
   9         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
  10         * i386-init.h: Regenerate.
  11         * i386-tbl.h: Likewise.
  12
  13 2018-01-16  Nick Clifton  <nickc@redhat.com>
  14
  15         * po/pt_BR.po: Updated Brazilian Portugese translation.
  16         * po/de.po: Updated German translation.
  17
  18 2018-01-15  Jim Wilson  <jimw@sifive.com>
  19
  20         * riscv-opc.c (match_c_nop): New.
  21         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
  22
  23 2018-01-15  Nick Clifton  <nickc@redhat.com>
  24
  25         * po/uk.po: Updated Ukranian translation.
  26
  27 2018-01-13  Nick Clifton  <nickc@redhat.com>
  28
  29         * po/opcodes.pot: Regenerated.
  30
  31 2018-01-13  Nick Clifton  <nickc@redhat.com>
  32
  33         * configure: Regenerate.
  34
  35 2018-01-13  Nick Clifton  <nickc@redhat.com>
  36
  37         2.30 branch created.
  38
  39 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  40
  41         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
  42         * i386-tbl.h: Regenerate.
  43
  44 2018-01-10  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
  47         * i386-tbl.h: Re-generate.
  48
  49 2018-01-10  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
  52         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
  53         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
  54         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
  55         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
  56         Disp8MemShift of AVX512VL forms.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-01-09  Jim Wilson  <jimw@sifive.com>
  60
  61         * riscv-dis.c (maybe_print_address): If base_reg is zero,
  62         then the hi_addr value is zero.
  63
  64 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
  65
  66         * arm-dis.c (arm_opcodes): Add csdb.
  67         (thumb32_opcodes): Add csdb.
  68
  69 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
  70
  71         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
  72         * aarch64-asm-2.c: Regenerate.
  73         * aarch64-dis-2.c: Regenerate.
  74         * aarch64-opc-2.c: Regenerate.
  75
  76 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         PR gas/22681
  79         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
  80         Remove AVX512 vmovd with 64-bit operands.
  81         * i386-tbl.h: Regenerated.
  82
  83 2018-01-05  Jim Wilson  <jimw@sifive.com>
  84
  85         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
  86         jalr.
  87
  88 2018-01-03  Alan Modra  <amodra@gmail.com>
  89
  90         Update year range in copyright notice of all files.
  91
  92 2018-01-02  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
  95         and OPERAND_TYPE_REGZMM entries.
  96
  97 For older changes see ChangeLog-2017
  98 \f
  99 Copyright (C) 2018 Free Software Foundation, Inc.
 100
 101 Copying and distribution of this file, with or without modification,
 102 are permitted in any medium without royalty provided the copyright
 103 notice and this notice are preserved.
 104
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