opcodes/ChangeLog

   1 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
   4         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
   5         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
   6         (cpu_flags): Add CpuCMOV and CpuFXSR.
   7         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
   8         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
   9         * i386-init.h: Regenerated.
  10         * i386-tbl.h: Likewise.
  11
  12 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
  13
  14         * arc-regs.h: Update auxiliary registers.
  15
  16 2018-08-06  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
  19         (RegIP, RegIZ): Define.
  20         * i386-reg.tbl: Adjust comments.
  21         (rip): Use Qword instead of BaseIndex. Use RegIP.
  22         (eip): Use Dword instead of BaseIndex. Use RegIP.
  23         (riz): Add Qword. Use RegIZ.
  24         (eiz): Add Dword. Use RegIZ.
  25         * i386-tbl.h: Re-generate.
  26
  27 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
  30         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
  31         vpmovzxdq, vpmovzxwd): Remove NoRex64.
  32         * i386-tbl.h: Re-generate.
  33
  34 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-gen.c (operand_types): Remove Mem field.
  37         * i386-opc.h (union i386_operand_type): Remove mem field.
  38         * i386-init.h, i386-tbl.h: Re-generate.
  39
  40 2018-08-01  Alan Modra  <amodra@gmail.com>
  41
  42         * po/POTFILES.in: Regenerate.
  43
  44 2018-07-31  Nick Clifton  <nickc@redhat.com>
  45
  46         * po/sv.po: Updated Swedish translation.
  47
  48 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  51         * i386-init.h, i386-tbl.h: Re-generate.
  52
  53 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-opc.h (ZEROING_MASKING) Rename to ...
  56         (DYNAMIC_MASKING): ... this. Adjust comment.
  57         * i386-opc.tbl (MaskingMorZ): Define.
  58         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  59         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  60         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  61         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  62         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  63         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  64         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  65         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  66         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  67
  68 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-opc.tbl: Use element rather than vector size for AVX512*
  71         scatter/gather insns.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  77         (cpu_flags): Drop CpuVREX.
  78         * i386-opc.h (CpuVREX): Delete.
  79         (union i386_cpu_flags): Remove cpuvrex.
  80         * i386-init.h, i386-tbl.h: Re-generate.
  81
  82 2018-07-30  Jim Wilson  <jimw@sifive.com>
  83
  84         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  85         fields.
  86         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  87
  88 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  89
  90         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  91         * Makefile.in: Regenerated.
  92         * configure.ac: Add C-SKY.
  93         * configure: Regenerated.
  94         * csky-dis.c: New file.
  95         * csky-opc.h: New file.
  96         * disassemble.c (ARCH_csky): Define.
  97         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  98         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  99
 100 2018-07-27  Alan Modra  <amodra@gmail.com>
 101
 102         * ppc-opc.c (insert_sprbat): Correct function parameter and
 103         return type.
 104         (extract_sprbat): Likewise, variable too.
 105
 106 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 107             Alan Modra  <amodra@gmail.com>
 108
 109         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 110         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 111         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 112         support disjointed BAT.
 113         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 114         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 115         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 116
 117 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 118             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 119
 120         * i386-gen.c (adjust_broadcast_modifier): New function.
 121         (process_i386_opcode_modifier): Add an argument for operands.
 122         Adjust the Broadcast value based on operands.
 123         (output_i386_opcode): Pass operand_types to
 124         process_i386_opcode_modifier.
 125         (process_i386_opcodes): Pass NULL as operands to
 126         process_i386_opcode_modifier.
 127         * i386-opc.h (BYTE_BROADCAST): New.
 128         (WORD_BROADCAST): Likewise.
 129         (DWORD_BROADCAST): Likewise.
 130         (QWORD_BROADCAST): Likewise.
 131         (i386_opcode_modifier): Expand broadcast to 3 bits.
 132         * i386-tbl.h: Regenerated.
 133
 134 2018-07-24  Alan Modra  <amodra@gmail.com>
 135
 136         PR 23430
 137         * or1k-desc.h: Regenerate.
 138
 139 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 142         vcvtusi2ss, and vcvtusi2sd.
 143         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 144         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 145         * i386-tbl.h: Re-generate.
 146
 147 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 148
 149         * arc-opc.c (extract_w6): Fix extending the sign.
 150
 151 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 152
 153         * arc-tbl.h (vewt): Allow it for ARC EM family.
 154
 155 2018-07-23  Alan Modra  <amodra@gmail.com>
 156
 157         PR 23419
 158         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 159         opcode variants for mtspr/mfspr encodings.
 160
 161 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 162             Maciej W. Rozycki  <macro@mips.com>
 163
 164         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 165         loongson3a descriptors.
 166         (parse_mips_ase_option): Handle -M loongson-mmi option.
 167         (print_mips_disassembler_options): Document -M loongson-mmi.
 168         * mips-opc.c (LMMI): New macro.
 169         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 170         instructions.
 171
 172 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 175         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 176         IgnoreSize and [XYZ]MMword where applicable.
 177         * i386-tbl.h: Re-generate.
 178
 179 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 182         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 183         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 184         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 185         * i386-tbl.h: Re-generate.
 186
 187 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 190         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 191         VPCLMULQDQ templates into their respective AVX512VL counterparts
 192         where possible, using Disp8ShiftVL and CheckRegSize instead of
 193         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 194         * i386-tbl.h: Re-generate.
 195
 196 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 199         AVX512VL counterparts where possible, using Disp8ShiftVL and
 200         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 201         IgnoreSize) as appropriate.
 202         * i386-tbl.h: Re-generate.
 203
 204 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-opc.tbl: Fold AVX512BW templates into their respective
 207         AVX512VL counterparts where possible, using Disp8ShiftVL and
 208         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 209         IgnoreSize) as appropriate.
 210         * i386-tbl.h: Re-generate.
 211
 212 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-opc.tbl: Fold AVX512CD templates into their respective
 215         AVX512VL counterparts where possible, using Disp8ShiftVL and
 216         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 217         IgnoreSize) as appropriate.
 218         * i386-tbl.h: Re-generate.
 219
 220 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.h (DISP8_SHIFT_VL): New.
 223         * i386-opc.tbl (Disp8ShiftVL):  Define.
 224         (various): Fold AVX512VL templates into their respective
 225         AVX512F counterparts where possible, using Disp8ShiftVL and
 226         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 227         IgnoreSize) as appropriate.
 228         * i386-tbl.h: Re-generate.
 229
 230 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 231
 232         * Makefile.am: Change dependencies and rule for
 233         $(srcdir)/i386-init.h.
 234         * Makefile.in: Re-generate.
 235         * i386-gen.c (process_i386_opcodes): New local variable
 236         "marker". Drop opening of input file. Recognize marker and line
 237         number directives.
 238         * i386-opc.tbl (OPCODE_I386_H): Define.
 239         (i386-opc.h): Include it.
 240         (None): Undefine.
 241
 242 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 243
 244         PR gas/23418
 245         * i386-opc.h (Byte): Update comments.
 246         (Word): Likewise.
 247         (Dword): Likewise.
 248         (Fword): Likewise.
 249         (Qword): Likewise.
 250         (Tbyte): Likewise.
 251         (Xmmword): Likewise.
 252         (Ymmword): Likewise.
 253         (Zmmword): Likewise.
 254         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 255         vcvttps2uqq.
 256         * i386-tbl.h: Regenerated.
 257
 258 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 259
 260         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 261         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 262         * aarch64-asm-2.c: Regenerate.
 263         * aarch64-dis-2.c: Regenerate.
 264         * aarch64-opc-2.c: Regenerate.
 265
 266 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 267
 268         PR binutils/23192
 269         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 270         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 271         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 272         sqdmulh, sqrdmulh): Use Em16.
 273
 274 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 275
 276         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 277         csdb together with them.
 278         (thumb32_opcodes): Likewise.
 279
 280 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 283         requiring 32-bit registers as operands 2 and 3. Improve
 284         comments.
 285         (mwait, mwaitx): Fold templates. Improve comments.
 286         OPERAND_TYPE_INOUTPORTREG.
 287         * i386-tbl.h: Re-generate.
 288
 289 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (operand_type_init): Remove
 292         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 293         OPERAND_TYPE_INOUTPORTREG.
 294         * i386-init.h: Re-generate.
 295
 296 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 299         (wrssq, wrussq): Add Qword.
 300         * i386-tbl.h: Re-generate.
 301
 302 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.h: Rename OTMax to OTNum.
 305         (OTNumOfUints): Adjust calculation.
 306         (OTUnused): Directly alias to OTNum.
 307
 308 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 309
 310         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 311         `reg_xys'.
 312         (lea_reg_xys): Likewise.
 313         (print_insn_loop_primitive): Rename `reg' local variable to
 314         `reg_dxy'.
 315
 316 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 317
 318         PR binutils/23242
 319         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 320
 321 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 322
 323         PR binutils/23369
 324         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 325         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 326
 327 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 328
 329         PR tdep/8282
 330         * mips-dis.c (mips_option_arg_t): New enumeration.
 331         (mips_options): New variable.
 332         (disassembler_options_mips): New function.
 333         (print_mips_disassembler_options): Reimplement in terms of
 334         `disassembler_options_mips'.
 335         * arm-dis.c (disassembler_options_arm): Adapt to using the
 336         `disasm_options_and_args_t' structure.
 337         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 338         * s390-dis.c (disassembler_options_s390): Likewise.
 339
 340 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 341
 342         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 343         expected result.
 344         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 345         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 346         * testsuite/ld-arm/tls-longplt.d: Likewise.
 347
 348 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 349
 350         PR binutils/23192
 351         * aarch64-asm-2.c: Regenerate.
 352         * aarch64-dis-2.c: Likewise.
 353         * aarch64-opc-2.c: Likewise.
 354         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 355         * aarch64-opc.c (operand_general_constraint_met_p,
 356         aarch64_print_operand): Likewise.
 357         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 358         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 359         fmlal2, fmlsl2.
 360         (AARCH64_OPERANDS): Add Em2.
 361
 362 2018-06-26  Nick Clifton  <nickc@redhat.com>
 363
 364         * po/uk.po: Updated Ukranian translation.
 365         * po/de.po: Updated German translation.
 366         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 367
 368 2018-06-26  Nick Clifton  <nickc@redhat.com>
 369
 370         * nfp-dis.c: Fix spelling mistake.
 371
 372 2018-06-24  Nick Clifton  <nickc@redhat.com>
 373
 374         * configure: Regenerate.
 375         * po/opcodes.pot: Regenerate.
 376
 377 2018-06-24  Nick Clifton  <nickc@redhat.com>
 378
 379         2.31 branch created.
 380
 381 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 382
 383         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 384         * aarch64-asm-2.c: Regenerate.
 385         * aarch64-dis-2.c: Likewise.
 386
 387 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 388
 389         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 390         `-M ginv' option description.
 391
 392 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 393
 394         PR gas/23305
 395         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 396         la and lla.
 397
 398 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 399
 400         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 401         * configure.ac: Remove AC_PREREQ.
 402         * Makefile.in: Re-generate.
 403         * aclocal.m4: Re-generate.
 404         * configure: Re-generate.
 405
 406 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 407
 408         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 409         mips64r6 descriptors.
 410         (parse_mips_ase_option): Handle -Mginv option.
 411         (print_mips_disassembler_options): Document -Mginv.
 412         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 413         (GINV): New macro.
 414         (mips_opcodes): Define ginvi and ginvt.
 415
 416 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 417             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 418
 419         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 420         * mips-opc.c (CRC, CRC64): New macros.
 421         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 422         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 423         crc32cd for CRC64.
 424
 425 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 426
 427         PR 20319
 428         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 429         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 430
 431 2018-06-06  Alan Modra  <amodra@gmail.com>
 432
 433         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 434         setjmp.  Move init for some other vars later too.
 435
 436 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 437
 438         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 439         (dis_private): Add new fields for property section tracking.
 440         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 441         (xtensa_instruction_fits): New functions.
 442         (fetch_data): Bump minimal fetch size to 4.
 443         (print_insn_xtensa): Make struct dis_private static.
 444         Load and prepare property table on section change.
 445         Don't disassemble literals. Don't disassemble instructions that
 446         cross property table boundaries.
 447
 448 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 449
 450         * configure: Regenerated.
 451
 452 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 455         * i386-tbl.h: Re-generate.
 456
 457 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-opc.tbl (sldt, str): Add NoRex64.
 460         * i386-tbl.h: Re-generate.
 461
 462 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-opc.tbl (invpcid): Add Oword.
 465         * i386-tbl.h: Re-generate.
 466
 467 2018-06-01  Alan Modra  <amodra@gmail.com>
 468
 469         * sysdep.h (_bfd_error_handler): Don't declare.
 470         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 471         * rl78-decode.opc: Likewise.
 472         * msp430-decode.c: Regenerate.
 473         * rl78-decode.c: Regenerate.
 474
 475 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 476
 477         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 478         * i386-init.h : Regenerated.
 479
 480 2018-05-25  Alan Modra  <amodra@gmail.com>
 481
 482         * Makefile.in: Regenerate.
 483         * po/POTFILES.in: Regenerate.
 484
 485 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 486
 487         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 488         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 489         (insert_bab, extract_bab, insert_btab, extract_btab,
 490         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 491         (BAT, BBA VBA RBS XB6S): Delete macros.
 492         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 493         (BB, BD, RBX, XC6): Update for new macros.
 494         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 495         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 496         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 497         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 498
 499 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 500
 501         * Makefile.am: Add support for s12z architecture.
 502         * configure.ac: Likewise.
 503         * disassemble.c: Likewise.
 504         * disassemble.h: Likewise.
 505         * Makefile.in: Regenerate.
 506         * configure: Regenerate.
 507         * s12z-dis.c: New file.
 508         * s12z.h: New file.
 509
 510 2018-05-18  Alan Modra  <amodra@gmail.com>
 511
 512         * nfp-dis.c: Don't #include libbfd.h.
 513         (init_nfp3200_priv): Use bfd_get_section_contents.
 514         (nit_nfp6000_mecsr_sec): Likewise.
 515
 516 2018-05-17  Nick Clifton  <nickc@redhat.com>
 517
 518         * po/zh_CN.po: Updated simplified Chinese translation.
 519
 520 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 521
 522         PR binutils/23109
 523         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 524         * aarch64-dis-2.c: Regenerate.
 525
 526 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 527
 528         PR binutils/21446
 529         * aarch64-asm.c (opintl.h): Include.
 530         (aarch64_ins_sysreg): Enforce read/write constraints.
 531         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 532         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 533         (F_REG_READ, F_REG_WRITE): New.
 534         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 535         AARCH64_OPND_SYSREG.
 536         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 537         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 538         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 539         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 540         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 541         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 542         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 543         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 544         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 545         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 546         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 547         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 548         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 549         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 550         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 551         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 552         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 553
 554 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 555
 556         PR binutils/21446
 557         * aarch64-dis.c (no_notes: New.
 558         (parse_aarch64_dis_option): Support notes.
 559         (aarch64_decode_insn, print_operands): Likewise.
 560         (print_aarch64_disassembler_options): Document notes.
 561         * aarch64-opc.c (aarch64_print_operand): Support notes.
 562
 563 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 564
 565         PR binutils/21446
 566         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 567         and take error struct.
 568         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 569         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 570         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 571         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 572         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 573         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 574         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 575         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 576         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 577         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 578         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 579         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 580         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 581         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 582         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 583         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 584         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 585         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 586         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 587         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 588         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 589         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 590         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 591         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 592         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 593         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 594         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 595         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 596         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 597         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 598         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 599         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 600         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 601         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 602         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 603         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 604         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 605         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 606         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 607         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 608         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 609         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 610         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 611         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 612         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 613         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 614         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 615         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 616         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 617         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 618         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 619         (determine_disassembling_preference, aarch64_decode_insn,
 620         print_insn_aarch64_word, print_insn_data): Take errors struct.
 621         (print_insn_aarch64): Use errors.
 622         * aarch64-asm-2.c: Regenerate.
 623         * aarch64-dis-2.c: Regenerate.
 624         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 625         boolean in aarch64_insert_operan.
 626         (print_operand_extractor): Likewise.
 627         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 628
 629 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 630
 631         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 632
 633 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 634
 635         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 636
 637 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 638
 639         * cr16-opc.c (cr16_instruction): Comment typo fix.
 640         * hppa-dis.c (print_insn_hppa): Likewise.
 641
 642 2018-05-08  Jim Wilson  <jimw@sifive.com>
 643
 644         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 645         (match_c_slli64, match_srxi_as_c_srxi): New.
 646         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 647         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 648         <c.slli, c.srli, c.srai>: Use match_s_slli.
 649         <c.slli64, c.srli64, c.srai64>: New.
 650
 651 2018-05-08  Alan Modra  <amodra@gmail.com>
 652
 653         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 654         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 655         partition opcode space for index lookup.
 656
 657 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 658
 659         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 660         <insn_length>: ...with this.  Update usage.
 661         Remove duplicate call to *info->memory_error_func.
 662
 663 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 664             H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * i386-dis.c (Gva): New.
 667         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 668         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 669         (prefix_table): New instructions (see prefix above).
 670         (mod_table): New instructions (see prefix above).
 671         (OP_G): Handle va_mode.
 672         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 673         CPU_MOVDIR64B_FLAGS.
 674         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 675         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 676         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 677         * i386-opc.tbl: Add movidir{i,64b}.
 678         * i386-init.h: Regenerated.
 679         * i386-tbl.h: Likewise.
 680
 681 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 684         AddrPrefixOpReg.
 685         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 686         (AddrPrefixOpReg): This.
 687         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 688         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 689
 690 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 691
 692         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 693         (vle_num_opcodes): Likewise.
 694         (spe2_num_opcodes): Likewise.
 695         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 696         initialization loop.
 697         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 698         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 699         only once.
 700
 701 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 702
 703         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 704
 705 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 706
 707         Makefile.am: Added nfp-dis.c.
 708         configure.ac: Added bfd_nfp_arch.
 709         disassemble.h: Added print_insn_nfp prototype.
 710         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 711         nfp-dis.c: New, for NFP support.
 712         po/POTFILES.in: Added nfp-dis.c to the list.
 713         Makefile.in: Regenerate.
 714         configure: Regenerate.
 715
 716 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 719         templates into their base ones.
 720         * i386-tlb.h: Re-generate.
 721
 722 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 725         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 726         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 727         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 728         * i386-init.h: Re-generate.
 729
 730 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 733         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 734         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 735         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 736         comment.
 737         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 738         and CpuRegMask.
 739         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 740         CpuRegMask: Delete.
 741         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 742         cpuregzmm, and cpuregmask.
 743         * i386-init.h: Re-generate.
 744         * i386-tbl.h: Re-generate.
 745
 746 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 749         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 750         * i386-init.h: Re-generate.
 751
 752 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-gen.c (VexImmExt): Delete.
 755         * i386-opc.h (VexImmExt, veximmext): Delete.
 756         * i386-opc.tbl: Drop all VexImmExt uses.
 757         * i386-tlb.h: Re-generate.
 758
 759 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 762         register-only forms.
 763         * i386-tlb.h: Re-generate.
 764
 765 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 766
 767         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 768
 769 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 770
 771         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 772         PREFIX_0F1C.
 773         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 774         (cpu_flags): Add CpuCLDEMOTE.
 775         * i386-init.h: Regenerate.
 776         * i386-opc.h (enum): Add CpuCLDEMOTE,
 777         (i386_cpu_flags): Add cpucldemote.
 778         * i386-opc.tbl: Add cldemote.
 779         * i386-tbl.h: Regenerate.
 780
 781 2018-04-16  Alan Modra  <amodra@gmail.com>
 782
 783         * Makefile.am: Remove sh5 and sh64 support.
 784         * configure.ac: Likewise.
 785         * disassemble.c: Likewise.
 786         * disassemble.h: Likewise.
 787         * sh-dis.c: Likewise.
 788         * sh64-dis.c: Delete.
 789         * sh64-opc.c: Delete.
 790         * sh64-opc.h: Delete.
 791         * Makefile.in: Regenerate.
 792         * configure: Regenerate.
 793         * po/POTFILES.in: Regenerate.
 794
 795 2018-04-16  Alan Modra  <amodra@gmail.com>
 796
 797         * Makefile.am: Remove w65 support.
 798         * configure.ac: Likewise.
 799         * disassemble.c: Likewise.
 800         * disassemble.h: Likewise.
 801         * w65-dis.c: Delete.
 802         * w65-opc.h: Delete.
 803         * Makefile.in: Regenerate.
 804         * configure: Regenerate.
 805         * po/POTFILES.in: Regenerate.
 806
 807 2018-04-16  Alan Modra  <amodra@gmail.com>
 808
 809         * configure.ac: Remove we32k support.
 810         * configure: Regenerate.
 811
 812 2018-04-16  Alan Modra  <amodra@gmail.com>
 813
 814         * Makefile.am: Remove m88k support.
 815         * configure.ac: Likewise.
 816         * disassemble.c: Likewise.
 817         * disassemble.h: Likewise.
 818         * m88k-dis.c: Delete.
 819         * Makefile.in: Regenerate.
 820         * configure: Regenerate.
 821         * po/POTFILES.in: Regenerate.
 822
 823 2018-04-16  Alan Modra  <amodra@gmail.com>
 824
 825         * Makefile.am: Remove i370 support.
 826         * configure.ac: Likewise.
 827         * disassemble.c: Likewise.
 828         * disassemble.h: Likewise.
 829         * i370-dis.c: Delete.
 830         * i370-opc.c: Delete.
 831         * Makefile.in: Regenerate.
 832         * configure: Regenerate.
 833         * po/POTFILES.in: Regenerate.
 834
 835 2018-04-16  Alan Modra  <amodra@gmail.com>
 836
 837         * Makefile.am: Remove h8500 support.
 838         * configure.ac: Likewise.
 839         * disassemble.c: Likewise.
 840         * disassemble.h: Likewise.
 841         * h8500-dis.c: Delete.
 842         * h8500-opc.h: Delete.
 843         * Makefile.in: Regenerate.
 844         * configure: Regenerate.
 845         * po/POTFILES.in: Regenerate.
 846
 847 2018-04-16  Alan Modra  <amodra@gmail.com>
 848
 849         * configure.ac: Remove tahoe support.
 850         * configure: Regenerate.
 851
 852 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 853
 854         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 855         umwait.
 856         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 857         64-bit mode.
 858         * i386-tbl.h: Regenerated.
 859
 860 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 861
 862         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 863         PREFIX_MOD_1_0FAE_REG_6.
 864         (va_mode): New.
 865         (OP_E_register): Use va_mode.
 866         * i386-dis-evex.h (prefix_table):
 867         New instructions (see prefixes above).
 868         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 869         (cpu_flags): Likewise.
 870         * i386-opc.h (enum): Likewise.
 871         (i386_cpu_flags): Likewise.
 872         * i386-opc.tbl: Add umonitor, umwait, tpause.
 873         * i386-init.h: Regenerate.
 874         * i386-tbl.h: Likewise.
 875
 876 2018-04-11  Alan Modra  <amodra@gmail.com>
 877
 878         * opcodes/i860-dis.c: Delete.
 879         * opcodes/i960-dis.c: Delete.
 880         * Makefile.am: Remove i860 and i960 support.
 881         * configure.ac: Likewise.
 882         * disassemble.c: Likewise.
 883         * disassemble.h: Likewise.
 884         * Makefile.in: Regenerate.
 885         * configure: Regenerate.
 886         * po/POTFILES.in: Regenerate.
 887
 888 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 889
 890         PR binutils/23025
 891         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 892         to 0.
 893         (print_insn): Clear vex instead of vex.evex.
 894
 895 2018-04-04  Nick Clifton  <nickc@redhat.com>
 896
 897         * po/es.po: Updated Spanish translation.
 898
 899 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-gen.c (opcode_modifiers): Delete VecESize.
 902         * i386-opc.h (VecESize): Delete.
 903         (struct i386_opcode_modifier): Delete vecesize.
 904         * i386-opc.tbl: Drop VecESize.
 905         * i386-tlb.h: Re-generate.
 906
 907 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 910         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 911         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 912         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 913         * i386-tlb.h: Re-generate.
 914
 915 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 918         Fold AVX512 forms
 919         * i386-tlb.h: Re-generate.
 920
 921 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 924         (vex_len_table): Drop Y for vcvt*2si.
 925         (putop): Replace plain 'Y' handling by abort().
 926
 927 2018-03-28  Nick Clifton  <nickc@redhat.com>
 928
 929         PR 22988
 930         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 931         instructions with only a base address register.
 932         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 933         handle AARHC64_OPND_SVE_ADDR_R.
 934         (aarch64_print_operand): Likewise.
 935         * aarch64-asm-2.c: Regenerate.
 936         * aarch64_dis-2.c: Regenerate.
 937         * aarch64-opc-2.c: Regenerate.
 938
 939 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-opc.tbl: Drop VecESize from register only insn forms and
 942         memory forms not allowing broadcast.
 943         * i386-tlb.h: Re-generate.
 944
 945 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 946
 947         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 948         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 949         sha256*): Drop Disp<N>.
 950
 951 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-dis.c (EbndS, bnd_swap_mode): New.
 954         (prefix_table): Use EbndS.
 955         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 956         * i386-opc.tbl (bndmov): Move misplaced Load.
 957         * i386-tlb.h: Re-generate.
 958
 959 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 962         templates allowing memory operands and folded ones for register
 963         only flavors.
 964         * i386-tlb.h: Re-generate.
 965
 966 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 969         256-bit templates. Drop redundant leftover Disp<N>.
 970         * i386-tlb.h: Re-generate.
 971
 972 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 973
 974         * riscv-opc.c (riscv_insn_types): New.
 975
 976 2018-03-13  Nick Clifton  <nickc@redhat.com>
 977
 978         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 979
 980 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         * i386-opc.tbl: Add Optimize to clr.
 983         * i386-tbl.h: Regenerated.
 984
 985 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 986
 987         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 988         * i386-opc.h (OldGcc): Removed.
 989         (i386_opcode_modifier): Remove oldgcc.
 990         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 991         instructions for old (<= 2.8.1) versions of gcc.
 992         * i386-tbl.h: Regenerated.
 993
 994 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.h (EVEXDYN): New.
 997         * i386-opc.tbl: Fold various AVX512VL templates.
 998         * i386-tlb.h: Re-generate.
 999
1000 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1003         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1004         vpexpandd, vpexpandq): Fold AFX512VF templates.
1005         * i386-tlb.h: Re-generate.
1006
1007 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1008
1009         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1010         Fold 128- and 256-bit VEX-encoded templates.
1011         * i386-tlb.h: Re-generate.
1012
1013 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1016         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1017         vpexpandd, vpexpandq): Fold AVX512F templates.
1018         * i386-tlb.h: Re-generate.
1019
1020 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1021
1022         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1023         64-bit templates. Drop Disp<N>.
1024         * i386-tlb.h: Re-generate.
1025
1026 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1029         and 256-bit templates.
1030         * i386-tlb.h: Re-generate.
1031
1032 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1035         * i386-tlb.h: Re-generate.
1036
1037 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1040         Drop NoAVX.
1041         * i386-tlb.h: Re-generate.
1042
1043 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1046         * i386-tlb.h: Re-generate.
1047
1048 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-gen.c (opcode_modifiers): Delete FloatD.
1051         * i386-opc.h (FloatD): Delete.
1052         (struct i386_opcode_modifier): Delete floatd.
1053         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1054         FloatD by D.
1055         * i386-tlb.h: Re-generate.
1056
1057 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1058
1059         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1060
1061 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1062
1063         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1064         * i386-tlb.h: Re-generate.
1065
1066 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1069         forms.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-07  Alan Modra  <amodra@gmail.com>
1073
1074         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1075         bfd_arch_rs6000.
1076         * disassemble.h (print_insn_rs6000): Delete.
1077         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1078         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1079         (print_insn_rs6000): Delete.
1080
1081 2018-03-03  Alan Modra  <amodra@gmail.com>
1082
1083         * sysdep.h (opcodes_error_handler): Define.
1084         (_bfd_error_handler): Declare.
1085         * Makefile.am: Remove stray #.
1086         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1087         EDIT" comment.
1088         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1089         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1090         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1091         opcodes_error_handler to print errors.  Standardize error messages.
1092         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1093         and include opintl.h.
1094         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1095         * i386-gen.c: Standardize error messages.
1096         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1097         * Makefile.in: Regenerate.
1098         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1099         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1100         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1101         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1102         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1103         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1104         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1105         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1106         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1107         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1108         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1109         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1110         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1111
1112 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1113
1114         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1115         vpsub[bwdq] instructions.
1116         * i386-tbl.h: Regenerated.
1117
1118 2018-03-01  Alan Modra  <amodra@gmail.com>
1119
1120         * configure.ac (ALL_LINGUAS): Sort.
1121         * configure: Regenerate.
1122
1123 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1124
1125         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1126         macro by assignements.
1127
1128 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1129
1130         PR gas/22871
1131         * i386-gen.c (opcode_modifiers): Add Optimize.
1132         * i386-opc.h (Optimize): New enum.
1133         (i386_opcode_modifier): Add optimize.
1134         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1135         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1136         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1137         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1138         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1139         vpxord and vpxorq.
1140         * i386-tbl.h: Regenerated.
1141
1142 2018-02-26  Alan Modra  <amodra@gmail.com>
1143
1144         * crx-dis.c (getregliststring): Allocate a large enough buffer
1145         to silence false positive gcc8 warning.
1146
1147 2018-02-22  Shea Levy <shea@shealevy.com>
1148
1149         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1150
1151 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1152
1153         * i386-opc.tbl: Add {rex},
1154         * i386-tbl.h: Regenerated.
1155
1156 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1157
1158         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1159         (mips16_opcodes): Replace `M' with `m' for "restore".
1160
1161 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1162
1163         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1164
1165 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1166
1167         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1168         variable to `function_index'.
1169
1170 2018-02-13  Nick Clifton  <nickc@redhat.com>
1171
1172         PR 22823
1173         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1174         about truncation of printing.
1175
1176 2018-02-12  Henry Wong <henry@stuffedcow.net>
1177
1178         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1179
1180 2018-02-05  Nick Clifton  <nickc@redhat.com>
1181
1182         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1183
1184 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1185
1186         * i386-dis.c (enum): Add pconfig.
1187         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1188         (cpu_flags): Add CpuPCONFIG.
1189         * i386-opc.h (enum): Add CpuPCONFIG.
1190         (i386_cpu_flags): Add cpupconfig.
1191         * i386-opc.tbl: Add PCONFIG instruction.
1192         * i386-init.h: Regenerate.
1193         * i386-tbl.h: Likewise.
1194
1195 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1196
1197         * i386-dis.c (enum): Add PREFIX_0F09.
1198         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1199         (cpu_flags): Add CpuWBNOINVD.
1200         * i386-opc.h (enum): Add CpuWBNOINVD.
1201         (i386_cpu_flags): Add cpuwbnoinvd.
1202         * i386-opc.tbl: Add WBNOINVD instruction.
1203         * i386-init.h: Regenerate.
1204         * i386-tbl.h: Likewise.
1205
1206 2018-01-17  Jim Wilson  <jimw@sifive.com>
1207
1208         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1209
1210 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1211
1212         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1213         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1214         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1215         (cpu_flags): Add CpuIBT, CpuSHSTK.
1216         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1217         (i386_cpu_flags): Add cpuibt, cpushstk.
1218         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1219         * i386-init.h: Regenerate.
1220         * i386-tbl.h: Likewise.
1221
1222 2018-01-16  Nick Clifton  <nickc@redhat.com>
1223
1224         * po/pt_BR.po: Updated Brazilian Portugese translation.
1225         * po/de.po: Updated German translation.
1226
1227 2018-01-15  Jim Wilson  <jimw@sifive.com>
1228
1229         * riscv-opc.c (match_c_nop): New.
1230         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1231
1232 2018-01-15  Nick Clifton  <nickc@redhat.com>
1233
1234         * po/uk.po: Updated Ukranian translation.
1235
1236 2018-01-13  Nick Clifton  <nickc@redhat.com>
1237
1238         * po/opcodes.pot: Regenerated.
1239
1240 2018-01-13  Nick Clifton  <nickc@redhat.com>
1241
1242         * configure: Regenerate.
1243
1244 2018-01-13  Nick Clifton  <nickc@redhat.com>
1245
1246         2.30 branch created.
1247
1248 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1249
1250         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1251         * i386-tbl.h: Regenerate.
1252
1253 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1256         * i386-tbl.h: Re-generate.
1257
1258 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1259
1260         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1261         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1262         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1263         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1264         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1265         Disp8MemShift of AVX512VL forms.
1266         * i386-tbl.h: Re-generate.
1267
1268 2018-01-09  Jim Wilson  <jimw@sifive.com>
1269
1270         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1271         then the hi_addr value is zero.
1272
1273 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1274
1275         * arm-dis.c (arm_opcodes): Add csdb.
1276         (thumb32_opcodes): Add csdb.
1277
1278 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1279
1280         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1281         * aarch64-asm-2.c: Regenerate.
1282         * aarch64-dis-2.c: Regenerate.
1283         * aarch64-opc-2.c: Regenerate.
1284
1285 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         PR gas/22681
1288         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1289         Remove AVX512 vmovd with 64-bit operands.
1290         * i386-tbl.h: Regenerated.
1291
1292 2018-01-05  Jim Wilson  <jimw@sifive.com>
1293
1294         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1295         jalr.
1296
1297 2018-01-03  Alan Modra  <amodra@gmail.com>
1298
1299         Update year range in copyright notice of all files.
1300
1301 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1304         and OPERAND_TYPE_REGZMM entries.
1305
1306 For older changes see ChangeLog-2017
1307 \f
1308 Copyright (C) 2018 Free Software Foundation, Inc.
1309
1310 Copying and distribution of this file, with or without modification,
1311 are permitted in any medium without royalty provided the copyright
1312 notice and this notice are preserved.
1313
1314 Local Variables:
1315 mode: change-log
1316 left-margin: 8
1317 fill-column: 74
1318 version-control: never
1319 End: