opcodes/ChangeLog

   1 2018-08-03  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
   4         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
   5         vpmovzxdq, vpmovzxwd): Remove NoRex64.
   6         * i386-tbl.h: Re-generate.
   7
   8 2018-08-03  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-gen.c (operand_types): Remove Mem field.
  11         * i386-opc.h (union i386_operand_type): Remove mem field.
  12         * i386-init.h, i386-tbl.h: Re-generate.
  13
  14 2018-08-01  Alan Modra  <amodra@gmail.com>
  15
  16         * po/POTFILES.in: Regenerate.
  17
  18 2018-07-31  Nick Clifton  <nickc@redhat.com>
  19
  20         * po/sv.po: Updated Swedish translation.
  21
  22 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  25         * i386-init.h, i386-tbl.h: Re-generate.
  26
  27 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-opc.h (ZEROING_MASKING) Rename to ...
  30         (DYNAMIC_MASKING): ... this. Adjust comment.
  31         * i386-opc.tbl (MaskingMorZ): Define.
  32         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  33         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  34         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  35         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  36         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  37         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  38         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  39         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  40         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  41
  42 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl: Use element rather than vector size for AVX512*
  45         scatter/gather insns.
  46         * i386-tbl.h: Re-generate.
  47
  48 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  51         (cpu_flags): Drop CpuVREX.
  52         * i386-opc.h (CpuVREX): Delete.
  53         (union i386_cpu_flags): Remove cpuvrex.
  54         * i386-init.h, i386-tbl.h: Re-generate.
  55
  56 2018-07-30  Jim Wilson  <jimw@sifive.com>
  57
  58         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  59         fields.
  60         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  61
  62 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  63
  64         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  65         * Makefile.in: Regenerated.
  66         * configure.ac: Add C-SKY.
  67         * configure: Regenerated.
  68         * csky-dis.c: New file.
  69         * csky-opc.h: New file.
  70         * disassemble.c (ARCH_csky): Define.
  71         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  72         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  73
  74 2018-07-27  Alan Modra  <amodra@gmail.com>
  75
  76         * ppc-opc.c (insert_sprbat): Correct function parameter and
  77         return type.
  78         (extract_sprbat): Likewise, variable too.
  79
  80 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  81             Alan Modra  <amodra@gmail.com>
  82
  83         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  84         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
  85         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
  86         support disjointed BAT.
  87         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
  88         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  89         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  90
  91 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  92             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  93
  94         * i386-gen.c (adjust_broadcast_modifier): New function.
  95         (process_i386_opcode_modifier): Add an argument for operands.
  96         Adjust the Broadcast value based on operands.
  97         (output_i386_opcode): Pass operand_types to
  98         process_i386_opcode_modifier.
  99         (process_i386_opcodes): Pass NULL as operands to
 100         process_i386_opcode_modifier.
 101         * i386-opc.h (BYTE_BROADCAST): New.
 102         (WORD_BROADCAST): Likewise.
 103         (DWORD_BROADCAST): Likewise.
 104         (QWORD_BROADCAST): Likewise.
 105         (i386_opcode_modifier): Expand broadcast to 3 bits.
 106         * i386-tbl.h: Regenerated.
 107
 108 2018-07-24  Alan Modra  <amodra@gmail.com>
 109
 110         PR 23430
 111         * or1k-desc.h: Regenerate.
 112
 113 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 116         vcvtusi2ss, and vcvtusi2sd.
 117         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 118         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 119         * i386-tbl.h: Re-generate.
 120
 121 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 122
 123         * arc-opc.c (extract_w6): Fix extending the sign.
 124
 125 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 126
 127         * arc-tbl.h (vewt): Allow it for ARC EM family.
 128
 129 2018-07-23  Alan Modra  <amodra@gmail.com>
 130
 131         PR 23419
 132         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 133         opcode variants for mtspr/mfspr encodings.
 134
 135 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 136             Maciej W. Rozycki  <macro@mips.com>
 137
 138         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 139         loongson3a descriptors.
 140         (parse_mips_ase_option): Handle -M loongson-mmi option.
 141         (print_mips_disassembler_options): Document -M loongson-mmi.
 142         * mips-opc.c (LMMI): New macro.
 143         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 144         instructions.
 145
 146 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 149         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 150         IgnoreSize and [XYZ]MMword where applicable.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 156         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 157         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 158         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 159         * i386-tbl.h: Re-generate.
 160
 161 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 164         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 165         VPCLMULQDQ templates into their respective AVX512VL counterparts
 166         where possible, using Disp8ShiftVL and CheckRegSize instead of
 167         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 168         * i386-tbl.h: Re-generate.
 169
 170 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 171
 172         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 173         AVX512VL counterparts where possible, using Disp8ShiftVL and
 174         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 175         IgnoreSize) as appropriate.
 176         * i386-tbl.h: Re-generate.
 177
 178 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl: Fold AVX512BW templates into their respective
 181         AVX512VL counterparts where possible, using Disp8ShiftVL and
 182         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 183         IgnoreSize) as appropriate.
 184         * i386-tbl.h: Re-generate.
 185
 186 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl: Fold AVX512CD templates into their respective
 189         AVX512VL counterparts where possible, using Disp8ShiftVL and
 190         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 191         IgnoreSize) as appropriate.
 192         * i386-tbl.h: Re-generate.
 193
 194 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-opc.h (DISP8_SHIFT_VL): New.
 197         * i386-opc.tbl (Disp8ShiftVL):  Define.
 198         (various): Fold AVX512VL templates into their respective
 199         AVX512F counterparts where possible, using Disp8ShiftVL and
 200         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 201         IgnoreSize) as appropriate.
 202         * i386-tbl.h: Re-generate.
 203
 204 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 205
 206         * Makefile.am: Change dependencies and rule for
 207         $(srcdir)/i386-init.h.
 208         * Makefile.in: Re-generate.
 209         * i386-gen.c (process_i386_opcodes): New local variable
 210         "marker". Drop opening of input file. Recognize marker and line
 211         number directives.
 212         * i386-opc.tbl (OPCODE_I386_H): Define.
 213         (i386-opc.h): Include it.
 214         (None): Undefine.
 215
 216 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         PR gas/23418
 219         * i386-opc.h (Byte): Update comments.
 220         (Word): Likewise.
 221         (Dword): Likewise.
 222         (Fword): Likewise.
 223         (Qword): Likewise.
 224         (Tbyte): Likewise.
 225         (Xmmword): Likewise.
 226         (Ymmword): Likewise.
 227         (Zmmword): Likewise.
 228         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 229         vcvttps2uqq.
 230         * i386-tbl.h: Regenerated.
 231
 232 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 233
 234         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 235         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 236         * aarch64-asm-2.c: Regenerate.
 237         * aarch64-dis-2.c: Regenerate.
 238         * aarch64-opc-2.c: Regenerate.
 239
 240 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 241
 242         PR binutils/23192
 243         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 244         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 245         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 246         sqdmulh, sqrdmulh): Use Em16.
 247
 248 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 249
 250         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 251         csdb together with them.
 252         (thumb32_opcodes): Likewise.
 253
 254 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 257         requiring 32-bit registers as operands 2 and 3. Improve
 258         comments.
 259         (mwait, mwaitx): Fold templates. Improve comments.
 260         OPERAND_TYPE_INOUTPORTREG.
 261         * i386-tbl.h: Re-generate.
 262
 263 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-gen.c (operand_type_init): Remove
 266         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 267         OPERAND_TYPE_INOUTPORTREG.
 268         * i386-init.h: Re-generate.
 269
 270 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 273         (wrssq, wrussq): Add Qword.
 274         * i386-tbl.h: Re-generate.
 275
 276 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-opc.h: Rename OTMax to OTNum.
 279         (OTNumOfUints): Adjust calculation.
 280         (OTUnused): Directly alias to OTNum.
 281
 282 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 283
 284         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 285         `reg_xys'.
 286         (lea_reg_xys): Likewise.
 287         (print_insn_loop_primitive): Rename `reg' local variable to
 288         `reg_dxy'.
 289
 290 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 291
 292         PR binutils/23242
 293         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 294
 295 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 296
 297         PR binutils/23369
 298         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 299         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 300
 301 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 302
 303         PR tdep/8282
 304         * mips-dis.c (mips_option_arg_t): New enumeration.
 305         (mips_options): New variable.
 306         (disassembler_options_mips): New function.
 307         (print_mips_disassembler_options): Reimplement in terms of
 308         `disassembler_options_mips'.
 309         * arm-dis.c (disassembler_options_arm): Adapt to using the
 310         `disasm_options_and_args_t' structure.
 311         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 312         * s390-dis.c (disassembler_options_s390): Likewise.
 313
 314 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 315
 316         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 317         expected result.
 318         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 319         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 320         * testsuite/ld-arm/tls-longplt.d: Likewise.
 321
 322 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 323
 324         PR binutils/23192
 325         * aarch64-asm-2.c: Regenerate.
 326         * aarch64-dis-2.c: Likewise.
 327         * aarch64-opc-2.c: Likewise.
 328         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 329         * aarch64-opc.c (operand_general_constraint_met_p,
 330         aarch64_print_operand): Likewise.
 331         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 332         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 333         fmlal2, fmlsl2.
 334         (AARCH64_OPERANDS): Add Em2.
 335
 336 2018-06-26  Nick Clifton  <nickc@redhat.com>
 337
 338         * po/uk.po: Updated Ukranian translation.
 339         * po/de.po: Updated German translation.
 340         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 341
 342 2018-06-26  Nick Clifton  <nickc@redhat.com>
 343
 344         * nfp-dis.c: Fix spelling mistake.
 345
 346 2018-06-24  Nick Clifton  <nickc@redhat.com>
 347
 348         * configure: Regenerate.
 349         * po/opcodes.pot: Regenerate.
 350
 351 2018-06-24  Nick Clifton  <nickc@redhat.com>
 352
 353         2.31 branch created.
 354
 355 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 356
 357         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 358         * aarch64-asm-2.c: Regenerate.
 359         * aarch64-dis-2.c: Likewise.
 360
 361 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 362
 363         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 364         `-M ginv' option description.
 365
 366 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 367
 368         PR gas/23305
 369         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 370         la and lla.
 371
 372 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 373
 374         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 375         * configure.ac: Remove AC_PREREQ.
 376         * Makefile.in: Re-generate.
 377         * aclocal.m4: Re-generate.
 378         * configure: Re-generate.
 379
 380 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 381
 382         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 383         mips64r6 descriptors.
 384         (parse_mips_ase_option): Handle -Mginv option.
 385         (print_mips_disassembler_options): Document -Mginv.
 386         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 387         (GINV): New macro.
 388         (mips_opcodes): Define ginvi and ginvt.
 389
 390 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 391             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 392
 393         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 394         * mips-opc.c (CRC, CRC64): New macros.
 395         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 396         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 397         crc32cd for CRC64.
 398
 399 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 400
 401         PR 20319
 402         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 403         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 404
 405 2018-06-06  Alan Modra  <amodra@gmail.com>
 406
 407         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 408         setjmp.  Move init for some other vars later too.
 409
 410 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 411
 412         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 413         (dis_private): Add new fields for property section tracking.
 414         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 415         (xtensa_instruction_fits): New functions.
 416         (fetch_data): Bump minimal fetch size to 4.
 417         (print_insn_xtensa): Make struct dis_private static.
 418         Load and prepare property table on section change.
 419         Don't disassemble literals. Don't disassemble instructions that
 420         cross property table boundaries.
 421
 422 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         * configure: Regenerated.
 425
 426 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 429         * i386-tbl.h: Re-generate.
 430
 431 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (sldt, str): Add NoRex64.
 434         * i386-tbl.h: Re-generate.
 435
 436 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-opc.tbl (invpcid): Add Oword.
 439         * i386-tbl.h: Re-generate.
 440
 441 2018-06-01  Alan Modra  <amodra@gmail.com>
 442
 443         * sysdep.h (_bfd_error_handler): Don't declare.
 444         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 445         * rl78-decode.opc: Likewise.
 446         * msp430-decode.c: Regenerate.
 447         * rl78-decode.c: Regenerate.
 448
 449 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 450
 451         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 452         * i386-init.h : Regenerated.
 453
 454 2018-05-25  Alan Modra  <amodra@gmail.com>
 455
 456         * Makefile.in: Regenerate.
 457         * po/POTFILES.in: Regenerate.
 458
 459 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 460
 461         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 462         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 463         (insert_bab, extract_bab, insert_btab, extract_btab,
 464         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 465         (BAT, BBA VBA RBS XB6S): Delete macros.
 466         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 467         (BB, BD, RBX, XC6): Update for new macros.
 468         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 469         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 470         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 471         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 472
 473 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 474
 475         * Makefile.am: Add support for s12z architecture.
 476         * configure.ac: Likewise.
 477         * disassemble.c: Likewise.
 478         * disassemble.h: Likewise.
 479         * Makefile.in: Regenerate.
 480         * configure: Regenerate.
 481         * s12z-dis.c: New file.
 482         * s12z.h: New file.
 483
 484 2018-05-18  Alan Modra  <amodra@gmail.com>
 485
 486         * nfp-dis.c: Don't #include libbfd.h.
 487         (init_nfp3200_priv): Use bfd_get_section_contents.
 488         (nit_nfp6000_mecsr_sec): Likewise.
 489
 490 2018-05-17  Nick Clifton  <nickc@redhat.com>
 491
 492         * po/zh_CN.po: Updated simplified Chinese translation.
 493
 494 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 495
 496         PR binutils/23109
 497         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 498         * aarch64-dis-2.c: Regenerate.
 499
 500 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 501
 502         PR binutils/21446
 503         * aarch64-asm.c (opintl.h): Include.
 504         (aarch64_ins_sysreg): Enforce read/write constraints.
 505         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 506         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 507         (F_REG_READ, F_REG_WRITE): New.
 508         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 509         AARCH64_OPND_SYSREG.
 510         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 511         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 512         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 513         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 514         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 515         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 516         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 517         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 518         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 519         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 520         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 521         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 522         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 523         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 524         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 525         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 526         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 527
 528 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 529
 530         PR binutils/21446
 531         * aarch64-dis.c (no_notes: New.
 532         (parse_aarch64_dis_option): Support notes.
 533         (aarch64_decode_insn, print_operands): Likewise.
 534         (print_aarch64_disassembler_options): Document notes.
 535         * aarch64-opc.c (aarch64_print_operand): Support notes.
 536
 537 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 538
 539         PR binutils/21446
 540         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 541         and take error struct.
 542         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 543         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 544         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 545         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 546         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 547         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 548         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 549         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 550         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 551         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 552         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 553         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 554         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 555         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 556         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 557         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 558         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 559         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 560         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 561         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 562         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 563         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 564         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 565         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 566         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 567         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 568         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 569         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 570         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 571         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 572         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 573         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 574         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 575         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 576         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 577         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 578         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 579         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 580         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 581         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 582         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 583         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 584         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 585         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 586         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 587         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 588         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 589         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 590         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 591         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 592         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 593         (determine_disassembling_preference, aarch64_decode_insn,
 594         print_insn_aarch64_word, print_insn_data): Take errors struct.
 595         (print_insn_aarch64): Use errors.
 596         * aarch64-asm-2.c: Regenerate.
 597         * aarch64-dis-2.c: Regenerate.
 598         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 599         boolean in aarch64_insert_operan.
 600         (print_operand_extractor): Likewise.
 601         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 602
 603 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 604
 605         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 606
 607 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 610
 611 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 612
 613         * cr16-opc.c (cr16_instruction): Comment typo fix.
 614         * hppa-dis.c (print_insn_hppa): Likewise.
 615
 616 2018-05-08  Jim Wilson  <jimw@sifive.com>
 617
 618         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 619         (match_c_slli64, match_srxi_as_c_srxi): New.
 620         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 621         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 622         <c.slli, c.srli, c.srai>: Use match_s_slli.
 623         <c.slli64, c.srli64, c.srai64>: New.
 624
 625 2018-05-08  Alan Modra  <amodra@gmail.com>
 626
 627         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 628         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 629         partition opcode space for index lookup.
 630
 631 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 632
 633         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 634         <insn_length>: ...with this.  Update usage.
 635         Remove duplicate call to *info->memory_error_func.
 636
 637 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 638             H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * i386-dis.c (Gva): New.
 641         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 642         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 643         (prefix_table): New instructions (see prefix above).
 644         (mod_table): New instructions (see prefix above).
 645         (OP_G): Handle va_mode.
 646         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 647         CPU_MOVDIR64B_FLAGS.
 648         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 649         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 650         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 651         * i386-opc.tbl: Add movidir{i,64b}.
 652         * i386-init.h: Regenerated.
 653         * i386-tbl.h: Likewise.
 654
 655 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 658         AddrPrefixOpReg.
 659         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 660         (AddrPrefixOpReg): This.
 661         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 662         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 663
 664 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 665
 666         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 667         (vle_num_opcodes): Likewise.
 668         (spe2_num_opcodes): Likewise.
 669         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 670         initialization loop.
 671         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 672         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 673         only once.
 674
 675 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 676
 677         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 678
 679 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 680
 681         Makefile.am: Added nfp-dis.c.
 682         configure.ac: Added bfd_nfp_arch.
 683         disassemble.h: Added print_insn_nfp prototype.
 684         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 685         nfp-dis.c: New, for NFP support.
 686         po/POTFILES.in: Added nfp-dis.c to the list.
 687         Makefile.in: Regenerate.
 688         configure: Regenerate.
 689
 690 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 693         templates into their base ones.
 694         * i386-tlb.h: Re-generate.
 695
 696 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 699         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 700         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 701         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 702         * i386-init.h: Re-generate.
 703
 704 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 707         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 708         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 709         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 710         comment.
 711         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 712         and CpuRegMask.
 713         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 714         CpuRegMask: Delete.
 715         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 716         cpuregzmm, and cpuregmask.
 717         * i386-init.h: Re-generate.
 718         * i386-tbl.h: Re-generate.
 719
 720 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 723         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 724         * i386-init.h: Re-generate.
 725
 726 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-gen.c (VexImmExt): Delete.
 729         * i386-opc.h (VexImmExt, veximmext): Delete.
 730         * i386-opc.tbl: Drop all VexImmExt uses.
 731         * i386-tlb.h: Re-generate.
 732
 733 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 736         register-only forms.
 737         * i386-tlb.h: Re-generate.
 738
 739 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 740
 741         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 742
 743 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 744
 745         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 746         PREFIX_0F1C.
 747         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 748         (cpu_flags): Add CpuCLDEMOTE.
 749         * i386-init.h: Regenerate.
 750         * i386-opc.h (enum): Add CpuCLDEMOTE,
 751         (i386_cpu_flags): Add cpucldemote.
 752         * i386-opc.tbl: Add cldemote.
 753         * i386-tbl.h: Regenerate.
 754
 755 2018-04-16  Alan Modra  <amodra@gmail.com>
 756
 757         * Makefile.am: Remove sh5 and sh64 support.
 758         * configure.ac: Likewise.
 759         * disassemble.c: Likewise.
 760         * disassemble.h: Likewise.
 761         * sh-dis.c: Likewise.
 762         * sh64-dis.c: Delete.
 763         * sh64-opc.c: Delete.
 764         * sh64-opc.h: Delete.
 765         * Makefile.in: Regenerate.
 766         * configure: Regenerate.
 767         * po/POTFILES.in: Regenerate.
 768
 769 2018-04-16  Alan Modra  <amodra@gmail.com>
 770
 771         * Makefile.am: Remove w65 support.
 772         * configure.ac: Likewise.
 773         * disassemble.c: Likewise.
 774         * disassemble.h: Likewise.
 775         * w65-dis.c: Delete.
 776         * w65-opc.h: Delete.
 777         * Makefile.in: Regenerate.
 778         * configure: Regenerate.
 779         * po/POTFILES.in: Regenerate.
 780
 781 2018-04-16  Alan Modra  <amodra@gmail.com>
 782
 783         * configure.ac: Remove we32k support.
 784         * configure: Regenerate.
 785
 786 2018-04-16  Alan Modra  <amodra@gmail.com>
 787
 788         * Makefile.am: Remove m88k support.
 789         * configure.ac: Likewise.
 790         * disassemble.c: Likewise.
 791         * disassemble.h: Likewise.
 792         * m88k-dis.c: Delete.
 793         * Makefile.in: Regenerate.
 794         * configure: Regenerate.
 795         * po/POTFILES.in: Regenerate.
 796
 797 2018-04-16  Alan Modra  <amodra@gmail.com>
 798
 799         * Makefile.am: Remove i370 support.
 800         * configure.ac: Likewise.
 801         * disassemble.c: Likewise.
 802         * disassemble.h: Likewise.
 803         * i370-dis.c: Delete.
 804         * i370-opc.c: Delete.
 805         * Makefile.in: Regenerate.
 806         * configure: Regenerate.
 807         * po/POTFILES.in: Regenerate.
 808
 809 2018-04-16  Alan Modra  <amodra@gmail.com>
 810
 811         * Makefile.am: Remove h8500 support.
 812         * configure.ac: Likewise.
 813         * disassemble.c: Likewise.
 814         * disassemble.h: Likewise.
 815         * h8500-dis.c: Delete.
 816         * h8500-opc.h: Delete.
 817         * Makefile.in: Regenerate.
 818         * configure: Regenerate.
 819         * po/POTFILES.in: Regenerate.
 820
 821 2018-04-16  Alan Modra  <amodra@gmail.com>
 822
 823         * configure.ac: Remove tahoe support.
 824         * configure: Regenerate.
 825
 826 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 829         umwait.
 830         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 831         64-bit mode.
 832         * i386-tbl.h: Regenerated.
 833
 834 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 835
 836         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 837         PREFIX_MOD_1_0FAE_REG_6.
 838         (va_mode): New.
 839         (OP_E_register): Use va_mode.
 840         * i386-dis-evex.h (prefix_table):
 841         New instructions (see prefixes above).
 842         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 843         (cpu_flags): Likewise.
 844         * i386-opc.h (enum): Likewise.
 845         (i386_cpu_flags): Likewise.
 846         * i386-opc.tbl: Add umonitor, umwait, tpause.
 847         * i386-init.h: Regenerate.
 848         * i386-tbl.h: Likewise.
 849
 850 2018-04-11  Alan Modra  <amodra@gmail.com>
 851
 852         * opcodes/i860-dis.c: Delete.
 853         * opcodes/i960-dis.c: Delete.
 854         * Makefile.am: Remove i860 and i960 support.
 855         * configure.ac: Likewise.
 856         * disassemble.c: Likewise.
 857         * disassemble.h: Likewise.
 858         * Makefile.in: Regenerate.
 859         * configure: Regenerate.
 860         * po/POTFILES.in: Regenerate.
 861
 862 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         PR binutils/23025
 865         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 866         to 0.
 867         (print_insn): Clear vex instead of vex.evex.
 868
 869 2018-04-04  Nick Clifton  <nickc@redhat.com>
 870
 871         * po/es.po: Updated Spanish translation.
 872
 873 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-gen.c (opcode_modifiers): Delete VecESize.
 876         * i386-opc.h (VecESize): Delete.
 877         (struct i386_opcode_modifier): Delete vecesize.
 878         * i386-opc.tbl: Drop VecESize.
 879         * i386-tlb.h: Re-generate.
 880
 881 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 884         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 885         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 886         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 887         * i386-tlb.h: Re-generate.
 888
 889 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 892         Fold AVX512 forms
 893         * i386-tlb.h: Re-generate.
 894
 895 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 896
 897         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 898         (vex_len_table): Drop Y for vcvt*2si.
 899         (putop): Replace plain 'Y' handling by abort().
 900
 901 2018-03-28  Nick Clifton  <nickc@redhat.com>
 902
 903         PR 22988
 904         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 905         instructions with only a base address register.
 906         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 907         handle AARHC64_OPND_SVE_ADDR_R.
 908         (aarch64_print_operand): Likewise.
 909         * aarch64-asm-2.c: Regenerate.
 910         * aarch64_dis-2.c: Regenerate.
 911         * aarch64-opc-2.c: Regenerate.
 912
 913 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl: Drop VecESize from register only insn forms and
 916         memory forms not allowing broadcast.
 917         * i386-tlb.h: Re-generate.
 918
 919 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 922         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 923         sha256*): Drop Disp<N>.
 924
 925 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-dis.c (EbndS, bnd_swap_mode): New.
 928         (prefix_table): Use EbndS.
 929         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 930         * i386-opc.tbl (bndmov): Move misplaced Load.
 931         * i386-tlb.h: Re-generate.
 932
 933 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 936         templates allowing memory operands and folded ones for register
 937         only flavors.
 938         * i386-tlb.h: Re-generate.
 939
 940 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 943         256-bit templates. Drop redundant leftover Disp<N>.
 944         * i386-tlb.h: Re-generate.
 945
 946 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 947
 948         * riscv-opc.c (riscv_insn_types): New.
 949
 950 2018-03-13  Nick Clifton  <nickc@redhat.com>
 951
 952         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 953
 954 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 955
 956         * i386-opc.tbl: Add Optimize to clr.
 957         * i386-tbl.h: Regenerated.
 958
 959 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 960
 961         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 962         * i386-opc.h (OldGcc): Removed.
 963         (i386_opcode_modifier): Remove oldgcc.
 964         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 965         instructions for old (<= 2.8.1) versions of gcc.
 966         * i386-tbl.h: Regenerated.
 967
 968 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-opc.h (EVEXDYN): New.
 971         * i386-opc.tbl: Fold various AVX512VL templates.
 972         * i386-tlb.h: Re-generate.
 973
 974 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 977         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 978         vpexpandd, vpexpandq): Fold AFX512VF templates.
 979         * i386-tlb.h: Re-generate.
 980
 981 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 982
 983         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 984         Fold 128- and 256-bit VEX-encoded templates.
 985         * i386-tlb.h: Re-generate.
 986
 987 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 990         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 991         vpexpandd, vpexpandq): Fold AVX512F templates.
 992         * i386-tlb.h: Re-generate.
 993
 994 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 997         64-bit templates. Drop Disp<N>.
 998         * i386-tlb.h: Re-generate.
 999
1000 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1003         and 256-bit templates.
1004         * i386-tlb.h: Re-generate.
1005
1006 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1009         * i386-tlb.h: Re-generate.
1010
1011 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1014         Drop NoAVX.
1015         * i386-tlb.h: Re-generate.
1016
1017 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1020         * i386-tlb.h: Re-generate.
1021
1022 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1023
1024         * i386-gen.c (opcode_modifiers): Delete FloatD.
1025         * i386-opc.h (FloatD): Delete.
1026         (struct i386_opcode_modifier): Delete floatd.
1027         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1028         FloatD by D.
1029         * i386-tlb.h: Re-generate.
1030
1031 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1034
1035 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1038         * i386-tlb.h: Re-generate.
1039
1040 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1043         forms.
1044         * i386-tlb.h: Re-generate.
1045
1046 2018-03-07  Alan Modra  <amodra@gmail.com>
1047
1048         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1049         bfd_arch_rs6000.
1050         * disassemble.h (print_insn_rs6000): Delete.
1051         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1052         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1053         (print_insn_rs6000): Delete.
1054
1055 2018-03-03  Alan Modra  <amodra@gmail.com>
1056
1057         * sysdep.h (opcodes_error_handler): Define.
1058         (_bfd_error_handler): Declare.
1059         * Makefile.am: Remove stray #.
1060         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1061         EDIT" comment.
1062         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1063         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1064         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1065         opcodes_error_handler to print errors.  Standardize error messages.
1066         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1067         and include opintl.h.
1068         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1069         * i386-gen.c: Standardize error messages.
1070         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1071         * Makefile.in: Regenerate.
1072         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1073         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1074         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1075         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1076         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1077         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1078         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1079         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1080         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1081         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1082         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1083         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1084         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1085
1086 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1087
1088         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1089         vpsub[bwdq] instructions.
1090         * i386-tbl.h: Regenerated.
1091
1092 2018-03-01  Alan Modra  <amodra@gmail.com>
1093
1094         * configure.ac (ALL_LINGUAS): Sort.
1095         * configure: Regenerate.
1096
1097 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1098
1099         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1100         macro by assignements.
1101
1102 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         PR gas/22871
1105         * i386-gen.c (opcode_modifiers): Add Optimize.
1106         * i386-opc.h (Optimize): New enum.
1107         (i386_opcode_modifier): Add optimize.
1108         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1109         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1110         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1111         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1112         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1113         vpxord and vpxorq.
1114         * i386-tbl.h: Regenerated.
1115
1116 2018-02-26  Alan Modra  <amodra@gmail.com>
1117
1118         * crx-dis.c (getregliststring): Allocate a large enough buffer
1119         to silence false positive gcc8 warning.
1120
1121 2018-02-22  Shea Levy <shea@shealevy.com>
1122
1123         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1124
1125 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         * i386-opc.tbl: Add {rex},
1128         * i386-tbl.h: Regenerated.
1129
1130 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1131
1132         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1133         (mips16_opcodes): Replace `M' with `m' for "restore".
1134
1135 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1136
1137         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1138
1139 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1140
1141         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1142         variable to `function_index'.
1143
1144 2018-02-13  Nick Clifton  <nickc@redhat.com>
1145
1146         PR 22823
1147         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1148         about truncation of printing.
1149
1150 2018-02-12  Henry Wong <henry@stuffedcow.net>
1151
1152         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1153
1154 2018-02-05  Nick Clifton  <nickc@redhat.com>
1155
1156         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1157
1158 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1159
1160         * i386-dis.c (enum): Add pconfig.
1161         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1162         (cpu_flags): Add CpuPCONFIG.
1163         * i386-opc.h (enum): Add CpuPCONFIG.
1164         (i386_cpu_flags): Add cpupconfig.
1165         * i386-opc.tbl: Add PCONFIG instruction.
1166         * i386-init.h: Regenerate.
1167         * i386-tbl.h: Likewise.
1168
1169 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1170
1171         * i386-dis.c (enum): Add PREFIX_0F09.
1172         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1173         (cpu_flags): Add CpuWBNOINVD.
1174         * i386-opc.h (enum): Add CpuWBNOINVD.
1175         (i386_cpu_flags): Add cpuwbnoinvd.
1176         * i386-opc.tbl: Add WBNOINVD instruction.
1177         * i386-init.h: Regenerate.
1178         * i386-tbl.h: Likewise.
1179
1180 2018-01-17  Jim Wilson  <jimw@sifive.com>
1181
1182         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1183
1184 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1185
1186         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1187         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1188         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1189         (cpu_flags): Add CpuIBT, CpuSHSTK.
1190         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1191         (i386_cpu_flags): Add cpuibt, cpushstk.
1192         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1193         * i386-init.h: Regenerate.
1194         * i386-tbl.h: Likewise.
1195
1196 2018-01-16  Nick Clifton  <nickc@redhat.com>
1197
1198         * po/pt_BR.po: Updated Brazilian Portugese translation.
1199         * po/de.po: Updated German translation.
1200
1201 2018-01-15  Jim Wilson  <jimw@sifive.com>
1202
1203         * riscv-opc.c (match_c_nop): New.
1204         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1205
1206 2018-01-15  Nick Clifton  <nickc@redhat.com>
1207
1208         * po/uk.po: Updated Ukranian translation.
1209
1210 2018-01-13  Nick Clifton  <nickc@redhat.com>
1211
1212         * po/opcodes.pot: Regenerated.
1213
1214 2018-01-13  Nick Clifton  <nickc@redhat.com>
1215
1216         * configure: Regenerate.
1217
1218 2018-01-13  Nick Clifton  <nickc@redhat.com>
1219
1220         2.30 branch created.
1221
1222 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1223
1224         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1225         * i386-tbl.h: Regenerate.
1226
1227 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1230         * i386-tbl.h: Re-generate.
1231
1232 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1233
1234         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1235         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1236         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1237         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1238         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1239         Disp8MemShift of AVX512VL forms.
1240         * i386-tbl.h: Re-generate.
1241
1242 2018-01-09  Jim Wilson  <jimw@sifive.com>
1243
1244         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1245         then the hi_addr value is zero.
1246
1247 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1248
1249         * arm-dis.c (arm_opcodes): Add csdb.
1250         (thumb32_opcodes): Add csdb.
1251
1252 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1253
1254         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1255         * aarch64-asm-2.c: Regenerate.
1256         * aarch64-dis-2.c: Regenerate.
1257         * aarch64-opc-2.c: Regenerate.
1258
1259 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1260
1261         PR gas/22681
1262         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1263         Remove AVX512 vmovd with 64-bit operands.
1264         * i386-tbl.h: Regenerated.
1265
1266 2018-01-05  Jim Wilson  <jimw@sifive.com>
1267
1268         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1269         jalr.
1270
1271 2018-01-03  Alan Modra  <amodra@gmail.com>
1272
1273         Update year range in copyright notice of all files.
1274
1275 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1276
1277         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1278         and OPERAND_TYPE_REGZMM entries.
1279
1280 For older changes see ChangeLog-2017
1281 \f
1282 Copyright (C) 2018 Free Software Foundation, Inc.
1283
1284 Copying and distribution of this file, with or without modification,
1285 are permitted in any medium without royalty provided the copyright
1286 notice and this notice are preserved.
1287
1288 Local Variables:
1289 mode: change-log
1290 left-margin: 8
1291 fill-column: 74
1292 version-control: never
1293 End: