opcodes/ChangeLog

   1 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
   2
   3         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
   4
   5 2021-05-25  Alan Modra  <amodra@gmail.com>
   6
   7         * cris-desc.c: Regenerate.
   8         * cris-desc.h: Regenerate.
   9         * cris-opc.h: Regenerate.
  10         * po/POTFILES.in: Regenerate.
  11
  12 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  13
  14         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  15         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  16         (CGEN_CPUS): Add cris.
  17         (CRIS_DEPS): Define.
  18         (stamp-cris): New rule.
  19         * cgen.sh: Handle desc action.
  20         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  21         * Makefile.in, configure: Regenerate.
  22
  23 2021-05-18  Job Noorman  <mtvec@pm.me>
  24
  25         PR 27814
  26         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  27         the elf objects.
  28
  29 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  30
  31         * arm-dis.c (mve_opcodes): Fix disassembly of
  32         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  33         (is_mve_encoding_conflict): MVE vector loads should not match
  34         when P = W = 0.
  35         (is_mve_unpredictable): It's not unpredictable to use the same
  36         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  37
  38 2021-05-11  Nick Clifton  <nickc@redhat.com>
  39
  40         PR 27840
  41         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  42         the end of the code buffer.
  43
  44 2021-05-06  Stafford Horne  <shorne@gmail.com>
  45
  46         PR 21464
  47         * or1k-asm.c: Regenerate.
  48
  49 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  50
  51         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  52         info->insn_info_valid.
  53
  54 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl (lea): Add Optimize.
  57         * opcodes/i386-tbl.h: Re-generate.
  58
  59 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  60
  61         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  62         of l32r fetch and display referenced literal value.
  63
  64 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  65
  66         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  67         to 4 for literal disassembly.
  68
  69 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  70
  71         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  72         for TLBI instruction.
  73
  74 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  75
  76         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  77         DC instruction.
  78
  79 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  80
  81         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  82         "qualifier".
  83         (convert_mov_to_movewide): Add initializer for "value".
  84
  85 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  86
  87         * aarch64-opc.c: Add RME system registers.
  88
  89 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  90
  91         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  92         "addi d,CV,z" to "c.mv d,CV".
  93
  94 2021-04-12  Alan Modra  <amodra@gmail.com>
  95
  96         * configure.ac (--enable-checking): Add support.
  97         * config.in: Regenerate.
  98         * configure: Regenerate.
  99
 100 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 101
 102         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 103         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 104
 105 2021-04-09  Alan Modra  <amodra@gmail.com>
 106
 107         * ppc-dis.c (struct dis_private): Add "special".
 108         (POWERPC_DIALECT): Delete.  Replace uses with..
 109         (private_data): ..this.  New inline function.
 110         (disassemble_init_powerpc): Init "special" names.
 111         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 112         field of prefix instructions.
 113         (bsearch_reloc, print_got_plt): New functions.
 114         (print_insn_powerpc): For pcrel instructions, print target address
 115         and symbol if known, and decode plt and got loads too.
 116
 117 2021-04-08  Alan Modra  <amodra@gmail.com>
 118
 119         PR 27684
 120         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 121
 122 2021-04-08  Alan Modra  <amodra@gmail.com>
 123
 124         PR 27676
 125         * ppc-opc.c (DCBT_EO): Move earlier.
 126         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 127         (powerpc_operands): Add THCT and THDS entries.
 128         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 129
 130 2021-04-06  Alan Modra  <amodra@gmail.com>
 131
 132         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 133         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 134         symbol_at_address_func.
 135
 136 2021-04-05  Alan Modra  <amodra@gmail.com>
 137
 138         * configure.ac: Don't check for limits.h, string.h, strings.h or
 139         stdlib.h.
 140         (AC_ISC_POSIX): Don't invoke.
 141         * sysdep.h: Include stdlib.h and string.h unconditionally.
 142         * i386-opc.h: Include limits.h unconditionally.
 143         * wasm32-dis.c: Likewise.
 144         * cgen-opc.c: Don't include alloca-conf.h.
 145         * config.in: Regenerate.
 146         * configure: Regenerate.
 147
 148 2021-04-01  Martin Liska  <mliska@suse.cz>
 149
 150         * arm-dis.c (strneq): Remove strneq and use startswith.
 151         * cr16-dis.c (print_insn_cr16): Likewise.
 152         * score-dis.c (streq): Likewise.
 153         (strneq): Likewise.
 154         * score7-dis.c (strneq): Likewise.
 155
 156 2021-04-01  Alan Modra  <amodra@gmail.com>
 157
 158         PR 27675
 159         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 160
 161 2021-03-31  Alan Modra  <amodra@gmail.com>
 162
 163         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 164         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 165         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 166         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 167         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 168         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 169         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 170         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 171         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 172         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 173         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 174         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 175         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 176         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 177         and TRUE with true throughout.
 178
 179 2021-03-31  Alan Modra  <amodra@gmail.com>
 180
 181         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 182         * aarch64-dis.h: Likewise.
 183         * aarch64-opc.c: Likewise.
 184         * avr-dis.c: Likewise.
 185         * csky-dis.c: Likewise.
 186         * nds32-asm.c: Likewise.
 187         * nds32-dis.c: Likewise.
 188         * nfp-dis.c: Likewise.
 189         * riscv-dis.c: Likewise.
 190         * s12z-dis.c: Likewise.
 191         * wasm32-dis.c: Likewise.
 192
 193 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 196         (i386_seg_prefixes): New.
 197         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 198         (i386_seg_prefixes): Declare.
 199
 200 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 203
 204 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 207         * i386-reg.tbl (st): Move down.
 208         (st(0)): Delete. Extend comment.
 209         * i386-tbl.h: Re-generate.
 210
 211 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 214         (cmpsd): Move next to cmps.
 215         (movsd): Move next to movs.
 216         (cmpxchg16b): Move to separate section.
 217         (fisttp, fisttpll): Likewise.
 218         (monitor, mwait): Likewise.
 219         * i386-tbl.h: Re-generate.
 220
 221 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 224         (vpsadbw): Add C.
 225         * i386-tbl.h: Re-generate.
 226
 227 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 230         pclmul, gfni): New templates. Use them wherever possible. Move
 231         SSE4.1 pextrw into respective section.
 232         * i386-tbl.h: Re-generate.
 233
 234 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 237         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 238         "length".
 239         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 240         Convert all of their uses to representation in opcode.
 241
 242 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 245         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 246         value of None. Shrink operands to 3 bits.
 247
 248 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-gen.c (process_i386_opcode_modifier): New parameter
 251         "space".
 252         (output_i386_opcode): New local variable "space". Adjust
 253         process_i386_opcode_modifier() invocation.
 254         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 255         invocation.
 256         * i386-tbl.h: Re-generate.
 257
 258 2021-03-29  Alan Modra  <amodra@gmail.com>
 259
 260         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 261         (fp_qualifier_p, get_data_pattern): Likewise.
 262         (aarch64_get_operand_modifier_from_value): Likewise.
 263         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 264         (operand_variant_qualifier_p): Likewise.
 265         (qualifier_value_in_range_constraint_p): Likewise.
 266         (aarch64_get_qualifier_esize): Likewise.
 267         (aarch64_get_qualifier_nelem): Likewise.
 268         (aarch64_get_qualifier_standard_value): Likewise.
 269         (get_lower_bound, get_upper_bound): Likewise.
 270         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 271         (aarch64_print_operand): Likewise.
 272         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 273         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 274         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 275         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 276         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 277         (print_insn_tic6x): Likewise.
 278
 279 2021-03-29  Alan Modra  <amodra@gmail.com>
 280
 281         * arc-dis.c (extract_operand_value): Correct NULL cast.
 282         * frv-opc.h: Regenerate.
 283
 284 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 287         MMX form.
 288         * i386-tbl.h: Re-generate.
 289
 290 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 291
 292         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 293         immediate in br.n instruction.
 294
 295 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-dis.c (XMGatherD, VexGatherD): New.
 298         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 299         (print_insn): Check masking for S/G insns.
 300         (OP_E_memory): New local variable check_gather. Extend mandatory
 301         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 302         Extend check for disallowed 16-bit addressing.
 303         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 304         if()s to switch(). Check register conflicts for (VEX-encoded)
 305         gathers. Drop no longer reachable cases.
 306         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 307         vgatherdp*.
 308
 309 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 312         zeroing-masking without masking.
 313
 314 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 317         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 318         single-operand forms as deprecated.
 319         * i386-tbl.h: Re-generate.
 320
 321 2021-03-25  Alan Modra  <amodra@gmail.com>
 322
 323         PR 27647
 324         * ppc-opc.c (XLOCB_MASK): Delete.
 325         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 326         XLBH_MASK.
 327         (powerpc_opcodes): Accept a BH field on all extended forms of
 328         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 329
 330 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-gen.c (output_i386_opcode): Drop processing of
 333         opcode_length. Calculate length from base_opcode. Adjust prefix
 334         encoding determination.
 335         (process_i386_opcodes): Drop output of fake opcode_length.
 336         * i386-opc.h (struct insn_template): Drop opcode_length field.
 337         * i386-opc.tbl: Drop opcode length field from all templates.
 338         * i386-tbl.h: Re-generate.
 339
 340 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 343         parameter "prefix". Drop local variable "regular_encoding".
 344         Record prefix setting / check for consistency.
 345         (output_i386_opcode): Parse opcode_length and base_opcode
 346         earlier. Derive prefix encoding. Drop no longer applicable
 347         consistency checking. Adjust process_i386_opcode_modifier()
 348         invocation.
 349         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 350         invocation.
 351         * i386-tbl.h: Re-generate.
 352
 353 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 356         check.
 357         * i386-opc.h (Prefix_*): Move #define-s.
 358         * i386-opc.tbl: Move pseudo prefix enumerator values to
 359         extension opcode field. Introduce pseudopfx template.
 360         * i386-tbl.h: Re-generate.
 361
 362 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 365         comment.
 366         * i386-tbl.h: Re-generate.
 367
 368 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-opc.h (struct insn_template): Move cpu_flags field past
 371         opcode_modifier one.
 372         * i386-tbl.h: Re-generate.
 373
 374 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 377         * i386-opc.h (OpcodeSpace): New enumerator.
 378         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 379         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 380         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 381         (struct i386_opcode_modifier): New field opcodespace. Shrink
 382         opcodeprefix field.
 383         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 384         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 385         OpcodePrefix uses.
 386         * i386-tbl.h: Re-generate.
 387
 388 2021-03-22  Martin Liska  <mliska@suse.cz>
 389
 390         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 391         * arc-dis.c (parse_option): Likewise.
 392         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 393         * cris-dis.c (print_with_operands): Likewise.
 394         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 395         * i386-dis.c (print_insn): Likewise.
 396         * ia64-gen.c (fetch_insn_class): Likewise.
 397         (parse_resource_users): Likewise.
 398         (in_iclass): Likewise.
 399         (lookup_specifier): Likewise.
 400         (insert_opcode_dependencies): Likewise.
 401         * mips-dis.c (parse_mips_ase_option): Likewise.
 402         (parse_mips_dis_option): Likewise.
 403         * s390-dis.c (disassemble_init_s390): Likewise.
 404         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 405
 406 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 407
 408         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 409
 410 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 411
 412         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 413         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 414
 415 2021-03-12  Alan Modra  <amodra@gmail.com>
 416
 417         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 418
 419 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (OP_XMM): Re-order checks.
 422
 423 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-dis.c (putop): Drop need_vex check when also checking
 426         vex.evex.
 427         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 428         checking vex.b.
 429
 430 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 433         checks. Move case label past broadcast check.
 434
 435 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 436
 437         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 438         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 439         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 440         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 441         EVEX_W_0F38C7_M_0_L_2): Delete.
 442         (REG_EVEX_0F38C7_M_0_L_2): New.
 443         (intel_operand_size): Handle VEX and EVEX the same for
 444         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 445         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 446         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 447         vex_vsib_q_w_d_mode uses.
 448         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 449         0F38A1, and 0F38A3 entries.
 450         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 451         entry.
 452         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 453         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 454         0F38A3 entries.
 455
 456 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 457
 458         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 459         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 460         MOD_VEX_0FXOP_09_12): Rename to ...
 461         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 462         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 463         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 464         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 465         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 466         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 467         (reg_table): Adjust comments.
 468         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 469         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 470         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 471         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 472         (vex_len_table): Adjust opcode 0A_12 entry.
 473         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 474         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 475         (rm_table): Move hreset entry.
 476
 477 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 478
 479         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 480         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 481         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 482         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 483         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 484         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 485         (get_valid_dis386): Also handle 512-bit vector length when
 486         vectoring into vex_len_table[].
 487         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 488         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 489         entries.
 490         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 491         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 492         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 493         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 494         entries.
 495
 496 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 497
 498         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 499         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 500         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 501         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 502         entries.
 503         * i386-dis-evex-len.h (evex_len_table): Likewise.
 504         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 505
 506 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 507
 508         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 509         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 510         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 511         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 512         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 513         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 514         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 515         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 516         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 517         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 518         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 519         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 520         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 521         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 522         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 523         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 524         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 525         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 526         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 527         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 528         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 529         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 530         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 531         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 532         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 533         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 534         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 535         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 536         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 537         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 538         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 539         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 540         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 541         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 542         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 543         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 544         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 545         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 546         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 547         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 548         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 549         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 550         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 551         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 552         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 553         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 554         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 555         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 556         EVEX_W_0F3A43_L_n): New.
 557         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 558         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 559         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 560         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 561         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 562         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 563         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 564         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 565         0F385B, 0F38C6, and 0F38C7 entries.
 566         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 567         0F38C6 and 0F38C7.
 568         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 569         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 570         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 571         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 572
 573 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 574
 575         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 576         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 577         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 578         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 579         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 580         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 581         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 582         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 583         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 584         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 585         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 586         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 587         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 588         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 589         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 590         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 591         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 592         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 593         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 594         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 595         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 596         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 597         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 598         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 599         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 600         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 601         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 602         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 603         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 604         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 605         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 606         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 607         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 608         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 609         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 610         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 611         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 612         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 613         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 614         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 615         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 616         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 617         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 618         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 619         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 620         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 621         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 622         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 623         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 624         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 625         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 626         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 627         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 628         VEX_W_0F99_P_2_LEN_0): Delete.
 629         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 630         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 631         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 632         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 633         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 634         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 635         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 636         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 637         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 638         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 639         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 640         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 641         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 642         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 643         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 644         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 645         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 646         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 647         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 648         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 649         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 650         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 651         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 652         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 653         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 654         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 655         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 656         (prefix_table): No longer link to vex_len_table[] for opcodes
 657         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 658         0F92, 0F93, 0F98, and 0F99.
 659         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 660         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 661         0F98, and 0F99.
 662         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 663         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 664         0F98, and 0F99.
 665         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 666         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 667         0F98, and 0F99.
 668         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 669         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 670         0F98, and 0F99.
 671
 672 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 673
 674         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 675         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 676         REG_VEX_0F73_M_0 respectively.
 677         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 678         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 679         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 680         MOD_VEX_0F73_REG_7): Delete.
 681         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 682         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 683         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 684         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 685         PREFIX_VEX_0F3AF0_L_0 respectively.
 686         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 687         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 688         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 689         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 690         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 691         VEX_LEN_0F38F7): New.
 692         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 693         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 694         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 695         0F38F3.
 696         (prefix_table): No longer link to vex_len_table[] for opcodes
 697         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 698         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 699         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 700         0F38F6, 0F38F7, and 0F3AF0.
 701         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 702         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 703         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 704         0F73.
 705
 706 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 707
 708         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 709         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 710         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 711         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 712         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 713         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 714         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 715         73.
 716         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 717         0F72, and 0F73.
 718         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 719         0F73.
 720
 721 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 722
 723         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 724         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 725         (reg_table): Don't link to mod_table[] where not needed. Add
 726         PREFIX_IGNORED to nop entries.
 727         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 728         (mod_table): Add nop entries next to prefetch ones. Drop
 729         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 730         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 731         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 732         PREFIX_OPCODE from endbr* entries.
 733         (get_valid_dis386): Also consider entry's name when zapping
 734         vindex.
 735         (print_insn): Handle PREFIX_IGNORED.
 736
 737 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 738
 739         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 740         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 741         element.
 742         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 743         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 744         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 745         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 746         (struct i386_opcode_modifier): Delete notrackprefixok,
 747         islockable, hleprefixok, and repprefixok fields. Add prefixok
 748         field.
 749         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 750         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 751         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 752         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 753         Replace HLEPrefixOk.
 754         * opcodes/i386-tbl.h: Re-generate.
 755
 756 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 757
 758         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 759         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 760         64-bit form.
 761         * opcodes/i386-tbl.h: Re-generate.
 762
 763 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 766         for {} instead of {0}. Don't look for '0'.
 767         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 768         size specifiers.
 769
 770 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 771
 772         PR 27158
 773         * riscv-dis.c (print_insn_args): Updated encoding macros.
 774         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 775         (match_c_addi16sp): Updated encoding macros.
 776         (match_c_lui): Likewise.
 777         (match_c_lui_with_hint): Likewise.
 778         (match_c_addi4spn): Likewise.
 779         (match_c_slli): Likewise.
 780         (match_slli_as_c_slli): Likewise.
 781         (match_c_slli64): Likewise.
 782         (match_srxi_as_c_srxi): Likewise.
 783         (riscv_insn_types): Added .insn css/cl/cs.
 784
 785 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 786
 787         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 788         (default_priv_spec): Updated type to riscv_spec_class.
 789         (parse_riscv_dis_option): Updated.
 790         * riscv-opc.c: Moved stuff and make the file tidy.
 791
 792 2021-02-17  Alan Modra  <amodra@gmail.com>
 793
 794         * wasm32-dis.c: Include limits.h.
 795         (CHAR_BIT): Provide backup define.
 796         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 797         Correct signed overflow checking.
 798
 799 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 802         * i386-tbl.h: Re-generate.
 803
 804 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 807         Oword.
 808         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 809
 810 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 811
 812         * s390-mkopc.c (main): Accept arch14 as cpu string.
 813         * s390-opc.txt: Add new arch14 instructions.
 814
 815 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 816
 817         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 818         favour of LIBINTL.
 819         * configure: Regenerated.
 820
 821 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 822
 823         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 824         * tic54x-opc.c (regs): Rename to ...
 825         (tic54x_regs): ... this.
 826         (mmregs): Rename to ...
 827         (tic54x_mmregs): ... this.
 828         (condition_codes): Rename to ...
 829         (tic54x_condition_codes): ... this.
 830         (cc2_codes): Rename to ...
 831         (tic54x_cc2_codes): ... this.
 832         (cc3_codes): Rename to ...
 833         (tic54x_cc3_codes): ... this.
 834         (status_bits): Rename to ...
 835         (tic54x_status_bits): ... this.
 836         (misc_symbols): Rename to ...
 837         (tic54x_misc_symbols): ... this.
 838
 839 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 840
 841         * riscv-opc.c (MASK_RVB_IMM): Removed.
 842         (riscv_opcodes): Removed zb* instructions.
 843         (riscv_ext_version_table): Removed versions for zb*.
 844
 845 2021-01-26  Alan Modra  <amodra@gmail.com>
 846
 847         * i386-gen.c (parse_template): Ensure entire template_instance
 848         is initialised.
 849
 850 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 851
 852         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 853         (riscv_fpr_names_abi): Likewise.
 854         (riscv_opcodes): Likewise.
 855         (riscv_insn_types): Likewise.
 856
 857 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 858
 859         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 860
 861 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 862
 863         * riscv-dis.c: Comments tidy and improvement.
 864         * riscv-opc.c: Likewise.
 865
 866 2021-01-13  Alan Modra  <amodra@gmail.com>
 867
 868         * Makefile.in: Regenerate.
 869
 870 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR binutils/26792
 873         * configure.ac: Use GNU_MAKE_JOBSERVER.
 874         * aclocal.m4: Regenerated.
 875         * configure: Likewise.
 876
 877 2021-01-12  Nick Clifton  <nickc@redhat.com>
 878
 879         * po/sr.po: Updated Serbian translation.
 880
 881 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         PR ld/27173
 884         * configure: Regenerated.
 885
 886 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 887
 888         * aarch64-asm-2.c: Regenerate.
 889         * aarch64-dis-2.c: Likewise.
 890         * aarch64-opc-2.c: Likewise.
 891         * aarch64-opc.c (aarch64_print_operand):
 892         Delete handling of AARCH64_OPND_CSRE_CSR.
 893         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 894         (CSRE): Likewise.
 895         (_CSRE_INSN): Likewise.
 896         (aarch64_opcode_table): Delete csr.
 897
 898 2021-01-11  Nick Clifton  <nickc@redhat.com>
 899
 900         * po/de.po: Updated German translation.
 901         * po/fr.po: Updated French translation.
 902         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 903         * po/sv.po: Updated Swedish translation.
 904         * po/uk.po: Updated Ukranian translation.
 905
 906 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         * configure: Regenerated.
 909
 910 2021-01-09  Nick Clifton  <nickc@redhat.com>
 911
 912         * configure: Regenerate.
 913         * po/opcodes.pot: Regenerate.
 914
 915 2021-01-09  Nick Clifton  <nickc@redhat.com>
 916
 917         * 2.36 release branch crated.
 918
 919 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 920
 921         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 922         (DW, (XRC_MASK): Define.
 923         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 924
 925 2021-01-09  Alan Modra  <amodra@gmail.com>
 926
 927         * configure: Regenerate.
 928
 929 2021-01-08  Nick Clifton  <nickc@redhat.com>
 930
 931         * po/sv.po: Updated Swedish translation.
 932
 933 2021-01-08  Nick Clifton  <nickc@redhat.com>
 934
 935         PR 27129
 936         * aarch64-dis.c (determine_disassembling_preference): Move call to
 937         aarch64_match_operands_constraint outside of the assertion.
 938         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 939         Replace with a return of FALSE.
 940
 941         PR 27139
 942         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 943         core system register.
 944
 945 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 946
 947         * configure: Regenerate.
 948
 949 2021-01-07  Nick Clifton  <nickc@redhat.com>
 950
 951         * po/fr.po: Updated French translation.
 952
 953 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 954
 955         * m68k-opc.c (chkl): Change minimum architecture requirement to
 956         m68020.
 957
 958 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 959
 960         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 961
 962 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 963             Jim Wilson  <jimw@sifive.com>
 964             Andrew Waterman  <andrew@sifive.com>
 965             Maxim Blinov  <maxim.blinov@embecosm.com>
 966             Kito Cheng  <kito.cheng@sifive.com>
 967             Nelson Chu  <nelson.chu@sifive.com>
 968
 969         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 970         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 971
 972 2021-01-01  Alan Modra  <amodra@gmail.com>
 973
 974         Update year range in copyright notice of all files.
 975
 976 For older changes see ChangeLog-2020
 977 \f
 978 Copyright (C) 2021 Free Software Foundation, Inc.
 979
 980 Copying and distribution of this file, with or without modification,
 981 are permitted in any medium without royalty provided the copyright
 982 notice and this notice are preserved.
 983
 984 Local Variables:
 985 mode: change-log
 986 left-margin: 8
 987 fill-column: 74
 988 version-control: never
 989 End: