opcodes/ChangeLog

   1 2018-06-26  Nick Clifton  <nickc@redhat.com>
   2
   3         * nfp-dis.c: Fix spelling mistake.
   4
   5 2018-06-24  Nick Clifton  <nickc@redhat.com>
   6
   7         * configure: Regenerate.
   8         * po/opcodes.pot: Regenerate.
   9
  10 2018-06-24  Nick Clifton  <nickc@redhat.com>
  11
  12         2.31 branch created.
  13
  14 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
  15
  16         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
  17         * aarch64-asm-2.c: Regenerate.
  18         * aarch64-dis-2.c: Likewise.
  19
  20 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
  21
  22         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
  23         `-M ginv' option description.
  24
  25 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  26
  27         PR gas/23305
  28         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
  29         la and lla.
  30
  31 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
  32
  33         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
  34         * configure.ac: Remove AC_PREREQ.
  35         * Makefile.in: Re-generate.
  36         * aclocal.m4: Re-generate.
  37         * configure: Re-generate.
  38
  39 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  40
  41         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
  42         mips64r6 descriptors.
  43         (parse_mips_ase_option): Handle -Mginv option.
  44         (print_mips_disassembler_options): Document -Mginv.
  45         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
  46         (GINV): New macro.
  47         (mips_opcodes): Define ginvi and ginvt.
  48
  49 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
  50             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  51
  52         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
  53         * mips-opc.c (CRC, CRC64): New macros.
  54         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
  55         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
  56         crc32cd for CRC64.
  57
  58 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
  59
  60         PR 20319
  61         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  62         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  63
  64 2018-06-06  Alan Modra  <amodra@gmail.com>
  65
  66         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
  67         setjmp.  Move init for some other vars later too.
  68
  69 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
  70
  71         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
  72         (dis_private): Add new fields for property section tracking.
  73         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
  74         (xtensa_instruction_fits): New functions.
  75         (fetch_data): Bump minimal fetch size to 4.
  76         (print_insn_xtensa): Make struct dis_private static.
  77         Load and prepare property table on section change.
  78         Don't disassemble literals. Don't disassemble instructions that
  79         cross property table boundaries.
  80
  81 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * configure: Regenerated.
  84
  85 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
  88         * i386-tbl.h: Re-generate.
  89
  90 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl (sldt, str): Add NoRex64.
  93         * i386-tbl.h: Re-generate.
  94
  95 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (invpcid): Add Oword.
  98         * i386-tbl.h: Re-generate.
  99
 100 2018-06-01  Alan Modra  <amodra@gmail.com>
 101
 102         * sysdep.h (_bfd_error_handler): Don't declare.
 103         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 104         * rl78-decode.opc: Likewise.
 105         * msp430-decode.c: Regenerate.
 106         * rl78-decode.c: Regenerate.
 107
 108 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 109
 110         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 111         * i386-init.h : Regenerated.
 112
 113 2018-05-25  Alan Modra  <amodra@gmail.com>
 114
 115         * Makefile.in: Regenerate.
 116         * po/POTFILES.in: Regenerate.
 117
 118 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 119
 120         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 121         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 122         (insert_bab, extract_bab, insert_btab, extract_btab,
 123         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 124         (BAT, BBA VBA RBS XB6S): Delete macros.
 125         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 126         (BB, BD, RBX, XC6): Update for new macros.
 127         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 128         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 129         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 130         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 131
 132 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 133
 134         * Makefile.am: Add support for s12z architecture.
 135         * configure.ac: Likewise.
 136         * disassemble.c: Likewise.
 137         * disassemble.h: Likewise.
 138         * Makefile.in: Regenerate.
 139         * configure: Regenerate.
 140         * s12z-dis.c: New file.
 141         * s12z.h: New file.
 142
 143 2018-05-18  Alan Modra  <amodra@gmail.com>
 144
 145         * nfp-dis.c: Don't #include libbfd.h.
 146         (init_nfp3200_priv): Use bfd_get_section_contents.
 147         (nit_nfp6000_mecsr_sec): Likewise.
 148
 149 2018-05-17  Nick Clifton  <nickc@redhat.com>
 150
 151         * po/zh_CN.po: Updated simplified Chinese translation.
 152
 153 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 154
 155         PR binutils/23109
 156         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 157         * aarch64-dis-2.c: Regenerate.
 158
 159 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 160
 161         PR binutils/21446
 162         * aarch64-asm.c (opintl.h): Include.
 163         (aarch64_ins_sysreg): Enforce read/write constraints.
 164         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 165         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 166         (F_REG_READ, F_REG_WRITE): New.
 167         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 168         AARCH64_OPND_SYSREG.
 169         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 170         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 171         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 172         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 173         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 174         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 175         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 176         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 177         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 178         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 179         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 180         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 181         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 182         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 183         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 184         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 185         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 186
 187 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 188
 189         PR binutils/21446
 190         * aarch64-dis.c (no_notes: New.
 191         (parse_aarch64_dis_option): Support notes.
 192         (aarch64_decode_insn, print_operands): Likewise.
 193         (print_aarch64_disassembler_options): Document notes.
 194         * aarch64-opc.c (aarch64_print_operand): Support notes.
 195
 196 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 197
 198         PR binutils/21446
 199         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 200         and take error struct.
 201         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 202         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 203         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 204         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 205         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 206         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 207         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 208         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 209         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 210         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 211         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 212         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 213         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 214         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 215         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 216         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 217         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 218         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 219         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 220         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 221         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 222         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 223         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 224         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 225         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 226         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 227         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 228         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 229         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 230         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 231         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 232         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 233         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 234         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 235         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 236         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 237         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 238         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 239         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 240         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 241         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 242         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 243         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 244         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 245         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 246         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 247         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 248         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 249         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 250         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 251         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 252         (determine_disassembling_preference, aarch64_decode_insn,
 253         print_insn_aarch64_word, print_insn_data): Take errors struct.
 254         (print_insn_aarch64): Use errors.
 255         * aarch64-asm-2.c: Regenerate.
 256         * aarch64-dis-2.c: Regenerate.
 257         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 258         boolean in aarch64_insert_operan.
 259         (print_operand_extractor): Likewise.
 260         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 261
 262 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 263
 264         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 265
 266 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 269
 270 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 271
 272         * cr16-opc.c (cr16_instruction): Comment typo fix.
 273         * hppa-dis.c (print_insn_hppa): Likewise.
 274
 275 2018-05-08  Jim Wilson  <jimw@sifive.com>
 276
 277         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 278         (match_c_slli64, match_srxi_as_c_srxi): New.
 279         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 280         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 281         <c.slli, c.srli, c.srai>: Use match_s_slli.
 282         <c.slli64, c.srli64, c.srai64>: New.
 283
 284 2018-05-08  Alan Modra  <amodra@gmail.com>
 285
 286         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 287         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 288         partition opcode space for index lookup.
 289
 290 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 291
 292         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 293         <insn_length>: ...with this.  Update usage.
 294         Remove duplicate call to *info->memory_error_func.
 295
 296 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 297             H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         * i386-dis.c (Gva): New.
 300         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 301         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 302         (prefix_table): New instructions (see prefix above).
 303         (mod_table): New instructions (see prefix above).
 304         (OP_G): Handle va_mode.
 305         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 306         CPU_MOVDIR64B_FLAGS.
 307         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 308         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 309         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 310         * i386-opc.tbl: Add movidir{i,64b}.
 311         * i386-init.h: Regenerated.
 312         * i386-tbl.h: Likewise.
 313
 314 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 315
 316         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 317         AddrPrefixOpReg.
 318         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 319         (AddrPrefixOpReg): This.
 320         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 321         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 322
 323 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 324
 325         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 326         (vle_num_opcodes): Likewise.
 327         (spe2_num_opcodes): Likewise.
 328         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 329         initialization loop.
 330         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 331         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 332         only once.
 333
 334 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 335
 336         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 337
 338 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 339
 340         Makefile.am: Added nfp-dis.c.
 341         configure.ac: Added bfd_nfp_arch.
 342         disassemble.h: Added print_insn_nfp prototype.
 343         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 344         nfp-dis.c: New, for NFP support.
 345         po/POTFILES.in: Added nfp-dis.c to the list.
 346         Makefile.in: Regenerate.
 347         configure: Regenerate.
 348
 349 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 352         templates into their base ones.
 353         * i386-tlb.h: Re-generate.
 354
 355 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 358         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 359         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 360         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 361         * i386-init.h: Re-generate.
 362
 363 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 366         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 367         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 368         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 369         comment.
 370         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 371         and CpuRegMask.
 372         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 373         CpuRegMask: Delete.
 374         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 375         cpuregzmm, and cpuregmask.
 376         * i386-init.h: Re-generate.
 377         * i386-tbl.h: Re-generate.
 378
 379 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 382         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 383         * i386-init.h: Re-generate.
 384
 385 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-gen.c (VexImmExt): Delete.
 388         * i386-opc.h (VexImmExt, veximmext): Delete.
 389         * i386-opc.tbl: Drop all VexImmExt uses.
 390         * i386-tlb.h: Re-generate.
 391
 392 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 395         register-only forms.
 396         * i386-tlb.h: Re-generate.
 397
 398 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 399
 400         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 401
 402 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 403
 404         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 405         PREFIX_0F1C.
 406         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 407         (cpu_flags): Add CpuCLDEMOTE.
 408         * i386-init.h: Regenerate.
 409         * i386-opc.h (enum): Add CpuCLDEMOTE,
 410         (i386_cpu_flags): Add cpucldemote.
 411         * i386-opc.tbl: Add cldemote.
 412         * i386-tbl.h: Regenerate.
 413
 414 2018-04-16  Alan Modra  <amodra@gmail.com>
 415
 416         * Makefile.am: Remove sh5 and sh64 support.
 417         * configure.ac: Likewise.
 418         * disassemble.c: Likewise.
 419         * disassemble.h: Likewise.
 420         * sh-dis.c: Likewise.
 421         * sh64-dis.c: Delete.
 422         * sh64-opc.c: Delete.
 423         * sh64-opc.h: Delete.
 424         * Makefile.in: Regenerate.
 425         * configure: Regenerate.
 426         * po/POTFILES.in: Regenerate.
 427
 428 2018-04-16  Alan Modra  <amodra@gmail.com>
 429
 430         * Makefile.am: Remove w65 support.
 431         * configure.ac: Likewise.
 432         * disassemble.c: Likewise.
 433         * disassemble.h: Likewise.
 434         * w65-dis.c: Delete.
 435         * w65-opc.h: Delete.
 436         * Makefile.in: Regenerate.
 437         * configure: Regenerate.
 438         * po/POTFILES.in: Regenerate.
 439
 440 2018-04-16  Alan Modra  <amodra@gmail.com>
 441
 442         * configure.ac: Remove we32k support.
 443         * configure: Regenerate.
 444
 445 2018-04-16  Alan Modra  <amodra@gmail.com>
 446
 447         * Makefile.am: Remove m88k support.
 448         * configure.ac: Likewise.
 449         * disassemble.c: Likewise.
 450         * disassemble.h: Likewise.
 451         * m88k-dis.c: Delete.
 452         * Makefile.in: Regenerate.
 453         * configure: Regenerate.
 454         * po/POTFILES.in: Regenerate.
 455
 456 2018-04-16  Alan Modra  <amodra@gmail.com>
 457
 458         * Makefile.am: Remove i370 support.
 459         * configure.ac: Likewise.
 460         * disassemble.c: Likewise.
 461         * disassemble.h: Likewise.
 462         * i370-dis.c: Delete.
 463         * i370-opc.c: Delete.
 464         * Makefile.in: Regenerate.
 465         * configure: Regenerate.
 466         * po/POTFILES.in: Regenerate.
 467
 468 2018-04-16  Alan Modra  <amodra@gmail.com>
 469
 470         * Makefile.am: Remove h8500 support.
 471         * configure.ac: Likewise.
 472         * disassemble.c: Likewise.
 473         * disassemble.h: Likewise.
 474         * h8500-dis.c: Delete.
 475         * h8500-opc.h: Delete.
 476         * Makefile.in: Regenerate.
 477         * configure: Regenerate.
 478         * po/POTFILES.in: Regenerate.
 479
 480 2018-04-16  Alan Modra  <amodra@gmail.com>
 481
 482         * configure.ac: Remove tahoe support.
 483         * configure: Regenerate.
 484
 485 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 488         umwait.
 489         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 490         64-bit mode.
 491         * i386-tbl.h: Regenerated.
 492
 493 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 494
 495         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 496         PREFIX_MOD_1_0FAE_REG_6.
 497         (va_mode): New.
 498         (OP_E_register): Use va_mode.
 499         * i386-dis-evex.h (prefix_table):
 500         New instructions (see prefixes above).
 501         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 502         (cpu_flags): Likewise.
 503         * i386-opc.h (enum): Likewise.
 504         (i386_cpu_flags): Likewise.
 505         * i386-opc.tbl: Add umonitor, umwait, tpause.
 506         * i386-init.h: Regenerate.
 507         * i386-tbl.h: Likewise.
 508
 509 2018-04-11  Alan Modra  <amodra@gmail.com>
 510
 511         * opcodes/i860-dis.c: Delete.
 512         * opcodes/i960-dis.c: Delete.
 513         * Makefile.am: Remove i860 and i960 support.
 514         * configure.ac: Likewise.
 515         * disassemble.c: Likewise.
 516         * disassemble.h: Likewise.
 517         * Makefile.in: Regenerate.
 518         * configure: Regenerate.
 519         * po/POTFILES.in: Regenerate.
 520
 521 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         PR binutils/23025
 524         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 525         to 0.
 526         (print_insn): Clear vex instead of vex.evex.
 527
 528 2018-04-04  Nick Clifton  <nickc@redhat.com>
 529
 530         * po/es.po: Updated Spanish translation.
 531
 532 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-gen.c (opcode_modifiers): Delete VecESize.
 535         * i386-opc.h (VecESize): Delete.
 536         (struct i386_opcode_modifier): Delete vecesize.
 537         * i386-opc.tbl: Drop VecESize.
 538         * i386-tlb.h: Re-generate.
 539
 540 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 541
 542         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 543         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 544         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 545         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 546         * i386-tlb.h: Re-generate.
 547
 548 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 551         Fold AVX512 forms
 552         * i386-tlb.h: Re-generate.
 553
 554 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 557         (vex_len_table): Drop Y for vcvt*2si.
 558         (putop): Replace plain 'Y' handling by abort().
 559
 560 2018-03-28  Nick Clifton  <nickc@redhat.com>
 561
 562         PR 22988
 563         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 564         instructions with only a base address register.
 565         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 566         handle AARHC64_OPND_SVE_ADDR_R.
 567         (aarch64_print_operand): Likewise.
 568         * aarch64-asm-2.c: Regenerate.
 569         * aarch64_dis-2.c: Regenerate.
 570         * aarch64-opc-2.c: Regenerate.
 571
 572 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-opc.tbl: Drop VecESize from register only insn forms and
 575         memory forms not allowing broadcast.
 576         * i386-tlb.h: Re-generate.
 577
 578 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 581         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 582         sha256*): Drop Disp<N>.
 583
 584 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-dis.c (EbndS, bnd_swap_mode): New.
 587         (prefix_table): Use EbndS.
 588         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 589         * i386-opc.tbl (bndmov): Move misplaced Load.
 590         * i386-tlb.h: Re-generate.
 591
 592 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 595         templates allowing memory operands and folded ones for register
 596         only flavors.
 597         * i386-tlb.h: Re-generate.
 598
 599 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 602         256-bit templates. Drop redundant leftover Disp<N>.
 603         * i386-tlb.h: Re-generate.
 604
 605 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 606
 607         * riscv-opc.c (riscv_insn_types): New.
 608
 609 2018-03-13  Nick Clifton  <nickc@redhat.com>
 610
 611         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 612
 613 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 614
 615         * i386-opc.tbl: Add Optimize to clr.
 616         * i386-tbl.h: Regenerated.
 617
 618 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 621         * i386-opc.h (OldGcc): Removed.
 622         (i386_opcode_modifier): Remove oldgcc.
 623         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 624         instructions for old (<= 2.8.1) versions of gcc.
 625         * i386-tbl.h: Regenerated.
 626
 627 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.h (EVEXDYN): New.
 630         * i386-opc.tbl: Fold various AVX512VL templates.
 631         * i386-tlb.h: Re-generate.
 632
 633 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 636         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 637         vpexpandd, vpexpandq): Fold AFX512VF templates.
 638         * i386-tlb.h: Re-generate.
 639
 640 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 643         Fold 128- and 256-bit VEX-encoded templates.
 644         * i386-tlb.h: Re-generate.
 645
 646 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 649         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 650         vpexpandd, vpexpandq): Fold AVX512F templates.
 651         * i386-tlb.h: Re-generate.
 652
 653 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 654
 655         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 656         64-bit templates. Drop Disp<N>.
 657         * i386-tlb.h: Re-generate.
 658
 659 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 662         and 256-bit templates.
 663         * i386-tlb.h: Re-generate.
 664
 665 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 668         * i386-tlb.h: Re-generate.
 669
 670 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 673         Drop NoAVX.
 674         * i386-tlb.h: Re-generate.
 675
 676 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 679         * i386-tlb.h: Re-generate.
 680
 681 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-gen.c (opcode_modifiers): Delete FloatD.
 684         * i386-opc.h (FloatD): Delete.
 685         (struct i386_opcode_modifier): Delete floatd.
 686         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 687         FloatD by D.
 688         * i386-tlb.h: Re-generate.
 689
 690 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 693
 694 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 695
 696         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 697         * i386-tlb.h: Re-generate.
 698
 699 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 700
 701         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 702         forms.
 703         * i386-tlb.h: Re-generate.
 704
 705 2018-03-07  Alan Modra  <amodra@gmail.com>
 706
 707         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 708         bfd_arch_rs6000.
 709         * disassemble.h (print_insn_rs6000): Delete.
 710         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 711         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 712         (print_insn_rs6000): Delete.
 713
 714 2018-03-03  Alan Modra  <amodra@gmail.com>
 715
 716         * sysdep.h (opcodes_error_handler): Define.
 717         (_bfd_error_handler): Declare.
 718         * Makefile.am: Remove stray #.
 719         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 720         EDIT" comment.
 721         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 722         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 723         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 724         opcodes_error_handler to print errors.  Standardize error messages.
 725         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 726         and include opintl.h.
 727         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 728         * i386-gen.c: Standardize error messages.
 729         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 730         * Makefile.in: Regenerate.
 731         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 732         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 733         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 734         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 735         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 736         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 737         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 738         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 739         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 740         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 741         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 742         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 743         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 744
 745 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 746
 747         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 748         vpsub[bwdq] instructions.
 749         * i386-tbl.h: Regenerated.
 750
 751 2018-03-01  Alan Modra  <amodra@gmail.com>
 752
 753         * configure.ac (ALL_LINGUAS): Sort.
 754         * configure: Regenerate.
 755
 756 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 757
 758         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 759         macro by assignements.
 760
 761 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         PR gas/22871
 764         * i386-gen.c (opcode_modifiers): Add Optimize.
 765         * i386-opc.h (Optimize): New enum.
 766         (i386_opcode_modifier): Add optimize.
 767         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 768         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 769         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 770         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 771         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 772         vpxord and vpxorq.
 773         * i386-tbl.h: Regenerated.
 774
 775 2018-02-26  Alan Modra  <amodra@gmail.com>
 776
 777         * crx-dis.c (getregliststring): Allocate a large enough buffer
 778         to silence false positive gcc8 warning.
 779
 780 2018-02-22  Shea Levy <shea@shealevy.com>
 781
 782         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 783
 784 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         * i386-opc.tbl: Add {rex},
 787         * i386-tbl.h: Regenerated.
 788
 789 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 790
 791         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 792         (mips16_opcodes): Replace `M' with `m' for "restore".
 793
 794 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 795
 796         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 797
 798 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 799
 800         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 801         variable to `function_index'.
 802
 803 2018-02-13  Nick Clifton  <nickc@redhat.com>
 804
 805         PR 22823
 806         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 807         about truncation of printing.
 808
 809 2018-02-12  Henry Wong <henry@stuffedcow.net>
 810
 811         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 812
 813 2018-02-05  Nick Clifton  <nickc@redhat.com>
 814
 815         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 816
 817 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 818
 819         * i386-dis.c (enum): Add pconfig.
 820         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 821         (cpu_flags): Add CpuPCONFIG.
 822         * i386-opc.h (enum): Add CpuPCONFIG.
 823         (i386_cpu_flags): Add cpupconfig.
 824         * i386-opc.tbl: Add PCONFIG instruction.
 825         * i386-init.h: Regenerate.
 826         * i386-tbl.h: Likewise.
 827
 828 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 829
 830         * i386-dis.c (enum): Add PREFIX_0F09.
 831         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 832         (cpu_flags): Add CpuWBNOINVD.
 833         * i386-opc.h (enum): Add CpuWBNOINVD.
 834         (i386_cpu_flags): Add cpuwbnoinvd.
 835         * i386-opc.tbl: Add WBNOINVD instruction.
 836         * i386-init.h: Regenerate.
 837         * i386-tbl.h: Likewise.
 838
 839 2018-01-17  Jim Wilson  <jimw@sifive.com>
 840
 841         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 842
 843 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 844
 845         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 846         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 847         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 848         (cpu_flags): Add CpuIBT, CpuSHSTK.
 849         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 850         (i386_cpu_flags): Add cpuibt, cpushstk.
 851         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 852         * i386-init.h: Regenerate.
 853         * i386-tbl.h: Likewise.
 854
 855 2018-01-16  Nick Clifton  <nickc@redhat.com>
 856
 857         * po/pt_BR.po: Updated Brazilian Portugese translation.
 858         * po/de.po: Updated German translation.
 859
 860 2018-01-15  Jim Wilson  <jimw@sifive.com>
 861
 862         * riscv-opc.c (match_c_nop): New.
 863         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 864
 865 2018-01-15  Nick Clifton  <nickc@redhat.com>
 866
 867         * po/uk.po: Updated Ukranian translation.
 868
 869 2018-01-13  Nick Clifton  <nickc@redhat.com>
 870
 871         * po/opcodes.pot: Regenerated.
 872
 873 2018-01-13  Nick Clifton  <nickc@redhat.com>
 874
 875         * configure: Regenerate.
 876
 877 2018-01-13  Nick Clifton  <nickc@redhat.com>
 878
 879         2.30 branch created.
 880
 881 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 882
 883         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 884         * i386-tbl.h: Regenerate.
 885
 886 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 889         * i386-tbl.h: Re-generate.
 890
 891 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 894         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 895         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 896         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 897         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 898         Disp8MemShift of AVX512VL forms.
 899         * i386-tbl.h: Re-generate.
 900
 901 2018-01-09  Jim Wilson  <jimw@sifive.com>
 902
 903         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 904         then the hi_addr value is zero.
 905
 906 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 907
 908         * arm-dis.c (arm_opcodes): Add csdb.
 909         (thumb32_opcodes): Add csdb.
 910
 911 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 912
 913         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 914         * aarch64-asm-2.c: Regenerate.
 915         * aarch64-dis-2.c: Regenerate.
 916         * aarch64-opc-2.c: Regenerate.
 917
 918 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 919
 920         PR gas/22681
 921         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 922         Remove AVX512 vmovd with 64-bit operands.
 923         * i386-tbl.h: Regenerated.
 924
 925 2018-01-05  Jim Wilson  <jimw@sifive.com>
 926
 927         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 928         jalr.
 929
 930 2018-01-03  Alan Modra  <amodra@gmail.com>
 931
 932         Update year range in copyright notice of all files.
 933
 934 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 937         and OPERAND_TYPE_REGZMM entries.
 938
 939 For older changes see ChangeLog-2017
 940 \f
 941 Copyright (C) 2018 Free Software Foundation, Inc.
 942
 943 Copying and distribution of this file, with or without modification,
 944 are permitted in any medium without royalty provided the copyright
 945 notice and this notice are preserved.
 946
 947 Local Variables:
 948 mode: change-log
 949 left-margin: 8
 950 fill-column: 74
 951 version-control: never
 952 End: