opcodes/ChangeLog

   1 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
   2
   3         PR binutils/23242
   4         * aarch64-tbl.h (ldarh): Fix disassembly mask.
   5
   6 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
   7
   8         PR binutils/23369
   9         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
  10         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
  11
  12 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
  13
  14         PR tdep/8282
  15         * mips-dis.c (mips_option_arg_t): New enumeration.
  16         (mips_options): New variable.
  17         (disassembler_options_mips): New function.
  18         (print_mips_disassembler_options): Reimplement in terms of
  19         `disassembler_options_mips'.
  20         * arm-dis.c (disassembler_options_arm): Adapt to using the
  21         `disasm_options_and_args_t' structure.
  22         * ppc-dis.c (disassembler_options_powerpc): Likewise.
  23         * s390-dis.c (disassembler_options_s390): Likewise.
  24
  25 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  26
  27         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
  28         expected result.
  29         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
  30         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
  31         * testsuite/ld-arm/tls-longplt.d: Likewise.
  32
  33 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
  34
  35         PR binutils/23192
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Likewise.
  38         * aarch64-opc-2.c: Likewise.
  39         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
  40         * aarch64-opc.c (operand_general_constraint_met_p,
  41         aarch64_print_operand): Likewise.
  42         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
  43         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
  44         fmlal2, fmlsl2.
  45         (AARCH64_OPERANDS): Add Em2.
  46
  47 2018-06-26  Nick Clifton  <nickc@redhat.com>
  48
  49         * po/uk.po: Updated Ukranian translation.
  50         * po/de.po: Updated German translation.
  51         * po/pt_BR.po: Updated Brazilian Portuguese translation.
  52
  53 2018-06-26  Nick Clifton  <nickc@redhat.com>
  54
  55         * nfp-dis.c: Fix spelling mistake.
  56
  57 2018-06-24  Nick Clifton  <nickc@redhat.com>
  58
  59         * configure: Regenerate.
  60         * po/opcodes.pot: Regenerate.
  61
  62 2018-06-24  Nick Clifton  <nickc@redhat.com>
  63
  64         2.31 branch created.
  65
  66 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
  67
  68         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
  69         * aarch64-asm-2.c: Regenerate.
  70         * aarch64-dis-2.c: Likewise.
  71
  72 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
  73
  74         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
  75         `-M ginv' option description.
  76
  77 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  78
  79         PR gas/23305
  80         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
  81         la and lla.
  82
  83 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
  84
  85         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
  86         * configure.ac: Remove AC_PREREQ.
  87         * Makefile.in: Re-generate.
  88         * aclocal.m4: Re-generate.
  89         * configure: Re-generate.
  90
  91 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  92
  93         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
  94         mips64r6 descriptors.
  95         (parse_mips_ase_option): Handle -Mginv option.
  96         (print_mips_disassembler_options): Document -Mginv.
  97         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
  98         (GINV): New macro.
  99         (mips_opcodes): Define ginvi and ginvt.
 100
 101 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 102             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 103
 104         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 105         * mips-opc.c (CRC, CRC64): New macros.
 106         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 107         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 108         crc32cd for CRC64.
 109
 110 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 111
 112         PR 20319
 113         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 114         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 115
 116 2018-06-06  Alan Modra  <amodra@gmail.com>
 117
 118         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 119         setjmp.  Move init for some other vars later too.
 120
 121 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 122
 123         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 124         (dis_private): Add new fields for property section tracking.
 125         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 126         (xtensa_instruction_fits): New functions.
 127         (fetch_data): Bump minimal fetch size to 4.
 128         (print_insn_xtensa): Make struct dis_private static.
 129         Load and prepare property table on section change.
 130         Don't disassemble literals. Don't disassemble instructions that
 131         cross property table boundaries.
 132
 133 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         * configure: Regenerated.
 136
 137 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 140         * i386-tbl.h: Re-generate.
 141
 142 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (sldt, str): Add NoRex64.
 145         * i386-tbl.h: Re-generate.
 146
 147 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.tbl (invpcid): Add Oword.
 150         * i386-tbl.h: Re-generate.
 151
 152 2018-06-01  Alan Modra  <amodra@gmail.com>
 153
 154         * sysdep.h (_bfd_error_handler): Don't declare.
 155         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 156         * rl78-decode.opc: Likewise.
 157         * msp430-decode.c: Regenerate.
 158         * rl78-decode.c: Regenerate.
 159
 160 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 161
 162         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 163         * i386-init.h : Regenerated.
 164
 165 2018-05-25  Alan Modra  <amodra@gmail.com>
 166
 167         * Makefile.in: Regenerate.
 168         * po/POTFILES.in: Regenerate.
 169
 170 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 171
 172         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 173         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 174         (insert_bab, extract_bab, insert_btab, extract_btab,
 175         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 176         (BAT, BBA VBA RBS XB6S): Delete macros.
 177         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 178         (BB, BD, RBX, XC6): Update for new macros.
 179         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 180         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 181         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 182         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 183
 184 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 185
 186         * Makefile.am: Add support for s12z architecture.
 187         * configure.ac: Likewise.
 188         * disassemble.c: Likewise.
 189         * disassemble.h: Likewise.
 190         * Makefile.in: Regenerate.
 191         * configure: Regenerate.
 192         * s12z-dis.c: New file.
 193         * s12z.h: New file.
 194
 195 2018-05-18  Alan Modra  <amodra@gmail.com>
 196
 197         * nfp-dis.c: Don't #include libbfd.h.
 198         (init_nfp3200_priv): Use bfd_get_section_contents.
 199         (nit_nfp6000_mecsr_sec): Likewise.
 200
 201 2018-05-17  Nick Clifton  <nickc@redhat.com>
 202
 203         * po/zh_CN.po: Updated simplified Chinese translation.
 204
 205 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 206
 207         PR binutils/23109
 208         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 209         * aarch64-dis-2.c: Regenerate.
 210
 211 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 212
 213         PR binutils/21446
 214         * aarch64-asm.c (opintl.h): Include.
 215         (aarch64_ins_sysreg): Enforce read/write constraints.
 216         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 217         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 218         (F_REG_READ, F_REG_WRITE): New.
 219         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 220         AARCH64_OPND_SYSREG.
 221         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 222         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 223         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 224         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 225         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 226         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 227         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 228         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 229         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 230         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 231         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 232         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 233         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 234         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 235         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 236         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 237         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 238
 239 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 240
 241         PR binutils/21446
 242         * aarch64-dis.c (no_notes: New.
 243         (parse_aarch64_dis_option): Support notes.
 244         (aarch64_decode_insn, print_operands): Likewise.
 245         (print_aarch64_disassembler_options): Document notes.
 246         * aarch64-opc.c (aarch64_print_operand): Support notes.
 247
 248 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 249
 250         PR binutils/21446
 251         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 252         and take error struct.
 253         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 254         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 255         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 256         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 257         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 258         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 259         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 260         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 261         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 262         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 263         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 264         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 265         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 266         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 267         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 268         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 269         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 270         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 271         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 272         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 273         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 274         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 275         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 276         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 277         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 278         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 279         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 280         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 281         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 282         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 283         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 284         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 285         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 286         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 287         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 288         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 289         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 290         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 291         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 292         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 293         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 294         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 295         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 296         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 297         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 298         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 299         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 300         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 301         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 302         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 303         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 304         (determine_disassembling_preference, aarch64_decode_insn,
 305         print_insn_aarch64_word, print_insn_data): Take errors struct.
 306         (print_insn_aarch64): Use errors.
 307         * aarch64-asm-2.c: Regenerate.
 308         * aarch64-dis-2.c: Regenerate.
 309         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 310         boolean in aarch64_insert_operan.
 311         (print_operand_extractor): Likewise.
 312         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 313
 314 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 315
 316         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 317
 318 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 321
 322 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 323
 324         * cr16-opc.c (cr16_instruction): Comment typo fix.
 325         * hppa-dis.c (print_insn_hppa): Likewise.
 326
 327 2018-05-08  Jim Wilson  <jimw@sifive.com>
 328
 329         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 330         (match_c_slli64, match_srxi_as_c_srxi): New.
 331         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 332         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 333         <c.slli, c.srli, c.srai>: Use match_s_slli.
 334         <c.slli64, c.srli64, c.srai64>: New.
 335
 336 2018-05-08  Alan Modra  <amodra@gmail.com>
 337
 338         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 339         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 340         partition opcode space for index lookup.
 341
 342 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 343
 344         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 345         <insn_length>: ...with this.  Update usage.
 346         Remove duplicate call to *info->memory_error_func.
 347
 348 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 349             H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         * i386-dis.c (Gva): New.
 352         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 353         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 354         (prefix_table): New instructions (see prefix above).
 355         (mod_table): New instructions (see prefix above).
 356         (OP_G): Handle va_mode.
 357         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 358         CPU_MOVDIR64B_FLAGS.
 359         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 360         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 361         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 362         * i386-opc.tbl: Add movidir{i,64b}.
 363         * i386-init.h: Regenerated.
 364         * i386-tbl.h: Likewise.
 365
 366 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 369         AddrPrefixOpReg.
 370         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 371         (AddrPrefixOpReg): This.
 372         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 373         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 374
 375 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 376
 377         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 378         (vle_num_opcodes): Likewise.
 379         (spe2_num_opcodes): Likewise.
 380         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 381         initialization loop.
 382         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 383         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 384         only once.
 385
 386 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 387
 388         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 389
 390 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 391
 392         Makefile.am: Added nfp-dis.c.
 393         configure.ac: Added bfd_nfp_arch.
 394         disassemble.h: Added print_insn_nfp prototype.
 395         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 396         nfp-dis.c: New, for NFP support.
 397         po/POTFILES.in: Added nfp-dis.c to the list.
 398         Makefile.in: Regenerate.
 399         configure: Regenerate.
 400
 401 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 404         templates into their base ones.
 405         * i386-tlb.h: Re-generate.
 406
 407 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 410         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 411         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 412         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 413         * i386-init.h: Re-generate.
 414
 415 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 418         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 419         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 420         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 421         comment.
 422         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 423         and CpuRegMask.
 424         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 425         CpuRegMask: Delete.
 426         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 427         cpuregzmm, and cpuregmask.
 428         * i386-init.h: Re-generate.
 429         * i386-tbl.h: Re-generate.
 430
 431 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 434         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 435         * i386-init.h: Re-generate.
 436
 437 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-gen.c (VexImmExt): Delete.
 440         * i386-opc.h (VexImmExt, veximmext): Delete.
 441         * i386-opc.tbl: Drop all VexImmExt uses.
 442         * i386-tlb.h: Re-generate.
 443
 444 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 447         register-only forms.
 448         * i386-tlb.h: Re-generate.
 449
 450 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 451
 452         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 453
 454 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 455
 456         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 457         PREFIX_0F1C.
 458         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 459         (cpu_flags): Add CpuCLDEMOTE.
 460         * i386-init.h: Regenerate.
 461         * i386-opc.h (enum): Add CpuCLDEMOTE,
 462         (i386_cpu_flags): Add cpucldemote.
 463         * i386-opc.tbl: Add cldemote.
 464         * i386-tbl.h: Regenerate.
 465
 466 2018-04-16  Alan Modra  <amodra@gmail.com>
 467
 468         * Makefile.am: Remove sh5 and sh64 support.
 469         * configure.ac: Likewise.
 470         * disassemble.c: Likewise.
 471         * disassemble.h: Likewise.
 472         * sh-dis.c: Likewise.
 473         * sh64-dis.c: Delete.
 474         * sh64-opc.c: Delete.
 475         * sh64-opc.h: Delete.
 476         * Makefile.in: Regenerate.
 477         * configure: Regenerate.
 478         * po/POTFILES.in: Regenerate.
 479
 480 2018-04-16  Alan Modra  <amodra@gmail.com>
 481
 482         * Makefile.am: Remove w65 support.
 483         * configure.ac: Likewise.
 484         * disassemble.c: Likewise.
 485         * disassemble.h: Likewise.
 486         * w65-dis.c: Delete.
 487         * w65-opc.h: Delete.
 488         * Makefile.in: Regenerate.
 489         * configure: Regenerate.
 490         * po/POTFILES.in: Regenerate.
 491
 492 2018-04-16  Alan Modra  <amodra@gmail.com>
 493
 494         * configure.ac: Remove we32k support.
 495         * configure: Regenerate.
 496
 497 2018-04-16  Alan Modra  <amodra@gmail.com>
 498
 499         * Makefile.am: Remove m88k support.
 500         * configure.ac: Likewise.
 501         * disassemble.c: Likewise.
 502         * disassemble.h: Likewise.
 503         * m88k-dis.c: Delete.
 504         * Makefile.in: Regenerate.
 505         * configure: Regenerate.
 506         * po/POTFILES.in: Regenerate.
 507
 508 2018-04-16  Alan Modra  <amodra@gmail.com>
 509
 510         * Makefile.am: Remove i370 support.
 511         * configure.ac: Likewise.
 512         * disassemble.c: Likewise.
 513         * disassemble.h: Likewise.
 514         * i370-dis.c: Delete.
 515         * i370-opc.c: Delete.
 516         * Makefile.in: Regenerate.
 517         * configure: Regenerate.
 518         * po/POTFILES.in: Regenerate.
 519
 520 2018-04-16  Alan Modra  <amodra@gmail.com>
 521
 522         * Makefile.am: Remove h8500 support.
 523         * configure.ac: Likewise.
 524         * disassemble.c: Likewise.
 525         * disassemble.h: Likewise.
 526         * h8500-dis.c: Delete.
 527         * h8500-opc.h: Delete.
 528         * Makefile.in: Regenerate.
 529         * configure: Regenerate.
 530         * po/POTFILES.in: Regenerate.
 531
 532 2018-04-16  Alan Modra  <amodra@gmail.com>
 533
 534         * configure.ac: Remove tahoe support.
 535         * configure: Regenerate.
 536
 537 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 538
 539         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 540         umwait.
 541         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 542         64-bit mode.
 543         * i386-tbl.h: Regenerated.
 544
 545 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 546
 547         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 548         PREFIX_MOD_1_0FAE_REG_6.
 549         (va_mode): New.
 550         (OP_E_register): Use va_mode.
 551         * i386-dis-evex.h (prefix_table):
 552         New instructions (see prefixes above).
 553         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 554         (cpu_flags): Likewise.
 555         * i386-opc.h (enum): Likewise.
 556         (i386_cpu_flags): Likewise.
 557         * i386-opc.tbl: Add umonitor, umwait, tpause.
 558         * i386-init.h: Regenerate.
 559         * i386-tbl.h: Likewise.
 560
 561 2018-04-11  Alan Modra  <amodra@gmail.com>
 562
 563         * opcodes/i860-dis.c: Delete.
 564         * opcodes/i960-dis.c: Delete.
 565         * Makefile.am: Remove i860 and i960 support.
 566         * configure.ac: Likewise.
 567         * disassemble.c: Likewise.
 568         * disassemble.h: Likewise.
 569         * Makefile.in: Regenerate.
 570         * configure: Regenerate.
 571         * po/POTFILES.in: Regenerate.
 572
 573 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR binutils/23025
 576         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 577         to 0.
 578         (print_insn): Clear vex instead of vex.evex.
 579
 580 2018-04-04  Nick Clifton  <nickc@redhat.com>
 581
 582         * po/es.po: Updated Spanish translation.
 583
 584 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (opcode_modifiers): Delete VecESize.
 587         * i386-opc.h (VecESize): Delete.
 588         (struct i386_opcode_modifier): Delete vecesize.
 589         * i386-opc.tbl: Drop VecESize.
 590         * i386-tlb.h: Re-generate.
 591
 592 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 595         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 596         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 597         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 598         * i386-tlb.h: Re-generate.
 599
 600 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 603         Fold AVX512 forms
 604         * i386-tlb.h: Re-generate.
 605
 606 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 609         (vex_len_table): Drop Y for vcvt*2si.
 610         (putop): Replace plain 'Y' handling by abort().
 611
 612 2018-03-28  Nick Clifton  <nickc@redhat.com>
 613
 614         PR 22988
 615         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 616         instructions with only a base address register.
 617         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 618         handle AARHC64_OPND_SVE_ADDR_R.
 619         (aarch64_print_operand): Likewise.
 620         * aarch64-asm-2.c: Regenerate.
 621         * aarch64_dis-2.c: Regenerate.
 622         * aarch64-opc-2.c: Regenerate.
 623
 624 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl: Drop VecESize from register only insn forms and
 627         memory forms not allowing broadcast.
 628         * i386-tlb.h: Re-generate.
 629
 630 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 633         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 634         sha256*): Drop Disp<N>.
 635
 636 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-dis.c (EbndS, bnd_swap_mode): New.
 639         (prefix_table): Use EbndS.
 640         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 641         * i386-opc.tbl (bndmov): Move misplaced Load.
 642         * i386-tlb.h: Re-generate.
 643
 644 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 647         templates allowing memory operands and folded ones for register
 648         only flavors.
 649         * i386-tlb.h: Re-generate.
 650
 651 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 654         256-bit templates. Drop redundant leftover Disp<N>.
 655         * i386-tlb.h: Re-generate.
 656
 657 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 658
 659         * riscv-opc.c (riscv_insn_types): New.
 660
 661 2018-03-13  Nick Clifton  <nickc@redhat.com>
 662
 663         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 664
 665 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 666
 667         * i386-opc.tbl: Add Optimize to clr.
 668         * i386-tbl.h: Regenerated.
 669
 670 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 673         * i386-opc.h (OldGcc): Removed.
 674         (i386_opcode_modifier): Remove oldgcc.
 675         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 676         instructions for old (<= 2.8.1) versions of gcc.
 677         * i386-tbl.h: Regenerated.
 678
 679 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 680
 681         * i386-opc.h (EVEXDYN): New.
 682         * i386-opc.tbl: Fold various AVX512VL templates.
 683         * i386-tlb.h: Re-generate.
 684
 685 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 688         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 689         vpexpandd, vpexpandq): Fold AFX512VF templates.
 690         * i386-tlb.h: Re-generate.
 691
 692 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 695         Fold 128- and 256-bit VEX-encoded templates.
 696         * i386-tlb.h: Re-generate.
 697
 698 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 701         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 702         vpexpandd, vpexpandq): Fold AVX512F templates.
 703         * i386-tlb.h: Re-generate.
 704
 705 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 708         64-bit templates. Drop Disp<N>.
 709         * i386-tlb.h: Re-generate.
 710
 711 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 714         and 256-bit templates.
 715         * i386-tlb.h: Re-generate.
 716
 717 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 720         * i386-tlb.h: Re-generate.
 721
 722 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 725         Drop NoAVX.
 726         * i386-tlb.h: Re-generate.
 727
 728 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 731         * i386-tlb.h: Re-generate.
 732
 733 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-gen.c (opcode_modifiers): Delete FloatD.
 736         * i386-opc.h (FloatD): Delete.
 737         (struct i386_opcode_modifier): Delete floatd.
 738         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 739         FloatD by D.
 740         * i386-tlb.h: Re-generate.
 741
 742 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 745
 746 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 749         * i386-tlb.h: Re-generate.
 750
 751 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 754         forms.
 755         * i386-tlb.h: Re-generate.
 756
 757 2018-03-07  Alan Modra  <amodra@gmail.com>
 758
 759         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 760         bfd_arch_rs6000.
 761         * disassemble.h (print_insn_rs6000): Delete.
 762         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 763         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 764         (print_insn_rs6000): Delete.
 765
 766 2018-03-03  Alan Modra  <amodra@gmail.com>
 767
 768         * sysdep.h (opcodes_error_handler): Define.
 769         (_bfd_error_handler): Declare.
 770         * Makefile.am: Remove stray #.
 771         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 772         EDIT" comment.
 773         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 774         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 775         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 776         opcodes_error_handler to print errors.  Standardize error messages.
 777         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 778         and include opintl.h.
 779         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 780         * i386-gen.c: Standardize error messages.
 781         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 782         * Makefile.in: Regenerate.
 783         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 784         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 785         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 786         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 787         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 788         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 789         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 790         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 791         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 792         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 793         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 794         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 795         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 796
 797 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 800         vpsub[bwdq] instructions.
 801         * i386-tbl.h: Regenerated.
 802
 803 2018-03-01  Alan Modra  <amodra@gmail.com>
 804
 805         * configure.ac (ALL_LINGUAS): Sort.
 806         * configure: Regenerate.
 807
 808 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 809
 810         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 811         macro by assignements.
 812
 813 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         PR gas/22871
 816         * i386-gen.c (opcode_modifiers): Add Optimize.
 817         * i386-opc.h (Optimize): New enum.
 818         (i386_opcode_modifier): Add optimize.
 819         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 820         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 821         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 822         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 823         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 824         vpxord and vpxorq.
 825         * i386-tbl.h: Regenerated.
 826
 827 2018-02-26  Alan Modra  <amodra@gmail.com>
 828
 829         * crx-dis.c (getregliststring): Allocate a large enough buffer
 830         to silence false positive gcc8 warning.
 831
 832 2018-02-22  Shea Levy <shea@shealevy.com>
 833
 834         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 835
 836 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 837
 838         * i386-opc.tbl: Add {rex},
 839         * i386-tbl.h: Regenerated.
 840
 841 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 842
 843         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 844         (mips16_opcodes): Replace `M' with `m' for "restore".
 845
 846 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 847
 848         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 849
 850 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 851
 852         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 853         variable to `function_index'.
 854
 855 2018-02-13  Nick Clifton  <nickc@redhat.com>
 856
 857         PR 22823
 858         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 859         about truncation of printing.
 860
 861 2018-02-12  Henry Wong <henry@stuffedcow.net>
 862
 863         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 864
 865 2018-02-05  Nick Clifton  <nickc@redhat.com>
 866
 867         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 868
 869 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 870
 871         * i386-dis.c (enum): Add pconfig.
 872         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 873         (cpu_flags): Add CpuPCONFIG.
 874         * i386-opc.h (enum): Add CpuPCONFIG.
 875         (i386_cpu_flags): Add cpupconfig.
 876         * i386-opc.tbl: Add PCONFIG instruction.
 877         * i386-init.h: Regenerate.
 878         * i386-tbl.h: Likewise.
 879
 880 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 881
 882         * i386-dis.c (enum): Add PREFIX_0F09.
 883         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 884         (cpu_flags): Add CpuWBNOINVD.
 885         * i386-opc.h (enum): Add CpuWBNOINVD.
 886         (i386_cpu_flags): Add cpuwbnoinvd.
 887         * i386-opc.tbl: Add WBNOINVD instruction.
 888         * i386-init.h: Regenerate.
 889         * i386-tbl.h: Likewise.
 890
 891 2018-01-17  Jim Wilson  <jimw@sifive.com>
 892
 893         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 894
 895 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 896
 897         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 898         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 899         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 900         (cpu_flags): Add CpuIBT, CpuSHSTK.
 901         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 902         (i386_cpu_flags): Add cpuibt, cpushstk.
 903         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 904         * i386-init.h: Regenerate.
 905         * i386-tbl.h: Likewise.
 906
 907 2018-01-16  Nick Clifton  <nickc@redhat.com>
 908
 909         * po/pt_BR.po: Updated Brazilian Portugese translation.
 910         * po/de.po: Updated German translation.
 911
 912 2018-01-15  Jim Wilson  <jimw@sifive.com>
 913
 914         * riscv-opc.c (match_c_nop): New.
 915         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 916
 917 2018-01-15  Nick Clifton  <nickc@redhat.com>
 918
 919         * po/uk.po: Updated Ukranian translation.
 920
 921 2018-01-13  Nick Clifton  <nickc@redhat.com>
 922
 923         * po/opcodes.pot: Regenerated.
 924
 925 2018-01-13  Nick Clifton  <nickc@redhat.com>
 926
 927         * configure: Regenerate.
 928
 929 2018-01-13  Nick Clifton  <nickc@redhat.com>
 930
 931         2.30 branch created.
 932
 933 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 934
 935         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 936         * i386-tbl.h: Regenerate.
 937
 938 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 941         * i386-tbl.h: Re-generate.
 942
 943 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 946         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 947         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 948         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 949         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 950         Disp8MemShift of AVX512VL forms.
 951         * i386-tbl.h: Re-generate.
 952
 953 2018-01-09  Jim Wilson  <jimw@sifive.com>
 954
 955         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 956         then the hi_addr value is zero.
 957
 958 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 959
 960         * arm-dis.c (arm_opcodes): Add csdb.
 961         (thumb32_opcodes): Add csdb.
 962
 963 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 964
 965         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 966         * aarch64-asm-2.c: Regenerate.
 967         * aarch64-dis-2.c: Regenerate.
 968         * aarch64-opc-2.c: Regenerate.
 969
 970 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 971
 972         PR gas/22681
 973         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 974         Remove AVX512 vmovd with 64-bit operands.
 975         * i386-tbl.h: Regenerated.
 976
 977 2018-01-05  Jim Wilson  <jimw@sifive.com>
 978
 979         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 980         jalr.
 981
 982 2018-01-03  Alan Modra  <amodra@gmail.com>
 983
 984         Update year range in copyright notice of all files.
 985
 986 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 987
 988         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 989         and OPERAND_TYPE_REGZMM entries.
 990
 991 For older changes see ChangeLog-2017
 992 \f
 993 Copyright (C) 2018 Free Software Foundation, Inc.
 994
 995 Copying and distribution of this file, with or without modification,
 996 are permitted in any medium without royalty provided the copyright
 997 notice and this notice are preserved.
 998
 999 Local Variables:
1000 mode: change-log
1001 left-margin: 8
1002 fill-column: 74
1003 version-control: never
1004 End: