1 2020-10-14 Lili Cui <lili.cui@intel.com>
3 * i386-dis.c (enum): Add
4 PREFIX_MOD_3_0F01_REG_5_RM_4,
5 PREFIX_MOD_3_0F01_REG_5_RM_5,
6 PREFIX_MOD_3_0F01_REG_5_RM_6,
7 PREFIX_MOD_3_0F01_REG_5_RM_7,
8 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
9 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
10 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
11 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
12 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
13 (prefix_table): New instructions (see prefixes above).
15 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
17 (cpu_flags): Add CpuUINTR.
18 * i386-opc.h (enum): Add CpuUINTR.
19 (i386_cpu_flags): Add cpuuintr.
20 * i386-opc.tbl: Add UINTR insns.
21 * i386-init.h: Regenerate.
22 * i386-tbl.h: Likewise.
24 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
26 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
27 non-VEX/EVEX/prefix encoding.
28 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
30 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
31 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
32 * i386-tbl.h: Regenerated.
34 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
38 * i386-opc.h (VexOpcode): Renamed to ...
41 (PREFIX_0X66): Likewise.
42 (PREFIX_0XF2): Likewise.
43 (PREFIX_0XF3): Likewise.
44 * i386-opc.tbl (Prefix_0X66): New.
45 (Prefix_0XF2): Likewise.
46 (Prefix_0XF3): Likewise.
47 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
48 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
49 * i386-tbl.h: Regenerated.
51 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
53 * cgen-asm.c: Fix spelling mistakes.
54 * cgen-dis.c: Fix spelling mistakes.
55 * tic30-dis.c: Fix spelling mistakes.
57 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
60 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
62 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-dis.c (print_insn): Clear modrm if not needed.
66 (putop): Check need_modrm for modrm.mod != 3. Don't check
67 need_modrm for modrm.mod == 3.
69 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
71 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
72 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
73 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
74 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
75 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
76 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
77 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
78 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
79 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
80 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
81 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
82 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
83 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
84 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
86 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
88 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
90 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
92 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
93 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
95 2020-09-26 Alan Modra <amodra@gmail.com>
97 * csky-opc.h: Formatting.
98 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
99 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
101 (get_register_number): Likewise.
102 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
104 2020-09-24 Lili Cui <lili.cui@intel.com>
107 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
109 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
111 * csky-dis.c (csky_output_operand): Enclose body of if in curly
114 2020-09-24 Lili Cui <lili.cui@intel.com>
116 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
117 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
118 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
119 X86_64_0F01_REG_1_RM_7_P_2.
120 (prefix_table): Likewise.
121 (x86_64_table): Likewise.
122 (rm_table): Likewise.
123 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
124 and CPU_ANY_TDX_FLAGS.
125 (cpu_flags): Add CpuTDX.
126 * i386-opc.h (enum): Add CpuTDX.
127 (i386_cpu_flags): Add cputdx.
128 * i386-opc.tbl: Add TDX insns.
129 * i386-init.h: Regenerate.
130 * i386-tbl.h: Likewise.
132 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
134 * csky-dis.c (using_abi): New.
135 (parse_csky_dis_options): New function.
136 (get_gr_name): New function.
137 (get_cr_name): New function.
138 (csky_output_operand): Use get_gr_name and get_cr_name to
139 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
140 (print_insn_csky): Parse disassembler options.
141 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
142 (GENARAL_REG_BANK): Define.
143 (REG_SUPPORT_ALL): Define.
144 (REG_SUPPORT_ALL): New.
146 (REG_SUPPORT_A): Define.
147 (REG_SUPPORT_B): Define.
148 (REG_SUPPORT_C): Define.
149 (REG_SUPPORT_D): Define.
150 (REG_SUPPORT_E): Define.
151 (csky_abiv1_general_regs): New.
152 (csky_abiv1_control_regs): New.
153 (csky_abiv2_general_regs): New.
154 (csky_abiv2_control_regs): New.
155 (get_register_name): New function.
156 (get_register_number): New function.
157 (csky_get_general_reg_name): New function.
158 (csky_get_general_regno): New function.
159 (csky_get_control_reg_name): New function.
160 (csky_get_control_regno): New function.
161 (csky_v2_opcodes): Prefer two oprerans format for bclri and
162 bseti, strengthen the operands legality check of addc, zext
165 2020-09-23 Lili Cui <lili.cui@intel.com>
167 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
168 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
169 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
170 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
171 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
172 (reg_table): New instructions (see prefixes above).
173 (prefix_table): Likewise.
174 (three_byte_table): Likewise.
175 (mod_table): Likewise
176 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
177 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
178 (cpu_flags): Likewise.
179 (operand_type_init): Likewise.
180 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
181 (i386_cpu_flags): Add cpukl and cpuwide_kl.
182 * i386-opc.tbl: Add KL and WIDE_KL insns.
183 * i386-init.h: Regenerate.
184 * i386-tbl.h: Likewise.
186 2020-09-21 Alan Modra <amodra@gmail.com>
188 * rx-dis.c (flag_names): Add missing comma.
189 (register_names, flag_names, double_register_names),
190 (double_register_high_names, double_register_low_names),
191 (double_control_register_names, double_condition_names): Remove
194 2020-09-18 David Faust <david.faust@oracle.com>
196 * bpf-desc.c: Regenerate.
197 * bpf-desc.h: Likewise.
198 * bpf-opc.c: Likewise.
199 * bpf-opc.h: Likewise.
201 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
203 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
206 2020-09-16 Alan Modra <amodra@gmail.com>
208 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
210 2020-09-10 Nick Clifton <nickc@redhat.com>
212 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
213 for hidden, local, no-type symbols.
214 (disassemble_init_powerpc): Point the symbol_is_valid field in the
215 info structure at the new function.
217 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
219 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
220 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
223 2020-09-10 Nick Clifton <nickc@redhat.com>
225 * csky-dis.c (csky_output_operand): Coerce the immediate values to
226 long before printing.
228 2020-09-10 Alan Modra <amodra@gmail.com>
230 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
232 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
234 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
237 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
239 * csky-dis.c (csky_output_operand): Add handlers for
240 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
241 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
242 to support FPUV3 instructions.
243 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
244 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
245 OPRND_TYPE_DFLOAT_FMOVI.
246 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
247 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
248 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
249 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
250 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
251 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
252 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
253 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
254 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
255 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
256 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
257 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
258 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
259 (csky_v2_opcodes): Add FPUV3 instructions.
261 2020-09-08 Alex Coplan <alex.coplan@arm.com>
263 * aarch64-dis.c (print_operands): Pass CPU features to
264 aarch64_print_operand().
265 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
266 preferred disassembly of system registers.
267 (SR_RNG): Refactor to use new SR_FEAT2 macro.
273 (SR_EXPAND_ELx): New.
274 (SR_EXPAND_EL12): New.
275 (aarch64_sys_regs): Specify which registers are only on
276 A-profile, add R-profile system registers.
280 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
283 2020-09-08 Alex Coplan <alex.coplan@arm.com>
285 * aarch64-tbl.h (aarch64_feature_v8_r): New.
288 (aarch64_opcode_table): Add dfb.
289 * aarch64-opc-2.c: Regenerate.
290 * aarch64-asm-2.c: Regenerate.
291 * aarch64-dis-2.c: Regenerate.
293 2020-09-08 Alex Coplan <alex.coplan@arm.com>
295 * aarch64-dis.c (arch_variant): New.
296 (determine_disassembling_preference): Disassemble according to
298 (select_aarch64_variant): New.
299 (print_insn_aarch64): Set feature set.
301 2020-09-02 Alan Modra <amodra@gmail.com>
303 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
304 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
305 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
306 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
307 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
308 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
309 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
310 for value parameter and update code to suit.
311 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
312 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
314 2020-09-02 Alan Modra <amodra@gmail.com>
316 * i386-dis.c (OP_E_memory): Don't cast to signed type when
318 (get32, get32s): Use unsigned types in shift expressions.
320 2020-09-02 Alan Modra <amodra@gmail.com>
322 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
324 2020-09-02 Alan Modra <amodra@gmail.com>
326 * crx-dis.c: Whitespace.
327 (print_arg): Use unsigned type for longdisp and mask variables,
328 and for left shift constant.
330 2020-09-02 Alan Modra <amodra@gmail.com>
332 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
333 * bpf-ibld.c: Regenerate.
334 * epiphany-ibld.c: Regenerate.
335 * fr30-ibld.c: Regenerate.
336 * frv-ibld.c: Regenerate.
337 * ip2k-ibld.c: Regenerate.
338 * iq2000-ibld.c: Regenerate.
339 * lm32-ibld.c: Regenerate.
340 * m32c-ibld.c: Regenerate.
341 * m32r-ibld.c: Regenerate.
342 * mep-ibld.c: Regenerate.
343 * mt-ibld.c: Regenerate.
344 * or1k-ibld.c: Regenerate.
345 * xc16x-ibld.c: Regenerate.
346 * xstormy16-ibld.c: Regenerate.
348 2020-09-02 Alan Modra <amodra@gmail.com>
350 * bfin-dis.c (MASKBITS): Use SIGNBIT.
352 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
354 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
355 to CSKYV2_ISA_3E3R3 instruction set.
357 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
359 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
361 2020-09-01 Alan Modra <amodra@gmail.com>
363 * mep-ibld.c: Regenerate.
365 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
367 * csky-dis.c (csky_output_operand): Assign dis_info.value for
370 2020-08-30 Alan Modra <amodra@gmail.com>
372 * cr16-dis.c: Formatting.
373 (parameter): Delete struct typedef. Use dwordU instead
375 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
377 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
379 2020-08-29 Alan Modra <amodra@gmail.com>
382 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
383 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
385 2020-08-28 Alan Modra <amodra@gmail.com>
389 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
390 (extract_normal): Likewise.
391 (insert_normal): Likewise, and move past zero length test.
392 (put_insn_int_value): Handle mask for zero length, use 1UL.
393 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
394 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
395 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
396 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
398 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
400 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
401 (csky_dis_info): Add member isa.
402 (csky_find_inst_info): Skip instructions that do not belong to
404 (csky_get_disassembler): Get infomation from attribute section.
405 (print_insn_csky): Set defualt ISA flag.
406 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
407 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
408 isa_flag32'type to unsigned 64 bits.
410 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
412 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
414 2020-08-26 David Faust <david.faust@oracle.com>
416 * bpf-desc.c: Regenerate.
417 * bpf-desc.h: Likewise.
418 * bpf-opc.c: Likewise.
419 * bpf-opc.h: Likewise.
420 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
421 ISA when appropriate.
423 2020-08-25 Alan Modra <amodra@gmail.com>
426 * vax-dis.c (parse_disassembler_options): Always add at least one
427 to entry_addr_total_slots.
429 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
431 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
432 in other CPUs to speed up disassembling.
433 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
434 Change plsli.u16 to plsli.16, change sync's operand format.
436 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
438 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
440 2020-08-21 Nick Clifton <nickc@redhat.com>
442 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
445 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
447 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
449 2020-08-19 Alan Modra <amodra@gmail.com>
451 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
454 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
456 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
457 <xvcvbf16spn>: ...to this.
459 2020-08-12 Alex Coplan <alex.coplan@arm.com>
461 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
463 2020-08-12 Nick Clifton <nickc@redhat.com>
465 * po/sr.po: Updated Serbian translation.
467 2020-08-11 Alan Modra <amodra@gmail.com>
469 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
471 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
473 * aarch64-opc.c (aarch64_print_operand):
474 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
475 (aarch64_sys_reg_supported_p): Function removed.
476 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
477 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
480 2020-08-10 Alan Modra <amodra@gmail.com>
482 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
485 2020-08-10 Alan Modra <amodra@gmail.com>
487 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
488 Enable icbt for power5, miso for power8.
490 2020-08-10 Alan Modra <amodra@gmail.com>
492 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
493 mtvsrd, and similarly for mfvsrd.
495 2020-08-04 Christian Groessler <chris@groessler.org>
496 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
498 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
499 opcodes (special "out" to absolute address).
500 * z8k-opc.h: Regenerate.
502 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-opc.h (Prefix_Disp8): New.
506 (Prefix_Disp16): Likewise.
507 (Prefix_Disp32): Likewise.
508 (Prefix_Load): Likewise.
509 (Prefix_Store): Likewise.
510 (Prefix_VEX): Likewise.
511 (Prefix_VEX3): Likewise.
512 (Prefix_EVEX): Likewise.
513 (Prefix_REX): Likewise.
514 (Prefix_NoOptimize): Likewise.
515 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
516 * i386-tbl.h: Regenerated.
518 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
520 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
521 default case with abort() instead of printing an error message and
522 continuing, to avoid a maybe-uninitialized warning.
524 2020-07-24 Nick Clifton <nickc@redhat.com>
526 * po/de.po: Updated German translation.
528 2020-07-21 Jan Beulich <jbeulich@suse.com>
530 * i386-dis.c (OP_E_memory): Revert previous change.
532 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
535 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
536 without base nor index registers.
538 2020-07-15 Jan Beulich <jbeulich@suse.com>
540 * i386-dis.c (putop): Move 'V' and 'W' handling.
542 2020-07-15 Jan Beulich <jbeulich@suse.com>
544 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
545 construct for push/pop of register.
546 (putop): Honor cond when handling 'P'. Drop handling of plain
549 2020-07-15 Jan Beulich <jbeulich@suse.com>
551 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
552 description. Drop '&' description. Use P for push of immediate,
553 pushf/popf, enter, and leave. Use %LP for lret/retf.
554 (dis386_twobyte): Use P for push/pop of fs/gs.
555 (reg_table): Use P for push/pop. Use @ for near call/jmp.
556 (x86_64_table): Use P for far call/jmp.
557 (putop): Drop handling of 'U' and '&'. Move and adjust handling
558 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
560 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
561 and dqw_mode (unconditional).
563 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
566 * i386-dis.c (OP_E_memory): Without base nor index registers,
567 32-bit displacement to 64 bits.
569 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
571 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
572 faulty double register pair is detected.
574 2020-07-14 Jan Beulich <jbeulich@suse.com>
576 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
578 2020-07-14 Jan Beulich <jbeulich@suse.com>
580 * i386-dis.c (OP_R, Rm): Delete.
581 (MOD_0F24, MOD_0F26): Rename to ...
582 (X86_64_0F24, X86_64_0F26): ... respectively.
583 (dis386): Update 'L' and 'Z' comments.
584 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
586 (mod_table): Move opcode 0F24 and 0F26 entries ...
587 (x86_64_table): ... here.
588 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
591 2020-07-14 Jan Beulich <jbeulich@suse.com>
593 * i386-dis.c (Rd, Rdq, MaskR): Delete.
594 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
595 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
596 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
597 MOD_EVEX_0F387C): New enumerators.
598 (reg_table): Use Edq for rdssp.
599 (prefix_table): Use Edq for incssp.
600 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
601 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
602 ktest*, and kshift*. Use Edq / MaskE for kmov*.
603 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
604 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
605 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
606 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
607 0F3828_P_1 and 0F3838_P_1.
608 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
609 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
611 2020-07-14 Jan Beulich <jbeulich@suse.com>
613 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
614 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
615 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
616 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
617 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
618 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
619 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
620 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
621 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
622 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
623 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
624 (reg_table, prefix_table, three_byte_table, vex_table,
625 vex_len_table, mod_table, rm_table): Replace / remove respective
627 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
628 of PREFIX_DATA in used_prefixes.
630 2020-07-14 Jan Beulich <jbeulich@suse.com>
632 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
633 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
634 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
635 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
636 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
637 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
638 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
639 VEX_W_0F3A33_L_0): Delete.
640 (dis386): Adjust "BW" description.
641 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
642 0F3A31, 0F3A32, and 0F3A33.
643 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
645 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
648 2020-07-14 Jan Beulich <jbeulich@suse.com>
650 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
651 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
652 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
653 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
654 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
655 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
656 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
657 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
658 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
659 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
660 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
661 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
662 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
663 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
664 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
665 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
666 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
667 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
668 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
669 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
670 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
671 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
672 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
673 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
674 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
675 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
676 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
677 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
678 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
679 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
680 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
681 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
682 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
683 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
684 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
685 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
686 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
687 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
688 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
689 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
690 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
691 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
692 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
693 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
694 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
695 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
696 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
697 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
698 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
699 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
700 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
701 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
702 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
703 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
704 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
705 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
706 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
707 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
708 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
709 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
710 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
711 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
712 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
713 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
714 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
715 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
716 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
717 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
718 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
719 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
720 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
721 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
722 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
723 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
724 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
725 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
726 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
727 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
728 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
729 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
730 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
731 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
732 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
733 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
734 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
735 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
736 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
737 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
738 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
739 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
740 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
741 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
742 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
743 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
744 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
745 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
746 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
747 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
748 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
749 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
750 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
751 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
752 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
753 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
754 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
755 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
756 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
757 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
758 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
759 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
760 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
761 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
762 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
763 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
764 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
765 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
766 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
767 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
768 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
769 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
770 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
771 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
772 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
773 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
774 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
775 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
776 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
777 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
778 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
779 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
780 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
781 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
782 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
783 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
784 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
785 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
786 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
787 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
788 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
789 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
790 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
791 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
792 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
793 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
794 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
795 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
796 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
797 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
798 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
799 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
800 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
801 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
802 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
803 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
804 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
805 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
806 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
807 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
808 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
809 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
810 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
811 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
812 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
813 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
814 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
815 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
816 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
817 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
818 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
819 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
820 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
821 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
822 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
823 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
824 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
825 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
826 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
827 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
828 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
829 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
830 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
831 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
832 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
833 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
834 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
835 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
836 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
837 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
838 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
839 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
840 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
841 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
842 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
843 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
844 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
845 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
846 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
847 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
848 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
849 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
850 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
851 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
852 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
853 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
854 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
855 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
856 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
857 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
858 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
859 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
860 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
861 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
862 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
863 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
864 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
865 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
866 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
867 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
868 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
869 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
870 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
871 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
872 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
873 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
874 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
875 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
876 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
877 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
878 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
879 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
880 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
881 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
882 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
883 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
884 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
885 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
886 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
887 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
888 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
889 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
890 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
891 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
892 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
893 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
894 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
895 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
896 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
897 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
898 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
899 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
900 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
901 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
902 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
903 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
904 EVEX_W_0F3A72_P_2): Rename to ...
905 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
906 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
907 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
908 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
909 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
910 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
911 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
912 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
913 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
914 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
915 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
916 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
917 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
918 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
919 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
920 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
921 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
922 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
923 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
924 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
925 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
926 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
927 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
928 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
929 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
930 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
931 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
932 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
933 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
934 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
935 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
936 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
937 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
938 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
939 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
940 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
941 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
942 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
943 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
944 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
945 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
946 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
947 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
948 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
949 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
950 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
951 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
952 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
953 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
954 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
955 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
956 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
957 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
958 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
959 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
960 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
961 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
962 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
963 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
964 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
965 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
966 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
967 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
968 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
969 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
970 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
971 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
972 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
973 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
974 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
975 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
976 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
978 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
979 vex_w_table, mod_table): Replace / remove respective entries.
980 (print_insn): Move up dp->prefix_requirement handling. Handle
982 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
983 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
984 Replace / remove respective entries.
986 2020-07-14 Jan Beulich <jbeulich@suse.com>
988 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
989 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
990 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
991 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
992 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
994 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
995 0F2C, 0F2D, 0F2E, and 0F2F.
996 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
999 2020-07-14 Jan Beulich <jbeulich@suse.com>
1001 * i386-dis.c (OP_VexR, VexScalarR): New.
1002 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1003 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1004 need_vex_reg): Delete.
1005 (prefix_table): Replace VexScalar by VexScalarR and
1006 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1007 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1008 (vex_len_table): Replace EXqVexScalarS by EXqS.
1009 (get_valid_dis386): Don't set need_vex_reg.
1010 (print_insn): Don't initialize need_vex_reg.
1011 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1012 q_scalar_swap_mode cases.
1013 (OP_EX): Don't check for d_scalar_swap_mode and
1015 (OP_VEX): Done check need_vex_reg.
1016 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1017 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1018 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1020 2020-07-14 Jan Beulich <jbeulich@suse.com>
1022 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1023 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1024 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1025 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1026 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1027 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1028 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1029 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1030 (vex_table): Replace Vex128 by Vex.
1031 (vex_len_table): Likewise. Adjust referenced enum names.
1032 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1033 referenced enum names.
1034 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1035 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1037 2020-07-14 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1040 (putop): Handle "DQ". Don't handle "LW" anymore.
1041 (prefix_table, mod_table): Replace %LW by %DQ.
1042 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1044 2020-07-14 Jan Beulich <jbeulich@suse.com>
1046 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1047 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1048 d_scalar_swap_mode case handling. Move shift adjsutment into
1049 the case its applicable to.
1051 2020-07-14 Jan Beulich <jbeulich@suse.com>
1053 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1054 (EXbScalar, EXwScalar): Fold to ...
1055 (EXbwUnit): ... this.
1056 (b_scalar_mode, w_scalar_mode): Fold to ...
1057 (bw_unit_mode): ... this.
1058 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1059 w_scalar_mode handling by bw_unit_mode one.
1060 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1062 * i386-dis-evex-prefix.h: ... here.
1064 2020-07-14 Jan Beulich <jbeulich@suse.com>
1066 * i386-dis.c (PCMPESTR_Fixup): Delete.
1067 (dis386): Adjust "LQ" description.
1068 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1069 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1070 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1071 vpcmpestrm, and vpcmpestri.
1072 (putop): Honor "cond" when handling LQ.
1073 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1074 vcvtsi2ss and vcvtusi2ss.
1075 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1076 vcvtsi2sd and vcvtusi2sd.
1078 2020-07-14 Jan Beulich <jbeulich@suse.com>
1080 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1081 (simd_cmp_op): Add const.
1082 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1083 (CMP_Fixup): Handle VEX case.
1084 (prefix_table): Replace VCMP by CMP.
1085 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1087 2020-07-14 Jan Beulich <jbeulich@suse.com>
1089 * i386-dis.c (MOVBE_Fixup): Delete.
1091 (prefix_table): Use Mv for movbe entries.
1093 2020-07-14 Jan Beulich <jbeulich@suse.com>
1095 * i386-dis.c (CRC32_Fixup): Delete.
1096 (prefix_table): Use Eb/Ev for crc32 entries.
1098 2020-07-14 Jan Beulich <jbeulich@suse.com>
1100 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1101 Conditionalize invocations of "USED_REX (0)".
1103 2020-07-14 Jan Beulich <jbeulich@suse.com>
1105 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1106 CH, DH, BH, AX, DX): Delete.
1107 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1108 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1109 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1111 2020-07-10 Lili Cui <lili.cui@intel.com>
1113 * i386-dis.c (TMM): New.
1116 (MVexSIBMEM): Likewise.
1117 (tmm_mode): Likewise.
1118 (vex_sibmem_mode): Likewise.
1119 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1120 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1121 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1122 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1123 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1124 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1125 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1126 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1127 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1128 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1129 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1130 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1131 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1132 (PREFIX_VEX_0F3849_X86_64): Likewise.
1133 (PREFIX_VEX_0F384B_X86_64): Likewise.
1134 (PREFIX_VEX_0F385C_X86_64): Likewise.
1135 (PREFIX_VEX_0F385E_X86_64): Likewise.
1136 (X86_64_VEX_0F3849): Likewise.
1137 (X86_64_VEX_0F384B): Likewise.
1138 (X86_64_VEX_0F385C): Likewise.
1139 (X86_64_VEX_0F385E): Likewise.
1140 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1141 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1142 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1143 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1144 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1145 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1146 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1147 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1148 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1149 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1150 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1151 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1152 (VEX_W_0F3849_X86_64_P_0): Likewise.
1153 (VEX_W_0F3849_X86_64_P_2): Likewise.
1154 (VEX_W_0F3849_X86_64_P_3): Likewise.
1155 (VEX_W_0F384B_X86_64_P_1): Likewise.
1156 (VEX_W_0F384B_X86_64_P_2): Likewise.
1157 (VEX_W_0F384B_X86_64_P_3): Likewise.
1158 (VEX_W_0F385C_X86_64_P_1): Likewise.
1159 (VEX_W_0F385E_X86_64_P_0): Likewise.
1160 (VEX_W_0F385E_X86_64_P_1): Likewise.
1161 (VEX_W_0F385E_X86_64_P_2): Likewise.
1162 (VEX_W_0F385E_X86_64_P_3): Likewise.
1163 (names_tmm): Likewise.
1164 (att_names_tmm): Likewise.
1165 (intel_operand_size): Handle void_mode.
1166 (OP_XMM): Handle tmm_mode.
1169 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1170 CpuAMX_BF16 and CpuAMX_TILE.
1171 (operand_type_shorthands): Add RegTMM.
1172 (operand_type_init): Likewise.
1173 (operand_types): Add Tmmword.
1174 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1175 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1176 * i386-opc.h (CpuAMX_INT8): New.
1177 (CpuAMX_BF16): Likewise.
1178 (CpuAMX_TILE): Likewise.
1180 (Tmmword): Likewise.
1181 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1182 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1183 (i386_operand_type): Add tmmword.
1184 * i386-opc.tbl: Add AMX instructions.
1185 * i386-reg.tbl: Add AMX registers.
1186 * i386-init.h: Regenerated.
1187 * i386-tbl.h: Likewise.
1189 2020-07-08 Jan Beulich <jbeulich@suse.com>
1191 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1192 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1194 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1195 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1197 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1198 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1199 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1200 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1201 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1202 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1203 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1204 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1205 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1206 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1207 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1208 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1209 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1210 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1211 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1212 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1213 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1214 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1215 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1216 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1217 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1218 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1219 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1220 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1221 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1222 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1223 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1224 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1225 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1226 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1227 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1228 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1229 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1230 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1231 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1232 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1233 (reg_table): Re-order XOP entries. Adjust their operands.
1234 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1235 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1236 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1237 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1238 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1239 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1240 entries by references ...
1241 (vex_len_table): ... to resepctive new entries here. For several
1242 new and existing entries reference ...
1243 (vex_w_table): ... new entries here.
1244 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1246 2020-07-08 Jan Beulich <jbeulich@suse.com>
1248 * i386-dis.c (XMVexScalarI4): Define.
1249 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1250 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1251 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1252 (vex_len_table): Move scalar FMA4 entries ...
1253 (prefix_table): ... here.
1254 (OP_REG_VexI4): Handle scalar_mode.
1255 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1256 * i386-tbl.h: Re-generate.
1258 2020-07-08 Jan Beulich <jbeulich@suse.com>
1260 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1261 Vex_2src_2): Delete.
1262 (OP_VexW, VexW): New.
1263 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1264 for shifts and rotates by register.
1266 2020-07-08 Jan Beulich <jbeulich@suse.com>
1268 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1269 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1270 OP_EX_VexReg): Delete.
1271 (OP_VexI4, VexI4): New.
1272 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1273 (prefix_table): ... here.
1274 (print_insn): Drop setting of vex_w_done.
1276 2020-07-08 Jan Beulich <jbeulich@suse.com>
1278 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1279 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1280 (xop_table): Replace operands of 4-operand insns.
1281 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1283 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1285 * arc-opc.c (insert_rbd): New function.
1288 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1291 2020-07-07 Jan Beulich <jbeulich@suse.com>
1293 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1294 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1295 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1296 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1298 (putop): Handle "BW".
1299 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1300 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1302 * i386-dis-evex-prefix.h: ... here.
1304 2020-07-06 Jan Beulich <jbeulich@suse.com>
1306 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1307 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1308 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1309 VEX_W_0FXOP_09_83): New enumerators.
1310 (xop_table): Reference the above.
1311 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1312 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1313 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1314 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1316 2020-07-06 Jan Beulich <jbeulich@suse.com>
1318 * i386-dis.c (EVEX_W_0F3838_P_1,
1319 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1320 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1321 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1322 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1323 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1324 (putop): Centralize management of last[]. Delete SAVE_LAST.
1325 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1326 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1327 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1328 * i386-dis-evex-prefix.h: here.
1330 2020-07-06 Jan Beulich <jbeulich@suse.com>
1332 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1333 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1334 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1335 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1337 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1338 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1339 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1340 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1341 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1342 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1343 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1344 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1345 these, respectively.
1346 * i386-dis-evex-len.h: Adjust comments.
1347 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1348 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1349 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1350 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1351 MOD_EVEX_0F385B_P_2_W_1 table entries.
1352 * i386-dis-evex-w.h: Reference mod_table[] for
1353 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1356 2020-07-06 Jan Beulich <jbeulich@suse.com>
1358 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1359 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1361 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1362 Likewise. Mark 256-bit entries invalid.
1364 2020-07-06 Jan Beulich <jbeulich@suse.com>
1366 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1367 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1368 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1369 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1370 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1371 PREFIX_EVEX_0F382B): Delete.
1372 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1373 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1374 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1375 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1376 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1378 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1379 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1380 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1381 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1383 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1384 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1385 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1386 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1387 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1388 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1389 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1390 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1391 PREFIX_EVEX_0F382B): Remove table entries.
1392 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1393 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1394 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1396 2020-07-06 Jan Beulich <jbeulich@suse.com>
1398 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1399 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1401 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1402 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1403 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1404 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1407 2020-07-06 Jan Beulich <jbeulich@suse.com>
1409 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1410 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1411 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1412 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1413 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1414 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1415 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1416 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1417 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1420 2020-07-06 Jan Beulich <jbeulich@suse.com>
1422 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1423 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1424 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1426 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1428 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1430 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1432 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1434 2020-07-06 Jan Beulich <jbeulich@suse.com>
1436 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1437 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1438 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1439 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1440 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1441 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1442 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1443 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1444 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1445 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1446 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1447 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1448 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1449 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1450 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1451 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1452 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1453 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1454 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1455 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1456 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1457 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1458 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1459 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1460 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1461 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1462 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1463 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1464 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1465 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1466 (prefix_table): Add EXxEVexR to FMA table entries.
1467 (OP_Rounding): Move abort() invocation.
1468 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1469 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1470 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1471 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1472 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1473 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1474 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1475 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1476 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1477 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1479 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1480 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1481 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1482 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1483 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1484 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1485 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1486 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1487 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1488 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1489 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1490 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1491 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1492 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1493 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1494 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1495 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1496 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1497 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1498 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1499 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1500 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1501 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1502 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1503 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1504 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1505 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1506 Delete table entries.
1507 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1508 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1509 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1512 2020-07-06 Jan Beulich <jbeulich@suse.com>
1514 * i386-dis.c (EXqScalarS): Delete.
1515 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1516 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1518 2020-07-06 Jan Beulich <jbeulich@suse.com>
1520 * i386-dis.c (safe-ctype.h): Include.
1521 (EXdScalar, EXqScalar): Delete.
1522 (d_scalar_mode, q_scalar_mode): Delete.
1523 (prefix_table, vex_len_table): Use EXxmm_md in place of
1524 EXdScalar and EXxmm_mq in place of EXqScalar.
1525 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1526 d_scalar_mode and q_scalar_mode.
1527 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1528 (vmovsd): Use EXxmm_mq.
1530 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1533 * arc-dis.c: Fix spelling mistake.
1534 * po/opcodes.pot: Regenerate.
1536 2020-07-06 Nick Clifton <nickc@redhat.com>
1538 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1539 * po/uk.po: Updated Ukranian translation.
1541 2020-07-04 Nick Clifton <nickc@redhat.com>
1543 * configure: Regenerate.
1544 * po/opcodes.pot: Regenerate.
1546 2020-07-04 Nick Clifton <nickc@redhat.com>
1548 Binutils 2.35 branch created.
1550 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1552 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1553 * i386-opc.h (VexSwapSources): New.
1554 (i386_opcode_modifier): Add vexswapsources.
1555 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1556 with two source operands swapped.
1557 * i386-tbl.h: Regenerated.
1559 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1561 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1562 unprivileged CSR can also be initialized.
1564 2020-06-29 Alan Modra <amodra@gmail.com>
1566 * arm-dis.c: Use C style comments.
1567 * cr16-opc.c: Likewise.
1568 * ft32-dis.c: Likewise.
1569 * moxie-opc.c: Likewise.
1570 * tic54x-dis.c: Likewise.
1571 * s12z-opc.c: Remove useless comment.
1572 * xgate-dis.c: Likewise.
1574 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1576 * i386-opc.tbl: Add a blank line.
1578 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1580 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1581 (VecSIB128): Renamed to ...
1583 (VecSIB256): Renamed to ...
1585 (VecSIB512): Renamed to ...
1587 (VecSIB): Renamed to ...
1589 (i386_opcode_modifier): Replace vecsib with sib.
1590 * i386-opc.tbl (VecSIB128): New.
1591 (VecSIB256): Likewise.
1592 (VecSIB512): Likewise.
1593 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1594 and VecSIB512, respectively.
1596 2020-06-26 Jan Beulich <jbeulich@suse.com>
1598 * i386-dis.c: Adjust description of I macro.
1599 (x86_64_table): Drop use of I.
1600 (float_mem): Replace use of I.
1601 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1603 2020-06-26 Jan Beulich <jbeulich@suse.com>
1605 * i386-dis.c: (print_insn): Avoid straight assignment to
1606 priv.orig_sizeflag when processing -M sub-options.
1608 2020-06-25 Jan Beulich <jbeulich@suse.com>
1610 * i386-dis.c: Adjust description of J macro.
1611 (dis386, x86_64_table, mod_table): Replace J.
1612 (putop): Remove handling of J.
1614 2020-06-25 Jan Beulich <jbeulich@suse.com>
1616 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1618 2020-06-25 Jan Beulich <jbeulich@suse.com>
1620 * i386-dis.c: Adjust description of "LQ" macro.
1621 (dis386_twobyte): Use LQ for sysret.
1622 (putop): Adjust handling of LQ.
1624 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1626 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1627 * riscv-dis.c: Include elfxx-riscv.h.
1629 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1631 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1633 2020-06-17 Lili Cui <lili.cui@intel.com>
1635 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1637 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1640 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1641 * i386-opc.tbl: Likewise.
1642 * i386-tbl.h: Regenerated.
1644 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1646 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1648 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1650 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1651 (SR_CORE): Likewise.
1652 (SR_FEAT): Likewise.
1654 (SR_V8_1): Likewise.
1655 (SR_V8_2): Likewise.
1656 (SR_V8_3): Likewise.
1657 (SR_V8_4): Likewise.
1660 (SR_SSBS): Likewise.
1662 (SR_ID_PFR2): Likewise.
1663 (SR_PROFILE): Likewise.
1664 (SR_MEMTAG): Likewise.
1665 (SR_SCXTNUM): Likewise.
1666 (aarch64_sys_regs): Refactor to store feature information in the table.
1667 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1668 that now describe their own features.
1669 (aarch64_pstatefield_supported_p): Likewise.
1671 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1673 * i386-dis.c (prefix_table): Fix a typo in comments.
1675 2020-06-09 Jan Beulich <jbeulich@suse.com>
1677 * i386-dis.c (rex_ignored): Delete.
1678 (ckprefix): Drop rex_ignored initialization.
1679 (get_valid_dis386): Drop setting of rex_ignored.
1680 (print_insn): Drop checking of rex_ignored. Don't record data
1681 size prefix as used with VEX-and-alike encodings.
1683 2020-06-09 Jan Beulich <jbeulich@suse.com>
1685 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1686 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1687 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1688 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1689 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1690 VEX_0F12, and VEX_0F16.
1691 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1692 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1693 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1694 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1695 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1696 MOD_VEX_0F16_PREFIX_2 entries.
1698 2020-06-09 Jan Beulich <jbeulich@suse.com>
1700 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1701 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1702 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1703 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1704 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1705 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1706 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1707 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1708 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1709 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1710 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1711 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1712 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1713 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1714 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1715 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1716 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1717 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1718 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1719 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1720 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1721 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1722 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1723 EVEX_W_0FC6_P_2): Delete.
1724 (print_insn): Add EVEX.W vs embedded prefix consistency check
1725 to prefix validation.
1726 * i386-dis-evex.h (evex_table): Don't further descend for
1727 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1728 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1730 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1731 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1732 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1733 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1734 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1735 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1736 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1737 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1738 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1739 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1740 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1741 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1742 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1743 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1744 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1745 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1746 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1747 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1748 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1749 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1750 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1751 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1752 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1753 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1754 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1755 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1756 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1758 2020-06-09 Jan Beulich <jbeulich@suse.com>
1760 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1761 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1762 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1764 (print_insn): Drop pointless check against bad_opcode. Split
1765 prefix validation into legacy and VEX-and-alike parts.
1766 (putop): Re-work 'X' macro handling.
1768 2020-06-09 Jan Beulich <jbeulich@suse.com>
1770 * i386-dis.c (MOD_0F51): Rename to ...
1771 (MOD_0F50): ... this.
1773 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1775 * arm-dis.c (arm_opcodes): Add dfb.
1776 (thumb32_opcodes): Add dfb.
1778 2020-06-08 Jan Beulich <jbeulich@suse.com>
1780 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1782 2020-06-06 Alan Modra <amodra@gmail.com>
1784 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1786 2020-06-05 Alan Modra <amodra@gmail.com>
1788 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1789 size is large enough.
1791 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1793 * disassemble.c (disassemble_init_for_target): Set endian_code for
1795 * bpf-desc.c: Regenerate.
1796 * bpf-opc.c: Likewise.
1797 * bpf-dis.c: Likewise.
1799 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1801 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1802 (cgen_put_insn_value): Likewise.
1803 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1804 * cgen-dis.in (print_insn): Likewise.
1805 * cgen-ibld.in (insert_1): Likewise.
1806 (insert_1): Likewise.
1807 (insert_insn_normal): Likewise.
1808 (extract_1): Likewise.
1809 * bpf-dis.c: Regenerate.
1810 * bpf-ibld.c: Likewise.
1811 * bpf-ibld.c: Likewise.
1812 * cgen-dis.in: Likewise.
1813 * cgen-ibld.in: Likewise.
1814 * cgen-opc.c: Likewise.
1815 * epiphany-dis.c: Likewise.
1816 * epiphany-ibld.c: Likewise.
1817 * fr30-dis.c: Likewise.
1818 * fr30-ibld.c: Likewise.
1819 * frv-dis.c: Likewise.
1820 * frv-ibld.c: Likewise.
1821 * ip2k-dis.c: Likewise.
1822 * ip2k-ibld.c: Likewise.
1823 * iq2000-dis.c: Likewise.
1824 * iq2000-ibld.c: Likewise.
1825 * lm32-dis.c: Likewise.
1826 * lm32-ibld.c: Likewise.
1827 * m32c-dis.c: Likewise.
1828 * m32c-ibld.c: Likewise.
1829 * m32r-dis.c: Likewise.
1830 * m32r-ibld.c: Likewise.
1831 * mep-dis.c: Likewise.
1832 * mep-ibld.c: Likewise.
1833 * mt-dis.c: Likewise.
1834 * mt-ibld.c: Likewise.
1835 * or1k-dis.c: Likewise.
1836 * or1k-ibld.c: Likewise.
1837 * xc16x-dis.c: Likewise.
1838 * xc16x-ibld.c: Likewise.
1839 * xstormy16-dis.c: Likewise.
1840 * xstormy16-ibld.c: Likewise.
1842 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1844 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1845 (print_insn_): Handle instruction endian.
1846 * bpf-dis.c: Regenerate.
1847 * bpf-desc.c: Regenerate.
1848 * epiphany-dis.c: Likewise.
1849 * epiphany-desc.c: Likewise.
1850 * fr30-dis.c: Likewise.
1851 * fr30-desc.c: Likewise.
1852 * frv-dis.c: Likewise.
1853 * frv-desc.c: Likewise.
1854 * ip2k-dis.c: Likewise.
1855 * ip2k-desc.c: Likewise.
1856 * iq2000-dis.c: Likewise.
1857 * iq2000-desc.c: Likewise.
1858 * lm32-dis.c: Likewise.
1859 * lm32-desc.c: Likewise.
1860 * m32c-dis.c: Likewise.
1861 * m32c-desc.c: Likewise.
1862 * m32r-dis.c: Likewise.
1863 * m32r-desc.c: Likewise.
1864 * mep-dis.c: Likewise.
1865 * mep-desc.c: Likewise.
1866 * mt-dis.c: Likewise.
1867 * mt-desc.c: Likewise.
1868 * or1k-dis.c: Likewise.
1869 * or1k-desc.c: Likewise.
1870 * xc16x-dis.c: Likewise.
1871 * xc16x-desc.c: Likewise.
1872 * xstormy16-dis.c: Likewise.
1873 * xstormy16-desc.c: Likewise.
1875 2020-06-03 Nick Clifton <nickc@redhat.com>
1877 * po/sr.po: Updated Serbian translation.
1879 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1881 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1882 (riscv_get_priv_spec_class): Likewise.
1884 2020-06-01 Alan Modra <amodra@gmail.com>
1886 * bpf-desc.c: Regenerate.
1888 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1889 David Faust <david.faust@oracle.com>
1891 * bpf-desc.c: Regenerate.
1892 * bpf-opc.h: Likewise.
1893 * bpf-opc.c: Likewise.
1894 * bpf-dis.c: Likewise.
1896 2020-05-28 Alan Modra <amodra@gmail.com>
1898 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1901 2020-05-28 Alan Modra <amodra@gmail.com>
1903 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1905 (print_insn_ns32k): Revert last change.
1907 2020-05-28 Nick Clifton <nickc@redhat.com>
1909 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1912 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1914 Fix extraction of signed constants in nios2 disassembler (again).
1916 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1917 extractions of signed fields.
1919 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1921 * s390-opc.txt: Relocate vector load/store instructions with
1922 additional alignment parameter and change architecture level
1923 constraint from z14 to z13.
1925 2020-05-21 Alan Modra <amodra@gmail.com>
1927 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1928 * sparc-dis.c: Likewise.
1929 * tic4x-dis.c: Likewise.
1930 * xtensa-dis.c: Likewise.
1931 * bpf-desc.c: Regenerate.
1932 * epiphany-desc.c: Regenerate.
1933 * fr30-desc.c: Regenerate.
1934 * frv-desc.c: Regenerate.
1935 * ip2k-desc.c: Regenerate.
1936 * iq2000-desc.c: Regenerate.
1937 * lm32-desc.c: Regenerate.
1938 * m32c-desc.c: Regenerate.
1939 * m32r-desc.c: Regenerate.
1940 * mep-asm.c: Regenerate.
1941 * mep-desc.c: Regenerate.
1942 * mt-desc.c: Regenerate.
1943 * or1k-desc.c: Regenerate.
1944 * xc16x-desc.c: Regenerate.
1945 * xstormy16-desc.c: Regenerate.
1947 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1949 * riscv-opc.c (riscv_ext_version_table): The table used to store
1950 all information about the supported spec and the corresponding ISA
1951 versions. Currently, only Zicsr is supported to verify the
1952 correctness of Z sub extension settings. Others will be supported
1953 in the future patches.
1954 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1955 classes and the corresponding strings.
1956 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1957 spec class by giving a ISA spec string.
1958 * riscv-opc.c (struct priv_spec_t): New structure.
1959 (struct priv_spec_t priv_specs): List for all supported privilege spec
1960 classes and the corresponding strings.
1961 (riscv_get_priv_spec_class): New function. Get the corresponding
1962 privilege spec class by giving a spec string.
1963 (riscv_get_priv_spec_name): New function. Get the corresponding
1964 privilege spec string by giving a CSR version class.
1965 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1966 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1967 according to the chosen version. Build a hash table riscv_csr_hash to
1968 store the valid CSR for the chosen pirv verison. Dump the direct
1969 CSR address rather than it's name if it is invalid.
1970 (parse_riscv_dis_option_without_args): New function. Parse the options
1972 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1973 parse the options without arguments first, and then handle the options
1974 with arguments. Add the new option -Mpriv-spec, which has argument.
1975 * riscv-dis.c (print_riscv_disassembler_options): Add description
1976 about the new OBJDUMP option.
1978 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1980 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1981 WC values on POWER10 sync, dcbf and wait instructions.
1982 (insert_pl, extract_pl): New functions.
1983 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1984 (LS3): New , 3-bit L for sync.
1985 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1986 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1987 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1988 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1989 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1990 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1991 <wait>: Enable PL operand on POWER10.
1992 <dcbf>: Enable L3OPT operand on POWER10.
1993 <sync>: Enable SC2 operand on POWER10.
1995 2020-05-19 Stafford Horne <shorne@gmail.com>
1998 * or1k-asm.c: Regenerate.
1999 * or1k-desc.c: Regenerate.
2000 * or1k-desc.h: Regenerate.
2001 * or1k-dis.c: Regenerate.
2002 * or1k-ibld.c: Regenerate.
2003 * or1k-opc.c: Regenerate.
2004 * or1k-opc.h: Regenerate.
2005 * or1k-opinst.c: Regenerate.
2007 2020-05-11 Alan Modra <amodra@gmail.com>
2009 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2012 2020-05-11 Alan Modra <amodra@gmail.com>
2014 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2015 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2017 2020-05-11 Alan Modra <amodra@gmail.com>
2019 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2021 2020-05-11 Alan Modra <amodra@gmail.com>
2023 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2024 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2026 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2028 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2031 2020-05-11 Alan Modra <amodra@gmail.com>
2033 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2034 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2035 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2036 (prefix_opcodes): Add xxeval.
2038 2020-05-11 Alan Modra <amodra@gmail.com>
2040 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2041 xxgenpcvwm, xxgenpcvdm.
2043 2020-05-11 Alan Modra <amodra@gmail.com>
2045 * ppc-opc.c (MP, VXVAM_MASK): Define.
2046 (VXVAPS_MASK): Use VXVA_MASK.
2047 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2048 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2049 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2050 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2052 2020-05-11 Alan Modra <amodra@gmail.com>
2053 Peter Bergner <bergner@linux.ibm.com>
2055 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2057 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2058 YMSK2, XA6a, XA6ap, XB6a entries.
2059 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2060 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2062 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2063 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2064 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2065 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2066 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2067 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2068 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2069 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2070 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2071 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2072 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2073 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2074 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2075 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2077 2020-05-11 Alan Modra <amodra@gmail.com>
2079 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2080 (insert_xts, extract_xts): New functions.
2081 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2082 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2083 (VXRC_MASK, VXSH_MASK): Define.
2084 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2085 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2086 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2087 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2088 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2089 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2090 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2092 2020-05-11 Alan Modra <amodra@gmail.com>
2094 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2095 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2096 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2097 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2098 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2100 2020-05-11 Alan Modra <amodra@gmail.com>
2102 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2103 (XTP, DQXP, DQXP_MASK): Define.
2104 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2105 (prefix_opcodes): Add plxvp and pstxvp.
2107 2020-05-11 Alan Modra <amodra@gmail.com>
2109 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2110 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2111 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2113 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2115 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2117 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2119 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2121 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2123 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2125 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2127 2020-05-11 Alan Modra <amodra@gmail.com>
2129 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2131 2020-05-11 Alan Modra <amodra@gmail.com>
2133 * ppc-dis.c (ppc_opts): Add "power10" entry.
2134 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2135 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2137 2020-05-11 Nick Clifton <nickc@redhat.com>
2139 * po/fr.po: Updated French translation.
2141 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2143 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2144 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2145 (operand_general_constraint_met_p): validate
2146 AARCH64_OPND_UNDEFINED.
2147 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2149 * aarch64-asm-2.c: Regenerated.
2150 * aarch64-dis-2.c: Regenerated.
2151 * aarch64-opc-2.c: Regenerated.
2153 2020-04-29 Nick Clifton <nickc@redhat.com>
2156 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2159 2020-04-29 Nick Clifton <nickc@redhat.com>
2161 * po/sv.po: Updated Swedish translation.
2163 2020-04-29 Nick Clifton <nickc@redhat.com>
2166 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2167 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2168 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2171 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2174 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2175 cmpi only on m68020up and cpu32.
2177 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2179 * aarch64-asm.c (aarch64_ins_none): New.
2180 * aarch64-asm.h (ins_none): New declaration.
2181 * aarch64-dis.c (aarch64_ext_none): New.
2182 * aarch64-dis.h (ext_none): New declaration.
2183 * aarch64-opc.c (aarch64_print_operand): Update case for
2184 AARCH64_OPND_BARRIER_PSB.
2185 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2186 (AARCH64_OPERANDS): Update inserter/extracter for
2187 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2188 * aarch64-asm-2.c: Regenerated.
2189 * aarch64-dis-2.c: Regenerated.
2190 * aarch64-opc-2.c: Regenerated.
2192 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2194 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2195 (aarch64_feature_ras, RAS): Likewise.
2196 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2197 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2198 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2199 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2200 * aarch64-asm-2.c: Regenerated.
2201 * aarch64-dis-2.c: Regenerated.
2202 * aarch64-opc-2.c: Regenerated.
2204 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2206 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2207 (print_insn_neon): Support disassembly of conditional
2210 2020-02-16 David Faust <david.faust@oracle.com>
2212 * bpf-desc.c: Regenerate.
2213 * bpf-desc.h: Likewise.
2214 * bpf-opc.c: Regenerate.
2215 * bpf-opc.h: Likewise.
2217 2020-04-07 Lili Cui <lili.cui@intel.com>
2219 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2220 (prefix_table): New instructions (see prefixes above).
2221 (rm_table): Likewise
2222 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2223 CPU_ANY_TSXLDTRK_FLAGS.
2224 (cpu_flags): Add CpuTSXLDTRK.
2225 * i386-opc.h (enum): Add CpuTSXLDTRK.
2226 (i386_cpu_flags): Add cputsxldtrk.
2227 * i386-opc.tbl: Add XSUSPLDTRK insns.
2228 * i386-init.h: Regenerate.
2229 * i386-tbl.h: Likewise.
2231 2020-04-02 Lili Cui <lili.cui@intel.com>
2233 * i386-dis.c (prefix_table): New instructions serialize.
2234 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2235 CPU_ANY_SERIALIZE_FLAGS.
2236 (cpu_flags): Add CpuSERIALIZE.
2237 * i386-opc.h (enum): Add CpuSERIALIZE.
2238 (i386_cpu_flags): Add cpuserialize.
2239 * i386-opc.tbl: Add SERIALIZE insns.
2240 * i386-init.h: Regenerate.
2241 * i386-tbl.h: Likewise.
2243 2020-03-26 Alan Modra <amodra@gmail.com>
2245 * disassemble.h (opcodes_assert): Declare.
2246 (OPCODES_ASSERT): Define.
2247 * disassemble.c: Don't include assert.h. Include opintl.h.
2248 (opcodes_assert): New function.
2249 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2250 (bfd_h8_disassemble): Reduce size of data array. Correctly
2251 calculate maxlen. Omit insn decoding when insn length exceeds
2252 maxlen. Exit from nibble loop when looking for E, before
2253 accessing next data byte. Move processing of E outside loop.
2254 Replace tests of maxlen in loop with assertions.
2256 2020-03-26 Alan Modra <amodra@gmail.com>
2258 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2260 2020-03-25 Alan Modra <amodra@gmail.com>
2262 * z80-dis.c (suffix): Init mybuf.
2264 2020-03-22 Alan Modra <amodra@gmail.com>
2266 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2267 successflly read from section.
2269 2020-03-22 Alan Modra <amodra@gmail.com>
2271 * arc-dis.c (find_format): Use ISO C string concatenation rather
2272 than line continuation within a string. Don't access needs_limm
2273 before testing opcode != NULL.
2275 2020-03-22 Alan Modra <amodra@gmail.com>
2277 * ns32k-dis.c (print_insn_arg): Update comment.
2278 (print_insn_ns32k): Reduce size of index_offset array, and
2279 initialize, passing -1 to print_insn_arg for args that are not
2280 an index. Don't exit arg loop early. Abort on bad arg number.
2282 2020-03-22 Alan Modra <amodra@gmail.com>
2284 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2285 * s12z-opc.c: Formatting.
2286 (operands_f): Return an int.
2287 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2288 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2289 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2290 (exg_sex_discrim): Likewise.
2291 (create_immediate_operand, create_bitfield_operand),
2292 (create_register_operand_with_size, create_register_all_operand),
2293 (create_register_all16_operand, create_simple_memory_operand),
2294 (create_memory_operand, create_memory_auto_operand): Don't
2295 segfault on malloc failure.
2296 (z_ext24_decode): Return an int status, negative on fail, zero
2298 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2299 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2300 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2301 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2302 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2303 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2304 (loop_primitive_decode, shift_decode, psh_pul_decode),
2305 (bit_field_decode): Similarly.
2306 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2307 to return value, update callers.
2308 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2309 Don't segfault on NULL operand.
2310 (decode_operation): Return OP_INVALID on first fail.
2311 (decode_s12z): Check all reads, returning -1 on fail.
2313 2020-03-20 Alan Modra <amodra@gmail.com>
2315 * metag-dis.c (print_insn_metag): Don't ignore status from
2318 2020-03-20 Alan Modra <amodra@gmail.com>
2320 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2321 Initialize parts of buffer not written when handling a possible
2322 2-byte insn at end of section. Don't attempt decoding of such
2323 an insn by the 4-byte machinery.
2325 2020-03-20 Alan Modra <amodra@gmail.com>
2327 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2328 partially filled buffer. Prevent lookup of 4-byte insns when
2329 only VLE 2-byte insns are possible due to section size. Print
2330 ".word" rather than ".long" for 2-byte leftovers.
2332 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2335 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2337 2020-03-13 Jan Beulich <jbeulich@suse.com>
2339 * i386-dis.c (X86_64_0D): Rename to ...
2340 (X86_64_0E): ... this.
2342 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2344 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2345 * Makefile.in: Regenerated.
2347 2020-03-09 Jan Beulich <jbeulich@suse.com>
2349 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2351 * i386-tbl.h: Re-generate.
2353 2020-03-09 Jan Beulich <jbeulich@suse.com>
2355 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2356 vprot*, vpsha*, and vpshl*.
2357 * i386-tbl.h: Re-generate.
2359 2020-03-09 Jan Beulich <jbeulich@suse.com>
2361 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2362 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2363 * i386-tbl.h: Re-generate.
2365 2020-03-09 Jan Beulich <jbeulich@suse.com>
2367 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2368 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2369 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2370 * i386-tbl.h: Re-generate.
2372 2020-03-09 Jan Beulich <jbeulich@suse.com>
2374 * i386-gen.c (struct template_arg, struct template_instance,
2375 struct template_param, struct template, templates,
2376 parse_template, expand_templates): New.
2377 (process_i386_opcodes): Various local variables moved to
2378 expand_templates. Call parse_template and expand_templates.
2379 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2380 * i386-tbl.h: Re-generate.
2382 2020-03-06 Jan Beulich <jbeulich@suse.com>
2384 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2385 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2386 register and memory source templates. Replace VexW= by VexW*
2388 * i386-tbl.h: Re-generate.
2390 2020-03-06 Jan Beulich <jbeulich@suse.com>
2392 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2393 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2394 * i386-tbl.h: Re-generate.
2396 2020-03-06 Jan Beulich <jbeulich@suse.com>
2398 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2399 * i386-tbl.h: Re-generate.
2401 2020-03-06 Jan Beulich <jbeulich@suse.com>
2403 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2404 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2405 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2406 VexW0 on SSE2AVX variants.
2407 (vmovq): Drop NoRex64 from XMM/XMM variants.
2408 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2409 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2410 applicable use VexW0.
2411 * i386-tbl.h: Re-generate.
2413 2020-03-06 Jan Beulich <jbeulich@suse.com>
2415 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2416 * i386-opc.h (Rex64): Delete.
2417 (struct i386_opcode_modifier): Remove rex64 field.
2418 * i386-opc.tbl (crc32): Drop Rex64.
2419 Replace Rex64 with Size64 everywhere else.
2420 * i386-tbl.h: Re-generate.
2422 2020-03-06 Jan Beulich <jbeulich@suse.com>
2424 * i386-dis.c (OP_E_memory): Exclude recording of used address
2425 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2426 addressed memory operands for MPX insns.
2428 2020-03-06 Jan Beulich <jbeulich@suse.com>
2430 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2431 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2432 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2433 (ptwrite): Split into non-64-bit and 64-bit forms.
2434 * i386-tbl.h: Re-generate.
2436 2020-03-06 Jan Beulich <jbeulich@suse.com>
2438 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2440 * i386-tbl.h: Re-generate.
2442 2020-03-04 Jan Beulich <jbeulich@suse.com>
2444 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2445 (prefix_table): Move vmmcall here. Add vmgexit.
2446 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2447 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2448 (cpu_flags): Add CpuSEV_ES entry.
2449 * i386-opc.h (CpuSEV_ES): New.
2450 (union i386_cpu_flags): Add cpusev_es field.
2451 * i386-opc.tbl (vmgexit): New.
2452 * i386-init.h, i386-tbl.h: Re-generate.
2454 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2456 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2458 * i386-opc.h (IGNORESIZE): New.
2459 (DEFAULTSIZE): Likewise.
2460 (IgnoreSize): Removed.
2461 (DefaultSize): Likewise.
2462 (MnemonicSize): New.
2463 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2465 * i386-opc.tbl (IgnoreSize): New.
2466 (DefaultSize): Likewise.
2467 * i386-tbl.h: Regenerated.
2469 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2472 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2475 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2478 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2479 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2480 * i386-tbl.h: Regenerated.
2482 2020-02-26 Alan Modra <amodra@gmail.com>
2484 * aarch64-asm.c: Indent labels correctly.
2485 * aarch64-dis.c: Likewise.
2486 * aarch64-gen.c: Likewise.
2487 * aarch64-opc.c: Likewise.
2488 * alpha-dis.c: Likewise.
2489 * i386-dis.c: Likewise.
2490 * nds32-asm.c: Likewise.
2491 * nfp-dis.c: Likewise.
2492 * visium-dis.c: Likewise.
2494 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2496 * arc-regs.h (int_vector_base): Make it available for all ARC
2499 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2501 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2504 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2506 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2507 c.mv/c.li if rs1 is zero.
2509 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2511 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2512 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2514 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2515 * i386-opc.h (CpuABM): Removed.
2517 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2518 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2519 popcnt. Remove CpuABM from lzcnt.
2520 * i386-init.h: Regenerated.
2521 * i386-tbl.h: Likewise.
2523 2020-02-17 Jan Beulich <jbeulich@suse.com>
2525 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2526 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2527 VexW1 instead of open-coding them.
2528 * i386-tbl.h: Re-generate.
2530 2020-02-17 Jan Beulich <jbeulich@suse.com>
2532 * i386-opc.tbl (AddrPrefixOpReg): Define.
2533 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2534 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2535 templates. Drop NoRex64.
2536 * i386-tbl.h: Re-generate.
2538 2020-02-17 Jan Beulich <jbeulich@suse.com>
2541 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2542 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2543 into Intel syntax instance (with Unpsecified) and AT&T one
2545 (vcvtneps2bf16): Likewise, along with folding the two so far
2547 * i386-tbl.h: Re-generate.
2549 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2551 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2552 CPU_ANY_SSE4A_FLAGS.
2554 2020-02-17 Alan Modra <amodra@gmail.com>
2556 * i386-gen.c (cpu_flag_init): Correct last change.
2558 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2560 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2563 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2565 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2568 2020-02-14 Jan Beulich <jbeulich@suse.com>
2571 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2572 destination for Cpu64-only variant.
2573 (movzx): Fold patterns.
2574 * i386-tbl.h: Re-generate.
2576 2020-02-13 Jan Beulich <jbeulich@suse.com>
2578 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2579 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2580 CPU_ANY_SSE4_FLAGS entry.
2581 * i386-init.h: Re-generate.
2583 2020-02-12 Jan Beulich <jbeulich@suse.com>
2585 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2586 with Unspecified, making the present one AT&T syntax only.
2587 * i386-tbl.h: Re-generate.
2589 2020-02-12 Jan Beulich <jbeulich@suse.com>
2591 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2592 * i386-tbl.h: Re-generate.
2594 2020-02-12 Jan Beulich <jbeulich@suse.com>
2597 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2598 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2599 Amd64 and Intel64 templates.
2600 (call, jmp): Likewise for far indirect variants. Dro
2602 * i386-tbl.h: Re-generate.
2604 2020-02-11 Jan Beulich <jbeulich@suse.com>
2606 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2607 * i386-opc.h (ShortForm): Delete.
2608 (struct i386_opcode_modifier): Remove shortform field.
2609 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2610 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2611 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2612 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2614 * i386-tbl.h: Re-generate.
2616 2020-02-11 Jan Beulich <jbeulich@suse.com>
2618 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2619 fucompi): Drop ShortForm from operand-less templates.
2620 * i386-tbl.h: Re-generate.
2622 2020-02-11 Alan Modra <amodra@gmail.com>
2624 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2625 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2626 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2627 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2628 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2630 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2632 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2633 (cde_opcodes): Add VCX* instructions.
2635 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2636 Matthew Malcomson <matthew.malcomson@arm.com>
2638 * arm-dis.c (struct cdeopcode32): New.
2639 (CDE_OPCODE): New macro.
2640 (cde_opcodes): New disassembly table.
2641 (regnames): New option to table.
2642 (cde_coprocs): New global variable.
2643 (print_insn_cde): New
2644 (print_insn_thumb32): Use print_insn_cde.
2645 (parse_arm_disassembler_options): Parse coprocN args.
2647 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2650 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2652 * i386-opc.h (AMD64): Removed.
2653 (Intel64): Likewose.
2655 (INTEL64): Likewise.
2656 (INTEL64ONLY): Likewise.
2657 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2658 * i386-opc.tbl (Amd64): New.
2659 (Intel64): Likewise.
2660 (Intel64Only): Likewise.
2661 Replace AMD64 with Amd64. Update sysenter/sysenter with
2662 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2663 * i386-tbl.h: Regenerated.
2665 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2668 * z80-dis.c: Add support for GBZ80 opcodes.
2670 2020-02-04 Alan Modra <amodra@gmail.com>
2672 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2674 2020-02-03 Alan Modra <amodra@gmail.com>
2676 * m32c-ibld.c: Regenerate.
2678 2020-02-01 Alan Modra <amodra@gmail.com>
2680 * frv-ibld.c: Regenerate.
2682 2020-01-31 Jan Beulich <jbeulich@suse.com>
2684 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2685 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2686 (OP_E_memory): Replace xmm_mdq_mode case label by
2687 vex_scalar_w_dq_mode one.
2688 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2690 2020-01-31 Jan Beulich <jbeulich@suse.com>
2692 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2693 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2694 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2695 (intel_operand_size): Drop vex_w_dq_mode case label.
2697 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2699 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2700 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2702 2020-01-30 Alan Modra <amodra@gmail.com>
2704 * m32c-ibld.c: Regenerate.
2706 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2708 * bpf-opc.c: Regenerate.
2710 2020-01-30 Jan Beulich <jbeulich@suse.com>
2712 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2713 (dis386): Use them to replace C2/C3 table entries.
2714 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2715 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2716 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2717 * i386-tbl.h: Re-generate.
2719 2020-01-30 Jan Beulich <jbeulich@suse.com>
2721 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2723 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2725 * i386-tbl.h: Re-generate.
2727 2020-01-30 Alan Modra <amodra@gmail.com>
2729 * tic4x-dis.c (tic4x_dp): Make unsigned.
2731 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2732 Jan Beulich <jbeulich@suse.com>
2735 * i386-dis.c (MOVSXD_Fixup): New function.
2736 (movsxd_mode): New enum.
2737 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2738 (intel_operand_size): Handle movsxd_mode.
2739 (OP_E_register): Likewise.
2741 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2742 register on movsxd. Add movsxd with 16-bit destination register
2743 for AMD64 and Intel64 ISAs.
2744 * i386-tbl.h: Regenerated.
2746 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2749 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2750 * aarch64-asm-2.c: Regenerate
2751 * aarch64-dis-2.c: Likewise.
2752 * aarch64-opc-2.c: Likewise.
2754 2020-01-21 Jan Beulich <jbeulich@suse.com>
2756 * i386-opc.tbl (sysret): Drop DefaultSize.
2757 * i386-tbl.h: Re-generate.
2759 2020-01-21 Jan Beulich <jbeulich@suse.com>
2761 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2763 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2764 * i386-tbl.h: Re-generate.
2766 2020-01-20 Nick Clifton <nickc@redhat.com>
2768 * po/de.po: Updated German translation.
2769 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2770 * po/uk.po: Updated Ukranian translation.
2772 2020-01-20 Alan Modra <amodra@gmail.com>
2774 * hppa-dis.c (fput_const): Remove useless cast.
2776 2020-01-20 Alan Modra <amodra@gmail.com>
2778 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2780 2020-01-18 Nick Clifton <nickc@redhat.com>
2782 * configure: Regenerate.
2783 * po/opcodes.pot: Regenerate.
2785 2020-01-18 Nick Clifton <nickc@redhat.com>
2787 Binutils 2.34 branch created.
2789 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2791 * opintl.h: Fix spelling error (seperate).
2793 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2795 * i386-opc.tbl: Add {vex} pseudo prefix.
2796 * i386-tbl.h: Regenerated.
2798 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2801 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2802 (neon_opcodes): Likewise.
2803 (select_arm_features): Make sure we enable MVE bits when selecting
2804 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2807 2020-01-16 Jan Beulich <jbeulich@suse.com>
2809 * i386-opc.tbl: Drop stale comment from XOP section.
2811 2020-01-16 Jan Beulich <jbeulich@suse.com>
2813 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2814 (extractps): Add VexWIG to SSE2AVX forms.
2815 * i386-tbl.h: Re-generate.
2817 2020-01-16 Jan Beulich <jbeulich@suse.com>
2819 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2820 Size64 from and use VexW1 on SSE2AVX forms.
2821 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2822 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2823 * i386-tbl.h: Re-generate.
2825 2020-01-15 Alan Modra <amodra@gmail.com>
2827 * tic4x-dis.c (tic4x_version): Make unsigned long.
2828 (optab, optab_special, registernames): New file scope vars.
2829 (tic4x_print_register): Set up registernames rather than
2830 malloc'd registertable.
2831 (tic4x_disassemble): Delete optable and optable_special. Use
2832 optab and optab_special instead. Throw away old optab,
2833 optab_special and registernames when info->mach changes.
2835 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2838 * z80-dis.c (suffix): Use .db instruction to generate double
2841 2020-01-14 Alan Modra <amodra@gmail.com>
2843 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2844 values to unsigned before shifting.
2846 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2848 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2850 (print_insn_thumb16, print_insn_thumb32): Likewise.
2851 (print_insn): Initialize the insn info.
2852 * i386-dis.c (print_insn): Initialize the insn info fields, and
2855 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2857 * arc-opc.c (C_NE): Make it required.
2859 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2861 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2862 reserved register name.
2864 2020-01-13 Alan Modra <amodra@gmail.com>
2866 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2867 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2869 2020-01-13 Alan Modra <amodra@gmail.com>
2871 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2872 result of wasm_read_leb128 in a uint64_t and check that bits
2873 are not lost when copying to other locals. Use uint32_t for
2874 most locals. Use PRId64 when printing int64_t.
2876 2020-01-13 Alan Modra <amodra@gmail.com>
2878 * score-dis.c: Formatting.
2879 * score7-dis.c: Formatting.
2881 2020-01-13 Alan Modra <amodra@gmail.com>
2883 * score-dis.c (print_insn_score48): Use unsigned variables for
2884 unsigned values. Don't left shift negative values.
2885 (print_insn_score32): Likewise.
2886 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2888 2020-01-13 Alan Modra <amodra@gmail.com>
2890 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2892 2020-01-13 Alan Modra <amodra@gmail.com>
2894 * fr30-ibld.c: Regenerate.
2896 2020-01-13 Alan Modra <amodra@gmail.com>
2898 * xgate-dis.c (print_insn): Don't left shift signed value.
2899 (ripBits): Formatting, use 1u.
2901 2020-01-10 Alan Modra <amodra@gmail.com>
2903 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2904 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2906 2020-01-10 Alan Modra <amodra@gmail.com>
2908 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2909 and XRREG value earlier to avoid a shift with negative exponent.
2910 * m10200-dis.c (disassemble): Similarly.
2912 2020-01-09 Nick Clifton <nickc@redhat.com>
2915 * z80-dis.c (ld_ii_ii): Use correct cast.
2917 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2920 * z80-dis.c (ld_ii_ii): Use character constant when checking
2923 2020-01-09 Jan Beulich <jbeulich@suse.com>
2925 * i386-dis.c (SEP_Fixup): New.
2927 (dis386_twobyte): Use it for sysenter/sysexit.
2928 (enum x86_64_isa): Change amd64 enumerator to value 1.
2929 (OP_J): Compare isa64 against intel64 instead of amd64.
2930 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2932 * i386-tbl.h: Re-generate.
2934 2020-01-08 Alan Modra <amodra@gmail.com>
2936 * z8k-dis.c: Include libiberty.h
2937 (instr_data_s): Make max_fetched unsigned.
2938 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2939 Don't exceed byte_info bounds.
2940 (output_instr): Make num_bytes unsigned.
2941 (unpack_instr): Likewise for nibl_count and loop.
2942 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2944 * z8k-opc.h: Regenerate.
2946 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2948 * arc-tbl.h (llock): Use 'LLOCK' as class.
2950 (scond): Use 'SCOND' as class.
2952 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2955 2020-01-06 Alan Modra <amodra@gmail.com>
2957 * m32c-ibld.c: Regenerate.
2959 2020-01-06 Alan Modra <amodra@gmail.com>
2962 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2963 Peek at next byte to prevent recursion on repeated prefix bytes.
2964 Ensure uninitialised "mybuf" is not accessed.
2965 (print_insn_z80): Don't zero n_fetch and n_used here,..
2966 (print_insn_z80_buf): ..do it here instead.
2968 2020-01-04 Alan Modra <amodra@gmail.com>
2970 * m32r-ibld.c: Regenerate.
2972 2020-01-04 Alan Modra <amodra@gmail.com>
2974 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2976 2020-01-04 Alan Modra <amodra@gmail.com>
2978 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2980 2020-01-04 Alan Modra <amodra@gmail.com>
2982 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2984 2020-01-03 Jan Beulich <jbeulich@suse.com>
2986 * aarch64-tbl.h (aarch64_opcode_table): Use
2987 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2989 2020-01-03 Jan Beulich <jbeulich@suse.com>
2991 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2992 forms of SUDOT and USDOT.
2994 2020-01-03 Jan Beulich <jbeulich@suse.com>
2996 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2998 * aarch64-dis-2.c: Re-generate.
3000 2020-01-03 Jan Beulich <jbeulich@suse.com>
3002 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3004 * aarch64-dis-2.c: Re-generate.
3006 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3008 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3010 2020-01-01 Alan Modra <amodra@gmail.com>
3012 Update year range in copyright notice of all files.
3014 For older changes see ChangeLog-2019
3016 Copyright (C) 2020 Free Software Foundation, Inc.
3018 Copying and distribution of this file, with or without modification,
3019 are permitted in any medium without royalty provided the copyright
3020 notice and this notice are preserved.
3026 version-control: never
projects / thirdparty / binutils-gdb.git / blob