opcodes/ChangeLog

   1 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
   2
   3         PR binutils/21446
   4         * aarch64-asm.c (opintl.h): Include.
   5         (aarch64_ins_sysreg): Enforce read/write constraints.
   6         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
   7         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
   8         (F_REG_READ, F_REG_WRITE): New.
   9         * aarch64-opc.c (aarch64_print_operand): Generate notes for
  10         AARCH64_OPND_SYSREG.
  11         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
  12         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
  13         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
  14         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
  15         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
  16         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
  17         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
  18         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
  19         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
  20         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
  21         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
  22         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
  23         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
  24         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
  25         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
  26         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
  27         msr (F_SYS_WRITE), mrs (F_SYS_READ).
  28
  29 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  30
  31         PR binutils/21446
  32         * aarch64-dis.c (no_notes: New.
  33         (parse_aarch64_dis_option): Support notes.
  34         (aarch64_decode_insn, print_operands): Likewise.
  35         (print_aarch64_disassembler_options): Document notes.
  36         * aarch64-opc.c (aarch64_print_operand): Support notes.
  37
  38 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  39
  40         PR binutils/21446
  41         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
  42         and take error struct.
  43         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
  44         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
  45         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
  46         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
  47         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
  48         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
  49         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
  50         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
  51         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
  52         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
  53         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
  54         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
  55         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
  56         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
  57         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
  58         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
  59         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
  60         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  61         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
  62         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
  63         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
  64         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
  65         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
  66         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
  67         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
  68         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
  69         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
  70         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
  71         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
  72         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
  73         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
  74         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
  75         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
  76         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
  77         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
  78         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
  79         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
  80         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
  81         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
  82         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
  83         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
  84         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
  85         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
  86         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  87         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
  88         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
  89         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
  90         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
  91         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
  92         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
  93         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
  94         (determine_disassembling_preference, aarch64_decode_insn,
  95         print_insn_aarch64_word, print_insn_data): Take errors struct.
  96         (print_insn_aarch64): Use errors.
  97         * aarch64-asm-2.c: Regenerate.
  98         * aarch64-dis-2.c: Regenerate.
  99         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 100         boolean in aarch64_insert_operan.
 101         (print_operand_extractor): Likewise.
 102         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 103
 104 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 105
 106         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 107
 108 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 111
 112 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 113
 114         * cr16-opc.c (cr16_instruction): Comment typo fix.
 115         * hppa-dis.c (print_insn_hppa): Likewise.
 116
 117 2018-05-08  Jim Wilson  <jimw@sifive.com>
 118
 119         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 120         (match_c_slli64, match_srxi_as_c_srxi): New.
 121         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 122         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 123         <c.slli, c.srli, c.srai>: Use match_s_slli.
 124         <c.slli64, c.srli64, c.srai64>: New.
 125
 126 2018-05-08  Alan Modra  <amodra@gmail.com>
 127
 128         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 129         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 130         partition opcode space for index lookup.
 131
 132 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 133
 134         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 135         <insn_length>: ...with this.  Update usage.
 136         Remove duplicate call to *info->memory_error_func.
 137
 138 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 139             H.J. Lu  <hongjiu.lu@intel.com>
 140
 141         * i386-dis.c (Gva): New.
 142         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 143         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 144         (prefix_table): New instructions (see prefix above).
 145         (mod_table): New instructions (see prefix above).
 146         (OP_G): Handle va_mode.
 147         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 148         CPU_MOVDIR64B_FLAGS.
 149         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 150         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 151         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 152         * i386-opc.tbl: Add movidir{i,64b}.
 153         * i386-init.h: Regenerated.
 154         * i386-tbl.h: Likewise.
 155
 156 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 159         AddrPrefixOpReg.
 160         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 161         (AddrPrefixOpReg): This.
 162         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 163         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 164
 165 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 166
 167         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 168         (vle_num_opcodes): Likewise.
 169         (spe2_num_opcodes): Likewise.
 170         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 171         initialization loop.
 172         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 173         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 174         only once.
 175
 176 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 177
 178         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 179
 180 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 181
 182         Makefile.am: Added nfp-dis.c.
 183         configure.ac: Added bfd_nfp_arch.
 184         disassemble.h: Added print_insn_nfp prototype.
 185         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 186         nfp-dis.c: New, for NFP support.
 187         po/POTFILES.in: Added nfp-dis.c to the list.
 188         Makefile.in: Regenerate.
 189         configure: Regenerate.
 190
 191 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 194         templates into their base ones.
 195         * i386-tlb.h: Re-generate.
 196
 197 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 200         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 201         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 202         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 203         * i386-init.h: Re-generate.
 204
 205 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 208         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 209         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 210         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 211         comment.
 212         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 213         and CpuRegMask.
 214         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 215         CpuRegMask: Delete.
 216         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 217         cpuregzmm, and cpuregmask.
 218         * i386-init.h: Re-generate.
 219         * i386-tbl.h: Re-generate.
 220
 221 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 224         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 225         * i386-init.h: Re-generate.
 226
 227 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-gen.c (VexImmExt): Delete.
 230         * i386-opc.h (VexImmExt, veximmext): Delete.
 231         * i386-opc.tbl: Drop all VexImmExt uses.
 232         * i386-tlb.h: Re-generate.
 233
 234 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 237         register-only forms.
 238         * i386-tlb.h: Re-generate.
 239
 240 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 241
 242         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 243
 244 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 245
 246         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 247         PREFIX_0F1C.
 248         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 249         (cpu_flags): Add CpuCLDEMOTE.
 250         * i386-init.h: Regenerate.
 251         * i386-opc.h (enum): Add CpuCLDEMOTE,
 252         (i386_cpu_flags): Add cpucldemote.
 253         * i386-opc.tbl: Add cldemote.
 254         * i386-tbl.h: Regenerate.
 255
 256 2018-04-16  Alan Modra  <amodra@gmail.com>
 257
 258         * Makefile.am: Remove sh5 and sh64 support.
 259         * configure.ac: Likewise.
 260         * disassemble.c: Likewise.
 261         * disassemble.h: Likewise.
 262         * sh-dis.c: Likewise.
 263         * sh64-dis.c: Delete.
 264         * sh64-opc.c: Delete.
 265         * sh64-opc.h: Delete.
 266         * Makefile.in: Regenerate.
 267         * configure: Regenerate.
 268         * po/POTFILES.in: Regenerate.
 269
 270 2018-04-16  Alan Modra  <amodra@gmail.com>
 271
 272         * Makefile.am: Remove w65 support.
 273         * configure.ac: Likewise.
 274         * disassemble.c: Likewise.
 275         * disassemble.h: Likewise.
 276         * w65-dis.c: Delete.
 277         * w65-opc.h: Delete.
 278         * Makefile.in: Regenerate.
 279         * configure: Regenerate.
 280         * po/POTFILES.in: Regenerate.
 281
 282 2018-04-16  Alan Modra  <amodra@gmail.com>
 283
 284         * configure.ac: Remove we32k support.
 285         * configure: Regenerate.
 286
 287 2018-04-16  Alan Modra  <amodra@gmail.com>
 288
 289         * Makefile.am: Remove m88k support.
 290         * configure.ac: Likewise.
 291         * disassemble.c: Likewise.
 292         * disassemble.h: Likewise.
 293         * m88k-dis.c: Delete.
 294         * Makefile.in: Regenerate.
 295         * configure: Regenerate.
 296         * po/POTFILES.in: Regenerate.
 297
 298 2018-04-16  Alan Modra  <amodra@gmail.com>
 299
 300         * Makefile.am: Remove i370 support.
 301         * configure.ac: Likewise.
 302         * disassemble.c: Likewise.
 303         * disassemble.h: Likewise.
 304         * i370-dis.c: Delete.
 305         * i370-opc.c: Delete.
 306         * Makefile.in: Regenerate.
 307         * configure: Regenerate.
 308         * po/POTFILES.in: Regenerate.
 309
 310 2018-04-16  Alan Modra  <amodra@gmail.com>
 311
 312         * Makefile.am: Remove h8500 support.
 313         * configure.ac: Likewise.
 314         * disassemble.c: Likewise.
 315         * disassemble.h: Likewise.
 316         * h8500-dis.c: Delete.
 317         * h8500-opc.h: Delete.
 318         * Makefile.in: Regenerate.
 319         * configure: Regenerate.
 320         * po/POTFILES.in: Regenerate.
 321
 322 2018-04-16  Alan Modra  <amodra@gmail.com>
 323
 324         * configure.ac: Remove tahoe support.
 325         * configure: Regenerate.
 326
 327 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 328
 329         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 330         umwait.
 331         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 332         64-bit mode.
 333         * i386-tbl.h: Regenerated.
 334
 335 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 336
 337         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 338         PREFIX_MOD_1_0FAE_REG_6.
 339         (va_mode): New.
 340         (OP_E_register): Use va_mode.
 341         * i386-dis-evex.h (prefix_table):
 342         New instructions (see prefixes above).
 343         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 344         (cpu_flags): Likewise.
 345         * i386-opc.h (enum): Likewise.
 346         (i386_cpu_flags): Likewise.
 347         * i386-opc.tbl: Add umonitor, umwait, tpause.
 348         * i386-init.h: Regenerate.
 349         * i386-tbl.h: Likewise.
 350
 351 2018-04-11  Alan Modra  <amodra@gmail.com>
 352
 353         * opcodes/i860-dis.c: Delete.
 354         * opcodes/i960-dis.c: Delete.
 355         * Makefile.am: Remove i860 and i960 support.
 356         * configure.ac: Likewise.
 357         * disassemble.c: Likewise.
 358         * disassemble.h: Likewise.
 359         * Makefile.in: Regenerate.
 360         * configure: Regenerate.
 361         * po/POTFILES.in: Regenerate.
 362
 363 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         PR binutils/23025
 366         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 367         to 0.
 368         (print_insn): Clear vex instead of vex.evex.
 369
 370 2018-04-04  Nick Clifton  <nickc@redhat.com>
 371
 372         * po/es.po: Updated Spanish translation.
 373
 374 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-gen.c (opcode_modifiers): Delete VecESize.
 377         * i386-opc.h (VecESize): Delete.
 378         (struct i386_opcode_modifier): Delete vecesize.
 379         * i386-opc.tbl: Drop VecESize.
 380         * i386-tlb.h: Re-generate.
 381
 382 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 385         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 386         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 387         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 388         * i386-tlb.h: Re-generate.
 389
 390 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 393         Fold AVX512 forms
 394         * i386-tlb.h: Re-generate.
 395
 396 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 397
 398         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 399         (vex_len_table): Drop Y for vcvt*2si.
 400         (putop): Replace plain 'Y' handling by abort().
 401
 402 2018-03-28  Nick Clifton  <nickc@redhat.com>
 403
 404         PR 22988
 405         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 406         instructions with only a base address register.
 407         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 408         handle AARHC64_OPND_SVE_ADDR_R.
 409         (aarch64_print_operand): Likewise.
 410         * aarch64-asm-2.c: Regenerate.
 411         * aarch64_dis-2.c: Regenerate.
 412         * aarch64-opc-2.c: Regenerate.
 413
 414 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl: Drop VecESize from register only insn forms and
 417         memory forms not allowing broadcast.
 418         * i386-tlb.h: Re-generate.
 419
 420 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 423         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 424         sha256*): Drop Disp<N>.
 425
 426 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-dis.c (EbndS, bnd_swap_mode): New.
 429         (prefix_table): Use EbndS.
 430         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 431         * i386-opc.tbl (bndmov): Move misplaced Load.
 432         * i386-tlb.h: Re-generate.
 433
 434 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 437         templates allowing memory operands and folded ones for register
 438         only flavors.
 439         * i386-tlb.h: Re-generate.
 440
 441 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 444         256-bit templates. Drop redundant leftover Disp<N>.
 445         * i386-tlb.h: Re-generate.
 446
 447 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 448
 449         * riscv-opc.c (riscv_insn_types): New.
 450
 451 2018-03-13  Nick Clifton  <nickc@redhat.com>
 452
 453         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 454
 455 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386-opc.tbl: Add Optimize to clr.
 458         * i386-tbl.h: Regenerated.
 459
 460 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 463         * i386-opc.h (OldGcc): Removed.
 464         (i386_opcode_modifier): Remove oldgcc.
 465         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 466         instructions for old (<= 2.8.1) versions of gcc.
 467         * i386-tbl.h: Regenerated.
 468
 469 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-opc.h (EVEXDYN): New.
 472         * i386-opc.tbl: Fold various AVX512VL templates.
 473         * i386-tlb.h: Re-generate.
 474
 475 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 478         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 479         vpexpandd, vpexpandq): Fold AFX512VF templates.
 480         * i386-tlb.h: Re-generate.
 481
 482 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 485         Fold 128- and 256-bit VEX-encoded templates.
 486         * i386-tlb.h: Re-generate.
 487
 488 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 491         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 492         vpexpandd, vpexpandq): Fold AVX512F templates.
 493         * i386-tlb.h: Re-generate.
 494
 495 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 498         64-bit templates. Drop Disp<N>.
 499         * i386-tlb.h: Re-generate.
 500
 501 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 504         and 256-bit templates.
 505         * i386-tlb.h: Re-generate.
 506
 507 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 510         * i386-tlb.h: Re-generate.
 511
 512 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 515         Drop NoAVX.
 516         * i386-tlb.h: Re-generate.
 517
 518 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 521         * i386-tlb.h: Re-generate.
 522
 523 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-gen.c (opcode_modifiers): Delete FloatD.
 526         * i386-opc.h (FloatD): Delete.
 527         (struct i386_opcode_modifier): Delete floatd.
 528         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 529         FloatD by D.
 530         * i386-tlb.h: Re-generate.
 531
 532 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 535
 536 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 539         * i386-tlb.h: Re-generate.
 540
 541 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 544         forms.
 545         * i386-tlb.h: Re-generate.
 546
 547 2018-03-07  Alan Modra  <amodra@gmail.com>
 548
 549         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 550         bfd_arch_rs6000.
 551         * disassemble.h (print_insn_rs6000): Delete.
 552         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 553         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 554         (print_insn_rs6000): Delete.
 555
 556 2018-03-03  Alan Modra  <amodra@gmail.com>
 557
 558         * sysdep.h (opcodes_error_handler): Define.
 559         (_bfd_error_handler): Declare.
 560         * Makefile.am: Remove stray #.
 561         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 562         EDIT" comment.
 563         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 564         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 565         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 566         opcodes_error_handler to print errors.  Standardize error messages.
 567         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 568         and include opintl.h.
 569         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 570         * i386-gen.c: Standardize error messages.
 571         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 572         * Makefile.in: Regenerate.
 573         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 574         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 575         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 576         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 577         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 578         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 579         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 580         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 581         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 582         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 583         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 584         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 585         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 586
 587 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 590         vpsub[bwdq] instructions.
 591         * i386-tbl.h: Regenerated.
 592
 593 2018-03-01  Alan Modra  <amodra@gmail.com>
 594
 595         * configure.ac (ALL_LINGUAS): Sort.
 596         * configure: Regenerate.
 597
 598 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 599
 600         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 601         macro by assignements.
 602
 603 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR gas/22871
 606         * i386-gen.c (opcode_modifiers): Add Optimize.
 607         * i386-opc.h (Optimize): New enum.
 608         (i386_opcode_modifier): Add optimize.
 609         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 610         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 611         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 612         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 613         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 614         vpxord and vpxorq.
 615         * i386-tbl.h: Regenerated.
 616
 617 2018-02-26  Alan Modra  <amodra@gmail.com>
 618
 619         * crx-dis.c (getregliststring): Allocate a large enough buffer
 620         to silence false positive gcc8 warning.
 621
 622 2018-02-22  Shea Levy <shea@shealevy.com>
 623
 624         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 625
 626 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         * i386-opc.tbl: Add {rex},
 629         * i386-tbl.h: Regenerated.
 630
 631 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 632
 633         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 634         (mips16_opcodes): Replace `M' with `m' for "restore".
 635
 636 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 637
 638         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 639
 640 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 641
 642         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 643         variable to `function_index'.
 644
 645 2018-02-13  Nick Clifton  <nickc@redhat.com>
 646
 647         PR 22823
 648         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 649         about truncation of printing.
 650
 651 2018-02-12  Henry Wong <henry@stuffedcow.net>
 652
 653         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 654
 655 2018-02-05  Nick Clifton  <nickc@redhat.com>
 656
 657         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 658
 659 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 660
 661         * i386-dis.c (enum): Add pconfig.
 662         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 663         (cpu_flags): Add CpuPCONFIG.
 664         * i386-opc.h (enum): Add CpuPCONFIG.
 665         (i386_cpu_flags): Add cpupconfig.
 666         * i386-opc.tbl: Add PCONFIG instruction.
 667         * i386-init.h: Regenerate.
 668         * i386-tbl.h: Likewise.
 669
 670 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 671
 672         * i386-dis.c (enum): Add PREFIX_0F09.
 673         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 674         (cpu_flags): Add CpuWBNOINVD.
 675         * i386-opc.h (enum): Add CpuWBNOINVD.
 676         (i386_cpu_flags): Add cpuwbnoinvd.
 677         * i386-opc.tbl: Add WBNOINVD instruction.
 678         * i386-init.h: Regenerate.
 679         * i386-tbl.h: Likewise.
 680
 681 2018-01-17  Jim Wilson  <jimw@sifive.com>
 682
 683         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 684
 685 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 686
 687         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 688         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 689         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 690         (cpu_flags): Add CpuIBT, CpuSHSTK.
 691         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 692         (i386_cpu_flags): Add cpuibt, cpushstk.
 693         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 694         * i386-init.h: Regenerate.
 695         * i386-tbl.h: Likewise.
 696
 697 2018-01-16  Nick Clifton  <nickc@redhat.com>
 698
 699         * po/pt_BR.po: Updated Brazilian Portugese translation.
 700         * po/de.po: Updated German translation.
 701
 702 2018-01-15  Jim Wilson  <jimw@sifive.com>
 703
 704         * riscv-opc.c (match_c_nop): New.
 705         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 706
 707 2018-01-15  Nick Clifton  <nickc@redhat.com>
 708
 709         * po/uk.po: Updated Ukranian translation.
 710
 711 2018-01-13  Nick Clifton  <nickc@redhat.com>
 712
 713         * po/opcodes.pot: Regenerated.
 714
 715 2018-01-13  Nick Clifton  <nickc@redhat.com>
 716
 717         * configure: Regenerate.
 718
 719 2018-01-13  Nick Clifton  <nickc@redhat.com>
 720
 721         2.30 branch created.
 722
 723 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 724
 725         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 726         * i386-tbl.h: Regenerate.
 727
 728 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 731         * i386-tbl.h: Re-generate.
 732
 733 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 736         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 737         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 738         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 739         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 740         Disp8MemShift of AVX512VL forms.
 741         * i386-tbl.h: Re-generate.
 742
 743 2018-01-09  Jim Wilson  <jimw@sifive.com>
 744
 745         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 746         then the hi_addr value is zero.
 747
 748 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 749
 750         * arm-dis.c (arm_opcodes): Add csdb.
 751         (thumb32_opcodes): Add csdb.
 752
 753 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 754
 755         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 756         * aarch64-asm-2.c: Regenerate.
 757         * aarch64-dis-2.c: Regenerate.
 758         * aarch64-opc-2.c: Regenerate.
 759
 760 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 761
 762         PR gas/22681
 763         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 764         Remove AVX512 vmovd with 64-bit operands.
 765         * i386-tbl.h: Regenerated.
 766
 767 2018-01-05  Jim Wilson  <jimw@sifive.com>
 768
 769         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 770         jalr.
 771
 772 2018-01-03  Alan Modra  <amodra@gmail.com>
 773
 774         Update year range in copyright notice of all files.
 775
 776 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 779         and OPERAND_TYPE_REGZMM entries.
 780
 781 For older changes see ChangeLog-2017
 782 \f
 783 Copyright (C) 2018 Free Software Foundation, Inc.
 784
 785 Copying and distribution of this file, with or without modification,
 786 are permitted in any medium without royalty provided the copyright
 787 notice and this notice are preserved.
 788
 789 Local Variables:
 790 mode: change-log
 791 left-margin: 8
 792 fill-column: 74
 793 version-control: never
 794 End: