1 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
3 * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
4 (LS64): Handler with +ls64 feature flags.
5 (_LS64_INSN): New instruction group macro.
6 (struct aarch64_opcode): Add LS64 instructions.
7 * aarch64-asm-2.c: Regenerated.
8 * aarch64-dis-2.c: Regenerated.
9 * aarch64-opc-2.c: Regenerated.
11 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
13 * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
14 * aarch64-asm-2.c: Regenerated.
15 * aarch64-dis-2.c: Regenerated.
16 * aarch64-opc-2.c: Regenerated.
18 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
20 * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
21 * aarch64-tbl.h (CSRE): New CSRE feature handler.
22 (_CSRE_INSN): New CSRE instruction type.
23 (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
24 * aarch64-asm-2.c: Regenerated.
25 * aarch64-dis-2.c: Regenerated.
26 * aarch64-opc-2.c: Regenerated.
28 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
30 * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
31 and operand description.
32 * aarch64-asm-2.c: Regenerated.
33 * aarch64-dis-2.c: Regenerated.
34 * aarch64-opc-2.c: Regenerated.
36 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
38 * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
40 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
42 * csky-dis.c (csky_output_operand): Add handler for
43 OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
44 * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
45 (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
46 some instructions for VDSPV1.
48 2020-10-26 Lili Cui <lili.cui@intel.com>
50 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
52 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
54 * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
55 * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
57 * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
58 * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
60 * aarch64-opc.c (aarch64_print_operand): New options table
61 aarch64_barrier_dsb_nxs_options.
62 * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
63 * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
64 Armv8.7-a instruction.
65 * aarch64-asm-2.c: Regenerated.
66 * aarch64-dis-2.c: Regenerated.
67 * aarch64-opc-2.c: Regenerated.
69 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
71 * po/es.po: Remove the duplicated entry.
73 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
75 * po/es.po: Fix printf format.
77 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
79 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
80 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
81 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
83 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
84 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
85 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
87 * i386-init.h: Re-generated.
88 * i386-tbl.h: Re-generated.
90 2020-10-16 Lili Cui <lili.cui@intel.com>
92 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
93 and move it from cpu_flags to opcode_modifiers.
94 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
95 * i386-gen.c: Likewise.
96 * i386-opc.h: Likewise.
97 * i386-opc.h: Likewise.
98 * i386-init.h: Regenerated.
99 * i386-tbl.h: Likewise.
101 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
103 * aarch64-tbl.h (ARMV8_7): New macro.
105 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
106 Lili Cui <lili.cui@intel.com>
108 * i386-dis.c (PREFIX_VEX_0F3850): New.
109 (PREFIX_VEX_0F3851): Likewise.
110 (PREFIX_VEX_0F3852): Likewise.
111 (PREFIX_VEX_0F3853): Likewise.
112 (VEX_W_0F3850_P_2): Likewise.
113 (VEX_W_0F3851_P_2): Likewise.
114 (VEX_W_0F3852_P_2): Likewise.
115 (VEX_W_0F3853_P_2): Likewise.
116 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
117 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
118 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
119 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
120 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
121 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
122 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
123 CPU_ANY_AVX_VNNI_FLAGS.
124 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
125 * i386-opc.h (CpuAVX_VNNI): New.
126 (CpuVEX_PREFIX): Likewise.
127 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
128 * i386-opc.tbl: Add Intel AVX VNNI instructions.
129 * i386-init.h: Regenerated.
130 * i386-tbl.h: Likewise.
132 2020-10-14 Lili Cui <lili.cui@intel.com>
133 H.J. Lu <hongjiu.lu@intel.com>
135 * i386-dis.c (PREFIX_0F3A0F): New.
136 (MOD_0F3A0F_PREFIX_1): Likewise.
137 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
138 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
139 (prefix_table): Add PREFIX_0F3A0F.
140 (mod_table): Add MOD_0F3A0F_PREFIX_1.
141 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
142 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
143 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
144 CPU_ANY_HRESET_FLAGS.
145 (cpu_flags): Add CpuHRESET.
146 (output_i386_opcode): Allow 4 byte base_opcode.
147 * i386-opc.h (enum): Add CpuHRESET.
148 (i386_cpu_flags): Add cpuhreset.
149 * i386-opc.tbl: Add Intel HRESET instruction.
150 * i386-init.h: Regenerate.
151 * i386-tbl.h: Likewise.
153 2020-10-14 Lili Cui <lili.cui@intel.com>
155 * i386-dis.c (enum): Add
156 PREFIX_MOD_3_0F01_REG_5_RM_4,
157 PREFIX_MOD_3_0F01_REG_5_RM_5,
158 PREFIX_MOD_3_0F01_REG_5_RM_6,
159 PREFIX_MOD_3_0F01_REG_5_RM_7,
160 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
161 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
162 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
163 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
164 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
165 (prefix_table): New instructions (see prefixes above).
167 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
169 (cpu_flags): Add CpuUINTR.
170 * i386-opc.h (enum): Add CpuUINTR.
171 (i386_cpu_flags): Add cpuuintr.
172 * i386-opc.tbl: Add UINTR insns.
173 * i386-init.h: Regenerate.
174 * i386-tbl.h: Likewise.
176 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
178 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
179 non-VEX/EVEX/prefix encoding.
180 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
182 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
183 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
184 * i386-tbl.h: Regenerated.
186 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
188 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
190 * i386-opc.h (VexOpcode): Renamed to ...
191 (OpcodePrefix): This.
193 (PREFIX_0X66): Likewise.
194 (PREFIX_0XF2): Likewise.
195 (PREFIX_0XF3): Likewise.
196 * i386-opc.tbl (Prefix_0X66): New.
197 (Prefix_0XF2): Likewise.
198 (Prefix_0XF3): Likewise.
199 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
200 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
201 * i386-tbl.h: Regenerated.
203 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
205 * aarch64-opc.c: Add BRBE system registers.
207 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
209 * aarch64-opc.c: New CSRE system registers defined.
211 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
213 * cgen-asm.c: Fix spelling mistakes.
214 * cgen-dis.c: Fix spelling mistakes.
215 * tic30-dis.c: Fix spelling mistakes.
217 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
220 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
222 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
225 * i386-dis.c (print_insn): Clear modrm if not needed.
226 (putop): Check need_modrm for modrm.mod != 3. Don't check
227 need_modrm for modrm.mod == 3.
229 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
231 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
232 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
233 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
234 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
235 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
236 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
237 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
238 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
239 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
240 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
241 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
242 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
243 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
244 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
246 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
248 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
250 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
252 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
253 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
255 2020-09-26 Alan Modra <amodra@gmail.com>
257 * csky-opc.h: Formatting.
258 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
259 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
261 (get_register_number): Likewise.
262 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
264 2020-09-24 Lili Cui <lili.cui@intel.com>
267 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
269 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
271 * csky-dis.c (csky_output_operand): Enclose body of if in curly
274 2020-09-24 Lili Cui <lili.cui@intel.com>
276 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
277 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
278 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
279 X86_64_0F01_REG_1_RM_7_P_2.
280 (prefix_table): Likewise.
281 (x86_64_table): Likewise.
282 (rm_table): Likewise.
283 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
284 and CPU_ANY_TDX_FLAGS.
285 (cpu_flags): Add CpuTDX.
286 * i386-opc.h (enum): Add CpuTDX.
287 (i386_cpu_flags): Add cputdx.
288 * i386-opc.tbl: Add TDX insns.
289 * i386-init.h: Regenerate.
290 * i386-tbl.h: Likewise.
292 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
294 * csky-dis.c (using_abi): New.
295 (parse_csky_dis_options): New function.
296 (get_gr_name): New function.
297 (get_cr_name): New function.
298 (csky_output_operand): Use get_gr_name and get_cr_name to
299 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
300 (print_insn_csky): Parse disassembler options.
301 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
302 (GENARAL_REG_BANK): Define.
303 (REG_SUPPORT_ALL): Define.
304 (REG_SUPPORT_ALL): New.
306 (REG_SUPPORT_A): Define.
307 (REG_SUPPORT_B): Define.
308 (REG_SUPPORT_C): Define.
309 (REG_SUPPORT_D): Define.
310 (REG_SUPPORT_E): Define.
311 (csky_abiv1_general_regs): New.
312 (csky_abiv1_control_regs): New.
313 (csky_abiv2_general_regs): New.
314 (csky_abiv2_control_regs): New.
315 (get_register_name): New function.
316 (get_register_number): New function.
317 (csky_get_general_reg_name): New function.
318 (csky_get_general_regno): New function.
319 (csky_get_control_reg_name): New function.
320 (csky_get_control_regno): New function.
321 (csky_v2_opcodes): Prefer two oprerans format for bclri and
322 bseti, strengthen the operands legality check of addc, zext
325 2020-09-23 Lili Cui <lili.cui@intel.com>
327 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
328 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
329 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
330 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
331 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
332 (reg_table): New instructions (see prefixes above).
333 (prefix_table): Likewise.
334 (three_byte_table): Likewise.
335 (mod_table): Likewise
336 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
337 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
338 (cpu_flags): Likewise.
339 (operand_type_init): Likewise.
340 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
341 (i386_cpu_flags): Add cpukl and cpuwide_kl.
342 * i386-opc.tbl: Add KL and WIDE_KL insns.
343 * i386-init.h: Regenerate.
344 * i386-tbl.h: Likewise.
346 2020-09-21 Alan Modra <amodra@gmail.com>
348 * rx-dis.c (flag_names): Add missing comma.
349 (register_names, flag_names, double_register_names),
350 (double_register_high_names, double_register_low_names),
351 (double_control_register_names, double_condition_names): Remove
354 2020-09-18 David Faust <david.faust@oracle.com>
356 * bpf-desc.c: Regenerate.
357 * bpf-desc.h: Likewise.
358 * bpf-opc.c: Likewise.
359 * bpf-opc.h: Likewise.
361 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
363 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
366 2020-09-16 Alan Modra <amodra@gmail.com>
368 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
370 2020-09-10 Nick Clifton <nickc@redhat.com>
372 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
373 for hidden, local, no-type symbols.
374 (disassemble_init_powerpc): Point the symbol_is_valid field in the
375 info structure at the new function.
377 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
379 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
380 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
383 2020-09-10 Nick Clifton <nickc@redhat.com>
385 * csky-dis.c (csky_output_operand): Coerce the immediate values to
386 long before printing.
388 2020-09-10 Alan Modra <amodra@gmail.com>
390 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
392 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
394 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
397 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
399 * csky-dis.c (csky_output_operand): Add handlers for
400 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
401 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
402 to support FPUV3 instructions.
403 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
404 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
405 OPRND_TYPE_DFLOAT_FMOVI.
406 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
407 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
408 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
409 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
410 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
411 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
412 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
413 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
414 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
415 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
416 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
417 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
418 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
419 (csky_v2_opcodes): Add FPUV3 instructions.
421 2020-09-08 Alex Coplan <alex.coplan@arm.com>
423 * aarch64-dis.c (print_operands): Pass CPU features to
424 aarch64_print_operand().
425 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
426 preferred disassembly of system registers.
427 (SR_RNG): Refactor to use new SR_FEAT2 macro.
433 (SR_EXPAND_ELx): New.
434 (SR_EXPAND_EL12): New.
435 (aarch64_sys_regs): Specify which registers are only on
436 A-profile, add R-profile system registers.
440 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
443 2020-09-08 Alex Coplan <alex.coplan@arm.com>
445 * aarch64-tbl.h (aarch64_feature_v8_r): New.
448 (aarch64_opcode_table): Add dfb.
449 * aarch64-opc-2.c: Regenerate.
450 * aarch64-asm-2.c: Regenerate.
451 * aarch64-dis-2.c: Regenerate.
453 2020-09-08 Alex Coplan <alex.coplan@arm.com>
455 * aarch64-dis.c (arch_variant): New.
456 (determine_disassembling_preference): Disassemble according to
458 (select_aarch64_variant): New.
459 (print_insn_aarch64): Set feature set.
461 2020-09-02 Alan Modra <amodra@gmail.com>
463 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
464 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
465 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
466 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
467 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
468 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
469 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
470 for value parameter and update code to suit.
471 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
472 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
474 2020-09-02 Alan Modra <amodra@gmail.com>
476 * i386-dis.c (OP_E_memory): Don't cast to signed type when
478 (get32, get32s): Use unsigned types in shift expressions.
480 2020-09-02 Alan Modra <amodra@gmail.com>
482 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
484 2020-09-02 Alan Modra <amodra@gmail.com>
486 * crx-dis.c: Whitespace.
487 (print_arg): Use unsigned type for longdisp and mask variables,
488 and for left shift constant.
490 2020-09-02 Alan Modra <amodra@gmail.com>
492 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
493 * bpf-ibld.c: Regenerate.
494 * epiphany-ibld.c: Regenerate.
495 * fr30-ibld.c: Regenerate.
496 * frv-ibld.c: Regenerate.
497 * ip2k-ibld.c: Regenerate.
498 * iq2000-ibld.c: Regenerate.
499 * lm32-ibld.c: Regenerate.
500 * m32c-ibld.c: Regenerate.
501 * m32r-ibld.c: Regenerate.
502 * mep-ibld.c: Regenerate.
503 * mt-ibld.c: Regenerate.
504 * or1k-ibld.c: Regenerate.
505 * xc16x-ibld.c: Regenerate.
506 * xstormy16-ibld.c: Regenerate.
508 2020-09-02 Alan Modra <amodra@gmail.com>
510 * bfin-dis.c (MASKBITS): Use SIGNBIT.
512 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
514 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
515 to CSKYV2_ISA_3E3R3 instruction set.
517 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
519 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
521 2020-09-01 Alan Modra <amodra@gmail.com>
523 * mep-ibld.c: Regenerate.
525 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
527 * csky-dis.c (csky_output_operand): Assign dis_info.value for
530 2020-08-30 Alan Modra <amodra@gmail.com>
532 * cr16-dis.c: Formatting.
533 (parameter): Delete struct typedef. Use dwordU instead
535 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
537 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
539 2020-08-29 Alan Modra <amodra@gmail.com>
542 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
543 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
545 2020-08-28 Alan Modra <amodra@gmail.com>
549 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
550 (extract_normal): Likewise.
551 (insert_normal): Likewise, and move past zero length test.
552 (put_insn_int_value): Handle mask for zero length, use 1UL.
553 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
554 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
555 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
556 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
558 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
560 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
561 (csky_dis_info): Add member isa.
562 (csky_find_inst_info): Skip instructions that do not belong to
564 (csky_get_disassembler): Get infomation from attribute section.
565 (print_insn_csky): Set defualt ISA flag.
566 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
567 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
568 isa_flag32'type to unsigned 64 bits.
570 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
572 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
574 2020-08-26 David Faust <david.faust@oracle.com>
576 * bpf-desc.c: Regenerate.
577 * bpf-desc.h: Likewise.
578 * bpf-opc.c: Likewise.
579 * bpf-opc.h: Likewise.
580 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
581 ISA when appropriate.
583 2020-08-25 Alan Modra <amodra@gmail.com>
586 * vax-dis.c (parse_disassembler_options): Always add at least one
587 to entry_addr_total_slots.
589 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
591 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
592 in other CPUs to speed up disassembling.
593 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
594 Change plsli.u16 to plsli.16, change sync's operand format.
596 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
598 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
600 2020-08-21 Nick Clifton <nickc@redhat.com>
602 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
605 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
607 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
609 2020-08-19 Alan Modra <amodra@gmail.com>
611 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
614 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
616 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
617 <xvcvbf16spn>: ...to this.
619 2020-08-12 Alex Coplan <alex.coplan@arm.com>
621 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
623 2020-08-12 Nick Clifton <nickc@redhat.com>
625 * po/sr.po: Updated Serbian translation.
627 2020-08-11 Alan Modra <amodra@gmail.com>
629 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
631 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
633 * aarch64-opc.c (aarch64_print_operand):
634 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
635 (aarch64_sys_reg_supported_p): Function removed.
636 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
637 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
640 2020-08-10 Alan Modra <amodra@gmail.com>
642 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
645 2020-08-10 Alan Modra <amodra@gmail.com>
647 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
648 Enable icbt for power5, miso for power8.
650 2020-08-10 Alan Modra <amodra@gmail.com>
652 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
653 mtvsrd, and similarly for mfvsrd.
655 2020-08-04 Christian Groessler <chris@groessler.org>
656 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
658 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
659 opcodes (special "out" to absolute address).
660 * z8k-opc.h: Regenerate.
662 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
665 * i386-opc.h (Prefix_Disp8): New.
666 (Prefix_Disp16): Likewise.
667 (Prefix_Disp32): Likewise.
668 (Prefix_Load): Likewise.
669 (Prefix_Store): Likewise.
670 (Prefix_VEX): Likewise.
671 (Prefix_VEX3): Likewise.
672 (Prefix_EVEX): Likewise.
673 (Prefix_REX): Likewise.
674 (Prefix_NoOptimize): Likewise.
675 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
676 * i386-tbl.h: Regenerated.
678 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
680 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
681 default case with abort() instead of printing an error message and
682 continuing, to avoid a maybe-uninitialized warning.
684 2020-07-24 Nick Clifton <nickc@redhat.com>
686 * po/de.po: Updated German translation.
688 2020-07-21 Jan Beulich <jbeulich@suse.com>
690 * i386-dis.c (OP_E_memory): Revert previous change.
692 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
695 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
696 without base nor index registers.
698 2020-07-15 Jan Beulich <jbeulich@suse.com>
700 * i386-dis.c (putop): Move 'V' and 'W' handling.
702 2020-07-15 Jan Beulich <jbeulich@suse.com>
704 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
705 construct for push/pop of register.
706 (putop): Honor cond when handling 'P'. Drop handling of plain
709 2020-07-15 Jan Beulich <jbeulich@suse.com>
711 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
712 description. Drop '&' description. Use P for push of immediate,
713 pushf/popf, enter, and leave. Use %LP for lret/retf.
714 (dis386_twobyte): Use P for push/pop of fs/gs.
715 (reg_table): Use P for push/pop. Use @ for near call/jmp.
716 (x86_64_table): Use P for far call/jmp.
717 (putop): Drop handling of 'U' and '&'. Move and adjust handling
718 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
720 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
721 and dqw_mode (unconditional).
723 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-dis.c (OP_E_memory): Without base nor index registers,
727 32-bit displacement to 64 bits.
729 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
731 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
732 faulty double register pair is detected.
734 2020-07-14 Jan Beulich <jbeulich@suse.com>
736 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
738 2020-07-14 Jan Beulich <jbeulich@suse.com>
740 * i386-dis.c (OP_R, Rm): Delete.
741 (MOD_0F24, MOD_0F26): Rename to ...
742 (X86_64_0F24, X86_64_0F26): ... respectively.
743 (dis386): Update 'L' and 'Z' comments.
744 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
746 (mod_table): Move opcode 0F24 and 0F26 entries ...
747 (x86_64_table): ... here.
748 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
751 2020-07-14 Jan Beulich <jbeulich@suse.com>
753 * i386-dis.c (Rd, Rdq, MaskR): Delete.
754 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
755 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
756 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
757 MOD_EVEX_0F387C): New enumerators.
758 (reg_table): Use Edq for rdssp.
759 (prefix_table): Use Edq for incssp.
760 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
761 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
762 ktest*, and kshift*. Use Edq / MaskE for kmov*.
763 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
764 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
765 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
766 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
767 0F3828_P_1 and 0F3838_P_1.
768 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
769 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
771 2020-07-14 Jan Beulich <jbeulich@suse.com>
773 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
774 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
775 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
776 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
777 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
778 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
779 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
780 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
781 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
782 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
783 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
784 (reg_table, prefix_table, three_byte_table, vex_table,
785 vex_len_table, mod_table, rm_table): Replace / remove respective
787 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
788 of PREFIX_DATA in used_prefixes.
790 2020-07-14 Jan Beulich <jbeulich@suse.com>
792 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
793 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
794 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
795 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
796 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
797 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
798 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
799 VEX_W_0F3A33_L_0): Delete.
800 (dis386): Adjust "BW" description.
801 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
802 0F3A31, 0F3A32, and 0F3A33.
803 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
805 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
808 2020-07-14 Jan Beulich <jbeulich@suse.com>
810 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
811 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
812 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
813 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
814 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
815 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
816 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
817 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
818 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
819 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
820 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
821 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
822 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
823 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
824 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
825 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
826 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
827 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
828 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
829 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
830 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
831 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
832 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
833 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
834 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
835 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
836 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
837 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
838 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
839 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
840 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
841 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
842 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
843 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
844 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
845 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
846 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
847 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
848 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
849 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
850 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
851 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
852 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
853 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
854 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
855 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
856 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
857 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
858 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
859 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
860 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
861 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
862 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
863 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
864 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
865 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
866 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
867 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
868 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
869 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
870 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
871 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
872 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
873 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
874 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
875 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
876 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
877 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
878 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
879 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
880 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
881 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
882 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
883 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
884 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
885 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
886 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
887 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
888 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
889 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
890 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
891 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
892 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
893 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
894 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
895 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
896 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
897 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
898 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
899 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
900 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
901 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
902 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
903 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
904 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
905 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
906 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
907 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
908 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
909 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
910 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
911 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
912 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
913 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
914 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
915 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
916 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
917 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
918 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
919 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
920 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
921 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
922 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
923 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
924 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
925 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
926 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
927 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
928 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
929 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
930 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
931 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
932 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
933 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
934 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
935 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
936 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
937 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
938 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
939 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
940 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
941 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
942 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
943 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
944 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
945 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
946 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
947 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
948 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
949 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
950 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
951 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
952 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
953 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
954 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
955 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
956 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
957 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
958 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
959 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
960 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
961 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
962 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
963 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
964 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
965 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
966 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
967 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
968 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
969 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
970 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
971 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
972 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
973 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
974 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
975 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
976 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
977 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
978 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
979 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
980 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
981 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
982 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
983 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
984 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
985 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
986 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
987 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
988 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
989 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
990 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
991 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
992 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
993 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
994 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
995 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
996 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
997 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
998 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
999 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1000 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1001 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1002 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1003 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1004 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1005 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1006 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1007 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1008 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1009 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1010 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1011 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1012 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1013 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1014 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1015 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1016 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1017 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1018 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1019 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1020 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1021 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1022 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1023 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1024 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1025 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1026 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1027 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1028 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1029 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1030 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1031 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1032 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1033 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1034 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1035 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1036 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1037 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1038 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1039 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1040 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1041 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1042 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1043 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1044 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1045 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1046 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1047 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1048 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1049 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1050 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1051 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1052 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1053 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1054 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1055 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1056 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1057 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1058 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1059 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1060 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1061 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1062 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1063 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1064 EVEX_W_0F3A72_P_2): Rename to ...
1065 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1066 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1067 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1068 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1069 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1070 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1071 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1072 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1073 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1074 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1075 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1076 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1077 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1078 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1079 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1080 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1081 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1082 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1083 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1084 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1085 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1086 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1087 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1088 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1089 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1090 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1091 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1092 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1093 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1094 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1095 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1096 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1097 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1098 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1099 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1100 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1101 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1102 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1103 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1104 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1105 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1106 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1107 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1108 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1109 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1110 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1111 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1112 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1113 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1114 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1115 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1116 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1117 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1118 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1119 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1120 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1121 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1122 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1123 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1124 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1125 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1126 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1127 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1128 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1129 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1130 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1131 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1132 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1133 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1134 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1135 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1136 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1138 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1139 vex_w_table, mod_table): Replace / remove respective entries.
1140 (print_insn): Move up dp->prefix_requirement handling. Handle
1142 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1143 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1144 Replace / remove respective entries.
1146 2020-07-14 Jan Beulich <jbeulich@suse.com>
1148 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1149 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1150 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1151 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1152 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1154 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1155 0F2C, 0F2D, 0F2E, and 0F2F.
1156 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1159 2020-07-14 Jan Beulich <jbeulich@suse.com>
1161 * i386-dis.c (OP_VexR, VexScalarR): New.
1162 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1163 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1164 need_vex_reg): Delete.
1165 (prefix_table): Replace VexScalar by VexScalarR and
1166 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1167 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1168 (vex_len_table): Replace EXqVexScalarS by EXqS.
1169 (get_valid_dis386): Don't set need_vex_reg.
1170 (print_insn): Don't initialize need_vex_reg.
1171 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1172 q_scalar_swap_mode cases.
1173 (OP_EX): Don't check for d_scalar_swap_mode and
1175 (OP_VEX): Done check need_vex_reg.
1176 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1177 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1178 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1180 2020-07-14 Jan Beulich <jbeulich@suse.com>
1182 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1183 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1184 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1185 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1186 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1187 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1188 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1189 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1190 (vex_table): Replace Vex128 by Vex.
1191 (vex_len_table): Likewise. Adjust referenced enum names.
1192 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1193 referenced enum names.
1194 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1195 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1197 2020-07-14 Jan Beulich <jbeulich@suse.com>
1199 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1200 (putop): Handle "DQ". Don't handle "LW" anymore.
1201 (prefix_table, mod_table): Replace %LW by %DQ.
1202 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1204 2020-07-14 Jan Beulich <jbeulich@suse.com>
1206 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1207 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1208 d_scalar_swap_mode case handling. Move shift adjsutment into
1209 the case its applicable to.
1211 2020-07-14 Jan Beulich <jbeulich@suse.com>
1213 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1214 (EXbScalar, EXwScalar): Fold to ...
1215 (EXbwUnit): ... this.
1216 (b_scalar_mode, w_scalar_mode): Fold to ...
1217 (bw_unit_mode): ... this.
1218 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1219 w_scalar_mode handling by bw_unit_mode one.
1220 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1222 * i386-dis-evex-prefix.h: ... here.
1224 2020-07-14 Jan Beulich <jbeulich@suse.com>
1226 * i386-dis.c (PCMPESTR_Fixup): Delete.
1227 (dis386): Adjust "LQ" description.
1228 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1229 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1230 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1231 vpcmpestrm, and vpcmpestri.
1232 (putop): Honor "cond" when handling LQ.
1233 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1234 vcvtsi2ss and vcvtusi2ss.
1235 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1236 vcvtsi2sd and vcvtusi2sd.
1238 2020-07-14 Jan Beulich <jbeulich@suse.com>
1240 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1241 (simd_cmp_op): Add const.
1242 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1243 (CMP_Fixup): Handle VEX case.
1244 (prefix_table): Replace VCMP by CMP.
1245 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1247 2020-07-14 Jan Beulich <jbeulich@suse.com>
1249 * i386-dis.c (MOVBE_Fixup): Delete.
1251 (prefix_table): Use Mv for movbe entries.
1253 2020-07-14 Jan Beulich <jbeulich@suse.com>
1255 * i386-dis.c (CRC32_Fixup): Delete.
1256 (prefix_table): Use Eb/Ev for crc32 entries.
1258 2020-07-14 Jan Beulich <jbeulich@suse.com>
1260 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1261 Conditionalize invocations of "USED_REX (0)".
1263 2020-07-14 Jan Beulich <jbeulich@suse.com>
1265 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1266 CH, DH, BH, AX, DX): Delete.
1267 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1268 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1269 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1271 2020-07-10 Lili Cui <lili.cui@intel.com>
1273 * i386-dis.c (TMM): New.
1276 (MVexSIBMEM): Likewise.
1277 (tmm_mode): Likewise.
1278 (vex_sibmem_mode): Likewise.
1279 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1280 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1281 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1282 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1283 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1284 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1285 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1286 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1287 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1288 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1289 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1290 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1291 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1292 (PREFIX_VEX_0F3849_X86_64): Likewise.
1293 (PREFIX_VEX_0F384B_X86_64): Likewise.
1294 (PREFIX_VEX_0F385C_X86_64): Likewise.
1295 (PREFIX_VEX_0F385E_X86_64): Likewise.
1296 (X86_64_VEX_0F3849): Likewise.
1297 (X86_64_VEX_0F384B): Likewise.
1298 (X86_64_VEX_0F385C): Likewise.
1299 (X86_64_VEX_0F385E): Likewise.
1300 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1301 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1302 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1303 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1304 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1305 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1306 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1307 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1308 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1309 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1310 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1311 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1312 (VEX_W_0F3849_X86_64_P_0): Likewise.
1313 (VEX_W_0F3849_X86_64_P_2): Likewise.
1314 (VEX_W_0F3849_X86_64_P_3): Likewise.
1315 (VEX_W_0F384B_X86_64_P_1): Likewise.
1316 (VEX_W_0F384B_X86_64_P_2): Likewise.
1317 (VEX_W_0F384B_X86_64_P_3): Likewise.
1318 (VEX_W_0F385C_X86_64_P_1): Likewise.
1319 (VEX_W_0F385E_X86_64_P_0): Likewise.
1320 (VEX_W_0F385E_X86_64_P_1): Likewise.
1321 (VEX_W_0F385E_X86_64_P_2): Likewise.
1322 (VEX_W_0F385E_X86_64_P_3): Likewise.
1323 (names_tmm): Likewise.
1324 (att_names_tmm): Likewise.
1325 (intel_operand_size): Handle void_mode.
1326 (OP_XMM): Handle tmm_mode.
1329 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1330 CpuAMX_BF16 and CpuAMX_TILE.
1331 (operand_type_shorthands): Add RegTMM.
1332 (operand_type_init): Likewise.
1333 (operand_types): Add Tmmword.
1334 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1335 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1336 * i386-opc.h (CpuAMX_INT8): New.
1337 (CpuAMX_BF16): Likewise.
1338 (CpuAMX_TILE): Likewise.
1340 (Tmmword): Likewise.
1341 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1342 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1343 (i386_operand_type): Add tmmword.
1344 * i386-opc.tbl: Add AMX instructions.
1345 * i386-reg.tbl: Add AMX registers.
1346 * i386-init.h: Regenerated.
1347 * i386-tbl.h: Likewise.
1349 2020-07-08 Jan Beulich <jbeulich@suse.com>
1351 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1352 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1354 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1355 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1357 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1358 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1359 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1360 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1361 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1362 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1363 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1364 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1365 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1366 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1367 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1368 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1369 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1370 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1371 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1372 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1373 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1374 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1375 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1376 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1377 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1378 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1379 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1380 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1381 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1382 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1383 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1384 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1385 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1386 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1387 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1388 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1389 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1390 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1391 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1392 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1393 (reg_table): Re-order XOP entries. Adjust their operands.
1394 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1395 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1396 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1397 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1398 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1399 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1400 entries by references ...
1401 (vex_len_table): ... to resepctive new entries here. For several
1402 new and existing entries reference ...
1403 (vex_w_table): ... new entries here.
1404 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1406 2020-07-08 Jan Beulich <jbeulich@suse.com>
1408 * i386-dis.c (XMVexScalarI4): Define.
1409 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1410 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1411 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1412 (vex_len_table): Move scalar FMA4 entries ...
1413 (prefix_table): ... here.
1414 (OP_REG_VexI4): Handle scalar_mode.
1415 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1416 * i386-tbl.h: Re-generate.
1418 2020-07-08 Jan Beulich <jbeulich@suse.com>
1420 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1421 Vex_2src_2): Delete.
1422 (OP_VexW, VexW): New.
1423 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1424 for shifts and rotates by register.
1426 2020-07-08 Jan Beulich <jbeulich@suse.com>
1428 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1429 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1430 OP_EX_VexReg): Delete.
1431 (OP_VexI4, VexI4): New.
1432 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1433 (prefix_table): ... here.
1434 (print_insn): Drop setting of vex_w_done.
1436 2020-07-08 Jan Beulich <jbeulich@suse.com>
1438 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1439 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1440 (xop_table): Replace operands of 4-operand insns.
1441 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1443 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1445 * arc-opc.c (insert_rbd): New function.
1448 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1451 2020-07-07 Jan Beulich <jbeulich@suse.com>
1453 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1454 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1455 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1456 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1458 (putop): Handle "BW".
1459 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1460 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1462 * i386-dis-evex-prefix.h: ... here.
1464 2020-07-06 Jan Beulich <jbeulich@suse.com>
1466 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1467 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1468 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1469 VEX_W_0FXOP_09_83): New enumerators.
1470 (xop_table): Reference the above.
1471 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1472 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1473 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1474 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1476 2020-07-06 Jan Beulich <jbeulich@suse.com>
1478 * i386-dis.c (EVEX_W_0F3838_P_1,
1479 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1480 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1481 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1482 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1483 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1484 (putop): Centralize management of last[]. Delete SAVE_LAST.
1485 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1486 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1487 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1488 * i386-dis-evex-prefix.h: here.
1490 2020-07-06 Jan Beulich <jbeulich@suse.com>
1492 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1493 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1494 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1495 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1497 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1498 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1499 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1500 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1501 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1502 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1503 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1504 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1505 these, respectively.
1506 * i386-dis-evex-len.h: Adjust comments.
1507 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1508 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1509 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1510 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1511 MOD_EVEX_0F385B_P_2_W_1 table entries.
1512 * i386-dis-evex-w.h: Reference mod_table[] for
1513 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1516 2020-07-06 Jan Beulich <jbeulich@suse.com>
1518 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1519 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1521 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1522 Likewise. Mark 256-bit entries invalid.
1524 2020-07-06 Jan Beulich <jbeulich@suse.com>
1526 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1527 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1528 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1529 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1530 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1531 PREFIX_EVEX_0F382B): Delete.
1532 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1533 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1534 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1535 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1536 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1538 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1539 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1540 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1541 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1543 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1544 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1545 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1546 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1547 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1548 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1549 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1550 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1551 PREFIX_EVEX_0F382B): Remove table entries.
1552 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1553 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1554 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1556 2020-07-06 Jan Beulich <jbeulich@suse.com>
1558 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1559 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1561 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1562 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1563 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1564 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1567 2020-07-06 Jan Beulich <jbeulich@suse.com>
1569 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1570 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1571 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1572 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1573 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1574 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1575 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1576 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1577 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1580 2020-07-06 Jan Beulich <jbeulich@suse.com>
1582 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1583 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1584 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1586 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1588 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1590 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1592 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1594 2020-07-06 Jan Beulich <jbeulich@suse.com>
1596 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1597 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1598 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1599 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1600 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1601 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1602 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1603 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1604 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1605 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1606 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1607 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1608 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1609 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1610 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1611 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1612 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1613 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1614 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1615 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1616 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1617 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1618 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1619 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1620 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1621 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1622 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1623 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1624 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1625 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1626 (prefix_table): Add EXxEVexR to FMA table entries.
1627 (OP_Rounding): Move abort() invocation.
1628 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1629 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1630 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1631 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1632 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1633 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1634 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1635 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1636 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1637 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1639 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1640 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1641 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1642 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1643 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1644 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1645 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1646 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1647 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1648 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1649 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1650 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1651 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1652 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1653 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1654 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1655 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1656 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1657 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1658 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1659 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1660 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1661 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1662 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1663 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1664 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1665 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1666 Delete table entries.
1667 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1668 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1669 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1672 2020-07-06 Jan Beulich <jbeulich@suse.com>
1674 * i386-dis.c (EXqScalarS): Delete.
1675 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1676 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1678 2020-07-06 Jan Beulich <jbeulich@suse.com>
1680 * i386-dis.c (safe-ctype.h): Include.
1681 (EXdScalar, EXqScalar): Delete.
1682 (d_scalar_mode, q_scalar_mode): Delete.
1683 (prefix_table, vex_len_table): Use EXxmm_md in place of
1684 EXdScalar and EXxmm_mq in place of EXqScalar.
1685 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1686 d_scalar_mode and q_scalar_mode.
1687 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1688 (vmovsd): Use EXxmm_mq.
1690 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1693 * arc-dis.c: Fix spelling mistake.
1694 * po/opcodes.pot: Regenerate.
1696 2020-07-06 Nick Clifton <nickc@redhat.com>
1698 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1699 * po/uk.po: Updated Ukranian translation.
1701 2020-07-04 Nick Clifton <nickc@redhat.com>
1703 * configure: Regenerate.
1704 * po/opcodes.pot: Regenerate.
1706 2020-07-04 Nick Clifton <nickc@redhat.com>
1708 Binutils 2.35 branch created.
1710 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1712 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1713 * i386-opc.h (VexSwapSources): New.
1714 (i386_opcode_modifier): Add vexswapsources.
1715 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1716 with two source operands swapped.
1717 * i386-tbl.h: Regenerated.
1719 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1721 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1722 unprivileged CSR can also be initialized.
1724 2020-06-29 Alan Modra <amodra@gmail.com>
1726 * arm-dis.c: Use C style comments.
1727 * cr16-opc.c: Likewise.
1728 * ft32-dis.c: Likewise.
1729 * moxie-opc.c: Likewise.
1730 * tic54x-dis.c: Likewise.
1731 * s12z-opc.c: Remove useless comment.
1732 * xgate-dis.c: Likewise.
1734 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1736 * i386-opc.tbl: Add a blank line.
1738 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1740 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1741 (VecSIB128): Renamed to ...
1743 (VecSIB256): Renamed to ...
1745 (VecSIB512): Renamed to ...
1747 (VecSIB): Renamed to ...
1749 (i386_opcode_modifier): Replace vecsib with sib.
1750 * i386-opc.tbl (VecSIB128): New.
1751 (VecSIB256): Likewise.
1752 (VecSIB512): Likewise.
1753 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1754 and VecSIB512, respectively.
1756 2020-06-26 Jan Beulich <jbeulich@suse.com>
1758 * i386-dis.c: Adjust description of I macro.
1759 (x86_64_table): Drop use of I.
1760 (float_mem): Replace use of I.
1761 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1763 2020-06-26 Jan Beulich <jbeulich@suse.com>
1765 * i386-dis.c: (print_insn): Avoid straight assignment to
1766 priv.orig_sizeflag when processing -M sub-options.
1768 2020-06-25 Jan Beulich <jbeulich@suse.com>
1770 * i386-dis.c: Adjust description of J macro.
1771 (dis386, x86_64_table, mod_table): Replace J.
1772 (putop): Remove handling of J.
1774 2020-06-25 Jan Beulich <jbeulich@suse.com>
1776 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1778 2020-06-25 Jan Beulich <jbeulich@suse.com>
1780 * i386-dis.c: Adjust description of "LQ" macro.
1781 (dis386_twobyte): Use LQ for sysret.
1782 (putop): Adjust handling of LQ.
1784 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1786 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1787 * riscv-dis.c: Include elfxx-riscv.h.
1789 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1791 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1793 2020-06-17 Lili Cui <lili.cui@intel.com>
1795 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1797 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1800 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1801 * i386-opc.tbl: Likewise.
1802 * i386-tbl.h: Regenerated.
1804 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1806 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1808 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1810 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1811 (SR_CORE): Likewise.
1812 (SR_FEAT): Likewise.
1814 (SR_V8_1): Likewise.
1815 (SR_V8_2): Likewise.
1816 (SR_V8_3): Likewise.
1817 (SR_V8_4): Likewise.
1820 (SR_SSBS): Likewise.
1822 (SR_ID_PFR2): Likewise.
1823 (SR_PROFILE): Likewise.
1824 (SR_MEMTAG): Likewise.
1825 (SR_SCXTNUM): Likewise.
1826 (aarch64_sys_regs): Refactor to store feature information in the table.
1827 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1828 that now describe their own features.
1829 (aarch64_pstatefield_supported_p): Likewise.
1831 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1833 * i386-dis.c (prefix_table): Fix a typo in comments.
1835 2020-06-09 Jan Beulich <jbeulich@suse.com>
1837 * i386-dis.c (rex_ignored): Delete.
1838 (ckprefix): Drop rex_ignored initialization.
1839 (get_valid_dis386): Drop setting of rex_ignored.
1840 (print_insn): Drop checking of rex_ignored. Don't record data
1841 size prefix as used with VEX-and-alike encodings.
1843 2020-06-09 Jan Beulich <jbeulich@suse.com>
1845 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1846 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1847 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1848 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1849 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1850 VEX_0F12, and VEX_0F16.
1851 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1852 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1853 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1854 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1855 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1856 MOD_VEX_0F16_PREFIX_2 entries.
1858 2020-06-09 Jan Beulich <jbeulich@suse.com>
1860 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1861 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1862 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1863 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1864 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1865 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1866 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1867 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1868 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1869 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1870 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1871 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1872 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1873 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1874 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1875 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1876 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1877 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1878 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1879 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1880 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1881 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1882 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1883 EVEX_W_0FC6_P_2): Delete.
1884 (print_insn): Add EVEX.W vs embedded prefix consistency check
1885 to prefix validation.
1886 * i386-dis-evex.h (evex_table): Don't further descend for
1887 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1888 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1890 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1891 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1892 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1893 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1894 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1895 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1896 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1897 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1898 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1899 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1900 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1901 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1902 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1903 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1904 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1905 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1906 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1907 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1908 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1909 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1910 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1911 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1912 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1913 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1914 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1915 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1916 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1918 2020-06-09 Jan Beulich <jbeulich@suse.com>
1920 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1921 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1922 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1924 (print_insn): Drop pointless check against bad_opcode. Split
1925 prefix validation into legacy and VEX-and-alike parts.
1926 (putop): Re-work 'X' macro handling.
1928 2020-06-09 Jan Beulich <jbeulich@suse.com>
1930 * i386-dis.c (MOD_0F51): Rename to ...
1931 (MOD_0F50): ... this.
1933 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1935 * arm-dis.c (arm_opcodes): Add dfb.
1936 (thumb32_opcodes): Add dfb.
1938 2020-06-08 Jan Beulich <jbeulich@suse.com>
1940 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1942 2020-06-06 Alan Modra <amodra@gmail.com>
1944 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1946 2020-06-05 Alan Modra <amodra@gmail.com>
1948 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1949 size is large enough.
1951 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1953 * disassemble.c (disassemble_init_for_target): Set endian_code for
1955 * bpf-desc.c: Regenerate.
1956 * bpf-opc.c: Likewise.
1957 * bpf-dis.c: Likewise.
1959 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1961 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1962 (cgen_put_insn_value): Likewise.
1963 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1964 * cgen-dis.in (print_insn): Likewise.
1965 * cgen-ibld.in (insert_1): Likewise.
1966 (insert_1): Likewise.
1967 (insert_insn_normal): Likewise.
1968 (extract_1): Likewise.
1969 * bpf-dis.c: Regenerate.
1970 * bpf-ibld.c: Likewise.
1971 * bpf-ibld.c: Likewise.
1972 * cgen-dis.in: Likewise.
1973 * cgen-ibld.in: Likewise.
1974 * cgen-opc.c: Likewise.
1975 * epiphany-dis.c: Likewise.
1976 * epiphany-ibld.c: Likewise.
1977 * fr30-dis.c: Likewise.
1978 * fr30-ibld.c: Likewise.
1979 * frv-dis.c: Likewise.
1980 * frv-ibld.c: Likewise.
1981 * ip2k-dis.c: Likewise.
1982 * ip2k-ibld.c: Likewise.
1983 * iq2000-dis.c: Likewise.
1984 * iq2000-ibld.c: Likewise.
1985 * lm32-dis.c: Likewise.
1986 * lm32-ibld.c: Likewise.
1987 * m32c-dis.c: Likewise.
1988 * m32c-ibld.c: Likewise.
1989 * m32r-dis.c: Likewise.
1990 * m32r-ibld.c: Likewise.
1991 * mep-dis.c: Likewise.
1992 * mep-ibld.c: Likewise.
1993 * mt-dis.c: Likewise.
1994 * mt-ibld.c: Likewise.
1995 * or1k-dis.c: Likewise.
1996 * or1k-ibld.c: Likewise.
1997 * xc16x-dis.c: Likewise.
1998 * xc16x-ibld.c: Likewise.
1999 * xstormy16-dis.c: Likewise.
2000 * xstormy16-ibld.c: Likewise.
2002 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
2004 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2005 (print_insn_): Handle instruction endian.
2006 * bpf-dis.c: Regenerate.
2007 * bpf-desc.c: Regenerate.
2008 * epiphany-dis.c: Likewise.
2009 * epiphany-desc.c: Likewise.
2010 * fr30-dis.c: Likewise.
2011 * fr30-desc.c: Likewise.
2012 * frv-dis.c: Likewise.
2013 * frv-desc.c: Likewise.
2014 * ip2k-dis.c: Likewise.
2015 * ip2k-desc.c: Likewise.
2016 * iq2000-dis.c: Likewise.
2017 * iq2000-desc.c: Likewise.
2018 * lm32-dis.c: Likewise.
2019 * lm32-desc.c: Likewise.
2020 * m32c-dis.c: Likewise.
2021 * m32c-desc.c: Likewise.
2022 * m32r-dis.c: Likewise.
2023 * m32r-desc.c: Likewise.
2024 * mep-dis.c: Likewise.
2025 * mep-desc.c: Likewise.
2026 * mt-dis.c: Likewise.
2027 * mt-desc.c: Likewise.
2028 * or1k-dis.c: Likewise.
2029 * or1k-desc.c: Likewise.
2030 * xc16x-dis.c: Likewise.
2031 * xc16x-desc.c: Likewise.
2032 * xstormy16-dis.c: Likewise.
2033 * xstormy16-desc.c: Likewise.
2035 2020-06-03 Nick Clifton <nickc@redhat.com>
2037 * po/sr.po: Updated Serbian translation.
2039 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
2041 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2042 (riscv_get_priv_spec_class): Likewise.
2044 2020-06-01 Alan Modra <amodra@gmail.com>
2046 * bpf-desc.c: Regenerate.
2048 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
2049 David Faust <david.faust@oracle.com>
2051 * bpf-desc.c: Regenerate.
2052 * bpf-opc.h: Likewise.
2053 * bpf-opc.c: Likewise.
2054 * bpf-dis.c: Likewise.
2056 2020-05-28 Alan Modra <amodra@gmail.com>
2058 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2061 2020-05-28 Alan Modra <amodra@gmail.com>
2063 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2065 (print_insn_ns32k): Revert last change.
2067 2020-05-28 Nick Clifton <nickc@redhat.com>
2069 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2072 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2074 Fix extraction of signed constants in nios2 disassembler (again).
2076 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2077 extractions of signed fields.
2079 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2081 * s390-opc.txt: Relocate vector load/store instructions with
2082 additional alignment parameter and change architecture level
2083 constraint from z14 to z13.
2085 2020-05-21 Alan Modra <amodra@gmail.com>
2087 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2088 * sparc-dis.c: Likewise.
2089 * tic4x-dis.c: Likewise.
2090 * xtensa-dis.c: Likewise.
2091 * bpf-desc.c: Regenerate.
2092 * epiphany-desc.c: Regenerate.
2093 * fr30-desc.c: Regenerate.
2094 * frv-desc.c: Regenerate.
2095 * ip2k-desc.c: Regenerate.
2096 * iq2000-desc.c: Regenerate.
2097 * lm32-desc.c: Regenerate.
2098 * m32c-desc.c: Regenerate.
2099 * m32r-desc.c: Regenerate.
2100 * mep-asm.c: Regenerate.
2101 * mep-desc.c: Regenerate.
2102 * mt-desc.c: Regenerate.
2103 * or1k-desc.c: Regenerate.
2104 * xc16x-desc.c: Regenerate.
2105 * xstormy16-desc.c: Regenerate.
2107 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2109 * riscv-opc.c (riscv_ext_version_table): The table used to store
2110 all information about the supported spec and the corresponding ISA
2111 versions. Currently, only Zicsr is supported to verify the
2112 correctness of Z sub extension settings. Others will be supported
2113 in the future patches.
2114 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2115 classes and the corresponding strings.
2116 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2117 spec class by giving a ISA spec string.
2118 * riscv-opc.c (struct priv_spec_t): New structure.
2119 (struct priv_spec_t priv_specs): List for all supported privilege spec
2120 classes and the corresponding strings.
2121 (riscv_get_priv_spec_class): New function. Get the corresponding
2122 privilege spec class by giving a spec string.
2123 (riscv_get_priv_spec_name): New function. Get the corresponding
2124 privilege spec string by giving a CSR version class.
2125 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2126 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2127 according to the chosen version. Build a hash table riscv_csr_hash to
2128 store the valid CSR for the chosen pirv verison. Dump the direct
2129 CSR address rather than it's name if it is invalid.
2130 (parse_riscv_dis_option_without_args): New function. Parse the options
2132 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2133 parse the options without arguments first, and then handle the options
2134 with arguments. Add the new option -Mpriv-spec, which has argument.
2135 * riscv-dis.c (print_riscv_disassembler_options): Add description
2136 about the new OBJDUMP option.
2138 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2140 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2141 WC values on POWER10 sync, dcbf and wait instructions.
2142 (insert_pl, extract_pl): New functions.
2143 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2144 (LS3): New , 3-bit L for sync.
2145 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2146 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2147 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2148 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2149 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2150 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2151 <wait>: Enable PL operand on POWER10.
2152 <dcbf>: Enable L3OPT operand on POWER10.
2153 <sync>: Enable SC2 operand on POWER10.
2155 2020-05-19 Stafford Horne <shorne@gmail.com>
2158 * or1k-asm.c: Regenerate.
2159 * or1k-desc.c: Regenerate.
2160 * or1k-desc.h: Regenerate.
2161 * or1k-dis.c: Regenerate.
2162 * or1k-ibld.c: Regenerate.
2163 * or1k-opc.c: Regenerate.
2164 * or1k-opc.h: Regenerate.
2165 * or1k-opinst.c: Regenerate.
2167 2020-05-11 Alan Modra <amodra@gmail.com>
2169 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2172 2020-05-11 Alan Modra <amodra@gmail.com>
2174 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2175 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2177 2020-05-11 Alan Modra <amodra@gmail.com>
2179 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2181 2020-05-11 Alan Modra <amodra@gmail.com>
2183 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2184 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2186 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2188 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2191 2020-05-11 Alan Modra <amodra@gmail.com>
2193 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2194 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2195 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2196 (prefix_opcodes): Add xxeval.
2198 2020-05-11 Alan Modra <amodra@gmail.com>
2200 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2201 xxgenpcvwm, xxgenpcvdm.
2203 2020-05-11 Alan Modra <amodra@gmail.com>
2205 * ppc-opc.c (MP, VXVAM_MASK): Define.
2206 (VXVAPS_MASK): Use VXVA_MASK.
2207 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2208 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2209 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2210 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2212 2020-05-11 Alan Modra <amodra@gmail.com>
2213 Peter Bergner <bergner@linux.ibm.com>
2215 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2217 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2218 YMSK2, XA6a, XA6ap, XB6a entries.
2219 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2220 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2222 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2223 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2224 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2225 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2226 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2227 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2228 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2229 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2230 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2231 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2232 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2233 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2234 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2235 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2237 2020-05-11 Alan Modra <amodra@gmail.com>
2239 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2240 (insert_xts, extract_xts): New functions.
2241 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2242 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2243 (VXRC_MASK, VXSH_MASK): Define.
2244 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2245 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2246 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2247 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2248 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2249 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2250 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2252 2020-05-11 Alan Modra <amodra@gmail.com>
2254 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2255 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2256 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2257 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2258 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2260 2020-05-11 Alan Modra <amodra@gmail.com>
2262 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2263 (XTP, DQXP, DQXP_MASK): Define.
2264 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2265 (prefix_opcodes): Add plxvp and pstxvp.
2267 2020-05-11 Alan Modra <amodra@gmail.com>
2269 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2270 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2271 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2273 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2275 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2277 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2279 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2281 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2283 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2285 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2287 2020-05-11 Alan Modra <amodra@gmail.com>
2289 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2291 2020-05-11 Alan Modra <amodra@gmail.com>
2293 * ppc-dis.c (ppc_opts): Add "power10" entry.
2294 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2295 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2297 2020-05-11 Nick Clifton <nickc@redhat.com>
2299 * po/fr.po: Updated French translation.
2301 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2303 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2304 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2305 (operand_general_constraint_met_p): validate
2306 AARCH64_OPND_UNDEFINED.
2307 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2309 * aarch64-asm-2.c: Regenerated.
2310 * aarch64-dis-2.c: Regenerated.
2311 * aarch64-opc-2.c: Regenerated.
2313 2020-04-29 Nick Clifton <nickc@redhat.com>
2316 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2319 2020-04-29 Nick Clifton <nickc@redhat.com>
2321 * po/sv.po: Updated Swedish translation.
2323 2020-04-29 Nick Clifton <nickc@redhat.com>
2326 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2327 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2328 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2331 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2334 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2335 cmpi only on m68020up and cpu32.
2337 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2339 * aarch64-asm.c (aarch64_ins_none): New.
2340 * aarch64-asm.h (ins_none): New declaration.
2341 * aarch64-dis.c (aarch64_ext_none): New.
2342 * aarch64-dis.h (ext_none): New declaration.
2343 * aarch64-opc.c (aarch64_print_operand): Update case for
2344 AARCH64_OPND_BARRIER_PSB.
2345 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2346 (AARCH64_OPERANDS): Update inserter/extracter for
2347 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2348 * aarch64-asm-2.c: Regenerated.
2349 * aarch64-dis-2.c: Regenerated.
2350 * aarch64-opc-2.c: Regenerated.
2352 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2354 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2355 (aarch64_feature_ras, RAS): Likewise.
2356 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2357 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2358 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2359 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2360 * aarch64-asm-2.c: Regenerated.
2361 * aarch64-dis-2.c: Regenerated.
2362 * aarch64-opc-2.c: Regenerated.
2364 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2366 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2367 (print_insn_neon): Support disassembly of conditional
2370 2020-02-16 David Faust <david.faust@oracle.com>
2372 * bpf-desc.c: Regenerate.
2373 * bpf-desc.h: Likewise.
2374 * bpf-opc.c: Regenerate.
2375 * bpf-opc.h: Likewise.
2377 2020-04-07 Lili Cui <lili.cui@intel.com>
2379 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2380 (prefix_table): New instructions (see prefixes above).
2381 (rm_table): Likewise
2382 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2383 CPU_ANY_TSXLDTRK_FLAGS.
2384 (cpu_flags): Add CpuTSXLDTRK.
2385 * i386-opc.h (enum): Add CpuTSXLDTRK.
2386 (i386_cpu_flags): Add cputsxldtrk.
2387 * i386-opc.tbl: Add XSUSPLDTRK insns.
2388 * i386-init.h: Regenerate.
2389 * i386-tbl.h: Likewise.
2391 2020-04-02 Lili Cui <lili.cui@intel.com>
2393 * i386-dis.c (prefix_table): New instructions serialize.
2394 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2395 CPU_ANY_SERIALIZE_FLAGS.
2396 (cpu_flags): Add CpuSERIALIZE.
2397 * i386-opc.h (enum): Add CpuSERIALIZE.
2398 (i386_cpu_flags): Add cpuserialize.
2399 * i386-opc.tbl: Add SERIALIZE insns.
2400 * i386-init.h: Regenerate.
2401 * i386-tbl.h: Likewise.
2403 2020-03-26 Alan Modra <amodra@gmail.com>
2405 * disassemble.h (opcodes_assert): Declare.
2406 (OPCODES_ASSERT): Define.
2407 * disassemble.c: Don't include assert.h. Include opintl.h.
2408 (opcodes_assert): New function.
2409 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2410 (bfd_h8_disassemble): Reduce size of data array. Correctly
2411 calculate maxlen. Omit insn decoding when insn length exceeds
2412 maxlen. Exit from nibble loop when looking for E, before
2413 accessing next data byte. Move processing of E outside loop.
2414 Replace tests of maxlen in loop with assertions.
2416 2020-03-26 Alan Modra <amodra@gmail.com>
2418 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2420 2020-03-25 Alan Modra <amodra@gmail.com>
2422 * z80-dis.c (suffix): Init mybuf.
2424 2020-03-22 Alan Modra <amodra@gmail.com>
2426 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2427 successflly read from section.
2429 2020-03-22 Alan Modra <amodra@gmail.com>
2431 * arc-dis.c (find_format): Use ISO C string concatenation rather
2432 than line continuation within a string. Don't access needs_limm
2433 before testing opcode != NULL.
2435 2020-03-22 Alan Modra <amodra@gmail.com>
2437 * ns32k-dis.c (print_insn_arg): Update comment.
2438 (print_insn_ns32k): Reduce size of index_offset array, and
2439 initialize, passing -1 to print_insn_arg for args that are not
2440 an index. Don't exit arg loop early. Abort on bad arg number.
2442 2020-03-22 Alan Modra <amodra@gmail.com>
2444 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2445 * s12z-opc.c: Formatting.
2446 (operands_f): Return an int.
2447 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2448 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2449 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2450 (exg_sex_discrim): Likewise.
2451 (create_immediate_operand, create_bitfield_operand),
2452 (create_register_operand_with_size, create_register_all_operand),
2453 (create_register_all16_operand, create_simple_memory_operand),
2454 (create_memory_operand, create_memory_auto_operand): Don't
2455 segfault on malloc failure.
2456 (z_ext24_decode): Return an int status, negative on fail, zero
2458 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2459 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2460 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2461 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2462 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2463 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2464 (loop_primitive_decode, shift_decode, psh_pul_decode),
2465 (bit_field_decode): Similarly.
2466 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2467 to return value, update callers.
2468 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2469 Don't segfault on NULL operand.
2470 (decode_operation): Return OP_INVALID on first fail.
2471 (decode_s12z): Check all reads, returning -1 on fail.
2473 2020-03-20 Alan Modra <amodra@gmail.com>
2475 * metag-dis.c (print_insn_metag): Don't ignore status from
2478 2020-03-20 Alan Modra <amodra@gmail.com>
2480 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2481 Initialize parts of buffer not written when handling a possible
2482 2-byte insn at end of section. Don't attempt decoding of such
2483 an insn by the 4-byte machinery.
2485 2020-03-20 Alan Modra <amodra@gmail.com>
2487 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2488 partially filled buffer. Prevent lookup of 4-byte insns when
2489 only VLE 2-byte insns are possible due to section size. Print
2490 ".word" rather than ".long" for 2-byte leftovers.
2492 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2495 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2497 2020-03-13 Jan Beulich <jbeulich@suse.com>
2499 * i386-dis.c (X86_64_0D): Rename to ...
2500 (X86_64_0E): ... this.
2502 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2504 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2505 * Makefile.in: Regenerated.
2507 2020-03-09 Jan Beulich <jbeulich@suse.com>
2509 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2511 * i386-tbl.h: Re-generate.
2513 2020-03-09 Jan Beulich <jbeulich@suse.com>
2515 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2516 vprot*, vpsha*, and vpshl*.
2517 * i386-tbl.h: Re-generate.
2519 2020-03-09 Jan Beulich <jbeulich@suse.com>
2521 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2522 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2523 * i386-tbl.h: Re-generate.
2525 2020-03-09 Jan Beulich <jbeulich@suse.com>
2527 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2528 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2529 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2530 * i386-tbl.h: Re-generate.
2532 2020-03-09 Jan Beulich <jbeulich@suse.com>
2534 * i386-gen.c (struct template_arg, struct template_instance,
2535 struct template_param, struct template, templates,
2536 parse_template, expand_templates): New.
2537 (process_i386_opcodes): Various local variables moved to
2538 expand_templates. Call parse_template and expand_templates.
2539 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2540 * i386-tbl.h: Re-generate.
2542 2020-03-06 Jan Beulich <jbeulich@suse.com>
2544 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2545 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2546 register and memory source templates. Replace VexW= by VexW*
2548 * i386-tbl.h: Re-generate.
2550 2020-03-06 Jan Beulich <jbeulich@suse.com>
2552 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2553 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2554 * i386-tbl.h: Re-generate.
2556 2020-03-06 Jan Beulich <jbeulich@suse.com>
2558 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2559 * i386-tbl.h: Re-generate.
2561 2020-03-06 Jan Beulich <jbeulich@suse.com>
2563 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2564 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2565 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2566 VexW0 on SSE2AVX variants.
2567 (vmovq): Drop NoRex64 from XMM/XMM variants.
2568 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2569 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2570 applicable use VexW0.
2571 * i386-tbl.h: Re-generate.
2573 2020-03-06 Jan Beulich <jbeulich@suse.com>
2575 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2576 * i386-opc.h (Rex64): Delete.
2577 (struct i386_opcode_modifier): Remove rex64 field.
2578 * i386-opc.tbl (crc32): Drop Rex64.
2579 Replace Rex64 with Size64 everywhere else.
2580 * i386-tbl.h: Re-generate.
2582 2020-03-06 Jan Beulich <jbeulich@suse.com>
2584 * i386-dis.c (OP_E_memory): Exclude recording of used address
2585 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2586 addressed memory operands for MPX insns.
2588 2020-03-06 Jan Beulich <jbeulich@suse.com>
2590 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2591 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2592 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2593 (ptwrite): Split into non-64-bit and 64-bit forms.
2594 * i386-tbl.h: Re-generate.
2596 2020-03-06 Jan Beulich <jbeulich@suse.com>
2598 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2600 * i386-tbl.h: Re-generate.
2602 2020-03-04 Jan Beulich <jbeulich@suse.com>
2604 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2605 (prefix_table): Move vmmcall here. Add vmgexit.
2606 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2607 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2608 (cpu_flags): Add CpuSEV_ES entry.
2609 * i386-opc.h (CpuSEV_ES): New.
2610 (union i386_cpu_flags): Add cpusev_es field.
2611 * i386-opc.tbl (vmgexit): New.
2612 * i386-init.h, i386-tbl.h: Re-generate.
2614 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2616 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2618 * i386-opc.h (IGNORESIZE): New.
2619 (DEFAULTSIZE): Likewise.
2620 (IgnoreSize): Removed.
2621 (DefaultSize): Likewise.
2622 (MnemonicSize): New.
2623 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2625 * i386-opc.tbl (IgnoreSize): New.
2626 (DefaultSize): Likewise.
2627 * i386-tbl.h: Regenerated.
2629 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2632 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2635 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2638 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2639 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2640 * i386-tbl.h: Regenerated.
2642 2020-02-26 Alan Modra <amodra@gmail.com>
2644 * aarch64-asm.c: Indent labels correctly.
2645 * aarch64-dis.c: Likewise.
2646 * aarch64-gen.c: Likewise.
2647 * aarch64-opc.c: Likewise.
2648 * alpha-dis.c: Likewise.
2649 * i386-dis.c: Likewise.
2650 * nds32-asm.c: Likewise.
2651 * nfp-dis.c: Likewise.
2652 * visium-dis.c: Likewise.
2654 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2656 * arc-regs.h (int_vector_base): Make it available for all ARC
2659 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2661 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2664 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2666 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2667 c.mv/c.li if rs1 is zero.
2669 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2671 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2672 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2674 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2675 * i386-opc.h (CpuABM): Removed.
2677 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2678 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2679 popcnt. Remove CpuABM from lzcnt.
2680 * i386-init.h: Regenerated.
2681 * i386-tbl.h: Likewise.
2683 2020-02-17 Jan Beulich <jbeulich@suse.com>
2685 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2686 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2687 VexW1 instead of open-coding them.
2688 * i386-tbl.h: Re-generate.
2690 2020-02-17 Jan Beulich <jbeulich@suse.com>
2692 * i386-opc.tbl (AddrPrefixOpReg): Define.
2693 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2694 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2695 templates. Drop NoRex64.
2696 * i386-tbl.h: Re-generate.
2698 2020-02-17 Jan Beulich <jbeulich@suse.com>
2701 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2702 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2703 into Intel syntax instance (with Unpsecified) and AT&T one
2705 (vcvtneps2bf16): Likewise, along with folding the two so far
2707 * i386-tbl.h: Re-generate.
2709 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2711 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2712 CPU_ANY_SSE4A_FLAGS.
2714 2020-02-17 Alan Modra <amodra@gmail.com>
2716 * i386-gen.c (cpu_flag_init): Correct last change.
2718 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2720 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2723 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2725 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2728 2020-02-14 Jan Beulich <jbeulich@suse.com>
2731 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2732 destination for Cpu64-only variant.
2733 (movzx): Fold patterns.
2734 * i386-tbl.h: Re-generate.
2736 2020-02-13 Jan Beulich <jbeulich@suse.com>
2738 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2739 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2740 CPU_ANY_SSE4_FLAGS entry.
2741 * i386-init.h: Re-generate.
2743 2020-02-12 Jan Beulich <jbeulich@suse.com>
2745 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2746 with Unspecified, making the present one AT&T syntax only.
2747 * i386-tbl.h: Re-generate.
2749 2020-02-12 Jan Beulich <jbeulich@suse.com>
2751 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2752 * i386-tbl.h: Re-generate.
2754 2020-02-12 Jan Beulich <jbeulich@suse.com>
2757 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2758 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2759 Amd64 and Intel64 templates.
2760 (call, jmp): Likewise for far indirect variants. Dro
2762 * i386-tbl.h: Re-generate.
2764 2020-02-11 Jan Beulich <jbeulich@suse.com>
2766 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2767 * i386-opc.h (ShortForm): Delete.
2768 (struct i386_opcode_modifier): Remove shortform field.
2769 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2770 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2771 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2772 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2774 * i386-tbl.h: Re-generate.
2776 2020-02-11 Jan Beulich <jbeulich@suse.com>
2778 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2779 fucompi): Drop ShortForm from operand-less templates.
2780 * i386-tbl.h: Re-generate.
2782 2020-02-11 Alan Modra <amodra@gmail.com>
2784 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2785 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2786 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2787 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2788 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2790 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2792 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2793 (cde_opcodes): Add VCX* instructions.
2795 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2796 Matthew Malcomson <matthew.malcomson@arm.com>
2798 * arm-dis.c (struct cdeopcode32): New.
2799 (CDE_OPCODE): New macro.
2800 (cde_opcodes): New disassembly table.
2801 (regnames): New option to table.
2802 (cde_coprocs): New global variable.
2803 (print_insn_cde): New
2804 (print_insn_thumb32): Use print_insn_cde.
2805 (parse_arm_disassembler_options): Parse coprocN args.
2807 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2810 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2812 * i386-opc.h (AMD64): Removed.
2813 (Intel64): Likewose.
2815 (INTEL64): Likewise.
2816 (INTEL64ONLY): Likewise.
2817 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2818 * i386-opc.tbl (Amd64): New.
2819 (Intel64): Likewise.
2820 (Intel64Only): Likewise.
2821 Replace AMD64 with Amd64. Update sysenter/sysenter with
2822 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2823 * i386-tbl.h: Regenerated.
2825 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2828 * z80-dis.c: Add support for GBZ80 opcodes.
2830 2020-02-04 Alan Modra <amodra@gmail.com>
2832 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2834 2020-02-03 Alan Modra <amodra@gmail.com>
2836 * m32c-ibld.c: Regenerate.
2838 2020-02-01 Alan Modra <amodra@gmail.com>
2840 * frv-ibld.c: Regenerate.
2842 2020-01-31 Jan Beulich <jbeulich@suse.com>
2844 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2845 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2846 (OP_E_memory): Replace xmm_mdq_mode case label by
2847 vex_scalar_w_dq_mode one.
2848 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2850 2020-01-31 Jan Beulich <jbeulich@suse.com>
2852 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2853 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2854 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2855 (intel_operand_size): Drop vex_w_dq_mode case label.
2857 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2859 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2860 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2862 2020-01-30 Alan Modra <amodra@gmail.com>
2864 * m32c-ibld.c: Regenerate.
2866 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2868 * bpf-opc.c: Regenerate.
2870 2020-01-30 Jan Beulich <jbeulich@suse.com>
2872 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2873 (dis386): Use them to replace C2/C3 table entries.
2874 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2875 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2876 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2877 * i386-tbl.h: Re-generate.
2879 2020-01-30 Jan Beulich <jbeulich@suse.com>
2881 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2883 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2885 * i386-tbl.h: Re-generate.
2887 2020-01-30 Alan Modra <amodra@gmail.com>
2889 * tic4x-dis.c (tic4x_dp): Make unsigned.
2891 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2892 Jan Beulich <jbeulich@suse.com>
2895 * i386-dis.c (MOVSXD_Fixup): New function.
2896 (movsxd_mode): New enum.
2897 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2898 (intel_operand_size): Handle movsxd_mode.
2899 (OP_E_register): Likewise.
2901 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2902 register on movsxd. Add movsxd with 16-bit destination register
2903 for AMD64 and Intel64 ISAs.
2904 * i386-tbl.h: Regenerated.
2906 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2909 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2910 * aarch64-asm-2.c: Regenerate
2911 * aarch64-dis-2.c: Likewise.
2912 * aarch64-opc-2.c: Likewise.
2914 2020-01-21 Jan Beulich <jbeulich@suse.com>
2916 * i386-opc.tbl (sysret): Drop DefaultSize.
2917 * i386-tbl.h: Re-generate.
2919 2020-01-21 Jan Beulich <jbeulich@suse.com>
2921 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2923 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2924 * i386-tbl.h: Re-generate.
2926 2020-01-20 Nick Clifton <nickc@redhat.com>
2928 * po/de.po: Updated German translation.
2929 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2930 * po/uk.po: Updated Ukranian translation.
2932 2020-01-20 Alan Modra <amodra@gmail.com>
2934 * hppa-dis.c (fput_const): Remove useless cast.
2936 2020-01-20 Alan Modra <amodra@gmail.com>
2938 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2940 2020-01-18 Nick Clifton <nickc@redhat.com>
2942 * configure: Regenerate.
2943 * po/opcodes.pot: Regenerate.
2945 2020-01-18 Nick Clifton <nickc@redhat.com>
2947 Binutils 2.34 branch created.
2949 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2951 * opintl.h: Fix spelling error (seperate).
2953 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2955 * i386-opc.tbl: Add {vex} pseudo prefix.
2956 * i386-tbl.h: Regenerated.
2958 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2961 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2962 (neon_opcodes): Likewise.
2963 (select_arm_features): Make sure we enable MVE bits when selecting
2964 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2967 2020-01-16 Jan Beulich <jbeulich@suse.com>
2969 * i386-opc.tbl: Drop stale comment from XOP section.
2971 2020-01-16 Jan Beulich <jbeulich@suse.com>
2973 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2974 (extractps): Add VexWIG to SSE2AVX forms.
2975 * i386-tbl.h: Re-generate.
2977 2020-01-16 Jan Beulich <jbeulich@suse.com>
2979 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2980 Size64 from and use VexW1 on SSE2AVX forms.
2981 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2982 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2983 * i386-tbl.h: Re-generate.
2985 2020-01-15 Alan Modra <amodra@gmail.com>
2987 * tic4x-dis.c (tic4x_version): Make unsigned long.
2988 (optab, optab_special, registernames): New file scope vars.
2989 (tic4x_print_register): Set up registernames rather than
2990 malloc'd registertable.
2991 (tic4x_disassemble): Delete optable and optable_special. Use
2992 optab and optab_special instead. Throw away old optab,
2993 optab_special and registernames when info->mach changes.
2995 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2998 * z80-dis.c (suffix): Use .db instruction to generate double
3001 2020-01-14 Alan Modra <amodra@gmail.com>
3003 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
3004 values to unsigned before shifting.
3006 2020-01-13 Thomas Troeger <tstroege@gmx.de>
3008 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3010 (print_insn_thumb16, print_insn_thumb32): Likewise.
3011 (print_insn): Initialize the insn info.
3012 * i386-dis.c (print_insn): Initialize the insn info fields, and
3015 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3017 * arc-opc.c (C_NE): Make it required.
3019 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3021 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3022 reserved register name.
3024 2020-01-13 Alan Modra <amodra@gmail.com>
3026 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3027 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3029 2020-01-13 Alan Modra <amodra@gmail.com>
3031 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
3032 result of wasm_read_leb128 in a uint64_t and check that bits
3033 are not lost when copying to other locals. Use uint32_t for
3034 most locals. Use PRId64 when printing int64_t.
3036 2020-01-13 Alan Modra <amodra@gmail.com>
3038 * score-dis.c: Formatting.
3039 * score7-dis.c: Formatting.
3041 2020-01-13 Alan Modra <amodra@gmail.com>
3043 * score-dis.c (print_insn_score48): Use unsigned variables for
3044 unsigned values. Don't left shift negative values.
3045 (print_insn_score32): Likewise.
3046 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3048 2020-01-13 Alan Modra <amodra@gmail.com>
3050 * tic4x-dis.c (tic4x_print_register): Remove dead code.
3052 2020-01-13 Alan Modra <amodra@gmail.com>
3054 * fr30-ibld.c: Regenerate.
3056 2020-01-13 Alan Modra <amodra@gmail.com>
3058 * xgate-dis.c (print_insn): Don't left shift signed value.
3059 (ripBits): Formatting, use 1u.
3061 2020-01-10 Alan Modra <amodra@gmail.com>
3063 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3064 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
3066 2020-01-10 Alan Modra <amodra@gmail.com>
3068 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3069 and XRREG value earlier to avoid a shift with negative exponent.
3070 * m10200-dis.c (disassemble): Similarly.
3072 2020-01-09 Nick Clifton <nickc@redhat.com>
3075 * z80-dis.c (ld_ii_ii): Use correct cast.
3077 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3080 * z80-dis.c (ld_ii_ii): Use character constant when checking
3083 2020-01-09 Jan Beulich <jbeulich@suse.com>
3085 * i386-dis.c (SEP_Fixup): New.
3087 (dis386_twobyte): Use it for sysenter/sysexit.
3088 (enum x86_64_isa): Change amd64 enumerator to value 1.
3089 (OP_J): Compare isa64 against intel64 instead of amd64.
3090 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3092 * i386-tbl.h: Re-generate.
3094 2020-01-08 Alan Modra <amodra@gmail.com>
3096 * z8k-dis.c: Include libiberty.h
3097 (instr_data_s): Make max_fetched unsigned.
3098 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3099 Don't exceed byte_info bounds.
3100 (output_instr): Make num_bytes unsigned.
3101 (unpack_instr): Likewise for nibl_count and loop.
3102 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3104 * z8k-opc.h: Regenerate.
3106 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3108 * arc-tbl.h (llock): Use 'LLOCK' as class.
3110 (scond): Use 'SCOND' as class.
3112 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3115 2020-01-06 Alan Modra <amodra@gmail.com>
3117 * m32c-ibld.c: Regenerate.
3119 2020-01-06 Alan Modra <amodra@gmail.com>
3122 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3123 Peek at next byte to prevent recursion on repeated prefix bytes.
3124 Ensure uninitialised "mybuf" is not accessed.
3125 (print_insn_z80): Don't zero n_fetch and n_used here,..
3126 (print_insn_z80_buf): ..do it here instead.
3128 2020-01-04 Alan Modra <amodra@gmail.com>
3130 * m32r-ibld.c: Regenerate.
3132 2020-01-04 Alan Modra <amodra@gmail.com>
3134 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3136 2020-01-04 Alan Modra <amodra@gmail.com>
3138 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3140 2020-01-04 Alan Modra <amodra@gmail.com>
3142 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3144 2020-01-03 Jan Beulich <jbeulich@suse.com>
3146 * aarch64-tbl.h (aarch64_opcode_table): Use
3147 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3149 2020-01-03 Jan Beulich <jbeulich@suse.com>
3151 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3152 forms of SUDOT and USDOT.
3154 2020-01-03 Jan Beulich <jbeulich@suse.com>
3156 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3158 * aarch64-dis-2.c: Re-generate.
3160 2020-01-03 Jan Beulich <jbeulich@suse.com>
3162 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3164 * aarch64-dis-2.c: Re-generate.
3166 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3168 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3170 2020-01-01 Alan Modra <amodra@gmail.com>
3172 Update year range in copyright notice of all files.
3174 For older changes see ChangeLog-2019
3176 Copyright (C) 2020 Free Software Foundation, Inc.
3178 Copying and distribution of this file, with or without modification,
3179 are permitted in any medium without royalty provided the copyright
3180 notice and this notice are preserved.
3186 version-control: never
projects / thirdparty / binutils-gdb.git / blob