opcodes/ChangeLog

   1 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
   2
   3         PR binutils/23109
   4         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
   5         * aarch64-dis-2.c: Regenerate.
   6
   7 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
   8
   9         PR binutils/21446
  10         * aarch64-asm.c (opintl.h): Include.
  11         (aarch64_ins_sysreg): Enforce read/write constraints.
  12         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
  13         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
  14         (F_REG_READ, F_REG_WRITE): New.
  15         * aarch64-opc.c (aarch64_print_operand): Generate notes for
  16         AARCH64_OPND_SYSREG.
  17         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
  18         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
  19         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
  20         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
  21         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
  22         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
  23         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
  24         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
  25         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
  26         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
  27         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
  28         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
  29         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
  30         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
  31         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
  32         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
  33         msr (F_SYS_WRITE), mrs (F_SYS_READ).
  34
  35 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  36
  37         PR binutils/21446
  38         * aarch64-dis.c (no_notes: New.
  39         (parse_aarch64_dis_option): Support notes.
  40         (aarch64_decode_insn, print_operands): Likewise.
  41         (print_aarch64_disassembler_options): Document notes.
  42         * aarch64-opc.c (aarch64_print_operand): Support notes.
  43
  44 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  45
  46         PR binutils/21446
  47         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
  48         and take error struct.
  49         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
  50         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
  51         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
  52         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
  53         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
  54         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
  55         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
  56         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
  57         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
  58         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
  59         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
  60         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
  61         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
  62         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
  63         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
  64         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
  65         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
  66         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  67         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
  68         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
  69         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
  70         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
  71         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
  72         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
  73         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
  74         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
  75         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
  76         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
  77         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
  78         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
  79         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
  80         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
  81         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
  82         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
  83         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
  84         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
  85         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
  86         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
  87         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
  88         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
  89         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
  90         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
  91         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
  92         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  93         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
  94         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
  95         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
  96         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
  97         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
  98         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
  99         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 100         (determine_disassembling_preference, aarch64_decode_insn,
 101         print_insn_aarch64_word, print_insn_data): Take errors struct.
 102         (print_insn_aarch64): Use errors.
 103         * aarch64-asm-2.c: Regenerate.
 104         * aarch64-dis-2.c: Regenerate.
 105         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 106         boolean in aarch64_insert_operan.
 107         (print_operand_extractor): Likewise.
 108         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 109
 110 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 111
 112         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 113
 114 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 117
 118 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 119
 120         * cr16-opc.c (cr16_instruction): Comment typo fix.
 121         * hppa-dis.c (print_insn_hppa): Likewise.
 122
 123 2018-05-08  Jim Wilson  <jimw@sifive.com>
 124
 125         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 126         (match_c_slli64, match_srxi_as_c_srxi): New.
 127         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 128         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 129         <c.slli, c.srli, c.srai>: Use match_s_slli.
 130         <c.slli64, c.srli64, c.srai64>: New.
 131
 132 2018-05-08  Alan Modra  <amodra@gmail.com>
 133
 134         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 135         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 136         partition opcode space for index lookup.
 137
 138 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 139
 140         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 141         <insn_length>: ...with this.  Update usage.
 142         Remove duplicate call to *info->memory_error_func.
 143
 144 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 145             H.J. Lu  <hongjiu.lu@intel.com>
 146
 147         * i386-dis.c (Gva): New.
 148         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 149         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 150         (prefix_table): New instructions (see prefix above).
 151         (mod_table): New instructions (see prefix above).
 152         (OP_G): Handle va_mode.
 153         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 154         CPU_MOVDIR64B_FLAGS.
 155         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 156         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 157         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 158         * i386-opc.tbl: Add movidir{i,64b}.
 159         * i386-init.h: Regenerated.
 160         * i386-tbl.h: Likewise.
 161
 162 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 165         AddrPrefixOpReg.
 166         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 167         (AddrPrefixOpReg): This.
 168         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 169         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 170
 171 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 172
 173         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 174         (vle_num_opcodes): Likewise.
 175         (spe2_num_opcodes): Likewise.
 176         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 177         initialization loop.
 178         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 179         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 180         only once.
 181
 182 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 183
 184         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 185
 186 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 187
 188         Makefile.am: Added nfp-dis.c.
 189         configure.ac: Added bfd_nfp_arch.
 190         disassemble.h: Added print_insn_nfp prototype.
 191         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 192         nfp-dis.c: New, for NFP support.
 193         po/POTFILES.in: Added nfp-dis.c to the list.
 194         Makefile.in: Regenerate.
 195         configure: Regenerate.
 196
 197 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 200         templates into their base ones.
 201         * i386-tlb.h: Re-generate.
 202
 203 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 206         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 207         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 208         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 209         * i386-init.h: Re-generate.
 210
 211 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 214         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 215         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 216         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 217         comment.
 218         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 219         and CpuRegMask.
 220         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 221         CpuRegMask: Delete.
 222         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 223         cpuregzmm, and cpuregmask.
 224         * i386-init.h: Re-generate.
 225         * i386-tbl.h: Re-generate.
 226
 227 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 230         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 231         * i386-init.h: Re-generate.
 232
 233 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-gen.c (VexImmExt): Delete.
 236         * i386-opc.h (VexImmExt, veximmext): Delete.
 237         * i386-opc.tbl: Drop all VexImmExt uses.
 238         * i386-tlb.h: Re-generate.
 239
 240 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 243         register-only forms.
 244         * i386-tlb.h: Re-generate.
 245
 246 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 247
 248         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 249
 250 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 251
 252         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 253         PREFIX_0F1C.
 254         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 255         (cpu_flags): Add CpuCLDEMOTE.
 256         * i386-init.h: Regenerate.
 257         * i386-opc.h (enum): Add CpuCLDEMOTE,
 258         (i386_cpu_flags): Add cpucldemote.
 259         * i386-opc.tbl: Add cldemote.
 260         * i386-tbl.h: Regenerate.
 261
 262 2018-04-16  Alan Modra  <amodra@gmail.com>
 263
 264         * Makefile.am: Remove sh5 and sh64 support.
 265         * configure.ac: Likewise.
 266         * disassemble.c: Likewise.
 267         * disassemble.h: Likewise.
 268         * sh-dis.c: Likewise.
 269         * sh64-dis.c: Delete.
 270         * sh64-opc.c: Delete.
 271         * sh64-opc.h: Delete.
 272         * Makefile.in: Regenerate.
 273         * configure: Regenerate.
 274         * po/POTFILES.in: Regenerate.
 275
 276 2018-04-16  Alan Modra  <amodra@gmail.com>
 277
 278         * Makefile.am: Remove w65 support.
 279         * configure.ac: Likewise.
 280         * disassemble.c: Likewise.
 281         * disassemble.h: Likewise.
 282         * w65-dis.c: Delete.
 283         * w65-opc.h: Delete.
 284         * Makefile.in: Regenerate.
 285         * configure: Regenerate.
 286         * po/POTFILES.in: Regenerate.
 287
 288 2018-04-16  Alan Modra  <amodra@gmail.com>
 289
 290         * configure.ac: Remove we32k support.
 291         * configure: Regenerate.
 292
 293 2018-04-16  Alan Modra  <amodra@gmail.com>
 294
 295         * Makefile.am: Remove m88k support.
 296         * configure.ac: Likewise.
 297         * disassemble.c: Likewise.
 298         * disassemble.h: Likewise.
 299         * m88k-dis.c: Delete.
 300         * Makefile.in: Regenerate.
 301         * configure: Regenerate.
 302         * po/POTFILES.in: Regenerate.
 303
 304 2018-04-16  Alan Modra  <amodra@gmail.com>
 305
 306         * Makefile.am: Remove i370 support.
 307         * configure.ac: Likewise.
 308         * disassemble.c: Likewise.
 309         * disassemble.h: Likewise.
 310         * i370-dis.c: Delete.
 311         * i370-opc.c: Delete.
 312         * Makefile.in: Regenerate.
 313         * configure: Regenerate.
 314         * po/POTFILES.in: Regenerate.
 315
 316 2018-04-16  Alan Modra  <amodra@gmail.com>
 317
 318         * Makefile.am: Remove h8500 support.
 319         * configure.ac: Likewise.
 320         * disassemble.c: Likewise.
 321         * disassemble.h: Likewise.
 322         * h8500-dis.c: Delete.
 323         * h8500-opc.h: Delete.
 324         * Makefile.in: Regenerate.
 325         * configure: Regenerate.
 326         * po/POTFILES.in: Regenerate.
 327
 328 2018-04-16  Alan Modra  <amodra@gmail.com>
 329
 330         * configure.ac: Remove tahoe support.
 331         * configure: Regenerate.
 332
 333 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 336         umwait.
 337         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 338         64-bit mode.
 339         * i386-tbl.h: Regenerated.
 340
 341 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 342
 343         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 344         PREFIX_MOD_1_0FAE_REG_6.
 345         (va_mode): New.
 346         (OP_E_register): Use va_mode.
 347         * i386-dis-evex.h (prefix_table):
 348         New instructions (see prefixes above).
 349         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 350         (cpu_flags): Likewise.
 351         * i386-opc.h (enum): Likewise.
 352         (i386_cpu_flags): Likewise.
 353         * i386-opc.tbl: Add umonitor, umwait, tpause.
 354         * i386-init.h: Regenerate.
 355         * i386-tbl.h: Likewise.
 356
 357 2018-04-11  Alan Modra  <amodra@gmail.com>
 358
 359         * opcodes/i860-dis.c: Delete.
 360         * opcodes/i960-dis.c: Delete.
 361         * Makefile.am: Remove i860 and i960 support.
 362         * configure.ac: Likewise.
 363         * disassemble.c: Likewise.
 364         * disassemble.h: Likewise.
 365         * Makefile.in: Regenerate.
 366         * configure: Regenerate.
 367         * po/POTFILES.in: Regenerate.
 368
 369 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         PR binutils/23025
 372         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 373         to 0.
 374         (print_insn): Clear vex instead of vex.evex.
 375
 376 2018-04-04  Nick Clifton  <nickc@redhat.com>
 377
 378         * po/es.po: Updated Spanish translation.
 379
 380 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-gen.c (opcode_modifiers): Delete VecESize.
 383         * i386-opc.h (VecESize): Delete.
 384         (struct i386_opcode_modifier): Delete vecesize.
 385         * i386-opc.tbl: Drop VecESize.
 386         * i386-tlb.h: Re-generate.
 387
 388 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 391         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 392         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 393         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 394         * i386-tlb.h: Re-generate.
 395
 396 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 397
 398         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 399         Fold AVX512 forms
 400         * i386-tlb.h: Re-generate.
 401
 402 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 405         (vex_len_table): Drop Y for vcvt*2si.
 406         (putop): Replace plain 'Y' handling by abort().
 407
 408 2018-03-28  Nick Clifton  <nickc@redhat.com>
 409
 410         PR 22988
 411         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 412         instructions with only a base address register.
 413         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 414         handle AARHC64_OPND_SVE_ADDR_R.
 415         (aarch64_print_operand): Likewise.
 416         * aarch64-asm-2.c: Regenerate.
 417         * aarch64_dis-2.c: Regenerate.
 418         * aarch64-opc-2.c: Regenerate.
 419
 420 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-opc.tbl: Drop VecESize from register only insn forms and
 423         memory forms not allowing broadcast.
 424         * i386-tlb.h: Re-generate.
 425
 426 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 429         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 430         sha256*): Drop Disp<N>.
 431
 432 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-dis.c (EbndS, bnd_swap_mode): New.
 435         (prefix_table): Use EbndS.
 436         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 437         * i386-opc.tbl (bndmov): Move misplaced Load.
 438         * i386-tlb.h: Re-generate.
 439
 440 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 443         templates allowing memory operands and folded ones for register
 444         only flavors.
 445         * i386-tlb.h: Re-generate.
 446
 447 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 450         256-bit templates. Drop redundant leftover Disp<N>.
 451         * i386-tlb.h: Re-generate.
 452
 453 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 454
 455         * riscv-opc.c (riscv_insn_types): New.
 456
 457 2018-03-13  Nick Clifton  <nickc@redhat.com>
 458
 459         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 460
 461 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-opc.tbl: Add Optimize to clr.
 464         * i386-tbl.h: Regenerated.
 465
 466 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 469         * i386-opc.h (OldGcc): Removed.
 470         (i386_opcode_modifier): Remove oldgcc.
 471         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 472         instructions for old (<= 2.8.1) versions of gcc.
 473         * i386-tbl.h: Regenerated.
 474
 475 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.h (EVEXDYN): New.
 478         * i386-opc.tbl: Fold various AVX512VL templates.
 479         * i386-tlb.h: Re-generate.
 480
 481 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 484         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 485         vpexpandd, vpexpandq): Fold AFX512VF templates.
 486         * i386-tlb.h: Re-generate.
 487
 488 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 491         Fold 128- and 256-bit VEX-encoded templates.
 492         * i386-tlb.h: Re-generate.
 493
 494 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 497         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 498         vpexpandd, vpexpandq): Fold AVX512F templates.
 499         * i386-tlb.h: Re-generate.
 500
 501 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 504         64-bit templates. Drop Disp<N>.
 505         * i386-tlb.h: Re-generate.
 506
 507 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 510         and 256-bit templates.
 511         * i386-tlb.h: Re-generate.
 512
 513 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 516         * i386-tlb.h: Re-generate.
 517
 518 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 521         Drop NoAVX.
 522         * i386-tlb.h: Re-generate.
 523
 524 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 527         * i386-tlb.h: Re-generate.
 528
 529 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-gen.c (opcode_modifiers): Delete FloatD.
 532         * i386-opc.h (FloatD): Delete.
 533         (struct i386_opcode_modifier): Delete floatd.
 534         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 535         FloatD by D.
 536         * i386-tlb.h: Re-generate.
 537
 538 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 541
 542 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 545         * i386-tlb.h: Re-generate.
 546
 547 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 550         forms.
 551         * i386-tlb.h: Re-generate.
 552
 553 2018-03-07  Alan Modra  <amodra@gmail.com>
 554
 555         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 556         bfd_arch_rs6000.
 557         * disassemble.h (print_insn_rs6000): Delete.
 558         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 559         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 560         (print_insn_rs6000): Delete.
 561
 562 2018-03-03  Alan Modra  <amodra@gmail.com>
 563
 564         * sysdep.h (opcodes_error_handler): Define.
 565         (_bfd_error_handler): Declare.
 566         * Makefile.am: Remove stray #.
 567         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 568         EDIT" comment.
 569         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 570         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 571         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 572         opcodes_error_handler to print errors.  Standardize error messages.
 573         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 574         and include opintl.h.
 575         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 576         * i386-gen.c: Standardize error messages.
 577         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 578         * Makefile.in: Regenerate.
 579         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 580         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 581         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 582         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 583         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 584         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 585         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 586         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 587         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 588         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 589         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 590         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 591         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 592
 593 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 596         vpsub[bwdq] instructions.
 597         * i386-tbl.h: Regenerated.
 598
 599 2018-03-01  Alan Modra  <amodra@gmail.com>
 600
 601         * configure.ac (ALL_LINGUAS): Sort.
 602         * configure: Regenerate.
 603
 604 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 605
 606         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 607         macro by assignements.
 608
 609 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 610
 611         PR gas/22871
 612         * i386-gen.c (opcode_modifiers): Add Optimize.
 613         * i386-opc.h (Optimize): New enum.
 614         (i386_opcode_modifier): Add optimize.
 615         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 616         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 617         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 618         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 619         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 620         vpxord and vpxorq.
 621         * i386-tbl.h: Regenerated.
 622
 623 2018-02-26  Alan Modra  <amodra@gmail.com>
 624
 625         * crx-dis.c (getregliststring): Allocate a large enough buffer
 626         to silence false positive gcc8 warning.
 627
 628 2018-02-22  Shea Levy <shea@shealevy.com>
 629
 630         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 631
 632 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         * i386-opc.tbl: Add {rex},
 635         * i386-tbl.h: Regenerated.
 636
 637 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 638
 639         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 640         (mips16_opcodes): Replace `M' with `m' for "restore".
 641
 642 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 643
 644         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 645
 646 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 647
 648         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 649         variable to `function_index'.
 650
 651 2018-02-13  Nick Clifton  <nickc@redhat.com>
 652
 653         PR 22823
 654         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 655         about truncation of printing.
 656
 657 2018-02-12  Henry Wong <henry@stuffedcow.net>
 658
 659         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 660
 661 2018-02-05  Nick Clifton  <nickc@redhat.com>
 662
 663         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 664
 665 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 666
 667         * i386-dis.c (enum): Add pconfig.
 668         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 669         (cpu_flags): Add CpuPCONFIG.
 670         * i386-opc.h (enum): Add CpuPCONFIG.
 671         (i386_cpu_flags): Add cpupconfig.
 672         * i386-opc.tbl: Add PCONFIG instruction.
 673         * i386-init.h: Regenerate.
 674         * i386-tbl.h: Likewise.
 675
 676 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 677
 678         * i386-dis.c (enum): Add PREFIX_0F09.
 679         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 680         (cpu_flags): Add CpuWBNOINVD.
 681         * i386-opc.h (enum): Add CpuWBNOINVD.
 682         (i386_cpu_flags): Add cpuwbnoinvd.
 683         * i386-opc.tbl: Add WBNOINVD instruction.
 684         * i386-init.h: Regenerate.
 685         * i386-tbl.h: Likewise.
 686
 687 2018-01-17  Jim Wilson  <jimw@sifive.com>
 688
 689         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 690
 691 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 692
 693         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 694         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 695         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 696         (cpu_flags): Add CpuIBT, CpuSHSTK.
 697         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 698         (i386_cpu_flags): Add cpuibt, cpushstk.
 699         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 700         * i386-init.h: Regenerate.
 701         * i386-tbl.h: Likewise.
 702
 703 2018-01-16  Nick Clifton  <nickc@redhat.com>
 704
 705         * po/pt_BR.po: Updated Brazilian Portugese translation.
 706         * po/de.po: Updated German translation.
 707
 708 2018-01-15  Jim Wilson  <jimw@sifive.com>
 709
 710         * riscv-opc.c (match_c_nop): New.
 711         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 712
 713 2018-01-15  Nick Clifton  <nickc@redhat.com>
 714
 715         * po/uk.po: Updated Ukranian translation.
 716
 717 2018-01-13  Nick Clifton  <nickc@redhat.com>
 718
 719         * po/opcodes.pot: Regenerated.
 720
 721 2018-01-13  Nick Clifton  <nickc@redhat.com>
 722
 723         * configure: Regenerate.
 724
 725 2018-01-13  Nick Clifton  <nickc@redhat.com>
 726
 727         2.30 branch created.
 728
 729 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 730
 731         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 732         * i386-tbl.h: Regenerate.
 733
 734 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 737         * i386-tbl.h: Re-generate.
 738
 739 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 742         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 743         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 744         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 745         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 746         Disp8MemShift of AVX512VL forms.
 747         * i386-tbl.h: Re-generate.
 748
 749 2018-01-09  Jim Wilson  <jimw@sifive.com>
 750
 751         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 752         then the hi_addr value is zero.
 753
 754 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 755
 756         * arm-dis.c (arm_opcodes): Add csdb.
 757         (thumb32_opcodes): Add csdb.
 758
 759 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 760
 761         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 762         * aarch64-asm-2.c: Regenerate.
 763         * aarch64-dis-2.c: Regenerate.
 764         * aarch64-opc-2.c: Regenerate.
 765
 766 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         PR gas/22681
 769         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 770         Remove AVX512 vmovd with 64-bit operands.
 771         * i386-tbl.h: Regenerated.
 772
 773 2018-01-05  Jim Wilson  <jimw@sifive.com>
 774
 775         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 776         jalr.
 777
 778 2018-01-03  Alan Modra  <amodra@gmail.com>
 779
 780         Update year range in copyright notice of all files.
 781
 782 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 783
 784         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 785         and OPERAND_TYPE_REGZMM entries.
 786
 787 For older changes see ChangeLog-2017
 788 \f
 789 Copyright (C) 2018 Free Software Foundation, Inc.
 790
 791 Copying and distribution of this file, with or without modification,
 792 are permitted in any medium without royalty provided the copyright
 793 notice and this notice are preserved.
 794
 795 Local Variables:
 796 mode: change-log
 797 left-margin: 8
 798 fill-column: 74
 799 version-control: never
 800 End: