opcodes/alpha-opc.c

   1 /* alpha-opc.c -- Alpha AXP opcode list
   2    Copyright 1996 Free Software Foundation, Inc.
   3    Contributed by Richard Henderson <rth@tamu.edu>,
   4    patterned after the PPC opcode handling written by Ian Lance Taylor.
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "ansidecl.h"
  25 #include "opcode/alpha.h"
  26
  27 /* This file holds the Alpha AXP opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions */
  39
  40 static unsigned insert_rba PARAMS((unsigned, int, const char **));
  41 static unsigned insert_rca PARAMS((unsigned, int, const char **));
  42 static unsigned insert_za PARAMS((unsigned, int, const char **));
  43 static unsigned insert_zb PARAMS((unsigned, int, const char **));
  44 static unsigned insert_zc PARAMS((unsigned, int, const char **));
  45 static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
  46 static unsigned insert_jhint PARAMS((unsigned, int, const char **));
  47
  48 static int extract_rba PARAMS((unsigned, int *));
  49 static int extract_rca PARAMS((unsigned, int *));
  50 static int extract_za PARAMS((unsigned, int *));
  51 static int extract_zb PARAMS((unsigned, int *));
  52 static int extract_zc PARAMS((unsigned, int *));
  53 static int extract_bdisp PARAMS((unsigned, int *));
  54 static int extract_jhint PARAMS((unsigned, int *));
  55
  56 \f
  57 /* The operands table  */
  58
  59 const struct alpha_operand alpha_operands[] =
  60 {
  61   /* The fields are bits, shift, insert, extract, flags */
  62   /* The zero index is used to indicate end-of-list */
  63 #define UNUSED          0
  64   { 0, 0, BFD_RELOC_UNUSED, 0, 0 },
  65
  66   /* The plain integer register fields */
  67 #define RA              (UNUSED + 1)
  68   { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
  69 #define RB              (RA + 1)
  70   { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
  71 #define RC              (RB + 1)
  72   { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
  73
  74   /* The plain fp register fields */
  75 #define FA              (RC + 1)
  76   { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
  77 #define FB              (FA + 1)
  78   { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
  79 #define FC              (FB + 1)
  80   { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
  81
  82   /* The integer registers when they are ZERO */
  83 #define ZA              (FC + 1)
  84   { 5, 21, BFD_RELOC_UNUSED, insert_za, extract_za, AXP_OPERAND_FAKE },
  85 #define ZB              (ZA + 1)
  86   { 5, 16, BFD_RELOC_UNUSED, insert_zb, extract_zb, AXP_OPERAND_FAKE },
  87 #define ZC              (ZB + 1)
  88   { 5, 0, BFD_RELOC_UNUSED, insert_zc, extract_zc, AXP_OPERAND_FAKE },
  89
  90   /* The RB field when it needs parentheses */
  91 #define PRB             (ZC + 1)
  92   { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS },
  93
  94   /* The RB field when it needs parentheses _and_ a preceding comma */
  95 #define CPRB            (PRB + 1)
  96   { 5, 16, BFD_RELOC_UNUSED, 0, 0,
  97     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA },
  98
  99   /* The RB field when it must be the same as the RA field */
 100 #define RBA             (CPRB + 1)
 101   { 5, 16, BFD_RELOC_UNUSED, insert_rba, extract_rba, AXP_OPERAND_FAKE },
 102
 103   /* The RC field when it must be the same as the RB field */
 104 #define RCA             (RBA + 1)
 105   { 5, 0, BFD_RELOC_UNUSED, insert_rca, extract_rca, AXP_OPERAND_FAKE },
 106
 107   /* The RC field when it can *default* to RA */
 108 #define DRC1            (RCA + 1)
 109   { 5, 0, BFD_RELOC_UNUSED, 0, 0,
 110     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST },
 111
 112   /* The RC field when it can *default* to RB */
 113 #define DRC2            (DRC1 + 1)
 114   { 5, 0, BFD_RELOC_UNUSED, 0, 0,
 115     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND },
 116
 117   /* The FC field when it can *default* to RA */
 118 #define DFC1            (DRC2 + 1)
 119   { 5, 0, BFD_RELOC_UNUSED, 0, 0,
 120     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST },
 121
 122   /* The FC field when it can *default* to RB */
 123 #define DFC2            (DFC1 + 1)
 124   { 5, 0, BFD_RELOC_UNUSED, 0, 0,
 125     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND },
 126
 127   /* The unsigned 8-bit literal of Operate format insns */
 128 #define LIT             (DFC2 + 1)
 129   { 8, 13, BFD_RELOC_UNUSED+LIT, 0, 0, AXP_OPERAND_UNSIGNED },
 130
 131   /* The signed 16-bit displacement of Memory format insns.  From here
 132      we can't tell what relocation should be used, so don't use a default. */
 133 #define MDISP           (LIT + 1)
 134   { 16, 0, BFD_RELOC_UNUSED+MDISP, 0, 0, AXP_OPERAND_SIGNED },
 135
 136   /* The signed "23-bit" aligned displacement of Branch format insns */
 137 #define BDISP           (MDISP + 1)
 138   { 21, 0, BFD_RELOC_23_PCREL_S2, insert_bdisp, extract_bdisp,
 139     AXP_OPERAND_RELATIVE },
 140
 141   /* The 26-bit PALcode function */
 142 #define PALFN           (BDISP + 1)
 143   { 26, 0, BFD_RELOC_UNUSED+PALFN, 0, 0, AXP_OPERAND_UNSIGNED },
 144
 145   /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
 146 #define JMPHINT         (PALFN + 1)
 147   { 14, 0, BFD_RELOC_ALPHA_HINT, insert_jhint, extract_jhint,
 148     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW },
 149
 150   /* The optional hint to RET/JSR_COROUTINE */
 151 #define RETHINT         (JMPHINT + 1)
 152   { 14, 0, BFD_RELOC_UNUSED+RETHINT, 0, 0,
 153     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO },
 154
 155   /* The 12-bit displacement for the ev4 hw_{ld,st} (pal1b/pal1f) insns */
 156 #define EV4HWDISP       (RETHINT + 1)
 157   { 12, 0, BFD_RELOC_UNUSED+EV4HWDISP, 0, 0, AXP_OPERAND_SIGNED },
 158
 159   /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
 160 #define EV4HWINDEX      (EV4HWDISP + 1)
 161   { 5, 0, BFD_RELOC_UNUSED+EV4HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
 162
 163   /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
 164      that occur in DEC PALcode.  */
 165 #define EV4EXTHWINDEX   (EV4HWINDEX + 1)
 166   { 5, 0, BFD_RELOC_UNUSED+EV4EXTHWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
 167
 168   /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
 169 #define EV5HWDISP       (EV4EXTHWINDEX + 1)
 170   { 10, 0, BFD_RELOC_UNUSED+EV5HWDISP, 0, 0, AXP_OPERAND_SIGNED },
 171
 172   /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
 173 #define EV5HWINDEX      (EV5HWDISP + 1)
 174   { 16, 0, BFD_RELOC_UNUSED+EV5HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
 175 };
 176
 177 const int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
 178
 179 /* The RB field when it is the same as the RA field in the same insn.
 180    This operand is marked fake.  The insertion function just copies
 181    the RA field into the RB field, and the extraction function just
 182    checks that the fields are the same. */
 183
 184 /*ARGSUSED*/
 185 static unsigned
 186 insert_rba(insn, value, errmsg)
 187      unsigned insn;
 188      int value;
 189      const char **errmsg;
 190 {
 191   return insn | (((insn >> 21) & 0x1f) << 16);
 192 }
 193
 194 static int
 195 extract_rba(insn, invalid)
 196      unsigned insn;
 197      int *invalid;
 198 {
 199   if (invalid != (int *) NULL
 200       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 201     *invalid = 1;
 202   return 0;
 203 }
 204
 205
 206 /* The same for the RC field */
 207
 208 /*ARGSUSED*/
 209 static unsigned
 210 insert_rca(insn, value, errmsg)
 211      unsigned insn;
 212      int value;
 213      const char **errmsg;
 214 {
 215   return insn | ((insn >> 21) & 0x1f);
 216 }
 217
 218 static int
 219 extract_rca(insn, invalid)
 220      unsigned insn;
 221      int *invalid;
 222 {
 223   if (invalid != (int *) NULL
 224       && ((insn >> 21) & 0x1f) != (insn & 0x1f))
 225     *invalid = 1;
 226   return 0;
 227 }
 228
 229
 230 /* Fake arguments in which the registers must be set to ZERO */
 231
 232 /*ARGSUSED*/
 233 static unsigned
 234 insert_za(insn, value, errmsg)
 235      unsigned insn;
 236      int value;
 237      const char **errmsg;
 238 {
 239   return insn | (31 << 21);
 240 }
 241
 242 static int
 243 extract_za(insn, invalid)
 244      unsigned insn;
 245      int *invalid;
 246 {
 247   if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
 248     *invalid = 1;
 249   return 0;
 250 }
 251
 252 /*ARGSUSED*/
 253 static unsigned
 254 insert_zb(insn, value, errmsg)
 255      unsigned insn;
 256      int value;
 257      const char **errmsg;
 258 {
 259   return insn | (31 << 16);
 260 }
 261
 262 static int
 263 extract_zb(insn, invalid)
 264      unsigned insn;
 265      int *invalid;
 266 {
 267   if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
 268     *invalid = 1;
 269   return 0;
 270 }
 271
 272 /*ARGSUSED*/
 273 static unsigned
 274 insert_zc(insn, value, errmsg)
 275      unsigned insn;
 276      int value;
 277      const char **errmsg;
 278 {
 279   return insn | 31;
 280 }
 281
 282 static int
 283 extract_zc(insn, invalid)
 284      unsigned insn;
 285      int *invalid;
 286 {
 287   if (invalid != (int *) NULL && (insn & 0x1f) != 31)
 288     *invalid = 1;
 289   return 0;
 290 }
 291
 292
 293 /* The displacement field of a Branch format insn.  */
 294
 295 static unsigned
 296 insert_bdisp(insn, value, errmsg)
 297      unsigned insn;
 298      int value;
 299      const char **errmsg;
 300 {
 301   if (errmsg != (const char **)NULL && (value & 3))
 302     *errmsg = "branch operand unaligned";
 303   return insn | ((value / 4) & 0x1FFFFF);
 304 }
 305
 306 /*ARGSUSED*/
 307 static int
 308 extract_bdisp(insn, invalid)
 309      unsigned insn;
 310      int *invalid;
 311 {
 312   return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
 313 }
 314
 315
 316 /* The hint field of a JMP/JSR insn.  */
 317
 318 static unsigned
 319 insert_jhint(insn, value, errmsg)
 320      unsigned insn;
 321      int value;
 322      const char **errmsg;
 323 {
 324   if (errmsg != (const char **)NULL && (value & 3))
 325     *errmsg = "jump hint unaligned";
 326   return insn | ((value / 4) & 0xFFFF);
 327 }
 328
 329 /*ARGSUSED*/
 330 static int
 331 extract_jhint(insn, invalid)
 332      unsigned insn;
 333      int *invalid;
 334 {
 335   return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
 336 }
 337
 338 \f
 339 /* Macros used to form opcodes */
 340
 341 /* The main opcode */
 342 #define OP(x)           (((x) & 0x3F) << 26)
 343 #define OP_MASK         0xFC000000
 344
 345 /* Branch format instructions */
 346 #define BRA_(oo)        OP(oo)
 347 #define BRA_MASK        OP_MASK
 348 #define BRA(oo)         BRA_(oo), BRA_MASK
 349
 350 /* Floating point format instructions */
 351 #define FP_(oo,fff)     (OP(oo) | (((fff) & 0x7FF) << 5))
 352 #define FP_MASK         (OP_MASK | 0xFFE0)
 353 #define FP(oo,fff)      FP_(oo,fff), FP_MASK
 354
 355 /* Memory format instructions */
 356 #define MEM_(oo)        OP(oo)
 357 #define MEM_MASK        OP_MASK
 358 #define MEM(oo)         MEM_(oo), MEM_MASK
 359
 360 /* Memory/Func Code format instructions */
 361 #define MFC_(oo,ffff)   (OP(oo) | ((ffff) & 0xFFFF))
 362 #define MFC_MASK        (OP_MASK | 0xFFFF)
 363 #define MFC(oo,ffff)    MFC_(oo,ffff), MFC_MASK
 364
 365 /* Memory/Branch format instructions */
 366 #define MBR_(oo,h)      (OP(oo) | (((h) & 3) << 14))
 367 #define MBR_MASK        (OP_MASK | 0xC000)
 368 #define MBR(oo,h)       MBR_(oo,h), MBR_MASK
 369
 370 /* Operate format instructions.  The OPRL variant specifies a
 371    literal second argument. */
 372 #define OPR_(oo,ff)     (OP(oo) | (((ff) & 0x7F) << 5))
 373 #define OPRL_(oo,ff)    (OPR_((oo),(ff)) | 0x1000)
 374 #define OPR_MASK        (OP_MASK | 0x1FE0)
 375 #define OPR(oo,ff)      OPR_(oo,ff), OPR_MASK
 376 #define OPRL(oo,ff)     OPRL_(oo,ff), OPR_MASK
 377
 378 /* Generic PALcode format instructions */
 379 #define PCD_(oo)        OP(oo)
 380 #define PCD_MASK        OP_MASK
 381 #define PCD(oo)         PCD_(oo), PCD_MASK
 382
 383 /* Specific PALcode instructions */
 384 #define SPCD_(oo,ffff)  (OP(oo) | ((ffff) & 0x3FFFFFF))
 385 #define SPCD_MASK       0xFFFFFFFF
 386 #define SPCD(oo,ffff)   SPCD_(oo,ffff), SPCD_MASK
 387
 388 /* Hardware memory (hw_{ld,st}) instructions */
 389 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
 390 #define EV4HWMEM_MASK   (OP_MASK | 0xF000)
 391 #define EV4HWMEM(oo,f)  EV4HWMEM_(oo,f), EV4HWMEM_MASK
 392
 393 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
 394 #define EV5HWMEM_MASK   (OP_MASK | 0xF800)
 395 #define EV5HWMEM(oo,f)  EV5HWMEM_(oo,f), EV5HWMEM_MASK
 396
 397 /* Common combinations of flags and arguments */
 398 #define ALL                     AXP_OPCODE_ALL
 399 #define EV4                     AXP_OPCODE_EV4
 400 #define EV5                     AXP_OPCODE_EV5
 401 #define EV56                    AXP_OPCODE_EV56
 402 #define EV5x                    EV5|EV56
 403
 404 #define ARG_NONE                { 0 }
 405 #define ARG_BRA                 { RA, BDISP }
 406 #define ARG_FBRA                { FA, BDISP }
 407 #define ARG_FP                  { FA, FB, DFC1 }
 408 #define ARG_FPZ1                { ZA, FB, DFC1 }
 409 #define ARG_MEM                 { RA, MDISP, PRB }
 410 #define ARG_FMEM                { FA, MDISP, PRB }
 411 #define ARG_OPR                 { RA, RB, DRC1 }
 412 #define ARG_OPRL                { RA, LIT, DRC1 }
 413 #define ARG_OPRZ1               { ZA, RB, DRC1 }
 414 #define ARG_OPRLZ1              { ZA, LIT, RC }
 415 #define ARG_PCD                 { PALFN }
 416 #define ARG_EV4HWMEM            { RA, EV4HWDISP, PRB }
 417 #define ARG_EV4HWMPR            { RA, RBA, EV4HWINDEX }
 418 #define ARG_EV5HWMEM            { RA, EV5HWDISP, PRB }
 419
 420 \f
 421 /* The opcode table.
 422
 423    The format of the opcode table is:
 424
 425    NAME OPCODE MASK { OPERANDS }
 426
 427    NAME         is the name of the instruction.
 428
 429    OPCODE       is the instruction opcode.
 430
 431    MASK         is the opcode mask; this is used to tell the disassembler
 432                 which bits in the actual opcode must match OPCODE.
 433
 434    OPERANDS     is the list of operands.
 435
 436    The preceding macros merge the text of the OPCODE and MASK fields.
 437
 438    The disassembler reads the table in order and prints the first
 439    instruction which matches, so this table is sorted to put more
 440    specific instructions before more general instructions.
 441
 442    Otherwise, it is sorted by major opcode and minor function code.
 443
 444    There are three classes of not-really-instructions in this table:
 445
 446    ALIAS        is another name for another instruction.  Some of
 447                 these come from the Architecture Handbook, some
 448                 come from the original gas opcode tables.  In all
 449                 cases, the functionality of the opcode is unchanged.
 450
 451    PSEUDO       a stylized code form endorsed by Chapter A.4 of the
 452                 Architecture Handbook.
 453
 454    EXTRA        a stylized code form found in the original gas tables.
 455
 456    XXX: Can anyone shed light on the pal{19,1b,1d,1e,1f} opcodes?
 457    XXX: Do we want to conditionally compile complete sets of the
 458         PALcodes described in the Architecture Handbook?
 459 */
 460
 461 const struct alpha_opcode alpha_opcodes[] = {
 462   { "halt",             SPCD(0x00,0x0000), ALL, ARG_NONE },
 463   { "draina",           SPCD(0x00,0x0002), ALL, ARG_NONE },
 464   { "bpt",              SPCD(0x00,0x0080), ALL, ARG_NONE },
 465   { "callsys",          SPCD(0x00,0x0083), ALL, ARG_NONE },
 466   { "chmk",             SPCD(0x00,0x0083), ALL, ARG_NONE },
 467   { "imb",              SPCD(0x00,0x0086), ALL, ARG_NONE },
 468   { "call_pal",         PCD(0x00), ALL, ARG_PCD },
 469   { "pal",              PCD(0x00), ALL, ARG_PCD },              /* alias */
 470
 471   { "lda",              MEM(0x08), ALL, ARG_MEM },
 472   { "ldah",             MEM(0x09), ALL, ARG_MEM },
 473   { "unop",             MEM(0x0B), ALL, { ZA } },               /* pseudo */
 474   { "ldq_u",            MEM(0x0B), ALL, ARG_MEM },
 475   { "stq_u",            MEM(0x0F), ALL, ARG_MEM },
 476
 477   { "sextl",            OPR(0x10,0x00), ALL, ARG_OPRZ1 },       /* pseudo */
 478   { "sextl",            OPRL(0x10,0x00), ALL, ARG_OPRLZ1 },     /* pseudo */
 479   { "addl",             OPR(0x10,0x00), ALL, ARG_OPR },
 480   { "addl",             OPRL(0x10,0x00), ALL, ARG_OPRL },
 481   { "s4addl",           OPR(0x10,0x02), ALL, ARG_OPR },
 482   { "s4addl",           OPRL(0x10,0x02), ALL, ARG_OPRL },
 483   { "negl",             OPR(0x10,0x09), ALL, ARG_OPRZ1 },       /* pseudo */
 484   { "negl",             OPRL(0x10,0x09), ALL, ARG_OPRLZ1 },     /* pseudo */
 485   { "subl",             OPR(0x10,0x09), ALL, ARG_OPR },
 486   { "subl",             OPRL(0x10,0x09), ALL, ARG_OPRL },
 487   { "s4subl",           OPR(0x10,0x0B), ALL, ARG_OPR },
 488   { "s4subl",           OPRL(0x10,0x0B), ALL, ARG_OPRL },
 489   { "cmpbge",           OPR(0x10,0x0F), ALL, ARG_OPR },
 490   { "cmpbge",           OPRL(0x10,0x0F), ALL, ARG_OPRL },
 491   { "s8addl",           OPR(0x10,0x12), ALL, ARG_OPR },
 492   { "s8addl",           OPRL(0x10,0x12), ALL, ARG_OPRL },
 493   { "s8subl",           OPR(0x10,0x1B), ALL, ARG_OPR },
 494   { "s8subl",           OPRL(0x10,0x1B), ALL, ARG_OPRL },
 495   { "cmpult",           OPR(0x10,0x1D), ALL, ARG_OPR },
 496   { "cmpult",           OPRL(0x10,0x1D), ALL, ARG_OPRL },
 497   { "addq",             OPR(0x10,0x20), ALL, ARG_OPR },
 498   { "addq",             OPRL(0x10,0x20), ALL, ARG_OPRL },
 499   { "s4addq",           OPR(0x10,0x22), ALL, ARG_OPR },
 500   { "s4addq",           OPRL(0x10,0x22), ALL, ARG_OPRL },
 501   { "negq",             OPR(0x10,0x29), ALL, ARG_OPRZ1 },       /* pseudo */
 502   { "negq",             OPRL(0x10,0x29), ALL, ARG_OPRLZ1 },     /* pseudo */
 503   { "subq",             OPR(0x10,0x29), ALL, ARG_OPR },
 504   { "subq",             OPRL(0x10,0x29), ALL, ARG_OPRL },
 505   { "s4subq",           OPR(0x10,0x2B), ALL, ARG_OPR },
 506   { "s4subq",           OPRL(0x10,0x2B), ALL, ARG_OPRL },
 507   { "cmpeq",            OPR(0x10,0x2D), ALL, ARG_OPR },
 508   { "cmpeq",            OPRL(0x10,0x2D), ALL, ARG_OPRL },
 509   { "s8addq",           OPR(0x10,0x32), ALL, ARG_OPR },
 510   { "s8addq",           OPRL(0x10,0x32), ALL, ARG_OPRL },
 511   { "s8subq",           OPR(0x10,0x3B), ALL, ARG_OPR },
 512   { "s8subq",           OPRL(0x10,0x3B), ALL, ARG_OPRL },
 513   { "cmpule",           OPR(0x10,0x3D), ALL, ARG_OPR },
 514   { "cmpule",           OPRL(0x10,0x3D), ALL, ARG_OPRL },
 515   { "addl/v",           OPR(0x10,0x40), ALL, ARG_OPR },
 516   { "addl/v",           OPRL(0x10,0x40), ALL, ARG_OPRL },
 517   { "negl/v",           OPR(0x10,0x49), ALL, ARG_OPRZ1 },       /* pseudo */
 518   { "negl/v",           OPRL(0x10,0x49), ALL, ARG_OPRLZ1 },     /* pseudo */
 519   { "subl/v",           OPR(0x10,0x49), ALL, ARG_OPR },
 520   { "subl/v",           OPRL(0x10,0x49), ALL, ARG_OPRL },
 521   { "cmplt",            OPR(0x10,0x4D), ALL, ARG_OPR },
 522   { "cmplt",            OPRL(0x10,0x4D), ALL, ARG_OPRL },
 523   { "addq/v",           OPR(0x10,0x60), ALL, ARG_OPR },
 524   { "addq/v",           OPRL(0x10,0x60), ALL, ARG_OPRL },
 525   { "negq/v",           OPR(0x10,0x69), ALL, ARG_OPRZ1 },       /* pseudo */
 526   { "negq/v",           OPRL(0x10,0x69), ALL, ARG_OPRLZ1 },     /* pseudo */
 527   { "subq/v",           OPR(0x10,0x69), ALL, ARG_OPR },
 528   { "subq/v",           OPRL(0x10,0x69), ALL, ARG_OPRL },
 529   { "cmple",            OPR(0x10,0x6D), ALL, ARG_OPR },
 530   { "cmple",            OPRL(0x10,0x6D), ALL, ARG_OPRL },
 531
 532   { "and",              OPR(0x11,0x00), ALL, ARG_OPR },
 533   { "and",              OPRL(0x11,0x00), ALL, ARG_OPRL },
 534   { "andnot",           OPR(0x11,0x08), ALL, ARG_OPR },         /* alias */
 535   { "andnot",           OPRL(0x11,0x08), ALL, ARG_OPRL },       /* alias */
 536   { "bic",              OPR(0x11,0x08), ALL, ARG_OPR },
 537   { "bic",              OPRL(0x11,0x08), ALL, ARG_OPRL },
 538   { "cmovlbs",          OPR(0x11,0x14), ALL, ARG_OPR },
 539   { "cmovlbs",          OPRL(0x11,0x14), ALL, ARG_OPRL },
 540   { "cmovlbc",          OPR(0x11,0x16), ALL, ARG_OPR },
 541   { "cmovlbc",          OPRL(0x11,0x16), ALL, ARG_OPRL },
 542   { "nop",              OPR(0x11,0x20), ALL, { ZA, ZB, ZC } }, /* pseudo */
 543   { "clr",              OPR(0x11,0x20), ALL, { ZA, ZB, RC } }, /* pseudo */
 544   { "mov",              OPR(0x11,0x20), ALL, { ZA, RB, RC } }, /* pseudo */
 545   { "mov",              OPR(0x11,0x20), ALL, { RA, RBA, RC } }, /* pseudo */
 546   { "mov",              OPRL(0x11,0x20), ALL, { ZA, LIT, RC } }, /* pseudo */
 547   { "or",               OPR(0x11,0x20), ALL, ARG_OPR },         /* alias */
 548   { "or",               OPRL(0x11,0x20), ALL, ARG_OPRL },       /* alias */
 549   { "bis",              OPR(0x11,0x20), ALL, ARG_OPR },
 550   { "bis",              OPRL(0x11,0x20), ALL, ARG_OPRL },
 551   { "cmoveq",           OPR(0x11,0x24), ALL, ARG_OPR },
 552   { "cmoveq",           OPRL(0x11,0x24), ALL, ARG_OPRL },
 553   { "cmovne",           OPR(0x11,0x26), ALL, ARG_OPR },
 554   { "cmovne",           OPRL(0x11,0x26), ALL, ARG_OPRL },
 555   { "not",              OPR(0x11,0x28), ALL, ARG_OPRZ1 },       /* pseudo */
 556   { "not",              OPRL(0x11,0x28), ALL, ARG_OPRLZ1 },     /* pseudo */
 557   { "ornot",            OPR(0x11,0x28), ALL, ARG_OPR },
 558   { "ornot",            OPRL(0x11,0x28), ALL, ARG_OPRL },
 559   { "xor",              OPR(0x11,0x40), ALL, ARG_OPR },
 560   { "xor",              OPRL(0x11,0x40), ALL, ARG_OPRL },
 561   { "cmovlt",           OPR(0x11,0x44), ALL, ARG_OPR },
 562   { "cmovlt",           OPRL(0x11,0x44), ALL, ARG_OPRL },
 563   { "cmovge",           OPR(0x11,0x46), ALL, ARG_OPR },
 564   { "cmovge",           OPRL(0x11,0x46), ALL, ARG_OPRL },
 565   { "eqv",              OPR(0x11,0x48), ALL, ARG_OPR },
 566   { "eqv",              OPRL(0x11,0x48), ALL, ARG_OPRL },
 567   { "xornot",           OPR(0x11,0x48), ALL, ARG_OPR },         /* alias */
 568   { "xornot",           OPRL(0x11,0x48), ALL, ARG_OPRL },       /* alias */
 569   { "amask",            OPR(0x11,0x61), EV56, ARG_OPRZ1 },      /* ev56 */
 570   { "amask",            OPRL(0x11,0x61), EV56, ARG_OPRLZ1 },    /* ev56 */
 571   { "cmovle",           OPR(0x11,0x64), ALL, ARG_OPR },
 572   { "cmovle",           OPRL(0x11,0x64), ALL, ARG_OPRL },
 573   { "cmovgt",           OPR(0x11,0x66), ALL, ARG_OPR },
 574   { "cmovgt",           OPRL(0x11,0x66), ALL, ARG_OPRL },
 575   { "implver",          OPR(0x11,0x6C), ALL, ARG_OPRZ1 },       /* ev56 */
 576   { "implver",          OPRL(0x11,0x6C), ALL, ARG_OPRLZ1 },     /* ev56 */
 577
 578   { "mskbl",            OPR(0x12,0x02), ALL, ARG_OPR },
 579   { "mskbl",            OPRL(0x12,0x02), ALL, ARG_OPRL },
 580   { "extbl",            OPR(0x12,0x06), ALL, ARG_OPR },
 581   { "extbl",            OPRL(0x12,0x06), ALL, ARG_OPRL },
 582   { "insbl",            OPR(0x12,0x0B), ALL, ARG_OPR },
 583   { "insbl",            OPRL(0x12,0x0B), ALL, ARG_OPRL },
 584   { "mskwl",            OPR(0x12,0x12), ALL, ARG_OPR },
 585   { "mskwl",            OPRL(0x12,0x12), ALL, ARG_OPRL },
 586   { "extwl",            OPR(0x12,0x16), ALL, ARG_OPR },
 587   { "extwl",            OPRL(0x12,0x16), ALL, ARG_OPRL },
 588   { "inswl",            OPR(0x12,0x1B), ALL, ARG_OPR },
 589   { "inswl",            OPRL(0x12,0x1B), ALL, ARG_OPRL },
 590   { "mskll",            OPR(0x12,0x22), ALL, ARG_OPR },
 591   { "mskll",            OPRL(0x12,0x22), ALL, ARG_OPRL },
 592   { "extll",            OPR(0x12,0x26), ALL, ARG_OPR },
 593   { "extll",            OPRL(0x12,0x26), ALL, ARG_OPRL },
 594   { "insll",            OPR(0x12,0x2B), ALL, ARG_OPR },
 595   { "insll",            OPRL(0x12,0x2B), ALL, ARG_OPRL },
 596   { "zap",              OPR(0x12,0x30), ALL, ARG_OPR },
 597   { "zap",              OPRL(0x12,0x30), ALL, ARG_OPRL },
 598   { "zapnot",           OPR(0x12,0x31), ALL, ARG_OPR },
 599   { "zapnot",           OPRL(0x12,0x31), ALL, ARG_OPRL },
 600   { "mskql",            OPR(0x12,0x32), ALL, ARG_OPR },
 601   { "mskql",            OPRL(0x12,0x32), ALL, ARG_OPRL },
 602   { "srl",              OPR(0x12,0x34), ALL, ARG_OPR },
 603   { "srl",              OPRL(0x12,0x34), ALL, ARG_OPRL },
 604   { "extql",            OPR(0x12,0x36), ALL, ARG_OPR },
 605   { "extql",            OPRL(0x12,0x36), ALL, ARG_OPRL },
 606   { "sll",              OPR(0x12,0x39), ALL, ARG_OPR },
 607   { "sll",              OPRL(0x12,0x39), ALL, ARG_OPRL },
 608   { "insql",            OPR(0x12,0x3B), ALL, ARG_OPR },
 609   { "insql",            OPRL(0x12,0x3B), ALL, ARG_OPRL },
 610   { "sra",              OPR(0x12,0x3C), ALL, ARG_OPR },
 611   { "sra",              OPRL(0x12,0x3C), ALL, ARG_OPRL },
 612   { "mskwh",            OPR(0x12,0x52), ALL, ARG_OPR },
 613   { "mskwh",            OPRL(0x12,0x52), ALL, ARG_OPRL },
 614   { "inswh",            OPR(0x12,0x57), ALL, ARG_OPR },
 615   { "inswh",            OPRL(0x12,0x57), ALL, ARG_OPRL },
 616   { "extwh",            OPR(0x12,0x5A), ALL, ARG_OPR },
 617   { "extwh",            OPRL(0x12,0x5A), ALL, ARG_OPRL },
 618   { "msklh",            OPR(0x12,0x62), ALL, ARG_OPR },
 619   { "msklh",            OPRL(0x12,0x62), ALL, ARG_OPRL },
 620   { "inslh",            OPR(0x12,0x67), ALL, ARG_OPR },
 621   { "inslh",            OPRL(0x12,0x67), ALL, ARG_OPRL },
 622   { "extlh",            OPR(0x12,0x6A), ALL, ARG_OPR },
 623   { "extlh",            OPRL(0x12,0x6A), ALL, ARG_OPRL },
 624   { "mskqh",            OPR(0x12,0x72), ALL, ARG_OPR },
 625   { "mskqh",            OPRL(0x12,0x72), ALL, ARG_OPRL },
 626   { "insqh",            OPR(0x12,0x77), ALL, ARG_OPR },
 627   { "insqh",            OPRL(0x12,0x77), ALL, ARG_OPRL },
 628   { "extqh",            OPR(0x12,0x7A), ALL, ARG_OPR },
 629   { "extqh",            OPRL(0x12,0x7A), ALL, ARG_OPRL },
 630
 631   { "mull",             OPR(0x13,0x00), ALL, ARG_OPR },
 632   { "mull",             OPRL(0x13,0x00), ALL, ARG_OPRL },
 633   { "mulq",             OPR(0x13,0x20), ALL, ARG_OPR },
 634   { "mulq",             OPRL(0x13,0x20), ALL, ARG_OPRL },
 635   { "umulh",            OPR(0x13,0x30), ALL, ARG_OPR },
 636   { "umulh",            OPRL(0x13,0x30), ALL, ARG_OPRL },
 637   { "mull/v",           OPR(0x13,0x40), ALL, ARG_OPR },
 638   { "mull/v",           OPRL(0x13,0x40), ALL, ARG_OPRL },
 639   { "mulq/v",           OPR(0x13,0x60), ALL, ARG_OPR },
 640   { "mulq/v",           OPRL(0x13,0x60), ALL, ARG_OPRL },
 641
 642   { "addf/c",           FP(0x15,0x000), ALL, ARG_FP },
 643   { "subf/c",           FP(0x15,0x001), ALL, ARG_FP },
 644   { "mulf/c",           FP(0x15,0x002), ALL, ARG_FP },
 645   { "divf/c",           FP(0x15,0x003), ALL, ARG_FP },
 646   { "cvtdg/c",          FP(0x15,0x01E), ALL, ARG_FPZ1 },
 647   { "addg/c",           FP(0x15,0x020), ALL, ARG_FP },
 648   { "subg/c",           FP(0x15,0x021), ALL, ARG_FP },
 649   { "mulg/c",           FP(0x15,0x022), ALL, ARG_FP },
 650   { "divg/c",           FP(0x15,0x023), ALL, ARG_FP },
 651   { "cvtgf/c",          FP(0x15,0x02C), ALL, ARG_FPZ1 },
 652   { "cvtgd/c",          FP(0x15,0x02D), ALL, ARG_FPZ1 },
 653   { "cvtgq/c",          FP(0x15,0x02F), ALL, ARG_FPZ1 },
 654   { "cvtqf/c",          FP(0x15,0x03C), ALL, ARG_FPZ1 },
 655   { "cvtqg/c",          FP(0x15,0x03E), ALL, ARG_FPZ1 },
 656   { "addf",             FP(0x15,0x080), ALL, ARG_FP },
 657   { "negf",             FP(0x15,0x081), ALL, ARG_FPZ1 },        /* pseudo */
 658   { "subf",             FP(0x15,0x081), ALL, ARG_FP },
 659   { "mulf",             FP(0x15,0x082), ALL, ARG_FP },
 660   { "divf",             FP(0x15,0x083), ALL, ARG_FP },
 661   { "cvtdg",            FP(0x15,0x09E), ALL, ARG_FPZ1 },
 662   { "addg",             FP(0x15,0x0A0), ALL, ARG_FP },
 663   { "negg",             FP(0x15,0x0A1), ALL, ARG_FPZ1 },        /* pseudo */
 664   { "subg",             FP(0x15,0x0A1), ALL, ARG_FP },
 665   { "mulg",             FP(0x15,0x0A2), ALL, ARG_FP },
 666   { "divg",             FP(0x15,0x0A3), ALL, ARG_FP },
 667   { "cmpgeq",           FP(0x15,0x0A5), ALL, ARG_FP },
 668   { "cmpglt",           FP(0x15,0x0A6), ALL, ARG_FP },
 669   { "cmpgle",           FP(0x15,0x0A7), ALL, ARG_FP },
 670   { "cvtgf",            FP(0x15,0x0AC), ALL, ARG_FPZ1 },
 671   { "cvtgd",            FP(0x15,0x0AD), ALL, ARG_FPZ1 },
 672   { "cvtgq",            FP(0x15,0x0AF), ALL, ARG_FPZ1 },
 673   { "cvtqf",            FP(0x15,0x0BC), ALL, ARG_FPZ1 },
 674   { "cvtqg",            FP(0x15,0x0BE), ALL, ARG_FPZ1 },
 675   { "addf/uc",          FP(0x15,0x100), ALL, ARG_FP },
 676   { "subf/uc",          FP(0x15,0x101), ALL, ARG_FP },
 677   { "mulf/uc",          FP(0x15,0x102), ALL, ARG_FP },
 678   { "divf/uc",          FP(0x15,0x103), ALL, ARG_FP },
 679   { "cvtdg/uc",         FP(0x15,0x11E), ALL, ARG_FPZ1 },
 680   { "addg/uc",          FP(0x15,0x120), ALL, ARG_FP },
 681   { "subg/uc",          FP(0x15,0x121), ALL, ARG_FP },
 682   { "mulg/uc",          FP(0x15,0x122), ALL, ARG_FP },
 683   { "divg/uc",          FP(0x15,0x123), ALL, ARG_FP },
 684   { "cvtgf/uc",         FP(0x15,0x12C), ALL, ARG_FPZ1 },
 685   { "cvtgd/uc",         FP(0x15,0x12D), ALL, ARG_FPZ1 },
 686   { "cvtgq/vc",         FP(0x15,0x12F), ALL, ARG_FPZ1 },
 687   { "addf/u",           FP(0x15,0x180), ALL, ARG_FP },
 688   { "subf/u",           FP(0x15,0x181), ALL, ARG_FP },
 689   { "mulf/u",           FP(0x15,0x182), ALL, ARG_FP },
 690   { "divf/u",           FP(0x15,0x183), ALL, ARG_FP },
 691   { "cvtdg/u",          FP(0x15,0x19E), ALL, ARG_FPZ1 },
 692   { "addg/u",           FP(0x15,0x1A0), ALL, ARG_FP },
 693   { "subg/u",           FP(0x15,0x1A1), ALL, ARG_FP },
 694   { "mulg/u",           FP(0x15,0x1A2), ALL, ARG_FP },
 695   { "divg/u",           FP(0x15,0x1A3), ALL, ARG_FP },
 696   { "cvtgf/u",          FP(0x15,0x1AC), ALL, ARG_FPZ1 },
 697   { "cvtgd/u",          FP(0x15,0x1AD), ALL, ARG_FPZ1 },
 698   { "cvtgq/v",          FP(0x15,0x1AF), ALL, ARG_FPZ1 },
 699   { "addf/sc",          FP(0x15,0x400), ALL, ARG_FP },
 700   { "subf/sc",          FP(0x15,0x401), ALL, ARG_FP },
 701   { "mulf/sc",          FP(0x15,0x402), ALL, ARG_FP },
 702   { "divf/sc",          FP(0x15,0x403), ALL, ARG_FP },
 703   { "cvtdg/sc",         FP(0x15,0x41E), ALL, ARG_FPZ1 },
 704   { "addg/sc",          FP(0x15,0x420), ALL, ARG_FP },
 705   { "subg/sc",          FP(0x15,0x421), ALL, ARG_FP },
 706   { "mulg/sc",          FP(0x15,0x422), ALL, ARG_FP },
 707   { "divg/sc",          FP(0x15,0x423), ALL, ARG_FP },
 708   { "cvtgf/sc",         FP(0x15,0x42C), ALL, ARG_FPZ1 },
 709   { "cvtgd/sc",         FP(0x15,0x42D), ALL, ARG_FPZ1 },
 710   { "cvtgq/sc",         FP(0x15,0x42F), ALL, ARG_FPZ1 },
 711   { "addf/s",           FP(0x15,0x480), ALL, ARG_FP },
 712   { "negf/s",           FP(0x15,0x481), ALL, ARG_FPZ1 },        /* pseudo */
 713   { "subf/s",           FP(0x15,0x481), ALL, ARG_FP },
 714   { "mulf/s",           FP(0x15,0x482), ALL, ARG_FP },
 715   { "divf/s",           FP(0x15,0x483), ALL, ARG_FP },
 716   { "cvtdg/s",          FP(0x15,0x49E), ALL, ARG_FPZ1 },
 717   { "addg/s",           FP(0x15,0x4A0), ALL, ARG_FP },
 718   { "negg/s",           FP(0x15,0x4A1), ALL, ARG_FPZ1 },        /* pseudo */
 719   { "subg/s",           FP(0x15,0x4A1), ALL, ARG_FP },
 720   { "mulg/s",           FP(0x15,0x4A2), ALL, ARG_FP },
 721   { "divg/s",           FP(0x15,0x4A3), ALL, ARG_FP },
 722   { "cmpgeq/s",         FP(0x15,0x4A5), ALL, ARG_FP },
 723   { "cmpglt/s",         FP(0x15,0x4A6), ALL, ARG_FP },
 724   { "cmpgle/s",         FP(0x15,0x4A7), ALL, ARG_FP },
 725   { "cvtgf/s",          FP(0x15,0x4AC), ALL, ARG_FPZ1 },
 726   { "cvtgd/s",          FP(0x15,0x4AD), ALL, ARG_FPZ1 },
 727   { "cvtgq/s",          FP(0x15,0x4AF), ALL, ARG_FPZ1 },
 728   { "addf/suc",         FP(0x15,0x500), ALL, ARG_FP },
 729   { "subf/suc",         FP(0x15,0x501), ALL, ARG_FP },
 730   { "mulf/suc",         FP(0x15,0x502), ALL, ARG_FP },
 731   { "divf/suc",         FP(0x15,0x503), ALL, ARG_FP },
 732   { "cvtdg/suc",        FP(0x15,0x51E), ALL, ARG_FPZ1 },
 733   { "addg/suc",         FP(0x15,0x520), ALL, ARG_FP },
 734   { "subg/suc",         FP(0x15,0x521), ALL, ARG_FP },
 735   { "mulg/suc",         FP(0x15,0x522), ALL, ARG_FP },
 736   { "divg/suc",         FP(0x15,0x523), ALL, ARG_FP },
 737   { "cvtgf/suc",        FP(0x15,0x52C), ALL, ARG_FPZ1 },
 738   { "cvtgd/suc",        FP(0x15,0x52D), ALL, ARG_FPZ1 },
 739   { "cvtgq/svc",        FP(0x15,0x52F), ALL, ARG_FPZ1 },
 740   { "addf/su",          FP(0x15,0x580), ALL, ARG_FP },
 741   { "subf/su",          FP(0x15,0x581), ALL, ARG_FP },
 742   { "mulf/su",          FP(0x15,0x582), ALL, ARG_FP },
 743   { "divf/su",          FP(0x15,0x583), ALL, ARG_FP },
 744   { "cvtdg/su",         FP(0x15,0x59E), ALL, ARG_FPZ1 },
 745   { "addg/su",          FP(0x15,0x5A0), ALL, ARG_FP },
 746   { "subg/su",          FP(0x15,0x5A1), ALL, ARG_FP },
 747   { "mulg/su",          FP(0x15,0x5A2), ALL, ARG_FP },
 748   { "divg/su",          FP(0x15,0x5A3), ALL, ARG_FP },
 749   { "cvtgf/su",         FP(0x15,0x5AC), ALL, ARG_FPZ1 },
 750   { "cvtgd/su",         FP(0x15,0x5AD), ALL, ARG_FPZ1 },
 751   { "cvtgq/sv",         FP(0x15,0x5AF), ALL, ARG_FPZ1 },
 752
 753   { "adds/c",           FP(0x16,0x000), ALL, ARG_FP },
 754   { "subs/c",           FP(0x16,0x001), ALL, ARG_FP },
 755   { "muls/c",           FP(0x16,0x002), ALL, ARG_FP },
 756   { "divs/c",           FP(0x16,0x003), ALL, ARG_FP },
 757   { "addt/c",           FP(0x16,0x020), ALL, ARG_FP },
 758   { "subt/c",           FP(0x16,0x021), ALL, ARG_FP },
 759   { "mult/c",           FP(0x16,0x022), ALL, ARG_FP },
 760   { "divt/c",           FP(0x16,0x023), ALL, ARG_FP },
 761   { "cvtts/c",          FP(0x16,0x02C), ALL, ARG_FPZ1 },
 762   { "cvttq/c",          FP(0x16,0x02F), ALL, ARG_FPZ1 },
 763   { "cvtqs/c",          FP(0x16,0x03C), ALL, ARG_FPZ1 },
 764   { "cvtqt/c",          FP(0x16,0x03E), ALL, ARG_FPZ1 },
 765   { "adds/m",           FP(0x16,0x040), ALL, ARG_FP },
 766   { "subs/m",           FP(0x16,0x041), ALL, ARG_FP },
 767   { "muls/m",           FP(0x16,0x042), ALL, ARG_FP },
 768   { "divs/m",           FP(0x16,0x043), ALL, ARG_FP },
 769   { "addt/m",           FP(0x16,0x060), ALL, ARG_FP },
 770   { "subt/m",           FP(0x16,0x061), ALL, ARG_FP },
 771   { "mult/m",           FP(0x16,0x062), ALL, ARG_FP },
 772   { "divt/m",           FP(0x16,0x063), ALL, ARG_FP },
 773   { "cvtts/m",          FP(0x16,0x06C), ALL, ARG_FPZ1 },
 774   { "cvttq/m",          FP(0x16,0x06F), ALL, ARG_FPZ1 },
 775   { "cvtqs/m",          FP(0x16,0x07C), ALL, ARG_FPZ1 },
 776   { "cvtqt/m",          FP(0x16,0x07E), ALL, ARG_FPZ1 },
 777   { "adds",             FP(0x16,0x080), ALL, ARG_FP },
 778   { "negs",             FP(0x16,0x081), ALL, ARG_FPZ1 },        /* pseudo */
 779   { "subs",             FP(0x16,0x081), ALL, ARG_FP },
 780   { "muls",             FP(0x16,0x082), ALL, ARG_FP },
 781   { "divs",             FP(0x16,0x083), ALL, ARG_FP },
 782   { "addt",             FP(0x16,0x0A0), ALL, ARG_FP },
 783   { "negt",             FP(0x16,0x0A1), ALL, ARG_FPZ1 },        /* pseudo */
 784   { "subt",             FP(0x16,0x0A1), ALL, ARG_FP },
 785   { "mult",             FP(0x16,0x0A2), ALL, ARG_FP },
 786   { "divt",             FP(0x16,0x0A3), ALL, ARG_FP },
 787   { "cmptun",           FP(0x16,0x0A4), ALL, ARG_FP },
 788   { "cmpteq",           FP(0x16,0x0A5), ALL, ARG_FP },
 789   { "cmptlt",           FP(0x16,0x0A6), ALL, ARG_FP },
 790   { "cmptle",           FP(0x16,0x0A7), ALL, ARG_FP },
 791   { "cvtts",            FP(0x16,0x0AC), ALL, ARG_FPZ1 },
 792   { "cvttq",            FP(0x16,0x0AF), ALL, ARG_FPZ1 },
 793   { "cvtqs",            FP(0x16,0x0BC), ALL, ARG_FPZ1 },
 794   { "cvtqt",            FP(0x16,0x0BE), ALL, ARG_FPZ1 },
 795   { "adds/d",           FP(0x16,0x0C0), ALL, ARG_FP },
 796   { "subs/d",           FP(0x16,0x0C1), ALL, ARG_FP },
 797   { "muls/d",           FP(0x16,0x0C2), ALL, ARG_FP },
 798   { "divs/d",           FP(0x16,0x0C3), ALL, ARG_FP },
 799   { "addt/d",           FP(0x16,0x0E0), ALL, ARG_FP },
 800   { "subt/d",           FP(0x16,0x0E1), ALL, ARG_FP },
 801   { "mult/d",           FP(0x16,0x0E2), ALL, ARG_FP },
 802   { "divt/d",           FP(0x16,0x0E3), ALL, ARG_FP },
 803   { "cvtts/d",          FP(0x16,0x0EC), ALL, ARG_FPZ1 },
 804   { "cvttq/d",          FP(0x16,0x0EF), ALL, ARG_FPZ1 },
 805   { "cvtqs/d",          FP(0x16,0x0FC), ALL, ARG_FPZ1 },
 806   { "cvtqt/d",          FP(0x16,0x0FE), ALL, ARG_FPZ1 },
 807   { "adds/uc",          FP(0x16,0x100), ALL, ARG_FP },
 808   { "subs/uc",          FP(0x16,0x101), ALL, ARG_FP },
 809   { "muls/uc",          FP(0x16,0x102), ALL, ARG_FP },
 810   { "divs/uc",          FP(0x16,0x103), ALL, ARG_FP },
 811   { "addt/uc",          FP(0x16,0x120), ALL, ARG_FP },
 812   { "subt/uc",          FP(0x16,0x121), ALL, ARG_FP },
 813   { "mult/uc",          FP(0x16,0x122), ALL, ARG_FP },
 814   { "divt/uc",          FP(0x16,0x123), ALL, ARG_FP },
 815   { "cvtts/uc",         FP(0x16,0x12C), ALL, ARG_FPZ1 },
 816   { "cvttq/vc",         FP(0x16,0x12F), ALL, ARG_FPZ1 },
 817   { "adds/um",          FP(0x16,0x140), ALL, ARG_FP },
 818   { "subs/um",          FP(0x16,0x141), ALL, ARG_FP },
 819   { "muls/um",          FP(0x16,0x142), ALL, ARG_FP },
 820   { "divs/um",          FP(0x16,0x143), ALL, ARG_FP },
 821   { "addt/um",          FP(0x16,0x160), ALL, ARG_FP },
 822   { "subt/um",          FP(0x16,0x161), ALL, ARG_FP },
 823   { "mult/um",          FP(0x16,0x162), ALL, ARG_FP },
 824   { "divt/um",          FP(0x16,0x163), ALL, ARG_FP },
 825   { "cvtts/um",         FP(0x16,0x16C), ALL, ARG_FPZ1 },
 826   { "cvttq/um",         FP(0x16,0x16F), ALL, ARG_FPZ1 },
 827   { "cvtqs/um",         FP(0x16,0x17C), ALL, ARG_FPZ1 },
 828   { "adds/u",           FP(0x16,0x180), ALL, ARG_FP },
 829   { "subs/u",           FP(0x16,0x181), ALL, ARG_FP },
 830   { "muls/u",           FP(0x16,0x182), ALL, ARG_FP },
 831   { "divs/u",           FP(0x16,0x183), ALL, ARG_FP },
 832   { "addt/u",           FP(0x16,0x1A0), ALL, ARG_FP },
 833   { "subt/u",           FP(0x16,0x1A1), ALL, ARG_FP },
 834   { "mult/u",           FP(0x16,0x1A2), ALL, ARG_FP },
 835   { "divt/u",           FP(0x16,0x1A3), ALL, ARG_FP },
 836   { "cvtts/u",          FP(0x16,0x1AC), ALL, ARG_FPZ1 },
 837   { "cvttq/v",          FP(0x16,0x1AF), ALL, ARG_FPZ1 },
 838   { "adds/ud",          FP(0x16,0x1C0), ALL, ARG_FP },
 839   { "subs/ud",          FP(0x16,0x1C1), ALL, ARG_FP },
 840   { "muls/ud",          FP(0x16,0x1C2), ALL, ARG_FP },
 841   { "divs/ud",          FP(0x16,0x1C3), ALL, ARG_FP },
 842   { "addt/ud",          FP(0x16,0x1E0), ALL, ARG_FP },
 843   { "subt/ud",          FP(0x16,0x1E1), ALL, ARG_FP },
 844   { "mult/ud",          FP(0x16,0x1E2), ALL, ARG_FP },
 845   { "divt/ud",          FP(0x16,0x1E3), ALL, ARG_FP },
 846   { "cvtts/ud",         FP(0x16,0x1EC), ALL, ARG_FPZ1 },
 847   { "cvttq/ud",         FP(0x16,0x1EF), ALL, ARG_FPZ1 },
 848   { "cvtst",            FP(0x16,0x2AC), ALL, ARG_FPZ1 },
 849   { "adds/suc",         FP(0x16,0x500), ALL, ARG_FP },
 850   { "subs/suc",         FP(0x16,0x501), ALL, ARG_FP },
 851   { "muls/suc",         FP(0x16,0x502), ALL, ARG_FP },
 852   { "divs/suc",         FP(0x16,0x503), ALL, ARG_FP },
 853   { "addt/suc",         FP(0x16,0x520), ALL, ARG_FP },
 854   { "subt/suc",         FP(0x16,0x521), ALL, ARG_FP },
 855   { "mult/suc",         FP(0x16,0x522), ALL, ARG_FP },
 856   { "divt/suc",         FP(0x16,0x523), ALL, ARG_FP },
 857   { "cvtts/suc",        FP(0x16,0x52C), ALL, ARG_FPZ1 },
 858   { "cvttq/svc",        FP(0x16,0x52F), ALL, ARG_FPZ1 },
 859   { "adds/sum",         FP(0x16,0x540), ALL, ARG_FP },
 860   { "subs/sum",         FP(0x16,0x541), ALL, ARG_FP },
 861   { "muls/sum",         FP(0x16,0x542), ALL, ARG_FP },
 862   { "divs/sum",         FP(0x16,0x543), ALL, ARG_FP },
 863   { "addt/sum",         FP(0x16,0x560), ALL, ARG_FP },
 864   { "subt/sum",         FP(0x16,0x561), ALL, ARG_FP },
 865   { "mult/sum",         FP(0x16,0x562), ALL, ARG_FP },
 866   { "divt/sum",         FP(0x16,0x563), ALL, ARG_FP },
 867   { "cvtts/sum",        FP(0x16,0x56C), ALL, ARG_FPZ1 },
 868   { "cvttq/sum",        FP(0x16,0x56F), ALL, ARG_FPZ1 },
 869   { "cvtqs/sum",        FP(0x16,0x57C), ALL, ARG_FPZ1 },
 870   { "adds/su",          FP(0x16,0x580), ALL, ARG_FP },
 871   { "negs/su",          FP(0x16,0x581), ALL, ARG_FPZ1 },        /* pseudo */
 872   { "subs/su",          FP(0x16,0x581), ALL, ARG_FP },
 873   { "muls/su",          FP(0x16,0x582), ALL, ARG_FP },
 874   { "divs/su",          FP(0x16,0x583), ALL, ARG_FP },
 875   { "addt/su",          FP(0x16,0x5A0), ALL, ARG_FP },
 876   { "negt/su",          FP(0x16,0x5A1), ALL, ARG_FPZ1 },        /* pseudo */
 877   { "subt/su",          FP(0x16,0x5A1), ALL, ARG_FP },
 878   { "mult/su",          FP(0x16,0x5A2), ALL, ARG_FP },
 879   { "divt/su",          FP(0x16,0x5A3), ALL, ARG_FP },
 880   { "cmptun/su",        FP(0x16,0x5A4), ALL, ARG_FP },
 881   { "cmpteq/su",        FP(0x16,0x5A5), ALL, ARG_FP },
 882   { "cmptlt/su",        FP(0x16,0x5A6), ALL, ARG_FP },
 883   { "cmptle/su",        FP(0x16,0x5A7), ALL, ARG_FP },
 884   { "cvtts/su",         FP(0x16,0x5AC), ALL, ARG_FPZ1 },
 885   { "cvttq/sv",         FP(0x16,0x5AF), ALL, ARG_FPZ1 },
 886   { "adds/sud",         FP(0x16,0x5C0), ALL, ARG_FP },
 887   { "subs/sud",         FP(0x16,0x5C1), ALL, ARG_FP },
 888   { "muls/sud",         FP(0x16,0x5C2), ALL, ARG_FP },
 889   { "divs/sud",         FP(0x16,0x5C3), ALL, ARG_FP },
 890   { "addt/sud",         FP(0x16,0x5E0), ALL, ARG_FP },
 891   { "subt/sud",         FP(0x16,0x5E1), ALL, ARG_FP },
 892   { "mult/sud",         FP(0x16,0x5E2), ALL, ARG_FP },
 893   { "divt/sud",         FP(0x16,0x5E3), ALL, ARG_FP },
 894   { "cvtts/sud",        FP(0x16,0x5EC), ALL, ARG_FPZ1 },
 895   { "cvttq/sud",        FP(0x16,0x5EF), ALL, ARG_FPZ1 },
 896   { "cvtst/s",          FP(0x16,0x6AC), ALL, ARG_FPZ1 },
 897   { "adds/suic",        FP(0x16,0x700), ALL, ARG_FP },
 898   { "subs/suic",        FP(0x16,0x701), ALL, ARG_FP },
 899   { "muls/suic",        FP(0x16,0x702), ALL, ARG_FP },
 900   { "divs/suic",        FP(0x16,0x703), ALL, ARG_FP },
 901   { "addt/suic",        FP(0x16,0x720), ALL, ARG_FP },
 902   { "subt/suic",        FP(0x16,0x721), ALL, ARG_FP },
 903   { "mult/suic",        FP(0x16,0x722), ALL, ARG_FP },
 904   { "divt/suic",        FP(0x16,0x723), ALL, ARG_FP },
 905   { "cvtts/suic",       FP(0x16,0x72C), ALL, ARG_FPZ1 },
 906   { "cvttq/svic",       FP(0x16,0x72F), ALL, ARG_FPZ1 },
 907   { "cvtqs/suic",       FP(0x16,0x73C), ALL, ARG_FPZ1 },
 908   { "cvtqt/suic",       FP(0x16,0x73E), ALL, ARG_FPZ1 },
 909   { "adds/suim",        FP(0x16,0x740), ALL, ARG_FP },
 910   { "subs/suim",        FP(0x16,0x741), ALL, ARG_FP },
 911   { "muls/suim",        FP(0x16,0x742), ALL, ARG_FP },
 912   { "divs/suim",        FP(0x16,0x743), ALL, ARG_FP },
 913   { "addt/suim",        FP(0x16,0x760), ALL, ARG_FP },
 914   { "subt/suim",        FP(0x16,0x761), ALL, ARG_FP },
 915   { "mult/suim",        FP(0x16,0x762), ALL, ARG_FP },
 916   { "divt/suim",        FP(0x16,0x763), ALL, ARG_FP },
 917   { "cvtts/suim",       FP(0x16,0x76C), ALL, ARG_FPZ1 },
 918   { "cvttq/suim",       FP(0x16,0x76F), ALL, ARG_FPZ1 },
 919   { "cvtqs/suim",       FP(0x16,0x77C), ALL, ARG_FPZ1 },
 920   { "cvtqt/suim",       FP(0x16,0x77E), ALL, ARG_FPZ1 },
 921   { "adds/sui",         FP(0x16,0x780), ALL, ARG_FP },
 922   { "negs/sui",         FP(0x16,0x781), ALL, ARG_FPZ1 },        /* pseudo */
 923   { "subs/sui",         FP(0x16,0x781), ALL, ARG_FP },
 924   { "muls/sui",         FP(0x16,0x782), ALL, ARG_FP },
 925   { "divs/sui",         FP(0x16,0x783), ALL, ARG_FP },
 926   { "addt/sui",         FP(0x16,0x7A0), ALL, ARG_FP },
 927   { "negt/sui",         FP(0x16,0x7A1), ALL, ARG_FPZ1 },        /* pseudo */
 928   { "subt/sui",         FP(0x16,0x7A1), ALL, ARG_FP },
 929   { "mult/sui",         FP(0x16,0x7A2), ALL, ARG_FP },
 930   { "divt/sui",         FP(0x16,0x7A3), ALL, ARG_FP },
 931   { "cvtts/sui",        FP(0x16,0x7AC), ALL, ARG_FPZ1 },
 932   { "cvttq/svi",        FP(0x16,0x7AF), ALL, ARG_FPZ1 },
 933   { "cvtqs/sui",        FP(0x16,0x7BC), ALL, ARG_FPZ1 },
 934   { "cvtqt/sui",        FP(0x16,0x7BE), ALL, ARG_FPZ1 },
 935   { "adds/suid",        FP(0x16,0x7C0), ALL, ARG_FP },
 936   { "subs/suid",        FP(0x16,0x7C1), ALL, ARG_FP },
 937   { "muls/suid",        FP(0x16,0x7C2), ALL, ARG_FP },
 938   { "divs/suid",        FP(0x16,0x7C3), ALL, ARG_FP },
 939   { "addt/suid",        FP(0x16,0x7E0), ALL, ARG_FP },
 940   { "subt/suid",        FP(0x16,0x7E1), ALL, ARG_FP },
 941   { "mult/suid",        FP(0x16,0x7E2), ALL, ARG_FP },
 942   { "divt/suid",        FP(0x16,0x7E3), ALL, ARG_FP },
 943   { "cvtts/suid",       FP(0x16,0x7EC), ALL, ARG_FPZ1 },
 944   { "cvttq/suid",       FP(0x16,0x7EF), ALL, ARG_FPZ1 },
 945   { "cvtqs/suid",       FP(0x16,0x7FC), ALL, ARG_FPZ1 },
 946   { "cvtqt/suid",       FP(0x16,0x7FE), ALL, ARG_FPZ1 },
 947
 948   { "cvtlq",            FP(0x17,0x010), ALL, ARG_FPZ1 },
 949   { "fnop",             FP(0x17,0x020), ALL, { ZA, ZB, ZC } },  /* pseudo */
 950   { "fclr",             FP(0x17,0x020), ALL, { ZA, ZB, FC } },  /* pseudo */
 951   { "fabs",             FP(0x17,0x020), ALL, ARG_FPZ1 },        /* pseudo */
 952   { "fmov",             FP(0x17,0x020), ALL, { FA, RBA, FC } }, /* pseudo */
 953   { "cpys",             FP(0x17,0x020), ALL, ARG_FP },
 954   { "fneg",             FP(0x17,0x021), ALL, { FA, RBA, FC } }, /* pseudo */
 955   { "cpysn",            FP(0x17,0x021), ALL, ARG_FP },
 956   { "cpyse",            FP(0x17,0x022), ALL, ARG_FP },
 957   { "mt_fpcr",          FP(0x17,0x024), ALL, { FA, RBA, RCA } },
 958   { "mf_fpcr",          FP(0x17,0x025), ALL, { FA, RBA, RCA } },
 959   { "fcmoveq",          FP(0x17,0x02A), ALL, ARG_FP },
 960   { "fcmovne",          FP(0x17,0x02B), ALL, ARG_FP },
 961   { "fcmovlt",          FP(0x17,0x02C), ALL, ARG_FP },
 962   { "fcmovge",          FP(0x17,0x02D), ALL, ARG_FP },
 963   { "fcmovle",          FP(0x17,0x02E), ALL, ARG_FP },
 964   { "fcmovgt",          FP(0x17,0x02F), ALL, ARG_FP },
 965   { "cvtql",            FP(0x17,0x030), ALL, ARG_FPZ1 },
 966   { "cvtql/v",          FP(0x17,0x130), ALL, ARG_FPZ1 },
 967   { "cvtql/sv",         FP(0x17,0x530), ALL, ARG_FPZ1 },
 968
 969   { "trapb",            MFC(0x18,0x0000), ALL, ARG_NONE },
 970   { "draint",           MFC(0x18,0x0000), ALL, ARG_NONE },      /* alias */
 971   { "excb",             MFC(0x18,0x0400), ALL, ARG_NONE },
 972   { "mb",               MFC(0x18,0x4000), ALL, ARG_NONE },
 973   { "wmb",              MFC(0x18,0x4400), ALL, ARG_NONE },
 974   { "fetch",            MFC(0x18,0x8000), ALL, { MDISP, RB } },
 975   { "fetch_m",          MFC(0x18,0xA000), ALL, { MDISP, RB } },
 976   { "rpcc",             MFC(0x18,0xC000), ALL, { RA } },
 977   { "rc",               MFC(0x18,0xE000), ALL, { RA } },
 978   { "rs",               MFC(0x18,0xF000), ALL, { RA } },
 979
 980   { "hw_mfpr",          OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
 981   { "hw_mfpr",          OP(0x19), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } },
 982   { "hw_mfpr/i",        OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
 983   { "hw_mfpr/a",        OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
 984   { "hw_mfpr/ai",       OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
 985   { "hw_mfpr/p",        OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
 986   { "hw_mfpr/pi",       OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
 987   { "hw_mfpr/pa",       OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
 988   { "hw_mfpr/pai",      OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
 989   { "pal19",            PCD(0x19), ALL, ARG_PCD },
 990
 991   { "jmp",              MBR(0x1A,0), ALL, { RA, CPRB, JMPHINT } },
 992   { "jsr",              MBR(0x1A,1), ALL, { RA, CPRB, JMPHINT } },
 993   { "ret",              MBR(0x1A,2), ALL, { RA, CPRB, RETHINT } },
 994   { "jcr",              MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } }, /* alias */
 995   { "jsr_coroutine",    MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } },
 996
 997   { "hw_ldl",           EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
 998   { "hw_ldl",           EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM },
 999   { "hw_ldl/a",         EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1000   { "hw_ldl/a",         EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM },
1001   { "hw_ldl/al",        EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
1002   { "hw_ldl/ar",        EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1003   { "hw_ldl/av",        EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM },
1004   { "hw_ldl/avl",       EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
1005   { "hw_ldl/aw",        EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM },
1006   { "hw_ldl/awl",       EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
1007   { "hw_ldl/awv",       EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM },
1008   { "hw_ldl/awvl",      EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
1009   { "hw_ldl/l",         EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
1010   { "hw_ldl/p",         EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1011   { "hw_ldl/p",         EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM },
1012   { "hw_ldl/pa",        EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1013   { "hw_ldl/pa",        EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM },
1014   { "hw_ldl/pal",       EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
1015   { "hw_ldl/par",       EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1016   { "hw_ldl/pav",       EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM },
1017   { "hw_ldl/pavl",      EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
1018   { "hw_ldl/paw",       EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM },
1019   { "hw_ldl/pawl",      EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
1020   { "hw_ldl/pawv",      EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM },
1021   { "hw_ldl/pawvl",     EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
1022   { "hw_ldl/pl",        EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
1023   { "hw_ldl/pr",        EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1024   { "hw_ldl/pv",        EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM },
1025   { "hw_ldl/pvl",       EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
1026   { "hw_ldl/pw",        EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM },
1027   { "hw_ldl/pwl",       EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
1028   { "hw_ldl/pwv",       EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM },
1029   { "hw_ldl/pwvl",      EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
1030   { "hw_ldl/r",         EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1031   { "hw_ldl/v",         EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM },
1032   { "hw_ldl/vl",        EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
1033   { "hw_ldl/w",         EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM },
1034   { "hw_ldl/wl",        EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
1035   { "hw_ldl/wv",        EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM },
1036   { "hw_ldl/wvl",       EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
1037   { "hw_ldl_l",         EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
1038   { "hw_ldl_l/a",       EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
1039   { "hw_ldl_l/av",      EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
1040   { "hw_ldl_l/aw",      EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
1041   { "hw_ldl_l/awv",     EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
1042   { "hw_ldl_l/p",       EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
1043   { "hw_ldl_l/pa",      EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
1044   { "hw_ldl_l/pav",     EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
1045   { "hw_ldl_l/paw",     EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
1046   { "hw_ldl_l/pawv",    EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
1047   { "hw_ldl_l/pv",      EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
1048   { "hw_ldl_l/pw",      EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
1049   { "hw_ldl_l/pwv",     EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
1050   { "hw_ldl_l/v",       EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
1051   { "hw_ldl_l/w",       EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
1052   { "hw_ldl_l/wv",      EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
1053   { "hw_ldq",           EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1054   { "hw_ldq",           EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM },
1055   { "hw_ldq/a",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1056   { "hw_ldq/a",         EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM },
1057   { "hw_ldq/al",        EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
1058   { "hw_ldq/ar",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1059   { "hw_ldq/av",        EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM },
1060   { "hw_ldq/avl",       EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
1061   { "hw_ldq/aw",        EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM },
1062   { "hw_ldq/awl",       EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
1063   { "hw_ldq/awv",       EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM },
1064   { "hw_ldq/awvl",      EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
1065   { "hw_ldq/l",         EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
1066   { "hw_ldq/p",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1067   { "hw_ldq/p",         EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM },
1068   { "hw_ldq/pa",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1069   { "hw_ldq/pa",        EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM },
1070   { "hw_ldq/pal",       EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
1071   { "hw_ldq/par",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1072   { "hw_ldq/pav",       EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM },
1073   { "hw_ldq/pavl",      EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
1074   { "hw_ldq/paw",       EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM },
1075   { "hw_ldq/pawl",      EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
1076   { "hw_ldq/pawv",      EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM },
1077   { "hw_ldq/pawvl",     EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
1078   { "hw_ldq/pl",        EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
1079   { "hw_ldq/pr",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1080   { "hw_ldq/pv",        EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM },
1081   { "hw_ldq/pvl",       EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
1082   { "hw_ldq/pw",        EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM },
1083   { "hw_ldq/pwl",       EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
1084   { "hw_ldq/pwv",       EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM },
1085   { "hw_ldq/pwvl",      EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
1086   { "hw_ldq/r",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1087   { "hw_ldq/v",         EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM },
1088   { "hw_ldq/vl",        EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
1089   { "hw_ldq/w",         EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM },
1090   { "hw_ldq/wl",        EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
1091   { "hw_ldq/wv",        EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM },
1092   { "hw_ldq/wvl",       EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
1093   { "hw_ldq_l",         EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
1094   { "hw_ldq_l/a",       EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
1095   { "hw_ldq_l/av",      EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
1096   { "hw_ldq_l/aw",      EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
1097   { "hw_ldq_l/awv",     EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
1098   { "hw_ldq_l/p",       EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
1099   { "hw_ldq_l/pa",      EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
1100   { "hw_ldq_l/pav",     EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
1101   { "hw_ldq_l/paw",     EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
1102   { "hw_ldq_l/pawv",    EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
1103   { "hw_ldq_l/pv",      EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
1104   { "hw_ldq_l/pw",      EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
1105   { "hw_ldq_l/pwv",     EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
1106   { "hw_ldq_l/v",       EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
1107   { "hw_ldq_l/w",       EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
1108   { "hw_ldq_l/wv",      EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
1109   { "hw_ld",            EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1110   { "hw_ld",            EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM },
1111   { "hw_ld/a",          EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1112   { "hw_ld/a",          EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM },
1113   { "hw_ld/al",         EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
1114   { "hw_ld/aq",         EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1115   { "hw_ld/aq",         EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM },
1116   { "hw_ld/aql",        EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
1117   { "hw_ld/aqv",        EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM },
1118   { "hw_ld/aqvl",       EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
1119   { "hw_ld/ar",         EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1120   { "hw_ld/arq",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1121   { "hw_ld/av",         EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM },
1122   { "hw_ld/avl",        EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
1123   { "hw_ld/aw",         EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM },
1124   { "hw_ld/awl",        EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
1125   { "hw_ld/awq",        EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM },
1126   { "hw_ld/awql",       EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
1127   { "hw_ld/awqv",       EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM },
1128   { "hw_ld/awqvl",      EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
1129   { "hw_ld/awv",        EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM },
1130   { "hw_ld/awvl",       EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
1131   { "hw_ld/l",          EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
1132   { "hw_ld/p",          EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1133   { "hw_ld/p",          EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM },
1134   { "hw_ld/pa",         EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1135   { "hw_ld/pa",         EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM },
1136   { "hw_ld/pal",        EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
1137   { "hw_ld/paq",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1138   { "hw_ld/paq",        EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM },
1139   { "hw_ld/paql",       EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
1140   { "hw_ld/paqv",       EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM },
1141   { "hw_ld/paqvl",      EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
1142   { "hw_ld/par",        EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1143   { "hw_ld/parq",       EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1144   { "hw_ld/pav",        EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM },
1145   { "hw_ld/pavl",       EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
1146   { "hw_ld/paw",        EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM },
1147   { "hw_ld/pawl",       EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
1148   { "hw_ld/pawq",       EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM },
1149   { "hw_ld/pawql",      EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
1150   { "hw_ld/pawqv",      EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM },
1151   { "hw_ld/pawqvl",     EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
1152   { "hw_ld/pawv",       EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM },
1153   { "hw_ld/pawvl",      EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
1154   { "hw_ld/pl",         EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
1155   { "hw_ld/pq",         EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1156   { "hw_ld/pq",         EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM },
1157   { "hw_ld/pql",        EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
1158   { "hw_ld/pqv",        EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM },
1159   { "hw_ld/pqvl",       EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
1160   { "hw_ld/pr",         EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1161   { "hw_ld/prq",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1162   { "hw_ld/pv",         EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM },
1163   { "hw_ld/pvl",        EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
1164   { "hw_ld/pw",         EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM },
1165   { "hw_ld/pwl",        EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
1166   { "hw_ld/pwq",        EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM },
1167   { "hw_ld/pwql",       EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
1168   { "hw_ld/pwqv",       EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM },
1169   { "hw_ld/pwqvl",      EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
1170   { "hw_ld/pwv",        EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM },
1171   { "hw_ld/pwvl",       EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
1172   { "hw_ld/q",          EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1173   { "hw_ld/q",          EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM },
1174   { "hw_ld/ql",         EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
1175   { "hw_ld/qv",         EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM },
1176   { "hw_ld/qvl",        EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
1177   { "hw_ld/r",          EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1178   { "hw_ld/rq",         EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1179   { "hw_ld/v",          EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM },
1180   { "hw_ld/vl",         EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
1181   { "hw_ld/w",          EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM },
1182   { "hw_ld/wl",         EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
1183   { "hw_ld/wq",         EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM },
1184   { "hw_ld/wql",        EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
1185   { "hw_ld/wqv",        EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM },
1186   { "hw_ld/wqvl",       EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
1187   { "hw_ld/wv",         EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM },
1188   { "hw_ld/wvl",        EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
1189   { "pal1b",            PCD(0x1B), ALL, ARG_PCD },
1190
1191   { "hw_mtpr",          OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1192   { "hw_mtpr",          OP(0x1D), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } },
1193   { "hw_mtpr/i",        OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1194   { "hw_mtpr/a",        OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1195   { "hw_mtpr/ai",       OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1196   { "hw_mtpr/p",        OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1197   { "hw_mtpr/pi",       OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1198   { "hw_mtpr/pa",       OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1199   { "hw_mtpr/pai",      OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1200   { "pal1d",            PCD(0x1D), ALL, ARG_PCD },
1201
1202   { "hw_rei",           SPCD(0x1E,0x3FF8000), EV4|EV5x, ARG_NONE },
1203   { "hw_rei_stall",     SPCD(0x1E,0x3FFC000), EV5x, ARG_NONE },
1204   { "pal1e",            PCD(0x1E), ALL, ARG_PCD },
1205
1206   { "hw_stl",           EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1207   { "hw_stl",           EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM },
1208   { "hw_stl/a",         EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1209   { "hw_stl/a",         EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM },
1210   { "hw_stl/ac",        EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
1211   { "hw_stl/ar",        EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1212   { "hw_stl/av",        EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM },
1213   { "hw_stl/avc",       EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
1214   { "hw_stl/c",         EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
1215   { "hw_stl/p",         EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1216   { "hw_stl/p",         EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM },
1217   { "hw_stl/pa",        EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1218   { "hw_stl/pa",        EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM },
1219   { "hw_stl/pac",       EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
1220   { "hw_stl/pav",       EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM },
1221   { "hw_stl/pavc",      EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
1222   { "hw_stl/pc",        EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
1223   { "hw_stl/pr",        EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1224   { "hw_stl/pv",        EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM },
1225   { "hw_stl/pvc",       EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
1226   { "hw_stl/r",         EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1227   { "hw_stl/v",         EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM },
1228   { "hw_stl/vc",        EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
1229   { "hw_stl_c",         EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
1230   { "hw_stl_c/a",       EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
1231   { "hw_stl_c/av",      EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
1232   { "hw_stl_c/p",       EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
1233   { "hw_stl_c/pa",      EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
1234   { "hw_stl_c/pav",     EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
1235   { "hw_stl_c/pv",      EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
1236   { "hw_stl_c/v",       EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
1237   { "hw_stq",           EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1238   { "hw_stq",           EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM },
1239   { "hw_stq/a",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1240   { "hw_stq/a",         EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM },
1241   { "hw_stq/ac",        EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
1242   { "hw_stq/ar",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1243   { "hw_stq/av",        EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM },
1244   { "hw_stq/avc",       EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
1245   { "hw_stq/c",         EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
1246   { "hw_stq/p",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1247   { "hw_stq/p",         EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM },
1248   { "hw_stq/pa",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1249   { "hw_stq/pa",        EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM },
1250   { "hw_stq/pac",       EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
1251   { "hw_stq/par",       EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1252   { "hw_stq/par",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1253   { "hw_stq/pav",       EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM },
1254   { "hw_stq/pavc",      EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
1255   { "hw_stq/pc",        EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
1256   { "hw_stq/pr",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1257   { "hw_stq/pv",        EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM },
1258   { "hw_stq/pvc",       EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
1259   { "hw_stq/r",         EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1260   { "hw_stq/v",         EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM },
1261   { "hw_stq/vc",        EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
1262   { "hw_stq_c",         EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
1263   { "hw_stq_c/a",       EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
1264   { "hw_stq_c/av",      EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
1265   { "hw_stq_c/p",       EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
1266   { "hw_stq_c/pa",      EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
1267   { "hw_stq_c/pav",     EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
1268   { "hw_stq_c/pv",      EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
1269   { "hw_stq_c/v",       EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
1270   { "hw_st",            EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1271   { "hw_st",            EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM },
1272   { "hw_st/a",          EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1273   { "hw_st/a",          EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM },
1274   { "hw_st/ac",         EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
1275   { "hw_st/aq",         EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1276   { "hw_st/aq",         EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM },
1277   { "hw_st/aqc",        EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
1278   { "hw_st/aqv",        EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM },
1279   { "hw_st/aqvc",       EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
1280   { "hw_st/ar",         EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1281   { "hw_st/arq",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1282   { "hw_st/av",         EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM },
1283   { "hw_st/avc",        EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
1284   { "hw_st/c",          EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
1285   { "hw_st/p",          EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1286   { "hw_st/p",          EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM },
1287   { "hw_st/pa",         EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1288   { "hw_st/pa",         EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM },
1289   { "hw_st/pac",        EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
1290   { "hw_st/paq",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1291   { "hw_st/paq",        EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM },
1292   { "hw_st/paqc",       EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
1293   { "hw_st/paqv",       EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM },
1294   { "hw_st/paqvc",      EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
1295   { "hw_st/par",        EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1296   { "hw_st/parq",       EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1297   { "hw_st/pav",        EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM },
1298   { "hw_st/pavc",       EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
1299   { "hw_st/pc",         EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
1300   { "hw_st/pq",         EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1301   { "hw_st/pq",         EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM },
1302   { "hw_st/pqc",        EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
1303   { "hw_st/pqv",        EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM },
1304   { "hw_st/pqvc",       EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
1305   { "hw_st/pr",         EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1306   { "hw_st/prq",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1307   { "hw_st/pv",         EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM },
1308   { "hw_st/pvc",        EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
1309   { "hw_st/q",          EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1310   { "hw_st/q",          EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM },
1311   { "hw_st/qc",         EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
1312   { "hw_st/qv",         EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM },
1313   { "hw_st/qvc",        EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
1314   { "hw_st/r",          EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1315   { "hw_st/v",          EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM },
1316   { "hw_st/vc",         EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
1317   { "pal1f",            PCD(0x1F), ALL, ARG_PCD },
1318
1319   { "ldf",              MEM(0x20), ALL, ARG_FMEM },
1320   { "ldg",              MEM(0x21), ALL, ARG_FMEM },
1321   { "lds",              MEM(0x22), ALL, ARG_FMEM },
1322   { "ldt",              MEM(0x23), ALL, ARG_FMEM },
1323   { "stf",              MEM(0x24), ALL, ARG_FMEM },
1324   { "stg",              MEM(0x25), ALL, ARG_FMEM },
1325   { "sts",              MEM(0x26), ALL, ARG_FMEM },
1326   { "stt",              MEM(0x27), ALL, ARG_FMEM },
1327
1328   { "ldl",              MEM(0x28), ALL, ARG_MEM },
1329   { "ldq",              MEM(0x29), ALL, ARG_MEM },
1330   { "ldl_l",            MEM(0x2A), ALL, ARG_MEM },
1331   { "ldq_l",            MEM(0x2B), ALL, ARG_MEM },
1332   { "stl",              MEM(0x2C), ALL, ARG_MEM },
1333   { "stq",              MEM(0x2D), ALL, ARG_MEM },
1334   { "stl_c",            MEM(0x2E), ALL, ARG_MEM },
1335   { "stq_c",            MEM(0x2F), ALL, ARG_MEM },
1336
1337   { "br",               BRA(0x30), ALL, { ZA, BDISP } },        /* pseudo */
1338   { "br",               BRA(0x30), ALL, ARG_BRA },
1339   { "fbeq",             BRA(0x31), ALL, ARG_FBRA },
1340   { "fblt",             BRA(0x32), ALL, ARG_FBRA },
1341   { "fble",             BRA(0x33), ALL, ARG_FBRA },
1342   { "bsr",              BRA(0x34), ALL, ARG_BRA },
1343   { "fbne",             BRA(0x35), ALL, ARG_FBRA },
1344   { "fbge",             BRA(0x36), ALL, ARG_FBRA },
1345   { "fbgt",             BRA(0x37), ALL, ARG_FBRA },
1346   { "blbc",             BRA(0x38), ALL, ARG_BRA },
1347   { "beq",              BRA(0x39), ALL, ARG_BRA },
1348   { "blt",              BRA(0x3A), ALL, ARG_BRA },
1349   { "ble",              BRA(0x3B), ALL, ARG_BRA },
1350   { "blbs",             BRA(0x3C), ALL, ARG_BRA },
1351   { "bne",              BRA(0x3D), ALL, ARG_BRA },
1352   { "bge",              BRA(0x3E), ALL, ARG_BRA },
1353   { "bgt",              BRA(0x3F), ALL, ARG_BRA },
1354 };
1355
1356 const int alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);