1 /* Instruction printing code for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modification by James G. Smith (jsmith@cygnus.co.uk)
8 This file is part of libopcodes.
10 This library is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
28 #include "opcode/arm.h"
30 #include "safe-ctype.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
37 #include "elf/internal.h"
40 /* FIXME: Belongs in global header. */
42 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
46 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
49 /* Cached mapping symbol state. */
57 struct arm_private_data
59 /* The features to use when disassembling optional instructions. */
60 arm_feature_set features
;
62 /* Whether any mapping symbols are present in the provided symbol
63 table. -1 if we do not know yet, otherwise 0 or 1. */
64 int has_mapping_symbols
;
66 /* Track the last type (although this doesn't seem to be useful) */
67 enum map_type last_type
;
69 /* Tracking symbol table information */
71 bfd_vma last_mapping_addr
;
76 unsigned long arch
; /* Architecture defining this insn. */
77 unsigned long value
; /* If arch == 0 then value is a sentinel. */
78 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
79 const char * assembler
; /* How to disassemble this insn. */
84 unsigned long arch
; /* Architecture defining this insn. */
85 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
86 const char *assembler
; /* How to disassemble this insn. */
89 /* print_insn_coprocessor recognizes the following format control codes:
93 %c print condition code (always bits 28-31 in ARM mode)
94 %q print shifter argument
95 %u print condition code (unconditional in ARM mode,
96 UNPREDICTABLE if not AL in Thumb)
97 %A print address for ldc/stc/ldf/stf instruction
98 %B print vstm/vldm register list
99 %I print cirrus signed shift immediate: bits 0..3|4..6
100 %F print the COUNT field of a LFM/SFM instruction.
101 %P print floating point precision in arithmetic insn
102 %Q print floating point precision in ldf/stf insn
103 %R print floating point rounding mode
105 %<bitfield>c print as a condition code (for vsel)
106 %<bitfield>r print as an ARM register
107 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
108 %<bitfield>ru as %<>r but each u register must be unique.
109 %<bitfield>d print the bitfield in decimal
110 %<bitfield>k print immediate for VFPv3 conversion instruction
111 %<bitfield>x print the bitfield in hex
112 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
113 %<bitfield>f print a floating point constant if >7 else a
114 floating point register
115 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
116 %<bitfield>g print as an iWMMXt 64-bit register
117 %<bitfield>G print as an iWMMXt general purpose or control register
118 %<bitfield>D print as a NEON D register
119 %<bitfield>Q print as a NEON Q register
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
134 %i print 5-bit immediate in bits 8,3..0
136 %r print register offset address for wldt/wstr instruction. */
138 enum opcode_sentinel_enum
140 SENTINEL_IWMMXT_START
= 1,
142 SENTINEL_GENERIC_START
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
150 static const struct opcode32 coprocessor_opcodes
[] =
152 /* XScale instructions. */
153 {ARM_CEXT_XSCALE
, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_CEXT_XSCALE
, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
155 {ARM_CEXT_XSCALE
, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
156 {ARM_CEXT_XSCALE
, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
157 {ARM_CEXT_XSCALE
, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
159 /* Intel Wireless MMX technology instructions. */
160 { 0, SENTINEL_IWMMXT_START
, 0, "" },
161 {ARM_CEXT_IWMMXT
, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
162 {ARM_CEXT_XSCALE
, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
163 {ARM_CEXT_XSCALE
, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
164 {ARM_CEXT_XSCALE
, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
165 {ARM_CEXT_XSCALE
, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
166 {ARM_CEXT_XSCALE
, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
167 {ARM_CEXT_XSCALE
, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
168 {ARM_CEXT_XSCALE
, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
169 {ARM_CEXT_XSCALE
, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
170 {ARM_CEXT_XSCALE
, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
171 {ARM_CEXT_XSCALE
, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
172 {ARM_CEXT_XSCALE
, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
173 {ARM_CEXT_XSCALE
, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
174 {ARM_CEXT_XSCALE
, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
175 {ARM_CEXT_XSCALE
, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
176 {ARM_CEXT_XSCALE
, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
177 {ARM_CEXT_XSCALE
, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
178 {ARM_CEXT_XSCALE
, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
179 {ARM_CEXT_XSCALE
, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
180 {ARM_CEXT_XSCALE
, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
181 {ARM_CEXT_XSCALE
, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
182 {ARM_CEXT_XSCALE
, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
183 {ARM_CEXT_XSCALE
, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
184 {ARM_CEXT_XSCALE
, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
185 {ARM_CEXT_XSCALE
, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
186 {ARM_CEXT_XSCALE
, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
187 {ARM_CEXT_XSCALE
, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
188 {ARM_CEXT_XSCALE
, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
189 {ARM_CEXT_XSCALE
, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
190 {ARM_CEXT_XSCALE
, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
191 {ARM_CEXT_XSCALE
, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
192 {ARM_CEXT_XSCALE
, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
193 {ARM_CEXT_XSCALE
, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
194 {ARM_CEXT_XSCALE
, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
195 {ARM_CEXT_XSCALE
, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
196 {ARM_CEXT_XSCALE
, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
197 {ARM_CEXT_XSCALE
, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
198 {ARM_CEXT_XSCALE
, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
199 {ARM_CEXT_XSCALE
, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
200 {ARM_CEXT_XSCALE
, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
201 {ARM_CEXT_XSCALE
, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_CEXT_XSCALE
, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
203 {ARM_CEXT_XSCALE
, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_CEXT_XSCALE
, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_CEXT_XSCALE
, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_CEXT_XSCALE
, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
207 {ARM_CEXT_XSCALE
, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_CEXT_XSCALE
, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_CEXT_XSCALE
, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
210 {ARM_CEXT_XSCALE
, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_CEXT_XSCALE
, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
212 {ARM_CEXT_XSCALE
, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
213 {ARM_CEXT_XSCALE
, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
214 {ARM_CEXT_XSCALE
, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
215 {ARM_CEXT_XSCALE
, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_CEXT_XSCALE
, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
217 {ARM_CEXT_XSCALE
, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
218 {ARM_CEXT_XSCALE
, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
219 {ARM_CEXT_XSCALE
, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
220 {ARM_CEXT_XSCALE
, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
221 {ARM_CEXT_XSCALE
, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_CEXT_XSCALE
, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
223 {ARM_CEXT_XSCALE
, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
224 {ARM_CEXT_XSCALE
, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
225 {ARM_CEXT_XSCALE
, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
226 {ARM_CEXT_XSCALE
, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
227 {ARM_CEXT_XSCALE
, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_CEXT_XSCALE
, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
229 {ARM_CEXT_XSCALE
, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
230 {ARM_CEXT_XSCALE
, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
231 {ARM_CEXT_XSCALE
, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
232 {ARM_CEXT_XSCALE
, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
233 {ARM_CEXT_XSCALE
, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_CEXT_XSCALE
, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
235 {ARM_CEXT_XSCALE
, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
236 { 0, SENTINEL_IWMMXT_END
, 0, "" },
238 /* Floating point coprocessor (FPA) instructions. */
239 {FPU_FPA_EXT_V1
, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
240 {FPU_FPA_EXT_V1
, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
241 {FPU_FPA_EXT_V1
, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
242 {FPU_FPA_EXT_V1
, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
243 {FPU_FPA_EXT_V1
, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
244 {FPU_FPA_EXT_V1
, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
245 {FPU_FPA_EXT_V1
, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
246 {FPU_FPA_EXT_V1
, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
247 {FPU_FPA_EXT_V1
, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
248 {FPU_FPA_EXT_V1
, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
249 {FPU_FPA_EXT_V1
, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
250 {FPU_FPA_EXT_V1
, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
251 {FPU_FPA_EXT_V1
, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
252 {FPU_FPA_EXT_V1
, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
253 {FPU_FPA_EXT_V1
, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
254 {FPU_FPA_EXT_V1
, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
255 {FPU_FPA_EXT_V1
, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
256 {FPU_FPA_EXT_V1
, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
257 {FPU_FPA_EXT_V1
, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
258 {FPU_FPA_EXT_V1
, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
259 {FPU_FPA_EXT_V1
, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
260 {FPU_FPA_EXT_V1
, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
261 {FPU_FPA_EXT_V1
, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
262 {FPU_FPA_EXT_V1
, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
263 {FPU_FPA_EXT_V1
, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
264 {FPU_FPA_EXT_V1
, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
265 {FPU_FPA_EXT_V1
, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
266 {FPU_FPA_EXT_V1
, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
267 {FPU_FPA_EXT_V1
, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
268 {FPU_FPA_EXT_V1
, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
269 {FPU_FPA_EXT_V1
, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
270 {FPU_FPA_EXT_V1
, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
271 {FPU_FPA_EXT_V1
, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
272 {FPU_FPA_EXT_V1
, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
273 {FPU_FPA_EXT_V1
, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
274 {FPU_FPA_EXT_V1
, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
275 {FPU_FPA_EXT_V1
, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
276 {FPU_FPA_EXT_V1
, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
277 {FPU_FPA_EXT_V1
, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
278 {FPU_FPA_EXT_V1
, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
279 {FPU_FPA_EXT_V1
, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
280 {FPU_FPA_EXT_V2
, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
281 {FPU_FPA_EXT_V2
, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
283 /* Register load/store. */
284 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
285 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
286 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
287 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
288 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
289 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
290 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
291 {FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
292 {FPU_VFP_EXT_V1xD
, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
293 {FPU_VFP_EXT_V1xD
, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
294 {FPU_VFP_EXT_V1xD
, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
295 {FPU_VFP_EXT_V1xD
, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
296 {FPU_VFP_EXT_V1xD
, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
297 {FPU_VFP_EXT_V1xD
, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
298 {FPU_VFP_EXT_V1xD
, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
299 {FPU_VFP_EXT_V1xD
, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
301 {FPU_VFP_EXT_V1xD
, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
302 {FPU_VFP_EXT_V1xD
, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
303 {FPU_VFP_EXT_V1xD
, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
304 {FPU_VFP_EXT_V1xD
, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
306 /* Data transfer between ARM and NEON registers. */
307 {FPU_NEON_EXT_V1
, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
308 {FPU_NEON_EXT_V1
, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
309 {FPU_NEON_EXT_V1
, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
310 {FPU_NEON_EXT_V1
, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
311 {FPU_NEON_EXT_V1
, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
312 {FPU_NEON_EXT_V1
, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
313 {FPU_NEON_EXT_V1
, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
314 {FPU_NEON_EXT_V1
, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
315 {FPU_NEON_EXT_V1
, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
316 {FPU_NEON_EXT_V1
, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
317 {FPU_NEON_EXT_V1
, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
318 {FPU_NEON_EXT_V1
, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
319 {FPU_NEON_EXT_V1
, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
320 {FPU_NEON_EXT_V1
, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
321 /* Half-precision conversion instructions. */
322 {FPU_VFP_EXT_FP16
, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
323 {FPU_VFP_EXT_FP16
, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
325 /* Floating point coprocessor (VFP) instructions. */
326 {FPU_VFP_EXT_V1xD
, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
327 {FPU_VFP_EXT_V1xD
, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
328 {FPU_VFP_EXT_V1xD
, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
329 {FPU_VFP_EXT_V1xD
, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
330 {FPU_VFP_EXT_V1xD
, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
331 {FPU_VFP_EXT_V1xD
, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
332 {FPU_VFP_EXT_V1xD
, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
333 {FPU_VFP_EXT_V1xD
, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
334 {FPU_VFP_EXT_V1xD
, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
335 {FPU_VFP_EXT_V1xD
, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
336 {FPU_VFP_EXT_V1xD
, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
337 {FPU_VFP_EXT_V1xD
, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
338 {FPU_VFP_EXT_V1xD
, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
339 {FPU_VFP_EXT_V1xD
, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
340 {FPU_VFP_EXT_V1xD
, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
341 {FPU_VFP_EXT_V1
, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
342 {FPU_VFP_EXT_V1
, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
343 {FPU_VFP_EXT_V1xD
, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
344 {FPU_VFP_EXT_V1xD
, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
345 {FPU_VFP_EXT_V1xD
, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
346 {FPU_VFP_EXT_V1xD
, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
347 {FPU_VFP_EXT_V1xD
, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
348 {FPU_VFP_EXT_V1
, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
349 {FPU_VFP_EXT_V1xD
, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
350 {FPU_VFP_EXT_V1xD
, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
351 {FPU_VFP_EXT_V1
, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
352 {FPU_VFP_EXT_V1
, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
353 {FPU_VFP_EXT_V1xD
, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
354 {FPU_VFP_EXT_V1xD
, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
355 {FPU_VFP_EXT_V1
, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
356 {FPU_VFP_EXT_V1
, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
357 {FPU_VFP_EXT_V1
, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
358 {FPU_VFP_EXT_V1
, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
359 {FPU_VFP_EXT_V1xD
, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
360 {FPU_VFP_EXT_V1
, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
361 {FPU_VFP_EXT_V1xD
, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
362 {FPU_VFP_EXT_V1
, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
363 {FPU_VFP_EXT_V3xD
, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
364 {FPU_VFP_EXT_V3
, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
365 {FPU_VFP_EXT_V1xD
, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
366 {FPU_VFP_EXT_V1
, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
367 {FPU_VFP_EXT_V3xD
, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
368 {FPU_VFP_EXT_V3
, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
369 {FPU_VFP_EXT_V1
, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
370 {FPU_VFP_EXT_V3xD
, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
371 {FPU_VFP_EXT_V3
, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
372 {FPU_VFP_EXT_V2
, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
373 {FPU_VFP_EXT_V2
, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
374 {FPU_VFP_EXT_V2
, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
375 {FPU_VFP_EXT_V1xD
, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
376 {FPU_VFP_EXT_V1xD
, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
377 {FPU_VFP_EXT_V1
, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
378 {FPU_VFP_EXT_V1
, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
379 {FPU_VFP_EXT_V1xD
, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
380 {FPU_VFP_EXT_V1xD
, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
381 {FPU_VFP_EXT_V1
, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
382 {FPU_VFP_EXT_V1
, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
383 {FPU_VFP_EXT_V1xD
, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
384 {FPU_VFP_EXT_V1xD
, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
385 {FPU_VFP_EXT_V1
, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
386 {FPU_VFP_EXT_V1
, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
387 {FPU_VFP_EXT_V1xD
, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
388 {FPU_VFP_EXT_V1xD
, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
389 {FPU_VFP_EXT_V1
, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
390 {FPU_VFP_EXT_V1
, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
391 {FPU_VFP_EXT_V1xD
, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
392 {FPU_VFP_EXT_V1
, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
394 /* Cirrus coprocessor instructions. */
395 {ARM_CEXT_MAVERICK
, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
396 {ARM_CEXT_MAVERICK
, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
397 {ARM_CEXT_MAVERICK
, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
398 {ARM_CEXT_MAVERICK
, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
399 {ARM_CEXT_MAVERICK
, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
400 {ARM_CEXT_MAVERICK
, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
401 {ARM_CEXT_MAVERICK
, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
402 {ARM_CEXT_MAVERICK
, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
403 {ARM_CEXT_MAVERICK
, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
404 {ARM_CEXT_MAVERICK
, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
405 {ARM_CEXT_MAVERICK
, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
406 {ARM_CEXT_MAVERICK
, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
407 {ARM_CEXT_MAVERICK
, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
408 {ARM_CEXT_MAVERICK
, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
409 {ARM_CEXT_MAVERICK
, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
410 {ARM_CEXT_MAVERICK
, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
411 {ARM_CEXT_MAVERICK
, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
412 {ARM_CEXT_MAVERICK
, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
413 {ARM_CEXT_MAVERICK
, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
414 {ARM_CEXT_MAVERICK
, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
415 {ARM_CEXT_MAVERICK
, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
416 {ARM_CEXT_MAVERICK
, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
417 {ARM_CEXT_MAVERICK
, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
418 {ARM_CEXT_MAVERICK
, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
419 {ARM_CEXT_MAVERICK
, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
420 {ARM_CEXT_MAVERICK
, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
421 {ARM_CEXT_MAVERICK
, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
422 {ARM_CEXT_MAVERICK
, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
423 {ARM_CEXT_MAVERICK
, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
424 {ARM_CEXT_MAVERICK
, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
425 {ARM_CEXT_MAVERICK
, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
426 {ARM_CEXT_MAVERICK
, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
427 {ARM_CEXT_MAVERICK
, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
428 {ARM_CEXT_MAVERICK
, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
429 {ARM_CEXT_MAVERICK
, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
430 {ARM_CEXT_MAVERICK
, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
431 {ARM_CEXT_MAVERICK
, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
432 {ARM_CEXT_MAVERICK
, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
433 {ARM_CEXT_MAVERICK
, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
434 {ARM_CEXT_MAVERICK
, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
435 {ARM_CEXT_MAVERICK
, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
436 {ARM_CEXT_MAVERICK
, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
437 {ARM_CEXT_MAVERICK
, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
438 {ARM_CEXT_MAVERICK
, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
439 {ARM_CEXT_MAVERICK
, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
440 {ARM_CEXT_MAVERICK
, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
441 {ARM_CEXT_MAVERICK
, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
442 {ARM_CEXT_MAVERICK
, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
443 {ARM_CEXT_MAVERICK
, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
444 {ARM_CEXT_MAVERICK
, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
445 {ARM_CEXT_MAVERICK
, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
446 {ARM_CEXT_MAVERICK
, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
447 {ARM_CEXT_MAVERICK
, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
448 {ARM_CEXT_MAVERICK
, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
449 {ARM_CEXT_MAVERICK
, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
450 {ARM_CEXT_MAVERICK
, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
451 {ARM_CEXT_MAVERICK
, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
452 {ARM_CEXT_MAVERICK
, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
453 {ARM_CEXT_MAVERICK
, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
454 {ARM_CEXT_MAVERICK
, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
455 {ARM_CEXT_MAVERICK
, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
456 {ARM_CEXT_MAVERICK
, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
457 {ARM_CEXT_MAVERICK
, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
458 {ARM_CEXT_MAVERICK
, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
459 {ARM_CEXT_MAVERICK
, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
460 {ARM_CEXT_MAVERICK
, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
461 {ARM_CEXT_MAVERICK
, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
462 {ARM_CEXT_MAVERICK
, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
463 {ARM_CEXT_MAVERICK
, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
464 {ARM_CEXT_MAVERICK
, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
465 {ARM_CEXT_MAVERICK
, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
466 {ARM_CEXT_MAVERICK
, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
467 {ARM_CEXT_MAVERICK
, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
468 {ARM_CEXT_MAVERICK
, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
469 {ARM_CEXT_MAVERICK
, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
470 {ARM_CEXT_MAVERICK
, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
471 {ARM_CEXT_MAVERICK
, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
472 {ARM_CEXT_MAVERICK
, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
473 {ARM_CEXT_MAVERICK
, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
474 {ARM_CEXT_MAVERICK
, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
475 {ARM_CEXT_MAVERICK
, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
476 {ARM_CEXT_MAVERICK
, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
477 {ARM_CEXT_MAVERICK
, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
478 {ARM_CEXT_MAVERICK
, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
480 /* VFP Fused multiply add instructions. */
481 {FPU_VFP_EXT_FMA
, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
482 {FPU_VFP_EXT_FMA
, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
483 {FPU_VFP_EXT_FMA
, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
484 {FPU_VFP_EXT_FMA
, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
485 {FPU_VFP_EXT_FMA
, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
486 {FPU_VFP_EXT_FMA
, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
487 {FPU_VFP_EXT_FMA
, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
488 {FPU_VFP_EXT_FMA
, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
491 {FPU_VFP_EXT_ARMV8
, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
492 {FPU_VFP_EXT_ARMV8
, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
494 /* Generic coprocessor instructions. */
495 { 0, SENTINEL_GENERIC_START
, 0, "" },
496 {ARM_EXT_V5E
, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
497 {ARM_EXT_V5E
, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
498 {ARM_EXT_V2
, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
499 {ARM_EXT_V2
, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
500 {ARM_EXT_V2
, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
501 {ARM_EXT_V2
, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
502 {ARM_EXT_V2
, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
503 {ARM_EXT_V2
, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
505 /* V6 coprocessor instructions. */
506 {ARM_EXT_V6
, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
507 {ARM_EXT_V6
, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
509 /* V5 coprocessor instructions. */
510 {ARM_EXT_V5
, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
511 {ARM_EXT_V5
, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
512 {ARM_EXT_V5
, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
513 {ARM_EXT_V5
, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
514 {ARM_EXT_V5
, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
519 /* Neon opcode table: This does not encode the top byte -- that is
520 checked by the print_insn_neon routine, as it depends on whether we are
521 doing thumb32 or arm32 disassembly. */
523 /* print_insn_neon recognizes the following format control codes:
527 %c print condition code
528 %u print condition code (unconditional in ARM mode,
529 UNPREDICTABLE if not AL in Thumb)
530 %A print v{st,ld}[1234] operands
531 %B print v{st,ld}[1234] any one operands
532 %C print v{st,ld}[1234] single->all operands
534 %E print vmov, vmvn, vorr, vbic encoded constant
535 %F print vtbl,vtbx register list
537 %<bitfield>r print as an ARM register
538 %<bitfield>d print the bitfield in decimal
539 %<bitfield>e print the 2^N - bitfield in decimal
540 %<bitfield>D print as a NEON D register
541 %<bitfield>Q print as a NEON Q register
542 %<bitfield>R print as a NEON D or Q register
543 %<bitfield>Sn print byte scaled width limited by n
544 %<bitfield>Tn print short scaled width limited by n
545 %<bitfield>Un print long scaled width limited by n
547 %<bitfield>'c print specified char iff bitfield is all ones
548 %<bitfield>`c print specified char iff bitfield is all zeroes
549 %<bitfield>?ab... select from array of values in big endian order. */
551 static const struct opcode32 neon_opcodes
[] =
554 {FPU_NEON_EXT_V1
, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
555 {FPU_NEON_EXT_V1
, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
557 /* Move data element to all lanes. */
558 {FPU_NEON_EXT_V1
, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
559 {FPU_NEON_EXT_V1
, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
560 {FPU_NEON_EXT_V1
, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
563 {FPU_NEON_EXT_V1
, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
564 {FPU_NEON_EXT_V1
, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
566 /* Half-precision conversions. */
567 {FPU_VFP_EXT_FP16
, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
568 {FPU_VFP_EXT_FP16
, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
570 /* NEON fused multiply add instructions. */
571 {FPU_NEON_EXT_FMA
, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
572 {FPU_NEON_EXT_FMA
, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
574 /* Two registers, miscellaneous. */
575 {FPU_NEON_EXT_V1
, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
576 {FPU_NEON_EXT_V1
, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
577 {FPU_NEON_EXT_V1
, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
578 {FPU_NEON_EXT_V1
, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
579 {FPU_NEON_EXT_V1
, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
580 {FPU_NEON_EXT_V1
, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
581 {FPU_NEON_EXT_V1
, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
582 {FPU_NEON_EXT_V1
, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
583 {FPU_NEON_EXT_V1
, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
584 {FPU_NEON_EXT_V1
, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
585 {FPU_NEON_EXT_V1
, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
586 {FPU_NEON_EXT_V1
, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
587 {FPU_NEON_EXT_V1
, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
588 {FPU_NEON_EXT_V1
, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
589 {FPU_NEON_EXT_V1
, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
590 {FPU_NEON_EXT_V1
, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
591 {FPU_NEON_EXT_V1
, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
592 {FPU_NEON_EXT_V1
, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
593 {FPU_NEON_EXT_V1
, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
594 {FPU_NEON_EXT_V1
, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
595 {FPU_NEON_EXT_V1
, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
596 {FPU_NEON_EXT_V1
, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
597 {FPU_NEON_EXT_V1
, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
598 {FPU_NEON_EXT_V1
, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
599 {FPU_NEON_EXT_V1
, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
600 {FPU_NEON_EXT_V1
, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
601 {FPU_NEON_EXT_V1
, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
602 {FPU_NEON_EXT_V1
, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
603 {FPU_NEON_EXT_V1
, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
604 {FPU_NEON_EXT_V1
, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
605 {FPU_NEON_EXT_V1
, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
606 {FPU_NEON_EXT_V1
, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
607 {FPU_NEON_EXT_V1
, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
609 /* Three registers of the same length. */
610 {FPU_NEON_EXT_V1
, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
611 {FPU_NEON_EXT_V1
, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
612 {FPU_NEON_EXT_V1
, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
613 {FPU_NEON_EXT_V1
, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
614 {FPU_NEON_EXT_V1
, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
615 {FPU_NEON_EXT_V1
, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
616 {FPU_NEON_EXT_V1
, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
617 {FPU_NEON_EXT_V1
, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
618 {FPU_NEON_EXT_V1
, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
619 {FPU_NEON_EXT_V1
, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
620 {FPU_NEON_EXT_V1
, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
621 {FPU_NEON_EXT_V1
, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
622 {FPU_NEON_EXT_V1
, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
623 {FPU_NEON_EXT_V1
, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
624 {FPU_NEON_EXT_V1
, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
625 {FPU_NEON_EXT_V1
, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
626 {FPU_NEON_EXT_V1
, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
627 {FPU_NEON_EXT_V1
, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
628 {FPU_NEON_EXT_V1
, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
629 {FPU_NEON_EXT_V1
, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
630 {FPU_NEON_EXT_V1
, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
631 {FPU_NEON_EXT_V1
, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
632 {FPU_NEON_EXT_V1
, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
633 {FPU_NEON_EXT_V1
, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
634 {FPU_NEON_EXT_V1
, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
635 {FPU_NEON_EXT_V1
, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
636 {FPU_NEON_EXT_V1
, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
637 {FPU_NEON_EXT_V1
, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
638 {FPU_NEON_EXT_V1
, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
639 {FPU_NEON_EXT_V1
, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
640 {FPU_NEON_EXT_V1
, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
641 {FPU_NEON_EXT_V1
, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
642 {FPU_NEON_EXT_V1
, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
643 {FPU_NEON_EXT_V1
, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
644 {FPU_NEON_EXT_V1
, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
645 {FPU_NEON_EXT_V1
, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
646 {FPU_NEON_EXT_V1
, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
647 {FPU_NEON_EXT_V1
, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
648 {FPU_NEON_EXT_V1
, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
649 {FPU_NEON_EXT_V1
, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
650 {FPU_NEON_EXT_V1
, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
651 {FPU_NEON_EXT_V1
, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
652 {FPU_NEON_EXT_V1
, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
653 {FPU_NEON_EXT_V1
, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
654 {FPU_NEON_EXT_V1
, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
655 {FPU_NEON_EXT_V1
, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
656 {FPU_NEON_EXT_V1
, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
657 {FPU_NEON_EXT_V1
, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
658 {FPU_NEON_EXT_V1
, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
659 {FPU_NEON_EXT_V1
, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
660 {FPU_NEON_EXT_V1
, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
661 {FPU_NEON_EXT_V1
, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
662 {FPU_NEON_EXT_V1
, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
664 /* One register and an immediate value. */
665 {FPU_NEON_EXT_V1
, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
666 {FPU_NEON_EXT_V1
, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
667 {FPU_NEON_EXT_V1
, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
668 {FPU_NEON_EXT_V1
, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
669 {FPU_NEON_EXT_V1
, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
670 {FPU_NEON_EXT_V1
, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
671 {FPU_NEON_EXT_V1
, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
672 {FPU_NEON_EXT_V1
, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
673 {FPU_NEON_EXT_V1
, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
674 {FPU_NEON_EXT_V1
, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
675 {FPU_NEON_EXT_V1
, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
676 {FPU_NEON_EXT_V1
, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
677 {FPU_NEON_EXT_V1
, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
679 /* Two registers and a shift amount. */
680 {FPU_NEON_EXT_V1
, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
681 {FPU_NEON_EXT_V1
, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
682 {FPU_NEON_EXT_V1
, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
683 {FPU_NEON_EXT_V1
, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
684 {FPU_NEON_EXT_V1
, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
685 {FPU_NEON_EXT_V1
, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
686 {FPU_NEON_EXT_V1
, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
687 {FPU_NEON_EXT_V1
, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
688 {FPU_NEON_EXT_V1
, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
689 {FPU_NEON_EXT_V1
, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
690 {FPU_NEON_EXT_V1
, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
691 {FPU_NEON_EXT_V1
, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
692 {FPU_NEON_EXT_V1
, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
693 {FPU_NEON_EXT_V1
, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
694 {FPU_NEON_EXT_V1
, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
695 {FPU_NEON_EXT_V1
, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
696 {FPU_NEON_EXT_V1
, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
697 {FPU_NEON_EXT_V1
, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
698 {FPU_NEON_EXT_V1
, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
699 {FPU_NEON_EXT_V1
, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
700 {FPU_NEON_EXT_V1
, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
701 {FPU_NEON_EXT_V1
, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
702 {FPU_NEON_EXT_V1
, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
703 {FPU_NEON_EXT_V1
, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
704 {FPU_NEON_EXT_V1
, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
705 {FPU_NEON_EXT_V1
, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
706 {FPU_NEON_EXT_V1
, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
707 {FPU_NEON_EXT_V1
, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
708 {FPU_NEON_EXT_V1
, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
709 {FPU_NEON_EXT_V1
, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
710 {FPU_NEON_EXT_V1
, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
711 {FPU_NEON_EXT_V1
, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
712 {FPU_NEON_EXT_V1
, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
713 {FPU_NEON_EXT_V1
, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
714 {FPU_NEON_EXT_V1
, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
715 {FPU_NEON_EXT_V1
, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
716 {FPU_NEON_EXT_V1
, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
717 {FPU_NEON_EXT_V1
, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
718 {FPU_NEON_EXT_V1
, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
719 {FPU_NEON_EXT_V1
, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
720 {FPU_NEON_EXT_V1
, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
721 {FPU_NEON_EXT_V1
, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
722 {FPU_NEON_EXT_V1
, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
723 {FPU_NEON_EXT_V1
, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
724 {FPU_NEON_EXT_V1
, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
725 {FPU_NEON_EXT_V1
, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
726 {FPU_NEON_EXT_V1
, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
727 {FPU_NEON_EXT_V1
, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
728 {FPU_NEON_EXT_V1
, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
729 {FPU_NEON_EXT_V1
, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
730 {FPU_NEON_EXT_V1
, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
731 {FPU_NEON_EXT_V1
, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
732 {FPU_NEON_EXT_V1
, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
733 {FPU_NEON_EXT_V1
, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
734 {FPU_NEON_EXT_V1
, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
735 {FPU_NEON_EXT_V1
, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
736 {FPU_NEON_EXT_V1
, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
737 {FPU_NEON_EXT_V1
, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
739 /* Three registers of different lengths. */
740 {FPU_NEON_EXT_V1
, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
741 {FPU_NEON_EXT_V1
, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
742 {FPU_NEON_EXT_V1
, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
743 {FPU_NEON_EXT_V1
, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
744 {FPU_NEON_EXT_V1
, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
745 {FPU_NEON_EXT_V1
, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
746 {FPU_NEON_EXT_V1
, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
747 {FPU_NEON_EXT_V1
, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
748 {FPU_NEON_EXT_V1
, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
749 {FPU_NEON_EXT_V1
, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
750 {FPU_NEON_EXT_V1
, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
751 {FPU_NEON_EXT_V1
, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
752 {FPU_NEON_EXT_V1
, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
753 {FPU_NEON_EXT_V1
, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
754 {FPU_NEON_EXT_V1
, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
755 {FPU_NEON_EXT_V1
, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
756 {FPU_NEON_EXT_V1
, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
758 /* Two registers and a scalar. */
759 {FPU_NEON_EXT_V1
, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
760 {FPU_NEON_EXT_V1
, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
761 {FPU_NEON_EXT_V1
, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
762 {FPU_NEON_EXT_V1
, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
763 {FPU_NEON_EXT_V1
, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
764 {FPU_NEON_EXT_V1
, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
765 {FPU_NEON_EXT_V1
, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
766 {FPU_NEON_EXT_V1
, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
767 {FPU_NEON_EXT_V1
, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
768 {FPU_NEON_EXT_V1
, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
769 {FPU_NEON_EXT_V1
, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
770 {FPU_NEON_EXT_V1
, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
771 {FPU_NEON_EXT_V1
, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
772 {FPU_NEON_EXT_V1
, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
773 {FPU_NEON_EXT_V1
, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
774 {FPU_NEON_EXT_V1
, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
775 {FPU_NEON_EXT_V1
, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
776 {FPU_NEON_EXT_V1
, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
777 {FPU_NEON_EXT_V1
, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
778 {FPU_NEON_EXT_V1
, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
779 {FPU_NEON_EXT_V1
, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
780 {FPU_NEON_EXT_V1
, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
782 /* Element and structure load/store. */
783 {FPU_NEON_EXT_V1
, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
784 {FPU_NEON_EXT_V1
, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
785 {FPU_NEON_EXT_V1
, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
786 {FPU_NEON_EXT_V1
, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
787 {FPU_NEON_EXT_V1
, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
788 {FPU_NEON_EXT_V1
, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
789 {FPU_NEON_EXT_V1
, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
790 {FPU_NEON_EXT_V1
, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
791 {FPU_NEON_EXT_V1
, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
792 {FPU_NEON_EXT_V1
, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
793 {FPU_NEON_EXT_V1
, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
794 {FPU_NEON_EXT_V1
, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
795 {FPU_NEON_EXT_V1
, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
796 {FPU_NEON_EXT_V1
, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
797 {FPU_NEON_EXT_V1
, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
798 {FPU_NEON_EXT_V1
, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
799 {FPU_NEON_EXT_V1
, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
800 {FPU_NEON_EXT_V1
, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
801 {FPU_NEON_EXT_V1
, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
806 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
807 ordered: they must be searched linearly from the top to obtain a correct
810 /* print_insn_arm recognizes the following format control codes:
814 %a print address for ldr/str instruction
815 %s print address for ldr/str halfword/signextend instruction
816 %S like %s but allow UNPREDICTABLE addressing
817 %b print branch destination
818 %c print condition code (always bits 28-31)
819 %m print register mask for ldm/stm instruction
820 %o print operand2 (immediate or register + shift)
821 %p print 'p' iff bits 12-15 are 15
822 %t print 't' iff bit 21 set and bit 24 clear
823 %B print arm BLX(1) destination
824 %C print the PSR sub type.
825 %U print barrier type.
826 %P print address for pli instruction.
828 %<bitfield>r print as an ARM register
829 %<bitfield>T print as an ARM register + 1
830 %<bitfield>R as %r but r15 is UNPREDICTABLE
831 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
832 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
833 %<bitfield>d print the bitfield in decimal
834 %<bitfield>W print the bitfield plus one in decimal
835 %<bitfield>x print the bitfield in hex
836 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
838 %<bitfield>'c print specified char iff bitfield is all ones
839 %<bitfield>`c print specified char iff bitfield is all zeroes
840 %<bitfield>?ab... select from array of values in big endian order
842 %e print arm SMI operand (bits 0..7,8..19).
843 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
844 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
845 %R print the SPSR/CPSR or banked register of an MRS. */
847 static const struct opcode32 arm_opcodes
[] =
849 /* ARM instructions. */
850 {ARM_EXT_V1
, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
851 {ARM_EXT_V4T
| ARM_EXT_V5
, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
852 {ARM_EXT_V2
, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
853 {ARM_EXT_V2
, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
854 {ARM_EXT_V2S
, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
855 {ARM_EXT_V3M
, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
856 {ARM_EXT_V3M
, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
858 /* V8 instructions. */
859 {ARM_EXT_V8
, 0x0320f005, 0x0fffffff, "sevl"},
860 {ARM_EXT_V8
, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
861 {ARM_EXT_V8
, 0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
862 {ARM_EXT_V8
, 0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
863 {ARM_EXT_V8
, 0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
864 {ARM_EXT_V8
, 0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
865 {ARM_EXT_V8
, 0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
866 {ARM_EXT_V8
, 0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
867 {ARM_EXT_V8
, 0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
868 {ARM_EXT_V8
, 0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
869 {ARM_EXT_V8
, 0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
870 {ARM_EXT_V8
, 0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
871 {ARM_EXT_V8
, 0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
872 {ARM_EXT_V8
, 0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
873 {ARM_EXT_V8
, 0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
874 {ARM_EXT_V8
, 0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
876 /* Virtualization Extension instructions. */
877 {ARM_EXT_VIRT
, 0x0160006e, 0x0fffffff, "eret%c"},
878 {ARM_EXT_VIRT
, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
880 /* Integer Divide Extension instructions. */
881 {ARM_EXT_ADIV
, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
882 {ARM_EXT_ADIV
, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
884 /* MP Extension instructions. */
885 {ARM_EXT_MP
, 0xf410f000, 0xfc70f000, "pldw\t%a"},
887 /* V7 instructions. */
888 {ARM_EXT_V7
, 0xf450f000, 0xfd70f000, "pli\t%P"},
889 {ARM_EXT_V7
, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
890 {ARM_EXT_V8
, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
891 {ARM_EXT_V8
, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
892 {ARM_EXT_V7
, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
893 {ARM_EXT_V7
, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
894 {ARM_EXT_V7
, 0xf57ff060, 0xfffffff0, "isb\t%U"},
896 /* ARM V6T2 instructions. */
897 {ARM_EXT_V6T2
, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
898 {ARM_EXT_V6T2
, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
899 {ARM_EXT_V6T2
, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
900 {ARM_EXT_V6T2
, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
902 {ARM_EXT_V6T2
, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
903 {ARM_EXT_V6T2
, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
905 {ARM_EXT_V6T2
, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
906 {ARM_EXT_V6T2
, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
907 {ARM_EXT_V6T2
, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
908 {ARM_EXT_V6T2
, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
910 /* ARM Security extension instructions. */
911 {ARM_EXT_SEC
, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
913 /* ARM V6K instructions. */
914 {ARM_EXT_V6K
, 0xf57ff01f, 0xffffffff, "clrex"},
915 {ARM_EXT_V6K
, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
916 {ARM_EXT_V6K
, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
917 {ARM_EXT_V6K
, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
918 {ARM_EXT_V6K
, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
919 {ARM_EXT_V6K
, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
920 {ARM_EXT_V6K
, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
922 /* ARM V6K NOP hints. */
923 {ARM_EXT_V6K
, 0x0320f001, 0x0fffffff, "yield%c"},
924 {ARM_EXT_V6K
, 0x0320f002, 0x0fffffff, "wfe%c"},
925 {ARM_EXT_V6K
, 0x0320f003, 0x0fffffff, "wfi%c"},
926 {ARM_EXT_V6K
, 0x0320f004, 0x0fffffff, "sev%c"},
927 {ARM_EXT_V6K
, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
929 /* ARM V6 instructions. */
930 {ARM_EXT_V6
, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
931 {ARM_EXT_V6
, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
932 {ARM_EXT_V6
, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
933 {ARM_EXT_V6
, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
934 {ARM_EXT_V6
, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
935 {ARM_EXT_V6
, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
936 {ARM_EXT_V6
, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
937 {ARM_EXT_V6
, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
938 {ARM_EXT_V6
, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
939 {ARM_EXT_V6
, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
940 {ARM_EXT_V6
, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
941 {ARM_EXT_V6
, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
942 {ARM_EXT_V6
, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
943 {ARM_EXT_V6
, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
944 {ARM_EXT_V6
, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
945 {ARM_EXT_V6
, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
946 {ARM_EXT_V6
, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
947 {ARM_EXT_V6
, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
948 {ARM_EXT_V6
, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
949 {ARM_EXT_V6
, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
950 {ARM_EXT_V6
, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
951 {ARM_EXT_V6
, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
952 {ARM_EXT_V6
, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
953 {ARM_EXT_V6
, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
954 {ARM_EXT_V6
, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
955 {ARM_EXT_V6
, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
956 {ARM_EXT_V6
, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
957 {ARM_EXT_V6
, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
958 {ARM_EXT_V6
, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
959 {ARM_EXT_V6
, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
960 {ARM_EXT_V6
, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
961 {ARM_EXT_V6
, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
962 {ARM_EXT_V6
, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
963 {ARM_EXT_V6
, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
964 {ARM_EXT_V6
, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
965 {ARM_EXT_V6
, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
966 {ARM_EXT_V6
, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
967 {ARM_EXT_V6
, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
968 {ARM_EXT_V6
, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
969 {ARM_EXT_V6
, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
970 {ARM_EXT_V6
, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
971 {ARM_EXT_V6
, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
972 {ARM_EXT_V6
, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
973 {ARM_EXT_V6
, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
974 {ARM_EXT_V6
, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
975 {ARM_EXT_V6
, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
976 {ARM_EXT_V6
, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
977 {ARM_EXT_V6
, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
978 {ARM_EXT_V6
, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
979 {ARM_EXT_V6
, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
980 {ARM_EXT_V6
, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
981 {ARM_EXT_V6
, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
982 {ARM_EXT_V6
, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
983 {ARM_EXT_V6
, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
984 {ARM_EXT_V6
, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
985 {ARM_EXT_V6
, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
986 {ARM_EXT_V6
, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
987 {ARM_EXT_V6
, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
988 {ARM_EXT_V6
, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
989 {ARM_EXT_V6
, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
990 {ARM_EXT_V6
, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
991 {ARM_EXT_V6
, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
992 {ARM_EXT_V6
, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
993 {ARM_EXT_V6
, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
994 {ARM_EXT_V6
, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
995 {ARM_EXT_V6
, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
996 {ARM_EXT_V6
, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
997 {ARM_EXT_V6
, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
998 {ARM_EXT_V6
, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
999 {ARM_EXT_V6
, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1000 {ARM_EXT_V6
, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1001 {ARM_EXT_V6
, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1002 {ARM_EXT_V6
, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1003 {ARM_EXT_V6
, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1004 {ARM_EXT_V6
, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1005 {ARM_EXT_V6
, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1006 {ARM_EXT_V6
, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1007 {ARM_EXT_V6
, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1008 {ARM_EXT_V6
, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1009 {ARM_EXT_V6
, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1010 {ARM_EXT_V6
, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1011 {ARM_EXT_V6
, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1012 {ARM_EXT_V6
, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1013 {ARM_EXT_V6
, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1014 {ARM_EXT_V6
, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1015 {ARM_EXT_V6
, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1016 {ARM_EXT_V6
, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1017 {ARM_EXT_V6
, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1018 {ARM_EXT_V6
, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1019 {ARM_EXT_V6
, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1020 {ARM_EXT_V6
, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1021 {ARM_EXT_V6
, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1022 {ARM_EXT_V6
, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1023 {ARM_EXT_V6
, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1024 {ARM_EXT_V6
, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1025 {ARM_EXT_V6
, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1026 {ARM_EXT_V6
, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1027 {ARM_EXT_V6
, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1028 {ARM_EXT_V6
, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1029 {ARM_EXT_V6
, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1030 {ARM_EXT_V6
, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1031 {ARM_EXT_V6
, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1032 {ARM_EXT_V6
, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1033 {ARM_EXT_V6
, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1034 {ARM_EXT_V6
, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1035 {ARM_EXT_V6
, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1036 {ARM_EXT_V6
, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1037 {ARM_EXT_V6
, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1038 {ARM_EXT_V6
, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1039 {ARM_EXT_V6
, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1040 {ARM_EXT_V6
, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1041 {ARM_EXT_V6
, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1042 {ARM_EXT_V6
, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1043 {ARM_EXT_V6
, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1044 {ARM_EXT_V6
, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1045 {ARM_EXT_V6
, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1046 {ARM_EXT_V6
, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1047 {ARM_EXT_V6
, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1048 {ARM_EXT_V6
, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1049 {ARM_EXT_V6
, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1050 {ARM_EXT_V6
, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1051 {ARM_EXT_V6
, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1053 /* V5J instruction. */
1054 {ARM_EXT_V5J
, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1056 /* V5 Instructions. */
1057 {ARM_EXT_V5
, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1058 {ARM_EXT_V5
, 0xfa000000, 0xfe000000, "blx\t%B"},
1059 {ARM_EXT_V5
, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1060 {ARM_EXT_V5
, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1062 /* V5E "El Segundo" Instructions. */
1063 {ARM_EXT_V5E
, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1064 {ARM_EXT_V5E
, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1065 {ARM_EXT_V5E
, 0xf450f000, 0xfc70f000, "pld\t%a"},
1066 {ARM_EXT_V5ExP
, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1067 {ARM_EXT_V5ExP
, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1068 {ARM_EXT_V5ExP
, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1069 {ARM_EXT_V5ExP
, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1071 {ARM_EXT_V5ExP
, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1072 {ARM_EXT_V5ExP
, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1074 {ARM_EXT_V5ExP
, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1075 {ARM_EXT_V5ExP
, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1076 {ARM_EXT_V5ExP
, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1077 {ARM_EXT_V5ExP
, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1079 {ARM_EXT_V5ExP
, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1080 {ARM_EXT_V5ExP
, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1081 {ARM_EXT_V5ExP
, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1082 {ARM_EXT_V5ExP
, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1084 {ARM_EXT_V5ExP
, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1085 {ARM_EXT_V5ExP
, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1087 {ARM_EXT_V5ExP
, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1088 {ARM_EXT_V5ExP
, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1089 {ARM_EXT_V5ExP
, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1090 {ARM_EXT_V5ExP
, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1092 /* ARM Instructions. */
1093 {ARM_EXT_V1
, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1095 {ARM_EXT_V1
, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1096 {ARM_EXT_V1
, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1097 {ARM_EXT_V1
, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1098 {ARM_EXT_V1
, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1099 {ARM_EXT_V1
, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1100 {ARM_EXT_V1
, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1102 {ARM_EXT_V1
, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1103 {ARM_EXT_V1
, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1104 {ARM_EXT_V1
, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1105 {ARM_EXT_V1
, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1107 {ARM_EXT_V1
, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
1108 {ARM_EXT_V1
, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1109 {ARM_EXT_V1
, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
1110 {ARM_EXT_V1
, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1112 {ARM_EXT_V1
, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1113 {ARM_EXT_V1
, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1114 {ARM_EXT_V1
, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1116 {ARM_EXT_V1
, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1117 {ARM_EXT_V1
, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1118 {ARM_EXT_V1
, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1120 {ARM_EXT_V1
, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1121 {ARM_EXT_V1
, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1122 {ARM_EXT_V1
, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1124 {ARM_EXT_V1
, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1125 {ARM_EXT_V1
, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1126 {ARM_EXT_V1
, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1128 {ARM_EXT_V1
, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1129 {ARM_EXT_V1
, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1130 {ARM_EXT_V1
, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1132 {ARM_EXT_V1
, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1133 {ARM_EXT_V1
, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1134 {ARM_EXT_V1
, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1136 {ARM_EXT_V1
, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1137 {ARM_EXT_V1
, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1138 {ARM_EXT_V1
, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1140 {ARM_EXT_V1
, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1141 {ARM_EXT_V1
, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1142 {ARM_EXT_V1
, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1144 {ARM_EXT_VIRT
, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1145 {ARM_EXT_V3
, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1146 {ARM_EXT_V3
, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1148 {ARM_EXT_V1
, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1149 {ARM_EXT_V1
, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1150 {ARM_EXT_V1
, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1152 {ARM_EXT_V1
, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1153 {ARM_EXT_V1
, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1154 {ARM_EXT_V1
, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1156 {ARM_EXT_V1
, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1157 {ARM_EXT_V1
, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1158 {ARM_EXT_V1
, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1160 {ARM_EXT_V1
, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1161 {ARM_EXT_V1
, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1162 {ARM_EXT_V1
, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1164 {ARM_EXT_V1
, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1165 {ARM_EXT_V1
, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1166 {ARM_EXT_V1
, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1168 {ARM_EXT_V1
, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1169 {ARM_EXT_V1
, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1170 {ARM_EXT_V1
, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1171 {ARM_EXT_V1
, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1172 {ARM_EXT_V1
, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1173 {ARM_EXT_V1
, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1174 {ARM_EXT_V1
, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1176 {ARM_EXT_V1
, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1177 {ARM_EXT_V1
, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1178 {ARM_EXT_V1
, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1180 {ARM_EXT_V1
, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1181 {ARM_EXT_V1
, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1182 {ARM_EXT_V1
, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1184 {ARM_EXT_V1
, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
1185 {ARM_EXT_V1
, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1187 {ARM_EXT_V1
, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1189 {ARM_EXT_V1
, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1190 {ARM_EXT_V1
, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1192 {ARM_EXT_V1
, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1193 {ARM_EXT_V1
, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1194 {ARM_EXT_V1
, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1195 {ARM_EXT_V1
, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1196 {ARM_EXT_V1
, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1197 {ARM_EXT_V1
, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1198 {ARM_EXT_V1
, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1199 {ARM_EXT_V1
, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1200 {ARM_EXT_V1
, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1201 {ARM_EXT_V1
, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1202 {ARM_EXT_V1
, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1203 {ARM_EXT_V1
, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1204 {ARM_EXT_V1
, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1205 {ARM_EXT_V1
, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1206 {ARM_EXT_V1
, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1207 {ARM_EXT_V1
, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1208 {ARM_EXT_V1
, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1209 {ARM_EXT_V1
, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1210 {ARM_EXT_V1
, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1212 {ARM_EXT_V1
, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1213 {ARM_EXT_V1
, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1214 {ARM_EXT_V1
, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1215 {ARM_EXT_V1
, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1216 {ARM_EXT_V1
, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1217 {ARM_EXT_V1
, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1218 {ARM_EXT_V1
, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1219 {ARM_EXT_V1
, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1220 {ARM_EXT_V1
, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1221 {ARM_EXT_V1
, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1222 {ARM_EXT_V1
, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1223 {ARM_EXT_V1
, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1224 {ARM_EXT_V1
, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1225 {ARM_EXT_V1
, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1226 {ARM_EXT_V1
, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1227 {ARM_EXT_V1
, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1228 {ARM_EXT_V1
, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1229 {ARM_EXT_V1
, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1230 {ARM_EXT_V1
, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1232 {ARM_EXT_V1
, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1233 {ARM_EXT_V1
, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1236 {ARM_EXT_V1
, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
1237 {0, 0x00000000, 0x00000000, 0}
1240 /* print_insn_thumb16 recognizes the following format control codes:
1242 %S print Thumb register (bits 3..5 as high number if bit 6 set)
1243 %D print Thumb register (bits 0..2 as high number if bit 7 set)
1244 %<bitfield>I print bitfield as a signed decimal
1245 (top bit of range being the sign bit)
1246 %N print Thumb register mask (with LR)
1247 %O print Thumb register mask (with PC)
1248 %M print Thumb register mask
1249 %b print CZB's 6-bit unsigned branch destination
1250 %s print Thumb right-shift immediate (6..10; 0 == 32).
1251 %c print the condition code
1252 %C print the condition code, or "s" if not conditional
1253 %x print warning if conditional an not at end of IT block"
1254 %X print "\t; unpredictable <IT:code>" if conditional
1255 %I print IT instruction suffix and operands
1256 %W print Thumb Writeback indicator for LDMIA
1257 %<bitfield>r print bitfield as an ARM register
1258 %<bitfield>d print bitfield as a decimal
1259 %<bitfield>H print (bitfield * 2) as a decimal
1260 %<bitfield>W print (bitfield * 4) as a decimal
1261 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1262 %<bitfield>B print Thumb branch destination (signed displacement)
1263 %<bitfield>c print bitfield as a condition code
1264 %<bitnum>'c print specified char iff bit is one
1265 %<bitnum>?ab print a if bit is one else print b. */
1267 static const struct opcode16 thumb_opcodes
[] =
1269 /* Thumb instructions. */
1271 /* ARM V8 instructions. */
1272 {ARM_EXT_V8
, 0xbf50, 0xffff, "sevl%c"},
1273 {ARM_EXT_V8
, 0xba80, 0xffc0, "hlt\t%0-5x"},
1275 /* ARM V6K no-argument instructions. */
1276 {ARM_EXT_V6K
, 0xbf00, 0xffff, "nop%c"},
1277 {ARM_EXT_V6K
, 0xbf10, 0xffff, "yield%c"},
1278 {ARM_EXT_V6K
, 0xbf20, 0xffff, "wfe%c"},
1279 {ARM_EXT_V6K
, 0xbf30, 0xffff, "wfi%c"},
1280 {ARM_EXT_V6K
, 0xbf40, 0xffff, "sev%c"},
1281 {ARM_EXT_V6K
, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1283 /* ARM V6T2 instructions. */
1284 {ARM_EXT_V6T2
, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1285 {ARM_EXT_V6T2
, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1286 {ARM_EXT_V6T2
, 0xbf00, 0xff00, "it%I%X"},
1289 {ARM_EXT_V6
, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1290 {ARM_EXT_V6
, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1291 {ARM_EXT_V6
, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1292 {ARM_EXT_V6
, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1293 {ARM_EXT_V6
, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1294 {ARM_EXT_V6
, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1295 {ARM_EXT_V6
, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1296 {ARM_EXT_V6
, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1297 {ARM_EXT_V6
, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1298 {ARM_EXT_V6
, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1299 {ARM_EXT_V6
, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1301 /* ARM V5 ISA extends Thumb. */
1302 {ARM_EXT_V5T
, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
1303 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1304 {ARM_EXT_V5T
, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
1305 /* ARM V4T ISA (Thumb v1). */
1306 {ARM_EXT_V4T
, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1308 {ARM_EXT_V4T
, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1309 {ARM_EXT_V4T
, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1310 {ARM_EXT_V4T
, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1311 {ARM_EXT_V4T
, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1312 {ARM_EXT_V4T
, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1313 {ARM_EXT_V4T
, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1314 {ARM_EXT_V4T
, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1315 {ARM_EXT_V4T
, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1316 {ARM_EXT_V4T
, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1317 {ARM_EXT_V4T
, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1318 {ARM_EXT_V4T
, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1319 {ARM_EXT_V4T
, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1320 {ARM_EXT_V4T
, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1321 {ARM_EXT_V4T
, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1322 {ARM_EXT_V4T
, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1323 {ARM_EXT_V4T
, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1325 {ARM_EXT_V4T
, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1326 {ARM_EXT_V4T
, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1328 {ARM_EXT_V4T
, 0x4700, 0xFF80, "bx%c\t%S%x"},
1329 {ARM_EXT_V4T
, 0x4400, 0xFF00, "add%c\t%D, %S"},
1330 {ARM_EXT_V4T
, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1331 {ARM_EXT_V4T
, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1333 {ARM_EXT_V4T
, 0xB400, 0xFE00, "push%c\t%N"},
1334 {ARM_EXT_V4T
, 0xBC00, 0xFE00, "pop%c\t%O"},
1336 {ARM_EXT_V4T
, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1337 {ARM_EXT_V4T
, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1338 {ARM_EXT_V4T
, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1339 {ARM_EXT_V4T
, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1341 {ARM_EXT_V4T
, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1342 {ARM_EXT_V4T
, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1343 {ARM_EXT_V4T
, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1345 {ARM_EXT_V4T
, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1346 {ARM_EXT_V4T
, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1348 {ARM_EXT_V4T
, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1349 {ARM_EXT_V4T
, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1350 {ARM_EXT_V4T
, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1351 {ARM_EXT_V4T
, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1353 {ARM_EXT_V4T
, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1354 {ARM_EXT_V4T
, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1355 {ARM_EXT_V4T
, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1356 {ARM_EXT_V4T
, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1358 {ARM_EXT_V4T
, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1360 {ARM_EXT_V4T
, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1361 {ARM_EXT_V4T
, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1362 {ARM_EXT_V4T
, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1363 {ARM_EXT_V4T
, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1365 {ARM_EXT_V4T
, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1366 {ARM_EXT_V4T
, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1368 {ARM_EXT_V4T
, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1369 {ARM_EXT_V4T
, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1371 {ARM_EXT_V4T
, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1372 {ARM_EXT_V4T
, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1374 {ARM_EXT_V4T
, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1375 {ARM_EXT_V4T
, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1377 {ARM_EXT_V4T
, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1379 {ARM_EXT_V4T
, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
1380 {ARM_EXT_V4T
, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1382 {ARM_EXT_V4T
, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1384 /* The E800 .. FFFF range is unconditionally redirected to the
1385 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1386 are processed via that table. Thus, we can never encounter a
1387 bare "second half of BL/BLX(1)" instruction here. */
1388 {ARM_EXT_V1
, 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
1392 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1393 We adopt the convention that hw1 is the high 16 bits of .value and
1394 .mask, hw2 the low 16 bits.
1396 print_insn_thumb32 recognizes the following format control codes:
1400 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1401 %M print a modified 12-bit immediate (same location)
1402 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1403 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1404 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
1405 %S print a possibly-shifted Rm
1407 %L print address for a ldrd/strd instruction
1408 %a print the address of a plain load/store
1409 %w print the width and signedness of a core load/store
1410 %m print register mask for ldm/stm
1412 %E print the lsb and width fields of a bfc/bfi instruction
1413 %F print the lsb and width fields of a sbfx/ubfx instruction
1414 %b print a conditional branch offset
1415 %B print an unconditional branch offset
1416 %s print the shift field of an SSAT instruction
1417 %R print the rotation field of an SXT instruction
1418 %U print barrier type.
1419 %P print address for pli instruction.
1420 %c print the condition code
1421 %x print warning if conditional an not at end of IT block"
1422 %X print "\t; unpredictable <IT:code>" if conditional
1424 %<bitfield>d print bitfield in decimal
1425 %<bitfield>W print bitfield*4 in decimal
1426 %<bitfield>r print bitfield as an ARM register
1427 %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
1428 %<bitfield>c print bitfield as a condition code
1430 %<bitfield>'c print specified char iff bitfield is all ones
1431 %<bitfield>`c print specified char iff bitfield is all zeroes
1432 %<bitfield>?ab... select from array of values in big endian order
1434 With one exception at the bottom (done because BL and BLX(1) need
1435 to come dead last), this table was machine-sorted first in
1436 decreasing order of number of bits set in the mask, then in
1437 increasing numeric order of mask, then in increasing numeric order
1438 of opcode. This order is not the clearest for a human reader, but
1439 is guaranteed never to catch a special-case bit pattern with a more
1440 general mask, which is important, because this instruction encoding
1441 makes heavy use of special-case bit patterns. */
1442 static const struct opcode32 thumb32_opcodes
[] =
1444 /* V8 instructions. */
1445 {ARM_EXT_V8
, 0xf3af8005, 0xffffffff, "sevl%c.w"},
1446 {ARM_EXT_V8
, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
1447 {ARM_EXT_V8
, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
1448 {ARM_EXT_V8
, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
1449 {ARM_EXT_V8
, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
1450 {ARM_EXT_V8
, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1451 {ARM_EXT_V8
, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1452 {ARM_EXT_V8
, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
1453 {ARM_EXT_V8
, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1454 {ARM_EXT_V8
, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
1455 {ARM_EXT_V8
, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
1456 {ARM_EXT_V8
, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
1457 {ARM_EXT_V8
, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
1458 {ARM_EXT_V8
, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
1459 {ARM_EXT_V8
, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
1460 {ARM_EXT_V8
, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
1462 /* V7 instructions. */
1463 {ARM_EXT_V7
, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1464 {ARM_EXT_V7
, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1465 {ARM_EXT_V8
, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1466 {ARM_EXT_V8
, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
1467 {ARM_EXT_V7
, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1468 {ARM_EXT_V7
, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1469 {ARM_EXT_V7
, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1470 {ARM_EXT_DIV
, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1471 {ARM_EXT_DIV
, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1473 /* Virtualization Extension instructions. */
1474 {ARM_EXT_VIRT
, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1475 /* We skip ERET as that is SUBS pc, lr, #0. */
1477 /* MP Extension instructions. */
1478 {ARM_EXT_MP
, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
1480 /* Security extension instructions. */
1481 {ARM_EXT_SEC
, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1483 /* Instructions defined in the basic V6T2 set. */
1484 {ARM_EXT_V6T2
, 0xf3af8000, 0xffffffff, "nop%c.w"},
1485 {ARM_EXT_V6T2
, 0xf3af8001, 0xffffffff, "yield%c.w"},
1486 {ARM_EXT_V6T2
, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1487 {ARM_EXT_V6T2
, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1488 {ARM_EXT_V6T2
, 0xf3af8004, 0xffffffff, "sev%c.w"},
1489 {ARM_EXT_V6T2
, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1491 {ARM_EXT_V6T2
, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1492 {ARM_EXT_V6T2
, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1493 {ARM_EXT_V6T2
, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1494 {ARM_EXT_V6T2
, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1495 {ARM_EXT_V6T2
, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1496 {ARM_EXT_V6T2
, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1497 {ARM_EXT_V6T2
, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1498 {ARM_EXT_V6T2
, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1499 {ARM_EXT_V6T2
, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1500 {ARM_EXT_V6T2
, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1501 {ARM_EXT_V6T2
, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1502 {ARM_EXT_V6T2
, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1503 {ARM_EXT_V6T2
, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1504 {ARM_EXT_V6T2
, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1505 {ARM_EXT_V6T2
, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1506 {ARM_EXT_V6T2
, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1507 {ARM_EXT_V6T2
, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1508 {ARM_EXT_V6T2
, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1509 {ARM_EXT_V6T2
, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1510 {ARM_EXT_V6T2
, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1511 {ARM_EXT_V6T2
, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1512 {ARM_EXT_V6T2
, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1513 {ARM_EXT_V6T2
, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1514 {ARM_EXT_V6T2
, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1515 {ARM_EXT_V6T2
, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1516 {ARM_EXT_V6T2
, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1517 {ARM_EXT_V6T2
, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1518 {ARM_EXT_V6T2
, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1519 {ARM_EXT_V6T2
, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1520 {ARM_EXT_V6T2
, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1521 {ARM_EXT_V6T2
, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1522 {ARM_EXT_V6T2
, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1523 {ARM_EXT_V6T2
, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1524 {ARM_EXT_V6T2
, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1525 {ARM_EXT_V6T2
, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1526 {ARM_EXT_V6T2
, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1527 {ARM_EXT_V6T2
, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1528 {ARM_EXT_V6T2
, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1529 {ARM_EXT_V6T2
, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1530 {ARM_EXT_V6T2
, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1531 {ARM_EXT_V6T2
, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1532 {ARM_EXT_V6T2
, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1533 {ARM_EXT_V6T2
, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1534 {ARM_EXT_V6T2
, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1535 {ARM_EXT_V6T2
, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1536 {ARM_EXT_V6T2
, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1537 {ARM_EXT_V6T2
, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1538 {ARM_EXT_V6T2
, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1539 {ARM_EXT_V6T2
, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1540 {ARM_EXT_V6T2
, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1541 {ARM_EXT_V6T2
, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1542 {ARM_EXT_V6T2
, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1543 {ARM_EXT_V6T2
, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1544 {ARM_EXT_V6T2
, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1545 {ARM_EXT_V6T2
, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1546 {ARM_EXT_V6T2
, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1547 {ARM_EXT_V6T2
, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1548 {ARM_EXT_V6T2
, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1549 {ARM_EXT_V6T2
, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1550 {ARM_EXT_V6T2
, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1551 {ARM_EXT_V6T2
, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1552 {ARM_EXT_V6T2
, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1553 {ARM_EXT_V6T2
, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1554 {ARM_EXT_V6T2
, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1555 {ARM_EXT_V6T2
, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1556 {ARM_EXT_V6T2
, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1557 {ARM_EXT_V6T2
, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1558 {ARM_EXT_V6T2
, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1559 {ARM_EXT_V6T2
, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1560 {ARM_EXT_V6T2
, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1561 {ARM_EXT_V6T2
, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1562 {ARM_EXT_V6T2
, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1563 {ARM_EXT_V6T2
, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1564 {ARM_EXT_V6T2
, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1565 {ARM_EXT_V6T2
, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1566 {ARM_EXT_V6T2
, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1567 {ARM_EXT_V6T2
, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1568 {ARM_EXT_V6T2
, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1569 {ARM_EXT_V6T2
, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1570 {ARM_EXT_V6T2
, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1571 {ARM_EXT_V6T2
, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1572 {ARM_EXT_V6T2
, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1573 {ARM_EXT_V6T2
, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1574 {ARM_EXT_V6T2
, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1575 {ARM_EXT_V6T2
, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1576 {ARM_EXT_V6T2
, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1577 {ARM_EXT_V6T2
, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1578 {ARM_EXT_V6T2
, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1579 {ARM_EXT_V6T2
, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1580 {ARM_EXT_V6T2
, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1581 {ARM_EXT_V6T2
, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1582 {ARM_EXT_V6T2
, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1583 {ARM_EXT_V6T2
, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1584 {ARM_EXT_V6T2
, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1585 {ARM_EXT_V6T2
, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1586 {ARM_EXT_V6T2
, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1587 {ARM_EXT_V6T2
, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1588 {ARM_EXT_V6T2
, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1589 {ARM_EXT_V6T2
, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1590 {ARM_EXT_V6T2
, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1591 {ARM_EXT_V6T2
, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1592 {ARM_EXT_V6T2
, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1593 {ARM_EXT_V6T2
, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1594 {ARM_EXT_V6T2
, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1595 {ARM_EXT_V6T2
, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1596 {ARM_EXT_V6T2
, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1597 {ARM_EXT_V6T2
, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1598 {ARM_EXT_V6T2
, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1599 {ARM_EXT_V6T2
, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1600 {ARM_EXT_V6T2
, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1601 {ARM_EXT_V6T2
, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1602 {ARM_EXT_V6T2
, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1603 {ARM_EXT_V6T2
, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1604 {ARM_EXT_V6T2
, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1605 {ARM_EXT_V6T2
, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1606 {ARM_EXT_V6T2
, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1607 {ARM_EXT_V6T2
, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1608 {ARM_EXT_V6T2
, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1609 {ARM_EXT_V6T2
, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1610 {ARM_EXT_V6T2
, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1611 {ARM_EXT_V6T2
, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1612 {ARM_EXT_V6T2
, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1613 {ARM_EXT_V6T2
, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1614 {ARM_EXT_V6T2
, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1615 {ARM_EXT_V6T2
, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1616 {ARM_EXT_V6T2
, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1617 {ARM_EXT_V6T2
, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1618 {ARM_EXT_V6T2
, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1619 {ARM_EXT_V6T2
, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1620 {ARM_EXT_V6T2
, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1621 {ARM_EXT_V6T2
, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1622 {ARM_EXT_V6T2
, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1623 {ARM_EXT_V6T2
, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1624 {ARM_EXT_V6T2
, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1625 {ARM_EXT_V6T2
, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1626 {ARM_EXT_V6T2
, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1627 {ARM_EXT_V6T2
, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1628 {ARM_EXT_V6T2
, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1629 {ARM_EXT_V6T2
, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1630 {ARM_EXT_V6T2
, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1631 {ARM_EXT_V6T2
, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1632 {ARM_EXT_V6T2
, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1633 {ARM_EXT_V6T2
, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1634 {ARM_EXT_V6T2
, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1635 {ARM_EXT_V6T2
, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1636 {ARM_EXT_V6T2
, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1637 {ARM_EXT_V6T2
, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1638 {ARM_EXT_V6T2
, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1639 {ARM_EXT_V6T2
, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1640 {ARM_EXT_V6T2
, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1641 {ARM_EXT_V6T2
, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1642 {ARM_EXT_V6T2
, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1643 {ARM_EXT_V6T2
, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1644 {ARM_EXT_V6T2
, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1645 {ARM_EXT_V6T2
, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1646 {ARM_EXT_V6T2
, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1647 {ARM_EXT_V6T2
, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1648 {ARM_EXT_V6T2
, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1649 {ARM_EXT_V6T2
, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1650 {ARM_EXT_V6T2
, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1651 {ARM_EXT_V6T2
, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1652 {ARM_EXT_V6T2
, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1653 {ARM_EXT_V6T2
, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1654 {ARM_EXT_V6T2
, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1655 {ARM_EXT_V6T2
, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1656 {ARM_EXT_V6T2
, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1657 {ARM_EXT_V6T2
, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1658 {ARM_EXT_V6T2
, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1659 {ARM_EXT_V6T2
, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1660 {ARM_EXT_V6T2
, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1661 {ARM_EXT_V6T2
, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1663 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1664 {ARM_EXT_V6T2
, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1665 {ARM_EXT_V6T2
, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1666 {ARM_EXT_V6T2
, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1667 {ARM_EXT_V6T2
, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1669 /* These have been 32-bit since the invention of Thumb. */
1670 {ARM_EXT_V4T
, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1671 {ARM_EXT_V4T
, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1674 {ARM_EXT_V1
, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
1678 static const char *const arm_conditional
[] =
1679 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1680 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1682 static const char *const arm_fp_const
[] =
1683 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1685 static const char *const arm_shift
[] =
1686 {"lsl", "lsr", "asr", "ror"};
1691 const char *description
;
1692 const char *reg_names
[16];
1696 static const arm_regname regnames
[] =
1698 { "raw" , "Select raw register names",
1699 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1700 { "gcc", "Select register names used by GCC",
1701 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1702 { "std", "Select register names used in ARM's ISA documentation",
1703 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1704 { "apcs", "Select register names used in the APCS",
1705 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1706 { "atpcs", "Select register names used in the ATPCS",
1707 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1708 { "special-atpcs", "Select special register names used in the ATPCS",
1709 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1712 static const char *const iwmmxt_wwnames
[] =
1713 {"b", "h", "w", "d"};
1715 static const char *const iwmmxt_wwssnames
[] =
1716 {"b", "bus", "bc", "bss",
1717 "h", "hus", "hc", "hss",
1718 "w", "wus", "wc", "wss",
1719 "d", "dus", "dc", "dss"
1722 static const char *const iwmmxt_regnames
[] =
1723 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1724 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1727 static const char *const iwmmxt_cregnames
[] =
1728 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1729 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1732 /* Default to GCC register name set. */
1733 static unsigned int regname_selected
= 1;
1735 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1736 #define arm_regnames regnames[regname_selected].reg_names
1738 static bfd_boolean force_thumb
= FALSE
;
1740 /* Current IT instruction state. This contains the same state as the IT
1741 bits in the CPSR. */
1742 static unsigned int ifthen_state
;
1743 /* IT state for the next instruction. */
1744 static unsigned int ifthen_next_state
;
1745 /* The address of the insn for which the IT state is valid. */
1746 static bfd_vma ifthen_address
;
1747 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1748 /* Indicates that the current Conditional state is unconditional or outside
1750 #define COND_UNCOND 16
1755 get_arm_regname_num_options (void)
1757 return NUM_ARM_REGNAMES
;
1761 set_arm_regname_option (int option
)
1763 int old
= regname_selected
;
1764 regname_selected
= option
;
1769 get_arm_regnames (int option
,
1770 const char **setname
,
1771 const char **setdescription
,
1772 const char *const **register_names
)
1774 *setname
= regnames
[option
].name
;
1775 *setdescription
= regnames
[option
].description
;
1776 *register_names
= regnames
[option
].reg_names
;
1780 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1781 Returns pointer to following character of the format string and
1782 fills in *VALUEP and *WIDTHP with the extracted value and number of
1783 bits extracted. WIDTHP can be NULL. */
1786 arm_decode_bitfield (const char *ptr
,
1788 unsigned long *valuep
,
1791 unsigned long value
= 0;
1799 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
1800 start
= start
* 10 + *ptr
- '0';
1802 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
1803 end
= end
* 10 + *ptr
- '0';
1809 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
1812 while (*ptr
++ == ',');
1820 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
1821 bfd_boolean print_shift
)
1823 func (stream
, "%s", arm_regnames
[given
& 0xf]);
1825 if ((given
& 0xff0) != 0)
1827 if ((given
& 0x10) == 0)
1829 int amount
= (given
& 0xf80) >> 7;
1830 int shift
= (given
& 0x60) >> 5;
1836 func (stream
, ", rrx");
1844 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
1846 func (stream
, ", #%d", amount
);
1848 else if ((given
& 0x80) == 0x80)
1849 func (stream
, "\t; <illegal shifter operand>");
1850 else if (print_shift
)
1851 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
1852 arm_regnames
[(given
& 0xf00) >> 8]);
1854 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
1863 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
1864 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
1865 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
1866 #define PRE_BIT_SET (given & (1 << P_BIT))
1868 /* Print one coprocessor instruction on INFO->STREAM.
1869 Return TRUE if the instuction matched, FALSE if this is not a
1870 recognised coprocessor instruction. */
1873 print_insn_coprocessor (bfd_vma pc
,
1874 struct disassemble_info
*info
,
1878 const struct opcode32
*insn
;
1879 void *stream
= info
->stream
;
1880 fprintf_ftype func
= info
->fprintf_func
;
1882 unsigned long value
= 0;
1883 struct arm_private_data
*private_data
= info
->private_data
;
1884 unsigned long allowed_arches
= private_data
->features
.coproc
;
1887 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
1889 unsigned long u_reg
= 16;
1890 bfd_boolean is_unpredictable
= FALSE
;
1891 signed long value_in_comment
= 0;
1894 if (insn
->arch
== 0)
1895 switch (insn
->value
)
1897 case SENTINEL_IWMMXT_START
:
1898 if (info
->mach
!= bfd_mach_arm_XScale
1899 && info
->mach
!= bfd_mach_arm_iWMMXt
1900 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
1903 while (insn
->arch
!= 0 && insn
->value
!= SENTINEL_IWMMXT_END
);
1906 case SENTINEL_IWMMXT_END
:
1909 case SENTINEL_GENERIC_START
:
1910 allowed_arches
= private_data
->features
.core
;
1918 value
= insn
->value
;
1921 /* The high 4 bits are 0xe for Arm conditional instructions, and
1922 0xe for arm unconditional instructions. The rest of the
1923 encoding is the same. */
1925 value
|= 0xe0000000;
1933 /* Only match unconditional instuctions against unconditional
1935 if ((given
& 0xf0000000) == 0xf0000000)
1942 cond
= (given
>> 28) & 0xf;
1948 if ((given
& mask
) != value
)
1951 if ((insn
->arch
& allowed_arches
) == 0)
1954 for (c
= insn
->assembler
; *c
; c
++)
1961 func (stream
, "%%");
1966 int rn
= (given
>> 16) & 0xf;
1967 bfd_vma offset
= given
& 0xff;
1969 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
1971 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
1973 /* Not unindexed. The offset is scaled. */
1974 offset
= offset
* 4;
1975 if (NEGATIVE_BIT_SET
)
1978 value_in_comment
= offset
;
1984 func (stream
, ", #%d]%s",
1986 WRITEBACK_BIT_SET
? "!" : "");
1987 else if (NEGATIVE_BIT_SET
)
1988 func (stream
, ", #-0]");
1996 if (WRITEBACK_BIT_SET
)
1999 func (stream
, ", #%d", (int) offset
);
2000 else if (NEGATIVE_BIT_SET
)
2001 func (stream
, ", #-0");
2005 func (stream
, ", {%s%d}",
2006 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
2008 value_in_comment
= offset
;
2011 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
2013 func (stream
, "\t; ");
2014 /* For unaligned PCs, apply off-by-alignment
2016 info
->print_address_func (offset
+ pc
2017 + info
->bytes_per_chunk
* 2
2026 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
2027 int offset
= (given
>> 1) & 0x3f;
2030 func (stream
, "{d%d}", regno
);
2031 else if (regno
+ offset
> 32)
2032 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
2034 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
2039 if (cond
!= COND_UNCOND
)
2040 is_unpredictable
= TRUE
;
2044 func (stream
, "%s", arm_conditional
[cond
]);
2048 /* Print a Cirrus/DSP shift immediate. */
2049 /* Immediates are 7bit signed ints with bits 0..3 in
2050 bits 0..3 of opcode and bits 4..6 in bits 5..7
2055 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
2057 /* Is ``imm'' a negative number? */
2061 func (stream
, "%d", imm
);
2067 switch (given
& 0x00408000)
2084 switch (given
& 0x00080080)
2096 func (stream
, _("<illegal precision>"));
2102 switch (given
& 0x00408000)
2120 switch (given
& 0x60)
2136 case '0': case '1': case '2': case '3': case '4':
2137 case '5': case '6': case '7': case '8': case '9':
2141 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
2147 is_unpredictable
= TRUE
;
2152 /* Eat the 'u' character. */
2156 is_unpredictable
= TRUE
;
2159 func (stream
, "%s", arm_regnames
[value
]);
2162 func (stream
, "d%ld", value
);
2166 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
2168 func (stream
, "q%ld", value
>> 1);
2171 func (stream
, "%ld", value
);
2172 value_in_comment
= value
;
2176 int from
= (given
& (1 << 7)) ? 32 : 16;
2177 func (stream
, "%ld", from
- value
);
2183 func (stream
, "#%s", arm_fp_const
[value
& 7]);
2185 func (stream
, "f%ld", value
);
2190 func (stream
, "%s", iwmmxt_wwnames
[value
]);
2192 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
2196 func (stream
, "%s", iwmmxt_regnames
[value
]);
2199 func (stream
, "%s", iwmmxt_cregnames
[value
]);
2203 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
2210 func (stream
, "eq");
2214 func (stream
, "vs");
2218 func (stream
, "ge");
2222 func (stream
, "gt");
2226 func (stream
, "??");
2234 func (stream
, "%c", *c
);
2238 if (value
== ((1ul << width
) - 1))
2239 func (stream
, "%c", *c
);
2242 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
2253 int single
= *c
++ == 'y';
2258 case '4': /* Sm pair */
2259 case '0': /* Sm, Dm */
2260 regno
= given
& 0x0000000f;
2264 regno
+= (given
>> 5) & 1;
2267 regno
+= ((given
>> 5) & 1) << 4;
2270 case '1': /* Sd, Dd */
2271 regno
= (given
>> 12) & 0x0000000f;
2275 regno
+= (given
>> 22) & 1;
2278 regno
+= ((given
>> 22) & 1) << 4;
2281 case '2': /* Sn, Dn */
2282 regno
= (given
>> 16) & 0x0000000f;
2286 regno
+= (given
>> 7) & 1;
2289 regno
+= ((given
>> 7) & 1) << 4;
2292 case '3': /* List */
2294 regno
= (given
>> 12) & 0x0000000f;
2298 regno
+= (given
>> 22) & 1;
2301 regno
+= ((given
>> 22) & 1) << 4;
2308 func (stream
, "%c%d", single
? 's' : 'd', regno
);
2312 int count
= given
& 0xff;
2319 func (stream
, "-%c%d",
2327 func (stream
, ", %c%d", single
? 's' : 'd',
2333 switch (given
& 0x00400100)
2335 case 0x00000000: func (stream
, "b"); break;
2336 case 0x00400000: func (stream
, "h"); break;
2337 case 0x00000100: func (stream
, "w"); break;
2338 case 0x00400100: func (stream
, "d"); break;
2346 /* given (20, 23) | given (0, 3) */
2347 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
2348 func (stream
, "%d", (int) value
);
2353 /* This is like the 'A' operator, except that if
2354 the width field "M" is zero, then the offset is
2355 *not* multiplied by four. */
2357 int offset
= given
& 0xff;
2358 int multiplier
= (given
& 0x00000100) ? 4 : 1;
2360 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
2364 value_in_comment
= offset
* multiplier
;
2365 if (NEGATIVE_BIT_SET
)
2366 value_in_comment
= - value_in_comment
;
2372 func (stream
, ", #%s%d]%s",
2373 NEGATIVE_BIT_SET
? "-" : "",
2374 offset
* multiplier
,
2375 WRITEBACK_BIT_SET
? "!" : "");
2377 func (stream
, "], #%s%d",
2378 NEGATIVE_BIT_SET
? "-" : "",
2379 offset
* multiplier
);
2388 int imm4
= (given
>> 4) & 0xf;
2389 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
2390 int ubit
= ! NEGATIVE_BIT_SET
;
2391 const char *rm
= arm_regnames
[given
& 0xf];
2392 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
2398 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
2400 func (stream
, ", lsl #%d", imm4
);
2407 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
2409 func (stream
, ", lsl #%d", imm4
);
2411 if (puw_bits
== 5 || puw_bits
== 7)
2416 func (stream
, "INVALID");
2424 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
2425 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
2435 func (stream
, "%c", *c
);
2438 if (value_in_comment
> 32 || value_in_comment
< -16)
2439 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
2441 if (is_unpredictable
)
2442 func (stream
, UNPREDICTABLE_INSTRUCTION
);
2449 /* Decodes and prints ARM addressing modes. Returns the offset
2450 used in the address, if any, if it is worthwhile printing the
2451 offset as a hexadecimal value in a comment at the end of the
2452 line of disassembly. */
2455 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
2457 void *stream
= info
->stream
;
2458 fprintf_ftype func
= info
->fprintf_func
;
2461 if (((given
& 0x000f0000) == 0x000f0000)
2462 && ((given
& 0x02000000) == 0))
2464 offset
= given
& 0xfff;
2466 func (stream
, "[pc");
2470 /* Pre-indexed. Elide offset of positive zero when
2472 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
2473 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
2475 if (NEGATIVE_BIT_SET
)
2480 /* Cope with the possibility of write-back
2481 being used. Probably a very dangerous thing
2482 for the programmer to do, but who are we to
2484 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
2486 else /* Post indexed. */
2488 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
2490 /* Ie ignore the offset. */
2494 func (stream
, "\t; ");
2495 info
->print_address_func (offset
, info
);
2500 func (stream
, "[%s",
2501 arm_regnames
[(given
>> 16) & 0xf]);
2505 if ((given
& 0x02000000) == 0)
2507 /* Elide offset of positive zero when non-writeback. */
2508 offset
= given
& 0xfff;
2509 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
2510 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
2514 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
2515 arm_decode_shift (given
, func
, stream
, TRUE
);
2518 func (stream
, "]%s",
2519 WRITEBACK_BIT_SET
? "!" : "");
2523 if ((given
& 0x02000000) == 0)
2525 /* Always show offset. */
2526 offset
= given
& 0xfff;
2527 func (stream
, "], #%s%d",
2528 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
2532 func (stream
, "], %s",
2533 NEGATIVE_BIT_SET
? "-" : "");
2534 arm_decode_shift (given
, func
, stream
, TRUE
);
2539 return (signed long) offset
;
2542 /* Print one neon instruction on INFO->STREAM.
2543 Return TRUE if the instuction matched, FALSE if this is not a
2544 recognised neon instruction. */
2547 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
2549 const struct opcode32
*insn
;
2550 void *stream
= info
->stream
;
2551 fprintf_ftype func
= info
->fprintf_func
;
2555 if ((given
& 0xef000000) == 0xef000000)
2557 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2558 unsigned long bit28
= given
& (1 << 28);
2560 given
&= 0x00ffffff;
2562 given
|= 0xf3000000;
2564 given
|= 0xf2000000;
2566 else if ((given
& 0xff000000) == 0xf9000000)
2567 given
^= 0xf9000000 ^ 0xf4000000;
2572 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
2574 if ((given
& insn
->mask
) == insn
->value
)
2576 signed long value_in_comment
= 0;
2577 bfd_boolean is_unpredictable
= FALSE
;
2580 for (c
= insn
->assembler
; *c
; c
++)
2587 func (stream
, "%%");
2591 if (thumb
&& ifthen_state
)
2592 is_unpredictable
= TRUE
;
2596 if (thumb
&& ifthen_state
)
2597 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
2602 static const unsigned char enc
[16] =
2604 0x4, 0x14, /* st4 0,1 */
2616 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
2617 int rn
= ((given
>> 16) & 0xf);
2618 int rm
= ((given
>> 0) & 0xf);
2619 int align
= ((given
>> 4) & 0x3);
2620 int type
= ((given
>> 8) & 0xf);
2621 int n
= enc
[type
] & 0xf;
2622 int stride
= (enc
[type
] >> 4) + 1;
2627 for (ix
= 0; ix
!= n
; ix
++)
2628 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
2630 func (stream
, "d%d", rd
);
2632 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
2633 func (stream
, "}, [%s", arm_regnames
[rn
]);
2635 func (stream
, " :%d", 32 << align
);
2640 func (stream
, ", %s", arm_regnames
[rm
]);
2646 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
2647 int rn
= ((given
>> 16) & 0xf);
2648 int rm
= ((given
>> 0) & 0xf);
2649 int idx_align
= ((given
>> 4) & 0xf);
2651 int size
= ((given
>> 10) & 0x3);
2652 int idx
= idx_align
>> (size
+ 1);
2653 int length
= ((given
>> 8) & 3) + 1;
2657 if (length
> 1 && size
> 0)
2658 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
2664 int amask
= (1 << size
) - 1;
2665 if ((idx_align
& (1 << size
)) != 0)
2669 if ((idx_align
& amask
) == amask
)
2671 else if ((idx_align
& amask
) != 0)
2678 if (size
== 2 && (idx_align
& 2) != 0)
2680 align
= (idx_align
& 1) ? 16 << size
: 0;
2684 if ((size
== 2 && (idx_align
& 3) != 0)
2685 || (idx_align
& 1) != 0)
2692 if ((idx_align
& 3) == 3)
2694 align
= (idx_align
& 3) * 64;
2697 align
= (idx_align
& 1) ? 32 << size
: 0;
2705 for (i
= 0; i
< length
; i
++)
2706 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
2707 rd
+ i
* stride
, idx
);
2708 func (stream
, "}, [%s", arm_regnames
[rn
]);
2710 func (stream
, " :%d", align
);
2715 func (stream
, ", %s", arm_regnames
[rm
]);
2721 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
2722 int rn
= ((given
>> 16) & 0xf);
2723 int rm
= ((given
>> 0) & 0xf);
2724 int align
= ((given
>> 4) & 0x1);
2725 int size
= ((given
>> 6) & 0x3);
2726 int type
= ((given
>> 8) & 0x3);
2728 int stride
= ((given
>> 5) & 0x1);
2731 if (stride
&& (n
== 1))
2738 for (ix
= 0; ix
!= n
; ix
++)
2739 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
2741 func (stream
, "d%d[]", rd
);
2743 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
2744 func (stream
, "}, [%s", arm_regnames
[rn
]);
2747 align
= (8 * (type
+ 1)) << size
;
2749 align
= (size
> 1) ? align
>> 1 : align
;
2750 if (type
== 2 || (type
== 0 && !size
))
2751 func (stream
, " :<bad align %d>", align
);
2753 func (stream
, " :%d", align
);
2759 func (stream
, ", %s", arm_regnames
[rm
]);
2765 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
2766 int size
= (given
>> 20) & 3;
2767 int reg
= raw_reg
& ((4 << size
) - 1);
2768 int ix
= raw_reg
>> size
>> 2;
2770 func (stream
, "d%d[%d]", reg
, ix
);
2775 /* Neon encoded constant for mov, mvn, vorr, vbic. */
2778 int cmode
= (given
>> 8) & 0xf;
2779 int op
= (given
>> 5) & 0x1;
2780 unsigned long value
= 0, hival
= 0;
2785 bits
|= ((given
>> 24) & 1) << 7;
2786 bits
|= ((given
>> 16) & 7) << 4;
2787 bits
|= ((given
>> 0) & 15) << 0;
2791 shift
= (cmode
>> 1) & 3;
2792 value
= (unsigned long) bits
<< (8 * shift
);
2795 else if (cmode
< 12)
2797 shift
= (cmode
>> 1) & 1;
2798 value
= (unsigned long) bits
<< (8 * shift
);
2801 else if (cmode
< 14)
2803 shift
= (cmode
& 1) + 1;
2804 value
= (unsigned long) bits
<< (8 * shift
);
2805 value
|= (1ul << (8 * shift
)) - 1;
2808 else if (cmode
== 14)
2812 /* Bit replication into bytes. */
2818 for (ix
= 7; ix
>= 0; ix
--)
2820 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
2822 value
= (value
<< 8) | mask
;
2824 hival
= (hival
<< 8) | mask
;
2830 /* Byte replication. */
2831 value
= (unsigned long) bits
;
2837 /* Floating point encoding. */
2840 value
= (unsigned long) (bits
& 0x7f) << 19;
2841 value
|= (unsigned long) (bits
& 0x80) << 24;
2842 tmp
= bits
& 0x40 ? 0x3c : 0x40;
2843 value
|= (unsigned long) tmp
<< 24;
2849 func (stream
, "<illegal constant %.8x:%x:%x>",
2857 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
2861 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
2867 unsigned char valbytes
[4];
2870 /* Do this a byte at a time so we don't have to
2871 worry about the host's endianness. */
2872 valbytes
[0] = value
& 0xff;
2873 valbytes
[1] = (value
>> 8) & 0xff;
2874 valbytes
[2] = (value
>> 16) & 0xff;
2875 valbytes
[3] = (value
>> 24) & 0xff;
2877 floatformat_to_double
2878 (& floatformat_ieee_single_little
, valbytes
,
2881 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
2885 func (stream
, "#%ld\t; 0x%.8lx",
2886 (long) (((value
& 0x80000000L
) != 0)
2887 ? value
| ~0xffffffffL
: value
),
2892 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
2903 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
2904 int num
= (given
>> 8) & 0x3;
2907 func (stream
, "{d%d}", regno
);
2908 else if (num
+ regno
>= 32)
2909 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
2911 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
2916 case '0': case '1': case '2': case '3': case '4':
2917 case '5': case '6': case '7': case '8': case '9':
2920 unsigned long value
;
2922 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
2927 func (stream
, "%s", arm_regnames
[value
]);
2930 func (stream
, "%ld", value
);
2931 value_in_comment
= value
;
2934 func (stream
, "%ld", (1ul << width
) - value
);
2940 /* Various width encodings. */
2942 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
2947 if (*c
>= '0' && *c
<= '9')
2949 else if (*c
>= 'a' && *c
<= 'f')
2950 limit
= *c
- 'a' + 10;
2956 if (value
< low
|| value
> high
)
2957 func (stream
, "<illegal width %d>", base
<< value
);
2959 func (stream
, "%d", base
<< value
);
2963 if (given
& (1 << 6))
2967 func (stream
, "d%ld", value
);
2972 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
2974 func (stream
, "q%ld", value
>> 1);
2980 func (stream
, "%c", *c
);
2984 if (value
== ((1ul << width
) - 1))
2985 func (stream
, "%c", *c
);
2988 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
3002 func (stream
, "%c", *c
);
3005 if (value_in_comment
> 32 || value_in_comment
< -16)
3006 func (stream
, "\t; 0x%lx", value_in_comment
);
3008 if (is_unpredictable
)
3009 func (stream
, UNPREDICTABLE_INSTRUCTION
);
3017 /* Return the name of a v7A special register. */
3020 banked_regname (unsigned reg
)
3024 case 15: return "CPSR";
3025 case 32: return "R8_usr";
3026 case 33: return "R9_usr";
3027 case 34: return "R10_usr";
3028 case 35: return "R11_usr";
3029 case 36: return "R12_usr";
3030 case 37: return "SP_usr";
3031 case 38: return "LR_usr";
3032 case 40: return "R8_fiq";
3033 case 41: return "R9_fiq";
3034 case 42: return "R10_fiq";
3035 case 43: return "R11_fiq";
3036 case 44: return "R12_fiq";
3037 case 45: return "SP_fiq";
3038 case 46: return "LR_fiq";
3039 case 48: return "LR_irq";
3040 case 49: return "SP_irq";
3041 case 50: return "LR_svc";
3042 case 51: return "SP_svc";
3043 case 52: return "LR_abt";
3044 case 53: return "SP_abt";
3045 case 54: return "LR_und";
3046 case 55: return "SP_und";
3047 case 60: return "LR_mon";
3048 case 61: return "SP_mon";
3049 case 62: return "ELR_hyp";
3050 case 63: return "SP_hyp";
3051 case 79: return "SPSR";
3052 case 110: return "SPSR_fiq";
3053 case 112: return "SPSR_irq";
3054 case 114: return "SPSR_svc";
3055 case 116: return "SPSR_abt";
3056 case 118: return "SPSR_und";
3057 case 124: return "SPSR_mon";
3058 case 126: return "SPSR_hyp";
3059 default: return NULL
;
3063 /* Return the name of the DMB/DSB option. */
3065 data_barrier_option (unsigned option
)
3067 switch (option
& 0xf)
3069 case 0xf: return "sy";
3070 case 0xe: return "st";
3071 case 0xd: return "ld";
3072 case 0xb: return "ish";
3073 case 0xa: return "ishst";
3074 case 0x9: return "ishld";
3075 case 0x7: return "un";
3076 case 0x6: return "unst";
3077 case 0x5: return "nshld";
3078 case 0x3: return "osh";
3079 case 0x2: return "oshst";
3080 case 0x1: return "oshld";
3081 default: return NULL
;
3085 /* Print one ARM instruction from PC on INFO->STREAM. */
3088 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
3090 const struct opcode32
*insn
;
3091 void *stream
= info
->stream
;
3092 fprintf_ftype func
= info
->fprintf_func
;
3093 struct arm_private_data
*private_data
= info
->private_data
;
3095 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
3098 if (print_insn_neon (info
, given
, FALSE
))
3101 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
3103 if ((given
& insn
->mask
) != insn
->value
)
3106 if ((insn
->arch
& private_data
->features
.core
) == 0)
3109 /* Special case: an instruction with all bits set in the condition field
3110 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3111 or by the catchall at the end of the table. */
3112 if ((given
& 0xF0000000) != 0xF0000000
3113 || (insn
->mask
& 0xF0000000) == 0xF0000000
3114 || (insn
->mask
== 0 && insn
->value
== 0))
3116 unsigned long u_reg
= 16;
3117 unsigned long U_reg
= 16;
3118 bfd_boolean is_unpredictable
= FALSE
;
3119 signed long value_in_comment
= 0;
3122 for (c
= insn
->assembler
; *c
; c
++)
3126 bfd_boolean allow_unpredictable
= FALSE
;
3131 func (stream
, "%%");
3135 value_in_comment
= print_arm_address (pc
, info
, given
);
3139 /* Set P address bit and use normal address
3140 printing routine. */
3141 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
3145 allow_unpredictable
= TRUE
;
3147 if ((given
& 0x004f0000) == 0x004f0000)
3149 /* PC relative with immediate offset. */
3150 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
3154 /* Elide positive zero offset. */
3155 if (offset
|| NEGATIVE_BIT_SET
)
3156 func (stream
, "[pc, #%s%d]\t; ",
3157 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
3159 func (stream
, "[pc]\t; ");
3160 if (NEGATIVE_BIT_SET
)
3162 info
->print_address_func (offset
+ pc
+ 8, info
);
3166 /* Always show the offset. */
3167 func (stream
, "[pc], #%s%d",
3168 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
3169 if (! allow_unpredictable
)
3170 is_unpredictable
= TRUE
;
3175 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
3177 func (stream
, "[%s",
3178 arm_regnames
[(given
>> 16) & 0xf]);
3182 if (IMMEDIATE_BIT_SET
)
3184 /* Elide offset for non-writeback
3186 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
3188 func (stream
, ", #%s%d",
3189 NEGATIVE_BIT_SET
? "-" : "", offset
);
3191 if (NEGATIVE_BIT_SET
)
3194 value_in_comment
= offset
;
3198 /* Register Offset or Register Pre-Indexed. */
3199 func (stream
, ", %s%s",
3200 NEGATIVE_BIT_SET
? "-" : "",
3201 arm_regnames
[given
& 0xf]);
3203 /* Writing back to the register that is the source/
3204 destination of the load/store is unpredictable. */
3205 if (! allow_unpredictable
3206 && WRITEBACK_BIT_SET
3207 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
3208 is_unpredictable
= TRUE
;
3211 func (stream
, "]%s",
3212 WRITEBACK_BIT_SET
? "!" : "");
3216 if (IMMEDIATE_BIT_SET
)
3218 /* Immediate Post-indexed. */
3219 /* PR 10924: Offset must be printed, even if it is zero. */
3220 func (stream
, "], #%s%d",
3221 NEGATIVE_BIT_SET
? "-" : "", offset
);
3222 if (NEGATIVE_BIT_SET
)
3224 value_in_comment
= offset
;
3228 /* Register Post-indexed. */
3229 func (stream
, "], %s%s",
3230 NEGATIVE_BIT_SET
? "-" : "",
3231 arm_regnames
[given
& 0xf]);
3233 /* Writing back to the register that is the source/
3234 destination of the load/store is unpredictable. */
3235 if (! allow_unpredictable
3236 && (given
& 0xf) == ((given
>> 12) & 0xf))
3237 is_unpredictable
= TRUE
;
3240 if (! allow_unpredictable
)
3242 /* Writeback is automatically implied by post- addressing.
3243 Setting the W bit is unnecessary and ARM specify it as
3244 being unpredictable. */
3245 if (WRITEBACK_BIT_SET
3246 /* Specifying the PC register as the post-indexed
3247 registers is also unpredictable. */
3248 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
3249 is_unpredictable
= TRUE
;
3257 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
3258 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
3263 if (((given
>> 28) & 0xf) != 0xe)
3265 arm_conditional
[(given
>> 28) & 0xf]);
3274 for (reg
= 0; reg
< 16; reg
++)
3275 if ((given
& (1 << reg
)) != 0)
3278 func (stream
, ", ");
3280 func (stream
, "%s", arm_regnames
[reg
]);
3284 is_unpredictable
= TRUE
;
3289 arm_decode_shift (given
, func
, stream
, FALSE
);
3293 if ((given
& 0x02000000) != 0)
3295 unsigned int rotate
= (given
& 0xf00) >> 7;
3296 unsigned int immed
= (given
& 0xff);
3299 a
= (((immed
<< (32 - rotate
))
3300 | (immed
>> rotate
)) & 0xffffffff);
3301 /* If there is another encoding with smaller rotate,
3302 the rotate should be specified directly. */
3303 for (i
= 0; i
< 32; i
+= 2)
3304 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
3308 func (stream
, "#%d, %d", immed
, rotate
);
3310 func (stream
, "#%d", a
);
3311 value_in_comment
= a
;
3314 arm_decode_shift (given
, func
, stream
, TRUE
);
3318 if ((given
& 0x0000f000) == 0x0000f000)
3320 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3321 mechanism for setting PSR flag bits. They are
3322 obsolete in V6 onwards. */
3323 if ((private_data
->features
.core
& ARM_EXT_V6
) == 0)
3329 if ((given
& 0x01200000) == 0x00200000)
3335 int offset
= given
& 0xff;
3337 value_in_comment
= offset
* 4;
3338 if (NEGATIVE_BIT_SET
)
3339 value_in_comment
= - value_in_comment
;
3341 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
3346 func (stream
, ", #%d]%s",
3347 (int) value_in_comment
,
3348 WRITEBACK_BIT_SET
? "!" : "");
3356 if (WRITEBACK_BIT_SET
)
3359 func (stream
, ", #%d", (int) value_in_comment
);
3363 func (stream
, ", {%d}", (int) offset
);
3364 value_in_comment
= offset
;
3371 /* Print ARM V5 BLX(1) address: pc+25 bits. */
3376 if (! NEGATIVE_BIT_SET
)
3377 /* Is signed, hi bits should be ones. */
3378 offset
= (-1) ^ 0x00ffffff;
3380 /* Offset is (SignExtend(offset field)<<2). */
3381 offset
+= given
& 0x00ffffff;
3383 address
= offset
+ pc
+ 8;
3385 if (given
& 0x01000000)
3386 /* H bit allows addressing to 2-byte boundaries. */
3389 info
->print_address_func (address
, info
);
3394 if ((given
& 0x02000200) == 0x200)
3397 unsigned sysm
= (given
& 0x004f0000) >> 16;
3399 sysm
|= (given
& 0x300) >> 4;
3400 name
= banked_regname (sysm
);
3403 func (stream
, "%s", name
);
3405 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
3409 func (stream
, "%cPSR_",
3410 (given
& 0x00400000) ? 'S' : 'C');
3411 if (given
& 0x80000)
3413 if (given
& 0x40000)
3415 if (given
& 0x20000)
3417 if (given
& 0x10000)
3423 if ((given
& 0xf0) == 0x60)
3425 switch (given
& 0xf)
3427 case 0xf: func (stream
, "sy"); break;
3429 func (stream
, "#%d", (int) given
& 0xf);
3435 const char * opt
= data_barrier_option (given
& 0xf);
3437 func (stream
, "%s", opt
);
3439 func (stream
, "#%d", (int) given
& 0xf);
3443 case '0': case '1': case '2': case '3': case '4':
3444 case '5': case '6': case '7': case '8': case '9':
3447 unsigned long value
;
3449 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
3455 is_unpredictable
= TRUE
;
3459 /* We want register + 1 when decoding T. */
3465 /* Eat the 'u' character. */
3469 is_unpredictable
= TRUE
;
3474 /* Eat the 'U' character. */
3478 is_unpredictable
= TRUE
;
3481 func (stream
, "%s", arm_regnames
[value
]);
3484 func (stream
, "%ld", value
);
3485 value_in_comment
= value
;
3488 func (stream
, "%ld", value
* 8);
3489 value_in_comment
= value
* 8;
3492 func (stream
, "%ld", value
+ 1);
3493 value_in_comment
= value
+ 1;
3496 func (stream
, "0x%08lx", value
);
3498 /* Some SWI instructions have special
3500 if ((given
& 0x0fffffff) == 0x0FF00000)
3501 func (stream
, "\t; IMB");
3502 else if ((given
& 0x0fffffff) == 0x0FF00001)
3503 func (stream
, "\t; IMBRange");
3506 func (stream
, "%01lx", value
& 0xf);
3507 value_in_comment
= value
;
3512 func (stream
, "%c", *c
);
3516 if (value
== ((1ul << width
) - 1))
3517 func (stream
, "%c", *c
);
3520 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
3532 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
3533 func (stream
, "%d", imm
);
3534 value_in_comment
= imm
;
3539 /* LSB and WIDTH fields of BFI or BFC. The machine-
3540 language instruction encodes LSB and MSB. */
3542 long msb
= (given
& 0x001f0000) >> 16;
3543 long lsb
= (given
& 0x00000f80) >> 7;
3544 long w
= msb
- lsb
+ 1;
3547 func (stream
, "#%lu, #%lu", lsb
, w
);
3549 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
3554 /* Get the PSR/banked register name. */
3557 unsigned sysm
= (given
& 0x004f0000) >> 16;
3559 sysm
|= (given
& 0x300) >> 4;
3560 name
= banked_regname (sysm
);
3563 func (stream
, "%s", name
);
3565 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
3570 /* 16-bit unsigned immediate from a MOVT or MOVW
3571 instruction, encoded in bits 0:11 and 15:19. */
3573 long hi
= (given
& 0x000f0000) >> 4;
3574 long lo
= (given
& 0x00000fff);
3575 long imm16
= hi
| lo
;
3577 func (stream
, "#%lu", imm16
);
3578 value_in_comment
= imm16
;
3588 func (stream
, "%c", *c
);
3591 if (value_in_comment
> 32 || value_in_comment
< -16)
3592 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
3594 if (is_unpredictable
)
3595 func (stream
, UNPREDICTABLE_INSTRUCTION
);
3603 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
3606 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
3608 const struct opcode16
*insn
;
3609 void *stream
= info
->stream
;
3610 fprintf_ftype func
= info
->fprintf_func
;
3612 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
3613 if ((given
& insn
->mask
) == insn
->value
)
3615 signed long value_in_comment
= 0;
3616 const char *c
= insn
->assembler
;
3625 func (stream
, "%c", *c
);
3632 func (stream
, "%%");
3637 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
3642 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
3651 ifthen_next_state
= given
& 0xff;
3652 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
3653 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
3654 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
3659 if (ifthen_next_state
)
3660 func (stream
, "\t; unpredictable branch in IT block\n");
3665 func (stream
, "\t; unpredictable <IT:%s>",
3666 arm_conditional
[IFTHEN_COND
]);
3673 reg
= (given
>> 3) & 0x7;
3674 if (given
& (1 << 6))
3677 func (stream
, "%s", arm_regnames
[reg
]);
3686 if (given
& (1 << 7))
3689 func (stream
, "%s", arm_regnames
[reg
]);
3694 if (given
& (1 << 8))
3698 if (*c
== 'O' && (given
& (1 << 8)))
3708 /* It would be nice if we could spot
3709 ranges, and generate the rS-rE format: */
3710 for (reg
= 0; (reg
< 8); reg
++)
3711 if ((given
& (1 << reg
)) != 0)
3714 func (stream
, ", ");
3716 func (stream
, "%s", arm_regnames
[reg
]);
3722 func (stream
, ", ");
3724 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
3730 func (stream
, ", ");
3731 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
3739 /* Print writeback indicator for a LDMIA. We are doing a
3740 writeback if the base register is not in the register
3742 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
3747 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3749 bfd_vma address
= (pc
+ 4
3750 + ((given
& 0x00f8) >> 2)
3751 + ((given
& 0x0200) >> 3));
3752 info
->print_address_func (address
, info
);
3757 /* Right shift immediate -- bits 6..10; 1-31 print
3758 as themselves, 0 prints as 32. */
3760 long imm
= (given
& 0x07c0) >> 6;
3763 func (stream
, "#%ld", imm
);
3767 case '0': case '1': case '2': case '3': case '4':
3768 case '5': case '6': case '7': case '8': case '9':
3770 int bitstart
= *c
++ - '0';
3773 while (*c
>= '0' && *c
<= '9')
3774 bitstart
= (bitstart
* 10) + *c
++ - '0';
3783 while (*c
>= '0' && *c
<= '9')
3784 bitend
= (bitend
* 10) + *c
++ - '0';
3787 reg
= given
>> bitstart
;
3788 reg
&= (2 << (bitend
- bitstart
)) - 1;
3793 func (stream
, "%s", arm_regnames
[reg
]);
3797 func (stream
, "%ld", (long) reg
);
3798 value_in_comment
= reg
;
3802 func (stream
, "%ld", (long) (reg
<< 1));
3803 value_in_comment
= reg
<< 1;
3807 func (stream
, "%ld", (long) (reg
<< 2));
3808 value_in_comment
= reg
<< 2;
3812 /* PC-relative address -- the bottom two
3813 bits of the address are dropped
3814 before the calculation. */
3815 info
->print_address_func
3816 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
3817 value_in_comment
= 0;
3821 func (stream
, "0x%04lx", (long) reg
);
3825 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
3826 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
3827 value_in_comment
= 0;
3831 func (stream
, "%s", arm_conditional
[reg
]);
3842 if ((given
& (1 << bitstart
)) != 0)
3843 func (stream
, "%c", *c
);
3848 if ((given
& (1 << bitstart
)) != 0)
3849 func (stream
, "%c", *c
++);
3851 func (stream
, "%c", *++c
);
3865 if (value_in_comment
> 32 || value_in_comment
< -16)
3866 func (stream
, "\t; 0x%lx", value_in_comment
);
3874 /* Return the name of an V7M special register. */
3877 psr_name (int regno
)
3881 case 0: return "APSR";
3882 case 1: return "IAPSR";
3883 case 2: return "EAPSR";
3884 case 3: return "PSR";
3885 case 5: return "IPSR";
3886 case 6: return "EPSR";
3887 case 7: return "IEPSR";
3888 case 8: return "MSP";
3889 case 9: return "PSP";
3890 case 16: return "PRIMASK";
3891 case 17: return "BASEPRI";
3892 case 18: return "BASEPRI_MAX";
3893 case 19: return "FAULTMASK";
3894 case 20: return "CONTROL";
3895 default: return "<unknown>";
3899 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3902 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
3904 const struct opcode32
*insn
;
3905 void *stream
= info
->stream
;
3906 fprintf_ftype func
= info
->fprintf_func
;
3908 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
3911 if (print_insn_neon (info
, given
, TRUE
))
3914 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
3915 if ((given
& insn
->mask
) == insn
->value
)
3917 bfd_boolean is_unpredictable
= FALSE
;
3918 signed long value_in_comment
= 0;
3919 const char *c
= insn
->assembler
;
3925 func (stream
, "%c", *c
);
3932 func (stream
, "%%");
3937 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
3941 if (ifthen_next_state
)
3942 func (stream
, "\t; unpredictable branch in IT block\n");
3947 func (stream
, "\t; unpredictable <IT:%s>",
3948 arm_conditional
[IFTHEN_COND
]);
3953 unsigned int imm12
= 0;
3955 imm12
|= (given
& 0x000000ffu
);
3956 imm12
|= (given
& 0x00007000u
) >> 4;
3957 imm12
|= (given
& 0x04000000u
) >> 15;
3958 func (stream
, "#%u", imm12
);
3959 value_in_comment
= imm12
;
3965 unsigned int bits
= 0, imm
, imm8
, mod
;
3967 bits
|= (given
& 0x000000ffu
);
3968 bits
|= (given
& 0x00007000u
) >> 4;
3969 bits
|= (given
& 0x04000000u
) >> 15;
3970 imm8
= (bits
& 0x0ff);
3971 mod
= (bits
& 0xf00) >> 8;
3974 case 0: imm
= imm8
; break;
3975 case 1: imm
= ((imm8
<< 16) | imm8
); break;
3976 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
3977 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
3979 mod
= (bits
& 0xf80) >> 7;
3980 imm8
= (bits
& 0x07f) | 0x80;
3981 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
3983 func (stream
, "#%u", imm
);
3984 value_in_comment
= imm
;
3990 unsigned int imm
= 0;
3992 imm
|= (given
& 0x000000ffu
);
3993 imm
|= (given
& 0x00007000u
) >> 4;
3994 imm
|= (given
& 0x04000000u
) >> 15;
3995 imm
|= (given
& 0x000f0000u
) >> 4;
3996 func (stream
, "#%u", imm
);
3997 value_in_comment
= imm
;
4003 unsigned int imm
= 0;
4005 imm
|= (given
& 0x000f0000u
) >> 16;
4006 imm
|= (given
& 0x00000ff0u
) >> 0;
4007 imm
|= (given
& 0x0000000fu
) << 12;
4008 func (stream
, "#%u", imm
);
4009 value_in_comment
= imm
;
4015 unsigned int imm
= 0;
4017 imm
|= (given
& 0x00000fffu
);
4018 imm
|= (given
& 0x000f0000u
) >> 4;
4019 func (stream
, "#%u", imm
);
4020 value_in_comment
= imm
;
4026 unsigned int reg
= (given
& 0x0000000fu
);
4027 unsigned int stp
= (given
& 0x00000030u
) >> 4;
4028 unsigned int imm
= 0;
4029 imm
|= (given
& 0x000000c0u
) >> 6;
4030 imm
|= (given
& 0x00007000u
) >> 10;
4032 func (stream
, "%s", arm_regnames
[reg
]);
4037 func (stream
, ", lsl #%u", imm
);
4043 func (stream
, ", lsr #%u", imm
);
4049 func (stream
, ", asr #%u", imm
);
4054 func (stream
, ", rrx");
4056 func (stream
, ", ror #%u", imm
);
4063 unsigned int Rn
= (given
& 0x000f0000) >> 16;
4064 unsigned int U
= ! NEGATIVE_BIT_SET
;
4065 unsigned int op
= (given
& 0x00000f00) >> 8;
4066 unsigned int i12
= (given
& 0x00000fff);
4067 unsigned int i8
= (given
& 0x000000ff);
4068 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
4071 func (stream
, "[%s", arm_regnames
[Rn
]);
4072 if (U
) /* 12-bit positive immediate offset. */
4076 value_in_comment
= offset
;
4078 else if (Rn
== 15) /* 12-bit negative immediate offset. */
4079 offset
= - (int) i12
;
4080 else if (op
== 0x0) /* Shifted register offset. */
4082 unsigned int Rm
= (i8
& 0x0f);
4083 unsigned int sh
= (i8
& 0x30) >> 4;
4085 func (stream
, ", %s", arm_regnames
[Rm
]);
4087 func (stream
, ", lsl #%u", sh
);
4093 case 0xE: /* 8-bit positive immediate offset. */
4097 case 0xC: /* 8-bit negative immediate offset. */
4101 case 0xF: /* 8-bit + preindex with wb. */
4106 case 0xD: /* 8-bit - preindex with wb. */
4111 case 0xB: /* 8-bit + postindex. */
4116 case 0x9: /* 8-bit - postindex. */
4122 func (stream
, ", <undefined>]");
4127 func (stream
, "], #%d", (int) offset
);
4131 func (stream
, ", #%d", (int) offset
);
4132 func (stream
, writeback
? "]!" : "]");
4137 func (stream
, "\t; ");
4138 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
4146 unsigned int U
= ! NEGATIVE_BIT_SET
;
4147 unsigned int W
= WRITEBACK_BIT_SET
;
4148 unsigned int Rn
= (given
& 0x000f0000) >> 16;
4149 unsigned int off
= (given
& 0x000000ff);
4151 func (stream
, "[%s", arm_regnames
[Rn
]);
4157 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
4158 value_in_comment
= off
* 4 * U
? 1 : -1;
4166 func (stream
, "], ");
4169 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
4170 value_in_comment
= off
* 4 * U
? 1 : -1;
4174 func (stream
, "{%u}", off
);
4175 value_in_comment
= off
;
4183 unsigned int Sbit
= (given
& 0x01000000) >> 24;
4184 unsigned int type
= (given
& 0x00600000) >> 21;
4188 case 0: func (stream
, Sbit
? "sb" : "b"); break;
4189 case 1: func (stream
, Sbit
? "sh" : "h"); break;
4192 func (stream
, "??");
4195 func (stream
, "??");
4207 for (reg
= 0; reg
< 16; reg
++)
4208 if ((given
& (1 << reg
)) != 0)
4211 func (stream
, ", ");
4213 func (stream
, "%s", arm_regnames
[reg
]);
4221 unsigned int msb
= (given
& 0x0000001f);
4222 unsigned int lsb
= 0;
4224 lsb
|= (given
& 0x000000c0u
) >> 6;
4225 lsb
|= (given
& 0x00007000u
) >> 10;
4226 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
4232 unsigned int width
= (given
& 0x0000001f) + 1;
4233 unsigned int lsb
= 0;
4235 lsb
|= (given
& 0x000000c0u
) >> 6;
4236 lsb
|= (given
& 0x00007000u
) >> 10;
4237 func (stream
, "#%u, #%u", lsb
, width
);
4243 unsigned int S
= (given
& 0x04000000u
) >> 26;
4244 unsigned int J1
= (given
& 0x00002000u
) >> 13;
4245 unsigned int J2
= (given
& 0x00000800u
) >> 11;
4251 offset
|= (given
& 0x003f0000) >> 4;
4252 offset
|= (given
& 0x000007ff) << 1;
4253 offset
-= (1 << 20);
4255 info
->print_address_func (pc
+ 4 + offset
, info
);
4261 unsigned int S
= (given
& 0x04000000u
) >> 26;
4262 unsigned int I1
= (given
& 0x00002000u
) >> 13;
4263 unsigned int I2
= (given
& 0x00000800u
) >> 11;
4267 offset
|= !(I1
^ S
) << 23;
4268 offset
|= !(I2
^ S
) << 22;
4269 offset
|= (given
& 0x03ff0000u
) >> 4;
4270 offset
|= (given
& 0x000007ffu
) << 1;
4271 offset
-= (1 << 24);
4274 /* BLX target addresses are always word aligned. */
4275 if ((given
& 0x00001000u
) == 0)
4278 info
->print_address_func (offset
, info
);
4284 unsigned int shift
= 0;
4286 shift
|= (given
& 0x000000c0u
) >> 6;
4287 shift
|= (given
& 0x00007000u
) >> 10;
4288 if (WRITEBACK_BIT_SET
)
4289 func (stream
, ", asr #%u", shift
);
4291 func (stream
, ", lsl #%u", shift
);
4292 /* else print nothing - lsl #0 */
4298 unsigned int rot
= (given
& 0x00000030) >> 4;
4301 func (stream
, ", ror #%u", rot
* 8);
4306 if ((given
& 0xf0) == 0x60)
4308 switch (given
& 0xf)
4310 case 0xf: func (stream
, "sy"); break;
4312 func (stream
, "#%d", (int) given
& 0xf);
4318 const char * opt
= data_barrier_option (given
& 0xf);
4320 func (stream
, "%s", opt
);
4322 func (stream
, "#%d", (int) given
& 0xf);
4327 if ((given
& 0xff) == 0)
4329 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
4339 else if ((given
& 0x20) == 0x20)
4342 unsigned sysm
= (given
& 0xf00) >> 8;
4344 sysm
|= (given
& 0x30);
4345 sysm
|= (given
& 0x00100000) >> 14;
4346 name
= banked_regname (sysm
);
4349 func (stream
, "%s", name
);
4351 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
4355 func (stream
, "%s", psr_name (given
& 0xff));
4360 if (((given
& 0xff) == 0)
4361 || ((given
& 0x20) == 0x20))
4364 unsigned sm
= (given
& 0xf0000) >> 16;
4366 sm
|= (given
& 0x30);
4367 sm
|= (given
& 0x00100000) >> 14;
4368 name
= banked_regname (sm
);
4371 func (stream
, "%s", name
);
4373 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
4376 func (stream
, "%s", psr_name (given
& 0xff));
4379 case '0': case '1': case '2': case '3': case '4':
4380 case '5': case '6': case '7': case '8': case '9':
4385 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
4390 func (stream
, "%lu", val
);
4391 value_in_comment
= val
;
4395 func (stream
, "%lu", val
* 4);
4396 value_in_comment
= val
* 4;
4401 is_unpredictable
= TRUE
;
4404 func (stream
, "%s", arm_regnames
[val
]);
4408 func (stream
, "%s", arm_conditional
[val
]);
4413 if (val
== ((1ul << width
) - 1))
4414 func (stream
, "%c", *c
);
4420 func (stream
, "%c", *c
);
4424 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
4429 func (stream
, "0x%lx", val
& 0xffffffffUL
);
4439 /* PR binutils/12534
4440 If we have a PC relative offset in an LDRD or STRD
4441 instructions then display the decoded address. */
4442 if (((given
>> 16) & 0xf) == 0xf)
4444 bfd_vma offset
= (given
& 0xff) * 4;
4446 if ((given
& (1 << 23)) == 0)
4448 func (stream
, "\t; ");
4449 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
4458 if (value_in_comment
> 32 || value_in_comment
< -16)
4459 func (stream
, "\t; 0x%lx", value_in_comment
);
4461 if (is_unpredictable
)
4462 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4471 /* Print data bytes on INFO->STREAM. */
4474 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
4475 struct disassemble_info
*info
,
4478 switch (info
->bytes_per_chunk
)
4481 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
4484 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
4487 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
4494 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4495 being displayed in symbol relative addresses. */
4498 arm_symbol_is_valid (asymbol
* sym
,
4499 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
4506 name
= bfd_asymbol_name (sym
);
4508 return (name
&& *name
!= '$');
4511 /* Parse an individual disassembler option. */
4514 parse_arm_disassembler_option (char *option
)
4519 if (CONST_STRNEQ (option
, "reg-names-"))
4525 for (i
= NUM_ARM_REGNAMES
; i
--;)
4526 if (strneq (option
, regnames
[i
].name
, strlen (regnames
[i
].name
)))
4528 regname_selected
= i
;
4533 /* XXX - should break 'option' at following delimiter. */
4534 fprintf (stderr
, _("Unrecognised register name set: %s\n"), option
);
4536 else if (CONST_STRNEQ (option
, "force-thumb"))
4538 else if (CONST_STRNEQ (option
, "no-force-thumb"))
4541 /* XXX - should break 'option' at following delimiter. */
4542 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
4547 /* Parse the string of disassembler options, spliting it at whitespaces
4548 or commas. (Whitespace separators supported for backwards compatibility). */
4551 parse_disassembler_options (char *options
)
4553 if (options
== NULL
)
4558 parse_arm_disassembler_option (options
);
4560 /* Skip forward to next seperator. */
4561 while ((*options
) && (! ISSPACE (*options
)) && (*options
!= ','))
4563 /* Skip forward past seperators. */
4564 while (ISSPACE (*options
) || (*options
== ','))
4569 /* Search back through the insn stream to determine if this instruction is
4570 conditionally executed. */
4573 find_ifthen_state (bfd_vma pc
,
4574 struct disassemble_info
*info
,
4580 /* COUNT is twice the number of instructions seen. It will be odd if we
4581 just crossed an instruction boundary. */
4584 unsigned int seen_it
;
4587 ifthen_address
= pc
;
4594 /* Scan backwards looking for IT instructions, keeping track of where
4595 instruction boundaries are. We don't know if something is actually an
4596 IT instruction until we find a definite instruction boundary. */
4599 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
4601 /* A symbol must be on an instruction boundary, and will not
4602 be within an IT block. */
4603 if (seen_it
&& (count
& 1))
4609 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
4614 insn
= (b
[0]) | (b
[1] << 8);
4616 insn
= (b
[1]) | (b
[0] << 8);
4619 if ((insn
& 0xf800) < 0xe800)
4621 /* Addr + 2 is an instruction boundary. See if this matches
4622 the expected boundary based on the position of the last
4629 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
4631 /* This could be an IT instruction. */
4633 it_count
= count
>> 1;
4635 if ((insn
& 0xf800) >= 0xe800)
4638 count
= (count
+ 2) | 1;
4639 /* IT blocks contain at most 4 instructions. */
4640 if (count
>= 8 && !seen_it
)
4643 /* We found an IT instruction. */
4644 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
4645 if ((ifthen_state
& 0xf) == 0)
4649 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4653 is_mapping_symbol (struct disassemble_info
*info
, int n
,
4654 enum map_type
*map_type
)
4658 name
= bfd_asymbol_name (info
->symtab
[n
]);
4659 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
4660 && (name
[2] == 0 || name
[2] == '.'))
4662 *map_type
= ((name
[1] == 'a') ? MAP_ARM
4663 : (name
[1] == 't') ? MAP_THUMB
4671 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4672 Returns nonzero if *MAP_TYPE was set. */
4675 get_map_sym_type (struct disassemble_info
*info
,
4677 enum map_type
*map_type
)
4679 /* If the symbol is in a different section, ignore it. */
4680 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
4683 return is_mapping_symbol (info
, n
, map_type
);
4686 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4687 Returns nonzero if *MAP_TYPE was set. */
4690 get_sym_code_type (struct disassemble_info
*info
,
4692 enum map_type
*map_type
)
4694 elf_symbol_type
*es
;
4697 /* If the symbol is in a different section, ignore it. */
4698 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
4701 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
4702 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
4704 /* If the symbol has function type then use that. */
4705 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
4707 if (ARM_SYM_BRANCH_TYPE (&es
->internal_elf_sym
) == ST_BRANCH_TO_THUMB
)
4708 *map_type
= MAP_THUMB
;
4710 *map_type
= MAP_ARM
;
4717 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4718 of the supplied arm_feature_set structure with bitmasks indicating
4719 the support base architectures and coprocessor extensions.
4721 FIXME: This could more efficiently implemented as a constant array,
4722 although it would also be less robust. */
4725 select_arm_features (unsigned long mach
,
4726 arm_feature_set
* features
)
4729 #define ARM_FEATURE(ARCH,CEXT) \
4730 features->core = (ARCH); \
4731 features->coproc = (CEXT) | FPU_FPA; \
4736 case bfd_mach_arm_2
: ARM_ARCH_V2
;
4737 case bfd_mach_arm_2a
: ARM_ARCH_V2S
;
4738 case bfd_mach_arm_3
: ARM_ARCH_V3
;
4739 case bfd_mach_arm_3M
: ARM_ARCH_V3M
;
4740 case bfd_mach_arm_4
: ARM_ARCH_V4
;
4741 case bfd_mach_arm_4T
: ARM_ARCH_V4T
;
4742 case bfd_mach_arm_5
: ARM_ARCH_V5
;
4743 case bfd_mach_arm_5T
: ARM_ARCH_V5T
;
4744 case bfd_mach_arm_5TE
: ARM_ARCH_V5TE
;
4745 case bfd_mach_arm_XScale
: ARM_ARCH_XSCALE
;
4746 case bfd_mach_arm_ep9312
: ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
| FPU_MAVERICK
);
4747 case bfd_mach_arm_iWMMXt
: ARM_ARCH_IWMMXT
;
4748 case bfd_mach_arm_iWMMXt2
: ARM_ARCH_IWMMXT2
;
4749 /* If the machine type is unknown allow all
4750 architecture types and all extensions. */
4751 case bfd_mach_arm_unknown
: ARM_FEATURE (-1UL, -1UL);
4758 /* NOTE: There are no checks in these routines that
4759 the relevant number of data bytes exist. */
4762 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
4767 int is_thumb
= FALSE
;
4768 int is_data
= FALSE
;
4770 unsigned int size
= 4;
4771 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
4772 bfd_boolean found
= FALSE
;
4773 struct arm_private_data
*private_data
;
4775 if (info
->disassembler_options
)
4777 parse_disassembler_options (info
->disassembler_options
);
4779 /* To avoid repeated parsing of these options, we remove them here. */
4780 info
->disassembler_options
= NULL
;
4783 /* PR 10288: Control which instructions will be disassembled. */
4784 if (info
->private_data
== NULL
)
4786 static struct arm_private_data
private;
4788 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
4789 /* If the user did not use the -m command line switch then default to
4790 disassembling all types of ARM instruction.
4792 The info->mach value has to be ignored as this will be based on
4793 the default archictecture for the target and/or hints in the notes
4794 section, but it will never be greater than the current largest arm
4795 machine value (iWMMXt2), which is only equivalent to the V5TE
4796 architecture. ARM architectures have advanced beyond the machine
4797 value encoding, and these newer architectures would be ignored if
4798 the machine value was used.
4800 Ie the -m switch is used to restrict which instructions will be
4801 disassembled. If it is necessary to use the -m switch to tell
4802 objdump that an ARM binary is being disassembled, eg because the
4803 input is a raw binary file, but it is also desired to disassemble
4804 all ARM instructions then use "-marm". This will select the
4805 "unknown" arm architecture which is compatible with any ARM
4807 info
->mach
= bfd_mach_arm_unknown
;
4809 /* Compute the architecture bitmask from the machine number.
4810 Note: This assumes that the machine number will not change
4811 during disassembly.... */
4812 select_arm_features (info
->mach
, & private.features
);
4814 private.has_mapping_symbols
= -1;
4815 private.last_mapping_sym
= -1;
4816 private.last_mapping_addr
= 0;
4818 info
->private_data
= & private;
4821 private_data
= info
->private_data
;
4823 /* Decide if our code is going to be little-endian, despite what the
4824 function argument might say. */
4825 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
4827 /* For ELF, consult the symbol table to determine what kind of code
4829 if (info
->symtab_size
!= 0
4830 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
4835 enum map_type type
= MAP_ARM
;
4837 /* Start scanning at the start of the function, or wherever
4838 we finished last time. */
4839 /* PR 14006. When the address is 0 we are either at the start of the
4840 very first function, or else the first function in a new, unlinked
4841 executable section (eg because uf -ffunction-sections). Either way
4842 start scanning from the beginning of the symbol table, not where we
4843 left off last time. */
4848 start
= info
->symtab_pos
+ 1;
4849 if (start
< private_data
->last_mapping_sym
)
4850 start
= private_data
->last_mapping_sym
;
4854 /* First, look for mapping symbols. */
4855 if (private_data
->has_mapping_symbols
!= 0)
4857 /* Scan up to the location being disassembled. */
4858 for (n
= start
; n
< info
->symtab_size
; n
++)
4860 addr
= bfd_asymbol_value (info
->symtab
[n
]);
4863 if (get_map_sym_type (info
, n
, &type
))
4872 /* No mapping symbol found at this address. Look backwards
4873 for a preceding one. */
4874 for (n
= start
- 1; n
>= 0; n
--)
4876 if (get_map_sym_type (info
, n
, &type
))
4886 private_data
->has_mapping_symbols
= 1;
4888 /* No mapping symbols were found. A leading $d may be
4889 omitted for sections which start with data; but for
4890 compatibility with legacy and stripped binaries, only
4891 assume the leading $d if there is at least one mapping
4892 symbol in the file. */
4893 if (!found
&& private_data
->has_mapping_symbols
== -1)
4895 /* Look for mapping symbols, in any section. */
4896 for (n
= 0; n
< info
->symtab_size
; n
++)
4897 if (is_mapping_symbol (info
, n
, &type
))
4899 private_data
->has_mapping_symbols
= 1;
4902 if (private_data
->has_mapping_symbols
== -1)
4903 private_data
->has_mapping_symbols
= 0;
4906 if (!found
&& private_data
->has_mapping_symbols
== 1)
4913 /* Next search for function symbols to separate ARM from Thumb
4914 in binaries without mapping symbols. */
4917 /* Scan up to the location being disassembled. */
4918 for (n
= start
; n
< info
->symtab_size
; n
++)
4920 addr
= bfd_asymbol_value (info
->symtab
[n
]);
4923 if (get_sym_code_type (info
, n
, &type
))
4932 /* No mapping symbol found at this address. Look backwards
4933 for a preceding one. */
4934 for (n
= start
- 1; n
>= 0; n
--)
4936 if (get_sym_code_type (info
, n
, &type
))
4946 private_data
->last_mapping_sym
= last_sym
;
4947 private_data
->last_type
= type
;
4948 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
4949 is_data
= (private_data
->last_type
== MAP_DATA
);
4951 /* Look a little bit ahead to see if we should print out
4952 two or four bytes of data. If there's a symbol,
4953 mapping or otherwise, after two bytes then don't
4957 size
= 4 - (pc
& 3);
4958 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
4960 addr
= bfd_asymbol_value (info
->symtab
[n
]);
4962 && (info
->section
== NULL
4963 || info
->section
== info
->symtab
[n
]->section
))
4965 if (addr
- pc
< size
)
4970 /* If the next symbol is after three bytes, we need to
4971 print only part of the data, so that we can use either
4974 size
= (pc
& 1) ? 1 : 2;
4978 if (info
->symbols
!= NULL
)
4980 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
4982 coff_symbol_type
* cs
;
4984 cs
= coffsymbol (*info
->symbols
);
4985 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
4986 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
4987 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
4988 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
4989 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
4991 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
4994 /* If no mapping symbol has been found then fall back to the type
4995 of the function symbol. */
4996 elf_symbol_type
* es
;
4999 es
= *(elf_symbol_type
**)(info
->symbols
);
5000 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
5002 is_thumb
= ((ARM_SYM_BRANCH_TYPE (&es
->internal_elf_sym
)
5003 == ST_BRANCH_TO_THUMB
)
5004 || type
== STT_ARM_16BIT
);
5012 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
5014 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
5016 info
->bytes_per_line
= 4;
5018 /* PR 10263: Disassemble data if requested to do so by the user. */
5019 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
5023 /* Size was already set above. */
5024 info
->bytes_per_chunk
= size
;
5025 printer
= print_insn_data
;
5027 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
5030 for (i
= size
- 1; i
>= 0; i
--)
5031 given
= b
[i
] | (given
<< 8);
5033 for (i
= 0; i
< (int) size
; i
++)
5034 given
= b
[i
] | (given
<< 8);
5038 /* In ARM mode endianness is a straightforward issue: the instruction
5039 is four bytes long and is either ordered 0123 or 3210. */
5040 printer
= print_insn_arm
;
5041 info
->bytes_per_chunk
= 4;
5044 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
5046 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
5048 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
5052 /* In Thumb mode we have the additional wrinkle of two
5053 instruction lengths. Fortunately, the bits that determine
5054 the length of the current instruction are always to be found
5055 in the first two bytes. */
5056 printer
= print_insn_thumb16
;
5057 info
->bytes_per_chunk
= 2;
5060 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
5062 given
= (b
[0]) | (b
[1] << 8);
5064 given
= (b
[1]) | (b
[0] << 8);
5068 /* These bit patterns signal a four-byte Thumb
5070 if ((given
& 0xF800) == 0xF800
5071 || (given
& 0xF800) == 0xF000
5072 || (given
& 0xF800) == 0xE800)
5074 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
5076 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
5078 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
5080 printer
= print_insn_thumb32
;
5085 if (ifthen_address
!= pc
)
5086 find_ifthen_state (pc
, info
, little_code
);
5090 if ((ifthen_state
& 0xf) == 0x8)
5091 ifthen_next_state
= 0;
5093 ifthen_next_state
= (ifthen_state
& 0xe0)
5094 | ((ifthen_state
& 0xf) << 1);
5100 info
->memory_error_func (status
, pc
, info
);
5103 if (info
->flags
& INSN_HAS_RELOC
)
5104 /* If the instruction has a reloc associated with it, then
5105 the offset field in the instruction will actually be the
5106 addend for the reloc. (We are using REL type relocs).
5107 In such cases, we can ignore the pc when computing
5108 addresses, since the addend is not currently pc-relative. */
5111 printer (pc
, info
, given
);
5115 ifthen_state
= ifthen_next_state
;
5116 ifthen_address
+= size
;
5122 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
5124 /* Detect BE8-ness and record it in the disassembler info. */
5125 if (info
->flavour
== bfd_target_elf_flavour
5126 && info
->section
!= NULL
5127 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
5128 info
->endian_code
= BFD_ENDIAN_LITTLE
;
5130 return print_insn (pc
, info
, FALSE
);
5134 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
5136 return print_insn (pc
, info
, TRUE
);
5140 print_arm_disassembler_options (FILE *stream
)
5144 fprintf (stream
, _("\n\
5145 The following ARM specific disassembler options are supported for use with\n\
5146 the -M switch:\n"));
5148 for (i
= NUM_ARM_REGNAMES
; i
--;)
5149 fprintf (stream
, " reg-names-%s %*c%s\n",
5151 (int)(14 - strlen (regnames
[i
].name
)), ' ',
5152 regnames
[i
].description
);
5154 fprintf (stream
, " force-thumb Assume all insns are Thumb insns\n");
5155 fprintf (stream
, " no-force-thumb Examine preceding label to determine an insn's type\n\n");