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Add LD and GAS testsuites for CRX port.
[thirdparty/binutils-gdb.git] / opcodes / crx-opc.c
1 /* crx-opc.c -- Table of opcodes for the CRX processor.
2 Copyright 2004 Free Software Foundation, Inc.
3 Contributed by Tomer Levi NSC, Israel.
4 Originally written for GAS 2.12 by Tomer Levi.
5
6 This file is part of GAS, GDB and the GNU binutils.
7
8 GAS, GDB, and GNU binutils is free software; you can redistribute it
9 and/or modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
12
13 GAS, GDB, and GNU binutils are distributed in the hope that they will be
14 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include <stdio.h>
23 #include "libiberty.h"
24 #include "symcat.h"
25 #include "opcode/crx.h"
26
27 const inst crx_instruction[] =
28 {
29 /* Create an arithmetic instruction - INST[bw]. */
30 #define ARITH_BYTE_INST(NAME, OPC) \
31 /* opc8 cst4 r */ \
32 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{cst4,20}, {regr,16}}}, \
33 /* opc8 i16 r */ \
34 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS, {{i16,0}, {regr,16}}}, \
35 /* opc8 r r */ \
36 {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
37
38 ARITH_BYTE_INST ("addub", 0x0),
39 ARITH_BYTE_INST ("addb", 0x1),
40 ARITH_BYTE_INST ("addcb", 0x2),
41 ARITH_BYTE_INST ("andb", 0x3),
42 ARITH_BYTE_INST ("cmpb", 0x4),
43 ARITH_BYTE_INST ("movb", 0x5),
44 ARITH_BYTE_INST ("orb", 0x6),
45 ARITH_BYTE_INST ("subb", 0x7),
46 ARITH_BYTE_INST ("subcb", 0x8),
47 ARITH_BYTE_INST ("xorb", 0x9),
48 ARITH_BYTE_INST ("mulb", 0xA),
49
50 ARITH_BYTE_INST ("adduw", 0x10),
51 ARITH_BYTE_INST ("addw", 0x11),
52 ARITH_BYTE_INST ("addcw", 0x12),
53 ARITH_BYTE_INST ("andw", 0x13),
54 ARITH_BYTE_INST ("cmpw", 0x14),
55 ARITH_BYTE_INST ("movw", 0x15),
56 ARITH_BYTE_INST ("orw", 0x16),
57 ARITH_BYTE_INST ("subw", 0x17),
58 ARITH_BYTE_INST ("subcw", 0x18),
59 ARITH_BYTE_INST ("xorw", 0x19),
60 ARITH_BYTE_INST ("mulw", 0x1A),
61
62 /* Create an arithmetic instruction - INST[d]. */
63 #define ARITH_INST(NAME, OPC) \
64 /* opc8 cst4 r */ \
65 {NAME, 1, OPC, 24, ARITH_INS, {{cst4,20}, {regr,16}}}, \
66 /* opc8 i16 r */ \
67 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS, {{i16,0}, {regr,16}}}, \
68 /* opc8 i32 r */ \
69 {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \
70 /* opc8 r r */ \
71 {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}}
72
73 ARITH_INST ("addud", 0x20),
74 ARITH_INST ("addd", 0x21),
75 ARITH_INST ("addcd", 0x22),
76 ARITH_INST ("andd", 0x23),
77 ARITH_INST ("cmpd", 0x24),
78 ARITH_INST ("movd", 0x25),
79 ARITH_INST ("ord", 0x26),
80 ARITH_INST ("subd", 0x27),
81 ARITH_INST ("subcd", 0x28),
82 ARITH_INST ("xord", 0x29),
83 ARITH_INST ("muld", 0x2A),
84
85 /* Create a shift instruction. */
86 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
87 /* OPRD=i3 -->> opc9 i3 r */ \
88 /* OPRD=i4 -->> opc8 i4 r */ \
89 /* OPRD=i5 -->> opc7 i5 r */ \
90 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
91 /* opc8 r r */ \
92 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
93
94 SHIFT_INST ("sllb", i3, 0x1F8, 23, 0x4D),
95 SHIFT_INST ("srlb", i3, 0x1F9, 23, 0x4E),
96 SHIFT_INST ("srab", i3, 0x1FA, 23, 0x4F),
97
98 SHIFT_INST ("sllw", i4, 0xB6, 24, 0x5D),
99 SHIFT_INST ("srlw", i4, 0xB7, 24, 0x5E),
100 SHIFT_INST ("sraw", i4, 0xB8, 24, 0x5F),
101
102 SHIFT_INST ("slld", i5, 0x78, 25, 0x6D),
103 SHIFT_INST ("srld", i5, 0x79, 25, 0x6E),
104 SHIFT_INST ("srad", i5, 0x7A, 25, 0x6F),
105
106 /* Create a conditional branch instruction. */
107 #define BRANCH_INST(NAME, OPC) \
108 /* opc4 c4 dispe9 */ \
109 {NAME, 1, OPC, 24, BRANCH_INS | RELAXABLE, {{d9,16}}}, \
110 /* opc4 c4 disps17 */ \
111 {NAME, 2, (OPC<<8)+0x7E, 16, BRANCH_INS | RELAXABLE, {{d17,0}}}, \
112 /* opc4 c4 disps33 */ \
113 {NAME, 3, (OPC<<8)+0x7F, 16, BRANCH_INS | RELAXABLE, {{d33,0}}}
114
115 BRANCH_INST ("beq", 0x70),
116 BRANCH_INST ("bne", 0x71),
117 BRANCH_INST ("bcs", 0x72),
118 BRANCH_INST ("bcc", 0x73),
119 BRANCH_INST ("bhi", 0x74),
120 BRANCH_INST ("bls", 0x75),
121 BRANCH_INST ("bgt", 0x76),
122 BRANCH_INST ("ble", 0x77),
123 BRANCH_INST ("bfs", 0x78),
124 BRANCH_INST ("bfc", 0x79),
125 BRANCH_INST ("blo", 0x7A),
126 BRANCH_INST ("bhs", 0x7B),
127 BRANCH_INST ("blt", 0x7C),
128 BRANCH_INST ("bge", 0x7D),
129 BRANCH_INST ("br", 0x7E),
130
131 /* Create a 'Branch if Equal to 0' instruction. */
132 #define BRANCH_NEQ_INST(NAME, OPC) \
133 /* opc8 dispu5 r */ \
134 {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {d5,20}}}
135
136 BRANCH_NEQ_INST ("beq0b", 0xB0),
137 BRANCH_NEQ_INST ("bne0b", 0xB1),
138 BRANCH_NEQ_INST ("beq0w", 0xB2),
139 BRANCH_NEQ_INST ("bne0w", 0xB3),
140 BRANCH_NEQ_INST ("beq0d", 0xB4),
141 BRANCH_NEQ_INST ("bne0d", 0xB5),
142
143 /* Create instruction with no operands. */
144 #define NO_OP_INST(NAME, OPC) \
145 /* opc16 */ \
146 {NAME, 1, OPC, 16, 0, {{0, 0}}}
147
148 NO_OP_INST ("nop", 0x3002),
149 NO_OP_INST ("retx", 0x3003),
150 NO_OP_INST ("di", 0x3004),
151 NO_OP_INST ("ei", 0x3005),
152 NO_OP_INST ("wait", 0x3006),
153 NO_OP_INST ("eiwait", 0x3007),
154
155 /* Create a 'Compare & Branch' instruction. */
156 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
157 /* opc12 r r c4 disps9 */ \
158 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, {{regr,16}, {regr,12}, {d9,0}}}, \
159 /* opc12 r r c4 disps25 */ \
160 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, {{regr,16}, {regr,12}, {d25,0}}}, \
161 /* opc12 i4cst4 r c4 disps9 */ \
162 {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, {{cst4,16}, {regr,12}, {d9,0}}}, \
163 /* opc12 i4cst4 r c4 disps25 */ \
164 {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, {{cst4,16}, {regr,12}, {d25,0}}}
165
166 CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0),
167 CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1),
168 CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4),
169 CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5),
170 CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6),
171 CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7),
172 CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA),
173 CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB),
174 CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC),
175 CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD),
176
177 CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0),
178 CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1),
179 CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4),
180 CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5),
181 CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6),
182 CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7),
183 CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA),
184 CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB),
185 CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC),
186 CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD),
187
188 CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0),
189 CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1),
190 CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4),
191 CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5),
192 CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6),
193 CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7),
194 CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA),
195 CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB),
196 CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC),
197 CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD),
198
199 /* Create an instruction using a single register operand. */
200 #define REG1_INST(NAME, OPC) \
201 /* opc8 c4 r */ \
202 {NAME, 1, OPC, 20, 0, {{regr,16}}}
203
204 /* JCond instructions */
205 REG1_INST ("jeq", 0xBA0),
206 REG1_INST ("jne", 0xBA1),
207 REG1_INST ("jcs", 0xBA2),
208 REG1_INST ("jcc", 0xBA3),
209 REG1_INST ("jhi", 0xBA4),
210 REG1_INST ("jls", 0xBA5),
211 REG1_INST ("jgt", 0xBA6),
212 REG1_INST ("jle", 0xBA7),
213 REG1_INST ("jfs", 0xBA8),
214 REG1_INST ("jfc", 0xBA9),
215 REG1_INST ("jlo", 0xBAA),
216 REG1_INST ("jhs", 0xBAB),
217 REG1_INST ("jlt", 0xBAC),
218 REG1_INST ("jge", 0xBAD),
219 REG1_INST ("jump", 0xBAE),
220
221 /* SCond instructions */
222 REG1_INST ("seq", 0xBB0),
223 REG1_INST ("sne", 0xBB1),
224 REG1_INST ("scs", 0xBB2),
225 REG1_INST ("scc", 0xBB3),
226 REG1_INST ("shi", 0xBB4),
227 REG1_INST ("sls", 0xBB5),
228 REG1_INST ("sgt", 0xBB6),
229 REG1_INST ("sle", 0xBB7),
230 REG1_INST ("sfs", 0xBB8),
231 REG1_INST ("sfc", 0xBB9),
232 REG1_INST ("slo", 0xBBA),
233 REG1_INST ("shs", 0xBBB),
234 REG1_INST ("slt", 0xBBC),
235 REG1_INST ("sge", 0xBBD),
236
237 /* Create an instruction using two register operands. */
238 #define REG2_INST(NAME, OPC) \
239 /* opc24 r r OR opc20 c4 r r */ \
240 {NAME, 2, 0x300800+OPC, 8, 0, {{regr,4}, {regr,0}}}
241
242 /* MULTIPLY INSTRUCTIONS */
243 REG2_INST ("macsb", 0x40),
244 REG2_INST ("macub", 0x41),
245 REG2_INST ("macqb", 0x42),
246
247 REG2_INST ("macsw", 0x50),
248 REG2_INST ("macuw", 0x51),
249 REG2_INST ("macqw", 0x52),
250
251 REG2_INST ("macsd", 0x60),
252 REG2_INST ("macud", 0x61),
253 REG2_INST ("macqd", 0x62),
254
255 REG2_INST ("mullsd", 0x65),
256 REG2_INST ("mullud", 0x66),
257
258 REG2_INST ("mulsbw", 0x3B),
259 REG2_INST ("mulubw", 0x3C),
260 REG2_INST ("mulswd", 0x3D),
261 REG2_INST ("muluwd", 0x3E),
262
263 /* SIGNEXTEND STUFF */
264 REG2_INST ("sextbw", 0x30),
265 REG2_INST ("sextbd", 0x31),
266 REG2_INST ("sextwd", 0x32),
267 REG2_INST ("zextbw", 0x34),
268 REG2_INST ("zextbd", 0x35),
269 REG2_INST ("zextwd", 0x36),
270
271 REG2_INST ("bswap", 0x3F),
272
273 REG2_INST ("maxsb", 0x80),
274 REG2_INST ("minsb", 0x81),
275 REG2_INST ("maxub", 0x82),
276 REG2_INST ("minub", 0x83),
277 REG2_INST ("absb", 0x84),
278 REG2_INST ("negb", 0x85),
279 REG2_INST ("cntl0b", 0x86),
280 REG2_INST ("cntl1b", 0x87),
281 REG2_INST ("popcntb",0x88),
282 REG2_INST ("rotlb", 0x89),
283 REG2_INST ("rotrb", 0x8A),
284 REG2_INST ("mulqb", 0x8B),
285 REG2_INST ("addqb", 0x8C),
286 REG2_INST ("subqb", 0x8D),
287 REG2_INST ("cntlsb", 0x8E),
288
289 REG2_INST ("maxsw", 0x90),
290 REG2_INST ("minsw", 0x91),
291 REG2_INST ("maxuw", 0x92),
292 REG2_INST ("minuw", 0x93),
293 REG2_INST ("absw", 0x94),
294 REG2_INST ("negw", 0x95),
295 REG2_INST ("cntl0w", 0x96),
296 REG2_INST ("cntl1w", 0x97),
297 REG2_INST ("popcntw",0x98),
298 REG2_INST ("rotlw", 0x99),
299 REG2_INST ("rotrw", 0x9A),
300 REG2_INST ("mulqw", 0x9B),
301 REG2_INST ("addqw", 0x9C),
302 REG2_INST ("subqw", 0x9D),
303 REG2_INST ("cntlsw", 0x9E),
304
305 REG2_INST ("maxsd", 0xA0),
306 REG2_INST ("minsd", 0xA1),
307 REG2_INST ("maxud", 0xA2),
308 REG2_INST ("minud", 0xA3),
309 REG2_INST ("absd", 0xA4),
310 REG2_INST ("negd", 0xA5),
311 REG2_INST ("cntl0d", 0xA6),
312 REG2_INST ("cntl1d", 0xA7),
313 REG2_INST ("popcntd",0xA8),
314 REG2_INST ("rotld", 0xA9),
315 REG2_INST ("rotrd", 0xAA),
316 REG2_INST ("mulqd", 0xAB),
317 REG2_INST ("addqd", 0xAC),
318 REG2_INST ("subqd", 0xAD),
319 REG2_INST ("cntlsd", 0xAE),
320
321 /* Conditional move instructions */
322 REG2_INST ("cmoveqd", 0x70),
323 REG2_INST ("cmovned", 0x71),
324 REG2_INST ("cmovcsd", 0x72),
325 REG2_INST ("cmovccd", 0x73),
326 REG2_INST ("cmovhid", 0x74),
327 REG2_INST ("cmovlsd", 0x75),
328 REG2_INST ("cmovgtd", 0x76),
329 REG2_INST ("cmovled", 0x77),
330 REG2_INST ("cmovfsd", 0x78),
331 REG2_INST ("cmovfcd", 0x79),
332 REG2_INST ("cmovlod", 0x7A),
333 REG2_INST ("cmovhsd", 0x7B),
334 REG2_INST ("cmovltd", 0x7C),
335 REG2_INST ("cmovged", 0x7D),
336
337 /* Load instructions (from memory to register). */
338 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
339 /* opc12 r abs16 */ \
340 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, {{abs16,0}, {regr,16}}}, \
341 /* opc12 r abs32 */ \
342 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, {{abs32,0}, {regr,16}}}, \
343 /* opc4 r c4 rbase */ \
344 {NAME, 1, ((0x8+OPC2)<<8), 20, LD_STOR_INS | DISP | FMT_1 | REVERSE_MATCH, {{rbase,20}, {regr,24}}},\
345 /* opc4 r rbase dispu[bwd]4 */ \
346 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, {{rbase_cst4,16}, {regr,24}}}, \
347 /* opc4 r rbase disps16 */ \
348 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | DISP | FMT_1 | REVERSE_MATCH, {{rbase_dispu16,16}, {regr,24}}}, \
349 /* opc4 r rbase disps32 */ \
350 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, {{rbase_dispu32,16}, {regr,24}}}, \
351 /* opc12 r rbase */ \
352 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC | REVERSE_MATCH, {{rbase,12}, {regr,16}}}, \
353 /* opc12 r rbase disps12 */ \
354 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC | REVERSE_MATCH, {{rbase_dispu12,12}, {regr,16}}}, \
355 /* opc12 r rbase ridx scl2 disps6 */ \
356 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, {{rbase_ridx_scl2_dispu6,0}, {regr,16}}}, \
357 /* opc12 r rbase ridx scl2 disps22 */ \
358 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, {{rbase_ridx_scl2_dispu22,0}, {regr,16}}}
359
360 LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4),
361 LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4),
362 LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4),
363
364 /* Store instructions (from Register to Memory). */
365 #define ST_REG_INST(NAME, OPC1, OPC2, DISP) \
366 /* opc12 r abs16 */ \
367 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs16,0}}}, \
368 /* opc12 r abs32 */ \
369 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs32,0}}}, \
370 /* opc4 r c4 rbase */ \
371 {NAME, 1, ((0x8+OPC2)<<8), 20, LD_STOR_INS | DISP | FMT_1, {{regr,24}, {rbase,20}}},\
372 /* opc4 r rbase dispu[bwd]4 */ \
373 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP, {{regr,24}, {rbase_cst4,16}}}, \
374 /* opc4 r rbase disps16 */ \
375 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | DISP | FMT_1, {{regr,24}, {rbase_dispu16,16}}}, \
376 /* opc4 r rbase disps32 */ \
377 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1, {{regr,24}, {rbase_dispu32,16}}}, \
378 /* opc12 r rbase */ \
379 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC, {{regr,16}, {rbase,12}}}, \
380 /* opc12 r rbase disps12 */ \
381 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC, {{regr,16}, {rbase_dispu12,12}}}, \
382 /* opc12 r rbase ridx scl2 disps6 */ \
383 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS, {{regr,16}, {rbase_ridx_scl2_dispu6,0}}}, \
384 /* opc12 r rbase ridx scl2 disps22 */ \
385 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS, {{regr,16}, {rbase_ridx_scl2_dispu22,0}}}
386
387 /* Store instructions (Immediate to Memory). */
388 #define ST_I_INST(NAME, OPC) \
389 /* opc12 i4 abs16 */ \
390 {NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{i4,16}, {abs16,0}}}, \
391 /* opc12 i4 abs32 */ \
392 {NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{i4,16}, {abs32,0}}}, \
393 /* opc12 i4 c4 rbase */ \
394 {NAME, 1, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase,12}}}, \
395 /* opc12 i4 rbase disps12 */ \
396 {NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase_dispu12,12}}}, \
397 /* opc4 i4 c4 rbase */ \
398 {NAME, 1, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase,12}}}, \
399 /* opc12 i4 rbase disps12 */ \
400 {NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu12,12}}}, \
401 /* opc12 i4 rbase disps28 */ \
402 {NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu28,12}}}, \
403 /* opc12 i4 rbase ridx scl2 disps6 */ \
404 {NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu6,0}}},\
405 /* opc12 i4 rbase ridx scl2 disps22 */ \
406 {NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu22,0}}}
407
408 ST_REG_INST ("storb", 0x20, 0x4, DISPUB4),
409 ST_I_INST ("storb", 0x0),
410
411 ST_REG_INST ("storw", 0x21, 0x5, DISPUW4),
412 ST_I_INST ("storw", 0x1),
413
414 ST_REG_INST ("stord", 0x22, 0x6, DISPUD4),
415 ST_I_INST ("stord", 0x2),
416
417 /* Create a bit instruction. */
418 #define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
419 /* OP=i3 -->> opc13 i3 */ \
420 /* OP=i4 -->> opc12 i4 */ \
421 /* OP=i5 -->> opc11 i5 */ \
422 \
423 /* opcNN iN abs16 */ \
424 {NAME, 2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}}, \
425 /* opcNN iN abs32 */ \
426 {NAME, 3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}}, \
427 /* opcNN iN rbase */ \
428 {NAME, 1, OPC2, SHIFT+4, CSTBIT_INS, {{OP,20}, {rbase,16}}}, \
429 /* opcNN iN rbase disps12 */ \
430 {NAME, 2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_dispu12,12}}}, \
431 /* opcNN iN rbase disps28 */ \
432 {NAME, 3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_dispu28,12}}}, \
433 /* opcNN iN rbase ridx scl2 disps6 */ \
434 {NAME, 2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_ridx_scl2_dispu6,0}}}, \
435 /* opcNN iN rbase ridx scl2 disps22 */ \
436 {NAME, 3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_ridx_scl2_dispu22,0}}}
437
438 CSTBIT_INST ("cbitb", i3, 0x700, 0x20, 19, 0x1FC),
439 CSTBIT_INST ("cbitw", i4, 0x382, 0x10, 20, 0xBD),
440 CSTBIT_INST ("cbitd", i5, 0x1C3, 0x8, 21, 0x7B),
441 {"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
442 {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
443
444 CSTBIT_INST ("sbitb", i3, 0x701, 0x20, 19, 0x1FD),
445 CSTBIT_INST ("sbitw", i4, 0x383, 0x10, 20, 0xBE),
446 CSTBIT_INST ("sbitd", i5, 0x1C4, 0x8, 21, 0x7C),
447 {"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
448 {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
449
450 CSTBIT_INST ("tbitb", i3, 0x702, 0x20, 19, 0x1FE),
451 CSTBIT_INST ("tbitw", i4, 0x384, 0x10, 20, 0xBF),
452 CSTBIT_INST ("tbitd", i5, 0x1C5, 0x8, 21, 0x7D),
453 {"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
454 {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
455
456 /* Instructions including a register list (opcode is represented as a mask). */
457 #define REGLIST_INST(NAME, OPC) \
458 /* opc12 r mask16 */ \
459 {NAME, 2, OPC, 20, REG_LIST, {{regr,16}, {i16,0}}}
460
461 REG1_INST ("getrfid", 0xFF9),
462 REG1_INST ("setrfid", 0xFFA),
463
464 REGLIST_INST ("push", 0x346),
465 REG1_INST ("push", 0xFFB),
466 REGLIST_INST ("pushx", 0x347),
467
468 REGLIST_INST ("pop", 0x324),
469 REG1_INST ("pop", 0xFFC),
470 REGLIST_INST ("popx", 0x327),
471
472 REGLIST_INST ("popret", 0x326),
473 REG1_INST ("popret", 0xFFD),
474
475 REGLIST_INST ("loadm", 0x324),
476 REGLIST_INST ("loadma", 0x325),
477 REGLIST_INST ("popa", 0x325),
478
479 REGLIST_INST ("storm", 0x344),
480 REGLIST_INST ("storma", 0x345),
481
482 /* Create a branch instruction. */
483 #define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
484 /* opc12 r disps17 */ \
485 {NAME, 2, OPC1, 20, INS_TYPE | RELAXABLE, {{regr,16}, {d17,0}}}, \
486 /* opc12 r disps33 */ \
487 {NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {d33,0}}}
488
489 BR_INST ("bal", 0x307, 0x317, 0),
490
491 /* Decrement and Branch instructions */
492 BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS),
493 BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS),
494 BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS),
495
496 /* Jump and link instructions */
497 REG1_INST ("jal", 0xFF8),
498 REG2_INST ("jal", 0x37),
499 REG2_INST ("jalid", 0x33),
500
501 /* opc12 c4 opc12 r mask16 */
502 {"loadmcr", 3, 0x3110300, 4, COP_REG_INS | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}},
503 {"stormcr", 3, 0x3110301, 4, COP_REG_INS | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}},
504
505 /* esc16 r procreg */
506 {"mtpr", 2, 0x3009, 16, 0, {{regr8,8}, {regr8,0}}},
507 /* esc16 procreg r */
508 {"mfpr", 2, 0x300A, 16, 0, {{regr8,8}, {regr8,0}}},
509 /* opc12 c4 opc8 r copreg */
510 {"mtcr", 2, 0x301030, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copregr,0}}},
511 /* opc12 c4 opc8 copreg r */
512 {"mfcr", 2, 0x301031, 8, COP_REG_INS | FMT_2, {{i4,16}, {copregr,4}, {regr,0}}},
513 /* opc12 c4 opc8 r copsreg */
514 {"mtcsr", 2, 0x301032, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copsregr,0}}},
515 /* opc12 c4 opc8 copsreg r */
516 {"mfcsr", 2, 0x301033, 8, COP_REG_INS | FMT_2, {{i4,16}, {copsregr,4}, {regr,0}}},
517
518 /* CO-processor extensions */
519 /* opc12 c4 opc4 i4 disps9 */
520 {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d9,0}}},
521 /* opc12 c4 opc4 i4 disps25 */
522 {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d25,0}}},
523
524 /* opc12 i4 */
525 {"excp", 1, 0xFFF, 20, 0, {{i4,16}}},
526 /* opc28 i4 */
527 {"cinv", 2, 0x3010000, 4, 0, {{i4,0}}},
528
529 /* opc9 i5 i5 i5 r r */
530 {"ram", 2, 0x7C, 23, 0, {{i5,18}, {i5,13}, {i5,8}, {regr,4}, {regr,0}}},
531 {"rim", 2, 0x7D, 23, 0, {{i5,18}, {i5,13}, {i5,8}, {regr,4}, {regr,0}}},
532
533 /* opc9 i3 r */
534 {"rotb", 1, 0x1FB, 23, 0, {{i3,20}, {regr,16}}},
535 /* opc8 i4 r */
536 {"rotw", 1, 0xB9, 24, 0, {{i4,20}, {regr,16}}},
537 /* opc23 i5 r */
538 {"rotd", 2, 0x180478, 9, 0, {{i5,4}, {regr,0}}},
539
540 {NULL, 0, 0, 0, 0, {{0, 0}}}
541 };
542
543 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction);
544
545 /* Macro to build a reg_entry, which have an opcode image :
546 For example :
547 REG(u4, 0x84, CRX_U_REGTYPE)
548 is interpreted as :
549 {"u4", u4, 0x84, CRX_U_REGTYPE} */
550 #define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE}
551
552 const reg_entry crx_regtab[] =
553 {
554 /* Build a general purpose register r<N>. */
555 #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
556
557 REG_R(0), REG_R(1), REG_R(2), REG_R(3),
558 REG_R(4), REG_R(5), REG_R(6), REG_R(7),
559 REG_R(8), REG_R(9), REG_R(10), REG_R(11),
560 REG_R(12), REG_R(13), REG_R(14), REG_R(15),
561 REG(ra, 0xe, CRX_R_REGTYPE),
562 REG(sp, 0xf, CRX_R_REGTYPE),
563
564 /* Build a user register u<N>. */
565 #define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
566
567 REG_U(0), REG_U(1), REG_U(2), REG_U(3),
568 REG_U(4), REG_U(5), REG_U(6), REG_U(7),
569 REG_U(8), REG_U(9), REG_U(10), REG_U(11),
570 REG_U(12), REG_U(13), REG_U(14), REG_U(15),
571 REG(ura, 0x8e, CRX_U_REGTYPE),
572 REG(usp, 0x8f, CRX_U_REGTYPE),
573
574 /* Build a configuration register. */
575 #define REG_CFG(NAME, N) REG(NAME, N, CRX_CFG_REGTYPE)
576
577 REG_CFG(hi, 0x10),
578 REG_CFG(lo, 0x11),
579 REG_CFG(uhi, 0x90),
580 REG_CFG(ulo, 0x91),
581 REG_CFG(psr, 0x12),
582 REG_CFG(cfg, 0x15),
583 REG_CFG(cpcfg, 0x16),
584 REG_CFG(ccfg, 0x1b),
585
586 /* Build a mptr register. */
587 #define REG_MPTR(NAME, N) REG(NAME, N, CRX_MTPR_REGTYPE)
588
589 REG_MPTR(intbase, 0x13),
590 REG_MPTR(isp, 0x14),
591 REG_MPTR(cen, 0x17),
592
593 /* Build a pc register. */
594 #define REG_PC(NAME, N) REG(NAME, N, CRX_PC_REGTYPE)
595
596 REG_PC(pc, 0x0)
597 };
598
599 const int crx_num_regs = ARRAY_SIZE (crx_regtab);
600
601 const reg_entry crx_copregtab[] =
602 {
603 /* Build a Coprocessor register c<N>. */
604 #define REG_C(N) REG(CONCAT2(c,N), N, CRX_C_REGTYPE)
605
606 REG_C(0), REG_C(1), REG_C(2), REG_C(3),
607 REG_C(4), REG_C(5), REG_C(6), REG_C(7),
608 REG_C(8), REG_C(9), REG_C(10), REG_C(11),
609 REG_C(12), REG_C(13), REG_C(14), REG_C(15),
610
611 /* Build a Coprocessor Special register cs<N>. */
612 #define REG_CS(N) REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)
613
614 REG_CS(0), REG_CS(1), REG_CS(2), REG_CS(3),
615 REG_CS(4), REG_CS(5), REG_CS(6), REG_CS(7),
616 REG_CS(8), REG_CS(9), REG_CS(10), REG_CS(11),
617 REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15)
618 };
619
620 const int crx_num_copregs = ARRAY_SIZE (crx_copregtab);
621
622 /* CRX operands table. */
623 const operand_entry crx_optab[] =
624 {
625 /* Index 0 is dummy, so we can count the instruction's operands. */
626 {0, nullargs}, /* dummy */
627 {4, arg_ic}, /* cst4 */
628 {8, arg_c}, /* disps9 */
629 {3, arg_ic}, /* i3 */
630 {4, arg_ic}, /* i4 */
631 {5, arg_ic}, /* i5 */
632 {8, arg_ic}, /* i8 */
633 {12, arg_ic}, /* i12 */
634 {16, arg_ic}, /* i16 */
635 {32, arg_ic}, /* i32 */
636 {4, arg_c}, /* d5 */
637 {8, arg_c}, /* d9 */
638 {16, arg_c}, /* d17 */
639 {24, arg_c}, /* d25 */
640 {32, arg_c}, /* d33 */
641 {16, arg_c}, /* abs16 */
642 {32, arg_c}, /* abs32 */
643 {4, arg_rbase}, /* rbase */
644 {4, arg_cr}, /* rbase_cst4 */
645 {8, arg_cr}, /* rbase_dispu8 */
646 {12, arg_cr}, /* rbase_dispu12 */
647 {16, arg_cr}, /* rbase_dispu16 */
648 {28, arg_cr}, /* rbase_dispu28 */
649 {32, arg_cr}, /* rbase_dispu32 */
650 {6, arg_icr}, /* rbase_ridx_scl2_dispu6 */
651 {22, arg_icr}, /* rbase_ridx_scl2_dispu22 */
652 {4, arg_r}, /* regr */
653 {8, arg_r}, /* regr8 */
654 {4, arg_copr}, /* copregr */
655 {8, arg_copr}, /* copregr8 */
656 {4, arg_copsr} /* copsregr */
657 };
658
659 /* CRX traps/interrupts. */
660 const trap_entry crx_traps[] =
661 {
662 {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7},
663 {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12}
664 };
665
666 const int crx_num_traps = ARRAY_SIZE (crx_traps);
667
668 /* cst4 operand mapping. */
669 const cst4_entry cst4_map[] =
670 {
671 {0,0}, {1,1}, {2,2}, {3,3}, {4,4}, {5,-4}, {6,-1},
672 {7,7}, {8,8}, {9,16}, {10,32}, {11,20}, {12,12}, {13,48}
673 };
674
675 const int cst4_maps = ARRAY_SIZE (cst4_map);
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