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Changes from Jeff Law, law@cs.utah.edu:
[thirdparty/binutils-gdb.git] / opcodes / hppa-dis.c
1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2 Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
3
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #include "dis-asm.h"
22 #include "sysdep.h"
23 #include "opcode/hppa.h"
24
25 /* Initializer for an array of names of registers.
26 There should be NUM_REGS strings in this initializer. */
27
28 #define REGISTER_NAMES \
29 {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
30 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
31 "r20", "r21", "r22", "arg3", "arg2", "arg1", "arg0", "dp", "ret0", "ret1", \
32 "sp", "r31", "sar", "pcoqh", "pcsqh", "pcoqt", "pcsqt", \
33 "eiem", "iir", "isr", "ior", "ipsw", "goto", "sr4", "sr0", "sr1", "sr2", \
34 "sr3", "sr5", "sr6", "sr7", "cr0", "cr8", "cr9", "ccr", "cr12", "cr13", \
35 "cr24", "cr25", "cr26", "mpsfu_high", "mpsfu_low", "mpsfu_ovflo", "pad", \
36 "fpsr", "fpe1", "fpe2", "fpe3", "fpe4", "fpe5", "fpe6", "fpe7", \
37 "fp4", "fp5", "fp6", "fp7", "fp8", \
38 "fp9", "fp10", "fp11", "fp12", "fp13", "fp14", "fp15", \
39 "fp16", "fp17", "fp18", "fp19", "fp20", "fp21", "fp22", "fp23", \
40 "fp24", "fp25", "fp26", "fp27", "fp28", "fp29", "fp30", "fp31"}
41
42 static const char *const reg_names[] = REGISTER_NAMES;
43
44 typedef unsigned int CORE_ADDR;
45
46 /* Get at various relevent fields of an instruction word. */
47
48 #define MASK_5 0x1f
49 #define MASK_11 0x7ff
50 #define MASK_14 0x3fff
51 #define MASK_21 0x1fffff
52
53 /* This macro gets bit fields using HP's numbering (MSB = 0) */
54
55 #define GET_FIELD(X, FROM, TO) \
56 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
57
58 /* Some of these have been converted to 2-d arrays because they
59 consume less storage this way. If the maintenance becomes a
60 problem, convert them back to const 1-d pointer arrays. */
61 static const char control_reg[][6] = {
62 "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
63 "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
64 "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
65 "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
66 "tr4", "tr5", "tr6", "tr7"
67 };
68
69 static const char compare_cond_names[][5] = {
70 "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv",
71 ",od", ",tr", ",<>", ",>=", ",>", ",>>=",
72 ",>>", ",nsv", ",ev"
73 };
74 static const char add_cond_names[][5] = {
75 "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv",
76 ",od", ",tr", ",<>", ",>=", ",>", ",uv",
77 ",vnz", ",nsv", ",ev"
78 };
79 static const char *const logical_cond_names[] = {
80 "", ",=", ",<", ",<=", 0, 0, 0, ",od",
81 ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
82 static const char *const unit_cond_names[] = {
83 "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc",
84 ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc"
85 };
86 static const char shift_cond_names[][4] = {
87 "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
88 };
89 static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"};
90 static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"};
91 static const char *const short_bytes_compl_names[] = {
92 "", ",b,m", ",e", ",e,m"
93 };
94 static const char *const float_format_names[] = {",sgl", ",dbl", ",quad"};
95 static const char float_comp_names[][8] =
96 {
97 ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
98 ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
99 ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
100 ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
101 };
102
103 /* For a bunch of different instructions form an index into a
104 completer name table. */
105 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
106 GET_FIELD (insn, 18, 18) << 1)
107
108 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
109 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
110
111 /* Utility function to print registers. Put these first, so gcc's function
112 inlining can do its stuff. */
113
114 #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
115
116 static void
117 fput_reg (reg, info)
118 unsigned reg;
119 disassemble_info *info;
120 {
121 (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
122 }
123
124 static void
125 fput_reg_r (reg, info)
126 unsigned reg;
127 disassemble_info *info;
128 {
129 (*info->fprintf_func) (info->stream, "%sR", reg ? reg_names[reg] : "r0");
130 }
131
132 static void
133 fput_creg (reg, info)
134 unsigned reg;
135 disassemble_info *info;
136 {
137 (*info->fprintf_func) (info->stream, control_reg[reg]);
138 }
139
140 /* print constants with sign */
141
142 static void
143 fput_const (num, info)
144 unsigned num;
145 disassemble_info *info;
146 {
147 if ((int)num < 0)
148 (*info->fprintf_func) (info->stream, "-%x", -(int)num);
149 else
150 (*info->fprintf_func) (info->stream, "%x", num);
151 }
152
153 /* Routines to extract various sized constants out of hppa
154 instructions. */
155
156 /* This assumes that no garbage lies outside of the lower bits of
157 value. */
158
159 static int
160 sign_extend (val, bits)
161 unsigned val, bits;
162 {
163 return (int)(val >> (bits - 1) ? (-1 << bits) | val : val);
164 }
165
166 /* For many immediate values the sign bit is the low bit! */
167
168 static int
169 low_sign_extend (val, bits)
170 unsigned val, bits;
171 {
172 return (int)((val & 0x1 ? (-1 << (bits - 1)) : 0) | val >> 1);
173 }
174 /* extract the immediate field from a ld{bhw}s instruction */
175
176 #if 0 /* not used */
177 static unsigned
178 get_field (val, from, to)
179 unsigned val, from, to;
180 {
181 val = val >> (31 - to);
182 return val & ((1 << (32 - from)) - 1);
183 }
184
185 static unsigned
186 set_field (val, from, to, new_val)
187 unsigned *val, from, to, new_val;
188 {
189 unsigned mask = ~((1 << (to - from + 1)) << (31 - from));
190 return *val = (*val & mask) | (new_val << (31 - from));
191 }
192 #endif
193
194 /* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
195 static int
196 extract_3 (word)
197 unsigned word;
198 {
199 return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
200 }
201
202 static int
203 extract_5_load (word)
204 unsigned word;
205 {
206 return low_sign_extend (word >> 16 & MASK_5, 5);
207 }
208
209 /* extract the immediate field from a st{bhw}s instruction */
210 static int
211 extract_5_store (word)
212 unsigned word;
213 {
214 return low_sign_extend (word & MASK_5, 5);
215 }
216
217 /* extract the immediate field from a break instruction */
218 static unsigned
219 extract_5r_store (word)
220 unsigned word;
221 {
222 return (word & MASK_5);
223 }
224
225 /* extract the immediate field from a {sr}sm instruction */
226 static unsigned
227 extract_5R_store (word)
228 unsigned word;
229 {
230 return (word >> 16 & MASK_5);
231 }
232
233 /* extract the immediate field from a bb instruction */
234 static unsigned
235 extract_5Q_store (word)
236 unsigned word;
237 {
238 return (word >> 21 & MASK_5);
239 }
240
241 /* extract an 11 bit immediate field */
242 static int
243 extract_11 (word)
244 unsigned word;
245 {
246 return low_sign_extend (word & MASK_11, 11);
247 }
248
249 /* extract a 14 bit immediate field */
250 static int
251 extract_14 (word)
252 unsigned word;
253 {
254 return low_sign_extend (word & MASK_14, 14);
255 }
256
257 #if 0
258 /* deposit a 14 bit constant in a word */
259 static unsigned
260 deposit_14 (opnd, word)
261 int opnd;
262 unsigned word;
263 {
264 unsigned sign = (opnd < 0 ? 1 : 0);
265
266 return word | ((unsigned)opnd << 1 & MASK_14) | sign;
267 }
268 #endif
269
270 /* extract a 21 bit constant */
271
272 static int
273 extract_21 (word)
274 unsigned word;
275 {
276 int val;
277
278 word &= MASK_21;
279 word <<= 11;
280 val = GET_FIELD (word, 20, 20);
281 val <<= 11;
282 val |= GET_FIELD (word, 9, 19);
283 val <<= 2;
284 val |= GET_FIELD (word, 5, 6);
285 val <<= 5;
286 val |= GET_FIELD (word, 0, 4);
287 val <<= 2;
288 val |= GET_FIELD (word, 7, 8);
289 return sign_extend (val, 21) << 11;
290 }
291
292 #if 0
293 /* deposit a 21 bit constant in a word. Although 21 bit constants are
294 usually the top 21 bits of a 32 bit constant, we assume that only
295 the low 21 bits of opnd are relevant */
296
297 static unsigned
298 deposit_21 (opnd, word)
299 unsigned opnd, word;
300 {
301 unsigned val = 0;
302
303 val |= GET_FIELD (opnd, 11 + 14, 11 + 18);
304 val <<= 2;
305 val |= GET_FIELD (opnd, 11 + 12, 11 + 13);
306 val <<= 2;
307 val |= GET_FIELD (opnd, 11 + 19, 11 + 20);
308 val <<= 11;
309 val |= GET_FIELD (opnd, 11 + 1, 11 + 11);
310 val <<= 1;
311 val |= GET_FIELD (opnd, 11 + 0, 11 + 0);
312 return word | val;
313 }
314 #endif
315
316 /* extract a 12 bit constant from branch instructions */
317
318 static int
319 extract_12 (word)
320 unsigned word;
321 {
322 return sign_extend (GET_FIELD (word, 19, 28) |
323 GET_FIELD (word, 29, 29) << 10 |
324 (word & 0x1) << 11, 12) << 2;
325 }
326
327 /* extract a 17 bit constant from branch instructions, returning the
328 19 bit signed value. */
329
330 static int
331 extract_17 (word)
332 unsigned word;
333 {
334 return sign_extend (GET_FIELD (word, 19, 28) |
335 GET_FIELD (word, 29, 29) << 10 |
336 GET_FIELD (word, 11, 15) << 11 |
337 (word & 0x1) << 16, 17) << 2;
338 }
339
340 /* Print one instruction. */
341 int
342 print_insn_hppa (memaddr, info)
343 bfd_vma memaddr;
344 disassemble_info *info;
345 {
346 unsigned int insn, i, op;
347 FILE *stream = info->stream;
348
349 {
350 int status =
351 (*info->read_memory_func) (memaddr, (bfd_byte*) &insn, sizeof (insn),
352 info);
353 if (status != 0)
354 {
355 (*info->memory_error_func) (status, memaddr, info);
356 return -1;
357 }
358 }
359
360 for (i = 0; i < NUMOPCODES; ++i)
361 {
362 const struct pa_opcode *opcode = &pa_opcodes[i];
363 if ((insn & opcode->mask) == opcode->match)
364 {
365 register const char *s;
366
367 (*info->fprintf_func) (info->stream, "%s", opcode->name);
368
369 if (!strchr ("cCY<?!@-+&U>~nZFIMad", opcode->args[0]))
370 (*info->fprintf_func) (info->stream, " ");
371 for (s = opcode->args; *s != '\0'; ++s)
372 {
373 switch (*s)
374 {
375 case 'x':
376 fput_reg (GET_FIELD (insn, 11, 15), info);
377 break;
378 case 'X':
379 if (GET_FIELD (insn, 25, 25))
380 fput_reg_r (GET_FIELD (insn, 11, 15), info);
381 else
382 fput_reg (GET_FIELD (insn, 11, 15), info);
383 break;
384 case 'b':
385 fput_reg (GET_FIELD (insn, 6, 10), info);
386 break;
387 case '^':
388 fput_creg (GET_FIELD (insn, 6, 10), info);
389 break;
390 case 'E':
391 if (GET_FIELD (insn, 25, 25))
392 fput_reg_r (GET_FIELD (insn, 6, 10), info);
393 else
394 fput_reg (GET_FIELD (insn, 6, 10), info);
395 break;
396 case 't':
397 fput_reg (GET_FIELD (insn, 27, 31), info);
398 break;
399 case 'v':
400 if (GET_FIELD (insn, 25, 25))
401 fput_reg_r (GET_FIELD (insn, 27, 31), info);
402 else
403 fput_reg (GET_FIELD (insn, 27, 31), info);
404 break;
405 case '4':
406 fput_creg (GET_FIELD (insn, 6, 10), info);
407 break;
408 case '6':
409 fput_reg (GET_FIELD (insn, 11, 15), info);
410 break;
411 case '7':
412 fput_reg (GET_FIELD (insn, 27, 31), info);
413 break;
414 case '8':
415 fput_reg (GET_FIELD (insn, 16, 20), info);
416 break;
417 case '9':
418 fput_reg (GET_FIELD (insn, 21, 25), info);
419 break;
420 case '5':
421 fput_const (extract_5_load (insn), info);
422 break;
423 case 's':
424 fprintf_filtered (stream, "sr%d", GET_FIELD (insn, 16, 17));
425 break;
426 case 'S':
427 (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn));
428 break;
429 case 'c':
430 (*info->fprintf_func) (info->stream, "%s ",
431 index_compl_names[GET_COMPL (insn)]);
432 break;
433 case 'C':
434 (*info->fprintf_func) (info->stream, "%s ",
435 short_ldst_compl_names[GET_COMPL (insn)]);
436 break;
437 case 'Y':
438 (*info->fprintf_func) (info->stream, "%s ",
439 short_bytes_compl_names[GET_COMPL (insn)]);
440 break;
441 /* these four conditions are for the set of instructions
442 which distinguish true/false conditions by opcode rather
443 than by the 'f' bit (sigh): comb, comib, addb, addib */
444 case '<':
445 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
446 info);
447 break;
448 case '?':
449 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18) + 8],
450 info);
451 break;
452 case '@':
453 fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18) + 8],
454 info);
455 break;
456 case 'a':
457 (*info->fprintf_func) (info->stream, "%s",
458 compare_cond_names[GET_COND (insn)]);
459 break;
460 case 'd':
461 case '!':
462 (*info->fprintf_func) (info->stream, "%s",
463 add_cond_names[GET_FIELD (insn, 16, 18)]);
464 break;
465
466 case '&':
467 (*info->fprintf_func) (info->stream, "%s ",
468 logical_cond_names[GET_COND (insn)]);
469 break;
470 case 'U':
471 (*info->fprintf_func) (info->stream, "%s ",
472 unit_cond_names[GET_COND (insn)]);
473 break;
474 case '>':
475 case '~':
476 (*info->fprintf_func) (info->stream, "%s ",
477 shift_cond_names[GET_FIELD (insn, 16, 18)]);
478 break;
479 case 'V':
480 fput_const (extract_5_store (insn), info);
481 break;
482 case 'R':
483 fput_const (extract_5R_store (insn), info);
484 break;
485 case 'Q':
486 fput_const (extract_5Q_store (insn), info);
487 break;
488 case 'i':
489 fput_const (extract_11 (insn), info);
490 break;
491 case 'j':
492 fput_const (extract_14 (insn), info);
493 break;
494 case 'k':
495 fput_const (extract_21 (insn), info);
496 break;
497 case 'n':
498 if (insn & 0x2)
499 (*info->fprintf_func) (info->stream, ",n ");
500 else
501 (*info->fprintf_func) (info->stream, " ");
502 break;
503 case 'w':
504 (*info->print_address_func) (memaddr + 8 + extract_12 (insn),
505 info);
506 break;
507 case 'W':
508 /* don't interpret an address if it's an external branch
509 instruction. */
510 op = GET_FIELD (insn, 0, 5);
511 if (op != 0x38 /* be */ && op != 0x39 /* ble */)
512 (*info->print_address_func) ((memaddr + 8
513 + extract_17 (insn)),
514 info);
515 else
516 fput_const (extract_17 (insn), info);
517 break;
518 case 'p':
519 (*info->fprintf_func) (info->stream, "%d",
520 31 - GET_FIELD (insn, 22, 26));
521 break;
522 case 'P':
523 (*info->fprintf_func) (info->stream, "%d",
524 GET_FIELD (insn, 22, 26));
525 break;
526 case 'T':
527 (*info->fprintf_func) (info->stream, "%d",
528 32 - GET_FIELD (insn, 27, 31));
529 break;
530 case 'A':
531 fput_const (GET_FIELD (insn, 6, 18), info);
532 break;
533 case 'Z':
534 if (GET_FIELD (insn, 26, 26))
535 (*info->fprintf_func) (info->stream, ",m ");
536 else
537 (*info->fprintf_func) (info->stream, " ");
538 break;
539 case 'D':
540 fput_const (GET_FIELD (insn, 6, 31), info);
541 break;
542 case 'f':
543 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
544 break;
545 case 'O':
546 fput_const ((GET_FIELD (insn, 6,20) << 5 |
547 GET_FIELD (insn, 27, 31)), info);
548 break;
549 case 'o':
550 fput_const (GET_FIELD (insn, 6, 20), info);
551 break;
552 case '2':
553 fput_const ((GET_FIELD (insn, 6, 22) << 5 |
554 GET_FIELD (insn, 27, 31)), info);
555 break;
556 case '1':
557 fput_const ((GET_FIELD (insn, 11, 20) << 5 |
558 GET_FIELD (insn, 27, 31)), info);
559 break;
560 case '0':
561 fput_const ((GET_FIELD (insn, 16, 20) << 5 |
562 GET_FIELD (insn, 27, 31)), info);
563 break;
564 case 'u':
565 (*info->fprintf_func) (info->stream, "%d", GET_FIELD (insn, 23, 25));
566 break;
567 case 'F':
568 /* if no destination completer, need a space here */
569 if (GET_FIELD (insn, 21, 22) == 1)
570 fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)],
571 info);
572 else
573 (*info->fprintf_func) (info->stream, "%s ",
574 float_format_names[GET_FIELD
575 (insn, 19, 20)]);
576 break;
577 case 'G':
578 (*info->fprintf_func) (info->stream, "%s ",
579 float_format_names[GET_FIELD (insn,
580 17, 18)]);
581 break;
582 case 'H':
583 fputs_filtered (float_format_names[GET_FIELD
584 (insn, 26, 26)], info);
585 break;
586 case 'I':
587 /* if no destination completer, need a space here */
588 if (GET_FIELD (insn, 21, 22) == 1)
589 fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)],
590 info);
591 else
592 fprintf_filtered (stream, "%s ",
593 float_format_names[GET_FIELD
594 (insn, 20, 20)]);
595 break;
596 case 'J':
597 if (GET_FIELD (insn, 24, 24))
598 fput_reg_r (GET_FIELD (insn, 6, 10), info);
599 else
600 fput_reg (GET_FIELD (insn, 6, 10), info);
601
602 break;
603 case 'K':
604 if (GET_FIELD (insn, 19, 19))
605 fput_reg_r (GET_FIELD (insn, 11, 15), info);
606 else
607 fput_reg (GET_FIELD (insn, 11, 15), info);
608 break;
609 case 'M':
610 fputs_filtered (float_comp_names[GET_FIELD (insn, 27, 31)],
611 info);
612 break;
613 default:
614 (*info->fprintf_func) (info->stream, "%c", *s);
615 break;
616 }
617 }
618 return sizeof(insn);
619 }
620 }
621 (*info->fprintf_func) (info->stream, "#%8x", insn);
622 return sizeof(insn);
623 }