1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_MMX (int, int);
80 static void OP_XMM (int, int);
81 static void OP_EM (int, int);
82 static void OP_EX (int, int);
83 static void OP_EMC (int,int);
84 static void OP_MXC (int,int);
85 static void OP_MS (int, int);
86 static void OP_XS (int, int);
87 static void OP_M (int, int);
88 static void OP_VEX (int, int);
89 static void OP_VexR (int, int);
90 static void OP_VexW (int, int);
91 static void OP_Rounding (int, int);
92 static void OP_REG_VexI4 (int, int);
93 static void OP_VexI4 (int, int);
94 static void PCLMUL_Fixup (int, int);
95 static void VPCMP_Fixup (int, int);
96 static void VPCOM_Fixup (int, int);
97 static void OP_0f07 (int, int);
98 static void OP_Monitor (int, int);
99 static void OP_Mwait (int, int);
100 static void NOP_Fixup1 (int, int);
101 static void NOP_Fixup2 (int, int);
102 static void OP_3DNowSuffix (int, int);
103 static void CMP_Fixup (int, int);
104 static void BadOp (void);
105 static void REP_Fixup (int, int);
106 static void SEP_Fixup (int, int);
107 static void BND_Fixup (int, int);
108 static void NOTRACK_Fixup (int, int);
109 static void HLE_Fixup1 (int, int);
110 static void HLE_Fixup2 (int, int);
111 static void HLE_Fixup3 (int, int);
112 static void CMPXCHG8B_Fixup (int, int);
113 static void XMM_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
116 static void MOVSXD_Fixup (int, int);
117 static void DistinctDest_Fixup (int, int);
120 /* Points to first byte not fetched. */
121 bfd_byte
*max_fetched
;
122 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
125 OPCODES_SIGJMP_BUF bailout
;
135 enum address_mode address_mode
;
137 /* Flags for the prefixes for the current instruction. See below. */
140 /* REX prefix the current instruction. See below. */
142 /* Bits of REX we've already used. */
144 /* Mark parts used in the REX prefix. When we are testing for
145 empty prefix (for 8bit register REX extension), just mask it
146 out. Otherwise test for REX bit is excuse for existence of REX
147 only in case value is nonzero. */
148 #define USED_REX(value) \
153 rex_used |= (value) | REX_OPCODE; \
156 rex_used |= REX_OPCODE; \
159 /* Flags for prefixes which we somehow handled when printing the
160 current instruction. */
161 static int used_prefixes
;
163 /* Flags for EVEX bits which we somehow handled when printing the
164 current instruction. */
165 #define EVEX_b_used 1
166 static int evex_used
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 /* Possible values for prefix requirement. */
219 #define PREFIX_IGNORED_SHIFT 16
220 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
222 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
223 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
224 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
226 /* Opcode prefixes. */
227 #define PREFIX_OPCODE (PREFIX_REPZ \
231 /* Prefixes ignored. */
232 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
233 | PREFIX_IGNORED_REPNZ \
234 | PREFIX_IGNORED_DATA)
236 #define XX { NULL, 0 }
237 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
239 #define Eb { OP_E, b_mode }
240 #define Ebnd { OP_E, bnd_mode }
241 #define EbS { OP_E, b_swap_mode }
242 #define EbndS { OP_E, bnd_swap_mode }
243 #define Ev { OP_E, v_mode }
244 #define Eva { OP_E, va_mode }
245 #define Ev_bnd { OP_E, v_bnd_mode }
246 #define EvS { OP_E, v_swap_mode }
247 #define Ed { OP_E, d_mode }
248 #define Edq { OP_E, dq_mode }
249 #define Edb { OP_E, db_mode }
250 #define Edw { OP_E, dw_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define TMM { OP_XMM, tmm_mode }
352 #define XMxmmq { OP_XMM, xmmq_mode }
353 #define EM { OP_EM, v_mode }
354 #define EMS { OP_EM, v_swap_mode }
355 #define EMd { OP_EM, d_mode }
356 #define EMx { OP_EM, x_mode }
357 #define EXbwUnit { OP_EX, bw_unit_mode }
358 #define EXb { OP_EX, b_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdS { OP_EX, d_swap_mode }
362 #define EXwS { OP_EX, w_swap_mode }
363 #define EXq { OP_EX, q_mode }
364 #define EXqS { OP_EX, q_swap_mode }
365 #define EXdq { OP_EX, dq_mode }
366 #define EXx { OP_EX, x_mode }
367 #define EXxh { OP_EX, xh_mode }
368 #define EXxS { OP_EX, x_swap_mode }
369 #define EXxmm { OP_EX, xmm_mode }
370 #define EXymm { OP_EX, ymm_mode }
371 #define EXtmm { OP_EX, tmm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
374 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
375 #define EXxmmdw { OP_EX, xmmdw_mode }
376 #define EXxmmqd { OP_EX, xmmqd_mode }
377 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
378 #define EXymmq { OP_EX, ymmq_mode }
379 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
380 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
381 #define MS { OP_MS, v_mode }
382 #define XS { OP_XS, v_mode }
383 #define EMCq { OP_EMC, q_mode }
384 #define MXC { OP_MXC, 0 }
385 #define OPSUF { OP_3DNowSuffix, 0 }
386 #define SEP { SEP_Fixup, 0 }
387 #define CMP { CMP_Fixup, 0 }
388 #define XMM0 { XMM_Fixup, 0 }
389 #define FXSAVE { FXSAVE_Fixup, 0 }
391 #define Vex { OP_VEX, x_mode }
392 #define VexW { OP_VexW, x_mode }
393 #define VexScalar { OP_VEX, scalar_mode }
394 #define VexScalarR { OP_VexR, scalar_mode }
395 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
397 #define VexGdq { OP_VEX, dq_mode }
398 #define VexTmm { OP_VEX, tmm_mode }
399 #define XMVexI4 { OP_REG_VexI4, x_mode }
400 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
401 #define VexI4 { OP_VexI4, 0 }
402 #define PCLMUL { PCLMUL_Fixup, 0 }
403 #define VPCMP { VPCMP_Fixup, 0 }
404 #define VPCOM { VPCOM_Fixup, 0 }
406 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
407 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
408 #define EXxEVexS { OP_Rounding, evex_sae_mode }
410 #define MaskG { OP_G, mask_mode }
411 #define MaskE { OP_E, mask_mode }
412 #define MaskBDE { OP_E, mask_bd_mode }
413 #define MaskVex { OP_VEX, mask_mode }
415 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
416 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* word operand with operand swapped */
469 /* double word operand with operand swapped */
471 /* quad word operand */
473 /* quad word operand with operand swapped */
475 /* ten-byte operand */
477 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
478 broadcast enabled. */
480 /* Similar to x_mode, but with different EVEX mem shifts. */
482 /* Similar to x_mode, but with yet different EVEX mem shifts. */
484 /* Similar to x_mode, but with disabled broadcast. */
486 /* Similar to x_mode, but with operands swapped and disabled broadcast
489 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
490 broadcast of 16bit enabled. */
492 /* 16-byte XMM operand */
494 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
495 memory operand (depending on vector length). Broadcast isn't
498 /* Same as xmmq_mode, but broadcast is allowed. */
499 evex_half_bcst_xmmq_mode
,
500 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
501 memory operand (depending on vector length). 16bit broadcast. */
502 evex_half_bcst_xmmqh_mode
,
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 16-byte XMM, double word, quad word operand or xmm word operand.
509 evex_half_bcst_xmmqdh_mode
,
510 /* 32-byte YMM operand */
512 /* quad word, ymmword or zmmword memory operand. */
514 /* 32-byte YMM or 16-byte word operand */
518 /* d_mode in 32bit, q_mode in 64bit mode. */
520 /* pair of v_mode operands */
526 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
528 /* operand size depends on REX.W / VEX.W. */
530 /* Displacements like v_mode without considering Intel64 ISA. */
534 /* bounds operand with operand swapped */
536 /* 4- or 6-byte pointer operand */
539 /* v_mode for indirect branch opcodes. */
541 /* v_mode for stack-related opcodes. */
543 /* non-quad operand size depends on prefixes */
545 /* 16-byte operand */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
552 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
553 vex_vsib_d_w_dq_mode
,
554 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
555 vex_vsib_q_w_dq_mode
,
556 /* mandatory non-vector SIB. */
559 /* scalar, ignore vector length. */
562 /* Static rounding. */
564 /* Static rounding, 64-bit mode only. */
565 evex_rounding_64_mode
,
566 /* Supress all exceptions. */
569 /* Mask register operand. */
571 /* Mask register operand. */
639 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
641 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
642 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
643 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
644 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
645 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
646 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
647 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
648 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
649 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
650 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
651 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
652 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
653 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
654 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
655 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
656 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
683 REG_0F3A0F_PREFIX_1_MOD_3
,
696 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
701 REG_XOP_09_12_M_1_L_0
,
707 REG_EVEX_0F38C6_M_0_L_2
,
708 REG_EVEX_0F38C7_M_0_L_2
785 MOD_VEX_0F12_PREFIX_0
,
786 MOD_VEX_0F12_PREFIX_2
,
788 MOD_VEX_0F16_PREFIX_0
,
789 MOD_VEX_0F16_PREFIX_2
,
813 MOD_VEX_0FF0_PREFIX_3
,
820 MOD_VEX_0F3849_X86_64_P_0_W_0
,
821 MOD_VEX_0F3849_X86_64_P_2_W_0
,
822 MOD_VEX_0F3849_X86_64_P_3_W_0
,
823 MOD_VEX_0F384B_X86_64_P_1_W_0
,
824 MOD_VEX_0F384B_X86_64_P_2_W_0
,
825 MOD_VEX_0F384B_X86_64_P_3_W_0
,
827 MOD_VEX_0F385C_X86_64_P_1_W_0
,
828 MOD_VEX_0F385E_X86_64_P_0_W_0
,
829 MOD_VEX_0F385E_X86_64_P_1_W_0
,
830 MOD_VEX_0F385E_X86_64_P_2_W_0
,
831 MOD_VEX_0F385E_X86_64_P_3_W_0
,
841 MOD_EVEX_0F12_PREFIX_0
,
842 MOD_EVEX_0F12_PREFIX_2
,
844 MOD_EVEX_0F16_PREFIX_0
,
845 MOD_EVEX_0F16_PREFIX_2
,
851 MOD_EVEX_0F382A_P_1_W_1
,
853 MOD_EVEX_0F383A_P_1_W_0
,
873 RM_0F1E_P_1_MOD_3_REG_7
,
874 RM_0FAE_REG_6_MOD_3_P_0
,
876 RM_0F3A0F_P_1_MOD_3_REG_0
,
878 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
884 PREFIX_0F01_REG_1_RM_4
,
885 PREFIX_0F01_REG_1_RM_5
,
886 PREFIX_0F01_REG_1_RM_6
,
887 PREFIX_0F01_REG_1_RM_7
,
888 PREFIX_0F01_REG_3_RM_1
,
889 PREFIX_0F01_REG_5_MOD_0
,
890 PREFIX_0F01_REG_5_MOD_3_RM_0
,
891 PREFIX_0F01_REG_5_MOD_3_RM_1
,
892 PREFIX_0F01_REG_5_MOD_3_RM_2
,
893 PREFIX_0F01_REG_5_MOD_3_RM_4
,
894 PREFIX_0F01_REG_5_MOD_3_RM_5
,
895 PREFIX_0F01_REG_5_MOD_3_RM_6
,
896 PREFIX_0F01_REG_5_MOD_3_RM_7
,
897 PREFIX_0F01_REG_7_MOD_3_RM_2
,
898 PREFIX_0F01_REG_7_MOD_3_RM_6
,
899 PREFIX_0F01_REG_7_MOD_3_RM_7
,
937 PREFIX_0FAE_REG_0_MOD_3
,
938 PREFIX_0FAE_REG_1_MOD_3
,
939 PREFIX_0FAE_REG_2_MOD_3
,
940 PREFIX_0FAE_REG_3_MOD_3
,
941 PREFIX_0FAE_REG_4_MOD_0
,
942 PREFIX_0FAE_REG_4_MOD_3
,
943 PREFIX_0FAE_REG_5_MOD_3
,
944 PREFIX_0FAE_REG_6_MOD_0
,
945 PREFIX_0FAE_REG_6_MOD_3
,
946 PREFIX_0FAE_REG_7_MOD_0
,
951 PREFIX_0FC7_REG_6_MOD_0
,
952 PREFIX_0FC7_REG_6_MOD_3
,
953 PREFIX_0FC7_REG_7_MOD_3
,
981 PREFIX_VEX_0F41_L_1_M_1_W_0
,
982 PREFIX_VEX_0F41_L_1_M_1_W_1
,
983 PREFIX_VEX_0F42_L_1_M_1_W_0
,
984 PREFIX_VEX_0F42_L_1_M_1_W_1
,
985 PREFIX_VEX_0F44_L_0_M_1_W_0
,
986 PREFIX_VEX_0F44_L_0_M_1_W_1
,
987 PREFIX_VEX_0F45_L_1_M_1_W_0
,
988 PREFIX_VEX_0F45_L_1_M_1_W_1
,
989 PREFIX_VEX_0F46_L_1_M_1_W_0
,
990 PREFIX_VEX_0F46_L_1_M_1_W_1
,
991 PREFIX_VEX_0F47_L_1_M_1_W_0
,
992 PREFIX_VEX_0F47_L_1_M_1_W_1
,
993 PREFIX_VEX_0F4A_L_1_M_1_W_0
,
994 PREFIX_VEX_0F4A_L_1_M_1_W_1
,
995 PREFIX_VEX_0F4B_L_1_M_1_W_0
,
996 PREFIX_VEX_0F4B_L_1_M_1_W_1
,
1014 PREFIX_VEX_0F90_L_0_W_0
,
1015 PREFIX_VEX_0F90_L_0_W_1
,
1016 PREFIX_VEX_0F91_L_0_M_0_W_0
,
1017 PREFIX_VEX_0F91_L_0_M_0_W_1
,
1018 PREFIX_VEX_0F92_L_0_M_1_W_0
,
1019 PREFIX_VEX_0F92_L_0_M_1_W_1
,
1020 PREFIX_VEX_0F93_L_0_M_1_W_0
,
1021 PREFIX_VEX_0F93_L_0_M_1_W_1
,
1022 PREFIX_VEX_0F98_L_0_M_1_W_0
,
1023 PREFIX_VEX_0F98_L_0_M_1_W_1
,
1024 PREFIX_VEX_0F99_L_0_M_1_W_0
,
1025 PREFIX_VEX_0F99_L_0_M_1_W_1
,
1030 PREFIX_VEX_0F3849_X86_64
,
1031 PREFIX_VEX_0F384B_X86_64
,
1032 PREFIX_VEX_0F385C_X86_64
,
1033 PREFIX_VEX_0F385E_X86_64
,
1034 PREFIX_VEX_0F38F5_L_0
,
1035 PREFIX_VEX_0F38F6_L_0
,
1036 PREFIX_VEX_0F38F7_L_0
,
1037 PREFIX_VEX_0F3AF0_L_0
,
1098 PREFIX_EVEX_0F3A08_W_0
,
1099 PREFIX_EVEX_0F3A0A_W_0
,
1108 PREFIX_EVEX_MAP5_10
,
1109 PREFIX_EVEX_MAP5_11
,
1110 PREFIX_EVEX_MAP5_1D
,
1111 PREFIX_EVEX_MAP5_2A
,
1112 PREFIX_EVEX_MAP5_2C
,
1113 PREFIX_EVEX_MAP5_2D
,
1114 PREFIX_EVEX_MAP5_2E
,
1115 PREFIX_EVEX_MAP5_2F
,
1116 PREFIX_EVEX_MAP5_51
,
1117 PREFIX_EVEX_MAP5_58
,
1118 PREFIX_EVEX_MAP5_59
,
1119 PREFIX_EVEX_MAP5_5A_W_0
,
1120 PREFIX_EVEX_MAP5_5A_W_1
,
1121 PREFIX_EVEX_MAP5_5B_W_0
,
1122 PREFIX_EVEX_MAP5_5B_W_1
,
1123 PREFIX_EVEX_MAP5_5C
,
1124 PREFIX_EVEX_MAP5_5D
,
1125 PREFIX_EVEX_MAP5_5E
,
1126 PREFIX_EVEX_MAP5_5F
,
1127 PREFIX_EVEX_MAP5_78
,
1128 PREFIX_EVEX_MAP5_79
,
1129 PREFIX_EVEX_MAP5_7A
,
1130 PREFIX_EVEX_MAP5_7B
,
1131 PREFIX_EVEX_MAP5_7C
,
1132 PREFIX_EVEX_MAP5_7D_W_0
,
1134 PREFIX_EVEX_MAP6_13
,
1135 PREFIX_EVEX_MAP6_56
,
1136 PREFIX_EVEX_MAP6_57
,
1137 PREFIX_EVEX_MAP6_D6
,
1138 PREFIX_EVEX_MAP6_D7
,
1174 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1175 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1176 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1179 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1180 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1181 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1182 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1183 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1184 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1185 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1188 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
,
1198 THREE_BYTE_0F38
= 0,
1227 VEX_LEN_0F12_P_0_M_0
= 0,
1228 VEX_LEN_0F12_P_0_M_1
,
1229 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1231 VEX_LEN_0F16_P_0_M_0
,
1232 VEX_LEN_0F16_P_0_M_1
,
1233 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1253 VEX_LEN_0FAE_R_2_M_0
,
1254 VEX_LEN_0FAE_R_3_M_0
,
1264 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1265 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1266 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1267 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1268 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1269 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1270 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1272 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1273 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1274 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1275 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1276 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1309 VEX_LEN_0FXOP_08_85
,
1310 VEX_LEN_0FXOP_08_86
,
1311 VEX_LEN_0FXOP_08_87
,
1312 VEX_LEN_0FXOP_08_8E
,
1313 VEX_LEN_0FXOP_08_8F
,
1314 VEX_LEN_0FXOP_08_95
,
1315 VEX_LEN_0FXOP_08_96
,
1316 VEX_LEN_0FXOP_08_97
,
1317 VEX_LEN_0FXOP_08_9E
,
1318 VEX_LEN_0FXOP_08_9F
,
1319 VEX_LEN_0FXOP_08_A3
,
1320 VEX_LEN_0FXOP_08_A6
,
1321 VEX_LEN_0FXOP_08_B6
,
1322 VEX_LEN_0FXOP_08_C0
,
1323 VEX_LEN_0FXOP_08_C1
,
1324 VEX_LEN_0FXOP_08_C2
,
1325 VEX_LEN_0FXOP_08_C3
,
1326 VEX_LEN_0FXOP_08_CC
,
1327 VEX_LEN_0FXOP_08_CD
,
1328 VEX_LEN_0FXOP_08_CE
,
1329 VEX_LEN_0FXOP_08_CF
,
1330 VEX_LEN_0FXOP_08_EC
,
1331 VEX_LEN_0FXOP_08_ED
,
1332 VEX_LEN_0FXOP_08_EE
,
1333 VEX_LEN_0FXOP_08_EF
,
1334 VEX_LEN_0FXOP_09_01
,
1335 VEX_LEN_0FXOP_09_02
,
1336 VEX_LEN_0FXOP_09_12_M_1
,
1337 VEX_LEN_0FXOP_09_82_W_0
,
1338 VEX_LEN_0FXOP_09_83_W_0
,
1339 VEX_LEN_0FXOP_09_90
,
1340 VEX_LEN_0FXOP_09_91
,
1341 VEX_LEN_0FXOP_09_92
,
1342 VEX_LEN_0FXOP_09_93
,
1343 VEX_LEN_0FXOP_09_94
,
1344 VEX_LEN_0FXOP_09_95
,
1345 VEX_LEN_0FXOP_09_96
,
1346 VEX_LEN_0FXOP_09_97
,
1347 VEX_LEN_0FXOP_09_98
,
1348 VEX_LEN_0FXOP_09_99
,
1349 VEX_LEN_0FXOP_09_9A
,
1350 VEX_LEN_0FXOP_09_9B
,
1351 VEX_LEN_0FXOP_09_C1
,
1352 VEX_LEN_0FXOP_09_C2
,
1353 VEX_LEN_0FXOP_09_C3
,
1354 VEX_LEN_0FXOP_09_C6
,
1355 VEX_LEN_0FXOP_09_C7
,
1356 VEX_LEN_0FXOP_09_CB
,
1357 VEX_LEN_0FXOP_09_D1
,
1358 VEX_LEN_0FXOP_09_D2
,
1359 VEX_LEN_0FXOP_09_D3
,
1360 VEX_LEN_0FXOP_09_D6
,
1361 VEX_LEN_0FXOP_09_D7
,
1362 VEX_LEN_0FXOP_09_DB
,
1363 VEX_LEN_0FXOP_09_E1
,
1364 VEX_LEN_0FXOP_09_E2
,
1365 VEX_LEN_0FXOP_09_E3
,
1366 VEX_LEN_0FXOP_0A_12
,
1371 EVEX_LEN_0F3816
= 0,
1373 EVEX_LEN_0F381A_M_0
,
1374 EVEX_LEN_0F381B_M_0
,
1376 EVEX_LEN_0F385A_M_0
,
1377 EVEX_LEN_0F385B_M_0
,
1378 EVEX_LEN_0F38C6_M_0
,
1379 EVEX_LEN_0F38C7_M_0
,
1396 VEX_W_0F41_L_1_M_1
= 0,
1418 VEX_W_0F381A_M_0_L_1
,
1425 VEX_W_0F3849_X86_64_P_0
,
1426 VEX_W_0F3849_X86_64_P_2
,
1427 VEX_W_0F3849_X86_64_P_3
,
1428 VEX_W_0F384B_X86_64_P_1
,
1429 VEX_W_0F384B_X86_64_P_2
,
1430 VEX_W_0F384B_X86_64_P_3
,
1437 VEX_W_0F385A_M_0_L_0
,
1438 VEX_W_0F385C_X86_64_P_1
,
1439 VEX_W_0F385E_X86_64_P_0
,
1440 VEX_W_0F385E_X86_64_P_1
,
1441 VEX_W_0F385E_X86_64_P_2
,
1442 VEX_W_0F385E_X86_64_P_3
,
1464 VEX_W_0FXOP_08_85_L_0
,
1465 VEX_W_0FXOP_08_86_L_0
,
1466 VEX_W_0FXOP_08_87_L_0
,
1467 VEX_W_0FXOP_08_8E_L_0
,
1468 VEX_W_0FXOP_08_8F_L_0
,
1469 VEX_W_0FXOP_08_95_L_0
,
1470 VEX_W_0FXOP_08_96_L_0
,
1471 VEX_W_0FXOP_08_97_L_0
,
1472 VEX_W_0FXOP_08_9E_L_0
,
1473 VEX_W_0FXOP_08_9F_L_0
,
1474 VEX_W_0FXOP_08_A6_L_0
,
1475 VEX_W_0FXOP_08_B6_L_0
,
1476 VEX_W_0FXOP_08_C0_L_0
,
1477 VEX_W_0FXOP_08_C1_L_0
,
1478 VEX_W_0FXOP_08_C2_L_0
,
1479 VEX_W_0FXOP_08_C3_L_0
,
1480 VEX_W_0FXOP_08_CC_L_0
,
1481 VEX_W_0FXOP_08_CD_L_0
,
1482 VEX_W_0FXOP_08_CE_L_0
,
1483 VEX_W_0FXOP_08_CF_L_0
,
1484 VEX_W_0FXOP_08_EC_L_0
,
1485 VEX_W_0FXOP_08_ED_L_0
,
1486 VEX_W_0FXOP_08_EE_L_0
,
1487 VEX_W_0FXOP_08_EF_L_0
,
1493 VEX_W_0FXOP_09_C1_L_0
,
1494 VEX_W_0FXOP_09_C2_L_0
,
1495 VEX_W_0FXOP_09_C3_L_0
,
1496 VEX_W_0FXOP_09_C6_L_0
,
1497 VEX_W_0FXOP_09_C7_L_0
,
1498 VEX_W_0FXOP_09_CB_L_0
,
1499 VEX_W_0FXOP_09_D1_L_0
,
1500 VEX_W_0FXOP_09_D2_L_0
,
1501 VEX_W_0FXOP_09_D3_L_0
,
1502 VEX_W_0FXOP_09_D6_L_0
,
1503 VEX_W_0FXOP_09_D7_L_0
,
1504 VEX_W_0FXOP_09_DB_L_0
,
1505 VEX_W_0FXOP_09_E1_L_0
,
1506 VEX_W_0FXOP_09_E2_L_0
,
1507 VEX_W_0FXOP_09_E3_L_0
,
1513 EVEX_W_0F12_P_0_M_1
,
1516 EVEX_W_0F16_P_0_M_1
,
1594 EVEX_W_0F381A_M_0_L_n
,
1595 EVEX_W_0F381B_M_0_L_2
,
1621 EVEX_W_0F385A_M_0_L_n
,
1622 EVEX_W_0F385B_M_0_L_2
,
1668 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1677 unsigned int prefix_requirement
;
1680 /* Upper case letters in the instruction names here are macros.
1681 'A' => print 'b' if no register operands or suffix_always is true
1682 'B' => print 'b' if suffix_always is true
1683 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1685 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1686 suffix_always is true
1687 'E' => print 'e' if 32-bit form of jcxz
1688 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1689 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1690 'H' => print ",pt" or ",pn" branch hint
1693 'K' => print 'd' or 'q' if rex prefix is present.
1695 'M' => print 'r' if intel_mnemonic is false.
1696 'N' => print 'n' if instruction has no wait "prefix"
1697 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1698 'P' => behave as 'T' except with register operand outside of suffix_always
1700 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1702 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1703 'S' => print 'w', 'l' or 'q' if suffix_always is true
1704 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1705 prefix or if suffix_always is true.
1708 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1709 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1711 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1712 '!' => change condition from true to false or from false to true.
1713 '%' => add 1 upper case letter to the macro.
1714 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1715 prefix or suffix_always is true (lcall/ljmp).
1716 '@' => in 64bit mode for Intel64 ISA or if instruction
1717 has no operand sizing prefix, print 'q' if suffix_always is true or
1718 nothing otherwise; behave as 'P' in all other cases
1720 2 upper case letter macros:
1721 "XY" => print 'x' or 'y' if suffix_always is true or no register
1722 operands and no broadcast.
1723 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1724 register operands and no broadcast.
1725 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1726 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1727 "XV" => print "{vex3}" pseudo prefix
1728 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1729 being false, or no operand at all in 64bit mode, or if suffix_always
1731 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1732 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1733 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1734 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1735 "BW" => print 'b' or 'w' depending on the VEX.W bit
1736 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1737 an operand size prefix, or suffix_always is true. print
1738 'q' if rex prefix is present.
1740 Many of the above letters print nothing in Intel mode. See "putop"
1743 Braces '{' and '}', and vertical bars '|', indicate alternative
1744 mnemonic strings for AT&T and Intel. */
1746 static const struct dis386 dis386
[] = {
1748 { "addB", { Ebh1
, Gb
}, 0 },
1749 { "addS", { Evh1
, Gv
}, 0 },
1750 { "addB", { Gb
, EbS
}, 0 },
1751 { "addS", { Gv
, EvS
}, 0 },
1752 { "addB", { AL
, Ib
}, 0 },
1753 { "addS", { eAX
, Iv
}, 0 },
1754 { X86_64_TABLE (X86_64_06
) },
1755 { X86_64_TABLE (X86_64_07
) },
1757 { "orB", { Ebh1
, Gb
}, 0 },
1758 { "orS", { Evh1
, Gv
}, 0 },
1759 { "orB", { Gb
, EbS
}, 0 },
1760 { "orS", { Gv
, EvS
}, 0 },
1761 { "orB", { AL
, Ib
}, 0 },
1762 { "orS", { eAX
, Iv
}, 0 },
1763 { X86_64_TABLE (X86_64_0E
) },
1764 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1766 { "adcB", { Ebh1
, Gb
}, 0 },
1767 { "adcS", { Evh1
, Gv
}, 0 },
1768 { "adcB", { Gb
, EbS
}, 0 },
1769 { "adcS", { Gv
, EvS
}, 0 },
1770 { "adcB", { AL
, Ib
}, 0 },
1771 { "adcS", { eAX
, Iv
}, 0 },
1772 { X86_64_TABLE (X86_64_16
) },
1773 { X86_64_TABLE (X86_64_17
) },
1775 { "sbbB", { Ebh1
, Gb
}, 0 },
1776 { "sbbS", { Evh1
, Gv
}, 0 },
1777 { "sbbB", { Gb
, EbS
}, 0 },
1778 { "sbbS", { Gv
, EvS
}, 0 },
1779 { "sbbB", { AL
, Ib
}, 0 },
1780 { "sbbS", { eAX
, Iv
}, 0 },
1781 { X86_64_TABLE (X86_64_1E
) },
1782 { X86_64_TABLE (X86_64_1F
) },
1784 { "andB", { Ebh1
, Gb
}, 0 },
1785 { "andS", { Evh1
, Gv
}, 0 },
1786 { "andB", { Gb
, EbS
}, 0 },
1787 { "andS", { Gv
, EvS
}, 0 },
1788 { "andB", { AL
, Ib
}, 0 },
1789 { "andS", { eAX
, Iv
}, 0 },
1790 { Bad_Opcode
}, /* SEG ES prefix */
1791 { X86_64_TABLE (X86_64_27
) },
1793 { "subB", { Ebh1
, Gb
}, 0 },
1794 { "subS", { Evh1
, Gv
}, 0 },
1795 { "subB", { Gb
, EbS
}, 0 },
1796 { "subS", { Gv
, EvS
}, 0 },
1797 { "subB", { AL
, Ib
}, 0 },
1798 { "subS", { eAX
, Iv
}, 0 },
1799 { Bad_Opcode
}, /* SEG CS prefix */
1800 { X86_64_TABLE (X86_64_2F
) },
1802 { "xorB", { Ebh1
, Gb
}, 0 },
1803 { "xorS", { Evh1
, Gv
}, 0 },
1804 { "xorB", { Gb
, EbS
}, 0 },
1805 { "xorS", { Gv
, EvS
}, 0 },
1806 { "xorB", { AL
, Ib
}, 0 },
1807 { "xorS", { eAX
, Iv
}, 0 },
1808 { Bad_Opcode
}, /* SEG SS prefix */
1809 { X86_64_TABLE (X86_64_37
) },
1811 { "cmpB", { Eb
, Gb
}, 0 },
1812 { "cmpS", { Ev
, Gv
}, 0 },
1813 { "cmpB", { Gb
, EbS
}, 0 },
1814 { "cmpS", { Gv
, EvS
}, 0 },
1815 { "cmpB", { AL
, Ib
}, 0 },
1816 { "cmpS", { eAX
, Iv
}, 0 },
1817 { Bad_Opcode
}, /* SEG DS prefix */
1818 { X86_64_TABLE (X86_64_3F
) },
1820 { "inc{S|}", { RMeAX
}, 0 },
1821 { "inc{S|}", { RMeCX
}, 0 },
1822 { "inc{S|}", { RMeDX
}, 0 },
1823 { "inc{S|}", { RMeBX
}, 0 },
1824 { "inc{S|}", { RMeSP
}, 0 },
1825 { "inc{S|}", { RMeBP
}, 0 },
1826 { "inc{S|}", { RMeSI
}, 0 },
1827 { "inc{S|}", { RMeDI
}, 0 },
1829 { "dec{S|}", { RMeAX
}, 0 },
1830 { "dec{S|}", { RMeCX
}, 0 },
1831 { "dec{S|}", { RMeDX
}, 0 },
1832 { "dec{S|}", { RMeBX
}, 0 },
1833 { "dec{S|}", { RMeSP
}, 0 },
1834 { "dec{S|}", { RMeBP
}, 0 },
1835 { "dec{S|}", { RMeSI
}, 0 },
1836 { "dec{S|}", { RMeDI
}, 0 },
1838 { "push{!P|}", { RMrAX
}, 0 },
1839 { "push{!P|}", { RMrCX
}, 0 },
1840 { "push{!P|}", { RMrDX
}, 0 },
1841 { "push{!P|}", { RMrBX
}, 0 },
1842 { "push{!P|}", { RMrSP
}, 0 },
1843 { "push{!P|}", { RMrBP
}, 0 },
1844 { "push{!P|}", { RMrSI
}, 0 },
1845 { "push{!P|}", { RMrDI
}, 0 },
1847 { "pop{!P|}", { RMrAX
}, 0 },
1848 { "pop{!P|}", { RMrCX
}, 0 },
1849 { "pop{!P|}", { RMrDX
}, 0 },
1850 { "pop{!P|}", { RMrBX
}, 0 },
1851 { "pop{!P|}", { RMrSP
}, 0 },
1852 { "pop{!P|}", { RMrBP
}, 0 },
1853 { "pop{!P|}", { RMrSI
}, 0 },
1854 { "pop{!P|}", { RMrDI
}, 0 },
1856 { X86_64_TABLE (X86_64_60
) },
1857 { X86_64_TABLE (X86_64_61
) },
1858 { X86_64_TABLE (X86_64_62
) },
1859 { X86_64_TABLE (X86_64_63
) },
1860 { Bad_Opcode
}, /* seg fs */
1861 { Bad_Opcode
}, /* seg gs */
1862 { Bad_Opcode
}, /* op size prefix */
1863 { Bad_Opcode
}, /* adr size prefix */
1865 { "pushP", { sIv
}, 0 },
1866 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1867 { "pushP", { sIbT
}, 0 },
1868 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1869 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1870 { X86_64_TABLE (X86_64_6D
) },
1871 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1872 { X86_64_TABLE (X86_64_6F
) },
1874 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1875 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1876 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1877 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1878 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1879 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1880 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1881 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1883 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1884 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1885 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1886 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1887 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1888 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1889 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1890 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1892 { REG_TABLE (REG_80
) },
1893 { REG_TABLE (REG_81
) },
1894 { X86_64_TABLE (X86_64_82
) },
1895 { REG_TABLE (REG_83
) },
1896 { "testB", { Eb
, Gb
}, 0 },
1897 { "testS", { Ev
, Gv
}, 0 },
1898 { "xchgB", { Ebh2
, Gb
}, 0 },
1899 { "xchgS", { Evh2
, Gv
}, 0 },
1901 { "movB", { Ebh3
, Gb
}, 0 },
1902 { "movS", { Evh3
, Gv
}, 0 },
1903 { "movB", { Gb
, EbS
}, 0 },
1904 { "movS", { Gv
, EvS
}, 0 },
1905 { "movD", { Sv
, Sw
}, 0 },
1906 { MOD_TABLE (MOD_8D
) },
1907 { "movD", { Sw
, Sv
}, 0 },
1908 { REG_TABLE (REG_8F
) },
1910 { PREFIX_TABLE (PREFIX_90
) },
1911 { "xchgS", { RMeCX
, eAX
}, 0 },
1912 { "xchgS", { RMeDX
, eAX
}, 0 },
1913 { "xchgS", { RMeBX
, eAX
}, 0 },
1914 { "xchgS", { RMeSP
, eAX
}, 0 },
1915 { "xchgS", { RMeBP
, eAX
}, 0 },
1916 { "xchgS", { RMeSI
, eAX
}, 0 },
1917 { "xchgS", { RMeDI
, eAX
}, 0 },
1919 { "cW{t|}R", { XX
}, 0 },
1920 { "cR{t|}O", { XX
}, 0 },
1921 { X86_64_TABLE (X86_64_9A
) },
1922 { Bad_Opcode
}, /* fwait */
1923 { "pushfP", { XX
}, 0 },
1924 { "popfP", { XX
}, 0 },
1925 { "sahf", { XX
}, 0 },
1926 { "lahf", { XX
}, 0 },
1928 { "mov%LB", { AL
, Ob
}, 0 },
1929 { "mov%LS", { eAX
, Ov
}, 0 },
1930 { "mov%LB", { Ob
, AL
}, 0 },
1931 { "mov%LS", { Ov
, eAX
}, 0 },
1932 { "movs{b|}", { Ybr
, Xb
}, 0 },
1933 { "movs{R|}", { Yvr
, Xv
}, 0 },
1934 { "cmps{b|}", { Xb
, Yb
}, 0 },
1935 { "cmps{R|}", { Xv
, Yv
}, 0 },
1937 { "testB", { AL
, Ib
}, 0 },
1938 { "testS", { eAX
, Iv
}, 0 },
1939 { "stosB", { Ybr
, AL
}, 0 },
1940 { "stosS", { Yvr
, eAX
}, 0 },
1941 { "lodsB", { ALr
, Xb
}, 0 },
1942 { "lodsS", { eAXr
, Xv
}, 0 },
1943 { "scasB", { AL
, Yb
}, 0 },
1944 { "scasS", { eAX
, Yv
}, 0 },
1946 { "movB", { RMAL
, Ib
}, 0 },
1947 { "movB", { RMCL
, Ib
}, 0 },
1948 { "movB", { RMDL
, Ib
}, 0 },
1949 { "movB", { RMBL
, Ib
}, 0 },
1950 { "movB", { RMAH
, Ib
}, 0 },
1951 { "movB", { RMCH
, Ib
}, 0 },
1952 { "movB", { RMDH
, Ib
}, 0 },
1953 { "movB", { RMBH
, Ib
}, 0 },
1955 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1956 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1957 { "mov%LV", { RMeDX
, Iv64
}, 0 },
1958 { "mov%LV", { RMeBX
, Iv64
}, 0 },
1959 { "mov%LV", { RMeSP
, Iv64
}, 0 },
1960 { "mov%LV", { RMeBP
, Iv64
}, 0 },
1961 { "mov%LV", { RMeSI
, Iv64
}, 0 },
1962 { "mov%LV", { RMeDI
, Iv64
}, 0 },
1964 { REG_TABLE (REG_C0
) },
1965 { REG_TABLE (REG_C1
) },
1966 { X86_64_TABLE (X86_64_C2
) },
1967 { X86_64_TABLE (X86_64_C3
) },
1968 { X86_64_TABLE (X86_64_C4
) },
1969 { X86_64_TABLE (X86_64_C5
) },
1970 { REG_TABLE (REG_C6
) },
1971 { REG_TABLE (REG_C7
) },
1973 { "enterP", { Iw
, Ib
}, 0 },
1974 { "leaveP", { XX
}, 0 },
1975 { "{l|}ret{|f}%LP", { Iw
}, 0 },
1976 { "{l|}ret{|f}%LP", { XX
}, 0 },
1977 { "int3", { XX
}, 0 },
1978 { "int", { Ib
}, 0 },
1979 { X86_64_TABLE (X86_64_CE
) },
1980 { "iret%LP", { XX
}, 0 },
1982 { REG_TABLE (REG_D0
) },
1983 { REG_TABLE (REG_D1
) },
1984 { REG_TABLE (REG_D2
) },
1985 { REG_TABLE (REG_D3
) },
1986 { X86_64_TABLE (X86_64_D4
) },
1987 { X86_64_TABLE (X86_64_D5
) },
1989 { "xlat", { DSBX
}, 0 },
2000 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2001 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2002 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2003 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2004 { "inB", { AL
, Ib
}, 0 },
2005 { "inG", { zAX
, Ib
}, 0 },
2006 { "outB", { Ib
, AL
}, 0 },
2007 { "outG", { Ib
, zAX
}, 0 },
2009 { X86_64_TABLE (X86_64_E8
) },
2010 { X86_64_TABLE (X86_64_E9
) },
2011 { X86_64_TABLE (X86_64_EA
) },
2012 { "jmp", { Jb
, BND
}, 0 },
2013 { "inB", { AL
, indirDX
}, 0 },
2014 { "inG", { zAX
, indirDX
}, 0 },
2015 { "outB", { indirDX
, AL
}, 0 },
2016 { "outG", { indirDX
, zAX
}, 0 },
2018 { Bad_Opcode
}, /* lock prefix */
2019 { "int1", { XX
}, 0 },
2020 { Bad_Opcode
}, /* repne */
2021 { Bad_Opcode
}, /* repz */
2022 { "hlt", { XX
}, 0 },
2023 { "cmc", { XX
}, 0 },
2024 { REG_TABLE (REG_F6
) },
2025 { REG_TABLE (REG_F7
) },
2027 { "clc", { XX
}, 0 },
2028 { "stc", { XX
}, 0 },
2029 { "cli", { XX
}, 0 },
2030 { "sti", { XX
}, 0 },
2031 { "cld", { XX
}, 0 },
2032 { "std", { XX
}, 0 },
2033 { REG_TABLE (REG_FE
) },
2034 { REG_TABLE (REG_FF
) },
2037 static const struct dis386 dis386_twobyte
[] = {
2039 { REG_TABLE (REG_0F00
) },
2040 { REG_TABLE (REG_0F01
) },
2041 { "larS", { Gv
, Ew
}, 0 },
2042 { "lslS", { Gv
, Ew
}, 0 },
2044 { "syscall", { XX
}, 0 },
2045 { "clts", { XX
}, 0 },
2046 { "sysret%LQ", { XX
}, 0 },
2048 { "invd", { XX
}, 0 },
2049 { PREFIX_TABLE (PREFIX_0F09
) },
2051 { "ud2", { XX
}, 0 },
2053 { REG_TABLE (REG_0F0D
) },
2054 { "femms", { XX
}, 0 },
2055 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2057 { PREFIX_TABLE (PREFIX_0F10
) },
2058 { PREFIX_TABLE (PREFIX_0F11
) },
2059 { PREFIX_TABLE (PREFIX_0F12
) },
2060 { MOD_TABLE (MOD_0F13
) },
2061 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2062 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2063 { PREFIX_TABLE (PREFIX_0F16
) },
2064 { MOD_TABLE (MOD_0F17
) },
2066 { REG_TABLE (REG_0F18
) },
2067 { "nopQ", { Ev
}, 0 },
2068 { PREFIX_TABLE (PREFIX_0F1A
) },
2069 { PREFIX_TABLE (PREFIX_0F1B
) },
2070 { PREFIX_TABLE (PREFIX_0F1C
) },
2071 { "nopQ", { Ev
}, 0 },
2072 { PREFIX_TABLE (PREFIX_0F1E
) },
2073 { "nopQ", { Ev
}, 0 },
2075 { "movZ", { Em
, Cm
}, 0 },
2076 { "movZ", { Em
, Dm
}, 0 },
2077 { "movZ", { Cm
, Em
}, 0 },
2078 { "movZ", { Dm
, Em
}, 0 },
2079 { X86_64_TABLE (X86_64_0F24
) },
2081 { X86_64_TABLE (X86_64_0F26
) },
2084 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2085 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2086 { PREFIX_TABLE (PREFIX_0F2A
) },
2087 { PREFIX_TABLE (PREFIX_0F2B
) },
2088 { PREFIX_TABLE (PREFIX_0F2C
) },
2089 { PREFIX_TABLE (PREFIX_0F2D
) },
2090 { PREFIX_TABLE (PREFIX_0F2E
) },
2091 { PREFIX_TABLE (PREFIX_0F2F
) },
2093 { "wrmsr", { XX
}, 0 },
2094 { "rdtsc", { XX
}, 0 },
2095 { "rdmsr", { XX
}, 0 },
2096 { "rdpmc", { XX
}, 0 },
2097 { "sysenter", { SEP
}, 0 },
2098 { "sysexit%LQ", { SEP
}, 0 },
2100 { "getsec", { XX
}, 0 },
2102 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2104 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2111 { "cmovoS", { Gv
, Ev
}, 0 },
2112 { "cmovnoS", { Gv
, Ev
}, 0 },
2113 { "cmovbS", { Gv
, Ev
}, 0 },
2114 { "cmovaeS", { Gv
, Ev
}, 0 },
2115 { "cmoveS", { Gv
, Ev
}, 0 },
2116 { "cmovneS", { Gv
, Ev
}, 0 },
2117 { "cmovbeS", { Gv
, Ev
}, 0 },
2118 { "cmovaS", { Gv
, Ev
}, 0 },
2120 { "cmovsS", { Gv
, Ev
}, 0 },
2121 { "cmovnsS", { Gv
, Ev
}, 0 },
2122 { "cmovpS", { Gv
, Ev
}, 0 },
2123 { "cmovnpS", { Gv
, Ev
}, 0 },
2124 { "cmovlS", { Gv
, Ev
}, 0 },
2125 { "cmovgeS", { Gv
, Ev
}, 0 },
2126 { "cmovleS", { Gv
, Ev
}, 0 },
2127 { "cmovgS", { Gv
, Ev
}, 0 },
2129 { MOD_TABLE (MOD_0F50
) },
2130 { PREFIX_TABLE (PREFIX_0F51
) },
2131 { PREFIX_TABLE (PREFIX_0F52
) },
2132 { PREFIX_TABLE (PREFIX_0F53
) },
2133 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2134 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2135 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2136 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2138 { PREFIX_TABLE (PREFIX_0F58
) },
2139 { PREFIX_TABLE (PREFIX_0F59
) },
2140 { PREFIX_TABLE (PREFIX_0F5A
) },
2141 { PREFIX_TABLE (PREFIX_0F5B
) },
2142 { PREFIX_TABLE (PREFIX_0F5C
) },
2143 { PREFIX_TABLE (PREFIX_0F5D
) },
2144 { PREFIX_TABLE (PREFIX_0F5E
) },
2145 { PREFIX_TABLE (PREFIX_0F5F
) },
2147 { PREFIX_TABLE (PREFIX_0F60
) },
2148 { PREFIX_TABLE (PREFIX_0F61
) },
2149 { PREFIX_TABLE (PREFIX_0F62
) },
2150 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2151 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2152 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2153 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2154 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2156 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2157 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2158 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2159 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2160 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2161 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2162 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2163 { PREFIX_TABLE (PREFIX_0F6F
) },
2165 { PREFIX_TABLE (PREFIX_0F70
) },
2166 { MOD_TABLE (MOD_0F71
) },
2167 { MOD_TABLE (MOD_0F72
) },
2168 { MOD_TABLE (MOD_0F73
) },
2169 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2170 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2171 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2172 { "emms", { XX
}, PREFIX_OPCODE
},
2174 { PREFIX_TABLE (PREFIX_0F78
) },
2175 { PREFIX_TABLE (PREFIX_0F79
) },
2178 { PREFIX_TABLE (PREFIX_0F7C
) },
2179 { PREFIX_TABLE (PREFIX_0F7D
) },
2180 { PREFIX_TABLE (PREFIX_0F7E
) },
2181 { PREFIX_TABLE (PREFIX_0F7F
) },
2183 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2184 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2185 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2186 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2187 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2188 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2189 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2190 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2192 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2193 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2194 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2195 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2196 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2197 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2198 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2199 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2201 { "seto", { Eb
}, 0 },
2202 { "setno", { Eb
}, 0 },
2203 { "setb", { Eb
}, 0 },
2204 { "setae", { Eb
}, 0 },
2205 { "sete", { Eb
}, 0 },
2206 { "setne", { Eb
}, 0 },
2207 { "setbe", { Eb
}, 0 },
2208 { "seta", { Eb
}, 0 },
2210 { "sets", { Eb
}, 0 },
2211 { "setns", { Eb
}, 0 },
2212 { "setp", { Eb
}, 0 },
2213 { "setnp", { Eb
}, 0 },
2214 { "setl", { Eb
}, 0 },
2215 { "setge", { Eb
}, 0 },
2216 { "setle", { Eb
}, 0 },
2217 { "setg", { Eb
}, 0 },
2219 { "pushP", { fs
}, 0 },
2220 { "popP", { fs
}, 0 },
2221 { "cpuid", { XX
}, 0 },
2222 { "btS", { Ev
, Gv
}, 0 },
2223 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2224 { "shldS", { Ev
, Gv
, CL
}, 0 },
2225 { REG_TABLE (REG_0FA6
) },
2226 { REG_TABLE (REG_0FA7
) },
2228 { "pushP", { gs
}, 0 },
2229 { "popP", { gs
}, 0 },
2230 { "rsm", { XX
}, 0 },
2231 { "btsS", { Evh1
, Gv
}, 0 },
2232 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2233 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2234 { REG_TABLE (REG_0FAE
) },
2235 { "imulS", { Gv
, Ev
}, 0 },
2237 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2238 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2239 { MOD_TABLE (MOD_0FB2
) },
2240 { "btrS", { Evh1
, Gv
}, 0 },
2241 { MOD_TABLE (MOD_0FB4
) },
2242 { MOD_TABLE (MOD_0FB5
) },
2243 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2244 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2246 { PREFIX_TABLE (PREFIX_0FB8
) },
2247 { "ud1S", { Gv
, Ev
}, 0 },
2248 { REG_TABLE (REG_0FBA
) },
2249 { "btcS", { Evh1
, Gv
}, 0 },
2250 { PREFIX_TABLE (PREFIX_0FBC
) },
2251 { PREFIX_TABLE (PREFIX_0FBD
) },
2252 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2253 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2255 { "xaddB", { Ebh1
, Gb
}, 0 },
2256 { "xaddS", { Evh1
, Gv
}, 0 },
2257 { PREFIX_TABLE (PREFIX_0FC2
) },
2258 { MOD_TABLE (MOD_0FC3
) },
2259 { "pinsrw", { MX
, Edw
, Ib
}, PREFIX_OPCODE
},
2260 { "pextrw", { Gd
, MS
, Ib
}, PREFIX_OPCODE
},
2261 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2262 { REG_TABLE (REG_0FC7
) },
2264 { "bswap", { RMeAX
}, 0 },
2265 { "bswap", { RMeCX
}, 0 },
2266 { "bswap", { RMeDX
}, 0 },
2267 { "bswap", { RMeBX
}, 0 },
2268 { "bswap", { RMeSP
}, 0 },
2269 { "bswap", { RMeBP
}, 0 },
2270 { "bswap", { RMeSI
}, 0 },
2271 { "bswap", { RMeDI
}, 0 },
2273 { PREFIX_TABLE (PREFIX_0FD0
) },
2274 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2275 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2276 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2277 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2278 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2279 { PREFIX_TABLE (PREFIX_0FD6
) },
2280 { MOD_TABLE (MOD_0FD7
) },
2282 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2283 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2284 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2285 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2286 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2287 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2288 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2289 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2291 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2292 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2293 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2294 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2295 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2296 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2297 { PREFIX_TABLE (PREFIX_0FE6
) },
2298 { PREFIX_TABLE (PREFIX_0FE7
) },
2300 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2301 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2302 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2303 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2304 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2305 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2306 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2307 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2309 { PREFIX_TABLE (PREFIX_0FF0
) },
2310 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2311 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2312 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2313 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2314 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2315 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2316 { PREFIX_TABLE (PREFIX_0FF7
) },
2318 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2319 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2320 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2321 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2322 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2323 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2324 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2325 { "ud0S", { Gv
, Ev
}, 0 },
2328 static const unsigned char onebyte_has_modrm
[256] = {
2329 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2330 /* ------------------------------- */
2331 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2332 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2333 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2334 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2335 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2336 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2337 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2338 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2339 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2340 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2341 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2342 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2343 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2344 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2345 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2346 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2347 /* ------------------------------- */
2348 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2351 static const unsigned char twobyte_has_modrm
[256] = {
2352 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2353 /* ------------------------------- */
2354 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2355 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2356 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2357 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2358 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2359 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2360 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2361 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2362 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2363 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2364 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2365 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2366 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2367 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2368 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2369 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2370 /* ------------------------------- */
2371 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2374 static char obuf
[100];
2376 static char *mnemonicendp
;
2377 static char scratchbuf
[100];
2378 static unsigned char *start_codep
;
2379 static unsigned char *insn_codep
;
2380 static unsigned char *codep
;
2381 static unsigned char *end_codep
;
2382 static int last_lock_prefix
;
2383 static int last_repz_prefix
;
2384 static int last_repnz_prefix
;
2385 static int last_data_prefix
;
2386 static int last_addr_prefix
;
2387 static int last_rex_prefix
;
2388 static int last_seg_prefix
;
2389 static int fwait_prefix
;
2390 /* The active segment register prefix. */
2391 static int active_seg_prefix
;
2392 #define MAX_CODE_LENGTH 15
2393 /* We can up to 14 prefixes since the maximum instruction length is
2395 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2396 static disassemble_info
*the_info
;
2404 static unsigned char need_modrm
;
2414 int register_specifier
;
2421 int mask_register_specifier
;
2428 static unsigned char need_vex
;
2436 /* If we are accessing mod/rm/reg without need_modrm set, then the
2437 values are stale. Hitting this abort likely indicates that you
2438 need to update onebyte_has_modrm or twobyte_has_modrm. */
2439 #define MODRM_CHECK if (!need_modrm) abort ()
2441 static const char **names64
;
2442 static const char **names32
;
2443 static const char **names16
;
2444 static const char **names8
;
2445 static const char **names8rex
;
2446 static const char **names_seg
;
2447 static const char *index64
;
2448 static const char *index32
;
2449 static const char **index16
;
2450 static const char **names_bnd
;
2452 static const char *intel_names64
[] = {
2453 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2454 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2456 static const char *intel_names32
[] = {
2457 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2458 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2460 static const char *intel_names16
[] = {
2461 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2462 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2464 static const char *intel_names8
[] = {
2465 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2467 static const char *intel_names8rex
[] = {
2468 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2469 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2471 static const char *intel_names_seg
[] = {
2472 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2474 static const char *intel_index64
= "riz";
2475 static const char *intel_index32
= "eiz";
2476 static const char *intel_index16
[] = {
2477 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2480 static const char *att_names64
[] = {
2481 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2482 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2484 static const char *att_names32
[] = {
2485 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2486 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2488 static const char *att_names16
[] = {
2489 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2490 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2492 static const char *att_names8
[] = {
2493 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2495 static const char *att_names8rex
[] = {
2496 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2497 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2499 static const char *att_names_seg
[] = {
2500 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2502 static const char *att_index64
= "%riz";
2503 static const char *att_index32
= "%eiz";
2504 static const char *att_index16
[] = {
2505 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2508 static const char **names_mm
;
2509 static const char *intel_names_mm
[] = {
2510 "mm0", "mm1", "mm2", "mm3",
2511 "mm4", "mm5", "mm6", "mm7"
2513 static const char *att_names_mm
[] = {
2514 "%mm0", "%mm1", "%mm2", "%mm3",
2515 "%mm4", "%mm5", "%mm6", "%mm7"
2518 static const char *intel_names_bnd
[] = {
2519 "bnd0", "bnd1", "bnd2", "bnd3"
2522 static const char *att_names_bnd
[] = {
2523 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2526 static const char **names_xmm
;
2527 static const char *intel_names_xmm
[] = {
2528 "xmm0", "xmm1", "xmm2", "xmm3",
2529 "xmm4", "xmm5", "xmm6", "xmm7",
2530 "xmm8", "xmm9", "xmm10", "xmm11",
2531 "xmm12", "xmm13", "xmm14", "xmm15",
2532 "xmm16", "xmm17", "xmm18", "xmm19",
2533 "xmm20", "xmm21", "xmm22", "xmm23",
2534 "xmm24", "xmm25", "xmm26", "xmm27",
2535 "xmm28", "xmm29", "xmm30", "xmm31"
2537 static const char *att_names_xmm
[] = {
2538 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2539 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2540 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2541 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2542 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2543 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2544 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2545 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2548 static const char **names_ymm
;
2549 static const char *intel_names_ymm
[] = {
2550 "ymm0", "ymm1", "ymm2", "ymm3",
2551 "ymm4", "ymm5", "ymm6", "ymm7",
2552 "ymm8", "ymm9", "ymm10", "ymm11",
2553 "ymm12", "ymm13", "ymm14", "ymm15",
2554 "ymm16", "ymm17", "ymm18", "ymm19",
2555 "ymm20", "ymm21", "ymm22", "ymm23",
2556 "ymm24", "ymm25", "ymm26", "ymm27",
2557 "ymm28", "ymm29", "ymm30", "ymm31"
2559 static const char *att_names_ymm
[] = {
2560 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2561 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2562 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2563 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2564 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2565 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2566 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2567 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2570 static const char **names_zmm
;
2571 static const char *intel_names_zmm
[] = {
2572 "zmm0", "zmm1", "zmm2", "zmm3",
2573 "zmm4", "zmm5", "zmm6", "zmm7",
2574 "zmm8", "zmm9", "zmm10", "zmm11",
2575 "zmm12", "zmm13", "zmm14", "zmm15",
2576 "zmm16", "zmm17", "zmm18", "zmm19",
2577 "zmm20", "zmm21", "zmm22", "zmm23",
2578 "zmm24", "zmm25", "zmm26", "zmm27",
2579 "zmm28", "zmm29", "zmm30", "zmm31"
2581 static const char *att_names_zmm
[] = {
2582 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2583 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2584 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2585 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2586 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2587 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2588 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2589 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2592 static const char **names_tmm
;
2593 static const char *intel_names_tmm
[] = {
2594 "tmm0", "tmm1", "tmm2", "tmm3",
2595 "tmm4", "tmm5", "tmm6", "tmm7"
2597 static const char *att_names_tmm
[] = {
2598 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2599 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2602 static const char **names_mask
;
2603 static const char *intel_names_mask
[] = {
2604 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2606 static const char *att_names_mask
[] = {
2607 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2610 static const char *const names_rounding
[] =
2618 static const struct dis386 reg_table
[][8] = {
2621 { "addA", { Ebh1
, Ib
}, 0 },
2622 { "orA", { Ebh1
, Ib
}, 0 },
2623 { "adcA", { Ebh1
, Ib
}, 0 },
2624 { "sbbA", { Ebh1
, Ib
}, 0 },
2625 { "andA", { Ebh1
, Ib
}, 0 },
2626 { "subA", { Ebh1
, Ib
}, 0 },
2627 { "xorA", { Ebh1
, Ib
}, 0 },
2628 { "cmpA", { Eb
, Ib
}, 0 },
2632 { "addQ", { Evh1
, Iv
}, 0 },
2633 { "orQ", { Evh1
, Iv
}, 0 },
2634 { "adcQ", { Evh1
, Iv
}, 0 },
2635 { "sbbQ", { Evh1
, Iv
}, 0 },
2636 { "andQ", { Evh1
, Iv
}, 0 },
2637 { "subQ", { Evh1
, Iv
}, 0 },
2638 { "xorQ", { Evh1
, Iv
}, 0 },
2639 { "cmpQ", { Ev
, Iv
}, 0 },
2643 { "addQ", { Evh1
, sIb
}, 0 },
2644 { "orQ", { Evh1
, sIb
}, 0 },
2645 { "adcQ", { Evh1
, sIb
}, 0 },
2646 { "sbbQ", { Evh1
, sIb
}, 0 },
2647 { "andQ", { Evh1
, sIb
}, 0 },
2648 { "subQ", { Evh1
, sIb
}, 0 },
2649 { "xorQ", { Evh1
, sIb
}, 0 },
2650 { "cmpQ", { Ev
, sIb
}, 0 },
2654 { "pop{P|}", { stackEv
}, 0 },
2655 { XOP_8F_TABLE (XOP_09
) },
2659 { XOP_8F_TABLE (XOP_09
) },
2663 { "rolA", { Eb
, Ib
}, 0 },
2664 { "rorA", { Eb
, Ib
}, 0 },
2665 { "rclA", { Eb
, Ib
}, 0 },
2666 { "rcrA", { Eb
, Ib
}, 0 },
2667 { "shlA", { Eb
, Ib
}, 0 },
2668 { "shrA", { Eb
, Ib
}, 0 },
2669 { "shlA", { Eb
, Ib
}, 0 },
2670 { "sarA", { Eb
, Ib
}, 0 },
2674 { "rolQ", { Ev
, Ib
}, 0 },
2675 { "rorQ", { Ev
, Ib
}, 0 },
2676 { "rclQ", { Ev
, Ib
}, 0 },
2677 { "rcrQ", { Ev
, Ib
}, 0 },
2678 { "shlQ", { Ev
, Ib
}, 0 },
2679 { "shrQ", { Ev
, Ib
}, 0 },
2680 { "shlQ", { Ev
, Ib
}, 0 },
2681 { "sarQ", { Ev
, Ib
}, 0 },
2685 { "movA", { Ebh3
, Ib
}, 0 },
2692 { MOD_TABLE (MOD_C6_REG_7
) },
2696 { "movQ", { Evh3
, Iv
}, 0 },
2703 { MOD_TABLE (MOD_C7_REG_7
) },
2707 { "rolA", { Eb
, I1
}, 0 },
2708 { "rorA", { Eb
, I1
}, 0 },
2709 { "rclA", { Eb
, I1
}, 0 },
2710 { "rcrA", { Eb
, I1
}, 0 },
2711 { "shlA", { Eb
, I1
}, 0 },
2712 { "shrA", { Eb
, I1
}, 0 },
2713 { "shlA", { Eb
, I1
}, 0 },
2714 { "sarA", { Eb
, I1
}, 0 },
2718 { "rolQ", { Ev
, I1
}, 0 },
2719 { "rorQ", { Ev
, I1
}, 0 },
2720 { "rclQ", { Ev
, I1
}, 0 },
2721 { "rcrQ", { Ev
, I1
}, 0 },
2722 { "shlQ", { Ev
, I1
}, 0 },
2723 { "shrQ", { Ev
, I1
}, 0 },
2724 { "shlQ", { Ev
, I1
}, 0 },
2725 { "sarQ", { Ev
, I1
}, 0 },
2729 { "rolA", { Eb
, CL
}, 0 },
2730 { "rorA", { Eb
, CL
}, 0 },
2731 { "rclA", { Eb
, CL
}, 0 },
2732 { "rcrA", { Eb
, CL
}, 0 },
2733 { "shlA", { Eb
, CL
}, 0 },
2734 { "shrA", { Eb
, CL
}, 0 },
2735 { "shlA", { Eb
, CL
}, 0 },
2736 { "sarA", { Eb
, CL
}, 0 },
2740 { "rolQ", { Ev
, CL
}, 0 },
2741 { "rorQ", { Ev
, CL
}, 0 },
2742 { "rclQ", { Ev
, CL
}, 0 },
2743 { "rcrQ", { Ev
, CL
}, 0 },
2744 { "shlQ", { Ev
, CL
}, 0 },
2745 { "shrQ", { Ev
, CL
}, 0 },
2746 { "shlQ", { Ev
, CL
}, 0 },
2747 { "sarQ", { Ev
, CL
}, 0 },
2751 { "testA", { Eb
, Ib
}, 0 },
2752 { "testA", { Eb
, Ib
}, 0 },
2753 { "notA", { Ebh1
}, 0 },
2754 { "negA", { Ebh1
}, 0 },
2755 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2756 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2757 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2758 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2762 { "testQ", { Ev
, Iv
}, 0 },
2763 { "testQ", { Ev
, Iv
}, 0 },
2764 { "notQ", { Evh1
}, 0 },
2765 { "negQ", { Evh1
}, 0 },
2766 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2767 { "imulQ", { Ev
}, 0 },
2768 { "divQ", { Ev
}, 0 },
2769 { "idivQ", { Ev
}, 0 },
2773 { "incA", { Ebh1
}, 0 },
2774 { "decA", { Ebh1
}, 0 },
2778 { "incQ", { Evh1
}, 0 },
2779 { "decQ", { Evh1
}, 0 },
2780 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2781 { MOD_TABLE (MOD_FF_REG_3
) },
2782 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2783 { MOD_TABLE (MOD_FF_REG_5
) },
2784 { "push{P|}", { stackEv
}, 0 },
2789 { "sldtD", { Sv
}, 0 },
2790 { "strD", { Sv
}, 0 },
2791 { "lldt", { Ew
}, 0 },
2792 { "ltr", { Ew
}, 0 },
2793 { "verr", { Ew
}, 0 },
2794 { "verw", { Ew
}, 0 },
2800 { MOD_TABLE (MOD_0F01_REG_0
) },
2801 { MOD_TABLE (MOD_0F01_REG_1
) },
2802 { MOD_TABLE (MOD_0F01_REG_2
) },
2803 { MOD_TABLE (MOD_0F01_REG_3
) },
2804 { "smswD", { Sv
}, 0 },
2805 { MOD_TABLE (MOD_0F01_REG_5
) },
2806 { "lmsw", { Ew
}, 0 },
2807 { MOD_TABLE (MOD_0F01_REG_7
) },
2811 { "prefetch", { Mb
}, 0 },
2812 { "prefetchw", { Mb
}, 0 },
2813 { "prefetchwt1", { Mb
}, 0 },
2814 { "prefetch", { Mb
}, 0 },
2815 { "prefetch", { Mb
}, 0 },
2816 { "prefetch", { Mb
}, 0 },
2817 { "prefetch", { Mb
}, 0 },
2818 { "prefetch", { Mb
}, 0 },
2822 { MOD_TABLE (MOD_0F18_REG_0
) },
2823 { MOD_TABLE (MOD_0F18_REG_1
) },
2824 { MOD_TABLE (MOD_0F18_REG_2
) },
2825 { MOD_TABLE (MOD_0F18_REG_3
) },
2826 { "nopQ", { Ev
}, 0 },
2827 { "nopQ", { Ev
}, 0 },
2828 { "nopQ", { Ev
}, 0 },
2829 { "nopQ", { Ev
}, 0 },
2831 /* REG_0F1C_P_0_MOD_0 */
2833 { "cldemote", { Mb
}, 0 },
2834 { "nopQ", { Ev
}, 0 },
2835 { "nopQ", { Ev
}, 0 },
2836 { "nopQ", { Ev
}, 0 },
2837 { "nopQ", { Ev
}, 0 },
2838 { "nopQ", { Ev
}, 0 },
2839 { "nopQ", { Ev
}, 0 },
2840 { "nopQ", { Ev
}, 0 },
2842 /* REG_0F1E_P_1_MOD_3 */
2844 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2845 { "rdsspK", { Edq
}, 0 },
2846 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2847 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2848 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2849 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2850 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2851 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2853 /* REG_0F38D8_PREFIX_1 */
2855 { "aesencwide128kl", { M
}, 0 },
2856 { "aesdecwide128kl", { M
}, 0 },
2857 { "aesencwide256kl", { M
}, 0 },
2858 { "aesdecwide256kl", { M
}, 0 },
2860 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2862 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2864 /* REG_0F71_MOD_0 */
2868 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
2870 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
2872 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
2874 /* REG_0F72_MOD_0 */
2878 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
2880 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
2882 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
2884 /* REG_0F73_MOD_0 */
2888 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
2889 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
2892 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
2893 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
2897 { "montmul", { { OP_0f07
, 0 } }, 0 },
2898 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2899 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2903 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2904 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2905 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2906 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2907 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2908 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2912 { MOD_TABLE (MOD_0FAE_REG_0
) },
2913 { MOD_TABLE (MOD_0FAE_REG_1
) },
2914 { MOD_TABLE (MOD_0FAE_REG_2
) },
2915 { MOD_TABLE (MOD_0FAE_REG_3
) },
2916 { MOD_TABLE (MOD_0FAE_REG_4
) },
2917 { MOD_TABLE (MOD_0FAE_REG_5
) },
2918 { MOD_TABLE (MOD_0FAE_REG_6
) },
2919 { MOD_TABLE (MOD_0FAE_REG_7
) },
2927 { "btQ", { Ev
, Ib
}, 0 },
2928 { "btsQ", { Evh1
, Ib
}, 0 },
2929 { "btrQ", { Evh1
, Ib
}, 0 },
2930 { "btcQ", { Evh1
, Ib
}, 0 },
2935 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2937 { MOD_TABLE (MOD_0FC7_REG_3
) },
2938 { MOD_TABLE (MOD_0FC7_REG_4
) },
2939 { MOD_TABLE (MOD_0FC7_REG_5
) },
2940 { MOD_TABLE (MOD_0FC7_REG_6
) },
2941 { MOD_TABLE (MOD_0FC7_REG_7
) },
2943 /* REG_VEX_0F71_M_0 */
2947 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2949 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2951 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2953 /* REG_VEX_0F72_M_0 */
2957 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2959 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2961 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2963 /* REG_VEX_0F73_M_0 */
2967 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2968 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2971 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2972 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2978 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2979 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2981 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2983 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
2985 /* REG_VEX_0F38F3_L_0 */
2988 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2989 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2990 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2992 /* REG_XOP_09_01_L_0 */
2995 { "blcfill", { VexGdq
, Edq
}, 0 },
2996 { "blsfill", { VexGdq
, Edq
}, 0 },
2997 { "blcs", { VexGdq
, Edq
}, 0 },
2998 { "tzmsk", { VexGdq
, Edq
}, 0 },
2999 { "blcic", { VexGdq
, Edq
}, 0 },
3000 { "blsic", { VexGdq
, Edq
}, 0 },
3001 { "t1mskc", { VexGdq
, Edq
}, 0 },
3003 /* REG_XOP_09_02_L_0 */
3006 { "blcmsk", { VexGdq
, Edq
}, 0 },
3011 { "blci", { VexGdq
, Edq
}, 0 },
3013 /* REG_XOP_09_12_M_1_L_0 */
3015 { "llwpcb", { Edq
}, 0 },
3016 { "slwpcb", { Edq
}, 0 },
3018 /* REG_XOP_0A_12_L_0 */
3020 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3021 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3024 #include "i386-dis-evex-reg.h"
3027 static const struct dis386 prefix_table
[][4] = {
3030 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3031 { "pause", { XX
}, 0 },
3032 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3033 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3036 /* PREFIX_0F01_REG_1_RM_4 */
3040 { "tdcall", { Skip_MODRM
}, 0 },
3044 /* PREFIX_0F01_REG_1_RM_5 */
3048 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
3052 /* PREFIX_0F01_REG_1_RM_6 */
3056 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3060 /* PREFIX_0F01_REG_1_RM_7 */
3062 { "encls", { Skip_MODRM
}, 0 },
3064 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3068 /* PREFIX_0F01_REG_3_RM_1 */
3070 { "vmmcall", { Skip_MODRM
}, 0 },
3071 { "vmgexit", { Skip_MODRM
}, 0 },
3073 { "vmgexit", { Skip_MODRM
}, 0 },
3076 /* PREFIX_0F01_REG_5_MOD_0 */
3079 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3082 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3084 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3085 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3087 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3090 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3095 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3098 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3101 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3104 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3107 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3110 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3113 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3116 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3118 { "rdpkru", { Skip_MODRM
}, 0 },
3119 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3122 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3124 { "wrpkru", { Skip_MODRM
}, 0 },
3125 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3128 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3130 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3131 { "mcommit", { Skip_MODRM
}, 0 },
3134 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3136 { "invlpgb", { Skip_MODRM
}, 0 },
3137 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3139 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3142 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3144 { "tlbsync", { Skip_MODRM
}, 0 },
3145 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3147 { "pvalidate", { Skip_MODRM
}, 0 },
3152 { "wbinvd", { XX
}, 0 },
3153 { "wbnoinvd", { XX
}, 0 },
3158 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3159 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3160 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3161 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3166 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3167 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3168 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3169 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3174 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3175 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3176 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3177 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3182 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3183 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3184 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3189 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3190 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3191 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3192 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3197 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3198 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3199 { "bndmov", { EbndS
, Gbnd
}, 0 },
3200 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3205 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3206 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3207 { "nopQ", { Ev
}, 0 },
3208 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3213 { "nopQ", { Ev
}, 0 },
3214 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3215 { "nopQ", { Ev
}, 0 },
3216 { NULL
, { XX
}, PREFIX_IGNORED
},
3221 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3222 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3223 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3224 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3229 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3230 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3231 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3232 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3237 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3238 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3239 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3240 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3245 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3246 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3247 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3248 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3253 { "ucomiss",{ XM
, EXd
}, 0 },
3255 { "ucomisd",{ XM
, EXq
}, 0 },
3260 { "comiss", { XM
, EXd
}, 0 },
3262 { "comisd", { XM
, EXq
}, 0 },
3267 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3268 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3269 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3270 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3275 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3276 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3281 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3282 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3287 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3288 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3289 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3290 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3295 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3296 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3297 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3298 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3303 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3304 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3305 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3306 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3311 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3312 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3313 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3318 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3319 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3320 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3321 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3326 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3327 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3328 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3329 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3334 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3335 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3336 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3337 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3342 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3343 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3344 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3345 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3350 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3352 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3357 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3359 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3364 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3366 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3371 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3372 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3373 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3378 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3379 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3380 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3381 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3386 {"vmread", { Em
, Gm
}, 0 },
3388 {"extrq", { XS
, Ib
, Ib
}, 0 },
3389 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3394 {"vmwrite", { Gm
, Em
}, 0 },
3396 {"extrq", { XM
, XS
}, 0 },
3397 {"insertq", { XM
, XS
}, 0 },
3404 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3405 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3412 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3413 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3418 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3419 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3420 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3425 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3426 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3427 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3430 /* PREFIX_0FAE_REG_0_MOD_3 */
3433 { "rdfsbase", { Ev
}, 0 },
3436 /* PREFIX_0FAE_REG_1_MOD_3 */
3439 { "rdgsbase", { Ev
}, 0 },
3442 /* PREFIX_0FAE_REG_2_MOD_3 */
3445 { "wrfsbase", { Ev
}, 0 },
3448 /* PREFIX_0FAE_REG_3_MOD_3 */
3451 { "wrgsbase", { Ev
}, 0 },
3454 /* PREFIX_0FAE_REG_4_MOD_0 */
3456 { "xsave", { FXSAVE
}, 0 },
3457 { "ptwrite{%LQ|}", { Edq
}, 0 },
3460 /* PREFIX_0FAE_REG_4_MOD_3 */
3463 { "ptwrite{%LQ|}", { Edq
}, 0 },
3466 /* PREFIX_0FAE_REG_5_MOD_3 */
3468 { "lfence", { Skip_MODRM
}, 0 },
3469 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3472 /* PREFIX_0FAE_REG_6_MOD_0 */
3474 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3475 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3476 { "clwb", { Mb
}, PREFIX_OPCODE
},
3479 /* PREFIX_0FAE_REG_6_MOD_3 */
3481 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3482 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3483 { "tpause", { Edq
}, PREFIX_OPCODE
},
3484 { "umwait", { Edq
}, PREFIX_OPCODE
},
3487 /* PREFIX_0FAE_REG_7_MOD_0 */
3489 { "clflush", { Mb
}, 0 },
3491 { "clflushopt", { Mb
}, 0 },
3497 { "popcntS", { Gv
, Ev
}, 0 },
3502 { "bsfS", { Gv
, Ev
}, 0 },
3503 { "tzcntS", { Gv
, Ev
}, 0 },
3504 { "bsfS", { Gv
, Ev
}, 0 },
3509 { "bsrS", { Gv
, Ev
}, 0 },
3510 { "lzcntS", { Gv
, Ev
}, 0 },
3511 { "bsrS", { Gv
, Ev
}, 0 },
3516 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3517 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3518 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3519 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3522 /* PREFIX_0FC7_REG_6_MOD_0 */
3524 { "vmptrld",{ Mq
}, 0 },
3525 { "vmxon", { Mq
}, 0 },
3526 { "vmclear",{ Mq
}, 0 },
3529 /* PREFIX_0FC7_REG_6_MOD_3 */
3531 { "rdrand", { Ev
}, 0 },
3532 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3533 { "rdrand", { Ev
}, 0 }
3536 /* PREFIX_0FC7_REG_7_MOD_3 */
3538 { "rdseed", { Ev
}, 0 },
3539 { "rdpid", { Em
}, 0 },
3540 { "rdseed", { Ev
}, 0 },
3547 { "addsubpd", { XM
, EXx
}, 0 },
3548 { "addsubps", { XM
, EXx
}, 0 },
3554 { "movq2dq",{ XM
, MS
}, 0 },
3555 { "movq", { EXqS
, XM
}, 0 },
3556 { "movdq2q",{ MX
, XS
}, 0 },
3562 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3563 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3564 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3569 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3571 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3579 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3584 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3586 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3592 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3598 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3599 { "aesenc", { XM
, EXx
}, 0 },
3605 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3606 { "aesenclast", { XM
, EXx
}, 0 },
3612 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3613 { "aesdec", { XM
, EXx
}, 0 },
3619 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3620 { "aesdeclast", { XM
, EXx
}, 0 },
3625 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3627 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3628 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3633 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3635 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3636 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3641 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3642 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3643 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3650 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3651 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3652 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3657 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3663 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3669 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3672 /* PREFIX_VEX_0F10 */
3674 { "vmovups", { XM
, EXx
}, 0 },
3675 { "vmovss", { XMScalar
, VexScalarR
, EXd
}, 0 },
3676 { "vmovupd", { XM
, EXx
}, 0 },
3677 { "vmovsd", { XMScalar
, VexScalarR
, EXq
}, 0 },
3680 /* PREFIX_VEX_0F11 */
3682 { "vmovups", { EXxS
, XM
}, 0 },
3683 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3684 { "vmovupd", { EXxS
, XM
}, 0 },
3685 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3688 /* PREFIX_VEX_0F12 */
3690 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3691 { "vmovsldup", { XM
, EXx
}, 0 },
3692 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3693 { "vmovddup", { XM
, EXymmq
}, 0 },
3696 /* PREFIX_VEX_0F16 */
3698 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3699 { "vmovshdup", { XM
, EXx
}, 0 },
3700 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3703 /* PREFIX_VEX_0F2A */
3706 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3708 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3711 /* PREFIX_VEX_0F2C */
3714 { "vcvttss2si", { Gdq
, EXd
, EXxEVexS
}, 0 },
3716 { "vcvttsd2si", { Gdq
, EXq
, EXxEVexS
}, 0 },
3719 /* PREFIX_VEX_0F2D */
3722 { "vcvtss2si", { Gdq
, EXd
, EXxEVexR
}, 0 },
3724 { "vcvtsd2si", { Gdq
, EXq
, EXxEVexR
}, 0 },
3727 /* PREFIX_VEX_0F2E */
3729 { "vucomisX", { XMScalar
, EXd
, EXxEVexS
}, PREFIX_OPCODE
},
3731 { "vucomisX", { XMScalar
, EXq
, EXxEVexS
}, PREFIX_OPCODE
},
3734 /* PREFIX_VEX_0F2F */
3736 { "vcomisX", { XMScalar
, EXd
, EXxEVexS
}, PREFIX_OPCODE
},
3738 { "vcomisX", { XMScalar
, EXq
, EXxEVexS
}, PREFIX_OPCODE
},
3741 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3743 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
3745 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
3748 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3750 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
3752 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
3755 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3757 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
3759 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
3762 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3764 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
3766 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
3769 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3771 { "knotw", { MaskG
, MaskE
}, 0 },
3773 { "knotb", { MaskG
, MaskE
}, 0 },
3776 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3778 { "knotq", { MaskG
, MaskE
}, 0 },
3780 { "knotd", { MaskG
, MaskE
}, 0 },
3783 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3785 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
3787 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
3790 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3792 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
3794 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
3797 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3799 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3801 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3804 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3806 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3808 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
3811 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3813 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3815 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3818 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3820 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3822 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
3825 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3827 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
3829 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
3832 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3834 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
3836 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
3839 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3841 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
3843 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
3846 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3848 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
3851 /* PREFIX_VEX_0F51 */
3853 { "vsqrtps", { XM
, EXx
}, 0 },
3854 { "vsqrtss", { XMScalar
, VexScalar
, EXd
}, 0 },
3855 { "vsqrtpd", { XM
, EXx
}, 0 },
3856 { "vsqrtsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3859 /* PREFIX_VEX_0F52 */
3861 { "vrsqrtps", { XM
, EXx
}, 0 },
3862 { "vrsqrtss", { XMScalar
, VexScalar
, EXd
}, 0 },
3865 /* PREFIX_VEX_0F53 */
3867 { "vrcpps", { XM
, EXx
}, 0 },
3868 { "vrcpss", { XMScalar
, VexScalar
, EXd
}, 0 },
3871 /* PREFIX_VEX_0F58 */
3873 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3874 { "vaddss", { XMScalar
, VexScalar
, EXd
}, 0 },
3875 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3876 { "vaddsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3879 /* PREFIX_VEX_0F59 */
3881 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3882 { "vmulss", { XMScalar
, VexScalar
, EXd
}, 0 },
3883 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3884 { "vmulsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3887 /* PREFIX_VEX_0F5A */
3889 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3890 { "vcvtss2sd", { XMScalar
, VexScalar
, EXd
}, 0 },
3891 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3892 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXq
}, 0 },
3895 /* PREFIX_VEX_0F5B */
3897 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3898 { "vcvttps2dq", { XM
, EXx
}, 0 },
3899 { "vcvtps2dq", { XM
, EXx
}, 0 },
3902 /* PREFIX_VEX_0F5C */
3904 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3905 { "vsubss", { XMScalar
, VexScalar
, EXd
}, 0 },
3906 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3907 { "vsubsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3910 /* PREFIX_VEX_0F5D */
3912 { "vminps", { XM
, Vex
, EXx
}, 0 },
3913 { "vminss", { XMScalar
, VexScalar
, EXd
}, 0 },
3914 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3915 { "vminsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3918 /* PREFIX_VEX_0F5E */
3920 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3921 { "vdivss", { XMScalar
, VexScalar
, EXd
}, 0 },
3922 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3923 { "vdivsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3926 /* PREFIX_VEX_0F5F */
3928 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3929 { "vmaxss", { XMScalar
, VexScalar
, EXd
}, 0 },
3930 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3931 { "vmaxsd", { XMScalar
, VexScalar
, EXq
}, 0 },
3934 /* PREFIX_VEX_0F6F */
3937 { "vmovdqu", { XM
, EXx
}, 0 },
3938 { "vmovdqa", { XM
, EXx
}, 0 },
3941 /* PREFIX_VEX_0F70 */
3944 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3945 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3946 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3949 /* PREFIX_VEX_0F7C */
3953 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3954 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3957 /* PREFIX_VEX_0F7D */
3961 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3962 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3965 /* PREFIX_VEX_0F7E */
3968 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3969 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3972 /* PREFIX_VEX_0F7F */
3975 { "vmovdqu", { EXxS
, XM
}, 0 },
3976 { "vmovdqa", { EXxS
, XM
}, 0 },
3979 /* PREFIX_VEX_0F90_L_0_W_0 */
3981 { "kmovw", { MaskG
, MaskE
}, 0 },
3983 { "kmovb", { MaskG
, MaskBDE
}, 0 },
3986 /* PREFIX_VEX_0F90_L_0_W_1 */
3988 { "kmovq", { MaskG
, MaskE
}, 0 },
3990 { "kmovd", { MaskG
, MaskBDE
}, 0 },
3993 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3995 { "kmovw", { Ew
, MaskG
}, 0 },
3997 { "kmovb", { Eb
, MaskG
}, 0 },
4000 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
4002 { "kmovq", { Eq
, MaskG
}, 0 },
4004 { "kmovd", { Ed
, MaskG
}, 0 },
4007 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
4009 { "kmovw", { MaskG
, Edq
}, 0 },
4011 { "kmovb", { MaskG
, Edq
}, 0 },
4012 { "kmovd", { MaskG
, Edq
}, 0 },
4015 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
4020 { "kmovK", { MaskG
, Edq
}, 0 },
4023 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4025 { "kmovw", { Gdq
, MaskE
}, 0 },
4027 { "kmovb", { Gdq
, MaskE
}, 0 },
4028 { "kmovd", { Gdq
, MaskE
}, 0 },
4031 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4036 { "kmovK", { Gdq
, MaskE
}, 0 },
4039 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4041 { "kortestw", { MaskG
, MaskE
}, 0 },
4043 { "kortestb", { MaskG
, MaskE
}, 0 },
4046 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4048 { "kortestq", { MaskG
, MaskE
}, 0 },
4050 { "kortestd", { MaskG
, MaskE
}, 0 },
4053 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4055 { "ktestw", { MaskG
, MaskE
}, 0 },
4057 { "ktestb", { MaskG
, MaskE
}, 0 },
4060 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4062 { "ktestq", { MaskG
, MaskE
}, 0 },
4064 { "ktestd", { MaskG
, MaskE
}, 0 },
4067 /* PREFIX_VEX_0FC2 */
4069 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4070 { "vcmpss", { XMScalar
, VexScalar
, EXd
, CMP
}, 0 },
4071 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4072 { "vcmpsd", { XMScalar
, VexScalar
, EXq
, CMP
}, 0 },
4075 /* PREFIX_VEX_0FD0 */
4079 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4080 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4083 /* PREFIX_VEX_0FE6 */
4086 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4087 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4088 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4091 /* PREFIX_VEX_0FF0 */
4096 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4099 /* PREFIX_VEX_0F3849_X86_64 */
4101 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4103 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4104 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4107 /* PREFIX_VEX_0F384B_X86_64 */
4110 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4111 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4112 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4115 /* PREFIX_VEX_0F385C_X86_64 */
4118 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4122 /* PREFIX_VEX_0F385E_X86_64 */
4124 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4125 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4126 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4127 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4130 /* PREFIX_VEX_0F38F5_L_0 */
4132 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
4133 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
4135 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
4138 /* PREFIX_VEX_0F38F6_L_0 */
4143 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
4146 /* PREFIX_VEX_0F38F7_L_0 */
4148 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
4149 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
4150 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
4151 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
4154 /* PREFIX_VEX_0F3AF0_L_0 */
4159 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
4162 #include "i386-dis-evex-prefix.h"
4165 static const struct dis386 x86_64_table
[][2] = {
4168 { "pushP", { es
}, 0 },
4173 { "popP", { es
}, 0 },
4178 { "pushP", { cs
}, 0 },
4183 { "pushP", { ss
}, 0 },
4188 { "popP", { ss
}, 0 },
4193 { "pushP", { ds
}, 0 },
4198 { "popP", { ds
}, 0 },
4203 { "daa", { XX
}, 0 },
4208 { "das", { XX
}, 0 },
4213 { "aaa", { XX
}, 0 },
4218 { "aas", { XX
}, 0 },
4223 { "pushaP", { XX
}, 0 },
4228 { "popaP", { XX
}, 0 },
4233 { MOD_TABLE (MOD_62_32BIT
) },
4234 { EVEX_TABLE (EVEX_0F
) },
4239 { "arpl", { Ew
, Gw
}, 0 },
4240 { "movs", { Gv
, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4245 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4246 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4251 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4252 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4257 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4258 { REG_TABLE (REG_80
) },
4263 { "{l|}call{P|}", { Ap
}, 0 },
4268 { "retP", { Iw
, BND
}, 0 },
4269 { "ret@", { Iw
, BND
}, 0 },
4274 { "retP", { BND
}, 0 },
4275 { "ret@", { BND
}, 0 },
4280 { MOD_TABLE (MOD_C4_32BIT
) },
4281 { VEX_C4_TABLE (VEX_0F
) },
4286 { MOD_TABLE (MOD_C5_32BIT
) },
4287 { VEX_C5_TABLE (VEX_0F
) },
4292 { "into", { XX
}, 0 },
4297 { "aam", { Ib
}, 0 },
4302 { "aad", { Ib
}, 0 },
4307 { "callP", { Jv
, BND
}, 0 },
4308 { "call@", { Jv
, BND
}, 0 }
4313 { "jmpP", { Jv
, BND
}, 0 },
4314 { "jmp@", { Jv
, BND
}, 0 }
4319 { "{l|}jmp{P|}", { Ap
}, 0 },
4322 /* X86_64_0F01_REG_0 */
4324 { "sgdt{Q|Q}", { M
}, 0 },
4325 { "sgdt", { M
}, 0 },
4328 /* X86_64_0F01_REG_1 */
4330 { "sidt{Q|Q}", { M
}, 0 },
4331 { "sidt", { M
}, 0 },
4334 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4337 { "seamret", { Skip_MODRM
}, 0 },
4340 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4343 { "seamops", { Skip_MODRM
}, 0 },
4346 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4349 { "seamcall", { Skip_MODRM
}, 0 },
4352 /* X86_64_0F01_REG_2 */
4354 { "lgdt{Q|Q}", { M
}, 0 },
4355 { "lgdt", { M
}, 0 },
4358 /* X86_64_0F01_REG_3 */
4360 { "lidt{Q|Q}", { M
}, 0 },
4361 { "lidt", { M
}, 0 },
4364 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4367 { "uiret", { Skip_MODRM
}, 0 },
4370 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4373 { "testui", { Skip_MODRM
}, 0 },
4376 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4379 { "clui", { Skip_MODRM
}, 0 },
4382 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4385 { "stui", { Skip_MODRM
}, 0 },
4388 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4391 { "rmpadjust", { Skip_MODRM
}, 0 },
4394 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4397 { "rmpupdate", { Skip_MODRM
}, 0 },
4400 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4403 { "psmash", { Skip_MODRM
}, 0 },
4408 { "movZ", { Em
, Td
}, 0 },
4413 { "movZ", { Td
, Em
}, 0 },
4416 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4419 { "senduipi", { Eq
}, 0 },
4422 /* X86_64_VEX_0F3849 */
4425 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4428 /* X86_64_VEX_0F384B */
4431 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4434 /* X86_64_VEX_0F385C */
4437 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4440 /* X86_64_VEX_0F385E */
4443 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4447 static const struct dis386 three_byte_table
[][256] = {
4449 /* THREE_BYTE_0F38 */
4452 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4453 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4454 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4455 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4456 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4457 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4458 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4459 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4461 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4462 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4463 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4464 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4470 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4474 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4475 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4477 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4483 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4484 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4485 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4488 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4489 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4490 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4491 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4492 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4493 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4497 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4498 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4499 { MOD_TABLE (MOD_0F382A
) },
4500 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4506 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4507 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4508 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4509 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4510 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4511 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4513 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4515 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4516 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4517 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4518 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4519 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4520 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4521 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4522 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4524 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4525 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4596 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4597 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4598 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4677 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4678 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4679 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4680 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4681 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4682 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4684 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4695 { PREFIX_TABLE (PREFIX_0F38D8
) },
4698 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4699 { PREFIX_TABLE (PREFIX_0F38DC
) },
4700 { PREFIX_TABLE (PREFIX_0F38DD
) },
4701 { PREFIX_TABLE (PREFIX_0F38DE
) },
4702 { PREFIX_TABLE (PREFIX_0F38DF
) },
4722 { PREFIX_TABLE (PREFIX_0F38F0
) },
4723 { PREFIX_TABLE (PREFIX_0F38F1
) },
4727 { MOD_TABLE (MOD_0F38F5
) },
4728 { PREFIX_TABLE (PREFIX_0F38F6
) },
4731 { PREFIX_TABLE (PREFIX_0F38F8
) },
4732 { MOD_TABLE (MOD_0F38F9
) },
4733 { PREFIX_TABLE (PREFIX_0F38FA
) },
4734 { PREFIX_TABLE (PREFIX_0F38FB
) },
4740 /* THREE_BYTE_0F3A */
4752 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4753 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4754 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4755 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4756 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4757 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4758 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4759 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4765 { "pextrb", { Edb
, XM
, Ib
}, PREFIX_DATA
},
4766 { "pextrw", { Edw
, XM
, Ib
}, PREFIX_DATA
},
4767 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4768 { "extractps", { Ed
, XM
, Ib
}, PREFIX_DATA
},
4779 { "pinsrb", { XM
, Edb
, Ib
}, PREFIX_DATA
},
4780 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4781 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4815 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4816 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4817 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4819 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4851 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4852 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4853 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4854 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4972 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4974 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4975 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4993 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5013 { PREFIX_TABLE (PREFIX_0F3A0F
) },
5033 static const struct dis386 xop_table
[][256] = {
5186 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5187 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5188 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5197 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5204 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5205 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5219 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5220 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5223 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5253 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5254 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5255 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5256 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5266 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5267 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5268 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5269 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5302 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5303 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5304 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5305 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5329 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5330 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5348 { MOD_TABLE (MOD_XOP_09_12
) },
5472 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5473 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5474 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5475 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5490 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5491 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5492 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5494 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5495 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5496 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5497 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5499 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5500 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5501 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5502 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5545 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5546 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5547 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5550 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5551 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5556 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5563 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5564 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5565 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5568 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5569 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5574 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5581 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5582 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5583 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5637 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5639 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5909 static const struct dis386 vex_table
[][256] = {
5931 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5932 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5933 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5934 { MOD_TABLE (MOD_VEX_0F13
) },
5935 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5936 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5937 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5938 { MOD_TABLE (MOD_VEX_0F17
) },
5958 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5959 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5960 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5961 { MOD_TABLE (MOD_VEX_0F2B
) },
5962 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5963 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5964 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5965 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5986 { VEX_LEN_TABLE (VEX_LEN_0F41
) },
5987 { VEX_LEN_TABLE (VEX_LEN_0F42
) },
5989 { VEX_LEN_TABLE (VEX_LEN_0F44
) },
5990 { VEX_LEN_TABLE (VEX_LEN_0F45
) },
5991 { VEX_LEN_TABLE (VEX_LEN_0F46
) },
5992 { VEX_LEN_TABLE (VEX_LEN_0F47
) },
5996 { VEX_LEN_TABLE (VEX_LEN_0F4A
) },
5997 { VEX_LEN_TABLE (VEX_LEN_0F4B
) },
6003 { MOD_TABLE (MOD_VEX_0F50
) },
6004 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
6005 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
6006 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
6007 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6008 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6009 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6010 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6012 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
6013 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
6014 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
6015 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
6016 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
6017 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
6018 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
6019 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
6021 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6022 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6023 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6024 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6025 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6026 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6027 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6028 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6030 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6031 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6032 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6033 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6034 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6035 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6036 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
6037 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
6039 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
6040 { MOD_TABLE (MOD_VEX_0F71
) },
6041 { MOD_TABLE (MOD_VEX_0F72
) },
6042 { MOD_TABLE (MOD_VEX_0F73
) },
6043 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6044 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6045 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6046 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
6052 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
6053 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
6054 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
6055 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6075 { VEX_LEN_TABLE (VEX_LEN_0F90
) },
6076 { VEX_LEN_TABLE (VEX_LEN_0F91
) },
6077 { VEX_LEN_TABLE (VEX_LEN_0F92
) },
6078 { VEX_LEN_TABLE (VEX_LEN_0F93
) },
6084 { VEX_LEN_TABLE (VEX_LEN_0F98
) },
6085 { VEX_LEN_TABLE (VEX_LEN_0F99
) },
6108 { REG_TABLE (REG_VEX_0FAE
) },
6131 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6133 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6134 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6135 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6147 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6148 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6149 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6150 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6151 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6154 { MOD_TABLE (MOD_VEX_0FD7
) },
6156 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6158 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6160 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6161 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6162 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6163 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6165 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6166 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6167 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6168 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6169 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6170 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6171 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6172 { MOD_TABLE (MOD_VEX_0FE7
) },
6174 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6175 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6176 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6177 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6178 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6179 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6180 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6181 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6183 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6184 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6185 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6186 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6187 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6188 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6189 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6190 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6192 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6193 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6194 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6195 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6197 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6198 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6204 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6205 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6206 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6207 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6208 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6209 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6210 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6211 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6213 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6214 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6215 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6216 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6217 { VEX_W_TABLE (VEX_W_0F380C
) },
6218 { VEX_W_TABLE (VEX_W_0F380D
) },
6219 { VEX_W_TABLE (VEX_W_0F380E
) },
6220 { VEX_W_TABLE (VEX_W_0F380F
) },
6225 { VEX_W_TABLE (VEX_W_0F3813
) },
6228 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6229 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6231 { VEX_W_TABLE (VEX_W_0F3818
) },
6232 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6233 { MOD_TABLE (MOD_VEX_0F381A
) },
6235 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6236 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6237 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6240 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6241 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6242 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6243 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6244 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6245 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6249 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6250 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6251 { MOD_TABLE (MOD_VEX_0F382A
) },
6252 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6253 { MOD_TABLE (MOD_VEX_0F382C
) },
6254 { MOD_TABLE (MOD_VEX_0F382D
) },
6255 { MOD_TABLE (MOD_VEX_0F382E
) },
6256 { MOD_TABLE (MOD_VEX_0F382F
) },
6258 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6259 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6260 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6261 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6262 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6263 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6264 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6265 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6267 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6268 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6269 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6270 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6271 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6272 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6273 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6274 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6276 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6277 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6281 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6282 { VEX_W_TABLE (VEX_W_0F3846
) },
6283 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6286 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6288 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6294 { VEX_W_TABLE (VEX_W_0F3850
) },
6295 { VEX_W_TABLE (VEX_W_0F3851
) },
6296 { VEX_W_TABLE (VEX_W_0F3852
) },
6297 { VEX_W_TABLE (VEX_W_0F3853
) },
6303 { VEX_W_TABLE (VEX_W_0F3858
) },
6304 { VEX_W_TABLE (VEX_W_0F3859
) },
6305 { MOD_TABLE (MOD_VEX_0F385A
) },
6307 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6309 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6339 { VEX_W_TABLE (VEX_W_0F3878
) },
6340 { VEX_W_TABLE (VEX_W_0F3879
) },
6361 { MOD_TABLE (MOD_VEX_0F388C
) },
6363 { MOD_TABLE (MOD_VEX_0F388E
) },
6366 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6367 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6368 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6369 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6372 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6373 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6375 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6376 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6377 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6378 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6379 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6380 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6381 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6382 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6390 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6391 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6393 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6394 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6395 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6396 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6397 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6398 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6399 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6400 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6408 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6409 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6411 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6412 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6413 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6414 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6415 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6416 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6417 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6418 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6436 { VEX_W_TABLE (VEX_W_0F38CF
) },
6450 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6451 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6452 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6453 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6454 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6476 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6477 { VEX_LEN_TABLE (VEX_LEN_0F38F3
) },
6479 { VEX_LEN_TABLE (VEX_LEN_0F38F5
) },
6480 { VEX_LEN_TABLE (VEX_LEN_0F38F6
) },
6481 { VEX_LEN_TABLE (VEX_LEN_0F38F7
) },
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6497 { VEX_W_TABLE (VEX_W_0F3A02
) },
6499 { VEX_W_TABLE (VEX_W_0F3A04
) },
6500 { VEX_W_TABLE (VEX_W_0F3A05
) },
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6504 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6505 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6506 { "vroundss", { XMScalar
, VexScalar
, EXd
, Ib
}, PREFIX_DATA
},
6507 { "vroundsd", { XMScalar
, VexScalar
, EXq
, Ib
}, PREFIX_DATA
},
6508 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6509 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6510 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6511 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6518 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6520 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6527 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6533 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6551 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6552 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6567 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6568 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6569 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6571 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6573 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6576 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6577 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6578 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6579 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6580 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6598 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6599 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6600 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6601 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6603 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6604 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6606 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6612 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6613 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6614 { "vfmaddss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6615 { "vfmaddsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6616 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6617 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6618 { "vfmsubss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6619 { "vfmsubsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6630 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6631 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6632 { "vfnmaddss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6633 { "vfnmaddsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6634 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6635 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6636 { "vfnmsubss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6637 { "vfnmsubsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6726 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6727 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6745 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6765 { VEX_LEN_TABLE (VEX_LEN_0F3AF0
) },
6785 #include "i386-dis-evex.h"
6787 static const struct dis386 vex_len_table
[][2] = {
6788 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6790 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6793 /* VEX_LEN_0F12_P_0_M_1 */
6795 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6798 /* VEX_LEN_0F13_M_0 */
6800 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6803 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6805 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6808 /* VEX_LEN_0F16_P_0_M_1 */
6810 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6813 /* VEX_LEN_0F17_M_0 */
6815 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6821 { MOD_TABLE (MOD_VEX_0F41_L_1
) },
6827 { MOD_TABLE (MOD_VEX_0F42_L_1
) },
6832 { MOD_TABLE (MOD_VEX_0F44_L_0
) },
6838 { MOD_TABLE (MOD_VEX_0F45_L_1
) },
6844 { MOD_TABLE (MOD_VEX_0F46_L_1
) },
6850 { MOD_TABLE (MOD_VEX_0F47_L_1
) },
6856 { MOD_TABLE (MOD_VEX_0F4A_L_1
) },
6862 { MOD_TABLE (MOD_VEX_0F4B_L_1
) },
6867 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6872 { "vzeroupper", { XX
}, 0 },
6873 { "vzeroall", { XX
}, 0 },
6876 /* VEX_LEN_0F7E_P_1 */
6878 { "vmovq", { XMScalar
, EXq
}, 0 },
6881 /* VEX_LEN_0F7E_P_2 */
6883 { "vmovK", { Edq
, XMScalar
}, 0 },
6888 { VEX_W_TABLE (VEX_W_0F90_L_0
) },
6893 { MOD_TABLE (MOD_VEX_0F91_L_0
) },
6898 { MOD_TABLE (MOD_VEX_0F92_L_0
) },
6903 { MOD_TABLE (MOD_VEX_0F93_L_0
) },
6908 { MOD_TABLE (MOD_VEX_0F98_L_0
) },
6913 { MOD_TABLE (MOD_VEX_0F99_L_0
) },
6916 /* VEX_LEN_0FAE_R_2_M_0 */
6918 { "vldmxcsr", { Md
}, 0 },
6921 /* VEX_LEN_0FAE_R_3_M_0 */
6923 { "vstmxcsr", { Md
}, 0 },
6928 { "vpinsrw", { XM
, Vex
, Edw
, Ib
}, PREFIX_DATA
},
6933 { "vpextrw", { Gd
, XS
, Ib
}, PREFIX_DATA
},
6938 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6943 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6946 /* VEX_LEN_0F3816 */
6949 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6952 /* VEX_LEN_0F3819 */
6955 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6958 /* VEX_LEN_0F381A_M_0 */
6961 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6964 /* VEX_LEN_0F3836 */
6967 { VEX_W_TABLE (VEX_W_0F3836
) },
6970 /* VEX_LEN_0F3841 */
6972 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6975 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6977 { "ldtilecfg", { M
}, 0 },
6980 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6982 { "tilerelease", { Skip_MODRM
}, 0 },
6985 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6987 { "sttilecfg", { M
}, 0 },
6990 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6992 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6995 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6997 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6999 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7001 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
7004 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7006 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
7009 /* VEX_LEN_0F385A_M_0 */
7012 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
7015 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7017 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
7020 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7022 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
7025 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7027 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
7030 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7032 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
7035 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7037 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
7040 /* VEX_LEN_0F38DB */
7042 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
7045 /* VEX_LEN_0F38F2 */
7047 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
7050 /* VEX_LEN_0F38F3 */
7052 { REG_TABLE(REG_VEX_0F38F3_L_0
) },
7055 /* VEX_LEN_0F38F5 */
7057 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0
) },
7060 /* VEX_LEN_0F38F6 */
7062 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0
) },
7065 /* VEX_LEN_0F38F7 */
7067 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0
) },
7070 /* VEX_LEN_0F3A00 */
7073 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7076 /* VEX_LEN_0F3A01 */
7079 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7082 /* VEX_LEN_0F3A06 */
7085 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7088 /* VEX_LEN_0F3A14 */
7090 { "vpextrb", { Edb
, XM
, Ib
}, PREFIX_DATA
},
7093 /* VEX_LEN_0F3A15 */
7095 { "vpextrw", { Edw
, XM
, Ib
}, PREFIX_DATA
},
7098 /* VEX_LEN_0F3A16 */
7100 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7103 /* VEX_LEN_0F3A17 */
7105 { "vextractps", { Ed
, XM
, Ib
}, PREFIX_DATA
},
7108 /* VEX_LEN_0F3A18 */
7111 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7114 /* VEX_LEN_0F3A19 */
7117 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7120 /* VEX_LEN_0F3A20 */
7122 { "vpinsrb", { XM
, Vex
, Edb
, Ib
}, PREFIX_DATA
},
7125 /* VEX_LEN_0F3A21 */
7127 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7130 /* VEX_LEN_0F3A22 */
7132 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7135 /* VEX_LEN_0F3A30 */
7137 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7140 /* VEX_LEN_0F3A31 */
7142 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7145 /* VEX_LEN_0F3A32 */
7147 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7150 /* VEX_LEN_0F3A33 */
7152 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7155 /* VEX_LEN_0F3A38 */
7158 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7161 /* VEX_LEN_0F3A39 */
7164 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7167 /* VEX_LEN_0F3A41 */
7169 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7172 /* VEX_LEN_0F3A46 */
7175 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7178 /* VEX_LEN_0F3A60 */
7180 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7183 /* VEX_LEN_0F3A61 */
7185 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7188 /* VEX_LEN_0F3A62 */
7190 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7193 /* VEX_LEN_0F3A63 */
7195 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7198 /* VEX_LEN_0F3ADF */
7200 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7203 /* VEX_LEN_0F3AF0 */
7205 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0
) },
7208 /* VEX_LEN_0FXOP_08_85 */
7210 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7213 /* VEX_LEN_0FXOP_08_86 */
7215 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7218 /* VEX_LEN_0FXOP_08_87 */
7220 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7223 /* VEX_LEN_0FXOP_08_8E */
7225 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7228 /* VEX_LEN_0FXOP_08_8F */
7230 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7233 /* VEX_LEN_0FXOP_08_95 */
7235 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7238 /* VEX_LEN_0FXOP_08_96 */
7240 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7243 /* VEX_LEN_0FXOP_08_97 */
7245 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7248 /* VEX_LEN_0FXOP_08_9E */
7250 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7253 /* VEX_LEN_0FXOP_08_9F */
7255 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7258 /* VEX_LEN_0FXOP_08_A3 */
7260 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7263 /* VEX_LEN_0FXOP_08_A6 */
7265 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7268 /* VEX_LEN_0FXOP_08_B6 */
7270 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7273 /* VEX_LEN_0FXOP_08_C0 */
7275 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7278 /* VEX_LEN_0FXOP_08_C1 */
7280 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7283 /* VEX_LEN_0FXOP_08_C2 */
7285 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7288 /* VEX_LEN_0FXOP_08_C3 */
7290 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7293 /* VEX_LEN_0FXOP_08_CC */
7295 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7298 /* VEX_LEN_0FXOP_08_CD */
7300 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7303 /* VEX_LEN_0FXOP_08_CE */
7305 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7308 /* VEX_LEN_0FXOP_08_CF */
7310 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7313 /* VEX_LEN_0FXOP_08_EC */
7315 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7318 /* VEX_LEN_0FXOP_08_ED */
7320 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7323 /* VEX_LEN_0FXOP_08_EE */
7325 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7328 /* VEX_LEN_0FXOP_08_EF */
7330 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7333 /* VEX_LEN_0FXOP_09_01 */
7335 { REG_TABLE (REG_XOP_09_01_L_0
) },
7338 /* VEX_LEN_0FXOP_09_02 */
7340 { REG_TABLE (REG_XOP_09_02_L_0
) },
7343 /* VEX_LEN_0FXOP_09_12_M_1 */
7345 { REG_TABLE (REG_XOP_09_12_M_1_L_0
) },
7348 /* VEX_LEN_0FXOP_09_82_W_0 */
7350 { "vfrczss", { XM
, EXd
}, 0 },
7353 /* VEX_LEN_0FXOP_09_83_W_0 */
7355 { "vfrczsd", { XM
, EXq
}, 0 },
7358 /* VEX_LEN_0FXOP_09_90 */
7360 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7363 /* VEX_LEN_0FXOP_09_91 */
7365 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7368 /* VEX_LEN_0FXOP_09_92 */
7370 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7373 /* VEX_LEN_0FXOP_09_93 */
7375 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7378 /* VEX_LEN_0FXOP_09_94 */
7380 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7383 /* VEX_LEN_0FXOP_09_95 */
7385 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7388 /* VEX_LEN_0FXOP_09_96 */
7390 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7393 /* VEX_LEN_0FXOP_09_97 */
7395 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7398 /* VEX_LEN_0FXOP_09_98 */
7400 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7403 /* VEX_LEN_0FXOP_09_99 */
7405 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7408 /* VEX_LEN_0FXOP_09_9A */
7410 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7413 /* VEX_LEN_0FXOP_09_9B */
7415 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7418 /* VEX_LEN_0FXOP_09_C1 */
7420 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7423 /* VEX_LEN_0FXOP_09_C2 */
7425 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7428 /* VEX_LEN_0FXOP_09_C3 */
7430 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7433 /* VEX_LEN_0FXOP_09_C6 */
7435 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7438 /* VEX_LEN_0FXOP_09_C7 */
7440 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7443 /* VEX_LEN_0FXOP_09_CB */
7445 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7448 /* VEX_LEN_0FXOP_09_D1 */
7450 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7453 /* VEX_LEN_0FXOP_09_D2 */
7455 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7458 /* VEX_LEN_0FXOP_09_D3 */
7460 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7463 /* VEX_LEN_0FXOP_09_D6 */
7465 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7468 /* VEX_LEN_0FXOP_09_D7 */
7470 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7473 /* VEX_LEN_0FXOP_09_DB */
7475 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7478 /* VEX_LEN_0FXOP_09_E1 */
7480 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7483 /* VEX_LEN_0FXOP_09_E2 */
7485 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7488 /* VEX_LEN_0FXOP_09_E3 */
7490 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7493 /* VEX_LEN_0FXOP_0A_12 */
7495 { REG_TABLE (REG_XOP_0A_12_L_0
) },
7499 #include "i386-dis-evex-len.h"
7501 static const struct dis386 vex_w_table
[][2] = {
7503 /* VEX_W_0F41_L_1_M_1 */
7504 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0
) },
7505 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1
) },
7508 /* VEX_W_0F42_L_1_M_1 */
7509 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0
) },
7510 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1
) },
7513 /* VEX_W_0F44_L_0_M_1 */
7514 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0
) },
7515 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1
) },
7518 /* VEX_W_0F45_L_1_M_1 */
7519 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0
) },
7520 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1
) },
7523 /* VEX_W_0F46_L_1_M_1 */
7524 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0
) },
7525 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1
) },
7528 /* VEX_W_0F47_L_1_M_1 */
7529 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0
) },
7530 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1
) },
7533 /* VEX_W_0F4A_L_1_M_1 */
7534 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0
) },
7535 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1
) },
7538 /* VEX_W_0F4B_L_1_M_1 */
7539 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0
) },
7540 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1
) },
7543 /* VEX_W_0F90_L_0 */
7544 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0
) },
7545 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1
) },
7548 /* VEX_W_0F91_L_0_M_0 */
7549 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0
) },
7550 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1
) },
7553 /* VEX_W_0F92_L_0_M_1 */
7554 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0
) },
7555 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1
) },
7558 /* VEX_W_0F93_L_0_M_1 */
7559 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0
) },
7560 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1
) },
7563 /* VEX_W_0F98_L_0_M_1 */
7564 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0
) },
7565 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1
) },
7568 /* VEX_W_0F99_L_0_M_1 */
7569 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0
) },
7570 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1
) },
7574 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7578 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7582 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7586 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7590 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7593 /* VEX_W_0F3816_L_1 */
7594 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7598 { "vbroadcastss", { XM
, EXd
}, PREFIX_DATA
},
7601 /* VEX_W_0F3819_L_1 */
7602 { "vbroadcastsd", { XM
, EXq
}, PREFIX_DATA
},
7605 /* VEX_W_0F381A_M_0_L_1 */
7606 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7609 /* VEX_W_0F382C_M_0 */
7610 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7613 /* VEX_W_0F382D_M_0 */
7614 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7617 /* VEX_W_0F382E_M_0 */
7618 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7621 /* VEX_W_0F382F_M_0 */
7622 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7626 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7630 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7633 /* VEX_W_0F3849_X86_64_P_0 */
7634 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7637 /* VEX_W_0F3849_X86_64_P_2 */
7638 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7641 /* VEX_W_0F3849_X86_64_P_3 */
7642 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7645 /* VEX_W_0F384B_X86_64_P_1 */
7646 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7649 /* VEX_W_0F384B_X86_64_P_2 */
7650 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7653 /* VEX_W_0F384B_X86_64_P_3 */
7654 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7658 { "%XV vpdpbusd", { XM
, Vex
, EXx
}, 0 },
7662 { "%XV vpdpbusds", { XM
, Vex
, EXx
}, 0 },
7666 { "%XV vpdpwssd", { XM
, Vex
, EXx
}, 0 },
7670 { "%XV vpdpwssds", { XM
, Vex
, EXx
}, 0 },
7674 { "vpbroadcastd", { XM
, EXd
}, PREFIX_DATA
},
7678 { "vpbroadcastq", { XM
, EXq
}, PREFIX_DATA
},
7681 /* VEX_W_0F385A_M_0_L_0 */
7682 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7685 /* VEX_W_0F385C_X86_64_P_1 */
7686 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7689 /* VEX_W_0F385E_X86_64_P_0 */
7690 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7693 /* VEX_W_0F385E_X86_64_P_1 */
7694 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7697 /* VEX_W_0F385E_X86_64_P_2 */
7698 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7701 /* VEX_W_0F385E_X86_64_P_3 */
7702 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7706 { "vpbroadcastb", { XM
, EXb
}, PREFIX_DATA
},
7710 { "vpbroadcastw", { XM
, EXw
}, PREFIX_DATA
},
7714 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7717 /* VEX_W_0F3A00_L_1 */
7719 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7722 /* VEX_W_0F3A01_L_1 */
7724 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7728 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7732 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7736 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7739 /* VEX_W_0F3A06_L_1 */
7740 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7743 /* VEX_W_0F3A18_L_1 */
7744 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7747 /* VEX_W_0F3A19_L_1 */
7748 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7752 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7755 /* VEX_W_0F3A38_L_1 */
7756 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7759 /* VEX_W_0F3A39_L_1 */
7760 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7763 /* VEX_W_0F3A46_L_1 */
7764 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7768 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7772 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7776 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7781 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7786 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7788 /* VEX_W_0FXOP_08_85_L_0 */
7790 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7792 /* VEX_W_0FXOP_08_86_L_0 */
7794 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7796 /* VEX_W_0FXOP_08_87_L_0 */
7798 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7800 /* VEX_W_0FXOP_08_8E_L_0 */
7802 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7804 /* VEX_W_0FXOP_08_8F_L_0 */
7806 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7808 /* VEX_W_0FXOP_08_95_L_0 */
7810 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7812 /* VEX_W_0FXOP_08_96_L_0 */
7814 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7816 /* VEX_W_0FXOP_08_97_L_0 */
7818 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7820 /* VEX_W_0FXOP_08_9E_L_0 */
7822 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7824 /* VEX_W_0FXOP_08_9F_L_0 */
7826 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7828 /* VEX_W_0FXOP_08_A6_L_0 */
7830 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7832 /* VEX_W_0FXOP_08_B6_L_0 */
7834 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7836 /* VEX_W_0FXOP_08_C0_L_0 */
7838 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7840 /* VEX_W_0FXOP_08_C1_L_0 */
7842 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7844 /* VEX_W_0FXOP_08_C2_L_0 */
7846 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7848 /* VEX_W_0FXOP_08_C3_L_0 */
7850 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7852 /* VEX_W_0FXOP_08_CC_L_0 */
7854 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7856 /* VEX_W_0FXOP_08_CD_L_0 */
7858 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7860 /* VEX_W_0FXOP_08_CE_L_0 */
7862 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7864 /* VEX_W_0FXOP_08_CF_L_0 */
7866 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7868 /* VEX_W_0FXOP_08_EC_L_0 */
7870 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7872 /* VEX_W_0FXOP_08_ED_L_0 */
7874 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7876 /* VEX_W_0FXOP_08_EE_L_0 */
7878 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7880 /* VEX_W_0FXOP_08_EF_L_0 */
7882 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7884 /* VEX_W_0FXOP_09_80 */
7886 { "vfrczps", { XM
, EXx
}, 0 },
7888 /* VEX_W_0FXOP_09_81 */
7890 { "vfrczpd", { XM
, EXx
}, 0 },
7892 /* VEX_W_0FXOP_09_82 */
7894 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7896 /* VEX_W_0FXOP_09_83 */
7898 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7900 /* VEX_W_0FXOP_09_C1_L_0 */
7902 { "vphaddbw", { XM
, EXxmm
}, 0 },
7904 /* VEX_W_0FXOP_09_C2_L_0 */
7906 { "vphaddbd", { XM
, EXxmm
}, 0 },
7908 /* VEX_W_0FXOP_09_C3_L_0 */
7910 { "vphaddbq", { XM
, EXxmm
}, 0 },
7912 /* VEX_W_0FXOP_09_C6_L_0 */
7914 { "vphaddwd", { XM
, EXxmm
}, 0 },
7916 /* VEX_W_0FXOP_09_C7_L_0 */
7918 { "vphaddwq", { XM
, EXxmm
}, 0 },
7920 /* VEX_W_0FXOP_09_CB_L_0 */
7922 { "vphadddq", { XM
, EXxmm
}, 0 },
7924 /* VEX_W_0FXOP_09_D1_L_0 */
7926 { "vphaddubw", { XM
, EXxmm
}, 0 },
7928 /* VEX_W_0FXOP_09_D2_L_0 */
7930 { "vphaddubd", { XM
, EXxmm
}, 0 },
7932 /* VEX_W_0FXOP_09_D3_L_0 */
7934 { "vphaddubq", { XM
, EXxmm
}, 0 },
7936 /* VEX_W_0FXOP_09_D6_L_0 */
7938 { "vphadduwd", { XM
, EXxmm
}, 0 },
7940 /* VEX_W_0FXOP_09_D7_L_0 */
7942 { "vphadduwq", { XM
, EXxmm
}, 0 },
7944 /* VEX_W_0FXOP_09_DB_L_0 */
7946 { "vphaddudq", { XM
, EXxmm
}, 0 },
7948 /* VEX_W_0FXOP_09_E1_L_0 */
7950 { "vphsubbw", { XM
, EXxmm
}, 0 },
7952 /* VEX_W_0FXOP_09_E2_L_0 */
7954 { "vphsubwd", { XM
, EXxmm
}, 0 },
7956 /* VEX_W_0FXOP_09_E3_L_0 */
7958 { "vphsubdq", { XM
, EXxmm
}, 0 },
7961 #include "i386-dis-evex-w.h"
7964 static const struct dis386 mod_table
[][2] = {
7967 { "bound{S|}", { Gv
, Ma
}, 0 },
7968 { EVEX_TABLE (EVEX_0F
) },
7972 { "leaS", { Gv
, M
}, 0 },
7976 { "lesS", { Gv
, Mp
}, 0 },
7977 { VEX_C4_TABLE (VEX_0F
) },
7981 { "ldsS", { Gv
, Mp
}, 0 },
7982 { VEX_C5_TABLE (VEX_0F
) },
7987 { RM_TABLE (RM_C6_REG_7
) },
7992 { RM_TABLE (RM_C7_REG_7
) },
7996 { "{l|}call^", { indirEp
}, 0 },
8000 { "{l|}jmp^", { indirEp
}, 0 },
8003 /* MOD_0F01_REG_0 */
8004 { X86_64_TABLE (X86_64_0F01_REG_0
) },
8005 { RM_TABLE (RM_0F01_REG_0
) },
8008 /* MOD_0F01_REG_1 */
8009 { X86_64_TABLE (X86_64_0F01_REG_1
) },
8010 { RM_TABLE (RM_0F01_REG_1
) },
8013 /* MOD_0F01_REG_2 */
8014 { X86_64_TABLE (X86_64_0F01_REG_2
) },
8015 { RM_TABLE (RM_0F01_REG_2
) },
8018 /* MOD_0F01_REG_3 */
8019 { X86_64_TABLE (X86_64_0F01_REG_3
) },
8020 { RM_TABLE (RM_0F01_REG_3
) },
8023 /* MOD_0F01_REG_5 */
8024 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
8025 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
8028 /* MOD_0F01_REG_7 */
8029 { "invlpg", { Mb
}, 0 },
8030 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
8033 /* MOD_0F12_PREFIX_0 */
8034 { "movlpX", { XM
, EXq
}, 0 },
8035 { "movhlps", { XM
, EXq
}, 0 },
8038 /* MOD_0F12_PREFIX_2 */
8039 { "movlpX", { XM
, EXq
}, 0 },
8043 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
8046 /* MOD_0F16_PREFIX_0 */
8047 { "movhpX", { XM
, EXq
}, 0 },
8048 { "movlhps", { XM
, EXq
}, 0 },
8051 /* MOD_0F16_PREFIX_2 */
8052 { "movhpX", { XM
, EXq
}, 0 },
8056 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8059 /* MOD_0F18_REG_0 */
8060 { "prefetchnta", { Mb
}, 0 },
8061 { "nopQ", { Ev
}, 0 },
8064 /* MOD_0F18_REG_1 */
8065 { "prefetcht0", { Mb
}, 0 },
8066 { "nopQ", { Ev
}, 0 },
8069 /* MOD_0F18_REG_2 */
8070 { "prefetcht1", { Mb
}, 0 },
8071 { "nopQ", { Ev
}, 0 },
8074 /* MOD_0F18_REG_3 */
8075 { "prefetcht2", { Mb
}, 0 },
8076 { "nopQ", { Ev
}, 0 },
8079 /* MOD_0F1A_PREFIX_0 */
8080 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8081 { "nopQ", { Ev
}, 0 },
8084 /* MOD_0F1B_PREFIX_0 */
8085 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8086 { "nopQ", { Ev
}, 0 },
8089 /* MOD_0F1B_PREFIX_1 */
8090 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8091 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8094 /* MOD_0F1C_PREFIX_0 */
8095 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8096 { "nopQ", { Ev
}, 0 },
8099 /* MOD_0F1E_PREFIX_1 */
8100 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8101 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8104 /* MOD_0F2B_PREFIX_0 */
8105 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8108 /* MOD_0F2B_PREFIX_1 */
8109 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8112 /* MOD_0F2B_PREFIX_2 */
8113 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8116 /* MOD_0F2B_PREFIX_3 */
8117 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8122 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8127 { REG_TABLE (REG_0F71_MOD_0
) },
8132 { REG_TABLE (REG_0F72_MOD_0
) },
8137 { REG_TABLE (REG_0F73_MOD_0
) },
8140 /* MOD_0FAE_REG_0 */
8141 { "fxsave", { FXSAVE
}, 0 },
8142 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8145 /* MOD_0FAE_REG_1 */
8146 { "fxrstor", { FXSAVE
}, 0 },
8147 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8150 /* MOD_0FAE_REG_2 */
8151 { "ldmxcsr", { Md
}, 0 },
8152 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8155 /* MOD_0FAE_REG_3 */
8156 { "stmxcsr", { Md
}, 0 },
8157 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8160 /* MOD_0FAE_REG_4 */
8161 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8162 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8165 /* MOD_0FAE_REG_5 */
8166 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8167 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8170 /* MOD_0FAE_REG_6 */
8171 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8172 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8175 /* MOD_0FAE_REG_7 */
8176 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8177 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8181 { "lssS", { Gv
, Mp
}, 0 },
8185 { "lfsS", { Gv
, Mp
}, 0 },
8189 { "lgsS", { Gv
, Mp
}, 0 },
8193 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8196 /* MOD_0FC7_REG_3 */
8197 { "xrstors", { FXSAVE
}, 0 },
8200 /* MOD_0FC7_REG_4 */
8201 { "xsavec", { FXSAVE
}, 0 },
8204 /* MOD_0FC7_REG_5 */
8205 { "xsaves", { FXSAVE
}, 0 },
8208 /* MOD_0FC7_REG_6 */
8209 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8210 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8213 /* MOD_0FC7_REG_7 */
8214 { "vmptrst", { Mq
}, 0 },
8215 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8220 { "pmovmskb", { Gdq
, MS
}, 0 },
8223 /* MOD_0FE7_PREFIX_2 */
8224 { "movntdq", { Mx
, XM
}, 0 },
8227 /* MOD_0FF0_PREFIX_3 */
8228 { "lddqu", { XM
, M
}, 0 },
8232 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8235 /* MOD_0F38DC_PREFIX_1 */
8236 { "aesenc128kl", { XM
, M
}, 0 },
8237 { "loadiwkey", { XM
, EXx
}, 0 },
8240 /* MOD_0F38DD_PREFIX_1 */
8241 { "aesdec128kl", { XM
, M
}, 0 },
8244 /* MOD_0F38DE_PREFIX_1 */
8245 { "aesenc256kl", { XM
, M
}, 0 },
8248 /* MOD_0F38DF_PREFIX_1 */
8249 { "aesdec256kl", { XM
, M
}, 0 },
8253 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8256 /* MOD_0F38F6_PREFIX_0 */
8257 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8260 /* MOD_0F38F8_PREFIX_1 */
8261 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8264 /* MOD_0F38F8_PREFIX_2 */
8265 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8268 /* MOD_0F38F8_PREFIX_3 */
8269 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8273 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8276 /* MOD_0F38FA_PREFIX_1 */
8278 { "encodekey128", { Gd
, Ed
}, 0 },
8281 /* MOD_0F38FB_PREFIX_1 */
8283 { "encodekey256", { Gd
, Ed
}, 0 },
8286 /* MOD_0F3A0F_PREFIX_1 */
8288 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8291 /* MOD_VEX_0F12_PREFIX_0 */
8292 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8293 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8296 /* MOD_VEX_0F12_PREFIX_2 */
8297 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8301 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8304 /* MOD_VEX_0F16_PREFIX_0 */
8305 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8306 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8309 /* MOD_VEX_0F16_PREFIX_2 */
8310 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8314 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8318 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8321 /* MOD_VEX_0F41_L_1 */
8323 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1
) },
8326 /* MOD_VEX_0F42_L_1 */
8328 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1
) },
8331 /* MOD_VEX_0F44_L_0 */
8333 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1
) },
8336 /* MOD_VEX_0F45_L_1 */
8338 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1
) },
8341 /* MOD_VEX_0F46_L_1 */
8343 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1
) },
8346 /* MOD_VEX_0F47_L_1 */
8348 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1
) },
8351 /* MOD_VEX_0F4A_L_1 */
8353 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1
) },
8356 /* MOD_VEX_0F4B_L_1 */
8358 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1
) },
8363 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8368 { REG_TABLE (REG_VEX_0F71_M_0
) },
8373 { REG_TABLE (REG_VEX_0F72_M_0
) },
8378 { REG_TABLE (REG_VEX_0F73_M_0
) },
8381 /* MOD_VEX_0F91_L_0 */
8382 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0
) },
8385 /* MOD_VEX_0F92_L_0 */
8387 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1
) },
8390 /* MOD_VEX_0F93_L_0 */
8392 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1
) },
8395 /* MOD_VEX_0F98_L_0 */
8397 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1
) },
8400 /* MOD_VEX_0F99_L_0 */
8402 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1
) },
8405 /* MOD_VEX_0FAE_REG_2 */
8406 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8409 /* MOD_VEX_0FAE_REG_3 */
8410 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8415 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8419 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8422 /* MOD_VEX_0FF0_PREFIX_3 */
8423 { "vlddqu", { XM
, M
}, 0 },
8426 /* MOD_VEX_0F381A */
8427 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8430 /* MOD_VEX_0F382A */
8431 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8434 /* MOD_VEX_0F382C */
8435 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8438 /* MOD_VEX_0F382D */
8439 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8442 /* MOD_VEX_0F382E */
8443 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8446 /* MOD_VEX_0F382F */
8447 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8450 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8451 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8452 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8455 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8456 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8459 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8461 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8464 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8465 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8468 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8469 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8472 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8473 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8476 /* MOD_VEX_0F385A */
8477 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8480 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8482 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8485 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8487 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8490 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8492 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8495 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8497 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8500 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8502 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8505 /* MOD_VEX_0F388C */
8506 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8509 /* MOD_VEX_0F388E */
8510 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8513 /* MOD_VEX_0F3A30_L_0 */
8515 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8518 /* MOD_VEX_0F3A31_L_0 */
8520 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8523 /* MOD_VEX_0F3A32_L_0 */
8525 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8528 /* MOD_VEX_0F3A33_L_0 */
8530 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8535 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8538 #include "i386-dis-evex-mod.h"
8541 static const struct dis386 rm_table
[][8] = {
8544 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8548 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8552 { "enclv", { Skip_MODRM
}, 0 },
8553 { "vmcall", { Skip_MODRM
}, 0 },
8554 { "vmlaunch", { Skip_MODRM
}, 0 },
8555 { "vmresume", { Skip_MODRM
}, 0 },
8556 { "vmxoff", { Skip_MODRM
}, 0 },
8557 { "pconfig", { Skip_MODRM
}, 0 },
8561 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8562 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8563 { "clac", { Skip_MODRM
}, 0 },
8564 { "stac", { Skip_MODRM
}, 0 },
8565 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8566 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8567 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8568 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8572 { "xgetbv", { Skip_MODRM
}, 0 },
8573 { "xsetbv", { Skip_MODRM
}, 0 },
8576 { "vmfunc", { Skip_MODRM
}, 0 },
8577 { "xend", { Skip_MODRM
}, 0 },
8578 { "xtest", { Skip_MODRM
}, 0 },
8579 { "enclu", { Skip_MODRM
}, 0 },
8583 { "vmrun", { Skip_MODRM
}, 0 },
8584 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8585 { "vmload", { Skip_MODRM
}, 0 },
8586 { "vmsave", { Skip_MODRM
}, 0 },
8587 { "stgi", { Skip_MODRM
}, 0 },
8588 { "clgi", { Skip_MODRM
}, 0 },
8589 { "skinit", { Skip_MODRM
}, 0 },
8590 { "invlpga", { Skip_MODRM
}, 0 },
8593 /* RM_0F01_REG_5_MOD_3 */
8594 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8595 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8596 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8598 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8599 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8600 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8601 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8604 /* RM_0F01_REG_7_MOD_3 */
8605 { "swapgs", { Skip_MODRM
}, 0 },
8606 { "rdtscp", { Skip_MODRM
}, 0 },
8607 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8608 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8609 { "clzero", { Skip_MODRM
}, 0 },
8610 { "rdpru", { Skip_MODRM
}, 0 },
8611 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
8612 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
8615 /* RM_0F1E_P_1_MOD_3_REG_7 */
8616 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8617 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8618 { "endbr64", { Skip_MODRM
}, 0 },
8619 { "endbr32", { Skip_MODRM
}, 0 },
8620 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8621 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8622 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8623 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8626 /* RM_0FAE_REG_6_MOD_3 */
8627 { "mfence", { Skip_MODRM
}, 0 },
8630 /* RM_0FAE_REG_7_MOD_3 */
8631 { "sfence", { Skip_MODRM
}, 0 },
8634 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8635 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8638 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8639 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8643 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8645 /* We use the high bit to indicate different name for the same
8647 #define REP_PREFIX (0xf3 | 0x100)
8648 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8649 #define XRELEASE_PREFIX (0xf3 | 0x400)
8650 #define BND_PREFIX (0xf2 | 0x400)
8651 #define NOTRACK_PREFIX (0x3e | 0x100)
8653 /* Remember if the current op is a jump instruction. */
8654 static bool op_is_jump
= false;
8659 int newrex
, i
, length
;
8665 last_lock_prefix
= -1;
8666 last_repz_prefix
= -1;
8667 last_repnz_prefix
= -1;
8668 last_data_prefix
= -1;
8669 last_addr_prefix
= -1;
8670 last_rex_prefix
= -1;
8671 last_seg_prefix
= -1;
8673 active_seg_prefix
= 0;
8674 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8675 all_prefixes
[i
] = 0;
8678 /* The maximum instruction length is 15bytes. */
8679 while (length
< MAX_CODE_LENGTH
- 1)
8681 FETCH_DATA (the_info
, codep
+ 1);
8685 /* REX prefixes family. */
8702 if (address_mode
== mode_64bit
)
8706 last_rex_prefix
= i
;
8709 prefixes
|= PREFIX_REPZ
;
8710 last_repz_prefix
= i
;
8713 prefixes
|= PREFIX_REPNZ
;
8714 last_repnz_prefix
= i
;
8717 prefixes
|= PREFIX_LOCK
;
8718 last_lock_prefix
= i
;
8721 prefixes
|= PREFIX_CS
;
8722 last_seg_prefix
= i
;
8724 if (address_mode
!= mode_64bit
)
8725 active_seg_prefix
= PREFIX_CS
;
8729 prefixes
|= PREFIX_SS
;
8730 last_seg_prefix
= i
;
8732 if (address_mode
!= mode_64bit
)
8733 active_seg_prefix
= PREFIX_SS
;
8737 prefixes
|= PREFIX_DS
;
8738 last_seg_prefix
= i
;
8740 if (address_mode
!= mode_64bit
)
8741 active_seg_prefix
= PREFIX_DS
;
8745 prefixes
|= PREFIX_ES
;
8746 last_seg_prefix
= i
;
8748 if (address_mode
!= mode_64bit
)
8749 active_seg_prefix
= PREFIX_ES
;
8753 prefixes
|= PREFIX_FS
;
8754 last_seg_prefix
= i
;
8755 active_seg_prefix
= PREFIX_FS
;
8758 prefixes
|= PREFIX_GS
;
8759 last_seg_prefix
= i
;
8760 active_seg_prefix
= PREFIX_GS
;
8763 prefixes
|= PREFIX_DATA
;
8764 last_data_prefix
= i
;
8767 prefixes
|= PREFIX_ADDR
;
8768 last_addr_prefix
= i
;
8771 /* fwait is really an instruction. If there are prefixes
8772 before the fwait, they belong to the fwait, *not* to the
8773 following instruction. */
8775 if (prefixes
|| rex
)
8777 prefixes
|= PREFIX_FWAIT
;
8779 /* This ensures that the previous REX prefixes are noticed
8780 as unused prefixes, as in the return case below. */
8784 prefixes
= PREFIX_FWAIT
;
8789 /* Rex is ignored when followed by another prefix. */
8795 if (*codep
!= FWAIT_OPCODE
)
8796 all_prefixes
[i
++] = *codep
;
8804 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8808 prefix_name (int pref
, int sizeflag
)
8810 static const char *rexes
[16] =
8815 "rex.XB", /* 0x43 */
8817 "rex.RB", /* 0x45 */
8818 "rex.RX", /* 0x46 */
8819 "rex.RXB", /* 0x47 */
8821 "rex.WB", /* 0x49 */
8822 "rex.WX", /* 0x4a */
8823 "rex.WXB", /* 0x4b */
8824 "rex.WR", /* 0x4c */
8825 "rex.WRB", /* 0x4d */
8826 "rex.WRX", /* 0x4e */
8827 "rex.WRXB", /* 0x4f */
8832 /* REX prefixes family. */
8849 return rexes
[pref
- 0x40];
8869 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8871 if (address_mode
== mode_64bit
)
8872 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8874 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8879 case XACQUIRE_PREFIX
:
8881 case XRELEASE_PREFIX
:
8885 case NOTRACK_PREFIX
:
8892 static char op_out
[MAX_OPERANDS
][100];
8893 static int op_ad
, op_index
[MAX_OPERANDS
];
8894 static int two_source_ops
;
8895 static bfd_vma op_address
[MAX_OPERANDS
];
8896 static bfd_vma op_riprel
[MAX_OPERANDS
];
8897 static bfd_vma start_pc
;
8900 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8901 * (see topic "Redundant prefixes" in the "Differences from 8086"
8902 * section of the "Virtual 8086 Mode" chapter.)
8903 * 'pc' should be the address of this instruction, it will
8904 * be used to print the target address if this is a relative jump or call
8905 * The function returns the length of this instruction in bytes.
8908 static char intel_syntax
;
8909 static char intel_mnemonic
= !SYSV386_COMPAT
;
8910 static char open_char
;
8911 static char close_char
;
8912 static char separator_char
;
8913 static char scale_char
;
8921 static enum x86_64_isa isa64
;
8923 /* Here for backwards compatibility. When gdb stops using
8924 print_insn_i386_att and print_insn_i386_intel these functions can
8925 disappear, and print_insn_i386 be merged into print_insn. */
8927 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
8931 return print_insn (pc
, info
);
8935 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
8939 return print_insn (pc
, info
);
8943 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
8947 return print_insn (pc
, info
);
8951 print_i386_disassembler_options (FILE *stream
)
8953 fprintf (stream
, _("\n\
8954 The following i386/x86-64 specific disassembler options are supported for use\n\
8955 with the -M switch (multiple options should be separated by commas):\n"));
8957 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
8958 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
8959 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
8960 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
8961 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
8962 fprintf (stream
, _(" att-mnemonic\n"
8963 " Display instruction in AT&T mnemonic\n"));
8964 fprintf (stream
, _(" intel-mnemonic\n"
8965 " Display instruction in Intel mnemonic\n"));
8966 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
8967 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
8968 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
8969 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
8970 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
8971 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8972 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
8973 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
8977 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
8979 /* Get a pointer to struct dis386 with a valid name. */
8981 static const struct dis386
*
8982 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
8984 int vindex
, vex_table_index
;
8986 if (dp
->name
!= NULL
)
8989 switch (dp
->op
[0].bytemode
)
8992 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
8996 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
8997 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
9001 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
9004 case USE_PREFIX_TABLE
:
9007 /* The prefix in VEX is implicit. */
9013 case REPE_PREFIX_OPCODE
:
9016 case DATA_PREFIX_OPCODE
:
9019 case REPNE_PREFIX_OPCODE
:
9029 int last_prefix
= -1;
9032 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9033 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9035 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9037 if (last_repz_prefix
> last_repnz_prefix
)
9040 prefix
= PREFIX_REPZ
;
9041 last_prefix
= last_repz_prefix
;
9046 prefix
= PREFIX_REPNZ
;
9047 last_prefix
= last_repnz_prefix
;
9050 /* Check if prefix should be ignored. */
9051 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
9052 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9054 && !prefix_table
[dp
->op
[1].bytemode
][vindex
].name
)
9058 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9061 prefix
= PREFIX_DATA
;
9062 last_prefix
= last_data_prefix
;
9067 used_prefixes
|= prefix
;
9068 all_prefixes
[last_prefix
] = 0;
9071 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9074 case USE_X86_64_TABLE
:
9075 vindex
= address_mode
== mode_64bit
? 1 : 0;
9076 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9079 case USE_3BYTE_TABLE
:
9080 FETCH_DATA (info
, codep
+ 2);
9082 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9084 modrm
.mod
= (*codep
>> 6) & 3;
9085 modrm
.reg
= (*codep
>> 3) & 7;
9086 modrm
.rm
= *codep
& 7;
9089 case USE_VEX_LEN_TABLE
:
9099 /* This allows re-using in particular table entries where only
9100 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9113 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9116 case USE_EVEX_LEN_TABLE
:
9136 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9139 case USE_XOP_8F_TABLE
:
9140 FETCH_DATA (info
, codep
+ 3);
9141 rex
= ~(*codep
>> 5) & 0x7;
9143 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9144 switch ((*codep
& 0x1f))
9150 vex_table_index
= XOP_08
;
9153 vex_table_index
= XOP_09
;
9156 vex_table_index
= XOP_0A
;
9160 vex
.w
= *codep
& 0x80;
9161 if (vex
.w
&& address_mode
== mode_64bit
)
9164 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9165 if (address_mode
!= mode_64bit
)
9167 /* In 16/32-bit mode REX_B is silently ignored. */
9171 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9172 switch ((*codep
& 0x3))
9177 vex
.prefix
= DATA_PREFIX_OPCODE
;
9180 vex
.prefix
= REPE_PREFIX_OPCODE
;
9183 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9189 dp
= &xop_table
[vex_table_index
][vindex
];
9192 FETCH_DATA (info
, codep
+ 1);
9193 modrm
.mod
= (*codep
>> 6) & 3;
9194 modrm
.reg
= (*codep
>> 3) & 7;
9195 modrm
.rm
= *codep
& 7;
9197 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9198 having to decode the bits for every otherwise valid encoding. */
9203 case USE_VEX_C4_TABLE
:
9205 FETCH_DATA (info
, codep
+ 3);
9206 rex
= ~(*codep
>> 5) & 0x7;
9207 switch ((*codep
& 0x1f))
9213 vex_table_index
= VEX_0F
;
9216 vex_table_index
= VEX_0F38
;
9219 vex_table_index
= VEX_0F3A
;
9223 vex
.w
= *codep
& 0x80;
9224 if (address_mode
== mode_64bit
)
9231 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9232 is ignored, other REX bits are 0 and the highest bit in
9233 VEX.vvvv is also ignored (but we mustn't clear it here). */
9236 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9237 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9238 switch ((*codep
& 0x3))
9243 vex
.prefix
= DATA_PREFIX_OPCODE
;
9246 vex
.prefix
= REPE_PREFIX_OPCODE
;
9249 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9255 dp
= &vex_table
[vex_table_index
][vindex
];
9257 /* There is no MODRM byte for VEX0F 77. */
9258 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9260 FETCH_DATA (info
, codep
+ 1);
9261 modrm
.mod
= (*codep
>> 6) & 3;
9262 modrm
.reg
= (*codep
>> 3) & 7;
9263 modrm
.rm
= *codep
& 7;
9267 case USE_VEX_C5_TABLE
:
9269 FETCH_DATA (info
, codep
+ 2);
9270 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9272 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9274 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9275 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9276 switch ((*codep
& 0x3))
9281 vex
.prefix
= DATA_PREFIX_OPCODE
;
9284 vex
.prefix
= REPE_PREFIX_OPCODE
;
9287 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9293 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9295 /* There is no MODRM byte for VEX 77. */
9298 FETCH_DATA (info
, codep
+ 1);
9299 modrm
.mod
= (*codep
>> 6) & 3;
9300 modrm
.reg
= (*codep
>> 3) & 7;
9301 modrm
.rm
= *codep
& 7;
9305 case USE_VEX_W_TABLE
:
9309 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9312 case USE_EVEX_TABLE
:
9316 FETCH_DATA (info
, codep
+ 4);
9317 /* The first byte after 0x62. */
9318 rex
= ~(*codep
>> 5) & 0x7;
9319 vex
.r
= *codep
& 0x10;
9320 switch ((*codep
& 0xf))
9325 vex_table_index
= EVEX_0F
;
9328 vex_table_index
= EVEX_0F38
;
9331 vex_table_index
= EVEX_0F3A
;
9334 vex_table_index
= EVEX_MAP5
;
9337 vex_table_index
= EVEX_MAP6
;
9341 /* The second byte after 0x62. */
9343 vex
.w
= *codep
& 0x80;
9344 if (vex
.w
&& address_mode
== mode_64bit
)
9347 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9350 if (!(*codep
& 0x4))
9353 switch ((*codep
& 0x3))
9358 vex
.prefix
= DATA_PREFIX_OPCODE
;
9361 vex
.prefix
= REPE_PREFIX_OPCODE
;
9364 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9368 /* The third byte after 0x62. */
9371 /* Remember the static rounding bits. */
9372 vex
.ll
= (*codep
>> 5) & 3;
9373 vex
.b
= (*codep
& 0x10) != 0;
9375 vex
.v
= *codep
& 0x8;
9376 vex
.mask_register_specifier
= *codep
& 0x7;
9377 vex
.zeroing
= *codep
& 0x80;
9379 if (address_mode
!= mode_64bit
)
9381 /* In 16/32-bit mode silently ignore following bits. */
9389 dp
= &evex_table
[vex_table_index
][vindex
];
9391 FETCH_DATA (info
, codep
+ 1);
9392 modrm
.mod
= (*codep
>> 6) & 3;
9393 modrm
.reg
= (*codep
>> 3) & 7;
9394 modrm
.rm
= *codep
& 7;
9396 /* Set vector length. */
9397 if (modrm
.mod
== 3 && vex
.b
)
9426 if (dp
->name
!= NULL
)
9429 return get_valid_dis386 (dp
, info
);
9433 get_sib (disassemble_info
*info
, int sizeflag
)
9435 /* If modrm.mod == 3, operand must be register. */
9437 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9441 FETCH_DATA (info
, codep
+ 2);
9442 sib
.index
= (codep
[1] >> 3) & 7;
9443 sib
.scale
= (codep
[1] >> 6) & 3;
9444 sib
.base
= codep
[1] & 7;
9449 print_insn (bfd_vma pc
, disassemble_info
*info
)
9451 const struct dis386
*dp
;
9453 char *op_txt
[MAX_OPERANDS
];
9455 int sizeflag
, orig_sizeflag
;
9457 struct dis_private priv
;
9460 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9461 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9462 address_mode
= mode_32bit
;
9463 else if (info
->mach
== bfd_mach_i386_i8086
)
9465 address_mode
= mode_16bit
;
9466 priv
.orig_sizeflag
= 0;
9469 address_mode
= mode_64bit
;
9471 if (intel_syntax
== (char) -1)
9472 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9474 for (p
= info
->disassembler_options
; p
!= NULL
; )
9476 if (startswith (p
, "amd64"))
9478 else if (startswith (p
, "intel64"))
9480 else if (startswith (p
, "x86-64"))
9482 address_mode
= mode_64bit
;
9483 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9485 else if (startswith (p
, "i386"))
9487 address_mode
= mode_32bit
;
9488 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9490 else if (startswith (p
, "i8086"))
9492 address_mode
= mode_16bit
;
9493 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9495 else if (startswith (p
, "intel"))
9498 if (startswith (p
+ 5, "-mnemonic"))
9501 else if (startswith (p
, "att"))
9504 if (startswith (p
+ 3, "-mnemonic"))
9507 else if (startswith (p
, "addr"))
9509 if (address_mode
== mode_64bit
)
9511 if (p
[4] == '3' && p
[5] == '2')
9512 priv
.orig_sizeflag
&= ~AFLAG
;
9513 else if (p
[4] == '6' && p
[5] == '4')
9514 priv
.orig_sizeflag
|= AFLAG
;
9518 if (p
[4] == '1' && p
[5] == '6')
9519 priv
.orig_sizeflag
&= ~AFLAG
;
9520 else if (p
[4] == '3' && p
[5] == '2')
9521 priv
.orig_sizeflag
|= AFLAG
;
9524 else if (startswith (p
, "data"))
9526 if (p
[4] == '1' && p
[5] == '6')
9527 priv
.orig_sizeflag
&= ~DFLAG
;
9528 else if (p
[4] == '3' && p
[5] == '2')
9529 priv
.orig_sizeflag
|= DFLAG
;
9531 else if (startswith (p
, "suffix"))
9532 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9534 p
= strchr (p
, ',');
9539 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9541 (*info
->fprintf_func
) (info
->stream
,
9542 _("64-bit address is disabled"));
9548 names64
= intel_names64
;
9549 names32
= intel_names32
;
9550 names16
= intel_names16
;
9551 names8
= intel_names8
;
9552 names8rex
= intel_names8rex
;
9553 names_seg
= intel_names_seg
;
9554 names_mm
= intel_names_mm
;
9555 names_bnd
= intel_names_bnd
;
9556 names_xmm
= intel_names_xmm
;
9557 names_ymm
= intel_names_ymm
;
9558 names_zmm
= intel_names_zmm
;
9559 names_tmm
= intel_names_tmm
;
9560 index64
= intel_index64
;
9561 index32
= intel_index32
;
9562 names_mask
= intel_names_mask
;
9563 index16
= intel_index16
;
9566 separator_char
= '+';
9571 names64
= att_names64
;
9572 names32
= att_names32
;
9573 names16
= att_names16
;
9574 names8
= att_names8
;
9575 names8rex
= att_names8rex
;
9576 names_seg
= att_names_seg
;
9577 names_mm
= att_names_mm
;
9578 names_bnd
= att_names_bnd
;
9579 names_xmm
= att_names_xmm
;
9580 names_ymm
= att_names_ymm
;
9581 names_zmm
= att_names_zmm
;
9582 names_tmm
= att_names_tmm
;
9583 index64
= att_index64
;
9584 index32
= att_index32
;
9585 names_mask
= att_names_mask
;
9586 index16
= att_index16
;
9589 separator_char
= ',';
9593 /* The output looks better if we put 7 bytes on a line, since that
9594 puts most long word instructions on a single line. Use 8 bytes
9596 if ((info
->mach
& bfd_mach_l1om
) != 0)
9597 info
->bytes_per_line
= 8;
9599 info
->bytes_per_line
= 7;
9601 info
->private_data
= &priv
;
9602 priv
.max_fetched
= priv
.the_buffer
;
9603 priv
.insn_start
= pc
;
9606 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9614 start_codep
= priv
.the_buffer
;
9615 codep
= priv
.the_buffer
;
9617 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9621 /* Getting here means we tried for data but didn't get it. That
9622 means we have an incomplete instruction of some sort. Just
9623 print the first byte as a prefix or a .byte pseudo-op. */
9624 if (codep
> priv
.the_buffer
)
9626 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9628 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9631 /* Just print the first byte as a .byte instruction. */
9632 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9633 (unsigned int) priv
.the_buffer
[0]);
9643 sizeflag
= priv
.orig_sizeflag
;
9645 if (!ckprefix () || rex_used
)
9647 /* Too many prefixes or unused REX prefixes. */
9649 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9651 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9653 prefix_name (all_prefixes
[i
], sizeflag
));
9659 FETCH_DATA (info
, codep
+ 1);
9660 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9662 if (((prefixes
& PREFIX_FWAIT
)
9663 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9665 /* Handle prefixes before fwait. */
9666 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9668 (*info
->fprintf_func
) (info
->stream
, "%s ",
9669 prefix_name (all_prefixes
[i
], sizeflag
));
9670 (*info
->fprintf_func
) (info
->stream
, "fwait");
9676 unsigned char threebyte
;
9679 FETCH_DATA (info
, codep
+ 1);
9681 dp
= &dis386_twobyte
[threebyte
];
9682 need_modrm
= twobyte_has_modrm
[threebyte
];
9687 dp
= &dis386
[*codep
];
9688 need_modrm
= onebyte_has_modrm
[*codep
];
9692 /* Save sizeflag for printing the extra prefixes later before updating
9693 it for mnemonic and operand processing. The prefix names depend
9694 only on the address mode. */
9695 orig_sizeflag
= sizeflag
;
9696 if (prefixes
& PREFIX_ADDR
)
9698 if ((prefixes
& PREFIX_DATA
))
9704 FETCH_DATA (info
, codep
+ 1);
9705 modrm
.mod
= (*codep
>> 6) & 3;
9706 modrm
.reg
= (*codep
>> 3) & 7;
9707 modrm
.rm
= *codep
& 7;
9710 memset (&modrm
, 0, sizeof (modrm
));
9713 memset (&vex
, 0, sizeof (vex
));
9715 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9717 get_sib (info
, sizeflag
);
9722 dp
= get_valid_dis386 (dp
, info
);
9723 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9725 get_sib (info
, sizeflag
);
9726 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9729 op_ad
= MAX_OPERANDS
- 1 - i
;
9731 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9732 /* For EVEX instruction after the last operand masking
9733 should be printed. */
9734 if (i
== 0 && vex
.evex
)
9736 /* Don't print {%k0}. */
9737 if (vex
.mask_register_specifier
)
9740 oappend (names_mask
[vex
.mask_register_specifier
]);
9746 /* S/G insns require a mask and don't allow
9748 if ((dp
->op
[0].bytemode
== vex_vsib_d_w_dq_mode
9749 || dp
->op
[0].bytemode
== vex_vsib_q_w_dq_mode
)
9750 && (vex
.mask_register_specifier
== 0 || vex
.zeroing
))
9755 /* Check whether rounding control was enabled for an insn not
9757 if (modrm
.mod
== 3 && vex
.b
&& !(evex_used
& EVEX_b_used
))
9759 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9764 oappend (names_rounding
[vex
.ll
]);
9772 /* Clear instruction information. */
9775 the_info
->insn_info_valid
= 0;
9776 the_info
->branch_delay_insns
= 0;
9777 the_info
->data_size
= 0;
9778 the_info
->insn_type
= dis_noninsn
;
9779 the_info
->target
= 0;
9780 the_info
->target2
= 0;
9783 /* Reset jump operation indicator. */
9787 int jump_detection
= 0;
9789 /* Extract flags. */
9790 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9792 if ((dp
->op
[i
].rtn
== OP_J
)
9793 || (dp
->op
[i
].rtn
== OP_indirE
))
9794 jump_detection
|= 1;
9795 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9796 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9797 jump_detection
|= 2;
9798 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9799 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9800 jump_detection
|= 4;
9803 /* Determine if this is a jump or branch. */
9804 if ((jump_detection
& 0x3) == 0x3)
9807 if (jump_detection
& 0x4)
9808 the_info
->insn_type
= dis_condbranch
;
9810 the_info
->insn_type
=
9811 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9812 ? dis_jsr
: dis_branch
;
9816 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9817 are all 0s in inverted form. */
9818 if (need_vex
&& vex
.register_specifier
!= 0)
9820 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9821 return end_codep
- priv
.the_buffer
;
9824 /* If EVEX.z is set, there must be an actual mask register in use. */
9825 if (vex
.zeroing
&& vex
.mask_register_specifier
== 0)
9827 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9828 return end_codep
- priv
.the_buffer
;
9831 switch (dp
->prefix_requirement
)
9834 /* If only the data prefix is marked as mandatory, its absence renders
9835 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9836 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9838 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9839 return end_codep
- priv
.the_buffer
;
9841 used_prefixes
|= PREFIX_DATA
;
9844 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9845 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9846 used by putop and MMX/SSE operand and may be overridden by the
9847 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9850 ? vex
.prefix
== REPE_PREFIX_OPCODE
9851 || vex
.prefix
== REPNE_PREFIX_OPCODE
9853 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9855 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9857 ? vex
.prefix
== DATA_PREFIX_OPCODE
9859 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9861 && (used_prefixes
& PREFIX_DATA
) == 0))
9862 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9863 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9865 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9866 return end_codep
- priv
.the_buffer
;
9870 case PREFIX_IGNORED
:
9871 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9872 origins in all_prefixes. */
9873 used_prefixes
&= ~PREFIX_OPCODE
;
9874 if (last_data_prefix
>= 0)
9875 all_prefixes
[last_data_prefix
] = 0x66;
9876 if (last_repz_prefix
>= 0)
9877 all_prefixes
[last_repz_prefix
] = 0xf3;
9878 if (last_repnz_prefix
>= 0)
9879 all_prefixes
[last_repnz_prefix
] = 0xf2;
9883 /* Check if the REX prefix is used. */
9884 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9885 all_prefixes
[last_rex_prefix
] = 0;
9887 /* Check if the SEG prefix is used. */
9888 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9889 | PREFIX_FS
| PREFIX_GS
)) != 0
9890 && (used_prefixes
& active_seg_prefix
) != 0)
9891 all_prefixes
[last_seg_prefix
] = 0;
9893 /* Check if the ADDR prefix is used. */
9894 if ((prefixes
& PREFIX_ADDR
) != 0
9895 && (used_prefixes
& PREFIX_ADDR
) != 0)
9896 all_prefixes
[last_addr_prefix
] = 0;
9898 /* Check if the DATA prefix is used. */
9899 if ((prefixes
& PREFIX_DATA
) != 0
9900 && (used_prefixes
& PREFIX_DATA
) != 0
9902 all_prefixes
[last_data_prefix
] = 0;
9904 /* Print the extra prefixes. */
9906 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9907 if (all_prefixes
[i
])
9910 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9913 prefix_length
+= strlen (name
) + 1;
9914 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9917 /* Check maximum code length. */
9918 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9920 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9921 return MAX_CODE_LENGTH
;
9924 obufp
= mnemonicendp
;
9925 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9928 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9930 /* The enter and bound instructions are printed with operands in the same
9931 order as the intel book; everything else is printed in reverse order. */
9932 if (intel_syntax
|| two_source_ops
)
9936 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9937 op_txt
[i
] = op_out
[i
];
9939 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9940 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9942 op_txt
[2] = op_out
[3];
9943 op_txt
[3] = op_out
[2];
9946 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
9948 op_ad
= op_index
[i
];
9949 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
9950 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
9951 riprel
= op_riprel
[i
];
9952 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
9953 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
9958 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9959 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
9963 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9967 (*info
->fprintf_func
) (info
->stream
, ",");
9968 if (op_index
[i
] != -1 && !op_riprel
[i
])
9970 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
9972 if (the_info
&& op_is_jump
)
9974 the_info
->insn_info_valid
= 1;
9975 the_info
->branch_delay_insns
= 0;
9976 the_info
->data_size
= 0;
9977 the_info
->target
= target
;
9978 the_info
->target2
= 0;
9980 (*info
->print_address_func
) (target
, info
);
9983 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
9987 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9988 if (op_index
[i
] != -1 && op_riprel
[i
])
9990 (*info
->fprintf_func
) (info
->stream
, " # ");
9991 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
9992 + op_address
[op_index
[i
]]), info
);
9995 return codep
- priv
.the_buffer
;
9998 static const char *float_mem
[] = {
10073 static const unsigned char float_mem_mode
[] = {
10148 #define ST { OP_ST, 0 }
10149 #define STi { OP_STi, 0 }
10151 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10152 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10153 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10154 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10155 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10156 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10157 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10158 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10159 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10161 static const struct dis386 float_reg
[][8] = {
10164 { "fadd", { ST
, STi
}, 0 },
10165 { "fmul", { ST
, STi
}, 0 },
10166 { "fcom", { STi
}, 0 },
10167 { "fcomp", { STi
}, 0 },
10168 { "fsub", { ST
, STi
}, 0 },
10169 { "fsubr", { ST
, STi
}, 0 },
10170 { "fdiv", { ST
, STi
}, 0 },
10171 { "fdivr", { ST
, STi
}, 0 },
10175 { "fld", { STi
}, 0 },
10176 { "fxch", { STi
}, 0 },
10186 { "fcmovb", { ST
, STi
}, 0 },
10187 { "fcmove", { ST
, STi
}, 0 },
10188 { "fcmovbe",{ ST
, STi
}, 0 },
10189 { "fcmovu", { ST
, STi
}, 0 },
10197 { "fcmovnb",{ ST
, STi
}, 0 },
10198 { "fcmovne",{ ST
, STi
}, 0 },
10199 { "fcmovnbe",{ ST
, STi
}, 0 },
10200 { "fcmovnu",{ ST
, STi
}, 0 },
10202 { "fucomi", { ST
, STi
}, 0 },
10203 { "fcomi", { ST
, STi
}, 0 },
10208 { "fadd", { STi
, ST
}, 0 },
10209 { "fmul", { STi
, ST
}, 0 },
10212 { "fsub{!M|r}", { STi
, ST
}, 0 },
10213 { "fsub{M|}", { STi
, ST
}, 0 },
10214 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10215 { "fdiv{M|}", { STi
, ST
}, 0 },
10219 { "ffree", { STi
}, 0 },
10221 { "fst", { STi
}, 0 },
10222 { "fstp", { STi
}, 0 },
10223 { "fucom", { STi
}, 0 },
10224 { "fucomp", { STi
}, 0 },
10230 { "faddp", { STi
, ST
}, 0 },
10231 { "fmulp", { STi
, ST
}, 0 },
10234 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10235 { "fsub{M|}p", { STi
, ST
}, 0 },
10236 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10237 { "fdiv{M|}p", { STi
, ST
}, 0 },
10241 { "ffreep", { STi
}, 0 },
10246 { "fucomip", { ST
, STi
}, 0 },
10247 { "fcomip", { ST
, STi
}, 0 },
10252 static char *fgrps
[][8] = {
10255 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10260 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10265 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10270 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10275 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10280 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10285 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10290 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10291 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10296 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10301 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10306 swap_operand (void)
10308 mnemonicendp
[0] = '.';
10309 mnemonicendp
[1] = 's';
10310 mnemonicendp
[2] = '\0';
10315 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10316 int sizeflag ATTRIBUTE_UNUSED
)
10318 /* Skip mod/rm byte. */
10324 dofloat (int sizeflag
)
10326 const struct dis386
*dp
;
10327 unsigned char floatop
;
10329 floatop
= codep
[-1];
10331 if (modrm
.mod
!= 3)
10333 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10335 putop (float_mem
[fp_indx
], sizeflag
);
10338 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10341 /* Skip mod/rm byte. */
10345 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10346 if (dp
->name
== NULL
)
10348 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10350 /* Instruction fnstsw is only one with strange arg. */
10351 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10352 strcpy (op_out
[0], names16
[0]);
10356 putop (dp
->name
, sizeflag
);
10361 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10366 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10370 /* Like oappend (below), but S is a string starting with '%'.
10371 In Intel syntax, the '%' is elided. */
10373 oappend_maybe_intel (const char *s
)
10375 oappend (s
+ intel_syntax
);
10379 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10381 oappend_maybe_intel ("%st");
10385 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10387 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10388 oappend_maybe_intel (scratchbuf
);
10391 /* Capital letters in template are macros. */
10393 putop (const char *in_template
, int sizeflag
)
10398 unsigned int l
= 0, len
= 0;
10401 for (p
= in_template
; *p
; p
++)
10405 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10424 while (*++p
!= '|')
10425 if (*p
== '}' || *p
== '\0')
10431 while (*++p
!= '}')
10443 if ((need_modrm
&& modrm
.mod
!= 3)
10444 || (sizeflag
& SUFFIX_ALWAYS
))
10453 if (sizeflag
& SUFFIX_ALWAYS
)
10456 else if (l
== 1 && last
[0] == 'L')
10458 if (address_mode
== mode_64bit
10459 && !(prefixes
& PREFIX_ADDR
))
10472 if (intel_syntax
&& !alt
)
10474 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10476 if (sizeflag
& DFLAG
)
10477 *obufp
++ = intel_syntax
? 'd' : 'l';
10479 *obufp
++ = intel_syntax
? 'w' : 's';
10480 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10484 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10487 if (modrm
.mod
== 3)
10493 if (sizeflag
& DFLAG
)
10494 *obufp
++ = intel_syntax
? 'd' : 'l';
10497 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10503 case 'E': /* For jcxz/jecxz */
10504 if (address_mode
== mode_64bit
)
10506 if (sizeflag
& AFLAG
)
10512 if (sizeflag
& AFLAG
)
10514 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10519 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10521 if (sizeflag
& AFLAG
)
10522 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10524 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10525 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10529 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10531 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10535 if (!(rex
& REX_W
))
10536 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10543 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10544 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10546 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10550 /* Set active_seg_prefix even if not set in 64-bit mode
10551 because here it is a valid branch hint. */
10552 if (prefixes
& PREFIX_DS
)
10554 active_seg_prefix
= PREFIX_DS
;
10559 active_seg_prefix
= PREFIX_CS
;
10564 else if (l
== 1 && last
[0] == 'X')
10590 if (intel_mnemonic
!= cond
)
10594 if ((prefixes
& PREFIX_FWAIT
) == 0)
10597 used_prefixes
|= PREFIX_FWAIT
;
10603 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10607 if (!(rex
& REX_W
))
10608 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10611 if (address_mode
== mode_64bit
10612 && (isa64
== intel64
|| (rex
& REX_W
)
10613 || !(prefixes
& PREFIX_DATA
)))
10615 if (sizeflag
& SUFFIX_ALWAYS
)
10619 /* Fall through. */
10623 if ((modrm
.mod
== 3 || !cond
)
10624 && !(sizeflag
& SUFFIX_ALWAYS
))
10626 /* Fall through. */
10628 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10629 || ((sizeflag
& SUFFIX_ALWAYS
)
10630 && address_mode
!= mode_64bit
))
10632 *obufp
++ = (sizeflag
& DFLAG
) ?
10633 intel_syntax
? 'd' : 'l' : 'w';
10634 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10636 else if (sizeflag
& SUFFIX_ALWAYS
)
10639 else if (l
== 1 && last
[0] == 'L')
10641 if ((prefixes
& PREFIX_DATA
)
10643 || (sizeflag
& SUFFIX_ALWAYS
))
10650 if (sizeflag
& DFLAG
)
10651 *obufp
++ = intel_syntax
? 'd' : 'l';
10654 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10664 if (intel_syntax
&& !alt
)
10667 if ((need_modrm
&& modrm
.mod
!= 3)
10668 || (sizeflag
& SUFFIX_ALWAYS
))
10674 if (sizeflag
& DFLAG
)
10675 *obufp
++ = intel_syntax
? 'd' : 'l';
10678 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10682 else if (l
== 1 && last
[0] == 'D')
10683 *obufp
++ = vex
.w
? 'q' : 'd';
10684 else if (l
== 1 && last
[0] == 'L')
10686 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10687 : address_mode
!= mode_64bit
)
10694 else if((address_mode
== mode_64bit
&& cond
)
10695 || (sizeflag
& SUFFIX_ALWAYS
))
10696 *obufp
++ = intel_syntax
? 'd' : 'l';
10705 else if (sizeflag
& DFLAG
)
10714 if (intel_syntax
&& !p
[1]
10715 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10717 if (!(rex
& REX_W
))
10718 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10726 if (sizeflag
& SUFFIX_ALWAYS
)
10732 if (sizeflag
& DFLAG
)
10736 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10740 else if (l
== 1 && last
[0] == 'L')
10742 if (address_mode
== mode_64bit
10743 && !(prefixes
& PREFIX_ADDR
))
10759 && (last
[0] == 'L' || last
[0] == 'X'))
10761 if (last
[0] == 'X')
10769 else if (rex
& REX_W
)
10782 /* operand size flag for cwtl, cbtw */
10791 else if (sizeflag
& DFLAG
)
10795 if (!(rex
& REX_W
))
10796 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10802 if (last
[0] == 'X')
10803 *obufp
++ = vex
.w
? 'd': 's';
10804 else if (last
[0] == 'B')
10805 *obufp
++ = vex
.w
? 'w': 'b';
10816 ? vex
.prefix
== DATA_PREFIX_OPCODE
10817 : prefixes
& PREFIX_DATA
)
10820 used_prefixes
|= PREFIX_DATA
;
10826 if (l
== 1 && last
[0] == 'X')
10831 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10833 switch (vex
.length
)
10853 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10855 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10856 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10858 else if (l
== 1 && last
[0] == 'X')
10863 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10865 switch (vex
.length
)
10886 if (isa64
== intel64
&& (rex
& REX_W
))
10892 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10894 if (sizeflag
& DFLAG
)
10898 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10907 mnemonicendp
= obufp
;
10912 oappend (const char *s
)
10914 obufp
= stpcpy (obufp
, s
);
10920 /* Only print the active segment register. */
10921 if (!active_seg_prefix
)
10924 used_prefixes
|= active_seg_prefix
;
10925 switch (active_seg_prefix
)
10928 oappend_maybe_intel ("%cs:");
10931 oappend_maybe_intel ("%ds:");
10934 oappend_maybe_intel ("%ss:");
10937 oappend_maybe_intel ("%es:");
10940 oappend_maybe_intel ("%fs:");
10943 oappend_maybe_intel ("%gs:");
10951 OP_indirE (int bytemode
, int sizeflag
)
10955 OP_E (bytemode
, sizeflag
);
10959 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10961 if (address_mode
== mode_64bit
)
10969 sprintf_vma (tmp
, disp
);
10970 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10971 strcpy (buf
+ 2, tmp
+ i
);
10975 bfd_signed_vma v
= disp
;
10982 /* Check for possible overflow on 0x8000000000000000. */
10985 strcpy (buf
, "9223372036854775808");
10999 tmp
[28 - i
] = (v
% 10) + '0';
11003 strcpy (buf
, tmp
+ 29 - i
);
11009 sprintf (buf
, "0x%x", (unsigned int) disp
);
11011 sprintf (buf
, "%d", (int) disp
);
11015 /* Put DISP in BUF as signed hex number. */
11018 print_displacement (char *buf
, bfd_vma disp
)
11020 bfd_signed_vma val
= disp
;
11029 /* Check for possible overflow. */
11032 switch (address_mode
)
11035 strcpy (buf
+ j
, "0x8000000000000000");
11038 strcpy (buf
+ j
, "0x80000000");
11041 strcpy (buf
+ j
, "0x8000");
11051 sprintf_vma (tmp
, (bfd_vma
) val
);
11052 for (i
= 0; tmp
[i
] == '0'; i
++)
11054 if (tmp
[i
] == '\0')
11056 strcpy (buf
+ j
, tmp
+ i
);
11060 intel_operand_size (int bytemode
, int sizeflag
)
11064 if (!vex
.no_broadcast
)
11068 case evex_half_bcst_xmmq_mode
:
11070 oappend ("QWORD PTR ");
11072 oappend ("DWORD PTR ");
11075 case evex_half_bcst_xmmqh_mode
:
11076 case evex_half_bcst_xmmqdh_mode
:
11077 oappend ("WORD PTR ");
11080 vex
.no_broadcast
= 1;
11090 oappend ("BYTE PTR ");
11095 oappend ("WORD PTR ");
11098 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11100 oappend ("QWORD PTR ");
11103 /* Fall through. */
11105 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11107 oappend ("QWORD PTR ");
11110 /* Fall through. */
11116 oappend ("QWORD PTR ");
11117 else if (bytemode
== dq_mode
)
11118 oappend ("DWORD PTR ");
11121 if (sizeflag
& DFLAG
)
11122 oappend ("DWORD PTR ");
11124 oappend ("WORD PTR ");
11125 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11129 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11131 oappend ("WORD PTR ");
11132 if (!(rex
& REX_W
))
11133 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11136 if (sizeflag
& DFLAG
)
11137 oappend ("QWORD PTR ");
11139 oappend ("DWORD PTR ");
11140 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11143 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11144 oappend ("WORD PTR ");
11146 oappend ("DWORD PTR ");
11147 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11151 oappend ("DWORD PTR ");
11155 oappend ("QWORD PTR ");
11158 if (address_mode
== mode_64bit
)
11159 oappend ("QWORD PTR ");
11161 oappend ("DWORD PTR ");
11164 if (sizeflag
& DFLAG
)
11165 oappend ("FWORD PTR ");
11167 oappend ("DWORD PTR ");
11168 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11171 oappend ("TBYTE PTR ");
11176 case evex_x_gscat_mode
:
11177 case evex_x_nobcst_mode
:
11181 switch (vex
.length
)
11184 oappend ("XMMWORD PTR ");
11187 oappend ("YMMWORD PTR ");
11190 oappend ("ZMMWORD PTR ");
11197 oappend ("XMMWORD PTR ");
11200 oappend ("XMMWORD PTR ");
11203 oappend ("YMMWORD PTR ");
11206 case evex_half_bcst_xmmqh_mode
:
11207 case evex_half_bcst_xmmq_mode
:
11211 switch (vex
.length
)
11214 oappend ("QWORD PTR ");
11217 oappend ("XMMWORD PTR ");
11220 oappend ("YMMWORD PTR ");
11230 switch (vex
.length
)
11233 oappend ("WORD PTR ");
11236 oappend ("DWORD PTR ");
11239 oappend ("QWORD PTR ");
11246 case evex_half_bcst_xmmqdh_mode
:
11250 switch (vex
.length
)
11253 oappend ("DWORD PTR ");
11256 oappend ("QWORD PTR ");
11259 oappend ("XMMWORD PTR ");
11269 switch (vex
.length
)
11272 oappend ("QWORD PTR ");
11275 oappend ("YMMWORD PTR ");
11278 oappend ("ZMMWORD PTR ");
11288 switch (vex
.length
)
11292 oappend ("XMMWORD PTR ");
11299 oappend ("OWORD PTR ");
11301 case vex_vsib_d_w_dq_mode
:
11302 case vex_vsib_q_w_dq_mode
:
11307 oappend ("QWORD PTR ");
11309 oappend ("DWORD PTR ");
11312 if (!need_vex
|| vex
.length
!= 128)
11315 oappend ("DWORD PTR ");
11317 oappend ("BYTE PTR ");
11323 oappend ("QWORD PTR ");
11325 oappend ("WORD PTR ");
11335 print_register (unsigned int reg
, unsigned int rexmask
, int bytemode
, int sizeflag
)
11337 const char **names
;
11339 USED_REX (rexmask
);
11367 names
= address_mode
== mode_64bit
? names64
: names32
;
11370 case bnd_swap_mode
:
11379 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11384 /* Fall through. */
11386 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11392 /* Fall through. */
11399 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11403 if (sizeflag
& DFLAG
)
11407 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11411 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11415 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11418 names
= (address_mode
== mode_64bit
11419 ? names64
: names32
);
11420 if (!(prefixes
& PREFIX_ADDR
))
11421 names
= (address_mode
== mode_16bit
11422 ? names16
: names
);
11425 /* Remove "addr16/addr32". */
11426 all_prefixes
[last_addr_prefix
] = 0;
11427 names
= (address_mode
!= mode_32bit
11428 ? names32
: names16
);
11429 used_prefixes
|= PREFIX_ADDR
;
11439 names
= names_mask
;
11444 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11447 oappend (names
[reg
]);
11451 OP_E_memory (int bytemode
, int sizeflag
)
11454 int add
= (rex
& REX_B
) ? 8 : 0;
11472 if (address_mode
!= mode_64bit
)
11480 case vex_vsib_d_w_dq_mode
:
11481 case vex_vsib_q_w_dq_mode
:
11482 case evex_x_gscat_mode
:
11483 shift
= vex
.w
? 3 : 2;
11486 case evex_half_bcst_xmmqh_mode
:
11487 case evex_half_bcst_xmmqdh_mode
:
11490 shift
= vex
.w
? 2 : 1;
11493 /* Fall through. */
11495 case evex_half_bcst_xmmq_mode
:
11498 shift
= vex
.w
? 3 : 2;
11501 /* Fall through. */
11506 case evex_x_nobcst_mode
:
11508 switch (vex
.length
)
11522 /* Make necessary corrections to shift for modes that need it. */
11523 if (bytemode
== xmmq_mode
11524 || bytemode
== evex_half_bcst_xmmqh_mode
11525 || bytemode
== evex_half_bcst_xmmq_mode
11526 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11528 else if (bytemode
== xmmqd_mode
11529 || bytemode
== evex_half_bcst_xmmqdh_mode
)
11531 else if (bytemode
== xmmdw_mode
)
11545 shift
= vex
.w
? 1 : 0;
11556 intel_operand_size (bytemode
, sizeflag
);
11559 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11561 /* 32/64 bit address mode */
11571 int addr32flag
= !((sizeflag
& AFLAG
)
11572 || bytemode
== v_bnd_mode
11573 || bytemode
== v_bndmk_mode
11574 || bytemode
== bnd_mode
11575 || bytemode
== bnd_swap_mode
);
11576 bool check_gather
= false;
11577 const char **indexes64
= names64
;
11578 const char **indexes32
= names32
;
11588 vindex
= sib
.index
;
11594 case vex_vsib_d_w_dq_mode
:
11595 case vex_vsib_q_w_dq_mode
:
11602 check_gather
= obufp
== op_out
[1];
11606 switch (vex
.length
)
11609 indexes64
= indexes32
= names_xmm
;
11613 || bytemode
== vex_vsib_q_w_dq_mode
)
11614 indexes64
= indexes32
= names_ymm
;
11616 indexes64
= indexes32
= names_xmm
;
11620 || bytemode
== vex_vsib_q_w_dq_mode
)
11621 indexes64
= indexes32
= names_zmm
;
11623 indexes64
= indexes32
= names_ymm
;
11630 haveindex
= vindex
!= 4;
11639 /* Check for mandatory SIB. */
11640 if (bytemode
== vex_vsib_d_w_dq_mode
11641 || bytemode
== vex_vsib_q_w_dq_mode
11642 || bytemode
== vex_sibmem_mode
)
11648 rbase
= base
+ add
;
11656 if (address_mode
== mode_64bit
&& !havesib
)
11659 if (riprel
&& bytemode
== v_bndmk_mode
)
11667 FETCH_DATA (the_info
, codep
+ 1);
11669 if ((disp
& 0x80) != 0)
11671 if (vex
.evex
&& shift
> 0)
11684 && address_mode
!= mode_16bit
)
11686 if (address_mode
== mode_64bit
)
11690 /* Without base nor index registers, zero-extend the
11691 lower 32-bit displacement to 64 bits. */
11692 disp
= (unsigned int) disp
;
11699 /* In 32-bit mode, we need index register to tell [offset]
11700 from [eiz*1 + offset]. */
11705 havedisp
= (havebase
11707 || (havesib
&& (haveindex
|| scale
!= 0)));
11710 if (modrm
.mod
!= 0 || base
== 5)
11712 if (havedisp
|| riprel
)
11713 print_displacement (scratchbuf
, disp
);
11715 print_operand_value (scratchbuf
, 1, disp
);
11716 oappend (scratchbuf
);
11720 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11724 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11725 && (address_mode
!= mode_64bit
11726 || ((bytemode
!= v_bnd_mode
)
11727 && (bytemode
!= v_bndmk_mode
)
11728 && (bytemode
!= bnd_mode
)
11729 && (bytemode
!= bnd_swap_mode
))))
11730 used_prefixes
|= PREFIX_ADDR
;
11732 if (havedisp
|| (intel_syntax
&& riprel
))
11734 *obufp
++ = open_char
;
11735 if (intel_syntax
&& riprel
)
11738 oappend (!addr32flag
? "rip" : "eip");
11742 oappend (address_mode
== mode_64bit
&& !addr32flag
11743 ? names64
[rbase
] : names32
[rbase
]);
11746 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11747 print index to tell base + index from base. */
11751 || (havebase
&& base
!= ESP_REG_NUM
))
11753 if (!intel_syntax
|| havebase
)
11755 *obufp
++ = separator_char
;
11760 if (address_mode
== mode_64bit
|| vindex
< 16)
11761 oappend (address_mode
== mode_64bit
&& !addr32flag
11762 ? indexes64
[vindex
] : indexes32
[vindex
]);
11767 oappend (address_mode
== mode_64bit
&& !addr32flag
11768 ? index64
: index32
);
11770 *obufp
++ = scale_char
;
11772 sprintf (scratchbuf
, "%d", 1 << scale
);
11773 oappend (scratchbuf
);
11777 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11779 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11784 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11792 print_displacement (scratchbuf
, disp
);
11794 print_operand_value (scratchbuf
, 1, disp
);
11795 oappend (scratchbuf
);
11798 *obufp
++ = close_char
;
11803 /* Both XMM/YMM/ZMM registers must be distinct. */
11804 int modrm_reg
= modrm
.reg
;
11810 if (vindex
== modrm_reg
)
11811 oappend ("/(bad)");
11814 else if (intel_syntax
)
11816 if (modrm
.mod
!= 0 || base
== 5)
11818 if (!active_seg_prefix
)
11820 oappend (names_seg
[ds_reg
- es_reg
]);
11823 print_operand_value (scratchbuf
, 1, disp
);
11824 oappend (scratchbuf
);
11828 else if (bytemode
== v_bnd_mode
11829 || bytemode
== v_bndmk_mode
11830 || bytemode
== bnd_mode
11831 || bytemode
== bnd_swap_mode
11832 || bytemode
== vex_vsib_d_w_dq_mode
11833 || bytemode
== vex_vsib_q_w_dq_mode
)
11840 /* 16 bit address mode */
11841 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11848 if ((disp
& 0x8000) != 0)
11853 FETCH_DATA (the_info
, codep
+ 1);
11855 if ((disp
& 0x80) != 0)
11857 if (vex
.evex
&& shift
> 0)
11862 if ((disp
& 0x8000) != 0)
11868 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11870 print_displacement (scratchbuf
, disp
);
11871 oappend (scratchbuf
);
11874 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11876 *obufp
++ = open_char
;
11878 oappend (index16
[modrm
.rm
]);
11880 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
11882 if ((bfd_signed_vma
) disp
>= 0)
11887 else if (modrm
.mod
!= 1)
11894 print_displacement (scratchbuf
, disp
);
11895 oappend (scratchbuf
);
11898 *obufp
++ = close_char
;
11901 else if (intel_syntax
)
11903 if (!active_seg_prefix
)
11905 oappend (names_seg
[ds_reg
- es_reg
]);
11908 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
11909 oappend (scratchbuf
);
11914 evex_used
|= EVEX_b_used
;
11915 if (!vex
.no_broadcast
)
11917 if (bytemode
== xh_mode
)
11923 switch (vex
.length
)
11926 oappend ("{1to8}");
11929 oappend ("{1to16}");
11932 oappend ("{1to32}");
11940 || bytemode
== evex_half_bcst_xmmqdh_mode
11941 || bytemode
== evex_half_bcst_xmmq_mode
)
11943 switch (vex
.length
)
11946 oappend ("{1to2}");
11949 oappend ("{1to4}");
11952 oappend ("{1to8}");
11958 else if (bytemode
== x_mode
11959 || bytemode
== evex_half_bcst_xmmqh_mode
)
11961 switch (vex
.length
)
11964 oappend ("{1to4}");
11967 oappend ("{1to8}");
11970 oappend ("{1to16}");
11977 vex
.no_broadcast
= 1;
11979 if (vex
.no_broadcast
)
11985 OP_E (int bytemode
, int sizeflag
)
11987 /* Skip mod/rm byte. */
11991 if (modrm
.mod
== 3)
11993 if ((sizeflag
& SUFFIX_ALWAYS
)
11994 && (bytemode
== b_swap_mode
11995 || bytemode
== bnd_swap_mode
11996 || bytemode
== v_swap_mode
))
11999 print_register (modrm
.rm
, REX_B
, bytemode
, sizeflag
);
12002 OP_E_memory (bytemode
, sizeflag
);
12006 OP_G (int bytemode
, int sizeflag
)
12008 if (vex
.evex
&& !vex
.r
&& address_mode
== mode_64bit
)
12014 print_register (modrm
.reg
, REX_R
, bytemode
, sizeflag
);
12025 FETCH_DATA (the_info
, codep
+ 8);
12026 a
= *codep
++ & 0xff;
12027 a
|= (*codep
++ & 0xff) << 8;
12028 a
|= (*codep
++ & 0xff) << 16;
12029 a
|= (*codep
++ & 0xffu
) << 24;
12030 b
= *codep
++ & 0xff;
12031 b
|= (*codep
++ & 0xff) << 8;
12032 b
|= (*codep
++ & 0xff) << 16;
12033 b
|= (*codep
++ & 0xffu
) << 24;
12034 x
= a
+ ((bfd_vma
) b
<< 32);
12042 static bfd_signed_vma
12047 FETCH_DATA (the_info
, codep
+ 4);
12048 x
= *codep
++ & (bfd_vma
) 0xff;
12049 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12050 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12051 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12055 static bfd_signed_vma
12060 FETCH_DATA (the_info
, codep
+ 4);
12061 x
= *codep
++ & (bfd_vma
) 0xff;
12062 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12063 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12064 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12066 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12076 FETCH_DATA (the_info
, codep
+ 2);
12077 x
= *codep
++ & 0xff;
12078 x
|= (*codep
++ & 0xff) << 8;
12083 set_op (bfd_vma op
, int riprel
)
12085 op_index
[op_ad
] = op_ad
;
12086 if (address_mode
== mode_64bit
)
12088 op_address
[op_ad
] = op
;
12089 op_riprel
[op_ad
] = riprel
;
12093 /* Mask to get a 32-bit address. */
12094 op_address
[op_ad
] = op
& 0xffffffff;
12095 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12100 OP_REG (int code
, int sizeflag
)
12107 case es_reg
: case ss_reg
: case cs_reg
:
12108 case ds_reg
: case fs_reg
: case gs_reg
:
12109 oappend (names_seg
[code
- es_reg
]);
12121 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12122 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12123 s
= names16
[code
- ax_reg
+ add
];
12125 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12127 /* Fall through. */
12128 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12130 s
= names8rex
[code
- al_reg
+ add
];
12132 s
= names8
[code
- al_reg
];
12134 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12135 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12136 if (address_mode
== mode_64bit
12137 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12139 s
= names64
[code
- rAX_reg
+ add
];
12142 code
+= eAX_reg
- rAX_reg
;
12143 /* Fall through. */
12144 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12145 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12148 s
= names64
[code
- eAX_reg
+ add
];
12151 if (sizeflag
& DFLAG
)
12152 s
= names32
[code
- eAX_reg
+ add
];
12154 s
= names16
[code
- eAX_reg
+ add
];
12155 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12159 s
= INTERNAL_DISASSEMBLER_ERROR
;
12166 OP_IMREG (int code
, int sizeflag
)
12178 case al_reg
: case cl_reg
:
12179 s
= names8
[code
- al_reg
];
12188 /* Fall through. */
12189 case z_mode_ax_reg
:
12190 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12194 if (!(rex
& REX_W
))
12195 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12198 s
= INTERNAL_DISASSEMBLER_ERROR
;
12205 OP_I (int bytemode
, int sizeflag
)
12208 bfd_signed_vma mask
= -1;
12213 FETCH_DATA (the_info
, codep
+ 1);
12223 if (sizeflag
& DFLAG
)
12233 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12249 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12254 scratchbuf
[0] = '$';
12255 print_operand_value (scratchbuf
+ 1, 1, op
);
12256 oappend_maybe_intel (scratchbuf
);
12257 scratchbuf
[0] = '\0';
12261 OP_I64 (int bytemode
, int sizeflag
)
12263 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12265 OP_I (bytemode
, sizeflag
);
12271 scratchbuf
[0] = '$';
12272 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12273 oappend_maybe_intel (scratchbuf
);
12274 scratchbuf
[0] = '\0';
12278 OP_sI (int bytemode
, int sizeflag
)
12286 FETCH_DATA (the_info
, codep
+ 1);
12288 if ((op
& 0x80) != 0)
12290 if (bytemode
== b_T_mode
)
12292 if (address_mode
!= mode_64bit
12293 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12295 /* The operand-size prefix is overridden by a REX prefix. */
12296 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12304 if (!(rex
& REX_W
))
12306 if (sizeflag
& DFLAG
)
12314 /* The operand-size prefix is overridden by a REX prefix. */
12315 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12321 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12325 scratchbuf
[0] = '$';
12326 print_operand_value (scratchbuf
+ 1, 1, op
);
12327 oappend_maybe_intel (scratchbuf
);
12331 OP_J (int bytemode
, int sizeflag
)
12335 bfd_vma segment
= 0;
12340 FETCH_DATA (the_info
, codep
+ 1);
12342 if ((disp
& 0x80) != 0)
12347 if ((sizeflag
& DFLAG
)
12348 || (address_mode
== mode_64bit
12349 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12350 || (rex
& REX_W
))))
12355 if ((disp
& 0x8000) != 0)
12357 /* In 16bit mode, address is wrapped around at 64k within
12358 the same segment. Otherwise, a data16 prefix on a jump
12359 instruction means that the pc is masked to 16 bits after
12360 the displacement is added! */
12362 if ((prefixes
& PREFIX_DATA
) == 0)
12363 segment
= ((start_pc
+ (codep
- start_codep
))
12364 & ~((bfd_vma
) 0xffff));
12366 if (address_mode
!= mode_64bit
12367 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12368 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12371 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12374 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12376 print_operand_value (scratchbuf
, 1, disp
);
12377 oappend (scratchbuf
);
12381 OP_SEG (int bytemode
, int sizeflag
)
12383 if (bytemode
== w_mode
)
12384 oappend (names_seg
[modrm
.reg
]);
12386 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12390 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12394 if (sizeflag
& DFLAG
)
12404 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12406 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12408 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12409 oappend (scratchbuf
);
12413 OP_OFF (int bytemode
, int sizeflag
)
12417 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12418 intel_operand_size (bytemode
, sizeflag
);
12421 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12428 if (!active_seg_prefix
)
12430 oappend (names_seg
[ds_reg
- es_reg
]);
12434 print_operand_value (scratchbuf
, 1, off
);
12435 oappend (scratchbuf
);
12439 OP_OFF64 (int bytemode
, int sizeflag
)
12443 if (address_mode
!= mode_64bit
12444 || (prefixes
& PREFIX_ADDR
))
12446 OP_OFF (bytemode
, sizeflag
);
12450 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12451 intel_operand_size (bytemode
, sizeflag
);
12458 if (!active_seg_prefix
)
12460 oappend (names_seg
[ds_reg
- es_reg
]);
12464 print_operand_value (scratchbuf
, 1, off
);
12465 oappend (scratchbuf
);
12469 ptr_reg (int code
, int sizeflag
)
12473 *obufp
++ = open_char
;
12474 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12475 if (address_mode
== mode_64bit
)
12477 if (!(sizeflag
& AFLAG
))
12478 s
= names32
[code
- eAX_reg
];
12480 s
= names64
[code
- eAX_reg
];
12482 else if (sizeflag
& AFLAG
)
12483 s
= names32
[code
- eAX_reg
];
12485 s
= names16
[code
- eAX_reg
];
12487 *obufp
++ = close_char
;
12492 OP_ESreg (int code
, int sizeflag
)
12498 case 0x6d: /* insw/insl */
12499 intel_operand_size (z_mode
, sizeflag
);
12501 case 0xa5: /* movsw/movsl/movsq */
12502 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12503 case 0xab: /* stosw/stosl */
12504 case 0xaf: /* scasw/scasl */
12505 intel_operand_size (v_mode
, sizeflag
);
12508 intel_operand_size (b_mode
, sizeflag
);
12511 oappend_maybe_intel ("%es:");
12512 ptr_reg (code
, sizeflag
);
12516 OP_DSreg (int code
, int sizeflag
)
12522 case 0x6f: /* outsw/outsl */
12523 intel_operand_size (z_mode
, sizeflag
);
12525 case 0xa5: /* movsw/movsl/movsq */
12526 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12527 case 0xad: /* lodsw/lodsl/lodsq */
12528 intel_operand_size (v_mode
, sizeflag
);
12531 intel_operand_size (b_mode
, sizeflag
);
12534 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12535 default segment register DS is printed. */
12536 if (!active_seg_prefix
)
12537 active_seg_prefix
= PREFIX_DS
;
12539 ptr_reg (code
, sizeflag
);
12543 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12551 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12553 all_prefixes
[last_lock_prefix
] = 0;
12554 used_prefixes
|= PREFIX_LOCK
;
12559 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12560 oappend_maybe_intel (scratchbuf
);
12564 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12573 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12575 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12576 oappend (scratchbuf
);
12580 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12582 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12583 oappend_maybe_intel (scratchbuf
);
12587 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12589 int reg
= modrm
.reg
;
12590 const char **names
;
12592 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12593 if (prefixes
& PREFIX_DATA
)
12602 oappend (names
[reg
]);
12606 print_vector_reg (unsigned int reg
, int bytemode
)
12608 const char **names
;
12610 if (bytemode
== xmmq_mode
12611 || bytemode
== evex_half_bcst_xmmqh_mode
12612 || bytemode
== evex_half_bcst_xmmq_mode
)
12614 switch (vex
.length
)
12627 else if (bytemode
== ymm_mode
)
12629 else if (bytemode
== tmm_mode
)
12639 && bytemode
!= xmm_mode
12640 && bytemode
!= scalar_mode
12641 && bytemode
!= xmmdw_mode
12642 && bytemode
!= xmmqd_mode
12643 && bytemode
!= evex_half_bcst_xmmqdh_mode
12644 && bytemode
!= w_swap_mode
12645 && bytemode
!= b_mode
12646 && bytemode
!= w_mode
12647 && bytemode
!= d_mode
12648 && bytemode
!= q_mode
)
12650 switch (vex
.length
)
12657 || bytemode
!= vex_vsib_q_w_dq_mode
)
12664 || bytemode
!= vex_vsib_q_w_dq_mode
)
12675 oappend (names
[reg
]);
12679 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12681 unsigned int reg
= modrm
.reg
;
12692 if (bytemode
== tmm_mode
)
12694 else if (bytemode
== scalar_mode
)
12695 vex
.no_broadcast
= 1;
12697 print_vector_reg (reg
, bytemode
);
12701 OP_EM (int bytemode
, int sizeflag
)
12704 const char **names
;
12706 if (modrm
.mod
!= 3)
12709 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12711 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12712 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12714 OP_E (bytemode
, sizeflag
);
12718 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12721 /* Skip mod/rm byte. */
12724 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12726 if (prefixes
& PREFIX_DATA
)
12735 oappend (names
[reg
]);
12738 /* cvt* are the only instructions in sse2 which have
12739 both SSE and MMX operands and also have 0x66 prefix
12740 in their opcode. 0x66 was originally used to differentiate
12741 between SSE and MMX instruction(operands). So we have to handle the
12742 cvt* separately using OP_EMC and OP_MXC */
12744 OP_EMC (int bytemode
, int sizeflag
)
12746 if (modrm
.mod
!= 3)
12748 if (intel_syntax
&& bytemode
== v_mode
)
12750 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12751 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12753 OP_E (bytemode
, sizeflag
);
12757 /* Skip mod/rm byte. */
12760 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12761 oappend (names_mm
[modrm
.rm
]);
12765 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12767 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12768 oappend (names_mm
[modrm
.reg
]);
12772 OP_EX (int bytemode
, int sizeflag
)
12776 /* Skip mod/rm byte. */
12780 if (bytemode
== dq_mode
)
12781 bytemode
= vex
.w
? q_mode
: d_mode
;
12783 if (modrm
.mod
!= 3)
12785 OP_E_memory (bytemode
, sizeflag
);
12800 if ((sizeflag
& SUFFIX_ALWAYS
)
12801 && (bytemode
== x_swap_mode
12802 || bytemode
== w_swap_mode
12803 || bytemode
== d_swap_mode
12804 || bytemode
== q_swap_mode
))
12807 if (bytemode
== tmm_mode
)
12810 print_vector_reg (reg
, bytemode
);
12814 OP_MS (int bytemode
, int sizeflag
)
12816 if (modrm
.mod
== 3)
12817 OP_EM (bytemode
, sizeflag
);
12823 OP_XS (int bytemode
, int sizeflag
)
12825 if (modrm
.mod
== 3)
12826 OP_EX (bytemode
, sizeflag
);
12832 OP_M (int bytemode
, int sizeflag
)
12834 if (modrm
.mod
== 3)
12835 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12838 OP_E (bytemode
, sizeflag
);
12842 OP_0f07 (int bytemode
, int sizeflag
)
12844 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
12847 OP_E (bytemode
, sizeflag
);
12850 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12851 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12854 NOP_Fixup1 (int bytemode
, int sizeflag
)
12856 if ((prefixes
& PREFIX_DATA
) != 0
12859 && address_mode
== mode_64bit
))
12860 OP_REG (bytemode
, sizeflag
);
12862 strcpy (obuf
, "nop");
12866 NOP_Fixup2 (int bytemode
, int sizeflag
)
12868 if ((prefixes
& PREFIX_DATA
) != 0
12871 && address_mode
== mode_64bit
))
12872 OP_IMREG (bytemode
, sizeflag
);
12875 static const char *const Suffix3DNow
[] = {
12876 /* 00 */ NULL
, NULL
, NULL
, NULL
,
12877 /* 04 */ NULL
, NULL
, NULL
, NULL
,
12878 /* 08 */ NULL
, NULL
, NULL
, NULL
,
12879 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
12880 /* 10 */ NULL
, NULL
, NULL
, NULL
,
12881 /* 14 */ NULL
, NULL
, NULL
, NULL
,
12882 /* 18 */ NULL
, NULL
, NULL
, NULL
,
12883 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
12884 /* 20 */ NULL
, NULL
, NULL
, NULL
,
12885 /* 24 */ NULL
, NULL
, NULL
, NULL
,
12886 /* 28 */ NULL
, NULL
, NULL
, NULL
,
12887 /* 2C */ NULL
, NULL
, NULL
, NULL
,
12888 /* 30 */ NULL
, NULL
, NULL
, NULL
,
12889 /* 34 */ NULL
, NULL
, NULL
, NULL
,
12890 /* 38 */ NULL
, NULL
, NULL
, NULL
,
12891 /* 3C */ NULL
, NULL
, NULL
, NULL
,
12892 /* 40 */ NULL
, NULL
, NULL
, NULL
,
12893 /* 44 */ NULL
, NULL
, NULL
, NULL
,
12894 /* 48 */ NULL
, NULL
, NULL
, NULL
,
12895 /* 4C */ NULL
, NULL
, NULL
, NULL
,
12896 /* 50 */ NULL
, NULL
, NULL
, NULL
,
12897 /* 54 */ NULL
, NULL
, NULL
, NULL
,
12898 /* 58 */ NULL
, NULL
, NULL
, NULL
,
12899 /* 5C */ NULL
, NULL
, NULL
, NULL
,
12900 /* 60 */ NULL
, NULL
, NULL
, NULL
,
12901 /* 64 */ NULL
, NULL
, NULL
, NULL
,
12902 /* 68 */ NULL
, NULL
, NULL
, NULL
,
12903 /* 6C */ NULL
, NULL
, NULL
, NULL
,
12904 /* 70 */ NULL
, NULL
, NULL
, NULL
,
12905 /* 74 */ NULL
, NULL
, NULL
, NULL
,
12906 /* 78 */ NULL
, NULL
, NULL
, NULL
,
12907 /* 7C */ NULL
, NULL
, NULL
, NULL
,
12908 /* 80 */ NULL
, NULL
, NULL
, NULL
,
12909 /* 84 */ NULL
, NULL
, NULL
, NULL
,
12910 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
12911 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
12912 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
12913 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
12914 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
12915 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
12916 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
12917 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
12918 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
12919 /* AC */ NULL
, NULL
, "pfacc", NULL
,
12920 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
12921 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
12922 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
12923 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
12924 /* C0 */ NULL
, NULL
, NULL
, NULL
,
12925 /* C4 */ NULL
, NULL
, NULL
, NULL
,
12926 /* C8 */ NULL
, NULL
, NULL
, NULL
,
12927 /* CC */ NULL
, NULL
, NULL
, NULL
,
12928 /* D0 */ NULL
, NULL
, NULL
, NULL
,
12929 /* D4 */ NULL
, NULL
, NULL
, NULL
,
12930 /* D8 */ NULL
, NULL
, NULL
, NULL
,
12931 /* DC */ NULL
, NULL
, NULL
, NULL
,
12932 /* E0 */ NULL
, NULL
, NULL
, NULL
,
12933 /* E4 */ NULL
, NULL
, NULL
, NULL
,
12934 /* E8 */ NULL
, NULL
, NULL
, NULL
,
12935 /* EC */ NULL
, NULL
, NULL
, NULL
,
12936 /* F0 */ NULL
, NULL
, NULL
, NULL
,
12937 /* F4 */ NULL
, NULL
, NULL
, NULL
,
12938 /* F8 */ NULL
, NULL
, NULL
, NULL
,
12939 /* FC */ NULL
, NULL
, NULL
, NULL
,
12943 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12945 const char *mnemonic
;
12947 FETCH_DATA (the_info
, codep
+ 1);
12948 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12949 place where an 8-bit immediate would normally go. ie. the last
12950 byte of the instruction. */
12951 obufp
= mnemonicendp
;
12952 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
12954 oappend (mnemonic
);
12957 /* Since a variable sized modrm/sib chunk is between the start
12958 of the opcode (0x0f0f) and the opcode suffix, we need to do
12959 all the modrm processing first, and don't know until now that
12960 we have a bad opcode. This necessitates some cleaning up. */
12961 op_out
[0][0] = '\0';
12962 op_out
[1][0] = '\0';
12965 mnemonicendp
= obufp
;
12968 static const struct op simd_cmp_op
[] =
12970 { STRING_COMMA_LEN ("eq") },
12971 { STRING_COMMA_LEN ("lt") },
12972 { STRING_COMMA_LEN ("le") },
12973 { STRING_COMMA_LEN ("unord") },
12974 { STRING_COMMA_LEN ("neq") },
12975 { STRING_COMMA_LEN ("nlt") },
12976 { STRING_COMMA_LEN ("nle") },
12977 { STRING_COMMA_LEN ("ord") }
12980 static const struct op vex_cmp_op
[] =
12982 { STRING_COMMA_LEN ("eq_uq") },
12983 { STRING_COMMA_LEN ("nge") },
12984 { STRING_COMMA_LEN ("ngt") },
12985 { STRING_COMMA_LEN ("false") },
12986 { STRING_COMMA_LEN ("neq_oq") },
12987 { STRING_COMMA_LEN ("ge") },
12988 { STRING_COMMA_LEN ("gt") },
12989 { STRING_COMMA_LEN ("true") },
12990 { STRING_COMMA_LEN ("eq_os") },
12991 { STRING_COMMA_LEN ("lt_oq") },
12992 { STRING_COMMA_LEN ("le_oq") },
12993 { STRING_COMMA_LEN ("unord_s") },
12994 { STRING_COMMA_LEN ("neq_us") },
12995 { STRING_COMMA_LEN ("nlt_uq") },
12996 { STRING_COMMA_LEN ("nle_uq") },
12997 { STRING_COMMA_LEN ("ord_s") },
12998 { STRING_COMMA_LEN ("eq_us") },
12999 { STRING_COMMA_LEN ("nge_uq") },
13000 { STRING_COMMA_LEN ("ngt_uq") },
13001 { STRING_COMMA_LEN ("false_os") },
13002 { STRING_COMMA_LEN ("neq_os") },
13003 { STRING_COMMA_LEN ("ge_oq") },
13004 { STRING_COMMA_LEN ("gt_oq") },
13005 { STRING_COMMA_LEN ("true_us") },
13009 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13011 unsigned int cmp_type
;
13013 FETCH_DATA (the_info
, codep
+ 1);
13014 cmp_type
= *codep
++ & 0xff;
13015 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13018 char *p
= mnemonicendp
- 2;
13022 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13023 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13026 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13029 char *p
= mnemonicendp
- 2;
13033 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13034 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13035 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13039 /* We have a reserved extension byte. Output it directly. */
13040 scratchbuf
[0] = '$';
13041 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13042 oappend_maybe_intel (scratchbuf
);
13043 scratchbuf
[0] = '\0';
13048 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13050 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13053 strcpy (op_out
[0], names32
[0]);
13054 strcpy (op_out
[1], names32
[1]);
13055 if (bytemode
== eBX_reg
)
13056 strcpy (op_out
[2], names32
[3]);
13057 two_source_ops
= 1;
13059 /* Skip mod/rm byte. */
13065 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13066 int sizeflag ATTRIBUTE_UNUSED
)
13068 /* monitor %{e,r,}ax,%ecx,%edx" */
13071 const char **names
= (address_mode
== mode_64bit
13072 ? names64
: names32
);
13074 if (prefixes
& PREFIX_ADDR
)
13076 /* Remove "addr16/addr32". */
13077 all_prefixes
[last_addr_prefix
] = 0;
13078 names
= (address_mode
!= mode_32bit
13079 ? names32
: names16
);
13080 used_prefixes
|= PREFIX_ADDR
;
13082 else if (address_mode
== mode_16bit
)
13084 strcpy (op_out
[0], names
[0]);
13085 strcpy (op_out
[1], names32
[1]);
13086 strcpy (op_out
[2], names32
[2]);
13087 two_source_ops
= 1;
13089 /* Skip mod/rm byte. */
13097 /* Throw away prefixes and 1st. opcode byte. */
13098 codep
= insn_codep
+ 1;
13103 REP_Fixup (int bytemode
, int sizeflag
)
13105 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13107 if (prefixes
& PREFIX_REPZ
)
13108 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13115 OP_IMREG (bytemode
, sizeflag
);
13118 OP_ESreg (bytemode
, sizeflag
);
13121 OP_DSreg (bytemode
, sizeflag
);
13130 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13132 if ( isa64
!= amd64
)
13137 mnemonicendp
= obufp
;
13141 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13145 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13147 if (prefixes
& PREFIX_REPNZ
)
13148 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13151 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13155 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13156 int sizeflag ATTRIBUTE_UNUSED
)
13159 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13160 we've seen a PREFIX_DS. */
13161 if ((prefixes
& PREFIX_DS
) != 0
13162 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13164 /* NOTRACK prefix is only valid on indirect branch instructions.
13165 NB: DATA prefix is unsupported for Intel64. */
13166 active_seg_prefix
= 0;
13167 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13171 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13172 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13176 HLE_Fixup1 (int bytemode
, int sizeflag
)
13179 && (prefixes
& PREFIX_LOCK
) != 0)
13181 if (prefixes
& PREFIX_REPZ
)
13182 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13183 if (prefixes
& PREFIX_REPNZ
)
13184 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13187 OP_E (bytemode
, sizeflag
);
13190 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13191 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13195 HLE_Fixup2 (int bytemode
, int sizeflag
)
13197 if (modrm
.mod
!= 3)
13199 if (prefixes
& PREFIX_REPZ
)
13200 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13201 if (prefixes
& PREFIX_REPNZ
)
13202 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13205 OP_E (bytemode
, sizeflag
);
13208 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13209 "xrelease" for memory operand. No check for LOCK prefix. */
13212 HLE_Fixup3 (int bytemode
, int sizeflag
)
13215 && last_repz_prefix
> last_repnz_prefix
13216 && (prefixes
& PREFIX_REPZ
) != 0)
13217 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13219 OP_E (bytemode
, sizeflag
);
13223 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13228 /* Change cmpxchg8b to cmpxchg16b. */
13229 char *p
= mnemonicendp
- 2;
13230 mnemonicendp
= stpcpy (p
, "16b");
13233 else if ((prefixes
& PREFIX_LOCK
) != 0)
13235 if (prefixes
& PREFIX_REPZ
)
13236 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13237 if (prefixes
& PREFIX_REPNZ
)
13238 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13241 OP_M (bytemode
, sizeflag
);
13245 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13247 const char **names
;
13251 switch (vex
.length
)
13265 oappend (names
[reg
]);
13269 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13271 /* Add proper suffix to "fxsave" and "fxrstor". */
13275 char *p
= mnemonicendp
;
13281 OP_M (bytemode
, sizeflag
);
13284 /* Display the destination register operand for instructions with
13288 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13290 int reg
, modrm_reg
, sib_index
= -1;
13291 const char **names
;
13296 reg
= vex
.register_specifier
;
13297 vex
.register_specifier
= 0;
13298 if (address_mode
!= mode_64bit
)
13300 if (vex
.evex
&& !vex
.v
)
13308 else if (vex
.evex
&& !vex
.v
)
13314 oappend (names_xmm
[reg
]);
13317 case vex_vsib_d_w_dq_mode
:
13318 case vex_vsib_q_w_dq_mode
:
13319 /* This must be the 3rd operand. */
13320 if (obufp
!= op_out
[2])
13322 if (vex
.length
== 128
13323 || (bytemode
!= vex_vsib_d_w_dq_mode
13325 oappend (names_xmm
[reg
]);
13327 oappend (names_ymm
[reg
]);
13329 /* All 3 XMM/YMM registers must be distinct. */
13330 modrm_reg
= modrm
.reg
;
13336 sib_index
= sib
.index
;
13341 if (reg
== modrm_reg
|| reg
== sib_index
)
13342 strcpy (obufp
, "/(bad)");
13343 if (modrm_reg
== sib_index
|| modrm_reg
== reg
)
13344 strcat (op_out
[0], "/(bad)");
13345 if (sib_index
== modrm_reg
|| sib_index
== reg
)
13346 strcat (op_out
[1], "/(bad)");
13351 /* All 3 TMM registers must be distinct. */
13356 /* This must be the 3rd operand. */
13357 if (obufp
!= op_out
[2])
13359 oappend (names_tmm
[reg
]);
13360 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13361 strcpy (obufp
, "/(bad)");
13364 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13367 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13368 strcat (op_out
[0], "/(bad)");
13370 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13371 strcat (op_out
[1], "/(bad)");
13377 switch (vex
.length
)
13398 names
= names_mask
;
13418 names
= names_mask
;
13421 /* See PR binutils/20893 for a reproducer. */
13433 oappend (names
[reg
]);
13437 OP_VexR (int bytemode
, int sizeflag
)
13439 if (modrm
.mod
== 3)
13440 OP_VEX (bytemode
, sizeflag
);
13444 OP_VexW (int bytemode
, int sizeflag
)
13446 OP_VEX (bytemode
, sizeflag
);
13450 /* Swap 2nd and 3rd operands. */
13451 strcpy (scratchbuf
, op_out
[2]);
13452 strcpy (op_out
[2], op_out
[1]);
13453 strcpy (op_out
[1], scratchbuf
);
13458 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13461 const char **names
= names_xmm
;
13463 FETCH_DATA (the_info
, codep
+ 1);
13466 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13470 if (address_mode
!= mode_64bit
)
13473 if (bytemode
== x_mode
&& vex
.length
== 256)
13476 oappend (names
[reg
]);
13480 /* Swap 3rd and 4th operands. */
13481 strcpy (scratchbuf
, op_out
[3]);
13482 strcpy (op_out
[3], op_out
[2]);
13483 strcpy (op_out
[2], scratchbuf
);
13488 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13489 int sizeflag ATTRIBUTE_UNUSED
)
13491 scratchbuf
[0] = '$';
13492 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13493 oappend_maybe_intel (scratchbuf
);
13497 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13498 int sizeflag ATTRIBUTE_UNUSED
)
13500 unsigned int cmp_type
;
13505 FETCH_DATA (the_info
, codep
+ 1);
13506 cmp_type
= *codep
++ & 0xff;
13507 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13508 If it's the case, print suffix, otherwise - print the immediate. */
13509 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13514 char *p
= mnemonicendp
- 2;
13516 /* vpcmp* can have both one- and two-lettered suffix. */
13530 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13531 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13535 /* We have a reserved extension byte. Output it directly. */
13536 scratchbuf
[0] = '$';
13537 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13538 oappend_maybe_intel (scratchbuf
);
13539 scratchbuf
[0] = '\0';
13543 static const struct op xop_cmp_op
[] =
13545 { STRING_COMMA_LEN ("lt") },
13546 { STRING_COMMA_LEN ("le") },
13547 { STRING_COMMA_LEN ("gt") },
13548 { STRING_COMMA_LEN ("ge") },
13549 { STRING_COMMA_LEN ("eq") },
13550 { STRING_COMMA_LEN ("neq") },
13551 { STRING_COMMA_LEN ("false") },
13552 { STRING_COMMA_LEN ("true") }
13556 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13557 int sizeflag ATTRIBUTE_UNUSED
)
13559 unsigned int cmp_type
;
13561 FETCH_DATA (the_info
, codep
+ 1);
13562 cmp_type
= *codep
++ & 0xff;
13563 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13566 char *p
= mnemonicendp
- 2;
13568 /* vpcom* can have both one- and two-lettered suffix. */
13582 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13583 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13587 /* We have a reserved extension byte. Output it directly. */
13588 scratchbuf
[0] = '$';
13589 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13590 oappend_maybe_intel (scratchbuf
);
13591 scratchbuf
[0] = '\0';
13595 static const struct op pclmul_op
[] =
13597 { STRING_COMMA_LEN ("lql") },
13598 { STRING_COMMA_LEN ("hql") },
13599 { STRING_COMMA_LEN ("lqh") },
13600 { STRING_COMMA_LEN ("hqh") }
13604 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13605 int sizeflag ATTRIBUTE_UNUSED
)
13607 unsigned int pclmul_type
;
13609 FETCH_DATA (the_info
, codep
+ 1);
13610 pclmul_type
= *codep
++ & 0xff;
13611 switch (pclmul_type
)
13622 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13625 char *p
= mnemonicendp
- 3;
13630 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13631 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13635 /* We have a reserved extension byte. Output it directly. */
13636 scratchbuf
[0] = '$';
13637 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13638 oappend_maybe_intel (scratchbuf
);
13639 scratchbuf
[0] = '\0';
13644 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13646 /* Add proper suffix to "movsxd". */
13647 char *p
= mnemonicendp
;
13667 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13673 OP_E (bytemode
, sizeflag
);
13677 DistinctDest_Fixup (int bytemode
, int sizeflag
)
13679 unsigned int reg
= vex
.register_specifier
;
13680 unsigned int modrm_reg
= modrm
.reg
;
13681 unsigned int modrm_rm
= modrm
.rm
;
13683 /* Calc destination register number. */
13689 /* Calc src1 register number. */
13690 if (address_mode
!= mode_64bit
)
13692 else if (vex
.evex
&& !vex
.v
)
13695 /* Calc src2 register number. */
13696 if (modrm
.mod
== 3)
13704 /* Destination and source registers must be distinct, output bad if
13705 dest == src1 or dest == src2. */
13706 if (modrm_reg
== reg
13708 && modrm_reg
== modrm_rm
))
13713 OP_XMM (bytemode
, sizeflag
);
13717 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13719 if (modrm
.mod
!= 3 || !vex
.b
)
13724 case evex_rounding_64_mode
:
13725 if (address_mode
!= mode_64bit
|| !vex
.w
)
13727 /* Fall through. */
13728 case evex_rounding_mode
:
13729 evex_used
|= EVEX_b_used
;
13730 oappend (names_rounding
[vex
.ll
]);
13732 case evex_sae_mode
:
13733 evex_used
|= EVEX_b_used
;