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[thirdparty/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F71,
695 REG_0F72,
696 REG_0F73,
697 REG_0FA6,
698 REG_0FA7,
699 REG_0FAE,
700 REG_0FBA,
701 REG_0FC7,
702 REG_VEX_0F71,
703 REG_VEX_0F72,
704 REG_VEX_0F73,
705 REG_VEX_0FAE,
706 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
707 REG_VEX_0F38F3,
708
709 REG_0FXOP_09_01_L_0,
710 REG_0FXOP_09_02_L_0,
711 REG_0FXOP_09_12_M_1_L_0,
712 REG_0FXOP_0A_12_L_0,
713
714 REG_EVEX_0F71,
715 REG_EVEX_0F72,
716 REG_EVEX_0F73,
717 REG_EVEX_0F38C6,
718 REG_EVEX_0F38C7
719 };
720
721 enum
722 {
723 MOD_8D = 0,
724 MOD_C6_REG_7,
725 MOD_C7_REG_7,
726 MOD_FF_REG_3,
727 MOD_FF_REG_5,
728 MOD_0F01_REG_0,
729 MOD_0F01_REG_1,
730 MOD_0F01_REG_2,
731 MOD_0F01_REG_3,
732 MOD_0F01_REG_5,
733 MOD_0F01_REG_7,
734 MOD_0F12_PREFIX_0,
735 MOD_0F12_PREFIX_2,
736 MOD_0F13,
737 MOD_0F16_PREFIX_0,
738 MOD_0F16_PREFIX_2,
739 MOD_0F17,
740 MOD_0F18_REG_0,
741 MOD_0F18_REG_1,
742 MOD_0F18_REG_2,
743 MOD_0F18_REG_3,
744 MOD_0F18_REG_4,
745 MOD_0F18_REG_5,
746 MOD_0F18_REG_6,
747 MOD_0F18_REG_7,
748 MOD_0F1A_PREFIX_0,
749 MOD_0F1B_PREFIX_0,
750 MOD_0F1B_PREFIX_1,
751 MOD_0F1C_PREFIX_0,
752 MOD_0F1E_PREFIX_1,
753 MOD_0F2B_PREFIX_0,
754 MOD_0F2B_PREFIX_1,
755 MOD_0F2B_PREFIX_2,
756 MOD_0F2B_PREFIX_3,
757 MOD_0F50,
758 MOD_0F71_REG_2,
759 MOD_0F71_REG_4,
760 MOD_0F71_REG_6,
761 MOD_0F72_REG_2,
762 MOD_0F72_REG_4,
763 MOD_0F72_REG_6,
764 MOD_0F73_REG_2,
765 MOD_0F73_REG_3,
766 MOD_0F73_REG_6,
767 MOD_0F73_REG_7,
768 MOD_0FAE_REG_0,
769 MOD_0FAE_REG_1,
770 MOD_0FAE_REG_2,
771 MOD_0FAE_REG_3,
772 MOD_0FAE_REG_4,
773 MOD_0FAE_REG_5,
774 MOD_0FAE_REG_6,
775 MOD_0FAE_REG_7,
776 MOD_0FB2,
777 MOD_0FB4,
778 MOD_0FB5,
779 MOD_0FC3,
780 MOD_0FC7_REG_3,
781 MOD_0FC7_REG_4,
782 MOD_0FC7_REG_5,
783 MOD_0FC7_REG_6,
784 MOD_0FC7_REG_7,
785 MOD_0FD7,
786 MOD_0FE7_PREFIX_2,
787 MOD_0FF0_PREFIX_3,
788 MOD_0F382A,
789 MOD_VEX_0F3849_X86_64_P_0_W_0,
790 MOD_VEX_0F3849_X86_64_P_2_W_0,
791 MOD_VEX_0F3849_X86_64_P_3_W_0,
792 MOD_VEX_0F384B_X86_64_P_1_W_0,
793 MOD_VEX_0F384B_X86_64_P_2_W_0,
794 MOD_VEX_0F384B_X86_64_P_3_W_0,
795 MOD_VEX_0F385C_X86_64_P_1_W_0,
796 MOD_VEX_0F385E_X86_64_P_0_W_0,
797 MOD_VEX_0F385E_X86_64_P_1_W_0,
798 MOD_VEX_0F385E_X86_64_P_2_W_0,
799 MOD_VEX_0F385E_X86_64_P_3_W_0,
800 MOD_0F38F5,
801 MOD_0F38F6_PREFIX_0,
802 MOD_0F38F8_PREFIX_1,
803 MOD_0F38F8_PREFIX_2,
804 MOD_0F38F8_PREFIX_3,
805 MOD_0F38F9,
806 MOD_62_32BIT,
807 MOD_C4_32BIT,
808 MOD_C5_32BIT,
809 MOD_VEX_0F12_PREFIX_0,
810 MOD_VEX_0F12_PREFIX_2,
811 MOD_VEX_0F13,
812 MOD_VEX_0F16_PREFIX_0,
813 MOD_VEX_0F16_PREFIX_2,
814 MOD_VEX_0F17,
815 MOD_VEX_0F2B,
816 MOD_VEX_W_0_0F41_P_0_LEN_1,
817 MOD_VEX_W_1_0F41_P_0_LEN_1,
818 MOD_VEX_W_0_0F41_P_2_LEN_1,
819 MOD_VEX_W_1_0F41_P_2_LEN_1,
820 MOD_VEX_W_0_0F42_P_0_LEN_1,
821 MOD_VEX_W_1_0F42_P_0_LEN_1,
822 MOD_VEX_W_0_0F42_P_2_LEN_1,
823 MOD_VEX_W_1_0F42_P_2_LEN_1,
824 MOD_VEX_W_0_0F44_P_0_LEN_1,
825 MOD_VEX_W_1_0F44_P_0_LEN_1,
826 MOD_VEX_W_0_0F44_P_2_LEN_1,
827 MOD_VEX_W_1_0F44_P_2_LEN_1,
828 MOD_VEX_W_0_0F45_P_0_LEN_1,
829 MOD_VEX_W_1_0F45_P_0_LEN_1,
830 MOD_VEX_W_0_0F45_P_2_LEN_1,
831 MOD_VEX_W_1_0F45_P_2_LEN_1,
832 MOD_VEX_W_0_0F46_P_0_LEN_1,
833 MOD_VEX_W_1_0F46_P_0_LEN_1,
834 MOD_VEX_W_0_0F46_P_2_LEN_1,
835 MOD_VEX_W_1_0F46_P_2_LEN_1,
836 MOD_VEX_W_0_0F47_P_0_LEN_1,
837 MOD_VEX_W_1_0F47_P_0_LEN_1,
838 MOD_VEX_W_0_0F47_P_2_LEN_1,
839 MOD_VEX_W_1_0F47_P_2_LEN_1,
840 MOD_VEX_W_0_0F4A_P_0_LEN_1,
841 MOD_VEX_W_1_0F4A_P_0_LEN_1,
842 MOD_VEX_W_0_0F4A_P_2_LEN_1,
843 MOD_VEX_W_1_0F4A_P_2_LEN_1,
844 MOD_VEX_W_0_0F4B_P_0_LEN_1,
845 MOD_VEX_W_1_0F4B_P_0_LEN_1,
846 MOD_VEX_W_0_0F4B_P_2_LEN_1,
847 MOD_VEX_0F50,
848 MOD_VEX_0F71_REG_2,
849 MOD_VEX_0F71_REG_4,
850 MOD_VEX_0F71_REG_6,
851 MOD_VEX_0F72_REG_2,
852 MOD_VEX_0F72_REG_4,
853 MOD_VEX_0F72_REG_6,
854 MOD_VEX_0F73_REG_2,
855 MOD_VEX_0F73_REG_3,
856 MOD_VEX_0F73_REG_6,
857 MOD_VEX_0F73_REG_7,
858 MOD_VEX_W_0_0F91_P_0_LEN_0,
859 MOD_VEX_W_1_0F91_P_0_LEN_0,
860 MOD_VEX_W_0_0F91_P_2_LEN_0,
861 MOD_VEX_W_1_0F91_P_2_LEN_0,
862 MOD_VEX_W_0_0F92_P_0_LEN_0,
863 MOD_VEX_W_0_0F92_P_2_LEN_0,
864 MOD_VEX_0F92_P_3_LEN_0,
865 MOD_VEX_W_0_0F93_P_0_LEN_0,
866 MOD_VEX_W_0_0F93_P_2_LEN_0,
867 MOD_VEX_0F93_P_3_LEN_0,
868 MOD_VEX_W_0_0F98_P_0_LEN_0,
869 MOD_VEX_W_1_0F98_P_0_LEN_0,
870 MOD_VEX_W_0_0F98_P_2_LEN_0,
871 MOD_VEX_W_1_0F98_P_2_LEN_0,
872 MOD_VEX_W_0_0F99_P_0_LEN_0,
873 MOD_VEX_W_1_0F99_P_0_LEN_0,
874 MOD_VEX_W_0_0F99_P_2_LEN_0,
875 MOD_VEX_W_1_0F99_P_2_LEN_0,
876 MOD_VEX_0FAE_REG_2,
877 MOD_VEX_0FAE_REG_3,
878 MOD_VEX_0FD7,
879 MOD_VEX_0FE7,
880 MOD_VEX_0FF0_PREFIX_3,
881 MOD_VEX_0F381A,
882 MOD_VEX_0F382A,
883 MOD_VEX_0F382C,
884 MOD_VEX_0F382D,
885 MOD_VEX_0F382E,
886 MOD_VEX_0F382F,
887 MOD_VEX_0F385A,
888 MOD_VEX_0F388C,
889 MOD_VEX_0F388E,
890 MOD_VEX_0F3A30_L_0,
891 MOD_VEX_0F3A31_L_0,
892 MOD_VEX_0F3A32_L_0,
893 MOD_VEX_0F3A33_L_0,
894
895 MOD_VEX_0FXOP_09_12,
896
897 MOD_EVEX_0F12_PREFIX_0,
898 MOD_EVEX_0F12_PREFIX_2,
899 MOD_EVEX_0F13,
900 MOD_EVEX_0F16_PREFIX_0,
901 MOD_EVEX_0F16_PREFIX_2,
902 MOD_EVEX_0F17,
903 MOD_EVEX_0F2B,
904 MOD_EVEX_0F381A_W_0,
905 MOD_EVEX_0F381A_W_1,
906 MOD_EVEX_0F381B_W_0,
907 MOD_EVEX_0F381B_W_1,
908 MOD_EVEX_0F3828_P_1,
909 MOD_EVEX_0F382A_P_1_W_1,
910 MOD_EVEX_0F3838_P_1,
911 MOD_EVEX_0F383A_P_1_W_0,
912 MOD_EVEX_0F385A_W_0,
913 MOD_EVEX_0F385A_W_1,
914 MOD_EVEX_0F385B_W_0,
915 MOD_EVEX_0F385B_W_1,
916 MOD_EVEX_0F387A_W_0,
917 MOD_EVEX_0F387B_W_0,
918 MOD_EVEX_0F387C,
919 MOD_EVEX_0F38C6_REG_1,
920 MOD_EVEX_0F38C6_REG_2,
921 MOD_EVEX_0F38C6_REG_5,
922 MOD_EVEX_0F38C6_REG_6,
923 MOD_EVEX_0F38C7_REG_1,
924 MOD_EVEX_0F38C7_REG_2,
925 MOD_EVEX_0F38C7_REG_5,
926 MOD_EVEX_0F38C7_REG_6
927 };
928
929 enum
930 {
931 RM_C6_REG_7 = 0,
932 RM_C7_REG_7,
933 RM_0F01_REG_0,
934 RM_0F01_REG_1,
935 RM_0F01_REG_2,
936 RM_0F01_REG_3,
937 RM_0F01_REG_5_MOD_3,
938 RM_0F01_REG_7_MOD_3,
939 RM_0F1E_P_1_MOD_3_REG_7,
940 RM_0FAE_REG_6_MOD_3_P_0,
941 RM_0FAE_REG_7_MOD_3,
942 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
943 };
944
945 enum
946 {
947 PREFIX_90 = 0,
948 PREFIX_0F01_REG_3_RM_1,
949 PREFIX_0F01_REG_5_MOD_0,
950 PREFIX_0F01_REG_5_MOD_3_RM_0,
951 PREFIX_0F01_REG_5_MOD_3_RM_1,
952 PREFIX_0F01_REG_5_MOD_3_RM_2,
953 PREFIX_0F01_REG_7_MOD_3_RM_2,
954 PREFIX_0F09,
955 PREFIX_0F10,
956 PREFIX_0F11,
957 PREFIX_0F12,
958 PREFIX_0F16,
959 PREFIX_0F1A,
960 PREFIX_0F1B,
961 PREFIX_0F1C,
962 PREFIX_0F1E,
963 PREFIX_0F2A,
964 PREFIX_0F2B,
965 PREFIX_0F2C,
966 PREFIX_0F2D,
967 PREFIX_0F2E,
968 PREFIX_0F2F,
969 PREFIX_0F51,
970 PREFIX_0F52,
971 PREFIX_0F53,
972 PREFIX_0F58,
973 PREFIX_0F59,
974 PREFIX_0F5A,
975 PREFIX_0F5B,
976 PREFIX_0F5C,
977 PREFIX_0F5D,
978 PREFIX_0F5E,
979 PREFIX_0F5F,
980 PREFIX_0F60,
981 PREFIX_0F61,
982 PREFIX_0F62,
983 PREFIX_0F6F,
984 PREFIX_0F70,
985 PREFIX_0F78,
986 PREFIX_0F79,
987 PREFIX_0F7C,
988 PREFIX_0F7D,
989 PREFIX_0F7E,
990 PREFIX_0F7F,
991 PREFIX_0FAE_REG_0_MOD_3,
992 PREFIX_0FAE_REG_1_MOD_3,
993 PREFIX_0FAE_REG_2_MOD_3,
994 PREFIX_0FAE_REG_3_MOD_3,
995 PREFIX_0FAE_REG_4_MOD_0,
996 PREFIX_0FAE_REG_4_MOD_3,
997 PREFIX_0FAE_REG_5_MOD_3,
998 PREFIX_0FAE_REG_6_MOD_0,
999 PREFIX_0FAE_REG_6_MOD_3,
1000 PREFIX_0FAE_REG_7_MOD_0,
1001 PREFIX_0FB8,
1002 PREFIX_0FBC,
1003 PREFIX_0FBD,
1004 PREFIX_0FC2,
1005 PREFIX_0FC7_REG_6_MOD_0,
1006 PREFIX_0FC7_REG_6_MOD_3,
1007 PREFIX_0FC7_REG_7_MOD_3,
1008 PREFIX_0FD0,
1009 PREFIX_0FD6,
1010 PREFIX_0FE6,
1011 PREFIX_0FE7,
1012 PREFIX_0FF0,
1013 PREFIX_0FF7,
1014 PREFIX_0F38F0,
1015 PREFIX_0F38F1,
1016 PREFIX_0F38F6,
1017 PREFIX_0F38F8,
1018 PREFIX_VEX_0F10,
1019 PREFIX_VEX_0F11,
1020 PREFIX_VEX_0F12,
1021 PREFIX_VEX_0F16,
1022 PREFIX_VEX_0F2A,
1023 PREFIX_VEX_0F2C,
1024 PREFIX_VEX_0F2D,
1025 PREFIX_VEX_0F2E,
1026 PREFIX_VEX_0F2F,
1027 PREFIX_VEX_0F41,
1028 PREFIX_VEX_0F42,
1029 PREFIX_VEX_0F44,
1030 PREFIX_VEX_0F45,
1031 PREFIX_VEX_0F46,
1032 PREFIX_VEX_0F47,
1033 PREFIX_VEX_0F4A,
1034 PREFIX_VEX_0F4B,
1035 PREFIX_VEX_0F51,
1036 PREFIX_VEX_0F52,
1037 PREFIX_VEX_0F53,
1038 PREFIX_VEX_0F58,
1039 PREFIX_VEX_0F59,
1040 PREFIX_VEX_0F5A,
1041 PREFIX_VEX_0F5B,
1042 PREFIX_VEX_0F5C,
1043 PREFIX_VEX_0F5D,
1044 PREFIX_VEX_0F5E,
1045 PREFIX_VEX_0F5F,
1046 PREFIX_VEX_0F6F,
1047 PREFIX_VEX_0F70,
1048 PREFIX_VEX_0F7C,
1049 PREFIX_VEX_0F7D,
1050 PREFIX_VEX_0F7E,
1051 PREFIX_VEX_0F7F,
1052 PREFIX_VEX_0F90,
1053 PREFIX_VEX_0F91,
1054 PREFIX_VEX_0F92,
1055 PREFIX_VEX_0F93,
1056 PREFIX_VEX_0F98,
1057 PREFIX_VEX_0F99,
1058 PREFIX_VEX_0FC2,
1059 PREFIX_VEX_0FD0,
1060 PREFIX_VEX_0FE6,
1061 PREFIX_VEX_0FF0,
1062 PREFIX_VEX_0F3849_X86_64,
1063 PREFIX_VEX_0F384B_X86_64,
1064 PREFIX_VEX_0F385C_X86_64,
1065 PREFIX_VEX_0F385E_X86_64,
1066 PREFIX_VEX_0F38F5,
1067 PREFIX_VEX_0F38F6,
1068 PREFIX_VEX_0F38F7,
1069 PREFIX_VEX_0F3AF0,
1070
1071 PREFIX_EVEX_0F10,
1072 PREFIX_EVEX_0F11,
1073 PREFIX_EVEX_0F12,
1074 PREFIX_EVEX_0F16,
1075 PREFIX_EVEX_0F2A,
1076 PREFIX_EVEX_0F51,
1077 PREFIX_EVEX_0F58,
1078 PREFIX_EVEX_0F59,
1079 PREFIX_EVEX_0F5A,
1080 PREFIX_EVEX_0F5B,
1081 PREFIX_EVEX_0F5C,
1082 PREFIX_EVEX_0F5D,
1083 PREFIX_EVEX_0F5E,
1084 PREFIX_EVEX_0F5F,
1085 PREFIX_EVEX_0F6F,
1086 PREFIX_EVEX_0F70,
1087 PREFIX_EVEX_0F78,
1088 PREFIX_EVEX_0F79,
1089 PREFIX_EVEX_0F7A,
1090 PREFIX_EVEX_0F7B,
1091 PREFIX_EVEX_0F7E,
1092 PREFIX_EVEX_0F7F,
1093 PREFIX_EVEX_0FC2,
1094 PREFIX_EVEX_0FE6,
1095 PREFIX_EVEX_0F3810,
1096 PREFIX_EVEX_0F3811,
1097 PREFIX_EVEX_0F3812,
1098 PREFIX_EVEX_0F3813,
1099 PREFIX_EVEX_0F3814,
1100 PREFIX_EVEX_0F3815,
1101 PREFIX_EVEX_0F3820,
1102 PREFIX_EVEX_0F3821,
1103 PREFIX_EVEX_0F3822,
1104 PREFIX_EVEX_0F3823,
1105 PREFIX_EVEX_0F3824,
1106 PREFIX_EVEX_0F3825,
1107 PREFIX_EVEX_0F3826,
1108 PREFIX_EVEX_0F3827,
1109 PREFIX_EVEX_0F3828,
1110 PREFIX_EVEX_0F3829,
1111 PREFIX_EVEX_0F382A,
1112 PREFIX_EVEX_0F3830,
1113 PREFIX_EVEX_0F3831,
1114 PREFIX_EVEX_0F3832,
1115 PREFIX_EVEX_0F3833,
1116 PREFIX_EVEX_0F3834,
1117 PREFIX_EVEX_0F3835,
1118 PREFIX_EVEX_0F3838,
1119 PREFIX_EVEX_0F3839,
1120 PREFIX_EVEX_0F383A,
1121 PREFIX_EVEX_0F3852,
1122 PREFIX_EVEX_0F3853,
1123 PREFIX_EVEX_0F3868,
1124 PREFIX_EVEX_0F3872,
1125 PREFIX_EVEX_0F389A,
1126 PREFIX_EVEX_0F389B,
1127 PREFIX_EVEX_0F38AA,
1128 PREFIX_EVEX_0F38AB,
1129 };
1130
1131 enum
1132 {
1133 X86_64_06 = 0,
1134 X86_64_07,
1135 X86_64_0E,
1136 X86_64_16,
1137 X86_64_17,
1138 X86_64_1E,
1139 X86_64_1F,
1140 X86_64_27,
1141 X86_64_2F,
1142 X86_64_37,
1143 X86_64_3F,
1144 X86_64_60,
1145 X86_64_61,
1146 X86_64_62,
1147 X86_64_63,
1148 X86_64_6D,
1149 X86_64_6F,
1150 X86_64_82,
1151 X86_64_9A,
1152 X86_64_C2,
1153 X86_64_C3,
1154 X86_64_C4,
1155 X86_64_C5,
1156 X86_64_CE,
1157 X86_64_D4,
1158 X86_64_D5,
1159 X86_64_E8,
1160 X86_64_E9,
1161 X86_64_EA,
1162 X86_64_0F01_REG_0,
1163 X86_64_0F01_REG_1,
1164 X86_64_0F01_REG_2,
1165 X86_64_0F01_REG_3,
1166 X86_64_0F24,
1167 X86_64_0F26,
1168 X86_64_VEX_0F3849,
1169 X86_64_VEX_0F384B,
1170 X86_64_VEX_0F385C,
1171 X86_64_VEX_0F385E
1172 };
1173
1174 enum
1175 {
1176 THREE_BYTE_0F38 = 0,
1177 THREE_BYTE_0F3A
1178 };
1179
1180 enum
1181 {
1182 XOP_08 = 0,
1183 XOP_09,
1184 XOP_0A
1185 };
1186
1187 enum
1188 {
1189 VEX_0F = 0,
1190 VEX_0F38,
1191 VEX_0F3A
1192 };
1193
1194 enum
1195 {
1196 EVEX_0F = 0,
1197 EVEX_0F38,
1198 EVEX_0F3A
1199 };
1200
1201 enum
1202 {
1203 VEX_LEN_0F12_P_0_M_0 = 0,
1204 VEX_LEN_0F12_P_0_M_1,
1205 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1206 VEX_LEN_0F13_M_0,
1207 VEX_LEN_0F16_P_0_M_0,
1208 VEX_LEN_0F16_P_0_M_1,
1209 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1210 VEX_LEN_0F17_M_0,
1211 VEX_LEN_0F41_P_0,
1212 VEX_LEN_0F41_P_2,
1213 VEX_LEN_0F42_P_0,
1214 VEX_LEN_0F42_P_2,
1215 VEX_LEN_0F44_P_0,
1216 VEX_LEN_0F44_P_2,
1217 VEX_LEN_0F45_P_0,
1218 VEX_LEN_0F45_P_2,
1219 VEX_LEN_0F46_P_0,
1220 VEX_LEN_0F46_P_2,
1221 VEX_LEN_0F47_P_0,
1222 VEX_LEN_0F47_P_2,
1223 VEX_LEN_0F4A_P_0,
1224 VEX_LEN_0F4A_P_2,
1225 VEX_LEN_0F4B_P_0,
1226 VEX_LEN_0F4B_P_2,
1227 VEX_LEN_0F6E,
1228 VEX_LEN_0F77,
1229 VEX_LEN_0F7E_P_1,
1230 VEX_LEN_0F7E_P_2,
1231 VEX_LEN_0F90_P_0,
1232 VEX_LEN_0F90_P_2,
1233 VEX_LEN_0F91_P_0,
1234 VEX_LEN_0F91_P_2,
1235 VEX_LEN_0F92_P_0,
1236 VEX_LEN_0F92_P_2,
1237 VEX_LEN_0F92_P_3,
1238 VEX_LEN_0F93_P_0,
1239 VEX_LEN_0F93_P_2,
1240 VEX_LEN_0F93_P_3,
1241 VEX_LEN_0F98_P_0,
1242 VEX_LEN_0F98_P_2,
1243 VEX_LEN_0F99_P_0,
1244 VEX_LEN_0F99_P_2,
1245 VEX_LEN_0FAE_R_2_M_0,
1246 VEX_LEN_0FAE_R_3_M_0,
1247 VEX_LEN_0FC4,
1248 VEX_LEN_0FC5,
1249 VEX_LEN_0FD6,
1250 VEX_LEN_0FF7,
1251 VEX_LEN_0F3816,
1252 VEX_LEN_0F3819,
1253 VEX_LEN_0F381A_M_0,
1254 VEX_LEN_0F3836,
1255 VEX_LEN_0F3841,
1256 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1257 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1258 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1259 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1260 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1261 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1262 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1263 VEX_LEN_0F385A_M_0,
1264 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1265 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1266 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1267 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1268 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1269 VEX_LEN_0F38DB,
1270 VEX_LEN_0F38F2,
1271 VEX_LEN_0F38F3_R_1,
1272 VEX_LEN_0F38F3_R_2,
1273 VEX_LEN_0F38F3_R_3,
1274 VEX_LEN_0F38F5_P_0,
1275 VEX_LEN_0F38F5_P_1,
1276 VEX_LEN_0F38F5_P_3,
1277 VEX_LEN_0F38F6_P_3,
1278 VEX_LEN_0F38F7_P_0,
1279 VEX_LEN_0F38F7_P_1,
1280 VEX_LEN_0F38F7_P_2,
1281 VEX_LEN_0F38F7_P_3,
1282 VEX_LEN_0F3A00,
1283 VEX_LEN_0F3A01,
1284 VEX_LEN_0F3A06,
1285 VEX_LEN_0F3A14,
1286 VEX_LEN_0F3A15,
1287 VEX_LEN_0F3A16,
1288 VEX_LEN_0F3A17,
1289 VEX_LEN_0F3A18,
1290 VEX_LEN_0F3A19,
1291 VEX_LEN_0F3A20,
1292 VEX_LEN_0F3A21,
1293 VEX_LEN_0F3A22,
1294 VEX_LEN_0F3A30,
1295 VEX_LEN_0F3A31,
1296 VEX_LEN_0F3A32,
1297 VEX_LEN_0F3A33,
1298 VEX_LEN_0F3A38,
1299 VEX_LEN_0F3A39,
1300 VEX_LEN_0F3A41,
1301 VEX_LEN_0F3A46,
1302 VEX_LEN_0F3A60,
1303 VEX_LEN_0F3A61,
1304 VEX_LEN_0F3A62,
1305 VEX_LEN_0F3A63,
1306 VEX_LEN_0F3ADF,
1307 VEX_LEN_0F3AF0_P_3,
1308 VEX_LEN_0FXOP_08_85,
1309 VEX_LEN_0FXOP_08_86,
1310 VEX_LEN_0FXOP_08_87,
1311 VEX_LEN_0FXOP_08_8E,
1312 VEX_LEN_0FXOP_08_8F,
1313 VEX_LEN_0FXOP_08_95,
1314 VEX_LEN_0FXOP_08_96,
1315 VEX_LEN_0FXOP_08_97,
1316 VEX_LEN_0FXOP_08_9E,
1317 VEX_LEN_0FXOP_08_9F,
1318 VEX_LEN_0FXOP_08_A3,
1319 VEX_LEN_0FXOP_08_A6,
1320 VEX_LEN_0FXOP_08_B6,
1321 VEX_LEN_0FXOP_08_C0,
1322 VEX_LEN_0FXOP_08_C1,
1323 VEX_LEN_0FXOP_08_C2,
1324 VEX_LEN_0FXOP_08_C3,
1325 VEX_LEN_0FXOP_08_CC,
1326 VEX_LEN_0FXOP_08_CD,
1327 VEX_LEN_0FXOP_08_CE,
1328 VEX_LEN_0FXOP_08_CF,
1329 VEX_LEN_0FXOP_08_EC,
1330 VEX_LEN_0FXOP_08_ED,
1331 VEX_LEN_0FXOP_08_EE,
1332 VEX_LEN_0FXOP_08_EF,
1333 VEX_LEN_0FXOP_09_01,
1334 VEX_LEN_0FXOP_09_02,
1335 VEX_LEN_0FXOP_09_12_M_1,
1336 VEX_LEN_0FXOP_09_82_W_0,
1337 VEX_LEN_0FXOP_09_83_W_0,
1338 VEX_LEN_0FXOP_09_90,
1339 VEX_LEN_0FXOP_09_91,
1340 VEX_LEN_0FXOP_09_92,
1341 VEX_LEN_0FXOP_09_93,
1342 VEX_LEN_0FXOP_09_94,
1343 VEX_LEN_0FXOP_09_95,
1344 VEX_LEN_0FXOP_09_96,
1345 VEX_LEN_0FXOP_09_97,
1346 VEX_LEN_0FXOP_09_98,
1347 VEX_LEN_0FXOP_09_99,
1348 VEX_LEN_0FXOP_09_9A,
1349 VEX_LEN_0FXOP_09_9B,
1350 VEX_LEN_0FXOP_09_C1,
1351 VEX_LEN_0FXOP_09_C2,
1352 VEX_LEN_0FXOP_09_C3,
1353 VEX_LEN_0FXOP_09_C6,
1354 VEX_LEN_0FXOP_09_C7,
1355 VEX_LEN_0FXOP_09_CB,
1356 VEX_LEN_0FXOP_09_D1,
1357 VEX_LEN_0FXOP_09_D2,
1358 VEX_LEN_0FXOP_09_D3,
1359 VEX_LEN_0FXOP_09_D6,
1360 VEX_LEN_0FXOP_09_D7,
1361 VEX_LEN_0FXOP_09_DB,
1362 VEX_LEN_0FXOP_09_E1,
1363 VEX_LEN_0FXOP_09_E2,
1364 VEX_LEN_0FXOP_09_E3,
1365 VEX_LEN_0FXOP_0A_12,
1366 };
1367
1368 enum
1369 {
1370 EVEX_LEN_0F6E = 0,
1371 EVEX_LEN_0F7E_P_1,
1372 EVEX_LEN_0F7E_P_2,
1373 EVEX_LEN_0FC4,
1374 EVEX_LEN_0FC5,
1375 EVEX_LEN_0FD6,
1376 EVEX_LEN_0F3816,
1377 EVEX_LEN_0F3819_W_0,
1378 EVEX_LEN_0F3819_W_1,
1379 EVEX_LEN_0F381A_W_0_M_0,
1380 EVEX_LEN_0F381A_W_1_M_0,
1381 EVEX_LEN_0F381B_W_0_M_0,
1382 EVEX_LEN_0F381B_W_1_M_0,
1383 EVEX_LEN_0F3836,
1384 EVEX_LEN_0F385A_W_0_M_0,
1385 EVEX_LEN_0F385A_W_1_M_0,
1386 EVEX_LEN_0F385B_W_0_M_0,
1387 EVEX_LEN_0F385B_W_1_M_0,
1388 EVEX_LEN_0F38C6_R_1_M_0,
1389 EVEX_LEN_0F38C6_R_2_M_0,
1390 EVEX_LEN_0F38C6_R_5_M_0,
1391 EVEX_LEN_0F38C6_R_6_M_0,
1392 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1393 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1394 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1395 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1396 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1397 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1398 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1399 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1400 EVEX_LEN_0F3A00_W_1,
1401 EVEX_LEN_0F3A01_W_1,
1402 EVEX_LEN_0F3A14,
1403 EVEX_LEN_0F3A15,
1404 EVEX_LEN_0F3A16,
1405 EVEX_LEN_0F3A17,
1406 EVEX_LEN_0F3A18_W_0,
1407 EVEX_LEN_0F3A18_W_1,
1408 EVEX_LEN_0F3A19_W_0,
1409 EVEX_LEN_0F3A19_W_1,
1410 EVEX_LEN_0F3A1A_W_0,
1411 EVEX_LEN_0F3A1A_W_1,
1412 EVEX_LEN_0F3A1B_W_0,
1413 EVEX_LEN_0F3A1B_W_1,
1414 EVEX_LEN_0F3A20,
1415 EVEX_LEN_0F3A21_W_0,
1416 EVEX_LEN_0F3A22,
1417 EVEX_LEN_0F3A23_W_0,
1418 EVEX_LEN_0F3A23_W_1,
1419 EVEX_LEN_0F3A38_W_0,
1420 EVEX_LEN_0F3A38_W_1,
1421 EVEX_LEN_0F3A39_W_0,
1422 EVEX_LEN_0F3A39_W_1,
1423 EVEX_LEN_0F3A3A_W_0,
1424 EVEX_LEN_0F3A3A_W_1,
1425 EVEX_LEN_0F3A3B_W_0,
1426 EVEX_LEN_0F3A3B_W_1,
1427 EVEX_LEN_0F3A43_W_0,
1428 EVEX_LEN_0F3A43_W_1
1429 };
1430
1431 enum
1432 {
1433 VEX_W_0F41_P_0_LEN_1 = 0,
1434 VEX_W_0F41_P_2_LEN_1,
1435 VEX_W_0F42_P_0_LEN_1,
1436 VEX_W_0F42_P_2_LEN_1,
1437 VEX_W_0F44_P_0_LEN_0,
1438 VEX_W_0F44_P_2_LEN_0,
1439 VEX_W_0F45_P_0_LEN_1,
1440 VEX_W_0F45_P_2_LEN_1,
1441 VEX_W_0F46_P_0_LEN_1,
1442 VEX_W_0F46_P_2_LEN_1,
1443 VEX_W_0F47_P_0_LEN_1,
1444 VEX_W_0F47_P_2_LEN_1,
1445 VEX_W_0F4A_P_0_LEN_1,
1446 VEX_W_0F4A_P_2_LEN_1,
1447 VEX_W_0F4B_P_0_LEN_1,
1448 VEX_W_0F4B_P_2_LEN_1,
1449 VEX_W_0F90_P_0_LEN_0,
1450 VEX_W_0F90_P_2_LEN_0,
1451 VEX_W_0F91_P_0_LEN_0,
1452 VEX_W_0F91_P_2_LEN_0,
1453 VEX_W_0F92_P_0_LEN_0,
1454 VEX_W_0F92_P_2_LEN_0,
1455 VEX_W_0F93_P_0_LEN_0,
1456 VEX_W_0F93_P_2_LEN_0,
1457 VEX_W_0F98_P_0_LEN_0,
1458 VEX_W_0F98_P_2_LEN_0,
1459 VEX_W_0F99_P_0_LEN_0,
1460 VEX_W_0F99_P_2_LEN_0,
1461 VEX_W_0F380C,
1462 VEX_W_0F380D,
1463 VEX_W_0F380E,
1464 VEX_W_0F380F,
1465 VEX_W_0F3813,
1466 VEX_W_0F3816_L_1,
1467 VEX_W_0F3818,
1468 VEX_W_0F3819_L_1,
1469 VEX_W_0F381A_M_0_L_1,
1470 VEX_W_0F382C_M_0,
1471 VEX_W_0F382D_M_0,
1472 VEX_W_0F382E_M_0,
1473 VEX_W_0F382F_M_0,
1474 VEX_W_0F3836,
1475 VEX_W_0F3846,
1476 VEX_W_0F3849_X86_64_P_0,
1477 VEX_W_0F3849_X86_64_P_2,
1478 VEX_W_0F3849_X86_64_P_3,
1479 VEX_W_0F384B_X86_64_P_1,
1480 VEX_W_0F384B_X86_64_P_2,
1481 VEX_W_0F384B_X86_64_P_3,
1482 VEX_W_0F3858,
1483 VEX_W_0F3859,
1484 VEX_W_0F385A_M_0_L_0,
1485 VEX_W_0F385C_X86_64_P_1,
1486 VEX_W_0F385E_X86_64_P_0,
1487 VEX_W_0F385E_X86_64_P_1,
1488 VEX_W_0F385E_X86_64_P_2,
1489 VEX_W_0F385E_X86_64_P_3,
1490 VEX_W_0F3878,
1491 VEX_W_0F3879,
1492 VEX_W_0F38CF,
1493 VEX_W_0F3A00_L_1,
1494 VEX_W_0F3A01_L_1,
1495 VEX_W_0F3A02,
1496 VEX_W_0F3A04,
1497 VEX_W_0F3A05,
1498 VEX_W_0F3A06_L_1,
1499 VEX_W_0F3A18_L_1,
1500 VEX_W_0F3A19_L_1,
1501 VEX_W_0F3A1D,
1502 VEX_W_0F3A38_L_1,
1503 VEX_W_0F3A39_L_1,
1504 VEX_W_0F3A46_L_1,
1505 VEX_W_0F3A4A,
1506 VEX_W_0F3A4B,
1507 VEX_W_0F3A4C,
1508 VEX_W_0F3ACE,
1509 VEX_W_0F3ACF,
1510
1511 VEX_W_0FXOP_08_85_L_0,
1512 VEX_W_0FXOP_08_86_L_0,
1513 VEX_W_0FXOP_08_87_L_0,
1514 VEX_W_0FXOP_08_8E_L_0,
1515 VEX_W_0FXOP_08_8F_L_0,
1516 VEX_W_0FXOP_08_95_L_0,
1517 VEX_W_0FXOP_08_96_L_0,
1518 VEX_W_0FXOP_08_97_L_0,
1519 VEX_W_0FXOP_08_9E_L_0,
1520 VEX_W_0FXOP_08_9F_L_0,
1521 VEX_W_0FXOP_08_A6_L_0,
1522 VEX_W_0FXOP_08_B6_L_0,
1523 VEX_W_0FXOP_08_C0_L_0,
1524 VEX_W_0FXOP_08_C1_L_0,
1525 VEX_W_0FXOP_08_C2_L_0,
1526 VEX_W_0FXOP_08_C3_L_0,
1527 VEX_W_0FXOP_08_CC_L_0,
1528 VEX_W_0FXOP_08_CD_L_0,
1529 VEX_W_0FXOP_08_CE_L_0,
1530 VEX_W_0FXOP_08_CF_L_0,
1531 VEX_W_0FXOP_08_EC_L_0,
1532 VEX_W_0FXOP_08_ED_L_0,
1533 VEX_W_0FXOP_08_EE_L_0,
1534 VEX_W_0FXOP_08_EF_L_0,
1535
1536 VEX_W_0FXOP_09_80,
1537 VEX_W_0FXOP_09_81,
1538 VEX_W_0FXOP_09_82,
1539 VEX_W_0FXOP_09_83,
1540 VEX_W_0FXOP_09_C1_L_0,
1541 VEX_W_0FXOP_09_C2_L_0,
1542 VEX_W_0FXOP_09_C3_L_0,
1543 VEX_W_0FXOP_09_C6_L_0,
1544 VEX_W_0FXOP_09_C7_L_0,
1545 VEX_W_0FXOP_09_CB_L_0,
1546 VEX_W_0FXOP_09_D1_L_0,
1547 VEX_W_0FXOP_09_D2_L_0,
1548 VEX_W_0FXOP_09_D3_L_0,
1549 VEX_W_0FXOP_09_D6_L_0,
1550 VEX_W_0FXOP_09_D7_L_0,
1551 VEX_W_0FXOP_09_DB_L_0,
1552 VEX_W_0FXOP_09_E1_L_0,
1553 VEX_W_0FXOP_09_E2_L_0,
1554 VEX_W_0FXOP_09_E3_L_0,
1555
1556 EVEX_W_0F10_P_1,
1557 EVEX_W_0F10_P_3,
1558 EVEX_W_0F11_P_1,
1559 EVEX_W_0F11_P_3,
1560 EVEX_W_0F12_P_0_M_1,
1561 EVEX_W_0F12_P_1,
1562 EVEX_W_0F12_P_3,
1563 EVEX_W_0F16_P_0_M_1,
1564 EVEX_W_0F16_P_1,
1565 EVEX_W_0F2A_P_3,
1566 EVEX_W_0F51_P_1,
1567 EVEX_W_0F51_P_3,
1568 EVEX_W_0F58_P_1,
1569 EVEX_W_0F58_P_3,
1570 EVEX_W_0F59_P_1,
1571 EVEX_W_0F59_P_3,
1572 EVEX_W_0F5A_P_0,
1573 EVEX_W_0F5A_P_1,
1574 EVEX_W_0F5A_P_2,
1575 EVEX_W_0F5A_P_3,
1576 EVEX_W_0F5B_P_0,
1577 EVEX_W_0F5B_P_1,
1578 EVEX_W_0F5B_P_2,
1579 EVEX_W_0F5C_P_1,
1580 EVEX_W_0F5C_P_3,
1581 EVEX_W_0F5D_P_1,
1582 EVEX_W_0F5D_P_3,
1583 EVEX_W_0F5E_P_1,
1584 EVEX_W_0F5E_P_3,
1585 EVEX_W_0F5F_P_1,
1586 EVEX_W_0F5F_P_3,
1587 EVEX_W_0F62,
1588 EVEX_W_0F66,
1589 EVEX_W_0F6A,
1590 EVEX_W_0F6B,
1591 EVEX_W_0F6C,
1592 EVEX_W_0F6D,
1593 EVEX_W_0F6F_P_1,
1594 EVEX_W_0F6F_P_2,
1595 EVEX_W_0F6F_P_3,
1596 EVEX_W_0F70_P_2,
1597 EVEX_W_0F72_R_2,
1598 EVEX_W_0F72_R_6,
1599 EVEX_W_0F73_R_2,
1600 EVEX_W_0F73_R_6,
1601 EVEX_W_0F76,
1602 EVEX_W_0F78_P_0,
1603 EVEX_W_0F78_P_2,
1604 EVEX_W_0F79_P_0,
1605 EVEX_W_0F79_P_2,
1606 EVEX_W_0F7A_P_1,
1607 EVEX_W_0F7A_P_2,
1608 EVEX_W_0F7A_P_3,
1609 EVEX_W_0F7B_P_2,
1610 EVEX_W_0F7B_P_3,
1611 EVEX_W_0F7E_P_1,
1612 EVEX_W_0F7F_P_1,
1613 EVEX_W_0F7F_P_2,
1614 EVEX_W_0F7F_P_3,
1615 EVEX_W_0FC2_P_1,
1616 EVEX_W_0FC2_P_3,
1617 EVEX_W_0FD2,
1618 EVEX_W_0FD3,
1619 EVEX_W_0FD4,
1620 EVEX_W_0FD6_L_0,
1621 EVEX_W_0FE6_P_1,
1622 EVEX_W_0FE6_P_2,
1623 EVEX_W_0FE6_P_3,
1624 EVEX_W_0FE7,
1625 EVEX_W_0FF2,
1626 EVEX_W_0FF3,
1627 EVEX_W_0FF4,
1628 EVEX_W_0FFA,
1629 EVEX_W_0FFB,
1630 EVEX_W_0FFE,
1631 EVEX_W_0F380D,
1632 EVEX_W_0F3810_P_1,
1633 EVEX_W_0F3810_P_2,
1634 EVEX_W_0F3811_P_1,
1635 EVEX_W_0F3811_P_2,
1636 EVEX_W_0F3812_P_1,
1637 EVEX_W_0F3812_P_2,
1638 EVEX_W_0F3813_P_1,
1639 EVEX_W_0F3813_P_2,
1640 EVEX_W_0F3814_P_1,
1641 EVEX_W_0F3815_P_1,
1642 EVEX_W_0F3819,
1643 EVEX_W_0F381A,
1644 EVEX_W_0F381B,
1645 EVEX_W_0F381E,
1646 EVEX_W_0F381F,
1647 EVEX_W_0F3820_P_1,
1648 EVEX_W_0F3821_P_1,
1649 EVEX_W_0F3822_P_1,
1650 EVEX_W_0F3823_P_1,
1651 EVEX_W_0F3824_P_1,
1652 EVEX_W_0F3825_P_1,
1653 EVEX_W_0F3825_P_2,
1654 EVEX_W_0F3828_P_2,
1655 EVEX_W_0F3829_P_2,
1656 EVEX_W_0F382A_P_1,
1657 EVEX_W_0F382A_P_2,
1658 EVEX_W_0F382B,
1659 EVEX_W_0F3830_P_1,
1660 EVEX_W_0F3831_P_1,
1661 EVEX_W_0F3832_P_1,
1662 EVEX_W_0F3833_P_1,
1663 EVEX_W_0F3834_P_1,
1664 EVEX_W_0F3835_P_1,
1665 EVEX_W_0F3835_P_2,
1666 EVEX_W_0F3837,
1667 EVEX_W_0F383A_P_1,
1668 EVEX_W_0F3852_P_1,
1669 EVEX_W_0F3859,
1670 EVEX_W_0F385A,
1671 EVEX_W_0F385B,
1672 EVEX_W_0F3870,
1673 EVEX_W_0F3872_P_1,
1674 EVEX_W_0F3872_P_2,
1675 EVEX_W_0F3872_P_3,
1676 EVEX_W_0F387A,
1677 EVEX_W_0F387B,
1678 EVEX_W_0F3883,
1679 EVEX_W_0F3891,
1680 EVEX_W_0F3893,
1681 EVEX_W_0F38A1,
1682 EVEX_W_0F38A3,
1683 EVEX_W_0F38C7_R_1_M_0,
1684 EVEX_W_0F38C7_R_2_M_0,
1685 EVEX_W_0F38C7_R_5_M_0,
1686 EVEX_W_0F38C7_R_6_M_0,
1687
1688 EVEX_W_0F3A00,
1689 EVEX_W_0F3A01,
1690 EVEX_W_0F3A05,
1691 EVEX_W_0F3A08,
1692 EVEX_W_0F3A09,
1693 EVEX_W_0F3A0A,
1694 EVEX_W_0F3A0B,
1695 EVEX_W_0F3A18,
1696 EVEX_W_0F3A19,
1697 EVEX_W_0F3A1A,
1698 EVEX_W_0F3A1B,
1699 EVEX_W_0F3A21,
1700 EVEX_W_0F3A23,
1701 EVEX_W_0F3A38,
1702 EVEX_W_0F3A39,
1703 EVEX_W_0F3A3A,
1704 EVEX_W_0F3A3B,
1705 EVEX_W_0F3A42,
1706 EVEX_W_0F3A43,
1707 EVEX_W_0F3A70,
1708 EVEX_W_0F3A72,
1709 };
1710
1711 typedef void (*op_rtn) (int bytemode, int sizeflag);
1712
1713 struct dis386 {
1714 const char *name;
1715 struct
1716 {
1717 op_rtn rtn;
1718 int bytemode;
1719 } op[MAX_OPERANDS];
1720 unsigned int prefix_requirement;
1721 };
1722
1723 /* Upper case letters in the instruction names here are macros.
1724 'A' => print 'b' if no register operands or suffix_always is true
1725 'B' => print 'b' if suffix_always is true
1726 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1727 size prefix
1728 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1729 suffix_always is true
1730 'E' => print 'e' if 32-bit form of jcxz
1731 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1732 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1733 'H' => print ",pt" or ",pn" branch hint
1734 'I' unused.
1735 'J' unused.
1736 'K' => print 'd' or 'q' if rex prefix is present.
1737 'L' unused.
1738 'M' => print 'r' if intel_mnemonic is false.
1739 'N' => print 'n' if instruction has no wait "prefix"
1740 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1741 'P' => behave as 'T' except with register operand outside of suffix_always
1742 mode
1743 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1744 is true
1745 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1746 'S' => print 'w', 'l' or 'q' if suffix_always is true
1747 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1748 prefix or if suffix_always is true.
1749 'U' unused.
1750 'V' unused.
1751 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1752 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1753 'Y' unused.
1754 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1755 '!' => change condition from true to false or from false to true.
1756 '%' => add 1 upper case letter to the macro.
1757 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1758 prefix or suffix_always is true (lcall/ljmp).
1759 '@' => in 64bit mode for Intel64 ISA or if instruction
1760 has no operand sizing prefix, print 'q' if suffix_always is true or
1761 nothing otherwise; behave as 'P' in all other cases
1762
1763 2 upper case letter macros:
1764 "XY" => print 'x' or 'y' if suffix_always is true or no register
1765 operands and no broadcast.
1766 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1767 register operands and no broadcast.
1768 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1769 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1770 being false, or no operand at all in 64bit mode, or if suffix_always
1771 is true.
1772 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1773 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1774 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1775 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1776 "BW" => print 'b' or 'w' depending on the VEX.W bit
1777 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1778 an operand size prefix, or suffix_always is true. print
1779 'q' if rex prefix is present.
1780
1781 Many of the above letters print nothing in Intel mode. See "putop"
1782 for the details.
1783
1784 Braces '{' and '}', and vertical bars '|', indicate alternative
1785 mnemonic strings for AT&T and Intel. */
1786
1787 static const struct dis386 dis386[] = {
1788 /* 00 */
1789 { "addB", { Ebh1, Gb }, 0 },
1790 { "addS", { Evh1, Gv }, 0 },
1791 { "addB", { Gb, EbS }, 0 },
1792 { "addS", { Gv, EvS }, 0 },
1793 { "addB", { AL, Ib }, 0 },
1794 { "addS", { eAX, Iv }, 0 },
1795 { X86_64_TABLE (X86_64_06) },
1796 { X86_64_TABLE (X86_64_07) },
1797 /* 08 */
1798 { "orB", { Ebh1, Gb }, 0 },
1799 { "orS", { Evh1, Gv }, 0 },
1800 { "orB", { Gb, EbS }, 0 },
1801 { "orS", { Gv, EvS }, 0 },
1802 { "orB", { AL, Ib }, 0 },
1803 { "orS", { eAX, Iv }, 0 },
1804 { X86_64_TABLE (X86_64_0E) },
1805 { Bad_Opcode }, /* 0x0f extended opcode escape */
1806 /* 10 */
1807 { "adcB", { Ebh1, Gb }, 0 },
1808 { "adcS", { Evh1, Gv }, 0 },
1809 { "adcB", { Gb, EbS }, 0 },
1810 { "adcS", { Gv, EvS }, 0 },
1811 { "adcB", { AL, Ib }, 0 },
1812 { "adcS", { eAX, Iv }, 0 },
1813 { X86_64_TABLE (X86_64_16) },
1814 { X86_64_TABLE (X86_64_17) },
1815 /* 18 */
1816 { "sbbB", { Ebh1, Gb }, 0 },
1817 { "sbbS", { Evh1, Gv }, 0 },
1818 { "sbbB", { Gb, EbS }, 0 },
1819 { "sbbS", { Gv, EvS }, 0 },
1820 { "sbbB", { AL, Ib }, 0 },
1821 { "sbbS", { eAX, Iv }, 0 },
1822 { X86_64_TABLE (X86_64_1E) },
1823 { X86_64_TABLE (X86_64_1F) },
1824 /* 20 */
1825 { "andB", { Ebh1, Gb }, 0 },
1826 { "andS", { Evh1, Gv }, 0 },
1827 { "andB", { Gb, EbS }, 0 },
1828 { "andS", { Gv, EvS }, 0 },
1829 { "andB", { AL, Ib }, 0 },
1830 { "andS", { eAX, Iv }, 0 },
1831 { Bad_Opcode }, /* SEG ES prefix */
1832 { X86_64_TABLE (X86_64_27) },
1833 /* 28 */
1834 { "subB", { Ebh1, Gb }, 0 },
1835 { "subS", { Evh1, Gv }, 0 },
1836 { "subB", { Gb, EbS }, 0 },
1837 { "subS", { Gv, EvS }, 0 },
1838 { "subB", { AL, Ib }, 0 },
1839 { "subS", { eAX, Iv }, 0 },
1840 { Bad_Opcode }, /* SEG CS prefix */
1841 { X86_64_TABLE (X86_64_2F) },
1842 /* 30 */
1843 { "xorB", { Ebh1, Gb }, 0 },
1844 { "xorS", { Evh1, Gv }, 0 },
1845 { "xorB", { Gb, EbS }, 0 },
1846 { "xorS", { Gv, EvS }, 0 },
1847 { "xorB", { AL, Ib }, 0 },
1848 { "xorS", { eAX, Iv }, 0 },
1849 { Bad_Opcode }, /* SEG SS prefix */
1850 { X86_64_TABLE (X86_64_37) },
1851 /* 38 */
1852 { "cmpB", { Eb, Gb }, 0 },
1853 { "cmpS", { Ev, Gv }, 0 },
1854 { "cmpB", { Gb, EbS }, 0 },
1855 { "cmpS", { Gv, EvS }, 0 },
1856 { "cmpB", { AL, Ib }, 0 },
1857 { "cmpS", { eAX, Iv }, 0 },
1858 { Bad_Opcode }, /* SEG DS prefix */
1859 { X86_64_TABLE (X86_64_3F) },
1860 /* 40 */
1861 { "inc{S|}", { RMeAX }, 0 },
1862 { "inc{S|}", { RMeCX }, 0 },
1863 { "inc{S|}", { RMeDX }, 0 },
1864 { "inc{S|}", { RMeBX }, 0 },
1865 { "inc{S|}", { RMeSP }, 0 },
1866 { "inc{S|}", { RMeBP }, 0 },
1867 { "inc{S|}", { RMeSI }, 0 },
1868 { "inc{S|}", { RMeDI }, 0 },
1869 /* 48 */
1870 { "dec{S|}", { RMeAX }, 0 },
1871 { "dec{S|}", { RMeCX }, 0 },
1872 { "dec{S|}", { RMeDX }, 0 },
1873 { "dec{S|}", { RMeBX }, 0 },
1874 { "dec{S|}", { RMeSP }, 0 },
1875 { "dec{S|}", { RMeBP }, 0 },
1876 { "dec{S|}", { RMeSI }, 0 },
1877 { "dec{S|}", { RMeDI }, 0 },
1878 /* 50 */
1879 { "push{!P|}", { RMrAX }, 0 },
1880 { "push{!P|}", { RMrCX }, 0 },
1881 { "push{!P|}", { RMrDX }, 0 },
1882 { "push{!P|}", { RMrBX }, 0 },
1883 { "push{!P|}", { RMrSP }, 0 },
1884 { "push{!P|}", { RMrBP }, 0 },
1885 { "push{!P|}", { RMrSI }, 0 },
1886 { "push{!P|}", { RMrDI }, 0 },
1887 /* 58 */
1888 { "pop{!P|}", { RMrAX }, 0 },
1889 { "pop{!P|}", { RMrCX }, 0 },
1890 { "pop{!P|}", { RMrDX }, 0 },
1891 { "pop{!P|}", { RMrBX }, 0 },
1892 { "pop{!P|}", { RMrSP }, 0 },
1893 { "pop{!P|}", { RMrBP }, 0 },
1894 { "pop{!P|}", { RMrSI }, 0 },
1895 { "pop{!P|}", { RMrDI }, 0 },
1896 /* 60 */
1897 { X86_64_TABLE (X86_64_60) },
1898 { X86_64_TABLE (X86_64_61) },
1899 { X86_64_TABLE (X86_64_62) },
1900 { X86_64_TABLE (X86_64_63) },
1901 { Bad_Opcode }, /* seg fs */
1902 { Bad_Opcode }, /* seg gs */
1903 { Bad_Opcode }, /* op size prefix */
1904 { Bad_Opcode }, /* adr size prefix */
1905 /* 68 */
1906 { "pushP", { sIv }, 0 },
1907 { "imulS", { Gv, Ev, Iv }, 0 },
1908 { "pushP", { sIbT }, 0 },
1909 { "imulS", { Gv, Ev, sIb }, 0 },
1910 { "ins{b|}", { Ybr, indirDX }, 0 },
1911 { X86_64_TABLE (X86_64_6D) },
1912 { "outs{b|}", { indirDXr, Xb }, 0 },
1913 { X86_64_TABLE (X86_64_6F) },
1914 /* 70 */
1915 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1916 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1917 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1918 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1919 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1920 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1921 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1922 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1923 /* 78 */
1924 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1925 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1926 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1927 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1928 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1929 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1930 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1931 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1932 /* 80 */
1933 { REG_TABLE (REG_80) },
1934 { REG_TABLE (REG_81) },
1935 { X86_64_TABLE (X86_64_82) },
1936 { REG_TABLE (REG_83) },
1937 { "testB", { Eb, Gb }, 0 },
1938 { "testS", { Ev, Gv }, 0 },
1939 { "xchgB", { Ebh2, Gb }, 0 },
1940 { "xchgS", { Evh2, Gv }, 0 },
1941 /* 88 */
1942 { "movB", { Ebh3, Gb }, 0 },
1943 { "movS", { Evh3, Gv }, 0 },
1944 { "movB", { Gb, EbS }, 0 },
1945 { "movS", { Gv, EvS }, 0 },
1946 { "movD", { Sv, Sw }, 0 },
1947 { MOD_TABLE (MOD_8D) },
1948 { "movD", { Sw, Sv }, 0 },
1949 { REG_TABLE (REG_8F) },
1950 /* 90 */
1951 { PREFIX_TABLE (PREFIX_90) },
1952 { "xchgS", { RMeCX, eAX }, 0 },
1953 { "xchgS", { RMeDX, eAX }, 0 },
1954 { "xchgS", { RMeBX, eAX }, 0 },
1955 { "xchgS", { RMeSP, eAX }, 0 },
1956 { "xchgS", { RMeBP, eAX }, 0 },
1957 { "xchgS", { RMeSI, eAX }, 0 },
1958 { "xchgS", { RMeDI, eAX }, 0 },
1959 /* 98 */
1960 { "cW{t|}R", { XX }, 0 },
1961 { "cR{t|}O", { XX }, 0 },
1962 { X86_64_TABLE (X86_64_9A) },
1963 { Bad_Opcode }, /* fwait */
1964 { "pushfP", { XX }, 0 },
1965 { "popfP", { XX }, 0 },
1966 { "sahf", { XX }, 0 },
1967 { "lahf", { XX }, 0 },
1968 /* a0 */
1969 { "mov%LB", { AL, Ob }, 0 },
1970 { "mov%LS", { eAX, Ov }, 0 },
1971 { "mov%LB", { Ob, AL }, 0 },
1972 { "mov%LS", { Ov, eAX }, 0 },
1973 { "movs{b|}", { Ybr, Xb }, 0 },
1974 { "movs{R|}", { Yvr, Xv }, 0 },
1975 { "cmps{b|}", { Xb, Yb }, 0 },
1976 { "cmps{R|}", { Xv, Yv }, 0 },
1977 /* a8 */
1978 { "testB", { AL, Ib }, 0 },
1979 { "testS", { eAX, Iv }, 0 },
1980 { "stosB", { Ybr, AL }, 0 },
1981 { "stosS", { Yvr, eAX }, 0 },
1982 { "lodsB", { ALr, Xb }, 0 },
1983 { "lodsS", { eAXr, Xv }, 0 },
1984 { "scasB", { AL, Yb }, 0 },
1985 { "scasS", { eAX, Yv }, 0 },
1986 /* b0 */
1987 { "movB", { RMAL, Ib }, 0 },
1988 { "movB", { RMCL, Ib }, 0 },
1989 { "movB", { RMDL, Ib }, 0 },
1990 { "movB", { RMBL, Ib }, 0 },
1991 { "movB", { RMAH, Ib }, 0 },
1992 { "movB", { RMCH, Ib }, 0 },
1993 { "movB", { RMDH, Ib }, 0 },
1994 { "movB", { RMBH, Ib }, 0 },
1995 /* b8 */
1996 { "mov%LV", { RMeAX, Iv64 }, 0 },
1997 { "mov%LV", { RMeCX, Iv64 }, 0 },
1998 { "mov%LV", { RMeDX, Iv64 }, 0 },
1999 { "mov%LV", { RMeBX, Iv64 }, 0 },
2000 { "mov%LV", { RMeSP, Iv64 }, 0 },
2001 { "mov%LV", { RMeBP, Iv64 }, 0 },
2002 { "mov%LV", { RMeSI, Iv64 }, 0 },
2003 { "mov%LV", { RMeDI, Iv64 }, 0 },
2004 /* c0 */
2005 { REG_TABLE (REG_C0) },
2006 { REG_TABLE (REG_C1) },
2007 { X86_64_TABLE (X86_64_C2) },
2008 { X86_64_TABLE (X86_64_C3) },
2009 { X86_64_TABLE (X86_64_C4) },
2010 { X86_64_TABLE (X86_64_C5) },
2011 { REG_TABLE (REG_C6) },
2012 { REG_TABLE (REG_C7) },
2013 /* c8 */
2014 { "enterP", { Iw, Ib }, 0 },
2015 { "leaveP", { XX }, 0 },
2016 { "{l|}ret{|f}%LP", { Iw }, 0 },
2017 { "{l|}ret{|f}%LP", { XX }, 0 },
2018 { "int3", { XX }, 0 },
2019 { "int", { Ib }, 0 },
2020 { X86_64_TABLE (X86_64_CE) },
2021 { "iret%LP", { XX }, 0 },
2022 /* d0 */
2023 { REG_TABLE (REG_D0) },
2024 { REG_TABLE (REG_D1) },
2025 { REG_TABLE (REG_D2) },
2026 { REG_TABLE (REG_D3) },
2027 { X86_64_TABLE (X86_64_D4) },
2028 { X86_64_TABLE (X86_64_D5) },
2029 { Bad_Opcode },
2030 { "xlat", { DSBX }, 0 },
2031 /* d8 */
2032 { FLOAT },
2033 { FLOAT },
2034 { FLOAT },
2035 { FLOAT },
2036 { FLOAT },
2037 { FLOAT },
2038 { FLOAT },
2039 { FLOAT },
2040 /* e0 */
2041 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2042 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2043 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2044 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2045 { "inB", { AL, Ib }, 0 },
2046 { "inG", { zAX, Ib }, 0 },
2047 { "outB", { Ib, AL }, 0 },
2048 { "outG", { Ib, zAX }, 0 },
2049 /* e8 */
2050 { X86_64_TABLE (X86_64_E8) },
2051 { X86_64_TABLE (X86_64_E9) },
2052 { X86_64_TABLE (X86_64_EA) },
2053 { "jmp", { Jb, BND }, 0 },
2054 { "inB", { AL, indirDX }, 0 },
2055 { "inG", { zAX, indirDX }, 0 },
2056 { "outB", { indirDX, AL }, 0 },
2057 { "outG", { indirDX, zAX }, 0 },
2058 /* f0 */
2059 { Bad_Opcode }, /* lock prefix */
2060 { "icebp", { XX }, 0 },
2061 { Bad_Opcode }, /* repne */
2062 { Bad_Opcode }, /* repz */
2063 { "hlt", { XX }, 0 },
2064 { "cmc", { XX }, 0 },
2065 { REG_TABLE (REG_F6) },
2066 { REG_TABLE (REG_F7) },
2067 /* f8 */
2068 { "clc", { XX }, 0 },
2069 { "stc", { XX }, 0 },
2070 { "cli", { XX }, 0 },
2071 { "sti", { XX }, 0 },
2072 { "cld", { XX }, 0 },
2073 { "std", { XX }, 0 },
2074 { REG_TABLE (REG_FE) },
2075 { REG_TABLE (REG_FF) },
2076 };
2077
2078 static const struct dis386 dis386_twobyte[] = {
2079 /* 00 */
2080 { REG_TABLE (REG_0F00 ) },
2081 { REG_TABLE (REG_0F01 ) },
2082 { "larS", { Gv, Ew }, 0 },
2083 { "lslS", { Gv, Ew }, 0 },
2084 { Bad_Opcode },
2085 { "syscall", { XX }, 0 },
2086 { "clts", { XX }, 0 },
2087 { "sysret%LQ", { XX }, 0 },
2088 /* 08 */
2089 { "invd", { XX }, 0 },
2090 { PREFIX_TABLE (PREFIX_0F09) },
2091 { Bad_Opcode },
2092 { "ud2", { XX }, 0 },
2093 { Bad_Opcode },
2094 { REG_TABLE (REG_0F0D) },
2095 { "femms", { XX }, 0 },
2096 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2097 /* 10 */
2098 { PREFIX_TABLE (PREFIX_0F10) },
2099 { PREFIX_TABLE (PREFIX_0F11) },
2100 { PREFIX_TABLE (PREFIX_0F12) },
2101 { MOD_TABLE (MOD_0F13) },
2102 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2103 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2104 { PREFIX_TABLE (PREFIX_0F16) },
2105 { MOD_TABLE (MOD_0F17) },
2106 /* 18 */
2107 { REG_TABLE (REG_0F18) },
2108 { "nopQ", { Ev }, 0 },
2109 { PREFIX_TABLE (PREFIX_0F1A) },
2110 { PREFIX_TABLE (PREFIX_0F1B) },
2111 { PREFIX_TABLE (PREFIX_0F1C) },
2112 { "nopQ", { Ev }, 0 },
2113 { PREFIX_TABLE (PREFIX_0F1E) },
2114 { "nopQ", { Ev }, 0 },
2115 /* 20 */
2116 { "movZ", { Em, Cm }, 0 },
2117 { "movZ", { Em, Dm }, 0 },
2118 { "movZ", { Cm, Em }, 0 },
2119 { "movZ", { Dm, Em }, 0 },
2120 { X86_64_TABLE (X86_64_0F24) },
2121 { Bad_Opcode },
2122 { X86_64_TABLE (X86_64_0F26) },
2123 { Bad_Opcode },
2124 /* 28 */
2125 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2126 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2127 { PREFIX_TABLE (PREFIX_0F2A) },
2128 { PREFIX_TABLE (PREFIX_0F2B) },
2129 { PREFIX_TABLE (PREFIX_0F2C) },
2130 { PREFIX_TABLE (PREFIX_0F2D) },
2131 { PREFIX_TABLE (PREFIX_0F2E) },
2132 { PREFIX_TABLE (PREFIX_0F2F) },
2133 /* 30 */
2134 { "wrmsr", { XX }, 0 },
2135 { "rdtsc", { XX }, 0 },
2136 { "rdmsr", { XX }, 0 },
2137 { "rdpmc", { XX }, 0 },
2138 { "sysenter", { SEP }, 0 },
2139 { "sysexit", { SEP }, 0 },
2140 { Bad_Opcode },
2141 { "getsec", { XX }, 0 },
2142 /* 38 */
2143 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2144 { Bad_Opcode },
2145 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2146 { Bad_Opcode },
2147 { Bad_Opcode },
2148 { Bad_Opcode },
2149 { Bad_Opcode },
2150 { Bad_Opcode },
2151 /* 40 */
2152 { "cmovoS", { Gv, Ev }, 0 },
2153 { "cmovnoS", { Gv, Ev }, 0 },
2154 { "cmovbS", { Gv, Ev }, 0 },
2155 { "cmovaeS", { Gv, Ev }, 0 },
2156 { "cmoveS", { Gv, Ev }, 0 },
2157 { "cmovneS", { Gv, Ev }, 0 },
2158 { "cmovbeS", { Gv, Ev }, 0 },
2159 { "cmovaS", { Gv, Ev }, 0 },
2160 /* 48 */
2161 { "cmovsS", { Gv, Ev }, 0 },
2162 { "cmovnsS", { Gv, Ev }, 0 },
2163 { "cmovpS", { Gv, Ev }, 0 },
2164 { "cmovnpS", { Gv, Ev }, 0 },
2165 { "cmovlS", { Gv, Ev }, 0 },
2166 { "cmovgeS", { Gv, Ev }, 0 },
2167 { "cmovleS", { Gv, Ev }, 0 },
2168 { "cmovgS", { Gv, Ev }, 0 },
2169 /* 50 */
2170 { MOD_TABLE (MOD_0F50) },
2171 { PREFIX_TABLE (PREFIX_0F51) },
2172 { PREFIX_TABLE (PREFIX_0F52) },
2173 { PREFIX_TABLE (PREFIX_0F53) },
2174 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2175 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2176 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2177 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2178 /* 58 */
2179 { PREFIX_TABLE (PREFIX_0F58) },
2180 { PREFIX_TABLE (PREFIX_0F59) },
2181 { PREFIX_TABLE (PREFIX_0F5A) },
2182 { PREFIX_TABLE (PREFIX_0F5B) },
2183 { PREFIX_TABLE (PREFIX_0F5C) },
2184 { PREFIX_TABLE (PREFIX_0F5D) },
2185 { PREFIX_TABLE (PREFIX_0F5E) },
2186 { PREFIX_TABLE (PREFIX_0F5F) },
2187 /* 60 */
2188 { PREFIX_TABLE (PREFIX_0F60) },
2189 { PREFIX_TABLE (PREFIX_0F61) },
2190 { PREFIX_TABLE (PREFIX_0F62) },
2191 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2192 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2193 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2194 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2195 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2196 /* 68 */
2197 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2198 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2199 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2200 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2201 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2202 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2203 { "movK", { MX, Edq }, PREFIX_OPCODE },
2204 { PREFIX_TABLE (PREFIX_0F6F) },
2205 /* 70 */
2206 { PREFIX_TABLE (PREFIX_0F70) },
2207 { REG_TABLE (REG_0F71) },
2208 { REG_TABLE (REG_0F72) },
2209 { REG_TABLE (REG_0F73) },
2210 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2211 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2212 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2213 { "emms", { XX }, PREFIX_OPCODE },
2214 /* 78 */
2215 { PREFIX_TABLE (PREFIX_0F78) },
2216 { PREFIX_TABLE (PREFIX_0F79) },
2217 { Bad_Opcode },
2218 { Bad_Opcode },
2219 { PREFIX_TABLE (PREFIX_0F7C) },
2220 { PREFIX_TABLE (PREFIX_0F7D) },
2221 { PREFIX_TABLE (PREFIX_0F7E) },
2222 { PREFIX_TABLE (PREFIX_0F7F) },
2223 /* 80 */
2224 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2225 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2226 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2227 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2228 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2229 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2230 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2231 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2232 /* 88 */
2233 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2234 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2235 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2236 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2237 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2238 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2239 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2240 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2241 /* 90 */
2242 { "seto", { Eb }, 0 },
2243 { "setno", { Eb }, 0 },
2244 { "setb", { Eb }, 0 },
2245 { "setae", { Eb }, 0 },
2246 { "sete", { Eb }, 0 },
2247 { "setne", { Eb }, 0 },
2248 { "setbe", { Eb }, 0 },
2249 { "seta", { Eb }, 0 },
2250 /* 98 */
2251 { "sets", { Eb }, 0 },
2252 { "setns", { Eb }, 0 },
2253 { "setp", { Eb }, 0 },
2254 { "setnp", { Eb }, 0 },
2255 { "setl", { Eb }, 0 },
2256 { "setge", { Eb }, 0 },
2257 { "setle", { Eb }, 0 },
2258 { "setg", { Eb }, 0 },
2259 /* a0 */
2260 { "pushP", { fs }, 0 },
2261 { "popP", { fs }, 0 },
2262 { "cpuid", { XX }, 0 },
2263 { "btS", { Ev, Gv }, 0 },
2264 { "shldS", { Ev, Gv, Ib }, 0 },
2265 { "shldS", { Ev, Gv, CL }, 0 },
2266 { REG_TABLE (REG_0FA6) },
2267 { REG_TABLE (REG_0FA7) },
2268 /* a8 */
2269 { "pushP", { gs }, 0 },
2270 { "popP", { gs }, 0 },
2271 { "rsm", { XX }, 0 },
2272 { "btsS", { Evh1, Gv }, 0 },
2273 { "shrdS", { Ev, Gv, Ib }, 0 },
2274 { "shrdS", { Ev, Gv, CL }, 0 },
2275 { REG_TABLE (REG_0FAE) },
2276 { "imulS", { Gv, Ev }, 0 },
2277 /* b0 */
2278 { "cmpxchgB", { Ebh1, Gb }, 0 },
2279 { "cmpxchgS", { Evh1, Gv }, 0 },
2280 { MOD_TABLE (MOD_0FB2) },
2281 { "btrS", { Evh1, Gv }, 0 },
2282 { MOD_TABLE (MOD_0FB4) },
2283 { MOD_TABLE (MOD_0FB5) },
2284 { "movz{bR|x}", { Gv, Eb }, 0 },
2285 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2286 /* b8 */
2287 { PREFIX_TABLE (PREFIX_0FB8) },
2288 { "ud1S", { Gv, Ev }, 0 },
2289 { REG_TABLE (REG_0FBA) },
2290 { "btcS", { Evh1, Gv }, 0 },
2291 { PREFIX_TABLE (PREFIX_0FBC) },
2292 { PREFIX_TABLE (PREFIX_0FBD) },
2293 { "movs{bR|x}", { Gv, Eb }, 0 },
2294 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2295 /* c0 */
2296 { "xaddB", { Ebh1, Gb }, 0 },
2297 { "xaddS", { Evh1, Gv }, 0 },
2298 { PREFIX_TABLE (PREFIX_0FC2) },
2299 { MOD_TABLE (MOD_0FC3) },
2300 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2301 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2302 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2303 { REG_TABLE (REG_0FC7) },
2304 /* c8 */
2305 { "bswap", { RMeAX }, 0 },
2306 { "bswap", { RMeCX }, 0 },
2307 { "bswap", { RMeDX }, 0 },
2308 { "bswap", { RMeBX }, 0 },
2309 { "bswap", { RMeSP }, 0 },
2310 { "bswap", { RMeBP }, 0 },
2311 { "bswap", { RMeSI }, 0 },
2312 { "bswap", { RMeDI }, 0 },
2313 /* d0 */
2314 { PREFIX_TABLE (PREFIX_0FD0) },
2315 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2316 { "psrld", { MX, EM }, PREFIX_OPCODE },
2317 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2318 { "paddq", { MX, EM }, PREFIX_OPCODE },
2319 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2320 { PREFIX_TABLE (PREFIX_0FD6) },
2321 { MOD_TABLE (MOD_0FD7) },
2322 /* d8 */
2323 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2324 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2325 { "pminub", { MX, EM }, PREFIX_OPCODE },
2326 { "pand", { MX, EM }, PREFIX_OPCODE },
2327 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2328 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2329 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2330 { "pandn", { MX, EM }, PREFIX_OPCODE },
2331 /* e0 */
2332 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2333 { "psraw", { MX, EM }, PREFIX_OPCODE },
2334 { "psrad", { MX, EM }, PREFIX_OPCODE },
2335 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2336 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2337 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2338 { PREFIX_TABLE (PREFIX_0FE6) },
2339 { PREFIX_TABLE (PREFIX_0FE7) },
2340 /* e8 */
2341 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2342 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2343 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2344 { "por", { MX, EM }, PREFIX_OPCODE },
2345 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2346 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2347 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2348 { "pxor", { MX, EM }, PREFIX_OPCODE },
2349 /* f0 */
2350 { PREFIX_TABLE (PREFIX_0FF0) },
2351 { "psllw", { MX, EM }, PREFIX_OPCODE },
2352 { "pslld", { MX, EM }, PREFIX_OPCODE },
2353 { "psllq", { MX, EM }, PREFIX_OPCODE },
2354 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2355 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2356 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2357 { PREFIX_TABLE (PREFIX_0FF7) },
2358 /* f8 */
2359 { "psubb", { MX, EM }, PREFIX_OPCODE },
2360 { "psubw", { MX, EM }, PREFIX_OPCODE },
2361 { "psubd", { MX, EM }, PREFIX_OPCODE },
2362 { "psubq", { MX, EM }, PREFIX_OPCODE },
2363 { "paddb", { MX, EM }, PREFIX_OPCODE },
2364 { "paddw", { MX, EM }, PREFIX_OPCODE },
2365 { "paddd", { MX, EM }, PREFIX_OPCODE },
2366 { "ud0S", { Gv, Ev }, 0 },
2367 };
2368
2369 static const unsigned char onebyte_has_modrm[256] = {
2370 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2371 /* ------------------------------- */
2372 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2373 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2374 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2375 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2376 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2377 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2378 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2379 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2380 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2381 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2382 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2383 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2384 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2385 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2386 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2387 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2388 /* ------------------------------- */
2389 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2390 };
2391
2392 static const unsigned char twobyte_has_modrm[256] = {
2393 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2394 /* ------------------------------- */
2395 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2396 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2397 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2398 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2399 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2400 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2401 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2402 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2403 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2404 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2405 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2406 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2407 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2408 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2409 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2410 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2411 /* ------------------------------- */
2412 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2413 };
2414
2415 static char obuf[100];
2416 static char *obufp;
2417 static char *mnemonicendp;
2418 static char scratchbuf[100];
2419 static unsigned char *start_codep;
2420 static unsigned char *insn_codep;
2421 static unsigned char *codep;
2422 static unsigned char *end_codep;
2423 static int last_lock_prefix;
2424 static int last_repz_prefix;
2425 static int last_repnz_prefix;
2426 static int last_data_prefix;
2427 static int last_addr_prefix;
2428 static int last_rex_prefix;
2429 static int last_seg_prefix;
2430 static int fwait_prefix;
2431 /* The active segment register prefix. */
2432 static int active_seg_prefix;
2433 #define MAX_CODE_LENGTH 15
2434 /* We can up to 14 prefixes since the maximum instruction length is
2435 15bytes. */
2436 static int all_prefixes[MAX_CODE_LENGTH - 1];
2437 static disassemble_info *the_info;
2438 static struct
2439 {
2440 int mod;
2441 int reg;
2442 int rm;
2443 }
2444 modrm;
2445 static unsigned char need_modrm;
2446 static struct
2447 {
2448 int scale;
2449 int index;
2450 int base;
2451 }
2452 sib;
2453 static struct
2454 {
2455 int register_specifier;
2456 int length;
2457 int prefix;
2458 int w;
2459 int evex;
2460 int r;
2461 int v;
2462 int mask_register_specifier;
2463 int zeroing;
2464 int ll;
2465 int b;
2466 }
2467 vex;
2468 static unsigned char need_vex;
2469
2470 struct op
2471 {
2472 const char *name;
2473 unsigned int len;
2474 };
2475
2476 /* If we are accessing mod/rm/reg without need_modrm set, then the
2477 values are stale. Hitting this abort likely indicates that you
2478 need to update onebyte_has_modrm or twobyte_has_modrm. */
2479 #define MODRM_CHECK if (!need_modrm) abort ()
2480
2481 static const char **names64;
2482 static const char **names32;
2483 static const char **names16;
2484 static const char **names8;
2485 static const char **names8rex;
2486 static const char **names_seg;
2487 static const char *index64;
2488 static const char *index32;
2489 static const char **index16;
2490 static const char **names_bnd;
2491
2492 static const char *intel_names64[] = {
2493 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2494 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2495 };
2496 static const char *intel_names32[] = {
2497 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2498 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2499 };
2500 static const char *intel_names16[] = {
2501 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2502 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2503 };
2504 static const char *intel_names8[] = {
2505 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2506 };
2507 static const char *intel_names8rex[] = {
2508 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2509 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2510 };
2511 static const char *intel_names_seg[] = {
2512 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2513 };
2514 static const char *intel_index64 = "riz";
2515 static const char *intel_index32 = "eiz";
2516 static const char *intel_index16[] = {
2517 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2518 };
2519
2520 static const char *att_names64[] = {
2521 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2522 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2523 };
2524 static const char *att_names32[] = {
2525 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2526 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2527 };
2528 static const char *att_names16[] = {
2529 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2530 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2531 };
2532 static const char *att_names8[] = {
2533 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2534 };
2535 static const char *att_names8rex[] = {
2536 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2537 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2538 };
2539 static const char *att_names_seg[] = {
2540 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2541 };
2542 static const char *att_index64 = "%riz";
2543 static const char *att_index32 = "%eiz";
2544 static const char *att_index16[] = {
2545 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2546 };
2547
2548 static const char **names_mm;
2549 static const char *intel_names_mm[] = {
2550 "mm0", "mm1", "mm2", "mm3",
2551 "mm4", "mm5", "mm6", "mm7"
2552 };
2553 static const char *att_names_mm[] = {
2554 "%mm0", "%mm1", "%mm2", "%mm3",
2555 "%mm4", "%mm5", "%mm6", "%mm7"
2556 };
2557
2558 static const char *intel_names_bnd[] = {
2559 "bnd0", "bnd1", "bnd2", "bnd3"
2560 };
2561
2562 static const char *att_names_bnd[] = {
2563 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2564 };
2565
2566 static const char **names_xmm;
2567 static const char *intel_names_xmm[] = {
2568 "xmm0", "xmm1", "xmm2", "xmm3",
2569 "xmm4", "xmm5", "xmm6", "xmm7",
2570 "xmm8", "xmm9", "xmm10", "xmm11",
2571 "xmm12", "xmm13", "xmm14", "xmm15",
2572 "xmm16", "xmm17", "xmm18", "xmm19",
2573 "xmm20", "xmm21", "xmm22", "xmm23",
2574 "xmm24", "xmm25", "xmm26", "xmm27",
2575 "xmm28", "xmm29", "xmm30", "xmm31"
2576 };
2577 static const char *att_names_xmm[] = {
2578 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2579 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2580 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2581 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2582 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2583 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2584 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2585 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2586 };
2587
2588 static const char **names_ymm;
2589 static const char *intel_names_ymm[] = {
2590 "ymm0", "ymm1", "ymm2", "ymm3",
2591 "ymm4", "ymm5", "ymm6", "ymm7",
2592 "ymm8", "ymm9", "ymm10", "ymm11",
2593 "ymm12", "ymm13", "ymm14", "ymm15",
2594 "ymm16", "ymm17", "ymm18", "ymm19",
2595 "ymm20", "ymm21", "ymm22", "ymm23",
2596 "ymm24", "ymm25", "ymm26", "ymm27",
2597 "ymm28", "ymm29", "ymm30", "ymm31"
2598 };
2599 static const char *att_names_ymm[] = {
2600 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2601 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2602 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2603 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2604 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2605 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2606 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2607 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2608 };
2609
2610 static const char **names_zmm;
2611 static const char *intel_names_zmm[] = {
2612 "zmm0", "zmm1", "zmm2", "zmm3",
2613 "zmm4", "zmm5", "zmm6", "zmm7",
2614 "zmm8", "zmm9", "zmm10", "zmm11",
2615 "zmm12", "zmm13", "zmm14", "zmm15",
2616 "zmm16", "zmm17", "zmm18", "zmm19",
2617 "zmm20", "zmm21", "zmm22", "zmm23",
2618 "zmm24", "zmm25", "zmm26", "zmm27",
2619 "zmm28", "zmm29", "zmm30", "zmm31"
2620 };
2621 static const char *att_names_zmm[] = {
2622 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2623 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2624 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2625 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2626 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2627 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2628 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2629 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2630 };
2631
2632 static const char **names_tmm;
2633 static const char *intel_names_tmm[] = {
2634 "tmm0", "tmm1", "tmm2", "tmm3",
2635 "tmm4", "tmm5", "tmm6", "tmm7"
2636 };
2637 static const char *att_names_tmm[] = {
2638 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2639 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2640 };
2641
2642 static const char **names_mask;
2643 static const char *intel_names_mask[] = {
2644 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2645 };
2646 static const char *att_names_mask[] = {
2647 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2648 };
2649
2650 static const char *names_rounding[] =
2651 {
2652 "{rn-sae}",
2653 "{rd-sae}",
2654 "{ru-sae}",
2655 "{rz-sae}"
2656 };
2657
2658 static const struct dis386 reg_table[][8] = {
2659 /* REG_80 */
2660 {
2661 { "addA", { Ebh1, Ib }, 0 },
2662 { "orA", { Ebh1, Ib }, 0 },
2663 { "adcA", { Ebh1, Ib }, 0 },
2664 { "sbbA", { Ebh1, Ib }, 0 },
2665 { "andA", { Ebh1, Ib }, 0 },
2666 { "subA", { Ebh1, Ib }, 0 },
2667 { "xorA", { Ebh1, Ib }, 0 },
2668 { "cmpA", { Eb, Ib }, 0 },
2669 },
2670 /* REG_81 */
2671 {
2672 { "addQ", { Evh1, Iv }, 0 },
2673 { "orQ", { Evh1, Iv }, 0 },
2674 { "adcQ", { Evh1, Iv }, 0 },
2675 { "sbbQ", { Evh1, Iv }, 0 },
2676 { "andQ", { Evh1, Iv }, 0 },
2677 { "subQ", { Evh1, Iv }, 0 },
2678 { "xorQ", { Evh1, Iv }, 0 },
2679 { "cmpQ", { Ev, Iv }, 0 },
2680 },
2681 /* REG_83 */
2682 {
2683 { "addQ", { Evh1, sIb }, 0 },
2684 { "orQ", { Evh1, sIb }, 0 },
2685 { "adcQ", { Evh1, sIb }, 0 },
2686 { "sbbQ", { Evh1, sIb }, 0 },
2687 { "andQ", { Evh1, sIb }, 0 },
2688 { "subQ", { Evh1, sIb }, 0 },
2689 { "xorQ", { Evh1, sIb }, 0 },
2690 { "cmpQ", { Ev, sIb }, 0 },
2691 },
2692 /* REG_8F */
2693 {
2694 { "pop{P|}", { stackEv }, 0 },
2695 { XOP_8F_TABLE (XOP_09) },
2696 { Bad_Opcode },
2697 { Bad_Opcode },
2698 { Bad_Opcode },
2699 { XOP_8F_TABLE (XOP_09) },
2700 },
2701 /* REG_C0 */
2702 {
2703 { "rolA", { Eb, Ib }, 0 },
2704 { "rorA", { Eb, Ib }, 0 },
2705 { "rclA", { Eb, Ib }, 0 },
2706 { "rcrA", { Eb, Ib }, 0 },
2707 { "shlA", { Eb, Ib }, 0 },
2708 { "shrA", { Eb, Ib }, 0 },
2709 { "shlA", { Eb, Ib }, 0 },
2710 { "sarA", { Eb, Ib }, 0 },
2711 },
2712 /* REG_C1 */
2713 {
2714 { "rolQ", { Ev, Ib }, 0 },
2715 { "rorQ", { Ev, Ib }, 0 },
2716 { "rclQ", { Ev, Ib }, 0 },
2717 { "rcrQ", { Ev, Ib }, 0 },
2718 { "shlQ", { Ev, Ib }, 0 },
2719 { "shrQ", { Ev, Ib }, 0 },
2720 { "shlQ", { Ev, Ib }, 0 },
2721 { "sarQ", { Ev, Ib }, 0 },
2722 },
2723 /* REG_C6 */
2724 {
2725 { "movA", { Ebh3, Ib }, 0 },
2726 { Bad_Opcode },
2727 { Bad_Opcode },
2728 { Bad_Opcode },
2729 { Bad_Opcode },
2730 { Bad_Opcode },
2731 { Bad_Opcode },
2732 { MOD_TABLE (MOD_C6_REG_7) },
2733 },
2734 /* REG_C7 */
2735 {
2736 { "movQ", { Evh3, Iv }, 0 },
2737 { Bad_Opcode },
2738 { Bad_Opcode },
2739 { Bad_Opcode },
2740 { Bad_Opcode },
2741 { Bad_Opcode },
2742 { Bad_Opcode },
2743 { MOD_TABLE (MOD_C7_REG_7) },
2744 },
2745 /* REG_D0 */
2746 {
2747 { "rolA", { Eb, I1 }, 0 },
2748 { "rorA", { Eb, I1 }, 0 },
2749 { "rclA", { Eb, I1 }, 0 },
2750 { "rcrA", { Eb, I1 }, 0 },
2751 { "shlA", { Eb, I1 }, 0 },
2752 { "shrA", { Eb, I1 }, 0 },
2753 { "shlA", { Eb, I1 }, 0 },
2754 { "sarA", { Eb, I1 }, 0 },
2755 },
2756 /* REG_D1 */
2757 {
2758 { "rolQ", { Ev, I1 }, 0 },
2759 { "rorQ", { Ev, I1 }, 0 },
2760 { "rclQ", { Ev, I1 }, 0 },
2761 { "rcrQ", { Ev, I1 }, 0 },
2762 { "shlQ", { Ev, I1 }, 0 },
2763 { "shrQ", { Ev, I1 }, 0 },
2764 { "shlQ", { Ev, I1 }, 0 },
2765 { "sarQ", { Ev, I1 }, 0 },
2766 },
2767 /* REG_D2 */
2768 {
2769 { "rolA", { Eb, CL }, 0 },
2770 { "rorA", { Eb, CL }, 0 },
2771 { "rclA", { Eb, CL }, 0 },
2772 { "rcrA", { Eb, CL }, 0 },
2773 { "shlA", { Eb, CL }, 0 },
2774 { "shrA", { Eb, CL }, 0 },
2775 { "shlA", { Eb, CL }, 0 },
2776 { "sarA", { Eb, CL }, 0 },
2777 },
2778 /* REG_D3 */
2779 {
2780 { "rolQ", { Ev, CL }, 0 },
2781 { "rorQ", { Ev, CL }, 0 },
2782 { "rclQ", { Ev, CL }, 0 },
2783 { "rcrQ", { Ev, CL }, 0 },
2784 { "shlQ", { Ev, CL }, 0 },
2785 { "shrQ", { Ev, CL }, 0 },
2786 { "shlQ", { Ev, CL }, 0 },
2787 { "sarQ", { Ev, CL }, 0 },
2788 },
2789 /* REG_F6 */
2790 {
2791 { "testA", { Eb, Ib }, 0 },
2792 { "testA", { Eb, Ib }, 0 },
2793 { "notA", { Ebh1 }, 0 },
2794 { "negA", { Ebh1 }, 0 },
2795 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2796 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2797 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2798 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2799 },
2800 /* REG_F7 */
2801 {
2802 { "testQ", { Ev, Iv }, 0 },
2803 { "testQ", { Ev, Iv }, 0 },
2804 { "notQ", { Evh1 }, 0 },
2805 { "negQ", { Evh1 }, 0 },
2806 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2807 { "imulQ", { Ev }, 0 },
2808 { "divQ", { Ev }, 0 },
2809 { "idivQ", { Ev }, 0 },
2810 },
2811 /* REG_FE */
2812 {
2813 { "incA", { Ebh1 }, 0 },
2814 { "decA", { Ebh1 }, 0 },
2815 },
2816 /* REG_FF */
2817 {
2818 { "incQ", { Evh1 }, 0 },
2819 { "decQ", { Evh1 }, 0 },
2820 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2821 { MOD_TABLE (MOD_FF_REG_3) },
2822 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2823 { MOD_TABLE (MOD_FF_REG_5) },
2824 { "push{P|}", { stackEv }, 0 },
2825 { Bad_Opcode },
2826 },
2827 /* REG_0F00 */
2828 {
2829 { "sldtD", { Sv }, 0 },
2830 { "strD", { Sv }, 0 },
2831 { "lldt", { Ew }, 0 },
2832 { "ltr", { Ew }, 0 },
2833 { "verr", { Ew }, 0 },
2834 { "verw", { Ew }, 0 },
2835 { Bad_Opcode },
2836 { Bad_Opcode },
2837 },
2838 /* REG_0F01 */
2839 {
2840 { MOD_TABLE (MOD_0F01_REG_0) },
2841 { MOD_TABLE (MOD_0F01_REG_1) },
2842 { MOD_TABLE (MOD_0F01_REG_2) },
2843 { MOD_TABLE (MOD_0F01_REG_3) },
2844 { "smswD", { Sv }, 0 },
2845 { MOD_TABLE (MOD_0F01_REG_5) },
2846 { "lmsw", { Ew }, 0 },
2847 { MOD_TABLE (MOD_0F01_REG_7) },
2848 },
2849 /* REG_0F0D */
2850 {
2851 { "prefetch", { Mb }, 0 },
2852 { "prefetchw", { Mb }, 0 },
2853 { "prefetchwt1", { Mb }, 0 },
2854 { "prefetch", { Mb }, 0 },
2855 { "prefetch", { Mb }, 0 },
2856 { "prefetch", { Mb }, 0 },
2857 { "prefetch", { Mb }, 0 },
2858 { "prefetch", { Mb }, 0 },
2859 },
2860 /* REG_0F18 */
2861 {
2862 { MOD_TABLE (MOD_0F18_REG_0) },
2863 { MOD_TABLE (MOD_0F18_REG_1) },
2864 { MOD_TABLE (MOD_0F18_REG_2) },
2865 { MOD_TABLE (MOD_0F18_REG_3) },
2866 { MOD_TABLE (MOD_0F18_REG_4) },
2867 { MOD_TABLE (MOD_0F18_REG_5) },
2868 { MOD_TABLE (MOD_0F18_REG_6) },
2869 { MOD_TABLE (MOD_0F18_REG_7) },
2870 },
2871 /* REG_0F1C_P_0_MOD_0 */
2872 {
2873 { "cldemote", { Mb }, 0 },
2874 { "nopQ", { Ev }, 0 },
2875 { "nopQ", { Ev }, 0 },
2876 { "nopQ", { Ev }, 0 },
2877 { "nopQ", { Ev }, 0 },
2878 { "nopQ", { Ev }, 0 },
2879 { "nopQ", { Ev }, 0 },
2880 { "nopQ", { Ev }, 0 },
2881 },
2882 /* REG_0F1E_P_1_MOD_3 */
2883 {
2884 { "nopQ", { Ev }, 0 },
2885 { "rdsspK", { Edq }, PREFIX_OPCODE },
2886 { "nopQ", { Ev }, 0 },
2887 { "nopQ", { Ev }, 0 },
2888 { "nopQ", { Ev }, 0 },
2889 { "nopQ", { Ev }, 0 },
2890 { "nopQ", { Ev }, 0 },
2891 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2892 },
2893 /* REG_0F71 */
2894 {
2895 { Bad_Opcode },
2896 { Bad_Opcode },
2897 { MOD_TABLE (MOD_0F71_REG_2) },
2898 { Bad_Opcode },
2899 { MOD_TABLE (MOD_0F71_REG_4) },
2900 { Bad_Opcode },
2901 { MOD_TABLE (MOD_0F71_REG_6) },
2902 },
2903 /* REG_0F72 */
2904 {
2905 { Bad_Opcode },
2906 { Bad_Opcode },
2907 { MOD_TABLE (MOD_0F72_REG_2) },
2908 { Bad_Opcode },
2909 { MOD_TABLE (MOD_0F72_REG_4) },
2910 { Bad_Opcode },
2911 { MOD_TABLE (MOD_0F72_REG_6) },
2912 },
2913 /* REG_0F73 */
2914 {
2915 { Bad_Opcode },
2916 { Bad_Opcode },
2917 { MOD_TABLE (MOD_0F73_REG_2) },
2918 { MOD_TABLE (MOD_0F73_REG_3) },
2919 { Bad_Opcode },
2920 { Bad_Opcode },
2921 { MOD_TABLE (MOD_0F73_REG_6) },
2922 { MOD_TABLE (MOD_0F73_REG_7) },
2923 },
2924 /* REG_0FA6 */
2925 {
2926 { "montmul", { { OP_0f07, 0 } }, 0 },
2927 { "xsha1", { { OP_0f07, 0 } }, 0 },
2928 { "xsha256", { { OP_0f07, 0 } }, 0 },
2929 },
2930 /* REG_0FA7 */
2931 {
2932 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2933 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2934 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2935 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2936 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2937 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2938 },
2939 /* REG_0FAE */
2940 {
2941 { MOD_TABLE (MOD_0FAE_REG_0) },
2942 { MOD_TABLE (MOD_0FAE_REG_1) },
2943 { MOD_TABLE (MOD_0FAE_REG_2) },
2944 { MOD_TABLE (MOD_0FAE_REG_3) },
2945 { MOD_TABLE (MOD_0FAE_REG_4) },
2946 { MOD_TABLE (MOD_0FAE_REG_5) },
2947 { MOD_TABLE (MOD_0FAE_REG_6) },
2948 { MOD_TABLE (MOD_0FAE_REG_7) },
2949 },
2950 /* REG_0FBA */
2951 {
2952 { Bad_Opcode },
2953 { Bad_Opcode },
2954 { Bad_Opcode },
2955 { Bad_Opcode },
2956 { "btQ", { Ev, Ib }, 0 },
2957 { "btsQ", { Evh1, Ib }, 0 },
2958 { "btrQ", { Evh1, Ib }, 0 },
2959 { "btcQ", { Evh1, Ib }, 0 },
2960 },
2961 /* REG_0FC7 */
2962 {
2963 { Bad_Opcode },
2964 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2965 { Bad_Opcode },
2966 { MOD_TABLE (MOD_0FC7_REG_3) },
2967 { MOD_TABLE (MOD_0FC7_REG_4) },
2968 { MOD_TABLE (MOD_0FC7_REG_5) },
2969 { MOD_TABLE (MOD_0FC7_REG_6) },
2970 { MOD_TABLE (MOD_0FC7_REG_7) },
2971 },
2972 /* REG_VEX_0F71 */
2973 {
2974 { Bad_Opcode },
2975 { Bad_Opcode },
2976 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2977 { Bad_Opcode },
2978 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2979 { Bad_Opcode },
2980 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2981 },
2982 /* REG_VEX_0F72 */
2983 {
2984 { Bad_Opcode },
2985 { Bad_Opcode },
2986 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2987 { Bad_Opcode },
2988 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2989 { Bad_Opcode },
2990 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2991 },
2992 /* REG_VEX_0F73 */
2993 {
2994 { Bad_Opcode },
2995 { Bad_Opcode },
2996 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2997 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2998 { Bad_Opcode },
2999 { Bad_Opcode },
3000 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3001 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3002 },
3003 /* REG_VEX_0FAE */
3004 {
3005 { Bad_Opcode },
3006 { Bad_Opcode },
3007 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3008 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3009 },
3010 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3011 {
3012 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3013 },
3014 /* REG_VEX_0F38F3 */
3015 {
3016 { Bad_Opcode },
3017 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3018 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3019 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3020 },
3021 /* REG_0FXOP_09_01_L_0 */
3022 {
3023 { Bad_Opcode },
3024 { "blcfill", { VexGdq, Edq }, 0 },
3025 { "blsfill", { VexGdq, Edq }, 0 },
3026 { "blcs", { VexGdq, Edq }, 0 },
3027 { "tzmsk", { VexGdq, Edq }, 0 },
3028 { "blcic", { VexGdq, Edq }, 0 },
3029 { "blsic", { VexGdq, Edq }, 0 },
3030 { "t1mskc", { VexGdq, Edq }, 0 },
3031 },
3032 /* REG_0FXOP_09_02_L_0 */
3033 {
3034 { Bad_Opcode },
3035 { "blcmsk", { VexGdq, Edq }, 0 },
3036 { Bad_Opcode },
3037 { Bad_Opcode },
3038 { Bad_Opcode },
3039 { Bad_Opcode },
3040 { "blci", { VexGdq, Edq }, 0 },
3041 },
3042 /* REG_0FXOP_09_12_M_1_L_0 */
3043 {
3044 { "llwpcb", { Edq }, 0 },
3045 { "slwpcb", { Edq }, 0 },
3046 },
3047 /* REG_0FXOP_0A_12_L_0 */
3048 {
3049 { "lwpins", { VexGdq, Ed, Id }, 0 },
3050 { "lwpval", { VexGdq, Ed, Id }, 0 },
3051 },
3052
3053 #include "i386-dis-evex-reg.h"
3054 };
3055
3056 static const struct dis386 prefix_table[][4] = {
3057 /* PREFIX_90 */
3058 {
3059 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3060 { "pause", { XX }, 0 },
3061 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3062 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3063 },
3064
3065 /* PREFIX_0F01_REG_3_RM_1 */
3066 {
3067 { "vmmcall", { Skip_MODRM }, 0 },
3068 { "vmgexit", { Skip_MODRM }, 0 },
3069 { Bad_Opcode },
3070 { "vmgexit", { Skip_MODRM }, 0 },
3071 },
3072
3073 /* PREFIX_0F01_REG_5_MOD_0 */
3074 {
3075 { Bad_Opcode },
3076 { "rstorssp", { Mq }, PREFIX_OPCODE },
3077 },
3078
3079 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3080 {
3081 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3082 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3083 { Bad_Opcode },
3084 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3085 },
3086
3087 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3088 {
3089 { Bad_Opcode },
3090 { Bad_Opcode },
3091 { Bad_Opcode },
3092 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3093 },
3094
3095 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3096 {
3097 { Bad_Opcode },
3098 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3099 },
3100
3101 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3102 {
3103 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3104 { "mcommit", { Skip_MODRM }, 0 },
3105 },
3106
3107 /* PREFIX_0F09 */
3108 {
3109 { "wbinvd", { XX }, 0 },
3110 { "wbnoinvd", { XX }, 0 },
3111 },
3112
3113 /* PREFIX_0F10 */
3114 {
3115 { "movups", { XM, EXx }, PREFIX_OPCODE },
3116 { "movss", { XM, EXd }, PREFIX_OPCODE },
3117 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3118 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3119 },
3120
3121 /* PREFIX_0F11 */
3122 {
3123 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3124 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3125 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3126 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3127 },
3128
3129 /* PREFIX_0F12 */
3130 {
3131 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3132 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3133 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3134 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3135 },
3136
3137 /* PREFIX_0F16 */
3138 {
3139 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3140 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3141 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3142 },
3143
3144 /* PREFIX_0F1A */
3145 {
3146 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3147 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3148 { "bndmov", { Gbnd, Ebnd }, 0 },
3149 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3150 },
3151
3152 /* PREFIX_0F1B */
3153 {
3154 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3155 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3156 { "bndmov", { EbndS, Gbnd }, 0 },
3157 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3158 },
3159
3160 /* PREFIX_0F1C */
3161 {
3162 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3163 { "nopQ", { Ev }, PREFIX_OPCODE },
3164 { "nopQ", { Ev }, PREFIX_OPCODE },
3165 { "nopQ", { Ev }, PREFIX_OPCODE },
3166 },
3167
3168 /* PREFIX_0F1E */
3169 {
3170 { "nopQ", { Ev }, PREFIX_OPCODE },
3171 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3172 { "nopQ", { Ev }, PREFIX_OPCODE },
3173 { "nopQ", { Ev }, PREFIX_OPCODE },
3174 },
3175
3176 /* PREFIX_0F2A */
3177 {
3178 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3179 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3180 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3181 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3182 },
3183
3184 /* PREFIX_0F2B */
3185 {
3186 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3187 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3188 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3189 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3190 },
3191
3192 /* PREFIX_0F2C */
3193 {
3194 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3195 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3196 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3197 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3198 },
3199
3200 /* PREFIX_0F2D */
3201 {
3202 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3203 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3204 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3205 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3206 },
3207
3208 /* PREFIX_0F2E */
3209 {
3210 { "ucomiss",{ XM, EXd }, 0 },
3211 { Bad_Opcode },
3212 { "ucomisd",{ XM, EXq }, 0 },
3213 },
3214
3215 /* PREFIX_0F2F */
3216 {
3217 { "comiss", { XM, EXd }, 0 },
3218 { Bad_Opcode },
3219 { "comisd", { XM, EXq }, 0 },
3220 },
3221
3222 /* PREFIX_0F51 */
3223 {
3224 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3225 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3226 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3227 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3228 },
3229
3230 /* PREFIX_0F52 */
3231 {
3232 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3233 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3234 },
3235
3236 /* PREFIX_0F53 */
3237 {
3238 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3239 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3240 },
3241
3242 /* PREFIX_0F58 */
3243 {
3244 { "addps", { XM, EXx }, PREFIX_OPCODE },
3245 { "addss", { XM, EXd }, PREFIX_OPCODE },
3246 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3247 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3248 },
3249
3250 /* PREFIX_0F59 */
3251 {
3252 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3253 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3254 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3255 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3256 },
3257
3258 /* PREFIX_0F5A */
3259 {
3260 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3261 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3262 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3263 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3264 },
3265
3266 /* PREFIX_0F5B */
3267 {
3268 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3269 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3270 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3271 },
3272
3273 /* PREFIX_0F5C */
3274 {
3275 { "subps", { XM, EXx }, PREFIX_OPCODE },
3276 { "subss", { XM, EXd }, PREFIX_OPCODE },
3277 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3278 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3279 },
3280
3281 /* PREFIX_0F5D */
3282 {
3283 { "minps", { XM, EXx }, PREFIX_OPCODE },
3284 { "minss", { XM, EXd }, PREFIX_OPCODE },
3285 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3286 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3287 },
3288
3289 /* PREFIX_0F5E */
3290 {
3291 { "divps", { XM, EXx }, PREFIX_OPCODE },
3292 { "divss", { XM, EXd }, PREFIX_OPCODE },
3293 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3294 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3295 },
3296
3297 /* PREFIX_0F5F */
3298 {
3299 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3300 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3301 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3302 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3303 },
3304
3305 /* PREFIX_0F60 */
3306 {
3307 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3308 { Bad_Opcode },
3309 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3310 },
3311
3312 /* PREFIX_0F61 */
3313 {
3314 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3315 { Bad_Opcode },
3316 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3317 },
3318
3319 /* PREFIX_0F62 */
3320 {
3321 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3322 { Bad_Opcode },
3323 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3324 },
3325
3326 /* PREFIX_0F6F */
3327 {
3328 { "movq", { MX, EM }, PREFIX_OPCODE },
3329 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3330 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3331 },
3332
3333 /* PREFIX_0F70 */
3334 {
3335 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3336 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3337 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3338 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3339 },
3340
3341 /* PREFIX_0F78 */
3342 {
3343 {"vmread", { Em, Gm }, 0 },
3344 { Bad_Opcode },
3345 {"extrq", { XS, Ib, Ib }, 0 },
3346 {"insertq", { XM, XS, Ib, Ib }, 0 },
3347 },
3348
3349 /* PREFIX_0F79 */
3350 {
3351 {"vmwrite", { Gm, Em }, 0 },
3352 { Bad_Opcode },
3353 {"extrq", { XM, XS }, 0 },
3354 {"insertq", { XM, XS }, 0 },
3355 },
3356
3357 /* PREFIX_0F7C */
3358 {
3359 { Bad_Opcode },
3360 { Bad_Opcode },
3361 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3362 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3363 },
3364
3365 /* PREFIX_0F7D */
3366 {
3367 { Bad_Opcode },
3368 { Bad_Opcode },
3369 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3370 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3371 },
3372
3373 /* PREFIX_0F7E */
3374 {
3375 { "movK", { Edq, MX }, PREFIX_OPCODE },
3376 { "movq", { XM, EXq }, PREFIX_OPCODE },
3377 { "movK", { Edq, XM }, PREFIX_OPCODE },
3378 },
3379
3380 /* PREFIX_0F7F */
3381 {
3382 { "movq", { EMS, MX }, PREFIX_OPCODE },
3383 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3384 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3385 },
3386
3387 /* PREFIX_0FAE_REG_0_MOD_3 */
3388 {
3389 { Bad_Opcode },
3390 { "rdfsbase", { Ev }, 0 },
3391 },
3392
3393 /* PREFIX_0FAE_REG_1_MOD_3 */
3394 {
3395 { Bad_Opcode },
3396 { "rdgsbase", { Ev }, 0 },
3397 },
3398
3399 /* PREFIX_0FAE_REG_2_MOD_3 */
3400 {
3401 { Bad_Opcode },
3402 { "wrfsbase", { Ev }, 0 },
3403 },
3404
3405 /* PREFIX_0FAE_REG_3_MOD_3 */
3406 {
3407 { Bad_Opcode },
3408 { "wrgsbase", { Ev }, 0 },
3409 },
3410
3411 /* PREFIX_0FAE_REG_4_MOD_0 */
3412 {
3413 { "xsave", { FXSAVE }, 0 },
3414 { "ptwrite{%LQ|}", { Edq }, 0 },
3415 },
3416
3417 /* PREFIX_0FAE_REG_4_MOD_3 */
3418 {
3419 { Bad_Opcode },
3420 { "ptwrite{%LQ|}", { Edq }, 0 },
3421 },
3422
3423 /* PREFIX_0FAE_REG_5_MOD_3 */
3424 {
3425 { "lfence", { Skip_MODRM }, 0 },
3426 { "incsspK", { Edq }, PREFIX_OPCODE },
3427 },
3428
3429 /* PREFIX_0FAE_REG_6_MOD_0 */
3430 {
3431 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3432 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3433 { "clwb", { Mb }, PREFIX_OPCODE },
3434 },
3435
3436 /* PREFIX_0FAE_REG_6_MOD_3 */
3437 {
3438 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3439 { "umonitor", { Eva }, PREFIX_OPCODE },
3440 { "tpause", { Edq }, PREFIX_OPCODE },
3441 { "umwait", { Edq }, PREFIX_OPCODE },
3442 },
3443
3444 /* PREFIX_0FAE_REG_7_MOD_0 */
3445 {
3446 { "clflush", { Mb }, 0 },
3447 { Bad_Opcode },
3448 { "clflushopt", { Mb }, 0 },
3449 },
3450
3451 /* PREFIX_0FB8 */
3452 {
3453 { Bad_Opcode },
3454 { "popcntS", { Gv, Ev }, 0 },
3455 },
3456
3457 /* PREFIX_0FBC */
3458 {
3459 { "bsfS", { Gv, Ev }, 0 },
3460 { "tzcntS", { Gv, Ev }, 0 },
3461 { "bsfS", { Gv, Ev }, 0 },
3462 },
3463
3464 /* PREFIX_0FBD */
3465 {
3466 { "bsrS", { Gv, Ev }, 0 },
3467 { "lzcntS", { Gv, Ev }, 0 },
3468 { "bsrS", { Gv, Ev }, 0 },
3469 },
3470
3471 /* PREFIX_0FC2 */
3472 {
3473 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3474 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3475 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3476 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3477 },
3478
3479 /* PREFIX_0FC7_REG_6_MOD_0 */
3480 {
3481 { "vmptrld",{ Mq }, 0 },
3482 { "vmxon", { Mq }, 0 },
3483 { "vmclear",{ Mq }, 0 },
3484 },
3485
3486 /* PREFIX_0FC7_REG_6_MOD_3 */
3487 {
3488 { "rdrand", { Ev }, 0 },
3489 { Bad_Opcode },
3490 { "rdrand", { Ev }, 0 }
3491 },
3492
3493 /* PREFIX_0FC7_REG_7_MOD_3 */
3494 {
3495 { "rdseed", { Ev }, 0 },
3496 { "rdpid", { Em }, 0 },
3497 { "rdseed", { Ev }, 0 },
3498 },
3499
3500 /* PREFIX_0FD0 */
3501 {
3502 { Bad_Opcode },
3503 { Bad_Opcode },
3504 { "addsubpd", { XM, EXx }, 0 },
3505 { "addsubps", { XM, EXx }, 0 },
3506 },
3507
3508 /* PREFIX_0FD6 */
3509 {
3510 { Bad_Opcode },
3511 { "movq2dq",{ XM, MS }, 0 },
3512 { "movq", { EXqS, XM }, 0 },
3513 { "movdq2q",{ MX, XS }, 0 },
3514 },
3515
3516 /* PREFIX_0FE6 */
3517 {
3518 { Bad_Opcode },
3519 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3520 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3521 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3522 },
3523
3524 /* PREFIX_0FE7 */
3525 {
3526 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3527 { Bad_Opcode },
3528 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3529 },
3530
3531 /* PREFIX_0FF0 */
3532 {
3533 { Bad_Opcode },
3534 { Bad_Opcode },
3535 { Bad_Opcode },
3536 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3537 },
3538
3539 /* PREFIX_0FF7 */
3540 {
3541 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3542 { Bad_Opcode },
3543 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3544 },
3545
3546 /* PREFIX_0F38F0 */
3547 {
3548 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3549 { Bad_Opcode },
3550 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3551 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3552 },
3553
3554 /* PREFIX_0F38F1 */
3555 {
3556 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3557 { Bad_Opcode },
3558 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3559 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3560 },
3561
3562 /* PREFIX_0F38F6 */
3563 {
3564 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3565 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3566 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3567 { Bad_Opcode },
3568 },
3569
3570 /* PREFIX_0F38F8 */
3571 {
3572 { Bad_Opcode },
3573 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3574 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3575 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3576 },
3577
3578 /* PREFIX_VEX_0F10 */
3579 {
3580 { "vmovups", { XM, EXx }, 0 },
3581 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3582 { "vmovupd", { XM, EXx }, 0 },
3583 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3584 },
3585
3586 /* PREFIX_VEX_0F11 */
3587 {
3588 { "vmovups", { EXxS, XM }, 0 },
3589 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3590 { "vmovupd", { EXxS, XM }, 0 },
3591 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3592 },
3593
3594 /* PREFIX_VEX_0F12 */
3595 {
3596 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3597 { "vmovsldup", { XM, EXx }, 0 },
3598 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3599 { "vmovddup", { XM, EXymmq }, 0 },
3600 },
3601
3602 /* PREFIX_VEX_0F16 */
3603 {
3604 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3605 { "vmovshdup", { XM, EXx }, 0 },
3606 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3607 },
3608
3609 /* PREFIX_VEX_0F2A */
3610 {
3611 { Bad_Opcode },
3612 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3613 { Bad_Opcode },
3614 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3615 },
3616
3617 /* PREFIX_VEX_0F2C */
3618 {
3619 { Bad_Opcode },
3620 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3621 { Bad_Opcode },
3622 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3623 },
3624
3625 /* PREFIX_VEX_0F2D */
3626 {
3627 { Bad_Opcode },
3628 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3629 { Bad_Opcode },
3630 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3631 },
3632
3633 /* PREFIX_VEX_0F2E */
3634 {
3635 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3636 { Bad_Opcode },
3637 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3638 },
3639
3640 /* PREFIX_VEX_0F2F */
3641 {
3642 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3643 { Bad_Opcode },
3644 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3645 },
3646
3647 /* PREFIX_VEX_0F41 */
3648 {
3649 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3650 { Bad_Opcode },
3651 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3652 },
3653
3654 /* PREFIX_VEX_0F42 */
3655 {
3656 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3657 { Bad_Opcode },
3658 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3659 },
3660
3661 /* PREFIX_VEX_0F44 */
3662 {
3663 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3664 { Bad_Opcode },
3665 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3666 },
3667
3668 /* PREFIX_VEX_0F45 */
3669 {
3670 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3671 { Bad_Opcode },
3672 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3673 },
3674
3675 /* PREFIX_VEX_0F46 */
3676 {
3677 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3678 { Bad_Opcode },
3679 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3680 },
3681
3682 /* PREFIX_VEX_0F47 */
3683 {
3684 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3685 { Bad_Opcode },
3686 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3687 },
3688
3689 /* PREFIX_VEX_0F4A */
3690 {
3691 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3692 { Bad_Opcode },
3693 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3694 },
3695
3696 /* PREFIX_VEX_0F4B */
3697 {
3698 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3699 { Bad_Opcode },
3700 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3701 },
3702
3703 /* PREFIX_VEX_0F51 */
3704 {
3705 { "vsqrtps", { XM, EXx }, 0 },
3706 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3707 { "vsqrtpd", { XM, EXx }, 0 },
3708 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3709 },
3710
3711 /* PREFIX_VEX_0F52 */
3712 {
3713 { "vrsqrtps", { XM, EXx }, 0 },
3714 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3715 },
3716
3717 /* PREFIX_VEX_0F53 */
3718 {
3719 { "vrcpps", { XM, EXx }, 0 },
3720 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3721 },
3722
3723 /* PREFIX_VEX_0F58 */
3724 {
3725 { "vaddps", { XM, Vex, EXx }, 0 },
3726 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3727 { "vaddpd", { XM, Vex, EXx }, 0 },
3728 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3729 },
3730
3731 /* PREFIX_VEX_0F59 */
3732 {
3733 { "vmulps", { XM, Vex, EXx }, 0 },
3734 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3735 { "vmulpd", { XM, Vex, EXx }, 0 },
3736 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F5A */
3740 {
3741 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3742 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3743 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3744 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3745 },
3746
3747 /* PREFIX_VEX_0F5B */
3748 {
3749 { "vcvtdq2ps", { XM, EXx }, 0 },
3750 { "vcvttps2dq", { XM, EXx }, 0 },
3751 { "vcvtps2dq", { XM, EXx }, 0 },
3752 },
3753
3754 /* PREFIX_VEX_0F5C */
3755 {
3756 { "vsubps", { XM, Vex, EXx }, 0 },
3757 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3758 { "vsubpd", { XM, Vex, EXx }, 0 },
3759 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3760 },
3761
3762 /* PREFIX_VEX_0F5D */
3763 {
3764 { "vminps", { XM, Vex, EXx }, 0 },
3765 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3766 { "vminpd", { XM, Vex, EXx }, 0 },
3767 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3768 },
3769
3770 /* PREFIX_VEX_0F5E */
3771 {
3772 { "vdivps", { XM, Vex, EXx }, 0 },
3773 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3774 { "vdivpd", { XM, Vex, EXx }, 0 },
3775 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3776 },
3777
3778 /* PREFIX_VEX_0F5F */
3779 {
3780 { "vmaxps", { XM, Vex, EXx }, 0 },
3781 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3782 { "vmaxpd", { XM, Vex, EXx }, 0 },
3783 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3784 },
3785
3786 /* PREFIX_VEX_0F6F */
3787 {
3788 { Bad_Opcode },
3789 { "vmovdqu", { XM, EXx }, 0 },
3790 { "vmovdqa", { XM, EXx }, 0 },
3791 },
3792
3793 /* PREFIX_VEX_0F70 */
3794 {
3795 { Bad_Opcode },
3796 { "vpshufhw", { XM, EXx, Ib }, 0 },
3797 { "vpshufd", { XM, EXx, Ib }, 0 },
3798 { "vpshuflw", { XM, EXx, Ib }, 0 },
3799 },
3800
3801 /* PREFIX_VEX_0F7C */
3802 {
3803 { Bad_Opcode },
3804 { Bad_Opcode },
3805 { "vhaddpd", { XM, Vex, EXx }, 0 },
3806 { "vhaddps", { XM, Vex, EXx }, 0 },
3807 },
3808
3809 /* PREFIX_VEX_0F7D */
3810 {
3811 { Bad_Opcode },
3812 { Bad_Opcode },
3813 { "vhsubpd", { XM, Vex, EXx }, 0 },
3814 { "vhsubps", { XM, Vex, EXx }, 0 },
3815 },
3816
3817 /* PREFIX_VEX_0F7E */
3818 {
3819 { Bad_Opcode },
3820 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3821 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3822 },
3823
3824 /* PREFIX_VEX_0F7F */
3825 {
3826 { Bad_Opcode },
3827 { "vmovdqu", { EXxS, XM }, 0 },
3828 { "vmovdqa", { EXxS, XM }, 0 },
3829 },
3830
3831 /* PREFIX_VEX_0F90 */
3832 {
3833 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3834 { Bad_Opcode },
3835 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3836 },
3837
3838 /* PREFIX_VEX_0F91 */
3839 {
3840 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3841 { Bad_Opcode },
3842 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3843 },
3844
3845 /* PREFIX_VEX_0F92 */
3846 {
3847 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3848 { Bad_Opcode },
3849 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3850 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3851 },
3852
3853 /* PREFIX_VEX_0F93 */
3854 {
3855 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3856 { Bad_Opcode },
3857 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3858 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3859 },
3860
3861 /* PREFIX_VEX_0F98 */
3862 {
3863 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3864 { Bad_Opcode },
3865 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3866 },
3867
3868 /* PREFIX_VEX_0F99 */
3869 {
3870 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3871 { Bad_Opcode },
3872 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3873 },
3874
3875 /* PREFIX_VEX_0FC2 */
3876 {
3877 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3878 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3879 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3880 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3881 },
3882
3883 /* PREFIX_VEX_0FD0 */
3884 {
3885 { Bad_Opcode },
3886 { Bad_Opcode },
3887 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3888 { "vaddsubps", { XM, Vex, EXx }, 0 },
3889 },
3890
3891 /* PREFIX_VEX_0FE6 */
3892 {
3893 { Bad_Opcode },
3894 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3895 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3896 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3897 },
3898
3899 /* PREFIX_VEX_0FF0 */
3900 {
3901 { Bad_Opcode },
3902 { Bad_Opcode },
3903 { Bad_Opcode },
3904 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3905 },
3906
3907 /* PREFIX_VEX_0F3849_X86_64 */
3908 {
3909 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3910 { Bad_Opcode },
3911 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3912 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3913 },
3914
3915 /* PREFIX_VEX_0F384B_X86_64 */
3916 {
3917 { Bad_Opcode },
3918 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3919 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3920 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3921 },
3922
3923 /* PREFIX_VEX_0F385C_X86_64 */
3924 {
3925 { Bad_Opcode },
3926 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
3927 { Bad_Opcode },
3928 },
3929
3930 /* PREFIX_VEX_0F385E_X86_64 */
3931 {
3932 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
3933 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
3934 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
3935 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
3936 },
3937
3938 /* PREFIX_VEX_0F38F5 */
3939 {
3940 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
3941 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
3942 { Bad_Opcode },
3943 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
3944 },
3945
3946 /* PREFIX_VEX_0F38F6 */
3947 {
3948 { Bad_Opcode },
3949 { Bad_Opcode },
3950 { Bad_Opcode },
3951 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
3952 },
3953
3954 /* PREFIX_VEX_0F38F7 */
3955 {
3956 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
3957 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
3958 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
3959 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
3960 },
3961
3962 /* PREFIX_VEX_0F3AF0 */
3963 {
3964 { Bad_Opcode },
3965 { Bad_Opcode },
3966 { Bad_Opcode },
3967 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
3968 },
3969
3970 #include "i386-dis-evex-prefix.h"
3971 };
3972
3973 static const struct dis386 x86_64_table[][2] = {
3974 /* X86_64_06 */
3975 {
3976 { "pushP", { es }, 0 },
3977 },
3978
3979 /* X86_64_07 */
3980 {
3981 { "popP", { es }, 0 },
3982 },
3983
3984 /* X86_64_0E */
3985 {
3986 { "pushP", { cs }, 0 },
3987 },
3988
3989 /* X86_64_16 */
3990 {
3991 { "pushP", { ss }, 0 },
3992 },
3993
3994 /* X86_64_17 */
3995 {
3996 { "popP", { ss }, 0 },
3997 },
3998
3999 /* X86_64_1E */
4000 {
4001 { "pushP", { ds }, 0 },
4002 },
4003
4004 /* X86_64_1F */
4005 {
4006 { "popP", { ds }, 0 },
4007 },
4008
4009 /* X86_64_27 */
4010 {
4011 { "daa", { XX }, 0 },
4012 },
4013
4014 /* X86_64_2F */
4015 {
4016 { "das", { XX }, 0 },
4017 },
4018
4019 /* X86_64_37 */
4020 {
4021 { "aaa", { XX }, 0 },
4022 },
4023
4024 /* X86_64_3F */
4025 {
4026 { "aas", { XX }, 0 },
4027 },
4028
4029 /* X86_64_60 */
4030 {
4031 { "pushaP", { XX }, 0 },
4032 },
4033
4034 /* X86_64_61 */
4035 {
4036 { "popaP", { XX }, 0 },
4037 },
4038
4039 /* X86_64_62 */
4040 {
4041 { MOD_TABLE (MOD_62_32BIT) },
4042 { EVEX_TABLE (EVEX_0F) },
4043 },
4044
4045 /* X86_64_63 */
4046 {
4047 { "arpl", { Ew, Gw }, 0 },
4048 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4049 },
4050
4051 /* X86_64_6D */
4052 {
4053 { "ins{R|}", { Yzr, indirDX }, 0 },
4054 { "ins{G|}", { Yzr, indirDX }, 0 },
4055 },
4056
4057 /* X86_64_6F */
4058 {
4059 { "outs{R|}", { indirDXr, Xz }, 0 },
4060 { "outs{G|}", { indirDXr, Xz }, 0 },
4061 },
4062
4063 /* X86_64_82 */
4064 {
4065 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4066 { REG_TABLE (REG_80) },
4067 },
4068
4069 /* X86_64_9A */
4070 {
4071 { "{l|}call{P|}", { Ap }, 0 },
4072 },
4073
4074 /* X86_64_C2 */
4075 {
4076 { "retP", { Iw, BND }, 0 },
4077 { "ret@", { Iw, BND }, 0 },
4078 },
4079
4080 /* X86_64_C3 */
4081 {
4082 { "retP", { BND }, 0 },
4083 { "ret@", { BND }, 0 },
4084 },
4085
4086 /* X86_64_C4 */
4087 {
4088 { MOD_TABLE (MOD_C4_32BIT) },
4089 { VEX_C4_TABLE (VEX_0F) },
4090 },
4091
4092 /* X86_64_C5 */
4093 {
4094 { MOD_TABLE (MOD_C5_32BIT) },
4095 { VEX_C5_TABLE (VEX_0F) },
4096 },
4097
4098 /* X86_64_CE */
4099 {
4100 { "into", { XX }, 0 },
4101 },
4102
4103 /* X86_64_D4 */
4104 {
4105 { "aam", { Ib }, 0 },
4106 },
4107
4108 /* X86_64_D5 */
4109 {
4110 { "aad", { Ib }, 0 },
4111 },
4112
4113 /* X86_64_E8 */
4114 {
4115 { "callP", { Jv, BND }, 0 },
4116 { "call@", { Jv, BND }, 0 }
4117 },
4118
4119 /* X86_64_E9 */
4120 {
4121 { "jmpP", { Jv, BND }, 0 },
4122 { "jmp@", { Jv, BND }, 0 }
4123 },
4124
4125 /* X86_64_EA */
4126 {
4127 { "{l|}jmp{P|}", { Ap }, 0 },
4128 },
4129
4130 /* X86_64_0F01_REG_0 */
4131 {
4132 { "sgdt{Q|Q}", { M }, 0 },
4133 { "sgdt", { M }, 0 },
4134 },
4135
4136 /* X86_64_0F01_REG_1 */
4137 {
4138 { "sidt{Q|Q}", { M }, 0 },
4139 { "sidt", { M }, 0 },
4140 },
4141
4142 /* X86_64_0F01_REG_2 */
4143 {
4144 { "lgdt{Q|Q}", { M }, 0 },
4145 { "lgdt", { M }, 0 },
4146 },
4147
4148 /* X86_64_0F01_REG_3 */
4149 {
4150 { "lidt{Q|Q}", { M }, 0 },
4151 { "lidt", { M }, 0 },
4152 },
4153
4154 {
4155 /* X86_64_0F24 */
4156 { "movZ", { Em, Td }, 0 },
4157 },
4158
4159 {
4160 /* X86_64_0F26 */
4161 { "movZ", { Td, Em }, 0 },
4162 },
4163
4164 /* X86_64_VEX_0F3849 */
4165 {
4166 { Bad_Opcode },
4167 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4168 },
4169
4170 /* X86_64_VEX_0F384B */
4171 {
4172 { Bad_Opcode },
4173 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4174 },
4175
4176 /* X86_64_VEX_0F385C */
4177 {
4178 { Bad_Opcode },
4179 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4180 },
4181
4182 /* X86_64_VEX_0F385E */
4183 {
4184 { Bad_Opcode },
4185 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4186 },
4187 };
4188
4189 static const struct dis386 three_byte_table[][256] = {
4190
4191 /* THREE_BYTE_0F38 */
4192 {
4193 /* 00 */
4194 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4195 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4196 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4197 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4198 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4199 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4200 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4201 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4202 /* 08 */
4203 { "psignb", { MX, EM }, PREFIX_OPCODE },
4204 { "psignw", { MX, EM }, PREFIX_OPCODE },
4205 { "psignd", { MX, EM }, PREFIX_OPCODE },
4206 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4207 { Bad_Opcode },
4208 { Bad_Opcode },
4209 { Bad_Opcode },
4210 { Bad_Opcode },
4211 /* 10 */
4212 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4213 { Bad_Opcode },
4214 { Bad_Opcode },
4215 { Bad_Opcode },
4216 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4217 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4218 { Bad_Opcode },
4219 { "ptest", { XM, EXx }, PREFIX_DATA },
4220 /* 18 */
4221 { Bad_Opcode },
4222 { Bad_Opcode },
4223 { Bad_Opcode },
4224 { Bad_Opcode },
4225 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4226 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4227 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4228 { Bad_Opcode },
4229 /* 20 */
4230 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4231 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4232 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4233 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4234 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4235 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4236 { Bad_Opcode },
4237 { Bad_Opcode },
4238 /* 28 */
4239 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4240 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4241 { MOD_TABLE (MOD_0F382A) },
4242 { "packusdw", { XM, EXx }, PREFIX_DATA },
4243 { Bad_Opcode },
4244 { Bad_Opcode },
4245 { Bad_Opcode },
4246 { Bad_Opcode },
4247 /* 30 */
4248 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4249 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4250 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4251 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4252 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4253 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4254 { Bad_Opcode },
4255 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4256 /* 38 */
4257 { "pminsb", { XM, EXx }, PREFIX_DATA },
4258 { "pminsd", { XM, EXx }, PREFIX_DATA },
4259 { "pminuw", { XM, EXx }, PREFIX_DATA },
4260 { "pminud", { XM, EXx }, PREFIX_DATA },
4261 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4262 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4263 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4264 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4265 /* 40 */
4266 { "pmulld", { XM, EXx }, PREFIX_DATA },
4267 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4268 { Bad_Opcode },
4269 { Bad_Opcode },
4270 { Bad_Opcode },
4271 { Bad_Opcode },
4272 { Bad_Opcode },
4273 { Bad_Opcode },
4274 /* 48 */
4275 { Bad_Opcode },
4276 { Bad_Opcode },
4277 { Bad_Opcode },
4278 { Bad_Opcode },
4279 { Bad_Opcode },
4280 { Bad_Opcode },
4281 { Bad_Opcode },
4282 { Bad_Opcode },
4283 /* 50 */
4284 { Bad_Opcode },
4285 { Bad_Opcode },
4286 { Bad_Opcode },
4287 { Bad_Opcode },
4288 { Bad_Opcode },
4289 { Bad_Opcode },
4290 { Bad_Opcode },
4291 { Bad_Opcode },
4292 /* 58 */
4293 { Bad_Opcode },
4294 { Bad_Opcode },
4295 { Bad_Opcode },
4296 { Bad_Opcode },
4297 { Bad_Opcode },
4298 { Bad_Opcode },
4299 { Bad_Opcode },
4300 { Bad_Opcode },
4301 /* 60 */
4302 { Bad_Opcode },
4303 { Bad_Opcode },
4304 { Bad_Opcode },
4305 { Bad_Opcode },
4306 { Bad_Opcode },
4307 { Bad_Opcode },
4308 { Bad_Opcode },
4309 { Bad_Opcode },
4310 /* 68 */
4311 { Bad_Opcode },
4312 { Bad_Opcode },
4313 { Bad_Opcode },
4314 { Bad_Opcode },
4315 { Bad_Opcode },
4316 { Bad_Opcode },
4317 { Bad_Opcode },
4318 { Bad_Opcode },
4319 /* 70 */
4320 { Bad_Opcode },
4321 { Bad_Opcode },
4322 { Bad_Opcode },
4323 { Bad_Opcode },
4324 { Bad_Opcode },
4325 { Bad_Opcode },
4326 { Bad_Opcode },
4327 { Bad_Opcode },
4328 /* 78 */
4329 { Bad_Opcode },
4330 { Bad_Opcode },
4331 { Bad_Opcode },
4332 { Bad_Opcode },
4333 { Bad_Opcode },
4334 { Bad_Opcode },
4335 { Bad_Opcode },
4336 { Bad_Opcode },
4337 /* 80 */
4338 { "invept", { Gm, Mo }, PREFIX_DATA },
4339 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4340 { "invpcid", { Gm, M }, PREFIX_DATA },
4341 { Bad_Opcode },
4342 { Bad_Opcode },
4343 { Bad_Opcode },
4344 { Bad_Opcode },
4345 { Bad_Opcode },
4346 /* 88 */
4347 { Bad_Opcode },
4348 { Bad_Opcode },
4349 { Bad_Opcode },
4350 { Bad_Opcode },
4351 { Bad_Opcode },
4352 { Bad_Opcode },
4353 { Bad_Opcode },
4354 { Bad_Opcode },
4355 /* 90 */
4356 { Bad_Opcode },
4357 { Bad_Opcode },
4358 { Bad_Opcode },
4359 { Bad_Opcode },
4360 { Bad_Opcode },
4361 { Bad_Opcode },
4362 { Bad_Opcode },
4363 { Bad_Opcode },
4364 /* 98 */
4365 { Bad_Opcode },
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 { Bad_Opcode },
4369 { Bad_Opcode },
4370 { Bad_Opcode },
4371 { Bad_Opcode },
4372 { Bad_Opcode },
4373 /* a0 */
4374 { Bad_Opcode },
4375 { Bad_Opcode },
4376 { Bad_Opcode },
4377 { Bad_Opcode },
4378 { Bad_Opcode },
4379 { Bad_Opcode },
4380 { Bad_Opcode },
4381 { Bad_Opcode },
4382 /* a8 */
4383 { Bad_Opcode },
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 { Bad_Opcode },
4387 { Bad_Opcode },
4388 { Bad_Opcode },
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 /* b0 */
4392 { Bad_Opcode },
4393 { Bad_Opcode },
4394 { Bad_Opcode },
4395 { Bad_Opcode },
4396 { Bad_Opcode },
4397 { Bad_Opcode },
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 /* b8 */
4401 { Bad_Opcode },
4402 { Bad_Opcode },
4403 { Bad_Opcode },
4404 { Bad_Opcode },
4405 { Bad_Opcode },
4406 { Bad_Opcode },
4407 { Bad_Opcode },
4408 { Bad_Opcode },
4409 /* c0 */
4410 { Bad_Opcode },
4411 { Bad_Opcode },
4412 { Bad_Opcode },
4413 { Bad_Opcode },
4414 { Bad_Opcode },
4415 { Bad_Opcode },
4416 { Bad_Opcode },
4417 { Bad_Opcode },
4418 /* c8 */
4419 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4420 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4421 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4422 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4423 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4424 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4425 { Bad_Opcode },
4426 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4427 /* d0 */
4428 { Bad_Opcode },
4429 { Bad_Opcode },
4430 { Bad_Opcode },
4431 { Bad_Opcode },
4432 { Bad_Opcode },
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { Bad_Opcode },
4436 /* d8 */
4437 { Bad_Opcode },
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { "aesimc", { XM, EXx }, PREFIX_DATA },
4441 { "aesenc", { XM, EXx }, PREFIX_DATA },
4442 { "aesenclast", { XM, EXx }, PREFIX_DATA },
4443 { "aesdec", { XM, EXx }, PREFIX_DATA },
4444 { "aesdeclast", { XM, EXx }, PREFIX_DATA },
4445 /* e0 */
4446 { Bad_Opcode },
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 /* e8 */
4455 { Bad_Opcode },
4456 { Bad_Opcode },
4457 { Bad_Opcode },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 /* f0 */
4464 { PREFIX_TABLE (PREFIX_0F38F0) },
4465 { PREFIX_TABLE (PREFIX_0F38F1) },
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 { MOD_TABLE (MOD_0F38F5) },
4470 { PREFIX_TABLE (PREFIX_0F38F6) },
4471 { Bad_Opcode },
4472 /* f8 */
4473 { PREFIX_TABLE (PREFIX_0F38F8) },
4474 { MOD_TABLE (MOD_0F38F9) },
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 },
4482 /* THREE_BYTE_0F3A */
4483 {
4484 /* 00 */
4485 { Bad_Opcode },
4486 { Bad_Opcode },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { Bad_Opcode },
4492 { Bad_Opcode },
4493 /* 08 */
4494 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4495 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4496 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4497 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4498 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4499 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4500 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4501 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4502 /* 10 */
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4508 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4509 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4510 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4511 /* 18 */
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 /* 20 */
4521 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4522 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4523 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 /* 28 */
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 /* 30 */
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 /* 38 */
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 /* 40 */
4557 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4558 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4559 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4560 { Bad_Opcode },
4561 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 /* 48 */
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 /* 50 */
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 /* 58 */
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 /* 60 */
4593 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4594 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4595 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4596 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 /* 68 */
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 /* 70 */
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 /* 78 */
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 /* 80 */
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 /* 88 */
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 /* 90 */
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 /* 98 */
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 /* a0 */
4665 { Bad_Opcode },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 /* a8 */
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 /* b0 */
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 /* b8 */
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 /* c0 */
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 /* c8 */
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4715 { Bad_Opcode },
4716 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4717 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4718 /* d0 */
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 /* d8 */
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4736 /* e0 */
4737 { Bad_Opcode },
4738 { Bad_Opcode },
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 /* e8 */
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 /* f0 */
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 /* f8 */
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 },
4773 };
4774
4775 static const struct dis386 xop_table[][256] = {
4776 /* XOP_08 */
4777 {
4778 /* 00 */
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 /* 08 */
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 /* 10 */
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 /* 18 */
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 /* 20 */
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 /* 28 */
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 /* 30 */
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 /* 38 */
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 /* 40 */
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 /* 48 */
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 /* 50 */
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 /* 58 */
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 /* 60 */
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 /* 68 */
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 /* 70 */
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 /* 78 */
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 /* 80 */
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
4929 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
4930 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
4931 /* 88 */
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
4939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
4940 /* 90 */
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
4947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
4948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
4949 /* 98 */
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
4957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
4958 /* a0 */
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
4962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
4966 { Bad_Opcode },
4967 /* a8 */
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 /* b0 */
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
4984 { Bad_Opcode },
4985 /* b8 */
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 /* c0 */
4995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
4996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
4997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
4998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 /* c8 */
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5009 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5010 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5011 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5012 /* d0 */
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 /* d8 */
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 /* e0 */
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 /* e8 */
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5046 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5048 /* f0 */
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 /* f8 */
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 },
5067 /* XOP_09 */
5068 {
5069 /* 00 */
5070 { Bad_Opcode },
5071 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5072 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 /* 08 */
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 /* 10 */
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 /* 18 */
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 /* 20 */
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 /* 28 */
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 /* 30 */
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 /* 38 */
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 /* 40 */
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 /* 48 */
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 /* 50 */
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 /* 58 */
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 /* 60 */
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 /* 68 */
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 /* 70 */
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 /* 78 */
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 /* 80 */
5214 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5215 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5216 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5217 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 /* 88 */
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 /* 90 */
5232 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5233 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5234 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5235 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5240 /* 98 */
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5243 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5244 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 /* a0 */
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 /* a8 */
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 /* b0 */
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 /* b8 */
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 /* c0 */
5286 { Bad_Opcode },
5287 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5293 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5294 /* c8 */
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 /* d0 */
5304 { Bad_Opcode },
5305 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5306 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5307 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5312 /* d8 */
5313 { Bad_Opcode },
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 /* e0 */
5322 { Bad_Opcode },
5323 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5324 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5325 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 /* e8 */
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 /* f0 */
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 /* f8 */
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 },
5358 /* XOP_0A */
5359 {
5360 /* 00 */
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 /* 08 */
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 /* 10 */
5379 { "bextrS", { Gdq, Edq, Id }, 0 },
5380 { Bad_Opcode },
5381 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 /* 18 */
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 /* 20 */
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 /* 28 */
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 /* 30 */
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 /* 38 */
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 /* 40 */
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 /* 48 */
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 /* 50 */
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 /* 58 */
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 /* 60 */
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 /* 68 */
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 /* 70 */
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 /* 78 */
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 /* 80 */
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 /* 88 */
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 /* 90 */
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 /* 98 */
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 /* a0 */
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 /* a8 */
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 /* b0 */
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 /* b8 */
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 /* c0 */
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 /* c8 */
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 /* d0 */
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 /* d8 */
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 /* e0 */
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 /* e8 */
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 /* f0 */
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 /* f8 */
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 },
5649 };
5650
5651 static const struct dis386 vex_table[][256] = {
5652 /* VEX_0F */
5653 {
5654 /* 00 */
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 /* 08 */
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 /* 10 */
5673 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5674 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5675 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5676 { MOD_TABLE (MOD_VEX_0F13) },
5677 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5678 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5679 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5680 { MOD_TABLE (MOD_VEX_0F17) },
5681 /* 18 */
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 /* 20 */
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 /* 28 */
5700 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5701 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5702 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5703 { MOD_TABLE (MOD_VEX_0F2B) },
5704 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5705 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5706 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5707 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5708 /* 30 */
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 /* 38 */
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 /* 40 */
5727 { Bad_Opcode },
5728 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5729 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5730 { Bad_Opcode },
5731 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5732 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5733 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5734 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5735 /* 48 */
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5739 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 /* 50 */
5745 { MOD_TABLE (MOD_VEX_0F50) },
5746 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5747 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5748 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5749 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5750 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5751 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5752 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5753 /* 58 */
5754 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5755 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5756 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5757 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5758 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5759 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5760 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5761 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5762 /* 60 */
5763 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5764 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5765 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5766 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5767 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5768 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5769 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5770 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5771 /* 68 */
5772 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5773 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5774 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5775 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5776 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5777 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5778 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5779 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5780 /* 70 */
5781 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5782 { REG_TABLE (REG_VEX_0F71) },
5783 { REG_TABLE (REG_VEX_0F72) },
5784 { REG_TABLE (REG_VEX_0F73) },
5785 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5786 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5787 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5788 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5789 /* 78 */
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5795 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5796 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5797 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5798 /* 80 */
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 /* 88 */
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 /* 90 */
5817 { PREFIX_TABLE (PREFIX_VEX_0F90) },
5818 { PREFIX_TABLE (PREFIX_VEX_0F91) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F92) },
5820 { PREFIX_TABLE (PREFIX_VEX_0F93) },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 /* 98 */
5826 { PREFIX_TABLE (PREFIX_VEX_0F98) },
5827 { PREFIX_TABLE (PREFIX_VEX_0F99) },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 /* a0 */
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 /* a8 */
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { REG_TABLE (REG_VEX_0FAE) },
5851 { Bad_Opcode },
5852 /* b0 */
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 /* b8 */
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 /* c0 */
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5874 { Bad_Opcode },
5875 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5876 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5877 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5878 { Bad_Opcode },
5879 /* c8 */
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 /* d0 */
5889 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5890 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
5891 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
5892 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
5893 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
5894 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
5895 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5896 { MOD_TABLE (MOD_VEX_0FD7) },
5897 /* d8 */
5898 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
5899 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
5900 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
5901 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
5902 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
5903 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
5904 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
5905 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
5906 /* e0 */
5907 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
5908 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
5909 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
5910 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
5911 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
5912 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
5913 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
5914 { MOD_TABLE (MOD_VEX_0FE7) },
5915 /* e8 */
5916 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
5917 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5918 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
5919 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
5920 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
5921 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5922 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
5923 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
5924 /* f0 */
5925 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
5926 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
5927 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
5928 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
5929 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
5930 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
5931 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
5932 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
5933 /* f8 */
5934 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
5935 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
5936 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
5937 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
5938 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
5939 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
5940 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
5941 { Bad_Opcode },
5942 },
5943 /* VEX_0F38 */
5944 {
5945 /* 00 */
5946 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
5947 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
5948 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
5949 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5950 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
5951 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
5952 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
5953 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5954 /* 08 */
5955 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
5956 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
5957 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
5958 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
5959 { VEX_W_TABLE (VEX_W_0F380C) },
5960 { VEX_W_TABLE (VEX_W_0F380D) },
5961 { VEX_W_TABLE (VEX_W_0F380E) },
5962 { VEX_W_TABLE (VEX_W_0F380F) },
5963 /* 10 */
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { VEX_W_TABLE (VEX_W_0F3813) },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
5971 { "vptest", { XM, EXx }, PREFIX_DATA },
5972 /* 18 */
5973 { VEX_W_TABLE (VEX_W_0F3818) },
5974 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
5975 { MOD_TABLE (MOD_VEX_0F381A) },
5976 { Bad_Opcode },
5977 { "vpabsb", { XM, EXx }, PREFIX_DATA },
5978 { "vpabsw", { XM, EXx }, PREFIX_DATA },
5979 { "vpabsd", { XM, EXx }, PREFIX_DATA },
5980 { Bad_Opcode },
5981 /* 20 */
5982 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
5983 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
5984 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
5985 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
5986 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
5987 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 /* 28 */
5991 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
5992 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
5993 { MOD_TABLE (MOD_VEX_0F382A) },
5994 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
5995 { MOD_TABLE (MOD_VEX_0F382C) },
5996 { MOD_TABLE (MOD_VEX_0F382D) },
5997 { MOD_TABLE (MOD_VEX_0F382E) },
5998 { MOD_TABLE (MOD_VEX_0F382F) },
5999 /* 30 */
6000 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6001 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6002 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6003 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6004 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6005 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6006 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6007 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6008 /* 38 */
6009 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6010 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6011 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6012 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6013 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6015 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6016 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6017 /* 40 */
6018 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6019 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 { Bad_Opcode },
6023 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6024 { VEX_W_TABLE (VEX_W_0F3846) },
6025 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6026 /* 48 */
6027 { Bad_Opcode },
6028 { X86_64_TABLE (X86_64_VEX_0F3849) },
6029 { Bad_Opcode },
6030 { X86_64_TABLE (X86_64_VEX_0F384B) },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 /* 50 */
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 /* 58 */
6045 { VEX_W_TABLE (VEX_W_0F3858) },
6046 { VEX_W_TABLE (VEX_W_0F3859) },
6047 { MOD_TABLE (MOD_VEX_0F385A) },
6048 { Bad_Opcode },
6049 { X86_64_TABLE (X86_64_VEX_0F385C) },
6050 { Bad_Opcode },
6051 { X86_64_TABLE (X86_64_VEX_0F385E) },
6052 { Bad_Opcode },
6053 /* 60 */
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 /* 68 */
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 /* 70 */
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 /* 78 */
6081 { VEX_W_TABLE (VEX_W_0F3878) },
6082 { VEX_W_TABLE (VEX_W_0F3879) },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 /* 80 */
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 /* 88 */
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { MOD_TABLE (MOD_VEX_0F388C) },
6104 { Bad_Opcode },
6105 { MOD_TABLE (MOD_VEX_0F388E) },
6106 { Bad_Opcode },
6107 /* 90 */
6108 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6109 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6110 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6111 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6115 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6116 /* 98 */
6117 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6118 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6119 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6120 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6121 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6122 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6123 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6124 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6125 /* a0 */
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6133 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6134 /* a8 */
6135 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6136 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6137 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6138 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6139 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6141 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6142 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6143 /* b0 */
6144 { Bad_Opcode },
6145 { Bad_Opcode },
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6151 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6152 /* b8 */
6153 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6154 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6155 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6156 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6157 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6159 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6161 /* c0 */
6162 { Bad_Opcode },
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 /* c8 */
6171 { Bad_Opcode },
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { VEX_W_TABLE (VEX_W_0F38CF) },
6179 /* d0 */
6180 { Bad_Opcode },
6181 { Bad_Opcode },
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 /* d8 */
6189 { Bad_Opcode },
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6193 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6194 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6197 /* e0 */
6198 { Bad_Opcode },
6199 { Bad_Opcode },
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 /* e8 */
6207 { Bad_Opcode },
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 /* f0 */
6216 { Bad_Opcode },
6217 { Bad_Opcode },
6218 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6219 { REG_TABLE (REG_VEX_0F38F3) },
6220 { Bad_Opcode },
6221 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6222 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6223 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6224 /* f8 */
6225 { Bad_Opcode },
6226 { Bad_Opcode },
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 },
6234 /* VEX_0F3A */
6235 {
6236 /* 00 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6239 { VEX_W_TABLE (VEX_W_0F3A02) },
6240 { Bad_Opcode },
6241 { VEX_W_TABLE (VEX_W_0F3A04) },
6242 { VEX_W_TABLE (VEX_W_0F3A05) },
6243 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6244 { Bad_Opcode },
6245 /* 08 */
6246 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6247 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6248 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6249 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6250 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6251 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6252 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6253 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6254 /* 10 */
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6260 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6261 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6262 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6263 /* 18 */
6264 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { VEX_W_TABLE (VEX_W_0F3A1D) },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 /* 20 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6275 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 { Bad_Opcode },
6281 /* 28 */
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 /* 30 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 /* 38 */
6300 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6301 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 /* 40 */
6309 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6310 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6311 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6312 { Bad_Opcode },
6313 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6314 { Bad_Opcode },
6315 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6316 { Bad_Opcode },
6317 /* 48 */
6318 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6319 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6320 { VEX_W_TABLE (VEX_W_0F3A4A) },
6321 { VEX_W_TABLE (VEX_W_0F3A4B) },
6322 { VEX_W_TABLE (VEX_W_0F3A4C) },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 /* 50 */
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 /* 58 */
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6341 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6342 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6343 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6344 /* 60 */
6345 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6346 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6349 { Bad_Opcode },
6350 { Bad_Opcode },
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 /* 68 */
6354 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6355 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6356 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6357 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6358 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6359 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6360 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6361 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6362 /* 70 */
6363 { Bad_Opcode },
6364 { Bad_Opcode },
6365 { Bad_Opcode },
6366 { Bad_Opcode },
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 /* 78 */
6372 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6373 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6374 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6375 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6376 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6377 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6378 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6379 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6380 /* 80 */
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 /* 88 */
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 /* 90 */
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 /* 98 */
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 /* a0 */
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 /* a8 */
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 /* b0 */
6435 { Bad_Opcode },
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 /* b8 */
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 /* c0 */
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 /* c8 */
6462 { Bad_Opcode },
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { VEX_W_TABLE (VEX_W_0F3ACE) },
6469 { VEX_W_TABLE (VEX_W_0F3ACF) },
6470 /* d0 */
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 /* d8 */
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6488 /* e0 */
6489 { Bad_Opcode },
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 /* e8 */
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 /* f0 */
6507 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 /* f8 */
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 },
6525 };
6526
6527 #include "i386-dis-evex.h"
6528
6529 static const struct dis386 vex_len_table[][2] = {
6530 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6531 {
6532 { "vmovlpX", { XM, Vex, EXq }, 0 },
6533 },
6534
6535 /* VEX_LEN_0F12_P_0_M_1 */
6536 {
6537 { "vmovhlps", { XM, Vex, EXq }, 0 },
6538 },
6539
6540 /* VEX_LEN_0F13_M_0 */
6541 {
6542 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6543 },
6544
6545 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6546 {
6547 { "vmovhpX", { XM, Vex, EXq }, 0 },
6548 },
6549
6550 /* VEX_LEN_0F16_P_0_M_1 */
6551 {
6552 { "vmovlhps", { XM, Vex, EXq }, 0 },
6553 },
6554
6555 /* VEX_LEN_0F17_M_0 */
6556 {
6557 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6558 },
6559
6560 /* VEX_LEN_0F41_P_0 */
6561 {
6562 { Bad_Opcode },
6563 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6564 },
6565 /* VEX_LEN_0F41_P_2 */
6566 {
6567 { Bad_Opcode },
6568 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6569 },
6570 /* VEX_LEN_0F42_P_0 */
6571 {
6572 { Bad_Opcode },
6573 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6574 },
6575 /* VEX_LEN_0F42_P_2 */
6576 {
6577 { Bad_Opcode },
6578 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6579 },
6580 /* VEX_LEN_0F44_P_0 */
6581 {
6582 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6583 },
6584 /* VEX_LEN_0F44_P_2 */
6585 {
6586 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6587 },
6588 /* VEX_LEN_0F45_P_0 */
6589 {
6590 { Bad_Opcode },
6591 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6592 },
6593 /* VEX_LEN_0F45_P_2 */
6594 {
6595 { Bad_Opcode },
6596 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6597 },
6598 /* VEX_LEN_0F46_P_0 */
6599 {
6600 { Bad_Opcode },
6601 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6602 },
6603 /* VEX_LEN_0F46_P_2 */
6604 {
6605 { Bad_Opcode },
6606 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6607 },
6608 /* VEX_LEN_0F47_P_0 */
6609 {
6610 { Bad_Opcode },
6611 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6612 },
6613 /* VEX_LEN_0F47_P_2 */
6614 {
6615 { Bad_Opcode },
6616 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6617 },
6618 /* VEX_LEN_0F4A_P_0 */
6619 {
6620 { Bad_Opcode },
6621 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6622 },
6623 /* VEX_LEN_0F4A_P_2 */
6624 {
6625 { Bad_Opcode },
6626 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6627 },
6628 /* VEX_LEN_0F4B_P_0 */
6629 {
6630 { Bad_Opcode },
6631 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6632 },
6633 /* VEX_LEN_0F4B_P_2 */
6634 {
6635 { Bad_Opcode },
6636 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6637 },
6638
6639 /* VEX_LEN_0F6E */
6640 {
6641 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6642 },
6643
6644 /* VEX_LEN_0F77 */
6645 {
6646 { "vzeroupper", { XX }, 0 },
6647 { "vzeroall", { XX }, 0 },
6648 },
6649
6650 /* VEX_LEN_0F7E_P_1 */
6651 {
6652 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6653 },
6654
6655 /* VEX_LEN_0F7E_P_2 */
6656 {
6657 { "vmovK", { Edq, XMScalar }, 0 },
6658 },
6659
6660 /* VEX_LEN_0F90_P_0 */
6661 {
6662 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6663 },
6664
6665 /* VEX_LEN_0F90_P_2 */
6666 {
6667 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6668 },
6669
6670 /* VEX_LEN_0F91_P_0 */
6671 {
6672 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6673 },
6674
6675 /* VEX_LEN_0F91_P_2 */
6676 {
6677 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6678 },
6679
6680 /* VEX_LEN_0F92_P_0 */
6681 {
6682 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6683 },
6684
6685 /* VEX_LEN_0F92_P_2 */
6686 {
6687 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6688 },
6689
6690 /* VEX_LEN_0F92_P_3 */
6691 {
6692 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6693 },
6694
6695 /* VEX_LEN_0F93_P_0 */
6696 {
6697 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6698 },
6699
6700 /* VEX_LEN_0F93_P_2 */
6701 {
6702 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6703 },
6704
6705 /* VEX_LEN_0F93_P_3 */
6706 {
6707 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6708 },
6709
6710 /* VEX_LEN_0F98_P_0 */
6711 {
6712 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6713 },
6714
6715 /* VEX_LEN_0F98_P_2 */
6716 {
6717 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6718 },
6719
6720 /* VEX_LEN_0F99_P_0 */
6721 {
6722 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6723 },
6724
6725 /* VEX_LEN_0F99_P_2 */
6726 {
6727 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6728 },
6729
6730 /* VEX_LEN_0FAE_R_2_M_0 */
6731 {
6732 { "vldmxcsr", { Md }, 0 },
6733 },
6734
6735 /* VEX_LEN_0FAE_R_3_M_0 */
6736 {
6737 { "vstmxcsr", { Md }, 0 },
6738 },
6739
6740 /* VEX_LEN_0FC4 */
6741 {
6742 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6743 },
6744
6745 /* VEX_LEN_0FC5 */
6746 {
6747 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6748 },
6749
6750 /* VEX_LEN_0FD6 */
6751 {
6752 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6753 },
6754
6755 /* VEX_LEN_0FF7 */
6756 {
6757 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6758 },
6759
6760 /* VEX_LEN_0F3816 */
6761 {
6762 { Bad_Opcode },
6763 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6764 },
6765
6766 /* VEX_LEN_0F3819 */
6767 {
6768 { Bad_Opcode },
6769 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6770 },
6771
6772 /* VEX_LEN_0F381A_M_0 */
6773 {
6774 { Bad_Opcode },
6775 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6776 },
6777
6778 /* VEX_LEN_0F3836 */
6779 {
6780 { Bad_Opcode },
6781 { VEX_W_TABLE (VEX_W_0F3836) },
6782 },
6783
6784 /* VEX_LEN_0F3841 */
6785 {
6786 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6787 },
6788
6789 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6790 {
6791 { "ldtilecfg", { M }, 0 },
6792 },
6793
6794 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6795 {
6796 { "tilerelease", { Skip_MODRM }, 0 },
6797 },
6798
6799 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6800 {
6801 { "sttilecfg", { M }, 0 },
6802 },
6803
6804 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6805 {
6806 { "tilezero", { TMM, Skip_MODRM }, 0 },
6807 },
6808
6809 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6810 {
6811 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6812 },
6813 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6814 {
6815 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6816 },
6817
6818 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6819 {
6820 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6821 },
6822
6823 /* VEX_LEN_0F385A_M_0 */
6824 {
6825 { Bad_Opcode },
6826 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6827 },
6828
6829 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6830 {
6831 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6832 },
6833
6834 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6835 {
6836 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6837 },
6838
6839 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6840 {
6841 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6842 },
6843
6844 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6845 {
6846 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6847 },
6848
6849 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6850 {
6851 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6852 },
6853
6854 /* VEX_LEN_0F38DB */
6855 {
6856 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6857 },
6858
6859 /* VEX_LEN_0F38F2 */
6860 {
6861 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6862 },
6863
6864 /* VEX_LEN_0F38F3_R_1 */
6865 {
6866 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
6867 },
6868
6869 /* VEX_LEN_0F38F3_R_2 */
6870 {
6871 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
6872 },
6873
6874 /* VEX_LEN_0F38F3_R_3 */
6875 {
6876 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
6877 },
6878
6879 /* VEX_LEN_0F38F5_P_0 */
6880 {
6881 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
6882 },
6883
6884 /* VEX_LEN_0F38F5_P_1 */
6885 {
6886 { "pextS", { Gdq, VexGdq, Edq }, 0 },
6887 },
6888
6889 /* VEX_LEN_0F38F5_P_3 */
6890 {
6891 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
6892 },
6893
6894 /* VEX_LEN_0F38F6_P_3 */
6895 {
6896 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
6897 },
6898
6899 /* VEX_LEN_0F38F7_P_0 */
6900 {
6901 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
6902 },
6903
6904 /* VEX_LEN_0F38F7_P_1 */
6905 {
6906 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
6907 },
6908
6909 /* VEX_LEN_0F38F7_P_2 */
6910 {
6911 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
6912 },
6913
6914 /* VEX_LEN_0F38F7_P_3 */
6915 {
6916 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
6917 },
6918
6919 /* VEX_LEN_0F3A00 */
6920 {
6921 { Bad_Opcode },
6922 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6923 },
6924
6925 /* VEX_LEN_0F3A01 */
6926 {
6927 { Bad_Opcode },
6928 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6929 },
6930
6931 /* VEX_LEN_0F3A06 */
6932 {
6933 { Bad_Opcode },
6934 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6935 },
6936
6937 /* VEX_LEN_0F3A14 */
6938 {
6939 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
6940 },
6941
6942 /* VEX_LEN_0F3A15 */
6943 {
6944 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
6945 },
6946
6947 /* VEX_LEN_0F3A16 */
6948 {
6949 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
6950 },
6951
6952 /* VEX_LEN_0F3A17 */
6953 {
6954 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
6955 },
6956
6957 /* VEX_LEN_0F3A18 */
6958 {
6959 { Bad_Opcode },
6960 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6961 },
6962
6963 /* VEX_LEN_0F3A19 */
6964 {
6965 { Bad_Opcode },
6966 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
6967 },
6968
6969 /* VEX_LEN_0F3A20 */
6970 {
6971 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
6972 },
6973
6974 /* VEX_LEN_0F3A21 */
6975 {
6976 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
6977 },
6978
6979 /* VEX_LEN_0F3A22 */
6980 {
6981 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
6982 },
6983
6984 /* VEX_LEN_0F3A30 */
6985 {
6986 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
6987 },
6988
6989 /* VEX_LEN_0F3A31 */
6990 {
6991 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
6992 },
6993
6994 /* VEX_LEN_0F3A32 */
6995 {
6996 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
6997 },
6998
6999 /* VEX_LEN_0F3A33 */
7000 {
7001 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7002 },
7003
7004 /* VEX_LEN_0F3A38 */
7005 {
7006 { Bad_Opcode },
7007 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7008 },
7009
7010 /* VEX_LEN_0F3A39 */
7011 {
7012 { Bad_Opcode },
7013 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7014 },
7015
7016 /* VEX_LEN_0F3A41 */
7017 {
7018 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7019 },
7020
7021 /* VEX_LEN_0F3A46 */
7022 {
7023 { Bad_Opcode },
7024 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7025 },
7026
7027 /* VEX_LEN_0F3A60 */
7028 {
7029 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7030 },
7031
7032 /* VEX_LEN_0F3A61 */
7033 {
7034 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7035 },
7036
7037 /* VEX_LEN_0F3A62 */
7038 {
7039 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7040 },
7041
7042 /* VEX_LEN_0F3A63 */
7043 {
7044 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7045 },
7046
7047 /* VEX_LEN_0F3ADF */
7048 {
7049 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7050 },
7051
7052 /* VEX_LEN_0F3AF0_P_3 */
7053 {
7054 { "rorxS", { Gdq, Edq, Ib }, 0 },
7055 },
7056
7057 /* VEX_LEN_0FXOP_08_85 */
7058 {
7059 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7060 },
7061
7062 /* VEX_LEN_0FXOP_08_86 */
7063 {
7064 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7065 },
7066
7067 /* VEX_LEN_0FXOP_08_87 */
7068 {
7069 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7070 },
7071
7072 /* VEX_LEN_0FXOP_08_8E */
7073 {
7074 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7075 },
7076
7077 /* VEX_LEN_0FXOP_08_8F */
7078 {
7079 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7080 },
7081
7082 /* VEX_LEN_0FXOP_08_95 */
7083 {
7084 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7085 },
7086
7087 /* VEX_LEN_0FXOP_08_96 */
7088 {
7089 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7090 },
7091
7092 /* VEX_LEN_0FXOP_08_97 */
7093 {
7094 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7095 },
7096
7097 /* VEX_LEN_0FXOP_08_9E */
7098 {
7099 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7100 },
7101
7102 /* VEX_LEN_0FXOP_08_9F */
7103 {
7104 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7105 },
7106
7107 /* VEX_LEN_0FXOP_08_A3 */
7108 {
7109 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7110 },
7111
7112 /* VEX_LEN_0FXOP_08_A6 */
7113 {
7114 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7115 },
7116
7117 /* VEX_LEN_0FXOP_08_B6 */
7118 {
7119 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7120 },
7121
7122 /* VEX_LEN_0FXOP_08_C0 */
7123 {
7124 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7125 },
7126
7127 /* VEX_LEN_0FXOP_08_C1 */
7128 {
7129 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7130 },
7131
7132 /* VEX_LEN_0FXOP_08_C2 */
7133 {
7134 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7135 },
7136
7137 /* VEX_LEN_0FXOP_08_C3 */
7138 {
7139 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7140 },
7141
7142 /* VEX_LEN_0FXOP_08_CC */
7143 {
7144 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7145 },
7146
7147 /* VEX_LEN_0FXOP_08_CD */
7148 {
7149 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7150 },
7151
7152 /* VEX_LEN_0FXOP_08_CE */
7153 {
7154 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7155 },
7156
7157 /* VEX_LEN_0FXOP_08_CF */
7158 {
7159 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7160 },
7161
7162 /* VEX_LEN_0FXOP_08_EC */
7163 {
7164 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7165 },
7166
7167 /* VEX_LEN_0FXOP_08_ED */
7168 {
7169 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7170 },
7171
7172 /* VEX_LEN_0FXOP_08_EE */
7173 {
7174 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7175 },
7176
7177 /* VEX_LEN_0FXOP_08_EF */
7178 {
7179 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7180 },
7181
7182 /* VEX_LEN_0FXOP_09_01 */
7183 {
7184 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7185 },
7186
7187 /* VEX_LEN_0FXOP_09_02 */
7188 {
7189 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7190 },
7191
7192 /* VEX_LEN_0FXOP_09_12_M_1 */
7193 {
7194 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7195 },
7196
7197 /* VEX_LEN_0FXOP_09_82_W_0 */
7198 {
7199 { "vfrczss", { XM, EXd }, 0 },
7200 },
7201
7202 /* VEX_LEN_0FXOP_09_83_W_0 */
7203 {
7204 { "vfrczsd", { XM, EXq }, 0 },
7205 },
7206
7207 /* VEX_LEN_0FXOP_09_90 */
7208 {
7209 { "vprotb", { XM, EXx, VexW }, 0 },
7210 },
7211
7212 /* VEX_LEN_0FXOP_09_91 */
7213 {
7214 { "vprotw", { XM, EXx, VexW }, 0 },
7215 },
7216
7217 /* VEX_LEN_0FXOP_09_92 */
7218 {
7219 { "vprotd", { XM, EXx, VexW }, 0 },
7220 },
7221
7222 /* VEX_LEN_0FXOP_09_93 */
7223 {
7224 { "vprotq", { XM, EXx, VexW }, 0 },
7225 },
7226
7227 /* VEX_LEN_0FXOP_09_94 */
7228 {
7229 { "vpshlb", { XM, EXx, VexW }, 0 },
7230 },
7231
7232 /* VEX_LEN_0FXOP_09_95 */
7233 {
7234 { "vpshlw", { XM, EXx, VexW }, 0 },
7235 },
7236
7237 /* VEX_LEN_0FXOP_09_96 */
7238 {
7239 { "vpshld", { XM, EXx, VexW }, 0 },
7240 },
7241
7242 /* VEX_LEN_0FXOP_09_97 */
7243 {
7244 { "vpshlq", { XM, EXx, VexW }, 0 },
7245 },
7246
7247 /* VEX_LEN_0FXOP_09_98 */
7248 {
7249 { "vpshab", { XM, EXx, VexW }, 0 },
7250 },
7251
7252 /* VEX_LEN_0FXOP_09_99 */
7253 {
7254 { "vpshaw", { XM, EXx, VexW }, 0 },
7255 },
7256
7257 /* VEX_LEN_0FXOP_09_9A */
7258 {
7259 { "vpshad", { XM, EXx, VexW }, 0 },
7260 },
7261
7262 /* VEX_LEN_0FXOP_09_9B */
7263 {
7264 { "vpshaq", { XM, EXx, VexW }, 0 },
7265 },
7266
7267 /* VEX_LEN_0FXOP_09_C1 */
7268 {
7269 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7270 },
7271
7272 /* VEX_LEN_0FXOP_09_C2 */
7273 {
7274 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7275 },
7276
7277 /* VEX_LEN_0FXOP_09_C3 */
7278 {
7279 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7280 },
7281
7282 /* VEX_LEN_0FXOP_09_C6 */
7283 {
7284 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7285 },
7286
7287 /* VEX_LEN_0FXOP_09_C7 */
7288 {
7289 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7290 },
7291
7292 /* VEX_LEN_0FXOP_09_CB */
7293 {
7294 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7295 },
7296
7297 /* VEX_LEN_0FXOP_09_D1 */
7298 {
7299 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7300 },
7301
7302 /* VEX_LEN_0FXOP_09_D2 */
7303 {
7304 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7305 },
7306
7307 /* VEX_LEN_0FXOP_09_D3 */
7308 {
7309 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7310 },
7311
7312 /* VEX_LEN_0FXOP_09_D6 */
7313 {
7314 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7315 },
7316
7317 /* VEX_LEN_0FXOP_09_D7 */
7318 {
7319 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7320 },
7321
7322 /* VEX_LEN_0FXOP_09_DB */
7323 {
7324 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7325 },
7326
7327 /* VEX_LEN_0FXOP_09_E1 */
7328 {
7329 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7330 },
7331
7332 /* VEX_LEN_0FXOP_09_E2 */
7333 {
7334 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7335 },
7336
7337 /* VEX_LEN_0FXOP_09_E3 */
7338 {
7339 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7340 },
7341
7342 /* VEX_LEN_0FXOP_0A_12 */
7343 {
7344 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7345 },
7346 };
7347
7348 #include "i386-dis-evex-len.h"
7349
7350 static const struct dis386 vex_w_table[][2] = {
7351 {
7352 /* VEX_W_0F41_P_0_LEN_1 */
7353 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7354 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7355 },
7356 {
7357 /* VEX_W_0F41_P_2_LEN_1 */
7358 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7359 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7360 },
7361 {
7362 /* VEX_W_0F42_P_0_LEN_1 */
7363 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7364 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7365 },
7366 {
7367 /* VEX_W_0F42_P_2_LEN_1 */
7368 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7369 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7370 },
7371 {
7372 /* VEX_W_0F44_P_0_LEN_0 */
7373 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7374 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7375 },
7376 {
7377 /* VEX_W_0F44_P_2_LEN_0 */
7378 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7379 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7380 },
7381 {
7382 /* VEX_W_0F45_P_0_LEN_1 */
7383 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7384 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7385 },
7386 {
7387 /* VEX_W_0F45_P_2_LEN_1 */
7388 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7389 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7390 },
7391 {
7392 /* VEX_W_0F46_P_0_LEN_1 */
7393 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7394 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7395 },
7396 {
7397 /* VEX_W_0F46_P_2_LEN_1 */
7398 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7399 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7400 },
7401 {
7402 /* VEX_W_0F47_P_0_LEN_1 */
7403 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7404 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7405 },
7406 {
7407 /* VEX_W_0F47_P_2_LEN_1 */
7408 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7409 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7410 },
7411 {
7412 /* VEX_W_0F4A_P_0_LEN_1 */
7413 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7414 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7415 },
7416 {
7417 /* VEX_W_0F4A_P_2_LEN_1 */
7418 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7419 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7420 },
7421 {
7422 /* VEX_W_0F4B_P_0_LEN_1 */
7423 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7424 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7425 },
7426 {
7427 /* VEX_W_0F4B_P_2_LEN_1 */
7428 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7429 },
7430 {
7431 /* VEX_W_0F90_P_0_LEN_0 */
7432 { "kmovw", { MaskG, MaskE }, 0 },
7433 { "kmovq", { MaskG, MaskE }, 0 },
7434 },
7435 {
7436 /* VEX_W_0F90_P_2_LEN_0 */
7437 { "kmovb", { MaskG, MaskBDE }, 0 },
7438 { "kmovd", { MaskG, MaskBDE }, 0 },
7439 },
7440 {
7441 /* VEX_W_0F91_P_0_LEN_0 */
7442 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7443 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7444 },
7445 {
7446 /* VEX_W_0F91_P_2_LEN_0 */
7447 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7448 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7449 },
7450 {
7451 /* VEX_W_0F92_P_0_LEN_0 */
7452 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7453 },
7454 {
7455 /* VEX_W_0F92_P_2_LEN_0 */
7456 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7457 },
7458 {
7459 /* VEX_W_0F93_P_0_LEN_0 */
7460 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7461 },
7462 {
7463 /* VEX_W_0F93_P_2_LEN_0 */
7464 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7465 },
7466 {
7467 /* VEX_W_0F98_P_0_LEN_0 */
7468 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7469 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7470 },
7471 {
7472 /* VEX_W_0F98_P_2_LEN_0 */
7473 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7474 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7475 },
7476 {
7477 /* VEX_W_0F99_P_0_LEN_0 */
7478 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7479 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7480 },
7481 {
7482 /* VEX_W_0F99_P_2_LEN_0 */
7483 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7484 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7485 },
7486 {
7487 /* VEX_W_0F380C */
7488 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7489 },
7490 {
7491 /* VEX_W_0F380D */
7492 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7493 },
7494 {
7495 /* VEX_W_0F380E */
7496 { "vtestps", { XM, EXx }, PREFIX_DATA },
7497 },
7498 {
7499 /* VEX_W_0F380F */
7500 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7501 },
7502 {
7503 /* VEX_W_0F3813 */
7504 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7505 },
7506 {
7507 /* VEX_W_0F3816_L_1 */
7508 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7509 },
7510 {
7511 /* VEX_W_0F3818 */
7512 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7513 },
7514 {
7515 /* VEX_W_0F3819_L_1 */
7516 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7517 },
7518 {
7519 /* VEX_W_0F381A_M_0_L_1 */
7520 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7521 },
7522 {
7523 /* VEX_W_0F382C_M_0 */
7524 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7525 },
7526 {
7527 /* VEX_W_0F382D_M_0 */
7528 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7529 },
7530 {
7531 /* VEX_W_0F382E_M_0 */
7532 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7533 },
7534 {
7535 /* VEX_W_0F382F_M_0 */
7536 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7537 },
7538 {
7539 /* VEX_W_0F3836 */
7540 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7541 },
7542 {
7543 /* VEX_W_0F3846 */
7544 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7545 },
7546 {
7547 /* VEX_W_0F3849_X86_64_P_0 */
7548 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7549 },
7550 {
7551 /* VEX_W_0F3849_X86_64_P_2 */
7552 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7553 },
7554 {
7555 /* VEX_W_0F3849_X86_64_P_3 */
7556 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7557 },
7558 {
7559 /* VEX_W_0F384B_X86_64_P_1 */
7560 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7561 },
7562 {
7563 /* VEX_W_0F384B_X86_64_P_2 */
7564 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7565 },
7566 {
7567 /* VEX_W_0F384B_X86_64_P_3 */
7568 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7569 },
7570 {
7571 /* VEX_W_0F3858 */
7572 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7573 },
7574 {
7575 /* VEX_W_0F3859 */
7576 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7577 },
7578 {
7579 /* VEX_W_0F385A_M_0_L_0 */
7580 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7581 },
7582 {
7583 /* VEX_W_0F385C_X86_64_P_1 */
7584 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7585 },
7586 {
7587 /* VEX_W_0F385E_X86_64_P_0 */
7588 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7589 },
7590 {
7591 /* VEX_W_0F385E_X86_64_P_1 */
7592 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7593 },
7594 {
7595 /* VEX_W_0F385E_X86_64_P_2 */
7596 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7597 },
7598 {
7599 /* VEX_W_0F385E_X86_64_P_3 */
7600 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7601 },
7602 {
7603 /* VEX_W_0F3878 */
7604 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7605 },
7606 {
7607 /* VEX_W_0F3879 */
7608 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7609 },
7610 {
7611 /* VEX_W_0F38CF */
7612 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7613 },
7614 {
7615 /* VEX_W_0F3A00_L_1 */
7616 { Bad_Opcode },
7617 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7618 },
7619 {
7620 /* VEX_W_0F3A01_L_1 */
7621 { Bad_Opcode },
7622 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7623 },
7624 {
7625 /* VEX_W_0F3A02 */
7626 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7627 },
7628 {
7629 /* VEX_W_0F3A04 */
7630 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7631 },
7632 {
7633 /* VEX_W_0F3A05 */
7634 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7635 },
7636 {
7637 /* VEX_W_0F3A06_L_1 */
7638 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7639 },
7640 {
7641 /* VEX_W_0F3A18_L_1 */
7642 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7643 },
7644 {
7645 /* VEX_W_0F3A19_L_1 */
7646 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7647 },
7648 {
7649 /* VEX_W_0F3A1D */
7650 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7651 },
7652 {
7653 /* VEX_W_0F3A38_L_1 */
7654 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7655 },
7656 {
7657 /* VEX_W_0F3A39_L_1 */
7658 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7659 },
7660 {
7661 /* VEX_W_0F3A46_L_1 */
7662 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7663 },
7664 {
7665 /* VEX_W_0F3A4A */
7666 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7667 },
7668 {
7669 /* VEX_W_0F3A4B */
7670 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7671 },
7672 {
7673 /* VEX_W_0F3A4C */
7674 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7675 },
7676 {
7677 /* VEX_W_0F3ACE */
7678 { Bad_Opcode },
7679 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7680 },
7681 {
7682 /* VEX_W_0F3ACF */
7683 { Bad_Opcode },
7684 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7685 },
7686 /* VEX_W_0FXOP_08_85_L_0 */
7687 {
7688 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7689 },
7690 /* VEX_W_0FXOP_08_86_L_0 */
7691 {
7692 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7693 },
7694 /* VEX_W_0FXOP_08_87_L_0 */
7695 {
7696 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7697 },
7698 /* VEX_W_0FXOP_08_8E_L_0 */
7699 {
7700 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7701 },
7702 /* VEX_W_0FXOP_08_8F_L_0 */
7703 {
7704 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7705 },
7706 /* VEX_W_0FXOP_08_95_L_0 */
7707 {
7708 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7709 },
7710 /* VEX_W_0FXOP_08_96_L_0 */
7711 {
7712 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7713 },
7714 /* VEX_W_0FXOP_08_97_L_0 */
7715 {
7716 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7717 },
7718 /* VEX_W_0FXOP_08_9E_L_0 */
7719 {
7720 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7721 },
7722 /* VEX_W_0FXOP_08_9F_L_0 */
7723 {
7724 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7725 },
7726 /* VEX_W_0FXOP_08_A6_L_0 */
7727 {
7728 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7729 },
7730 /* VEX_W_0FXOP_08_B6_L_0 */
7731 {
7732 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7733 },
7734 /* VEX_W_0FXOP_08_C0_L_0 */
7735 {
7736 { "vprotb", { XM, EXx, Ib }, 0 },
7737 },
7738 /* VEX_W_0FXOP_08_C1_L_0 */
7739 {
7740 { "vprotw", { XM, EXx, Ib }, 0 },
7741 },
7742 /* VEX_W_0FXOP_08_C2_L_0 */
7743 {
7744 { "vprotd", { XM, EXx, Ib }, 0 },
7745 },
7746 /* VEX_W_0FXOP_08_C3_L_0 */
7747 {
7748 { "vprotq", { XM, EXx, Ib }, 0 },
7749 },
7750 /* VEX_W_0FXOP_08_CC_L_0 */
7751 {
7752 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7753 },
7754 /* VEX_W_0FXOP_08_CD_L_0 */
7755 {
7756 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7757 },
7758 /* VEX_W_0FXOP_08_CE_L_0 */
7759 {
7760 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_CF_L_0 */
7763 {
7764 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_EC_L_0 */
7767 {
7768 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7769 },
7770 /* VEX_W_0FXOP_08_ED_L_0 */
7771 {
7772 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7773 },
7774 /* VEX_W_0FXOP_08_EE_L_0 */
7775 {
7776 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7777 },
7778 /* VEX_W_0FXOP_08_EF_L_0 */
7779 {
7780 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7781 },
7782 /* VEX_W_0FXOP_09_80 */
7783 {
7784 { "vfrczps", { XM, EXx }, 0 },
7785 },
7786 /* VEX_W_0FXOP_09_81 */
7787 {
7788 { "vfrczpd", { XM, EXx }, 0 },
7789 },
7790 /* VEX_W_0FXOP_09_82 */
7791 {
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7793 },
7794 /* VEX_W_0FXOP_09_83 */
7795 {
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7797 },
7798 /* VEX_W_0FXOP_09_C1_L_0 */
7799 {
7800 { "vphaddbw", { XM, EXxmm }, 0 },
7801 },
7802 /* VEX_W_0FXOP_09_C2_L_0 */
7803 {
7804 { "vphaddbd", { XM, EXxmm }, 0 },
7805 },
7806 /* VEX_W_0FXOP_09_C3_L_0 */
7807 {
7808 { "vphaddbq", { XM, EXxmm }, 0 },
7809 },
7810 /* VEX_W_0FXOP_09_C6_L_0 */
7811 {
7812 { "vphaddwd", { XM, EXxmm }, 0 },
7813 },
7814 /* VEX_W_0FXOP_09_C7_L_0 */
7815 {
7816 { "vphaddwq", { XM, EXxmm }, 0 },
7817 },
7818 /* VEX_W_0FXOP_09_CB_L_0 */
7819 {
7820 { "vphadddq", { XM, EXxmm }, 0 },
7821 },
7822 /* VEX_W_0FXOP_09_D1_L_0 */
7823 {
7824 { "vphaddubw", { XM, EXxmm }, 0 },
7825 },
7826 /* VEX_W_0FXOP_09_D2_L_0 */
7827 {
7828 { "vphaddubd", { XM, EXxmm }, 0 },
7829 },
7830 /* VEX_W_0FXOP_09_D3_L_0 */
7831 {
7832 { "vphaddubq", { XM, EXxmm }, 0 },
7833 },
7834 /* VEX_W_0FXOP_09_D6_L_0 */
7835 {
7836 { "vphadduwd", { XM, EXxmm }, 0 },
7837 },
7838 /* VEX_W_0FXOP_09_D7_L_0 */
7839 {
7840 { "vphadduwq", { XM, EXxmm }, 0 },
7841 },
7842 /* VEX_W_0FXOP_09_DB_L_0 */
7843 {
7844 { "vphaddudq", { XM, EXxmm }, 0 },
7845 },
7846 /* VEX_W_0FXOP_09_E1_L_0 */
7847 {
7848 { "vphsubbw", { XM, EXxmm }, 0 },
7849 },
7850 /* VEX_W_0FXOP_09_E2_L_0 */
7851 {
7852 { "vphsubwd", { XM, EXxmm }, 0 },
7853 },
7854 /* VEX_W_0FXOP_09_E3_L_0 */
7855 {
7856 { "vphsubdq", { XM, EXxmm }, 0 },
7857 },
7858
7859 #include "i386-dis-evex-w.h"
7860 };
7861
7862 static const struct dis386 mod_table[][2] = {
7863 {
7864 /* MOD_8D */
7865 { "leaS", { Gv, M }, 0 },
7866 },
7867 {
7868 /* MOD_C6_REG_7 */
7869 { Bad_Opcode },
7870 { RM_TABLE (RM_C6_REG_7) },
7871 },
7872 {
7873 /* MOD_C7_REG_7 */
7874 { Bad_Opcode },
7875 { RM_TABLE (RM_C7_REG_7) },
7876 },
7877 {
7878 /* MOD_FF_REG_3 */
7879 { "{l|}call^", { indirEp }, 0 },
7880 },
7881 {
7882 /* MOD_FF_REG_5 */
7883 { "{l|}jmp^", { indirEp }, 0 },
7884 },
7885 {
7886 /* MOD_0F01_REG_0 */
7887 { X86_64_TABLE (X86_64_0F01_REG_0) },
7888 { RM_TABLE (RM_0F01_REG_0) },
7889 },
7890 {
7891 /* MOD_0F01_REG_1 */
7892 { X86_64_TABLE (X86_64_0F01_REG_1) },
7893 { RM_TABLE (RM_0F01_REG_1) },
7894 },
7895 {
7896 /* MOD_0F01_REG_2 */
7897 { X86_64_TABLE (X86_64_0F01_REG_2) },
7898 { RM_TABLE (RM_0F01_REG_2) },
7899 },
7900 {
7901 /* MOD_0F01_REG_3 */
7902 { X86_64_TABLE (X86_64_0F01_REG_3) },
7903 { RM_TABLE (RM_0F01_REG_3) },
7904 },
7905 {
7906 /* MOD_0F01_REG_5 */
7907 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7908 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7909 },
7910 {
7911 /* MOD_0F01_REG_7 */
7912 { "invlpg", { Mb }, 0 },
7913 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7914 },
7915 {
7916 /* MOD_0F12_PREFIX_0 */
7917 { "movlpX", { XM, EXq }, 0 },
7918 { "movhlps", { XM, EXq }, 0 },
7919 },
7920 {
7921 /* MOD_0F12_PREFIX_2 */
7922 { "movlpX", { XM, EXq }, 0 },
7923 },
7924 {
7925 /* MOD_0F13 */
7926 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7927 },
7928 {
7929 /* MOD_0F16_PREFIX_0 */
7930 { "movhpX", { XM, EXq }, 0 },
7931 { "movlhps", { XM, EXq }, 0 },
7932 },
7933 {
7934 /* MOD_0F16_PREFIX_2 */
7935 { "movhpX", { XM, EXq }, 0 },
7936 },
7937 {
7938 /* MOD_0F17 */
7939 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7940 },
7941 {
7942 /* MOD_0F18_REG_0 */
7943 { "prefetchnta", { Mb }, 0 },
7944 },
7945 {
7946 /* MOD_0F18_REG_1 */
7947 { "prefetcht0", { Mb }, 0 },
7948 },
7949 {
7950 /* MOD_0F18_REG_2 */
7951 { "prefetcht1", { Mb }, 0 },
7952 },
7953 {
7954 /* MOD_0F18_REG_3 */
7955 { "prefetcht2", { Mb }, 0 },
7956 },
7957 {
7958 /* MOD_0F18_REG_4 */
7959 { "nop/reserved", { Mb }, 0 },
7960 },
7961 {
7962 /* MOD_0F18_REG_5 */
7963 { "nop/reserved", { Mb }, 0 },
7964 },
7965 {
7966 /* MOD_0F18_REG_6 */
7967 { "nop/reserved", { Mb }, 0 },
7968 },
7969 {
7970 /* MOD_0F18_REG_7 */
7971 { "nop/reserved", { Mb }, 0 },
7972 },
7973 {
7974 /* MOD_0F1A_PREFIX_0 */
7975 { "bndldx", { Gbnd, Mv_bnd }, 0 },
7976 { "nopQ", { Ev }, 0 },
7977 },
7978 {
7979 /* MOD_0F1B_PREFIX_0 */
7980 { "bndstx", { Mv_bnd, Gbnd }, 0 },
7981 { "nopQ", { Ev }, 0 },
7982 },
7983 {
7984 /* MOD_0F1B_PREFIX_1 */
7985 { "bndmk", { Gbnd, Mv_bnd }, 0 },
7986 { "nopQ", { Ev }, 0 },
7987 },
7988 {
7989 /* MOD_0F1C_PREFIX_0 */
7990 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7991 { "nopQ", { Ev }, 0 },
7992 },
7993 {
7994 /* MOD_0F1E_PREFIX_1 */
7995 { "nopQ", { Ev }, 0 },
7996 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7997 },
7998 {
7999 /* MOD_0F2B_PREFIX_0 */
8000 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8001 },
8002 {
8003 /* MOD_0F2B_PREFIX_1 */
8004 {"movntss", { Md, XM }, PREFIX_OPCODE },
8005 },
8006 {
8007 /* MOD_0F2B_PREFIX_2 */
8008 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8009 },
8010 {
8011 /* MOD_0F2B_PREFIX_3 */
8012 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8013 },
8014 {
8015 /* MOD_0F50 */
8016 { Bad_Opcode },
8017 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8018 },
8019 {
8020 /* MOD_0F71_REG_2 */
8021 { Bad_Opcode },
8022 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8023 },
8024 {
8025 /* MOD_0F71_REG_4 */
8026 { Bad_Opcode },
8027 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8028 },
8029 {
8030 /* MOD_0F71_REG_6 */
8031 { Bad_Opcode },
8032 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8033 },
8034 {
8035 /* MOD_0F72_REG_2 */
8036 { Bad_Opcode },
8037 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8038 },
8039 {
8040 /* MOD_0F72_REG_4 */
8041 { Bad_Opcode },
8042 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8043 },
8044 {
8045 /* MOD_0F72_REG_6 */
8046 { Bad_Opcode },
8047 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8048 },
8049 {
8050 /* MOD_0F73_REG_2 */
8051 { Bad_Opcode },
8052 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8053 },
8054 {
8055 /* MOD_0F73_REG_3 */
8056 { Bad_Opcode },
8057 { "psrldq", { XS, Ib }, PREFIX_DATA },
8058 },
8059 {
8060 /* MOD_0F73_REG_6 */
8061 { Bad_Opcode },
8062 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8063 },
8064 {
8065 /* MOD_0F73_REG_7 */
8066 { Bad_Opcode },
8067 { "pslldq", { XS, Ib }, PREFIX_DATA },
8068 },
8069 {
8070 /* MOD_0FAE_REG_0 */
8071 { "fxsave", { FXSAVE }, 0 },
8072 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8073 },
8074 {
8075 /* MOD_0FAE_REG_1 */
8076 { "fxrstor", { FXSAVE }, 0 },
8077 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8078 },
8079 {
8080 /* MOD_0FAE_REG_2 */
8081 { "ldmxcsr", { Md }, 0 },
8082 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8083 },
8084 {
8085 /* MOD_0FAE_REG_3 */
8086 { "stmxcsr", { Md }, 0 },
8087 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8088 },
8089 {
8090 /* MOD_0FAE_REG_4 */
8091 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8092 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8093 },
8094 {
8095 /* MOD_0FAE_REG_5 */
8096 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8097 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8098 },
8099 {
8100 /* MOD_0FAE_REG_6 */
8101 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8102 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8103 },
8104 {
8105 /* MOD_0FAE_REG_7 */
8106 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8107 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8108 },
8109 {
8110 /* MOD_0FB2 */
8111 { "lssS", { Gv, Mp }, 0 },
8112 },
8113 {
8114 /* MOD_0FB4 */
8115 { "lfsS", { Gv, Mp }, 0 },
8116 },
8117 {
8118 /* MOD_0FB5 */
8119 { "lgsS", { Gv, Mp }, 0 },
8120 },
8121 {
8122 /* MOD_0FC3 */
8123 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8124 },
8125 {
8126 /* MOD_0FC7_REG_3 */
8127 { "xrstors", { FXSAVE }, 0 },
8128 },
8129 {
8130 /* MOD_0FC7_REG_4 */
8131 { "xsavec", { FXSAVE }, 0 },
8132 },
8133 {
8134 /* MOD_0FC7_REG_5 */
8135 { "xsaves", { FXSAVE }, 0 },
8136 },
8137 {
8138 /* MOD_0FC7_REG_6 */
8139 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8140 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8141 },
8142 {
8143 /* MOD_0FC7_REG_7 */
8144 { "vmptrst", { Mq }, 0 },
8145 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8146 },
8147 {
8148 /* MOD_0FD7 */
8149 { Bad_Opcode },
8150 { "pmovmskb", { Gdq, MS }, 0 },
8151 },
8152 {
8153 /* MOD_0FE7_PREFIX_2 */
8154 { "movntdq", { Mx, XM }, 0 },
8155 },
8156 {
8157 /* MOD_0FF0_PREFIX_3 */
8158 { "lddqu", { XM, M }, 0 },
8159 },
8160 {
8161 /* MOD_0F382A */
8162 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8163 },
8164 {
8165 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8166 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8167 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8168 },
8169 {
8170 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8171 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8172 },
8173 {
8174 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8175 { Bad_Opcode },
8176 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8177 },
8178 {
8179 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8180 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8181 },
8182 {
8183 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8184 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8185 },
8186 {
8187 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8188 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8189 },
8190 {
8191 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8192 { Bad_Opcode },
8193 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8194 },
8195 {
8196 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8197 { Bad_Opcode },
8198 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8199 },
8200 {
8201 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8202 { Bad_Opcode },
8203 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8204 },
8205 {
8206 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8207 { Bad_Opcode },
8208 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8209 },
8210 {
8211 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8212 { Bad_Opcode },
8213 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8214 },
8215 {
8216 /* MOD_0F38F5 */
8217 { "wrussK", { M, Gdq }, PREFIX_DATA },
8218 },
8219 {
8220 /* MOD_0F38F6_PREFIX_0 */
8221 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8222 },
8223 {
8224 /* MOD_0F38F8_PREFIX_1 */
8225 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8226 },
8227 {
8228 /* MOD_0F38F8_PREFIX_2 */
8229 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8230 },
8231 {
8232 /* MOD_0F38F8_PREFIX_3 */
8233 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8234 },
8235 {
8236 /* MOD_0F38F9 */
8237 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8238 },
8239 {
8240 /* MOD_62_32BIT */
8241 { "bound{S|}", { Gv, Ma }, 0 },
8242 { EVEX_TABLE (EVEX_0F) },
8243 },
8244 {
8245 /* MOD_C4_32BIT */
8246 { "lesS", { Gv, Mp }, 0 },
8247 { VEX_C4_TABLE (VEX_0F) },
8248 },
8249 {
8250 /* MOD_C5_32BIT */
8251 { "ldsS", { Gv, Mp }, 0 },
8252 { VEX_C5_TABLE (VEX_0F) },
8253 },
8254 {
8255 /* MOD_VEX_0F12_PREFIX_0 */
8256 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8257 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8258 },
8259 {
8260 /* MOD_VEX_0F12_PREFIX_2 */
8261 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8262 },
8263 {
8264 /* MOD_VEX_0F13 */
8265 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8266 },
8267 {
8268 /* MOD_VEX_0F16_PREFIX_0 */
8269 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8270 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8271 },
8272 {
8273 /* MOD_VEX_0F16_PREFIX_2 */
8274 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8275 },
8276 {
8277 /* MOD_VEX_0F17 */
8278 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8279 },
8280 {
8281 /* MOD_VEX_0F2B */
8282 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8283 },
8284 {
8285 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8286 { Bad_Opcode },
8287 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
8288 },
8289 {
8290 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8291 { Bad_Opcode },
8292 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
8293 },
8294 {
8295 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8296 { Bad_Opcode },
8297 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
8298 },
8299 {
8300 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8301 { Bad_Opcode },
8302 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
8303 },
8304 {
8305 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8306 { Bad_Opcode },
8307 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
8308 },
8309 {
8310 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8311 { Bad_Opcode },
8312 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
8313 },
8314 {
8315 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8316 { Bad_Opcode },
8317 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
8318 },
8319 {
8320 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8321 { Bad_Opcode },
8322 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
8323 },
8324 {
8325 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8326 { Bad_Opcode },
8327 { "knotw", { MaskG, MaskE }, 0 },
8328 },
8329 {
8330 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8331 { Bad_Opcode },
8332 { "knotq", { MaskG, MaskE }, 0 },
8333 },
8334 {
8335 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8336 { Bad_Opcode },
8337 { "knotb", { MaskG, MaskE }, 0 },
8338 },
8339 {
8340 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8341 { Bad_Opcode },
8342 { "knotd", { MaskG, MaskE }, 0 },
8343 },
8344 {
8345 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8346 { Bad_Opcode },
8347 { "korw", { MaskG, MaskVex, MaskE }, 0 },
8348 },
8349 {
8350 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8351 { Bad_Opcode },
8352 { "korq", { MaskG, MaskVex, MaskE }, 0 },
8353 },
8354 {
8355 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8356 { Bad_Opcode },
8357 { "korb", { MaskG, MaskVex, MaskE }, 0 },
8358 },
8359 {
8360 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8361 { Bad_Opcode },
8362 { "kord", { MaskG, MaskVex, MaskE }, 0 },
8363 },
8364 {
8365 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8366 { Bad_Opcode },
8367 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
8368 },
8369 {
8370 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8371 { Bad_Opcode },
8372 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
8373 },
8374 {
8375 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8376 { Bad_Opcode },
8377 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
8378 },
8379 {
8380 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8381 { Bad_Opcode },
8382 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
8383 },
8384 {
8385 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8386 { Bad_Opcode },
8387 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
8388 },
8389 {
8390 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8391 { Bad_Opcode },
8392 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
8393 },
8394 {
8395 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8396 { Bad_Opcode },
8397 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
8398 },
8399 {
8400 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8401 { Bad_Opcode },
8402 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
8403 },
8404 {
8405 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8406 { Bad_Opcode },
8407 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
8408 },
8409 {
8410 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8411 { Bad_Opcode },
8412 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
8413 },
8414 {
8415 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8416 { Bad_Opcode },
8417 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
8418 },
8419 {
8420 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8421 { Bad_Opcode },
8422 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
8423 },
8424 {
8425 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8426 { Bad_Opcode },
8427 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
8428 },
8429 {
8430 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8431 { Bad_Opcode },
8432 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
8433 },
8434 {
8435 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8436 { Bad_Opcode },
8437 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
8438 },
8439 {
8440 /* MOD_VEX_0F50 */
8441 { Bad_Opcode },
8442 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8443 },
8444 {
8445 /* MOD_VEX_0F71_REG_2 */
8446 { Bad_Opcode },
8447 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8448 },
8449 {
8450 /* MOD_VEX_0F71_REG_4 */
8451 { Bad_Opcode },
8452 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8453 },
8454 {
8455 /* MOD_VEX_0F71_REG_6 */
8456 { Bad_Opcode },
8457 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8458 },
8459 {
8460 /* MOD_VEX_0F72_REG_2 */
8461 { Bad_Opcode },
8462 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8463 },
8464 {
8465 /* MOD_VEX_0F72_REG_4 */
8466 { Bad_Opcode },
8467 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8468 },
8469 {
8470 /* MOD_VEX_0F72_REG_6 */
8471 { Bad_Opcode },
8472 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8473 },
8474 {
8475 /* MOD_VEX_0F73_REG_2 */
8476 { Bad_Opcode },
8477 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8478 },
8479 {
8480 /* MOD_VEX_0F73_REG_3 */
8481 { Bad_Opcode },
8482 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8483 },
8484 {
8485 /* MOD_VEX_0F73_REG_6 */
8486 { Bad_Opcode },
8487 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8488 },
8489 {
8490 /* MOD_VEX_0F73_REG_7 */
8491 { Bad_Opcode },
8492 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8493 },
8494 {
8495 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8496 { "kmovw", { Ew, MaskG }, 0 },
8497 { Bad_Opcode },
8498 },
8499 {
8500 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8501 { "kmovq", { Eq, MaskG }, 0 },
8502 { Bad_Opcode },
8503 },
8504 {
8505 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8506 { "kmovb", { Eb, MaskG }, 0 },
8507 { Bad_Opcode },
8508 },
8509 {
8510 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8511 { "kmovd", { Ed, MaskG }, 0 },
8512 { Bad_Opcode },
8513 },
8514 {
8515 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8516 { Bad_Opcode },
8517 { "kmovw", { MaskG, Edq }, 0 },
8518 },
8519 {
8520 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8521 { Bad_Opcode },
8522 { "kmovb", { MaskG, Edq }, 0 },
8523 },
8524 {
8525 /* MOD_VEX_0F92_P_3_LEN_0 */
8526 { Bad_Opcode },
8527 { "kmovK", { MaskG, Edq }, 0 },
8528 },
8529 {
8530 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8531 { Bad_Opcode },
8532 { "kmovw", { Gdq, MaskE }, 0 },
8533 },
8534 {
8535 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8536 { Bad_Opcode },
8537 { "kmovb", { Gdq, MaskE }, 0 },
8538 },
8539 {
8540 /* MOD_VEX_0F93_P_3_LEN_0 */
8541 { Bad_Opcode },
8542 { "kmovK", { Gdq, MaskE }, 0 },
8543 },
8544 {
8545 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8546 { Bad_Opcode },
8547 { "kortestw", { MaskG, MaskE }, 0 },
8548 },
8549 {
8550 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8551 { Bad_Opcode },
8552 { "kortestq", { MaskG, MaskE }, 0 },
8553 },
8554 {
8555 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8556 { Bad_Opcode },
8557 { "kortestb", { MaskG, MaskE }, 0 },
8558 },
8559 {
8560 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8561 { Bad_Opcode },
8562 { "kortestd", { MaskG, MaskE }, 0 },
8563 },
8564 {
8565 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8566 { Bad_Opcode },
8567 { "ktestw", { MaskG, MaskE }, 0 },
8568 },
8569 {
8570 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8571 { Bad_Opcode },
8572 { "ktestq", { MaskG, MaskE }, 0 },
8573 },
8574 {
8575 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8576 { Bad_Opcode },
8577 { "ktestb", { MaskG, MaskE }, 0 },
8578 },
8579 {
8580 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8581 { Bad_Opcode },
8582 { "ktestd", { MaskG, MaskE }, 0 },
8583 },
8584 {
8585 /* MOD_VEX_0FAE_REG_2 */
8586 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8587 },
8588 {
8589 /* MOD_VEX_0FAE_REG_3 */
8590 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8591 },
8592 {
8593 /* MOD_VEX_0FD7 */
8594 { Bad_Opcode },
8595 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8596 },
8597 {
8598 /* MOD_VEX_0FE7 */
8599 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8600 },
8601 {
8602 /* MOD_VEX_0FF0_PREFIX_3 */
8603 { "vlddqu", { XM, M }, 0 },
8604 },
8605 {
8606 /* MOD_VEX_0F381A */
8607 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8608 },
8609 {
8610 /* MOD_VEX_0F382A */
8611 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8612 },
8613 {
8614 /* MOD_VEX_0F382C */
8615 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8616 },
8617 {
8618 /* MOD_VEX_0F382D */
8619 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8620 },
8621 {
8622 /* MOD_VEX_0F382E */
8623 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8624 },
8625 {
8626 /* MOD_VEX_0F382F */
8627 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8628 },
8629 {
8630 /* MOD_VEX_0F385A */
8631 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8632 },
8633 {
8634 /* MOD_VEX_0F388C */
8635 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8636 },
8637 {
8638 /* MOD_VEX_0F388E */
8639 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8640 },
8641 {
8642 /* MOD_VEX_0F3A30_L_0 */
8643 { Bad_Opcode },
8644 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8645 },
8646 {
8647 /* MOD_VEX_0F3A31_L_0 */
8648 { Bad_Opcode },
8649 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8650 },
8651 {
8652 /* MOD_VEX_0F3A32_L_0 */
8653 { Bad_Opcode },
8654 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8655 },
8656 {
8657 /* MOD_VEX_0F3A33_L_0 */
8658 { Bad_Opcode },
8659 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8660 },
8661 {
8662 /* MOD_VEX_0FXOP_09_12 */
8663 { Bad_Opcode },
8664 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8665 },
8666
8667 #include "i386-dis-evex-mod.h"
8668 };
8669
8670 static const struct dis386 rm_table[][8] = {
8671 {
8672 /* RM_C6_REG_7 */
8673 { "xabort", { Skip_MODRM, Ib }, 0 },
8674 },
8675 {
8676 /* RM_C7_REG_7 */
8677 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8678 },
8679 {
8680 /* RM_0F01_REG_0 */
8681 { "enclv", { Skip_MODRM }, 0 },
8682 { "vmcall", { Skip_MODRM }, 0 },
8683 { "vmlaunch", { Skip_MODRM }, 0 },
8684 { "vmresume", { Skip_MODRM }, 0 },
8685 { "vmxoff", { Skip_MODRM }, 0 },
8686 { "pconfig", { Skip_MODRM }, 0 },
8687 },
8688 {
8689 /* RM_0F01_REG_1 */
8690 { "monitor", { { OP_Monitor, 0 } }, 0 },
8691 { "mwait", { { OP_Mwait, 0 } }, 0 },
8692 { "clac", { Skip_MODRM }, 0 },
8693 { "stac", { Skip_MODRM }, 0 },
8694 { Bad_Opcode },
8695 { Bad_Opcode },
8696 { Bad_Opcode },
8697 { "encls", { Skip_MODRM }, 0 },
8698 },
8699 {
8700 /* RM_0F01_REG_2 */
8701 { "xgetbv", { Skip_MODRM }, 0 },
8702 { "xsetbv", { Skip_MODRM }, 0 },
8703 { Bad_Opcode },
8704 { Bad_Opcode },
8705 { "vmfunc", { Skip_MODRM }, 0 },
8706 { "xend", { Skip_MODRM }, 0 },
8707 { "xtest", { Skip_MODRM }, 0 },
8708 { "enclu", { Skip_MODRM }, 0 },
8709 },
8710 {
8711 /* RM_0F01_REG_3 */
8712 { "vmrun", { Skip_MODRM }, 0 },
8713 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8714 { "vmload", { Skip_MODRM }, 0 },
8715 { "vmsave", { Skip_MODRM }, 0 },
8716 { "stgi", { Skip_MODRM }, 0 },
8717 { "clgi", { Skip_MODRM }, 0 },
8718 { "skinit", { Skip_MODRM }, 0 },
8719 { "invlpga", { Skip_MODRM }, 0 },
8720 },
8721 {
8722 /* RM_0F01_REG_5_MOD_3 */
8723 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8724 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8725 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8726 { Bad_Opcode },
8727 { Bad_Opcode },
8728 { Bad_Opcode },
8729 { "rdpkru", { Skip_MODRM }, 0 },
8730 { "wrpkru", { Skip_MODRM }, 0 },
8731 },
8732 {
8733 /* RM_0F01_REG_7_MOD_3 */
8734 { "swapgs", { Skip_MODRM }, 0 },
8735 { "rdtscp", { Skip_MODRM }, 0 },
8736 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8737 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8738 { "clzero", { Skip_MODRM }, 0 },
8739 { "rdpru", { Skip_MODRM }, 0 },
8740 },
8741 {
8742 /* RM_0F1E_P_1_MOD_3_REG_7 */
8743 { "nopQ", { Ev }, 0 },
8744 { "nopQ", { Ev }, 0 },
8745 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
8746 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
8747 { "nopQ", { Ev }, 0 },
8748 { "nopQ", { Ev }, 0 },
8749 { "nopQ", { Ev }, 0 },
8750 { "nopQ", { Ev }, 0 },
8751 },
8752 {
8753 /* RM_0FAE_REG_6_MOD_3 */
8754 { "mfence", { Skip_MODRM }, 0 },
8755 },
8756 {
8757 /* RM_0FAE_REG_7_MOD_3 */
8758 { "sfence", { Skip_MODRM }, 0 },
8759
8760 },
8761 {
8762 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8763 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8764 },
8765 };
8766
8767 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8768
8769 /* We use the high bit to indicate different name for the same
8770 prefix. */
8771 #define REP_PREFIX (0xf3 | 0x100)
8772 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8773 #define XRELEASE_PREFIX (0xf3 | 0x400)
8774 #define BND_PREFIX (0xf2 | 0x400)
8775 #define NOTRACK_PREFIX (0x3e | 0x100)
8776
8777 /* Remember if the current op is a jump instruction. */
8778 static bfd_boolean op_is_jump = FALSE;
8779
8780 static int
8781 ckprefix (void)
8782 {
8783 int newrex, i, length;
8784 rex = 0;
8785 prefixes = 0;
8786 used_prefixes = 0;
8787 rex_used = 0;
8788 last_lock_prefix = -1;
8789 last_repz_prefix = -1;
8790 last_repnz_prefix = -1;
8791 last_data_prefix = -1;
8792 last_addr_prefix = -1;
8793 last_rex_prefix = -1;
8794 last_seg_prefix = -1;
8795 fwait_prefix = -1;
8796 active_seg_prefix = 0;
8797 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8798 all_prefixes[i] = 0;
8799 i = 0;
8800 length = 0;
8801 /* The maximum instruction length is 15bytes. */
8802 while (length < MAX_CODE_LENGTH - 1)
8803 {
8804 FETCH_DATA (the_info, codep + 1);
8805 newrex = 0;
8806 switch (*codep)
8807 {
8808 /* REX prefixes family. */
8809 case 0x40:
8810 case 0x41:
8811 case 0x42:
8812 case 0x43:
8813 case 0x44:
8814 case 0x45:
8815 case 0x46:
8816 case 0x47:
8817 case 0x48:
8818 case 0x49:
8819 case 0x4a:
8820 case 0x4b:
8821 case 0x4c:
8822 case 0x4d:
8823 case 0x4e:
8824 case 0x4f:
8825 if (address_mode == mode_64bit)
8826 newrex = *codep;
8827 else
8828 return 1;
8829 last_rex_prefix = i;
8830 break;
8831 case 0xf3:
8832 prefixes |= PREFIX_REPZ;
8833 last_repz_prefix = i;
8834 break;
8835 case 0xf2:
8836 prefixes |= PREFIX_REPNZ;
8837 last_repnz_prefix = i;
8838 break;
8839 case 0xf0:
8840 prefixes |= PREFIX_LOCK;
8841 last_lock_prefix = i;
8842 break;
8843 case 0x2e:
8844 prefixes |= PREFIX_CS;
8845 last_seg_prefix = i;
8846 active_seg_prefix = PREFIX_CS;
8847 break;
8848 case 0x36:
8849 prefixes |= PREFIX_SS;
8850 last_seg_prefix = i;
8851 active_seg_prefix = PREFIX_SS;
8852 break;
8853 case 0x3e:
8854 prefixes |= PREFIX_DS;
8855 last_seg_prefix = i;
8856 active_seg_prefix = PREFIX_DS;
8857 break;
8858 case 0x26:
8859 prefixes |= PREFIX_ES;
8860 last_seg_prefix = i;
8861 active_seg_prefix = PREFIX_ES;
8862 break;
8863 case 0x64:
8864 prefixes |= PREFIX_FS;
8865 last_seg_prefix = i;
8866 active_seg_prefix = PREFIX_FS;
8867 break;
8868 case 0x65:
8869 prefixes |= PREFIX_GS;
8870 last_seg_prefix = i;
8871 active_seg_prefix = PREFIX_GS;
8872 break;
8873 case 0x66:
8874 prefixes |= PREFIX_DATA;
8875 last_data_prefix = i;
8876 break;
8877 case 0x67:
8878 prefixes |= PREFIX_ADDR;
8879 last_addr_prefix = i;
8880 break;
8881 case FWAIT_OPCODE:
8882 /* fwait is really an instruction. If there are prefixes
8883 before the fwait, they belong to the fwait, *not* to the
8884 following instruction. */
8885 fwait_prefix = i;
8886 if (prefixes || rex)
8887 {
8888 prefixes |= PREFIX_FWAIT;
8889 codep++;
8890 /* This ensures that the previous REX prefixes are noticed
8891 as unused prefixes, as in the return case below. */
8892 rex_used = rex;
8893 return 1;
8894 }
8895 prefixes = PREFIX_FWAIT;
8896 break;
8897 default:
8898 return 1;
8899 }
8900 /* Rex is ignored when followed by another prefix. */
8901 if (rex)
8902 {
8903 rex_used = rex;
8904 return 1;
8905 }
8906 if (*codep != FWAIT_OPCODE)
8907 all_prefixes[i++] = *codep;
8908 rex = newrex;
8909 codep++;
8910 length++;
8911 }
8912 return 0;
8913 }
8914
8915 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8916 prefix byte. */
8917
8918 static const char *
8919 prefix_name (int pref, int sizeflag)
8920 {
8921 static const char *rexes [16] =
8922 {
8923 "rex", /* 0x40 */
8924 "rex.B", /* 0x41 */
8925 "rex.X", /* 0x42 */
8926 "rex.XB", /* 0x43 */
8927 "rex.R", /* 0x44 */
8928 "rex.RB", /* 0x45 */
8929 "rex.RX", /* 0x46 */
8930 "rex.RXB", /* 0x47 */
8931 "rex.W", /* 0x48 */
8932 "rex.WB", /* 0x49 */
8933 "rex.WX", /* 0x4a */
8934 "rex.WXB", /* 0x4b */
8935 "rex.WR", /* 0x4c */
8936 "rex.WRB", /* 0x4d */
8937 "rex.WRX", /* 0x4e */
8938 "rex.WRXB", /* 0x4f */
8939 };
8940
8941 switch (pref)
8942 {
8943 /* REX prefixes family. */
8944 case 0x40:
8945 case 0x41:
8946 case 0x42:
8947 case 0x43:
8948 case 0x44:
8949 case 0x45:
8950 case 0x46:
8951 case 0x47:
8952 case 0x48:
8953 case 0x49:
8954 case 0x4a:
8955 case 0x4b:
8956 case 0x4c:
8957 case 0x4d:
8958 case 0x4e:
8959 case 0x4f:
8960 return rexes [pref - 0x40];
8961 case 0xf3:
8962 return "repz";
8963 case 0xf2:
8964 return "repnz";
8965 case 0xf0:
8966 return "lock";
8967 case 0x2e:
8968 return "cs";
8969 case 0x36:
8970 return "ss";
8971 case 0x3e:
8972 return "ds";
8973 case 0x26:
8974 return "es";
8975 case 0x64:
8976 return "fs";
8977 case 0x65:
8978 return "gs";
8979 case 0x66:
8980 return (sizeflag & DFLAG) ? "data16" : "data32";
8981 case 0x67:
8982 if (address_mode == mode_64bit)
8983 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8984 else
8985 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8986 case FWAIT_OPCODE:
8987 return "fwait";
8988 case REP_PREFIX:
8989 return "rep";
8990 case XACQUIRE_PREFIX:
8991 return "xacquire";
8992 case XRELEASE_PREFIX:
8993 return "xrelease";
8994 case BND_PREFIX:
8995 return "bnd";
8996 case NOTRACK_PREFIX:
8997 return "notrack";
8998 default:
8999 return NULL;
9000 }
9001 }
9002
9003 static char op_out[MAX_OPERANDS][100];
9004 static int op_ad, op_index[MAX_OPERANDS];
9005 static int two_source_ops;
9006 static bfd_vma op_address[MAX_OPERANDS];
9007 static bfd_vma op_riprel[MAX_OPERANDS];
9008 static bfd_vma start_pc;
9009
9010 /*
9011 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9012 * (see topic "Redundant prefixes" in the "Differences from 8086"
9013 * section of the "Virtual 8086 Mode" chapter.)
9014 * 'pc' should be the address of this instruction, it will
9015 * be used to print the target address if this is a relative jump or call
9016 * The function returns the length of this instruction in bytes.
9017 */
9018
9019 static char intel_syntax;
9020 static char intel_mnemonic = !SYSV386_COMPAT;
9021 static char open_char;
9022 static char close_char;
9023 static char separator_char;
9024 static char scale_char;
9025
9026 enum x86_64_isa
9027 {
9028 amd64 = 1,
9029 intel64
9030 };
9031
9032 static enum x86_64_isa isa64;
9033
9034 /* Here for backwards compatibility. When gdb stops using
9035 print_insn_i386_att and print_insn_i386_intel these functions can
9036 disappear, and print_insn_i386 be merged into print_insn. */
9037 int
9038 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9039 {
9040 intel_syntax = 0;
9041
9042 return print_insn (pc, info);
9043 }
9044
9045 int
9046 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9047 {
9048 intel_syntax = 1;
9049
9050 return print_insn (pc, info);
9051 }
9052
9053 int
9054 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9055 {
9056 intel_syntax = -1;
9057
9058 return print_insn (pc, info);
9059 }
9060
9061 void
9062 print_i386_disassembler_options (FILE *stream)
9063 {
9064 fprintf (stream, _("\n\
9065 The following i386/x86-64 specific disassembler options are supported for use\n\
9066 with the -M switch (multiple options should be separated by commas):\n"));
9067
9068 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9069 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9070 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9071 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9072 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9073 fprintf (stream, _(" att-mnemonic\n"
9074 " Display instruction in AT&T mnemonic\n"));
9075 fprintf (stream, _(" intel-mnemonic\n"
9076 " Display instruction in Intel mnemonic\n"));
9077 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9078 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9079 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9080 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9081 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9082 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9083 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9084 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9085 }
9086
9087 /* Bad opcode. */
9088 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9089
9090 /* Get a pointer to struct dis386 with a valid name. */
9091
9092 static const struct dis386 *
9093 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9094 {
9095 int vindex, vex_table_index;
9096
9097 if (dp->name != NULL)
9098 return dp;
9099
9100 switch (dp->op[0].bytemode)
9101 {
9102 case USE_REG_TABLE:
9103 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9104 break;
9105
9106 case USE_MOD_TABLE:
9107 vindex = modrm.mod == 0x3 ? 1 : 0;
9108 dp = &mod_table[dp->op[1].bytemode][vindex];
9109 break;
9110
9111 case USE_RM_TABLE:
9112 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9113 break;
9114
9115 case USE_PREFIX_TABLE:
9116 if (need_vex)
9117 {
9118 /* The prefix in VEX is implicit. */
9119 switch (vex.prefix)
9120 {
9121 case 0:
9122 vindex = 0;
9123 break;
9124 case REPE_PREFIX_OPCODE:
9125 vindex = 1;
9126 break;
9127 case DATA_PREFIX_OPCODE:
9128 vindex = 2;
9129 break;
9130 case REPNE_PREFIX_OPCODE:
9131 vindex = 3;
9132 break;
9133 default:
9134 abort ();
9135 break;
9136 }
9137 }
9138 else
9139 {
9140 int last_prefix = -1;
9141 int prefix = 0;
9142 vindex = 0;
9143 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9144 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9145 last one wins. */
9146 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9147 {
9148 if (last_repz_prefix > last_repnz_prefix)
9149 {
9150 vindex = 1;
9151 prefix = PREFIX_REPZ;
9152 last_prefix = last_repz_prefix;
9153 }
9154 else
9155 {
9156 vindex = 3;
9157 prefix = PREFIX_REPNZ;
9158 last_prefix = last_repnz_prefix;
9159 }
9160
9161 /* Check if prefix should be ignored. */
9162 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9163 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9164 & prefix) != 0)
9165 vindex = 0;
9166 }
9167
9168 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9169 {
9170 vindex = 2;
9171 prefix = PREFIX_DATA;
9172 last_prefix = last_data_prefix;
9173 }
9174
9175 if (vindex != 0)
9176 {
9177 used_prefixes |= prefix;
9178 all_prefixes[last_prefix] = 0;
9179 }
9180 }
9181 dp = &prefix_table[dp->op[1].bytemode][vindex];
9182 break;
9183
9184 case USE_X86_64_TABLE:
9185 vindex = address_mode == mode_64bit ? 1 : 0;
9186 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9187 break;
9188
9189 case USE_3BYTE_TABLE:
9190 FETCH_DATA (info, codep + 2);
9191 vindex = *codep++;
9192 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9193 end_codep = codep;
9194 modrm.mod = (*codep >> 6) & 3;
9195 modrm.reg = (*codep >> 3) & 7;
9196 modrm.rm = *codep & 7;
9197 break;
9198
9199 case USE_VEX_LEN_TABLE:
9200 if (!need_vex)
9201 abort ();
9202
9203 switch (vex.length)
9204 {
9205 case 128:
9206 vindex = 0;
9207 break;
9208 case 256:
9209 vindex = 1;
9210 break;
9211 default:
9212 abort ();
9213 break;
9214 }
9215
9216 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9217 break;
9218
9219 case USE_EVEX_LEN_TABLE:
9220 if (!vex.evex)
9221 abort ();
9222
9223 switch (vex.length)
9224 {
9225 case 128:
9226 vindex = 0;
9227 break;
9228 case 256:
9229 vindex = 1;
9230 break;
9231 case 512:
9232 vindex = 2;
9233 break;
9234 default:
9235 abort ();
9236 break;
9237 }
9238
9239 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9240 break;
9241
9242 case USE_XOP_8F_TABLE:
9243 FETCH_DATA (info, codep + 3);
9244 rex = ~(*codep >> 5) & 0x7;
9245
9246 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9247 switch ((*codep & 0x1f))
9248 {
9249 default:
9250 dp = &bad_opcode;
9251 return dp;
9252 case 0x8:
9253 vex_table_index = XOP_08;
9254 break;
9255 case 0x9:
9256 vex_table_index = XOP_09;
9257 break;
9258 case 0xa:
9259 vex_table_index = XOP_0A;
9260 break;
9261 }
9262 codep++;
9263 vex.w = *codep & 0x80;
9264 if (vex.w && address_mode == mode_64bit)
9265 rex |= REX_W;
9266
9267 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9268 if (address_mode != mode_64bit)
9269 {
9270 /* In 16/32-bit mode REX_B is silently ignored. */
9271 rex &= ~REX_B;
9272 }
9273
9274 vex.length = (*codep & 0x4) ? 256 : 128;
9275 switch ((*codep & 0x3))
9276 {
9277 case 0:
9278 break;
9279 case 1:
9280 vex.prefix = DATA_PREFIX_OPCODE;
9281 break;
9282 case 2:
9283 vex.prefix = REPE_PREFIX_OPCODE;
9284 break;
9285 case 3:
9286 vex.prefix = REPNE_PREFIX_OPCODE;
9287 break;
9288 }
9289 need_vex = 1;
9290 codep++;
9291 vindex = *codep++;
9292 dp = &xop_table[vex_table_index][vindex];
9293
9294 end_codep = codep;
9295 FETCH_DATA (info, codep + 1);
9296 modrm.mod = (*codep >> 6) & 3;
9297 modrm.reg = (*codep >> 3) & 7;
9298 modrm.rm = *codep & 7;
9299
9300 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9301 having to decode the bits for every otherwise valid encoding. */
9302 if (vex.prefix)
9303 return &bad_opcode;
9304 break;
9305
9306 case USE_VEX_C4_TABLE:
9307 /* VEX prefix. */
9308 FETCH_DATA (info, codep + 3);
9309 rex = ~(*codep >> 5) & 0x7;
9310 switch ((*codep & 0x1f))
9311 {
9312 default:
9313 dp = &bad_opcode;
9314 return dp;
9315 case 0x1:
9316 vex_table_index = VEX_0F;
9317 break;
9318 case 0x2:
9319 vex_table_index = VEX_0F38;
9320 break;
9321 case 0x3:
9322 vex_table_index = VEX_0F3A;
9323 break;
9324 }
9325 codep++;
9326 vex.w = *codep & 0x80;
9327 if (address_mode == mode_64bit)
9328 {
9329 if (vex.w)
9330 rex |= REX_W;
9331 }
9332 else
9333 {
9334 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9335 is ignored, other REX bits are 0 and the highest bit in
9336 VEX.vvvv is also ignored (but we mustn't clear it here). */
9337 rex = 0;
9338 }
9339 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9340 vex.length = (*codep & 0x4) ? 256 : 128;
9341 switch ((*codep & 0x3))
9342 {
9343 case 0:
9344 break;
9345 case 1:
9346 vex.prefix = DATA_PREFIX_OPCODE;
9347 break;
9348 case 2:
9349 vex.prefix = REPE_PREFIX_OPCODE;
9350 break;
9351 case 3:
9352 vex.prefix = REPNE_PREFIX_OPCODE;
9353 break;
9354 }
9355 need_vex = 1;
9356 codep++;
9357 vindex = *codep++;
9358 dp = &vex_table[vex_table_index][vindex];
9359 end_codep = codep;
9360 /* There is no MODRM byte for VEX0F 77. */
9361 if (vex_table_index != VEX_0F || vindex != 0x77)
9362 {
9363 FETCH_DATA (info, codep + 1);
9364 modrm.mod = (*codep >> 6) & 3;
9365 modrm.reg = (*codep >> 3) & 7;
9366 modrm.rm = *codep & 7;
9367 }
9368 break;
9369
9370 case USE_VEX_C5_TABLE:
9371 /* VEX prefix. */
9372 FETCH_DATA (info, codep + 2);
9373 rex = (*codep & 0x80) ? 0 : REX_R;
9374
9375 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9376 VEX.vvvv is 1. */
9377 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9378 vex.length = (*codep & 0x4) ? 256 : 128;
9379 switch ((*codep & 0x3))
9380 {
9381 case 0:
9382 break;
9383 case 1:
9384 vex.prefix = DATA_PREFIX_OPCODE;
9385 break;
9386 case 2:
9387 vex.prefix = REPE_PREFIX_OPCODE;
9388 break;
9389 case 3:
9390 vex.prefix = REPNE_PREFIX_OPCODE;
9391 break;
9392 }
9393 need_vex = 1;
9394 codep++;
9395 vindex = *codep++;
9396 dp = &vex_table[dp->op[1].bytemode][vindex];
9397 end_codep = codep;
9398 /* There is no MODRM byte for VEX 77. */
9399 if (vindex != 0x77)
9400 {
9401 FETCH_DATA (info, codep + 1);
9402 modrm.mod = (*codep >> 6) & 3;
9403 modrm.reg = (*codep >> 3) & 7;
9404 modrm.rm = *codep & 7;
9405 }
9406 break;
9407
9408 case USE_VEX_W_TABLE:
9409 if (!need_vex)
9410 abort ();
9411
9412 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9413 break;
9414
9415 case USE_EVEX_TABLE:
9416 two_source_ops = 0;
9417 /* EVEX prefix. */
9418 vex.evex = 1;
9419 FETCH_DATA (info, codep + 4);
9420 /* The first byte after 0x62. */
9421 rex = ~(*codep >> 5) & 0x7;
9422 vex.r = *codep & 0x10;
9423 switch ((*codep & 0xf))
9424 {
9425 default:
9426 return &bad_opcode;
9427 case 0x1:
9428 vex_table_index = EVEX_0F;
9429 break;
9430 case 0x2:
9431 vex_table_index = EVEX_0F38;
9432 break;
9433 case 0x3:
9434 vex_table_index = EVEX_0F3A;
9435 break;
9436 }
9437
9438 /* The second byte after 0x62. */
9439 codep++;
9440 vex.w = *codep & 0x80;
9441 if (vex.w && address_mode == mode_64bit)
9442 rex |= REX_W;
9443
9444 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9445
9446 /* The U bit. */
9447 if (!(*codep & 0x4))
9448 return &bad_opcode;
9449
9450 switch ((*codep & 0x3))
9451 {
9452 case 0:
9453 break;
9454 case 1:
9455 vex.prefix = DATA_PREFIX_OPCODE;
9456 break;
9457 case 2:
9458 vex.prefix = REPE_PREFIX_OPCODE;
9459 break;
9460 case 3:
9461 vex.prefix = REPNE_PREFIX_OPCODE;
9462 break;
9463 }
9464
9465 /* The third byte after 0x62. */
9466 codep++;
9467
9468 /* Remember the static rounding bits. */
9469 vex.ll = (*codep >> 5) & 3;
9470 vex.b = (*codep & 0x10) != 0;
9471
9472 vex.v = *codep & 0x8;
9473 vex.mask_register_specifier = *codep & 0x7;
9474 vex.zeroing = *codep & 0x80;
9475
9476 if (address_mode != mode_64bit)
9477 {
9478 /* In 16/32-bit mode silently ignore following bits. */
9479 rex &= ~REX_B;
9480 vex.r = 1;
9481 vex.v = 1;
9482 }
9483
9484 need_vex = 1;
9485 codep++;
9486 vindex = *codep++;
9487 dp = &evex_table[vex_table_index][vindex];
9488 end_codep = codep;
9489 FETCH_DATA (info, codep + 1);
9490 modrm.mod = (*codep >> 6) & 3;
9491 modrm.reg = (*codep >> 3) & 7;
9492 modrm.rm = *codep & 7;
9493
9494 /* Set vector length. */
9495 if (modrm.mod == 3 && vex.b)
9496 vex.length = 512;
9497 else
9498 {
9499 switch (vex.ll)
9500 {
9501 case 0x0:
9502 vex.length = 128;
9503 break;
9504 case 0x1:
9505 vex.length = 256;
9506 break;
9507 case 0x2:
9508 vex.length = 512;
9509 break;
9510 default:
9511 return &bad_opcode;
9512 }
9513 }
9514 break;
9515
9516 case 0:
9517 dp = &bad_opcode;
9518 break;
9519
9520 default:
9521 abort ();
9522 }
9523
9524 if (dp->name != NULL)
9525 return dp;
9526 else
9527 return get_valid_dis386 (dp, info);
9528 }
9529
9530 static void
9531 get_sib (disassemble_info *info, int sizeflag)
9532 {
9533 /* If modrm.mod == 3, operand must be register. */
9534 if (need_modrm
9535 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9536 && modrm.mod != 3
9537 && modrm.rm == 4)
9538 {
9539 FETCH_DATA (info, codep + 2);
9540 sib.index = (codep [1] >> 3) & 7;
9541 sib.scale = (codep [1] >> 6) & 3;
9542 sib.base = codep [1] & 7;
9543 }
9544 }
9545
9546 static int
9547 print_insn (bfd_vma pc, disassemble_info *info)
9548 {
9549 const struct dis386 *dp;
9550 int i;
9551 char *op_txt[MAX_OPERANDS];
9552 int needcomma;
9553 int sizeflag, orig_sizeflag;
9554 const char *p;
9555 struct dis_private priv;
9556 int prefix_length;
9557
9558 priv.orig_sizeflag = AFLAG | DFLAG;
9559 if ((info->mach & bfd_mach_i386_i386) != 0)
9560 address_mode = mode_32bit;
9561 else if (info->mach == bfd_mach_i386_i8086)
9562 {
9563 address_mode = mode_16bit;
9564 priv.orig_sizeflag = 0;
9565 }
9566 else
9567 address_mode = mode_64bit;
9568
9569 if (intel_syntax == (char) -1)
9570 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9571
9572 for (p = info->disassembler_options; p != NULL; )
9573 {
9574 if (CONST_STRNEQ (p, "amd64"))
9575 isa64 = amd64;
9576 else if (CONST_STRNEQ (p, "intel64"))
9577 isa64 = intel64;
9578 else if (CONST_STRNEQ (p, "x86-64"))
9579 {
9580 address_mode = mode_64bit;
9581 priv.orig_sizeflag |= AFLAG | DFLAG;
9582 }
9583 else if (CONST_STRNEQ (p, "i386"))
9584 {
9585 address_mode = mode_32bit;
9586 priv.orig_sizeflag |= AFLAG | DFLAG;
9587 }
9588 else if (CONST_STRNEQ (p, "i8086"))
9589 {
9590 address_mode = mode_16bit;
9591 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9592 }
9593 else if (CONST_STRNEQ (p, "intel"))
9594 {
9595 intel_syntax = 1;
9596 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9597 intel_mnemonic = 1;
9598 }
9599 else if (CONST_STRNEQ (p, "att"))
9600 {
9601 intel_syntax = 0;
9602 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9603 intel_mnemonic = 0;
9604 }
9605 else if (CONST_STRNEQ (p, "addr"))
9606 {
9607 if (address_mode == mode_64bit)
9608 {
9609 if (p[4] == '3' && p[5] == '2')
9610 priv.orig_sizeflag &= ~AFLAG;
9611 else if (p[4] == '6' && p[5] == '4')
9612 priv.orig_sizeflag |= AFLAG;
9613 }
9614 else
9615 {
9616 if (p[4] == '1' && p[5] == '6')
9617 priv.orig_sizeflag &= ~AFLAG;
9618 else if (p[4] == '3' && p[5] == '2')
9619 priv.orig_sizeflag |= AFLAG;
9620 }
9621 }
9622 else if (CONST_STRNEQ (p, "data"))
9623 {
9624 if (p[4] == '1' && p[5] == '6')
9625 priv.orig_sizeflag &= ~DFLAG;
9626 else if (p[4] == '3' && p[5] == '2')
9627 priv.orig_sizeflag |= DFLAG;
9628 }
9629 else if (CONST_STRNEQ (p, "suffix"))
9630 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9631
9632 p = strchr (p, ',');
9633 if (p != NULL)
9634 p++;
9635 }
9636
9637 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9638 {
9639 (*info->fprintf_func) (info->stream,
9640 _("64-bit address is disabled"));
9641 return -1;
9642 }
9643
9644 if (intel_syntax)
9645 {
9646 names64 = intel_names64;
9647 names32 = intel_names32;
9648 names16 = intel_names16;
9649 names8 = intel_names8;
9650 names8rex = intel_names8rex;
9651 names_seg = intel_names_seg;
9652 names_mm = intel_names_mm;
9653 names_bnd = intel_names_bnd;
9654 names_xmm = intel_names_xmm;
9655 names_ymm = intel_names_ymm;
9656 names_zmm = intel_names_zmm;
9657 names_tmm = intel_names_tmm;
9658 index64 = intel_index64;
9659 index32 = intel_index32;
9660 names_mask = intel_names_mask;
9661 index16 = intel_index16;
9662 open_char = '[';
9663 close_char = ']';
9664 separator_char = '+';
9665 scale_char = '*';
9666 }
9667 else
9668 {
9669 names64 = att_names64;
9670 names32 = att_names32;
9671 names16 = att_names16;
9672 names8 = att_names8;
9673 names8rex = att_names8rex;
9674 names_seg = att_names_seg;
9675 names_mm = att_names_mm;
9676 names_bnd = att_names_bnd;
9677 names_xmm = att_names_xmm;
9678 names_ymm = att_names_ymm;
9679 names_zmm = att_names_zmm;
9680 names_tmm = att_names_tmm;
9681 index64 = att_index64;
9682 index32 = att_index32;
9683 names_mask = att_names_mask;
9684 index16 = att_index16;
9685 open_char = '(';
9686 close_char = ')';
9687 separator_char = ',';
9688 scale_char = ',';
9689 }
9690
9691 /* The output looks better if we put 7 bytes on a line, since that
9692 puts most long word instructions on a single line. Use 8 bytes
9693 for Intel L1OM. */
9694 if ((info->mach & bfd_mach_l1om) != 0)
9695 info->bytes_per_line = 8;
9696 else
9697 info->bytes_per_line = 7;
9698
9699 info->private_data = &priv;
9700 priv.max_fetched = priv.the_buffer;
9701 priv.insn_start = pc;
9702
9703 obuf[0] = 0;
9704 for (i = 0; i < MAX_OPERANDS; ++i)
9705 {
9706 op_out[i][0] = 0;
9707 op_index[i] = -1;
9708 }
9709
9710 the_info = info;
9711 start_pc = pc;
9712 start_codep = priv.the_buffer;
9713 codep = priv.the_buffer;
9714
9715 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9716 {
9717 const char *name;
9718
9719 /* Getting here means we tried for data but didn't get it. That
9720 means we have an incomplete instruction of some sort. Just
9721 print the first byte as a prefix or a .byte pseudo-op. */
9722 if (codep > priv.the_buffer)
9723 {
9724 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9725 if (name != NULL)
9726 (*info->fprintf_func) (info->stream, "%s", name);
9727 else
9728 {
9729 /* Just print the first byte as a .byte instruction. */
9730 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9731 (unsigned int) priv.the_buffer[0]);
9732 }
9733
9734 return 1;
9735 }
9736
9737 return -1;
9738 }
9739
9740 obufp = obuf;
9741 sizeflag = priv.orig_sizeflag;
9742
9743 if (!ckprefix () || rex_used)
9744 {
9745 /* Too many prefixes or unused REX prefixes. */
9746 for (i = 0;
9747 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9748 i++)
9749 (*info->fprintf_func) (info->stream, "%s%s",
9750 i == 0 ? "" : " ",
9751 prefix_name (all_prefixes[i], sizeflag));
9752 return i;
9753 }
9754
9755 insn_codep = codep;
9756
9757 FETCH_DATA (info, codep + 1);
9758 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9759
9760 if (((prefixes & PREFIX_FWAIT)
9761 && ((*codep < 0xd8) || (*codep > 0xdf))))
9762 {
9763 /* Handle prefixes before fwait. */
9764 for (i = 0; i < fwait_prefix && all_prefixes[i];
9765 i++)
9766 (*info->fprintf_func) (info->stream, "%s ",
9767 prefix_name (all_prefixes[i], sizeflag));
9768 (*info->fprintf_func) (info->stream, "fwait");
9769 return i + 1;
9770 }
9771
9772 if (*codep == 0x0f)
9773 {
9774 unsigned char threebyte;
9775
9776 codep++;
9777 FETCH_DATA (info, codep + 1);
9778 threebyte = *codep;
9779 dp = &dis386_twobyte[threebyte];
9780 need_modrm = twobyte_has_modrm[*codep];
9781 codep++;
9782 }
9783 else
9784 {
9785 dp = &dis386[*codep];
9786 need_modrm = onebyte_has_modrm[*codep];
9787 codep++;
9788 }
9789
9790 /* Save sizeflag for printing the extra prefixes later before updating
9791 it for mnemonic and operand processing. The prefix names depend
9792 only on the address mode. */
9793 orig_sizeflag = sizeflag;
9794 if (prefixes & PREFIX_ADDR)
9795 sizeflag ^= AFLAG;
9796 if ((prefixes & PREFIX_DATA))
9797 sizeflag ^= DFLAG;
9798
9799 end_codep = codep;
9800 if (need_modrm)
9801 {
9802 FETCH_DATA (info, codep + 1);
9803 modrm.mod = (*codep >> 6) & 3;
9804 modrm.reg = (*codep >> 3) & 7;
9805 modrm.rm = *codep & 7;
9806 }
9807
9808 need_vex = 0;
9809 memset (&vex, 0, sizeof (vex));
9810
9811 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9812 {
9813 get_sib (info, sizeflag);
9814 dofloat (sizeflag);
9815 }
9816 else
9817 {
9818 dp = get_valid_dis386 (dp, info);
9819 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9820 {
9821 get_sib (info, sizeflag);
9822 for (i = 0; i < MAX_OPERANDS; ++i)
9823 {
9824 obufp = op_out[i];
9825 op_ad = MAX_OPERANDS - 1 - i;
9826 if (dp->op[i].rtn)
9827 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9828 /* For EVEX instruction after the last operand masking
9829 should be printed. */
9830 if (i == 0 && vex.evex)
9831 {
9832 /* Don't print {%k0}. */
9833 if (vex.mask_register_specifier)
9834 {
9835 oappend ("{");
9836 oappend (names_mask[vex.mask_register_specifier]);
9837 oappend ("}");
9838 }
9839 if (vex.zeroing)
9840 oappend ("{z}");
9841 }
9842 }
9843 }
9844 }
9845
9846 /* Clear instruction information. */
9847 if (the_info)
9848 {
9849 the_info->insn_info_valid = 0;
9850 the_info->branch_delay_insns = 0;
9851 the_info->data_size = 0;
9852 the_info->insn_type = dis_noninsn;
9853 the_info->target = 0;
9854 the_info->target2 = 0;
9855 }
9856
9857 /* Reset jump operation indicator. */
9858 op_is_jump = FALSE;
9859
9860 {
9861 int jump_detection = 0;
9862
9863 /* Extract flags. */
9864 for (i = 0; i < MAX_OPERANDS; ++i)
9865 {
9866 if ((dp->op[i].rtn == OP_J)
9867 || (dp->op[i].rtn == OP_indirE))
9868 jump_detection |= 1;
9869 else if ((dp->op[i].rtn == BND_Fixup)
9870 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9871 jump_detection |= 2;
9872 else if ((dp->op[i].bytemode == cond_jump_mode)
9873 || (dp->op[i].bytemode == loop_jcxz_mode))
9874 jump_detection |= 4;
9875 }
9876
9877 /* Determine if this is a jump or branch. */
9878 if ((jump_detection & 0x3) == 0x3)
9879 {
9880 op_is_jump = TRUE;
9881 if (jump_detection & 0x4)
9882 the_info->insn_type = dis_condbranch;
9883 else
9884 the_info->insn_type =
9885 (dp->name && !strncmp(dp->name, "call", 4))
9886 ? dis_jsr : dis_branch;
9887 }
9888 }
9889
9890 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9891 are all 0s in inverted form. */
9892 if (need_vex && vex.register_specifier != 0)
9893 {
9894 (*info->fprintf_func) (info->stream, "(bad)");
9895 return end_codep - priv.the_buffer;
9896 }
9897
9898 switch (dp->prefix_requirement)
9899 {
9900 case PREFIX_DATA:
9901 /* If only the data prefix is marked as mandatory, its absence renders
9902 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9903 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9904 {
9905 (*info->fprintf_func) (info->stream, "(bad)");
9906 return end_codep - priv.the_buffer;
9907 }
9908 used_prefixes |= PREFIX_DATA;
9909 /* Fall through. */
9910 case PREFIX_OPCODE:
9911 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9912 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9913 used by putop and MMX/SSE operand and may be overridden by the
9914 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9915 separately. */
9916 if (((need_vex
9917 ? vex.prefix == REPE_PREFIX_OPCODE
9918 || vex.prefix == REPNE_PREFIX_OPCODE
9919 : (prefixes
9920 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9921 && (used_prefixes
9922 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9923 || (((need_vex
9924 ? vex.prefix == DATA_PREFIX_OPCODE
9925 : ((prefixes
9926 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9927 == PREFIX_DATA))
9928 && (used_prefixes & PREFIX_DATA) == 0))
9929 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9930 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9931 {
9932 (*info->fprintf_func) (info->stream, "(bad)");
9933 return end_codep - priv.the_buffer;
9934 }
9935 break;
9936 }
9937
9938 /* Check if the REX prefix is used. */
9939 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9940 all_prefixes[last_rex_prefix] = 0;
9941
9942 /* Check if the SEG prefix is used. */
9943 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9944 | PREFIX_FS | PREFIX_GS)) != 0
9945 && (used_prefixes & active_seg_prefix) != 0)
9946 all_prefixes[last_seg_prefix] = 0;
9947
9948 /* Check if the ADDR prefix is used. */
9949 if ((prefixes & PREFIX_ADDR) != 0
9950 && (used_prefixes & PREFIX_ADDR) != 0)
9951 all_prefixes[last_addr_prefix] = 0;
9952
9953 /* Check if the DATA prefix is used. */
9954 if ((prefixes & PREFIX_DATA) != 0
9955 && (used_prefixes & PREFIX_DATA) != 0
9956 && !need_vex)
9957 all_prefixes[last_data_prefix] = 0;
9958
9959 /* Print the extra prefixes. */
9960 prefix_length = 0;
9961 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9962 if (all_prefixes[i])
9963 {
9964 const char *name;
9965 name = prefix_name (all_prefixes[i], orig_sizeflag);
9966 if (name == NULL)
9967 abort ();
9968 prefix_length += strlen (name) + 1;
9969 (*info->fprintf_func) (info->stream, "%s ", name);
9970 }
9971
9972 /* Check maximum code length. */
9973 if ((codep - start_codep) > MAX_CODE_LENGTH)
9974 {
9975 (*info->fprintf_func) (info->stream, "(bad)");
9976 return MAX_CODE_LENGTH;
9977 }
9978
9979 obufp = mnemonicendp;
9980 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9981 oappend (" ");
9982 oappend (" ");
9983 (*info->fprintf_func) (info->stream, "%s", obuf);
9984
9985 /* The enter and bound instructions are printed with operands in the same
9986 order as the intel book; everything else is printed in reverse order. */
9987 if (intel_syntax || two_source_ops)
9988 {
9989 bfd_vma riprel;
9990
9991 for (i = 0; i < MAX_OPERANDS; ++i)
9992 op_txt[i] = op_out[i];
9993
9994 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9995 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9996 {
9997 op_txt[2] = op_out[3];
9998 op_txt[3] = op_out[2];
9999 }
10000
10001 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10002 {
10003 op_ad = op_index[i];
10004 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10005 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10006 riprel = op_riprel[i];
10007 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10008 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10009 }
10010 }
10011 else
10012 {
10013 for (i = 0; i < MAX_OPERANDS; ++i)
10014 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10015 }
10016
10017 needcomma = 0;
10018 for (i = 0; i < MAX_OPERANDS; ++i)
10019 if (*op_txt[i])
10020 {
10021 if (needcomma)
10022 (*info->fprintf_func) (info->stream, ",");
10023 if (op_index[i] != -1 && !op_riprel[i])
10024 {
10025 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10026
10027 if (the_info && op_is_jump)
10028 {
10029 the_info->insn_info_valid = 1;
10030 the_info->branch_delay_insns = 0;
10031 the_info->data_size = 0;
10032 the_info->target = target;
10033 the_info->target2 = 0;
10034 }
10035 (*info->print_address_func) (target, info);
10036 }
10037 else
10038 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10039 needcomma = 1;
10040 }
10041
10042 for (i = 0; i < MAX_OPERANDS; i++)
10043 if (op_index[i] != -1 && op_riprel[i])
10044 {
10045 (*info->fprintf_func) (info->stream, " # ");
10046 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10047 + op_address[op_index[i]]), info);
10048 break;
10049 }
10050 return codep - priv.the_buffer;
10051 }
10052
10053 static const char *float_mem[] = {
10054 /* d8 */
10055 "fadd{s|}",
10056 "fmul{s|}",
10057 "fcom{s|}",
10058 "fcomp{s|}",
10059 "fsub{s|}",
10060 "fsubr{s|}",
10061 "fdiv{s|}",
10062 "fdivr{s|}",
10063 /* d9 */
10064 "fld{s|}",
10065 "(bad)",
10066 "fst{s|}",
10067 "fstp{s|}",
10068 "fldenv{C|C}",
10069 "fldcw",
10070 "fNstenv{C|C}",
10071 "fNstcw",
10072 /* da */
10073 "fiadd{l|}",
10074 "fimul{l|}",
10075 "ficom{l|}",
10076 "ficomp{l|}",
10077 "fisub{l|}",
10078 "fisubr{l|}",
10079 "fidiv{l|}",
10080 "fidivr{l|}",
10081 /* db */
10082 "fild{l|}",
10083 "fisttp{l|}",
10084 "fist{l|}",
10085 "fistp{l|}",
10086 "(bad)",
10087 "fld{t|}",
10088 "(bad)",
10089 "fstp{t|}",
10090 /* dc */
10091 "fadd{l|}",
10092 "fmul{l|}",
10093 "fcom{l|}",
10094 "fcomp{l|}",
10095 "fsub{l|}",
10096 "fsubr{l|}",
10097 "fdiv{l|}",
10098 "fdivr{l|}",
10099 /* dd */
10100 "fld{l|}",
10101 "fisttp{ll|}",
10102 "fst{l||}",
10103 "fstp{l|}",
10104 "frstor{C|C}",
10105 "(bad)",
10106 "fNsave{C|C}",
10107 "fNstsw",
10108 /* de */
10109 "fiadd{s|}",
10110 "fimul{s|}",
10111 "ficom{s|}",
10112 "ficomp{s|}",
10113 "fisub{s|}",
10114 "fisubr{s|}",
10115 "fidiv{s|}",
10116 "fidivr{s|}",
10117 /* df */
10118 "fild{s|}",
10119 "fisttp{s|}",
10120 "fist{s|}",
10121 "fistp{s|}",
10122 "fbld",
10123 "fild{ll|}",
10124 "fbstp",
10125 "fistp{ll|}",
10126 };
10127
10128 static const unsigned char float_mem_mode[] = {
10129 /* d8 */
10130 d_mode,
10131 d_mode,
10132 d_mode,
10133 d_mode,
10134 d_mode,
10135 d_mode,
10136 d_mode,
10137 d_mode,
10138 /* d9 */
10139 d_mode,
10140 0,
10141 d_mode,
10142 d_mode,
10143 0,
10144 w_mode,
10145 0,
10146 w_mode,
10147 /* da */
10148 d_mode,
10149 d_mode,
10150 d_mode,
10151 d_mode,
10152 d_mode,
10153 d_mode,
10154 d_mode,
10155 d_mode,
10156 /* db */
10157 d_mode,
10158 d_mode,
10159 d_mode,
10160 d_mode,
10161 0,
10162 t_mode,
10163 0,
10164 t_mode,
10165 /* dc */
10166 q_mode,
10167 q_mode,
10168 q_mode,
10169 q_mode,
10170 q_mode,
10171 q_mode,
10172 q_mode,
10173 q_mode,
10174 /* dd */
10175 q_mode,
10176 q_mode,
10177 q_mode,
10178 q_mode,
10179 0,
10180 0,
10181 0,
10182 w_mode,
10183 /* de */
10184 w_mode,
10185 w_mode,
10186 w_mode,
10187 w_mode,
10188 w_mode,
10189 w_mode,
10190 w_mode,
10191 w_mode,
10192 /* df */
10193 w_mode,
10194 w_mode,
10195 w_mode,
10196 w_mode,
10197 t_mode,
10198 q_mode,
10199 t_mode,
10200 q_mode
10201 };
10202
10203 #define ST { OP_ST, 0 }
10204 #define STi { OP_STi, 0 }
10205
10206 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10207 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10208 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10209 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10210 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10211 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10212 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10213 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10214 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10215
10216 static const struct dis386 float_reg[][8] = {
10217 /* d8 */
10218 {
10219 { "fadd", { ST, STi }, 0 },
10220 { "fmul", { ST, STi }, 0 },
10221 { "fcom", { STi }, 0 },
10222 { "fcomp", { STi }, 0 },
10223 { "fsub", { ST, STi }, 0 },
10224 { "fsubr", { ST, STi }, 0 },
10225 { "fdiv", { ST, STi }, 0 },
10226 { "fdivr", { ST, STi }, 0 },
10227 },
10228 /* d9 */
10229 {
10230 { "fld", { STi }, 0 },
10231 { "fxch", { STi }, 0 },
10232 { FGRPd9_2 },
10233 { Bad_Opcode },
10234 { FGRPd9_4 },
10235 { FGRPd9_5 },
10236 { FGRPd9_6 },
10237 { FGRPd9_7 },
10238 },
10239 /* da */
10240 {
10241 { "fcmovb", { ST, STi }, 0 },
10242 { "fcmove", { ST, STi }, 0 },
10243 { "fcmovbe",{ ST, STi }, 0 },
10244 { "fcmovu", { ST, STi }, 0 },
10245 { Bad_Opcode },
10246 { FGRPda_5 },
10247 { Bad_Opcode },
10248 { Bad_Opcode },
10249 },
10250 /* db */
10251 {
10252 { "fcmovnb",{ ST, STi }, 0 },
10253 { "fcmovne",{ ST, STi }, 0 },
10254 { "fcmovnbe",{ ST, STi }, 0 },
10255 { "fcmovnu",{ ST, STi }, 0 },
10256 { FGRPdb_4 },
10257 { "fucomi", { ST, STi }, 0 },
10258 { "fcomi", { ST, STi }, 0 },
10259 { Bad_Opcode },
10260 },
10261 /* dc */
10262 {
10263 { "fadd", { STi, ST }, 0 },
10264 { "fmul", { STi, ST }, 0 },
10265 { Bad_Opcode },
10266 { Bad_Opcode },
10267 { "fsub{!M|r}", { STi, ST }, 0 },
10268 { "fsub{M|}", { STi, ST }, 0 },
10269 { "fdiv{!M|r}", { STi, ST }, 0 },
10270 { "fdiv{M|}", { STi, ST }, 0 },
10271 },
10272 /* dd */
10273 {
10274 { "ffree", { STi }, 0 },
10275 { Bad_Opcode },
10276 { "fst", { STi }, 0 },
10277 { "fstp", { STi }, 0 },
10278 { "fucom", { STi }, 0 },
10279 { "fucomp", { STi }, 0 },
10280 { Bad_Opcode },
10281 { Bad_Opcode },
10282 },
10283 /* de */
10284 {
10285 { "faddp", { STi, ST }, 0 },
10286 { "fmulp", { STi, ST }, 0 },
10287 { Bad_Opcode },
10288 { FGRPde_3 },
10289 { "fsub{!M|r}p", { STi, ST }, 0 },
10290 { "fsub{M|}p", { STi, ST }, 0 },
10291 { "fdiv{!M|r}p", { STi, ST }, 0 },
10292 { "fdiv{M|}p", { STi, ST }, 0 },
10293 },
10294 /* df */
10295 {
10296 { "ffreep", { STi }, 0 },
10297 { Bad_Opcode },
10298 { Bad_Opcode },
10299 { Bad_Opcode },
10300 { FGRPdf_4 },
10301 { "fucomip", { ST, STi }, 0 },
10302 { "fcomip", { ST, STi }, 0 },
10303 { Bad_Opcode },
10304 },
10305 };
10306
10307 static char *fgrps[][8] = {
10308 /* Bad opcode 0 */
10309 {
10310 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10311 },
10312
10313 /* d9_2 1 */
10314 {
10315 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10316 },
10317
10318 /* d9_4 2 */
10319 {
10320 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10321 },
10322
10323 /* d9_5 3 */
10324 {
10325 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10326 },
10327
10328 /* d9_6 4 */
10329 {
10330 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10331 },
10332
10333 /* d9_7 5 */
10334 {
10335 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10336 },
10337
10338 /* da_5 6 */
10339 {
10340 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10341 },
10342
10343 /* db_4 7 */
10344 {
10345 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10346 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10347 },
10348
10349 /* de_3 8 */
10350 {
10351 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10352 },
10353
10354 /* df_4 9 */
10355 {
10356 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10357 },
10358 };
10359
10360 static void
10361 swap_operand (void)
10362 {
10363 mnemonicendp[0] = '.';
10364 mnemonicendp[1] = 's';
10365 mnemonicendp += 2;
10366 }
10367
10368 static void
10369 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10370 int sizeflag ATTRIBUTE_UNUSED)
10371 {
10372 /* Skip mod/rm byte. */
10373 MODRM_CHECK;
10374 codep++;
10375 }
10376
10377 static void
10378 dofloat (int sizeflag)
10379 {
10380 const struct dis386 *dp;
10381 unsigned char floatop;
10382
10383 floatop = codep[-1];
10384
10385 if (modrm.mod != 3)
10386 {
10387 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10388
10389 putop (float_mem[fp_indx], sizeflag);
10390 obufp = op_out[0];
10391 op_ad = 2;
10392 OP_E (float_mem_mode[fp_indx], sizeflag);
10393 return;
10394 }
10395 /* Skip mod/rm byte. */
10396 MODRM_CHECK;
10397 codep++;
10398
10399 dp = &float_reg[floatop - 0xd8][modrm.reg];
10400 if (dp->name == NULL)
10401 {
10402 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10403
10404 /* Instruction fnstsw is only one with strange arg. */
10405 if (floatop == 0xdf && codep[-1] == 0xe0)
10406 strcpy (op_out[0], names16[0]);
10407 }
10408 else
10409 {
10410 putop (dp->name, sizeflag);
10411
10412 obufp = op_out[0];
10413 op_ad = 2;
10414 if (dp->op[0].rtn)
10415 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10416
10417 obufp = op_out[1];
10418 op_ad = 1;
10419 if (dp->op[1].rtn)
10420 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10421 }
10422 }
10423
10424 /* Like oappend (below), but S is a string starting with '%'.
10425 In Intel syntax, the '%' is elided. */
10426 static void
10427 oappend_maybe_intel (const char *s)
10428 {
10429 oappend (s + intel_syntax);
10430 }
10431
10432 static void
10433 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10434 {
10435 oappend_maybe_intel ("%st");
10436 }
10437
10438 static void
10439 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10440 {
10441 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10442 oappend_maybe_intel (scratchbuf);
10443 }
10444
10445 /* Capital letters in template are macros. */
10446 static int
10447 putop (const char *in_template, int sizeflag)
10448 {
10449 const char *p;
10450 int alt = 0;
10451 int cond = 1;
10452 unsigned int l = 0, len = 0;
10453 char last[4];
10454
10455 for (p = in_template; *p; p++)
10456 {
10457 if (len > l)
10458 {
10459 if (l >= sizeof (last) || !ISUPPER (*p))
10460 abort ();
10461 last[l++] = *p;
10462 continue;
10463 }
10464 switch (*p)
10465 {
10466 default:
10467 *obufp++ = *p;
10468 break;
10469 case '%':
10470 len++;
10471 break;
10472 case '!':
10473 cond = 0;
10474 break;
10475 case '{':
10476 if (intel_syntax)
10477 {
10478 while (*++p != '|')
10479 if (*p == '}' || *p == '\0')
10480 abort ();
10481 alt = 1;
10482 }
10483 break;
10484 case '|':
10485 while (*++p != '}')
10486 {
10487 if (*p == '\0')
10488 abort ();
10489 }
10490 break;
10491 case '}':
10492 alt = 0;
10493 break;
10494 case 'A':
10495 if (intel_syntax)
10496 break;
10497 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10498 *obufp++ = 'b';
10499 break;
10500 case 'B':
10501 if (l == 0)
10502 {
10503 case_B:
10504 if (intel_syntax)
10505 break;
10506 if (sizeflag & SUFFIX_ALWAYS)
10507 *obufp++ = 'b';
10508 }
10509 else if (l == 1 && last[0] == 'L')
10510 {
10511 if (address_mode == mode_64bit
10512 && !(prefixes & PREFIX_ADDR))
10513 {
10514 *obufp++ = 'a';
10515 *obufp++ = 'b';
10516 *obufp++ = 's';
10517 }
10518
10519 goto case_B;
10520 }
10521 else
10522 abort ();
10523 break;
10524 case 'C':
10525 if (intel_syntax && !alt)
10526 break;
10527 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10528 {
10529 if (sizeflag & DFLAG)
10530 *obufp++ = intel_syntax ? 'd' : 'l';
10531 else
10532 *obufp++ = intel_syntax ? 'w' : 's';
10533 used_prefixes |= (prefixes & PREFIX_DATA);
10534 }
10535 break;
10536 case 'D':
10537 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10538 break;
10539 USED_REX (REX_W);
10540 if (modrm.mod == 3)
10541 {
10542 if (rex & REX_W)
10543 *obufp++ = 'q';
10544 else
10545 {
10546 if (sizeflag & DFLAG)
10547 *obufp++ = intel_syntax ? 'd' : 'l';
10548 else
10549 *obufp++ = 'w';
10550 used_prefixes |= (prefixes & PREFIX_DATA);
10551 }
10552 }
10553 else
10554 *obufp++ = 'w';
10555 break;
10556 case 'E': /* For jcxz/jecxz */
10557 if (address_mode == mode_64bit)
10558 {
10559 if (sizeflag & AFLAG)
10560 *obufp++ = 'r';
10561 else
10562 *obufp++ = 'e';
10563 }
10564 else
10565 if (sizeflag & AFLAG)
10566 *obufp++ = 'e';
10567 used_prefixes |= (prefixes & PREFIX_ADDR);
10568 break;
10569 case 'F':
10570 if (intel_syntax)
10571 break;
10572 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10573 {
10574 if (sizeflag & AFLAG)
10575 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10576 else
10577 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10578 used_prefixes |= (prefixes & PREFIX_ADDR);
10579 }
10580 break;
10581 case 'G':
10582 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10583 break;
10584 if ((rex & REX_W) || (sizeflag & DFLAG))
10585 *obufp++ = 'l';
10586 else
10587 *obufp++ = 'w';
10588 if (!(rex & REX_W))
10589 used_prefixes |= (prefixes & PREFIX_DATA);
10590 break;
10591 case 'H':
10592 if (intel_syntax)
10593 break;
10594 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10595 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10596 {
10597 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10598 *obufp++ = ',';
10599 *obufp++ = 'p';
10600 if (prefixes & PREFIX_DS)
10601 *obufp++ = 't';
10602 else
10603 *obufp++ = 'n';
10604 }
10605 break;
10606 case 'K':
10607 USED_REX (REX_W);
10608 if (rex & REX_W)
10609 *obufp++ = 'q';
10610 else
10611 *obufp++ = 'd';
10612 break;
10613 case 'L':
10614 abort ();
10615 case 'M':
10616 if (intel_mnemonic != cond)
10617 *obufp++ = 'r';
10618 break;
10619 case 'N':
10620 if ((prefixes & PREFIX_FWAIT) == 0)
10621 *obufp++ = 'n';
10622 else
10623 used_prefixes |= PREFIX_FWAIT;
10624 break;
10625 case 'O':
10626 USED_REX (REX_W);
10627 if (rex & REX_W)
10628 *obufp++ = 'o';
10629 else if (intel_syntax && (sizeflag & DFLAG))
10630 *obufp++ = 'q';
10631 else
10632 *obufp++ = 'd';
10633 if (!(rex & REX_W))
10634 used_prefixes |= (prefixes & PREFIX_DATA);
10635 break;
10636 case '@':
10637 if (address_mode == mode_64bit
10638 && (isa64 == intel64 || (rex & REX_W)
10639 || !(prefixes & PREFIX_DATA)))
10640 {
10641 if (sizeflag & SUFFIX_ALWAYS)
10642 *obufp++ = 'q';
10643 break;
10644 }
10645 /* Fall through. */
10646 case 'P':
10647 if (l == 0)
10648 {
10649 if (((need_modrm && modrm.mod == 3) || !cond)
10650 && !(sizeflag & SUFFIX_ALWAYS))
10651 break;
10652 /* Fall through. */
10653 case 'T':
10654 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10655 || ((sizeflag & SUFFIX_ALWAYS)
10656 && address_mode != mode_64bit))
10657 {
10658 *obufp++ = (sizeflag & DFLAG) ?
10659 intel_syntax ? 'd' : 'l' : 'w';
10660 used_prefixes |= (prefixes & PREFIX_DATA);
10661 }
10662 else if (sizeflag & SUFFIX_ALWAYS)
10663 *obufp++ = 'q';
10664 }
10665 else if (l == 1 && last[0] == 'L')
10666 {
10667 if ((prefixes & PREFIX_DATA)
10668 || (rex & REX_W)
10669 || (sizeflag & SUFFIX_ALWAYS))
10670 {
10671 USED_REX (REX_W);
10672 if (rex & REX_W)
10673 *obufp++ = 'q';
10674 else
10675 {
10676 if (sizeflag & DFLAG)
10677 *obufp++ = intel_syntax ? 'd' : 'l';
10678 else
10679 *obufp++ = 'w';
10680 used_prefixes |= (prefixes & PREFIX_DATA);
10681 }
10682 }
10683 }
10684 else
10685 abort ();
10686 break;
10687 case 'Q':
10688 if (l == 0)
10689 {
10690 if (intel_syntax && !alt)
10691 break;
10692 USED_REX (REX_W);
10693 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10694 {
10695 if (rex & REX_W)
10696 *obufp++ = 'q';
10697 else
10698 {
10699 if (sizeflag & DFLAG)
10700 *obufp++ = intel_syntax ? 'd' : 'l';
10701 else
10702 *obufp++ = 'w';
10703 used_prefixes |= (prefixes & PREFIX_DATA);
10704 }
10705 }
10706 }
10707 else if (l == 1 && last[0] == 'D')
10708 *obufp++ = vex.w ? 'q' : 'd';
10709 else if (l == 1 && last[0] == 'L')
10710 {
10711 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10712 : address_mode != mode_64bit)
10713 break;
10714 if ((rex & REX_W))
10715 {
10716 USED_REX (REX_W);
10717 *obufp++ = 'q';
10718 }
10719 else if((address_mode == mode_64bit && need_modrm && cond)
10720 || (sizeflag & SUFFIX_ALWAYS))
10721 *obufp++ = intel_syntax? 'd' : 'l';
10722 }
10723 else
10724 abort ();
10725 break;
10726 case 'R':
10727 USED_REX (REX_W);
10728 if (rex & REX_W)
10729 *obufp++ = 'q';
10730 else if (sizeflag & DFLAG)
10731 {
10732 if (intel_syntax)
10733 *obufp++ = 'd';
10734 else
10735 *obufp++ = 'l';
10736 }
10737 else
10738 *obufp++ = 'w';
10739 if (intel_syntax && !p[1]
10740 && ((rex & REX_W) || (sizeflag & DFLAG)))
10741 *obufp++ = 'e';
10742 if (!(rex & REX_W))
10743 used_prefixes |= (prefixes & PREFIX_DATA);
10744 break;
10745 case 'S':
10746 if (l == 0)
10747 {
10748 case_S:
10749 if (intel_syntax)
10750 break;
10751 if (sizeflag & SUFFIX_ALWAYS)
10752 {
10753 if (rex & REX_W)
10754 *obufp++ = 'q';
10755 else
10756 {
10757 if (sizeflag & DFLAG)
10758 *obufp++ = 'l';
10759 else
10760 *obufp++ = 'w';
10761 used_prefixes |= (prefixes & PREFIX_DATA);
10762 }
10763 }
10764 }
10765 else if (l == 1 && last[0] == 'L')
10766 {
10767 if (address_mode == mode_64bit
10768 && !(prefixes & PREFIX_ADDR))
10769 {
10770 *obufp++ = 'a';
10771 *obufp++ = 'b';
10772 *obufp++ = 's';
10773 }
10774
10775 goto case_S;
10776 }
10777 else
10778 abort ();
10779 break;
10780 case 'V':
10781 if (l == 0)
10782 abort ();
10783 else if (l == 1 && last[0] == 'L')
10784 {
10785 if (rex & REX_W)
10786 {
10787 *obufp++ = 'a';
10788 *obufp++ = 'b';
10789 *obufp++ = 's';
10790 }
10791 }
10792 else
10793 abort ();
10794 goto case_S;
10795 case 'W':
10796 if (l == 0)
10797 {
10798 /* operand size flag for cwtl, cbtw */
10799 USED_REX (REX_W);
10800 if (rex & REX_W)
10801 {
10802 if (intel_syntax)
10803 *obufp++ = 'd';
10804 else
10805 *obufp++ = 'l';
10806 }
10807 else if (sizeflag & DFLAG)
10808 *obufp++ = 'w';
10809 else
10810 *obufp++ = 'b';
10811 if (!(rex & REX_W))
10812 used_prefixes |= (prefixes & PREFIX_DATA);
10813 }
10814 else if (l == 1)
10815 {
10816 if (!need_vex)
10817 abort ();
10818 if (last[0] == 'X')
10819 *obufp++ = vex.w ? 'd': 's';
10820 else if (last[0] == 'B')
10821 *obufp++ = vex.w ? 'w': 'b';
10822 else
10823 abort ();
10824 }
10825 else
10826 abort ();
10827 break;
10828 case 'X':
10829 if (l != 0)
10830 abort ();
10831 if (need_vex
10832 ? vex.prefix == DATA_PREFIX_OPCODE
10833 : prefixes & PREFIX_DATA)
10834 {
10835 *obufp++ = 'd';
10836 used_prefixes |= PREFIX_DATA;
10837 }
10838 else
10839 *obufp++ = 's';
10840 break;
10841 case 'Y':
10842 if (l == 1 && last[0] == 'X')
10843 {
10844 if (!need_vex)
10845 abort ();
10846 if (intel_syntax
10847 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10848 break;
10849 switch (vex.length)
10850 {
10851 case 128:
10852 *obufp++ = 'x';
10853 break;
10854 case 256:
10855 *obufp++ = 'y';
10856 break;
10857 case 512:
10858 if (!vex.evex)
10859 default:
10860 abort ();
10861 }
10862 }
10863 else
10864 abort ();
10865 break;
10866 case 'Z':
10867 if (l == 0)
10868 {
10869 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10870 modrm.mod = 3;
10871 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10872 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10873 }
10874 else if (l == 1 && last[0] == 'X')
10875 {
10876 if (!need_vex || !vex.evex)
10877 abort ();
10878 if (intel_syntax
10879 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10880 break;
10881 switch (vex.length)
10882 {
10883 case 128:
10884 *obufp++ = 'x';
10885 break;
10886 case 256:
10887 *obufp++ = 'y';
10888 break;
10889 case 512:
10890 *obufp++ = 'z';
10891 break;
10892 default:
10893 abort ();
10894 }
10895 }
10896 else
10897 abort ();
10898 break;
10899 case '^':
10900 if (intel_syntax)
10901 break;
10902 if (isa64 == intel64 && (rex & REX_W))
10903 {
10904 USED_REX (REX_W);
10905 *obufp++ = 'q';
10906 break;
10907 }
10908 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10909 {
10910 if (sizeflag & DFLAG)
10911 *obufp++ = 'l';
10912 else
10913 *obufp++ = 'w';
10914 used_prefixes |= (prefixes & PREFIX_DATA);
10915 }
10916 break;
10917 }
10918
10919 if (len == l)
10920 len = l = 0;
10921 }
10922 *obufp = 0;
10923 mnemonicendp = obufp;
10924 return 0;
10925 }
10926
10927 static void
10928 oappend (const char *s)
10929 {
10930 obufp = stpcpy (obufp, s);
10931 }
10932
10933 static void
10934 append_seg (void)
10935 {
10936 /* Only print the active segment register. */
10937 if (!active_seg_prefix)
10938 return;
10939
10940 used_prefixes |= active_seg_prefix;
10941 switch (active_seg_prefix)
10942 {
10943 case PREFIX_CS:
10944 oappend_maybe_intel ("%cs:");
10945 break;
10946 case PREFIX_DS:
10947 oappend_maybe_intel ("%ds:");
10948 break;
10949 case PREFIX_SS:
10950 oappend_maybe_intel ("%ss:");
10951 break;
10952 case PREFIX_ES:
10953 oappend_maybe_intel ("%es:");
10954 break;
10955 case PREFIX_FS:
10956 oappend_maybe_intel ("%fs:");
10957 break;
10958 case PREFIX_GS:
10959 oappend_maybe_intel ("%gs:");
10960 break;
10961 default:
10962 break;
10963 }
10964 }
10965
10966 static void
10967 OP_indirE (int bytemode, int sizeflag)
10968 {
10969 if (!intel_syntax)
10970 oappend ("*");
10971 OP_E (bytemode, sizeflag);
10972 }
10973
10974 static void
10975 print_operand_value (char *buf, int hex, bfd_vma disp)
10976 {
10977 if (address_mode == mode_64bit)
10978 {
10979 if (hex)
10980 {
10981 char tmp[30];
10982 int i;
10983 buf[0] = '0';
10984 buf[1] = 'x';
10985 sprintf_vma (tmp, disp);
10986 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10987 strcpy (buf + 2, tmp + i);
10988 }
10989 else
10990 {
10991 bfd_signed_vma v = disp;
10992 char tmp[30];
10993 int i;
10994 if (v < 0)
10995 {
10996 *(buf++) = '-';
10997 v = -disp;
10998 /* Check for possible overflow on 0x8000000000000000. */
10999 if (v < 0)
11000 {
11001 strcpy (buf, "9223372036854775808");
11002 return;
11003 }
11004 }
11005 if (!v)
11006 {
11007 strcpy (buf, "0");
11008 return;
11009 }
11010
11011 i = 0;
11012 tmp[29] = 0;
11013 while (v)
11014 {
11015 tmp[28 - i] = (v % 10) + '0';
11016 v /= 10;
11017 i++;
11018 }
11019 strcpy (buf, tmp + 29 - i);
11020 }
11021 }
11022 else
11023 {
11024 if (hex)
11025 sprintf (buf, "0x%x", (unsigned int) disp);
11026 else
11027 sprintf (buf, "%d", (int) disp);
11028 }
11029 }
11030
11031 /* Put DISP in BUF as signed hex number. */
11032
11033 static void
11034 print_displacement (char *buf, bfd_vma disp)
11035 {
11036 bfd_signed_vma val = disp;
11037 char tmp[30];
11038 int i, j = 0;
11039
11040 if (val < 0)
11041 {
11042 buf[j++] = '-';
11043 val = -disp;
11044
11045 /* Check for possible overflow. */
11046 if (val < 0)
11047 {
11048 switch (address_mode)
11049 {
11050 case mode_64bit:
11051 strcpy (buf + j, "0x8000000000000000");
11052 break;
11053 case mode_32bit:
11054 strcpy (buf + j, "0x80000000");
11055 break;
11056 case mode_16bit:
11057 strcpy (buf + j, "0x8000");
11058 break;
11059 }
11060 return;
11061 }
11062 }
11063
11064 buf[j++] = '0';
11065 buf[j++] = 'x';
11066
11067 sprintf_vma (tmp, (bfd_vma) val);
11068 for (i = 0; tmp[i] == '0'; i++)
11069 continue;
11070 if (tmp[i] == '\0')
11071 i--;
11072 strcpy (buf + j, tmp + i);
11073 }
11074
11075 static void
11076 intel_operand_size (int bytemode, int sizeflag)
11077 {
11078 if (vex.evex
11079 && vex.b
11080 && (bytemode == x_mode
11081 || bytemode == evex_half_bcst_xmmq_mode))
11082 {
11083 if (vex.w)
11084 oappend ("QWORD PTR ");
11085 else
11086 oappend ("DWORD PTR ");
11087 return;
11088 }
11089 switch (bytemode)
11090 {
11091 case b_mode:
11092 case b_swap_mode:
11093 case dqb_mode:
11094 case db_mode:
11095 oappend ("BYTE PTR ");
11096 break;
11097 case w_mode:
11098 case dw_mode:
11099 case dqw_mode:
11100 oappend ("WORD PTR ");
11101 break;
11102 case indir_v_mode:
11103 if (address_mode == mode_64bit && isa64 == intel64)
11104 {
11105 oappend ("QWORD PTR ");
11106 break;
11107 }
11108 /* Fall through. */
11109 case stack_v_mode:
11110 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11111 {
11112 oappend ("QWORD PTR ");
11113 break;
11114 }
11115 /* Fall through. */
11116 case v_mode:
11117 case v_swap_mode:
11118 case dq_mode:
11119 USED_REX (REX_W);
11120 if (rex & REX_W)
11121 oappend ("QWORD PTR ");
11122 else if (bytemode == dq_mode)
11123 oappend ("DWORD PTR ");
11124 else
11125 {
11126 if (sizeflag & DFLAG)
11127 oappend ("DWORD PTR ");
11128 else
11129 oappend ("WORD PTR ");
11130 used_prefixes |= (prefixes & PREFIX_DATA);
11131 }
11132 break;
11133 case z_mode:
11134 if ((rex & REX_W) || (sizeflag & DFLAG))
11135 *obufp++ = 'D';
11136 oappend ("WORD PTR ");
11137 if (!(rex & REX_W))
11138 used_prefixes |= (prefixes & PREFIX_DATA);
11139 break;
11140 case a_mode:
11141 if (sizeflag & DFLAG)
11142 oappend ("QWORD PTR ");
11143 else
11144 oappend ("DWORD PTR ");
11145 used_prefixes |= (prefixes & PREFIX_DATA);
11146 break;
11147 case movsxd_mode:
11148 if (!(sizeflag & DFLAG) && isa64 == intel64)
11149 oappend ("WORD PTR ");
11150 else
11151 oappend ("DWORD PTR ");
11152 used_prefixes |= (prefixes & PREFIX_DATA);
11153 break;
11154 case d_mode:
11155 case d_swap_mode:
11156 case dqd_mode:
11157 oappend ("DWORD PTR ");
11158 break;
11159 case q_mode:
11160 case q_swap_mode:
11161 oappend ("QWORD PTR ");
11162 break;
11163 case m_mode:
11164 if (address_mode == mode_64bit)
11165 oappend ("QWORD PTR ");
11166 else
11167 oappend ("DWORD PTR ");
11168 break;
11169 case f_mode:
11170 if (sizeflag & DFLAG)
11171 oappend ("FWORD PTR ");
11172 else
11173 oappend ("DWORD PTR ");
11174 used_prefixes |= (prefixes & PREFIX_DATA);
11175 break;
11176 case t_mode:
11177 oappend ("TBYTE PTR ");
11178 break;
11179 case x_mode:
11180 case x_swap_mode:
11181 case evex_x_gscat_mode:
11182 case evex_x_nobcst_mode:
11183 case bw_unit_mode:
11184 if (need_vex)
11185 {
11186 switch (vex.length)
11187 {
11188 case 128:
11189 oappend ("XMMWORD PTR ");
11190 break;
11191 case 256:
11192 oappend ("YMMWORD PTR ");
11193 break;
11194 case 512:
11195 oappend ("ZMMWORD PTR ");
11196 break;
11197 default:
11198 abort ();
11199 }
11200 }
11201 else
11202 oappend ("XMMWORD PTR ");
11203 break;
11204 case xmm_mode:
11205 oappend ("XMMWORD PTR ");
11206 break;
11207 case ymm_mode:
11208 oappend ("YMMWORD PTR ");
11209 break;
11210 case xmmq_mode:
11211 case evex_half_bcst_xmmq_mode:
11212 if (!need_vex)
11213 abort ();
11214
11215 switch (vex.length)
11216 {
11217 case 128:
11218 oappend ("QWORD PTR ");
11219 break;
11220 case 256:
11221 oappend ("XMMWORD PTR ");
11222 break;
11223 case 512:
11224 oappend ("YMMWORD PTR ");
11225 break;
11226 default:
11227 abort ();
11228 }
11229 break;
11230 case xmm_mb_mode:
11231 if (!need_vex)
11232 abort ();
11233
11234 switch (vex.length)
11235 {
11236 case 128:
11237 case 256:
11238 case 512:
11239 oappend ("BYTE PTR ");
11240 break;
11241 default:
11242 abort ();
11243 }
11244 break;
11245 case xmm_mw_mode:
11246 if (!need_vex)
11247 abort ();
11248
11249 switch (vex.length)
11250 {
11251 case 128:
11252 case 256:
11253 case 512:
11254 oappend ("WORD PTR ");
11255 break;
11256 default:
11257 abort ();
11258 }
11259 break;
11260 case xmm_md_mode:
11261 if (!need_vex)
11262 abort ();
11263
11264 switch (vex.length)
11265 {
11266 case 128:
11267 case 256:
11268 case 512:
11269 oappend ("DWORD PTR ");
11270 break;
11271 default:
11272 abort ();
11273 }
11274 break;
11275 case xmm_mq_mode:
11276 if (!need_vex)
11277 abort ();
11278
11279 switch (vex.length)
11280 {
11281 case 128:
11282 case 256:
11283 case 512:
11284 oappend ("QWORD PTR ");
11285 break;
11286 default:
11287 abort ();
11288 }
11289 break;
11290 case xmmdw_mode:
11291 if (!need_vex)
11292 abort ();
11293
11294 switch (vex.length)
11295 {
11296 case 128:
11297 oappend ("WORD PTR ");
11298 break;
11299 case 256:
11300 oappend ("DWORD PTR ");
11301 break;
11302 case 512:
11303 oappend ("QWORD PTR ");
11304 break;
11305 default:
11306 abort ();
11307 }
11308 break;
11309 case xmmqd_mode:
11310 if (!need_vex)
11311 abort ();
11312
11313 switch (vex.length)
11314 {
11315 case 128:
11316 oappend ("DWORD PTR ");
11317 break;
11318 case 256:
11319 oappend ("QWORD PTR ");
11320 break;
11321 case 512:
11322 oappend ("XMMWORD PTR ");
11323 break;
11324 default:
11325 abort ();
11326 }
11327 break;
11328 case ymmq_mode:
11329 if (!need_vex)
11330 abort ();
11331
11332 switch (vex.length)
11333 {
11334 case 128:
11335 oappend ("QWORD PTR ");
11336 break;
11337 case 256:
11338 oappend ("YMMWORD PTR ");
11339 break;
11340 case 512:
11341 oappend ("ZMMWORD PTR ");
11342 break;
11343 default:
11344 abort ();
11345 }
11346 break;
11347 case ymmxmm_mode:
11348 if (!need_vex)
11349 abort ();
11350
11351 switch (vex.length)
11352 {
11353 case 128:
11354 case 256:
11355 oappend ("XMMWORD PTR ");
11356 break;
11357 default:
11358 abort ();
11359 }
11360 break;
11361 case o_mode:
11362 oappend ("OWORD PTR ");
11363 break;
11364 case vex_scalar_w_dq_mode:
11365 if (!need_vex)
11366 abort ();
11367
11368 if (vex.w)
11369 oappend ("QWORD PTR ");
11370 else
11371 oappend ("DWORD PTR ");
11372 break;
11373 case vex_vsib_d_w_dq_mode:
11374 case vex_vsib_q_w_dq_mode:
11375 if (!need_vex)
11376 abort ();
11377
11378 if (!vex.evex)
11379 {
11380 if (vex.w)
11381 oappend ("QWORD PTR ");
11382 else
11383 oappend ("DWORD PTR ");
11384 }
11385 else
11386 {
11387 switch (vex.length)
11388 {
11389 case 128:
11390 oappend ("XMMWORD PTR ");
11391 break;
11392 case 256:
11393 oappend ("YMMWORD PTR ");
11394 break;
11395 case 512:
11396 oappend ("ZMMWORD PTR ");
11397 break;
11398 default:
11399 abort ();
11400 }
11401 }
11402 break;
11403 case vex_vsib_q_w_d_mode:
11404 case vex_vsib_d_w_d_mode:
11405 if (!need_vex || !vex.evex)
11406 abort ();
11407
11408 switch (vex.length)
11409 {
11410 case 128:
11411 oappend ("QWORD PTR ");
11412 break;
11413 case 256:
11414 oappend ("XMMWORD PTR ");
11415 break;
11416 case 512:
11417 oappend ("YMMWORD PTR ");
11418 break;
11419 default:
11420 abort ();
11421 }
11422
11423 break;
11424 case mask_bd_mode:
11425 if (!need_vex || vex.length != 128)
11426 abort ();
11427 if (vex.w)
11428 oappend ("DWORD PTR ");
11429 else
11430 oappend ("BYTE PTR ");
11431 break;
11432 case mask_mode:
11433 if (!need_vex)
11434 abort ();
11435 if (vex.w)
11436 oappend ("QWORD PTR ");
11437 else
11438 oappend ("WORD PTR ");
11439 break;
11440 case v_bnd_mode:
11441 case v_bndmk_mode:
11442 default:
11443 break;
11444 }
11445 }
11446
11447 static void
11448 OP_E_register (int bytemode, int sizeflag)
11449 {
11450 int reg = modrm.rm;
11451 const char **names;
11452
11453 USED_REX (REX_B);
11454 if ((rex & REX_B))
11455 reg += 8;
11456
11457 if ((sizeflag & SUFFIX_ALWAYS)
11458 && (bytemode == b_swap_mode
11459 || bytemode == bnd_swap_mode
11460 || bytemode == v_swap_mode))
11461 swap_operand ();
11462
11463 switch (bytemode)
11464 {
11465 case b_mode:
11466 case b_swap_mode:
11467 if (reg & 4)
11468 USED_REX (0);
11469 if (rex)
11470 names = names8rex;
11471 else
11472 names = names8;
11473 break;
11474 case w_mode:
11475 names = names16;
11476 break;
11477 case d_mode:
11478 case dw_mode:
11479 case db_mode:
11480 names = names32;
11481 break;
11482 case q_mode:
11483 names = names64;
11484 break;
11485 case m_mode:
11486 case v_bnd_mode:
11487 names = address_mode == mode_64bit ? names64 : names32;
11488 break;
11489 case bnd_mode:
11490 case bnd_swap_mode:
11491 if (reg > 0x3)
11492 {
11493 oappend ("(bad)");
11494 return;
11495 }
11496 names = names_bnd;
11497 break;
11498 case indir_v_mode:
11499 if (address_mode == mode_64bit && isa64 == intel64)
11500 {
11501 names = names64;
11502 break;
11503 }
11504 /* Fall through. */
11505 case stack_v_mode:
11506 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11507 {
11508 names = names64;
11509 break;
11510 }
11511 bytemode = v_mode;
11512 /* Fall through. */
11513 case v_mode:
11514 case v_swap_mode:
11515 case dq_mode:
11516 case dqb_mode:
11517 case dqd_mode:
11518 case dqw_mode:
11519 USED_REX (REX_W);
11520 if (rex & REX_W)
11521 names = names64;
11522 else if (bytemode != v_mode && bytemode != v_swap_mode)
11523 names = names32;
11524 else
11525 {
11526 if (sizeflag & DFLAG)
11527 names = names32;
11528 else
11529 names = names16;
11530 used_prefixes |= (prefixes & PREFIX_DATA);
11531 }
11532 break;
11533 case movsxd_mode:
11534 if (!(sizeflag & DFLAG) && isa64 == intel64)
11535 names = names16;
11536 else
11537 names = names32;
11538 used_prefixes |= (prefixes & PREFIX_DATA);
11539 break;
11540 case va_mode:
11541 names = (address_mode == mode_64bit
11542 ? names64 : names32);
11543 if (!(prefixes & PREFIX_ADDR))
11544 names = (address_mode == mode_16bit
11545 ? names16 : names);
11546 else
11547 {
11548 /* Remove "addr16/addr32". */
11549 all_prefixes[last_addr_prefix] = 0;
11550 names = (address_mode != mode_32bit
11551 ? names32 : names16);
11552 used_prefixes |= PREFIX_ADDR;
11553 }
11554 break;
11555 case mask_bd_mode:
11556 case mask_mode:
11557 if (reg > 0x7)
11558 {
11559 oappend ("(bad)");
11560 return;
11561 }
11562 names = names_mask;
11563 break;
11564 case 0:
11565 return;
11566 default:
11567 oappend (INTERNAL_DISASSEMBLER_ERROR);
11568 return;
11569 }
11570 oappend (names[reg]);
11571 }
11572
11573 static void
11574 OP_E_memory (int bytemode, int sizeflag)
11575 {
11576 bfd_vma disp = 0;
11577 int add = (rex & REX_B) ? 8 : 0;
11578 int riprel = 0;
11579 int shift;
11580
11581 if (vex.evex)
11582 {
11583 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11584 if (vex.b
11585 && bytemode != x_mode
11586 && bytemode != xmmq_mode
11587 && bytemode != evex_half_bcst_xmmq_mode)
11588 {
11589 BadOp ();
11590 return;
11591 }
11592 switch (bytemode)
11593 {
11594 case dqw_mode:
11595 case dw_mode:
11596 case xmm_mw_mode:
11597 shift = 1;
11598 break;
11599 case dqb_mode:
11600 case db_mode:
11601 case xmm_mb_mode:
11602 shift = 0;
11603 break;
11604 case dq_mode:
11605 if (address_mode != mode_64bit)
11606 {
11607 case dqd_mode:
11608 case xmm_md_mode:
11609 case d_mode:
11610 case d_swap_mode:
11611 shift = 2;
11612 break;
11613 }
11614 /* fall through */
11615 case vex_scalar_w_dq_mode:
11616 case vex_vsib_d_w_dq_mode:
11617 case vex_vsib_d_w_d_mode:
11618 case vex_vsib_q_w_dq_mode:
11619 case vex_vsib_q_w_d_mode:
11620 case evex_x_gscat_mode:
11621 shift = vex.w ? 3 : 2;
11622 break;
11623 case x_mode:
11624 case evex_half_bcst_xmmq_mode:
11625 case xmmq_mode:
11626 if (vex.b)
11627 {
11628 shift = vex.w ? 3 : 2;
11629 break;
11630 }
11631 /* Fall through. */
11632 case xmmqd_mode:
11633 case xmmdw_mode:
11634 case ymmq_mode:
11635 case evex_x_nobcst_mode:
11636 case x_swap_mode:
11637 switch (vex.length)
11638 {
11639 case 128:
11640 shift = 4;
11641 break;
11642 case 256:
11643 shift = 5;
11644 break;
11645 case 512:
11646 shift = 6;
11647 break;
11648 default:
11649 abort ();
11650 }
11651 /* Make necessary corrections to shift for modes that need it. */
11652 if (bytemode == xmmq_mode
11653 || bytemode == evex_half_bcst_xmmq_mode
11654 || (bytemode == ymmq_mode && vex.length == 128))
11655 shift -= 1;
11656 else if (bytemode == xmmqd_mode)
11657 shift -= 2;
11658 else if (bytemode == xmmdw_mode)
11659 shift -= 3;
11660 break;
11661 case ymm_mode:
11662 shift = 5;
11663 break;
11664 case xmm_mode:
11665 shift = 4;
11666 break;
11667 case xmm_mq_mode:
11668 case q_mode:
11669 case q_swap_mode:
11670 shift = 3;
11671 break;
11672 case bw_unit_mode:
11673 shift = vex.w ? 1 : 0;
11674 break;
11675 default:
11676 abort ();
11677 }
11678 }
11679 else
11680 shift = 0;
11681
11682 USED_REX (REX_B);
11683 if (intel_syntax)
11684 intel_operand_size (bytemode, sizeflag);
11685 append_seg ();
11686
11687 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11688 {
11689 /* 32/64 bit address mode */
11690 int havedisp;
11691 int havesib;
11692 int havebase;
11693 int haveindex;
11694 int needindex;
11695 int needaddr32;
11696 int base, rbase;
11697 int vindex = 0;
11698 int scale = 0;
11699 int addr32flag = !((sizeflag & AFLAG)
11700 || bytemode == v_bnd_mode
11701 || bytemode == v_bndmk_mode
11702 || bytemode == bnd_mode
11703 || bytemode == bnd_swap_mode);
11704 const char **indexes64 = names64;
11705 const char **indexes32 = names32;
11706
11707 havesib = 0;
11708 havebase = 1;
11709 haveindex = 0;
11710 base = modrm.rm;
11711
11712 if (base == 4)
11713 {
11714 havesib = 1;
11715 vindex = sib.index;
11716 USED_REX (REX_X);
11717 if (rex & REX_X)
11718 vindex += 8;
11719 switch (bytemode)
11720 {
11721 case vex_vsib_d_w_dq_mode:
11722 case vex_vsib_d_w_d_mode:
11723 case vex_vsib_q_w_dq_mode:
11724 case vex_vsib_q_w_d_mode:
11725 if (!need_vex)
11726 abort ();
11727 if (vex.evex)
11728 {
11729 if (!vex.v)
11730 vindex += 16;
11731 }
11732
11733 haveindex = 1;
11734 switch (vex.length)
11735 {
11736 case 128:
11737 indexes64 = indexes32 = names_xmm;
11738 break;
11739 case 256:
11740 if (!vex.w
11741 || bytemode == vex_vsib_q_w_dq_mode
11742 || bytemode == vex_vsib_q_w_d_mode)
11743 indexes64 = indexes32 = names_ymm;
11744 else
11745 indexes64 = indexes32 = names_xmm;
11746 break;
11747 case 512:
11748 if (!vex.w
11749 || bytemode == vex_vsib_q_w_dq_mode
11750 || bytemode == vex_vsib_q_w_d_mode)
11751 indexes64 = indexes32 = names_zmm;
11752 else
11753 indexes64 = indexes32 = names_ymm;
11754 break;
11755 default:
11756 abort ();
11757 }
11758 break;
11759 default:
11760 haveindex = vindex != 4;
11761 break;
11762 }
11763 scale = sib.scale;
11764 base = sib.base;
11765 codep++;
11766 }
11767 else
11768 {
11769 /* mandatory non-vector SIB must have sib */
11770 if (bytemode == vex_sibmem_mode)
11771 {
11772 oappend ("(bad)");
11773 return;
11774 }
11775 }
11776 rbase = base + add;
11777
11778 switch (modrm.mod)
11779 {
11780 case 0:
11781 if (base == 5)
11782 {
11783 havebase = 0;
11784 if (address_mode == mode_64bit && !havesib)
11785 riprel = 1;
11786 disp = get32s ();
11787 if (riprel && bytemode == v_bndmk_mode)
11788 {
11789 oappend ("(bad)");
11790 return;
11791 }
11792 }
11793 break;
11794 case 1:
11795 FETCH_DATA (the_info, codep + 1);
11796 disp = *codep++;
11797 if ((disp & 0x80) != 0)
11798 disp -= 0x100;
11799 if (vex.evex && shift > 0)
11800 disp <<= shift;
11801 break;
11802 case 2:
11803 disp = get32s ();
11804 break;
11805 }
11806
11807 needindex = 0;
11808 needaddr32 = 0;
11809 if (havesib
11810 && !havebase
11811 && !haveindex
11812 && address_mode != mode_16bit)
11813 {
11814 if (address_mode == mode_64bit)
11815 {
11816 if (addr32flag)
11817 {
11818 /* Without base nor index registers, zero-extend the
11819 lower 32-bit displacement to 64 bits. */
11820 disp = (unsigned int) disp;
11821 needindex = scale;
11822 }
11823 needaddr32 = 1;
11824 }
11825 else
11826 {
11827 /* In 32-bit mode, we need index register to tell [offset]
11828 from [eiz*1 + offset]. */
11829 needindex = 1;
11830 }
11831 }
11832
11833 havedisp = (havebase
11834 || needindex
11835 || (havesib && (haveindex || scale != 0)));
11836
11837 if (!intel_syntax)
11838 if (modrm.mod != 0 || base == 5)
11839 {
11840 if (havedisp || riprel)
11841 print_displacement (scratchbuf, disp);
11842 else
11843 print_operand_value (scratchbuf, 1, disp);
11844 oappend (scratchbuf);
11845 if (riprel)
11846 {
11847 set_op (disp, 1);
11848 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11849 }
11850 }
11851
11852 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11853 && (address_mode != mode_64bit
11854 || ((bytemode != v_bnd_mode)
11855 && (bytemode != v_bndmk_mode)
11856 && (bytemode != bnd_mode)
11857 && (bytemode != bnd_swap_mode))))
11858 used_prefixes |= PREFIX_ADDR;
11859
11860 if (havedisp || (intel_syntax && riprel))
11861 {
11862 *obufp++ = open_char;
11863 if (intel_syntax && riprel)
11864 {
11865 set_op (disp, 1);
11866 oappend (!addr32flag ? "rip" : "eip");
11867 }
11868 *obufp = '\0';
11869 if (havebase)
11870 oappend (address_mode == mode_64bit && !addr32flag
11871 ? names64[rbase] : names32[rbase]);
11872 if (havesib)
11873 {
11874 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11875 print index to tell base + index from base. */
11876 if (scale != 0
11877 || needindex
11878 || haveindex
11879 || (havebase && base != ESP_REG_NUM))
11880 {
11881 if (!intel_syntax || havebase)
11882 {
11883 *obufp++ = separator_char;
11884 *obufp = '\0';
11885 }
11886 if (haveindex)
11887 oappend (address_mode == mode_64bit && !addr32flag
11888 ? indexes64[vindex] : indexes32[vindex]);
11889 else
11890 oappend (address_mode == mode_64bit && !addr32flag
11891 ? index64 : index32);
11892
11893 *obufp++ = scale_char;
11894 *obufp = '\0';
11895 sprintf (scratchbuf, "%d", 1 << scale);
11896 oappend (scratchbuf);
11897 }
11898 }
11899 if (intel_syntax
11900 && (disp || modrm.mod != 0 || base == 5))
11901 {
11902 if (!havedisp || (bfd_signed_vma) disp >= 0)
11903 {
11904 *obufp++ = '+';
11905 *obufp = '\0';
11906 }
11907 else if (modrm.mod != 1 && disp != -disp)
11908 {
11909 *obufp++ = '-';
11910 *obufp = '\0';
11911 disp = - (bfd_signed_vma) disp;
11912 }
11913
11914 if (havedisp)
11915 print_displacement (scratchbuf, disp);
11916 else
11917 print_operand_value (scratchbuf, 1, disp);
11918 oappend (scratchbuf);
11919 }
11920
11921 *obufp++ = close_char;
11922 *obufp = '\0';
11923 }
11924 else if (intel_syntax)
11925 {
11926 if (modrm.mod != 0 || base == 5)
11927 {
11928 if (!active_seg_prefix)
11929 {
11930 oappend (names_seg[ds_reg - es_reg]);
11931 oappend (":");
11932 }
11933 print_operand_value (scratchbuf, 1, disp);
11934 oappend (scratchbuf);
11935 }
11936 }
11937 }
11938 else if (bytemode == v_bnd_mode
11939 || bytemode == v_bndmk_mode
11940 || bytemode == bnd_mode
11941 || bytemode == bnd_swap_mode)
11942 {
11943 oappend ("(bad)");
11944 return;
11945 }
11946 else
11947 {
11948 /* 16 bit address mode */
11949 used_prefixes |= prefixes & PREFIX_ADDR;
11950 switch (modrm.mod)
11951 {
11952 case 0:
11953 if (modrm.rm == 6)
11954 {
11955 disp = get16 ();
11956 if ((disp & 0x8000) != 0)
11957 disp -= 0x10000;
11958 }
11959 break;
11960 case 1:
11961 FETCH_DATA (the_info, codep + 1);
11962 disp = *codep++;
11963 if ((disp & 0x80) != 0)
11964 disp -= 0x100;
11965 if (vex.evex && shift > 0)
11966 disp <<= shift;
11967 break;
11968 case 2:
11969 disp = get16 ();
11970 if ((disp & 0x8000) != 0)
11971 disp -= 0x10000;
11972 break;
11973 }
11974
11975 if (!intel_syntax)
11976 if (modrm.mod != 0 || modrm.rm == 6)
11977 {
11978 print_displacement (scratchbuf, disp);
11979 oappend (scratchbuf);
11980 }
11981
11982 if (modrm.mod != 0 || modrm.rm != 6)
11983 {
11984 *obufp++ = open_char;
11985 *obufp = '\0';
11986 oappend (index16[modrm.rm]);
11987 if (intel_syntax
11988 && (disp || modrm.mod != 0 || modrm.rm == 6))
11989 {
11990 if ((bfd_signed_vma) disp >= 0)
11991 {
11992 *obufp++ = '+';
11993 *obufp = '\0';
11994 }
11995 else if (modrm.mod != 1)
11996 {
11997 *obufp++ = '-';
11998 *obufp = '\0';
11999 disp = - (bfd_signed_vma) disp;
12000 }
12001
12002 print_displacement (scratchbuf, disp);
12003 oappend (scratchbuf);
12004 }
12005
12006 *obufp++ = close_char;
12007 *obufp = '\0';
12008 }
12009 else if (intel_syntax)
12010 {
12011 if (!active_seg_prefix)
12012 {
12013 oappend (names_seg[ds_reg - es_reg]);
12014 oappend (":");
12015 }
12016 print_operand_value (scratchbuf, 1, disp & 0xffff);
12017 oappend (scratchbuf);
12018 }
12019 }
12020 if (vex.evex && vex.b
12021 && (bytemode == x_mode
12022 || bytemode == xmmq_mode
12023 || bytemode == evex_half_bcst_xmmq_mode))
12024 {
12025 if (vex.w
12026 || bytemode == xmmq_mode
12027 || bytemode == evex_half_bcst_xmmq_mode)
12028 {
12029 switch (vex.length)
12030 {
12031 case 128:
12032 oappend ("{1to2}");
12033 break;
12034 case 256:
12035 oappend ("{1to4}");
12036 break;
12037 case 512:
12038 oappend ("{1to8}");
12039 break;
12040 default:
12041 abort ();
12042 }
12043 }
12044 else
12045 {
12046 switch (vex.length)
12047 {
12048 case 128:
12049 oappend ("{1to4}");
12050 break;
12051 case 256:
12052 oappend ("{1to8}");
12053 break;
12054 case 512:
12055 oappend ("{1to16}");
12056 break;
12057 default:
12058 abort ();
12059 }
12060 }
12061 }
12062 }
12063
12064 static void
12065 OP_E (int bytemode, int sizeflag)
12066 {
12067 /* Skip mod/rm byte. */
12068 MODRM_CHECK;
12069 codep++;
12070
12071 if (modrm.mod == 3)
12072 OP_E_register (bytemode, sizeflag);
12073 else
12074 OP_E_memory (bytemode, sizeflag);
12075 }
12076
12077 static void
12078 OP_G (int bytemode, int sizeflag)
12079 {
12080 int add = 0;
12081 const char **names;
12082 USED_REX (REX_R);
12083 if (rex & REX_R)
12084 add += 8;
12085 switch (bytemode)
12086 {
12087 case b_mode:
12088 if (modrm.reg & 4)
12089 USED_REX (0);
12090 if (rex)
12091 oappend (names8rex[modrm.reg + add]);
12092 else
12093 oappend (names8[modrm.reg + add]);
12094 break;
12095 case w_mode:
12096 oappend (names16[modrm.reg + add]);
12097 break;
12098 case d_mode:
12099 case db_mode:
12100 case dw_mode:
12101 oappend (names32[modrm.reg + add]);
12102 break;
12103 case q_mode:
12104 oappend (names64[modrm.reg + add]);
12105 break;
12106 case bnd_mode:
12107 if (modrm.reg > 0x3)
12108 {
12109 oappend ("(bad)");
12110 return;
12111 }
12112 oappend (names_bnd[modrm.reg]);
12113 break;
12114 case v_mode:
12115 case dq_mode:
12116 case dqb_mode:
12117 case dqd_mode:
12118 case dqw_mode:
12119 case movsxd_mode:
12120 USED_REX (REX_W);
12121 if (rex & REX_W)
12122 oappend (names64[modrm.reg + add]);
12123 else if (bytemode != v_mode && bytemode != movsxd_mode)
12124 oappend (names32[modrm.reg + add]);
12125 else
12126 {
12127 if (sizeflag & DFLAG)
12128 oappend (names32[modrm.reg + add]);
12129 else
12130 oappend (names16[modrm.reg + add]);
12131 used_prefixes |= (prefixes & PREFIX_DATA);
12132 }
12133 break;
12134 case va_mode:
12135 names = (address_mode == mode_64bit
12136 ? names64 : names32);
12137 if (!(prefixes & PREFIX_ADDR))
12138 {
12139 if (address_mode == mode_16bit)
12140 names = names16;
12141 }
12142 else
12143 {
12144 /* Remove "addr16/addr32". */
12145 all_prefixes[last_addr_prefix] = 0;
12146 names = (address_mode != mode_32bit
12147 ? names32 : names16);
12148 used_prefixes |= PREFIX_ADDR;
12149 }
12150 oappend (names[modrm.reg + add]);
12151 break;
12152 case m_mode:
12153 if (address_mode == mode_64bit)
12154 oappend (names64[modrm.reg + add]);
12155 else
12156 oappend (names32[modrm.reg + add]);
12157 break;
12158 case mask_bd_mode:
12159 case mask_mode:
12160 if ((modrm.reg + add) > 0x7)
12161 {
12162 oappend ("(bad)");
12163 return;
12164 }
12165 oappend (names_mask[modrm.reg + add]);
12166 break;
12167 default:
12168 oappend (INTERNAL_DISASSEMBLER_ERROR);
12169 break;
12170 }
12171 }
12172
12173 static bfd_vma
12174 get64 (void)
12175 {
12176 bfd_vma x;
12177 #ifdef BFD64
12178 unsigned int a;
12179 unsigned int b;
12180
12181 FETCH_DATA (the_info, codep + 8);
12182 a = *codep++ & 0xff;
12183 a |= (*codep++ & 0xff) << 8;
12184 a |= (*codep++ & 0xff) << 16;
12185 a |= (*codep++ & 0xffu) << 24;
12186 b = *codep++ & 0xff;
12187 b |= (*codep++ & 0xff) << 8;
12188 b |= (*codep++ & 0xff) << 16;
12189 b |= (*codep++ & 0xffu) << 24;
12190 x = a + ((bfd_vma) b << 32);
12191 #else
12192 abort ();
12193 x = 0;
12194 #endif
12195 return x;
12196 }
12197
12198 static bfd_signed_vma
12199 get32 (void)
12200 {
12201 bfd_signed_vma x = 0;
12202
12203 FETCH_DATA (the_info, codep + 4);
12204 x = *codep++ & (bfd_signed_vma) 0xff;
12205 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12206 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12207 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12208 return x;
12209 }
12210
12211 static bfd_signed_vma
12212 get32s (void)
12213 {
12214 bfd_signed_vma x = 0;
12215
12216 FETCH_DATA (the_info, codep + 4);
12217 x = *codep++ & (bfd_signed_vma) 0xff;
12218 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12219 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12220 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12221
12222 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12223
12224 return x;
12225 }
12226
12227 static int
12228 get16 (void)
12229 {
12230 int x = 0;
12231
12232 FETCH_DATA (the_info, codep + 2);
12233 x = *codep++ & 0xff;
12234 x |= (*codep++ & 0xff) << 8;
12235 return x;
12236 }
12237
12238 static void
12239 set_op (bfd_vma op, int riprel)
12240 {
12241 op_index[op_ad] = op_ad;
12242 if (address_mode == mode_64bit)
12243 {
12244 op_address[op_ad] = op;
12245 op_riprel[op_ad] = riprel;
12246 }
12247 else
12248 {
12249 /* Mask to get a 32-bit address. */
12250 op_address[op_ad] = op & 0xffffffff;
12251 op_riprel[op_ad] = riprel & 0xffffffff;
12252 }
12253 }
12254
12255 static void
12256 OP_REG (int code, int sizeflag)
12257 {
12258 const char *s;
12259 int add;
12260
12261 switch (code)
12262 {
12263 case es_reg: case ss_reg: case cs_reg:
12264 case ds_reg: case fs_reg: case gs_reg:
12265 oappend (names_seg[code - es_reg]);
12266 return;
12267 }
12268
12269 USED_REX (REX_B);
12270 if (rex & REX_B)
12271 add = 8;
12272 else
12273 add = 0;
12274
12275 switch (code)
12276 {
12277 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12278 case sp_reg: case bp_reg: case si_reg: case di_reg:
12279 s = names16[code - ax_reg + add];
12280 break;
12281 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12282 USED_REX (0);
12283 /* Fall through. */
12284 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12285 if (rex)
12286 s = names8rex[code - al_reg + add];
12287 else
12288 s = names8[code - al_reg];
12289 break;
12290 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12291 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12292 if (address_mode == mode_64bit
12293 && ((sizeflag & DFLAG) || (rex & REX_W)))
12294 {
12295 s = names64[code - rAX_reg + add];
12296 break;
12297 }
12298 code += eAX_reg - rAX_reg;
12299 /* Fall through. */
12300 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12301 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12302 USED_REX (REX_W);
12303 if (rex & REX_W)
12304 s = names64[code - eAX_reg + add];
12305 else
12306 {
12307 if (sizeflag & DFLAG)
12308 s = names32[code - eAX_reg + add];
12309 else
12310 s = names16[code - eAX_reg + add];
12311 used_prefixes |= (prefixes & PREFIX_DATA);
12312 }
12313 break;
12314 default:
12315 s = INTERNAL_DISASSEMBLER_ERROR;
12316 break;
12317 }
12318 oappend (s);
12319 }
12320
12321 static void
12322 OP_IMREG (int code, int sizeflag)
12323 {
12324 const char *s;
12325
12326 switch (code)
12327 {
12328 case indir_dx_reg:
12329 if (intel_syntax)
12330 s = "dx";
12331 else
12332 s = "(%dx)";
12333 break;
12334 case al_reg: case cl_reg:
12335 s = names8[code - al_reg];
12336 break;
12337 case eAX_reg:
12338 USED_REX (REX_W);
12339 if (rex & REX_W)
12340 {
12341 s = *names64;
12342 break;
12343 }
12344 /* Fall through. */
12345 case z_mode_ax_reg:
12346 if ((rex & REX_W) || (sizeflag & DFLAG))
12347 s = *names32;
12348 else
12349 s = *names16;
12350 if (!(rex & REX_W))
12351 used_prefixes |= (prefixes & PREFIX_DATA);
12352 break;
12353 default:
12354 s = INTERNAL_DISASSEMBLER_ERROR;
12355 break;
12356 }
12357 oappend (s);
12358 }
12359
12360 static void
12361 OP_I (int bytemode, int sizeflag)
12362 {
12363 bfd_signed_vma op;
12364 bfd_signed_vma mask = -1;
12365
12366 switch (bytemode)
12367 {
12368 case b_mode:
12369 FETCH_DATA (the_info, codep + 1);
12370 op = *codep++;
12371 mask = 0xff;
12372 break;
12373 case v_mode:
12374 USED_REX (REX_W);
12375 if (rex & REX_W)
12376 op = get32s ();
12377 else
12378 {
12379 if (sizeflag & DFLAG)
12380 {
12381 op = get32 ();
12382 mask = 0xffffffff;
12383 }
12384 else
12385 {
12386 op = get16 ();
12387 mask = 0xfffff;
12388 }
12389 used_prefixes |= (prefixes & PREFIX_DATA);
12390 }
12391 break;
12392 case d_mode:
12393 mask = 0xffffffff;
12394 op = get32 ();
12395 break;
12396 case w_mode:
12397 mask = 0xfffff;
12398 op = get16 ();
12399 break;
12400 case const_1_mode:
12401 if (intel_syntax)
12402 oappend ("1");
12403 return;
12404 default:
12405 oappend (INTERNAL_DISASSEMBLER_ERROR);
12406 return;
12407 }
12408
12409 op &= mask;
12410 scratchbuf[0] = '$';
12411 print_operand_value (scratchbuf + 1, 1, op);
12412 oappend_maybe_intel (scratchbuf);
12413 scratchbuf[0] = '\0';
12414 }
12415
12416 static void
12417 OP_I64 (int bytemode, int sizeflag)
12418 {
12419 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12420 {
12421 OP_I (bytemode, sizeflag);
12422 return;
12423 }
12424
12425 USED_REX (REX_W);
12426
12427 scratchbuf[0] = '$';
12428 print_operand_value (scratchbuf + 1, 1, get64 ());
12429 oappend_maybe_intel (scratchbuf);
12430 scratchbuf[0] = '\0';
12431 }
12432
12433 static void
12434 OP_sI (int bytemode, int sizeflag)
12435 {
12436 bfd_signed_vma op;
12437
12438 switch (bytemode)
12439 {
12440 case b_mode:
12441 case b_T_mode:
12442 FETCH_DATA (the_info, codep + 1);
12443 op = *codep++;
12444 if ((op & 0x80) != 0)
12445 op -= 0x100;
12446 if (bytemode == b_T_mode)
12447 {
12448 if (address_mode != mode_64bit
12449 || !((sizeflag & DFLAG) || (rex & REX_W)))
12450 {
12451 /* The operand-size prefix is overridden by a REX prefix. */
12452 if ((sizeflag & DFLAG) || (rex & REX_W))
12453 op &= 0xffffffff;
12454 else
12455 op &= 0xffff;
12456 }
12457 }
12458 else
12459 {
12460 if (!(rex & REX_W))
12461 {
12462 if (sizeflag & DFLAG)
12463 op &= 0xffffffff;
12464 else
12465 op &= 0xffff;
12466 }
12467 }
12468 break;
12469 case v_mode:
12470 /* The operand-size prefix is overridden by a REX prefix. */
12471 if ((sizeflag & DFLAG) || (rex & REX_W))
12472 op = get32s ();
12473 else
12474 op = get16 ();
12475 break;
12476 default:
12477 oappend (INTERNAL_DISASSEMBLER_ERROR);
12478 return;
12479 }
12480
12481 scratchbuf[0] = '$';
12482 print_operand_value (scratchbuf + 1, 1, op);
12483 oappend_maybe_intel (scratchbuf);
12484 }
12485
12486 static void
12487 OP_J (int bytemode, int sizeflag)
12488 {
12489 bfd_vma disp;
12490 bfd_vma mask = -1;
12491 bfd_vma segment = 0;
12492
12493 switch (bytemode)
12494 {
12495 case b_mode:
12496 FETCH_DATA (the_info, codep + 1);
12497 disp = *codep++;
12498 if ((disp & 0x80) != 0)
12499 disp -= 0x100;
12500 break;
12501 case v_mode:
12502 case dqw_mode:
12503 if ((sizeflag & DFLAG)
12504 || (address_mode == mode_64bit
12505 && ((isa64 == intel64 && bytemode != dqw_mode)
12506 || (rex & REX_W))))
12507 disp = get32s ();
12508 else
12509 {
12510 disp = get16 ();
12511 if ((disp & 0x8000) != 0)
12512 disp -= 0x10000;
12513 /* In 16bit mode, address is wrapped around at 64k within
12514 the same segment. Otherwise, a data16 prefix on a jump
12515 instruction means that the pc is masked to 16 bits after
12516 the displacement is added! */
12517 mask = 0xffff;
12518 if ((prefixes & PREFIX_DATA) == 0)
12519 segment = ((start_pc + (codep - start_codep))
12520 & ~((bfd_vma) 0xffff));
12521 }
12522 if (address_mode != mode_64bit
12523 || (isa64 != intel64 && !(rex & REX_W)))
12524 used_prefixes |= (prefixes & PREFIX_DATA);
12525 break;
12526 default:
12527 oappend (INTERNAL_DISASSEMBLER_ERROR);
12528 return;
12529 }
12530 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12531 set_op (disp, 0);
12532 print_operand_value (scratchbuf, 1, disp);
12533 oappend (scratchbuf);
12534 }
12535
12536 static void
12537 OP_SEG (int bytemode, int sizeflag)
12538 {
12539 if (bytemode == w_mode)
12540 oappend (names_seg[modrm.reg]);
12541 else
12542 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12543 }
12544
12545 static void
12546 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12547 {
12548 int seg, offset;
12549
12550 if (sizeflag & DFLAG)
12551 {
12552 offset = get32 ();
12553 seg = get16 ();
12554 }
12555 else
12556 {
12557 offset = get16 ();
12558 seg = get16 ();
12559 }
12560 used_prefixes |= (prefixes & PREFIX_DATA);
12561 if (intel_syntax)
12562 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12563 else
12564 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12565 oappend (scratchbuf);
12566 }
12567
12568 static void
12569 OP_OFF (int bytemode, int sizeflag)
12570 {
12571 bfd_vma off;
12572
12573 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12574 intel_operand_size (bytemode, sizeflag);
12575 append_seg ();
12576
12577 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12578 off = get32 ();
12579 else
12580 off = get16 ();
12581
12582 if (intel_syntax)
12583 {
12584 if (!active_seg_prefix)
12585 {
12586 oappend (names_seg[ds_reg - es_reg]);
12587 oappend (":");
12588 }
12589 }
12590 print_operand_value (scratchbuf, 1, off);
12591 oappend (scratchbuf);
12592 }
12593
12594 static void
12595 OP_OFF64 (int bytemode, int sizeflag)
12596 {
12597 bfd_vma off;
12598
12599 if (address_mode != mode_64bit
12600 || (prefixes & PREFIX_ADDR))
12601 {
12602 OP_OFF (bytemode, sizeflag);
12603 return;
12604 }
12605
12606 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12607 intel_operand_size (bytemode, sizeflag);
12608 append_seg ();
12609
12610 off = get64 ();
12611
12612 if (intel_syntax)
12613 {
12614 if (!active_seg_prefix)
12615 {
12616 oappend (names_seg[ds_reg - es_reg]);
12617 oappend (":");
12618 }
12619 }
12620 print_operand_value (scratchbuf, 1, off);
12621 oappend (scratchbuf);
12622 }
12623
12624 static void
12625 ptr_reg (int code, int sizeflag)
12626 {
12627 const char *s;
12628
12629 *obufp++ = open_char;
12630 used_prefixes |= (prefixes & PREFIX_ADDR);
12631 if (address_mode == mode_64bit)
12632 {
12633 if (!(sizeflag & AFLAG))
12634 s = names32[code - eAX_reg];
12635 else
12636 s = names64[code - eAX_reg];
12637 }
12638 else if (sizeflag & AFLAG)
12639 s = names32[code - eAX_reg];
12640 else
12641 s = names16[code - eAX_reg];
12642 oappend (s);
12643 *obufp++ = close_char;
12644 *obufp = 0;
12645 }
12646
12647 static void
12648 OP_ESreg (int code, int sizeflag)
12649 {
12650 if (intel_syntax)
12651 {
12652 switch (codep[-1])
12653 {
12654 case 0x6d: /* insw/insl */
12655 intel_operand_size (z_mode, sizeflag);
12656 break;
12657 case 0xa5: /* movsw/movsl/movsq */
12658 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12659 case 0xab: /* stosw/stosl */
12660 case 0xaf: /* scasw/scasl */
12661 intel_operand_size (v_mode, sizeflag);
12662 break;
12663 default:
12664 intel_operand_size (b_mode, sizeflag);
12665 }
12666 }
12667 oappend_maybe_intel ("%es:");
12668 ptr_reg (code, sizeflag);
12669 }
12670
12671 static void
12672 OP_DSreg (int code, int sizeflag)
12673 {
12674 if (intel_syntax)
12675 {
12676 switch (codep[-1])
12677 {
12678 case 0x6f: /* outsw/outsl */
12679 intel_operand_size (z_mode, sizeflag);
12680 break;
12681 case 0xa5: /* movsw/movsl/movsq */
12682 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12683 case 0xad: /* lodsw/lodsl/lodsq */
12684 intel_operand_size (v_mode, sizeflag);
12685 break;
12686 default:
12687 intel_operand_size (b_mode, sizeflag);
12688 }
12689 }
12690 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12691 default segment register DS is printed. */
12692 if (!active_seg_prefix)
12693 active_seg_prefix = PREFIX_DS;
12694 append_seg ();
12695 ptr_reg (code, sizeflag);
12696 }
12697
12698 static void
12699 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12700 {
12701 int add;
12702 if (rex & REX_R)
12703 {
12704 USED_REX (REX_R);
12705 add = 8;
12706 }
12707 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12708 {
12709 all_prefixes[last_lock_prefix] = 0;
12710 used_prefixes |= PREFIX_LOCK;
12711 add = 8;
12712 }
12713 else
12714 add = 0;
12715 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12716 oappend_maybe_intel (scratchbuf);
12717 }
12718
12719 static void
12720 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12721 {
12722 int add;
12723 USED_REX (REX_R);
12724 if (rex & REX_R)
12725 add = 8;
12726 else
12727 add = 0;
12728 if (intel_syntax)
12729 sprintf (scratchbuf, "dr%d", modrm.reg + add);
12730 else
12731 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12732 oappend (scratchbuf);
12733 }
12734
12735 static void
12736 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12737 {
12738 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12739 oappend_maybe_intel (scratchbuf);
12740 }
12741
12742 static void
12743 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12744 {
12745 int reg = modrm.reg;
12746 const char **names;
12747
12748 used_prefixes |= (prefixes & PREFIX_DATA);
12749 if (prefixes & PREFIX_DATA)
12750 {
12751 names = names_xmm;
12752 USED_REX (REX_R);
12753 if (rex & REX_R)
12754 reg += 8;
12755 }
12756 else
12757 names = names_mm;
12758 oappend (names[reg]);
12759 }
12760
12761 static void
12762 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12763 {
12764 int reg = modrm.reg;
12765 const char **names;
12766
12767 USED_REX (REX_R);
12768 if (rex & REX_R)
12769 reg += 8;
12770 if (vex.evex)
12771 {
12772 if (!vex.r)
12773 reg += 16;
12774 }
12775
12776 if (need_vex
12777 && bytemode != xmm_mode
12778 && bytemode != xmmq_mode
12779 && bytemode != evex_half_bcst_xmmq_mode
12780 && bytemode != ymm_mode
12781 && bytemode != tmm_mode
12782 && bytemode != scalar_mode)
12783 {
12784 switch (vex.length)
12785 {
12786 case 128:
12787 names = names_xmm;
12788 break;
12789 case 256:
12790 if (vex.w
12791 || (bytemode != vex_vsib_q_w_dq_mode
12792 && bytemode != vex_vsib_q_w_d_mode))
12793 names = names_ymm;
12794 else
12795 names = names_xmm;
12796 break;
12797 case 512:
12798 names = names_zmm;
12799 break;
12800 default:
12801 abort ();
12802 }
12803 }
12804 else if (bytemode == xmmq_mode
12805 || bytemode == evex_half_bcst_xmmq_mode)
12806 {
12807 switch (vex.length)
12808 {
12809 case 128:
12810 case 256:
12811 names = names_xmm;
12812 break;
12813 case 512:
12814 names = names_ymm;
12815 break;
12816 default:
12817 abort ();
12818 }
12819 }
12820 else if (bytemode == tmm_mode)
12821 {
12822 modrm.reg = reg;
12823 if (reg >= 8)
12824 {
12825 oappend ("(bad)");
12826 return;
12827 }
12828 names = names_tmm;
12829 }
12830 else if (bytemode == ymm_mode)
12831 names = names_ymm;
12832 else
12833 names = names_xmm;
12834 oappend (names[reg]);
12835 }
12836
12837 static void
12838 OP_EM (int bytemode, int sizeflag)
12839 {
12840 int reg;
12841 const char **names;
12842
12843 if (modrm.mod != 3)
12844 {
12845 if (intel_syntax
12846 && (bytemode == v_mode || bytemode == v_swap_mode))
12847 {
12848 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12849 used_prefixes |= (prefixes & PREFIX_DATA);
12850 }
12851 OP_E (bytemode, sizeflag);
12852 return;
12853 }
12854
12855 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12856 swap_operand ();
12857
12858 /* Skip mod/rm byte. */
12859 MODRM_CHECK;
12860 codep++;
12861 used_prefixes |= (prefixes & PREFIX_DATA);
12862 reg = modrm.rm;
12863 if (prefixes & PREFIX_DATA)
12864 {
12865 names = names_xmm;
12866 USED_REX (REX_B);
12867 if (rex & REX_B)
12868 reg += 8;
12869 }
12870 else
12871 names = names_mm;
12872 oappend (names[reg]);
12873 }
12874
12875 /* cvt* are the only instructions in sse2 which have
12876 both SSE and MMX operands and also have 0x66 prefix
12877 in their opcode. 0x66 was originally used to differentiate
12878 between SSE and MMX instruction(operands). So we have to handle the
12879 cvt* separately using OP_EMC and OP_MXC */
12880 static void
12881 OP_EMC (int bytemode, int sizeflag)
12882 {
12883 if (modrm.mod != 3)
12884 {
12885 if (intel_syntax && bytemode == v_mode)
12886 {
12887 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12888 used_prefixes |= (prefixes & PREFIX_DATA);
12889 }
12890 OP_E (bytemode, sizeflag);
12891 return;
12892 }
12893
12894 /* Skip mod/rm byte. */
12895 MODRM_CHECK;
12896 codep++;
12897 used_prefixes |= (prefixes & PREFIX_DATA);
12898 oappend (names_mm[modrm.rm]);
12899 }
12900
12901 static void
12902 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12903 {
12904 used_prefixes |= (prefixes & PREFIX_DATA);
12905 oappend (names_mm[modrm.reg]);
12906 }
12907
12908 static void
12909 OP_EX (int bytemode, int sizeflag)
12910 {
12911 int reg;
12912 const char **names;
12913
12914 /* Skip mod/rm byte. */
12915 MODRM_CHECK;
12916 codep++;
12917
12918 if (modrm.mod != 3)
12919 {
12920 OP_E_memory (bytemode, sizeflag);
12921 return;
12922 }
12923
12924 reg = modrm.rm;
12925 USED_REX (REX_B);
12926 if (rex & REX_B)
12927 reg += 8;
12928 if (vex.evex)
12929 {
12930 USED_REX (REX_X);
12931 if ((rex & REX_X))
12932 reg += 16;
12933 }
12934
12935 if ((sizeflag & SUFFIX_ALWAYS)
12936 && (bytemode == x_swap_mode
12937 || bytemode == d_swap_mode
12938 || bytemode == q_swap_mode))
12939 swap_operand ();
12940
12941 if (need_vex
12942 && bytemode != xmm_mode
12943 && bytemode != xmmdw_mode
12944 && bytemode != xmmqd_mode
12945 && bytemode != xmm_mb_mode
12946 && bytemode != xmm_mw_mode
12947 && bytemode != xmm_md_mode
12948 && bytemode != xmm_mq_mode
12949 && bytemode != xmmq_mode
12950 && bytemode != evex_half_bcst_xmmq_mode
12951 && bytemode != ymm_mode
12952 && bytemode != tmm_mode
12953 && bytemode != vex_scalar_w_dq_mode)
12954 {
12955 switch (vex.length)
12956 {
12957 case 128:
12958 names = names_xmm;
12959 break;
12960 case 256:
12961 names = names_ymm;
12962 break;
12963 case 512:
12964 names = names_zmm;
12965 break;
12966 default:
12967 abort ();
12968 }
12969 }
12970 else if (bytemode == xmmq_mode
12971 || bytemode == evex_half_bcst_xmmq_mode)
12972 {
12973 switch (vex.length)
12974 {
12975 case 128:
12976 case 256:
12977 names = names_xmm;
12978 break;
12979 case 512:
12980 names = names_ymm;
12981 break;
12982 default:
12983 abort ();
12984 }
12985 }
12986 else if (bytemode == tmm_mode)
12987 {
12988 modrm.rm = reg;
12989 if (reg >= 8)
12990 {
12991 oappend ("(bad)");
12992 return;
12993 }
12994 names = names_tmm;
12995 }
12996 else if (bytemode == ymm_mode)
12997 names = names_ymm;
12998 else
12999 names = names_xmm;
13000 oappend (names[reg]);
13001 }
13002
13003 static void
13004 OP_MS (int bytemode, int sizeflag)
13005 {
13006 if (modrm.mod == 3)
13007 OP_EM (bytemode, sizeflag);
13008 else
13009 BadOp ();
13010 }
13011
13012 static void
13013 OP_XS (int bytemode, int sizeflag)
13014 {
13015 if (modrm.mod == 3)
13016 OP_EX (bytemode, sizeflag);
13017 else
13018 BadOp ();
13019 }
13020
13021 static void
13022 OP_M (int bytemode, int sizeflag)
13023 {
13024 if (modrm.mod == 3)
13025 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13026 BadOp ();
13027 else
13028 OP_E (bytemode, sizeflag);
13029 }
13030
13031 static void
13032 OP_0f07 (int bytemode, int sizeflag)
13033 {
13034 if (modrm.mod != 3 || modrm.rm != 0)
13035 BadOp ();
13036 else
13037 OP_E (bytemode, sizeflag);
13038 }
13039
13040 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13041 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13042
13043 static void
13044 NOP_Fixup1 (int bytemode, int sizeflag)
13045 {
13046 if ((prefixes & PREFIX_DATA) != 0
13047 || (rex != 0
13048 && rex != 0x48
13049 && address_mode == mode_64bit))
13050 OP_REG (bytemode, sizeflag);
13051 else
13052 strcpy (obuf, "nop");
13053 }
13054
13055 static void
13056 NOP_Fixup2 (int bytemode, int sizeflag)
13057 {
13058 if ((prefixes & PREFIX_DATA) != 0
13059 || (rex != 0
13060 && rex != 0x48
13061 && address_mode == mode_64bit))
13062 OP_IMREG (bytemode, sizeflag);
13063 }
13064
13065 static const char *const Suffix3DNow[] = {
13066 /* 00 */ NULL, NULL, NULL, NULL,
13067 /* 04 */ NULL, NULL, NULL, NULL,
13068 /* 08 */ NULL, NULL, NULL, NULL,
13069 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13070 /* 10 */ NULL, NULL, NULL, NULL,
13071 /* 14 */ NULL, NULL, NULL, NULL,
13072 /* 18 */ NULL, NULL, NULL, NULL,
13073 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13074 /* 20 */ NULL, NULL, NULL, NULL,
13075 /* 24 */ NULL, NULL, NULL, NULL,
13076 /* 28 */ NULL, NULL, NULL, NULL,
13077 /* 2C */ NULL, NULL, NULL, NULL,
13078 /* 30 */ NULL, NULL, NULL, NULL,
13079 /* 34 */ NULL, NULL, NULL, NULL,
13080 /* 38 */ NULL, NULL, NULL, NULL,
13081 /* 3C */ NULL, NULL, NULL, NULL,
13082 /* 40 */ NULL, NULL, NULL, NULL,
13083 /* 44 */ NULL, NULL, NULL, NULL,
13084 /* 48 */ NULL, NULL, NULL, NULL,
13085 /* 4C */ NULL, NULL, NULL, NULL,
13086 /* 50 */ NULL, NULL, NULL, NULL,
13087 /* 54 */ NULL, NULL, NULL, NULL,
13088 /* 58 */ NULL, NULL, NULL, NULL,
13089 /* 5C */ NULL, NULL, NULL, NULL,
13090 /* 60 */ NULL, NULL, NULL, NULL,
13091 /* 64 */ NULL, NULL, NULL, NULL,
13092 /* 68 */ NULL, NULL, NULL, NULL,
13093 /* 6C */ NULL, NULL, NULL, NULL,
13094 /* 70 */ NULL, NULL, NULL, NULL,
13095 /* 74 */ NULL, NULL, NULL, NULL,
13096 /* 78 */ NULL, NULL, NULL, NULL,
13097 /* 7C */ NULL, NULL, NULL, NULL,
13098 /* 80 */ NULL, NULL, NULL, NULL,
13099 /* 84 */ NULL, NULL, NULL, NULL,
13100 /* 88 */ NULL, NULL, "pfnacc", NULL,
13101 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13102 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13103 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13104 /* 98 */ NULL, NULL, "pfsub", NULL,
13105 /* 9C */ NULL, NULL, "pfadd", NULL,
13106 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13107 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13108 /* A8 */ NULL, NULL, "pfsubr", NULL,
13109 /* AC */ NULL, NULL, "pfacc", NULL,
13110 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13111 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13112 /* B8 */ NULL, NULL, NULL, "pswapd",
13113 /* BC */ NULL, NULL, NULL, "pavgusb",
13114 /* C0 */ NULL, NULL, NULL, NULL,
13115 /* C4 */ NULL, NULL, NULL, NULL,
13116 /* C8 */ NULL, NULL, NULL, NULL,
13117 /* CC */ NULL, NULL, NULL, NULL,
13118 /* D0 */ NULL, NULL, NULL, NULL,
13119 /* D4 */ NULL, NULL, NULL, NULL,
13120 /* D8 */ NULL, NULL, NULL, NULL,
13121 /* DC */ NULL, NULL, NULL, NULL,
13122 /* E0 */ NULL, NULL, NULL, NULL,
13123 /* E4 */ NULL, NULL, NULL, NULL,
13124 /* E8 */ NULL, NULL, NULL, NULL,
13125 /* EC */ NULL, NULL, NULL, NULL,
13126 /* F0 */ NULL, NULL, NULL, NULL,
13127 /* F4 */ NULL, NULL, NULL, NULL,
13128 /* F8 */ NULL, NULL, NULL, NULL,
13129 /* FC */ NULL, NULL, NULL, NULL,
13130 };
13131
13132 static void
13133 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13134 {
13135 const char *mnemonic;
13136
13137 FETCH_DATA (the_info, codep + 1);
13138 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13139 place where an 8-bit immediate would normally go. ie. the last
13140 byte of the instruction. */
13141 obufp = mnemonicendp;
13142 mnemonic = Suffix3DNow[*codep++ & 0xff];
13143 if (mnemonic)
13144 oappend (mnemonic);
13145 else
13146 {
13147 /* Since a variable sized modrm/sib chunk is between the start
13148 of the opcode (0x0f0f) and the opcode suffix, we need to do
13149 all the modrm processing first, and don't know until now that
13150 we have a bad opcode. This necessitates some cleaning up. */
13151 op_out[0][0] = '\0';
13152 op_out[1][0] = '\0';
13153 BadOp ();
13154 }
13155 mnemonicendp = obufp;
13156 }
13157
13158 static const struct op simd_cmp_op[] =
13159 {
13160 { STRING_COMMA_LEN ("eq") },
13161 { STRING_COMMA_LEN ("lt") },
13162 { STRING_COMMA_LEN ("le") },
13163 { STRING_COMMA_LEN ("unord") },
13164 { STRING_COMMA_LEN ("neq") },
13165 { STRING_COMMA_LEN ("nlt") },
13166 { STRING_COMMA_LEN ("nle") },
13167 { STRING_COMMA_LEN ("ord") }
13168 };
13169
13170 static const struct op vex_cmp_op[] =
13171 {
13172 { STRING_COMMA_LEN ("eq_uq") },
13173 { STRING_COMMA_LEN ("nge") },
13174 { STRING_COMMA_LEN ("ngt") },
13175 { STRING_COMMA_LEN ("false") },
13176 { STRING_COMMA_LEN ("neq_oq") },
13177 { STRING_COMMA_LEN ("ge") },
13178 { STRING_COMMA_LEN ("gt") },
13179 { STRING_COMMA_LEN ("true") },
13180 { STRING_COMMA_LEN ("eq_os") },
13181 { STRING_COMMA_LEN ("lt_oq") },
13182 { STRING_COMMA_LEN ("le_oq") },
13183 { STRING_COMMA_LEN ("unord_s") },
13184 { STRING_COMMA_LEN ("neq_us") },
13185 { STRING_COMMA_LEN ("nlt_uq") },
13186 { STRING_COMMA_LEN ("nle_uq") },
13187 { STRING_COMMA_LEN ("ord_s") },
13188 { STRING_COMMA_LEN ("eq_us") },
13189 { STRING_COMMA_LEN ("nge_uq") },
13190 { STRING_COMMA_LEN ("ngt_uq") },
13191 { STRING_COMMA_LEN ("false_os") },
13192 { STRING_COMMA_LEN ("neq_os") },
13193 { STRING_COMMA_LEN ("ge_oq") },
13194 { STRING_COMMA_LEN ("gt_oq") },
13195 { STRING_COMMA_LEN ("true_us") },
13196 };
13197
13198 static void
13199 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13200 {
13201 unsigned int cmp_type;
13202
13203 FETCH_DATA (the_info, codep + 1);
13204 cmp_type = *codep++ & 0xff;
13205 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13206 {
13207 char suffix [3];
13208 char *p = mnemonicendp - 2;
13209 suffix[0] = p[0];
13210 suffix[1] = p[1];
13211 suffix[2] = '\0';
13212 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13213 mnemonicendp += simd_cmp_op[cmp_type].len;
13214 }
13215 else if (need_vex
13216 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13217 {
13218 char suffix [3];
13219 char *p = mnemonicendp - 2;
13220 suffix[0] = p[0];
13221 suffix[1] = p[1];
13222 suffix[2] = '\0';
13223 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13224 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13225 mnemonicendp += vex_cmp_op[cmp_type].len;
13226 }
13227 else
13228 {
13229 /* We have a reserved extension byte. Output it directly. */
13230 scratchbuf[0] = '$';
13231 print_operand_value (scratchbuf + 1, 1, cmp_type);
13232 oappend_maybe_intel (scratchbuf);
13233 scratchbuf[0] = '\0';
13234 }
13235 }
13236
13237 static void
13238 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13239 {
13240 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13241 if (!intel_syntax)
13242 {
13243 strcpy (op_out[0], names32[0]);
13244 strcpy (op_out[1], names32[1]);
13245 if (bytemode == eBX_reg)
13246 strcpy (op_out[2], names32[3]);
13247 two_source_ops = 1;
13248 }
13249 /* Skip mod/rm byte. */
13250 MODRM_CHECK;
13251 codep++;
13252 }
13253
13254 static void
13255 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13256 int sizeflag ATTRIBUTE_UNUSED)
13257 {
13258 /* monitor %{e,r,}ax,%ecx,%edx" */
13259 if (!intel_syntax)
13260 {
13261 const char **names = (address_mode == mode_64bit
13262 ? names64 : names32);
13263
13264 if (prefixes & PREFIX_ADDR)
13265 {
13266 /* Remove "addr16/addr32". */
13267 all_prefixes[last_addr_prefix] = 0;
13268 names = (address_mode != mode_32bit
13269 ? names32 : names16);
13270 used_prefixes |= PREFIX_ADDR;
13271 }
13272 else if (address_mode == mode_16bit)
13273 names = names16;
13274 strcpy (op_out[0], names[0]);
13275 strcpy (op_out[1], names32[1]);
13276 strcpy (op_out[2], names32[2]);
13277 two_source_ops = 1;
13278 }
13279 /* Skip mod/rm byte. */
13280 MODRM_CHECK;
13281 codep++;
13282 }
13283
13284 static void
13285 BadOp (void)
13286 {
13287 /* Throw away prefixes and 1st. opcode byte. */
13288 codep = insn_codep + 1;
13289 oappend ("(bad)");
13290 }
13291
13292 static void
13293 REP_Fixup (int bytemode, int sizeflag)
13294 {
13295 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13296 lods and stos. */
13297 if (prefixes & PREFIX_REPZ)
13298 all_prefixes[last_repz_prefix] = REP_PREFIX;
13299
13300 switch (bytemode)
13301 {
13302 case al_reg:
13303 case eAX_reg:
13304 case indir_dx_reg:
13305 OP_IMREG (bytemode, sizeflag);
13306 break;
13307 case eDI_reg:
13308 OP_ESreg (bytemode, sizeflag);
13309 break;
13310 case eSI_reg:
13311 OP_DSreg (bytemode, sizeflag);
13312 break;
13313 default:
13314 abort ();
13315 break;
13316 }
13317 }
13318
13319 static void
13320 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13321 {
13322 if ( isa64 != amd64 )
13323 return;
13324
13325 obufp = obuf;
13326 BadOp ();
13327 mnemonicendp = obufp;
13328 ++codep;
13329 }
13330
13331 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13332 "bnd". */
13333
13334 static void
13335 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13336 {
13337 if (prefixes & PREFIX_REPNZ)
13338 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13339 }
13340
13341 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13342 "notrack". */
13343
13344 static void
13345 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13346 int sizeflag ATTRIBUTE_UNUSED)
13347 {
13348 if (active_seg_prefix == PREFIX_DS
13349 && (address_mode != mode_64bit || last_data_prefix < 0))
13350 {
13351 /* NOTRACK prefix is only valid on indirect branch instructions.
13352 NB: DATA prefix is unsupported for Intel64. */
13353 active_seg_prefix = 0;
13354 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13355 }
13356 }
13357
13358 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13359 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13360 */
13361
13362 static void
13363 HLE_Fixup1 (int bytemode, int sizeflag)
13364 {
13365 if (modrm.mod != 3
13366 && (prefixes & PREFIX_LOCK) != 0)
13367 {
13368 if (prefixes & PREFIX_REPZ)
13369 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13370 if (prefixes & PREFIX_REPNZ)
13371 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13372 }
13373
13374 OP_E (bytemode, sizeflag);
13375 }
13376
13377 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13378 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13379 */
13380
13381 static void
13382 HLE_Fixup2 (int bytemode, int sizeflag)
13383 {
13384 if (modrm.mod != 3)
13385 {
13386 if (prefixes & PREFIX_REPZ)
13387 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13388 if (prefixes & PREFIX_REPNZ)
13389 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13390 }
13391
13392 OP_E (bytemode, sizeflag);
13393 }
13394
13395 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13396 "xrelease" for memory operand. No check for LOCK prefix. */
13397
13398 static void
13399 HLE_Fixup3 (int bytemode, int sizeflag)
13400 {
13401 if (modrm.mod != 3
13402 && last_repz_prefix > last_repnz_prefix
13403 && (prefixes & PREFIX_REPZ) != 0)
13404 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13405
13406 OP_E (bytemode, sizeflag);
13407 }
13408
13409 static void
13410 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13411 {
13412 USED_REX (REX_W);
13413 if (rex & REX_W)
13414 {
13415 /* Change cmpxchg8b to cmpxchg16b. */
13416 char *p = mnemonicendp - 2;
13417 mnemonicendp = stpcpy (p, "16b");
13418 bytemode = o_mode;
13419 }
13420 else if ((prefixes & PREFIX_LOCK) != 0)
13421 {
13422 if (prefixes & PREFIX_REPZ)
13423 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13424 if (prefixes & PREFIX_REPNZ)
13425 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13426 }
13427
13428 OP_M (bytemode, sizeflag);
13429 }
13430
13431 static void
13432 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13433 {
13434 const char **names;
13435
13436 if (need_vex)
13437 {
13438 switch (vex.length)
13439 {
13440 case 128:
13441 names = names_xmm;
13442 break;
13443 case 256:
13444 names = names_ymm;
13445 break;
13446 default:
13447 abort ();
13448 }
13449 }
13450 else
13451 names = names_xmm;
13452 oappend (names[reg]);
13453 }
13454
13455 static void
13456 FXSAVE_Fixup (int bytemode, int sizeflag)
13457 {
13458 /* Add proper suffix to "fxsave" and "fxrstor". */
13459 USED_REX (REX_W);
13460 if (rex & REX_W)
13461 {
13462 char *p = mnemonicendp;
13463 *p++ = '6';
13464 *p++ = '4';
13465 *p = '\0';
13466 mnemonicendp = p;
13467 }
13468 OP_M (bytemode, sizeflag);
13469 }
13470
13471 /* Display the destination register operand for instructions with
13472 VEX. */
13473
13474 static void
13475 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13476 {
13477 int reg;
13478 const char **names;
13479
13480 if (!need_vex)
13481 abort ();
13482
13483 reg = vex.register_specifier;
13484 vex.register_specifier = 0;
13485 if (address_mode != mode_64bit)
13486 reg &= 7;
13487 else if (vex.evex && !vex.v)
13488 reg += 16;
13489
13490 if (bytemode == vex_scalar_mode)
13491 {
13492 oappend (names_xmm[reg]);
13493 return;
13494 }
13495
13496 if (bytemode == tmm_mode)
13497 {
13498 /* All 3 TMM registers must be distinct. */
13499 if (reg >= 8)
13500 oappend ("(bad)");
13501 else
13502 {
13503 /* This must be the 3rd operand. */
13504 if (obufp != op_out[2])
13505 abort ();
13506 oappend (names_tmm[reg]);
13507 if (reg == modrm.reg || reg == modrm.rm)
13508 strcpy (obufp, "/(bad)");
13509 }
13510
13511 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13512 {
13513 if (modrm.reg <= 8
13514 && (modrm.reg == modrm.rm || modrm.reg == reg))
13515 strcat (op_out[0], "/(bad)");
13516 if (modrm.rm <= 8
13517 && (modrm.rm == modrm.reg || modrm.rm == reg))
13518 strcat (op_out[1], "/(bad)");
13519 }
13520
13521 return;
13522 }
13523
13524 switch (vex.length)
13525 {
13526 case 128:
13527 switch (bytemode)
13528 {
13529 case vex_mode:
13530 case vex_vsib_q_w_dq_mode:
13531 case vex_vsib_q_w_d_mode:
13532 names = names_xmm;
13533 break;
13534 case dq_mode:
13535 if (rex & REX_W)
13536 names = names64;
13537 else
13538 names = names32;
13539 break;
13540 case mask_bd_mode:
13541 case mask_mode:
13542 if (reg > 0x7)
13543 {
13544 oappend ("(bad)");
13545 return;
13546 }
13547 names = names_mask;
13548 break;
13549 default:
13550 abort ();
13551 return;
13552 }
13553 break;
13554 case 256:
13555 switch (bytemode)
13556 {
13557 case vex_mode:
13558 names = names_ymm;
13559 break;
13560 case vex_vsib_q_w_dq_mode:
13561 case vex_vsib_q_w_d_mode:
13562 names = vex.w ? names_ymm : names_xmm;
13563 break;
13564 case mask_bd_mode:
13565 case mask_mode:
13566 if (reg > 0x7)
13567 {
13568 oappend ("(bad)");
13569 return;
13570 }
13571 names = names_mask;
13572 break;
13573 default:
13574 /* See PR binutils/20893 for a reproducer. */
13575 oappend ("(bad)");
13576 return;
13577 }
13578 break;
13579 case 512:
13580 names = names_zmm;
13581 break;
13582 default:
13583 abort ();
13584 break;
13585 }
13586 oappend (names[reg]);
13587 }
13588
13589 static void
13590 OP_VexR (int bytemode, int sizeflag)
13591 {
13592 if (modrm.mod == 3)
13593 OP_VEX (bytemode, sizeflag);
13594 }
13595
13596 static void
13597 OP_VexW (int bytemode, int sizeflag)
13598 {
13599 OP_VEX (bytemode, sizeflag);
13600
13601 if (vex.w)
13602 {
13603 /* Swap 2nd and 3rd operands. */
13604 strcpy (scratchbuf, op_out[2]);
13605 strcpy (op_out[2], op_out[1]);
13606 strcpy (op_out[1], scratchbuf);
13607 }
13608 }
13609
13610 static void
13611 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13612 {
13613 int reg;
13614 const char **names = names_xmm;
13615
13616 FETCH_DATA (the_info, codep + 1);
13617 reg = *codep++;
13618
13619 if (bytemode != x_mode && bytemode != scalar_mode)
13620 abort ();
13621
13622 reg >>= 4;
13623 if (address_mode != mode_64bit)
13624 reg &= 7;
13625
13626 if (bytemode == x_mode && vex.length == 256)
13627 names = names_ymm;
13628
13629 oappend (names[reg]);
13630
13631 if (vex.w)
13632 {
13633 /* Swap 3rd and 4th operands. */
13634 strcpy (scratchbuf, op_out[3]);
13635 strcpy (op_out[3], op_out[2]);
13636 strcpy (op_out[2], scratchbuf);
13637 }
13638 }
13639
13640 static void
13641 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13642 int sizeflag ATTRIBUTE_UNUSED)
13643 {
13644 scratchbuf[0] = '$';
13645 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13646 oappend_maybe_intel (scratchbuf);
13647 }
13648
13649 static void
13650 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13651 int sizeflag ATTRIBUTE_UNUSED)
13652 {
13653 unsigned int cmp_type;
13654
13655 if (!vex.evex)
13656 abort ();
13657
13658 FETCH_DATA (the_info, codep + 1);
13659 cmp_type = *codep++ & 0xff;
13660 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13661 If it's the case, print suffix, otherwise - print the immediate. */
13662 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13663 && cmp_type != 3
13664 && cmp_type != 7)
13665 {
13666 char suffix [3];
13667 char *p = mnemonicendp - 2;
13668
13669 /* vpcmp* can have both one- and two-lettered suffix. */
13670 if (p[0] == 'p')
13671 {
13672 p++;
13673 suffix[0] = p[0];
13674 suffix[1] = '\0';
13675 }
13676 else
13677 {
13678 suffix[0] = p[0];
13679 suffix[1] = p[1];
13680 suffix[2] = '\0';
13681 }
13682
13683 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13684 mnemonicendp += simd_cmp_op[cmp_type].len;
13685 }
13686 else
13687 {
13688 /* We have a reserved extension byte. Output it directly. */
13689 scratchbuf[0] = '$';
13690 print_operand_value (scratchbuf + 1, 1, cmp_type);
13691 oappend_maybe_intel (scratchbuf);
13692 scratchbuf[0] = '\0';
13693 }
13694 }
13695
13696 static const struct op xop_cmp_op[] =
13697 {
13698 { STRING_COMMA_LEN ("lt") },
13699 { STRING_COMMA_LEN ("le") },
13700 { STRING_COMMA_LEN ("gt") },
13701 { STRING_COMMA_LEN ("ge") },
13702 { STRING_COMMA_LEN ("eq") },
13703 { STRING_COMMA_LEN ("neq") },
13704 { STRING_COMMA_LEN ("false") },
13705 { STRING_COMMA_LEN ("true") }
13706 };
13707
13708 static void
13709 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13710 int sizeflag ATTRIBUTE_UNUSED)
13711 {
13712 unsigned int cmp_type;
13713
13714 FETCH_DATA (the_info, codep + 1);
13715 cmp_type = *codep++ & 0xff;
13716 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13717 {
13718 char suffix[3];
13719 char *p = mnemonicendp - 2;
13720
13721 /* vpcom* can have both one- and two-lettered suffix. */
13722 if (p[0] == 'm')
13723 {
13724 p++;
13725 suffix[0] = p[0];
13726 suffix[1] = '\0';
13727 }
13728 else
13729 {
13730 suffix[0] = p[0];
13731 suffix[1] = p[1];
13732 suffix[2] = '\0';
13733 }
13734
13735 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13736 mnemonicendp += xop_cmp_op[cmp_type].len;
13737 }
13738 else
13739 {
13740 /* We have a reserved extension byte. Output it directly. */
13741 scratchbuf[0] = '$';
13742 print_operand_value (scratchbuf + 1, 1, cmp_type);
13743 oappend_maybe_intel (scratchbuf);
13744 scratchbuf[0] = '\0';
13745 }
13746 }
13747
13748 static const struct op pclmul_op[] =
13749 {
13750 { STRING_COMMA_LEN ("lql") },
13751 { STRING_COMMA_LEN ("hql") },
13752 { STRING_COMMA_LEN ("lqh") },
13753 { STRING_COMMA_LEN ("hqh") }
13754 };
13755
13756 static void
13757 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13758 int sizeflag ATTRIBUTE_UNUSED)
13759 {
13760 unsigned int pclmul_type;
13761
13762 FETCH_DATA (the_info, codep + 1);
13763 pclmul_type = *codep++ & 0xff;
13764 switch (pclmul_type)
13765 {
13766 case 0x10:
13767 pclmul_type = 2;
13768 break;
13769 case 0x11:
13770 pclmul_type = 3;
13771 break;
13772 default:
13773 break;
13774 }
13775 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13776 {
13777 char suffix [4];
13778 char *p = mnemonicendp - 3;
13779 suffix[0] = p[0];
13780 suffix[1] = p[1];
13781 suffix[2] = p[2];
13782 suffix[3] = '\0';
13783 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13784 mnemonicendp += pclmul_op[pclmul_type].len;
13785 }
13786 else
13787 {
13788 /* We have a reserved extension byte. Output it directly. */
13789 scratchbuf[0] = '$';
13790 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13791 oappend_maybe_intel (scratchbuf);
13792 scratchbuf[0] = '\0';
13793 }
13794 }
13795
13796 static void
13797 MOVSXD_Fixup (int bytemode, int sizeflag)
13798 {
13799 /* Add proper suffix to "movsxd". */
13800 char *p = mnemonicendp;
13801
13802 switch (bytemode)
13803 {
13804 case movsxd_mode:
13805 if (intel_syntax)
13806 {
13807 *p++ = 'x';
13808 *p++ = 'd';
13809 goto skip;
13810 }
13811
13812 USED_REX (REX_W);
13813 if (rex & REX_W)
13814 {
13815 *p++ = 'l';
13816 *p++ = 'q';
13817 }
13818 else
13819 {
13820 *p++ = 'x';
13821 *p++ = 'd';
13822 }
13823 break;
13824 default:
13825 oappend (INTERNAL_DISASSEMBLER_ERROR);
13826 break;
13827 }
13828
13829 skip:
13830 mnemonicendp = p;
13831 *p = '\0';
13832 OP_E (bytemode, sizeflag);
13833 }
13834
13835 static void
13836 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13837 {
13838 if (!vex.evex
13839 || (bytemode != mask_mode && bytemode != mask_bd_mode))
13840 abort ();
13841
13842 USED_REX (REX_R);
13843 if ((rex & REX_R) != 0 || !vex.r)
13844 {
13845 BadOp ();
13846 return;
13847 }
13848
13849 oappend (names_mask [modrm.reg]);
13850 }
13851
13852 static void
13853 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13854 {
13855 if (modrm.mod == 3 && vex.b)
13856 switch (bytemode)
13857 {
13858 case evex_rounding_64_mode:
13859 if (address_mode != mode_64bit)
13860 {
13861 oappend ("(bad)");
13862 break;
13863 }
13864 /* Fall through. */
13865 case evex_rounding_mode:
13866 oappend (names_rounding[vex.ll]);
13867 break;
13868 case evex_sae_mode:
13869 oappend ("{sae}");
13870 break;
13871 default:
13872 abort ();
13873 break;
13874 }
13875 }
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