opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXw { OP_EX, w_mode }
 380 #define EXd { OP_EX, d_mode }
 381 #define EXdScalar { OP_EX, d_scalar_mode }
 382 #define EXdS { OP_EX, d_swap_mode }
 383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 384 #define EXq { OP_EX, q_mode }
 385 #define EXqScalar { OP_EX, q_scalar_mode }
 386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 387 #define EXqS { OP_EX, q_swap_mode }
 388 #define EXx { OP_EX, x_mode }
 389 #define EXxS { OP_EX, x_swap_mode }
 390 #define EXxmm { OP_EX, xmm_mode }
 391 #define EXymm { OP_EX, ymm_mode }
 392 #define EXxmmq { OP_EX, xmmq_mode }
 393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 396 #define EXxmm_md { OP_EX, xmm_md_mode }
 397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 399 #define EXxmmdw { OP_EX, xmmdw_mode }
 400 #define EXxmmqd { OP_EX, xmmqd_mode }
 401 #define EXymmq { OP_EX, ymmq_mode }
 402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define CMP { CMP_Fixup, 0 }
 412 #define XMM0 { XMM_Fixup, 0 }
 413 #define FXSAVE { FXSAVE_Fixup, 0 }
 414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 416
 417 #define Vex { OP_VEX, vex_mode }
 418 #define VexScalar { OP_VEX, vex_scalar_mode }
 419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 420 #define Vex128 { OP_VEX, vex128_mode }
 421 #define Vex256 { OP_VEX, vex256_mode }
 422 #define VexGdq { OP_VEX, dq_mode }
 423 #define VexI4 { VEXI4_Fixup, 0}
 424 #define EXdVex { OP_EX_Vex, d_mode }
 425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVex { OP_EX_Vex, q_mode }
 428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVex { OP_XMM_Vex, 0 }
 435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 436 #define XMVexW { OP_XMM_VexW, 0 }
 437 #define XMVexI4 { OP_REG_VexI4, x_mode }
 438 #define PCLMUL { PCLMUL_Fixup, 0 }
 439 #define VZERO { VZERO_Fixup, 0 }
 440 #define VCMP { VCMP_Fixup, 0 }
 441 #define VPCMP { VPCMP_Fixup, 0 }
 442
 443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* XMM register or double/quad word memory operand, depending on
 538      VEX.W.  */
 539   xmm_mdq_mode,
 540   /* 16-byte XMM, word, double word or quad word operand.  */
 541   xmmdw_mode,
 542   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 543   xmmqd_mode,
 544   /* 32-byte YMM operand */
 545   ymm_mode,
 546   /* quad word, ymmword or zmmword memory operand.  */
 547   ymmq_mode,
 548   /* 32-byte YMM or 16-byte word operand */
 549   ymmxmm_mode,
 550   /* d_mode in 32bit, q_mode in 64bit mode.  */
 551   m_mode,
 552   /* pair of v_mode operands */
 553   a_mode,
 554   cond_jump_mode,
 555   loop_jcxz_mode,
 556   v_bnd_mode,
 557   /* operand size depends on REX prefixes.  */
 558   dq_mode,
 559   /* registers like dq_mode, memory like w_mode.  */
 560   dqw_mode,
 561   bnd_mode,
 562   /* 4- or 6-byte pointer operand */
 563   f_mode,
 564   const_1_mode,
 565   /* v_mode for indirect branch opcodes.  */
 566   indir_v_mode,
 567   /* v_mode for stack-related opcodes.  */
 568   stack_v_mode,
 569   /* non-quad operand size depends on prefixes */
 570   z_mode,
 571   /* 16-byte operand */
 572   o_mode,
 573   /* registers like dq_mode, memory like b_mode.  */
 574   dqb_mode,
 575   /* registers like d_mode, memory like b_mode.  */
 576   db_mode,
 577   /* registers like d_mode, memory like w_mode.  */
 578   dw_mode,
 579   /* registers like dq_mode, memory like d_mode.  */
 580   dqd_mode,
 581   /* normal vex mode */
 582   vex_mode,
 583   /* 128bit vex mode */
 584   vex128_mode,
 585   /* 256bit vex mode */
 586   vex256_mode,
 587   /* operand size depends on the VEX.W bit.  */
 588   vex_w_dq_mode,
 589
 590   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like d_mode, ignore vector length.  */
 602   d_scalar_mode,
 603   /* like d_swap_mode, ignore vector length.  */
 604   d_scalar_swap_mode,
 605   /* like q_mode, ignore vector length.  */
 606   q_scalar_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* like vex_w_dq_mode, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Supress all exceptions.  */
 617   evex_sae_mode,
 618
 619   /* Mask register operand.  */
 620   mask_mode,
 621   /* Mask register operand.  */
 622   mask_bd_mode,
 623
 624   es_reg,
 625   cs_reg,
 626   ss_reg,
 627   ds_reg,
 628   fs_reg,
 629   gs_reg,
 630
 631   eAX_reg,
 632   eCX_reg,
 633   eDX_reg,
 634   eBX_reg,
 635   eSP_reg,
 636   eBP_reg,
 637   eSI_reg,
 638   eDI_reg,
 639
 640   al_reg,
 641   cl_reg,
 642   dl_reg,
 643   bl_reg,
 644   ah_reg,
 645   ch_reg,
 646   dh_reg,
 647   bh_reg,
 648
 649   ax_reg,
 650   cx_reg,
 651   dx_reg,
 652   bx_reg,
 653   sp_reg,
 654   bp_reg,
 655   si_reg,
 656   di_reg,
 657
 658   rAX_reg,
 659   rCX_reg,
 660   rDX_reg,
 661   rBX_reg,
 662   rSP_reg,
 663   rBP_reg,
 664   rSI_reg,
 665   rDI_reg,
 666
 667   z_mode_ax_reg,
 668   indir_dx_reg
 669 };
 670
 671 enum
 672 {
 673   FLOATCODE = 1,
 674   USE_REG_TABLE,
 675   USE_MOD_TABLE,
 676   USE_RM_TABLE,
 677   USE_PREFIX_TABLE,
 678   USE_X86_64_TABLE,
 679   USE_3BYTE_TABLE,
 680   USE_XOP_8F_TABLE,
 681   USE_VEX_C4_TABLE,
 682   USE_VEX_C5_TABLE,
 683   USE_VEX_LEN_TABLE,
 684   USE_VEX_W_TABLE,
 685   USE_EVEX_TABLE
 686 };
 687
 688 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 689
 690 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 691 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 692 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 693 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 694 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 695 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 696 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 697 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 698 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 699 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 700 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 701 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 702 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 703 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 704 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 705
 706 enum
 707 {
 708   REG_80 = 0,
 709   REG_81,
 710   REG_83,
 711   REG_8F,
 712   REG_C0,
 713   REG_C1,
 714   REG_C6,
 715   REG_C7,
 716   REG_D0,
 717   REG_D1,
 718   REG_D2,
 719   REG_D3,
 720   REG_F6,
 721   REG_F7,
 722   REG_FE,
 723   REG_FF,
 724   REG_0F00,
 725   REG_0F01,
 726   REG_0F0D,
 727   REG_0F18,
 728   REG_0F1E_MOD_3,
 729   REG_0F71,
 730   REG_0F72,
 731   REG_0F73,
 732   REG_0FA6,
 733   REG_0FA7,
 734   REG_0FAE,
 735   REG_0FBA,
 736   REG_0FC7,
 737   REG_VEX_0F71,
 738   REG_VEX_0F72,
 739   REG_VEX_0F73,
 740   REG_VEX_0FAE,
 741   REG_VEX_0F38F3,
 742   REG_XOP_LWPCB,
 743   REG_XOP_LWP,
 744   REG_XOP_TBM_01,
 745   REG_XOP_TBM_02,
 746
 747   REG_EVEX_0F71,
 748   REG_EVEX_0F72,
 749   REG_EVEX_0F73,
 750   REG_EVEX_0F38C6,
 751   REG_EVEX_0F38C7
 752 };
 753
 754 enum
 755 {
 756   MOD_8D = 0,
 757   MOD_C6_REG_7,
 758   MOD_C7_REG_7,
 759   MOD_FF_REG_3,
 760   MOD_FF_REG_5,
 761   MOD_0F01_REG_0,
 762   MOD_0F01_REG_1,
 763   MOD_0F01_REG_2,
 764   MOD_0F01_REG_3,
 765   MOD_0F01_REG_5,
 766   MOD_0F01_REG_7,
 767   MOD_0F12_PREFIX_0,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F1E_PREFIX_1,
 783   MOD_0F24,
 784   MOD_0F26,
 785   MOD_0F2B_PREFIX_0,
 786   MOD_0F2B_PREFIX_1,
 787   MOD_0F2B_PREFIX_2,
 788   MOD_0F2B_PREFIX_3,
 789   MOD_0F51,
 790   MOD_0F71_REG_2,
 791   MOD_0F71_REG_4,
 792   MOD_0F71_REG_6,
 793   MOD_0F72_REG_2,
 794   MOD_0F72_REG_4,
 795   MOD_0F72_REG_6,
 796   MOD_0F73_REG_2,
 797   MOD_0F73_REG_3,
 798   MOD_0F73_REG_6,
 799   MOD_0F73_REG_7,
 800   MOD_0FAE_REG_0,
 801   MOD_0FAE_REG_1,
 802   MOD_0FAE_REG_2,
 803   MOD_0FAE_REG_3,
 804   MOD_0FAE_REG_4,
 805   MOD_0FAE_REG_5,
 806   MOD_0FAE_REG_6,
 807   MOD_0FAE_REG_7,
 808   MOD_0FB2,
 809   MOD_0FB4,
 810   MOD_0FB5,
 811   MOD_0FC3,
 812   MOD_0FC7_REG_3,
 813   MOD_0FC7_REG_4,
 814   MOD_0FC7_REG_5,
 815   MOD_0FC7_REG_6,
 816   MOD_0FC7_REG_7,
 817   MOD_0FD7,
 818   MOD_0FE7_PREFIX_2,
 819   MOD_0FF0_PREFIX_3,
 820   MOD_0F382A_PREFIX_2,
 821   MOD_0F38F5_PREFIX_2,
 822   MOD_0F38F6_PREFIX_0,
 823   MOD_62_32BIT,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_VEX_0F12_PREFIX_0,
 827   MOD_VEX_0F13,
 828   MOD_VEX_0F16_PREFIX_0,
 829   MOD_VEX_0F17,
 830   MOD_VEX_0F2B,
 831   MOD_VEX_W_0_0F41_P_0_LEN_1,
 832   MOD_VEX_W_1_0F41_P_0_LEN_1,
 833   MOD_VEX_W_0_0F41_P_2_LEN_1,
 834   MOD_VEX_W_1_0F41_P_2_LEN_1,
 835   MOD_VEX_W_0_0F42_P_0_LEN_1,
 836   MOD_VEX_W_1_0F42_P_0_LEN_1,
 837   MOD_VEX_W_0_0F42_P_2_LEN_1,
 838   MOD_VEX_W_1_0F42_P_2_LEN_1,
 839   MOD_VEX_W_0_0F44_P_0_LEN_1,
 840   MOD_VEX_W_1_0F44_P_0_LEN_1,
 841   MOD_VEX_W_0_0F44_P_2_LEN_1,
 842   MOD_VEX_W_1_0F44_P_2_LEN_1,
 843   MOD_VEX_W_0_0F45_P_0_LEN_1,
 844   MOD_VEX_W_1_0F45_P_0_LEN_1,
 845   MOD_VEX_W_0_0F45_P_2_LEN_1,
 846   MOD_VEX_W_1_0F45_P_2_LEN_1,
 847   MOD_VEX_W_0_0F46_P_0_LEN_1,
 848   MOD_VEX_W_1_0F46_P_0_LEN_1,
 849   MOD_VEX_W_0_0F46_P_2_LEN_1,
 850   MOD_VEX_W_1_0F46_P_2_LEN_1,
 851   MOD_VEX_W_0_0F47_P_0_LEN_1,
 852   MOD_VEX_W_1_0F47_P_0_LEN_1,
 853   MOD_VEX_W_0_0F47_P_2_LEN_1,
 854   MOD_VEX_W_1_0F47_P_2_LEN_1,
 855   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 856   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 857   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 858   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 859   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 860   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 861   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 862   MOD_VEX_0F50,
 863   MOD_VEX_0F71_REG_2,
 864   MOD_VEX_0F71_REG_4,
 865   MOD_VEX_0F71_REG_6,
 866   MOD_VEX_0F72_REG_2,
 867   MOD_VEX_0F72_REG_4,
 868   MOD_VEX_0F72_REG_6,
 869   MOD_VEX_0F73_REG_2,
 870   MOD_VEX_0F73_REG_3,
 871   MOD_VEX_0F73_REG_6,
 872   MOD_VEX_0F73_REG_7,
 873   MOD_VEX_W_0_0F91_P_0_LEN_0,
 874   MOD_VEX_W_1_0F91_P_0_LEN_0,
 875   MOD_VEX_W_0_0F91_P_2_LEN_0,
 876   MOD_VEX_W_1_0F91_P_2_LEN_0,
 877   MOD_VEX_W_0_0F92_P_0_LEN_0,
 878   MOD_VEX_W_0_0F92_P_2_LEN_0,
 879   MOD_VEX_W_0_0F92_P_3_LEN_0,
 880   MOD_VEX_W_1_0F92_P_3_LEN_0,
 881   MOD_VEX_W_0_0F93_P_0_LEN_0,
 882   MOD_VEX_W_0_0F93_P_2_LEN_0,
 883   MOD_VEX_W_0_0F93_P_3_LEN_0,
 884   MOD_VEX_W_1_0F93_P_3_LEN_0,
 885   MOD_VEX_W_0_0F98_P_0_LEN_0,
 886   MOD_VEX_W_1_0F98_P_0_LEN_0,
 887   MOD_VEX_W_0_0F98_P_2_LEN_0,
 888   MOD_VEX_W_1_0F98_P_2_LEN_0,
 889   MOD_VEX_W_0_0F99_P_0_LEN_0,
 890   MOD_VEX_W_1_0F99_P_0_LEN_0,
 891   MOD_VEX_W_0_0F99_P_2_LEN_0,
 892   MOD_VEX_W_1_0F99_P_2_LEN_0,
 893   MOD_VEX_0FAE_REG_2,
 894   MOD_VEX_0FAE_REG_3,
 895   MOD_VEX_0FD7_PREFIX_2,
 896   MOD_VEX_0FE7_PREFIX_2,
 897   MOD_VEX_0FF0_PREFIX_3,
 898   MOD_VEX_0F381A_PREFIX_2,
 899   MOD_VEX_0F382A_PREFIX_2,
 900   MOD_VEX_0F382C_PREFIX_2,
 901   MOD_VEX_0F382D_PREFIX_2,
 902   MOD_VEX_0F382E_PREFIX_2,
 903   MOD_VEX_0F382F_PREFIX_2,
 904   MOD_VEX_0F385A_PREFIX_2,
 905   MOD_VEX_0F388C_PREFIX_2,
 906   MOD_VEX_0F388E_PREFIX_2,
 907   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 909   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 910   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 911   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 913   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 915
 916   MOD_EVEX_0F10_PREFIX_1,
 917   MOD_EVEX_0F10_PREFIX_3,
 918   MOD_EVEX_0F11_PREFIX_1,
 919   MOD_EVEX_0F11_PREFIX_3,
 920   MOD_EVEX_0F12_PREFIX_0,
 921   MOD_EVEX_0F16_PREFIX_0,
 922   MOD_EVEX_0F38C6_REG_1,
 923   MOD_EVEX_0F38C6_REG_2,
 924   MOD_EVEX_0F38C6_REG_5,
 925   MOD_EVEX_0F38C6_REG_6,
 926   MOD_EVEX_0F38C7_REG_1,
 927   MOD_EVEX_0F38C7_REG_2,
 928   MOD_EVEX_0F38C7_REG_5,
 929   MOD_EVEX_0F38C7_REG_6
 930 };
 931
 932 enum
 933 {
 934   RM_C6_REG_7 = 0,
 935   RM_C7_REG_7,
 936   RM_0F01_REG_0,
 937   RM_0F01_REG_1,
 938   RM_0F01_REG_2,
 939   RM_0F01_REG_3,
 940   RM_0F01_REG_5,
 941   RM_0F01_REG_7,
 942   RM_0F1E_MOD_3_REG_7,
 943   RM_0FAE_REG_5,
 944   RM_0FAE_REG_6,
 945   RM_0FAE_REG_7
 946 };
 947
 948 enum
 949 {
 950   PREFIX_90 = 0,
 951   PREFIX_MOD_0_0F01_REG_5,
 952   PREFIX_MOD_3_0F01_REG_5_RM_1,
 953   PREFIX_MOD_3_0F01_REG_5_RM_2,
 954   PREFIX_0F10,
 955   PREFIX_0F11,
 956   PREFIX_0F12,
 957   PREFIX_0F16,
 958   PREFIX_0F1A,
 959   PREFIX_0F1B,
 960   PREFIX_0F1E,
 961   PREFIX_0F2A,
 962   PREFIX_0F2B,
 963   PREFIX_0F2C,
 964   PREFIX_0F2D,
 965   PREFIX_0F2E,
 966   PREFIX_0F2F,
 967   PREFIX_0F51,
 968   PREFIX_0F52,
 969   PREFIX_0F53,
 970   PREFIX_0F58,
 971   PREFIX_0F59,
 972   PREFIX_0F5A,
 973   PREFIX_0F5B,
 974   PREFIX_0F5C,
 975   PREFIX_0F5D,
 976   PREFIX_0F5E,
 977   PREFIX_0F5F,
 978   PREFIX_0F60,
 979   PREFIX_0F61,
 980   PREFIX_0F62,
 981   PREFIX_0F6C,
 982   PREFIX_0F6D,
 983   PREFIX_0F6F,
 984   PREFIX_0F70,
 985   PREFIX_0F73_REG_3,
 986   PREFIX_0F73_REG_7,
 987   PREFIX_0F78,
 988   PREFIX_0F79,
 989   PREFIX_0F7C,
 990   PREFIX_0F7D,
 991   PREFIX_0F7E,
 992   PREFIX_0F7F,
 993   PREFIX_0FAE_REG_0,
 994   PREFIX_0FAE_REG_1,
 995   PREFIX_0FAE_REG_2,
 996   PREFIX_0FAE_REG_3,
 997   PREFIX_MOD_0_0FAE_REG_4,
 998   PREFIX_MOD_3_0FAE_REG_4,
 999   PREFIX_MOD_0_0FAE_REG_5,
1000   PREFIX_0FAE_REG_6,
1001   PREFIX_0FAE_REG_7,
1002   PREFIX_0FB8,
1003   PREFIX_0FBC,
1004   PREFIX_0FBD,
1005   PREFIX_0FC2,
1006   PREFIX_MOD_0_0FC3,
1007   PREFIX_MOD_0_0FC7_REG_6,
1008   PREFIX_MOD_3_0FC7_REG_6,
1009   PREFIX_MOD_3_0FC7_REG_7,
1010   PREFIX_0FD0,
1011   PREFIX_0FD6,
1012   PREFIX_0FE6,
1013   PREFIX_0FE7,
1014   PREFIX_0FF0,
1015   PREFIX_0FF7,
1016   PREFIX_0F3810,
1017   PREFIX_0F3814,
1018   PREFIX_0F3815,
1019   PREFIX_0F3817,
1020   PREFIX_0F3820,
1021   PREFIX_0F3821,
1022   PREFIX_0F3822,
1023   PREFIX_0F3823,
1024   PREFIX_0F3824,
1025   PREFIX_0F3825,
1026   PREFIX_0F3828,
1027   PREFIX_0F3829,
1028   PREFIX_0F382A,
1029   PREFIX_0F382B,
1030   PREFIX_0F3830,
1031   PREFIX_0F3831,
1032   PREFIX_0F3832,
1033   PREFIX_0F3833,
1034   PREFIX_0F3834,
1035   PREFIX_0F3835,
1036   PREFIX_0F3837,
1037   PREFIX_0F3838,
1038   PREFIX_0F3839,
1039   PREFIX_0F383A,
1040   PREFIX_0F383B,
1041   PREFIX_0F383C,
1042   PREFIX_0F383D,
1043   PREFIX_0F383E,
1044   PREFIX_0F383F,
1045   PREFIX_0F3840,
1046   PREFIX_0F3841,
1047   PREFIX_0F3880,
1048   PREFIX_0F3881,
1049   PREFIX_0F3882,
1050   PREFIX_0F38C8,
1051   PREFIX_0F38C9,
1052   PREFIX_0F38CA,
1053   PREFIX_0F38CB,
1054   PREFIX_0F38CC,
1055   PREFIX_0F38CD,
1056   PREFIX_0F38DB,
1057   PREFIX_0F38DC,
1058   PREFIX_0F38DD,
1059   PREFIX_0F38DE,
1060   PREFIX_0F38DF,
1061   PREFIX_0F38F0,
1062   PREFIX_0F38F1,
1063   PREFIX_0F38F5,
1064   PREFIX_0F38F6,
1065   PREFIX_0F3A08,
1066   PREFIX_0F3A09,
1067   PREFIX_0F3A0A,
1068   PREFIX_0F3A0B,
1069   PREFIX_0F3A0C,
1070   PREFIX_0F3A0D,
1071   PREFIX_0F3A0E,
1072   PREFIX_0F3A14,
1073   PREFIX_0F3A15,
1074   PREFIX_0F3A16,
1075   PREFIX_0F3A17,
1076   PREFIX_0F3A20,
1077   PREFIX_0F3A21,
1078   PREFIX_0F3A22,
1079   PREFIX_0F3A40,
1080   PREFIX_0F3A41,
1081   PREFIX_0F3A42,
1082   PREFIX_0F3A44,
1083   PREFIX_0F3A60,
1084   PREFIX_0F3A61,
1085   PREFIX_0F3A62,
1086   PREFIX_0F3A63,
1087   PREFIX_0F3ACC,
1088   PREFIX_0F3ADF,
1089   PREFIX_VEX_0F10,
1090   PREFIX_VEX_0F11,
1091   PREFIX_VEX_0F12,
1092   PREFIX_VEX_0F16,
1093   PREFIX_VEX_0F2A,
1094   PREFIX_VEX_0F2C,
1095   PREFIX_VEX_0F2D,
1096   PREFIX_VEX_0F2E,
1097   PREFIX_VEX_0F2F,
1098   PREFIX_VEX_0F41,
1099   PREFIX_VEX_0F42,
1100   PREFIX_VEX_0F44,
1101   PREFIX_VEX_0F45,
1102   PREFIX_VEX_0F46,
1103   PREFIX_VEX_0F47,
1104   PREFIX_VEX_0F4A,
1105   PREFIX_VEX_0F4B,
1106   PREFIX_VEX_0F51,
1107   PREFIX_VEX_0F52,
1108   PREFIX_VEX_0F53,
1109   PREFIX_VEX_0F58,
1110   PREFIX_VEX_0F59,
1111   PREFIX_VEX_0F5A,
1112   PREFIX_VEX_0F5B,
1113   PREFIX_VEX_0F5C,
1114   PREFIX_VEX_0F5D,
1115   PREFIX_VEX_0F5E,
1116   PREFIX_VEX_0F5F,
1117   PREFIX_VEX_0F60,
1118   PREFIX_VEX_0F61,
1119   PREFIX_VEX_0F62,
1120   PREFIX_VEX_0F63,
1121   PREFIX_VEX_0F64,
1122   PREFIX_VEX_0F65,
1123   PREFIX_VEX_0F66,
1124   PREFIX_VEX_0F67,
1125   PREFIX_VEX_0F68,
1126   PREFIX_VEX_0F69,
1127   PREFIX_VEX_0F6A,
1128   PREFIX_VEX_0F6B,
1129   PREFIX_VEX_0F6C,
1130   PREFIX_VEX_0F6D,
1131   PREFIX_VEX_0F6E,
1132   PREFIX_VEX_0F6F,
1133   PREFIX_VEX_0F70,
1134   PREFIX_VEX_0F71_REG_2,
1135   PREFIX_VEX_0F71_REG_4,
1136   PREFIX_VEX_0F71_REG_6,
1137   PREFIX_VEX_0F72_REG_2,
1138   PREFIX_VEX_0F72_REG_4,
1139   PREFIX_VEX_0F72_REG_6,
1140   PREFIX_VEX_0F73_REG_2,
1141   PREFIX_VEX_0F73_REG_3,
1142   PREFIX_VEX_0F73_REG_6,
1143   PREFIX_VEX_0F73_REG_7,
1144   PREFIX_VEX_0F74,
1145   PREFIX_VEX_0F75,
1146   PREFIX_VEX_0F76,
1147   PREFIX_VEX_0F77,
1148   PREFIX_VEX_0F7C,
1149   PREFIX_VEX_0F7D,
1150   PREFIX_VEX_0F7E,
1151   PREFIX_VEX_0F7F,
1152   PREFIX_VEX_0F90,
1153   PREFIX_VEX_0F91,
1154   PREFIX_VEX_0F92,
1155   PREFIX_VEX_0F93,
1156   PREFIX_VEX_0F98,
1157   PREFIX_VEX_0F99,
1158   PREFIX_VEX_0FC2,
1159   PREFIX_VEX_0FC4,
1160   PREFIX_VEX_0FC5,
1161   PREFIX_VEX_0FD0,
1162   PREFIX_VEX_0FD1,
1163   PREFIX_VEX_0FD2,
1164   PREFIX_VEX_0FD3,
1165   PREFIX_VEX_0FD4,
1166   PREFIX_VEX_0FD5,
1167   PREFIX_VEX_0FD6,
1168   PREFIX_VEX_0FD7,
1169   PREFIX_VEX_0FD8,
1170   PREFIX_VEX_0FD9,
1171   PREFIX_VEX_0FDA,
1172   PREFIX_VEX_0FDB,
1173   PREFIX_VEX_0FDC,
1174   PREFIX_VEX_0FDD,
1175   PREFIX_VEX_0FDE,
1176   PREFIX_VEX_0FDF,
1177   PREFIX_VEX_0FE0,
1178   PREFIX_VEX_0FE1,
1179   PREFIX_VEX_0FE2,
1180   PREFIX_VEX_0FE3,
1181   PREFIX_VEX_0FE4,
1182   PREFIX_VEX_0FE5,
1183   PREFIX_VEX_0FE6,
1184   PREFIX_VEX_0FE7,
1185   PREFIX_VEX_0FE8,
1186   PREFIX_VEX_0FE9,
1187   PREFIX_VEX_0FEA,
1188   PREFIX_VEX_0FEB,
1189   PREFIX_VEX_0FEC,
1190   PREFIX_VEX_0FED,
1191   PREFIX_VEX_0FEE,
1192   PREFIX_VEX_0FEF,
1193   PREFIX_VEX_0FF0,
1194   PREFIX_VEX_0FF1,
1195   PREFIX_VEX_0FF2,
1196   PREFIX_VEX_0FF3,
1197   PREFIX_VEX_0FF4,
1198   PREFIX_VEX_0FF5,
1199   PREFIX_VEX_0FF6,
1200   PREFIX_VEX_0FF7,
1201   PREFIX_VEX_0FF8,
1202   PREFIX_VEX_0FF9,
1203   PREFIX_VEX_0FFA,
1204   PREFIX_VEX_0FFB,
1205   PREFIX_VEX_0FFC,
1206   PREFIX_VEX_0FFD,
1207   PREFIX_VEX_0FFE,
1208   PREFIX_VEX_0F3800,
1209   PREFIX_VEX_0F3801,
1210   PREFIX_VEX_0F3802,
1211   PREFIX_VEX_0F3803,
1212   PREFIX_VEX_0F3804,
1213   PREFIX_VEX_0F3805,
1214   PREFIX_VEX_0F3806,
1215   PREFIX_VEX_0F3807,
1216   PREFIX_VEX_0F3808,
1217   PREFIX_VEX_0F3809,
1218   PREFIX_VEX_0F380A,
1219   PREFIX_VEX_0F380B,
1220   PREFIX_VEX_0F380C,
1221   PREFIX_VEX_0F380D,
1222   PREFIX_VEX_0F380E,
1223   PREFIX_VEX_0F380F,
1224   PREFIX_VEX_0F3813,
1225   PREFIX_VEX_0F3816,
1226   PREFIX_VEX_0F3817,
1227   PREFIX_VEX_0F3818,
1228   PREFIX_VEX_0F3819,
1229   PREFIX_VEX_0F381A,
1230   PREFIX_VEX_0F381C,
1231   PREFIX_VEX_0F381D,
1232   PREFIX_VEX_0F381E,
1233   PREFIX_VEX_0F3820,
1234   PREFIX_VEX_0F3821,
1235   PREFIX_VEX_0F3822,
1236   PREFIX_VEX_0F3823,
1237   PREFIX_VEX_0F3824,
1238   PREFIX_VEX_0F3825,
1239   PREFIX_VEX_0F3828,
1240   PREFIX_VEX_0F3829,
1241   PREFIX_VEX_0F382A,
1242   PREFIX_VEX_0F382B,
1243   PREFIX_VEX_0F382C,
1244   PREFIX_VEX_0F382D,
1245   PREFIX_VEX_0F382E,
1246   PREFIX_VEX_0F382F,
1247   PREFIX_VEX_0F3830,
1248   PREFIX_VEX_0F3831,
1249   PREFIX_VEX_0F3832,
1250   PREFIX_VEX_0F3833,
1251   PREFIX_VEX_0F3834,
1252   PREFIX_VEX_0F3835,
1253   PREFIX_VEX_0F3836,
1254   PREFIX_VEX_0F3837,
1255   PREFIX_VEX_0F3838,
1256   PREFIX_VEX_0F3839,
1257   PREFIX_VEX_0F383A,
1258   PREFIX_VEX_0F383B,
1259   PREFIX_VEX_0F383C,
1260   PREFIX_VEX_0F383D,
1261   PREFIX_VEX_0F383E,
1262   PREFIX_VEX_0F383F,
1263   PREFIX_VEX_0F3840,
1264   PREFIX_VEX_0F3841,
1265   PREFIX_VEX_0F3845,
1266   PREFIX_VEX_0F3846,
1267   PREFIX_VEX_0F3847,
1268   PREFIX_VEX_0F3858,
1269   PREFIX_VEX_0F3859,
1270   PREFIX_VEX_0F385A,
1271   PREFIX_VEX_0F3878,
1272   PREFIX_VEX_0F3879,
1273   PREFIX_VEX_0F388C,
1274   PREFIX_VEX_0F388E,
1275   PREFIX_VEX_0F3890,
1276   PREFIX_VEX_0F3891,
1277   PREFIX_VEX_0F3892,
1278   PREFIX_VEX_0F3893,
1279   PREFIX_VEX_0F3896,
1280   PREFIX_VEX_0F3897,
1281   PREFIX_VEX_0F3898,
1282   PREFIX_VEX_0F3899,
1283   PREFIX_VEX_0F389A,
1284   PREFIX_VEX_0F389B,
1285   PREFIX_VEX_0F389C,
1286   PREFIX_VEX_0F389D,
1287   PREFIX_VEX_0F389E,
1288   PREFIX_VEX_0F389F,
1289   PREFIX_VEX_0F38A6,
1290   PREFIX_VEX_0F38A7,
1291   PREFIX_VEX_0F38A8,
1292   PREFIX_VEX_0F38A9,
1293   PREFIX_VEX_0F38AA,
1294   PREFIX_VEX_0F38AB,
1295   PREFIX_VEX_0F38AC,
1296   PREFIX_VEX_0F38AD,
1297   PREFIX_VEX_0F38AE,
1298   PREFIX_VEX_0F38AF,
1299   PREFIX_VEX_0F38B6,
1300   PREFIX_VEX_0F38B7,
1301   PREFIX_VEX_0F38B8,
1302   PREFIX_VEX_0F38B9,
1303   PREFIX_VEX_0F38BA,
1304   PREFIX_VEX_0F38BB,
1305   PREFIX_VEX_0F38BC,
1306   PREFIX_VEX_0F38BD,
1307   PREFIX_VEX_0F38BE,
1308   PREFIX_VEX_0F38BF,
1309   PREFIX_VEX_0F38DB,
1310   PREFIX_VEX_0F38DC,
1311   PREFIX_VEX_0F38DD,
1312   PREFIX_VEX_0F38DE,
1313   PREFIX_VEX_0F38DF,
1314   PREFIX_VEX_0F38F2,
1315   PREFIX_VEX_0F38F3_REG_1,
1316   PREFIX_VEX_0F38F3_REG_2,
1317   PREFIX_VEX_0F38F3_REG_3,
1318   PREFIX_VEX_0F38F5,
1319   PREFIX_VEX_0F38F6,
1320   PREFIX_VEX_0F38F7,
1321   PREFIX_VEX_0F3A00,
1322   PREFIX_VEX_0F3A01,
1323   PREFIX_VEX_0F3A02,
1324   PREFIX_VEX_0F3A04,
1325   PREFIX_VEX_0F3A05,
1326   PREFIX_VEX_0F3A06,
1327   PREFIX_VEX_0F3A08,
1328   PREFIX_VEX_0F3A09,
1329   PREFIX_VEX_0F3A0A,
1330   PREFIX_VEX_0F3A0B,
1331   PREFIX_VEX_0F3A0C,
1332   PREFIX_VEX_0F3A0D,
1333   PREFIX_VEX_0F3A0E,
1334   PREFIX_VEX_0F3A0F,
1335   PREFIX_VEX_0F3A14,
1336   PREFIX_VEX_0F3A15,
1337   PREFIX_VEX_0F3A16,
1338   PREFIX_VEX_0F3A17,
1339   PREFIX_VEX_0F3A18,
1340   PREFIX_VEX_0F3A19,
1341   PREFIX_VEX_0F3A1D,
1342   PREFIX_VEX_0F3A20,
1343   PREFIX_VEX_0F3A21,
1344   PREFIX_VEX_0F3A22,
1345   PREFIX_VEX_0F3A30,
1346   PREFIX_VEX_0F3A31,
1347   PREFIX_VEX_0F3A32,
1348   PREFIX_VEX_0F3A33,
1349   PREFIX_VEX_0F3A38,
1350   PREFIX_VEX_0F3A39,
1351   PREFIX_VEX_0F3A40,
1352   PREFIX_VEX_0F3A41,
1353   PREFIX_VEX_0F3A42,
1354   PREFIX_VEX_0F3A44,
1355   PREFIX_VEX_0F3A46,
1356   PREFIX_VEX_0F3A48,
1357   PREFIX_VEX_0F3A49,
1358   PREFIX_VEX_0F3A4A,
1359   PREFIX_VEX_0F3A4B,
1360   PREFIX_VEX_0F3A4C,
1361   PREFIX_VEX_0F3A5C,
1362   PREFIX_VEX_0F3A5D,
1363   PREFIX_VEX_0F3A5E,
1364   PREFIX_VEX_0F3A5F,
1365   PREFIX_VEX_0F3A60,
1366   PREFIX_VEX_0F3A61,
1367   PREFIX_VEX_0F3A62,
1368   PREFIX_VEX_0F3A63,
1369   PREFIX_VEX_0F3A68,
1370   PREFIX_VEX_0F3A69,
1371   PREFIX_VEX_0F3A6A,
1372   PREFIX_VEX_0F3A6B,
1373   PREFIX_VEX_0F3A6C,
1374   PREFIX_VEX_0F3A6D,
1375   PREFIX_VEX_0F3A6E,
1376   PREFIX_VEX_0F3A6F,
1377   PREFIX_VEX_0F3A78,
1378   PREFIX_VEX_0F3A79,
1379   PREFIX_VEX_0F3A7A,
1380   PREFIX_VEX_0F3A7B,
1381   PREFIX_VEX_0F3A7C,
1382   PREFIX_VEX_0F3A7D,
1383   PREFIX_VEX_0F3A7E,
1384   PREFIX_VEX_0F3A7F,
1385   PREFIX_VEX_0F3ADF,
1386   PREFIX_VEX_0F3AF0,
1387
1388   PREFIX_EVEX_0F10,
1389   PREFIX_EVEX_0F11,
1390   PREFIX_EVEX_0F12,
1391   PREFIX_EVEX_0F13,
1392   PREFIX_EVEX_0F14,
1393   PREFIX_EVEX_0F15,
1394   PREFIX_EVEX_0F16,
1395   PREFIX_EVEX_0F17,
1396   PREFIX_EVEX_0F28,
1397   PREFIX_EVEX_0F29,
1398   PREFIX_EVEX_0F2A,
1399   PREFIX_EVEX_0F2B,
1400   PREFIX_EVEX_0F2C,
1401   PREFIX_EVEX_0F2D,
1402   PREFIX_EVEX_0F2E,
1403   PREFIX_EVEX_0F2F,
1404   PREFIX_EVEX_0F51,
1405   PREFIX_EVEX_0F54,
1406   PREFIX_EVEX_0F55,
1407   PREFIX_EVEX_0F56,
1408   PREFIX_EVEX_0F57,
1409   PREFIX_EVEX_0F58,
1410   PREFIX_EVEX_0F59,
1411   PREFIX_EVEX_0F5A,
1412   PREFIX_EVEX_0F5B,
1413   PREFIX_EVEX_0F5C,
1414   PREFIX_EVEX_0F5D,
1415   PREFIX_EVEX_0F5E,
1416   PREFIX_EVEX_0F5F,
1417   PREFIX_EVEX_0F60,
1418   PREFIX_EVEX_0F61,
1419   PREFIX_EVEX_0F62,
1420   PREFIX_EVEX_0F63,
1421   PREFIX_EVEX_0F64,
1422   PREFIX_EVEX_0F65,
1423   PREFIX_EVEX_0F66,
1424   PREFIX_EVEX_0F67,
1425   PREFIX_EVEX_0F68,
1426   PREFIX_EVEX_0F69,
1427   PREFIX_EVEX_0F6A,
1428   PREFIX_EVEX_0F6B,
1429   PREFIX_EVEX_0F6C,
1430   PREFIX_EVEX_0F6D,
1431   PREFIX_EVEX_0F6E,
1432   PREFIX_EVEX_0F6F,
1433   PREFIX_EVEX_0F70,
1434   PREFIX_EVEX_0F71_REG_2,
1435   PREFIX_EVEX_0F71_REG_4,
1436   PREFIX_EVEX_0F71_REG_6,
1437   PREFIX_EVEX_0F72_REG_0,
1438   PREFIX_EVEX_0F72_REG_1,
1439   PREFIX_EVEX_0F72_REG_2,
1440   PREFIX_EVEX_0F72_REG_4,
1441   PREFIX_EVEX_0F72_REG_6,
1442   PREFIX_EVEX_0F73_REG_2,
1443   PREFIX_EVEX_0F73_REG_3,
1444   PREFIX_EVEX_0F73_REG_6,
1445   PREFIX_EVEX_0F73_REG_7,
1446   PREFIX_EVEX_0F74,
1447   PREFIX_EVEX_0F75,
1448   PREFIX_EVEX_0F76,
1449   PREFIX_EVEX_0F78,
1450   PREFIX_EVEX_0F79,
1451   PREFIX_EVEX_0F7A,
1452   PREFIX_EVEX_0F7B,
1453   PREFIX_EVEX_0F7E,
1454   PREFIX_EVEX_0F7F,
1455   PREFIX_EVEX_0FC2,
1456   PREFIX_EVEX_0FC4,
1457   PREFIX_EVEX_0FC5,
1458   PREFIX_EVEX_0FC6,
1459   PREFIX_EVEX_0FD1,
1460   PREFIX_EVEX_0FD2,
1461   PREFIX_EVEX_0FD3,
1462   PREFIX_EVEX_0FD4,
1463   PREFIX_EVEX_0FD5,
1464   PREFIX_EVEX_0FD6,
1465   PREFIX_EVEX_0FD8,
1466   PREFIX_EVEX_0FD9,
1467   PREFIX_EVEX_0FDA,
1468   PREFIX_EVEX_0FDB,
1469   PREFIX_EVEX_0FDC,
1470   PREFIX_EVEX_0FDD,
1471   PREFIX_EVEX_0FDE,
1472   PREFIX_EVEX_0FDF,
1473   PREFIX_EVEX_0FE0,
1474   PREFIX_EVEX_0FE1,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE3,
1477   PREFIX_EVEX_0FE4,
1478   PREFIX_EVEX_0FE5,
1479   PREFIX_EVEX_0FE6,
1480   PREFIX_EVEX_0FE7,
1481   PREFIX_EVEX_0FE8,
1482   PREFIX_EVEX_0FE9,
1483   PREFIX_EVEX_0FEA,
1484   PREFIX_EVEX_0FEB,
1485   PREFIX_EVEX_0FEC,
1486   PREFIX_EVEX_0FED,
1487   PREFIX_EVEX_0FEE,
1488   PREFIX_EVEX_0FEF,
1489   PREFIX_EVEX_0FF1,
1490   PREFIX_EVEX_0FF2,
1491   PREFIX_EVEX_0FF3,
1492   PREFIX_EVEX_0FF4,
1493   PREFIX_EVEX_0FF5,
1494   PREFIX_EVEX_0FF6,
1495   PREFIX_EVEX_0FF8,
1496   PREFIX_EVEX_0FF9,
1497   PREFIX_EVEX_0FFA,
1498   PREFIX_EVEX_0FFB,
1499   PREFIX_EVEX_0FFC,
1500   PREFIX_EVEX_0FFD,
1501   PREFIX_EVEX_0FFE,
1502   PREFIX_EVEX_0F3800,
1503   PREFIX_EVEX_0F3804,
1504   PREFIX_EVEX_0F380B,
1505   PREFIX_EVEX_0F380C,
1506   PREFIX_EVEX_0F380D,
1507   PREFIX_EVEX_0F3810,
1508   PREFIX_EVEX_0F3811,
1509   PREFIX_EVEX_0F3812,
1510   PREFIX_EVEX_0F3813,
1511   PREFIX_EVEX_0F3814,
1512   PREFIX_EVEX_0F3815,
1513   PREFIX_EVEX_0F3816,
1514   PREFIX_EVEX_0F3818,
1515   PREFIX_EVEX_0F3819,
1516   PREFIX_EVEX_0F381A,
1517   PREFIX_EVEX_0F381B,
1518   PREFIX_EVEX_0F381C,
1519   PREFIX_EVEX_0F381D,
1520   PREFIX_EVEX_0F381E,
1521   PREFIX_EVEX_0F381F,
1522   PREFIX_EVEX_0F3820,
1523   PREFIX_EVEX_0F3821,
1524   PREFIX_EVEX_0F3822,
1525   PREFIX_EVEX_0F3823,
1526   PREFIX_EVEX_0F3824,
1527   PREFIX_EVEX_0F3825,
1528   PREFIX_EVEX_0F3826,
1529   PREFIX_EVEX_0F3827,
1530   PREFIX_EVEX_0F3828,
1531   PREFIX_EVEX_0F3829,
1532   PREFIX_EVEX_0F382A,
1533   PREFIX_EVEX_0F382B,
1534   PREFIX_EVEX_0F382C,
1535   PREFIX_EVEX_0F382D,
1536   PREFIX_EVEX_0F3830,
1537   PREFIX_EVEX_0F3831,
1538   PREFIX_EVEX_0F3832,
1539   PREFIX_EVEX_0F3833,
1540   PREFIX_EVEX_0F3834,
1541   PREFIX_EVEX_0F3835,
1542   PREFIX_EVEX_0F3836,
1543   PREFIX_EVEX_0F3837,
1544   PREFIX_EVEX_0F3838,
1545   PREFIX_EVEX_0F3839,
1546   PREFIX_EVEX_0F383A,
1547   PREFIX_EVEX_0F383B,
1548   PREFIX_EVEX_0F383C,
1549   PREFIX_EVEX_0F383D,
1550   PREFIX_EVEX_0F383E,
1551   PREFIX_EVEX_0F383F,
1552   PREFIX_EVEX_0F3840,
1553   PREFIX_EVEX_0F3842,
1554   PREFIX_EVEX_0F3843,
1555   PREFIX_EVEX_0F3844,
1556   PREFIX_EVEX_0F3845,
1557   PREFIX_EVEX_0F3846,
1558   PREFIX_EVEX_0F3847,
1559   PREFIX_EVEX_0F384C,
1560   PREFIX_EVEX_0F384D,
1561   PREFIX_EVEX_0F384E,
1562   PREFIX_EVEX_0F384F,
1563   PREFIX_EVEX_0F3852,
1564   PREFIX_EVEX_0F3853,
1565   PREFIX_EVEX_0F3855,
1566   PREFIX_EVEX_0F3858,
1567   PREFIX_EVEX_0F3859,
1568   PREFIX_EVEX_0F385A,
1569   PREFIX_EVEX_0F385B,
1570   PREFIX_EVEX_0F3864,
1571   PREFIX_EVEX_0F3865,
1572   PREFIX_EVEX_0F3866,
1573   PREFIX_EVEX_0F3875,
1574   PREFIX_EVEX_0F3876,
1575   PREFIX_EVEX_0F3877,
1576   PREFIX_EVEX_0F3878,
1577   PREFIX_EVEX_0F3879,
1578   PREFIX_EVEX_0F387A,
1579   PREFIX_EVEX_0F387B,
1580   PREFIX_EVEX_0F387C,
1581   PREFIX_EVEX_0F387D,
1582   PREFIX_EVEX_0F387E,
1583   PREFIX_EVEX_0F387F,
1584   PREFIX_EVEX_0F3883,
1585   PREFIX_EVEX_0F3888,
1586   PREFIX_EVEX_0F3889,
1587   PREFIX_EVEX_0F388A,
1588   PREFIX_EVEX_0F388B,
1589   PREFIX_EVEX_0F388D,
1590   PREFIX_EVEX_0F3890,
1591   PREFIX_EVEX_0F3891,
1592   PREFIX_EVEX_0F3892,
1593   PREFIX_EVEX_0F3893,
1594   PREFIX_EVEX_0F3896,
1595   PREFIX_EVEX_0F3897,
1596   PREFIX_EVEX_0F3898,
1597   PREFIX_EVEX_0F3899,
1598   PREFIX_EVEX_0F389A,
1599   PREFIX_EVEX_0F389B,
1600   PREFIX_EVEX_0F389C,
1601   PREFIX_EVEX_0F389D,
1602   PREFIX_EVEX_0F389E,
1603   PREFIX_EVEX_0F389F,
1604   PREFIX_EVEX_0F38A0,
1605   PREFIX_EVEX_0F38A1,
1606   PREFIX_EVEX_0F38A2,
1607   PREFIX_EVEX_0F38A3,
1608   PREFIX_EVEX_0F38A6,
1609   PREFIX_EVEX_0F38A7,
1610   PREFIX_EVEX_0F38A8,
1611   PREFIX_EVEX_0F38A9,
1612   PREFIX_EVEX_0F38AA,
1613   PREFIX_EVEX_0F38AB,
1614   PREFIX_EVEX_0F38AC,
1615   PREFIX_EVEX_0F38AD,
1616   PREFIX_EVEX_0F38AE,
1617   PREFIX_EVEX_0F38AF,
1618   PREFIX_EVEX_0F38B4,
1619   PREFIX_EVEX_0F38B5,
1620   PREFIX_EVEX_0F38B6,
1621   PREFIX_EVEX_0F38B7,
1622   PREFIX_EVEX_0F38B8,
1623   PREFIX_EVEX_0F38B9,
1624   PREFIX_EVEX_0F38BA,
1625   PREFIX_EVEX_0F38BB,
1626   PREFIX_EVEX_0F38BC,
1627   PREFIX_EVEX_0F38BD,
1628   PREFIX_EVEX_0F38BE,
1629   PREFIX_EVEX_0F38BF,
1630   PREFIX_EVEX_0F38C4,
1631   PREFIX_EVEX_0F38C6_REG_1,
1632   PREFIX_EVEX_0F38C6_REG_2,
1633   PREFIX_EVEX_0F38C6_REG_5,
1634   PREFIX_EVEX_0F38C6_REG_6,
1635   PREFIX_EVEX_0F38C7_REG_1,
1636   PREFIX_EVEX_0F38C7_REG_2,
1637   PREFIX_EVEX_0F38C7_REG_5,
1638   PREFIX_EVEX_0F38C7_REG_6,
1639   PREFIX_EVEX_0F38C8,
1640   PREFIX_EVEX_0F38CA,
1641   PREFIX_EVEX_0F38CB,
1642   PREFIX_EVEX_0F38CC,
1643   PREFIX_EVEX_0F38CD,
1644
1645   PREFIX_EVEX_0F3A00,
1646   PREFIX_EVEX_0F3A01,
1647   PREFIX_EVEX_0F3A03,
1648   PREFIX_EVEX_0F3A04,
1649   PREFIX_EVEX_0F3A05,
1650   PREFIX_EVEX_0F3A08,
1651   PREFIX_EVEX_0F3A09,
1652   PREFIX_EVEX_0F3A0A,
1653   PREFIX_EVEX_0F3A0B,
1654   PREFIX_EVEX_0F3A0F,
1655   PREFIX_EVEX_0F3A14,
1656   PREFIX_EVEX_0F3A15,
1657   PREFIX_EVEX_0F3A16,
1658   PREFIX_EVEX_0F3A17,
1659   PREFIX_EVEX_0F3A18,
1660   PREFIX_EVEX_0F3A19,
1661   PREFIX_EVEX_0F3A1A,
1662   PREFIX_EVEX_0F3A1B,
1663   PREFIX_EVEX_0F3A1D,
1664   PREFIX_EVEX_0F3A1E,
1665   PREFIX_EVEX_0F3A1F,
1666   PREFIX_EVEX_0F3A20,
1667   PREFIX_EVEX_0F3A21,
1668   PREFIX_EVEX_0F3A22,
1669   PREFIX_EVEX_0F3A23,
1670   PREFIX_EVEX_0F3A25,
1671   PREFIX_EVEX_0F3A26,
1672   PREFIX_EVEX_0F3A27,
1673   PREFIX_EVEX_0F3A38,
1674   PREFIX_EVEX_0F3A39,
1675   PREFIX_EVEX_0F3A3A,
1676   PREFIX_EVEX_0F3A3B,
1677   PREFIX_EVEX_0F3A3E,
1678   PREFIX_EVEX_0F3A3F,
1679   PREFIX_EVEX_0F3A42,
1680   PREFIX_EVEX_0F3A43,
1681   PREFIX_EVEX_0F3A50,
1682   PREFIX_EVEX_0F3A51,
1683   PREFIX_EVEX_0F3A54,
1684   PREFIX_EVEX_0F3A55,
1685   PREFIX_EVEX_0F3A56,
1686   PREFIX_EVEX_0F3A57,
1687   PREFIX_EVEX_0F3A66,
1688   PREFIX_EVEX_0F3A67
1689 };
1690
1691 enum
1692 {
1693   X86_64_06 = 0,
1694   X86_64_07,
1695   X86_64_0D,
1696   X86_64_16,
1697   X86_64_17,
1698   X86_64_1E,
1699   X86_64_1F,
1700   X86_64_27,
1701   X86_64_2F,
1702   X86_64_37,
1703   X86_64_3F,
1704   X86_64_60,
1705   X86_64_61,
1706   X86_64_62,
1707   X86_64_63,
1708   X86_64_6D,
1709   X86_64_6F,
1710   X86_64_82,
1711   X86_64_9A,
1712   X86_64_C4,
1713   X86_64_C5,
1714   X86_64_CE,
1715   X86_64_D4,
1716   X86_64_D5,
1717   X86_64_E8,
1718   X86_64_E9,
1719   X86_64_EA,
1720   X86_64_0F01_REG_0,
1721   X86_64_0F01_REG_1,
1722   X86_64_0F01_REG_2,
1723   X86_64_0F01_REG_3
1724 };
1725
1726 enum
1727 {
1728   THREE_BYTE_0F38 = 0,
1729   THREE_BYTE_0F3A
1730 };
1731
1732 enum
1733 {
1734   XOP_08 = 0,
1735   XOP_09,
1736   XOP_0A
1737 };
1738
1739 enum
1740 {
1741   VEX_0F = 0,
1742   VEX_0F38,
1743   VEX_0F3A
1744 };
1745
1746 enum
1747 {
1748   EVEX_0F = 0,
1749   EVEX_0F38,
1750   EVEX_0F3A
1751 };
1752
1753 enum
1754 {
1755   VEX_LEN_0F10_P_1 = 0,
1756   VEX_LEN_0F10_P_3,
1757   VEX_LEN_0F11_P_1,
1758   VEX_LEN_0F11_P_3,
1759   VEX_LEN_0F12_P_0_M_0,
1760   VEX_LEN_0F12_P_0_M_1,
1761   VEX_LEN_0F12_P_2,
1762   VEX_LEN_0F13_M_0,
1763   VEX_LEN_0F16_P_0_M_0,
1764   VEX_LEN_0F16_P_0_M_1,
1765   VEX_LEN_0F16_P_2,
1766   VEX_LEN_0F17_M_0,
1767   VEX_LEN_0F2A_P_1,
1768   VEX_LEN_0F2A_P_3,
1769   VEX_LEN_0F2C_P_1,
1770   VEX_LEN_0F2C_P_3,
1771   VEX_LEN_0F2D_P_1,
1772   VEX_LEN_0F2D_P_3,
1773   VEX_LEN_0F2E_P_0,
1774   VEX_LEN_0F2E_P_2,
1775   VEX_LEN_0F2F_P_0,
1776   VEX_LEN_0F2F_P_2,
1777   VEX_LEN_0F41_P_0,
1778   VEX_LEN_0F41_P_2,
1779   VEX_LEN_0F42_P_0,
1780   VEX_LEN_0F42_P_2,
1781   VEX_LEN_0F44_P_0,
1782   VEX_LEN_0F44_P_2,
1783   VEX_LEN_0F45_P_0,
1784   VEX_LEN_0F45_P_2,
1785   VEX_LEN_0F46_P_0,
1786   VEX_LEN_0F46_P_2,
1787   VEX_LEN_0F47_P_0,
1788   VEX_LEN_0F47_P_2,
1789   VEX_LEN_0F4A_P_0,
1790   VEX_LEN_0F4A_P_2,
1791   VEX_LEN_0F4B_P_0,
1792   VEX_LEN_0F4B_P_2,
1793   VEX_LEN_0F51_P_1,
1794   VEX_LEN_0F51_P_3,
1795   VEX_LEN_0F52_P_1,
1796   VEX_LEN_0F53_P_1,
1797   VEX_LEN_0F58_P_1,
1798   VEX_LEN_0F58_P_3,
1799   VEX_LEN_0F59_P_1,
1800   VEX_LEN_0F59_P_3,
1801   VEX_LEN_0F5A_P_1,
1802   VEX_LEN_0F5A_P_3,
1803   VEX_LEN_0F5C_P_1,
1804   VEX_LEN_0F5C_P_3,
1805   VEX_LEN_0F5D_P_1,
1806   VEX_LEN_0F5D_P_3,
1807   VEX_LEN_0F5E_P_1,
1808   VEX_LEN_0F5E_P_3,
1809   VEX_LEN_0F5F_P_1,
1810   VEX_LEN_0F5F_P_3,
1811   VEX_LEN_0F6E_P_2,
1812   VEX_LEN_0F7E_P_1,
1813   VEX_LEN_0F7E_P_2,
1814   VEX_LEN_0F90_P_0,
1815   VEX_LEN_0F90_P_2,
1816   VEX_LEN_0F91_P_0,
1817   VEX_LEN_0F91_P_2,
1818   VEX_LEN_0F92_P_0,
1819   VEX_LEN_0F92_P_2,
1820   VEX_LEN_0F92_P_3,
1821   VEX_LEN_0F93_P_0,
1822   VEX_LEN_0F93_P_2,
1823   VEX_LEN_0F93_P_3,
1824   VEX_LEN_0F98_P_0,
1825   VEX_LEN_0F98_P_2,
1826   VEX_LEN_0F99_P_0,
1827   VEX_LEN_0F99_P_2,
1828   VEX_LEN_0FAE_R_2_M_0,
1829   VEX_LEN_0FAE_R_3_M_0,
1830   VEX_LEN_0FC2_P_1,
1831   VEX_LEN_0FC2_P_3,
1832   VEX_LEN_0FC4_P_2,
1833   VEX_LEN_0FC5_P_2,
1834   VEX_LEN_0FD6_P_2,
1835   VEX_LEN_0FF7_P_2,
1836   VEX_LEN_0F3816_P_2,
1837   VEX_LEN_0F3819_P_2,
1838   VEX_LEN_0F381A_P_2_M_0,
1839   VEX_LEN_0F3836_P_2,
1840   VEX_LEN_0F3841_P_2,
1841   VEX_LEN_0F385A_P_2_M_0,
1842   VEX_LEN_0F38DB_P_2,
1843   VEX_LEN_0F38DC_P_2,
1844   VEX_LEN_0F38DD_P_2,
1845   VEX_LEN_0F38DE_P_2,
1846   VEX_LEN_0F38DF_P_2,
1847   VEX_LEN_0F38F2_P_0,
1848   VEX_LEN_0F38F3_R_1_P_0,
1849   VEX_LEN_0F38F3_R_2_P_0,
1850   VEX_LEN_0F38F3_R_3_P_0,
1851   VEX_LEN_0F38F5_P_0,
1852   VEX_LEN_0F38F5_P_1,
1853   VEX_LEN_0F38F5_P_3,
1854   VEX_LEN_0F38F6_P_3,
1855   VEX_LEN_0F38F7_P_0,
1856   VEX_LEN_0F38F7_P_1,
1857   VEX_LEN_0F38F7_P_2,
1858   VEX_LEN_0F38F7_P_3,
1859   VEX_LEN_0F3A00_P_2,
1860   VEX_LEN_0F3A01_P_2,
1861   VEX_LEN_0F3A06_P_2,
1862   VEX_LEN_0F3A0A_P_2,
1863   VEX_LEN_0F3A0B_P_2,
1864   VEX_LEN_0F3A14_P_2,
1865   VEX_LEN_0F3A15_P_2,
1866   VEX_LEN_0F3A16_P_2,
1867   VEX_LEN_0F3A17_P_2,
1868   VEX_LEN_0F3A18_P_2,
1869   VEX_LEN_0F3A19_P_2,
1870   VEX_LEN_0F3A20_P_2,
1871   VEX_LEN_0F3A21_P_2,
1872   VEX_LEN_0F3A22_P_2,
1873   VEX_LEN_0F3A30_P_2,
1874   VEX_LEN_0F3A31_P_2,
1875   VEX_LEN_0F3A32_P_2,
1876   VEX_LEN_0F3A33_P_2,
1877   VEX_LEN_0F3A38_P_2,
1878   VEX_LEN_0F3A39_P_2,
1879   VEX_LEN_0F3A41_P_2,
1880   VEX_LEN_0F3A44_P_2,
1881   VEX_LEN_0F3A46_P_2,
1882   VEX_LEN_0F3A60_P_2,
1883   VEX_LEN_0F3A61_P_2,
1884   VEX_LEN_0F3A62_P_2,
1885   VEX_LEN_0F3A63_P_2,
1886   VEX_LEN_0F3A6A_P_2,
1887   VEX_LEN_0F3A6B_P_2,
1888   VEX_LEN_0F3A6E_P_2,
1889   VEX_LEN_0F3A6F_P_2,
1890   VEX_LEN_0F3A7A_P_2,
1891   VEX_LEN_0F3A7B_P_2,
1892   VEX_LEN_0F3A7E_P_2,
1893   VEX_LEN_0F3A7F_P_2,
1894   VEX_LEN_0F3ADF_P_2,
1895   VEX_LEN_0F3AF0_P_3,
1896   VEX_LEN_0FXOP_08_CC,
1897   VEX_LEN_0FXOP_08_CD,
1898   VEX_LEN_0FXOP_08_CE,
1899   VEX_LEN_0FXOP_08_CF,
1900   VEX_LEN_0FXOP_08_EC,
1901   VEX_LEN_0FXOP_08_ED,
1902   VEX_LEN_0FXOP_08_EE,
1903   VEX_LEN_0FXOP_08_EF,
1904   VEX_LEN_0FXOP_09_80,
1905   VEX_LEN_0FXOP_09_81
1906 };
1907
1908 enum
1909 {
1910   VEX_W_0F10_P_0 = 0,
1911   VEX_W_0F10_P_1,
1912   VEX_W_0F10_P_2,
1913   VEX_W_0F10_P_3,
1914   VEX_W_0F11_P_0,
1915   VEX_W_0F11_P_1,
1916   VEX_W_0F11_P_2,
1917   VEX_W_0F11_P_3,
1918   VEX_W_0F12_P_0_M_0,
1919   VEX_W_0F12_P_0_M_1,
1920   VEX_W_0F12_P_1,
1921   VEX_W_0F12_P_2,
1922   VEX_W_0F12_P_3,
1923   VEX_W_0F13_M_0,
1924   VEX_W_0F14,
1925   VEX_W_0F15,
1926   VEX_W_0F16_P_0_M_0,
1927   VEX_W_0F16_P_0_M_1,
1928   VEX_W_0F16_P_1,
1929   VEX_W_0F16_P_2,
1930   VEX_W_0F17_M_0,
1931   VEX_W_0F28,
1932   VEX_W_0F29,
1933   VEX_W_0F2B_M_0,
1934   VEX_W_0F2E_P_0,
1935   VEX_W_0F2E_P_2,
1936   VEX_W_0F2F_P_0,
1937   VEX_W_0F2F_P_2,
1938   VEX_W_0F41_P_0_LEN_1,
1939   VEX_W_0F41_P_2_LEN_1,
1940   VEX_W_0F42_P_0_LEN_1,
1941   VEX_W_0F42_P_2_LEN_1,
1942   VEX_W_0F44_P_0_LEN_0,
1943   VEX_W_0F44_P_2_LEN_0,
1944   VEX_W_0F45_P_0_LEN_1,
1945   VEX_W_0F45_P_2_LEN_1,
1946   VEX_W_0F46_P_0_LEN_1,
1947   VEX_W_0F46_P_2_LEN_1,
1948   VEX_W_0F47_P_0_LEN_1,
1949   VEX_W_0F47_P_2_LEN_1,
1950   VEX_W_0F4A_P_0_LEN_1,
1951   VEX_W_0F4A_P_2_LEN_1,
1952   VEX_W_0F4B_P_0_LEN_1,
1953   VEX_W_0F4B_P_2_LEN_1,
1954   VEX_W_0F50_M_0,
1955   VEX_W_0F51_P_0,
1956   VEX_W_0F51_P_1,
1957   VEX_W_0F51_P_2,
1958   VEX_W_0F51_P_3,
1959   VEX_W_0F52_P_0,
1960   VEX_W_0F52_P_1,
1961   VEX_W_0F53_P_0,
1962   VEX_W_0F53_P_1,
1963   VEX_W_0F58_P_0,
1964   VEX_W_0F58_P_1,
1965   VEX_W_0F58_P_2,
1966   VEX_W_0F58_P_3,
1967   VEX_W_0F59_P_0,
1968   VEX_W_0F59_P_1,
1969   VEX_W_0F59_P_2,
1970   VEX_W_0F59_P_3,
1971   VEX_W_0F5A_P_0,
1972   VEX_W_0F5A_P_1,
1973   VEX_W_0F5A_P_3,
1974   VEX_W_0F5B_P_0,
1975   VEX_W_0F5B_P_1,
1976   VEX_W_0F5B_P_2,
1977   VEX_W_0F5C_P_0,
1978   VEX_W_0F5C_P_1,
1979   VEX_W_0F5C_P_2,
1980   VEX_W_0F5C_P_3,
1981   VEX_W_0F5D_P_0,
1982   VEX_W_0F5D_P_1,
1983   VEX_W_0F5D_P_2,
1984   VEX_W_0F5D_P_3,
1985   VEX_W_0F5E_P_0,
1986   VEX_W_0F5E_P_1,
1987   VEX_W_0F5E_P_2,
1988   VEX_W_0F5E_P_3,
1989   VEX_W_0F5F_P_0,
1990   VEX_W_0F5F_P_1,
1991   VEX_W_0F5F_P_2,
1992   VEX_W_0F5F_P_3,
1993   VEX_W_0F60_P_2,
1994   VEX_W_0F61_P_2,
1995   VEX_W_0F62_P_2,
1996   VEX_W_0F63_P_2,
1997   VEX_W_0F64_P_2,
1998   VEX_W_0F65_P_2,
1999   VEX_W_0F66_P_2,
2000   VEX_W_0F67_P_2,
2001   VEX_W_0F68_P_2,
2002   VEX_W_0F69_P_2,
2003   VEX_W_0F6A_P_2,
2004   VEX_W_0F6B_P_2,
2005   VEX_W_0F6C_P_2,
2006   VEX_W_0F6D_P_2,
2007   VEX_W_0F6F_P_1,
2008   VEX_W_0F6F_P_2,
2009   VEX_W_0F70_P_1,
2010   VEX_W_0F70_P_2,
2011   VEX_W_0F70_P_3,
2012   VEX_W_0F71_R_2_P_2,
2013   VEX_W_0F71_R_4_P_2,
2014   VEX_W_0F71_R_6_P_2,
2015   VEX_W_0F72_R_2_P_2,
2016   VEX_W_0F72_R_4_P_2,
2017   VEX_W_0F72_R_6_P_2,
2018   VEX_W_0F73_R_2_P_2,
2019   VEX_W_0F73_R_3_P_2,
2020   VEX_W_0F73_R_6_P_2,
2021   VEX_W_0F73_R_7_P_2,
2022   VEX_W_0F74_P_2,
2023   VEX_W_0F75_P_2,
2024   VEX_W_0F76_P_2,
2025   VEX_W_0F77_P_0,
2026   VEX_W_0F7C_P_2,
2027   VEX_W_0F7C_P_3,
2028   VEX_W_0F7D_P_2,
2029   VEX_W_0F7D_P_3,
2030   VEX_W_0F7E_P_1,
2031   VEX_W_0F7F_P_1,
2032   VEX_W_0F7F_P_2,
2033   VEX_W_0F90_P_0_LEN_0,
2034   VEX_W_0F90_P_2_LEN_0,
2035   VEX_W_0F91_P_0_LEN_0,
2036   VEX_W_0F91_P_2_LEN_0,
2037   VEX_W_0F92_P_0_LEN_0,
2038   VEX_W_0F92_P_2_LEN_0,
2039   VEX_W_0F92_P_3_LEN_0,
2040   VEX_W_0F93_P_0_LEN_0,
2041   VEX_W_0F93_P_2_LEN_0,
2042   VEX_W_0F93_P_3_LEN_0,
2043   VEX_W_0F98_P_0_LEN_0,
2044   VEX_W_0F98_P_2_LEN_0,
2045   VEX_W_0F99_P_0_LEN_0,
2046   VEX_W_0F99_P_2_LEN_0,
2047   VEX_W_0FAE_R_2_M_0,
2048   VEX_W_0FAE_R_3_M_0,
2049   VEX_W_0FC2_P_0,
2050   VEX_W_0FC2_P_1,
2051   VEX_W_0FC2_P_2,
2052   VEX_W_0FC2_P_3,
2053   VEX_W_0FC4_P_2,
2054   VEX_W_0FC5_P_2,
2055   VEX_W_0FD0_P_2,
2056   VEX_W_0FD0_P_3,
2057   VEX_W_0FD1_P_2,
2058   VEX_W_0FD2_P_2,
2059   VEX_W_0FD3_P_2,
2060   VEX_W_0FD4_P_2,
2061   VEX_W_0FD5_P_2,
2062   VEX_W_0FD6_P_2,
2063   VEX_W_0FD7_P_2_M_1,
2064   VEX_W_0FD8_P_2,
2065   VEX_W_0FD9_P_2,
2066   VEX_W_0FDA_P_2,
2067   VEX_W_0FDB_P_2,
2068   VEX_W_0FDC_P_2,
2069   VEX_W_0FDD_P_2,
2070   VEX_W_0FDE_P_2,
2071   VEX_W_0FDF_P_2,
2072   VEX_W_0FE0_P_2,
2073   VEX_W_0FE1_P_2,
2074   VEX_W_0FE2_P_2,
2075   VEX_W_0FE3_P_2,
2076   VEX_W_0FE4_P_2,
2077   VEX_W_0FE5_P_2,
2078   VEX_W_0FE6_P_1,
2079   VEX_W_0FE6_P_2,
2080   VEX_W_0FE6_P_3,
2081   VEX_W_0FE7_P_2_M_0,
2082   VEX_W_0FE8_P_2,
2083   VEX_W_0FE9_P_2,
2084   VEX_W_0FEA_P_2,
2085   VEX_W_0FEB_P_2,
2086   VEX_W_0FEC_P_2,
2087   VEX_W_0FED_P_2,
2088   VEX_W_0FEE_P_2,
2089   VEX_W_0FEF_P_2,
2090   VEX_W_0FF0_P_3_M_0,
2091   VEX_W_0FF1_P_2,
2092   VEX_W_0FF2_P_2,
2093   VEX_W_0FF3_P_2,
2094   VEX_W_0FF4_P_2,
2095   VEX_W_0FF5_P_2,
2096   VEX_W_0FF6_P_2,
2097   VEX_W_0FF7_P_2,
2098   VEX_W_0FF8_P_2,
2099   VEX_W_0FF9_P_2,
2100   VEX_W_0FFA_P_2,
2101   VEX_W_0FFB_P_2,
2102   VEX_W_0FFC_P_2,
2103   VEX_W_0FFD_P_2,
2104   VEX_W_0FFE_P_2,
2105   VEX_W_0F3800_P_2,
2106   VEX_W_0F3801_P_2,
2107   VEX_W_0F3802_P_2,
2108   VEX_W_0F3803_P_2,
2109   VEX_W_0F3804_P_2,
2110   VEX_W_0F3805_P_2,
2111   VEX_W_0F3806_P_2,
2112   VEX_W_0F3807_P_2,
2113   VEX_W_0F3808_P_2,
2114   VEX_W_0F3809_P_2,
2115   VEX_W_0F380A_P_2,
2116   VEX_W_0F380B_P_2,
2117   VEX_W_0F380C_P_2,
2118   VEX_W_0F380D_P_2,
2119   VEX_W_0F380E_P_2,
2120   VEX_W_0F380F_P_2,
2121   VEX_W_0F3816_P_2,
2122   VEX_W_0F3817_P_2,
2123   VEX_W_0F3818_P_2,
2124   VEX_W_0F3819_P_2,
2125   VEX_W_0F381A_P_2_M_0,
2126   VEX_W_0F381C_P_2,
2127   VEX_W_0F381D_P_2,
2128   VEX_W_0F381E_P_2,
2129   VEX_W_0F3820_P_2,
2130   VEX_W_0F3821_P_2,
2131   VEX_W_0F3822_P_2,
2132   VEX_W_0F3823_P_2,
2133   VEX_W_0F3824_P_2,
2134   VEX_W_0F3825_P_2,
2135   VEX_W_0F3828_P_2,
2136   VEX_W_0F3829_P_2,
2137   VEX_W_0F382A_P_2_M_0,
2138   VEX_W_0F382B_P_2,
2139   VEX_W_0F382C_P_2_M_0,
2140   VEX_W_0F382D_P_2_M_0,
2141   VEX_W_0F382E_P_2_M_0,
2142   VEX_W_0F382F_P_2_M_0,
2143   VEX_W_0F3830_P_2,
2144   VEX_W_0F3831_P_2,
2145   VEX_W_0F3832_P_2,
2146   VEX_W_0F3833_P_2,
2147   VEX_W_0F3834_P_2,
2148   VEX_W_0F3835_P_2,
2149   VEX_W_0F3836_P_2,
2150   VEX_W_0F3837_P_2,
2151   VEX_W_0F3838_P_2,
2152   VEX_W_0F3839_P_2,
2153   VEX_W_0F383A_P_2,
2154   VEX_W_0F383B_P_2,
2155   VEX_W_0F383C_P_2,
2156   VEX_W_0F383D_P_2,
2157   VEX_W_0F383E_P_2,
2158   VEX_W_0F383F_P_2,
2159   VEX_W_0F3840_P_2,
2160   VEX_W_0F3841_P_2,
2161   VEX_W_0F3846_P_2,
2162   VEX_W_0F3858_P_2,
2163   VEX_W_0F3859_P_2,
2164   VEX_W_0F385A_P_2_M_0,
2165   VEX_W_0F3878_P_2,
2166   VEX_W_0F3879_P_2,
2167   VEX_W_0F38DB_P_2,
2168   VEX_W_0F38DC_P_2,
2169   VEX_W_0F38DD_P_2,
2170   VEX_W_0F38DE_P_2,
2171   VEX_W_0F38DF_P_2,
2172   VEX_W_0F3A00_P_2,
2173   VEX_W_0F3A01_P_2,
2174   VEX_W_0F3A02_P_2,
2175   VEX_W_0F3A04_P_2,
2176   VEX_W_0F3A05_P_2,
2177   VEX_W_0F3A06_P_2,
2178   VEX_W_0F3A08_P_2,
2179   VEX_W_0F3A09_P_2,
2180   VEX_W_0F3A0A_P_2,
2181   VEX_W_0F3A0B_P_2,
2182   VEX_W_0F3A0C_P_2,
2183   VEX_W_0F3A0D_P_2,
2184   VEX_W_0F3A0E_P_2,
2185   VEX_W_0F3A0F_P_2,
2186   VEX_W_0F3A14_P_2,
2187   VEX_W_0F3A15_P_2,
2188   VEX_W_0F3A18_P_2,
2189   VEX_W_0F3A19_P_2,
2190   VEX_W_0F3A20_P_2,
2191   VEX_W_0F3A21_P_2,
2192   VEX_W_0F3A30_P_2_LEN_0,
2193   VEX_W_0F3A31_P_2_LEN_0,
2194   VEX_W_0F3A32_P_2_LEN_0,
2195   VEX_W_0F3A33_P_2_LEN_0,
2196   VEX_W_0F3A38_P_2,
2197   VEX_W_0F3A39_P_2,
2198   VEX_W_0F3A40_P_2,
2199   VEX_W_0F3A41_P_2,
2200   VEX_W_0F3A42_P_2,
2201   VEX_W_0F3A44_P_2,
2202   VEX_W_0F3A46_P_2,
2203   VEX_W_0F3A48_P_2,
2204   VEX_W_0F3A49_P_2,
2205   VEX_W_0F3A4A_P_2,
2206   VEX_W_0F3A4B_P_2,
2207   VEX_W_0F3A4C_P_2,
2208   VEX_W_0F3A62_P_2,
2209   VEX_W_0F3A63_P_2,
2210   VEX_W_0F3ADF_P_2,
2211
2212   EVEX_W_0F10_P_0,
2213   EVEX_W_0F10_P_1_M_0,
2214   EVEX_W_0F10_P_1_M_1,
2215   EVEX_W_0F10_P_2,
2216   EVEX_W_0F10_P_3_M_0,
2217   EVEX_W_0F10_P_3_M_1,
2218   EVEX_W_0F11_P_0,
2219   EVEX_W_0F11_P_1_M_0,
2220   EVEX_W_0F11_P_1_M_1,
2221   EVEX_W_0F11_P_2,
2222   EVEX_W_0F11_P_3_M_0,
2223   EVEX_W_0F11_P_3_M_1,
2224   EVEX_W_0F12_P_0_M_0,
2225   EVEX_W_0F12_P_0_M_1,
2226   EVEX_W_0F12_P_1,
2227   EVEX_W_0F12_P_2,
2228   EVEX_W_0F12_P_3,
2229   EVEX_W_0F13_P_0,
2230   EVEX_W_0F13_P_2,
2231   EVEX_W_0F14_P_0,
2232   EVEX_W_0F14_P_2,
2233   EVEX_W_0F15_P_0,
2234   EVEX_W_0F15_P_2,
2235   EVEX_W_0F16_P_0_M_0,
2236   EVEX_W_0F16_P_0_M_1,
2237   EVEX_W_0F16_P_1,
2238   EVEX_W_0F16_P_2,
2239   EVEX_W_0F17_P_0,
2240   EVEX_W_0F17_P_2,
2241   EVEX_W_0F28_P_0,
2242   EVEX_W_0F28_P_2,
2243   EVEX_W_0F29_P_0,
2244   EVEX_W_0F29_P_2,
2245   EVEX_W_0F2A_P_1,
2246   EVEX_W_0F2A_P_3,
2247   EVEX_W_0F2B_P_0,
2248   EVEX_W_0F2B_P_2,
2249   EVEX_W_0F2E_P_0,
2250   EVEX_W_0F2E_P_2,
2251   EVEX_W_0F2F_P_0,
2252   EVEX_W_0F2F_P_2,
2253   EVEX_W_0F51_P_0,
2254   EVEX_W_0F51_P_1,
2255   EVEX_W_0F51_P_2,
2256   EVEX_W_0F51_P_3,
2257   EVEX_W_0F54_P_0,
2258   EVEX_W_0F54_P_2,
2259   EVEX_W_0F55_P_0,
2260   EVEX_W_0F55_P_2,
2261   EVEX_W_0F56_P_0,
2262   EVEX_W_0F56_P_2,
2263   EVEX_W_0F57_P_0,
2264   EVEX_W_0F57_P_2,
2265   EVEX_W_0F58_P_0,
2266   EVEX_W_0F58_P_1,
2267   EVEX_W_0F58_P_2,
2268   EVEX_W_0F58_P_3,
2269   EVEX_W_0F59_P_0,
2270   EVEX_W_0F59_P_1,
2271   EVEX_W_0F59_P_2,
2272   EVEX_W_0F59_P_3,
2273   EVEX_W_0F5A_P_0,
2274   EVEX_W_0F5A_P_1,
2275   EVEX_W_0F5A_P_2,
2276   EVEX_W_0F5A_P_3,
2277   EVEX_W_0F5B_P_0,
2278   EVEX_W_0F5B_P_1,
2279   EVEX_W_0F5B_P_2,
2280   EVEX_W_0F5C_P_0,
2281   EVEX_W_0F5C_P_1,
2282   EVEX_W_0F5C_P_2,
2283   EVEX_W_0F5C_P_3,
2284   EVEX_W_0F5D_P_0,
2285   EVEX_W_0F5D_P_1,
2286   EVEX_W_0F5D_P_2,
2287   EVEX_W_0F5D_P_3,
2288   EVEX_W_0F5E_P_0,
2289   EVEX_W_0F5E_P_1,
2290   EVEX_W_0F5E_P_2,
2291   EVEX_W_0F5E_P_3,
2292   EVEX_W_0F5F_P_0,
2293   EVEX_W_0F5F_P_1,
2294   EVEX_W_0F5F_P_2,
2295   EVEX_W_0F5F_P_3,
2296   EVEX_W_0F62_P_2,
2297   EVEX_W_0F66_P_2,
2298   EVEX_W_0F6A_P_2,
2299   EVEX_W_0F6B_P_2,
2300   EVEX_W_0F6C_P_2,
2301   EVEX_W_0F6D_P_2,
2302   EVEX_W_0F6E_P_2,
2303   EVEX_W_0F6F_P_1,
2304   EVEX_W_0F6F_P_2,
2305   EVEX_W_0F6F_P_3,
2306   EVEX_W_0F70_P_2,
2307   EVEX_W_0F72_R_2_P_2,
2308   EVEX_W_0F72_R_6_P_2,
2309   EVEX_W_0F73_R_2_P_2,
2310   EVEX_W_0F73_R_6_P_2,
2311   EVEX_W_0F76_P_2,
2312   EVEX_W_0F78_P_0,
2313   EVEX_W_0F78_P_2,
2314   EVEX_W_0F79_P_0,
2315   EVEX_W_0F79_P_2,
2316   EVEX_W_0F7A_P_1,
2317   EVEX_W_0F7A_P_2,
2318   EVEX_W_0F7A_P_3,
2319   EVEX_W_0F7B_P_1,
2320   EVEX_W_0F7B_P_2,
2321   EVEX_W_0F7B_P_3,
2322   EVEX_W_0F7E_P_1,
2323   EVEX_W_0F7E_P_2,
2324   EVEX_W_0F7F_P_1,
2325   EVEX_W_0F7F_P_2,
2326   EVEX_W_0F7F_P_3,
2327   EVEX_W_0FC2_P_0,
2328   EVEX_W_0FC2_P_1,
2329   EVEX_W_0FC2_P_2,
2330   EVEX_W_0FC2_P_3,
2331   EVEX_W_0FC6_P_0,
2332   EVEX_W_0FC6_P_2,
2333   EVEX_W_0FD2_P_2,
2334   EVEX_W_0FD3_P_2,
2335   EVEX_W_0FD4_P_2,
2336   EVEX_W_0FD6_P_2,
2337   EVEX_W_0FE6_P_1,
2338   EVEX_W_0FE6_P_2,
2339   EVEX_W_0FE6_P_3,
2340   EVEX_W_0FE7_P_2,
2341   EVEX_W_0FF2_P_2,
2342   EVEX_W_0FF3_P_2,
2343   EVEX_W_0FF4_P_2,
2344   EVEX_W_0FFA_P_2,
2345   EVEX_W_0FFB_P_2,
2346   EVEX_W_0FFE_P_2,
2347   EVEX_W_0F380C_P_2,
2348   EVEX_W_0F380D_P_2,
2349   EVEX_W_0F3810_P_1,
2350   EVEX_W_0F3810_P_2,
2351   EVEX_W_0F3811_P_1,
2352   EVEX_W_0F3811_P_2,
2353   EVEX_W_0F3812_P_1,
2354   EVEX_W_0F3812_P_2,
2355   EVEX_W_0F3813_P_1,
2356   EVEX_W_0F3813_P_2,
2357   EVEX_W_0F3814_P_1,
2358   EVEX_W_0F3815_P_1,
2359   EVEX_W_0F3818_P_2,
2360   EVEX_W_0F3819_P_2,
2361   EVEX_W_0F381A_P_2,
2362   EVEX_W_0F381B_P_2,
2363   EVEX_W_0F381E_P_2,
2364   EVEX_W_0F381F_P_2,
2365   EVEX_W_0F3820_P_1,
2366   EVEX_W_0F3821_P_1,
2367   EVEX_W_0F3822_P_1,
2368   EVEX_W_0F3823_P_1,
2369   EVEX_W_0F3824_P_1,
2370   EVEX_W_0F3825_P_1,
2371   EVEX_W_0F3825_P_2,
2372   EVEX_W_0F3826_P_1,
2373   EVEX_W_0F3826_P_2,
2374   EVEX_W_0F3828_P_1,
2375   EVEX_W_0F3828_P_2,
2376   EVEX_W_0F3829_P_1,
2377   EVEX_W_0F3829_P_2,
2378   EVEX_W_0F382A_P_1,
2379   EVEX_W_0F382A_P_2,
2380   EVEX_W_0F382B_P_2,
2381   EVEX_W_0F3830_P_1,
2382   EVEX_W_0F3831_P_1,
2383   EVEX_W_0F3832_P_1,
2384   EVEX_W_0F3833_P_1,
2385   EVEX_W_0F3834_P_1,
2386   EVEX_W_0F3835_P_1,
2387   EVEX_W_0F3835_P_2,
2388   EVEX_W_0F3837_P_2,
2389   EVEX_W_0F3838_P_1,
2390   EVEX_W_0F3839_P_1,
2391   EVEX_W_0F383A_P_1,
2392   EVEX_W_0F3840_P_2,
2393   EVEX_W_0F3855_P_2,
2394   EVEX_W_0F3858_P_2,
2395   EVEX_W_0F3859_P_2,
2396   EVEX_W_0F385A_P_2,
2397   EVEX_W_0F385B_P_2,
2398   EVEX_W_0F3866_P_2,
2399   EVEX_W_0F3875_P_2,
2400   EVEX_W_0F3878_P_2,
2401   EVEX_W_0F3879_P_2,
2402   EVEX_W_0F387A_P_2,
2403   EVEX_W_0F387B_P_2,
2404   EVEX_W_0F387D_P_2,
2405   EVEX_W_0F3883_P_2,
2406   EVEX_W_0F388D_P_2,
2407   EVEX_W_0F3891_P_2,
2408   EVEX_W_0F3893_P_2,
2409   EVEX_W_0F38A1_P_2,
2410   EVEX_W_0F38A3_P_2,
2411   EVEX_W_0F38C7_R_1_P_2,
2412   EVEX_W_0F38C7_R_2_P_2,
2413   EVEX_W_0F38C7_R_5_P_2,
2414   EVEX_W_0F38C7_R_6_P_2,
2415
2416   EVEX_W_0F3A00_P_2,
2417   EVEX_W_0F3A01_P_2,
2418   EVEX_W_0F3A04_P_2,
2419   EVEX_W_0F3A05_P_2,
2420   EVEX_W_0F3A08_P_2,
2421   EVEX_W_0F3A09_P_2,
2422   EVEX_W_0F3A0A_P_2,
2423   EVEX_W_0F3A0B_P_2,
2424   EVEX_W_0F3A16_P_2,
2425   EVEX_W_0F3A18_P_2,
2426   EVEX_W_0F3A19_P_2,
2427   EVEX_W_0F3A1A_P_2,
2428   EVEX_W_0F3A1B_P_2,
2429   EVEX_W_0F3A1D_P_2,
2430   EVEX_W_0F3A21_P_2,
2431   EVEX_W_0F3A22_P_2,
2432   EVEX_W_0F3A23_P_2,
2433   EVEX_W_0F3A38_P_2,
2434   EVEX_W_0F3A39_P_2,
2435   EVEX_W_0F3A3A_P_2,
2436   EVEX_W_0F3A3B_P_2,
2437   EVEX_W_0F3A3E_P_2,
2438   EVEX_W_0F3A3F_P_2,
2439   EVEX_W_0F3A42_P_2,
2440   EVEX_W_0F3A43_P_2,
2441   EVEX_W_0F3A50_P_2,
2442   EVEX_W_0F3A51_P_2,
2443   EVEX_W_0F3A56_P_2,
2444   EVEX_W_0F3A57_P_2,
2445   EVEX_W_0F3A66_P_2,
2446   EVEX_W_0F3A67_P_2
2447 };
2448
2449 typedef void (*op_rtn) (int bytemode, int sizeflag);
2450
2451 struct dis386 {
2452   const char *name;
2453   struct
2454     {
2455       op_rtn rtn;
2456       int bytemode;
2457     } op[MAX_OPERANDS];
2458   unsigned int prefix_requirement;
2459 };
2460
2461 /* Upper case letters in the instruction names here are macros.
2462    'A' => print 'b' if no register operands or suffix_always is true
2463    'B' => print 'b' if suffix_always is true
2464    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2465           size prefix
2466    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467           suffix_always is true
2468    'E' => print 'e' if 32-bit form of jcxz
2469    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471    'H' => print ",pt" or ",pn" branch hint
2472    'I' => honor following macro letter even in Intel mode (implemented only
2473           for some of the macro letters)
2474    'J' => print 'l'
2475    'K' => print 'd' or 'q' if rex prefix is present.
2476    'L' => print 'l' if suffix_always is true
2477    'M' => print 'r' if intel_mnemonic is false.
2478    'N' => print 'n' if instruction has no wait "prefix"
2479    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481           or suffix_always is true.  print 'q' if rex prefix is present.
2482    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2483           is true
2484    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485    'S' => print 'w', 'l' or 'q' if suffix_always is true
2486    'T' => print 'q' in 64bit mode if instruction has no operand size
2487           prefix and behave as 'P' otherwise
2488    'U' => print 'q' in 64bit mode if instruction has no operand size
2489           prefix and behave as 'Q' otherwise
2490    'V' => print 'q' in 64bit mode if instruction has no operand size
2491           prefix and behave as 'S' otherwise
2492    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495           suffix_always is true.
2496    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497    '!' => change condition from true to false or from false to true.
2498    '%' => add 1 upper case letter to the macro.
2499    '^' => print 'w' or 'l' depending on operand size prefix or
2500           suffix_always is true (lcall/ljmp).
2501    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502           on operand size prefix.
2503    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504           has no operand size prefix for AMD64 ISA, behave as 'P'
2505           otherwise
2506
2507    2 upper case letter macros:
2508    "XY" => print 'x' or 'y' if suffix_always is true or no register
2509            operands and no broadcast.
2510    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511            register operands and no broadcast.
2512    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514            or suffix_always is true
2515    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518    "LW" => print 'd', 'q' depending on the VEX.W bit
2519    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520            an operand size prefix, or suffix_always is true.  print
2521            'q' if rex prefix is present.
2522
2523    Many of the above letters print nothing in Intel mode.  See "putop"
2524    for the details.
2525
2526    Braces '{' and '}', and vertical bars '|', indicate alternative
2527    mnemonic strings for AT&T and Intel.  */
2528
2529 static const struct dis386 dis386[] = {
2530   /* 00 */
2531   { "addB",             { Ebh1, Gb }, 0 },
2532   { "addS",             { Evh1, Gv }, 0 },
2533   { "addB",             { Gb, EbS }, 0 },
2534   { "addS",             { Gv, EvS }, 0 },
2535   { "addB",             { AL, Ib }, 0 },
2536   { "addS",             { eAX, Iv }, 0 },
2537   { X86_64_TABLE (X86_64_06) },
2538   { X86_64_TABLE (X86_64_07) },
2539   /* 08 */
2540   { "orB",              { Ebh1, Gb }, 0 },
2541   { "orS",              { Evh1, Gv }, 0 },
2542   { "orB",              { Gb, EbS }, 0 },
2543   { "orS",              { Gv, EvS }, 0 },
2544   { "orB",              { AL, Ib }, 0 },
2545   { "orS",              { eAX, Iv }, 0 },
2546   { X86_64_TABLE (X86_64_0D) },
2547   { Bad_Opcode },       /* 0x0f extended opcode escape */
2548   /* 10 */
2549   { "adcB",             { Ebh1, Gb }, 0 },
2550   { "adcS",             { Evh1, Gv }, 0 },
2551   { "adcB",             { Gb, EbS }, 0 },
2552   { "adcS",             { Gv, EvS }, 0 },
2553   { "adcB",             { AL, Ib }, 0 },
2554   { "adcS",             { eAX, Iv }, 0 },
2555   { X86_64_TABLE (X86_64_16) },
2556   { X86_64_TABLE (X86_64_17) },
2557   /* 18 */
2558   { "sbbB",             { Ebh1, Gb }, 0 },
2559   { "sbbS",             { Evh1, Gv }, 0 },
2560   { "sbbB",             { Gb, EbS }, 0 },
2561   { "sbbS",             { Gv, EvS }, 0 },
2562   { "sbbB",             { AL, Ib }, 0 },
2563   { "sbbS",             { eAX, Iv }, 0 },
2564   { X86_64_TABLE (X86_64_1E) },
2565   { X86_64_TABLE (X86_64_1F) },
2566   /* 20 */
2567   { "andB",             { Ebh1, Gb }, 0 },
2568   { "andS",             { Evh1, Gv }, 0 },
2569   { "andB",             { Gb, EbS }, 0 },
2570   { "andS",             { Gv, EvS }, 0 },
2571   { "andB",             { AL, Ib }, 0 },
2572   { "andS",             { eAX, Iv }, 0 },
2573   { Bad_Opcode },       /* SEG ES prefix */
2574   { X86_64_TABLE (X86_64_27) },
2575   /* 28 */
2576   { "subB",             { Ebh1, Gb }, 0 },
2577   { "subS",             { Evh1, Gv }, 0 },
2578   { "subB",             { Gb, EbS }, 0 },
2579   { "subS",             { Gv, EvS }, 0 },
2580   { "subB",             { AL, Ib }, 0 },
2581   { "subS",             { eAX, Iv }, 0 },
2582   { Bad_Opcode },       /* SEG CS prefix */
2583   { X86_64_TABLE (X86_64_2F) },
2584   /* 30 */
2585   { "xorB",             { Ebh1, Gb }, 0 },
2586   { "xorS",             { Evh1, Gv }, 0 },
2587   { "xorB",             { Gb, EbS }, 0 },
2588   { "xorS",             { Gv, EvS }, 0 },
2589   { "xorB",             { AL, Ib }, 0 },
2590   { "xorS",             { eAX, Iv }, 0 },
2591   { Bad_Opcode },       /* SEG SS prefix */
2592   { X86_64_TABLE (X86_64_37) },
2593   /* 38 */
2594   { "cmpB",             { Eb, Gb }, 0 },
2595   { "cmpS",             { Ev, Gv }, 0 },
2596   { "cmpB",             { Gb, EbS }, 0 },
2597   { "cmpS",             { Gv, EvS }, 0 },
2598   { "cmpB",             { AL, Ib }, 0 },
2599   { "cmpS",             { eAX, Iv }, 0 },
2600   { Bad_Opcode },       /* SEG DS prefix */
2601   { X86_64_TABLE (X86_64_3F) },
2602   /* 40 */
2603   { "inc{S|}",          { RMeAX }, 0 },
2604   { "inc{S|}",          { RMeCX }, 0 },
2605   { "inc{S|}",          { RMeDX }, 0 },
2606   { "inc{S|}",          { RMeBX }, 0 },
2607   { "inc{S|}",          { RMeSP }, 0 },
2608   { "inc{S|}",          { RMeBP }, 0 },
2609   { "inc{S|}",          { RMeSI }, 0 },
2610   { "inc{S|}",          { RMeDI }, 0 },
2611   /* 48 */
2612   { "dec{S|}",          { RMeAX }, 0 },
2613   { "dec{S|}",          { RMeCX }, 0 },
2614   { "dec{S|}",          { RMeDX }, 0 },
2615   { "dec{S|}",          { RMeBX }, 0 },
2616   { "dec{S|}",          { RMeSP }, 0 },
2617   { "dec{S|}",          { RMeBP }, 0 },
2618   { "dec{S|}",          { RMeSI }, 0 },
2619   { "dec{S|}",          { RMeDI }, 0 },
2620   /* 50 */
2621   { "pushV",            { RMrAX }, 0 },
2622   { "pushV",            { RMrCX }, 0 },
2623   { "pushV",            { RMrDX }, 0 },
2624   { "pushV",            { RMrBX }, 0 },
2625   { "pushV",            { RMrSP }, 0 },
2626   { "pushV",            { RMrBP }, 0 },
2627   { "pushV",            { RMrSI }, 0 },
2628   { "pushV",            { RMrDI }, 0 },
2629   /* 58 */
2630   { "popV",             { RMrAX }, 0 },
2631   { "popV",             { RMrCX }, 0 },
2632   { "popV",             { RMrDX }, 0 },
2633   { "popV",             { RMrBX }, 0 },
2634   { "popV",             { RMrSP }, 0 },
2635   { "popV",             { RMrBP }, 0 },
2636   { "popV",             { RMrSI }, 0 },
2637   { "popV",             { RMrDI }, 0 },
2638   /* 60 */
2639   { X86_64_TABLE (X86_64_60) },
2640   { X86_64_TABLE (X86_64_61) },
2641   { X86_64_TABLE (X86_64_62) },
2642   { X86_64_TABLE (X86_64_63) },
2643   { Bad_Opcode },       /* seg fs */
2644   { Bad_Opcode },       /* seg gs */
2645   { Bad_Opcode },       /* op size prefix */
2646   { Bad_Opcode },       /* adr size prefix */
2647   /* 68 */
2648   { "pushT",            { sIv }, 0 },
2649   { "imulS",            { Gv, Ev, Iv }, 0 },
2650   { "pushT",            { sIbT }, 0 },
2651   { "imulS",            { Gv, Ev, sIb }, 0 },
2652   { "ins{b|}",          { Ybr, indirDX }, 0 },
2653   { X86_64_TABLE (X86_64_6D) },
2654   { "outs{b|}",         { indirDXr, Xb }, 0 },
2655   { X86_64_TABLE (X86_64_6F) },
2656   /* 70 */
2657   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2660   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2662   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2663   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2664   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2665   /* 78 */
2666   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2667   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2668   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2669   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2670   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2671   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2672   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2673   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2674   /* 80 */
2675   { REG_TABLE (REG_80) },
2676   { REG_TABLE (REG_81) },
2677   { X86_64_TABLE (X86_64_82) },
2678   { REG_TABLE (REG_83) },
2679   { "testB",            { Eb, Gb }, 0 },
2680   { "testS",            { Ev, Gv }, 0 },
2681   { "xchgB",            { Ebh2, Gb }, 0 },
2682   { "xchgS",            { Evh2, Gv }, 0 },
2683   /* 88 */
2684   { "movB",             { Ebh3, Gb }, 0 },
2685   { "movS",             { Evh3, Gv }, 0 },
2686   { "movB",             { Gb, EbS }, 0 },
2687   { "movS",             { Gv, EvS }, 0 },
2688   { "movD",             { Sv, Sw }, 0 },
2689   { MOD_TABLE (MOD_8D) },
2690   { "movD",             { Sw, Sv }, 0 },
2691   { REG_TABLE (REG_8F) },
2692   /* 90 */
2693   { PREFIX_TABLE (PREFIX_90) },
2694   { "xchgS",            { RMeCX, eAX }, 0 },
2695   { "xchgS",            { RMeDX, eAX }, 0 },
2696   { "xchgS",            { RMeBX, eAX }, 0 },
2697   { "xchgS",            { RMeSP, eAX }, 0 },
2698   { "xchgS",            { RMeBP, eAX }, 0 },
2699   { "xchgS",            { RMeSI, eAX }, 0 },
2700   { "xchgS",            { RMeDI, eAX }, 0 },
2701   /* 98 */
2702   { "cW{t|}R",          { XX }, 0 },
2703   { "cR{t|}O",          { XX }, 0 },
2704   { X86_64_TABLE (X86_64_9A) },
2705   { Bad_Opcode },       /* fwait */
2706   { "pushfT",           { XX }, 0 },
2707   { "popfT",            { XX }, 0 },
2708   { "sahf",             { XX }, 0 },
2709   { "lahf",             { XX }, 0 },
2710   /* a0 */
2711   { "mov%LB",           { AL, Ob }, 0 },
2712   { "mov%LS",           { eAX, Ov }, 0 },
2713   { "mov%LB",           { Ob, AL }, 0 },
2714   { "mov%LS",           { Ov, eAX }, 0 },
2715   { "movs{b|}",         { Ybr, Xb }, 0 },
2716   { "movs{R|}",         { Yvr, Xv }, 0 },
2717   { "cmps{b|}",         { Xb, Yb }, 0 },
2718   { "cmps{R|}",         { Xv, Yv }, 0 },
2719   /* a8 */
2720   { "testB",            { AL, Ib }, 0 },
2721   { "testS",            { eAX, Iv }, 0 },
2722   { "stosB",            { Ybr, AL }, 0 },
2723   { "stosS",            { Yvr, eAX }, 0 },
2724   { "lodsB",            { ALr, Xb }, 0 },
2725   { "lodsS",            { eAXr, Xv }, 0 },
2726   { "scasB",            { AL, Yb }, 0 },
2727   { "scasS",            { eAX, Yv }, 0 },
2728   /* b0 */
2729   { "movB",             { RMAL, Ib }, 0 },
2730   { "movB",             { RMCL, Ib }, 0 },
2731   { "movB",             { RMDL, Ib }, 0 },
2732   { "movB",             { RMBL, Ib }, 0 },
2733   { "movB",             { RMAH, Ib }, 0 },
2734   { "movB",             { RMCH, Ib }, 0 },
2735   { "movB",             { RMDH, Ib }, 0 },
2736   { "movB",             { RMBH, Ib }, 0 },
2737   /* b8 */
2738   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2739   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2740   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2741   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2742   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2743   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2744   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2745   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2746   /* c0 */
2747   { REG_TABLE (REG_C0) },
2748   { REG_TABLE (REG_C1) },
2749   { "retT",             { Iw, BND }, 0 },
2750   { "retT",             { BND }, 0 },
2751   { X86_64_TABLE (X86_64_C4) },
2752   { X86_64_TABLE (X86_64_C5) },
2753   { REG_TABLE (REG_C6) },
2754   { REG_TABLE (REG_C7) },
2755   /* c8 */
2756   { "enterT",           { Iw, Ib }, 0 },
2757   { "leaveT",           { XX }, 0 },
2758   { "Jret{|f}P",        { Iw }, 0 },
2759   { "Jret{|f}P",        { XX }, 0 },
2760   { "int3",             { XX }, 0 },
2761   { "int",              { Ib }, 0 },
2762   { X86_64_TABLE (X86_64_CE) },
2763   { "iret%LP",          { XX }, 0 },
2764   /* d0 */
2765   { REG_TABLE (REG_D0) },
2766   { REG_TABLE (REG_D1) },
2767   { REG_TABLE (REG_D2) },
2768   { REG_TABLE (REG_D3) },
2769   { X86_64_TABLE (X86_64_D4) },
2770   { X86_64_TABLE (X86_64_D5) },
2771   { Bad_Opcode },
2772   { "xlat",             { DSBX }, 0 },
2773   /* d8 */
2774   { FLOAT },
2775   { FLOAT },
2776   { FLOAT },
2777   { FLOAT },
2778   { FLOAT },
2779   { FLOAT },
2780   { FLOAT },
2781   { FLOAT },
2782   /* e0 */
2783   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2784   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2785   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2786   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2787   { "inB",              { AL, Ib }, 0 },
2788   { "inG",              { zAX, Ib }, 0 },
2789   { "outB",             { Ib, AL }, 0 },
2790   { "outG",             { Ib, zAX }, 0 },
2791   /* e8 */
2792   { X86_64_TABLE (X86_64_E8) },
2793   { X86_64_TABLE (X86_64_E9) },
2794   { X86_64_TABLE (X86_64_EA) },
2795   { "jmp",              { Jb, BND }, 0 },
2796   { "inB",              { AL, indirDX }, 0 },
2797   { "inG",              { zAX, indirDX }, 0 },
2798   { "outB",             { indirDX, AL }, 0 },
2799   { "outG",             { indirDX, zAX }, 0 },
2800   /* f0 */
2801   { Bad_Opcode },       /* lock prefix */
2802   { "icebp",            { XX }, 0 },
2803   { Bad_Opcode },       /* repne */
2804   { Bad_Opcode },       /* repz */
2805   { "hlt",              { XX }, 0 },
2806   { "cmc",              { XX }, 0 },
2807   { REG_TABLE (REG_F6) },
2808   { REG_TABLE (REG_F7) },
2809   /* f8 */
2810   { "clc",              { XX }, 0 },
2811   { "stc",              { XX }, 0 },
2812   { "cli",              { XX }, 0 },
2813   { "sti",              { XX }, 0 },
2814   { "cld",              { XX }, 0 },
2815   { "std",              { XX }, 0 },
2816   { REG_TABLE (REG_FE) },
2817   { REG_TABLE (REG_FF) },
2818 };
2819
2820 static const struct dis386 dis386_twobyte[] = {
2821   /* 00 */
2822   { REG_TABLE (REG_0F00 ) },
2823   { REG_TABLE (REG_0F01 ) },
2824   { "larS",             { Gv, Ew }, 0 },
2825   { "lslS",             { Gv, Ew }, 0 },
2826   { Bad_Opcode },
2827   { "syscall",          { XX }, 0 },
2828   { "clts",             { XX }, 0 },
2829   { "sysret%LP",                { XX }, 0 },
2830   /* 08 */
2831   { "invd",             { XX }, 0 },
2832   { "wbinvd",           { XX }, 0 },
2833   { Bad_Opcode },
2834   { "ud2",              { XX }, 0 },
2835   { Bad_Opcode },
2836   { REG_TABLE (REG_0F0D) },
2837   { "femms",            { XX }, 0 },
2838   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2839   /* 10 */
2840   { PREFIX_TABLE (PREFIX_0F10) },
2841   { PREFIX_TABLE (PREFIX_0F11) },
2842   { PREFIX_TABLE (PREFIX_0F12) },
2843   { MOD_TABLE (MOD_0F13) },
2844   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2845   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2846   { PREFIX_TABLE (PREFIX_0F16) },
2847   { MOD_TABLE (MOD_0F17) },
2848   /* 18 */
2849   { REG_TABLE (REG_0F18) },
2850   { "nopQ",             { Ev }, 0 },
2851   { PREFIX_TABLE (PREFIX_0F1A) },
2852   { PREFIX_TABLE (PREFIX_0F1B) },
2853   { "nopQ",             { Ev }, 0 },
2854   { "nopQ",             { Ev }, 0 },
2855   { PREFIX_TABLE (PREFIX_0F1E) },
2856   { "nopQ",             { Ev }, 0 },
2857   /* 20 */
2858   { "movZ",             { Rm, Cm }, 0 },
2859   { "movZ",             { Rm, Dm }, 0 },
2860   { "movZ",             { Cm, Rm }, 0 },
2861   { "movZ",             { Dm, Rm }, 0 },
2862   { MOD_TABLE (MOD_0F24) },
2863   { Bad_Opcode },
2864   { MOD_TABLE (MOD_0F26) },
2865   { Bad_Opcode },
2866   /* 28 */
2867   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2868   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2869   { PREFIX_TABLE (PREFIX_0F2A) },
2870   { PREFIX_TABLE (PREFIX_0F2B) },
2871   { PREFIX_TABLE (PREFIX_0F2C) },
2872   { PREFIX_TABLE (PREFIX_0F2D) },
2873   { PREFIX_TABLE (PREFIX_0F2E) },
2874   { PREFIX_TABLE (PREFIX_0F2F) },
2875   /* 30 */
2876   { "wrmsr",            { XX }, 0 },
2877   { "rdtsc",            { XX }, 0 },
2878   { "rdmsr",            { XX }, 0 },
2879   { "rdpmc",            { XX }, 0 },
2880   { "sysenter",         { XX }, 0 },
2881   { "sysexit",          { XX }, 0 },
2882   { Bad_Opcode },
2883   { "getsec",           { XX }, 0 },
2884   /* 38 */
2885   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2886   { Bad_Opcode },
2887   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2888   { Bad_Opcode },
2889   { Bad_Opcode },
2890   { Bad_Opcode },
2891   { Bad_Opcode },
2892   { Bad_Opcode },
2893   /* 40 */
2894   { "cmovoS",           { Gv, Ev }, 0 },
2895   { "cmovnoS",          { Gv, Ev }, 0 },
2896   { "cmovbS",           { Gv, Ev }, 0 },
2897   { "cmovaeS",          { Gv, Ev }, 0 },
2898   { "cmoveS",           { Gv, Ev }, 0 },
2899   { "cmovneS",          { Gv, Ev }, 0 },
2900   { "cmovbeS",          { Gv, Ev }, 0 },
2901   { "cmovaS",           { Gv, Ev }, 0 },
2902   /* 48 */
2903   { "cmovsS",           { Gv, Ev }, 0 },
2904   { "cmovnsS",          { Gv, Ev }, 0 },
2905   { "cmovpS",           { Gv, Ev }, 0 },
2906   { "cmovnpS",          { Gv, Ev }, 0 },
2907   { "cmovlS",           { Gv, Ev }, 0 },
2908   { "cmovgeS",          { Gv, Ev }, 0 },
2909   { "cmovleS",          { Gv, Ev }, 0 },
2910   { "cmovgS",           { Gv, Ev }, 0 },
2911   /* 50 */
2912   { MOD_TABLE (MOD_0F51) },
2913   { PREFIX_TABLE (PREFIX_0F51) },
2914   { PREFIX_TABLE (PREFIX_0F52) },
2915   { PREFIX_TABLE (PREFIX_0F53) },
2916   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2917   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2918   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2919   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2920   /* 58 */
2921   { PREFIX_TABLE (PREFIX_0F58) },
2922   { PREFIX_TABLE (PREFIX_0F59) },
2923   { PREFIX_TABLE (PREFIX_0F5A) },
2924   { PREFIX_TABLE (PREFIX_0F5B) },
2925   { PREFIX_TABLE (PREFIX_0F5C) },
2926   { PREFIX_TABLE (PREFIX_0F5D) },
2927   { PREFIX_TABLE (PREFIX_0F5E) },
2928   { PREFIX_TABLE (PREFIX_0F5F) },
2929   /* 60 */
2930   { PREFIX_TABLE (PREFIX_0F60) },
2931   { PREFIX_TABLE (PREFIX_0F61) },
2932   { PREFIX_TABLE (PREFIX_0F62) },
2933   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2934   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2935   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2936   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2937   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2938   /* 68 */
2939   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2940   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2941   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2942   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2943   { PREFIX_TABLE (PREFIX_0F6C) },
2944   { PREFIX_TABLE (PREFIX_0F6D) },
2945   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2946   { PREFIX_TABLE (PREFIX_0F6F) },
2947   /* 70 */
2948   { PREFIX_TABLE (PREFIX_0F70) },
2949   { REG_TABLE (REG_0F71) },
2950   { REG_TABLE (REG_0F72) },
2951   { REG_TABLE (REG_0F73) },
2952   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2953   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2954   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2955   { "emms",             { XX }, PREFIX_OPCODE },
2956   /* 78 */
2957   { PREFIX_TABLE (PREFIX_0F78) },
2958   { PREFIX_TABLE (PREFIX_0F79) },
2959   { Bad_Opcode },
2960   { Bad_Opcode },
2961   { PREFIX_TABLE (PREFIX_0F7C) },
2962   { PREFIX_TABLE (PREFIX_0F7D) },
2963   { PREFIX_TABLE (PREFIX_0F7E) },
2964   { PREFIX_TABLE (PREFIX_0F7F) },
2965   /* 80 */
2966   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2969   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2971   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2972   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2973   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2974   /* 88 */
2975   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2976   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2977   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2978   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2979   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2980   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2981   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2982   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2983   /* 90 */
2984   { "seto",             { Eb }, 0 },
2985   { "setno",            { Eb }, 0 },
2986   { "setb",             { Eb }, 0 },
2987   { "setae",            { Eb }, 0 },
2988   { "sete",             { Eb }, 0 },
2989   { "setne",            { Eb }, 0 },
2990   { "setbe",            { Eb }, 0 },
2991   { "seta",             { Eb }, 0 },
2992   /* 98 */
2993   { "sets",             { Eb }, 0 },
2994   { "setns",            { Eb }, 0 },
2995   { "setp",             { Eb }, 0 },
2996   { "setnp",            { Eb }, 0 },
2997   { "setl",             { Eb }, 0 },
2998   { "setge",            { Eb }, 0 },
2999   { "setle",            { Eb }, 0 },
3000   { "setg",             { Eb }, 0 },
3001   /* a0 */
3002   { "pushT",            { fs }, 0 },
3003   { "popT",             { fs }, 0 },
3004   { "cpuid",            { XX }, 0 },
3005   { "btS",              { Ev, Gv }, 0 },
3006   { "shldS",            { Ev, Gv, Ib }, 0 },
3007   { "shldS",            { Ev, Gv, CL }, 0 },
3008   { REG_TABLE (REG_0FA6) },
3009   { REG_TABLE (REG_0FA7) },
3010   /* a8 */
3011   { "pushT",            { gs }, 0 },
3012   { "popT",             { gs }, 0 },
3013   { "rsm",              { XX }, 0 },
3014   { "btsS",             { Evh1, Gv }, 0 },
3015   { "shrdS",            { Ev, Gv, Ib }, 0 },
3016   { "shrdS",            { Ev, Gv, CL }, 0 },
3017   { REG_TABLE (REG_0FAE) },
3018   { "imulS",            { Gv, Ev }, 0 },
3019   /* b0 */
3020   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3021   { "cmpxchgS",         { Evh1, Gv }, 0 },
3022   { MOD_TABLE (MOD_0FB2) },
3023   { "btrS",             { Evh1, Gv }, 0 },
3024   { MOD_TABLE (MOD_0FB4) },
3025   { MOD_TABLE (MOD_0FB5) },
3026   { "movz{bR|x}",       { Gv, Eb }, 0 },
3027   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3028   /* b8 */
3029   { PREFIX_TABLE (PREFIX_0FB8) },
3030   { "ud1",              { XX }, 0 },
3031   { REG_TABLE (REG_0FBA) },
3032   { "btcS",             { Evh1, Gv }, 0 },
3033   { PREFIX_TABLE (PREFIX_0FBC) },
3034   { PREFIX_TABLE (PREFIX_0FBD) },
3035   { "movs{bR|x}",       { Gv, Eb }, 0 },
3036   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3037   /* c0 */
3038   { "xaddB",            { Ebh1, Gb }, 0 },
3039   { "xaddS",            { Evh1, Gv }, 0 },
3040   { PREFIX_TABLE (PREFIX_0FC2) },
3041   { MOD_TABLE (MOD_0FC3) },
3042   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3043   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3044   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3045   { REG_TABLE (REG_0FC7) },
3046   /* c8 */
3047   { "bswap",            { RMeAX }, 0 },
3048   { "bswap",            { RMeCX }, 0 },
3049   { "bswap",            { RMeDX }, 0 },
3050   { "bswap",            { RMeBX }, 0 },
3051   { "bswap",            { RMeSP }, 0 },
3052   { "bswap",            { RMeBP }, 0 },
3053   { "bswap",            { RMeSI }, 0 },
3054   { "bswap",            { RMeDI }, 0 },
3055   /* d0 */
3056   { PREFIX_TABLE (PREFIX_0FD0) },
3057   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3058   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3059   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3060   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3061   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3062   { PREFIX_TABLE (PREFIX_0FD6) },
3063   { MOD_TABLE (MOD_0FD7) },
3064   /* d8 */
3065   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3066   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3067   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3068   { "pand",             { MX, EM }, PREFIX_OPCODE },
3069   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3070   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3071   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3072   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3073   /* e0 */
3074   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3075   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3076   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3077   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3078   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3079   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3080   { PREFIX_TABLE (PREFIX_0FE6) },
3081   { PREFIX_TABLE (PREFIX_0FE7) },
3082   /* e8 */
3083   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3084   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3085   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3086   { "por",              { MX, EM }, PREFIX_OPCODE },
3087   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3088   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3089   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3090   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3091   /* f0 */
3092   { PREFIX_TABLE (PREFIX_0FF0) },
3093   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3094   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3095   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3096   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3097   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3098   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3099   { PREFIX_TABLE (PREFIX_0FF7) },
3100   /* f8 */
3101   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3102   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3103   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3104   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3105   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3106   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3107   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3108   { Bad_Opcode },
3109 };
3110
3111 static const unsigned char onebyte_has_modrm[256] = {
3112   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3113   /*       -------------------------------        */
3114   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3130   /*       -------------------------------        */
3131   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3132 };
3133
3134 static const unsigned char twobyte_has_modrm[256] = {
3135   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3136   /*       -------------------------------        */
3137   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3153   /*       -------------------------------        */
3154   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3155 };
3156
3157 static char obuf[100];
3158 static char *obufp;
3159 static char *mnemonicendp;
3160 static char scratchbuf[100];
3161 static unsigned char *start_codep;
3162 static unsigned char *insn_codep;
3163 static unsigned char *codep;
3164 static unsigned char *end_codep;
3165 static int last_lock_prefix;
3166 static int last_repz_prefix;
3167 static int last_repnz_prefix;
3168 static int last_data_prefix;
3169 static int last_addr_prefix;
3170 static int last_rex_prefix;
3171 static int last_seg_prefix;
3172 static int last_active_prefix;
3173 static int fwait_prefix;
3174 /* The active segment register prefix.  */
3175 static int active_seg_prefix;
3176 #define MAX_CODE_LENGTH 15
3177 /* We can up to 14 prefixes since the maximum instruction length is
3178    15bytes.  */
3179 static int all_prefixes[MAX_CODE_LENGTH - 1];
3180 static disassemble_info *the_info;
3181 static struct
3182   {
3183     int mod;
3184     int reg;
3185     int rm;
3186   }
3187 modrm;
3188 static unsigned char need_modrm;
3189 static struct
3190   {
3191     int scale;
3192     int index;
3193     int base;
3194   }
3195 sib;
3196 static struct
3197   {
3198     int register_specifier;
3199     int length;
3200     int prefix;
3201     int w;
3202     int evex;
3203     int r;
3204     int v;
3205     int mask_register_specifier;
3206     int zeroing;
3207     int ll;
3208     int b;
3209   }
3210 vex;
3211 static unsigned char need_vex;
3212 static unsigned char need_vex_reg;
3213 static unsigned char vex_w_done;
3214
3215 struct op
3216   {
3217     const char *name;
3218     unsigned int len;
3219   };
3220
3221 /* If we are accessing mod/rm/reg without need_modrm set, then the
3222    values are stale.  Hitting this abort likely indicates that you
3223    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3224 #define MODRM_CHECK  if (!need_modrm) abort ()
3225
3226 static const char **names64;
3227 static const char **names32;
3228 static const char **names16;
3229 static const char **names8;
3230 static const char **names8rex;
3231 static const char **names_seg;
3232 static const char *index64;
3233 static const char *index32;
3234 static const char **index16;
3235 static const char **names_bnd;
3236
3237 static const char *intel_names64[] = {
3238   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3239   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3240 };
3241 static const char *intel_names32[] = {
3242   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3243   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3244 };
3245 static const char *intel_names16[] = {
3246   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3247   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3248 };
3249 static const char *intel_names8[] = {
3250   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3251 };
3252 static const char *intel_names8rex[] = {
3253   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3254   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3255 };
3256 static const char *intel_names_seg[] = {
3257   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3258 };
3259 static const char *intel_index64 = "riz";
3260 static const char *intel_index32 = "eiz";
3261 static const char *intel_index16[] = {
3262   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3263 };
3264
3265 static const char *att_names64[] = {
3266   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3267   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3268 };
3269 static const char *att_names32[] = {
3270   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3271   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3272 };
3273 static const char *att_names16[] = {
3274   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3275   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3276 };
3277 static const char *att_names8[] = {
3278   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3279 };
3280 static const char *att_names8rex[] = {
3281   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3282   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3283 };
3284 static const char *att_names_seg[] = {
3285   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3286 };
3287 static const char *att_index64 = "%riz";
3288 static const char *att_index32 = "%eiz";
3289 static const char *att_index16[] = {
3290   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3291 };
3292
3293 static const char **names_mm;
3294 static const char *intel_names_mm[] = {
3295   "mm0", "mm1", "mm2", "mm3",
3296   "mm4", "mm5", "mm6", "mm7"
3297 };
3298 static const char *att_names_mm[] = {
3299   "%mm0", "%mm1", "%mm2", "%mm3",
3300   "%mm4", "%mm5", "%mm6", "%mm7"
3301 };
3302
3303 static const char *intel_names_bnd[] = {
3304   "bnd0", "bnd1", "bnd2", "bnd3"
3305 };
3306
3307 static const char *att_names_bnd[] = {
3308   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3309 };
3310
3311 static const char **names_xmm;
3312 static const char *intel_names_xmm[] = {
3313   "xmm0", "xmm1", "xmm2", "xmm3",
3314   "xmm4", "xmm5", "xmm6", "xmm7",
3315   "xmm8", "xmm9", "xmm10", "xmm11",
3316   "xmm12", "xmm13", "xmm14", "xmm15",
3317   "xmm16", "xmm17", "xmm18", "xmm19",
3318   "xmm20", "xmm21", "xmm22", "xmm23",
3319   "xmm24", "xmm25", "xmm26", "xmm27",
3320   "xmm28", "xmm29", "xmm30", "xmm31"
3321 };
3322 static const char *att_names_xmm[] = {
3323   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3324   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3325   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3326   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3327   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3328   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3329   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3330   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3331 };
3332
3333 static const char **names_ymm;
3334 static const char *intel_names_ymm[] = {
3335   "ymm0", "ymm1", "ymm2", "ymm3",
3336   "ymm4", "ymm5", "ymm6", "ymm7",
3337   "ymm8", "ymm9", "ymm10", "ymm11",
3338   "ymm12", "ymm13", "ymm14", "ymm15",
3339   "ymm16", "ymm17", "ymm18", "ymm19",
3340   "ymm20", "ymm21", "ymm22", "ymm23",
3341   "ymm24", "ymm25", "ymm26", "ymm27",
3342   "ymm28", "ymm29", "ymm30", "ymm31"
3343 };
3344 static const char *att_names_ymm[] = {
3345   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3346   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3347   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3348   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3349   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3350   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3351   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3352   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3353 };
3354
3355 static const char **names_zmm;
3356 static const char *intel_names_zmm[] = {
3357   "zmm0", "zmm1", "zmm2", "zmm3",
3358   "zmm4", "zmm5", "zmm6", "zmm7",
3359   "zmm8", "zmm9", "zmm10", "zmm11",
3360   "zmm12", "zmm13", "zmm14", "zmm15",
3361   "zmm16", "zmm17", "zmm18", "zmm19",
3362   "zmm20", "zmm21", "zmm22", "zmm23",
3363   "zmm24", "zmm25", "zmm26", "zmm27",
3364   "zmm28", "zmm29", "zmm30", "zmm31"
3365 };
3366 static const char *att_names_zmm[] = {
3367   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3368   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3369   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3370   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3371   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3372   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3373   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3374   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3375 };
3376
3377 static const char **names_mask;
3378 static const char *intel_names_mask[] = {
3379   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3380 };
3381 static const char *att_names_mask[] = {
3382   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3383 };
3384
3385 static const char *names_rounding[] =
3386 {
3387   "{rn-sae}",
3388   "{rd-sae}",
3389   "{ru-sae}",
3390   "{rz-sae}"
3391 };
3392
3393 static const struct dis386 reg_table[][8] = {
3394   /* REG_80 */
3395   {
3396     { "addA",   { Ebh1, Ib }, 0 },
3397     { "orA",    { Ebh1, Ib }, 0 },
3398     { "adcA",   { Ebh1, Ib }, 0 },
3399     { "sbbA",   { Ebh1, Ib }, 0 },
3400     { "andA",   { Ebh1, Ib }, 0 },
3401     { "subA",   { Ebh1, Ib }, 0 },
3402     { "xorA",   { Ebh1, Ib }, 0 },
3403     { "cmpA",   { Eb, Ib }, 0 },
3404   },
3405   /* REG_81 */
3406   {
3407     { "addQ",   { Evh1, Iv }, 0 },
3408     { "orQ",    { Evh1, Iv }, 0 },
3409     { "adcQ",   { Evh1, Iv }, 0 },
3410     { "sbbQ",   { Evh1, Iv }, 0 },
3411     { "andQ",   { Evh1, Iv }, 0 },
3412     { "subQ",   { Evh1, Iv }, 0 },
3413     { "xorQ",   { Evh1, Iv }, 0 },
3414     { "cmpQ",   { Ev, Iv }, 0 },
3415   },
3416   /* REG_83 */
3417   {
3418     { "addQ",   { Evh1, sIb }, 0 },
3419     { "orQ",    { Evh1, sIb }, 0 },
3420     { "adcQ",   { Evh1, sIb }, 0 },
3421     { "sbbQ",   { Evh1, sIb }, 0 },
3422     { "andQ",   { Evh1, sIb }, 0 },
3423     { "subQ",   { Evh1, sIb }, 0 },
3424     { "xorQ",   { Evh1, sIb }, 0 },
3425     { "cmpQ",   { Ev, sIb }, 0 },
3426   },
3427   /* REG_8F */
3428   {
3429     { "popU",   { stackEv }, 0 },
3430     { XOP_8F_TABLE (XOP_09) },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { Bad_Opcode },
3434     { XOP_8F_TABLE (XOP_09) },
3435   },
3436   /* REG_C0 */
3437   {
3438     { "rolA",   { Eb, Ib }, 0 },
3439     { "rorA",   { Eb, Ib }, 0 },
3440     { "rclA",   { Eb, Ib }, 0 },
3441     { "rcrA",   { Eb, Ib }, 0 },
3442     { "shlA",   { Eb, Ib }, 0 },
3443     { "shrA",   { Eb, Ib }, 0 },
3444     { Bad_Opcode },
3445     { "sarA",   { Eb, Ib }, 0 },
3446   },
3447   /* REG_C1 */
3448   {
3449     { "rolQ",   { Ev, Ib }, 0 },
3450     { "rorQ",   { Ev, Ib }, 0 },
3451     { "rclQ",   { Ev, Ib }, 0 },
3452     { "rcrQ",   { Ev, Ib }, 0 },
3453     { "shlQ",   { Ev, Ib }, 0 },
3454     { "shrQ",   { Ev, Ib }, 0 },
3455     { Bad_Opcode },
3456     { "sarQ",   { Ev, Ib }, 0 },
3457   },
3458   /* REG_C6 */
3459   {
3460     { "movA",   { Ebh3, Ib }, 0 },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_C6_REG_7) },
3468   },
3469   /* REG_C7 */
3470   {
3471     { "movQ",   { Evh3, Iv }, 0 },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_C7_REG_7) },
3479   },
3480   /* REG_D0 */
3481   {
3482     { "rolA",   { Eb, I1 }, 0 },
3483     { "rorA",   { Eb, I1 }, 0 },
3484     { "rclA",   { Eb, I1 }, 0 },
3485     { "rcrA",   { Eb, I1 }, 0 },
3486     { "shlA",   { Eb, I1 }, 0 },
3487     { "shrA",   { Eb, I1 }, 0 },
3488     { Bad_Opcode },
3489     { "sarA",   { Eb, I1 }, 0 },
3490   },
3491   /* REG_D1 */
3492   {
3493     { "rolQ",   { Ev, I1 }, 0 },
3494     { "rorQ",   { Ev, I1 }, 0 },
3495     { "rclQ",   { Ev, I1 }, 0 },
3496     { "rcrQ",   { Ev, I1 }, 0 },
3497     { "shlQ",   { Ev, I1 }, 0 },
3498     { "shrQ",   { Ev, I1 }, 0 },
3499     { Bad_Opcode },
3500     { "sarQ",   { Ev, I1 }, 0 },
3501   },
3502   /* REG_D2 */
3503   {
3504     { "rolA",   { Eb, CL }, 0 },
3505     { "rorA",   { Eb, CL }, 0 },
3506     { "rclA",   { Eb, CL }, 0 },
3507     { "rcrA",   { Eb, CL }, 0 },
3508     { "shlA",   { Eb, CL }, 0 },
3509     { "shrA",   { Eb, CL }, 0 },
3510     { Bad_Opcode },
3511     { "sarA",   { Eb, CL }, 0 },
3512   },
3513   /* REG_D3 */
3514   {
3515     { "rolQ",   { Ev, CL }, 0 },
3516     { "rorQ",   { Ev, CL }, 0 },
3517     { "rclQ",   { Ev, CL }, 0 },
3518     { "rcrQ",   { Ev, CL }, 0 },
3519     { "shlQ",   { Ev, CL }, 0 },
3520     { "shrQ",   { Ev, CL }, 0 },
3521     { Bad_Opcode },
3522     { "sarQ",   { Ev, CL }, 0 },
3523   },
3524   /* REG_F6 */
3525   {
3526     { "testA",  { Eb, Ib }, 0 },
3527     { "testA",  { Eb, Ib }, 0 },
3528     { "notA",   { Ebh1 }, 0 },
3529     { "negA",   { Ebh1 }, 0 },
3530     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3531     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3532     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3533     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3534   },
3535   /* REG_F7 */
3536   {
3537     { "testQ",  { Ev, Iv }, 0 },
3538     { "testQ",  { Ev, Iv }, 0 },
3539     { "notQ",   { Evh1 }, 0 },
3540     { "negQ",   { Evh1 }, 0 },
3541     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3542     { "imulQ",  { Ev }, 0 },
3543     { "divQ",   { Ev }, 0 },
3544     { "idivQ",  { Ev }, 0 },
3545   },
3546   /* REG_FE */
3547   {
3548     { "incA",   { Ebh1 }, 0 },
3549     { "decA",   { Ebh1 }, 0 },
3550   },
3551   /* REG_FF */
3552   {
3553     { "incQ",   { Evh1 }, 0 },
3554     { "decQ",   { Evh1 }, 0 },
3555     { "call{&|}", { indirEv, NOTRACK, BND }, 0 },
3556     { MOD_TABLE (MOD_FF_REG_3) },
3557     { "jmp{&|}", { indirEv, NOTRACK, BND }, 0 },
3558     { MOD_TABLE (MOD_FF_REG_5) },
3559     { "pushU",  { stackEv }, 0 },
3560     { Bad_Opcode },
3561   },
3562   /* REG_0F00 */
3563   {
3564     { "sldtD",  { Sv }, 0 },
3565     { "strD",   { Sv }, 0 },
3566     { "lldt",   { Ew }, 0 },
3567     { "ltr",    { Ew }, 0 },
3568     { "verr",   { Ew }, 0 },
3569     { "verw",   { Ew }, 0 },
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572   },
3573   /* REG_0F01 */
3574   {
3575     { MOD_TABLE (MOD_0F01_REG_0) },
3576     { MOD_TABLE (MOD_0F01_REG_1) },
3577     { MOD_TABLE (MOD_0F01_REG_2) },
3578     { MOD_TABLE (MOD_0F01_REG_3) },
3579     { "smswD",  { Sv }, 0 },
3580     { MOD_TABLE (MOD_0F01_REG_5) },
3581     { "lmsw",   { Ew }, 0 },
3582     { MOD_TABLE (MOD_0F01_REG_7) },
3583   },
3584   /* REG_0F0D */
3585   {
3586     { "prefetch",       { Mb }, 0 },
3587     { "prefetchw",      { Mb }, 0 },
3588     { "prefetchwt1",    { Mb }, 0 },
3589     { "prefetch",       { Mb }, 0 },
3590     { "prefetch",       { Mb }, 0 },
3591     { "prefetch",       { Mb }, 0 },
3592     { "prefetch",       { Mb }, 0 },
3593     { "prefetch",       { Mb }, 0 },
3594   },
3595   /* REG_0F18 */
3596   {
3597     { MOD_TABLE (MOD_0F18_REG_0) },
3598     { MOD_TABLE (MOD_0F18_REG_1) },
3599     { MOD_TABLE (MOD_0F18_REG_2) },
3600     { MOD_TABLE (MOD_0F18_REG_3) },
3601     { MOD_TABLE (MOD_0F18_REG_4) },
3602     { MOD_TABLE (MOD_0F18_REG_5) },
3603     { MOD_TABLE (MOD_0F18_REG_6) },
3604     { MOD_TABLE (MOD_0F18_REG_7) },
3605   },
3606   /* REG_0F1E_MOD_3 */
3607   {
3608     { "nopQ",           { Ev }, 0 },
3609     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3610     { "nopQ",           { Ev }, 0 },
3611     { "nopQ",           { Ev }, 0 },
3612     { "nopQ",           { Ev }, 0 },
3613     { "nopQ",           { Ev }, 0 },
3614     { "nopQ",           { Ev }, 0 },
3615     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3616   },
3617   /* REG_0F71 */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_0F71_REG_2) },
3622     { Bad_Opcode },
3623     { MOD_TABLE (MOD_0F71_REG_4) },
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_0F71_REG_6) },
3626   },
3627   /* REG_0F72 */
3628   {
3629     { Bad_Opcode },
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F72_REG_2) },
3632     { Bad_Opcode },
3633     { MOD_TABLE (MOD_0F72_REG_4) },
3634     { Bad_Opcode },
3635     { MOD_TABLE (MOD_0F72_REG_6) },
3636   },
3637   /* REG_0F73 */
3638   {
3639     { Bad_Opcode },
3640     { Bad_Opcode },
3641     { MOD_TABLE (MOD_0F73_REG_2) },
3642     { MOD_TABLE (MOD_0F73_REG_3) },
3643     { Bad_Opcode },
3644     { Bad_Opcode },
3645     { MOD_TABLE (MOD_0F73_REG_6) },
3646     { MOD_TABLE (MOD_0F73_REG_7) },
3647   },
3648   /* REG_0FA6 */
3649   {
3650     { "montmul",        { { OP_0f07, 0 } }, 0 },
3651     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3652     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3653   },
3654   /* REG_0FA7 */
3655   {
3656     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3657     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3658     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3659     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3660     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3661     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3662   },
3663   /* REG_0FAE */
3664   {
3665     { MOD_TABLE (MOD_0FAE_REG_0) },
3666     { MOD_TABLE (MOD_0FAE_REG_1) },
3667     { MOD_TABLE (MOD_0FAE_REG_2) },
3668     { MOD_TABLE (MOD_0FAE_REG_3) },
3669     { MOD_TABLE (MOD_0FAE_REG_4) },
3670     { MOD_TABLE (MOD_0FAE_REG_5) },
3671     { MOD_TABLE (MOD_0FAE_REG_6) },
3672     { MOD_TABLE (MOD_0FAE_REG_7) },
3673   },
3674   /* REG_0FBA */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { "btQ",    { Ev, Ib }, 0 },
3681     { "btsQ",   { Evh1, Ib }, 0 },
3682     { "btrQ",   { Evh1, Ib }, 0 },
3683     { "btcQ",   { Evh1, Ib }, 0 },
3684   },
3685   /* REG_0FC7 */
3686   {
3687     { Bad_Opcode },
3688     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3689     { Bad_Opcode },
3690     { MOD_TABLE (MOD_0FC7_REG_3) },
3691     { MOD_TABLE (MOD_0FC7_REG_4) },
3692     { MOD_TABLE (MOD_0FC7_REG_5) },
3693     { MOD_TABLE (MOD_0FC7_REG_6) },
3694     { MOD_TABLE (MOD_0FC7_REG_7) },
3695   },
3696   /* REG_VEX_0F71 */
3697   {
3698     { Bad_Opcode },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3701     { Bad_Opcode },
3702     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3703     { Bad_Opcode },
3704     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3705   },
3706   /* REG_VEX_0F72 */
3707   {
3708     { Bad_Opcode },
3709     { Bad_Opcode },
3710     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3711     { Bad_Opcode },
3712     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3713     { Bad_Opcode },
3714     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3715   },
3716   /* REG_VEX_0F73 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3721     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3722     { Bad_Opcode },
3723     { Bad_Opcode },
3724     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3725     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3726   },
3727   /* REG_VEX_0FAE */
3728   {
3729     { Bad_Opcode },
3730     { Bad_Opcode },
3731     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3732     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3733   },
3734   /* REG_VEX_0F38F3 */
3735   {
3736     { Bad_Opcode },
3737     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3738     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3739     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3740   },
3741   /* REG_XOP_LWPCB */
3742   {
3743     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3744     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3745   },
3746   /* REG_XOP_LWP */
3747   {
3748     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3749     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3750   },
3751   /* REG_XOP_TBM_01 */
3752   {
3753     { Bad_Opcode },
3754     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3755     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3756     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3757     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3758     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3759     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3760     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3761   },
3762   /* REG_XOP_TBM_02 */
3763   {
3764     { Bad_Opcode },
3765     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3766     { Bad_Opcode },
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { Bad_Opcode },
3770     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3771   },
3772 #define NEED_REG_TABLE
3773 #include "i386-dis-evex.h"
3774 #undef NEED_REG_TABLE
3775 };
3776
3777 static const struct dis386 prefix_table[][4] = {
3778   /* PREFIX_90 */
3779   {
3780     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3781     { "pause", { XX }, 0 },
3782     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3783     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3784   },
3785
3786   /* PREFIX_MOD_0_0F01_REG_5 */
3787   {
3788     { Bad_Opcode },
3789     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_MOD_3_0F01_REG_5_RM_1 */
3793   {
3794     { Bad_Opcode },
3795     { "incsspK",        { Skip_MODRM }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3799   {
3800     { Bad_Opcode },
3801     { "savessp",        { Skip_MODRM }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F10 */
3805   {
3806     { "movups", { XM, EXx }, PREFIX_OPCODE },
3807     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3809     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F11 */
3813   {
3814     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3815     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3816     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3817     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F12 */
3821   {
3822     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3823     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3824     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3825     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F16 */
3829   {
3830     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3831     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3832     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F1A */
3836   {
3837     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3838     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3839     { "bndmov", { Gbnd, Ebnd }, 0 },
3840     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3841   },
3842
3843   /* PREFIX_0F1B */
3844   {
3845     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3846     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3847     { "bndmov", { Ebnd, Gbnd }, 0 },
3848     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3849   },
3850
3851   /* PREFIX_0F1E */
3852   {
3853     { "nopQ",   { Ev }, PREFIX_OPCODE },
3854     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3855     { "nopQ",   { Ev }, PREFIX_OPCODE },
3856     { "nopQ",   { Ev }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F2A */
3860   {
3861     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3862     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3863     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3864     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3865   },
3866
3867   /* PREFIX_0F2B */
3868   {
3869     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3870     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3871     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3872     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3873   },
3874
3875   /* PREFIX_0F2C */
3876   {
3877     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3878     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3879     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3880     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F2D */
3884   {
3885     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3886     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3887     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3888     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F2E */
3892   {
3893     { "ucomiss",{ XM, EXd }, 0 },
3894     { Bad_Opcode },
3895     { "ucomisd",{ XM, EXq }, 0 },
3896   },
3897
3898   /* PREFIX_0F2F */
3899   {
3900     { "comiss", { XM, EXd }, 0 },
3901     { Bad_Opcode },
3902     { "comisd", { XM, EXq }, 0 },
3903   },
3904
3905   /* PREFIX_0F51 */
3906   {
3907     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3908     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3909     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3910     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0F52 */
3914   {
3915     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3916     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F53 */
3920   {
3921     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3922     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3923   },
3924
3925   /* PREFIX_0F58 */
3926   {
3927     { "addps", { XM, EXx }, PREFIX_OPCODE },
3928     { "addss", { XM, EXd }, PREFIX_OPCODE },
3929     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3930     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3931   },
3932
3933   /* PREFIX_0F59 */
3934   {
3935     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3936     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3937     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3938     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3939   },
3940
3941   /* PREFIX_0F5A */
3942   {
3943     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3944     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3945     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3946     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F5B */
3950   {
3951     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3952     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3953     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0F5C */
3957   {
3958     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3959     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3960     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3961     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F5D */
3965   {
3966     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3967     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3968     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3969     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F5E */
3973   {
3974     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3975     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3976     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3977     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F5F */
3981   {
3982     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3983     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3984     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3985     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_0F60 */
3989   {
3990     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3991     { Bad_Opcode },
3992     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0F61 */
3996   {
3997     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3998     { Bad_Opcode },
3999     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F62 */
4003   {
4004     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4005     { Bad_Opcode },
4006     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_0F6C */
4010   {
4011     { Bad_Opcode },
4012     { Bad_Opcode },
4013     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0F6D */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4021   },
4022
4023   /* PREFIX_0F6F */
4024   {
4025     { "movq",   { MX, EM }, PREFIX_OPCODE },
4026     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4027     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0F70 */
4031   {
4032     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4033     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4034     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4035     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F73_REG_3 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "psrldq", { XS, Ib }, 0 },
4043   },
4044
4045   /* PREFIX_0F73_REG_7 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pslldq", { XS, Ib }, 0 },
4050   },
4051
4052   /* PREFIX_0F78 */
4053   {
4054     {"vmread",  { Em, Gm }, 0 },
4055     { Bad_Opcode },
4056     {"extrq",   { XS, Ib, Ib }, 0 },
4057     {"insertq", { XM, XS, Ib, Ib }, 0 },
4058   },
4059
4060   /* PREFIX_0F79 */
4061   {
4062     {"vmwrite", { Gm, Em }, 0 },
4063     { Bad_Opcode },
4064     {"extrq",   { XM, XS }, 0 },
4065     {"insertq", { XM, XS }, 0 },
4066   },
4067
4068   /* PREFIX_0F7C */
4069   {
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4073     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0F7D */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4081     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F7E */
4085   {
4086     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4087     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4088     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F7F */
4092   {
4093     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4094     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4095     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0FAE_REG_0 */
4099   {
4100     { Bad_Opcode },
4101     { "rdfsbase", { Ev }, 0 },
4102   },
4103
4104   /* PREFIX_0FAE_REG_1 */
4105   {
4106     { Bad_Opcode },
4107     { "rdgsbase", { Ev }, 0 },
4108   },
4109
4110   /* PREFIX_0FAE_REG_2 */
4111   {
4112     { Bad_Opcode },
4113     { "wrfsbase", { Ev }, 0 },
4114   },
4115
4116   /* PREFIX_0FAE_REG_3 */
4117   {
4118     { Bad_Opcode },
4119     { "wrgsbase", { Ev }, 0 },
4120   },
4121
4122   /* PREFIX_MOD_0_0FAE_REG_4 */
4123   {
4124     { "xsave",  { FXSAVE }, 0 },
4125     { "ptwrite%LQ", { Edq }, 0 },
4126   },
4127
4128   /* PREFIX_MOD_3_0FAE_REG_4 */
4129   {
4130     { Bad_Opcode },
4131     { "ptwrite%LQ", { Edq }, 0 },
4132   },
4133
4134   /* PREFIX_MOD_0_0FAE_REG_5 */
4135   {
4136     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4137     { "setssbsy",       { Mq }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0FAE_REG_6 */
4141   {
4142     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4143     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4144     { "clwb",   { Mb }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0FAE_REG_7 */
4148   {
4149     { "clflush",        { Mb }, 0 },
4150     { Bad_Opcode },
4151     { "clflushopt",     { Mb }, 0 },
4152   },
4153
4154   /* PREFIX_0FB8 */
4155   {
4156     { Bad_Opcode },
4157     { "popcntS", { Gv, Ev }, 0 },
4158   },
4159
4160   /* PREFIX_0FBC */
4161   {
4162     { "bsfS",   { Gv, Ev }, 0 },
4163     { "tzcntS", { Gv, Ev }, 0 },
4164     { "bsfS",   { Gv, Ev }, 0 },
4165   },
4166
4167   /* PREFIX_0FBD */
4168   {
4169     { "bsrS",   { Gv, Ev }, 0 },
4170     { "lzcntS", { Gv, Ev }, 0 },
4171     { "bsrS",   { Gv, Ev }, 0 },
4172   },
4173
4174   /* PREFIX_0FC2 */
4175   {
4176     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4177     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4178     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4179     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_MOD_0_0FC3 */
4183   {
4184     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_MOD_0_0FC7_REG_6 */
4188   {
4189     { "vmptrld",{ Mq }, 0 },
4190     { "vmxon",  { Mq }, 0 },
4191     { "vmclear",{ Mq }, 0 },
4192   },
4193
4194   /* PREFIX_MOD_3_0FC7_REG_6 */
4195   {
4196     { "rdrand", { Ev }, 0 },
4197     { Bad_Opcode },
4198     { "rdrand", { Ev }, 0 }
4199   },
4200
4201   /* PREFIX_MOD_3_0FC7_REG_7 */
4202   {
4203     { "rdseed", { Ev }, 0 },
4204     { "rdpid",  { Em }, 0 },
4205     { "rdseed", { Ev }, 0 },
4206   },
4207
4208   /* PREFIX_0FD0 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "addsubpd", { XM, EXx }, 0 },
4213     { "addsubps", { XM, EXx }, 0 },
4214   },
4215
4216   /* PREFIX_0FD6 */
4217   {
4218     { Bad_Opcode },
4219     { "movq2dq",{ XM, MS }, 0 },
4220     { "movq",   { EXqS, XM }, 0 },
4221     { "movdq2q",{ MX, XS }, 0 },
4222   },
4223
4224   /* PREFIX_0FE6 */
4225   {
4226     { Bad_Opcode },
4227     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4228     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4229     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0FE7 */
4233   {
4234     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4235     { Bad_Opcode },
4236     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4237   },
4238
4239   /* PREFIX_0FF0 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4245   },
4246
4247   /* PREFIX_0FF7 */
4248   {
4249     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4250     { Bad_Opcode },
4251     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3810 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3814 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3815 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F3817 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F3820 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F3821 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F3822 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3823 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3824 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3825 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3828 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3829 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F382A */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4343   },
4344
4345   /* PREFIX_0F382B */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F3830 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F3831 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3832 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F3833 */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F3834 */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F3835 */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F3837 */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F3838 */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F3839 */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F383A */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F383B */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F383C */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F383D */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F383E */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F383F */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F3840 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4462   },
4463
4464   /* PREFIX_0F3841 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F3880 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4476   },
4477
4478   /* PREFIX_0F3881 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4483   },
4484
4485   /* PREFIX_0F3882 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F38C8 */
4493   {
4494     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F38C9 */
4498   {
4499     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F38CA */
4503   {
4504     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38CB */
4508   {
4509     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F38CC */
4513   {
4514     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F38CD */
4518   {
4519     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F38DB */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F38DC */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F38DD */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F38DE */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F38DF */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F38F0 */
4558   {
4559     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4560     { Bad_Opcode },
4561     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4562     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F38F1 */
4566   {
4567     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4568     { Bad_Opcode },
4569     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4570     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F38F5 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4578   },
4579
4580   /* PREFIX_0F38F6 */
4581   {
4582     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4583     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4584     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4585     { Bad_Opcode },
4586   },
4587
4588   /* PREFIX_0F3A08 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A09 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A0A */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A0B */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A0C */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3A0D */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4628   },
4629
4630   /* PREFIX_0F3A0E */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4635   },
4636
4637   /* PREFIX_0F3A14 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3A15 */
4645   {
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4649   },
4650
4651   /* PREFIX_0F3A16 */
4652   {
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4656   },
4657
4658   /* PREFIX_0F3A17 */
4659   {
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4663   },
4664
4665   /* PREFIX_0F3A20 */
4666   {
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4670   },
4671
4672   /* PREFIX_0F3A21 */
4673   {
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4677   },
4678
4679   /* PREFIX_0F3A22 */
4680   {
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4684   },
4685
4686   /* PREFIX_0F3A40 */
4687   {
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4691   },
4692
4693   /* PREFIX_0F3A41 */
4694   {
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4698   },
4699
4700   /* PREFIX_0F3A42 */
4701   {
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4705   },
4706
4707   /* PREFIX_0F3A44 */
4708   {
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4712   },
4713
4714   /* PREFIX_0F3A60 */
4715   {
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4719   },
4720
4721   /* PREFIX_0F3A61 */
4722   {
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4726   },
4727
4728   /* PREFIX_0F3A62 */
4729   {
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4733   },
4734
4735   /* PREFIX_0F3A63 */
4736   {
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4740   },
4741
4742   /* PREFIX_0F3ACC */
4743   {
4744     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4745   },
4746
4747   /* PREFIX_0F3ADF */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4752   },
4753
4754   /* PREFIX_VEX_0F10 */
4755   {
4756     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4757     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4758     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4759     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4760   },
4761
4762   /* PREFIX_VEX_0F11 */
4763   {
4764     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4765     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4766     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4767     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4768   },
4769
4770   /* PREFIX_VEX_0F12 */
4771   {
4772     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4773     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4774     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4775     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4776   },
4777
4778   /* PREFIX_VEX_0F16 */
4779   {
4780     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4781     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4782     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F2A */
4786   {
4787     { Bad_Opcode },
4788     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4789     { Bad_Opcode },
4790     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4791   },
4792
4793   /* PREFIX_VEX_0F2C */
4794   {
4795     { Bad_Opcode },
4796     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4799   },
4800
4801   /* PREFIX_VEX_0F2D */
4802   {
4803     { Bad_Opcode },
4804     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4805     { Bad_Opcode },
4806     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4807   },
4808
4809   /* PREFIX_VEX_0F2E */
4810   {
4811     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4812     { Bad_Opcode },
4813     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4814   },
4815
4816   /* PREFIX_VEX_0F2F */
4817   {
4818     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4819     { Bad_Opcode },
4820     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4821   },
4822
4823   /* PREFIX_VEX_0F41 */
4824   {
4825     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4826     { Bad_Opcode },
4827     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4828   },
4829
4830   /* PREFIX_VEX_0F42 */
4831   {
4832     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4833     { Bad_Opcode },
4834     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4835   },
4836
4837   /* PREFIX_VEX_0F44 */
4838   {
4839     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4840     { Bad_Opcode },
4841     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4842   },
4843
4844   /* PREFIX_VEX_0F45 */
4845   {
4846     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4847     { Bad_Opcode },
4848     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4849   },
4850
4851   /* PREFIX_VEX_0F46 */
4852   {
4853     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4854     { Bad_Opcode },
4855     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4856   },
4857
4858   /* PREFIX_VEX_0F47 */
4859   {
4860     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4861     { Bad_Opcode },
4862     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F4A */
4866   {
4867     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4868     { Bad_Opcode },
4869     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4870   },
4871
4872   /* PREFIX_VEX_0F4B */
4873   {
4874     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4875     { Bad_Opcode },
4876     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4877   },
4878
4879   /* PREFIX_VEX_0F51 */
4880   {
4881     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4882     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4883     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4884     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4885   },
4886
4887   /* PREFIX_VEX_0F52 */
4888   {
4889     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4890     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4891   },
4892
4893   /* PREFIX_VEX_0F53 */
4894   {
4895     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4896     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4897   },
4898
4899   /* PREFIX_VEX_0F58 */
4900   {
4901     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4902     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4903     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4904     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4905   },
4906
4907   /* PREFIX_VEX_0F59 */
4908   {
4909     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4910     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4911     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4912     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4913   },
4914
4915   /* PREFIX_VEX_0F5A */
4916   {
4917     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4918     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4919     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4920     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4921   },
4922
4923   /* PREFIX_VEX_0F5B */
4924   {
4925     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4926     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4927     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F5C */
4931   {
4932     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4933     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4934     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4935     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4936   },
4937
4938   /* PREFIX_VEX_0F5D */
4939   {
4940     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4941     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4942     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4943     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4944   },
4945
4946   /* PREFIX_VEX_0F5E */
4947   {
4948     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4949     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4950     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4951     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4952   },
4953
4954   /* PREFIX_VEX_0F5F */
4955   {
4956     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4957     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4958     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4959     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4960   },
4961
4962   /* PREFIX_VEX_0F60 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F61 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F62 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F63 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F64 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F65 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_0F66 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F67 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0F68 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F69 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F6A */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F6B */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0F6C */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F6D */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F6E */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F6F */
5068   {
5069     { Bad_Opcode },
5070     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5071     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F70 */
5075   {
5076     { Bad_Opcode },
5077     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5078     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5079     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5080   },
5081
5082   /* PREFIX_VEX_0F71_REG_2 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_0F71_REG_4 */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F71_REG_6 */
5097   {
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0F72_REG_2 */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_0F72_REG_4 */
5111   {
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0F72_REG_6 */
5118   {
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0F73_REG_2 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0F73_REG_3 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F73_REG_6 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0F73_REG_7 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0F74 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0F75 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0F76 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0F77 */
5174   {
5175     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5176   },
5177
5178   /* PREFIX_VEX_0F7C */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5183     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5184   },
5185
5186   /* PREFIX_VEX_0F7D */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5191     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5192   },
5193
5194   /* PREFIX_VEX_0F7E */
5195   {
5196     { Bad_Opcode },
5197     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5198     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0F7F */
5202   {
5203     { Bad_Opcode },
5204     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5205     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0F90 */
5209   {
5210     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5211     { Bad_Opcode },
5212     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0F91 */
5216   {
5217     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0F92 */
5223   {
5224     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5227     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5228   },
5229
5230   /* PREFIX_VEX_0F93 */
5231   {
5232     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5233     { Bad_Opcode },
5234     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5235     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5236   },
5237
5238   /* PREFIX_VEX_0F98 */
5239   {
5240     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5241     { Bad_Opcode },
5242     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0F99 */
5246   {
5247     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5248     { Bad_Opcode },
5249     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0FC2 */
5253   {
5254     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5255     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5256     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5257     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5258   },
5259
5260   /* PREFIX_VEX_0FC4 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FC5 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FD0 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5279     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5280   },
5281
5282   /* PREFIX_VEX_0FD1 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0FD2 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0FD3 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0FD4 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FD5 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FD6 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FD7 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5329   },
5330
5331   /* PREFIX_VEX_0FD8 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FD9 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0FDA */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0FDB */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0FDC */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5364   },
5365
5366   /* PREFIX_VEX_0FDD */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0FDE */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0FDF */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FE0 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0FE1 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FE2 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FE3 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FE4 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FE5 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0FE6 */
5430   {
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5433     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5434     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5435   },
5436
5437   /* PREFIX_VEX_0FE7 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5442   },
5443
5444   /* PREFIX_VEX_0FE8 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FE9 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0FEA */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0FEB */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FEC */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0FED */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0FEE */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FEF */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0FF0 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5506   },
5507
5508   /* PREFIX_VEX_0FF1 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0FF2 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0FF3 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0FF4 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5534   },
5535
5536   /* PREFIX_VEX_0FF5 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5541   },
5542
5543   /* PREFIX_VEX_0FF6 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5548   },
5549
5550   /* PREFIX_VEX_0FF7 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5555   },
5556
5557   /* PREFIX_VEX_0FF8 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0FF9 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0FFA */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0FFB */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0FFC */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0FFD */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0FFE */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F3800 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3801 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F3802 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3803 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3804 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3805 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3806 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F3807 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5660   },
5661
5662   /* PREFIX_VEX_0F3808 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F3809 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F380A */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5681   },
5682
5683   /* PREFIX_VEX_0F380B */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5688   },
5689
5690   /* PREFIX_VEX_0F380C */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5695   },
5696
5697   /* PREFIX_VEX_0F380D */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5702   },
5703
5704   /* PREFIX_VEX_0F380E */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5709   },
5710
5711   /* PREFIX_VEX_0F380F */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5716   },
5717
5718   /* PREFIX_VEX_0F3813 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F3816 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F3817 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F3818 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F3819 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F381A */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F381C */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F381D */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F381E */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F3820 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F3821 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3822 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F3823 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3824 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F3825 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3828 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5828   },
5829
5830   /* PREFIX_VEX_0F3829 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5835   },
5836
5837   /* PREFIX_VEX_0F382A */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F382B */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5849   },
5850
5851   /* PREFIX_VEX_0F382C */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5856   },
5857
5858   /* PREFIX_VEX_0F382D */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5863   },
5864
5865   /* PREFIX_VEX_0F382E */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5870   },
5871
5872   /* PREFIX_VEX_0F382F */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F3830 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F3831 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F3832 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F3833 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5905   },
5906
5907   /* PREFIX_VEX_0F3834 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F3835 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F3836 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3837 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3838 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F3839 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F383A */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F383B */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F383C */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F383D */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F383E */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F383F */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3840 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5996   },
5997
5998   /* PREFIX_VEX_0F3841 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6003   },
6004
6005   /* PREFIX_VEX_0F3845 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3846 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6017   },
6018
6019   /* PREFIX_VEX_0F3847 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3858 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6031   },
6032
6033   /* PREFIX_VEX_0F3859 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6038   },
6039
6040   /* PREFIX_VEX_0F385A */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6045   },
6046
6047   /* PREFIX_VEX_0F3878 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6052   },
6053
6054   /* PREFIX_VEX_0F3879 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6059   },
6060
6061   /* PREFIX_VEX_0F388C */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6066   },
6067
6068   /* PREFIX_VEX_0F388E */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6073   },
6074
6075   /* PREFIX_VEX_0F3890 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F3891 */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F3892 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F3893 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F3896 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F3897 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F3898 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F3899 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F389A */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F389B */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F389C */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F389D */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F389E */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F389F */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38A6 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6178     { Bad_Opcode },
6179   },
6180
6181   /* PREFIX_VEX_0F38A7 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38A8 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38A9 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38AA */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38AB */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38AC */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38AD */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38AE */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38AF */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F38B6 */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38B7 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38B8 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F38B9 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F38BA */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6277   },
6278
6279   /* PREFIX_VEX_0F38BB */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6284   },
6285
6286   /* PREFIX_VEX_0F38BC */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6291   },
6292
6293   /* PREFIX_VEX_0F38BD */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6298   },
6299
6300   /* PREFIX_VEX_0F38BE */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6305   },
6306
6307   /* PREFIX_VEX_0F38BF */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6312   },
6313
6314   /* PREFIX_VEX_0F38DB */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F38DC */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F38DD */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F38DE */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F38DF */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F38F2 */
6350   {
6351     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6352   },
6353
6354   /* PREFIX_VEX_0F38F3_REG_1 */
6355   {
6356     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6357   },
6358
6359   /* PREFIX_VEX_0F38F3_REG_2 */
6360   {
6361     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6362   },
6363
6364   /* PREFIX_VEX_0F38F3_REG_3 */
6365   {
6366     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6367   },
6368
6369   /* PREFIX_VEX_0F38F5 */
6370   {
6371     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6372     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6373     { Bad_Opcode },
6374     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6375   },
6376
6377   /* PREFIX_VEX_0F38F6 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6383   },
6384
6385   /* PREFIX_VEX_0F38F7 */
6386   {
6387     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6388     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6389     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6390     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A00 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A01 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A02 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A04 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A05 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A06 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A08 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A09 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A0A */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A0B */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A0C */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A0D */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A0E */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A0F */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A14 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A15 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A16 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A17 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A18 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A19 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A1D */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6538   },
6539
6540   /* PREFIX_VEX_0F3A20 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A21 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A22 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A30 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A31 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A32 */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A33 */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A38 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A39 */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A40 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A41 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3A42 */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3A44 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3A46 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A48 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A49 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A4A */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A4B */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A4C */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A5C */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A5D */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A5E */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A5F */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6699   },
6700
6701   /* PREFIX_VEX_0F3A60 */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6706     { Bad_Opcode },
6707   },
6708
6709   /* PREFIX_VEX_0F3A61 */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6714   },
6715
6716   /* PREFIX_VEX_0F3A62 */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6721   },
6722
6723   /* PREFIX_VEX_0F3A63 */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3A68 */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6735   },
6736
6737   /* PREFIX_VEX_0F3A69 */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6742   },
6743
6744   /* PREFIX_VEX_0F3A6A */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6749   },
6750
6751   /* PREFIX_VEX_0F3A6B */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6756   },
6757
6758   /* PREFIX_VEX_0F3A6C */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6763   },
6764
6765   /* PREFIX_VEX_0F3A6D */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6770   },
6771
6772   /* PREFIX_VEX_0F3A6E */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3A6F */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3A78 */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6791   },
6792
6793   /* PREFIX_VEX_0F3A79 */
6794   {
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6798   },
6799
6800   /* PREFIX_VEX_0F3A7A */
6801   {
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6805   },
6806
6807   /* PREFIX_VEX_0F3A7B */
6808   {
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6812   },
6813
6814   /* PREFIX_VEX_0F3A7C */
6815   {
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6819     { Bad_Opcode },
6820   },
6821
6822   /* PREFIX_VEX_0F3A7D */
6823   {
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6827   },
6828
6829   /* PREFIX_VEX_0F3A7E */
6830   {
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6834   },
6835
6836   /* PREFIX_VEX_0F3A7F */
6837   {
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6841   },
6842
6843   /* PREFIX_VEX_0F3ADF */
6844   {
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6848   },
6849
6850   /* PREFIX_VEX_0F3AF0 */
6851   {
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6856   },
6857
6858 #define NEED_PREFIX_TABLE
6859 #include "i386-dis-evex.h"
6860 #undef NEED_PREFIX_TABLE
6861 };
6862
6863 static const struct dis386 x86_64_table[][2] = {
6864   /* X86_64_06 */
6865   {
6866     { "pushP", { es }, 0 },
6867   },
6868
6869   /* X86_64_07 */
6870   {
6871     { "popP", { es }, 0 },
6872   },
6873
6874   /* X86_64_0D */
6875   {
6876     { "pushP", { cs }, 0 },
6877   },
6878
6879   /* X86_64_16 */
6880   {
6881     { "pushP", { ss }, 0 },
6882   },
6883
6884   /* X86_64_17 */
6885   {
6886     { "popP", { ss }, 0 },
6887   },
6888
6889   /* X86_64_1E */
6890   {
6891     { "pushP", { ds }, 0 },
6892   },
6893
6894   /* X86_64_1F */
6895   {
6896     { "popP", { ds }, 0 },
6897   },
6898
6899   /* X86_64_27 */
6900   {
6901     { "daa", { XX }, 0 },
6902   },
6903
6904   /* X86_64_2F */
6905   {
6906     { "das", { XX }, 0 },
6907   },
6908
6909   /* X86_64_37 */
6910   {
6911     { "aaa", { XX }, 0 },
6912   },
6913
6914   /* X86_64_3F */
6915   {
6916     { "aas", { XX }, 0 },
6917   },
6918
6919   /* X86_64_60 */
6920   {
6921     { "pushaP", { XX }, 0 },
6922   },
6923
6924   /* X86_64_61 */
6925   {
6926     { "popaP", { XX }, 0 },
6927   },
6928
6929   /* X86_64_62 */
6930   {
6931     { MOD_TABLE (MOD_62_32BIT) },
6932     { EVEX_TABLE (EVEX_0F) },
6933   },
6934
6935   /* X86_64_63 */
6936   {
6937     { "arpl", { Ew, Gw }, 0 },
6938     { "movs{lq|xd}", { Gv, Ed }, 0 },
6939   },
6940
6941   /* X86_64_6D */
6942   {
6943     { "ins{R|}", { Yzr, indirDX }, 0 },
6944     { "ins{G|}", { Yzr, indirDX }, 0 },
6945   },
6946
6947   /* X86_64_6F */
6948   {
6949     { "outs{R|}", { indirDXr, Xz }, 0 },
6950     { "outs{G|}", { indirDXr, Xz }, 0 },
6951   },
6952
6953   /* X86_64_82 */
6954   {
6955     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6956     { REG_TABLE (REG_80) },
6957   },
6958
6959   /* X86_64_9A */
6960   {
6961     { "Jcall{T|}", { Ap }, 0 },
6962   },
6963
6964   /* X86_64_C4 */
6965   {
6966     { MOD_TABLE (MOD_C4_32BIT) },
6967     { VEX_C4_TABLE (VEX_0F) },
6968   },
6969
6970   /* X86_64_C5 */
6971   {
6972     { MOD_TABLE (MOD_C5_32BIT) },
6973     { VEX_C5_TABLE (VEX_0F) },
6974   },
6975
6976   /* X86_64_CE */
6977   {
6978     { "into", { XX }, 0 },
6979   },
6980
6981   /* X86_64_D4 */
6982   {
6983     { "aam", { Ib }, 0 },
6984   },
6985
6986   /* X86_64_D5 */
6987   {
6988     { "aad", { Ib }, 0 },
6989   },
6990
6991   /* X86_64_E8 */
6992   {
6993     { "callP",          { Jv, BND }, 0 },
6994     { "call@",          { Jv, BND }, 0 }
6995   },
6996
6997   /* X86_64_E9 */
6998   {
6999     { "jmpP",           { Jv, BND }, 0 },
7000     { "jmp@",           { Jv, BND }, 0 }
7001   },
7002
7003   /* X86_64_EA */
7004   {
7005     { "Jjmp{T|}", { Ap }, 0 },
7006   },
7007
7008   /* X86_64_0F01_REG_0 */
7009   {
7010     { "sgdt{Q|IQ}", { M }, 0 },
7011     { "sgdt", { M }, 0 },
7012   },
7013
7014   /* X86_64_0F01_REG_1 */
7015   {
7016     { "sidt{Q|IQ}", { M }, 0 },
7017     { "sidt", { M }, 0 },
7018   },
7019
7020   /* X86_64_0F01_REG_2 */
7021   {
7022     { "lgdt{Q|Q}", { M }, 0 },
7023     { "lgdt", { M }, 0 },
7024   },
7025
7026   /* X86_64_0F01_REG_3 */
7027   {
7028     { "lidt{Q|Q}", { M }, 0 },
7029     { "lidt", { M }, 0 },
7030   },
7031 };
7032
7033 static const struct dis386 three_byte_table[][256] = {
7034
7035   /* THREE_BYTE_0F38 */
7036   {
7037     /* 00 */
7038     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7039     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7040     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7041     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7042     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7043     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7044     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7045     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7046     /* 08 */
7047     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7048     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7049     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7050     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 10 */
7056     { PREFIX_TABLE (PREFIX_0F3810) },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { PREFIX_TABLE (PREFIX_0F3814) },
7061     { PREFIX_TABLE (PREFIX_0F3815) },
7062     { Bad_Opcode },
7063     { PREFIX_TABLE (PREFIX_0F3817) },
7064     /* 18 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7070     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7071     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7072     { Bad_Opcode },
7073     /* 20 */
7074     { PREFIX_TABLE (PREFIX_0F3820) },
7075     { PREFIX_TABLE (PREFIX_0F3821) },
7076     { PREFIX_TABLE (PREFIX_0F3822) },
7077     { PREFIX_TABLE (PREFIX_0F3823) },
7078     { PREFIX_TABLE (PREFIX_0F3824) },
7079     { PREFIX_TABLE (PREFIX_0F3825) },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 28 */
7083     { PREFIX_TABLE (PREFIX_0F3828) },
7084     { PREFIX_TABLE (PREFIX_0F3829) },
7085     { PREFIX_TABLE (PREFIX_0F382A) },
7086     { PREFIX_TABLE (PREFIX_0F382B) },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* 30 */
7092     { PREFIX_TABLE (PREFIX_0F3830) },
7093     { PREFIX_TABLE (PREFIX_0F3831) },
7094     { PREFIX_TABLE (PREFIX_0F3832) },
7095     { PREFIX_TABLE (PREFIX_0F3833) },
7096     { PREFIX_TABLE (PREFIX_0F3834) },
7097     { PREFIX_TABLE (PREFIX_0F3835) },
7098     { Bad_Opcode },
7099     { PREFIX_TABLE (PREFIX_0F3837) },
7100     /* 38 */
7101     { PREFIX_TABLE (PREFIX_0F3838) },
7102     { PREFIX_TABLE (PREFIX_0F3839) },
7103     { PREFIX_TABLE (PREFIX_0F383A) },
7104     { PREFIX_TABLE (PREFIX_0F383B) },
7105     { PREFIX_TABLE (PREFIX_0F383C) },
7106     { PREFIX_TABLE (PREFIX_0F383D) },
7107     { PREFIX_TABLE (PREFIX_0F383E) },
7108     { PREFIX_TABLE (PREFIX_0F383F) },
7109     /* 40 */
7110     { PREFIX_TABLE (PREFIX_0F3840) },
7111     { PREFIX_TABLE (PREFIX_0F3841) },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* 48 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* 50 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 58 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* 60 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* 68 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* 70 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* 78 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* 80 */
7182     { PREFIX_TABLE (PREFIX_0F3880) },
7183     { PREFIX_TABLE (PREFIX_0F3881) },
7184     { PREFIX_TABLE (PREFIX_0F3882) },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 88 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* 90 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* 98 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* a0 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* a8 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* b0 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* b8 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* c0 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* c8 */
7263     { PREFIX_TABLE (PREFIX_0F38C8) },
7264     { PREFIX_TABLE (PREFIX_0F38C9) },
7265     { PREFIX_TABLE (PREFIX_0F38CA) },
7266     { PREFIX_TABLE (PREFIX_0F38CB) },
7267     { PREFIX_TABLE (PREFIX_0F38CC) },
7268     { PREFIX_TABLE (PREFIX_0F38CD) },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* d0 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* d8 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { PREFIX_TABLE (PREFIX_0F38DB) },
7285     { PREFIX_TABLE (PREFIX_0F38DC) },
7286     { PREFIX_TABLE (PREFIX_0F38DD) },
7287     { PREFIX_TABLE (PREFIX_0F38DE) },
7288     { PREFIX_TABLE (PREFIX_0F38DF) },
7289     /* e0 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* e8 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* f0 */
7308     { PREFIX_TABLE (PREFIX_0F38F0) },
7309     { PREFIX_TABLE (PREFIX_0F38F1) },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { PREFIX_TABLE (PREFIX_0F38F5) },
7314     { PREFIX_TABLE (PREFIX_0F38F6) },
7315     { Bad_Opcode },
7316     /* f8 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325   },
7326   /* THREE_BYTE_0F3A */
7327   {
7328     /* 00 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 08 */
7338     { PREFIX_TABLE (PREFIX_0F3A08) },
7339     { PREFIX_TABLE (PREFIX_0F3A09) },
7340     { PREFIX_TABLE (PREFIX_0F3A0A) },
7341     { PREFIX_TABLE (PREFIX_0F3A0B) },
7342     { PREFIX_TABLE (PREFIX_0F3A0C) },
7343     { PREFIX_TABLE (PREFIX_0F3A0D) },
7344     { PREFIX_TABLE (PREFIX_0F3A0E) },
7345     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7346     /* 10 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { PREFIX_TABLE (PREFIX_0F3A14) },
7352     { PREFIX_TABLE (PREFIX_0F3A15) },
7353     { PREFIX_TABLE (PREFIX_0F3A16) },
7354     { PREFIX_TABLE (PREFIX_0F3A17) },
7355     /* 18 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 20 */
7365     { PREFIX_TABLE (PREFIX_0F3A20) },
7366     { PREFIX_TABLE (PREFIX_0F3A21) },
7367     { PREFIX_TABLE (PREFIX_0F3A22) },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* 28 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 30 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 38 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 40 */
7401     { PREFIX_TABLE (PREFIX_0F3A40) },
7402     { PREFIX_TABLE (PREFIX_0F3A41) },
7403     { PREFIX_TABLE (PREFIX_0F3A42) },
7404     { Bad_Opcode },
7405     { PREFIX_TABLE (PREFIX_0F3A44) },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 48 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* 50 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* 58 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 60 */
7437     { PREFIX_TABLE (PREFIX_0F3A60) },
7438     { PREFIX_TABLE (PREFIX_0F3A61) },
7439     { PREFIX_TABLE (PREFIX_0F3A62) },
7440     { PREFIX_TABLE (PREFIX_0F3A63) },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* 68 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* 70 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* 78 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 80 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 88 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 90 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* 98 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* a0 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* a8 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* b0 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* b8 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* c0 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* c8 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { PREFIX_TABLE (PREFIX_0F3ACC) },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* d0 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* d8 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { PREFIX_TABLE (PREFIX_0F3ADF) },
7580     /* e0 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* e8 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* f0 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* f8 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616   },
7617 };
7618
7619 static const struct dis386 xop_table[][256] = {
7620   /* XOP_08 */
7621   {
7622     /* 00 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* 08 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* 10 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* 18 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* 20 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* 28 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* 30 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* 38 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* 40 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* 48 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* 50 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* 58 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     /* 60 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* 68 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* 70 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* 78 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     /* 80 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7773     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7774     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7775     /* 88 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7783     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7784     /* 90 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7791     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7792     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7793     /* 98 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7801     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7802     /* a0 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7806     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7810     { Bad_Opcode },
7811     /* a8 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* b0 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7828     { Bad_Opcode },
7829     /* b8 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* c0 */
7839     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7840     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7841     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7842     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* c8 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7853     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7854     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7855     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7856     /* d0 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* d8 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* e0 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* e8 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7889     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7890     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7891     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7892     /* f0 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* f8 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910   },
7911   /* XOP_09 */
7912   {
7913     /* 00 */
7914     { Bad_Opcode },
7915     { REG_TABLE (REG_XOP_TBM_01) },
7916     { REG_TABLE (REG_XOP_TBM_02) },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 08 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* 10 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { REG_TABLE (REG_XOP_LWPCB) },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 18 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* 20 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* 28 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* 30 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* 38 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* 40 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* 48 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* 50 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* 58 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* 60 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* 68 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* 70 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* 78 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* 80 */
8058     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8059     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8060     { "vfrczss",        { XM, EXd }, 0 },
8061     { "vfrczsd",        { XM, EXq }, 0 },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 88 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 90 */
8076     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8077     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8078     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8079     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8080     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8081     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8082     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084     /* 98 */
8085     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8087     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8088     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* a0 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* a8 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* b0 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* b8 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* c0 */
8130     { Bad_Opcode },
8131     { "vphaddbw",       { XM, EXxmm }, 0 },
8132     { "vphaddbd",       { XM, EXxmm }, 0 },
8133     { "vphaddbq",       { XM, EXxmm }, 0 },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { "vphaddwd",       { XM, EXxmm }, 0 },
8137     { "vphaddwq",       { XM, EXxmm }, 0 },
8138     /* c8 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { "vphadddq",       { XM, EXxmm }, 0 },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* d0 */
8148     { Bad_Opcode },
8149     { "vphaddubw",      { XM, EXxmm }, 0 },
8150     { "vphaddubd",      { XM, EXxmm }, 0 },
8151     { "vphaddubq",      { XM, EXxmm }, 0 },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { "vphadduwd",      { XM, EXxmm }, 0 },
8155     { "vphadduwq",      { XM, EXxmm }, 0 },
8156     /* d8 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { "vphaddudq",      { XM, EXxmm }, 0 },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* e0 */
8166     { Bad_Opcode },
8167     { "vphsubbw",       { XM, EXxmm }, 0 },
8168     { "vphsubwd",       { XM, EXxmm }, 0 },
8169     { "vphsubdq",       { XM, EXxmm }, 0 },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* e8 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* f0 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* f8 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201   },
8202   /* XOP_0A */
8203   {
8204     /* 00 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* 08 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 10 */
8223     { "bextr",  { Gv, Ev, Iq }, 0 },
8224     { Bad_Opcode },
8225     { REG_TABLE (REG_XOP_LWP) },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* 18 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* 20 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* 28 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* 30 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* 38 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* 40 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* 48 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* 50 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* 58 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* 60 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* 68 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* 70 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* 78 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* 80 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* 88 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 90 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 98 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* a0 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* a8 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* b0 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* b8 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* c0 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* c8 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* d0 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* d8 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* e0 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* e8 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* f0 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* f8 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492   },
8493 };
8494
8495 static const struct dis386 vex_table[][256] = {
8496   /* VEX_0F */
8497   {
8498     /* 00 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* 08 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* 10 */
8517     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8520     { MOD_TABLE (MOD_VEX_0F13) },
8521     { VEX_W_TABLE (VEX_W_0F14) },
8522     { VEX_W_TABLE (VEX_W_0F15) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8524     { MOD_TABLE (MOD_VEX_0F17) },
8525     /* 18 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* 20 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     /* 28 */
8544     { VEX_W_TABLE (VEX_W_0F28) },
8545     { VEX_W_TABLE (VEX_W_0F29) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8547     { MOD_TABLE (MOD_VEX_0F2B) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8552     /* 30 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* 38 */
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     /* 40 */
8571     { Bad_Opcode },
8572     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8574     { Bad_Opcode },
8575     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8579     /* 48 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     /* 50 */
8589     { MOD_TABLE (MOD_VEX_0F50) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8593     { "vandpX",         { XM, Vex, EXx }, 0 },
8594     { "vandnpX",        { XM, Vex, EXx }, 0 },
8595     { "vorpX",          { XM, Vex, EXx }, 0 },
8596     { "vxorpX",         { XM, Vex, EXx }, 0 },
8597     /* 58 */
8598     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8606     /* 60 */
8607     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8615     /* 68 */
8616     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8624     /* 70 */
8625     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8626     { REG_TABLE (REG_VEX_0F71) },
8627     { REG_TABLE (REG_VEX_0F72) },
8628     { REG_TABLE (REG_VEX_0F73) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8633     /* 78 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8642     /* 80 */
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     /* 88 */
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     /* 90 */
8661     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* 98 */
8670     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     /* a0 */
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     /* a8 */
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { REG_TABLE (REG_VEX_0FAE) },
8695     { Bad_Opcode },
8696     /* b0 */
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     /* b8 */
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     /* c0 */
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8718     { Bad_Opcode },
8719     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8721     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8722     { Bad_Opcode },
8723     /* c8 */
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     /* d0 */
8733     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8741     /* d8 */
8742     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8748     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8750     /* e0 */
8751     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8755     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8756     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8757     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8758     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8759     /* e8 */
8760     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8763     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8764     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8765     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8766     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8767     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8768     /* f0 */
8769     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8770     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8771     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8772     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8773     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8774     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8775     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8776     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8777     /* f8 */
8778     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8779     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8780     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8781     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8782     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8783     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8784     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8785     { Bad_Opcode },
8786   },
8787   /* VEX_0F38 */
8788   {
8789     /* 00 */
8790     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8798     /* 08 */
8799     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8807     /* 10 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8816     /* 18 */
8817     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8820     { Bad_Opcode },
8821     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8824     { Bad_Opcode },
8825     /* 20 */
8826     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* 28 */
8835     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8843     /* 30 */
8844     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8852     /* 38 */
8853     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8861     /* 40 */
8862     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8870     /* 48 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* 50 */
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     /* 58 */
8889     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     /* 60 */
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     /* 68 */
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     /* 70 */
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     /* 78 */
8925     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     /* 80 */
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     /* 88 */
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8948     { Bad_Opcode },
8949     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8950     { Bad_Opcode },
8951     /* 90 */
8952     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8960     /* 98 */
8961     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8969     /* a0 */
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8978     /* a8 */
8979     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8987     /* b0 */
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8996     /* b8 */
8997     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9005     /* c0 */
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     /* c8 */
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     /* d0 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* d8 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9041     /* e0 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* e8 */
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* f0 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9063     { REG_TABLE (REG_VEX_0F38F3) },
9064     { Bad_Opcode },
9065     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9068     /* f8 */
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077   },
9078   /* VEX_0F3A */
9079   {
9080     /* 00 */
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9084     { Bad_Opcode },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9088     { Bad_Opcode },
9089     /* 08 */
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9098     /* 10 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9107     /* 18 */
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* 20 */
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* 28 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* 30 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* 38 */
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* 40 */
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9156     { Bad_Opcode },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9158     { Bad_Opcode },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9160     { Bad_Opcode },
9161     /* 48 */
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* 50 */
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* 58 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9188     /* 60 */
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     /* 68 */
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9206     /* 70 */
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     /* 78 */
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9224     /* 80 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* 88 */
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* 90 */
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* 98 */
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     /* a0 */
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* a8 */
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* b0 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     /* b8 */
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* c0 */
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     /* c8 */
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     /* d0 */
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     /* d8 */
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9332     /* e0 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     /* e8 */
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     /* f0 */
9351     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     /* f8 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368   },
9369 };
9370
9371 #define NEED_OPCODE_TABLE
9372 #include "i386-dis-evex.h"
9373 #undef NEED_OPCODE_TABLE
9374 static const struct dis386 vex_len_table[][2] = {
9375   /* VEX_LEN_0F10_P_1 */
9376   {
9377     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9378     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9379   },
9380
9381   /* VEX_LEN_0F10_P_3 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9384     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9385   },
9386
9387   /* VEX_LEN_0F11_P_1 */
9388   {
9389     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9390     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9391   },
9392
9393   /* VEX_LEN_0F11_P_3 */
9394   {
9395     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9396     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9397   },
9398
9399   /* VEX_LEN_0F12_P_0_M_0 */
9400   {
9401     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9402   },
9403
9404   /* VEX_LEN_0F12_P_0_M_1 */
9405   {
9406     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9407   },
9408
9409   /* VEX_LEN_0F12_P_2 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9412   },
9413
9414   /* VEX_LEN_0F13_M_0 */
9415   {
9416     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9417   },
9418
9419   /* VEX_LEN_0F16_P_0_M_0 */
9420   {
9421     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9422   },
9423
9424   /* VEX_LEN_0F16_P_0_M_1 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9427   },
9428
9429   /* VEX_LEN_0F16_P_2 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9432   },
9433
9434   /* VEX_LEN_0F17_M_0 */
9435   {
9436     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9437   },
9438
9439   /* VEX_LEN_0F2A_P_1 */
9440   {
9441     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9442     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F2A_P_3 */
9446   {
9447     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9448     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F2C_P_1 */
9452   {
9453     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9454     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9455   },
9456
9457   /* VEX_LEN_0F2C_P_3 */
9458   {
9459     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9460     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9461   },
9462
9463   /* VEX_LEN_0F2D_P_1 */
9464   {
9465     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9466     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9467   },
9468
9469   /* VEX_LEN_0F2D_P_3 */
9470   {
9471     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9472     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F2E_P_0 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9478     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9479   },
9480
9481   /* VEX_LEN_0F2E_P_2 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9484     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9485   },
9486
9487   /* VEX_LEN_0F2F_P_0 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9490     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9491   },
9492
9493   /* VEX_LEN_0F2F_P_2 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9496     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9497   },
9498
9499   /* VEX_LEN_0F41_P_0 */
9500   {
9501     { Bad_Opcode },
9502     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9503   },
9504   /* VEX_LEN_0F41_P_2 */
9505   {
9506     { Bad_Opcode },
9507     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9508   },
9509   /* VEX_LEN_0F42_P_0 */
9510   {
9511     { Bad_Opcode },
9512     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9513   },
9514   /* VEX_LEN_0F42_P_2 */
9515   {
9516     { Bad_Opcode },
9517     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9518   },
9519   /* VEX_LEN_0F44_P_0 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9522   },
9523   /* VEX_LEN_0F44_P_2 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9526   },
9527   /* VEX_LEN_0F45_P_0 */
9528   {
9529     { Bad_Opcode },
9530     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9531   },
9532   /* VEX_LEN_0F45_P_2 */
9533   {
9534     { Bad_Opcode },
9535     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9536   },
9537   /* VEX_LEN_0F46_P_0 */
9538   {
9539     { Bad_Opcode },
9540     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9541   },
9542   /* VEX_LEN_0F46_P_2 */
9543   {
9544     { Bad_Opcode },
9545     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9546   },
9547   /* VEX_LEN_0F47_P_0 */
9548   {
9549     { Bad_Opcode },
9550     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9551   },
9552   /* VEX_LEN_0F47_P_2 */
9553   {
9554     { Bad_Opcode },
9555     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9556   },
9557   /* VEX_LEN_0F4A_P_0 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9561   },
9562   /* VEX_LEN_0F4A_P_2 */
9563   {
9564     { Bad_Opcode },
9565     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9566   },
9567   /* VEX_LEN_0F4B_P_0 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9571   },
9572   /* VEX_LEN_0F4B_P_2 */
9573   {
9574     { Bad_Opcode },
9575     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9576   },
9577
9578   /* VEX_LEN_0F51_P_1 */
9579   {
9580     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9581     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9582   },
9583
9584   /* VEX_LEN_0F51_P_3 */
9585   {
9586     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9587     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9588   },
9589
9590   /* VEX_LEN_0F52_P_1 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9593     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9594   },
9595
9596   /* VEX_LEN_0F53_P_1 */
9597   {
9598     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9599     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9600   },
9601
9602   /* VEX_LEN_0F58_P_1 */
9603   {
9604     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9605     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9606   },
9607
9608   /* VEX_LEN_0F58_P_3 */
9609   {
9610     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9611     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9612   },
9613
9614   /* VEX_LEN_0F59_P_1 */
9615   {
9616     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9617     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9618   },
9619
9620   /* VEX_LEN_0F59_P_3 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9623     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9624   },
9625
9626   /* VEX_LEN_0F5A_P_1 */
9627   {
9628     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9629     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9630   },
9631
9632   /* VEX_LEN_0F5A_P_3 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9635     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9636   },
9637
9638   /* VEX_LEN_0F5C_P_1 */
9639   {
9640     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9641     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9642   },
9643
9644   /* VEX_LEN_0F5C_P_3 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9647     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9648   },
9649
9650   /* VEX_LEN_0F5D_P_1 */
9651   {
9652     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9653     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9654   },
9655
9656   /* VEX_LEN_0F5D_P_3 */
9657   {
9658     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9659     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9660   },
9661
9662   /* VEX_LEN_0F5E_P_1 */
9663   {
9664     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9665     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9666   },
9667
9668   /* VEX_LEN_0F5E_P_3 */
9669   {
9670     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9671     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9672   },
9673
9674   /* VEX_LEN_0F5F_P_1 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9677     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9678   },
9679
9680   /* VEX_LEN_0F5F_P_3 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9683     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9684   },
9685
9686   /* VEX_LEN_0F6E_P_2 */
9687   {
9688     { "vmovK",          { XMScalar, Edq }, 0 },
9689     { "vmovK",          { XMScalar, Edq }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F7E_P_1 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9695     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9696   },
9697
9698   /* VEX_LEN_0F7E_P_2 */
9699   {
9700     { "vmovK",          { Edq, XMScalar }, 0 },
9701     { "vmovK",          { Edq, XMScalar }, 0 },
9702   },
9703
9704   /* VEX_LEN_0F90_P_0 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9707   },
9708
9709   /* VEX_LEN_0F90_P_2 */
9710   {
9711     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9712   },
9713
9714   /* VEX_LEN_0F91_P_0 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9717   },
9718
9719   /* VEX_LEN_0F91_P_2 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9722   },
9723
9724   /* VEX_LEN_0F92_P_0 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9727   },
9728
9729   /* VEX_LEN_0F92_P_2 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9732   },
9733
9734   /* VEX_LEN_0F92_P_3 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F93_P_0 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F93_P_2 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9747   },
9748
9749   /* VEX_LEN_0F93_P_3 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9752   },
9753
9754   /* VEX_LEN_0F98_P_0 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9757   },
9758
9759   /* VEX_LEN_0F98_P_2 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9762   },
9763
9764   /* VEX_LEN_0F99_P_0 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9767   },
9768
9769   /* VEX_LEN_0F99_P_2 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9772   },
9773
9774   /* VEX_LEN_0FAE_R_2_M_0 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9777   },
9778
9779   /* VEX_LEN_0FAE_R_3_M_0 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9782   },
9783
9784   /* VEX_LEN_0FC2_P_1 */
9785   {
9786     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9787     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9788   },
9789
9790   /* VEX_LEN_0FC2_P_3 */
9791   {
9792     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9793     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9794   },
9795
9796   /* VEX_LEN_0FC4_P_2 */
9797   {
9798     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9799   },
9800
9801   /* VEX_LEN_0FC5_P_2 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9804   },
9805
9806   /* VEX_LEN_0FD6_P_2 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9809     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9810   },
9811
9812   /* VEX_LEN_0FF7_P_2 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9815   },
9816
9817   /* VEX_LEN_0F3816_P_2 */
9818   {
9819     { Bad_Opcode },
9820     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9821   },
9822
9823   /* VEX_LEN_0F3819_P_2 */
9824   {
9825     { Bad_Opcode },
9826     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9827   },
9828
9829   /* VEX_LEN_0F381A_P_2_M_0 */
9830   {
9831     { Bad_Opcode },
9832     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9833   },
9834
9835   /* VEX_LEN_0F3836_P_2 */
9836   {
9837     { Bad_Opcode },
9838     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9839   },
9840
9841   /* VEX_LEN_0F3841_P_2 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9844   },
9845
9846   /* VEX_LEN_0F385A_P_2_M_0 */
9847   {
9848     { Bad_Opcode },
9849     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9850   },
9851
9852   /* VEX_LEN_0F38DB_P_2 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9855   },
9856
9857   /* VEX_LEN_0F38DC_P_2 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9860   },
9861
9862   /* VEX_LEN_0F38DD_P_2 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9865   },
9866
9867   /* VEX_LEN_0F38DE_P_2 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9870   },
9871
9872   /* VEX_LEN_0F38DF_P_2 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9875   },
9876
9877   /* VEX_LEN_0F38F2_P_0 */
9878   {
9879     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9880   },
9881
9882   /* VEX_LEN_0F38F3_R_1_P_0 */
9883   {
9884     { "blsrS",          { VexGdq, Edq }, 0 },
9885   },
9886
9887   /* VEX_LEN_0F38F3_R_2_P_0 */
9888   {
9889     { "blsmskS",        { VexGdq, Edq }, 0 },
9890   },
9891
9892   /* VEX_LEN_0F38F3_R_3_P_0 */
9893   {
9894     { "blsiS",          { VexGdq, Edq }, 0 },
9895   },
9896
9897   /* VEX_LEN_0F38F5_P_0 */
9898   {
9899     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9900   },
9901
9902   /* VEX_LEN_0F38F5_P_1 */
9903   {
9904     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9905   },
9906
9907   /* VEX_LEN_0F38F5_P_3 */
9908   {
9909     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9910   },
9911
9912   /* VEX_LEN_0F38F6_P_3 */
9913   {
9914     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9915   },
9916
9917   /* VEX_LEN_0F38F7_P_0 */
9918   {
9919     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9920   },
9921
9922   /* VEX_LEN_0F38F7_P_1 */
9923   {
9924     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9925   },
9926
9927   /* VEX_LEN_0F38F7_P_2 */
9928   {
9929     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9930   },
9931
9932   /* VEX_LEN_0F38F7_P_3 */
9933   {
9934     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9935   },
9936
9937   /* VEX_LEN_0F3A00_P_2 */
9938   {
9939     { Bad_Opcode },
9940     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9941   },
9942
9943   /* VEX_LEN_0F3A01_P_2 */
9944   {
9945     { Bad_Opcode },
9946     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9947   },
9948
9949   /* VEX_LEN_0F3A06_P_2 */
9950   {
9951     { Bad_Opcode },
9952     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9953   },
9954
9955   /* VEX_LEN_0F3A0A_P_2 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9958     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9959   },
9960
9961   /* VEX_LEN_0F3A0B_P_2 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9964     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9965   },
9966
9967   /* VEX_LEN_0F3A14_P_2 */
9968   {
9969     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9970   },
9971
9972   /* VEX_LEN_0F3A15_P_2 */
9973   {
9974     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9975   },
9976
9977   /* VEX_LEN_0F3A16_P_2  */
9978   {
9979     { "vpextrK",        { Edq, XM, Ib }, 0 },
9980   },
9981
9982   /* VEX_LEN_0F3A17_P_2 */
9983   {
9984     { "vextractps",     { Edqd, XM, Ib }, 0 },
9985   },
9986
9987   /* VEX_LEN_0F3A18_P_2 */
9988   {
9989     { Bad_Opcode },
9990     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9991   },
9992
9993   /* VEX_LEN_0F3A19_P_2 */
9994   {
9995     { Bad_Opcode },
9996     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9997   },
9998
9999   /* VEX_LEN_0F3A20_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10002   },
10003
10004   /* VEX_LEN_0F3A21_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F3A22_P_2 */
10010   {
10011     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10012   },
10013
10014   /* VEX_LEN_0F3A30_P_2 */
10015   {
10016     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10017   },
10018
10019   /* VEX_LEN_0F3A31_P_2 */
10020   {
10021     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10022   },
10023
10024   /* VEX_LEN_0F3A32_P_2 */
10025   {
10026     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10027   },
10028
10029   /* VEX_LEN_0F3A33_P_2 */
10030   {
10031     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10032   },
10033
10034   /* VEX_LEN_0F3A38_P_2 */
10035   {
10036     { Bad_Opcode },
10037     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10038   },
10039
10040   /* VEX_LEN_0F3A39_P_2 */
10041   {
10042     { Bad_Opcode },
10043     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10044   },
10045
10046   /* VEX_LEN_0F3A41_P_2 */
10047   {
10048     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10049   },
10050
10051   /* VEX_LEN_0F3A44_P_2 */
10052   {
10053     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10054   },
10055
10056   /* VEX_LEN_0F3A46_P_2 */
10057   {
10058     { Bad_Opcode },
10059     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10060   },
10061
10062   /* VEX_LEN_0F3A60_P_2 */
10063   {
10064     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10065   },
10066
10067   /* VEX_LEN_0F3A61_P_2 */
10068   {
10069     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10070   },
10071
10072   /* VEX_LEN_0F3A62_P_2 */
10073   {
10074     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F3A63_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A6A_P_2 */
10083   {
10084     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10085   },
10086
10087   /* VEX_LEN_0F3A6B_P_2 */
10088   {
10089     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10090   },
10091
10092   /* VEX_LEN_0F3A6E_P_2 */
10093   {
10094     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10095   },
10096
10097   /* VEX_LEN_0F3A6F_P_2 */
10098   {
10099     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10100   },
10101
10102   /* VEX_LEN_0F3A7A_P_2 */
10103   {
10104     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10105   },
10106
10107   /* VEX_LEN_0F3A7B_P_2 */
10108   {
10109     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F3A7E_P_2 */
10113   {
10114     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F3A7F_P_2 */
10118   {
10119     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F3ADF_P_2 */
10123   {
10124     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10125   },
10126
10127   /* VEX_LEN_0F3AF0_P_3 */
10128   {
10129     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10130   },
10131
10132   /* VEX_LEN_0FXOP_08_CC */
10133   {
10134      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10135   },
10136
10137   /* VEX_LEN_0FXOP_08_CD */
10138   {
10139      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10140   },
10141
10142   /* VEX_LEN_0FXOP_08_CE */
10143   {
10144      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10145   },
10146
10147   /* VEX_LEN_0FXOP_08_CF */
10148   {
10149      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10150   },
10151
10152   /* VEX_LEN_0FXOP_08_EC */
10153   {
10154      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10155   },
10156
10157   /* VEX_LEN_0FXOP_08_ED */
10158   {
10159      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10160   },
10161
10162   /* VEX_LEN_0FXOP_08_EE */
10163   {
10164      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10165   },
10166
10167   /* VEX_LEN_0FXOP_08_EF */
10168   {
10169      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10170   },
10171
10172   /* VEX_LEN_0FXOP_09_80 */
10173   {
10174     { "vfrczps",        { XM, EXxmm }, 0 },
10175     { "vfrczps",        { XM, EXymmq }, 0 },
10176   },
10177
10178   /* VEX_LEN_0FXOP_09_81 */
10179   {
10180     { "vfrczpd",        { XM, EXxmm }, 0 },
10181     { "vfrczpd",        { XM, EXymmq }, 0 },
10182   },
10183 };
10184
10185 static const struct dis386 vex_w_table[][2] = {
10186   {
10187     /* VEX_W_0F10_P_0 */
10188     { "vmovups",        { XM, EXx }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F10_P_1 */
10192     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F10_P_2 */
10196     { "vmovupd",        { XM, EXx }, 0 },
10197   },
10198   {
10199     /* VEX_W_0F10_P_3 */
10200     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10201   },
10202   {
10203     /* VEX_W_0F11_P_0 */
10204     { "vmovups",        { EXxS, XM }, 0 },
10205   },
10206   {
10207     /* VEX_W_0F11_P_1 */
10208     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F11_P_2 */
10212     { "vmovupd",        { EXxS, XM }, 0 },
10213   },
10214   {
10215     /* VEX_W_0F11_P_3 */
10216     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F12_P_0_M_0 */
10220     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F12_P_0_M_1 */
10224     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10225   },
10226   {
10227     /* VEX_W_0F12_P_1 */
10228     { "vmovsldup",      { XM, EXx }, 0 },
10229   },
10230   {
10231     /* VEX_W_0F12_P_2 */
10232     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10233   },
10234   {
10235     /* VEX_W_0F12_P_3 */
10236     { "vmovddup",       { XM, EXymmq }, 0 },
10237   },
10238   {
10239     /* VEX_W_0F13_M_0 */
10240     { "vmovlpX",        { EXq, XM }, 0 },
10241   },
10242   {
10243     /* VEX_W_0F14 */
10244     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10245   },
10246   {
10247     /* VEX_W_0F15 */
10248     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10249   },
10250   {
10251     /* VEX_W_0F16_P_0_M_0 */
10252     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10253   },
10254   {
10255     /* VEX_W_0F16_P_0_M_1 */
10256     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F16_P_1 */
10260     { "vmovshdup",      { XM, EXx }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F16_P_2 */
10264     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F17_M_0 */
10268     { "vmovhpX",        { EXq, XM }, 0 },
10269   },
10270   {
10271     /* VEX_W_0F28 */
10272     { "vmovapX",        { XM, EXx }, 0 },
10273   },
10274   {
10275     /* VEX_W_0F29 */
10276     { "vmovapX",        { EXxS, XM }, 0 },
10277   },
10278   {
10279     /* VEX_W_0F2B_M_0 */
10280     { "vmovntpX",       { Mx, XM }, 0 },
10281   },
10282   {
10283     /* VEX_W_0F2E_P_0 */
10284     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10285   },
10286   {
10287     /* VEX_W_0F2E_P_2 */
10288     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F2F_P_0 */
10292     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F2F_P_2 */
10296     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F41_P_0_LEN_1 */
10300     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10301     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10302   },
10303   {
10304     /* VEX_W_0F41_P_2_LEN_1 */
10305     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10306     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10307   },
10308   {
10309     /* VEX_W_0F42_P_0_LEN_1 */
10310     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10311     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10312   },
10313   {
10314     /* VEX_W_0F42_P_2_LEN_1 */
10315     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10316     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10317   },
10318   {
10319     /* VEX_W_0F44_P_0_LEN_0 */
10320     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10321     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10322   },
10323   {
10324     /* VEX_W_0F44_P_2_LEN_0 */
10325     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10326     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10327   },
10328   {
10329     /* VEX_W_0F45_P_0_LEN_1 */
10330     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10331     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10332   },
10333   {
10334     /* VEX_W_0F45_P_2_LEN_1 */
10335     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10336     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10337   },
10338   {
10339     /* VEX_W_0F46_P_0_LEN_1 */
10340     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10341     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10342   },
10343   {
10344     /* VEX_W_0F46_P_2_LEN_1 */
10345     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10346     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10347   },
10348   {
10349     /* VEX_W_0F47_P_0_LEN_1 */
10350     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10351     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10352   },
10353   {
10354     /* VEX_W_0F47_P_2_LEN_1 */
10355     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10356     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10357   },
10358   {
10359     /* VEX_W_0F4A_P_0_LEN_1 */
10360     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10361     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10362   },
10363   {
10364     /* VEX_W_0F4A_P_2_LEN_1 */
10365     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10366     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10367   },
10368   {
10369     /* VEX_W_0F4B_P_0_LEN_1 */
10370     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10371     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10372   },
10373   {
10374     /* VEX_W_0F4B_P_2_LEN_1 */
10375     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10376   },
10377   {
10378     /* VEX_W_0F50_M_0 */
10379     { "vmovmskpX",      { Gdq, XS }, 0 },
10380   },
10381   {
10382     /* VEX_W_0F51_P_0 */
10383     { "vsqrtps",        { XM, EXx }, 0 },
10384   },
10385   {
10386     /* VEX_W_0F51_P_1 */
10387     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F51_P_2  */
10391     { "vsqrtpd",        { XM, EXx }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F51_P_3 */
10395     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F52_P_0 */
10399     { "vrsqrtps",       { XM, EXx }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F52_P_1 */
10403     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F53_P_0  */
10407     { "vrcpps",         { XM, EXx }, 0 },
10408   },
10409   {
10410     /* VEX_W_0F53_P_1  */
10411     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10412   },
10413   {
10414     /* VEX_W_0F58_P_0  */
10415     { "vaddps",         { XM, Vex, EXx }, 0 },
10416   },
10417   {
10418     /* VEX_W_0F58_P_1  */
10419     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F58_P_2  */
10423     { "vaddpd",         { XM, Vex, EXx }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F58_P_3  */
10427     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F59_P_0  */
10431     { "vmulps",         { XM, Vex, EXx }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F59_P_1  */
10435     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F59_P_2  */
10439     { "vmulpd",         { XM, Vex, EXx }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F59_P_3  */
10443     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F5A_P_0  */
10447     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F5A_P_1  */
10451     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F5A_P_3  */
10455     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F5B_P_0  */
10459     { "vcvtdq2ps",      { XM, EXx }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F5B_P_1  */
10463     { "vcvttps2dq",     { XM, EXx }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F5B_P_2  */
10467     { "vcvtps2dq",      { XM, EXx }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F5C_P_0  */
10471     { "vsubps",         { XM, Vex, EXx }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F5C_P_1  */
10475     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F5C_P_2  */
10479     { "vsubpd",         { XM, Vex, EXx }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F5C_P_3  */
10483     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F5D_P_0  */
10487     { "vminps",         { XM, Vex, EXx }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F5D_P_1  */
10491     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F5D_P_2  */
10495     { "vminpd",         { XM, Vex, EXx }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F5D_P_3  */
10499     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F5E_P_0  */
10503     { "vdivps",         { XM, Vex, EXx }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F5E_P_1  */
10507     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F5E_P_2  */
10511     { "vdivpd",         { XM, Vex, EXx }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F5E_P_3  */
10515     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F5F_P_0  */
10519     { "vmaxps",         { XM, Vex, EXx }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F5F_P_1  */
10523     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F5F_P_2  */
10527     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F5F_P_3  */
10531     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F60_P_2  */
10535     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F61_P_2  */
10539     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F62_P_2  */
10543     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F63_P_2  */
10547     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F64_P_2  */
10551     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F65_P_2  */
10555     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F66_P_2  */
10559     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F67_P_2  */
10563     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F68_P_2  */
10567     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F69_P_2  */
10571     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F6A_P_2  */
10575     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F6B_P_2  */
10579     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F6C_P_2  */
10583     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F6D_P_2  */
10587     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F6F_P_1  */
10591     { "vmovdqu",        { XM, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F6F_P_2  */
10595     { "vmovdqa",        { XM, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F70_P_1 */
10599     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F70_P_2 */
10603     { "vpshufd",        { XM, EXx, Ib }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F70_P_3 */
10607     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F71_R_2_P_2  */
10611     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F71_R_4_P_2  */
10615     { "vpsraw",         { Vex, XS, Ib }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F71_R_6_P_2  */
10619     { "vpsllw",         { Vex, XS, Ib }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F72_R_2_P_2  */
10623     { "vpsrld",         { Vex, XS, Ib }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F72_R_4_P_2  */
10627     { "vpsrad",         { Vex, XS, Ib }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F72_R_6_P_2  */
10631     { "vpslld",         { Vex, XS, Ib }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F73_R_2_P_2  */
10635     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F73_R_3_P_2  */
10639     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F73_R_6_P_2  */
10643     { "vpsllq",         { Vex, XS, Ib }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F73_R_7_P_2  */
10647     { "vpslldq",        { Vex, XS, Ib }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F74_P_2 */
10651     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F75_P_2 */
10655     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F76_P_2 */
10659     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F77_P_0 */
10663     { "",               { VZERO }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F7C_P_2 */
10667     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F7C_P_3 */
10671     { "vhaddps",        { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F7D_P_2 */
10675     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F7D_P_3 */
10679     { "vhsubps",        { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F7E_P_1 */
10683     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F7F_P_1 */
10687     { "vmovdqu",        { EXxS, XM }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F7F_P_2 */
10691     { "vmovdqa",        { EXxS, XM }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F90_P_0_LEN_0 */
10695     { "kmovw",          { MaskG, MaskE }, 0 },
10696     { "kmovq",          { MaskG, MaskE }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F90_P_2_LEN_0 */
10700     { "kmovb",          { MaskG, MaskBDE }, 0 },
10701     { "kmovd",          { MaskG, MaskBDE }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F91_P_0_LEN_0 */
10705     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10706     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10707   },
10708   {
10709     /* VEX_W_0F91_P_2_LEN_0 */
10710     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10711     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10712   },
10713   {
10714     /* VEX_W_0F92_P_0_LEN_0 */
10715     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10716   },
10717   {
10718     /* VEX_W_0F92_P_2_LEN_0 */
10719     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10720   },
10721   {
10722     /* VEX_W_0F92_P_3_LEN_0 */
10723     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10724     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10725   },
10726   {
10727     /* VEX_W_0F93_P_0_LEN_0 */
10728     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10729   },
10730   {
10731     /* VEX_W_0F93_P_2_LEN_0 */
10732     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10733   },
10734   {
10735     /* VEX_W_0F93_P_3_LEN_0 */
10736     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10737     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10738   },
10739   {
10740     /* VEX_W_0F98_P_0_LEN_0 */
10741     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10742     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10743   },
10744   {
10745     /* VEX_W_0F98_P_2_LEN_0 */
10746     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10747     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10748   },
10749   {
10750     /* VEX_W_0F99_P_0_LEN_0 */
10751     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10752     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10753   },
10754   {
10755     /* VEX_W_0F99_P_2_LEN_0 */
10756     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10757     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10758   },
10759   {
10760     /* VEX_W_0FAE_R_2_M_0 */
10761     { "vldmxcsr",       { Md }, 0 },
10762   },
10763   {
10764     /* VEX_W_0FAE_R_3_M_0 */
10765     { "vstmxcsr",       { Md }, 0 },
10766   },
10767   {
10768     /* VEX_W_0FC2_P_0 */
10769     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10770   },
10771   {
10772     /* VEX_W_0FC2_P_1 */
10773     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10774   },
10775   {
10776     /* VEX_W_0FC2_P_2 */
10777     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10778   },
10779   {
10780     /* VEX_W_0FC2_P_3 */
10781     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10782   },
10783   {
10784     /* VEX_W_0FC4_P_2 */
10785     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10786   },
10787   {
10788     /* VEX_W_0FC5_P_2 */
10789     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10790   },
10791   {
10792     /* VEX_W_0FD0_P_2 */
10793     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10794   },
10795   {
10796     /* VEX_W_0FD0_P_3 */
10797     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0FD1_P_2 */
10801     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10802   },
10803   {
10804     /* VEX_W_0FD2_P_2 */
10805     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10806   },
10807   {
10808     /* VEX_W_0FD3_P_2 */
10809     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10810   },
10811   {
10812     /* VEX_W_0FD4_P_2 */
10813     { "vpaddq",         { XM, Vex, EXx }, 0 },
10814   },
10815   {
10816     /* VEX_W_0FD5_P_2 */
10817     { "vpmullw",        { XM, Vex, EXx }, 0 },
10818   },
10819   {
10820     /* VEX_W_0FD6_P_2 */
10821     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10822   },
10823   {
10824     /* VEX_W_0FD7_P_2_M_1 */
10825     { "vpmovmskb",      { Gdq, XS }, 0 },
10826   },
10827   {
10828     /* VEX_W_0FD8_P_2 */
10829     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10830   },
10831   {
10832     /* VEX_W_0FD9_P_2 */
10833     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FDA_P_2 */
10837     { "vpminub",        { XM, Vex, EXx }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FDB_P_2 */
10841     { "vpand",          { XM, Vex, EXx }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FDC_P_2 */
10845     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FDD_P_2 */
10849     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FDE_P_2 */
10853     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FDF_P_2 */
10857     { "vpandn",         { XM, Vex, EXx }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FE0_P_2  */
10861     { "vpavgb",         { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FE1_P_2  */
10865     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FE2_P_2  */
10869     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FE3_P_2  */
10873     { "vpavgw",         { XM, Vex, EXx }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FE4_P_2  */
10877     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FE5_P_2  */
10881     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FE6_P_1  */
10885     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FE6_P_2  */
10889     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FE6_P_3  */
10893     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FE7_P_2_M_0 */
10897     { "vmovntdq",       { Mx, XM }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FE8_P_2  */
10901     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FE9_P_2  */
10905     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FEA_P_2  */
10909     { "vpminsw",        { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FEB_P_2  */
10913     { "vpor",           { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FEC_P_2  */
10917     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FED_P_2  */
10921     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FEE_P_2  */
10925     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FEF_P_2  */
10929     { "vpxor",          { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FF0_P_3_M_0 */
10933     { "vlddqu",         { XM, M }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FF1_P_2 */
10937     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FF2_P_2 */
10941     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FF3_P_2 */
10945     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FF4_P_2 */
10949     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FF5_P_2 */
10953     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FF6_P_2 */
10957     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FF7_P_2 */
10961     { "vmaskmovdqu",    { XM, XS }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FF8_P_2 */
10965     { "vpsubb",         { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FF9_P_2 */
10969     { "vpsubw",         { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FFA_P_2 */
10973     { "vpsubd",         { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FFB_P_2 */
10977     { "vpsubq",         { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FFC_P_2 */
10981     { "vpaddb",         { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FFD_P_2 */
10985     { "vpaddw",         { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FFE_P_2 */
10989     { "vpaddd",         { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0F3800_P_2  */
10993     { "vpshufb",        { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0F3801_P_2  */
10997     { "vphaddw",        { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0F3802_P_2  */
11001     { "vphaddd",        { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0F3803_P_2  */
11005     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0F3804_P_2  */
11009     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11010   },
11011   {
11012     /* VEX_W_0F3805_P_2  */
11013     { "vphsubw",        { XM, Vex, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0F3806_P_2  */
11017     { "vphsubd",        { XM, Vex, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0F3807_P_2  */
11021     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0F3808_P_2  */
11025     { "vpsignb",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0F3809_P_2  */
11029     { "vpsignw",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0F380A_P_2  */
11033     { "vpsignd",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0F380B_P_2  */
11037     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0F380C_P_2  */
11041     { "vpermilps",      { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0F380D_P_2  */
11045     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0F380E_P_2  */
11049     { "vtestps",        { XM, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0F380F_P_2  */
11053     { "vtestpd",        { XM, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0F3816_P_2  */
11057     { "vpermps",        { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0F3817_P_2 */
11061     { "vptest",         { XM, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F3818_P_2 */
11065     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F3819_P_2 */
11069     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F381A_P_2_M_0 */
11073     { "vbroadcastf128", { XM, Mxmm }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F381C_P_2 */
11077     { "vpabsb",         { XM, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F381D_P_2 */
11081     { "vpabsw",         { XM, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F381E_P_2 */
11085     { "vpabsd",         { XM, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F3820_P_2 */
11089     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3821_P_2 */
11093     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3822_P_2 */
11097     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F3823_P_2 */
11101     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F3824_P_2 */
11105     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F3825_P_2 */
11109     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F3828_P_2 */
11113     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F3829_P_2 */
11117     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F382A_P_2_M_0 */
11121     { "vmovntdqa",      { XM, Mx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F382B_P_2 */
11125     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F382C_P_2_M_0 */
11129     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F382D_P_2_M_0 */
11133     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F382E_P_2_M_0 */
11137     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F382F_P_2_M_0 */
11141     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F3830_P_2 */
11145     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3831_P_2 */
11149     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3832_P_2 */
11153     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3833_P_2 */
11157     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3834_P_2 */
11161     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3835_P_2 */
11165     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3836_P_2  */
11169     { "vpermd",         { XM, Vex, EXx }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3837_P_2 */
11173     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3838_P_2 */
11177     { "vpminsb",        { XM, Vex, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3839_P_2 */
11181     { "vpminsd",        { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F383A_P_2 */
11185     { "vpminuw",        { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F383B_P_2 */
11189     { "vpminud",        { XM, Vex, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F383C_P_2 */
11193     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F383D_P_2 */
11197     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F383E_P_2 */
11201     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F383F_P_2 */
11205     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F3840_P_2 */
11209     { "vpmulld",        { XM, Vex, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3841_P_2 */
11213     { "vphminposuw",    { XM, EXx }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3846_P_2 */
11217     { "vpsravd",        { XM, Vex, EXx }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3858_P_2 */
11221     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3859_P_2 */
11225     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F385A_P_2_M_0 */
11229     { "vbroadcasti128", { XM, Mxmm }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3878_P_2 */
11233     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3879_P_2 */
11237     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F38DB_P_2 */
11241     { "vaesimc",        { XM, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F38DC_P_2 */
11245     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F38DD_P_2 */
11249     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F38DE_P_2 */
11253     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F38DF_P_2 */
11257     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F3A00_P_2 */
11261     { Bad_Opcode },
11262     { "vpermq",         { XM, EXx, Ib }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F3A01_P_2 */
11266     { Bad_Opcode },
11267     { "vpermpd",        { XM, EXx, Ib }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3A02_P_2 */
11271     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3A04_P_2 */
11275     { "vpermilps",      { XM, EXx, Ib }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3A05_P_2 */
11279     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F3A06_P_2 */
11283     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3A08_P_2 */
11287     { "vroundps",       { XM, EXx, Ib }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3A09_P_2 */
11291     { "vroundpd",       { XM, EXx, Ib }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3A0A_P_2 */
11295     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3A0B_P_2 */
11299     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3A0C_P_2 */
11303     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3A0D_P_2 */
11307     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3A0E_P_2 */
11311     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F3A0F_P_2 */
11315     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F3A14_P_2 */
11319     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F3A15_P_2 */
11323     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3A18_P_2 */
11327     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A19_P_2 */
11331     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3A20_P_2 */
11335     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3A21_P_2 */
11339     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3A30_P_2_LEN_0 */
11343     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11344     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11345   },
11346   {
11347     /* VEX_W_0F3A31_P_2_LEN_0 */
11348     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11349     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11350   },
11351   {
11352     /* VEX_W_0F3A32_P_2_LEN_0 */
11353     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11354     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11355   },
11356   {
11357     /* VEX_W_0F3A33_P_2_LEN_0 */
11358     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11359     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11360   },
11361   {
11362     /* VEX_W_0F3A38_P_2 */
11363     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3A39_P_2 */
11367     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3A40_P_2 */
11371     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3A41_P_2 */
11375     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A42_P_2 */
11379     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A44_P_2 */
11383     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A46_P_2 */
11387     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A48_P_2 */
11391     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11392     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3A49_P_2 */
11396     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11397     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F3A4A_P_2 */
11401     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F3A4B_P_2 */
11405     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F3A4C_P_2 */
11409     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A62_P_2 */
11413     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A63_P_2 */
11417     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3ADF_P_2 */
11421     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11422   },
11423 #define NEED_VEX_W_TABLE
11424 #include "i386-dis-evex.h"
11425 #undef NEED_VEX_W_TABLE
11426 };
11427
11428 static const struct dis386 mod_table[][2] = {
11429   {
11430     /* MOD_8D */
11431     { "leaS",           { Gv, M }, 0 },
11432   },
11433   {
11434     /* MOD_C6_REG_7 */
11435     { Bad_Opcode },
11436     { RM_TABLE (RM_C6_REG_7) },
11437   },
11438   {
11439     /* MOD_C7_REG_7 */
11440     { Bad_Opcode },
11441     { RM_TABLE (RM_C7_REG_7) },
11442   },
11443   {
11444     /* MOD_FF_REG_3 */
11445     { "Jcall^", { indirEp }, 0 },
11446   },
11447   {
11448     /* MOD_FF_REG_5 */
11449     { "Jjmp^", { indirEp }, 0 },
11450   },
11451   {
11452     /* MOD_0F01_REG_0 */
11453     { X86_64_TABLE (X86_64_0F01_REG_0) },
11454     { RM_TABLE (RM_0F01_REG_0) },
11455   },
11456   {
11457     /* MOD_0F01_REG_1 */
11458     { X86_64_TABLE (X86_64_0F01_REG_1) },
11459     { RM_TABLE (RM_0F01_REG_1) },
11460   },
11461   {
11462     /* MOD_0F01_REG_2 */
11463     { X86_64_TABLE (X86_64_0F01_REG_2) },
11464     { RM_TABLE (RM_0F01_REG_2) },
11465   },
11466   {
11467     /* MOD_0F01_REG_3 */
11468     { X86_64_TABLE (X86_64_0F01_REG_3) },
11469     { RM_TABLE (RM_0F01_REG_3) },
11470   },
11471   {
11472     /* MOD_0F01_REG_5 */
11473     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11474     { RM_TABLE (RM_0F01_REG_5) },
11475   },
11476   {
11477     /* MOD_0F01_REG_7 */
11478     { "invlpg",         { Mb }, 0 },
11479     { RM_TABLE (RM_0F01_REG_7) },
11480   },
11481   {
11482     /* MOD_0F12_PREFIX_0 */
11483     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11484     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11485   },
11486   {
11487     /* MOD_0F13 */
11488     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11489   },
11490   {
11491     /* MOD_0F16_PREFIX_0 */
11492     { "movhps",         { XM, EXq }, 0 },
11493     { "movlhps",        { XM, EXq }, 0 },
11494   },
11495   {
11496     /* MOD_0F17 */
11497     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11498   },
11499   {
11500     /* MOD_0F18_REG_0 */
11501     { "prefetchnta",    { Mb }, 0 },
11502   },
11503   {
11504     /* MOD_0F18_REG_1 */
11505     { "prefetcht0",     { Mb }, 0 },
11506   },
11507   {
11508     /* MOD_0F18_REG_2 */
11509     { "prefetcht1",     { Mb }, 0 },
11510   },
11511   {
11512     /* MOD_0F18_REG_3 */
11513     { "prefetcht2",     { Mb }, 0 },
11514   },
11515   {
11516     /* MOD_0F18_REG_4 */
11517     { "nop/reserved",   { Mb }, 0 },
11518   },
11519   {
11520     /* MOD_0F18_REG_5 */
11521     { "nop/reserved",   { Mb }, 0 },
11522   },
11523   {
11524     /* MOD_0F18_REG_6 */
11525     { "nop/reserved",   { Mb }, 0 },
11526   },
11527   {
11528     /* MOD_0F18_REG_7 */
11529     { "nop/reserved",   { Mb }, 0 },
11530   },
11531   {
11532     /* MOD_0F1A_PREFIX_0 */
11533     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11534     { "nopQ",           { Ev }, 0 },
11535   },
11536   {
11537     /* MOD_0F1B_PREFIX_0 */
11538     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11539     { "nopQ",           { Ev }, 0 },
11540   },
11541   {
11542     /* MOD_0F1B_PREFIX_1 */
11543     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11544     { "nopQ",           { Ev }, 0 },
11545   },
11546   {
11547     /* MOD_0F1E_PREFIX_1 */
11548     { "nopQ",           { Ev }, 0 },
11549     { REG_TABLE (REG_0F1E_MOD_3) },
11550   },
11551   {
11552     /* MOD_0F24 */
11553     { Bad_Opcode },
11554     { "movL",           { Rd, Td }, 0 },
11555   },
11556   {
11557     /* MOD_0F26 */
11558     { Bad_Opcode },
11559     { "movL",           { Td, Rd }, 0 },
11560   },
11561   {
11562     /* MOD_0F2B_PREFIX_0 */
11563     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11564   },
11565   {
11566     /* MOD_0F2B_PREFIX_1 */
11567     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11568   },
11569   {
11570     /* MOD_0F2B_PREFIX_2 */
11571     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11572   },
11573   {
11574     /* MOD_0F2B_PREFIX_3 */
11575     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11576   },
11577   {
11578     /* MOD_0F51 */
11579     { Bad_Opcode },
11580     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11581   },
11582   {
11583     /* MOD_0F71_REG_2 */
11584     { Bad_Opcode },
11585     { "psrlw",          { MS, Ib }, 0 },
11586   },
11587   {
11588     /* MOD_0F71_REG_4 */
11589     { Bad_Opcode },
11590     { "psraw",          { MS, Ib }, 0 },
11591   },
11592   {
11593     /* MOD_0F71_REG_6 */
11594     { Bad_Opcode },
11595     { "psllw",          { MS, Ib }, 0 },
11596   },
11597   {
11598     /* MOD_0F72_REG_2 */
11599     { Bad_Opcode },
11600     { "psrld",          { MS, Ib }, 0 },
11601   },
11602   {
11603     /* MOD_0F72_REG_4 */
11604     { Bad_Opcode },
11605     { "psrad",          { MS, Ib }, 0 },
11606   },
11607   {
11608     /* MOD_0F72_REG_6 */
11609     { Bad_Opcode },
11610     { "pslld",          { MS, Ib }, 0 },
11611   },
11612   {
11613     /* MOD_0F73_REG_2 */
11614     { Bad_Opcode },
11615     { "psrlq",          { MS, Ib }, 0 },
11616   },
11617   {
11618     /* MOD_0F73_REG_3 */
11619     { Bad_Opcode },
11620     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11621   },
11622   {
11623     /* MOD_0F73_REG_6 */
11624     { Bad_Opcode },
11625     { "psllq",          { MS, Ib }, 0 },
11626   },
11627   {
11628     /* MOD_0F73_REG_7 */
11629     { Bad_Opcode },
11630     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11631   },
11632   {
11633     /* MOD_0FAE_REG_0 */
11634     { "fxsave",         { FXSAVE }, 0 },
11635     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11636   },
11637   {
11638     /* MOD_0FAE_REG_1 */
11639     { "fxrstor",        { FXSAVE }, 0 },
11640     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11641   },
11642   {
11643     /* MOD_0FAE_REG_2 */
11644     { "ldmxcsr",        { Md }, 0 },
11645     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11646   },
11647   {
11648     /* MOD_0FAE_REG_3 */
11649     { "stmxcsr",        { Md }, 0 },
11650     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11651   },
11652   {
11653     /* MOD_0FAE_REG_4 */
11654     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11655     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11656   },
11657   {
11658     /* MOD_0FAE_REG_5 */
11659     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11660     { RM_TABLE (RM_0FAE_REG_5) },
11661   },
11662   {
11663     /* MOD_0FAE_REG_6 */
11664     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11665     { RM_TABLE (RM_0FAE_REG_6) },
11666   },
11667   {
11668     /* MOD_0FAE_REG_7 */
11669     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11670     { RM_TABLE (RM_0FAE_REG_7) },
11671   },
11672   {
11673     /* MOD_0FB2 */
11674     { "lssS",           { Gv, Mp }, 0 },
11675   },
11676   {
11677     /* MOD_0FB4 */
11678     { "lfsS",           { Gv, Mp }, 0 },
11679   },
11680   {
11681     /* MOD_0FB5 */
11682     { "lgsS",           { Gv, Mp }, 0 },
11683   },
11684   {
11685     /* MOD_0FC3 */
11686     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11687   },
11688   {
11689     /* MOD_0FC7_REG_3 */
11690     { "xrstors",        { FXSAVE }, 0 },
11691   },
11692   {
11693     /* MOD_0FC7_REG_4 */
11694     { "xsavec",         { FXSAVE }, 0 },
11695   },
11696   {
11697     /* MOD_0FC7_REG_5 */
11698     { "xsaves",         { FXSAVE }, 0 },
11699   },
11700   {
11701     /* MOD_0FC7_REG_6 */
11702     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11703     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11704   },
11705   {
11706     /* MOD_0FC7_REG_7 */
11707     { "vmptrst",        { Mq }, 0 },
11708     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11709   },
11710   {
11711     /* MOD_0FD7 */
11712     { Bad_Opcode },
11713     { "pmovmskb",       { Gdq, MS }, 0 },
11714   },
11715   {
11716     /* MOD_0FE7_PREFIX_2 */
11717     { "movntdq",        { Mx, XM }, 0 },
11718   },
11719   {
11720     /* MOD_0FF0_PREFIX_3 */
11721     { "lddqu",          { XM, M }, 0 },
11722   },
11723   {
11724     /* MOD_0F382A_PREFIX_2 */
11725     { "movntdqa",       { XM, Mx }, 0 },
11726   },
11727   {
11728     /* MOD_0F38F5_PREFIX_2 */
11729     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11730   },
11731   {
11732     /* MOD_0F38F6_PREFIX_0 */
11733     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11734   },
11735   {
11736     /* MOD_62_32BIT */
11737     { "bound{S|}",      { Gv, Ma }, 0 },
11738     { EVEX_TABLE (EVEX_0F) },
11739   },
11740   {
11741     /* MOD_C4_32BIT */
11742     { "lesS",           { Gv, Mp }, 0 },
11743     { VEX_C4_TABLE (VEX_0F) },
11744   },
11745   {
11746     /* MOD_C5_32BIT */
11747     { "ldsS",           { Gv, Mp }, 0 },
11748     { VEX_C5_TABLE (VEX_0F) },
11749   },
11750   {
11751     /* MOD_VEX_0F12_PREFIX_0 */
11752     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11753     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11754   },
11755   {
11756     /* MOD_VEX_0F13 */
11757     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11758   },
11759   {
11760     /* MOD_VEX_0F16_PREFIX_0 */
11761     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11762     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11763   },
11764   {
11765     /* MOD_VEX_0F17 */
11766     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11767   },
11768   {
11769     /* MOD_VEX_0F2B */
11770     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11771   },
11772   {
11773     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11774     { Bad_Opcode },
11775     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11776   },
11777   {
11778     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11779     { Bad_Opcode },
11780     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11781   },
11782   {
11783     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11784     { Bad_Opcode },
11785     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11786   },
11787   {
11788     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11789     { Bad_Opcode },
11790     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11791   },
11792   {
11793     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11794     { Bad_Opcode },
11795     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11796   },
11797   {
11798     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11799     { Bad_Opcode },
11800     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11801   },
11802   {
11803     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11804     { Bad_Opcode },
11805     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11806   },
11807   {
11808     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11809     { Bad_Opcode },
11810     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11811   },
11812   {
11813     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11814     { Bad_Opcode },
11815     { "knotw",          { MaskG, MaskR }, 0 },
11816   },
11817   {
11818     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11819     { Bad_Opcode },
11820     { "knotq",          { MaskG, MaskR }, 0 },
11821   },
11822   {
11823     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11824     { Bad_Opcode },
11825     { "knotb",          { MaskG, MaskR }, 0 },
11826   },
11827   {
11828     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11829     { Bad_Opcode },
11830     { "knotd",          { MaskG, MaskR }, 0 },
11831   },
11832   {
11833     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11834     { Bad_Opcode },
11835     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11839     { Bad_Opcode },
11840     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11844     { Bad_Opcode },
11845     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11849     { Bad_Opcode },
11850     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852  {
11853     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11854     { Bad_Opcode },
11855     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11859     { Bad_Opcode },
11860     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11864     { Bad_Opcode },
11865     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11869     { Bad_Opcode },
11870     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11874     { Bad_Opcode },
11875     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11879     { Bad_Opcode },
11880     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11881   },
11882   {
11883     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11884     { Bad_Opcode },
11885     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11889     { Bad_Opcode },
11890     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11894     { Bad_Opcode },
11895     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11899     { Bad_Opcode },
11900     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11904     { Bad_Opcode },
11905     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907   {
11908     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11909     { Bad_Opcode },
11910     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11914     { Bad_Opcode },
11915     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11919     { Bad_Opcode },
11920     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11924     { Bad_Opcode },
11925     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_0F50 */
11929     { Bad_Opcode },
11930     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11931   },
11932   {
11933     /* MOD_VEX_0F71_REG_2 */
11934     { Bad_Opcode },
11935     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11936   },
11937   {
11938     /* MOD_VEX_0F71_REG_4 */
11939     { Bad_Opcode },
11940     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11941   },
11942   {
11943     /* MOD_VEX_0F71_REG_6 */
11944     { Bad_Opcode },
11945     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11946   },
11947   {
11948     /* MOD_VEX_0F72_REG_2 */
11949     { Bad_Opcode },
11950     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11951   },
11952   {
11953     /* MOD_VEX_0F72_REG_4 */
11954     { Bad_Opcode },
11955     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11956   },
11957   {
11958     /* MOD_VEX_0F72_REG_6 */
11959     { Bad_Opcode },
11960     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11961   },
11962   {
11963     /* MOD_VEX_0F73_REG_2 */
11964     { Bad_Opcode },
11965     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11966   },
11967   {
11968     /* MOD_VEX_0F73_REG_3 */
11969     { Bad_Opcode },
11970     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11971   },
11972   {
11973     /* MOD_VEX_0F73_REG_6 */
11974     { Bad_Opcode },
11975     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11976   },
11977   {
11978     /* MOD_VEX_0F73_REG_7 */
11979     { Bad_Opcode },
11980     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11981   },
11982   {
11983     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11984     { "kmovw",          { Ew, MaskG }, 0 },
11985     { Bad_Opcode },
11986   },
11987   {
11988     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11989     { "kmovq",          { Eq, MaskG }, 0 },
11990     { Bad_Opcode },
11991   },
11992   {
11993     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11994     { "kmovb",          { Eb, MaskG }, 0 },
11995     { Bad_Opcode },
11996   },
11997   {
11998     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11999     { "kmovd",          { Ed, MaskG }, 0 },
12000     { Bad_Opcode },
12001   },
12002   {
12003     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12004     { Bad_Opcode },
12005     { "kmovw",          { MaskG, Rdq }, 0 },
12006   },
12007   {
12008     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12009     { Bad_Opcode },
12010     { "kmovb",          { MaskG, Rdq }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12014     { Bad_Opcode },
12015     { "kmovd",          { MaskG, Rdq }, 0 },
12016   },
12017   {
12018     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12019     { Bad_Opcode },
12020     { "kmovq",          { MaskG, Rdq }, 0 },
12021   },
12022   {
12023     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12024     { Bad_Opcode },
12025     { "kmovw",          { Gdq, MaskR }, 0 },
12026   },
12027   {
12028     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12029     { Bad_Opcode },
12030     { "kmovb",          { Gdq, MaskR }, 0 },
12031   },
12032   {
12033     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12034     { Bad_Opcode },
12035     { "kmovd",          { Gdq, MaskR }, 0 },
12036   },
12037   {
12038     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12039     { Bad_Opcode },
12040     { "kmovq",          { Gdq, MaskR }, 0 },
12041   },
12042   {
12043     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12044     { Bad_Opcode },
12045     { "kortestw", { MaskG, MaskR }, 0 },
12046   },
12047   {
12048     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12049     { Bad_Opcode },
12050     { "kortestq", { MaskG, MaskR }, 0 },
12051   },
12052   {
12053     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12054     { Bad_Opcode },
12055     { "kortestb", { MaskG, MaskR }, 0 },
12056   },
12057   {
12058     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12059     { Bad_Opcode },
12060     { "kortestd", { MaskG, MaskR }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12064     { Bad_Opcode },
12065     { "ktestw", { MaskG, MaskR }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12069     { Bad_Opcode },
12070     { "ktestq", { MaskG, MaskR }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12074     { Bad_Opcode },
12075     { "ktestb", { MaskG, MaskR }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12079     { Bad_Opcode },
12080     { "ktestd", { MaskG, MaskR }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_0FAE_REG_2 */
12084     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12085   },
12086   {
12087     /* MOD_VEX_0FAE_REG_3 */
12088     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12089   },
12090   {
12091     /* MOD_VEX_0FD7_PREFIX_2 */
12092     { Bad_Opcode },
12093     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12094   },
12095   {
12096     /* MOD_VEX_0FE7_PREFIX_2 */
12097     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12098   },
12099   {
12100     /* MOD_VEX_0FF0_PREFIX_3 */
12101     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12102   },
12103   {
12104     /* MOD_VEX_0F381A_PREFIX_2 */
12105     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12106   },
12107   {
12108     /* MOD_VEX_0F382A_PREFIX_2 */
12109     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12110   },
12111   {
12112     /* MOD_VEX_0F382C_PREFIX_2 */
12113     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12114   },
12115   {
12116     /* MOD_VEX_0F382D_PREFIX_2 */
12117     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12118   },
12119   {
12120     /* MOD_VEX_0F382E_PREFIX_2 */
12121     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12122   },
12123   {
12124     /* MOD_VEX_0F382F_PREFIX_2 */
12125     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12126   },
12127   {
12128     /* MOD_VEX_0F385A_PREFIX_2 */
12129     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12130   },
12131   {
12132     /* MOD_VEX_0F388C_PREFIX_2 */
12133     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12134   },
12135   {
12136     /* MOD_VEX_0F388E_PREFIX_2 */
12137     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12141     { Bad_Opcode },
12142     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12143   },
12144   {
12145     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12146     { Bad_Opcode },
12147     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12148   },
12149   {
12150     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12151     { Bad_Opcode },
12152     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12153   },
12154   {
12155     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12156     { Bad_Opcode },
12157     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12158   },
12159   {
12160     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12161     { Bad_Opcode },
12162     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12163   },
12164   {
12165     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12166     { Bad_Opcode },
12167     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12168   },
12169   {
12170     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12171     { Bad_Opcode },
12172     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12173   },
12174   {
12175     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12176     { Bad_Opcode },
12177     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12178   },
12179 #define NEED_MOD_TABLE
12180 #include "i386-dis-evex.h"
12181 #undef NEED_MOD_TABLE
12182 };
12183
12184 static const struct dis386 rm_table[][8] = {
12185   {
12186     /* RM_C6_REG_7 */
12187     { "xabort",         { Skip_MODRM, Ib }, 0 },
12188   },
12189   {
12190     /* RM_C7_REG_7 */
12191     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12192   },
12193   {
12194     /* RM_0F01_REG_0 */
12195     { Bad_Opcode },
12196     { "vmcall",         { Skip_MODRM }, 0 },
12197     { "vmlaunch",       { Skip_MODRM }, 0 },
12198     { "vmresume",       { Skip_MODRM }, 0 },
12199     { "vmxoff",         { Skip_MODRM }, 0 },
12200   },
12201   {
12202     /* RM_0F01_REG_1 */
12203     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12204     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12205     { "clac",           { Skip_MODRM }, 0 },
12206     { "stac",           { Skip_MODRM }, 0 },
12207     { Bad_Opcode },
12208     { Bad_Opcode },
12209     { Bad_Opcode },
12210     { "encls",          { Skip_MODRM }, 0 },
12211   },
12212   {
12213     /* RM_0F01_REG_2 */
12214     { "xgetbv",         { Skip_MODRM }, 0 },
12215     { "xsetbv",         { Skip_MODRM }, 0 },
12216     { Bad_Opcode },
12217     { Bad_Opcode },
12218     { "vmfunc",         { Skip_MODRM }, 0 },
12219     { "xend",           { Skip_MODRM }, 0 },
12220     { "xtest",          { Skip_MODRM }, 0 },
12221     { "enclu",          { Skip_MODRM }, 0 },
12222   },
12223   {
12224     /* RM_0F01_REG_3 */
12225     { "vmrun",          { Skip_MODRM }, 0 },
12226     { "vmmcall",        { Skip_MODRM }, 0 },
12227     { "vmload",         { Skip_MODRM }, 0 },
12228     { "vmsave",         { Skip_MODRM }, 0 },
12229     { "stgi",           { Skip_MODRM }, 0 },
12230     { "clgi",           { Skip_MODRM }, 0 },
12231     { "skinit",         { Skip_MODRM }, 0 },
12232     { "invlpga",        { Skip_MODRM }, 0 },
12233   },
12234   {
12235     /* RM_0F01_REG_5 */
12236     { Bad_Opcode },
12237     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
12238     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12239     { Bad_Opcode },
12240     { Bad_Opcode },
12241     { Bad_Opcode },
12242     { "rdpkru",         { Skip_MODRM }, 0 },
12243     { "wrpkru",         { Skip_MODRM }, 0 },
12244   },
12245   {
12246     /* RM_0F01_REG_7 */
12247     { "swapgs",         { Skip_MODRM }, 0  },
12248     { "rdtscp",         { Skip_MODRM }, 0  },
12249     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12250     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12251     { "clzero",         { Skip_MODRM }, 0  },
12252   },
12253   {
12254     /* RM_0F1E_MOD_3_REG_7 */
12255     { "nopQ",           { Ev }, 0 },
12256     { "nopQ",           { Ev }, 0 },
12257     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12258     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12259     { "nopQ",           { Ev }, 0 },
12260     { "nopQ",           { Ev }, 0 },
12261     { "nopQ",           { Ev }, 0 },
12262     { "nopQ",           { Ev }, 0 },
12263   },
12264   {
12265     /* RM_0FAE_REG_5 */
12266     { "lfence",         { Skip_MODRM }, 0 },
12267   },
12268   {
12269     /* RM_0FAE_REG_6 */
12270     { "mfence",         { Skip_MODRM }, 0 },
12271   },
12272   {
12273     /* RM_0FAE_REG_7 */
12274     { "sfence",         { Skip_MODRM }, 0 },
12275
12276   },
12277 };
12278
12279 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12280
12281 /* We use the high bit to indicate different name for the same
12282    prefix.  */
12283 #define REP_PREFIX      (0xf3 | 0x100)
12284 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12285 #define XRELEASE_PREFIX (0xf3 | 0x400)
12286 #define BND_PREFIX      (0xf2 | 0x400)
12287 #define NOTRACK_PREFIX  (0x3e | 0x100)
12288
12289 static int
12290 ckprefix (void)
12291 {
12292   int newrex, i, length;
12293   rex = 0;
12294   rex_ignored = 0;
12295   prefixes = 0;
12296   used_prefixes = 0;
12297   rex_used = 0;
12298   last_lock_prefix = -1;
12299   last_repz_prefix = -1;
12300   last_repnz_prefix = -1;
12301   last_data_prefix = -1;
12302   last_addr_prefix = -1;
12303   last_rex_prefix = -1;
12304   last_seg_prefix = -1;
12305   last_active_prefix = -1;
12306   fwait_prefix = -1;
12307   active_seg_prefix = 0;
12308   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12309     all_prefixes[i] = 0;
12310   i = 0;
12311   length = 0;
12312   /* The maximum instruction length is 15bytes.  */
12313   while (length < MAX_CODE_LENGTH - 1)
12314     {
12315       FETCH_DATA (the_info, codep + 1);
12316       newrex = 0;
12317       switch (*codep)
12318         {
12319         /* REX prefixes family.  */
12320         case 0x40:
12321         case 0x41:
12322         case 0x42:
12323         case 0x43:
12324         case 0x44:
12325         case 0x45:
12326         case 0x46:
12327         case 0x47:
12328         case 0x48:
12329         case 0x49:
12330         case 0x4a:
12331         case 0x4b:
12332         case 0x4c:
12333         case 0x4d:
12334         case 0x4e:
12335         case 0x4f:
12336           if (address_mode == mode_64bit)
12337             newrex = *codep;
12338           else
12339             return 1;
12340           last_rex_prefix = i;
12341           break;
12342         case 0xf3:
12343           prefixes |= PREFIX_REPZ;
12344           last_repz_prefix = i;
12345           break;
12346         case 0xf2:
12347           prefixes |= PREFIX_REPNZ;
12348           last_repnz_prefix = i;
12349           break;
12350         case 0xf0:
12351           prefixes |= PREFIX_LOCK;
12352           last_lock_prefix = i;
12353           break;
12354         case 0x2e:
12355           prefixes |= PREFIX_CS;
12356           last_seg_prefix = i;
12357           active_seg_prefix = PREFIX_CS;
12358           break;
12359         case 0x36:
12360           prefixes |= PREFIX_SS;
12361           last_seg_prefix = i;
12362           active_seg_prefix = PREFIX_SS;
12363           break;
12364         case 0x3e:
12365           prefixes |= PREFIX_DS;
12366           last_seg_prefix = i;
12367           active_seg_prefix = PREFIX_DS;
12368           break;
12369         case 0x26:
12370           prefixes |= PREFIX_ES;
12371           last_seg_prefix = i;
12372           active_seg_prefix = PREFIX_ES;
12373           break;
12374         case 0x64:
12375           prefixes |= PREFIX_FS;
12376           last_seg_prefix = i;
12377           active_seg_prefix = PREFIX_FS;
12378           break;
12379         case 0x65:
12380           prefixes |= PREFIX_GS;
12381           last_seg_prefix = i;
12382           active_seg_prefix = PREFIX_GS;
12383           break;
12384         case 0x66:
12385           prefixes |= PREFIX_DATA;
12386           last_data_prefix = i;
12387           break;
12388         case 0x67:
12389           prefixes |= PREFIX_ADDR;
12390           last_addr_prefix = i;
12391           break;
12392         case FWAIT_OPCODE:
12393           /* fwait is really an instruction.  If there are prefixes
12394              before the fwait, they belong to the fwait, *not* to the
12395              following instruction.  */
12396           fwait_prefix = i;
12397           if (prefixes || rex)
12398             {
12399               prefixes |= PREFIX_FWAIT;
12400               codep++;
12401               /* This ensures that the previous REX prefixes are noticed
12402                  as unused prefixes, as in the return case below.  */
12403               rex_used = rex;
12404               return 1;
12405             }
12406           prefixes = PREFIX_FWAIT;
12407           break;
12408         default:
12409           return 1;
12410         }
12411       /* Rex is ignored when followed by another prefix.  */
12412       if (rex)
12413         {
12414           rex_used = rex;
12415           return 1;
12416         }
12417       if (*codep != FWAIT_OPCODE)
12418         {
12419           last_active_prefix = i;
12420           all_prefixes[i++] = *codep;
12421         }
12422       rex = newrex;
12423       codep++;
12424       length++;
12425     }
12426   return 0;
12427 }
12428
12429 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12430    prefix byte.  */
12431
12432 static const char *
12433 prefix_name (int pref, int sizeflag)
12434 {
12435   static const char *rexes [16] =
12436     {
12437       "rex",            /* 0x40 */
12438       "rex.B",          /* 0x41 */
12439       "rex.X",          /* 0x42 */
12440       "rex.XB",         /* 0x43 */
12441       "rex.R",          /* 0x44 */
12442       "rex.RB",         /* 0x45 */
12443       "rex.RX",         /* 0x46 */
12444       "rex.RXB",        /* 0x47 */
12445       "rex.W",          /* 0x48 */
12446       "rex.WB",         /* 0x49 */
12447       "rex.WX",         /* 0x4a */
12448       "rex.WXB",        /* 0x4b */
12449       "rex.WR",         /* 0x4c */
12450       "rex.WRB",        /* 0x4d */
12451       "rex.WRX",        /* 0x4e */
12452       "rex.WRXB",       /* 0x4f */
12453     };
12454
12455   switch (pref)
12456     {
12457     /* REX prefixes family.  */
12458     case 0x40:
12459     case 0x41:
12460     case 0x42:
12461     case 0x43:
12462     case 0x44:
12463     case 0x45:
12464     case 0x46:
12465     case 0x47:
12466     case 0x48:
12467     case 0x49:
12468     case 0x4a:
12469     case 0x4b:
12470     case 0x4c:
12471     case 0x4d:
12472     case 0x4e:
12473     case 0x4f:
12474       return rexes [pref - 0x40];
12475     case 0xf3:
12476       return "repz";
12477     case 0xf2:
12478       return "repnz";
12479     case 0xf0:
12480       return "lock";
12481     case 0x2e:
12482       return "cs";
12483     case 0x36:
12484       return "ss";
12485     case 0x3e:
12486       return "ds";
12487     case 0x26:
12488       return "es";
12489     case 0x64:
12490       return "fs";
12491     case 0x65:
12492       return "gs";
12493     case 0x66:
12494       return (sizeflag & DFLAG) ? "data16" : "data32";
12495     case 0x67:
12496       if (address_mode == mode_64bit)
12497         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12498       else
12499         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12500     case FWAIT_OPCODE:
12501       return "fwait";
12502     case REP_PREFIX:
12503       return "rep";
12504     case XACQUIRE_PREFIX:
12505       return "xacquire";
12506     case XRELEASE_PREFIX:
12507       return "xrelease";
12508     case BND_PREFIX:
12509       return "bnd";
12510     case NOTRACK_PREFIX:
12511       return "notrack";
12512     default:
12513       return NULL;
12514     }
12515 }
12516
12517 static char op_out[MAX_OPERANDS][100];
12518 static int op_ad, op_index[MAX_OPERANDS];
12519 static int two_source_ops;
12520 static bfd_vma op_address[MAX_OPERANDS];
12521 static bfd_vma op_riprel[MAX_OPERANDS];
12522 static bfd_vma start_pc;
12523
12524 /*
12525  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12526  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12527  *   section of the "Virtual 8086 Mode" chapter.)
12528  * 'pc' should be the address of this instruction, it will
12529  *   be used to print the target address if this is a relative jump or call
12530  * The function returns the length of this instruction in bytes.
12531  */
12532
12533 static char intel_syntax;
12534 static char intel_mnemonic = !SYSV386_COMPAT;
12535 static char open_char;
12536 static char close_char;
12537 static char separator_char;
12538 static char scale_char;
12539
12540 enum x86_64_isa
12541 {
12542   amd64 = 0,
12543   intel64
12544 };
12545
12546 static enum x86_64_isa isa64;
12547
12548 /* Here for backwards compatibility.  When gdb stops using
12549    print_insn_i386_att and print_insn_i386_intel these functions can
12550    disappear, and print_insn_i386 be merged into print_insn.  */
12551 int
12552 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12553 {
12554   intel_syntax = 0;
12555
12556   return print_insn (pc, info);
12557 }
12558
12559 int
12560 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12561 {
12562   intel_syntax = 1;
12563
12564   return print_insn (pc, info);
12565 }
12566
12567 int
12568 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12569 {
12570   intel_syntax = -1;
12571
12572   return print_insn (pc, info);
12573 }
12574
12575 void
12576 print_i386_disassembler_options (FILE *stream)
12577 {
12578   fprintf (stream, _("\n\
12579 The following i386/x86-64 specific disassembler options are supported for use\n\
12580 with the -M switch (multiple options should be separated by commas):\n"));
12581
12582   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12583   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12584   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12585   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12586   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12587   fprintf (stream, _("  att-mnemonic\n"
12588                      "              Display instruction in AT&T mnemonic\n"));
12589   fprintf (stream, _("  intel-mnemonic\n"
12590                      "              Display instruction in Intel mnemonic\n"));
12591   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12592   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12593   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12594   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12595   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12596   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12597   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12598   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12599 }
12600
12601 /* Bad opcode.  */
12602 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12603
12604 /* Get a pointer to struct dis386 with a valid name.  */
12605
12606 static const struct dis386 *
12607 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12608 {
12609   int vindex, vex_table_index;
12610
12611   if (dp->name != NULL)
12612     return dp;
12613
12614   switch (dp->op[0].bytemode)
12615     {
12616     case USE_REG_TABLE:
12617       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12618       break;
12619
12620     case USE_MOD_TABLE:
12621       vindex = modrm.mod == 0x3 ? 1 : 0;
12622       dp = &mod_table[dp->op[1].bytemode][vindex];
12623       break;
12624
12625     case USE_RM_TABLE:
12626       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12627       break;
12628
12629     case USE_PREFIX_TABLE:
12630       if (need_vex)
12631         {
12632           /* The prefix in VEX is implicit.  */
12633           switch (vex.prefix)
12634             {
12635             case 0:
12636               vindex = 0;
12637               break;
12638             case REPE_PREFIX_OPCODE:
12639               vindex = 1;
12640               break;
12641             case DATA_PREFIX_OPCODE:
12642               vindex = 2;
12643               break;
12644             case REPNE_PREFIX_OPCODE:
12645               vindex = 3;
12646               break;
12647             default:
12648               abort ();
12649               break;
12650             }
12651         }
12652       else
12653         {
12654           int last_prefix = -1;
12655           int prefix = 0;
12656           vindex = 0;
12657           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12658              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12659              last one wins.  */
12660           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12661             {
12662               if (last_repz_prefix > last_repnz_prefix)
12663                 {
12664                   vindex = 1;
12665                   prefix = PREFIX_REPZ;
12666                   last_prefix = last_repz_prefix;
12667                 }
12668               else
12669                 {
12670                   vindex = 3;
12671                   prefix = PREFIX_REPNZ;
12672                   last_prefix = last_repnz_prefix;
12673                 }
12674
12675               /* Check if prefix should be ignored.  */
12676               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12677                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12678                    & prefix) != 0)
12679                 vindex = 0;
12680             }
12681
12682           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12683             {
12684               vindex = 2;
12685               prefix = PREFIX_DATA;
12686               last_prefix = last_data_prefix;
12687             }
12688
12689           if (vindex != 0)
12690             {
12691               used_prefixes |= prefix;
12692               all_prefixes[last_prefix] = 0;
12693             }
12694         }
12695       dp = &prefix_table[dp->op[1].bytemode][vindex];
12696       break;
12697
12698     case USE_X86_64_TABLE:
12699       vindex = address_mode == mode_64bit ? 1 : 0;
12700       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12701       break;
12702
12703     case USE_3BYTE_TABLE:
12704       FETCH_DATA (info, codep + 2);
12705       vindex = *codep++;
12706       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12707       end_codep = codep;
12708       modrm.mod = (*codep >> 6) & 3;
12709       modrm.reg = (*codep >> 3) & 7;
12710       modrm.rm = *codep & 7;
12711       break;
12712
12713     case USE_VEX_LEN_TABLE:
12714       if (!need_vex)
12715         abort ();
12716
12717       switch (vex.length)
12718         {
12719         case 128:
12720           vindex = 0;
12721           break;
12722         case 256:
12723           vindex = 1;
12724           break;
12725         default:
12726           abort ();
12727           break;
12728         }
12729
12730       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12731       break;
12732
12733     case USE_XOP_8F_TABLE:
12734       FETCH_DATA (info, codep + 3);
12735       /* All bits in the REX prefix are ignored.  */
12736       rex_ignored = rex;
12737       rex = ~(*codep >> 5) & 0x7;
12738
12739       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12740       switch ((*codep & 0x1f))
12741         {
12742         default:
12743           dp = &bad_opcode;
12744           return dp;
12745         case 0x8:
12746           vex_table_index = XOP_08;
12747           break;
12748         case 0x9:
12749           vex_table_index = XOP_09;
12750           break;
12751         case 0xa:
12752           vex_table_index = XOP_0A;
12753           break;
12754         }
12755       codep++;
12756       vex.w = *codep & 0x80;
12757       if (vex.w && address_mode == mode_64bit)
12758         rex |= REX_W;
12759
12760       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12761       if (address_mode != mode_64bit)
12762         {
12763           /* In 16/32-bit mode REX_B is silently ignored.  */
12764           rex &= ~REX_B;
12765           if (vex.register_specifier > 0x7)
12766             {
12767               dp = &bad_opcode;
12768               return dp;
12769             }
12770         }
12771
12772       vex.length = (*codep & 0x4) ? 256 : 128;
12773       switch ((*codep & 0x3))
12774         {
12775         case 0:
12776           vex.prefix = 0;
12777           break;
12778         case 1:
12779           vex.prefix = DATA_PREFIX_OPCODE;
12780           break;
12781         case 2:
12782           vex.prefix = REPE_PREFIX_OPCODE;
12783           break;
12784         case 3:
12785           vex.prefix = REPNE_PREFIX_OPCODE;
12786           break;
12787         }
12788       need_vex = 1;
12789       need_vex_reg = 1;
12790       codep++;
12791       vindex = *codep++;
12792       dp = &xop_table[vex_table_index][vindex];
12793
12794       end_codep = codep;
12795       FETCH_DATA (info, codep + 1);
12796       modrm.mod = (*codep >> 6) & 3;
12797       modrm.reg = (*codep >> 3) & 7;
12798       modrm.rm = *codep & 7;
12799       break;
12800
12801     case USE_VEX_C4_TABLE:
12802       /* VEX prefix.  */
12803       FETCH_DATA (info, codep + 3);
12804       /* All bits in the REX prefix are ignored.  */
12805       rex_ignored = rex;
12806       rex = ~(*codep >> 5) & 0x7;
12807       switch ((*codep & 0x1f))
12808         {
12809         default:
12810           dp = &bad_opcode;
12811           return dp;
12812         case 0x1:
12813           vex_table_index = VEX_0F;
12814           break;
12815         case 0x2:
12816           vex_table_index = VEX_0F38;
12817           break;
12818         case 0x3:
12819           vex_table_index = VEX_0F3A;
12820           break;
12821         }
12822       codep++;
12823       vex.w = *codep & 0x80;
12824       if (address_mode == mode_64bit)
12825         {
12826           if (vex.w)
12827             rex |= REX_W;
12828           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12829         }
12830       else
12831         {
12832           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12833              is ignored, other REX bits are 0 and the highest bit in
12834              VEX.vvvv is also ignored.  */
12835           rex = 0;
12836           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12837         }
12838       vex.length = (*codep & 0x4) ? 256 : 128;
12839       switch ((*codep & 0x3))
12840         {
12841         case 0:
12842           vex.prefix = 0;
12843           break;
12844         case 1:
12845           vex.prefix = DATA_PREFIX_OPCODE;
12846           break;
12847         case 2:
12848           vex.prefix = REPE_PREFIX_OPCODE;
12849           break;
12850         case 3:
12851           vex.prefix = REPNE_PREFIX_OPCODE;
12852           break;
12853         }
12854       need_vex = 1;
12855       need_vex_reg = 1;
12856       codep++;
12857       vindex = *codep++;
12858       dp = &vex_table[vex_table_index][vindex];
12859       end_codep = codep;
12860       /* There is no MODRM byte for VEX0F 77.  */
12861       if (vex_table_index != VEX_0F || vindex != 0x77)
12862         {
12863           FETCH_DATA (info, codep + 1);
12864           modrm.mod = (*codep >> 6) & 3;
12865           modrm.reg = (*codep >> 3) & 7;
12866           modrm.rm = *codep & 7;
12867         }
12868       break;
12869
12870     case USE_VEX_C5_TABLE:
12871       /* VEX prefix.  */
12872       FETCH_DATA (info, codep + 2);
12873       /* All bits in the REX prefix are ignored.  */
12874       rex_ignored = rex;
12875       rex = (*codep & 0x80) ? 0 : REX_R;
12876
12877       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12878          VEX.vvvv is 1.  */
12879       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12880       vex.w = 0;
12881       vex.length = (*codep & 0x4) ? 256 : 128;
12882       switch ((*codep & 0x3))
12883         {
12884         case 0:
12885           vex.prefix = 0;
12886           break;
12887         case 1:
12888           vex.prefix = DATA_PREFIX_OPCODE;
12889           break;
12890         case 2:
12891           vex.prefix = REPE_PREFIX_OPCODE;
12892           break;
12893         case 3:
12894           vex.prefix = REPNE_PREFIX_OPCODE;
12895           break;
12896         }
12897       need_vex = 1;
12898       need_vex_reg = 1;
12899       codep++;
12900       vindex = *codep++;
12901       dp = &vex_table[dp->op[1].bytemode][vindex];
12902       end_codep = codep;
12903       /* There is no MODRM byte for VEX 77.  */
12904       if (vindex != 0x77)
12905         {
12906           FETCH_DATA (info, codep + 1);
12907           modrm.mod = (*codep >> 6) & 3;
12908           modrm.reg = (*codep >> 3) & 7;
12909           modrm.rm = *codep & 7;
12910         }
12911       break;
12912
12913     case USE_VEX_W_TABLE:
12914       if (!need_vex)
12915         abort ();
12916
12917       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12918       break;
12919
12920     case USE_EVEX_TABLE:
12921       two_source_ops = 0;
12922       /* EVEX prefix.  */
12923       vex.evex = 1;
12924       FETCH_DATA (info, codep + 4);
12925       /* All bits in the REX prefix are ignored.  */
12926       rex_ignored = rex;
12927       /* The first byte after 0x62.  */
12928       rex = ~(*codep >> 5) & 0x7;
12929       vex.r = *codep & 0x10;
12930       switch ((*codep & 0xf))
12931         {
12932         default:
12933           return &bad_opcode;
12934         case 0x1:
12935           vex_table_index = EVEX_0F;
12936           break;
12937         case 0x2:
12938           vex_table_index = EVEX_0F38;
12939           break;
12940         case 0x3:
12941           vex_table_index = EVEX_0F3A;
12942           break;
12943         }
12944
12945       /* The second byte after 0x62.  */
12946       codep++;
12947       vex.w = *codep & 0x80;
12948       if (vex.w && address_mode == mode_64bit)
12949         rex |= REX_W;
12950
12951       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12952       if (address_mode != mode_64bit)
12953         {
12954           /* In 16/32-bit mode silently ignore following bits.  */
12955           rex &= ~REX_B;
12956           vex.r = 1;
12957           vex.v = 1;
12958           vex.register_specifier &= 0x7;
12959         }
12960
12961       /* The U bit.  */
12962       if (!(*codep & 0x4))
12963         return &bad_opcode;
12964
12965       switch ((*codep & 0x3))
12966         {
12967         case 0:
12968           vex.prefix = 0;
12969           break;
12970         case 1:
12971           vex.prefix = DATA_PREFIX_OPCODE;
12972           break;
12973         case 2:
12974           vex.prefix = REPE_PREFIX_OPCODE;
12975           break;
12976         case 3:
12977           vex.prefix = REPNE_PREFIX_OPCODE;
12978           break;
12979         }
12980
12981       /* The third byte after 0x62.  */
12982       codep++;
12983
12984       /* Remember the static rounding bits.  */
12985       vex.ll = (*codep >> 5) & 3;
12986       vex.b = (*codep & 0x10) != 0;
12987
12988       vex.v = *codep & 0x8;
12989       vex.mask_register_specifier = *codep & 0x7;
12990       vex.zeroing = *codep & 0x80;
12991
12992       need_vex = 1;
12993       need_vex_reg = 1;
12994       codep++;
12995       vindex = *codep++;
12996       dp = &evex_table[vex_table_index][vindex];
12997       end_codep = codep;
12998       FETCH_DATA (info, codep + 1);
12999       modrm.mod = (*codep >> 6) & 3;
13000       modrm.reg = (*codep >> 3) & 7;
13001       modrm.rm = *codep & 7;
13002
13003       /* Set vector length.  */
13004       if (modrm.mod == 3 && vex.b)
13005         vex.length = 512;
13006       else
13007         {
13008           switch (vex.ll)
13009             {
13010             case 0x0:
13011               vex.length = 128;
13012               break;
13013             case 0x1:
13014               vex.length = 256;
13015               break;
13016             case 0x2:
13017               vex.length = 512;
13018               break;
13019             default:
13020               return &bad_opcode;
13021             }
13022         }
13023       break;
13024
13025     case 0:
13026       dp = &bad_opcode;
13027       break;
13028
13029     default:
13030       abort ();
13031     }
13032
13033   if (dp->name != NULL)
13034     return dp;
13035   else
13036     return get_valid_dis386 (dp, info);
13037 }
13038
13039 static void
13040 get_sib (disassemble_info *info, int sizeflag)
13041 {
13042   /* If modrm.mod == 3, operand must be register.  */
13043   if (need_modrm
13044       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13045       && modrm.mod != 3
13046       && modrm.rm == 4)
13047     {
13048       FETCH_DATA (info, codep + 2);
13049       sib.index = (codep [1] >> 3) & 7;
13050       sib.scale = (codep [1] >> 6) & 3;
13051       sib.base = codep [1] & 7;
13052     }
13053 }
13054
13055 static int
13056 print_insn (bfd_vma pc, disassemble_info *info)
13057 {
13058   const struct dis386 *dp;
13059   int i;
13060   char *op_txt[MAX_OPERANDS];
13061   int needcomma;
13062   int sizeflag, orig_sizeflag;
13063   const char *p;
13064   struct dis_private priv;
13065   int prefix_length;
13066
13067   priv.orig_sizeflag = AFLAG | DFLAG;
13068   if ((info->mach & bfd_mach_i386_i386) != 0)
13069     address_mode = mode_32bit;
13070   else if (info->mach == bfd_mach_i386_i8086)
13071     {
13072       address_mode = mode_16bit;
13073       priv.orig_sizeflag = 0;
13074     }
13075   else
13076     address_mode = mode_64bit;
13077
13078   if (intel_syntax == (char) -1)
13079     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13080
13081   for (p = info->disassembler_options; p != NULL; )
13082     {
13083       if (CONST_STRNEQ (p, "amd64"))
13084         isa64 = amd64;
13085       else if (CONST_STRNEQ (p, "intel64"))
13086         isa64 = intel64;
13087       else if (CONST_STRNEQ (p, "x86-64"))
13088         {
13089           address_mode = mode_64bit;
13090           priv.orig_sizeflag = AFLAG | DFLAG;
13091         }
13092       else if (CONST_STRNEQ (p, "i386"))
13093         {
13094           address_mode = mode_32bit;
13095           priv.orig_sizeflag = AFLAG | DFLAG;
13096         }
13097       else if (CONST_STRNEQ (p, "i8086"))
13098         {
13099           address_mode = mode_16bit;
13100           priv.orig_sizeflag = 0;
13101         }
13102       else if (CONST_STRNEQ (p, "intel"))
13103         {
13104           intel_syntax = 1;
13105           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13106             intel_mnemonic = 1;
13107         }
13108       else if (CONST_STRNEQ (p, "att"))
13109         {
13110           intel_syntax = 0;
13111           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13112             intel_mnemonic = 0;
13113         }
13114       else if (CONST_STRNEQ (p, "addr"))
13115         {
13116           if (address_mode == mode_64bit)
13117             {
13118               if (p[4] == '3' && p[5] == '2')
13119                 priv.orig_sizeflag &= ~AFLAG;
13120               else if (p[4] == '6' && p[5] == '4')
13121                 priv.orig_sizeflag |= AFLAG;
13122             }
13123           else
13124             {
13125               if (p[4] == '1' && p[5] == '6')
13126                 priv.orig_sizeflag &= ~AFLAG;
13127               else if (p[4] == '3' && p[5] == '2')
13128                 priv.orig_sizeflag |= AFLAG;
13129             }
13130         }
13131       else if (CONST_STRNEQ (p, "data"))
13132         {
13133           if (p[4] == '1' && p[5] == '6')
13134             priv.orig_sizeflag &= ~DFLAG;
13135           else if (p[4] == '3' && p[5] == '2')
13136             priv.orig_sizeflag |= DFLAG;
13137         }
13138       else if (CONST_STRNEQ (p, "suffix"))
13139         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13140
13141       p = strchr (p, ',');
13142       if (p != NULL)
13143         p++;
13144     }
13145
13146   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13147     {
13148       (*info->fprintf_func) (info->stream,
13149                              _("64-bit address is disabled"));
13150       return -1;
13151     }
13152
13153   if (intel_syntax)
13154     {
13155       names64 = intel_names64;
13156       names32 = intel_names32;
13157       names16 = intel_names16;
13158       names8 = intel_names8;
13159       names8rex = intel_names8rex;
13160       names_seg = intel_names_seg;
13161       names_mm = intel_names_mm;
13162       names_bnd = intel_names_bnd;
13163       names_xmm = intel_names_xmm;
13164       names_ymm = intel_names_ymm;
13165       names_zmm = intel_names_zmm;
13166       index64 = intel_index64;
13167       index32 = intel_index32;
13168       names_mask = intel_names_mask;
13169       index16 = intel_index16;
13170       open_char = '[';
13171       close_char = ']';
13172       separator_char = '+';
13173       scale_char = '*';
13174     }
13175   else
13176     {
13177       names64 = att_names64;
13178       names32 = att_names32;
13179       names16 = att_names16;
13180       names8 = att_names8;
13181       names8rex = att_names8rex;
13182       names_seg = att_names_seg;
13183       names_mm = att_names_mm;
13184       names_bnd = att_names_bnd;
13185       names_xmm = att_names_xmm;
13186       names_ymm = att_names_ymm;
13187       names_zmm = att_names_zmm;
13188       index64 = att_index64;
13189       index32 = att_index32;
13190       names_mask = att_names_mask;
13191       index16 = att_index16;
13192       open_char = '(';
13193       close_char =  ')';
13194       separator_char = ',';
13195       scale_char = ',';
13196     }
13197
13198   /* The output looks better if we put 7 bytes on a line, since that
13199      puts most long word instructions on a single line.  Use 8 bytes
13200      for Intel L1OM.  */
13201   if ((info->mach & bfd_mach_l1om) != 0)
13202     info->bytes_per_line = 8;
13203   else
13204     info->bytes_per_line = 7;
13205
13206   info->private_data = &priv;
13207   priv.max_fetched = priv.the_buffer;
13208   priv.insn_start = pc;
13209
13210   obuf[0] = 0;
13211   for (i = 0; i < MAX_OPERANDS; ++i)
13212     {
13213       op_out[i][0] = 0;
13214       op_index[i] = -1;
13215     }
13216
13217   the_info = info;
13218   start_pc = pc;
13219   start_codep = priv.the_buffer;
13220   codep = priv.the_buffer;
13221
13222   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13223     {
13224       const char *name;
13225
13226       /* Getting here means we tried for data but didn't get it.  That
13227          means we have an incomplete instruction of some sort.  Just
13228          print the first byte as a prefix or a .byte pseudo-op.  */
13229       if (codep > priv.the_buffer)
13230         {
13231           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13232           if (name != NULL)
13233             (*info->fprintf_func) (info->stream, "%s", name);
13234           else
13235             {
13236               /* Just print the first byte as a .byte instruction.  */
13237               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13238                                      (unsigned int) priv.the_buffer[0]);
13239             }
13240
13241           return 1;
13242         }
13243
13244       return -1;
13245     }
13246
13247   obufp = obuf;
13248   sizeflag = priv.orig_sizeflag;
13249
13250   if (!ckprefix () || rex_used)
13251     {
13252       /* Too many prefixes or unused REX prefixes.  */
13253       for (i = 0;
13254            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13255            i++)
13256         (*info->fprintf_func) (info->stream, "%s%s",
13257                                i == 0 ? "" : " ",
13258                                prefix_name (all_prefixes[i], sizeflag));
13259       return i;
13260     }
13261
13262   insn_codep = codep;
13263
13264   FETCH_DATA (info, codep + 1);
13265   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13266
13267   if (((prefixes & PREFIX_FWAIT)
13268        && ((*codep < 0xd8) || (*codep > 0xdf))))
13269     {
13270       /* Handle prefixes before fwait.  */
13271       for (i = 0; i < fwait_prefix && all_prefixes[i];
13272            i++)
13273         (*info->fprintf_func) (info->stream, "%s ",
13274                                prefix_name (all_prefixes[i], sizeflag));
13275       (*info->fprintf_func) (info->stream, "fwait");
13276       return i + 1;
13277     }
13278
13279   if (*codep == 0x0f)
13280     {
13281       unsigned char threebyte;
13282
13283       codep++;
13284       FETCH_DATA (info, codep + 1);
13285       threebyte = *codep;
13286       dp = &dis386_twobyte[threebyte];
13287       need_modrm = twobyte_has_modrm[*codep];
13288       codep++;
13289     }
13290   else
13291     {
13292       dp = &dis386[*codep];
13293       need_modrm = onebyte_has_modrm[*codep];
13294       codep++;
13295     }
13296
13297   /* Save sizeflag for printing the extra prefixes later before updating
13298      it for mnemonic and operand processing.  The prefix names depend
13299      only on the address mode.  */
13300   orig_sizeflag = sizeflag;
13301   if (prefixes & PREFIX_ADDR)
13302     sizeflag ^= AFLAG;
13303   if ((prefixes & PREFIX_DATA))
13304     sizeflag ^= DFLAG;
13305
13306   end_codep = codep;
13307   if (need_modrm)
13308     {
13309       FETCH_DATA (info, codep + 1);
13310       modrm.mod = (*codep >> 6) & 3;
13311       modrm.reg = (*codep >> 3) & 7;
13312       modrm.rm = *codep & 7;
13313     }
13314
13315   need_vex = 0;
13316   need_vex_reg = 0;
13317   vex_w_done = 0;
13318   vex.evex = 0;
13319
13320   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13321     {
13322       get_sib (info, sizeflag);
13323       dofloat (sizeflag);
13324     }
13325   else
13326     {
13327       dp = get_valid_dis386 (dp, info);
13328       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13329         {
13330           get_sib (info, sizeflag);
13331           for (i = 0; i < MAX_OPERANDS; ++i)
13332             {
13333               obufp = op_out[i];
13334               op_ad = MAX_OPERANDS - 1 - i;
13335               if (dp->op[i].rtn)
13336                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13337               /* For EVEX instruction after the last operand masking
13338                  should be printed.  */
13339               if (i == 0 && vex.evex)
13340                 {
13341                   /* Don't print {%k0}.  */
13342                   if (vex.mask_register_specifier)
13343                     {
13344                       oappend ("{");
13345                       oappend (names_mask[vex.mask_register_specifier]);
13346                       oappend ("}");
13347                     }
13348                   if (vex.zeroing)
13349                     oappend ("{z}");
13350                 }
13351             }
13352         }
13353     }
13354
13355   /* Check if the REX prefix is used.  */
13356   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13357     all_prefixes[last_rex_prefix] = 0;
13358
13359   /* Check if the SEG prefix is used.  */
13360   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13361                    | PREFIX_FS | PREFIX_GS)) != 0
13362       && (used_prefixes & active_seg_prefix) != 0)
13363     all_prefixes[last_seg_prefix] = 0;
13364
13365   /* Check if the ADDR prefix is used.  */
13366   if ((prefixes & PREFIX_ADDR) != 0
13367       && (used_prefixes & PREFIX_ADDR) != 0)
13368     all_prefixes[last_addr_prefix] = 0;
13369
13370   /* Check if the DATA prefix is used.  */
13371   if ((prefixes & PREFIX_DATA) != 0
13372       && (used_prefixes & PREFIX_DATA) != 0)
13373     all_prefixes[last_data_prefix] = 0;
13374
13375   /* Print the extra prefixes.  */
13376   prefix_length = 0;
13377   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13378     if (all_prefixes[i])
13379       {
13380         const char *name;
13381         name = prefix_name (all_prefixes[i], orig_sizeflag);
13382         if (name == NULL)
13383           abort ();
13384         prefix_length += strlen (name) + 1;
13385         (*info->fprintf_func) (info->stream, "%s ", name);
13386       }
13387
13388   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13389      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13390      used by putop and MMX/SSE operand and may be overriden by the
13391      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13392      separately.  */
13393   if (dp->prefix_requirement == PREFIX_OPCODE
13394       && dp != &bad_opcode
13395       && (((prefixes
13396             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13397            && (used_prefixes
13398                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13399           || ((((prefixes
13400                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13401                 == PREFIX_DATA)
13402                && (used_prefixes & PREFIX_DATA) == 0))))
13403     {
13404       (*info->fprintf_func) (info->stream, "(bad)");
13405       return end_codep - priv.the_buffer;
13406     }
13407
13408   /* Check maximum code length.  */
13409   if ((codep - start_codep) > MAX_CODE_LENGTH)
13410     {
13411       (*info->fprintf_func) (info->stream, "(bad)");
13412       return MAX_CODE_LENGTH;
13413     }
13414
13415   obufp = mnemonicendp;
13416   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13417     oappend (" ");
13418   oappend (" ");
13419   (*info->fprintf_func) (info->stream, "%s", obuf);
13420
13421   /* The enter and bound instructions are printed with operands in the same
13422      order as the intel book; everything else is printed in reverse order.  */
13423   if (intel_syntax || two_source_ops)
13424     {
13425       bfd_vma riprel;
13426
13427       for (i = 0; i < MAX_OPERANDS; ++i)
13428         op_txt[i] = op_out[i];
13429
13430       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13431           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13432         {
13433           op_txt[2] = op_out[3];
13434           op_txt[3] = op_out[2];
13435         }
13436
13437       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13438         {
13439           op_ad = op_index[i];
13440           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13441           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13442           riprel = op_riprel[i];
13443           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13444           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13445         }
13446     }
13447   else
13448     {
13449       for (i = 0; i < MAX_OPERANDS; ++i)
13450         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13451     }
13452
13453   needcomma = 0;
13454   for (i = 0; i < MAX_OPERANDS; ++i)
13455     if (*op_txt[i])
13456       {
13457         if (needcomma)
13458           (*info->fprintf_func) (info->stream, ",");
13459         if (op_index[i] != -1 && !op_riprel[i])
13460           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13461         else
13462           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13463         needcomma = 1;
13464       }
13465
13466   for (i = 0; i < MAX_OPERANDS; i++)
13467     if (op_index[i] != -1 && op_riprel[i])
13468       {
13469         (*info->fprintf_func) (info->stream, "        # ");
13470         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13471                                                 + op_address[op_index[i]]), info);
13472         break;
13473       }
13474   return codep - priv.the_buffer;
13475 }
13476
13477 static const char *float_mem[] = {
13478   /* d8 */
13479   "fadd{s|}",
13480   "fmul{s|}",
13481   "fcom{s|}",
13482   "fcomp{s|}",
13483   "fsub{s|}",
13484   "fsubr{s|}",
13485   "fdiv{s|}",
13486   "fdivr{s|}",
13487   /* d9 */
13488   "fld{s|}",
13489   "(bad)",
13490   "fst{s|}",
13491   "fstp{s|}",
13492   "fldenvIC",
13493   "fldcw",
13494   "fNstenvIC",
13495   "fNstcw",
13496   /* da */
13497   "fiadd{l|}",
13498   "fimul{l|}",
13499   "ficom{l|}",
13500   "ficomp{l|}",
13501   "fisub{l|}",
13502   "fisubr{l|}",
13503   "fidiv{l|}",
13504   "fidivr{l|}",
13505   /* db */
13506   "fild{l|}",
13507   "fisttp{l|}",
13508   "fist{l|}",
13509   "fistp{l|}",
13510   "(bad)",
13511   "fld{t||t|}",
13512   "(bad)",
13513   "fstp{t||t|}",
13514   /* dc */
13515   "fadd{l|}",
13516   "fmul{l|}",
13517   "fcom{l|}",
13518   "fcomp{l|}",
13519   "fsub{l|}",
13520   "fsubr{l|}",
13521   "fdiv{l|}",
13522   "fdivr{l|}",
13523   /* dd */
13524   "fld{l|}",
13525   "fisttp{ll|}",
13526   "fst{l||}",
13527   "fstp{l|}",
13528   "frstorIC",
13529   "(bad)",
13530   "fNsaveIC",
13531   "fNstsw",
13532   /* de */
13533   "fiadd",
13534   "fimul",
13535   "ficom",
13536   "ficomp",
13537   "fisub",
13538   "fisubr",
13539   "fidiv",
13540   "fidivr",
13541   /* df */
13542   "fild",
13543   "fisttp",
13544   "fist",
13545   "fistp",
13546   "fbld",
13547   "fild{ll|}",
13548   "fbstp",
13549   "fistp{ll|}",
13550 };
13551
13552 static const unsigned char float_mem_mode[] = {
13553   /* d8 */
13554   d_mode,
13555   d_mode,
13556   d_mode,
13557   d_mode,
13558   d_mode,
13559   d_mode,
13560   d_mode,
13561   d_mode,
13562   /* d9 */
13563   d_mode,
13564   0,
13565   d_mode,
13566   d_mode,
13567   0,
13568   w_mode,
13569   0,
13570   w_mode,
13571   /* da */
13572   d_mode,
13573   d_mode,
13574   d_mode,
13575   d_mode,
13576   d_mode,
13577   d_mode,
13578   d_mode,
13579   d_mode,
13580   /* db */
13581   d_mode,
13582   d_mode,
13583   d_mode,
13584   d_mode,
13585   0,
13586   t_mode,
13587   0,
13588   t_mode,
13589   /* dc */
13590   q_mode,
13591   q_mode,
13592   q_mode,
13593   q_mode,
13594   q_mode,
13595   q_mode,
13596   q_mode,
13597   q_mode,
13598   /* dd */
13599   q_mode,
13600   q_mode,
13601   q_mode,
13602   q_mode,
13603   0,
13604   0,
13605   0,
13606   w_mode,
13607   /* de */
13608   w_mode,
13609   w_mode,
13610   w_mode,
13611   w_mode,
13612   w_mode,
13613   w_mode,
13614   w_mode,
13615   w_mode,
13616   /* df */
13617   w_mode,
13618   w_mode,
13619   w_mode,
13620   w_mode,
13621   t_mode,
13622   q_mode,
13623   t_mode,
13624   q_mode
13625 };
13626
13627 #define ST { OP_ST, 0 }
13628 #define STi { OP_STi, 0 }
13629
13630 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13631 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13632 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13633 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13634 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13635 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13636 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13637 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13638 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13639
13640 static const struct dis386 float_reg[][8] = {
13641   /* d8 */
13642   {
13643     { "fadd",   { ST, STi }, 0 },
13644     { "fmul",   { ST, STi }, 0 },
13645     { "fcom",   { STi }, 0 },
13646     { "fcomp",  { STi }, 0 },
13647     { "fsub",   { ST, STi }, 0 },
13648     { "fsubr",  { ST, STi }, 0 },
13649     { "fdiv",   { ST, STi }, 0 },
13650     { "fdivr",  { ST, STi }, 0 },
13651   },
13652   /* d9 */
13653   {
13654     { "fld",    { STi }, 0 },
13655     { "fxch",   { STi }, 0 },
13656     { FGRPd9_2 },
13657     { Bad_Opcode },
13658     { FGRPd9_4 },
13659     { FGRPd9_5 },
13660     { FGRPd9_6 },
13661     { FGRPd9_7 },
13662   },
13663   /* da */
13664   {
13665     { "fcmovb", { ST, STi }, 0 },
13666     { "fcmove", { ST, STi }, 0 },
13667     { "fcmovbe",{ ST, STi }, 0 },
13668     { "fcmovu", { ST, STi }, 0 },
13669     { Bad_Opcode },
13670     { FGRPda_5 },
13671     { Bad_Opcode },
13672     { Bad_Opcode },
13673   },
13674   /* db */
13675   {
13676     { "fcmovnb",{ ST, STi }, 0 },
13677     { "fcmovne",{ ST, STi }, 0 },
13678     { "fcmovnbe",{ ST, STi }, 0 },
13679     { "fcmovnu",{ ST, STi }, 0 },
13680     { FGRPdb_4 },
13681     { "fucomi", { ST, STi }, 0 },
13682     { "fcomi",  { ST, STi }, 0 },
13683     { Bad_Opcode },
13684   },
13685   /* dc */
13686   {
13687     { "fadd",   { STi, ST }, 0 },
13688     { "fmul",   { STi, ST }, 0 },
13689     { Bad_Opcode },
13690     { Bad_Opcode },
13691     { "fsub!M", { STi, ST }, 0 },
13692     { "fsubM",  { STi, ST }, 0 },
13693     { "fdiv!M", { STi, ST }, 0 },
13694     { "fdivM",  { STi, ST }, 0 },
13695   },
13696   /* dd */
13697   {
13698     { "ffree",  { STi }, 0 },
13699     { Bad_Opcode },
13700     { "fst",    { STi }, 0 },
13701     { "fstp",   { STi }, 0 },
13702     { "fucom",  { STi }, 0 },
13703     { "fucomp", { STi }, 0 },
13704     { Bad_Opcode },
13705     { Bad_Opcode },
13706   },
13707   /* de */
13708   {
13709     { "faddp",  { STi, ST }, 0 },
13710     { "fmulp",  { STi, ST }, 0 },
13711     { Bad_Opcode },
13712     { FGRPde_3 },
13713     { "fsub!Mp", { STi, ST }, 0 },
13714     { "fsubMp", { STi, ST }, 0 },
13715     { "fdiv!Mp", { STi, ST }, 0 },
13716     { "fdivMp", { STi, ST }, 0 },
13717   },
13718   /* df */
13719   {
13720     { "ffreep", { STi }, 0 },
13721     { Bad_Opcode },
13722     { Bad_Opcode },
13723     { Bad_Opcode },
13724     { FGRPdf_4 },
13725     { "fucomip", { ST, STi }, 0 },
13726     { "fcomip", { ST, STi }, 0 },
13727     { Bad_Opcode },
13728   },
13729 };
13730
13731 static char *fgrps[][8] = {
13732   /* Bad opcode 0 */
13733   {
13734     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13735   },
13736
13737   /* d9_2  1 */
13738   {
13739     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13740   },
13741
13742   /* d9_4  2 */
13743   {
13744     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13745   },
13746
13747   /* d9_5  3 */
13748   {
13749     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13750   },
13751
13752   /* d9_6  4 */
13753   {
13754     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13755   },
13756
13757   /* d9_7  5 */
13758   {
13759     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13760   },
13761
13762   /* da_5  6 */
13763   {
13764     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13765   },
13766
13767   /* db_4  7 */
13768   {
13769     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13770     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13771   },
13772
13773   /* de_3  8 */
13774   {
13775     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13776   },
13777
13778   /* df_4  9 */
13779   {
13780     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13781   },
13782 };
13783
13784 static void
13785 swap_operand (void)
13786 {
13787   mnemonicendp[0] = '.';
13788   mnemonicendp[1] = 's';
13789   mnemonicendp += 2;
13790 }
13791
13792 static void
13793 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13794                int sizeflag ATTRIBUTE_UNUSED)
13795 {
13796   /* Skip mod/rm byte.  */
13797   MODRM_CHECK;
13798   codep++;
13799 }
13800
13801 static void
13802 dofloat (int sizeflag)
13803 {
13804   const struct dis386 *dp;
13805   unsigned char floatop;
13806
13807   floatop = codep[-1];
13808
13809   if (modrm.mod != 3)
13810     {
13811       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13812
13813       putop (float_mem[fp_indx], sizeflag);
13814       obufp = op_out[0];
13815       op_ad = 2;
13816       OP_E (float_mem_mode[fp_indx], sizeflag);
13817       return;
13818     }
13819   /* Skip mod/rm byte.  */
13820   MODRM_CHECK;
13821   codep++;
13822
13823   dp = &float_reg[floatop - 0xd8][modrm.reg];
13824   if (dp->name == NULL)
13825     {
13826       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13827
13828       /* Instruction fnstsw is only one with strange arg.  */
13829       if (floatop == 0xdf && codep[-1] == 0xe0)
13830         strcpy (op_out[0], names16[0]);
13831     }
13832   else
13833     {
13834       putop (dp->name, sizeflag);
13835
13836       obufp = op_out[0];
13837       op_ad = 2;
13838       if (dp->op[0].rtn)
13839         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13840
13841       obufp = op_out[1];
13842       op_ad = 1;
13843       if (dp->op[1].rtn)
13844         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13845     }
13846 }
13847
13848 /* Like oappend (below), but S is a string starting with '%'.
13849    In Intel syntax, the '%' is elided.  */
13850 static void
13851 oappend_maybe_intel (const char *s)
13852 {
13853   oappend (s + intel_syntax);
13854 }
13855
13856 static void
13857 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13858 {
13859   oappend_maybe_intel ("%st");
13860 }
13861
13862 static void
13863 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13864 {
13865   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13866   oappend_maybe_intel (scratchbuf);
13867 }
13868
13869 /* Capital letters in template are macros.  */
13870 static int
13871 putop (const char *in_template, int sizeflag)
13872 {
13873   const char *p;
13874   int alt = 0;
13875   int cond = 1;
13876   unsigned int l = 0, len = 1;
13877   char last[4];
13878
13879 #define SAVE_LAST(c)                    \
13880   if (l < len && l < sizeof (last))     \
13881     last[l++] = c;                      \
13882   else                                  \
13883     abort ();
13884
13885   for (p = in_template; *p; p++)
13886     {
13887       switch (*p)
13888         {
13889         default:
13890           *obufp++ = *p;
13891           break;
13892         case '%':
13893           len++;
13894           break;
13895         case '!':
13896           cond = 0;
13897           break;
13898         case '{':
13899           if (intel_syntax)
13900             {
13901               while (*++p != '|')
13902                 if (*p == '}' || *p == '\0')
13903                   abort ();
13904             }
13905           /* Fall through.  */
13906         case 'I':
13907           alt = 1;
13908           continue;
13909         case '|':
13910           while (*++p != '}')
13911             {
13912               if (*p == '\0')
13913                 abort ();
13914             }
13915           break;
13916         case '}':
13917           break;
13918         case 'A':
13919           if (intel_syntax)
13920             break;
13921           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13922             *obufp++ = 'b';
13923           break;
13924         case 'B':
13925           if (l == 0 && len == 1)
13926             {
13927 case_B:
13928               if (intel_syntax)
13929                 break;
13930               if (sizeflag & SUFFIX_ALWAYS)
13931                 *obufp++ = 'b';
13932             }
13933           else
13934             {
13935               if (l != 1
13936                   || len != 2
13937                   || last[0] != 'L')
13938                 {
13939                   SAVE_LAST (*p);
13940                   break;
13941                 }
13942
13943               if (address_mode == mode_64bit
13944                   && !(prefixes & PREFIX_ADDR))
13945                 {
13946                   *obufp++ = 'a';
13947                   *obufp++ = 'b';
13948                   *obufp++ = 's';
13949                 }
13950
13951               goto case_B;
13952             }
13953           break;
13954         case 'C':
13955           if (intel_syntax && !alt)
13956             break;
13957           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13958             {
13959               if (sizeflag & DFLAG)
13960                 *obufp++ = intel_syntax ? 'd' : 'l';
13961               else
13962                 *obufp++ = intel_syntax ? 'w' : 's';
13963               used_prefixes |= (prefixes & PREFIX_DATA);
13964             }
13965           break;
13966         case 'D':
13967           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13968             break;
13969           USED_REX (REX_W);
13970           if (modrm.mod == 3)
13971             {
13972               if (rex & REX_W)
13973                 *obufp++ = 'q';
13974               else
13975                 {
13976                   if (sizeflag & DFLAG)
13977                     *obufp++ = intel_syntax ? 'd' : 'l';
13978                   else
13979                     *obufp++ = 'w';
13980                   used_prefixes |= (prefixes & PREFIX_DATA);
13981                 }
13982             }
13983           else
13984             *obufp++ = 'w';
13985           break;
13986         case 'E':               /* For jcxz/jecxz */
13987           if (address_mode == mode_64bit)
13988             {
13989               if (sizeflag & AFLAG)
13990                 *obufp++ = 'r';
13991               else
13992                 *obufp++ = 'e';
13993             }
13994           else
13995             if (sizeflag & AFLAG)
13996               *obufp++ = 'e';
13997           used_prefixes |= (prefixes & PREFIX_ADDR);
13998           break;
13999         case 'F':
14000           if (intel_syntax)
14001             break;
14002           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14003             {
14004               if (sizeflag & AFLAG)
14005                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14006               else
14007                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14008               used_prefixes |= (prefixes & PREFIX_ADDR);
14009             }
14010           break;
14011         case 'G':
14012           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14013             break;
14014           if ((rex & REX_W) || (sizeflag & DFLAG))
14015             *obufp++ = 'l';
14016           else
14017             *obufp++ = 'w';
14018           if (!(rex & REX_W))
14019             used_prefixes |= (prefixes & PREFIX_DATA);
14020           break;
14021         case 'H':
14022           if (intel_syntax)
14023             break;
14024           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14025               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14026             {
14027               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14028               *obufp++ = ',';
14029               *obufp++ = 'p';
14030               if (prefixes & PREFIX_DS)
14031                 *obufp++ = 't';
14032               else
14033                 *obufp++ = 'n';
14034             }
14035           break;
14036         case 'J':
14037           if (intel_syntax)
14038             break;
14039           *obufp++ = 'l';
14040           break;
14041         case 'K':
14042           USED_REX (REX_W);
14043           if (rex & REX_W)
14044             *obufp++ = 'q';
14045           else
14046             *obufp++ = 'd';
14047           break;
14048         case 'Z':
14049           if (l != 0 || len != 1)
14050             {
14051               if (l != 1 || len != 2 || last[0] != 'X')
14052                 {
14053                   SAVE_LAST (*p);
14054                   break;
14055                 }
14056               if (!need_vex || !vex.evex)
14057                 abort ();
14058               if (intel_syntax
14059                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14060                 break;
14061               switch (vex.length)
14062                 {
14063                 case 128:
14064                   *obufp++ = 'x';
14065                   break;
14066                 case 256:
14067                   *obufp++ = 'y';
14068                   break;
14069                 case 512:
14070                   *obufp++ = 'z';
14071                   break;
14072                 default:
14073                   abort ();
14074                 }
14075               break;
14076             }
14077           if (intel_syntax)
14078             break;
14079           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14080             {
14081               *obufp++ = 'q';
14082               break;
14083             }
14084           /* Fall through.  */
14085           goto case_L;
14086         case 'L':
14087           if (l != 0 || len != 1)
14088             {
14089               SAVE_LAST (*p);
14090               break;
14091             }
14092 case_L:
14093           if (intel_syntax)
14094             break;
14095           if (sizeflag & SUFFIX_ALWAYS)
14096             *obufp++ = 'l';
14097           break;
14098         case 'M':
14099           if (intel_mnemonic != cond)
14100             *obufp++ = 'r';
14101           break;
14102         case 'N':
14103           if ((prefixes & PREFIX_FWAIT) == 0)
14104             *obufp++ = 'n';
14105           else
14106             used_prefixes |= PREFIX_FWAIT;
14107           break;
14108         case 'O':
14109           USED_REX (REX_W);
14110           if (rex & REX_W)
14111             *obufp++ = 'o';
14112           else if (intel_syntax && (sizeflag & DFLAG))
14113             *obufp++ = 'q';
14114           else
14115             *obufp++ = 'd';
14116           if (!(rex & REX_W))
14117             used_prefixes |= (prefixes & PREFIX_DATA);
14118           break;
14119         case '&':
14120           if (!intel_syntax
14121               && address_mode == mode_64bit
14122               && isa64 == intel64)
14123             {
14124               *obufp++ = 'q';
14125               break;
14126             }
14127           /* Fall through.  */
14128         case 'T':
14129           if (!intel_syntax
14130               && address_mode == mode_64bit
14131               && ((sizeflag & DFLAG) || (rex & REX_W)))
14132             {
14133               *obufp++ = 'q';
14134               break;
14135             }
14136           /* Fall through.  */
14137           goto case_P;
14138         case 'P':
14139           if (l == 0 && len == 1)
14140             {
14141 case_P:
14142               if (intel_syntax)
14143                 {
14144                   if ((rex & REX_W) == 0
14145                       && (prefixes & PREFIX_DATA))
14146                     {
14147                       if ((sizeflag & DFLAG) == 0)
14148                         *obufp++ = 'w';
14149                       used_prefixes |= (prefixes & PREFIX_DATA);
14150                     }
14151                   break;
14152                 }
14153               if ((prefixes & PREFIX_DATA)
14154                   || (rex & REX_W)
14155                   || (sizeflag & SUFFIX_ALWAYS))
14156                 {
14157                   USED_REX (REX_W);
14158                   if (rex & REX_W)
14159                     *obufp++ = 'q';
14160                   else
14161                     {
14162                       if (sizeflag & DFLAG)
14163                         *obufp++ = 'l';
14164                       else
14165                         *obufp++ = 'w';
14166                       used_prefixes |= (prefixes & PREFIX_DATA);
14167                     }
14168                 }
14169             }
14170           else
14171             {
14172               if (l != 1 || len != 2 || last[0] != 'L')
14173                 {
14174                   SAVE_LAST (*p);
14175                   break;
14176                 }
14177
14178               if ((prefixes & PREFIX_DATA)
14179                   || (rex & REX_W)
14180                   || (sizeflag & SUFFIX_ALWAYS))
14181                 {
14182                   USED_REX (REX_W);
14183                   if (rex & REX_W)
14184                     *obufp++ = 'q';
14185                   else
14186                     {
14187                       if (sizeflag & DFLAG)
14188                         *obufp++ = intel_syntax ? 'd' : 'l';
14189                       else
14190                         *obufp++ = 'w';
14191                       used_prefixes |= (prefixes & PREFIX_DATA);
14192                     }
14193                 }
14194             }
14195           break;
14196         case 'U':
14197           if (intel_syntax)
14198             break;
14199           if (address_mode == mode_64bit
14200               && ((sizeflag & DFLAG) || (rex & REX_W)))
14201             {
14202               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14203                 *obufp++ = 'q';
14204               break;
14205             }
14206           /* Fall through.  */
14207           goto case_Q;
14208         case 'Q':
14209           if (l == 0 && len == 1)
14210             {
14211 case_Q:
14212               if (intel_syntax && !alt)
14213                 break;
14214               USED_REX (REX_W);
14215               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14216                 {
14217                   if (rex & REX_W)
14218                     *obufp++ = 'q';
14219                   else
14220                     {
14221                       if (sizeflag & DFLAG)
14222                         *obufp++ = intel_syntax ? 'd' : 'l';
14223                       else
14224                         *obufp++ = 'w';
14225                       used_prefixes |= (prefixes & PREFIX_DATA);
14226                     }
14227                 }
14228             }
14229           else
14230             {
14231               if (l != 1 || len != 2 || last[0] != 'L')
14232                 {
14233                   SAVE_LAST (*p);
14234                   break;
14235                 }
14236               if (intel_syntax
14237                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14238                 break;
14239               if ((rex & REX_W))
14240                 {
14241                   USED_REX (REX_W);
14242                   *obufp++ = 'q';
14243                 }
14244               else
14245                 *obufp++ = 'l';
14246             }
14247           break;
14248         case 'R':
14249           USED_REX (REX_W);
14250           if (rex & REX_W)
14251             *obufp++ = 'q';
14252           else if (sizeflag & DFLAG)
14253             {
14254               if (intel_syntax)
14255                   *obufp++ = 'd';
14256               else
14257                   *obufp++ = 'l';
14258             }
14259           else
14260             *obufp++ = 'w';
14261           if (intel_syntax && !p[1]
14262               && ((rex & REX_W) || (sizeflag & DFLAG)))
14263             *obufp++ = 'e';
14264           if (!(rex & REX_W))
14265             used_prefixes |= (prefixes & PREFIX_DATA);
14266           break;
14267         case 'V':
14268           if (l == 0 && len == 1)
14269             {
14270               if (intel_syntax)
14271                 break;
14272               if (address_mode == mode_64bit
14273                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14274                 {
14275                   if (sizeflag & SUFFIX_ALWAYS)
14276                     *obufp++ = 'q';
14277                   break;
14278                 }
14279             }
14280           else
14281             {
14282               if (l != 1
14283                   || len != 2
14284                   || last[0] != 'L')
14285                 {
14286                   SAVE_LAST (*p);
14287                   break;
14288                 }
14289
14290               if (rex & REX_W)
14291                 {
14292                   *obufp++ = 'a';
14293                   *obufp++ = 'b';
14294                   *obufp++ = 's';
14295                 }
14296             }
14297           /* Fall through.  */
14298           goto case_S;
14299         case 'S':
14300           if (l == 0 && len == 1)
14301             {
14302 case_S:
14303               if (intel_syntax)
14304                 break;
14305               if (sizeflag & SUFFIX_ALWAYS)
14306                 {
14307                   if (rex & REX_W)
14308                     *obufp++ = 'q';
14309                   else
14310                     {
14311                       if (sizeflag & DFLAG)
14312                         *obufp++ = 'l';
14313                       else
14314                         *obufp++ = 'w';
14315                       used_prefixes |= (prefixes & PREFIX_DATA);
14316                     }
14317                 }
14318             }
14319           else
14320             {
14321               if (l != 1
14322                   || len != 2
14323                   || last[0] != 'L')
14324                 {
14325                   SAVE_LAST (*p);
14326                   break;
14327                 }
14328
14329               if (address_mode == mode_64bit
14330                   && !(prefixes & PREFIX_ADDR))
14331                 {
14332                   *obufp++ = 'a';
14333                   *obufp++ = 'b';
14334                   *obufp++ = 's';
14335                 }
14336
14337               goto case_S;
14338             }
14339           break;
14340         case 'X':
14341           if (l != 0 || len != 1)
14342             {
14343               SAVE_LAST (*p);
14344               break;
14345             }
14346           if (need_vex && vex.prefix)
14347             {
14348               if (vex.prefix == DATA_PREFIX_OPCODE)
14349                 *obufp++ = 'd';
14350               else
14351                 *obufp++ = 's';
14352             }
14353           else
14354             {
14355               if (prefixes & PREFIX_DATA)
14356                 *obufp++ = 'd';
14357               else
14358                 *obufp++ = 's';
14359               used_prefixes |= (prefixes & PREFIX_DATA);
14360             }
14361           break;
14362         case 'Y':
14363           if (l == 0 && len == 1)
14364             {
14365               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14366                 break;
14367               if (rex & REX_W)
14368                 {
14369                   USED_REX (REX_W);
14370                   *obufp++ = 'q';
14371                 }
14372               break;
14373             }
14374           else
14375             {
14376               if (l != 1 || len != 2 || last[0] != 'X')
14377                 {
14378                   SAVE_LAST (*p);
14379                   break;
14380                 }
14381               if (!need_vex)
14382                 abort ();
14383               if (intel_syntax
14384                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14385                 break;
14386               switch (vex.length)
14387                 {
14388                 case 128:
14389                   *obufp++ = 'x';
14390                   break;
14391                 case 256:
14392                   *obufp++ = 'y';
14393                   break;
14394                 case 512:
14395                   if (!vex.evex)
14396                 default:
14397                     abort ();
14398                 }
14399             }
14400           break;
14401         case 'W':
14402           if (l == 0 && len == 1)
14403             {
14404               /* operand size flag for cwtl, cbtw */
14405               USED_REX (REX_W);
14406               if (rex & REX_W)
14407                 {
14408                   if (intel_syntax)
14409                     *obufp++ = 'd';
14410                   else
14411                     *obufp++ = 'l';
14412                 }
14413               else if (sizeflag & DFLAG)
14414                 *obufp++ = 'w';
14415               else
14416                 *obufp++ = 'b';
14417               if (!(rex & REX_W))
14418                 used_prefixes |= (prefixes & PREFIX_DATA);
14419             }
14420           else
14421             {
14422               if (l != 1
14423                   || len != 2
14424                   || (last[0] != 'X'
14425                       && last[0] != 'L'))
14426                 {
14427                   SAVE_LAST (*p);
14428                   break;
14429                 }
14430               if (!need_vex)
14431                 abort ();
14432               if (last[0] == 'X')
14433                 *obufp++ = vex.w ? 'd': 's';
14434               else
14435                 *obufp++ = vex.w ? 'q': 'd';
14436             }
14437           break;
14438         case '^':
14439           if (intel_syntax)
14440             break;
14441           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14442             {
14443               if (sizeflag & DFLAG)
14444                 *obufp++ = 'l';
14445               else
14446                 *obufp++ = 'w';
14447               used_prefixes |= (prefixes & PREFIX_DATA);
14448             }
14449           break;
14450         case '@':
14451           if (intel_syntax)
14452             break;
14453           if (address_mode == mode_64bit
14454               && (isa64 == intel64
14455                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14456               *obufp++ = 'q';
14457           else if ((prefixes & PREFIX_DATA))
14458             {
14459               if (!(sizeflag & DFLAG))
14460                 *obufp++ = 'w';
14461               used_prefixes |= (prefixes & PREFIX_DATA);
14462             }
14463           break;
14464         }
14465       alt = 0;
14466     }
14467   *obufp = 0;
14468   mnemonicendp = obufp;
14469   return 0;
14470 }
14471
14472 static void
14473 oappend (const char *s)
14474 {
14475   obufp = stpcpy (obufp, s);
14476 }
14477
14478 static void
14479 append_seg (void)
14480 {
14481   /* Only print the active segment register.  */
14482   if (!active_seg_prefix)
14483     return;
14484
14485   used_prefixes |= active_seg_prefix;
14486   switch (active_seg_prefix)
14487     {
14488     case PREFIX_CS:
14489       oappend_maybe_intel ("%cs:");
14490       break;
14491     case PREFIX_DS:
14492       oappend_maybe_intel ("%ds:");
14493       break;
14494     case PREFIX_SS:
14495       oappend_maybe_intel ("%ss:");
14496       break;
14497     case PREFIX_ES:
14498       oappend_maybe_intel ("%es:");
14499       break;
14500     case PREFIX_FS:
14501       oappend_maybe_intel ("%fs:");
14502       break;
14503     case PREFIX_GS:
14504       oappend_maybe_intel ("%gs:");
14505       break;
14506     default:
14507       break;
14508     }
14509 }
14510
14511 static void
14512 OP_indirE (int bytemode, int sizeflag)
14513 {
14514   if (!intel_syntax)
14515     oappend ("*");
14516   OP_E (bytemode, sizeflag);
14517 }
14518
14519 static void
14520 print_operand_value (char *buf, int hex, bfd_vma disp)
14521 {
14522   if (address_mode == mode_64bit)
14523     {
14524       if (hex)
14525         {
14526           char tmp[30];
14527           int i;
14528           buf[0] = '0';
14529           buf[1] = 'x';
14530           sprintf_vma (tmp, disp);
14531           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14532           strcpy (buf + 2, tmp + i);
14533         }
14534       else
14535         {
14536           bfd_signed_vma v = disp;
14537           char tmp[30];
14538           int i;
14539           if (v < 0)
14540             {
14541               *(buf++) = '-';
14542               v = -disp;
14543               /* Check for possible overflow on 0x8000000000000000.  */
14544               if (v < 0)
14545                 {
14546                   strcpy (buf, "9223372036854775808");
14547                   return;
14548                 }
14549             }
14550           if (!v)
14551             {
14552               strcpy (buf, "0");
14553               return;
14554             }
14555
14556           i = 0;
14557           tmp[29] = 0;
14558           while (v)
14559             {
14560               tmp[28 - i] = (v % 10) + '0';
14561               v /= 10;
14562               i++;
14563             }
14564           strcpy (buf, tmp + 29 - i);
14565         }
14566     }
14567   else
14568     {
14569       if (hex)
14570         sprintf (buf, "0x%x", (unsigned int) disp);
14571       else
14572         sprintf (buf, "%d", (int) disp);
14573     }
14574 }
14575
14576 /* Put DISP in BUF as signed hex number.  */
14577
14578 static void
14579 print_displacement (char *buf, bfd_vma disp)
14580 {
14581   bfd_signed_vma val = disp;
14582   char tmp[30];
14583   int i, j = 0;
14584
14585   if (val < 0)
14586     {
14587       buf[j++] = '-';
14588       val = -disp;
14589
14590       /* Check for possible overflow.  */
14591       if (val < 0)
14592         {
14593           switch (address_mode)
14594             {
14595             case mode_64bit:
14596               strcpy (buf + j, "0x8000000000000000");
14597               break;
14598             case mode_32bit:
14599               strcpy (buf + j, "0x80000000");
14600               break;
14601             case mode_16bit:
14602               strcpy (buf + j, "0x8000");
14603               break;
14604             }
14605           return;
14606         }
14607     }
14608
14609   buf[j++] = '0';
14610   buf[j++] = 'x';
14611
14612   sprintf_vma (tmp, (bfd_vma) val);
14613   for (i = 0; tmp[i] == '0'; i++)
14614     continue;
14615   if (tmp[i] == '\0')
14616     i--;
14617   strcpy (buf + j, tmp + i);
14618 }
14619
14620 static void
14621 intel_operand_size (int bytemode, int sizeflag)
14622 {
14623   if (vex.evex
14624       && vex.b
14625       && (bytemode == x_mode
14626           || bytemode == evex_half_bcst_xmmq_mode))
14627     {
14628       if (vex.w)
14629         oappend ("QWORD PTR ");
14630       else
14631         oappend ("DWORD PTR ");
14632       return;
14633     }
14634   switch (bytemode)
14635     {
14636     case b_mode:
14637     case b_swap_mode:
14638     case dqb_mode:
14639     case db_mode:
14640       oappend ("BYTE PTR ");
14641       break;
14642     case w_mode:
14643     case dw_mode:
14644     case dqw_mode:
14645       oappend ("WORD PTR ");
14646       break;
14647     case indir_v_mode:
14648       if (address_mode == mode_64bit && isa64 == intel64)
14649         {
14650           oappend ("QWORD PTR ");
14651           break;
14652         }
14653       /* Fall through.  */
14654     case stack_v_mode:
14655       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14656         {
14657           oappend ("QWORD PTR ");
14658           break;
14659         }
14660       /* Fall through.  */
14661     case v_mode:
14662     case v_swap_mode:
14663     case dq_mode:
14664       USED_REX (REX_W);
14665       if (rex & REX_W)
14666         oappend ("QWORD PTR ");
14667       else
14668         {
14669           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14670             oappend ("DWORD PTR ");
14671           else
14672             oappend ("WORD PTR ");
14673           used_prefixes |= (prefixes & PREFIX_DATA);
14674         }
14675       break;
14676     case z_mode:
14677       if ((rex & REX_W) || (sizeflag & DFLAG))
14678         *obufp++ = 'D';
14679       oappend ("WORD PTR ");
14680       if (!(rex & REX_W))
14681         used_prefixes |= (prefixes & PREFIX_DATA);
14682       break;
14683     case a_mode:
14684       if (sizeflag & DFLAG)
14685         oappend ("QWORD PTR ");
14686       else
14687         oappend ("DWORD PTR ");
14688       used_prefixes |= (prefixes & PREFIX_DATA);
14689       break;
14690     case d_mode:
14691     case d_scalar_mode:
14692     case d_scalar_swap_mode:
14693     case d_swap_mode:
14694     case dqd_mode:
14695       oappend ("DWORD PTR ");
14696       break;
14697     case q_mode:
14698     case q_scalar_mode:
14699     case q_scalar_swap_mode:
14700     case q_swap_mode:
14701       oappend ("QWORD PTR ");
14702       break;
14703     case m_mode:
14704       if (address_mode == mode_64bit)
14705         oappend ("QWORD PTR ");
14706       else
14707         oappend ("DWORD PTR ");
14708       break;
14709     case f_mode:
14710       if (sizeflag & DFLAG)
14711         oappend ("FWORD PTR ");
14712       else
14713         oappend ("DWORD PTR ");
14714       used_prefixes |= (prefixes & PREFIX_DATA);
14715       break;
14716     case t_mode:
14717       oappend ("TBYTE PTR ");
14718       break;
14719     case x_mode:
14720     case x_swap_mode:
14721     case evex_x_gscat_mode:
14722     case evex_x_nobcst_mode:
14723       if (need_vex)
14724         {
14725           switch (vex.length)
14726             {
14727             case 128:
14728               oappend ("XMMWORD PTR ");
14729               break;
14730             case 256:
14731               oappend ("YMMWORD PTR ");
14732               break;
14733             case 512:
14734               oappend ("ZMMWORD PTR ");
14735               break;
14736             default:
14737               abort ();
14738             }
14739         }
14740       else
14741         oappend ("XMMWORD PTR ");
14742       break;
14743     case xmm_mode:
14744       oappend ("XMMWORD PTR ");
14745       break;
14746     case ymm_mode:
14747       oappend ("YMMWORD PTR ");
14748       break;
14749     case xmmq_mode:
14750     case evex_half_bcst_xmmq_mode:
14751       if (!need_vex)
14752         abort ();
14753
14754       switch (vex.length)
14755         {
14756         case 128:
14757           oappend ("QWORD PTR ");
14758           break;
14759         case 256:
14760           oappend ("XMMWORD PTR ");
14761           break;
14762         case 512:
14763           oappend ("YMMWORD PTR ");
14764           break;
14765         default:
14766           abort ();
14767         }
14768       break;
14769     case xmm_mb_mode:
14770       if (!need_vex)
14771         abort ();
14772
14773       switch (vex.length)
14774         {
14775         case 128:
14776         case 256:
14777         case 512:
14778           oappend ("BYTE PTR ");
14779           break;
14780         default:
14781           abort ();
14782         }
14783       break;
14784     case xmm_mw_mode:
14785       if (!need_vex)
14786         abort ();
14787
14788       switch (vex.length)
14789         {
14790         case 128:
14791         case 256:
14792         case 512:
14793           oappend ("WORD PTR ");
14794           break;
14795         default:
14796           abort ();
14797         }
14798       break;
14799     case xmm_md_mode:
14800       if (!need_vex)
14801         abort ();
14802
14803       switch (vex.length)
14804         {
14805         case 128:
14806         case 256:
14807         case 512:
14808           oappend ("DWORD PTR ");
14809           break;
14810         default:
14811           abort ();
14812         }
14813       break;
14814     case xmm_mq_mode:
14815       if (!need_vex)
14816         abort ();
14817
14818       switch (vex.length)
14819         {
14820         case 128:
14821         case 256:
14822         case 512:
14823           oappend ("QWORD PTR ");
14824           break;
14825         default:
14826           abort ();
14827         }
14828       break;
14829     case xmmdw_mode:
14830       if (!need_vex)
14831         abort ();
14832
14833       switch (vex.length)
14834         {
14835         case 128:
14836           oappend ("WORD PTR ");
14837           break;
14838         case 256:
14839           oappend ("DWORD PTR ");
14840           break;
14841         case 512:
14842           oappend ("QWORD PTR ");
14843           break;
14844         default:
14845           abort ();
14846         }
14847       break;
14848     case xmmqd_mode:
14849       if (!need_vex)
14850         abort ();
14851
14852       switch (vex.length)
14853         {
14854         case 128:
14855           oappend ("DWORD PTR ");
14856           break;
14857         case 256:
14858           oappend ("QWORD PTR ");
14859           break;
14860         case 512:
14861           oappend ("XMMWORD PTR ");
14862           break;
14863         default:
14864           abort ();
14865         }
14866       break;
14867     case ymmq_mode:
14868       if (!need_vex)
14869         abort ();
14870
14871       switch (vex.length)
14872         {
14873         case 128:
14874           oappend ("QWORD PTR ");
14875           break;
14876         case 256:
14877           oappend ("YMMWORD PTR ");
14878           break;
14879         case 512:
14880           oappend ("ZMMWORD PTR ");
14881           break;
14882         default:
14883           abort ();
14884         }
14885       break;
14886     case ymmxmm_mode:
14887       if (!need_vex)
14888         abort ();
14889
14890       switch (vex.length)
14891         {
14892         case 128:
14893         case 256:
14894           oappend ("XMMWORD PTR ");
14895           break;
14896         default:
14897           abort ();
14898         }
14899       break;
14900     case o_mode:
14901       oappend ("OWORD PTR ");
14902       break;
14903     case xmm_mdq_mode:
14904     case vex_w_dq_mode:
14905     case vex_scalar_w_dq_mode:
14906       if (!need_vex)
14907         abort ();
14908
14909       if (vex.w)
14910         oappend ("QWORD PTR ");
14911       else
14912         oappend ("DWORD PTR ");
14913       break;
14914     case vex_vsib_d_w_dq_mode:
14915     case vex_vsib_q_w_dq_mode:
14916       if (!need_vex)
14917         abort ();
14918
14919       if (!vex.evex)
14920         {
14921           if (vex.w)
14922             oappend ("QWORD PTR ");
14923           else
14924             oappend ("DWORD PTR ");
14925         }
14926       else
14927         {
14928           switch (vex.length)
14929             {
14930             case 128:
14931               oappend ("XMMWORD PTR ");
14932               break;
14933             case 256:
14934               oappend ("YMMWORD PTR ");
14935               break;
14936             case 512:
14937               oappend ("ZMMWORD PTR ");
14938               break;
14939             default:
14940               abort ();
14941             }
14942         }
14943       break;
14944     case vex_vsib_q_w_d_mode:
14945     case vex_vsib_d_w_d_mode:
14946       if (!need_vex || !vex.evex)
14947         abort ();
14948
14949       switch (vex.length)
14950         {
14951         case 128:
14952           oappend ("QWORD PTR ");
14953           break;
14954         case 256:
14955           oappend ("XMMWORD PTR ");
14956           break;
14957         case 512:
14958           oappend ("YMMWORD PTR ");
14959           break;
14960         default:
14961           abort ();
14962         }
14963
14964       break;
14965     case mask_bd_mode:
14966       if (!need_vex || vex.length != 128)
14967         abort ();
14968       if (vex.w)
14969         oappend ("DWORD PTR ");
14970       else
14971         oappend ("BYTE PTR ");
14972       break;
14973     case mask_mode:
14974       if (!need_vex)
14975         abort ();
14976       if (vex.w)
14977         oappend ("QWORD PTR ");
14978       else
14979         oappend ("WORD PTR ");
14980       break;
14981     case v_bnd_mode:
14982     default:
14983       break;
14984     }
14985 }
14986
14987 static void
14988 OP_E_register (int bytemode, int sizeflag)
14989 {
14990   int reg = modrm.rm;
14991   const char **names;
14992
14993   USED_REX (REX_B);
14994   if ((rex & REX_B))
14995     reg += 8;
14996
14997   if ((sizeflag & SUFFIX_ALWAYS)
14998       && (bytemode == b_swap_mode
14999           || bytemode == v_swap_mode))
15000     swap_operand ();
15001
15002   switch (bytemode)
15003     {
15004     case b_mode:
15005     case b_swap_mode:
15006       USED_REX (0);
15007       if (rex)
15008         names = names8rex;
15009       else
15010         names = names8;
15011       break;
15012     case w_mode:
15013       names = names16;
15014       break;
15015     case d_mode:
15016     case dw_mode:
15017     case db_mode:
15018       names = names32;
15019       break;
15020     case q_mode:
15021       names = names64;
15022       break;
15023     case m_mode:
15024     case v_bnd_mode:
15025       names = address_mode == mode_64bit ? names64 : names32;
15026       break;
15027     case bnd_mode:
15028       names = names_bnd;
15029       break;
15030     case indir_v_mode:
15031       if (address_mode == mode_64bit && isa64 == intel64)
15032         {
15033           names = names64;
15034           break;
15035         }
15036       /* Fall through.  */
15037     case stack_v_mode:
15038       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15039         {
15040           names = names64;
15041           break;
15042         }
15043       bytemode = v_mode;
15044       /* Fall through.  */
15045     case v_mode:
15046     case v_swap_mode:
15047     case dq_mode:
15048     case dqb_mode:
15049     case dqd_mode:
15050     case dqw_mode:
15051       USED_REX (REX_W);
15052       if (rex & REX_W)
15053         names = names64;
15054       else
15055         {
15056           if ((sizeflag & DFLAG)
15057               || (bytemode != v_mode
15058                   && bytemode != v_swap_mode))
15059             names = names32;
15060           else
15061             names = names16;
15062           used_prefixes |= (prefixes & PREFIX_DATA);
15063         }
15064       break;
15065     case mask_bd_mode:
15066     case mask_mode:
15067       if (reg > 0x7)
15068         {
15069           oappend ("(bad)");
15070           return;
15071         }
15072       names = names_mask;
15073       break;
15074     case 0:
15075       return;
15076     default:
15077       oappend (INTERNAL_DISASSEMBLER_ERROR);
15078       return;
15079     }
15080   oappend (names[reg]);
15081 }
15082
15083 static void
15084 OP_E_memory (int bytemode, int sizeflag)
15085 {
15086   bfd_vma disp = 0;
15087   int add = (rex & REX_B) ? 8 : 0;
15088   int riprel = 0;
15089   int shift;
15090
15091   if (vex.evex)
15092     {
15093       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15094       if (vex.b
15095           && bytemode != x_mode
15096           && bytemode != xmmq_mode
15097           && bytemode != evex_half_bcst_xmmq_mode)
15098         {
15099           BadOp ();
15100           return;
15101         }
15102       switch (bytemode)
15103         {
15104         case dqw_mode:
15105         case dw_mode:
15106           shift = 1;
15107           break;
15108         case dqb_mode:
15109         case db_mode:
15110           shift = 0;
15111           break;
15112         case vex_vsib_d_w_dq_mode:
15113         case vex_vsib_d_w_d_mode:
15114         case vex_vsib_q_w_dq_mode:
15115         case vex_vsib_q_w_d_mode:
15116         case evex_x_gscat_mode:
15117         case xmm_mdq_mode:
15118           shift = vex.w ? 3 : 2;
15119           break;
15120         case x_mode:
15121         case evex_half_bcst_xmmq_mode:
15122         case xmmq_mode:
15123           if (vex.b)
15124             {
15125               shift = vex.w ? 3 : 2;
15126               break;
15127             }
15128           /* Fall through.  */
15129         case xmmqd_mode:
15130         case xmmdw_mode:
15131         case ymmq_mode:
15132         case evex_x_nobcst_mode:
15133         case x_swap_mode:
15134           switch (vex.length)
15135             {
15136             case 128:
15137               shift = 4;
15138               break;
15139             case 256:
15140               shift = 5;
15141               break;
15142             case 512:
15143               shift = 6;
15144               break;
15145             default:
15146               abort ();
15147             }
15148           break;
15149         case ymm_mode:
15150           shift = 5;
15151           break;
15152         case xmm_mode:
15153           shift = 4;
15154           break;
15155         case xmm_mq_mode:
15156         case q_mode:
15157         case q_scalar_mode:
15158         case q_swap_mode:
15159         case q_scalar_swap_mode:
15160           shift = 3;
15161           break;
15162         case dqd_mode:
15163         case xmm_md_mode:
15164         case d_mode:
15165         case d_scalar_mode:
15166         case d_swap_mode:
15167         case d_scalar_swap_mode:
15168           shift = 2;
15169           break;
15170         case xmm_mw_mode:
15171           shift = 1;
15172           break;
15173         case xmm_mb_mode:
15174           shift = 0;
15175           break;
15176         default:
15177           abort ();
15178         }
15179       /* Make necessary corrections to shift for modes that need it.
15180          For these modes we currently have shift 4, 5 or 6 depending on
15181          vex.length (it corresponds to xmmword, ymmword or zmmword
15182          operand).  We might want to make it 3, 4 or 5 (e.g. for
15183          xmmq_mode).  In case of broadcast enabled the corrections
15184          aren't needed, as element size is always 32 or 64 bits.  */
15185       if (!vex.b
15186           && (bytemode == xmmq_mode
15187               || bytemode == evex_half_bcst_xmmq_mode))
15188         shift -= 1;
15189       else if (bytemode == xmmqd_mode)
15190         shift -= 2;
15191       else if (bytemode == xmmdw_mode)
15192         shift -= 3;
15193       else if (bytemode == ymmq_mode && vex.length == 128)
15194         shift -= 1;
15195     }
15196   else
15197     shift = 0;
15198
15199   USED_REX (REX_B);
15200   if (intel_syntax)
15201     intel_operand_size (bytemode, sizeflag);
15202   append_seg ();
15203
15204   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15205     {
15206       /* 32/64 bit address mode */
15207       int havedisp;
15208       int havesib;
15209       int havebase;
15210       int haveindex;
15211       int needindex;
15212       int base, rbase;
15213       int vindex = 0;
15214       int scale = 0;
15215       int addr32flag = !((sizeflag & AFLAG)
15216                          || bytemode == v_bnd_mode
15217                          || bytemode == bnd_mode);
15218       const char **indexes64 = names64;
15219       const char **indexes32 = names32;
15220
15221       havesib = 0;
15222       havebase = 1;
15223       haveindex = 0;
15224       base = modrm.rm;
15225
15226       if (base == 4)
15227         {
15228           havesib = 1;
15229           vindex = sib.index;
15230           USED_REX (REX_X);
15231           if (rex & REX_X)
15232             vindex += 8;
15233           switch (bytemode)
15234             {
15235             case vex_vsib_d_w_dq_mode:
15236             case vex_vsib_d_w_d_mode:
15237             case vex_vsib_q_w_dq_mode:
15238             case vex_vsib_q_w_d_mode:
15239               if (!need_vex)
15240                 abort ();
15241               if (vex.evex)
15242                 {
15243                   if (!vex.v)
15244                     vindex += 16;
15245                 }
15246
15247               haveindex = 1;
15248               switch (vex.length)
15249                 {
15250                 case 128:
15251                   indexes64 = indexes32 = names_xmm;
15252                   break;
15253                 case 256:
15254                   if (!vex.w
15255                       || bytemode == vex_vsib_q_w_dq_mode
15256                       || bytemode == vex_vsib_q_w_d_mode)
15257                     indexes64 = indexes32 = names_ymm;
15258                   else
15259                     indexes64 = indexes32 = names_xmm;
15260                   break;
15261                 case 512:
15262                   if (!vex.w
15263                       || bytemode == vex_vsib_q_w_dq_mode
15264                       || bytemode == vex_vsib_q_w_d_mode)
15265                     indexes64 = indexes32 = names_zmm;
15266                   else
15267                     indexes64 = indexes32 = names_ymm;
15268                   break;
15269                 default:
15270                   abort ();
15271                 }
15272               break;
15273             default:
15274               haveindex = vindex != 4;
15275               break;
15276             }
15277           scale = sib.scale;
15278           base = sib.base;
15279           codep++;
15280         }
15281       rbase = base + add;
15282
15283       switch (modrm.mod)
15284         {
15285         case 0:
15286           if (base == 5)
15287             {
15288               havebase = 0;
15289               if (address_mode == mode_64bit && !havesib)
15290                 riprel = 1;
15291               disp = get32s ();
15292             }
15293           break;
15294         case 1:
15295           FETCH_DATA (the_info, codep + 1);
15296           disp = *codep++;
15297           if ((disp & 0x80) != 0)
15298             disp -= 0x100;
15299           if (vex.evex && shift > 0)
15300             disp <<= shift;
15301           break;
15302         case 2:
15303           disp = get32s ();
15304           break;
15305         }
15306
15307       /* In 32bit mode, we need index register to tell [offset] from
15308          [eiz*1 + offset].  */
15309       needindex = (havesib
15310                    && !havebase
15311                    && !haveindex
15312                    && address_mode == mode_32bit);
15313       havedisp = (havebase
15314                   || needindex
15315                   || (havesib && (haveindex || scale != 0)));
15316
15317       if (!intel_syntax)
15318         if (modrm.mod != 0 || base == 5)
15319           {
15320             if (havedisp || riprel)
15321               print_displacement (scratchbuf, disp);
15322             else
15323               print_operand_value (scratchbuf, 1, disp);
15324             oappend (scratchbuf);
15325             if (riprel)
15326               {
15327                 set_op (disp, 1);
15328                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15329               }
15330           }
15331
15332       if ((havebase || haveindex || riprel)
15333           && (bytemode != v_bnd_mode)
15334           && (bytemode != bnd_mode))
15335         used_prefixes |= PREFIX_ADDR;
15336
15337       if (havedisp || (intel_syntax && riprel))
15338         {
15339           *obufp++ = open_char;
15340           if (intel_syntax && riprel)
15341             {
15342               set_op (disp, 1);
15343               oappend (!addr32flag ? "rip" : "eip");
15344             }
15345           *obufp = '\0';
15346           if (havebase)
15347             oappend (address_mode == mode_64bit && !addr32flag
15348                      ? names64[rbase] : names32[rbase]);
15349           if (havesib)
15350             {
15351               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15352                  print index to tell base + index from base.  */
15353               if (scale != 0
15354                   || needindex
15355                   || haveindex
15356                   || (havebase && base != ESP_REG_NUM))
15357                 {
15358                   if (!intel_syntax || havebase)
15359                     {
15360                       *obufp++ = separator_char;
15361                       *obufp = '\0';
15362                     }
15363                   if (haveindex)
15364                     oappend (address_mode == mode_64bit && !addr32flag
15365                              ? indexes64[vindex] : indexes32[vindex]);
15366                   else
15367                     oappend (address_mode == mode_64bit && !addr32flag
15368                              ? index64 : index32);
15369
15370                   *obufp++ = scale_char;
15371                   *obufp = '\0';
15372                   sprintf (scratchbuf, "%d", 1 << scale);
15373                   oappend (scratchbuf);
15374                 }
15375             }
15376           if (intel_syntax
15377               && (disp || modrm.mod != 0 || base == 5))
15378             {
15379               if (!havedisp || (bfd_signed_vma) disp >= 0)
15380                 {
15381                   *obufp++ = '+';
15382                   *obufp = '\0';
15383                 }
15384               else if (modrm.mod != 1 && disp != -disp)
15385                 {
15386                   *obufp++ = '-';
15387                   *obufp = '\0';
15388                   disp = - (bfd_signed_vma) disp;
15389                 }
15390
15391               if (havedisp)
15392                 print_displacement (scratchbuf, disp);
15393               else
15394                 print_operand_value (scratchbuf, 1, disp);
15395               oappend (scratchbuf);
15396             }
15397
15398           *obufp++ = close_char;
15399           *obufp = '\0';
15400         }
15401       else if (intel_syntax)
15402         {
15403           if (modrm.mod != 0 || base == 5)
15404             {
15405               if (!active_seg_prefix)
15406                 {
15407                   oappend (names_seg[ds_reg - es_reg]);
15408                   oappend (":");
15409                 }
15410               print_operand_value (scratchbuf, 1, disp);
15411               oappend (scratchbuf);
15412             }
15413         }
15414     }
15415   else
15416     {
15417       /* 16 bit address mode */
15418       used_prefixes |= prefixes & PREFIX_ADDR;
15419       switch (modrm.mod)
15420         {
15421         case 0:
15422           if (modrm.rm == 6)
15423             {
15424               disp = get16 ();
15425               if ((disp & 0x8000) != 0)
15426                 disp -= 0x10000;
15427             }
15428           break;
15429         case 1:
15430           FETCH_DATA (the_info, codep + 1);
15431           disp = *codep++;
15432           if ((disp & 0x80) != 0)
15433             disp -= 0x100;
15434           break;
15435         case 2:
15436           disp = get16 ();
15437           if ((disp & 0x8000) != 0)
15438             disp -= 0x10000;
15439           break;
15440         }
15441
15442       if (!intel_syntax)
15443         if (modrm.mod != 0 || modrm.rm == 6)
15444           {
15445             print_displacement (scratchbuf, disp);
15446             oappend (scratchbuf);
15447           }
15448
15449       if (modrm.mod != 0 || modrm.rm != 6)
15450         {
15451           *obufp++ = open_char;
15452           *obufp = '\0';
15453           oappend (index16[modrm.rm]);
15454           if (intel_syntax
15455               && (disp || modrm.mod != 0 || modrm.rm == 6))
15456             {
15457               if ((bfd_signed_vma) disp >= 0)
15458                 {
15459                   *obufp++ = '+';
15460                   *obufp = '\0';
15461                 }
15462               else if (modrm.mod != 1)
15463                 {
15464                   *obufp++ = '-';
15465                   *obufp = '\0';
15466                   disp = - (bfd_signed_vma) disp;
15467                 }
15468
15469               print_displacement (scratchbuf, disp);
15470               oappend (scratchbuf);
15471             }
15472
15473           *obufp++ = close_char;
15474           *obufp = '\0';
15475         }
15476       else if (intel_syntax)
15477         {
15478           if (!active_seg_prefix)
15479             {
15480               oappend (names_seg[ds_reg - es_reg]);
15481               oappend (":");
15482             }
15483           print_operand_value (scratchbuf, 1, disp & 0xffff);
15484           oappend (scratchbuf);
15485         }
15486     }
15487   if (vex.evex && vex.b
15488       && (bytemode == x_mode
15489           || bytemode == xmmq_mode
15490           || bytemode == evex_half_bcst_xmmq_mode))
15491     {
15492       if (vex.w
15493           || bytemode == xmmq_mode
15494           || bytemode == evex_half_bcst_xmmq_mode)
15495         {
15496           switch (vex.length)
15497             {
15498             case 128:
15499               oappend ("{1to2}");
15500               break;
15501             case 256:
15502               oappend ("{1to4}");
15503               break;
15504             case 512:
15505               oappend ("{1to8}");
15506               break;
15507             default:
15508               abort ();
15509             }
15510         }
15511       else
15512         {
15513           switch (vex.length)
15514             {
15515             case 128:
15516               oappend ("{1to4}");
15517               break;
15518             case 256:
15519               oappend ("{1to8}");
15520               break;
15521             case 512:
15522               oappend ("{1to16}");
15523               break;
15524             default:
15525               abort ();
15526             }
15527         }
15528     }
15529 }
15530
15531 static void
15532 OP_E (int bytemode, int sizeflag)
15533 {
15534   /* Skip mod/rm byte.  */
15535   MODRM_CHECK;
15536   codep++;
15537
15538   if (modrm.mod == 3)
15539     OP_E_register (bytemode, sizeflag);
15540   else
15541     OP_E_memory (bytemode, sizeflag);
15542 }
15543
15544 static void
15545 OP_G (int bytemode, int sizeflag)
15546 {
15547   int add = 0;
15548   USED_REX (REX_R);
15549   if (rex & REX_R)
15550     add += 8;
15551   switch (bytemode)
15552     {
15553     case b_mode:
15554       USED_REX (0);
15555       if (rex)
15556         oappend (names8rex[modrm.reg + add]);
15557       else
15558         oappend (names8[modrm.reg + add]);
15559       break;
15560     case w_mode:
15561       oappend (names16[modrm.reg + add]);
15562       break;
15563     case d_mode:
15564     case db_mode:
15565     case dw_mode:
15566       oappend (names32[modrm.reg + add]);
15567       break;
15568     case q_mode:
15569       oappend (names64[modrm.reg + add]);
15570       break;
15571     case bnd_mode:
15572       oappend (names_bnd[modrm.reg]);
15573       break;
15574     case v_mode:
15575     case dq_mode:
15576     case dqb_mode:
15577     case dqd_mode:
15578     case dqw_mode:
15579       USED_REX (REX_W);
15580       if (rex & REX_W)
15581         oappend (names64[modrm.reg + add]);
15582       else
15583         {
15584           if ((sizeflag & DFLAG) || bytemode != v_mode)
15585             oappend (names32[modrm.reg + add]);
15586           else
15587             oappend (names16[modrm.reg + add]);
15588           used_prefixes |= (prefixes & PREFIX_DATA);
15589         }
15590       break;
15591     case m_mode:
15592       if (address_mode == mode_64bit)
15593         oappend (names64[modrm.reg + add]);
15594       else
15595         oappend (names32[modrm.reg + add]);
15596       break;
15597     case mask_bd_mode:
15598     case mask_mode:
15599       if ((modrm.reg + add) > 0x7)
15600         {
15601           oappend ("(bad)");
15602           return;
15603         }
15604       oappend (names_mask[modrm.reg + add]);
15605       break;
15606     default:
15607       oappend (INTERNAL_DISASSEMBLER_ERROR);
15608       break;
15609     }
15610 }
15611
15612 static bfd_vma
15613 get64 (void)
15614 {
15615   bfd_vma x;
15616 #ifdef BFD64
15617   unsigned int a;
15618   unsigned int b;
15619
15620   FETCH_DATA (the_info, codep + 8);
15621   a = *codep++ & 0xff;
15622   a |= (*codep++ & 0xff) << 8;
15623   a |= (*codep++ & 0xff) << 16;
15624   a |= (*codep++ & 0xffu) << 24;
15625   b = *codep++ & 0xff;
15626   b |= (*codep++ & 0xff) << 8;
15627   b |= (*codep++ & 0xff) << 16;
15628   b |= (*codep++ & 0xffu) << 24;
15629   x = a + ((bfd_vma) b << 32);
15630 #else
15631   abort ();
15632   x = 0;
15633 #endif
15634   return x;
15635 }
15636
15637 static bfd_signed_vma
15638 get32 (void)
15639 {
15640   bfd_signed_vma x = 0;
15641
15642   FETCH_DATA (the_info, codep + 4);
15643   x = *codep++ & (bfd_signed_vma) 0xff;
15644   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15645   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15646   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15647   return x;
15648 }
15649
15650 static bfd_signed_vma
15651 get32s (void)
15652 {
15653   bfd_signed_vma x = 0;
15654
15655   FETCH_DATA (the_info, codep + 4);
15656   x = *codep++ & (bfd_signed_vma) 0xff;
15657   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15658   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15659   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15660
15661   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15662
15663   return x;
15664 }
15665
15666 static int
15667 get16 (void)
15668 {
15669   int x = 0;
15670
15671   FETCH_DATA (the_info, codep + 2);
15672   x = *codep++ & 0xff;
15673   x |= (*codep++ & 0xff) << 8;
15674   return x;
15675 }
15676
15677 static void
15678 set_op (bfd_vma op, int riprel)
15679 {
15680   op_index[op_ad] = op_ad;
15681   if (address_mode == mode_64bit)
15682     {
15683       op_address[op_ad] = op;
15684       op_riprel[op_ad] = riprel;
15685     }
15686   else
15687     {
15688       /* Mask to get a 32-bit address.  */
15689       op_address[op_ad] = op & 0xffffffff;
15690       op_riprel[op_ad] = riprel & 0xffffffff;
15691     }
15692 }
15693
15694 static void
15695 OP_REG (int code, int sizeflag)
15696 {
15697   const char *s;
15698   int add;
15699
15700   switch (code)
15701     {
15702     case es_reg: case ss_reg: case cs_reg:
15703     case ds_reg: case fs_reg: case gs_reg:
15704       oappend (names_seg[code - es_reg]);
15705       return;
15706     }
15707
15708   USED_REX (REX_B);
15709   if (rex & REX_B)
15710     add = 8;
15711   else
15712     add = 0;
15713
15714   switch (code)
15715     {
15716     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15717     case sp_reg: case bp_reg: case si_reg: case di_reg:
15718       s = names16[code - ax_reg + add];
15719       break;
15720     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15721     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15722       USED_REX (0);
15723       if (rex)
15724         s = names8rex[code - al_reg + add];
15725       else
15726         s = names8[code - al_reg];
15727       break;
15728     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15729     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15730       if (address_mode == mode_64bit
15731           && ((sizeflag & DFLAG) || (rex & REX_W)))
15732         {
15733           s = names64[code - rAX_reg + add];
15734           break;
15735         }
15736       code += eAX_reg - rAX_reg;
15737       /* Fall through.  */
15738     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15739     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15740       USED_REX (REX_W);
15741       if (rex & REX_W)
15742         s = names64[code - eAX_reg + add];
15743       else
15744         {
15745           if (sizeflag & DFLAG)
15746             s = names32[code - eAX_reg + add];
15747           else
15748             s = names16[code - eAX_reg + add];
15749           used_prefixes |= (prefixes & PREFIX_DATA);
15750         }
15751       break;
15752     default:
15753       s = INTERNAL_DISASSEMBLER_ERROR;
15754       break;
15755     }
15756   oappend (s);
15757 }
15758
15759 static void
15760 OP_IMREG (int code, int sizeflag)
15761 {
15762   const char *s;
15763
15764   switch (code)
15765     {
15766     case indir_dx_reg:
15767       if (intel_syntax)
15768         s = "dx";
15769       else
15770         s = "(%dx)";
15771       break;
15772     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15773     case sp_reg: case bp_reg: case si_reg: case di_reg:
15774       s = names16[code - ax_reg];
15775       break;
15776     case es_reg: case ss_reg: case cs_reg:
15777     case ds_reg: case fs_reg: case gs_reg:
15778       s = names_seg[code - es_reg];
15779       break;
15780     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15781     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15782       USED_REX (0);
15783       if (rex)
15784         s = names8rex[code - al_reg];
15785       else
15786         s = names8[code - al_reg];
15787       break;
15788     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15789     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15790       USED_REX (REX_W);
15791       if (rex & REX_W)
15792         s = names64[code - eAX_reg];
15793       else
15794         {
15795           if (sizeflag & DFLAG)
15796             s = names32[code - eAX_reg];
15797           else
15798             s = names16[code - eAX_reg];
15799           used_prefixes |= (prefixes & PREFIX_DATA);
15800         }
15801       break;
15802     case z_mode_ax_reg:
15803       if ((rex & REX_W) || (sizeflag & DFLAG))
15804         s = *names32;
15805       else
15806         s = *names16;
15807       if (!(rex & REX_W))
15808         used_prefixes |= (prefixes & PREFIX_DATA);
15809       break;
15810     default:
15811       s = INTERNAL_DISASSEMBLER_ERROR;
15812       break;
15813     }
15814   oappend (s);
15815 }
15816
15817 static void
15818 OP_I (int bytemode, int sizeflag)
15819 {
15820   bfd_signed_vma op;
15821   bfd_signed_vma mask = -1;
15822
15823   switch (bytemode)
15824     {
15825     case b_mode:
15826       FETCH_DATA (the_info, codep + 1);
15827       op = *codep++;
15828       mask = 0xff;
15829       break;
15830     case q_mode:
15831       if (address_mode == mode_64bit)
15832         {
15833           op = get32s ();
15834           break;
15835         }
15836       /* Fall through.  */
15837     case v_mode:
15838       USED_REX (REX_W);
15839       if (rex & REX_W)
15840         op = get32s ();
15841       else
15842         {
15843           if (sizeflag & DFLAG)
15844             {
15845               op = get32 ();
15846               mask = 0xffffffff;
15847             }
15848           else
15849             {
15850               op = get16 ();
15851               mask = 0xfffff;
15852             }
15853           used_prefixes |= (prefixes & PREFIX_DATA);
15854         }
15855       break;
15856     case w_mode:
15857       mask = 0xfffff;
15858       op = get16 ();
15859       break;
15860     case const_1_mode:
15861       if (intel_syntax)
15862         oappend ("1");
15863       return;
15864     default:
15865       oappend (INTERNAL_DISASSEMBLER_ERROR);
15866       return;
15867     }
15868
15869   op &= mask;
15870   scratchbuf[0] = '$';
15871   print_operand_value (scratchbuf + 1, 1, op);
15872   oappend_maybe_intel (scratchbuf);
15873   scratchbuf[0] = '\0';
15874 }
15875
15876 static void
15877 OP_I64 (int bytemode, int sizeflag)
15878 {
15879   bfd_signed_vma op;
15880   bfd_signed_vma mask = -1;
15881
15882   if (address_mode != mode_64bit)
15883     {
15884       OP_I (bytemode, sizeflag);
15885       return;
15886     }
15887
15888   switch (bytemode)
15889     {
15890     case b_mode:
15891       FETCH_DATA (the_info, codep + 1);
15892       op = *codep++;
15893       mask = 0xff;
15894       break;
15895     case v_mode:
15896       USED_REX (REX_W);
15897       if (rex & REX_W)
15898         op = get64 ();
15899       else
15900         {
15901           if (sizeflag & DFLAG)
15902             {
15903               op = get32 ();
15904               mask = 0xffffffff;
15905             }
15906           else
15907             {
15908               op = get16 ();
15909               mask = 0xfffff;
15910             }
15911           used_prefixes |= (prefixes & PREFIX_DATA);
15912         }
15913       break;
15914     case w_mode:
15915       mask = 0xfffff;
15916       op = get16 ();
15917       break;
15918     default:
15919       oappend (INTERNAL_DISASSEMBLER_ERROR);
15920       return;
15921     }
15922
15923   op &= mask;
15924   scratchbuf[0] = '$';
15925   print_operand_value (scratchbuf + 1, 1, op);
15926   oappend_maybe_intel (scratchbuf);
15927   scratchbuf[0] = '\0';
15928 }
15929
15930 static void
15931 OP_sI (int bytemode, int sizeflag)
15932 {
15933   bfd_signed_vma op;
15934
15935   switch (bytemode)
15936     {
15937     case b_mode:
15938     case b_T_mode:
15939       FETCH_DATA (the_info, codep + 1);
15940       op = *codep++;
15941       if ((op & 0x80) != 0)
15942         op -= 0x100;
15943       if (bytemode == b_T_mode)
15944         {
15945           if (address_mode != mode_64bit
15946               || !((sizeflag & DFLAG) || (rex & REX_W)))
15947             {
15948               /* The operand-size prefix is overridden by a REX prefix.  */
15949               if ((sizeflag & DFLAG) || (rex & REX_W))
15950                 op &= 0xffffffff;
15951               else
15952                 op &= 0xffff;
15953           }
15954         }
15955       else
15956         {
15957           if (!(rex & REX_W))
15958             {
15959               if (sizeflag & DFLAG)
15960                 op &= 0xffffffff;
15961               else
15962                 op &= 0xffff;
15963             }
15964         }
15965       break;
15966     case v_mode:
15967       /* The operand-size prefix is overridden by a REX prefix.  */
15968       if ((sizeflag & DFLAG) || (rex & REX_W))
15969         op = get32s ();
15970       else
15971         op = get16 ();
15972       break;
15973     default:
15974       oappend (INTERNAL_DISASSEMBLER_ERROR);
15975       return;
15976     }
15977
15978   scratchbuf[0] = '$';
15979   print_operand_value (scratchbuf + 1, 1, op);
15980   oappend_maybe_intel (scratchbuf);
15981 }
15982
15983 static void
15984 OP_J (int bytemode, int sizeflag)
15985 {
15986   bfd_vma disp;
15987   bfd_vma mask = -1;
15988   bfd_vma segment = 0;
15989
15990   switch (bytemode)
15991     {
15992     case b_mode:
15993       FETCH_DATA (the_info, codep + 1);
15994       disp = *codep++;
15995       if ((disp & 0x80) != 0)
15996         disp -= 0x100;
15997       break;
15998     case v_mode:
15999       if (isa64 == amd64)
16000         USED_REX (REX_W);
16001       if ((sizeflag & DFLAG)
16002           || (address_mode == mode_64bit
16003               && (isa64 != amd64 || (rex & REX_W))))
16004         disp = get32s ();
16005       else
16006         {
16007           disp = get16 ();
16008           if ((disp & 0x8000) != 0)
16009             disp -= 0x10000;
16010           /* In 16bit mode, address is wrapped around at 64k within
16011              the same segment.  Otherwise, a data16 prefix on a jump
16012              instruction means that the pc is masked to 16 bits after
16013              the displacement is added!  */
16014           mask = 0xffff;
16015           if ((prefixes & PREFIX_DATA) == 0)
16016             segment = ((start_pc + (codep - start_codep))
16017                        & ~((bfd_vma) 0xffff));
16018         }
16019       if (address_mode != mode_64bit
16020           || (isa64 == amd64 && !(rex & REX_W)))
16021         used_prefixes |= (prefixes & PREFIX_DATA);
16022       break;
16023     default:
16024       oappend (INTERNAL_DISASSEMBLER_ERROR);
16025       return;
16026     }
16027   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16028   set_op (disp, 0);
16029   print_operand_value (scratchbuf, 1, disp);
16030   oappend (scratchbuf);
16031 }
16032
16033 static void
16034 OP_SEG (int bytemode, int sizeflag)
16035 {
16036   if (bytemode == w_mode)
16037     oappend (names_seg[modrm.reg]);
16038   else
16039     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16040 }
16041
16042 static void
16043 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16044 {
16045   int seg, offset;
16046
16047   if (sizeflag & DFLAG)
16048     {
16049       offset = get32 ();
16050       seg = get16 ();
16051     }
16052   else
16053     {
16054       offset = get16 ();
16055       seg = get16 ();
16056     }
16057   used_prefixes |= (prefixes & PREFIX_DATA);
16058   if (intel_syntax)
16059     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16060   else
16061     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16062   oappend (scratchbuf);
16063 }
16064
16065 static void
16066 OP_OFF (int bytemode, int sizeflag)
16067 {
16068   bfd_vma off;
16069
16070   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16071     intel_operand_size (bytemode, sizeflag);
16072   append_seg ();
16073
16074   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16075     off = get32 ();
16076   else
16077     off = get16 ();
16078
16079   if (intel_syntax)
16080     {
16081       if (!active_seg_prefix)
16082         {
16083           oappend (names_seg[ds_reg - es_reg]);
16084           oappend (":");
16085         }
16086     }
16087   print_operand_value (scratchbuf, 1, off);
16088   oappend (scratchbuf);
16089 }
16090
16091 static void
16092 OP_OFF64 (int bytemode, int sizeflag)
16093 {
16094   bfd_vma off;
16095
16096   if (address_mode != mode_64bit
16097       || (prefixes & PREFIX_ADDR))
16098     {
16099       OP_OFF (bytemode, sizeflag);
16100       return;
16101     }
16102
16103   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16104     intel_operand_size (bytemode, sizeflag);
16105   append_seg ();
16106
16107   off = get64 ();
16108
16109   if (intel_syntax)
16110     {
16111       if (!active_seg_prefix)
16112         {
16113           oappend (names_seg[ds_reg - es_reg]);
16114           oappend (":");
16115         }
16116     }
16117   print_operand_value (scratchbuf, 1, off);
16118   oappend (scratchbuf);
16119 }
16120
16121 static void
16122 ptr_reg (int code, int sizeflag)
16123 {
16124   const char *s;
16125
16126   *obufp++ = open_char;
16127   used_prefixes |= (prefixes & PREFIX_ADDR);
16128   if (address_mode == mode_64bit)
16129     {
16130       if (!(sizeflag & AFLAG))
16131         s = names32[code - eAX_reg];
16132       else
16133         s = names64[code - eAX_reg];
16134     }
16135   else if (sizeflag & AFLAG)
16136     s = names32[code - eAX_reg];
16137   else
16138     s = names16[code - eAX_reg];
16139   oappend (s);
16140   *obufp++ = close_char;
16141   *obufp = 0;
16142 }
16143
16144 static void
16145 OP_ESreg (int code, int sizeflag)
16146 {
16147   if (intel_syntax)
16148     {
16149       switch (codep[-1])
16150         {
16151         case 0x6d:      /* insw/insl */
16152           intel_operand_size (z_mode, sizeflag);
16153           break;
16154         case 0xa5:      /* movsw/movsl/movsq */
16155         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16156         case 0xab:      /* stosw/stosl */
16157         case 0xaf:      /* scasw/scasl */
16158           intel_operand_size (v_mode, sizeflag);
16159           break;
16160         default:
16161           intel_operand_size (b_mode, sizeflag);
16162         }
16163     }
16164   oappend_maybe_intel ("%es:");
16165   ptr_reg (code, sizeflag);
16166 }
16167
16168 static void
16169 OP_DSreg (int code, int sizeflag)
16170 {
16171   if (intel_syntax)
16172     {
16173       switch (codep[-1])
16174         {
16175         case 0x6f:      /* outsw/outsl */
16176           intel_operand_size (z_mode, sizeflag);
16177           break;
16178         case 0xa5:      /* movsw/movsl/movsq */
16179         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16180         case 0xad:      /* lodsw/lodsl/lodsq */
16181           intel_operand_size (v_mode, sizeflag);
16182           break;
16183         default:
16184           intel_operand_size (b_mode, sizeflag);
16185         }
16186     }
16187   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16188      default segment register DS is printed.  */
16189   if (!active_seg_prefix)
16190     active_seg_prefix = PREFIX_DS;
16191   append_seg ();
16192   ptr_reg (code, sizeflag);
16193 }
16194
16195 static void
16196 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16197 {
16198   int add;
16199   if (rex & REX_R)
16200     {
16201       USED_REX (REX_R);
16202       add = 8;
16203     }
16204   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16205     {
16206       all_prefixes[last_lock_prefix] = 0;
16207       used_prefixes |= PREFIX_LOCK;
16208       add = 8;
16209     }
16210   else
16211     add = 0;
16212   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16213   oappend_maybe_intel (scratchbuf);
16214 }
16215
16216 static void
16217 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16218 {
16219   int add;
16220   USED_REX (REX_R);
16221   if (rex & REX_R)
16222     add = 8;
16223   else
16224     add = 0;
16225   if (intel_syntax)
16226     sprintf (scratchbuf, "db%d", modrm.reg + add);
16227   else
16228     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16229   oappend (scratchbuf);
16230 }
16231
16232 static void
16233 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16234 {
16235   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16236   oappend_maybe_intel (scratchbuf);
16237 }
16238
16239 static void
16240 OP_R (int bytemode, int sizeflag)
16241 {
16242   /* Skip mod/rm byte.  */
16243   MODRM_CHECK;
16244   codep++;
16245   OP_E_register (bytemode, sizeflag);
16246 }
16247
16248 static void
16249 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16250 {
16251   int reg = modrm.reg;
16252   const char **names;
16253
16254   used_prefixes |= (prefixes & PREFIX_DATA);
16255   if (prefixes & PREFIX_DATA)
16256     {
16257       names = names_xmm;
16258       USED_REX (REX_R);
16259       if (rex & REX_R)
16260         reg += 8;
16261     }
16262   else
16263     names = names_mm;
16264   oappend (names[reg]);
16265 }
16266
16267 static void
16268 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16269 {
16270   int reg = modrm.reg;
16271   const char **names;
16272
16273   USED_REX (REX_R);
16274   if (rex & REX_R)
16275     reg += 8;
16276   if (vex.evex)
16277     {
16278       if (!vex.r)
16279         reg += 16;
16280     }
16281
16282   if (need_vex
16283       && bytemode != xmm_mode
16284       && bytemode != xmmq_mode
16285       && bytemode != evex_half_bcst_xmmq_mode
16286       && bytemode != ymm_mode
16287       && bytemode != scalar_mode)
16288     {
16289       switch (vex.length)
16290         {
16291         case 128:
16292           names = names_xmm;
16293           break;
16294         case 256:
16295           if (vex.w
16296               || (bytemode != vex_vsib_q_w_dq_mode
16297                   && bytemode != vex_vsib_q_w_d_mode))
16298             names = names_ymm;
16299           else
16300             names = names_xmm;
16301           break;
16302         case 512:
16303           names = names_zmm;
16304           break;
16305         default:
16306           abort ();
16307         }
16308     }
16309   else if (bytemode == xmmq_mode
16310            || bytemode == evex_half_bcst_xmmq_mode)
16311     {
16312       switch (vex.length)
16313         {
16314         case 128:
16315         case 256:
16316           names = names_xmm;
16317           break;
16318         case 512:
16319           names = names_ymm;
16320           break;
16321         default:
16322           abort ();
16323         }
16324     }
16325   else if (bytemode == ymm_mode)
16326     names = names_ymm;
16327   else
16328     names = names_xmm;
16329   oappend (names[reg]);
16330 }
16331
16332 static void
16333 OP_EM (int bytemode, int sizeflag)
16334 {
16335   int reg;
16336   const char **names;
16337
16338   if (modrm.mod != 3)
16339     {
16340       if (intel_syntax
16341           && (bytemode == v_mode || bytemode == v_swap_mode))
16342         {
16343           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16344           used_prefixes |= (prefixes & PREFIX_DATA);
16345         }
16346       OP_E (bytemode, sizeflag);
16347       return;
16348     }
16349
16350   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16351     swap_operand ();
16352
16353   /* Skip mod/rm byte.  */
16354   MODRM_CHECK;
16355   codep++;
16356   used_prefixes |= (prefixes & PREFIX_DATA);
16357   reg = modrm.rm;
16358   if (prefixes & PREFIX_DATA)
16359     {
16360       names = names_xmm;
16361       USED_REX (REX_B);
16362       if (rex & REX_B)
16363         reg += 8;
16364     }
16365   else
16366     names = names_mm;
16367   oappend (names[reg]);
16368 }
16369
16370 /* cvt* are the only instructions in sse2 which have
16371    both SSE and MMX operands and also have 0x66 prefix
16372    in their opcode. 0x66 was originally used to differentiate
16373    between SSE and MMX instruction(operands). So we have to handle the
16374    cvt* separately using OP_EMC and OP_MXC */
16375 static void
16376 OP_EMC (int bytemode, int sizeflag)
16377 {
16378   if (modrm.mod != 3)
16379     {
16380       if (intel_syntax && bytemode == v_mode)
16381         {
16382           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16383           used_prefixes |= (prefixes & PREFIX_DATA);
16384         }
16385       OP_E (bytemode, sizeflag);
16386       return;
16387     }
16388
16389   /* Skip mod/rm byte.  */
16390   MODRM_CHECK;
16391   codep++;
16392   used_prefixes |= (prefixes & PREFIX_DATA);
16393   oappend (names_mm[modrm.rm]);
16394 }
16395
16396 static void
16397 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16398 {
16399   used_prefixes |= (prefixes & PREFIX_DATA);
16400   oappend (names_mm[modrm.reg]);
16401 }
16402
16403 static void
16404 OP_EX (int bytemode, int sizeflag)
16405 {
16406   int reg;
16407   const char **names;
16408
16409   /* Skip mod/rm byte.  */
16410   MODRM_CHECK;
16411   codep++;
16412
16413   if (modrm.mod != 3)
16414     {
16415       OP_E_memory (bytemode, sizeflag);
16416       return;
16417     }
16418
16419   reg = modrm.rm;
16420   USED_REX (REX_B);
16421   if (rex & REX_B)
16422     reg += 8;
16423   if (vex.evex)
16424     {
16425       USED_REX (REX_X);
16426       if ((rex & REX_X))
16427         reg += 16;
16428     }
16429
16430   if ((sizeflag & SUFFIX_ALWAYS)
16431       && (bytemode == x_swap_mode
16432           || bytemode == d_swap_mode
16433           || bytemode == d_scalar_swap_mode
16434           || bytemode == q_swap_mode
16435           || bytemode == q_scalar_swap_mode))
16436     swap_operand ();
16437
16438   if (need_vex
16439       && bytemode != xmm_mode
16440       && bytemode != xmmdw_mode
16441       && bytemode != xmmqd_mode
16442       && bytemode != xmm_mb_mode
16443       && bytemode != xmm_mw_mode
16444       && bytemode != xmm_md_mode
16445       && bytemode != xmm_mq_mode
16446       && bytemode != xmm_mdq_mode
16447       && bytemode != xmmq_mode
16448       && bytemode != evex_half_bcst_xmmq_mode
16449       && bytemode != ymm_mode
16450       && bytemode != d_scalar_mode
16451       && bytemode != d_scalar_swap_mode
16452       && bytemode != q_scalar_mode
16453       && bytemode != q_scalar_swap_mode
16454       && bytemode != vex_scalar_w_dq_mode)
16455     {
16456       switch (vex.length)
16457         {
16458         case 128:
16459           names = names_xmm;
16460           break;
16461         case 256:
16462           names = names_ymm;
16463           break;
16464         case 512:
16465           names = names_zmm;
16466           break;
16467         default:
16468           abort ();
16469         }
16470     }
16471   else if (bytemode == xmmq_mode
16472            || bytemode == evex_half_bcst_xmmq_mode)
16473     {
16474       switch (vex.length)
16475         {
16476         case 128:
16477         case 256:
16478           names = names_xmm;
16479           break;
16480         case 512:
16481           names = names_ymm;
16482           break;
16483         default:
16484           abort ();
16485         }
16486     }
16487   else if (bytemode == ymm_mode)
16488     names = names_ymm;
16489   else
16490     names = names_xmm;
16491   oappend (names[reg]);
16492 }
16493
16494 static void
16495 OP_MS (int bytemode, int sizeflag)
16496 {
16497   if (modrm.mod == 3)
16498     OP_EM (bytemode, sizeflag);
16499   else
16500     BadOp ();
16501 }
16502
16503 static void
16504 OP_XS (int bytemode, int sizeflag)
16505 {
16506   if (modrm.mod == 3)
16507     OP_EX (bytemode, sizeflag);
16508   else
16509     BadOp ();
16510 }
16511
16512 static void
16513 OP_M (int bytemode, int sizeflag)
16514 {
16515   if (modrm.mod == 3)
16516     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16517     BadOp ();
16518   else
16519     OP_E (bytemode, sizeflag);
16520 }
16521
16522 static void
16523 OP_0f07 (int bytemode, int sizeflag)
16524 {
16525   if (modrm.mod != 3 || modrm.rm != 0)
16526     BadOp ();
16527   else
16528     OP_E (bytemode, sizeflag);
16529 }
16530
16531 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16532    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16533
16534 static void
16535 NOP_Fixup1 (int bytemode, int sizeflag)
16536 {
16537   if ((prefixes & PREFIX_DATA) != 0
16538       || (rex != 0
16539           && rex != 0x48
16540           && address_mode == mode_64bit))
16541     OP_REG (bytemode, sizeflag);
16542   else
16543     strcpy (obuf, "nop");
16544 }
16545
16546 static void
16547 NOP_Fixup2 (int bytemode, int sizeflag)
16548 {
16549   if ((prefixes & PREFIX_DATA) != 0
16550       || (rex != 0
16551           && rex != 0x48
16552           && address_mode == mode_64bit))
16553     OP_IMREG (bytemode, sizeflag);
16554 }
16555
16556 static const char *const Suffix3DNow[] = {
16557 /* 00 */        NULL,           NULL,           NULL,           NULL,
16558 /* 04 */        NULL,           NULL,           NULL,           NULL,
16559 /* 08 */        NULL,           NULL,           NULL,           NULL,
16560 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16561 /* 10 */        NULL,           NULL,           NULL,           NULL,
16562 /* 14 */        NULL,           NULL,           NULL,           NULL,
16563 /* 18 */        NULL,           NULL,           NULL,           NULL,
16564 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16565 /* 20 */        NULL,           NULL,           NULL,           NULL,
16566 /* 24 */        NULL,           NULL,           NULL,           NULL,
16567 /* 28 */        NULL,           NULL,           NULL,           NULL,
16568 /* 2C */        NULL,           NULL,           NULL,           NULL,
16569 /* 30 */        NULL,           NULL,           NULL,           NULL,
16570 /* 34 */        NULL,           NULL,           NULL,           NULL,
16571 /* 38 */        NULL,           NULL,           NULL,           NULL,
16572 /* 3C */        NULL,           NULL,           NULL,           NULL,
16573 /* 40 */        NULL,           NULL,           NULL,           NULL,
16574 /* 44 */        NULL,           NULL,           NULL,           NULL,
16575 /* 48 */        NULL,           NULL,           NULL,           NULL,
16576 /* 4C */        NULL,           NULL,           NULL,           NULL,
16577 /* 50 */        NULL,           NULL,           NULL,           NULL,
16578 /* 54 */        NULL,           NULL,           NULL,           NULL,
16579 /* 58 */        NULL,           NULL,           NULL,           NULL,
16580 /* 5C */        NULL,           NULL,           NULL,           NULL,
16581 /* 60 */        NULL,           NULL,           NULL,           NULL,
16582 /* 64 */        NULL,           NULL,           NULL,           NULL,
16583 /* 68 */        NULL,           NULL,           NULL,           NULL,
16584 /* 6C */        NULL,           NULL,           NULL,           NULL,
16585 /* 70 */        NULL,           NULL,           NULL,           NULL,
16586 /* 74 */        NULL,           NULL,           NULL,           NULL,
16587 /* 78 */        NULL,           NULL,           NULL,           NULL,
16588 /* 7C */        NULL,           NULL,           NULL,           NULL,
16589 /* 80 */        NULL,           NULL,           NULL,           NULL,
16590 /* 84 */        NULL,           NULL,           NULL,           NULL,
16591 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16592 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16593 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16594 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16595 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16596 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16597 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16598 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16599 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16600 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16601 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16602 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16603 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16604 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16605 /* C0 */        NULL,           NULL,           NULL,           NULL,
16606 /* C4 */        NULL,           NULL,           NULL,           NULL,
16607 /* C8 */        NULL,           NULL,           NULL,           NULL,
16608 /* CC */        NULL,           NULL,           NULL,           NULL,
16609 /* D0 */        NULL,           NULL,           NULL,           NULL,
16610 /* D4 */        NULL,           NULL,           NULL,           NULL,
16611 /* D8 */        NULL,           NULL,           NULL,           NULL,
16612 /* DC */        NULL,           NULL,           NULL,           NULL,
16613 /* E0 */        NULL,           NULL,           NULL,           NULL,
16614 /* E4 */        NULL,           NULL,           NULL,           NULL,
16615 /* E8 */        NULL,           NULL,           NULL,           NULL,
16616 /* EC */        NULL,           NULL,           NULL,           NULL,
16617 /* F0 */        NULL,           NULL,           NULL,           NULL,
16618 /* F4 */        NULL,           NULL,           NULL,           NULL,
16619 /* F8 */        NULL,           NULL,           NULL,           NULL,
16620 /* FC */        NULL,           NULL,           NULL,           NULL,
16621 };
16622
16623 static void
16624 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16625 {
16626   const char *mnemonic;
16627
16628   FETCH_DATA (the_info, codep + 1);
16629   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16630      place where an 8-bit immediate would normally go.  ie. the last
16631      byte of the instruction.  */
16632   obufp = mnemonicendp;
16633   mnemonic = Suffix3DNow[*codep++ & 0xff];
16634   if (mnemonic)
16635     oappend (mnemonic);
16636   else
16637     {
16638       /* Since a variable sized modrm/sib chunk is between the start
16639          of the opcode (0x0f0f) and the opcode suffix, we need to do
16640          all the modrm processing first, and don't know until now that
16641          we have a bad opcode.  This necessitates some cleaning up.  */
16642       op_out[0][0] = '\0';
16643       op_out[1][0] = '\0';
16644       BadOp ();
16645     }
16646   mnemonicendp = obufp;
16647 }
16648
16649 static struct op simd_cmp_op[] =
16650 {
16651   { STRING_COMMA_LEN ("eq") },
16652   { STRING_COMMA_LEN ("lt") },
16653   { STRING_COMMA_LEN ("le") },
16654   { STRING_COMMA_LEN ("unord") },
16655   { STRING_COMMA_LEN ("neq") },
16656   { STRING_COMMA_LEN ("nlt") },
16657   { STRING_COMMA_LEN ("nle") },
16658   { STRING_COMMA_LEN ("ord") }
16659 };
16660
16661 static void
16662 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16663 {
16664   unsigned int cmp_type;
16665
16666   FETCH_DATA (the_info, codep + 1);
16667   cmp_type = *codep++ & 0xff;
16668   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16669     {
16670       char suffix [3];
16671       char *p = mnemonicendp - 2;
16672       suffix[0] = p[0];
16673       suffix[1] = p[1];
16674       suffix[2] = '\0';
16675       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16676       mnemonicendp += simd_cmp_op[cmp_type].len;
16677     }
16678   else
16679     {
16680       /* We have a reserved extension byte.  Output it directly.  */
16681       scratchbuf[0] = '$';
16682       print_operand_value (scratchbuf + 1, 1, cmp_type);
16683       oappend_maybe_intel (scratchbuf);
16684       scratchbuf[0] = '\0';
16685     }
16686 }
16687
16688 static void
16689 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16690           int sizeflag ATTRIBUTE_UNUSED)
16691 {
16692   /* mwaitx %eax,%ecx,%ebx */
16693   if (!intel_syntax)
16694     {
16695       const char **names = (address_mode == mode_64bit
16696                             ? names64 : names32);
16697       strcpy (op_out[0], names[0]);
16698       strcpy (op_out[1], names[1]);
16699       strcpy (op_out[2], names[3]);
16700       two_source_ops = 1;
16701     }
16702   /* Skip mod/rm byte.  */
16703   MODRM_CHECK;
16704   codep++;
16705 }
16706
16707 static void
16708 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16709           int sizeflag ATTRIBUTE_UNUSED)
16710 {
16711   /* mwait %eax,%ecx  */
16712   if (!intel_syntax)
16713     {
16714       const char **names = (address_mode == mode_64bit
16715                             ? names64 : names32);
16716       strcpy (op_out[0], names[0]);
16717       strcpy (op_out[1], names[1]);
16718       two_source_ops = 1;
16719     }
16720   /* Skip mod/rm byte.  */
16721   MODRM_CHECK;
16722   codep++;
16723 }
16724
16725 static void
16726 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16727             int sizeflag ATTRIBUTE_UNUSED)
16728 {
16729   /* monitor %eax,%ecx,%edx"  */
16730   if (!intel_syntax)
16731     {
16732       const char **op1_names;
16733       const char **names = (address_mode == mode_64bit
16734                             ? names64 : names32);
16735
16736       if (!(prefixes & PREFIX_ADDR))
16737         op1_names = (address_mode == mode_16bit
16738                      ? names16 : names);
16739       else
16740         {
16741           /* Remove "addr16/addr32".  */
16742           all_prefixes[last_addr_prefix] = 0;
16743           op1_names = (address_mode != mode_32bit
16744                        ? names32 : names16);
16745           used_prefixes |= PREFIX_ADDR;
16746         }
16747       strcpy (op_out[0], op1_names[0]);
16748       strcpy (op_out[1], names[1]);
16749       strcpy (op_out[2], names[2]);
16750       two_source_ops = 1;
16751     }
16752   /* Skip mod/rm byte.  */
16753   MODRM_CHECK;
16754   codep++;
16755 }
16756
16757 static void
16758 BadOp (void)
16759 {
16760   /* Throw away prefixes and 1st. opcode byte.  */
16761   codep = insn_codep + 1;
16762   oappend ("(bad)");
16763 }
16764
16765 static void
16766 REP_Fixup (int bytemode, int sizeflag)
16767 {
16768   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16769      lods and stos.  */
16770   if (prefixes & PREFIX_REPZ)
16771     all_prefixes[last_repz_prefix] = REP_PREFIX;
16772
16773   switch (bytemode)
16774     {
16775     case al_reg:
16776     case eAX_reg:
16777     case indir_dx_reg:
16778       OP_IMREG (bytemode, sizeflag);
16779       break;
16780     case eDI_reg:
16781       OP_ESreg (bytemode, sizeflag);
16782       break;
16783     case eSI_reg:
16784       OP_DSreg (bytemode, sizeflag);
16785       break;
16786     default:
16787       abort ();
16788       break;
16789     }
16790 }
16791
16792 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16793    "bnd".  */
16794
16795 static void
16796 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16797 {
16798   if (prefixes & PREFIX_REPNZ)
16799     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16800 }
16801
16802 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16803    "notrack".  */
16804
16805 static void
16806 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16807                int sizeflag ATTRIBUTE_UNUSED)
16808 {
16809   if (modrm.mod == 3
16810       && active_seg_prefix == PREFIX_DS
16811       && (address_mode != mode_64bit || last_data_prefix < 0))
16812     {
16813       /* NOTRACK prefix is only valid on register indirect branch
16814          instructions and it must be the last prefix before REX
16815          prefix and opcode.  NB: DATA prefix is unsupported for
16816          Intel64.  */
16817       if (last_active_prefix >= 0)
16818         {
16819           int notrack_prefix = last_active_prefix;
16820           if (last_rex_prefix == last_active_prefix)
16821             notrack_prefix--;
16822           if (all_prefixes[notrack_prefix] != NOTRACK_PREFIX_OPCODE)
16823             return;
16824         }
16825       active_seg_prefix = 0;
16826       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16827     }
16828 }
16829
16830 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16831    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16832  */
16833
16834 static void
16835 HLE_Fixup1 (int bytemode, int sizeflag)
16836 {
16837   if (modrm.mod != 3
16838       && (prefixes & PREFIX_LOCK) != 0)
16839     {
16840       if (prefixes & PREFIX_REPZ)
16841         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16842       if (prefixes & PREFIX_REPNZ)
16843         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16844     }
16845
16846   OP_E (bytemode, sizeflag);
16847 }
16848
16849 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16850    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16851  */
16852
16853 static void
16854 HLE_Fixup2 (int bytemode, int sizeflag)
16855 {
16856   if (modrm.mod != 3)
16857     {
16858       if (prefixes & PREFIX_REPZ)
16859         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16860       if (prefixes & PREFIX_REPNZ)
16861         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16862     }
16863
16864   OP_E (bytemode, sizeflag);
16865 }
16866
16867 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16868    "xrelease" for memory operand.  No check for LOCK prefix.   */
16869
16870 static void
16871 HLE_Fixup3 (int bytemode, int sizeflag)
16872 {
16873   if (modrm.mod != 3
16874       && last_repz_prefix > last_repnz_prefix
16875       && (prefixes & PREFIX_REPZ) != 0)
16876     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16877
16878   OP_E (bytemode, sizeflag);
16879 }
16880
16881 static void
16882 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16883 {
16884   USED_REX (REX_W);
16885   if (rex & REX_W)
16886     {
16887       /* Change cmpxchg8b to cmpxchg16b.  */
16888       char *p = mnemonicendp - 2;
16889       mnemonicendp = stpcpy (p, "16b");
16890       bytemode = o_mode;
16891     }
16892   else if ((prefixes & PREFIX_LOCK) != 0)
16893     {
16894       if (prefixes & PREFIX_REPZ)
16895         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16896       if (prefixes & PREFIX_REPNZ)
16897         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16898     }
16899
16900   OP_M (bytemode, sizeflag);
16901 }
16902
16903 static void
16904 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16905 {
16906   const char **names;
16907
16908   if (need_vex)
16909     {
16910       switch (vex.length)
16911         {
16912         case 128:
16913           names = names_xmm;
16914           break;
16915         case 256:
16916           names = names_ymm;
16917           break;
16918         default:
16919           abort ();
16920         }
16921     }
16922   else
16923     names = names_xmm;
16924   oappend (names[reg]);
16925 }
16926
16927 static void
16928 CRC32_Fixup (int bytemode, int sizeflag)
16929 {
16930   /* Add proper suffix to "crc32".  */
16931   char *p = mnemonicendp;
16932
16933   switch (bytemode)
16934     {
16935     case b_mode:
16936       if (intel_syntax)
16937         goto skip;
16938
16939       *p++ = 'b';
16940       break;
16941     case v_mode:
16942       if (intel_syntax)
16943         goto skip;
16944
16945       USED_REX (REX_W);
16946       if (rex & REX_W)
16947         *p++ = 'q';
16948       else
16949         {
16950           if (sizeflag & DFLAG)
16951             *p++ = 'l';
16952           else
16953             *p++ = 'w';
16954           used_prefixes |= (prefixes & PREFIX_DATA);
16955         }
16956       break;
16957     default:
16958       oappend (INTERNAL_DISASSEMBLER_ERROR);
16959       break;
16960     }
16961   mnemonicendp = p;
16962   *p = '\0';
16963
16964 skip:
16965   if (modrm.mod == 3)
16966     {
16967       int add;
16968
16969       /* Skip mod/rm byte.  */
16970       MODRM_CHECK;
16971       codep++;
16972
16973       USED_REX (REX_B);
16974       add = (rex & REX_B) ? 8 : 0;
16975       if (bytemode == b_mode)
16976         {
16977           USED_REX (0);
16978           if (rex)
16979             oappend (names8rex[modrm.rm + add]);
16980           else
16981             oappend (names8[modrm.rm + add]);
16982         }
16983       else
16984         {
16985           USED_REX (REX_W);
16986           if (rex & REX_W)
16987             oappend (names64[modrm.rm + add]);
16988           else if ((prefixes & PREFIX_DATA))
16989             oappend (names16[modrm.rm + add]);
16990           else
16991             oappend (names32[modrm.rm + add]);
16992         }
16993     }
16994   else
16995     OP_E (bytemode, sizeflag);
16996 }
16997
16998 static void
16999 FXSAVE_Fixup (int bytemode, int sizeflag)
17000 {
17001   /* Add proper suffix to "fxsave" and "fxrstor".  */
17002   USED_REX (REX_W);
17003   if (rex & REX_W)
17004     {
17005       char *p = mnemonicendp;
17006       *p++ = '6';
17007       *p++ = '4';
17008       *p = '\0';
17009       mnemonicendp = p;
17010     }
17011   OP_M (bytemode, sizeflag);
17012 }
17013
17014 static void
17015 PCMPESTR_Fixup (int bytemode, int sizeflag)
17016 {
17017   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17018   if (!intel_syntax)
17019     {
17020       char *p = mnemonicendp;
17021
17022       USED_REX (REX_W);
17023       if (rex & REX_W)
17024         *p++ = 'q';
17025       else if (sizeflag & SUFFIX_ALWAYS)
17026         *p++ = 'l';
17027
17028       *p = '\0';
17029       mnemonicendp = p;
17030     }
17031
17032   OP_EX (bytemode, sizeflag);
17033 }
17034
17035 /* Display the destination register operand for instructions with
17036    VEX. */
17037
17038 static void
17039 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17040 {
17041   int reg;
17042   const char **names;
17043
17044   if (!need_vex)
17045     abort ();
17046
17047   if (!need_vex_reg)
17048     return;
17049
17050   reg = vex.register_specifier;
17051   if (vex.evex)
17052     {
17053       if (!vex.v)
17054         reg += 16;
17055     }
17056
17057   if (bytemode == vex_scalar_mode)
17058     {
17059       oappend (names_xmm[reg]);
17060       return;
17061     }
17062
17063   switch (vex.length)
17064     {
17065     case 128:
17066       switch (bytemode)
17067         {
17068         case vex_mode:
17069         case vex128_mode:
17070         case vex_vsib_q_w_dq_mode:
17071         case vex_vsib_q_w_d_mode:
17072           names = names_xmm;
17073           break;
17074         case dq_mode:
17075           if (vex.w)
17076             names = names64;
17077           else
17078             names = names32;
17079           break;
17080         case mask_bd_mode:
17081         case mask_mode:
17082           if (reg > 0x7)
17083             {
17084               oappend ("(bad)");
17085               return;
17086             }
17087           names = names_mask;
17088           break;
17089         default:
17090           abort ();
17091           return;
17092         }
17093       break;
17094     case 256:
17095       switch (bytemode)
17096         {
17097         case vex_mode:
17098         case vex256_mode:
17099           names = names_ymm;
17100           break;
17101         case vex_vsib_q_w_dq_mode:
17102         case vex_vsib_q_w_d_mode:
17103           names = vex.w ? names_ymm : names_xmm;
17104           break;
17105         case mask_bd_mode:
17106         case mask_mode:
17107           if (reg > 0x7)
17108             {
17109               oappend ("(bad)");
17110               return;
17111             }
17112           names = names_mask;
17113           break;
17114         default:
17115           /* See PR binutils/20893 for a reproducer.  */
17116           oappend ("(bad)");
17117           return;
17118         }
17119       break;
17120     case 512:
17121       names = names_zmm;
17122       break;
17123     default:
17124       abort ();
17125       break;
17126     }
17127   oappend (names[reg]);
17128 }
17129
17130 /* Get the VEX immediate byte without moving codep.  */
17131
17132 static unsigned char
17133 get_vex_imm8 (int sizeflag, int opnum)
17134 {
17135   int bytes_before_imm = 0;
17136
17137   if (modrm.mod != 3)
17138     {
17139       /* There are SIB/displacement bytes.  */
17140       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17141         {
17142           /* 32/64 bit address mode */
17143           int base = modrm.rm;
17144
17145           /* Check SIB byte.  */
17146           if (base == 4)
17147             {
17148               FETCH_DATA (the_info, codep + 1);
17149               base = *codep & 7;
17150               /* When decoding the third source, don't increase
17151                  bytes_before_imm as this has already been incremented
17152                  by one in OP_E_memory while decoding the second
17153                  source operand.  */
17154               if (opnum == 0)
17155                 bytes_before_imm++;
17156             }
17157
17158           /* Don't increase bytes_before_imm when decoding the third source,
17159              it has already been incremented by OP_E_memory while decoding
17160              the second source operand.  */
17161           if (opnum == 0)
17162             {
17163               switch (modrm.mod)
17164                 {
17165                   case 0:
17166                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17167                        SIB == 5, there is a 4 byte displacement.  */
17168                     if (base != 5)
17169                       /* No displacement. */
17170                       break;
17171                     /* Fall through.  */
17172                   case 2:
17173                     /* 4 byte displacement.  */
17174                     bytes_before_imm += 4;
17175                     break;
17176                   case 1:
17177                     /* 1 byte displacement.  */
17178                     bytes_before_imm++;
17179                     break;
17180                 }
17181             }
17182         }
17183       else
17184         {
17185           /* 16 bit address mode */
17186           /* Don't increase bytes_before_imm when decoding the third source,
17187              it has already been incremented by OP_E_memory while decoding
17188              the second source operand.  */
17189           if (opnum == 0)
17190             {
17191               switch (modrm.mod)
17192                 {
17193                 case 0:
17194                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17195                   if (modrm.rm != 6)
17196                     /* No displacement. */
17197                     break;
17198                   /* Fall through.  */
17199                 case 2:
17200                   /* 2 byte displacement.  */
17201                   bytes_before_imm += 2;
17202                   break;
17203                 case 1:
17204                   /* 1 byte displacement: when decoding the third source,
17205                      don't increase bytes_before_imm as this has already
17206                      been incremented by one in OP_E_memory while decoding
17207                      the second source operand.  */
17208                   if (opnum == 0)
17209                     bytes_before_imm++;
17210
17211                   break;
17212                 }
17213             }
17214         }
17215     }
17216
17217   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17218   return codep [bytes_before_imm];
17219 }
17220
17221 static void
17222 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17223 {
17224   const char **names;
17225
17226   if (reg == -1 && modrm.mod != 3)
17227     {
17228       OP_E_memory (bytemode, sizeflag);
17229       return;
17230     }
17231   else
17232     {
17233       if (reg == -1)
17234         {
17235           reg = modrm.rm;
17236           USED_REX (REX_B);
17237           if (rex & REX_B)
17238             reg += 8;
17239         }
17240       else if (reg > 7 && address_mode != mode_64bit)
17241         BadOp ();
17242     }
17243
17244   switch (vex.length)
17245     {
17246     case 128:
17247       names = names_xmm;
17248       break;
17249     case 256:
17250       names = names_ymm;
17251       break;
17252     default:
17253       abort ();
17254     }
17255   oappend (names[reg]);
17256 }
17257
17258 static void
17259 OP_EX_VexImmW (int bytemode, int sizeflag)
17260 {
17261   int reg = -1;
17262   static unsigned char vex_imm8;
17263
17264   if (vex_w_done == 0)
17265     {
17266       vex_w_done = 1;
17267
17268       /* Skip mod/rm byte.  */
17269       MODRM_CHECK;
17270       codep++;
17271
17272       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17273
17274       if (vex.w)
17275           reg = vex_imm8 >> 4;
17276
17277       OP_EX_VexReg (bytemode, sizeflag, reg);
17278     }
17279   else if (vex_w_done == 1)
17280     {
17281       vex_w_done = 2;
17282
17283       if (!vex.w)
17284           reg = vex_imm8 >> 4;
17285
17286       OP_EX_VexReg (bytemode, sizeflag, reg);
17287     }
17288   else
17289     {
17290       /* Output the imm8 directly.  */
17291       scratchbuf[0] = '$';
17292       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17293       oappend_maybe_intel (scratchbuf);
17294       scratchbuf[0] = '\0';
17295       codep++;
17296     }
17297 }
17298
17299 static void
17300 OP_Vex_2src (int bytemode, int sizeflag)
17301 {
17302   if (modrm.mod == 3)
17303     {
17304       int reg = modrm.rm;
17305       USED_REX (REX_B);
17306       if (rex & REX_B)
17307         reg += 8;
17308       oappend (names_xmm[reg]);
17309     }
17310   else
17311     {
17312       if (intel_syntax
17313           && (bytemode == v_mode || bytemode == v_swap_mode))
17314         {
17315           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17316           used_prefixes |= (prefixes & PREFIX_DATA);
17317         }
17318       OP_E (bytemode, sizeflag);
17319     }
17320 }
17321
17322 static void
17323 OP_Vex_2src_1 (int bytemode, int sizeflag)
17324 {
17325   if (modrm.mod == 3)
17326     {
17327       /* Skip mod/rm byte.   */
17328       MODRM_CHECK;
17329       codep++;
17330     }
17331
17332   if (vex.w)
17333     oappend (names_xmm[vex.register_specifier]);
17334   else
17335     OP_Vex_2src (bytemode, sizeflag);
17336 }
17337
17338 static void
17339 OP_Vex_2src_2 (int bytemode, int sizeflag)
17340 {
17341   if (vex.w)
17342     OP_Vex_2src (bytemode, sizeflag);
17343   else
17344     oappend (names_xmm[vex.register_specifier]);
17345 }
17346
17347 static void
17348 OP_EX_VexW (int bytemode, int sizeflag)
17349 {
17350   int reg = -1;
17351
17352   if (!vex_w_done)
17353     {
17354       vex_w_done = 1;
17355
17356       /* Skip mod/rm byte.  */
17357       MODRM_CHECK;
17358       codep++;
17359
17360       if (vex.w)
17361         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17362     }
17363   else
17364     {
17365       if (!vex.w)
17366         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17367     }
17368
17369   OP_EX_VexReg (bytemode, sizeflag, reg);
17370 }
17371
17372 static void
17373 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17374              int sizeflag ATTRIBUTE_UNUSED)
17375 {
17376   /* Skip the immediate byte and check for invalid bits.  */
17377   FETCH_DATA (the_info, codep + 1);
17378   if (*codep++ & 0xf)
17379     BadOp ();
17380 }
17381
17382 static void
17383 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17384 {
17385   int reg;
17386   const char **names;
17387
17388   FETCH_DATA (the_info, codep + 1);
17389   reg = *codep++;
17390
17391   if (bytemode != x_mode)
17392     abort ();
17393
17394   if (reg & 0xf)
17395       BadOp ();
17396
17397   reg >>= 4;
17398   if (reg > 7 && address_mode != mode_64bit)
17399     BadOp ();
17400
17401   switch (vex.length)
17402     {
17403     case 128:
17404       names = names_xmm;
17405       break;
17406     case 256:
17407       names = names_ymm;
17408       break;
17409     default:
17410       abort ();
17411     }
17412   oappend (names[reg]);
17413 }
17414
17415 static void
17416 OP_XMM_VexW (int bytemode, int sizeflag)
17417 {
17418   /* Turn off the REX.W bit since it is used for swapping operands
17419      now.  */
17420   rex &= ~REX_W;
17421   OP_XMM (bytemode, sizeflag);
17422 }
17423
17424 static void
17425 OP_EX_Vex (int bytemode, int sizeflag)
17426 {
17427   if (modrm.mod != 3)
17428     {
17429       if (vex.register_specifier != 0)
17430         BadOp ();
17431       need_vex_reg = 0;
17432     }
17433   OP_EX (bytemode, sizeflag);
17434 }
17435
17436 static void
17437 OP_XMM_Vex (int bytemode, int sizeflag)
17438 {
17439   if (modrm.mod != 3)
17440     {
17441       if (vex.register_specifier != 0)
17442         BadOp ();
17443       need_vex_reg = 0;
17444     }
17445   OP_XMM (bytemode, sizeflag);
17446 }
17447
17448 static void
17449 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17450 {
17451   switch (vex.length)
17452     {
17453     case 128:
17454       mnemonicendp = stpcpy (obuf, "vzeroupper");
17455       break;
17456     case 256:
17457       mnemonicendp = stpcpy (obuf, "vzeroall");
17458       break;
17459     default:
17460       abort ();
17461     }
17462 }
17463
17464 static struct op vex_cmp_op[] =
17465 {
17466   { STRING_COMMA_LEN ("eq") },
17467   { STRING_COMMA_LEN ("lt") },
17468   { STRING_COMMA_LEN ("le") },
17469   { STRING_COMMA_LEN ("unord") },
17470   { STRING_COMMA_LEN ("neq") },
17471   { STRING_COMMA_LEN ("nlt") },
17472   { STRING_COMMA_LEN ("nle") },
17473   { STRING_COMMA_LEN ("ord") },
17474   { STRING_COMMA_LEN ("eq_uq") },
17475   { STRING_COMMA_LEN ("nge") },
17476   { STRING_COMMA_LEN ("ngt") },
17477   { STRING_COMMA_LEN ("false") },
17478   { STRING_COMMA_LEN ("neq_oq") },
17479   { STRING_COMMA_LEN ("ge") },
17480   { STRING_COMMA_LEN ("gt") },
17481   { STRING_COMMA_LEN ("true") },
17482   { STRING_COMMA_LEN ("eq_os") },
17483   { STRING_COMMA_LEN ("lt_oq") },
17484   { STRING_COMMA_LEN ("le_oq") },
17485   { STRING_COMMA_LEN ("unord_s") },
17486   { STRING_COMMA_LEN ("neq_us") },
17487   { STRING_COMMA_LEN ("nlt_uq") },
17488   { STRING_COMMA_LEN ("nle_uq") },
17489   { STRING_COMMA_LEN ("ord_s") },
17490   { STRING_COMMA_LEN ("eq_us") },
17491   { STRING_COMMA_LEN ("nge_uq") },
17492   { STRING_COMMA_LEN ("ngt_uq") },
17493   { STRING_COMMA_LEN ("false_os") },
17494   { STRING_COMMA_LEN ("neq_os") },
17495   { STRING_COMMA_LEN ("ge_oq") },
17496   { STRING_COMMA_LEN ("gt_oq") },
17497   { STRING_COMMA_LEN ("true_us") },
17498 };
17499
17500 static void
17501 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17502 {
17503   unsigned int cmp_type;
17504
17505   FETCH_DATA (the_info, codep + 1);
17506   cmp_type = *codep++ & 0xff;
17507   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17508     {
17509       char suffix [3];
17510       char *p = mnemonicendp - 2;
17511       suffix[0] = p[0];
17512       suffix[1] = p[1];
17513       suffix[2] = '\0';
17514       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17515       mnemonicendp += vex_cmp_op[cmp_type].len;
17516     }
17517   else
17518     {
17519       /* We have a reserved extension byte.  Output it directly.  */
17520       scratchbuf[0] = '$';
17521       print_operand_value (scratchbuf + 1, 1, cmp_type);
17522       oappend_maybe_intel (scratchbuf);
17523       scratchbuf[0] = '\0';
17524     }
17525 }
17526
17527 static void
17528 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17529              int sizeflag ATTRIBUTE_UNUSED)
17530 {
17531   unsigned int cmp_type;
17532
17533   if (!vex.evex)
17534     abort ();
17535
17536   FETCH_DATA (the_info, codep + 1);
17537   cmp_type = *codep++ & 0xff;
17538   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17539      If it's the case, print suffix, otherwise - print the immediate.  */
17540   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17541       && cmp_type != 3
17542       && cmp_type != 7)
17543     {
17544       char suffix [3];
17545       char *p = mnemonicendp - 2;
17546
17547       /* vpcmp* can have both one- and two-lettered suffix.  */
17548       if (p[0] == 'p')
17549         {
17550           p++;
17551           suffix[0] = p[0];
17552           suffix[1] = '\0';
17553         }
17554       else
17555         {
17556           suffix[0] = p[0];
17557           suffix[1] = p[1];
17558           suffix[2] = '\0';
17559         }
17560
17561       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17562       mnemonicendp += simd_cmp_op[cmp_type].len;
17563     }
17564   else
17565     {
17566       /* We have a reserved extension byte.  Output it directly.  */
17567       scratchbuf[0] = '$';
17568       print_operand_value (scratchbuf + 1, 1, cmp_type);
17569       oappend_maybe_intel (scratchbuf);
17570       scratchbuf[0] = '\0';
17571     }
17572 }
17573
17574 static const struct op pclmul_op[] =
17575 {
17576   { STRING_COMMA_LEN ("lql") },
17577   { STRING_COMMA_LEN ("hql") },
17578   { STRING_COMMA_LEN ("lqh") },
17579   { STRING_COMMA_LEN ("hqh") }
17580 };
17581
17582 static void
17583 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17584               int sizeflag ATTRIBUTE_UNUSED)
17585 {
17586   unsigned int pclmul_type;
17587
17588   FETCH_DATA (the_info, codep + 1);
17589   pclmul_type = *codep++ & 0xff;
17590   switch (pclmul_type)
17591     {
17592     case 0x10:
17593       pclmul_type = 2;
17594       break;
17595     case 0x11:
17596       pclmul_type = 3;
17597       break;
17598     default:
17599       break;
17600     }
17601   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17602     {
17603       char suffix [4];
17604       char *p = mnemonicendp - 3;
17605       suffix[0] = p[0];
17606       suffix[1] = p[1];
17607       suffix[2] = p[2];
17608       suffix[3] = '\0';
17609       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17610       mnemonicendp += pclmul_op[pclmul_type].len;
17611     }
17612   else
17613     {
17614       /* We have a reserved extension byte.  Output it directly.  */
17615       scratchbuf[0] = '$';
17616       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17617       oappend_maybe_intel (scratchbuf);
17618       scratchbuf[0] = '\0';
17619     }
17620 }
17621
17622 static void
17623 MOVBE_Fixup (int bytemode, int sizeflag)
17624 {
17625   /* Add proper suffix to "movbe".  */
17626   char *p = mnemonicendp;
17627
17628   switch (bytemode)
17629     {
17630     case v_mode:
17631       if (intel_syntax)
17632         goto skip;
17633
17634       USED_REX (REX_W);
17635       if (sizeflag & SUFFIX_ALWAYS)
17636         {
17637           if (rex & REX_W)
17638             *p++ = 'q';
17639           else
17640             {
17641               if (sizeflag & DFLAG)
17642                 *p++ = 'l';
17643               else
17644                 *p++ = 'w';
17645               used_prefixes |= (prefixes & PREFIX_DATA);
17646             }
17647         }
17648       break;
17649     default:
17650       oappend (INTERNAL_DISASSEMBLER_ERROR);
17651       break;
17652     }
17653   mnemonicendp = p;
17654   *p = '\0';
17655
17656 skip:
17657   OP_M (bytemode, sizeflag);
17658 }
17659
17660 static void
17661 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17662 {
17663   int reg;
17664   const char **names;
17665
17666   /* Skip mod/rm byte.  */
17667   MODRM_CHECK;
17668   codep++;
17669
17670   if (vex.w)
17671     names = names64;
17672   else
17673     names = names32;
17674
17675   reg = modrm.rm;
17676   USED_REX (REX_B);
17677   if (rex & REX_B)
17678     reg += 8;
17679
17680   oappend (names[reg]);
17681 }
17682
17683 static void
17684 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17685 {
17686   const char **names;
17687
17688   if (vex.w)
17689     names = names64;
17690   else
17691     names = names32;
17692
17693   oappend (names[vex.register_specifier]);
17694 }
17695
17696 static void
17697 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17698 {
17699   if (!vex.evex
17700       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17701     abort ();
17702
17703   USED_REX (REX_R);
17704   if ((rex & REX_R) != 0 || !vex.r)
17705     {
17706       BadOp ();
17707       return;
17708     }
17709
17710   oappend (names_mask [modrm.reg]);
17711 }
17712
17713 static void
17714 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17715 {
17716   if (!vex.evex
17717       || (bytemode != evex_rounding_mode
17718           && bytemode != evex_sae_mode))
17719     abort ();
17720   if (modrm.mod == 3 && vex.b)
17721     switch (bytemode)
17722       {
17723       case evex_rounding_mode:
17724         oappend (names_rounding[vex.ll]);
17725         break;
17726       case evex_sae_mode:
17727         oappend ("{sae}");
17728         break;
17729       default:
17730         break;
17731       }
17732 }