opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_1,
 849   MOD_0F38F8_PREFIX_2,
 850   MOD_0F38F8_PREFIX_3,
 851   MOD_0F38F9_PREFIX_0,
 852   MOD_62_32BIT,
 853   MOD_C4_32BIT,
 854   MOD_C5_32BIT,
 855   MOD_VEX_0F12_PREFIX_0,
 856   MOD_VEX_0F13,
 857   MOD_VEX_0F16_PREFIX_0,
 858   MOD_VEX_0F17,
 859   MOD_VEX_0F2B,
 860   MOD_VEX_W_0_0F41_P_0_LEN_1,
 861   MOD_VEX_W_1_0F41_P_0_LEN_1,
 862   MOD_VEX_W_0_0F41_P_2_LEN_1,
 863   MOD_VEX_W_1_0F41_P_2_LEN_1,
 864   MOD_VEX_W_0_0F42_P_0_LEN_1,
 865   MOD_VEX_W_1_0F42_P_0_LEN_1,
 866   MOD_VEX_W_0_0F42_P_2_LEN_1,
 867   MOD_VEX_W_1_0F42_P_2_LEN_1,
 868   MOD_VEX_W_0_0F44_P_0_LEN_1,
 869   MOD_VEX_W_1_0F44_P_0_LEN_1,
 870   MOD_VEX_W_0_0F44_P_2_LEN_1,
 871   MOD_VEX_W_1_0F44_P_2_LEN_1,
 872   MOD_VEX_W_0_0F45_P_0_LEN_1,
 873   MOD_VEX_W_1_0F45_P_0_LEN_1,
 874   MOD_VEX_W_0_0F45_P_2_LEN_1,
 875   MOD_VEX_W_1_0F45_P_2_LEN_1,
 876   MOD_VEX_W_0_0F46_P_0_LEN_1,
 877   MOD_VEX_W_1_0F46_P_0_LEN_1,
 878   MOD_VEX_W_0_0F46_P_2_LEN_1,
 879   MOD_VEX_W_1_0F46_P_2_LEN_1,
 880   MOD_VEX_W_0_0F47_P_0_LEN_1,
 881   MOD_VEX_W_1_0F47_P_0_LEN_1,
 882   MOD_VEX_W_0_0F47_P_2_LEN_1,
 883   MOD_VEX_W_1_0F47_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 887   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 889   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 890   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 891   MOD_VEX_0F50,
 892   MOD_VEX_0F71_REG_2,
 893   MOD_VEX_0F71_REG_4,
 894   MOD_VEX_0F71_REG_6,
 895   MOD_VEX_0F72_REG_2,
 896   MOD_VEX_0F72_REG_4,
 897   MOD_VEX_0F72_REG_6,
 898   MOD_VEX_0F73_REG_2,
 899   MOD_VEX_0F73_REG_3,
 900   MOD_VEX_0F73_REG_6,
 901   MOD_VEX_0F73_REG_7,
 902   MOD_VEX_W_0_0F91_P_0_LEN_0,
 903   MOD_VEX_W_1_0F91_P_0_LEN_0,
 904   MOD_VEX_W_0_0F91_P_2_LEN_0,
 905   MOD_VEX_W_1_0F91_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_0_LEN_0,
 907   MOD_VEX_W_0_0F92_P_2_LEN_0,
 908   MOD_VEX_0F92_P_3_LEN_0,
 909   MOD_VEX_W_0_0F93_P_0_LEN_0,
 910   MOD_VEX_W_0_0F93_P_2_LEN_0,
 911   MOD_VEX_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3868,
1617   PREFIX_EVEX_0F3870,
1618   PREFIX_EVEX_0F3871,
1619   PREFIX_EVEX_0F3872,
1620   PREFIX_EVEX_0F3873,
1621   PREFIX_EVEX_0F3875,
1622   PREFIX_EVEX_0F3876,
1623   PREFIX_EVEX_0F3877,
1624   PREFIX_EVEX_0F3878,
1625   PREFIX_EVEX_0F3879,
1626   PREFIX_EVEX_0F387A,
1627   PREFIX_EVEX_0F387B,
1628   PREFIX_EVEX_0F387C,
1629   PREFIX_EVEX_0F387D,
1630   PREFIX_EVEX_0F387E,
1631   PREFIX_EVEX_0F387F,
1632   PREFIX_EVEX_0F3883,
1633   PREFIX_EVEX_0F3888,
1634   PREFIX_EVEX_0F3889,
1635   PREFIX_EVEX_0F388A,
1636   PREFIX_EVEX_0F388B,
1637   PREFIX_EVEX_0F388D,
1638   PREFIX_EVEX_0F388F,
1639   PREFIX_EVEX_0F3890,
1640   PREFIX_EVEX_0F3891,
1641   PREFIX_EVEX_0F3892,
1642   PREFIX_EVEX_0F3893,
1643   PREFIX_EVEX_0F3896,
1644   PREFIX_EVEX_0F3897,
1645   PREFIX_EVEX_0F3898,
1646   PREFIX_EVEX_0F3899,
1647   PREFIX_EVEX_0F389A,
1648   PREFIX_EVEX_0F389B,
1649   PREFIX_EVEX_0F389C,
1650   PREFIX_EVEX_0F389D,
1651   PREFIX_EVEX_0F389E,
1652   PREFIX_EVEX_0F389F,
1653   PREFIX_EVEX_0F38A0,
1654   PREFIX_EVEX_0F38A1,
1655   PREFIX_EVEX_0F38A2,
1656   PREFIX_EVEX_0F38A3,
1657   PREFIX_EVEX_0F38A6,
1658   PREFIX_EVEX_0F38A7,
1659   PREFIX_EVEX_0F38A8,
1660   PREFIX_EVEX_0F38A9,
1661   PREFIX_EVEX_0F38AA,
1662   PREFIX_EVEX_0F38AB,
1663   PREFIX_EVEX_0F38AC,
1664   PREFIX_EVEX_0F38AD,
1665   PREFIX_EVEX_0F38AE,
1666   PREFIX_EVEX_0F38AF,
1667   PREFIX_EVEX_0F38B4,
1668   PREFIX_EVEX_0F38B5,
1669   PREFIX_EVEX_0F38B6,
1670   PREFIX_EVEX_0F38B7,
1671   PREFIX_EVEX_0F38B8,
1672   PREFIX_EVEX_0F38B9,
1673   PREFIX_EVEX_0F38BA,
1674   PREFIX_EVEX_0F38BB,
1675   PREFIX_EVEX_0F38BC,
1676   PREFIX_EVEX_0F38BD,
1677   PREFIX_EVEX_0F38BE,
1678   PREFIX_EVEX_0F38BF,
1679   PREFIX_EVEX_0F38C4,
1680   PREFIX_EVEX_0F38C6_REG_1,
1681   PREFIX_EVEX_0F38C6_REG_2,
1682   PREFIX_EVEX_0F38C6_REG_5,
1683   PREFIX_EVEX_0F38C6_REG_6,
1684   PREFIX_EVEX_0F38C7_REG_1,
1685   PREFIX_EVEX_0F38C7_REG_2,
1686   PREFIX_EVEX_0F38C7_REG_5,
1687   PREFIX_EVEX_0F38C7_REG_6,
1688   PREFIX_EVEX_0F38C8,
1689   PREFIX_EVEX_0F38CA,
1690   PREFIX_EVEX_0F38CB,
1691   PREFIX_EVEX_0F38CC,
1692   PREFIX_EVEX_0F38CD,
1693   PREFIX_EVEX_0F38CF,
1694   PREFIX_EVEX_0F38DC,
1695   PREFIX_EVEX_0F38DD,
1696   PREFIX_EVEX_0F38DE,
1697   PREFIX_EVEX_0F38DF,
1698
1699   PREFIX_EVEX_0F3A00,
1700   PREFIX_EVEX_0F3A01,
1701   PREFIX_EVEX_0F3A03,
1702   PREFIX_EVEX_0F3A04,
1703   PREFIX_EVEX_0F3A05,
1704   PREFIX_EVEX_0F3A08,
1705   PREFIX_EVEX_0F3A09,
1706   PREFIX_EVEX_0F3A0A,
1707   PREFIX_EVEX_0F3A0B,
1708   PREFIX_EVEX_0F3A0F,
1709   PREFIX_EVEX_0F3A14,
1710   PREFIX_EVEX_0F3A15,
1711   PREFIX_EVEX_0F3A16,
1712   PREFIX_EVEX_0F3A17,
1713   PREFIX_EVEX_0F3A18,
1714   PREFIX_EVEX_0F3A19,
1715   PREFIX_EVEX_0F3A1A,
1716   PREFIX_EVEX_0F3A1B,
1717   PREFIX_EVEX_0F3A1D,
1718   PREFIX_EVEX_0F3A1E,
1719   PREFIX_EVEX_0F3A1F,
1720   PREFIX_EVEX_0F3A20,
1721   PREFIX_EVEX_0F3A21,
1722   PREFIX_EVEX_0F3A22,
1723   PREFIX_EVEX_0F3A23,
1724   PREFIX_EVEX_0F3A25,
1725   PREFIX_EVEX_0F3A26,
1726   PREFIX_EVEX_0F3A27,
1727   PREFIX_EVEX_0F3A38,
1728   PREFIX_EVEX_0F3A39,
1729   PREFIX_EVEX_0F3A3A,
1730   PREFIX_EVEX_0F3A3B,
1731   PREFIX_EVEX_0F3A3E,
1732   PREFIX_EVEX_0F3A3F,
1733   PREFIX_EVEX_0F3A42,
1734   PREFIX_EVEX_0F3A43,
1735   PREFIX_EVEX_0F3A44,
1736   PREFIX_EVEX_0F3A50,
1737   PREFIX_EVEX_0F3A51,
1738   PREFIX_EVEX_0F3A54,
1739   PREFIX_EVEX_0F3A55,
1740   PREFIX_EVEX_0F3A56,
1741   PREFIX_EVEX_0F3A57,
1742   PREFIX_EVEX_0F3A66,
1743   PREFIX_EVEX_0F3A67,
1744   PREFIX_EVEX_0F3A70,
1745   PREFIX_EVEX_0F3A71,
1746   PREFIX_EVEX_0F3A72,
1747   PREFIX_EVEX_0F3A73,
1748   PREFIX_EVEX_0F3ACE,
1749   PREFIX_EVEX_0F3ACF
1750 };
1751
1752 enum
1753 {
1754   X86_64_06 = 0,
1755   X86_64_07,
1756   X86_64_0D,
1757   X86_64_16,
1758   X86_64_17,
1759   X86_64_1E,
1760   X86_64_1F,
1761   X86_64_27,
1762   X86_64_2F,
1763   X86_64_37,
1764   X86_64_3F,
1765   X86_64_60,
1766   X86_64_61,
1767   X86_64_62,
1768   X86_64_63,
1769   X86_64_6D,
1770   X86_64_6F,
1771   X86_64_82,
1772   X86_64_9A,
1773   X86_64_C4,
1774   X86_64_C5,
1775   X86_64_CE,
1776   X86_64_D4,
1777   X86_64_D5,
1778   X86_64_E8,
1779   X86_64_E9,
1780   X86_64_EA,
1781   X86_64_0F01_REG_0,
1782   X86_64_0F01_REG_1,
1783   X86_64_0F01_REG_2,
1784   X86_64_0F01_REG_3
1785 };
1786
1787 enum
1788 {
1789   THREE_BYTE_0F38 = 0,
1790   THREE_BYTE_0F3A
1791 };
1792
1793 enum
1794 {
1795   XOP_08 = 0,
1796   XOP_09,
1797   XOP_0A
1798 };
1799
1800 enum
1801 {
1802   VEX_0F = 0,
1803   VEX_0F38,
1804   VEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   EVEX_0F = 0,
1810   EVEX_0F38,
1811   EVEX_0F3A
1812 };
1813
1814 enum
1815 {
1816   VEX_LEN_0F12_P_0_M_0 = 0,
1817   VEX_LEN_0F12_P_0_M_1,
1818   VEX_LEN_0F12_P_2,
1819   VEX_LEN_0F13_M_0,
1820   VEX_LEN_0F16_P_0_M_0,
1821   VEX_LEN_0F16_P_0_M_1,
1822   VEX_LEN_0F16_P_2,
1823   VEX_LEN_0F17_M_0,
1824   VEX_LEN_0F2A_P_1,
1825   VEX_LEN_0F2A_P_3,
1826   VEX_LEN_0F2C_P_1,
1827   VEX_LEN_0F2C_P_3,
1828   VEX_LEN_0F2D_P_1,
1829   VEX_LEN_0F2D_P_3,
1830   VEX_LEN_0F41_P_0,
1831   VEX_LEN_0F41_P_2,
1832   VEX_LEN_0F42_P_0,
1833   VEX_LEN_0F42_P_2,
1834   VEX_LEN_0F44_P_0,
1835   VEX_LEN_0F44_P_2,
1836   VEX_LEN_0F45_P_0,
1837   VEX_LEN_0F45_P_2,
1838   VEX_LEN_0F46_P_0,
1839   VEX_LEN_0F46_P_2,
1840   VEX_LEN_0F47_P_0,
1841   VEX_LEN_0F47_P_2,
1842   VEX_LEN_0F4A_P_0,
1843   VEX_LEN_0F4A_P_2,
1844   VEX_LEN_0F4B_P_0,
1845   VEX_LEN_0F4B_P_2,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F77_P_0,
1848   VEX_LEN_0F7E_P_1,
1849   VEX_LEN_0F7E_P_2,
1850   VEX_LEN_0F90_P_0,
1851   VEX_LEN_0F90_P_2,
1852   VEX_LEN_0F91_P_0,
1853   VEX_LEN_0F91_P_2,
1854   VEX_LEN_0F92_P_0,
1855   VEX_LEN_0F92_P_2,
1856   VEX_LEN_0F92_P_3,
1857   VEX_LEN_0F93_P_0,
1858   VEX_LEN_0F93_P_2,
1859   VEX_LEN_0F93_P_3,
1860   VEX_LEN_0F98_P_0,
1861   VEX_LEN_0F98_P_2,
1862   VEX_LEN_0F99_P_0,
1863   VEX_LEN_0F99_P_2,
1864   VEX_LEN_0FAE_R_2_M_0,
1865   VEX_LEN_0FAE_R_3_M_0,
1866   VEX_LEN_0FC4_P_2,
1867   VEX_LEN_0FC5_P_2,
1868   VEX_LEN_0FD6_P_2,
1869   VEX_LEN_0FF7_P_2,
1870   VEX_LEN_0F3816_P_2,
1871   VEX_LEN_0F3819_P_2,
1872   VEX_LEN_0F381A_P_2_M_0,
1873   VEX_LEN_0F3836_P_2,
1874   VEX_LEN_0F3841_P_2,
1875   VEX_LEN_0F385A_P_2_M_0,
1876   VEX_LEN_0F38DB_P_2,
1877   VEX_LEN_0F38F2_P_0,
1878   VEX_LEN_0F38F3_R_1_P_0,
1879   VEX_LEN_0F38F3_R_2_P_0,
1880   VEX_LEN_0F38F3_R_3_P_0,
1881   VEX_LEN_0F38F5_P_0,
1882   VEX_LEN_0F38F5_P_1,
1883   VEX_LEN_0F38F5_P_3,
1884   VEX_LEN_0F38F6_P_3,
1885   VEX_LEN_0F38F7_P_0,
1886   VEX_LEN_0F38F7_P_1,
1887   VEX_LEN_0F38F7_P_2,
1888   VEX_LEN_0F38F7_P_3,
1889   VEX_LEN_0F3A00_P_2,
1890   VEX_LEN_0F3A01_P_2,
1891   VEX_LEN_0F3A06_P_2,
1892   VEX_LEN_0F3A14_P_2,
1893   VEX_LEN_0F3A15_P_2,
1894   VEX_LEN_0F3A16_P_2,
1895   VEX_LEN_0F3A17_P_2,
1896   VEX_LEN_0F3A18_P_2,
1897   VEX_LEN_0F3A19_P_2,
1898   VEX_LEN_0F3A20_P_2,
1899   VEX_LEN_0F3A21_P_2,
1900   VEX_LEN_0F3A22_P_2,
1901   VEX_LEN_0F3A30_P_2,
1902   VEX_LEN_0F3A31_P_2,
1903   VEX_LEN_0F3A32_P_2,
1904   VEX_LEN_0F3A33_P_2,
1905   VEX_LEN_0F3A38_P_2,
1906   VEX_LEN_0F3A39_P_2,
1907   VEX_LEN_0F3A41_P_2,
1908   VEX_LEN_0F3A46_P_2,
1909   VEX_LEN_0F3A60_P_2,
1910   VEX_LEN_0F3A61_P_2,
1911   VEX_LEN_0F3A62_P_2,
1912   VEX_LEN_0F3A63_P_2,
1913   VEX_LEN_0F3A6A_P_2,
1914   VEX_LEN_0F3A6B_P_2,
1915   VEX_LEN_0F3A6E_P_2,
1916   VEX_LEN_0F3A6F_P_2,
1917   VEX_LEN_0F3A7A_P_2,
1918   VEX_LEN_0F3A7B_P_2,
1919   VEX_LEN_0F3A7E_P_2,
1920   VEX_LEN_0F3A7F_P_2,
1921   VEX_LEN_0F3ADF_P_2,
1922   VEX_LEN_0F3AF0_P_3,
1923   VEX_LEN_0FXOP_08_CC,
1924   VEX_LEN_0FXOP_08_CD,
1925   VEX_LEN_0FXOP_08_CE,
1926   VEX_LEN_0FXOP_08_CF,
1927   VEX_LEN_0FXOP_08_EC,
1928   VEX_LEN_0FXOP_08_ED,
1929   VEX_LEN_0FXOP_08_EE,
1930   VEX_LEN_0FXOP_08_EF,
1931   VEX_LEN_0FXOP_09_80,
1932   VEX_LEN_0FXOP_09_81
1933 };
1934
1935 enum
1936 {
1937   EVEX_LEN_0F6E_P_2 = 0,
1938   EVEX_LEN_0F7E_P_1,
1939   EVEX_LEN_0F7E_P_2,
1940   EVEX_LEN_0FD6_P_2,
1941   EVEX_LEN_0F3A18_P_2_W_0,
1942   EVEX_LEN_0F3A18_P_2_W_1,
1943   EVEX_LEN_0F3A19_P_2_W_0,
1944   EVEX_LEN_0F3A19_P_2_W_1,
1945   EVEX_LEN_0F3A1A_P_2_W_0,
1946   EVEX_LEN_0F3A1A_P_2_W_1,
1947   EVEX_LEN_0F3A1B_P_2_W_0,
1948   EVEX_LEN_0F3A1B_P_2_W_1
1949 };
1950
1951 enum
1952 {
1953   VEX_W_0F41_P_0_LEN_1 = 0,
1954   VEX_W_0F41_P_2_LEN_1,
1955   VEX_W_0F42_P_0_LEN_1,
1956   VEX_W_0F42_P_2_LEN_1,
1957   VEX_W_0F44_P_0_LEN_0,
1958   VEX_W_0F44_P_2_LEN_0,
1959   VEX_W_0F45_P_0_LEN_1,
1960   VEX_W_0F45_P_2_LEN_1,
1961   VEX_W_0F46_P_0_LEN_1,
1962   VEX_W_0F46_P_2_LEN_1,
1963   VEX_W_0F47_P_0_LEN_1,
1964   VEX_W_0F47_P_2_LEN_1,
1965   VEX_W_0F4A_P_0_LEN_1,
1966   VEX_W_0F4A_P_2_LEN_1,
1967   VEX_W_0F4B_P_0_LEN_1,
1968   VEX_W_0F4B_P_2_LEN_1,
1969   VEX_W_0F90_P_0_LEN_0,
1970   VEX_W_0F90_P_2_LEN_0,
1971   VEX_W_0F91_P_0_LEN_0,
1972   VEX_W_0F91_P_2_LEN_0,
1973   VEX_W_0F92_P_0_LEN_0,
1974   VEX_W_0F92_P_2_LEN_0,
1975   VEX_W_0F93_P_0_LEN_0,
1976   VEX_W_0F93_P_2_LEN_0,
1977   VEX_W_0F98_P_0_LEN_0,
1978   VEX_W_0F98_P_2_LEN_0,
1979   VEX_W_0F99_P_0_LEN_0,
1980   VEX_W_0F99_P_2_LEN_0,
1981   VEX_W_0F380C_P_2,
1982   VEX_W_0F380D_P_2,
1983   VEX_W_0F380E_P_2,
1984   VEX_W_0F380F_P_2,
1985   VEX_W_0F3816_P_2,
1986   VEX_W_0F3818_P_2,
1987   VEX_W_0F3819_P_2,
1988   VEX_W_0F381A_P_2_M_0,
1989   VEX_W_0F382C_P_2_M_0,
1990   VEX_W_0F382D_P_2_M_0,
1991   VEX_W_0F382E_P_2_M_0,
1992   VEX_W_0F382F_P_2_M_0,
1993   VEX_W_0F3836_P_2,
1994   VEX_W_0F3846_P_2,
1995   VEX_W_0F3858_P_2,
1996   VEX_W_0F3859_P_2,
1997   VEX_W_0F385A_P_2_M_0,
1998   VEX_W_0F3878_P_2,
1999   VEX_W_0F3879_P_2,
2000   VEX_W_0F38CF_P_2,
2001   VEX_W_0F3A00_P_2,
2002   VEX_W_0F3A01_P_2,
2003   VEX_W_0F3A02_P_2,
2004   VEX_W_0F3A04_P_2,
2005   VEX_W_0F3A05_P_2,
2006   VEX_W_0F3A06_P_2,
2007   VEX_W_0F3A18_P_2,
2008   VEX_W_0F3A19_P_2,
2009   VEX_W_0F3A30_P_2_LEN_0,
2010   VEX_W_0F3A31_P_2_LEN_0,
2011   VEX_W_0F3A32_P_2_LEN_0,
2012   VEX_W_0F3A33_P_2_LEN_0,
2013   VEX_W_0F3A38_P_2,
2014   VEX_W_0F3A39_P_2,
2015   VEX_W_0F3A46_P_2,
2016   VEX_W_0F3A48_P_2,
2017   VEX_W_0F3A49_P_2,
2018   VEX_W_0F3A4A_P_2,
2019   VEX_W_0F3A4B_P_2,
2020   VEX_W_0F3A4C_P_2,
2021   VEX_W_0F3ACE_P_2,
2022   VEX_W_0F3ACF_P_2,
2023
2024   EVEX_W_0F10_P_0,
2025   EVEX_W_0F10_P_1_M_0,
2026   EVEX_W_0F10_P_1_M_1,
2027   EVEX_W_0F10_P_2,
2028   EVEX_W_0F10_P_3_M_0,
2029   EVEX_W_0F10_P_3_M_1,
2030   EVEX_W_0F11_P_0,
2031   EVEX_W_0F11_P_1_M_0,
2032   EVEX_W_0F11_P_1_M_1,
2033   EVEX_W_0F11_P_2,
2034   EVEX_W_0F11_P_3_M_0,
2035   EVEX_W_0F11_P_3_M_1,
2036   EVEX_W_0F12_P_0_M_0,
2037   EVEX_W_0F12_P_0_M_1,
2038   EVEX_W_0F12_P_1,
2039   EVEX_W_0F12_P_2,
2040   EVEX_W_0F12_P_3,
2041   EVEX_W_0F13_P_0,
2042   EVEX_W_0F13_P_2,
2043   EVEX_W_0F14_P_0,
2044   EVEX_W_0F14_P_2,
2045   EVEX_W_0F15_P_0,
2046   EVEX_W_0F15_P_2,
2047   EVEX_W_0F16_P_0_M_0,
2048   EVEX_W_0F16_P_0_M_1,
2049   EVEX_W_0F16_P_1,
2050   EVEX_W_0F16_P_2,
2051   EVEX_W_0F17_P_0,
2052   EVEX_W_0F17_P_2,
2053   EVEX_W_0F28_P_0,
2054   EVEX_W_0F28_P_2,
2055   EVEX_W_0F29_P_0,
2056   EVEX_W_0F29_P_2,
2057   EVEX_W_0F2A_P_1,
2058   EVEX_W_0F2A_P_3,
2059   EVEX_W_0F2B_P_0,
2060   EVEX_W_0F2B_P_2,
2061   EVEX_W_0F2E_P_0,
2062   EVEX_W_0F2E_P_2,
2063   EVEX_W_0F2F_P_0,
2064   EVEX_W_0F2F_P_2,
2065   EVEX_W_0F51_P_0,
2066   EVEX_W_0F51_P_1,
2067   EVEX_W_0F51_P_2,
2068   EVEX_W_0F51_P_3,
2069   EVEX_W_0F54_P_0,
2070   EVEX_W_0F54_P_2,
2071   EVEX_W_0F55_P_0,
2072   EVEX_W_0F55_P_2,
2073   EVEX_W_0F56_P_0,
2074   EVEX_W_0F56_P_2,
2075   EVEX_W_0F57_P_0,
2076   EVEX_W_0F57_P_2,
2077   EVEX_W_0F58_P_0,
2078   EVEX_W_0F58_P_1,
2079   EVEX_W_0F58_P_2,
2080   EVEX_W_0F58_P_3,
2081   EVEX_W_0F59_P_0,
2082   EVEX_W_0F59_P_1,
2083   EVEX_W_0F59_P_2,
2084   EVEX_W_0F59_P_3,
2085   EVEX_W_0F5A_P_0,
2086   EVEX_W_0F5A_P_1,
2087   EVEX_W_0F5A_P_2,
2088   EVEX_W_0F5A_P_3,
2089   EVEX_W_0F5B_P_0,
2090   EVEX_W_0F5B_P_1,
2091   EVEX_W_0F5B_P_2,
2092   EVEX_W_0F5C_P_0,
2093   EVEX_W_0F5C_P_1,
2094   EVEX_W_0F5C_P_2,
2095   EVEX_W_0F5C_P_3,
2096   EVEX_W_0F5D_P_0,
2097   EVEX_W_0F5D_P_1,
2098   EVEX_W_0F5D_P_2,
2099   EVEX_W_0F5D_P_3,
2100   EVEX_W_0F5E_P_0,
2101   EVEX_W_0F5E_P_1,
2102   EVEX_W_0F5E_P_2,
2103   EVEX_W_0F5E_P_3,
2104   EVEX_W_0F5F_P_0,
2105   EVEX_W_0F5F_P_1,
2106   EVEX_W_0F5F_P_2,
2107   EVEX_W_0F5F_P_3,
2108   EVEX_W_0F62_P_2,
2109   EVEX_W_0F66_P_2,
2110   EVEX_W_0F6A_P_2,
2111   EVEX_W_0F6B_P_2,
2112   EVEX_W_0F6C_P_2,
2113   EVEX_W_0F6D_P_2,
2114   EVEX_W_0F6F_P_1,
2115   EVEX_W_0F6F_P_2,
2116   EVEX_W_0F6F_P_3,
2117   EVEX_W_0F70_P_2,
2118   EVEX_W_0F72_R_2_P_2,
2119   EVEX_W_0F72_R_6_P_2,
2120   EVEX_W_0F73_R_2_P_2,
2121   EVEX_W_0F73_R_6_P_2,
2122   EVEX_W_0F76_P_2,
2123   EVEX_W_0F78_P_0,
2124   EVEX_W_0F78_P_2,
2125   EVEX_W_0F79_P_0,
2126   EVEX_W_0F79_P_2,
2127   EVEX_W_0F7A_P_1,
2128   EVEX_W_0F7A_P_2,
2129   EVEX_W_0F7A_P_3,
2130   EVEX_W_0F7B_P_1,
2131   EVEX_W_0F7B_P_2,
2132   EVEX_W_0F7B_P_3,
2133   EVEX_W_0F7E_P_1,
2134   EVEX_W_0F7F_P_1,
2135   EVEX_W_0F7F_P_2,
2136   EVEX_W_0F7F_P_3,
2137   EVEX_W_0FC2_P_0,
2138   EVEX_W_0FC2_P_1,
2139   EVEX_W_0FC2_P_2,
2140   EVEX_W_0FC2_P_3,
2141   EVEX_W_0FC6_P_0,
2142   EVEX_W_0FC6_P_2,
2143   EVEX_W_0FD2_P_2,
2144   EVEX_W_0FD3_P_2,
2145   EVEX_W_0FD4_P_2,
2146   EVEX_W_0FD6_P_2,
2147   EVEX_W_0FE6_P_1,
2148   EVEX_W_0FE6_P_2,
2149   EVEX_W_0FE6_P_3,
2150   EVEX_W_0FE7_P_2,
2151   EVEX_W_0FF2_P_2,
2152   EVEX_W_0FF3_P_2,
2153   EVEX_W_0FF4_P_2,
2154   EVEX_W_0FFA_P_2,
2155   EVEX_W_0FFB_P_2,
2156   EVEX_W_0FFE_P_2,
2157   EVEX_W_0F380C_P_2,
2158   EVEX_W_0F380D_P_2,
2159   EVEX_W_0F3810_P_1,
2160   EVEX_W_0F3810_P_2,
2161   EVEX_W_0F3811_P_1,
2162   EVEX_W_0F3811_P_2,
2163   EVEX_W_0F3812_P_1,
2164   EVEX_W_0F3812_P_2,
2165   EVEX_W_0F3813_P_1,
2166   EVEX_W_0F3813_P_2,
2167   EVEX_W_0F3814_P_1,
2168   EVEX_W_0F3815_P_1,
2169   EVEX_W_0F3818_P_2,
2170   EVEX_W_0F3819_P_2,
2171   EVEX_W_0F381A_P_2,
2172   EVEX_W_0F381B_P_2,
2173   EVEX_W_0F381E_P_2,
2174   EVEX_W_0F381F_P_2,
2175   EVEX_W_0F3820_P_1,
2176   EVEX_W_0F3821_P_1,
2177   EVEX_W_0F3822_P_1,
2178   EVEX_W_0F3823_P_1,
2179   EVEX_W_0F3824_P_1,
2180   EVEX_W_0F3825_P_1,
2181   EVEX_W_0F3825_P_2,
2182   EVEX_W_0F3826_P_1,
2183   EVEX_W_0F3826_P_2,
2184   EVEX_W_0F3828_P_1,
2185   EVEX_W_0F3828_P_2,
2186   EVEX_W_0F3829_P_1,
2187   EVEX_W_0F3829_P_2,
2188   EVEX_W_0F382A_P_1,
2189   EVEX_W_0F382A_P_2,
2190   EVEX_W_0F382B_P_2,
2191   EVEX_W_0F3830_P_1,
2192   EVEX_W_0F3831_P_1,
2193   EVEX_W_0F3832_P_1,
2194   EVEX_W_0F3833_P_1,
2195   EVEX_W_0F3834_P_1,
2196   EVEX_W_0F3835_P_1,
2197   EVEX_W_0F3835_P_2,
2198   EVEX_W_0F3837_P_2,
2199   EVEX_W_0F3838_P_1,
2200   EVEX_W_0F3839_P_1,
2201   EVEX_W_0F383A_P_1,
2202   EVEX_W_0F3840_P_2,
2203   EVEX_W_0F3852_P_1,
2204   EVEX_W_0F3854_P_2,
2205   EVEX_W_0F3855_P_2,
2206   EVEX_W_0F3858_P_2,
2207   EVEX_W_0F3859_P_2,
2208   EVEX_W_0F385A_P_2,
2209   EVEX_W_0F385B_P_2,
2210   EVEX_W_0F3862_P_2,
2211   EVEX_W_0F3863_P_2,
2212   EVEX_W_0F3866_P_2,
2213   EVEX_W_0F3868_P_3,
2214   EVEX_W_0F3870_P_2,
2215   EVEX_W_0F3871_P_2,
2216   EVEX_W_0F3872_P_1,
2217   EVEX_W_0F3872_P_2,
2218   EVEX_W_0F3872_P_3,
2219   EVEX_W_0F3873_P_2,
2220   EVEX_W_0F3875_P_2,
2221   EVEX_W_0F3878_P_2,
2222   EVEX_W_0F3879_P_2,
2223   EVEX_W_0F387A_P_2,
2224   EVEX_W_0F387B_P_2,
2225   EVEX_W_0F387D_P_2,
2226   EVEX_W_0F3883_P_2,
2227   EVEX_W_0F388D_P_2,
2228   EVEX_W_0F3891_P_2,
2229   EVEX_W_0F3893_P_2,
2230   EVEX_W_0F38A1_P_2,
2231   EVEX_W_0F38A3_P_2,
2232   EVEX_W_0F38C7_R_1_P_2,
2233   EVEX_W_0F38C7_R_2_P_2,
2234   EVEX_W_0F38C7_R_5_P_2,
2235   EVEX_W_0F38C7_R_6_P_2,
2236
2237   EVEX_W_0F3A00_P_2,
2238   EVEX_W_0F3A01_P_2,
2239   EVEX_W_0F3A04_P_2,
2240   EVEX_W_0F3A05_P_2,
2241   EVEX_W_0F3A08_P_2,
2242   EVEX_W_0F3A09_P_2,
2243   EVEX_W_0F3A0A_P_2,
2244   EVEX_W_0F3A0B_P_2,
2245   EVEX_W_0F3A18_P_2,
2246   EVEX_W_0F3A19_P_2,
2247   EVEX_W_0F3A1A_P_2,
2248   EVEX_W_0F3A1B_P_2,
2249   EVEX_W_0F3A1D_P_2,
2250   EVEX_W_0F3A21_P_2,
2251   EVEX_W_0F3A23_P_2,
2252   EVEX_W_0F3A38_P_2,
2253   EVEX_W_0F3A39_P_2,
2254   EVEX_W_0F3A3A_P_2,
2255   EVEX_W_0F3A3B_P_2,
2256   EVEX_W_0F3A3E_P_2,
2257   EVEX_W_0F3A3F_P_2,
2258   EVEX_W_0F3A42_P_2,
2259   EVEX_W_0F3A43_P_2,
2260   EVEX_W_0F3A50_P_2,
2261   EVEX_W_0F3A51_P_2,
2262   EVEX_W_0F3A56_P_2,
2263   EVEX_W_0F3A57_P_2,
2264   EVEX_W_0F3A66_P_2,
2265   EVEX_W_0F3A67_P_2,
2266   EVEX_W_0F3A70_P_2,
2267   EVEX_W_0F3A71_P_2,
2268   EVEX_W_0F3A72_P_2,
2269   EVEX_W_0F3A73_P_2,
2270   EVEX_W_0F3ACE_P_2,
2271   EVEX_W_0F3ACF_P_2
2272 };
2273
2274 typedef void (*op_rtn) (int bytemode, int sizeflag);
2275
2276 struct dis386 {
2277   const char *name;
2278   struct
2279     {
2280       op_rtn rtn;
2281       int bytemode;
2282     } op[MAX_OPERANDS];
2283   unsigned int prefix_requirement;
2284 };
2285
2286 /* Upper case letters in the instruction names here are macros.
2287    'A' => print 'b' if no register operands or suffix_always is true
2288    'B' => print 'b' if suffix_always is true
2289    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2290           size prefix
2291    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2292           suffix_always is true
2293    'E' => print 'e' if 32-bit form of jcxz
2294    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2295    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2296    'H' => print ",pt" or ",pn" branch hint
2297    'I' => honor following macro letter even in Intel mode (implemented only
2298           for some of the macro letters)
2299    'J' => print 'l'
2300    'K' => print 'd' or 'q' if rex prefix is present.
2301    'L' => print 'l' if suffix_always is true
2302    'M' => print 'r' if intel_mnemonic is false.
2303    'N' => print 'n' if instruction has no wait "prefix"
2304    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2305    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2306           or suffix_always is true.  print 'q' if rex prefix is present.
2307    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2308           is true
2309    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2310    'S' => print 'w', 'l' or 'q' if suffix_always is true
2311    'T' => print 'q' in 64bit mode if instruction has no operand size
2312           prefix and behave as 'P' otherwise
2313    'U' => print 'q' in 64bit mode if instruction has no operand size
2314           prefix and behave as 'Q' otherwise
2315    'V' => print 'q' in 64bit mode if instruction has no operand size
2316           prefix and behave as 'S' otherwise
2317    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2318    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2319    'Y' unused.
2320    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2321    '!' => change condition from true to false or from false to true.
2322    '%' => add 1 upper case letter to the macro.
2323    '^' => print 'w' or 'l' depending on operand size prefix or
2324           suffix_always is true (lcall/ljmp).
2325    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2326           on operand size prefix.
2327    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2328           has no operand size prefix for AMD64 ISA, behave as 'P'
2329           otherwise
2330
2331    2 upper case letter macros:
2332    "XY" => print 'x' or 'y' if suffix_always is true or no register
2333            operands and no broadcast.
2334    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2335            register operands and no broadcast.
2336    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2337    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2338            or suffix_always is true
2339    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2340    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2341    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2342    "LW" => print 'd', 'q' depending on the VEX.W bit
2343    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2344            an operand size prefix, or suffix_always is true.  print
2345            'q' if rex prefix is present.
2346
2347    Many of the above letters print nothing in Intel mode.  See "putop"
2348    for the details.
2349
2350    Braces '{' and '}', and vertical bars '|', indicate alternative
2351    mnemonic strings for AT&T and Intel.  */
2352
2353 static const struct dis386 dis386[] = {
2354   /* 00 */
2355   { "addB",             { Ebh1, Gb }, 0 },
2356   { "addS",             { Evh1, Gv }, 0 },
2357   { "addB",             { Gb, EbS }, 0 },
2358   { "addS",             { Gv, EvS }, 0 },
2359   { "addB",             { AL, Ib }, 0 },
2360   { "addS",             { eAX, Iv }, 0 },
2361   { X86_64_TABLE (X86_64_06) },
2362   { X86_64_TABLE (X86_64_07) },
2363   /* 08 */
2364   { "orB",              { Ebh1, Gb }, 0 },
2365   { "orS",              { Evh1, Gv }, 0 },
2366   { "orB",              { Gb, EbS }, 0 },
2367   { "orS",              { Gv, EvS }, 0 },
2368   { "orB",              { AL, Ib }, 0 },
2369   { "orS",              { eAX, Iv }, 0 },
2370   { X86_64_TABLE (X86_64_0D) },
2371   { Bad_Opcode },       /* 0x0f extended opcode escape */
2372   /* 10 */
2373   { "adcB",             { Ebh1, Gb }, 0 },
2374   { "adcS",             { Evh1, Gv }, 0 },
2375   { "adcB",             { Gb, EbS }, 0 },
2376   { "adcS",             { Gv, EvS }, 0 },
2377   { "adcB",             { AL, Ib }, 0 },
2378   { "adcS",             { eAX, Iv }, 0 },
2379   { X86_64_TABLE (X86_64_16) },
2380   { X86_64_TABLE (X86_64_17) },
2381   /* 18 */
2382   { "sbbB",             { Ebh1, Gb }, 0 },
2383   { "sbbS",             { Evh1, Gv }, 0 },
2384   { "sbbB",             { Gb, EbS }, 0 },
2385   { "sbbS",             { Gv, EvS }, 0 },
2386   { "sbbB",             { AL, Ib }, 0 },
2387   { "sbbS",             { eAX, Iv }, 0 },
2388   { X86_64_TABLE (X86_64_1E) },
2389   { X86_64_TABLE (X86_64_1F) },
2390   /* 20 */
2391   { "andB",             { Ebh1, Gb }, 0 },
2392   { "andS",             { Evh1, Gv }, 0 },
2393   { "andB",             { Gb, EbS }, 0 },
2394   { "andS",             { Gv, EvS }, 0 },
2395   { "andB",             { AL, Ib }, 0 },
2396   { "andS",             { eAX, Iv }, 0 },
2397   { Bad_Opcode },       /* SEG ES prefix */
2398   { X86_64_TABLE (X86_64_27) },
2399   /* 28 */
2400   { "subB",             { Ebh1, Gb }, 0 },
2401   { "subS",             { Evh1, Gv }, 0 },
2402   { "subB",             { Gb, EbS }, 0 },
2403   { "subS",             { Gv, EvS }, 0 },
2404   { "subB",             { AL, Ib }, 0 },
2405   { "subS",             { eAX, Iv }, 0 },
2406   { Bad_Opcode },       /* SEG CS prefix */
2407   { X86_64_TABLE (X86_64_2F) },
2408   /* 30 */
2409   { "xorB",             { Ebh1, Gb }, 0 },
2410   { "xorS",             { Evh1, Gv }, 0 },
2411   { "xorB",             { Gb, EbS }, 0 },
2412   { "xorS",             { Gv, EvS }, 0 },
2413   { "xorB",             { AL, Ib }, 0 },
2414   { "xorS",             { eAX, Iv }, 0 },
2415   { Bad_Opcode },       /* SEG SS prefix */
2416   { X86_64_TABLE (X86_64_37) },
2417   /* 38 */
2418   { "cmpB",             { Eb, Gb }, 0 },
2419   { "cmpS",             { Ev, Gv }, 0 },
2420   { "cmpB",             { Gb, EbS }, 0 },
2421   { "cmpS",             { Gv, EvS }, 0 },
2422   { "cmpB",             { AL, Ib }, 0 },
2423   { "cmpS",             { eAX, Iv }, 0 },
2424   { Bad_Opcode },       /* SEG DS prefix */
2425   { X86_64_TABLE (X86_64_3F) },
2426   /* 40 */
2427   { "inc{S|}",          { RMeAX }, 0 },
2428   { "inc{S|}",          { RMeCX }, 0 },
2429   { "inc{S|}",          { RMeDX }, 0 },
2430   { "inc{S|}",          { RMeBX }, 0 },
2431   { "inc{S|}",          { RMeSP }, 0 },
2432   { "inc{S|}",          { RMeBP }, 0 },
2433   { "inc{S|}",          { RMeSI }, 0 },
2434   { "inc{S|}",          { RMeDI }, 0 },
2435   /* 48 */
2436   { "dec{S|}",          { RMeAX }, 0 },
2437   { "dec{S|}",          { RMeCX }, 0 },
2438   { "dec{S|}",          { RMeDX }, 0 },
2439   { "dec{S|}",          { RMeBX }, 0 },
2440   { "dec{S|}",          { RMeSP }, 0 },
2441   { "dec{S|}",          { RMeBP }, 0 },
2442   { "dec{S|}",          { RMeSI }, 0 },
2443   { "dec{S|}",          { RMeDI }, 0 },
2444   /* 50 */
2445   { "pushV",            { RMrAX }, 0 },
2446   { "pushV",            { RMrCX }, 0 },
2447   { "pushV",            { RMrDX }, 0 },
2448   { "pushV",            { RMrBX }, 0 },
2449   { "pushV",            { RMrSP }, 0 },
2450   { "pushV",            { RMrBP }, 0 },
2451   { "pushV",            { RMrSI }, 0 },
2452   { "pushV",            { RMrDI }, 0 },
2453   /* 58 */
2454   { "popV",             { RMrAX }, 0 },
2455   { "popV",             { RMrCX }, 0 },
2456   { "popV",             { RMrDX }, 0 },
2457   { "popV",             { RMrBX }, 0 },
2458   { "popV",             { RMrSP }, 0 },
2459   { "popV",             { RMrBP }, 0 },
2460   { "popV",             { RMrSI }, 0 },
2461   { "popV",             { RMrDI }, 0 },
2462   /* 60 */
2463   { X86_64_TABLE (X86_64_60) },
2464   { X86_64_TABLE (X86_64_61) },
2465   { X86_64_TABLE (X86_64_62) },
2466   { X86_64_TABLE (X86_64_63) },
2467   { Bad_Opcode },       /* seg fs */
2468   { Bad_Opcode },       /* seg gs */
2469   { Bad_Opcode },       /* op size prefix */
2470   { Bad_Opcode },       /* adr size prefix */
2471   /* 68 */
2472   { "pushT",            { sIv }, 0 },
2473   { "imulS",            { Gv, Ev, Iv }, 0 },
2474   { "pushT",            { sIbT }, 0 },
2475   { "imulS",            { Gv, Ev, sIb }, 0 },
2476   { "ins{b|}",          { Ybr, indirDX }, 0 },
2477   { X86_64_TABLE (X86_64_6D) },
2478   { "outs{b|}",         { indirDXr, Xb }, 0 },
2479   { X86_64_TABLE (X86_64_6F) },
2480   /* 70 */
2481   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2482   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2483   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2484   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2485   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2486   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2487   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2488   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2489   /* 78 */
2490   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2491   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2492   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2498   /* 80 */
2499   { REG_TABLE (REG_80) },
2500   { REG_TABLE (REG_81) },
2501   { X86_64_TABLE (X86_64_82) },
2502   { REG_TABLE (REG_83) },
2503   { "testB",            { Eb, Gb }, 0 },
2504   { "testS",            { Ev, Gv }, 0 },
2505   { "xchgB",            { Ebh2, Gb }, 0 },
2506   { "xchgS",            { Evh2, Gv }, 0 },
2507   /* 88 */
2508   { "movB",             { Ebh3, Gb }, 0 },
2509   { "movS",             { Evh3, Gv }, 0 },
2510   { "movB",             { Gb, EbS }, 0 },
2511   { "movS",             { Gv, EvS }, 0 },
2512   { "movD",             { Sv, Sw }, 0 },
2513   { MOD_TABLE (MOD_8D) },
2514   { "movD",             { Sw, Sv }, 0 },
2515   { REG_TABLE (REG_8F) },
2516   /* 90 */
2517   { PREFIX_TABLE (PREFIX_90) },
2518   { "xchgS",            { RMeCX, eAX }, 0 },
2519   { "xchgS",            { RMeDX, eAX }, 0 },
2520   { "xchgS",            { RMeBX, eAX }, 0 },
2521   { "xchgS",            { RMeSP, eAX }, 0 },
2522   { "xchgS",            { RMeBP, eAX }, 0 },
2523   { "xchgS",            { RMeSI, eAX }, 0 },
2524   { "xchgS",            { RMeDI, eAX }, 0 },
2525   /* 98 */
2526   { "cW{t|}R",          { XX }, 0 },
2527   { "cR{t|}O",          { XX }, 0 },
2528   { X86_64_TABLE (X86_64_9A) },
2529   { Bad_Opcode },       /* fwait */
2530   { "pushfT",           { XX }, 0 },
2531   { "popfT",            { XX }, 0 },
2532   { "sahf",             { XX }, 0 },
2533   { "lahf",             { XX }, 0 },
2534   /* a0 */
2535   { "mov%LB",           { AL, Ob }, 0 },
2536   { "mov%LS",           { eAX, Ov }, 0 },
2537   { "mov%LB",           { Ob, AL }, 0 },
2538   { "mov%LS",           { Ov, eAX }, 0 },
2539   { "movs{b|}",         { Ybr, Xb }, 0 },
2540   { "movs{R|}",         { Yvr, Xv }, 0 },
2541   { "cmps{b|}",         { Xb, Yb }, 0 },
2542   { "cmps{R|}",         { Xv, Yv }, 0 },
2543   /* a8 */
2544   { "testB",            { AL, Ib }, 0 },
2545   { "testS",            { eAX, Iv }, 0 },
2546   { "stosB",            { Ybr, AL }, 0 },
2547   { "stosS",            { Yvr, eAX }, 0 },
2548   { "lodsB",            { ALr, Xb }, 0 },
2549   { "lodsS",            { eAXr, Xv }, 0 },
2550   { "scasB",            { AL, Yb }, 0 },
2551   { "scasS",            { eAX, Yv }, 0 },
2552   /* b0 */
2553   { "movB",             { RMAL, Ib }, 0 },
2554   { "movB",             { RMCL, Ib }, 0 },
2555   { "movB",             { RMDL, Ib }, 0 },
2556   { "movB",             { RMBL, Ib }, 0 },
2557   { "movB",             { RMAH, Ib }, 0 },
2558   { "movB",             { RMCH, Ib }, 0 },
2559   { "movB",             { RMDH, Ib }, 0 },
2560   { "movB",             { RMBH, Ib }, 0 },
2561   /* b8 */
2562   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2563   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2564   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2565   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2566   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2567   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2568   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2569   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2570   /* c0 */
2571   { REG_TABLE (REG_C0) },
2572   { REG_TABLE (REG_C1) },
2573   { "retT",             { Iw, BND }, 0 },
2574   { "retT",             { BND }, 0 },
2575   { X86_64_TABLE (X86_64_C4) },
2576   { X86_64_TABLE (X86_64_C5) },
2577   { REG_TABLE (REG_C6) },
2578   { REG_TABLE (REG_C7) },
2579   /* c8 */
2580   { "enterT",           { Iw, Ib }, 0 },
2581   { "leaveT",           { XX }, 0 },
2582   { "Jret{|f}P",        { Iw }, 0 },
2583   { "Jret{|f}P",        { XX }, 0 },
2584   { "int3",             { XX }, 0 },
2585   { "int",              { Ib }, 0 },
2586   { X86_64_TABLE (X86_64_CE) },
2587   { "iret%LP",          { XX }, 0 },
2588   /* d0 */
2589   { REG_TABLE (REG_D0) },
2590   { REG_TABLE (REG_D1) },
2591   { REG_TABLE (REG_D2) },
2592   { REG_TABLE (REG_D3) },
2593   { X86_64_TABLE (X86_64_D4) },
2594   { X86_64_TABLE (X86_64_D5) },
2595   { Bad_Opcode },
2596   { "xlat",             { DSBX }, 0 },
2597   /* d8 */
2598   { FLOAT },
2599   { FLOAT },
2600   { FLOAT },
2601   { FLOAT },
2602   { FLOAT },
2603   { FLOAT },
2604   { FLOAT },
2605   { FLOAT },
2606   /* e0 */
2607   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2608   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2609   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2610   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2611   { "inB",              { AL, Ib }, 0 },
2612   { "inG",              { zAX, Ib }, 0 },
2613   { "outB",             { Ib, AL }, 0 },
2614   { "outG",             { Ib, zAX }, 0 },
2615   /* e8 */
2616   { X86_64_TABLE (X86_64_E8) },
2617   { X86_64_TABLE (X86_64_E9) },
2618   { X86_64_TABLE (X86_64_EA) },
2619   { "jmp",              { Jb, BND }, 0 },
2620   { "inB",              { AL, indirDX }, 0 },
2621   { "inG",              { zAX, indirDX }, 0 },
2622   { "outB",             { indirDX, AL }, 0 },
2623   { "outG",             { indirDX, zAX }, 0 },
2624   /* f0 */
2625   { Bad_Opcode },       /* lock prefix */
2626   { "icebp",            { XX }, 0 },
2627   { Bad_Opcode },       /* repne */
2628   { Bad_Opcode },       /* repz */
2629   { "hlt",              { XX }, 0 },
2630   { "cmc",              { XX }, 0 },
2631   { REG_TABLE (REG_F6) },
2632   { REG_TABLE (REG_F7) },
2633   /* f8 */
2634   { "clc",              { XX }, 0 },
2635   { "stc",              { XX }, 0 },
2636   { "cli",              { XX }, 0 },
2637   { "sti",              { XX }, 0 },
2638   { "cld",              { XX }, 0 },
2639   { "std",              { XX }, 0 },
2640   { REG_TABLE (REG_FE) },
2641   { REG_TABLE (REG_FF) },
2642 };
2643
2644 static const struct dis386 dis386_twobyte[] = {
2645   /* 00 */
2646   { REG_TABLE (REG_0F00 ) },
2647   { REG_TABLE (REG_0F01 ) },
2648   { "larS",             { Gv, Ew }, 0 },
2649   { "lslS",             { Gv, Ew }, 0 },
2650   { Bad_Opcode },
2651   { "syscall",          { XX }, 0 },
2652   { "clts",             { XX }, 0 },
2653   { "sysret%LP",                { XX }, 0 },
2654   /* 08 */
2655   { "invd",             { XX }, 0 },
2656   { PREFIX_TABLE (PREFIX_0F09) },
2657   { Bad_Opcode },
2658   { "ud2",              { XX }, 0 },
2659   { Bad_Opcode },
2660   { REG_TABLE (REG_0F0D) },
2661   { "femms",            { XX }, 0 },
2662   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2663   /* 10 */
2664   { PREFIX_TABLE (PREFIX_0F10) },
2665   { PREFIX_TABLE (PREFIX_0F11) },
2666   { PREFIX_TABLE (PREFIX_0F12) },
2667   { MOD_TABLE (MOD_0F13) },
2668   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2669   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2670   { PREFIX_TABLE (PREFIX_0F16) },
2671   { MOD_TABLE (MOD_0F17) },
2672   /* 18 */
2673   { REG_TABLE (REG_0F18) },
2674   { "nopQ",             { Ev }, 0 },
2675   { PREFIX_TABLE (PREFIX_0F1A) },
2676   { PREFIX_TABLE (PREFIX_0F1B) },
2677   { PREFIX_TABLE (PREFIX_0F1C) },
2678   { "nopQ",             { Ev }, 0 },
2679   { PREFIX_TABLE (PREFIX_0F1E) },
2680   { "nopQ",             { Ev }, 0 },
2681   /* 20 */
2682   { "movZ",             { Rm, Cm }, 0 },
2683   { "movZ",             { Rm, Dm }, 0 },
2684   { "movZ",             { Cm, Rm }, 0 },
2685   { "movZ",             { Dm, Rm }, 0 },
2686   { MOD_TABLE (MOD_0F24) },
2687   { Bad_Opcode },
2688   { MOD_TABLE (MOD_0F26) },
2689   { Bad_Opcode },
2690   /* 28 */
2691   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2692   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2693   { PREFIX_TABLE (PREFIX_0F2A) },
2694   { PREFIX_TABLE (PREFIX_0F2B) },
2695   { PREFIX_TABLE (PREFIX_0F2C) },
2696   { PREFIX_TABLE (PREFIX_0F2D) },
2697   { PREFIX_TABLE (PREFIX_0F2E) },
2698   { PREFIX_TABLE (PREFIX_0F2F) },
2699   /* 30 */
2700   { "wrmsr",            { XX }, 0 },
2701   { "rdtsc",            { XX }, 0 },
2702   { "rdmsr",            { XX }, 0 },
2703   { "rdpmc",            { XX }, 0 },
2704   { "sysenter",         { XX }, 0 },
2705   { "sysexit",          { XX }, 0 },
2706   { Bad_Opcode },
2707   { "getsec",           { XX }, 0 },
2708   /* 38 */
2709   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2710   { Bad_Opcode },
2711   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2712   { Bad_Opcode },
2713   { Bad_Opcode },
2714   { Bad_Opcode },
2715   { Bad_Opcode },
2716   { Bad_Opcode },
2717   /* 40 */
2718   { "cmovoS",           { Gv, Ev }, 0 },
2719   { "cmovnoS",          { Gv, Ev }, 0 },
2720   { "cmovbS",           { Gv, Ev }, 0 },
2721   { "cmovaeS",          { Gv, Ev }, 0 },
2722   { "cmoveS",           { Gv, Ev }, 0 },
2723   { "cmovneS",          { Gv, Ev }, 0 },
2724   { "cmovbeS",          { Gv, Ev }, 0 },
2725   { "cmovaS",           { Gv, Ev }, 0 },
2726   /* 48 */
2727   { "cmovsS",           { Gv, Ev }, 0 },
2728   { "cmovnsS",          { Gv, Ev }, 0 },
2729   { "cmovpS",           { Gv, Ev }, 0 },
2730   { "cmovnpS",          { Gv, Ev }, 0 },
2731   { "cmovlS",           { Gv, Ev }, 0 },
2732   { "cmovgeS",          { Gv, Ev }, 0 },
2733   { "cmovleS",          { Gv, Ev }, 0 },
2734   { "cmovgS",           { Gv, Ev }, 0 },
2735   /* 50 */
2736   { MOD_TABLE (MOD_0F51) },
2737   { PREFIX_TABLE (PREFIX_0F51) },
2738   { PREFIX_TABLE (PREFIX_0F52) },
2739   { PREFIX_TABLE (PREFIX_0F53) },
2740   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2741   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2742   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2743   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2744   /* 58 */
2745   { PREFIX_TABLE (PREFIX_0F58) },
2746   { PREFIX_TABLE (PREFIX_0F59) },
2747   { PREFIX_TABLE (PREFIX_0F5A) },
2748   { PREFIX_TABLE (PREFIX_0F5B) },
2749   { PREFIX_TABLE (PREFIX_0F5C) },
2750   { PREFIX_TABLE (PREFIX_0F5D) },
2751   { PREFIX_TABLE (PREFIX_0F5E) },
2752   { PREFIX_TABLE (PREFIX_0F5F) },
2753   /* 60 */
2754   { PREFIX_TABLE (PREFIX_0F60) },
2755   { PREFIX_TABLE (PREFIX_0F61) },
2756   { PREFIX_TABLE (PREFIX_0F62) },
2757   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2758   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2759   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2760   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2761   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2762   /* 68 */
2763   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2764   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2765   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2766   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2767   { PREFIX_TABLE (PREFIX_0F6C) },
2768   { PREFIX_TABLE (PREFIX_0F6D) },
2769   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2770   { PREFIX_TABLE (PREFIX_0F6F) },
2771   /* 70 */
2772   { PREFIX_TABLE (PREFIX_0F70) },
2773   { REG_TABLE (REG_0F71) },
2774   { REG_TABLE (REG_0F72) },
2775   { REG_TABLE (REG_0F73) },
2776   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2777   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2778   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2779   { "emms",             { XX }, PREFIX_OPCODE },
2780   /* 78 */
2781   { PREFIX_TABLE (PREFIX_0F78) },
2782   { PREFIX_TABLE (PREFIX_0F79) },
2783   { Bad_Opcode },
2784   { Bad_Opcode },
2785   { PREFIX_TABLE (PREFIX_0F7C) },
2786   { PREFIX_TABLE (PREFIX_0F7D) },
2787   { PREFIX_TABLE (PREFIX_0F7E) },
2788   { PREFIX_TABLE (PREFIX_0F7F) },
2789   /* 80 */
2790   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2791   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2792   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2793   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2794   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2795   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2796   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2797   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2798   /* 88 */
2799   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2800   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2801   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2807   /* 90 */
2808   { "seto",             { Eb }, 0 },
2809   { "setno",            { Eb }, 0 },
2810   { "setb",             { Eb }, 0 },
2811   { "setae",            { Eb }, 0 },
2812   { "sete",             { Eb }, 0 },
2813   { "setne",            { Eb }, 0 },
2814   { "setbe",            { Eb }, 0 },
2815   { "seta",             { Eb }, 0 },
2816   /* 98 */
2817   { "sets",             { Eb }, 0 },
2818   { "setns",            { Eb }, 0 },
2819   { "setp",             { Eb }, 0 },
2820   { "setnp",            { Eb }, 0 },
2821   { "setl",             { Eb }, 0 },
2822   { "setge",            { Eb }, 0 },
2823   { "setle",            { Eb }, 0 },
2824   { "setg",             { Eb }, 0 },
2825   /* a0 */
2826   { "pushT",            { fs }, 0 },
2827   { "popT",             { fs }, 0 },
2828   { "cpuid",            { XX }, 0 },
2829   { "btS",              { Ev, Gv }, 0 },
2830   { "shldS",            { Ev, Gv, Ib }, 0 },
2831   { "shldS",            { Ev, Gv, CL }, 0 },
2832   { REG_TABLE (REG_0FA6) },
2833   { REG_TABLE (REG_0FA7) },
2834   /* a8 */
2835   { "pushT",            { gs }, 0 },
2836   { "popT",             { gs }, 0 },
2837   { "rsm",              { XX }, 0 },
2838   { "btsS",             { Evh1, Gv }, 0 },
2839   { "shrdS",            { Ev, Gv, Ib }, 0 },
2840   { "shrdS",            { Ev, Gv, CL }, 0 },
2841   { REG_TABLE (REG_0FAE) },
2842   { "imulS",            { Gv, Ev }, 0 },
2843   /* b0 */
2844   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2845   { "cmpxchgS",         { Evh1, Gv }, 0 },
2846   { MOD_TABLE (MOD_0FB2) },
2847   { "btrS",             { Evh1, Gv }, 0 },
2848   { MOD_TABLE (MOD_0FB4) },
2849   { MOD_TABLE (MOD_0FB5) },
2850   { "movz{bR|x}",       { Gv, Eb }, 0 },
2851   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2852   /* b8 */
2853   { PREFIX_TABLE (PREFIX_0FB8) },
2854   { "ud1S",             { Gv, Ev }, 0 },
2855   { REG_TABLE (REG_0FBA) },
2856   { "btcS",             { Evh1, Gv }, 0 },
2857   { PREFIX_TABLE (PREFIX_0FBC) },
2858   { PREFIX_TABLE (PREFIX_0FBD) },
2859   { "movs{bR|x}",       { Gv, Eb }, 0 },
2860   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2861   /* c0 */
2862   { "xaddB",            { Ebh1, Gb }, 0 },
2863   { "xaddS",            { Evh1, Gv }, 0 },
2864   { PREFIX_TABLE (PREFIX_0FC2) },
2865   { MOD_TABLE (MOD_0FC3) },
2866   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2867   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2868   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2869   { REG_TABLE (REG_0FC7) },
2870   /* c8 */
2871   { "bswap",            { RMeAX }, 0 },
2872   { "bswap",            { RMeCX }, 0 },
2873   { "bswap",            { RMeDX }, 0 },
2874   { "bswap",            { RMeBX }, 0 },
2875   { "bswap",            { RMeSP }, 0 },
2876   { "bswap",            { RMeBP }, 0 },
2877   { "bswap",            { RMeSI }, 0 },
2878   { "bswap",            { RMeDI }, 0 },
2879   /* d0 */
2880   { PREFIX_TABLE (PREFIX_0FD0) },
2881   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2882   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2883   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2884   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2885   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2886   { PREFIX_TABLE (PREFIX_0FD6) },
2887   { MOD_TABLE (MOD_0FD7) },
2888   /* d8 */
2889   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2890   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2891   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2892   { "pand",             { MX, EM }, PREFIX_OPCODE },
2893   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2894   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2895   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2896   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2897   /* e0 */
2898   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2899   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2900   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2901   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2902   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2903   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2904   { PREFIX_TABLE (PREFIX_0FE6) },
2905   { PREFIX_TABLE (PREFIX_0FE7) },
2906   /* e8 */
2907   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2908   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2909   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2910   { "por",              { MX, EM }, PREFIX_OPCODE },
2911   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2912   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2913   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2914   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2915   /* f0 */
2916   { PREFIX_TABLE (PREFIX_0FF0) },
2917   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2918   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2919   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2920   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2921   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2922   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2923   { PREFIX_TABLE (PREFIX_0FF7) },
2924   /* f8 */
2925   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2926   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2927   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2928   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2929   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2930   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2931   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2932   { "ud0S",             { Gv, Ev }, 0 },
2933 };
2934
2935 static const unsigned char onebyte_has_modrm[256] = {
2936   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2937   /*       -------------------------------        */
2938   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2939   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2940   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2941   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2942   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2943   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2944   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2945   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2946   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2947   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2948   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2949   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2950   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2951   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2952   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2953   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2954   /*       -------------------------------        */
2955   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2956 };
2957
2958 static const unsigned char twobyte_has_modrm[256] = {
2959   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2960   /*       -------------------------------        */
2961   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2962   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2963   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2964   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2965   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2966   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2967   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2968   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2969   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2970   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2971   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2972   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2973   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2974   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2975   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2976   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2977   /*       -------------------------------        */
2978   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2979 };
2980
2981 static char obuf[100];
2982 static char *obufp;
2983 static char *mnemonicendp;
2984 static char scratchbuf[100];
2985 static unsigned char *start_codep;
2986 static unsigned char *insn_codep;
2987 static unsigned char *codep;
2988 static unsigned char *end_codep;
2989 static int last_lock_prefix;
2990 static int last_repz_prefix;
2991 static int last_repnz_prefix;
2992 static int last_data_prefix;
2993 static int last_addr_prefix;
2994 static int last_rex_prefix;
2995 static int last_seg_prefix;
2996 static int fwait_prefix;
2997 /* The active segment register prefix.  */
2998 static int active_seg_prefix;
2999 #define MAX_CODE_LENGTH 15
3000 /* We can up to 14 prefixes since the maximum instruction length is
3001    15bytes.  */
3002 static int all_prefixes[MAX_CODE_LENGTH - 1];
3003 static disassemble_info *the_info;
3004 static struct
3005   {
3006     int mod;
3007     int reg;
3008     int rm;
3009   }
3010 modrm;
3011 static unsigned char need_modrm;
3012 static struct
3013   {
3014     int scale;
3015     int index;
3016     int base;
3017   }
3018 sib;
3019 static struct
3020   {
3021     int register_specifier;
3022     int length;
3023     int prefix;
3024     int w;
3025     int evex;
3026     int r;
3027     int v;
3028     int mask_register_specifier;
3029     int zeroing;
3030     int ll;
3031     int b;
3032   }
3033 vex;
3034 static unsigned char need_vex;
3035 static unsigned char need_vex_reg;
3036 static unsigned char vex_w_done;
3037
3038 struct op
3039   {
3040     const char *name;
3041     unsigned int len;
3042   };
3043
3044 /* If we are accessing mod/rm/reg without need_modrm set, then the
3045    values are stale.  Hitting this abort likely indicates that you
3046    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3047 #define MODRM_CHECK  if (!need_modrm) abort ()
3048
3049 static const char **names64;
3050 static const char **names32;
3051 static const char **names16;
3052 static const char **names8;
3053 static const char **names8rex;
3054 static const char **names_seg;
3055 static const char *index64;
3056 static const char *index32;
3057 static const char **index16;
3058 static const char **names_bnd;
3059
3060 static const char *intel_names64[] = {
3061   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3062   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3063 };
3064 static const char *intel_names32[] = {
3065   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3066   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3067 };
3068 static const char *intel_names16[] = {
3069   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3070   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3071 };
3072 static const char *intel_names8[] = {
3073   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3074 };
3075 static const char *intel_names8rex[] = {
3076   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3077   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3078 };
3079 static const char *intel_names_seg[] = {
3080   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3081 };
3082 static const char *intel_index64 = "riz";
3083 static const char *intel_index32 = "eiz";
3084 static const char *intel_index16[] = {
3085   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3086 };
3087
3088 static const char *att_names64[] = {
3089   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3090   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3091 };
3092 static const char *att_names32[] = {
3093   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3094   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3095 };
3096 static const char *att_names16[] = {
3097   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3098   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3099 };
3100 static const char *att_names8[] = {
3101   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3102 };
3103 static const char *att_names8rex[] = {
3104   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3105   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3106 };
3107 static const char *att_names_seg[] = {
3108   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3109 };
3110 static const char *att_index64 = "%riz";
3111 static const char *att_index32 = "%eiz";
3112 static const char *att_index16[] = {
3113   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3114 };
3115
3116 static const char **names_mm;
3117 static const char *intel_names_mm[] = {
3118   "mm0", "mm1", "mm2", "mm3",
3119   "mm4", "mm5", "mm6", "mm7"
3120 };
3121 static const char *att_names_mm[] = {
3122   "%mm0", "%mm1", "%mm2", "%mm3",
3123   "%mm4", "%mm5", "%mm6", "%mm7"
3124 };
3125
3126 static const char *intel_names_bnd[] = {
3127   "bnd0", "bnd1", "bnd2", "bnd3"
3128 };
3129
3130 static const char *att_names_bnd[] = {
3131   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3132 };
3133
3134 static const char **names_xmm;
3135 static const char *intel_names_xmm[] = {
3136   "xmm0", "xmm1", "xmm2", "xmm3",
3137   "xmm4", "xmm5", "xmm6", "xmm7",
3138   "xmm8", "xmm9", "xmm10", "xmm11",
3139   "xmm12", "xmm13", "xmm14", "xmm15",
3140   "xmm16", "xmm17", "xmm18", "xmm19",
3141   "xmm20", "xmm21", "xmm22", "xmm23",
3142   "xmm24", "xmm25", "xmm26", "xmm27",
3143   "xmm28", "xmm29", "xmm30", "xmm31"
3144 };
3145 static const char *att_names_xmm[] = {
3146   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3147   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3148   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3149   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3150   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3151   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3152   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3153   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3154 };
3155
3156 static const char **names_ymm;
3157 static const char *intel_names_ymm[] = {
3158   "ymm0", "ymm1", "ymm2", "ymm3",
3159   "ymm4", "ymm5", "ymm6", "ymm7",
3160   "ymm8", "ymm9", "ymm10", "ymm11",
3161   "ymm12", "ymm13", "ymm14", "ymm15",
3162   "ymm16", "ymm17", "ymm18", "ymm19",
3163   "ymm20", "ymm21", "ymm22", "ymm23",
3164   "ymm24", "ymm25", "ymm26", "ymm27",
3165   "ymm28", "ymm29", "ymm30", "ymm31"
3166 };
3167 static const char *att_names_ymm[] = {
3168   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3169   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3170   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3171   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3172   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3173   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3174   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3175   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3176 };
3177
3178 static const char **names_zmm;
3179 static const char *intel_names_zmm[] = {
3180   "zmm0", "zmm1", "zmm2", "zmm3",
3181   "zmm4", "zmm5", "zmm6", "zmm7",
3182   "zmm8", "zmm9", "zmm10", "zmm11",
3183   "zmm12", "zmm13", "zmm14", "zmm15",
3184   "zmm16", "zmm17", "zmm18", "zmm19",
3185   "zmm20", "zmm21", "zmm22", "zmm23",
3186   "zmm24", "zmm25", "zmm26", "zmm27",
3187   "zmm28", "zmm29", "zmm30", "zmm31"
3188 };
3189 static const char *att_names_zmm[] = {
3190   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3191   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3192   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3193   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3194   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3195   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3196   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3197   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3198 };
3199
3200 static const char **names_mask;
3201 static const char *intel_names_mask[] = {
3202   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3203 };
3204 static const char *att_names_mask[] = {
3205   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3206 };
3207
3208 static const char *names_rounding[] =
3209 {
3210   "{rn-sae}",
3211   "{rd-sae}",
3212   "{ru-sae}",
3213   "{rz-sae}"
3214 };
3215
3216 static const struct dis386 reg_table[][8] = {
3217   /* REG_80 */
3218   {
3219     { "addA",   { Ebh1, Ib }, 0 },
3220     { "orA",    { Ebh1, Ib }, 0 },
3221     { "adcA",   { Ebh1, Ib }, 0 },
3222     { "sbbA",   { Ebh1, Ib }, 0 },
3223     { "andA",   { Ebh1, Ib }, 0 },
3224     { "subA",   { Ebh1, Ib }, 0 },
3225     { "xorA",   { Ebh1, Ib }, 0 },
3226     { "cmpA",   { Eb, Ib }, 0 },
3227   },
3228   /* REG_81 */
3229   {
3230     { "addQ",   { Evh1, Iv }, 0 },
3231     { "orQ",    { Evh1, Iv }, 0 },
3232     { "adcQ",   { Evh1, Iv }, 0 },
3233     { "sbbQ",   { Evh1, Iv }, 0 },
3234     { "andQ",   { Evh1, Iv }, 0 },
3235     { "subQ",   { Evh1, Iv }, 0 },
3236     { "xorQ",   { Evh1, Iv }, 0 },
3237     { "cmpQ",   { Ev, Iv }, 0 },
3238   },
3239   /* REG_83 */
3240   {
3241     { "addQ",   { Evh1, sIb }, 0 },
3242     { "orQ",    { Evh1, sIb }, 0 },
3243     { "adcQ",   { Evh1, sIb }, 0 },
3244     { "sbbQ",   { Evh1, sIb }, 0 },
3245     { "andQ",   { Evh1, sIb }, 0 },
3246     { "subQ",   { Evh1, sIb }, 0 },
3247     { "xorQ",   { Evh1, sIb }, 0 },
3248     { "cmpQ",   { Ev, sIb }, 0 },
3249   },
3250   /* REG_8F */
3251   {
3252     { "popU",   { stackEv }, 0 },
3253     { XOP_8F_TABLE (XOP_09) },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257     { XOP_8F_TABLE (XOP_09) },
3258   },
3259   /* REG_C0 */
3260   {
3261     { "rolA",   { Eb, Ib }, 0 },
3262     { "rorA",   { Eb, Ib }, 0 },
3263     { "rclA",   { Eb, Ib }, 0 },
3264     { "rcrA",   { Eb, Ib }, 0 },
3265     { "shlA",   { Eb, Ib }, 0 },
3266     { "shrA",   { Eb, Ib }, 0 },
3267     { "shlA",   { Eb, Ib }, 0 },
3268     { "sarA",   { Eb, Ib }, 0 },
3269   },
3270   /* REG_C1 */
3271   {
3272     { "rolQ",   { Ev, Ib }, 0 },
3273     { "rorQ",   { Ev, Ib }, 0 },
3274     { "rclQ",   { Ev, Ib }, 0 },
3275     { "rcrQ",   { Ev, Ib }, 0 },
3276     { "shlQ",   { Ev, Ib }, 0 },
3277     { "shrQ",   { Ev, Ib }, 0 },
3278     { "shlQ",   { Ev, Ib }, 0 },
3279     { "sarQ",   { Ev, Ib }, 0 },
3280   },
3281   /* REG_C6 */
3282   {
3283     { "movA",   { Ebh3, Ib }, 0 },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { MOD_TABLE (MOD_C6_REG_7) },
3291   },
3292   /* REG_C7 */
3293   {
3294     { "movQ",   { Evh3, Iv }, 0 },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { MOD_TABLE (MOD_C7_REG_7) },
3302   },
3303   /* REG_D0 */
3304   {
3305     { "rolA",   { Eb, I1 }, 0 },
3306     { "rorA",   { Eb, I1 }, 0 },
3307     { "rclA",   { Eb, I1 }, 0 },
3308     { "rcrA",   { Eb, I1 }, 0 },
3309     { "shlA",   { Eb, I1 }, 0 },
3310     { "shrA",   { Eb, I1 }, 0 },
3311     { "shlA",   { Eb, I1 }, 0 },
3312     { "sarA",   { Eb, I1 }, 0 },
3313   },
3314   /* REG_D1 */
3315   {
3316     { "rolQ",   { Ev, I1 }, 0 },
3317     { "rorQ",   { Ev, I1 }, 0 },
3318     { "rclQ",   { Ev, I1 }, 0 },
3319     { "rcrQ",   { Ev, I1 }, 0 },
3320     { "shlQ",   { Ev, I1 }, 0 },
3321     { "shrQ",   { Ev, I1 }, 0 },
3322     { "shlQ",   { Ev, I1 }, 0 },
3323     { "sarQ",   { Ev, I1 }, 0 },
3324   },
3325   /* REG_D2 */
3326   {
3327     { "rolA",   { Eb, CL }, 0 },
3328     { "rorA",   { Eb, CL }, 0 },
3329     { "rclA",   { Eb, CL }, 0 },
3330     { "rcrA",   { Eb, CL }, 0 },
3331     { "shlA",   { Eb, CL }, 0 },
3332     { "shrA",   { Eb, CL }, 0 },
3333     { "shlA",   { Eb, CL }, 0 },
3334     { "sarA",   { Eb, CL }, 0 },
3335   },
3336   /* REG_D3 */
3337   {
3338     { "rolQ",   { Ev, CL }, 0 },
3339     { "rorQ",   { Ev, CL }, 0 },
3340     { "rclQ",   { Ev, CL }, 0 },
3341     { "rcrQ",   { Ev, CL }, 0 },
3342     { "shlQ",   { Ev, CL }, 0 },
3343     { "shrQ",   { Ev, CL }, 0 },
3344     { "shlQ",   { Ev, CL }, 0 },
3345     { "sarQ",   { Ev, CL }, 0 },
3346   },
3347   /* REG_F6 */
3348   {
3349     { "testA",  { Eb, Ib }, 0 },
3350     { "testA",  { Eb, Ib }, 0 },
3351     { "notA",   { Ebh1 }, 0 },
3352     { "negA",   { Ebh1 }, 0 },
3353     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3354     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3355     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3356     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3357   },
3358   /* REG_F7 */
3359   {
3360     { "testQ",  { Ev, Iv }, 0 },
3361     { "testQ",  { Ev, Iv }, 0 },
3362     { "notQ",   { Evh1 }, 0 },
3363     { "negQ",   { Evh1 }, 0 },
3364     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3365     { "imulQ",  { Ev }, 0 },
3366     { "divQ",   { Ev }, 0 },
3367     { "idivQ",  { Ev }, 0 },
3368   },
3369   /* REG_FE */
3370   {
3371     { "incA",   { Ebh1 }, 0 },
3372     { "decA",   { Ebh1 }, 0 },
3373   },
3374   /* REG_FF */
3375   {
3376     { "incQ",   { Evh1 }, 0 },
3377     { "decQ",   { Evh1 }, 0 },
3378     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3379     { MOD_TABLE (MOD_FF_REG_3) },
3380     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3381     { MOD_TABLE (MOD_FF_REG_5) },
3382     { "pushU",  { stackEv }, 0 },
3383     { Bad_Opcode },
3384   },
3385   /* REG_0F00 */
3386   {
3387     { "sldtD",  { Sv }, 0 },
3388     { "strD",   { Sv }, 0 },
3389     { "lldt",   { Ew }, 0 },
3390     { "ltr",    { Ew }, 0 },
3391     { "verr",   { Ew }, 0 },
3392     { "verw",   { Ew }, 0 },
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395   },
3396   /* REG_0F01 */
3397   {
3398     { MOD_TABLE (MOD_0F01_REG_0) },
3399     { MOD_TABLE (MOD_0F01_REG_1) },
3400     { MOD_TABLE (MOD_0F01_REG_2) },
3401     { MOD_TABLE (MOD_0F01_REG_3) },
3402     { "smswD",  { Sv }, 0 },
3403     { MOD_TABLE (MOD_0F01_REG_5) },
3404     { "lmsw",   { Ew }, 0 },
3405     { MOD_TABLE (MOD_0F01_REG_7) },
3406   },
3407   /* REG_0F0D */
3408   {
3409     { "prefetch",       { Mb }, 0 },
3410     { "prefetchw",      { Mb }, 0 },
3411     { "prefetchwt1",    { Mb }, 0 },
3412     { "prefetch",       { Mb }, 0 },
3413     { "prefetch",       { Mb }, 0 },
3414     { "prefetch",       { Mb }, 0 },
3415     { "prefetch",       { Mb }, 0 },
3416     { "prefetch",       { Mb }, 0 },
3417   },
3418   /* REG_0F18 */
3419   {
3420     { MOD_TABLE (MOD_0F18_REG_0) },
3421     { MOD_TABLE (MOD_0F18_REG_1) },
3422     { MOD_TABLE (MOD_0F18_REG_2) },
3423     { MOD_TABLE (MOD_0F18_REG_3) },
3424     { MOD_TABLE (MOD_0F18_REG_4) },
3425     { MOD_TABLE (MOD_0F18_REG_5) },
3426     { MOD_TABLE (MOD_0F18_REG_6) },
3427     { MOD_TABLE (MOD_0F18_REG_7) },
3428   },
3429   /* REG_0F1C_MOD_0 */
3430   {
3431     { "cldemote",       { Mb }, 0 },
3432     { "nopQ",           { Ev }, 0 },
3433     { "nopQ",           { Ev }, 0 },
3434     { "nopQ",           { Ev }, 0 },
3435     { "nopQ",           { Ev }, 0 },
3436     { "nopQ",           { Ev }, 0 },
3437     { "nopQ",           { Ev }, 0 },
3438     { "nopQ",           { Ev }, 0 },
3439   },
3440   /* REG_0F1E_MOD_3 */
3441   {
3442     { "nopQ",           { Ev }, 0 },
3443     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3450   },
3451   /* REG_0F71 */
3452   {
3453     { Bad_Opcode },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_0F71_REG_2) },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_0F71_REG_4) },
3458     { Bad_Opcode },
3459     { MOD_TABLE (MOD_0F71_REG_6) },
3460   },
3461   /* REG_0F72 */
3462   {
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_0F72_REG_2) },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F72_REG_4) },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F72_REG_6) },
3470   },
3471   /* REG_0F73 */
3472   {
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0F73_REG_2) },
3476     { MOD_TABLE (MOD_0F73_REG_3) },
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F73_REG_6) },
3480     { MOD_TABLE (MOD_0F73_REG_7) },
3481   },
3482   /* REG_0FA6 */
3483   {
3484     { "montmul",        { { OP_0f07, 0 } }, 0 },
3485     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3486     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3487   },
3488   /* REG_0FA7 */
3489   {
3490     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3491     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3492     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3493     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3494     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3495     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3496   },
3497   /* REG_0FAE */
3498   {
3499     { MOD_TABLE (MOD_0FAE_REG_0) },
3500     { MOD_TABLE (MOD_0FAE_REG_1) },
3501     { MOD_TABLE (MOD_0FAE_REG_2) },
3502     { MOD_TABLE (MOD_0FAE_REG_3) },
3503     { MOD_TABLE (MOD_0FAE_REG_4) },
3504     { MOD_TABLE (MOD_0FAE_REG_5) },
3505     { MOD_TABLE (MOD_0FAE_REG_6) },
3506     { MOD_TABLE (MOD_0FAE_REG_7) },
3507   },
3508   /* REG_0FBA */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { "btQ",    { Ev, Ib }, 0 },
3515     { "btsQ",   { Evh1, Ib }, 0 },
3516     { "btrQ",   { Evh1, Ib }, 0 },
3517     { "btcQ",   { Evh1, Ib }, 0 },
3518   },
3519   /* REG_0FC7 */
3520   {
3521     { Bad_Opcode },
3522     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_0FC7_REG_3) },
3525     { MOD_TABLE (MOD_0FC7_REG_4) },
3526     { MOD_TABLE (MOD_0FC7_REG_5) },
3527     { MOD_TABLE (MOD_0FC7_REG_6) },
3528     { MOD_TABLE (MOD_0FC7_REG_7) },
3529   },
3530   /* REG_VEX_0F71 */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3539   },
3540   /* REG_VEX_0F72 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3549   },
3550   /* REG_VEX_0F73 */
3551   {
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3555     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3559     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3560   },
3561   /* REG_VEX_0FAE */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3566     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3567   },
3568   /* REG_VEX_0F38F3 */
3569   {
3570     { Bad_Opcode },
3571     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3572     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3573     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3574   },
3575   /* REG_XOP_LWPCB */
3576   {
3577     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3578     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3579   },
3580   /* REG_XOP_LWP */
3581   {
3582     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3583     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3584   },
3585   /* REG_XOP_TBM_01 */
3586   {
3587     { Bad_Opcode },
3588     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3589     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3590     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3591     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3592     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3593     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3594     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3595   },
3596   /* REG_XOP_TBM_02 */
3597   {
3598     { Bad_Opcode },
3599     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { Bad_Opcode },
3604     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3605   },
3606 #define NEED_REG_TABLE
3607 #include "i386-dis-evex.h"
3608 #undef NEED_REG_TABLE
3609 };
3610
3611 static const struct dis386 prefix_table[][4] = {
3612   /* PREFIX_90 */
3613   {
3614     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3615     { "pause", { XX }, 0 },
3616     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3617     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3618   },
3619
3620   /* PREFIX_MOD_0_0F01_REG_5 */
3621   {
3622     { Bad_Opcode },
3623     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3624   },
3625
3626   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3627   {
3628     { Bad_Opcode },
3629     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3630   },
3631
3632   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3633   {
3634     { Bad_Opcode },
3635     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F09 */
3639   {
3640     { "wbinvd",   { XX }, 0 },
3641     { "wbnoinvd", { XX }, 0 },
3642   },
3643
3644   /* PREFIX_0F10 */
3645   {
3646     { "movups", { XM, EXx }, PREFIX_OPCODE },
3647     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3648     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3649     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3650   },
3651
3652   /* PREFIX_0F11 */
3653   {
3654     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3655     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3656     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3657     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F12 */
3661   {
3662     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3663     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3664     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3665     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3666   },
3667
3668   /* PREFIX_0F16 */
3669   {
3670     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3671     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3672     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3673   },
3674
3675   /* PREFIX_0F1A */
3676   {
3677     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3678     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3679     { "bndmov", { Gbnd, Ebnd }, 0 },
3680     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3681   },
3682
3683   /* PREFIX_0F1B */
3684   {
3685     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3686     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3687     { "bndmov", { EbndS, Gbnd }, 0 },
3688     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3689   },
3690
3691   /* PREFIX_0F1C */
3692   {
3693     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695     { "nopQ",   { Ev }, PREFIX_OPCODE },
3696     { "nopQ",   { Ev }, PREFIX_OPCODE },
3697   },
3698
3699   /* PREFIX_0F1E */
3700   {
3701     { "nopQ",   { Ev }, PREFIX_OPCODE },
3702     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3703     { "nopQ",   { Ev }, PREFIX_OPCODE },
3704     { "nopQ",   { Ev }, PREFIX_OPCODE },
3705   },
3706
3707   /* PREFIX_0F2A */
3708   {
3709     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3710     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3711     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3712     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3713   },
3714
3715   /* PREFIX_0F2B */
3716   {
3717     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3718     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3719     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3720     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3721   },
3722
3723   /* PREFIX_0F2C */
3724   {
3725     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3726     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3727     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3728     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F2D */
3732   {
3733     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3734     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3735     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3736     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3737   },
3738
3739   /* PREFIX_0F2E */
3740   {
3741     { "ucomiss",{ XM, EXd }, 0 },
3742     { Bad_Opcode },
3743     { "ucomisd",{ XM, EXq }, 0 },
3744   },
3745
3746   /* PREFIX_0F2F */
3747   {
3748     { "comiss", { XM, EXd }, 0 },
3749     { Bad_Opcode },
3750     { "comisd", { XM, EXq }, 0 },
3751   },
3752
3753   /* PREFIX_0F51 */
3754   {
3755     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3756     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3757     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3758     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F52 */
3762   {
3763     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3764     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F53 */
3768   {
3769     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3770     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3771   },
3772
3773   /* PREFIX_0F58 */
3774   {
3775     { "addps", { XM, EXx }, PREFIX_OPCODE },
3776     { "addss", { XM, EXd }, PREFIX_OPCODE },
3777     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3778     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F59 */
3782   {
3783     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3784     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3785     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3786     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F5A */
3790   {
3791     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3792     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3793     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3794     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F5B */
3798   {
3799     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3800     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3801     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F5C */
3805   {
3806     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3807     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3809     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F5D */
3813   {
3814     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3815     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3816     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3817     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F5E */
3821   {
3822     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3823     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3824     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3825     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F5F */
3829   {
3830     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3831     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3832     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3833     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F60 */
3837   {
3838     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3839     { Bad_Opcode },
3840     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F61 */
3844   {
3845     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3846     { Bad_Opcode },
3847     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F62 */
3851   {
3852     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3853     { Bad_Opcode },
3854     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F6C */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F6D */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F6F */
3872   {
3873     { "movq",   { MX, EM }, PREFIX_OPCODE },
3874     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3875     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F70 */
3879   {
3880     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3881     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3882     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3883     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F73_REG_3 */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "psrldq", { XS, Ib }, 0 },
3891   },
3892
3893   /* PREFIX_0F73_REG_7 */
3894   {
3895     { Bad_Opcode },
3896     { Bad_Opcode },
3897     { "pslldq", { XS, Ib }, 0 },
3898   },
3899
3900   /* PREFIX_0F78 */
3901   {
3902     {"vmread",  { Em, Gm }, 0 },
3903     { Bad_Opcode },
3904     {"extrq",   { XS, Ib, Ib }, 0 },
3905     {"insertq", { XM, XS, Ib, Ib }, 0 },
3906   },
3907
3908   /* PREFIX_0F79 */
3909   {
3910     {"vmwrite", { Gm, Em }, 0 },
3911     { Bad_Opcode },
3912     {"extrq",   { XM, XS }, 0 },
3913     {"insertq", { XM, XS }, 0 },
3914   },
3915
3916   /* PREFIX_0F7C */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3921     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F7D */
3925   {
3926     { Bad_Opcode },
3927     { Bad_Opcode },
3928     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3929     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0F7E */
3933   {
3934     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3935     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3936     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3937   },
3938
3939   /* PREFIX_0F7F */
3940   {
3941     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3942     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3943     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0FAE_REG_0 */
3947   {
3948     { Bad_Opcode },
3949     { "rdfsbase", { Ev }, 0 },
3950   },
3951
3952   /* PREFIX_0FAE_REG_1 */
3953   {
3954     { Bad_Opcode },
3955     { "rdgsbase", { Ev }, 0 },
3956   },
3957
3958   /* PREFIX_0FAE_REG_2 */
3959   {
3960     { Bad_Opcode },
3961     { "wrfsbase", { Ev }, 0 },
3962   },
3963
3964   /* PREFIX_0FAE_REG_3 */
3965   {
3966     { Bad_Opcode },
3967     { "wrgsbase", { Ev }, 0 },
3968   },
3969
3970   /* PREFIX_MOD_0_0FAE_REG_4 */
3971   {
3972     { "xsave",  { FXSAVE }, 0 },
3973     { "ptwrite%LQ", { Edq }, 0 },
3974   },
3975
3976   /* PREFIX_MOD_3_0FAE_REG_4 */
3977   {
3978     { Bad_Opcode },
3979     { "ptwrite%LQ", { Edq }, 0 },
3980   },
3981
3982   /* PREFIX_MOD_0_0FAE_REG_5 */
3983   {
3984     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_MOD_3_0FAE_REG_5 */
3988   {
3989     { "lfence",         { Skip_MODRM }, 0 },
3990     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3991   },
3992
3993   /* PREFIX_MOD_0_0FAE_REG_6 */
3994   {
3995     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3996     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3997     { "clwb",   { Mb }, PREFIX_OPCODE },
3998   },
3999
4000   /* PREFIX_MOD_1_0FAE_REG_6 */
4001   {
4002     { RM_TABLE (RM_0FAE_REG_6) },
4003     { "umonitor",       { Eva }, PREFIX_OPCODE },
4004     { "tpause", { Edq }, PREFIX_OPCODE },
4005     { "umwait", { Edq }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0FAE_REG_7 */
4009   {
4010     { "clflush",        { Mb }, 0 },
4011     { Bad_Opcode },
4012     { "clflushopt",     { Mb }, 0 },
4013   },
4014
4015   /* PREFIX_0FB8 */
4016   {
4017     { Bad_Opcode },
4018     { "popcntS", { Gv, Ev }, 0 },
4019   },
4020
4021   /* PREFIX_0FBC */
4022   {
4023     { "bsfS",   { Gv, Ev }, 0 },
4024     { "tzcntS", { Gv, Ev }, 0 },
4025     { "bsfS",   { Gv, Ev }, 0 },
4026   },
4027
4028   /* PREFIX_0FBD */
4029   {
4030     { "bsrS",   { Gv, Ev }, 0 },
4031     { "lzcntS", { Gv, Ev }, 0 },
4032     { "bsrS",   { Gv, Ev }, 0 },
4033   },
4034
4035   /* PREFIX_0FC2 */
4036   {
4037     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4038     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4039     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4040     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4041   },
4042
4043   /* PREFIX_MOD_0_0FC3 */
4044   {
4045     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_MOD_0_0FC7_REG_6 */
4049   {
4050     { "vmptrld",{ Mq }, 0 },
4051     { "vmxon",  { Mq }, 0 },
4052     { "vmclear",{ Mq }, 0 },
4053   },
4054
4055   /* PREFIX_MOD_3_0FC7_REG_6 */
4056   {
4057     { "rdrand", { Ev }, 0 },
4058     { Bad_Opcode },
4059     { "rdrand", { Ev }, 0 }
4060   },
4061
4062   /* PREFIX_MOD_3_0FC7_REG_7 */
4063   {
4064     { "rdseed", { Ev }, 0 },
4065     { "rdpid",  { Em }, 0 },
4066     { "rdseed", { Ev }, 0 },
4067   },
4068
4069   /* PREFIX_0FD0 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { "addsubpd", { XM, EXx }, 0 },
4074     { "addsubps", { XM, EXx }, 0 },
4075   },
4076
4077   /* PREFIX_0FD6 */
4078   {
4079     { Bad_Opcode },
4080     { "movq2dq",{ XM, MS }, 0 },
4081     { "movq",   { EXqS, XM }, 0 },
4082     { "movdq2q",{ MX, XS }, 0 },
4083   },
4084
4085   /* PREFIX_0FE6 */
4086   {
4087     { Bad_Opcode },
4088     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4089     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4090     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4091   },
4092
4093   /* PREFIX_0FE7 */
4094   {
4095     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4096     { Bad_Opcode },
4097     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4098   },
4099
4100   /* PREFIX_0FF0 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4106   },
4107
4108   /* PREFIX_0FF7 */
4109   {
4110     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4111     { Bad_Opcode },
4112     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3810 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3814 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3815 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3817 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3820 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3821 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3822 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3823 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3824 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3825 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3828 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3829 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F382A */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4204   },
4205
4206   /* PREFIX_0F382B */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3830 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3831 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3832 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3833 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3834 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3835 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3837 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3838 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3839 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F383A */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F383B */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F383C */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F383D */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F383E */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F383F */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3840 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3841 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F3880 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3881 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3882 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F38C8 */
4354   {
4355     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38C9 */
4359   {
4360     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38CA */
4364   {
4365     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38CB */
4369   {
4370     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38CC */
4374   {
4375     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38CD */
4379   {
4380     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38CF */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38DB */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38DC */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38DD */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38DE */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38DF */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38F0 */
4426   {
4427     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428     { Bad_Opcode },
4429     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4430     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38F1 */
4434   {
4435     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436     { Bad_Opcode },
4437     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4438     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38F5 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4446   },
4447
4448   /* PREFIX_0F38F6 */
4449   {
4450     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4451     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4452     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4453     { Bad_Opcode },
4454   },
4455
4456   /* PREFIX_0F38F8 */
4457   {
4458     { Bad_Opcode },
4459     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4460     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4461     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4462   },
4463
4464   /* PREFIX_0F38F9 */
4465   {
4466     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4467   },
4468
4469   /* PREFIX_0F3A08 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A09 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A0A */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A0B */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A0C */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A0D */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A0E */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A14 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A15 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A16 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A17 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A20 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A21 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A22 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A40 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A41 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A42 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A44 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A60 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A61 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A62 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A63 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3ACC */
4624   {
4625     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3ACE */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F3ACF */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3ADF */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_VEX_0F10 */
4650   {
4651     { "vmovups",        { XM, EXx }, 0 },
4652     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4653     { "vmovupd",        { XM, EXx }, 0 },
4654     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4655   },
4656
4657   /* PREFIX_VEX_0F11 */
4658   {
4659     { "vmovups",        { EXxS, XM }, 0 },
4660     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4661     { "vmovupd",        { EXxS, XM }, 0 },
4662     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4663   },
4664
4665   /* PREFIX_VEX_0F12 */
4666   {
4667     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4668     { "vmovsldup",      { XM, EXx }, 0 },
4669     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4670     { "vmovddup",       { XM, EXymmq }, 0 },
4671   },
4672
4673   /* PREFIX_VEX_0F16 */
4674   {
4675     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4676     { "vmovshdup",      { XM, EXx }, 0 },
4677     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4678   },
4679
4680   /* PREFIX_VEX_0F2A */
4681   {
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4686   },
4687
4688   /* PREFIX_VEX_0F2C */
4689   {
4690     { Bad_Opcode },
4691     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4694   },
4695
4696   /* PREFIX_VEX_0F2D */
4697   {
4698     { Bad_Opcode },
4699     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4702   },
4703
4704   /* PREFIX_VEX_0F2E */
4705   {
4706     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4707     { Bad_Opcode },
4708     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4709   },
4710
4711   /* PREFIX_VEX_0F2F */
4712   {
4713     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4714     { Bad_Opcode },
4715     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4716   },
4717
4718   /* PREFIX_VEX_0F41 */
4719   {
4720     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F42 */
4726   {
4727     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F44 */
4733   {
4734     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F45 */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F46 */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F47 */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F4A */
4761   {
4762     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4763     { Bad_Opcode },
4764     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F4B */
4768   {
4769     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4770     { Bad_Opcode },
4771     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F51 */
4775   {
4776     { "vsqrtps",        { XM, EXx }, 0 },
4777     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4778     { "vsqrtpd",        { XM, EXx }, 0 },
4779     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4780   },
4781
4782   /* PREFIX_VEX_0F52 */
4783   {
4784     { "vrsqrtps",       { XM, EXx }, 0 },
4785     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F53 */
4789   {
4790     { "vrcpps",         { XM, EXx }, 0 },
4791     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F58 */
4795   {
4796     { "vaddps",         { XM, Vex, EXx }, 0 },
4797     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4798     { "vaddpd",         { XM, Vex, EXx }, 0 },
4799     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F59 */
4803   {
4804     { "vmulps",         { XM, Vex, EXx }, 0 },
4805     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4806     { "vmulpd",         { XM, Vex, EXx }, 0 },
4807     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F5A */
4811   {
4812     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4813     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4814     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4815     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F5B */
4819   {
4820     { "vcvtdq2ps",      { XM, EXx }, 0 },
4821     { "vcvttps2dq",     { XM, EXx }, 0 },
4822     { "vcvtps2dq",      { XM, EXx }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F5C */
4826   {
4827     { "vsubps",         { XM, Vex, EXx }, 0 },
4828     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4829     { "vsubpd",         { XM, Vex, EXx }, 0 },
4830     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F5D */
4834   {
4835     { "vminps",         { XM, Vex, EXx }, 0 },
4836     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4837     { "vminpd",         { XM, Vex, EXx }, 0 },
4838     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F5E */
4842   {
4843     { "vdivps",         { XM, Vex, EXx }, 0 },
4844     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4845     { "vdivpd",         { XM, Vex, EXx }, 0 },
4846     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F5F */
4850   {
4851     { "vmaxps",         { XM, Vex, EXx }, 0 },
4852     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4853     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4854     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F60 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4862   },
4863
4864   /* PREFIX_VEX_0F61 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F62 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F63 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F64 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F65 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F66 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F67 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F68 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F69 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F6A */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F6B */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F6C */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F6D */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F6E */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F6F */
4963   {
4964     { Bad_Opcode },
4965     { "vmovdqu",        { XM, EXx }, 0 },
4966     { "vmovdqa",        { XM, EXx }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F70 */
4970   {
4971     { Bad_Opcode },
4972     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4973     { "vpshufd",        { XM, EXx, Ib }, 0 },
4974     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F71_REG_2 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F71_REG_4 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vpsraw",         { Vex, XS, Ib }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F71_REG_6 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { "vpsllw",         { Vex, XS, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F72_REG_2 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpsrld",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F72_REG_4 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsrad",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F72_REG_6 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpslld",         { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F73_REG_2 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F73_REG_3 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F73_REG_6 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpsllq",         { Vex, XS, Ib }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F73_REG_7 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpslldq",        { Vex, XS, Ib }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F74 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F75 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5059   },
5060
5061   /* PREFIX_VEX_0F76 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F77 */
5069   {
5070     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5071   },
5072
5073   /* PREFIX_VEX_0F7C */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5078     { "vhaddps",        { XM, Vex, EXx }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F7D */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5086     { "vhsubps",        { XM, Vex, EXx }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F7E */
5090   {
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5093     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F7F */
5097   {
5098     { Bad_Opcode },
5099     { "vmovdqu",        { EXxS, XM }, 0 },
5100     { "vmovdqa",        { EXxS, XM }, 0 },
5101   },
5102
5103   /* PREFIX_VEX_0F90 */
5104   {
5105     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5106     { Bad_Opcode },
5107     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_0F91 */
5111   {
5112     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0F92 */
5118   {
5119     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5122     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5123   },
5124
5125   /* PREFIX_VEX_0F93 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5130     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5131   },
5132
5133   /* PREFIX_VEX_0F98 */
5134   {
5135     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F99 */
5141   {
5142     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0FC2 */
5148   {
5149     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5150     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5151     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5152     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5153   },
5154
5155   /* PREFIX_VEX_0FC4 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0FC5 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FD0 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5174     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FD1 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FD2 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FD3 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FD4 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { "vpaddq",         { XM, Vex, EXx }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FD5 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpmullw",        { XM, Vex, EXx }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FD6 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0FD7 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5224   },
5225
5226   /* PREFIX_VEX_0FD8 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FD9 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FDA */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vpminub",        { XM, Vex, EXx }, 0 },
5245   },
5246
5247   /* PREFIX_VEX_0FDB */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpand",          { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FDC */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FDD */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FDE */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FDF */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpandn",         { XM, Vex, EXx }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FE0 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpavgb",         { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FE1 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FE2 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE3 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpavgw",         { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE4 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FE5 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE6 */
5325   {
5326     { Bad_Opcode },
5327     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5328     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5329     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE7 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FE8 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FE9 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FEA */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vpminsw",        { XM, Vex, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FEB */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpor",           { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FEC */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FED */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FEE */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5386   },
5387
5388   /* PREFIX_VEX_0FEF */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpxor",          { XM, Vex, EXx }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FF0 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5401   },
5402
5403   /* PREFIX_VEX_0FF1 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FF2 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF3 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0FF4 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF5 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FF6 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF7 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FF8 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpsubb",         { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FF9 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpsubw",         { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FFA */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpsubd",         { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0FFB */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpsubq",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0FFC */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpaddb",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0FFD */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpaddw",         { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0FFE */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vpaddd",         { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3800 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vpshufb",        { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0F3801 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vphaddw",        { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3802 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vphaddd",        { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3803 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3804 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3805 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphsubw",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3806 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vphsubd",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3807 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3808 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpsignb",        { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3809 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vpsignw",        { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F380A */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vpsignd",        { XM, Vex, EXx }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F380B */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F380C */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F380D */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F380E */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F380F */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3813 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5618   },
5619
5620   /* PREFIX_VEX_0F3816 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3817 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { "vptest",         { XM, EXx }, 0 },
5632   },
5633
5634   /* PREFIX_VEX_0F3818 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3819 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F381A */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F381C */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpabsb",         { XM, EXx }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F381D */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpabsw",         { XM, EXx }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F381E */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpabsd",         { XM, EXx }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3820 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3821 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3822 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3823 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3824 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3825 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F3828 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F3829 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F382A */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F382B */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F382C */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F382D */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F382E */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F382F */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F3830 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5779   },
5780
5781   /* PREFIX_VEX_0F3831 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3832 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5793   },
5794
5795   /* PREFIX_VEX_0F3833 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3834 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3835 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3836 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3837 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F3838 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpminsb",        { XM, Vex, EXx }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F3839 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpminsd",        { XM, Vex, EXx }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F383A */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpminuw",        { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F383B */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpminud",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F383C */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F383D */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F383E */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F383F */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F3840 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpmulld",        { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F3841 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F3845 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F3846 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F3847 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5919   },
5920
5921   /* PREFIX_VEX_0F3858 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3859 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F385A */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F3878 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3879 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F388C */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F388E */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3890 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5975   },
5976
5977   /* PREFIX_VEX_0F3891 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5982   },
5983
5984   /* PREFIX_VEX_0F3892 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5989   },
5990
5991   /* PREFIX_VEX_0F3893 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3896 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3897 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3898 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3899 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F389A */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F389B */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F389C */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389D */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389E */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389F */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F38A6 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6073     { Bad_Opcode },
6074   },
6075
6076   /* PREFIX_VEX_0F38A7 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38A8 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38A9 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38AA */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38AB */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38AC */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AD */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AE */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AF */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38B6 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38B7 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38B8 */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38B9 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38BA */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38BB */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38BC */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BD */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BE */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BF */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38CF */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6214   },
6215
6216   /* PREFIX_VEX_0F38DB */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6221   },
6222
6223   /* PREFIX_VEX_0F38DC */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vaesenc",        { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38DD */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38DE */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vaesdec",        { XM, Vex, EXx }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F38DF */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38F2 */
6252   {
6253     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6254   },
6255
6256   /* PREFIX_VEX_0F38F3_REG_1 */
6257   {
6258     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6259   },
6260
6261   /* PREFIX_VEX_0F38F3_REG_2 */
6262   {
6263     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6264   },
6265
6266   /* PREFIX_VEX_0F38F3_REG_3 */
6267   {
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F5 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6275     { Bad_Opcode },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6277   },
6278
6279   /* PREFIX_VEX_0F38F6 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F7 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A00 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A01 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A02 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A04 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A05 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A06 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A08 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vroundps",       { XM, EXx, Ib }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F3A09 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vroundpd",       { XM, EXx, Ib }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F3A0A */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F3A0B */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A0C */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0D */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0E */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0F */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A14 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A15 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A16 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A17 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A18 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A19 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A1D */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6440   },
6441
6442   /* PREFIX_VEX_0F3A20 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A21 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A22 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A30 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A31 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A32 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A33 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A38 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A39 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A40 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6510   },
6511
6512   /* PREFIX_VEX_0F3A41 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A42 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6524   },
6525
6526   /* PREFIX_VEX_0F3A44 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6531   },
6532
6533   /* PREFIX_VEX_0F3A46 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A48 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A49 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A4A */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A4B */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A4C */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A5C */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6580   },
6581
6582   /* PREFIX_VEX_0F3A5D */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A5E */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A5F */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A60 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6608     { Bad_Opcode },
6609   },
6610
6611   /* PREFIX_VEX_0F3A61 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6616   },
6617
6618   /* PREFIX_VEX_0F3A62 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6623   },
6624
6625   /* PREFIX_VEX_0F3A63 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6630   },
6631
6632   /* PREFIX_VEX_0F3A68 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6637   },
6638
6639   /* PREFIX_VEX_0F3A69 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6644   },
6645
6646   /* PREFIX_VEX_0F3A6A */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A6B */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6658   },
6659
6660   /* PREFIX_VEX_0F3A6C */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6D */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6E */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6F */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6686   },
6687
6688   /* PREFIX_VEX_0F3A78 */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A79 */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6700   },
6701
6702   /* PREFIX_VEX_0F3A7A */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6707   },
6708
6709   /* PREFIX_VEX_0F3A7B */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6714   },
6715
6716   /* PREFIX_VEX_0F3A7C */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721     { Bad_Opcode },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7D */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7E */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7F */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3ACE */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3ACF */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6757   },
6758
6759   /* PREFIX_VEX_0F3ADF */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3AF0 */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6772   },
6773
6774 #define NEED_PREFIX_TABLE
6775 #include "i386-dis-evex.h"
6776 #undef NEED_PREFIX_TABLE
6777 };
6778
6779 static const struct dis386 x86_64_table[][2] = {
6780   /* X86_64_06 */
6781   {
6782     { "pushP", { es }, 0 },
6783   },
6784
6785   /* X86_64_07 */
6786   {
6787     { "popP", { es }, 0 },
6788   },
6789
6790   /* X86_64_0D */
6791   {
6792     { "pushP", { cs }, 0 },
6793   },
6794
6795   /* X86_64_16 */
6796   {
6797     { "pushP", { ss }, 0 },
6798   },
6799
6800   /* X86_64_17 */
6801   {
6802     { "popP", { ss }, 0 },
6803   },
6804
6805   /* X86_64_1E */
6806   {
6807     { "pushP", { ds }, 0 },
6808   },
6809
6810   /* X86_64_1F */
6811   {
6812     { "popP", { ds }, 0 },
6813   },
6814
6815   /* X86_64_27 */
6816   {
6817     { "daa", { XX }, 0 },
6818   },
6819
6820   /* X86_64_2F */
6821   {
6822     { "das", { XX }, 0 },
6823   },
6824
6825   /* X86_64_37 */
6826   {
6827     { "aaa", { XX }, 0 },
6828   },
6829
6830   /* X86_64_3F */
6831   {
6832     { "aas", { XX }, 0 },
6833   },
6834
6835   /* X86_64_60 */
6836   {
6837     { "pushaP", { XX }, 0 },
6838   },
6839
6840   /* X86_64_61 */
6841   {
6842     { "popaP", { XX }, 0 },
6843   },
6844
6845   /* X86_64_62 */
6846   {
6847     { MOD_TABLE (MOD_62_32BIT) },
6848     { EVEX_TABLE (EVEX_0F) },
6849   },
6850
6851   /* X86_64_63 */
6852   {
6853     { "arpl", { Ew, Gw }, 0 },
6854     { "movs{lq|xd}", { Gv, Ed }, 0 },
6855   },
6856
6857   /* X86_64_6D */
6858   {
6859     { "ins{R|}", { Yzr, indirDX }, 0 },
6860     { "ins{G|}", { Yzr, indirDX }, 0 },
6861   },
6862
6863   /* X86_64_6F */
6864   {
6865     { "outs{R|}", { indirDXr, Xz }, 0 },
6866     { "outs{G|}", { indirDXr, Xz }, 0 },
6867   },
6868
6869   /* X86_64_82 */
6870   {
6871     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6872     { REG_TABLE (REG_80) },
6873   },
6874
6875   /* X86_64_9A */
6876   {
6877     { "Jcall{T|}", { Ap }, 0 },
6878   },
6879
6880   /* X86_64_C4 */
6881   {
6882     { MOD_TABLE (MOD_C4_32BIT) },
6883     { VEX_C4_TABLE (VEX_0F) },
6884   },
6885
6886   /* X86_64_C5 */
6887   {
6888     { MOD_TABLE (MOD_C5_32BIT) },
6889     { VEX_C5_TABLE (VEX_0F) },
6890   },
6891
6892   /* X86_64_CE */
6893   {
6894     { "into", { XX }, 0 },
6895   },
6896
6897   /* X86_64_D4 */
6898   {
6899     { "aam", { Ib }, 0 },
6900   },
6901
6902   /* X86_64_D5 */
6903   {
6904     { "aad", { Ib }, 0 },
6905   },
6906
6907   /* X86_64_E8 */
6908   {
6909     { "callP",          { Jv, BND }, 0 },
6910     { "call@",          { Jv, BND }, 0 }
6911   },
6912
6913   /* X86_64_E9 */
6914   {
6915     { "jmpP",           { Jv, BND }, 0 },
6916     { "jmp@",           { Jv, BND }, 0 }
6917   },
6918
6919   /* X86_64_EA */
6920   {
6921     { "Jjmp{T|}", { Ap }, 0 },
6922   },
6923
6924   /* X86_64_0F01_REG_0 */
6925   {
6926     { "sgdt{Q|IQ}", { M }, 0 },
6927     { "sgdt", { M }, 0 },
6928   },
6929
6930   /* X86_64_0F01_REG_1 */
6931   {
6932     { "sidt{Q|IQ}", { M }, 0 },
6933     { "sidt", { M }, 0 },
6934   },
6935
6936   /* X86_64_0F01_REG_2 */
6937   {
6938     { "lgdt{Q|Q}", { M }, 0 },
6939     { "lgdt", { M }, 0 },
6940   },
6941
6942   /* X86_64_0F01_REG_3 */
6943   {
6944     { "lidt{Q|Q}", { M }, 0 },
6945     { "lidt", { M }, 0 },
6946   },
6947 };
6948
6949 static const struct dis386 three_byte_table[][256] = {
6950
6951   /* THREE_BYTE_0F38 */
6952   {
6953     /* 00 */
6954     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6955     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6956     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6957     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6958     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6959     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6960     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6961     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6962     /* 08 */
6963     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6964     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6965     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6966     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 10 */
6972     { PREFIX_TABLE (PREFIX_0F3810) },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { PREFIX_TABLE (PREFIX_0F3814) },
6977     { PREFIX_TABLE (PREFIX_0F3815) },
6978     { Bad_Opcode },
6979     { PREFIX_TABLE (PREFIX_0F3817) },
6980     /* 18 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6986     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6987     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6988     { Bad_Opcode },
6989     /* 20 */
6990     { PREFIX_TABLE (PREFIX_0F3820) },
6991     { PREFIX_TABLE (PREFIX_0F3821) },
6992     { PREFIX_TABLE (PREFIX_0F3822) },
6993     { PREFIX_TABLE (PREFIX_0F3823) },
6994     { PREFIX_TABLE (PREFIX_0F3824) },
6995     { PREFIX_TABLE (PREFIX_0F3825) },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 28 */
6999     { PREFIX_TABLE (PREFIX_0F3828) },
7000     { PREFIX_TABLE (PREFIX_0F3829) },
7001     { PREFIX_TABLE (PREFIX_0F382A) },
7002     { PREFIX_TABLE (PREFIX_0F382B) },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 30 */
7008     { PREFIX_TABLE (PREFIX_0F3830) },
7009     { PREFIX_TABLE (PREFIX_0F3831) },
7010     { PREFIX_TABLE (PREFIX_0F3832) },
7011     { PREFIX_TABLE (PREFIX_0F3833) },
7012     { PREFIX_TABLE (PREFIX_0F3834) },
7013     { PREFIX_TABLE (PREFIX_0F3835) },
7014     { Bad_Opcode },
7015     { PREFIX_TABLE (PREFIX_0F3837) },
7016     /* 38 */
7017     { PREFIX_TABLE (PREFIX_0F3838) },
7018     { PREFIX_TABLE (PREFIX_0F3839) },
7019     { PREFIX_TABLE (PREFIX_0F383A) },
7020     { PREFIX_TABLE (PREFIX_0F383B) },
7021     { PREFIX_TABLE (PREFIX_0F383C) },
7022     { PREFIX_TABLE (PREFIX_0F383D) },
7023     { PREFIX_TABLE (PREFIX_0F383E) },
7024     { PREFIX_TABLE (PREFIX_0F383F) },
7025     /* 40 */
7026     { PREFIX_TABLE (PREFIX_0F3840) },
7027     { PREFIX_TABLE (PREFIX_0F3841) },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 48 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 50 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 58 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 60 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 68 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 70 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 78 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 80 */
7098     { PREFIX_TABLE (PREFIX_0F3880) },
7099     { PREFIX_TABLE (PREFIX_0F3881) },
7100     { PREFIX_TABLE (PREFIX_0F3882) },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 88 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 90 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 98 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* a0 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* a8 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* b0 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* b8 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* c0 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* c8 */
7179     { PREFIX_TABLE (PREFIX_0F38C8) },
7180     { PREFIX_TABLE (PREFIX_0F38C9) },
7181     { PREFIX_TABLE (PREFIX_0F38CA) },
7182     { PREFIX_TABLE (PREFIX_0F38CB) },
7183     { PREFIX_TABLE (PREFIX_0F38CC) },
7184     { PREFIX_TABLE (PREFIX_0F38CD) },
7185     { Bad_Opcode },
7186     { PREFIX_TABLE (PREFIX_0F38CF) },
7187     /* d0 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* d8 */
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { PREFIX_TABLE (PREFIX_0F38DB) },
7201     { PREFIX_TABLE (PREFIX_0F38DC) },
7202     { PREFIX_TABLE (PREFIX_0F38DD) },
7203     { PREFIX_TABLE (PREFIX_0F38DE) },
7204     { PREFIX_TABLE (PREFIX_0F38DF) },
7205     /* e0 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* e8 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* f0 */
7224     { PREFIX_TABLE (PREFIX_0F38F0) },
7225     { PREFIX_TABLE (PREFIX_0F38F1) },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { PREFIX_TABLE (PREFIX_0F38F5) },
7230     { PREFIX_TABLE (PREFIX_0F38F6) },
7231     { Bad_Opcode },
7232     /* f8 */
7233     { PREFIX_TABLE (PREFIX_0F38F8) },
7234     { PREFIX_TABLE (PREFIX_0F38F9) },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241   },
7242   /* THREE_BYTE_0F3A */
7243   {
7244     /* 00 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 08 */
7254     { PREFIX_TABLE (PREFIX_0F3A08) },
7255     { PREFIX_TABLE (PREFIX_0F3A09) },
7256     { PREFIX_TABLE (PREFIX_0F3A0A) },
7257     { PREFIX_TABLE (PREFIX_0F3A0B) },
7258     { PREFIX_TABLE (PREFIX_0F3A0C) },
7259     { PREFIX_TABLE (PREFIX_0F3A0D) },
7260     { PREFIX_TABLE (PREFIX_0F3A0E) },
7261     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7262     /* 10 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { PREFIX_TABLE (PREFIX_0F3A14) },
7268     { PREFIX_TABLE (PREFIX_0F3A15) },
7269     { PREFIX_TABLE (PREFIX_0F3A16) },
7270     { PREFIX_TABLE (PREFIX_0F3A17) },
7271     /* 18 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 20 */
7281     { PREFIX_TABLE (PREFIX_0F3A20) },
7282     { PREFIX_TABLE (PREFIX_0F3A21) },
7283     { PREFIX_TABLE (PREFIX_0F3A22) },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 28 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 30 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 38 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 40 */
7317     { PREFIX_TABLE (PREFIX_0F3A40) },
7318     { PREFIX_TABLE (PREFIX_0F3A41) },
7319     { PREFIX_TABLE (PREFIX_0F3A42) },
7320     { Bad_Opcode },
7321     { PREFIX_TABLE (PREFIX_0F3A44) },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 48 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 50 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 58 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 60 */
7353     { PREFIX_TABLE (PREFIX_0F3A60) },
7354     { PREFIX_TABLE (PREFIX_0F3A61) },
7355     { PREFIX_TABLE (PREFIX_0F3A62) },
7356     { PREFIX_TABLE (PREFIX_0F3A63) },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 68 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 70 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 78 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 80 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 88 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 90 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 98 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* a0 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* a8 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* b0 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* b8 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* c0 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* c8 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { PREFIX_TABLE (PREFIX_0F3ACC) },
7475     { Bad_Opcode },
7476     { PREFIX_TABLE (PREFIX_0F3ACE) },
7477     { PREFIX_TABLE (PREFIX_0F3ACF) },
7478     /* d0 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* d8 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { PREFIX_TABLE (PREFIX_0F3ADF) },
7496     /* e0 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* e8 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* f0 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* f8 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532   },
7533 };
7534
7535 static const struct dis386 xop_table[][256] = {
7536   /* XOP_08 */
7537   {
7538     /* 00 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 08 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 10 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 18 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 20 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 28 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 30 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 38 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 40 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 48 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 50 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 58 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 60 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 68 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 70 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 78 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 80 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7689     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7690     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7691     /* 88 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7699     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7700     /* 90 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     /* 98 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     /* a0 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     { Bad_Opcode },
7727     /* a8 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* b0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     { Bad_Opcode },
7745     /* b8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* c0 */
7755     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7756     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7757     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7758     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* c8 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7769     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7770     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7771     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7772     /* d0 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* d8 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     /* e0 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* e8 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7805     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7807     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7808     /* f0 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* f8 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826   },
7827   /* XOP_09 */
7828   {
7829     /* 00 */
7830     { Bad_Opcode },
7831     { REG_TABLE (REG_XOP_TBM_01) },
7832     { REG_TABLE (REG_XOP_TBM_02) },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 08 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 10 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { REG_TABLE (REG_XOP_LWPCB) },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 18 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 20 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 28 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 30 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 38 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 40 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 48 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 50 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 58 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 60 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 68 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 70 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 78 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 80 */
7974     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7975     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7976     { "vfrczss",        { XM, EXd }, 0 },
7977     { "vfrczsd",        { XM, EXq }, 0 },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 88 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 90 */
7992     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7996     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7997     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7998     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000     /* 98 */
8001     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8002     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8003     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8004     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* a0 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* a8 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* b0 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* b8 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* c0 */
8046     { Bad_Opcode },
8047     { "vphaddbw",       { XM, EXxmm }, 0 },
8048     { "vphaddbd",       { XM, EXxmm }, 0 },
8049     { "vphaddbq",       { XM, EXxmm }, 0 },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { "vphaddwd",       { XM, EXxmm }, 0 },
8053     { "vphaddwq",       { XM, EXxmm }, 0 },
8054     /* c8 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { "vphadddq",       { XM, EXxmm }, 0 },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* d0 */
8064     { Bad_Opcode },
8065     { "vphaddubw",      { XM, EXxmm }, 0 },
8066     { "vphaddubd",      { XM, EXxmm }, 0 },
8067     { "vphaddubq",      { XM, EXxmm }, 0 },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { "vphadduwd",      { XM, EXxmm }, 0 },
8071     { "vphadduwq",      { XM, EXxmm }, 0 },
8072     /* d8 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { "vphaddudq",      { XM, EXxmm }, 0 },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* e0 */
8082     { Bad_Opcode },
8083     { "vphsubbw",       { XM, EXxmm }, 0 },
8084     { "vphsubwd",       { XM, EXxmm }, 0 },
8085     { "vphsubdq",       { XM, EXxmm }, 0 },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* e8 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* f0 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* f8 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117   },
8118   /* XOP_0A */
8119   {
8120     /* 00 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 08 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 10 */
8139     { "bextr",  { Gv, Ev, Iq }, 0 },
8140     { Bad_Opcode },
8141     { REG_TABLE (REG_XOP_LWP) },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 18 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 20 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 28 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 30 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 38 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 40 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 48 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 50 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 58 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 60 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 68 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 70 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* 78 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 80 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* 88 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 90 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 98 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* a0 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* a8 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* b0 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* b8 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* c0 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* c8 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* d0 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* d8 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* e0 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* e8 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* f0 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* f8 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408   },
8409 };
8410
8411 static const struct dis386 vex_table[][256] = {
8412   /* VEX_0F */
8413   {
8414     /* 00 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 08 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 10 */
8433     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8436     { MOD_TABLE (MOD_VEX_0F13) },
8437     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8438     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8439     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8440     { MOD_TABLE (MOD_VEX_0F17) },
8441     /* 18 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 20 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 28 */
8460     { "vmovapX",        { XM, EXx }, 0 },
8461     { "vmovapX",        { EXxS, XM }, 0 },
8462     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8463     { MOD_TABLE (MOD_VEX_0F2B) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8467     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8468     /* 30 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 38 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* 40 */
8487     { Bad_Opcode },
8488     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8490     { Bad_Opcode },
8491     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8495     /* 48 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 50 */
8505     { MOD_TABLE (MOD_VEX_0F50) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8509     { "vandpX",         { XM, Vex, EXx }, 0 },
8510     { "vandnpX",        { XM, Vex, EXx }, 0 },
8511     { "vorpX",          { XM, Vex, EXx }, 0 },
8512     { "vxorpX",         { XM, Vex, EXx }, 0 },
8513     /* 58 */
8514     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8522     /* 60 */
8523     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8531     /* 68 */
8532     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8540     /* 70 */
8541     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8542     { REG_TABLE (REG_VEX_0F71) },
8543     { REG_TABLE (REG_VEX_0F72) },
8544     { REG_TABLE (REG_VEX_0F73) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8549     /* 78 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8558     /* 80 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* 88 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* 90 */
8577     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* 98 */
8586     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* a0 */
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* a8 */
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { REG_TABLE (REG_VEX_0FAE) },
8611     { Bad_Opcode },
8612     /* b0 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* b8 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* c0 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8634     { Bad_Opcode },
8635     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8637     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8638     { Bad_Opcode },
8639     /* c8 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* d0 */
8649     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8657     /* d8 */
8658     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8666     /* e0 */
8667     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8675     /* e8 */
8676     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8684     /* f0 */
8685     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8693     /* f8 */
8694     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8701     { Bad_Opcode },
8702   },
8703   /* VEX_0F38 */
8704   {
8705     /* 00 */
8706     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8714     /* 08 */
8715     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8723     /* 10 */
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8732     /* 18 */
8733     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8736     { Bad_Opcode },
8737     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8740     { Bad_Opcode },
8741     /* 20 */
8742     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     /* 28 */
8751     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8759     /* 30 */
8760     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8768     /* 38 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8777     /* 40 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8786     /* 48 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     /* 50 */
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     /* 58 */
8805     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* 60 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     /* 68 */
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* 70 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* 78 */
8841     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     /* 80 */
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* 88 */
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8864     { Bad_Opcode },
8865     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8866     { Bad_Opcode },
8867     /* 90 */
8868     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8876     /* 98 */
8877     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8885     /* a0 */
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8894     /* a8 */
8895     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8903     /* b0 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8912     /* b8 */
8913     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8921     /* c0 */
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     /* c8 */
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8939     /* d0 */
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     /* d8 */
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8957     /* e0 */
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     /* e8 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     /* f0 */
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8979     { REG_TABLE (REG_VEX_0F38F3) },
8980     { Bad_Opcode },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8984     /* f8 */
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993   },
8994   /* VEX_0F3A */
8995   {
8996     /* 00 */
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9004     { Bad_Opcode },
9005     /* 08 */
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9014     /* 10 */
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9023     /* 18 */
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 20 */
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     /* 28 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 30 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* 38 */
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 40 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9072     { Bad_Opcode },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9074     { Bad_Opcode },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9076     { Bad_Opcode },
9077     /* 48 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* 50 */
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     /* 58 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9104     /* 60 */
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* 68 */
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9122     /* 70 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* 78 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9140     /* 80 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* 88 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* 90 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* 98 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* a0 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     /* a8 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* b0 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     /* b8 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* c0 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     /* c8 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9229     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9230     /* d0 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* d8 */
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9248     /* e0 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* e8 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* f0 */
9267     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* f8 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284   },
9285 };
9286
9287 #define NEED_OPCODE_TABLE
9288 #include "i386-dis-evex.h"
9289 #undef NEED_OPCODE_TABLE
9290 static const struct dis386 vex_len_table[][2] = {
9291   /* VEX_LEN_0F12_P_0_M_0 */
9292   {
9293     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9294   },
9295
9296   /* VEX_LEN_0F12_P_0_M_1 */
9297   {
9298     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9299   },
9300
9301   /* VEX_LEN_0F12_P_2 */
9302   {
9303     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F13_M_0 */
9307   {
9308     { "vmovlpX",        { EXq, XM }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F16_P_0_M_0 */
9312   {
9313     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9314   },
9315
9316   /* VEX_LEN_0F16_P_0_M_1 */
9317   {
9318     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9319   },
9320
9321   /* VEX_LEN_0F16_P_2 */
9322   {
9323     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9324   },
9325
9326   /* VEX_LEN_0F17_M_0 */
9327   {
9328     { "vmovhpX",        { EXq, XM }, 0 },
9329   },
9330
9331   /* VEX_LEN_0F2A_P_1 */
9332   {
9333     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9334     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9335   },
9336
9337   /* VEX_LEN_0F2A_P_3 */
9338   {
9339     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9340     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9341   },
9342
9343   /* VEX_LEN_0F2C_P_1 */
9344   {
9345     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9346     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9347   },
9348
9349   /* VEX_LEN_0F2C_P_3 */
9350   {
9351     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9352     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9353   },
9354
9355   /* VEX_LEN_0F2D_P_1 */
9356   {
9357     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9358     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9359   },
9360
9361   /* VEX_LEN_0F2D_P_3 */
9362   {
9363     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9364     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9365   },
9366
9367   /* VEX_LEN_0F41_P_0 */
9368   {
9369     { Bad_Opcode },
9370     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9371   },
9372   /* VEX_LEN_0F41_P_2 */
9373   {
9374     { Bad_Opcode },
9375     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9376   },
9377   /* VEX_LEN_0F42_P_0 */
9378   {
9379     { Bad_Opcode },
9380     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9381   },
9382   /* VEX_LEN_0F42_P_2 */
9383   {
9384     { Bad_Opcode },
9385     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9386   },
9387   /* VEX_LEN_0F44_P_0 */
9388   {
9389     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9390   },
9391   /* VEX_LEN_0F44_P_2 */
9392   {
9393     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9394   },
9395   /* VEX_LEN_0F45_P_0 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9399   },
9400   /* VEX_LEN_0F45_P_2 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9404   },
9405   /* VEX_LEN_0F46_P_0 */
9406   {
9407     { Bad_Opcode },
9408     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9409   },
9410   /* VEX_LEN_0F46_P_2 */
9411   {
9412     { Bad_Opcode },
9413     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9414   },
9415   /* VEX_LEN_0F47_P_0 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9419   },
9420   /* VEX_LEN_0F47_P_2 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9424   },
9425   /* VEX_LEN_0F4A_P_0 */
9426   {
9427     { Bad_Opcode },
9428     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9429   },
9430   /* VEX_LEN_0F4A_P_2 */
9431   {
9432     { Bad_Opcode },
9433     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9434   },
9435   /* VEX_LEN_0F4B_P_0 */
9436   {
9437     { Bad_Opcode },
9438     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9439   },
9440   /* VEX_LEN_0F4B_P_2 */
9441   {
9442     { Bad_Opcode },
9443     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9444   },
9445
9446   /* VEX_LEN_0F6E_P_2 */
9447   {
9448     { "vmovK",          { XMScalar, Edq }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F77_P_1 */
9452   {
9453     { "vzeroupper",     { XX }, 0 },
9454     { "vzeroall",       { XX }, 0 },
9455   },
9456
9457   /* VEX_LEN_0F7E_P_1 */
9458   {
9459     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9460   },
9461
9462   /* VEX_LEN_0F7E_P_2 */
9463   {
9464     { "vmovK",          { Edq, XMScalar }, 0 },
9465   },
9466
9467   /* VEX_LEN_0F90_P_0 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F90_P_2 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F91_P_0 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F91_P_2 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F92_P_0 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0F92_P_2 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9495   },
9496
9497   /* VEX_LEN_0F92_P_3 */
9498   {
9499     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9500   },
9501
9502   /* VEX_LEN_0F93_P_0 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9505   },
9506
9507   /* VEX_LEN_0F93_P_2 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9510   },
9511
9512   /* VEX_LEN_0F93_P_3 */
9513   {
9514     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0F98_P_0 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9520   },
9521
9522   /* VEX_LEN_0F98_P_2 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9525   },
9526
9527   /* VEX_LEN_0F99_P_0 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9530   },
9531
9532   /* VEX_LEN_0F99_P_2 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9535   },
9536
9537   /* VEX_LEN_0FAE_R_2_M_0 */
9538   {
9539     { "vldmxcsr",       { Md }, 0 },
9540   },
9541
9542   /* VEX_LEN_0FAE_R_3_M_0 */
9543   {
9544     { "vstmxcsr",       { Md }, 0 },
9545   },
9546
9547   /* VEX_LEN_0FC4_P_2 */
9548   {
9549     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9550   },
9551
9552   /* VEX_LEN_0FC5_P_2 */
9553   {
9554     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9555   },
9556
9557   /* VEX_LEN_0FD6_P_2 */
9558   {
9559     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9560   },
9561
9562   /* VEX_LEN_0FF7_P_2 */
9563   {
9564     { "vmaskmovdqu",    { XM, XS }, 0 },
9565   },
9566
9567   /* VEX_LEN_0F3816_P_2 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9571   },
9572
9573   /* VEX_LEN_0F3819_P_2 */
9574   {
9575     { Bad_Opcode },
9576     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9577   },
9578
9579   /* VEX_LEN_0F381A_P_2_M_0 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9583   },
9584
9585   /* VEX_LEN_0F3836_P_2 */
9586   {
9587     { Bad_Opcode },
9588     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9589   },
9590
9591   /* VEX_LEN_0F3841_P_2 */
9592   {
9593     { "vphminposuw",    { XM, EXx }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F385A_P_2_M_0 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9600   },
9601
9602   /* VEX_LEN_0F38DB_P_2 */
9603   {
9604     { "vaesimc",        { XM, EXx }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F38F2_P_0 */
9608   {
9609     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9610   },
9611
9612   /* VEX_LEN_0F38F3_R_1_P_0 */
9613   {
9614     { "blsrS",          { VexGdq, Edq }, 0 },
9615   },
9616
9617   /* VEX_LEN_0F38F3_R_2_P_0 */
9618   {
9619     { "blsmskS",        { VexGdq, Edq }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F38F3_R_3_P_0 */
9623   {
9624     { "blsiS",          { VexGdq, Edq }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F38F5_P_0 */
9628   {
9629     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F38F5_P_1 */
9633   {
9634     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F38F5_P_3 */
9638   {
9639     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F38F6_P_3 */
9643   {
9644     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F38F7_P_0 */
9648   {
9649     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9650   },
9651
9652   /* VEX_LEN_0F38F7_P_1 */
9653   {
9654     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9655   },
9656
9657   /* VEX_LEN_0F38F7_P_2 */
9658   {
9659     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9660   },
9661
9662   /* VEX_LEN_0F38F7_P_3 */
9663   {
9664     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9665   },
9666
9667   /* VEX_LEN_0F3A00_P_2 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9671   },
9672
9673   /* VEX_LEN_0F3A01_P_2 */
9674   {
9675     { Bad_Opcode },
9676     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9677   },
9678
9679   /* VEX_LEN_0F3A06_P_2 */
9680   {
9681     { Bad_Opcode },
9682     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9683   },
9684
9685   /* VEX_LEN_0F3A14_P_2 */
9686   {
9687     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F3A15_P_2 */
9691   {
9692     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9693   },
9694
9695   /* VEX_LEN_0F3A16_P_2  */
9696   {
9697     { "vpextrK",        { Edq, XM, Ib }, 0 },
9698   },
9699
9700   /* VEX_LEN_0F3A17_P_2 */
9701   {
9702     { "vextractps",     { Edqd, XM, Ib }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F3A18_P_2 */
9706   {
9707     { Bad_Opcode },
9708     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9709   },
9710
9711   /* VEX_LEN_0F3A19_P_2 */
9712   {
9713     { Bad_Opcode },
9714     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9715   },
9716
9717   /* VEX_LEN_0F3A20_P_2 */
9718   {
9719     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F3A21_P_2 */
9723   {
9724     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9725   },
9726
9727   /* VEX_LEN_0F3A22_P_2 */
9728   {
9729     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9730   },
9731
9732   /* VEX_LEN_0F3A30_P_2 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9735   },
9736
9737   /* VEX_LEN_0F3A31_P_2 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9740   },
9741
9742   /* VEX_LEN_0F3A32_P_2 */
9743   {
9744     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9745   },
9746
9747   /* VEX_LEN_0F3A33_P_2 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9750   },
9751
9752   /* VEX_LEN_0F3A38_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9756   },
9757
9758   /* VEX_LEN_0F3A39_P_2 */
9759   {
9760     { Bad_Opcode },
9761     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9762   },
9763
9764   /* VEX_LEN_0F3A41_P_2 */
9765   {
9766     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9767   },
9768
9769   /* VEX_LEN_0F3A46_P_2 */
9770   {
9771     { Bad_Opcode },
9772     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9773   },
9774
9775   /* VEX_LEN_0F3A60_P_2 */
9776   {
9777     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A61_P_2 */
9781   {
9782     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F3A62_P_2 */
9786   {
9787     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9788   },
9789
9790   /* VEX_LEN_0F3A63_P_2 */
9791   {
9792     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9793   },
9794
9795   /* VEX_LEN_0F3A6A_P_2 */
9796   {
9797     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F3A6B_P_2 */
9801   {
9802     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9803   },
9804
9805   /* VEX_LEN_0F3A6E_P_2 */
9806   {
9807     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9808   },
9809
9810   /* VEX_LEN_0F3A6F_P_2 */
9811   {
9812     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9813   },
9814
9815   /* VEX_LEN_0F3A7A_P_2 */
9816   {
9817     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9818   },
9819
9820   /* VEX_LEN_0F3A7B_P_2 */
9821   {
9822     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9823   },
9824
9825   /* VEX_LEN_0F3A7E_P_2 */
9826   {
9827     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9828   },
9829
9830   /* VEX_LEN_0F3A7F_P_2 */
9831   {
9832     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9833   },
9834
9835   /* VEX_LEN_0F3ADF_P_2 */
9836   {
9837     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9838   },
9839
9840   /* VEX_LEN_0F3AF0_P_3 */
9841   {
9842     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9843   },
9844
9845   /* VEX_LEN_0FXOP_08_CC */
9846   {
9847      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9848   },
9849
9850   /* VEX_LEN_0FXOP_08_CD */
9851   {
9852      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9853   },
9854
9855   /* VEX_LEN_0FXOP_08_CE */
9856   {
9857      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_08_CF */
9861   {
9862      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9863   },
9864
9865   /* VEX_LEN_0FXOP_08_EC */
9866   {
9867      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9868   },
9869
9870   /* VEX_LEN_0FXOP_08_ED */
9871   {
9872      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9873   },
9874
9875   /* VEX_LEN_0FXOP_08_EE */
9876   {
9877      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9878   },
9879
9880   /* VEX_LEN_0FXOP_08_EF */
9881   {
9882      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9883   },
9884
9885   /* VEX_LEN_0FXOP_09_80 */
9886   {
9887     { "vfrczps",        { XM, EXxmm }, 0 },
9888     { "vfrczps",        { XM, EXymmq }, 0 },
9889   },
9890
9891   /* VEX_LEN_0FXOP_09_81 */
9892   {
9893     { "vfrczpd",        { XM, EXxmm }, 0 },
9894     { "vfrczpd",        { XM, EXymmq }, 0 },
9895   },
9896 };
9897
9898 static const struct dis386 evex_len_table[][3] = {
9899 #define NEED_EVEX_LEN_TABLE
9900 #include "i386-dis-evex.h"
9901 #undef NEED_EVEX_LEN_TABLE
9902 };
9903
9904 static const struct dis386 vex_w_table[][2] = {
9905   {
9906     /* VEX_W_0F41_P_0_LEN_1 */
9907     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9908     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9909   },
9910   {
9911     /* VEX_W_0F41_P_2_LEN_1 */
9912     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9913     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9914   },
9915   {
9916     /* VEX_W_0F42_P_0_LEN_1 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F42_P_2_LEN_1 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9924   },
9925   {
9926     /* VEX_W_0F44_P_0_LEN_0 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9928     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9929   },
9930   {
9931     /* VEX_W_0F44_P_2_LEN_0 */
9932     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9933     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9934   },
9935   {
9936     /* VEX_W_0F45_P_0_LEN_1 */
9937     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9938     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9939   },
9940   {
9941     /* VEX_W_0F45_P_2_LEN_1 */
9942     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9943     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9944   },
9945   {
9946     /* VEX_W_0F46_P_0_LEN_1 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9948     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9949   },
9950   {
9951     /* VEX_W_0F46_P_2_LEN_1 */
9952     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9953     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9954   },
9955   {
9956     /* VEX_W_0F47_P_0_LEN_1 */
9957     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9958     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9959   },
9960   {
9961     /* VEX_W_0F47_P_2_LEN_1 */
9962     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9963     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F4A_P_0_LEN_1 */
9967     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9968     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9969   },
9970   {
9971     /* VEX_W_0F4A_P_2_LEN_1 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9973     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9974   },
9975   {
9976     /* VEX_W_0F4B_P_0_LEN_1 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9979   },
9980   {
9981     /* VEX_W_0F4B_P_2_LEN_1 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9983   },
9984   {
9985     /* VEX_W_0F90_P_0_LEN_0 */
9986     { "kmovw",          { MaskG, MaskE }, 0 },
9987     { "kmovq",          { MaskG, MaskE }, 0 },
9988   },
9989   {
9990     /* VEX_W_0F90_P_2_LEN_0 */
9991     { "kmovb",          { MaskG, MaskBDE }, 0 },
9992     { "kmovd",          { MaskG, MaskBDE }, 0 },
9993   },
9994   {
9995     /* VEX_W_0F91_P_0_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9997     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9998   },
9999   {
10000     /* VEX_W_0F91_P_2_LEN_0 */
10001     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10002     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F92_P_0_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10007   },
10008   {
10009     /* VEX_W_0F92_P_2_LEN_0 */
10010     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10011   },
10012   {
10013     /* VEX_W_0F93_P_0_LEN_0 */
10014     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10015   },
10016   {
10017     /* VEX_W_0F93_P_2_LEN_0 */
10018     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10019   },
10020   {
10021     /* VEX_W_0F98_P_0_LEN_0 */
10022     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10023     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F98_P_2_LEN_0 */
10027     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10028     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F99_P_0_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10033     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10034   },
10035   {
10036     /* VEX_W_0F99_P_2_LEN_0 */
10037     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10038     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10039   },
10040   {
10041     /* VEX_W_0F380C_P_2  */
10042     { "vpermilps",      { XM, Vex, EXx }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F380D_P_2  */
10046     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F380E_P_2  */
10050     { "vtestps",        { XM, EXx }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F380F_P_2  */
10054     { "vtestpd",        { XM, EXx }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3816_P_2  */
10058     { "vpermps",        { XM, Vex, EXx }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F3818_P_2 */
10062     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F3819_P_2 */
10066     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F381A_P_2_M_0 */
10070     { "vbroadcastf128", { XM, Mxmm }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F382C_P_2_M_0 */
10074     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F382D_P_2_M_0 */
10078     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F382E_P_2_M_0 */
10082     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F382F_P_2_M_0 */
10086     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F3836_P_2  */
10090     { "vpermd",         { XM, Vex, EXx }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3846_P_2 */
10094     { "vpsravd",        { XM, Vex, EXx }, 0 },
10095   },
10096   {
10097     /* VEX_W_0F3858_P_2 */
10098     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10099   },
10100   {
10101     /* VEX_W_0F3859_P_2 */
10102     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F385A_P_2_M_0 */
10106     { "vbroadcasti128", { XM, Mxmm }, 0 },
10107   },
10108   {
10109     /* VEX_W_0F3878_P_2 */
10110     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10111   },
10112   {
10113     /* VEX_W_0F3879_P_2 */
10114     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10115   },
10116   {
10117     /* VEX_W_0F38CF_P_2 */
10118     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A00_P_2 */
10122     { Bad_Opcode },
10123     { "vpermq",         { XM, EXx, Ib }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F3A01_P_2 */
10127     { Bad_Opcode },
10128     { "vpermpd",        { XM, EXx, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A02_P_2 */
10132     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A04_P_2 */
10136     { "vpermilps",      { XM, EXx, Ib }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F3A05_P_2 */
10140     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F3A06_P_2 */
10144     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10145   },
10146   {
10147     /* VEX_W_0F3A18_P_2 */
10148     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10149   },
10150   {
10151     /* VEX_W_0F3A19_P_2 */
10152     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10153   },
10154   {
10155     /* VEX_W_0F3A30_P_2_LEN_0 */
10156     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10157     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10158   },
10159   {
10160     /* VEX_W_0F3A31_P_2_LEN_0 */
10161     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10162     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10163   },
10164   {
10165     /* VEX_W_0F3A32_P_2_LEN_0 */
10166     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10167     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10168   },
10169   {
10170     /* VEX_W_0F3A33_P_2_LEN_0 */
10171     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10172     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10173   },
10174   {
10175     /* VEX_W_0F3A38_P_2 */
10176     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F3A39_P_2 */
10180     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10181   },
10182   {
10183     /* VEX_W_0F3A46_P_2 */
10184     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10185   },
10186   {
10187     /* VEX_W_0F3A48_P_2 */
10188     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10189     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10190   },
10191   {
10192     /* VEX_W_0F3A49_P_2 */
10193     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10194     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3A4A_P_2 */
10198     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3A4B_P_2 */
10202     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10203   },
10204   {
10205     /* VEX_W_0F3A4C_P_2 */
10206     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10207   },
10208   {
10209     /* VEX_W_0F3ACE_P_2 */
10210     { Bad_Opcode },
10211     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F3ACF_P_2 */
10215     { Bad_Opcode },
10216     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10217   },
10218 #define NEED_VEX_W_TABLE
10219 #include "i386-dis-evex.h"
10220 #undef NEED_VEX_W_TABLE
10221 };
10222
10223 static const struct dis386 mod_table[][2] = {
10224   {
10225     /* MOD_8D */
10226     { "leaS",           { Gv, M }, 0 },
10227   },
10228   {
10229     /* MOD_C6_REG_7 */
10230     { Bad_Opcode },
10231     { RM_TABLE (RM_C6_REG_7) },
10232   },
10233   {
10234     /* MOD_C7_REG_7 */
10235     { Bad_Opcode },
10236     { RM_TABLE (RM_C7_REG_7) },
10237   },
10238   {
10239     /* MOD_FF_REG_3 */
10240     { "Jcall^", { indirEp }, 0 },
10241   },
10242   {
10243     /* MOD_FF_REG_5 */
10244     { "Jjmp^", { indirEp }, 0 },
10245   },
10246   {
10247     /* MOD_0F01_REG_0 */
10248     { X86_64_TABLE (X86_64_0F01_REG_0) },
10249     { RM_TABLE (RM_0F01_REG_0) },
10250   },
10251   {
10252     /* MOD_0F01_REG_1 */
10253     { X86_64_TABLE (X86_64_0F01_REG_1) },
10254     { RM_TABLE (RM_0F01_REG_1) },
10255   },
10256   {
10257     /* MOD_0F01_REG_2 */
10258     { X86_64_TABLE (X86_64_0F01_REG_2) },
10259     { RM_TABLE (RM_0F01_REG_2) },
10260   },
10261   {
10262     /* MOD_0F01_REG_3 */
10263     { X86_64_TABLE (X86_64_0F01_REG_3) },
10264     { RM_TABLE (RM_0F01_REG_3) },
10265   },
10266   {
10267     /* MOD_0F01_REG_5 */
10268     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10269     { RM_TABLE (RM_0F01_REG_5) },
10270   },
10271   {
10272     /* MOD_0F01_REG_7 */
10273     { "invlpg",         { Mb }, 0 },
10274     { RM_TABLE (RM_0F01_REG_7) },
10275   },
10276   {
10277     /* MOD_0F12_PREFIX_0 */
10278     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10279     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10280   },
10281   {
10282     /* MOD_0F13 */
10283     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10284   },
10285   {
10286     /* MOD_0F16_PREFIX_0 */
10287     { "movhps",         { XM, EXq }, 0 },
10288     { "movlhps",        { XM, EXq }, 0 },
10289   },
10290   {
10291     /* MOD_0F17 */
10292     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10293   },
10294   {
10295     /* MOD_0F18_REG_0 */
10296     { "prefetchnta",    { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_1 */
10300     { "prefetcht0",     { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_2 */
10304     { "prefetcht1",     { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_3 */
10308     { "prefetcht2",     { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F18_REG_4 */
10312     { "nop/reserved",   { Mb }, 0 },
10313   },
10314   {
10315     /* MOD_0F18_REG_5 */
10316     { "nop/reserved",   { Mb }, 0 },
10317   },
10318   {
10319     /* MOD_0F18_REG_6 */
10320     { "nop/reserved",   { Mb }, 0 },
10321   },
10322   {
10323     /* MOD_0F18_REG_7 */
10324     { "nop/reserved",   { Mb }, 0 },
10325   },
10326   {
10327     /* MOD_0F1A_PREFIX_0 */
10328     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10329     { "nopQ",           { Ev }, 0 },
10330   },
10331   {
10332     /* MOD_0F1B_PREFIX_0 */
10333     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10334     { "nopQ",           { Ev }, 0 },
10335   },
10336   {
10337     /* MOD_0F1B_PREFIX_1 */
10338     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10339     { "nopQ",           { Ev }, 0 },
10340   },
10341   {
10342     /* MOD_0F1C_PREFIX_0 */
10343     { REG_TABLE (REG_0F1C_MOD_0) },
10344     { "nopQ",           { Ev }, 0 },
10345   },
10346   {
10347     /* MOD_0F1E_PREFIX_1 */
10348     { "nopQ",           { Ev }, 0 },
10349     { REG_TABLE (REG_0F1E_MOD_3) },
10350   },
10351   {
10352     /* MOD_0F24 */
10353     { Bad_Opcode },
10354     { "movL",           { Rd, Td }, 0 },
10355   },
10356   {
10357     /* MOD_0F26 */
10358     { Bad_Opcode },
10359     { "movL",           { Td, Rd }, 0 },
10360   },
10361   {
10362     /* MOD_0F2B_PREFIX_0 */
10363     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10364   },
10365   {
10366     /* MOD_0F2B_PREFIX_1 */
10367     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10368   },
10369   {
10370     /* MOD_0F2B_PREFIX_2 */
10371     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10372   },
10373   {
10374     /* MOD_0F2B_PREFIX_3 */
10375     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10376   },
10377   {
10378     /* MOD_0F51 */
10379     { Bad_Opcode },
10380     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10381   },
10382   {
10383     /* MOD_0F71_REG_2 */
10384     { Bad_Opcode },
10385     { "psrlw",          { MS, Ib }, 0 },
10386   },
10387   {
10388     /* MOD_0F71_REG_4 */
10389     { Bad_Opcode },
10390     { "psraw",          { MS, Ib }, 0 },
10391   },
10392   {
10393     /* MOD_0F71_REG_6 */
10394     { Bad_Opcode },
10395     { "psllw",          { MS, Ib }, 0 },
10396   },
10397   {
10398     /* MOD_0F72_REG_2 */
10399     { Bad_Opcode },
10400     { "psrld",          { MS, Ib }, 0 },
10401   },
10402   {
10403     /* MOD_0F72_REG_4 */
10404     { Bad_Opcode },
10405     { "psrad",          { MS, Ib }, 0 },
10406   },
10407   {
10408     /* MOD_0F72_REG_6 */
10409     { Bad_Opcode },
10410     { "pslld",          { MS, Ib }, 0 },
10411   },
10412   {
10413     /* MOD_0F73_REG_2 */
10414     { Bad_Opcode },
10415     { "psrlq",          { MS, Ib }, 0 },
10416   },
10417   {
10418     /* MOD_0F73_REG_3 */
10419     { Bad_Opcode },
10420     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10421   },
10422   {
10423     /* MOD_0F73_REG_6 */
10424     { Bad_Opcode },
10425     { "psllq",          { MS, Ib }, 0 },
10426   },
10427   {
10428     /* MOD_0F73_REG_7 */
10429     { Bad_Opcode },
10430     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10431   },
10432   {
10433     /* MOD_0FAE_REG_0 */
10434     { "fxsave",         { FXSAVE }, 0 },
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10436   },
10437   {
10438     /* MOD_0FAE_REG_1 */
10439     { "fxrstor",        { FXSAVE }, 0 },
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10441   },
10442   {
10443     /* MOD_0FAE_REG_2 */
10444     { "ldmxcsr",        { Md }, 0 },
10445     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10446   },
10447   {
10448     /* MOD_0FAE_REG_3 */
10449     { "stmxcsr",        { Md }, 0 },
10450     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10451   },
10452   {
10453     /* MOD_0FAE_REG_4 */
10454     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10455     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10456   },
10457   {
10458     /* MOD_0FAE_REG_5 */
10459     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10460     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10461   },
10462   {
10463     /* MOD_0FAE_REG_6 */
10464     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10465     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10466   },
10467   {
10468     /* MOD_0FAE_REG_7 */
10469     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10470     { RM_TABLE (RM_0FAE_REG_7) },
10471   },
10472   {
10473     /* MOD_0FB2 */
10474     { "lssS",           { Gv, Mp }, 0 },
10475   },
10476   {
10477     /* MOD_0FB4 */
10478     { "lfsS",           { Gv, Mp }, 0 },
10479   },
10480   {
10481     /* MOD_0FB5 */
10482     { "lgsS",           { Gv, Mp }, 0 },
10483   },
10484   {
10485     /* MOD_0FC3 */
10486     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10487   },
10488   {
10489     /* MOD_0FC7_REG_3 */
10490     { "xrstors",        { FXSAVE }, 0 },
10491   },
10492   {
10493     /* MOD_0FC7_REG_4 */
10494     { "xsavec",         { FXSAVE }, 0 },
10495   },
10496   {
10497     /* MOD_0FC7_REG_5 */
10498     { "xsaves",         { FXSAVE }, 0 },
10499   },
10500   {
10501     /* MOD_0FC7_REG_6 */
10502     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10503     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10504   },
10505   {
10506     /* MOD_0FC7_REG_7 */
10507     { "vmptrst",        { Mq }, 0 },
10508     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10509   },
10510   {
10511     /* MOD_0FD7 */
10512     { Bad_Opcode },
10513     { "pmovmskb",       { Gdq, MS }, 0 },
10514   },
10515   {
10516     /* MOD_0FE7_PREFIX_2 */
10517     { "movntdq",        { Mx, XM }, 0 },
10518   },
10519   {
10520     /* MOD_0FF0_PREFIX_3 */
10521     { "lddqu",          { XM, M }, 0 },
10522   },
10523   {
10524     /* MOD_0F382A_PREFIX_2 */
10525     { "movntdqa",       { XM, Mx }, 0 },
10526   },
10527   {
10528     /* MOD_0F38F5_PREFIX_2 */
10529     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10530   },
10531   {
10532     /* MOD_0F38F6_PREFIX_0 */
10533     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10534   },
10535   {
10536     /* MOD_0F38F8_PREFIX_1 */
10537     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10538   },
10539   {
10540     /* MOD_0F38F8_PREFIX_2 */
10541     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10542   },
10543   {
10544     /* MOD_0F38F8_PREFIX_3 */
10545     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10546   },
10547   {
10548     /* MOD_0F38F9_PREFIX_0 */
10549     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10550   },
10551   {
10552     /* MOD_62_32BIT */
10553     { "bound{S|}",      { Gv, Ma }, 0 },
10554     { EVEX_TABLE (EVEX_0F) },
10555   },
10556   {
10557     /* MOD_C4_32BIT */
10558     { "lesS",           { Gv, Mp }, 0 },
10559     { VEX_C4_TABLE (VEX_0F) },
10560   },
10561   {
10562     /* MOD_C5_32BIT */
10563     { "ldsS",           { Gv, Mp }, 0 },
10564     { VEX_C5_TABLE (VEX_0F) },
10565   },
10566   {
10567     /* MOD_VEX_0F12_PREFIX_0 */
10568     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10569     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10570   },
10571   {
10572     /* MOD_VEX_0F13 */
10573     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10574   },
10575   {
10576     /* MOD_VEX_0F16_PREFIX_0 */
10577     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10578     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10579   },
10580   {
10581     /* MOD_VEX_0F17 */
10582     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10583   },
10584   {
10585     /* MOD_VEX_0F2B */
10586     { "vmovntpX",       { Mx, XM }, 0 },
10587   },
10588   {
10589     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10590     { Bad_Opcode },
10591     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10592   },
10593   {
10594     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10595     { Bad_Opcode },
10596     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10597   },
10598   {
10599     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10600     { Bad_Opcode },
10601     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10602   },
10603   {
10604     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10605     { Bad_Opcode },
10606     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10607   },
10608   {
10609     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10610     { Bad_Opcode },
10611     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10612   },
10613   {
10614     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10615     { Bad_Opcode },
10616     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10617   },
10618   {
10619     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10620     { Bad_Opcode },
10621     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10622   },
10623   {
10624     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10625     { Bad_Opcode },
10626     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10627   },
10628   {
10629     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10630     { Bad_Opcode },
10631     { "knotw",          { MaskG, MaskR }, 0 },
10632   },
10633   {
10634     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10635     { Bad_Opcode },
10636     { "knotq",          { MaskG, MaskR }, 0 },
10637   },
10638   {
10639     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10640     { Bad_Opcode },
10641     { "knotb",          { MaskG, MaskR }, 0 },
10642   },
10643   {
10644     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10645     { Bad_Opcode },
10646     { "knotd",          { MaskG, MaskR }, 0 },
10647   },
10648   {
10649     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10650     { Bad_Opcode },
10651     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10652   },
10653   {
10654     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10655     { Bad_Opcode },
10656     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10657   },
10658   {
10659     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10660     { Bad_Opcode },
10661     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10662   },
10663   {
10664     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10665     { Bad_Opcode },
10666     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10667   },
10668  {
10669     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10670     { Bad_Opcode },
10671     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10672   },
10673   {
10674     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10675     { Bad_Opcode },
10676     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10677   },
10678   {
10679     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10680     { Bad_Opcode },
10681     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10682   },
10683   {
10684     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10685     { Bad_Opcode },
10686     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10687   },
10688   {
10689     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10690     { Bad_Opcode },
10691     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10692   },
10693   {
10694     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10695     { Bad_Opcode },
10696     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10697   },
10698   {
10699     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10700     { Bad_Opcode },
10701     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10702   },
10703   {
10704     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10705     { Bad_Opcode },
10706     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10707   },
10708   {
10709     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10710     { Bad_Opcode },
10711     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10712   },
10713   {
10714     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10715     { Bad_Opcode },
10716     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10717   },
10718   {
10719     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10720     { Bad_Opcode },
10721     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10722   },
10723   {
10724     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10725     { Bad_Opcode },
10726     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10727   },
10728   {
10729     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10730     { Bad_Opcode },
10731     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10732   },
10733   {
10734     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10735     { Bad_Opcode },
10736     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10737   },
10738   {
10739     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10740     { Bad_Opcode },
10741     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10742   },
10743   {
10744     /* MOD_VEX_0F50 */
10745     { Bad_Opcode },
10746     { "vmovmskpX",      { Gdq, XS }, 0 },
10747   },
10748   {
10749     /* MOD_VEX_0F71_REG_2 */
10750     { Bad_Opcode },
10751     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10752   },
10753   {
10754     /* MOD_VEX_0F71_REG_4 */
10755     { Bad_Opcode },
10756     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10757   },
10758   {
10759     /* MOD_VEX_0F71_REG_6 */
10760     { Bad_Opcode },
10761     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10762   },
10763   {
10764     /* MOD_VEX_0F72_REG_2 */
10765     { Bad_Opcode },
10766     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10767   },
10768   {
10769     /* MOD_VEX_0F72_REG_4 */
10770     { Bad_Opcode },
10771     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10772   },
10773   {
10774     /* MOD_VEX_0F72_REG_6 */
10775     { Bad_Opcode },
10776     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10777   },
10778   {
10779     /* MOD_VEX_0F73_REG_2 */
10780     { Bad_Opcode },
10781     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10782   },
10783   {
10784     /* MOD_VEX_0F73_REG_3 */
10785     { Bad_Opcode },
10786     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10787   },
10788   {
10789     /* MOD_VEX_0F73_REG_6 */
10790     { Bad_Opcode },
10791     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10792   },
10793   {
10794     /* MOD_VEX_0F73_REG_7 */
10795     { Bad_Opcode },
10796     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10797   },
10798   {
10799     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10800     { "kmovw",          { Ew, MaskG }, 0 },
10801     { Bad_Opcode },
10802   },
10803   {
10804     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10805     { "kmovq",          { Eq, MaskG }, 0 },
10806     { Bad_Opcode },
10807   },
10808   {
10809     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10810     { "kmovb",          { Eb, MaskG }, 0 },
10811     { Bad_Opcode },
10812   },
10813   {
10814     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10815     { "kmovd",          { Ed, MaskG }, 0 },
10816     { Bad_Opcode },
10817   },
10818   {
10819     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10820     { Bad_Opcode },
10821     { "kmovw",          { MaskG, Rdq }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10825     { Bad_Opcode },
10826     { "kmovb",          { MaskG, Rdq }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_0F92_P_3_LEN_0 */
10830     { Bad_Opcode },
10831     { "kmovK",          { MaskG, Rdq }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10835     { Bad_Opcode },
10836     { "kmovw",          { Gdq, MaskR }, 0 },
10837   },
10838   {
10839     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10840     { Bad_Opcode },
10841     { "kmovb",          { Gdq, MaskR }, 0 },
10842   },
10843   {
10844     /* MOD_VEX_0F93_P_3_LEN_0 */
10845     { Bad_Opcode },
10846     { "kmovK",          { Gdq, MaskR }, 0 },
10847   },
10848   {
10849     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10850     { Bad_Opcode },
10851     { "kortestw", { MaskG, MaskR }, 0 },
10852   },
10853   {
10854     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10855     { Bad_Opcode },
10856     { "kortestq", { MaskG, MaskR }, 0 },
10857   },
10858   {
10859     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10860     { Bad_Opcode },
10861     { "kortestb", { MaskG, MaskR }, 0 },
10862   },
10863   {
10864     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10865     { Bad_Opcode },
10866     { "kortestd", { MaskG, MaskR }, 0 },
10867   },
10868   {
10869     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10870     { Bad_Opcode },
10871     { "ktestw", { MaskG, MaskR }, 0 },
10872   },
10873   {
10874     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10875     { Bad_Opcode },
10876     { "ktestq", { MaskG, MaskR }, 0 },
10877   },
10878   {
10879     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10880     { Bad_Opcode },
10881     { "ktestb", { MaskG, MaskR }, 0 },
10882   },
10883   {
10884     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10885     { Bad_Opcode },
10886     { "ktestd", { MaskG, MaskR }, 0 },
10887   },
10888   {
10889     /* MOD_VEX_0FAE_REG_2 */
10890     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10891   },
10892   {
10893     /* MOD_VEX_0FAE_REG_3 */
10894     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10895   },
10896   {
10897     /* MOD_VEX_0FD7_PREFIX_2 */
10898     { Bad_Opcode },
10899     { "vpmovmskb",      { Gdq, XS }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0FE7_PREFIX_2 */
10903     { "vmovntdq",       { Mx, XM }, 0 },
10904   },
10905   {
10906     /* MOD_VEX_0FF0_PREFIX_3 */
10907     { "vlddqu",         { XM, M }, 0 },
10908   },
10909   {
10910     /* MOD_VEX_0F381A_PREFIX_2 */
10911     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F382A_PREFIX_2 */
10915     { "vmovntdqa",      { XM, Mx }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0F382C_PREFIX_2 */
10919     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10920   },
10921   {
10922     /* MOD_VEX_0F382D_PREFIX_2 */
10923     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10924   },
10925   {
10926     /* MOD_VEX_0F382E_PREFIX_2 */
10927     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10928   },
10929   {
10930     /* MOD_VEX_0F382F_PREFIX_2 */
10931     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10932   },
10933   {
10934     /* MOD_VEX_0F385A_PREFIX_2 */
10935     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10936   },
10937   {
10938     /* MOD_VEX_0F388C_PREFIX_2 */
10939     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_0F388E_PREFIX_2 */
10943     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10944   },
10945   {
10946     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10947     { Bad_Opcode },
10948     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10949   },
10950   {
10951     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10952     { Bad_Opcode },
10953     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10954   },
10955   {
10956     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10957     { Bad_Opcode },
10958     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10959   },
10960   {
10961     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10962     { Bad_Opcode },
10963     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10964   },
10965   {
10966     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10967     { Bad_Opcode },
10968     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10969   },
10970   {
10971     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10972     { Bad_Opcode },
10973     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10974   },
10975   {
10976     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10977     { Bad_Opcode },
10978     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10979   },
10980   {
10981     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10982     { Bad_Opcode },
10983     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10984   },
10985 #define NEED_MOD_TABLE
10986 #include "i386-dis-evex.h"
10987 #undef NEED_MOD_TABLE
10988 };
10989
10990 static const struct dis386 rm_table[][8] = {
10991   {
10992     /* RM_C6_REG_7 */
10993     { "xabort",         { Skip_MODRM, Ib }, 0 },
10994   },
10995   {
10996     /* RM_C7_REG_7 */
10997     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10998   },
10999   {
11000     /* RM_0F01_REG_0 */
11001     { "enclv",          { Skip_MODRM }, 0 },
11002     { "vmcall",         { Skip_MODRM }, 0 },
11003     { "vmlaunch",       { Skip_MODRM }, 0 },
11004     { "vmresume",       { Skip_MODRM }, 0 },
11005     { "vmxoff",         { Skip_MODRM }, 0 },
11006     { "pconfig",        { Skip_MODRM }, 0 },
11007   },
11008   {
11009     /* RM_0F01_REG_1 */
11010     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11011     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11012     { "clac",           { Skip_MODRM }, 0 },
11013     { "stac",           { Skip_MODRM }, 0 },
11014     { Bad_Opcode },
11015     { Bad_Opcode },
11016     { Bad_Opcode },
11017     { "encls",          { Skip_MODRM }, 0 },
11018   },
11019   {
11020     /* RM_0F01_REG_2 */
11021     { "xgetbv",         { Skip_MODRM }, 0 },
11022     { "xsetbv",         { Skip_MODRM }, 0 },
11023     { Bad_Opcode },
11024     { Bad_Opcode },
11025     { "vmfunc",         { Skip_MODRM }, 0 },
11026     { "xend",           { Skip_MODRM }, 0 },
11027     { "xtest",          { Skip_MODRM }, 0 },
11028     { "enclu",          { Skip_MODRM }, 0 },
11029   },
11030   {
11031     /* RM_0F01_REG_3 */
11032     { "vmrun",          { Skip_MODRM }, 0 },
11033     { "vmmcall",        { Skip_MODRM }, 0 },
11034     { "vmload",         { Skip_MODRM }, 0 },
11035     { "vmsave",         { Skip_MODRM }, 0 },
11036     { "stgi",           { Skip_MODRM }, 0 },
11037     { "clgi",           { Skip_MODRM }, 0 },
11038     { "skinit",         { Skip_MODRM }, 0 },
11039     { "invlpga",        { Skip_MODRM }, 0 },
11040   },
11041   {
11042     /* RM_0F01_REG_5 */
11043     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11044     { Bad_Opcode },
11045     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11046     { Bad_Opcode },
11047     { Bad_Opcode },
11048     { Bad_Opcode },
11049     { "rdpkru",         { Skip_MODRM }, 0 },
11050     { "wrpkru",         { Skip_MODRM }, 0 },
11051   },
11052   {
11053     /* RM_0F01_REG_7 */
11054     { "swapgs",         { Skip_MODRM }, 0  },
11055     { "rdtscp",         { Skip_MODRM }, 0  },
11056     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11057     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11058     { "clzero",         { Skip_MODRM }, 0  },
11059   },
11060   {
11061     /* RM_0F1E_MOD_3_REG_7 */
11062     { "nopQ",           { Ev }, 0 },
11063     { "nopQ",           { Ev }, 0 },
11064     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11065     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11066     { "nopQ",           { Ev }, 0 },
11067     { "nopQ",           { Ev }, 0 },
11068     { "nopQ",           { Ev }, 0 },
11069     { "nopQ",           { Ev }, 0 },
11070   },
11071   {
11072     /* RM_0FAE_REG_6 */
11073     { "mfence",         { Skip_MODRM }, 0 },
11074   },
11075   {
11076     /* RM_0FAE_REG_7 */
11077     { "sfence",         { Skip_MODRM }, 0 },
11078
11079   },
11080 };
11081
11082 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11083
11084 /* We use the high bit to indicate different name for the same
11085    prefix.  */
11086 #define REP_PREFIX      (0xf3 | 0x100)
11087 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11088 #define XRELEASE_PREFIX (0xf3 | 0x400)
11089 #define BND_PREFIX      (0xf2 | 0x400)
11090 #define NOTRACK_PREFIX  (0x3e | 0x100)
11091
11092 static int
11093 ckprefix (void)
11094 {
11095   int newrex, i, length;
11096   rex = 0;
11097   rex_ignored = 0;
11098   prefixes = 0;
11099   used_prefixes = 0;
11100   rex_used = 0;
11101   last_lock_prefix = -1;
11102   last_repz_prefix = -1;
11103   last_repnz_prefix = -1;
11104   last_data_prefix = -1;
11105   last_addr_prefix = -1;
11106   last_rex_prefix = -1;
11107   last_seg_prefix = -1;
11108   fwait_prefix = -1;
11109   active_seg_prefix = 0;
11110   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11111     all_prefixes[i] = 0;
11112   i = 0;
11113   length = 0;
11114   /* The maximum instruction length is 15bytes.  */
11115   while (length < MAX_CODE_LENGTH - 1)
11116     {
11117       FETCH_DATA (the_info, codep + 1);
11118       newrex = 0;
11119       switch (*codep)
11120         {
11121         /* REX prefixes family.  */
11122         case 0x40:
11123         case 0x41:
11124         case 0x42:
11125         case 0x43:
11126         case 0x44:
11127         case 0x45:
11128         case 0x46:
11129         case 0x47:
11130         case 0x48:
11131         case 0x49:
11132         case 0x4a:
11133         case 0x4b:
11134         case 0x4c:
11135         case 0x4d:
11136         case 0x4e:
11137         case 0x4f:
11138           if (address_mode == mode_64bit)
11139             newrex = *codep;
11140           else
11141             return 1;
11142           last_rex_prefix = i;
11143           break;
11144         case 0xf3:
11145           prefixes |= PREFIX_REPZ;
11146           last_repz_prefix = i;
11147           break;
11148         case 0xf2:
11149           prefixes |= PREFIX_REPNZ;
11150           last_repnz_prefix = i;
11151           break;
11152         case 0xf0:
11153           prefixes |= PREFIX_LOCK;
11154           last_lock_prefix = i;
11155           break;
11156         case 0x2e:
11157           prefixes |= PREFIX_CS;
11158           last_seg_prefix = i;
11159           active_seg_prefix = PREFIX_CS;
11160           break;
11161         case 0x36:
11162           prefixes |= PREFIX_SS;
11163           last_seg_prefix = i;
11164           active_seg_prefix = PREFIX_SS;
11165           break;
11166         case 0x3e:
11167           prefixes |= PREFIX_DS;
11168           last_seg_prefix = i;
11169           active_seg_prefix = PREFIX_DS;
11170           break;
11171         case 0x26:
11172           prefixes |= PREFIX_ES;
11173           last_seg_prefix = i;
11174           active_seg_prefix = PREFIX_ES;
11175           break;
11176         case 0x64:
11177           prefixes |= PREFIX_FS;
11178           last_seg_prefix = i;
11179           active_seg_prefix = PREFIX_FS;
11180           break;
11181         case 0x65:
11182           prefixes |= PREFIX_GS;
11183           last_seg_prefix = i;
11184           active_seg_prefix = PREFIX_GS;
11185           break;
11186         case 0x66:
11187           prefixes |= PREFIX_DATA;
11188           last_data_prefix = i;
11189           break;
11190         case 0x67:
11191           prefixes |= PREFIX_ADDR;
11192           last_addr_prefix = i;
11193           break;
11194         case FWAIT_OPCODE:
11195           /* fwait is really an instruction.  If there are prefixes
11196              before the fwait, they belong to the fwait, *not* to the
11197              following instruction.  */
11198           fwait_prefix = i;
11199           if (prefixes || rex)
11200             {
11201               prefixes |= PREFIX_FWAIT;
11202               codep++;
11203               /* This ensures that the previous REX prefixes are noticed
11204                  as unused prefixes, as in the return case below.  */
11205               rex_used = rex;
11206               return 1;
11207             }
11208           prefixes = PREFIX_FWAIT;
11209           break;
11210         default:
11211           return 1;
11212         }
11213       /* Rex is ignored when followed by another prefix.  */
11214       if (rex)
11215         {
11216           rex_used = rex;
11217           return 1;
11218         }
11219       if (*codep != FWAIT_OPCODE)
11220         all_prefixes[i++] = *codep;
11221       rex = newrex;
11222       codep++;
11223       length++;
11224     }
11225   return 0;
11226 }
11227
11228 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11229    prefix byte.  */
11230
11231 static const char *
11232 prefix_name (int pref, int sizeflag)
11233 {
11234   static const char *rexes [16] =
11235     {
11236       "rex",            /* 0x40 */
11237       "rex.B",          /* 0x41 */
11238       "rex.X",          /* 0x42 */
11239       "rex.XB",         /* 0x43 */
11240       "rex.R",          /* 0x44 */
11241       "rex.RB",         /* 0x45 */
11242       "rex.RX",         /* 0x46 */
11243       "rex.RXB",        /* 0x47 */
11244       "rex.W",          /* 0x48 */
11245       "rex.WB",         /* 0x49 */
11246       "rex.WX",         /* 0x4a */
11247       "rex.WXB",        /* 0x4b */
11248       "rex.WR",         /* 0x4c */
11249       "rex.WRB",        /* 0x4d */
11250       "rex.WRX",        /* 0x4e */
11251       "rex.WRXB",       /* 0x4f */
11252     };
11253
11254   switch (pref)
11255     {
11256     /* REX prefixes family.  */
11257     case 0x40:
11258     case 0x41:
11259     case 0x42:
11260     case 0x43:
11261     case 0x44:
11262     case 0x45:
11263     case 0x46:
11264     case 0x47:
11265     case 0x48:
11266     case 0x49:
11267     case 0x4a:
11268     case 0x4b:
11269     case 0x4c:
11270     case 0x4d:
11271     case 0x4e:
11272     case 0x4f:
11273       return rexes [pref - 0x40];
11274     case 0xf3:
11275       return "repz";
11276     case 0xf2:
11277       return "repnz";
11278     case 0xf0:
11279       return "lock";
11280     case 0x2e:
11281       return "cs";
11282     case 0x36:
11283       return "ss";
11284     case 0x3e:
11285       return "ds";
11286     case 0x26:
11287       return "es";
11288     case 0x64:
11289       return "fs";
11290     case 0x65:
11291       return "gs";
11292     case 0x66:
11293       return (sizeflag & DFLAG) ? "data16" : "data32";
11294     case 0x67:
11295       if (address_mode == mode_64bit)
11296         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11297       else
11298         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11299     case FWAIT_OPCODE:
11300       return "fwait";
11301     case REP_PREFIX:
11302       return "rep";
11303     case XACQUIRE_PREFIX:
11304       return "xacquire";
11305     case XRELEASE_PREFIX:
11306       return "xrelease";
11307     case BND_PREFIX:
11308       return "bnd";
11309     case NOTRACK_PREFIX:
11310       return "notrack";
11311     default:
11312       return NULL;
11313     }
11314 }
11315
11316 static char op_out[MAX_OPERANDS][100];
11317 static int op_ad, op_index[MAX_OPERANDS];
11318 static int two_source_ops;
11319 static bfd_vma op_address[MAX_OPERANDS];
11320 static bfd_vma op_riprel[MAX_OPERANDS];
11321 static bfd_vma start_pc;
11322
11323 /*
11324  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11325  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11326  *   section of the "Virtual 8086 Mode" chapter.)
11327  * 'pc' should be the address of this instruction, it will
11328  *   be used to print the target address if this is a relative jump or call
11329  * The function returns the length of this instruction in bytes.
11330  */
11331
11332 static char intel_syntax;
11333 static char intel_mnemonic = !SYSV386_COMPAT;
11334 static char open_char;
11335 static char close_char;
11336 static char separator_char;
11337 static char scale_char;
11338
11339 enum x86_64_isa
11340 {
11341   amd64 = 0,
11342   intel64
11343 };
11344
11345 static enum x86_64_isa isa64;
11346
11347 /* Here for backwards compatibility.  When gdb stops using
11348    print_insn_i386_att and print_insn_i386_intel these functions can
11349    disappear, and print_insn_i386 be merged into print_insn.  */
11350 int
11351 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11352 {
11353   intel_syntax = 0;
11354
11355   return print_insn (pc, info);
11356 }
11357
11358 int
11359 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11360 {
11361   intel_syntax = 1;
11362
11363   return print_insn (pc, info);
11364 }
11365
11366 int
11367 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11368 {
11369   intel_syntax = -1;
11370
11371   return print_insn (pc, info);
11372 }
11373
11374 void
11375 print_i386_disassembler_options (FILE *stream)
11376 {
11377   fprintf (stream, _("\n\
11378 The following i386/x86-64 specific disassembler options are supported for use\n\
11379 with the -M switch (multiple options should be separated by commas):\n"));
11380
11381   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11382   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11383   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11384   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11385   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11386   fprintf (stream, _("  att-mnemonic\n"
11387                      "              Display instruction in AT&T mnemonic\n"));
11388   fprintf (stream, _("  intel-mnemonic\n"
11389                      "              Display instruction in Intel mnemonic\n"));
11390   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11391   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11392   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11393   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11394   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11395   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11396   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11397   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11398 }
11399
11400 /* Bad opcode.  */
11401 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11402
11403 /* Get a pointer to struct dis386 with a valid name.  */
11404
11405 static const struct dis386 *
11406 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11407 {
11408   int vindex, vex_table_index;
11409
11410   if (dp->name != NULL)
11411     return dp;
11412
11413   switch (dp->op[0].bytemode)
11414     {
11415     case USE_REG_TABLE:
11416       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11417       break;
11418
11419     case USE_MOD_TABLE:
11420       vindex = modrm.mod == 0x3 ? 1 : 0;
11421       dp = &mod_table[dp->op[1].bytemode][vindex];
11422       break;
11423
11424     case USE_RM_TABLE:
11425       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11426       break;
11427
11428     case USE_PREFIX_TABLE:
11429       if (need_vex)
11430         {
11431           /* The prefix in VEX is implicit.  */
11432           switch (vex.prefix)
11433             {
11434             case 0:
11435               vindex = 0;
11436               break;
11437             case REPE_PREFIX_OPCODE:
11438               vindex = 1;
11439               break;
11440             case DATA_PREFIX_OPCODE:
11441               vindex = 2;
11442               break;
11443             case REPNE_PREFIX_OPCODE:
11444               vindex = 3;
11445               break;
11446             default:
11447               abort ();
11448               break;
11449             }
11450         }
11451       else
11452         {
11453           int last_prefix = -1;
11454           int prefix = 0;
11455           vindex = 0;
11456           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11457              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11458              last one wins.  */
11459           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11460             {
11461               if (last_repz_prefix > last_repnz_prefix)
11462                 {
11463                   vindex = 1;
11464                   prefix = PREFIX_REPZ;
11465                   last_prefix = last_repz_prefix;
11466                 }
11467               else
11468                 {
11469                   vindex = 3;
11470                   prefix = PREFIX_REPNZ;
11471                   last_prefix = last_repnz_prefix;
11472                 }
11473
11474               /* Check if prefix should be ignored.  */
11475               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11476                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11477                    & prefix) != 0)
11478                 vindex = 0;
11479             }
11480
11481           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11482             {
11483               vindex = 2;
11484               prefix = PREFIX_DATA;
11485               last_prefix = last_data_prefix;
11486             }
11487
11488           if (vindex != 0)
11489             {
11490               used_prefixes |= prefix;
11491               all_prefixes[last_prefix] = 0;
11492             }
11493         }
11494       dp = &prefix_table[dp->op[1].bytemode][vindex];
11495       break;
11496
11497     case USE_X86_64_TABLE:
11498       vindex = address_mode == mode_64bit ? 1 : 0;
11499       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11500       break;
11501
11502     case USE_3BYTE_TABLE:
11503       FETCH_DATA (info, codep + 2);
11504       vindex = *codep++;
11505       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11506       end_codep = codep;
11507       modrm.mod = (*codep >> 6) & 3;
11508       modrm.reg = (*codep >> 3) & 7;
11509       modrm.rm = *codep & 7;
11510       break;
11511
11512     case USE_VEX_LEN_TABLE:
11513       if (!need_vex)
11514         abort ();
11515
11516       switch (vex.length)
11517         {
11518         case 128:
11519           vindex = 0;
11520           break;
11521         case 256:
11522           vindex = 1;
11523           break;
11524         default:
11525           abort ();
11526           break;
11527         }
11528
11529       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11530       break;
11531
11532     case USE_EVEX_LEN_TABLE:
11533       if (!vex.evex)
11534         abort ();
11535
11536       switch (vex.length)
11537         {
11538         case 128:
11539           vindex = 0;
11540           break;
11541         case 256:
11542           vindex = 1;
11543           break;
11544         case 512:
11545           vindex = 2;
11546           break;
11547         default:
11548           abort ();
11549           break;
11550         }
11551
11552       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11553       break;
11554
11555     case USE_XOP_8F_TABLE:
11556       FETCH_DATA (info, codep + 3);
11557       /* All bits in the REX prefix are ignored.  */
11558       rex_ignored = rex;
11559       rex = ~(*codep >> 5) & 0x7;
11560
11561       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11562       switch ((*codep & 0x1f))
11563         {
11564         default:
11565           dp = &bad_opcode;
11566           return dp;
11567         case 0x8:
11568           vex_table_index = XOP_08;
11569           break;
11570         case 0x9:
11571           vex_table_index = XOP_09;
11572           break;
11573         case 0xa:
11574           vex_table_index = XOP_0A;
11575           break;
11576         }
11577       codep++;
11578       vex.w = *codep & 0x80;
11579       if (vex.w && address_mode == mode_64bit)
11580         rex |= REX_W;
11581
11582       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11583       if (address_mode != mode_64bit)
11584         {
11585           /* In 16/32-bit mode REX_B is silently ignored.  */
11586           rex &= ~REX_B;
11587         }
11588
11589       vex.length = (*codep & 0x4) ? 256 : 128;
11590       switch ((*codep & 0x3))
11591         {
11592         case 0:
11593           break;
11594         case 1:
11595           vex.prefix = DATA_PREFIX_OPCODE;
11596           break;
11597         case 2:
11598           vex.prefix = REPE_PREFIX_OPCODE;
11599           break;
11600         case 3:
11601           vex.prefix = REPNE_PREFIX_OPCODE;
11602           break;
11603         }
11604       need_vex = 1;
11605       need_vex_reg = 1;
11606       codep++;
11607       vindex = *codep++;
11608       dp = &xop_table[vex_table_index][vindex];
11609
11610       end_codep = codep;
11611       FETCH_DATA (info, codep + 1);
11612       modrm.mod = (*codep >> 6) & 3;
11613       modrm.reg = (*codep >> 3) & 7;
11614       modrm.rm = *codep & 7;
11615       break;
11616
11617     case USE_VEX_C4_TABLE:
11618       /* VEX prefix.  */
11619       FETCH_DATA (info, codep + 3);
11620       /* All bits in the REX prefix are ignored.  */
11621       rex_ignored = rex;
11622       rex = ~(*codep >> 5) & 0x7;
11623       switch ((*codep & 0x1f))
11624         {
11625         default:
11626           dp = &bad_opcode;
11627           return dp;
11628         case 0x1:
11629           vex_table_index = VEX_0F;
11630           break;
11631         case 0x2:
11632           vex_table_index = VEX_0F38;
11633           break;
11634         case 0x3:
11635           vex_table_index = VEX_0F3A;
11636           break;
11637         }
11638       codep++;
11639       vex.w = *codep & 0x80;
11640       if (address_mode == mode_64bit)
11641         {
11642           if (vex.w)
11643             rex |= REX_W;
11644         }
11645       else
11646         {
11647           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11648              is ignored, other REX bits are 0 and the highest bit in
11649              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11650           rex = 0;
11651         }
11652       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11653       vex.length = (*codep & 0x4) ? 256 : 128;
11654       switch ((*codep & 0x3))
11655         {
11656         case 0:
11657           break;
11658         case 1:
11659           vex.prefix = DATA_PREFIX_OPCODE;
11660           break;
11661         case 2:
11662           vex.prefix = REPE_PREFIX_OPCODE;
11663           break;
11664         case 3:
11665           vex.prefix = REPNE_PREFIX_OPCODE;
11666           break;
11667         }
11668       need_vex = 1;
11669       need_vex_reg = 1;
11670       codep++;
11671       vindex = *codep++;
11672       dp = &vex_table[vex_table_index][vindex];
11673       end_codep = codep;
11674       /* There is no MODRM byte for VEX0F 77.  */
11675       if (vex_table_index != VEX_0F || vindex != 0x77)
11676         {
11677           FETCH_DATA (info, codep + 1);
11678           modrm.mod = (*codep >> 6) & 3;
11679           modrm.reg = (*codep >> 3) & 7;
11680           modrm.rm = *codep & 7;
11681         }
11682       break;
11683
11684     case USE_VEX_C5_TABLE:
11685       /* VEX prefix.  */
11686       FETCH_DATA (info, codep + 2);
11687       /* All bits in the REX prefix are ignored.  */
11688       rex_ignored = rex;
11689       rex = (*codep & 0x80) ? 0 : REX_R;
11690
11691       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11692          VEX.vvvv is 1.  */
11693       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11694       vex.length = (*codep & 0x4) ? 256 : 128;
11695       switch ((*codep & 0x3))
11696         {
11697         case 0:
11698           break;
11699         case 1:
11700           vex.prefix = DATA_PREFIX_OPCODE;
11701           break;
11702         case 2:
11703           vex.prefix = REPE_PREFIX_OPCODE;
11704           break;
11705         case 3:
11706           vex.prefix = REPNE_PREFIX_OPCODE;
11707           break;
11708         }
11709       need_vex = 1;
11710       need_vex_reg = 1;
11711       codep++;
11712       vindex = *codep++;
11713       dp = &vex_table[dp->op[1].bytemode][vindex];
11714       end_codep = codep;
11715       /* There is no MODRM byte for VEX 77.  */
11716       if (vindex != 0x77)
11717         {
11718           FETCH_DATA (info, codep + 1);
11719           modrm.mod = (*codep >> 6) & 3;
11720           modrm.reg = (*codep >> 3) & 7;
11721           modrm.rm = *codep & 7;
11722         }
11723       break;
11724
11725     case USE_VEX_W_TABLE:
11726       if (!need_vex)
11727         abort ();
11728
11729       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11730       break;
11731
11732     case USE_EVEX_TABLE:
11733       two_source_ops = 0;
11734       /* EVEX prefix.  */
11735       vex.evex = 1;
11736       FETCH_DATA (info, codep + 4);
11737       /* All bits in the REX prefix are ignored.  */
11738       rex_ignored = rex;
11739       /* The first byte after 0x62.  */
11740       rex = ~(*codep >> 5) & 0x7;
11741       vex.r = *codep & 0x10;
11742       switch ((*codep & 0xf))
11743         {
11744         default:
11745           return &bad_opcode;
11746         case 0x1:
11747           vex_table_index = EVEX_0F;
11748           break;
11749         case 0x2:
11750           vex_table_index = EVEX_0F38;
11751           break;
11752         case 0x3:
11753           vex_table_index = EVEX_0F3A;
11754           break;
11755         }
11756
11757       /* The second byte after 0x62.  */
11758       codep++;
11759       vex.w = *codep & 0x80;
11760       if (vex.w && address_mode == mode_64bit)
11761         rex |= REX_W;
11762
11763       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11764
11765       /* The U bit.  */
11766       if (!(*codep & 0x4))
11767         return &bad_opcode;
11768
11769       switch ((*codep & 0x3))
11770         {
11771         case 0:
11772           break;
11773         case 1:
11774           vex.prefix = DATA_PREFIX_OPCODE;
11775           break;
11776         case 2:
11777           vex.prefix = REPE_PREFIX_OPCODE;
11778           break;
11779         case 3:
11780           vex.prefix = REPNE_PREFIX_OPCODE;
11781           break;
11782         }
11783
11784       /* The third byte after 0x62.  */
11785       codep++;
11786
11787       /* Remember the static rounding bits.  */
11788       vex.ll = (*codep >> 5) & 3;
11789       vex.b = (*codep & 0x10) != 0;
11790
11791       vex.v = *codep & 0x8;
11792       vex.mask_register_specifier = *codep & 0x7;
11793       vex.zeroing = *codep & 0x80;
11794
11795       if (address_mode != mode_64bit)
11796         {
11797           /* In 16/32-bit mode silently ignore following bits.  */
11798           rex &= ~REX_B;
11799           vex.r = 1;
11800           vex.v = 1;
11801         }
11802
11803       need_vex = 1;
11804       need_vex_reg = 1;
11805       codep++;
11806       vindex = *codep++;
11807       dp = &evex_table[vex_table_index][vindex];
11808       end_codep = codep;
11809       FETCH_DATA (info, codep + 1);
11810       modrm.mod = (*codep >> 6) & 3;
11811       modrm.reg = (*codep >> 3) & 7;
11812       modrm.rm = *codep & 7;
11813
11814       /* Set vector length.  */
11815       if (modrm.mod == 3 && vex.b)
11816         vex.length = 512;
11817       else
11818         {
11819           switch (vex.ll)
11820             {
11821             case 0x0:
11822               vex.length = 128;
11823               break;
11824             case 0x1:
11825               vex.length = 256;
11826               break;
11827             case 0x2:
11828               vex.length = 512;
11829               break;
11830             default:
11831               return &bad_opcode;
11832             }
11833         }
11834       break;
11835
11836     case 0:
11837       dp = &bad_opcode;
11838       break;
11839
11840     default:
11841       abort ();
11842     }
11843
11844   if (dp->name != NULL)
11845     return dp;
11846   else
11847     return get_valid_dis386 (dp, info);
11848 }
11849
11850 static void
11851 get_sib (disassemble_info *info, int sizeflag)
11852 {
11853   /* If modrm.mod == 3, operand must be register.  */
11854   if (need_modrm
11855       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11856       && modrm.mod != 3
11857       && modrm.rm == 4)
11858     {
11859       FETCH_DATA (info, codep + 2);
11860       sib.index = (codep [1] >> 3) & 7;
11861       sib.scale = (codep [1] >> 6) & 3;
11862       sib.base = codep [1] & 7;
11863     }
11864 }
11865
11866 static int
11867 print_insn (bfd_vma pc, disassemble_info *info)
11868 {
11869   const struct dis386 *dp;
11870   int i;
11871   char *op_txt[MAX_OPERANDS];
11872   int needcomma;
11873   int sizeflag, orig_sizeflag;
11874   const char *p;
11875   struct dis_private priv;
11876   int prefix_length;
11877
11878   priv.orig_sizeflag = AFLAG | DFLAG;
11879   if ((info->mach & bfd_mach_i386_i386) != 0)
11880     address_mode = mode_32bit;
11881   else if (info->mach == bfd_mach_i386_i8086)
11882     {
11883       address_mode = mode_16bit;
11884       priv.orig_sizeflag = 0;
11885     }
11886   else
11887     address_mode = mode_64bit;
11888
11889   if (intel_syntax == (char) -1)
11890     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11891
11892   for (p = info->disassembler_options; p != NULL; )
11893     {
11894       if (CONST_STRNEQ (p, "amd64"))
11895         isa64 = amd64;
11896       else if (CONST_STRNEQ (p, "intel64"))
11897         isa64 = intel64;
11898       else if (CONST_STRNEQ (p, "x86-64"))
11899         {
11900           address_mode = mode_64bit;
11901           priv.orig_sizeflag = AFLAG | DFLAG;
11902         }
11903       else if (CONST_STRNEQ (p, "i386"))
11904         {
11905           address_mode = mode_32bit;
11906           priv.orig_sizeflag = AFLAG | DFLAG;
11907         }
11908       else if (CONST_STRNEQ (p, "i8086"))
11909         {
11910           address_mode = mode_16bit;
11911           priv.orig_sizeflag = 0;
11912         }
11913       else if (CONST_STRNEQ (p, "intel"))
11914         {
11915           intel_syntax = 1;
11916           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11917             intel_mnemonic = 1;
11918         }
11919       else if (CONST_STRNEQ (p, "att"))
11920         {
11921           intel_syntax = 0;
11922           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11923             intel_mnemonic = 0;
11924         }
11925       else if (CONST_STRNEQ (p, "addr"))
11926         {
11927           if (address_mode == mode_64bit)
11928             {
11929               if (p[4] == '3' && p[5] == '2')
11930                 priv.orig_sizeflag &= ~AFLAG;
11931               else if (p[4] == '6' && p[5] == '4')
11932                 priv.orig_sizeflag |= AFLAG;
11933             }
11934           else
11935             {
11936               if (p[4] == '1' && p[5] == '6')
11937                 priv.orig_sizeflag &= ~AFLAG;
11938               else if (p[4] == '3' && p[5] == '2')
11939                 priv.orig_sizeflag |= AFLAG;
11940             }
11941         }
11942       else if (CONST_STRNEQ (p, "data"))
11943         {
11944           if (p[4] == '1' && p[5] == '6')
11945             priv.orig_sizeflag &= ~DFLAG;
11946           else if (p[4] == '3' && p[5] == '2')
11947             priv.orig_sizeflag |= DFLAG;
11948         }
11949       else if (CONST_STRNEQ (p, "suffix"))
11950         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11951
11952       p = strchr (p, ',');
11953       if (p != NULL)
11954         p++;
11955     }
11956
11957   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11958     {
11959       (*info->fprintf_func) (info->stream,
11960                              _("64-bit address is disabled"));
11961       return -1;
11962     }
11963
11964   if (intel_syntax)
11965     {
11966       names64 = intel_names64;
11967       names32 = intel_names32;
11968       names16 = intel_names16;
11969       names8 = intel_names8;
11970       names8rex = intel_names8rex;
11971       names_seg = intel_names_seg;
11972       names_mm = intel_names_mm;
11973       names_bnd = intel_names_bnd;
11974       names_xmm = intel_names_xmm;
11975       names_ymm = intel_names_ymm;
11976       names_zmm = intel_names_zmm;
11977       index64 = intel_index64;
11978       index32 = intel_index32;
11979       names_mask = intel_names_mask;
11980       index16 = intel_index16;
11981       open_char = '[';
11982       close_char = ']';
11983       separator_char = '+';
11984       scale_char = '*';
11985     }
11986   else
11987     {
11988       names64 = att_names64;
11989       names32 = att_names32;
11990       names16 = att_names16;
11991       names8 = att_names8;
11992       names8rex = att_names8rex;
11993       names_seg = att_names_seg;
11994       names_mm = att_names_mm;
11995       names_bnd = att_names_bnd;
11996       names_xmm = att_names_xmm;
11997       names_ymm = att_names_ymm;
11998       names_zmm = att_names_zmm;
11999       index64 = att_index64;
12000       index32 = att_index32;
12001       names_mask = att_names_mask;
12002       index16 = att_index16;
12003       open_char = '(';
12004       close_char =  ')';
12005       separator_char = ',';
12006       scale_char = ',';
12007     }
12008
12009   /* The output looks better if we put 7 bytes on a line, since that
12010      puts most long word instructions on a single line.  Use 8 bytes
12011      for Intel L1OM.  */
12012   if ((info->mach & bfd_mach_l1om) != 0)
12013     info->bytes_per_line = 8;
12014   else
12015     info->bytes_per_line = 7;
12016
12017   info->private_data = &priv;
12018   priv.max_fetched = priv.the_buffer;
12019   priv.insn_start = pc;
12020
12021   obuf[0] = 0;
12022   for (i = 0; i < MAX_OPERANDS; ++i)
12023     {
12024       op_out[i][0] = 0;
12025       op_index[i] = -1;
12026     }
12027
12028   the_info = info;
12029   start_pc = pc;
12030   start_codep = priv.the_buffer;
12031   codep = priv.the_buffer;
12032
12033   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12034     {
12035       const char *name;
12036
12037       /* Getting here means we tried for data but didn't get it.  That
12038          means we have an incomplete instruction of some sort.  Just
12039          print the first byte as a prefix or a .byte pseudo-op.  */
12040       if (codep > priv.the_buffer)
12041         {
12042           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12043           if (name != NULL)
12044             (*info->fprintf_func) (info->stream, "%s", name);
12045           else
12046             {
12047               /* Just print the first byte as a .byte instruction.  */
12048               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12049                                      (unsigned int) priv.the_buffer[0]);
12050             }
12051
12052           return 1;
12053         }
12054
12055       return -1;
12056     }
12057
12058   obufp = obuf;
12059   sizeflag = priv.orig_sizeflag;
12060
12061   if (!ckprefix () || rex_used)
12062     {
12063       /* Too many prefixes or unused REX prefixes.  */
12064       for (i = 0;
12065            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12066            i++)
12067         (*info->fprintf_func) (info->stream, "%s%s",
12068                                i == 0 ? "" : " ",
12069                                prefix_name (all_prefixes[i], sizeflag));
12070       return i;
12071     }
12072
12073   insn_codep = codep;
12074
12075   FETCH_DATA (info, codep + 1);
12076   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12077
12078   if (((prefixes & PREFIX_FWAIT)
12079        && ((*codep < 0xd8) || (*codep > 0xdf))))
12080     {
12081       /* Handle prefixes before fwait.  */
12082       for (i = 0; i < fwait_prefix && all_prefixes[i];
12083            i++)
12084         (*info->fprintf_func) (info->stream, "%s ",
12085                                prefix_name (all_prefixes[i], sizeflag));
12086       (*info->fprintf_func) (info->stream, "fwait");
12087       return i + 1;
12088     }
12089
12090   if (*codep == 0x0f)
12091     {
12092       unsigned char threebyte;
12093
12094       codep++;
12095       FETCH_DATA (info, codep + 1);
12096       threebyte = *codep;
12097       dp = &dis386_twobyte[threebyte];
12098       need_modrm = twobyte_has_modrm[*codep];
12099       codep++;
12100     }
12101   else
12102     {
12103       dp = &dis386[*codep];
12104       need_modrm = onebyte_has_modrm[*codep];
12105       codep++;
12106     }
12107
12108   /* Save sizeflag for printing the extra prefixes later before updating
12109      it for mnemonic and operand processing.  The prefix names depend
12110      only on the address mode.  */
12111   orig_sizeflag = sizeflag;
12112   if (prefixes & PREFIX_ADDR)
12113     sizeflag ^= AFLAG;
12114   if ((prefixes & PREFIX_DATA))
12115     sizeflag ^= DFLAG;
12116
12117   end_codep = codep;
12118   if (need_modrm)
12119     {
12120       FETCH_DATA (info, codep + 1);
12121       modrm.mod = (*codep >> 6) & 3;
12122       modrm.reg = (*codep >> 3) & 7;
12123       modrm.rm = *codep & 7;
12124     }
12125
12126   need_vex = 0;
12127   need_vex_reg = 0;
12128   vex_w_done = 0;
12129   memset (&vex, 0, sizeof (vex));
12130
12131   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12132     {
12133       get_sib (info, sizeflag);
12134       dofloat (sizeflag);
12135     }
12136   else
12137     {
12138       dp = get_valid_dis386 (dp, info);
12139       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12140         {
12141           get_sib (info, sizeflag);
12142           for (i = 0; i < MAX_OPERANDS; ++i)
12143             {
12144               obufp = op_out[i];
12145               op_ad = MAX_OPERANDS - 1 - i;
12146               if (dp->op[i].rtn)
12147                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12148               /* For EVEX instruction after the last operand masking
12149                  should be printed.  */
12150               if (i == 0 && vex.evex)
12151                 {
12152                   /* Don't print {%k0}.  */
12153                   if (vex.mask_register_specifier)
12154                     {
12155                       oappend ("{");
12156                       oappend (names_mask[vex.mask_register_specifier]);
12157                       oappend ("}");
12158                     }
12159                   if (vex.zeroing)
12160                     oappend ("{z}");
12161                 }
12162             }
12163         }
12164     }
12165
12166   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12167      are all 0s in inverted form.  */
12168   if (need_vex && vex.register_specifier != 0)
12169     {
12170       (*info->fprintf_func) (info->stream, "(bad)");
12171       return end_codep - priv.the_buffer;
12172     }
12173
12174   /* Check if the REX prefix is used.  */
12175   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12176     all_prefixes[last_rex_prefix] = 0;
12177
12178   /* Check if the SEG prefix is used.  */
12179   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12180                    | PREFIX_FS | PREFIX_GS)) != 0
12181       && (used_prefixes & active_seg_prefix) != 0)
12182     all_prefixes[last_seg_prefix] = 0;
12183
12184   /* Check if the ADDR prefix is used.  */
12185   if ((prefixes & PREFIX_ADDR) != 0
12186       && (used_prefixes & PREFIX_ADDR) != 0)
12187     all_prefixes[last_addr_prefix] = 0;
12188
12189   /* Check if the DATA prefix is used.  */
12190   if ((prefixes & PREFIX_DATA) != 0
12191       && (used_prefixes & PREFIX_DATA) != 0)
12192     all_prefixes[last_data_prefix] = 0;
12193
12194   /* Print the extra prefixes.  */
12195   prefix_length = 0;
12196   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12197     if (all_prefixes[i])
12198       {
12199         const char *name;
12200         name = prefix_name (all_prefixes[i], orig_sizeflag);
12201         if (name == NULL)
12202           abort ();
12203         prefix_length += strlen (name) + 1;
12204         (*info->fprintf_func) (info->stream, "%s ", name);
12205       }
12206
12207   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12208      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12209      used by putop and MMX/SSE operand and may be overriden by the
12210      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12211      separately.  */
12212   if (dp->prefix_requirement == PREFIX_OPCODE
12213       && dp != &bad_opcode
12214       && (((prefixes
12215             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12216            && (used_prefixes
12217                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12218           || ((((prefixes
12219                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12220                 == PREFIX_DATA)
12221                && (used_prefixes & PREFIX_DATA) == 0))))
12222     {
12223       (*info->fprintf_func) (info->stream, "(bad)");
12224       return end_codep - priv.the_buffer;
12225     }
12226
12227   /* Check maximum code length.  */
12228   if ((codep - start_codep) > MAX_CODE_LENGTH)
12229     {
12230       (*info->fprintf_func) (info->stream, "(bad)");
12231       return MAX_CODE_LENGTH;
12232     }
12233
12234   obufp = mnemonicendp;
12235   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12236     oappend (" ");
12237   oappend (" ");
12238   (*info->fprintf_func) (info->stream, "%s", obuf);
12239
12240   /* The enter and bound instructions are printed with operands in the same
12241      order as the intel book; everything else is printed in reverse order.  */
12242   if (intel_syntax || two_source_ops)
12243     {
12244       bfd_vma riprel;
12245
12246       for (i = 0; i < MAX_OPERANDS; ++i)
12247         op_txt[i] = op_out[i];
12248
12249       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12250           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12251         {
12252           op_txt[2] = op_out[3];
12253           op_txt[3] = op_out[2];
12254         }
12255
12256       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12257         {
12258           op_ad = op_index[i];
12259           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12260           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12261           riprel = op_riprel[i];
12262           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12263           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12264         }
12265     }
12266   else
12267     {
12268       for (i = 0; i < MAX_OPERANDS; ++i)
12269         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12270     }
12271
12272   needcomma = 0;
12273   for (i = 0; i < MAX_OPERANDS; ++i)
12274     if (*op_txt[i])
12275       {
12276         if (needcomma)
12277           (*info->fprintf_func) (info->stream, ",");
12278         if (op_index[i] != -1 && !op_riprel[i])
12279           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12280         else
12281           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12282         needcomma = 1;
12283       }
12284
12285   for (i = 0; i < MAX_OPERANDS; i++)
12286     if (op_index[i] != -1 && op_riprel[i])
12287       {
12288         (*info->fprintf_func) (info->stream, "        # ");
12289         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12290                                                 + op_address[op_index[i]]), info);
12291         break;
12292       }
12293   return codep - priv.the_buffer;
12294 }
12295
12296 static const char *float_mem[] = {
12297   /* d8 */
12298   "fadd{s|}",
12299   "fmul{s|}",
12300   "fcom{s|}",
12301   "fcomp{s|}",
12302   "fsub{s|}",
12303   "fsubr{s|}",
12304   "fdiv{s|}",
12305   "fdivr{s|}",
12306   /* d9 */
12307   "fld{s|}",
12308   "(bad)",
12309   "fst{s|}",
12310   "fstp{s|}",
12311   "fldenvIC",
12312   "fldcw",
12313   "fNstenvIC",
12314   "fNstcw",
12315   /* da */
12316   "fiadd{l|}",
12317   "fimul{l|}",
12318   "ficom{l|}",
12319   "ficomp{l|}",
12320   "fisub{l|}",
12321   "fisubr{l|}",
12322   "fidiv{l|}",
12323   "fidivr{l|}",
12324   /* db */
12325   "fild{l|}",
12326   "fisttp{l|}",
12327   "fist{l|}",
12328   "fistp{l|}",
12329   "(bad)",
12330   "fld{t||t|}",
12331   "(bad)",
12332   "fstp{t||t|}",
12333   /* dc */
12334   "fadd{l|}",
12335   "fmul{l|}",
12336   "fcom{l|}",
12337   "fcomp{l|}",
12338   "fsub{l|}",
12339   "fsubr{l|}",
12340   "fdiv{l|}",
12341   "fdivr{l|}",
12342   /* dd */
12343   "fld{l|}",
12344   "fisttp{ll|}",
12345   "fst{l||}",
12346   "fstp{l|}",
12347   "frstorIC",
12348   "(bad)",
12349   "fNsaveIC",
12350   "fNstsw",
12351   /* de */
12352   "fiadd{s|}",
12353   "fimul{s|}",
12354   "ficom{s|}",
12355   "ficomp{s|}",
12356   "fisub{s|}",
12357   "fisubr{s|}",
12358   "fidiv{s|}",
12359   "fidivr{s|}",
12360   /* df */
12361   "fild{s|}",
12362   "fisttp{s|}",
12363   "fist{s|}",
12364   "fistp{s|}",
12365   "fbld",
12366   "fild{ll|}",
12367   "fbstp",
12368   "fistp{ll|}",
12369 };
12370
12371 static const unsigned char float_mem_mode[] = {
12372   /* d8 */
12373   d_mode,
12374   d_mode,
12375   d_mode,
12376   d_mode,
12377   d_mode,
12378   d_mode,
12379   d_mode,
12380   d_mode,
12381   /* d9 */
12382   d_mode,
12383   0,
12384   d_mode,
12385   d_mode,
12386   0,
12387   w_mode,
12388   0,
12389   w_mode,
12390   /* da */
12391   d_mode,
12392   d_mode,
12393   d_mode,
12394   d_mode,
12395   d_mode,
12396   d_mode,
12397   d_mode,
12398   d_mode,
12399   /* db */
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   d_mode,
12404   0,
12405   t_mode,
12406   0,
12407   t_mode,
12408   /* dc */
12409   q_mode,
12410   q_mode,
12411   q_mode,
12412   q_mode,
12413   q_mode,
12414   q_mode,
12415   q_mode,
12416   q_mode,
12417   /* dd */
12418   q_mode,
12419   q_mode,
12420   q_mode,
12421   q_mode,
12422   0,
12423   0,
12424   0,
12425   w_mode,
12426   /* de */
12427   w_mode,
12428   w_mode,
12429   w_mode,
12430   w_mode,
12431   w_mode,
12432   w_mode,
12433   w_mode,
12434   w_mode,
12435   /* df */
12436   w_mode,
12437   w_mode,
12438   w_mode,
12439   w_mode,
12440   t_mode,
12441   q_mode,
12442   t_mode,
12443   q_mode
12444 };
12445
12446 #define ST { OP_ST, 0 }
12447 #define STi { OP_STi, 0 }
12448
12449 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12450 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12451 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12452 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12453 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12454 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12455 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12456 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12457 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12458
12459 static const struct dis386 float_reg[][8] = {
12460   /* d8 */
12461   {
12462     { "fadd",   { ST, STi }, 0 },
12463     { "fmul",   { ST, STi }, 0 },
12464     { "fcom",   { STi }, 0 },
12465     { "fcomp",  { STi }, 0 },
12466     { "fsub",   { ST, STi }, 0 },
12467     { "fsubr",  { ST, STi }, 0 },
12468     { "fdiv",   { ST, STi }, 0 },
12469     { "fdivr",  { ST, STi }, 0 },
12470   },
12471   /* d9 */
12472   {
12473     { "fld",    { STi }, 0 },
12474     { "fxch",   { STi }, 0 },
12475     { FGRPd9_2 },
12476     { Bad_Opcode },
12477     { FGRPd9_4 },
12478     { FGRPd9_5 },
12479     { FGRPd9_6 },
12480     { FGRPd9_7 },
12481   },
12482   /* da */
12483   {
12484     { "fcmovb", { ST, STi }, 0 },
12485     { "fcmove", { ST, STi }, 0 },
12486     { "fcmovbe",{ ST, STi }, 0 },
12487     { "fcmovu", { ST, STi }, 0 },
12488     { Bad_Opcode },
12489     { FGRPda_5 },
12490     { Bad_Opcode },
12491     { Bad_Opcode },
12492   },
12493   /* db */
12494   {
12495     { "fcmovnb",{ ST, STi }, 0 },
12496     { "fcmovne",{ ST, STi }, 0 },
12497     { "fcmovnbe",{ ST, STi }, 0 },
12498     { "fcmovnu",{ ST, STi }, 0 },
12499     { FGRPdb_4 },
12500     { "fucomi", { ST, STi }, 0 },
12501     { "fcomi",  { ST, STi }, 0 },
12502     { Bad_Opcode },
12503   },
12504   /* dc */
12505   {
12506     { "fadd",   { STi, ST }, 0 },
12507     { "fmul",   { STi, ST }, 0 },
12508     { Bad_Opcode },
12509     { Bad_Opcode },
12510     { "fsub{!M|r}",     { STi, ST }, 0 },
12511     { "fsub{M|}",       { STi, ST }, 0 },
12512     { "fdiv{!M|r}",     { STi, ST }, 0 },
12513     { "fdiv{M|}",       { STi, ST }, 0 },
12514   },
12515   /* dd */
12516   {
12517     { "ffree",  { STi }, 0 },
12518     { Bad_Opcode },
12519     { "fst",    { STi }, 0 },
12520     { "fstp",   { STi }, 0 },
12521     { "fucom",  { STi }, 0 },
12522     { "fucomp", { STi }, 0 },
12523     { Bad_Opcode },
12524     { Bad_Opcode },
12525   },
12526   /* de */
12527   {
12528     { "faddp",  { STi, ST }, 0 },
12529     { "fmulp",  { STi, ST }, 0 },
12530     { Bad_Opcode },
12531     { FGRPde_3 },
12532     { "fsub{!M|r}p",    { STi, ST }, 0 },
12533     { "fsub{M|}p",      { STi, ST }, 0 },
12534     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12535     { "fdiv{M|}p",      { STi, ST }, 0 },
12536   },
12537   /* df */
12538   {
12539     { "ffreep", { STi }, 0 },
12540     { Bad_Opcode },
12541     { Bad_Opcode },
12542     { Bad_Opcode },
12543     { FGRPdf_4 },
12544     { "fucomip", { ST, STi }, 0 },
12545     { "fcomip", { ST, STi }, 0 },
12546     { Bad_Opcode },
12547   },
12548 };
12549
12550 static char *fgrps[][8] = {
12551   /* Bad opcode 0 */
12552   {
12553     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12554   },
12555
12556   /* d9_2  1 */
12557   {
12558     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12559   },
12560
12561   /* d9_4  2 */
12562   {
12563     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12564   },
12565
12566   /* d9_5  3 */
12567   {
12568     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12569   },
12570
12571   /* d9_6  4 */
12572   {
12573     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12574   },
12575
12576   /* d9_7  5 */
12577   {
12578     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12579   },
12580
12581   /* da_5  6 */
12582   {
12583     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12584   },
12585
12586   /* db_4  7 */
12587   {
12588     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12589     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12590   },
12591
12592   /* de_3  8 */
12593   {
12594     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12595   },
12596
12597   /* df_4  9 */
12598   {
12599     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12600   },
12601 };
12602
12603 static void
12604 swap_operand (void)
12605 {
12606   mnemonicendp[0] = '.';
12607   mnemonicendp[1] = 's';
12608   mnemonicendp += 2;
12609 }
12610
12611 static void
12612 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12613                int sizeflag ATTRIBUTE_UNUSED)
12614 {
12615   /* Skip mod/rm byte.  */
12616   MODRM_CHECK;
12617   codep++;
12618 }
12619
12620 static void
12621 dofloat (int sizeflag)
12622 {
12623   const struct dis386 *dp;
12624   unsigned char floatop;
12625
12626   floatop = codep[-1];
12627
12628   if (modrm.mod != 3)
12629     {
12630       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12631
12632       putop (float_mem[fp_indx], sizeflag);
12633       obufp = op_out[0];
12634       op_ad = 2;
12635       OP_E (float_mem_mode[fp_indx], sizeflag);
12636       return;
12637     }
12638   /* Skip mod/rm byte.  */
12639   MODRM_CHECK;
12640   codep++;
12641
12642   dp = &float_reg[floatop - 0xd8][modrm.reg];
12643   if (dp->name == NULL)
12644     {
12645       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12646
12647       /* Instruction fnstsw is only one with strange arg.  */
12648       if (floatop == 0xdf && codep[-1] == 0xe0)
12649         strcpy (op_out[0], names16[0]);
12650     }
12651   else
12652     {
12653       putop (dp->name, sizeflag);
12654
12655       obufp = op_out[0];
12656       op_ad = 2;
12657       if (dp->op[0].rtn)
12658         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12659
12660       obufp = op_out[1];
12661       op_ad = 1;
12662       if (dp->op[1].rtn)
12663         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12664     }
12665 }
12666
12667 /* Like oappend (below), but S is a string starting with '%'.
12668    In Intel syntax, the '%' is elided.  */
12669 static void
12670 oappend_maybe_intel (const char *s)
12671 {
12672   oappend (s + intel_syntax);
12673 }
12674
12675 static void
12676 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12677 {
12678   oappend_maybe_intel ("%st");
12679 }
12680
12681 static void
12682 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12683 {
12684   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12685   oappend_maybe_intel (scratchbuf);
12686 }
12687
12688 /* Capital letters in template are macros.  */
12689 static int
12690 putop (const char *in_template, int sizeflag)
12691 {
12692   const char *p;
12693   int alt = 0;
12694   int cond = 1;
12695   unsigned int l = 0, len = 1;
12696   char last[4];
12697
12698 #define SAVE_LAST(c)                    \
12699   if (l < len && l < sizeof (last))     \
12700     last[l++] = c;                      \
12701   else                                  \
12702     abort ();
12703
12704   for (p = in_template; *p; p++)
12705     {
12706       switch (*p)
12707         {
12708         default:
12709           *obufp++ = *p;
12710           break;
12711         case '%':
12712           len++;
12713           break;
12714         case '!':
12715           cond = 0;
12716           break;
12717         case '{':
12718           if (intel_syntax)
12719             {
12720               while (*++p != '|')
12721                 if (*p == '}' || *p == '\0')
12722                   abort ();
12723             }
12724           /* Fall through.  */
12725         case 'I':
12726           alt = 1;
12727           continue;
12728         case '|':
12729           while (*++p != '}')
12730             {
12731               if (*p == '\0')
12732                 abort ();
12733             }
12734           break;
12735         case '}':
12736           break;
12737         case 'A':
12738           if (intel_syntax)
12739             break;
12740           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12741             *obufp++ = 'b';
12742           break;
12743         case 'B':
12744           if (l == 0 && len == 1)
12745             {
12746 case_B:
12747               if (intel_syntax)
12748                 break;
12749               if (sizeflag & SUFFIX_ALWAYS)
12750                 *obufp++ = 'b';
12751             }
12752           else
12753             {
12754               if (l != 1
12755                   || len != 2
12756                   || last[0] != 'L')
12757                 {
12758                   SAVE_LAST (*p);
12759                   break;
12760                 }
12761
12762               if (address_mode == mode_64bit
12763                   && !(prefixes & PREFIX_ADDR))
12764                 {
12765                   *obufp++ = 'a';
12766                   *obufp++ = 'b';
12767                   *obufp++ = 's';
12768                 }
12769
12770               goto case_B;
12771             }
12772           break;
12773         case 'C':
12774           if (intel_syntax && !alt)
12775             break;
12776           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12777             {
12778               if (sizeflag & DFLAG)
12779                 *obufp++ = intel_syntax ? 'd' : 'l';
12780               else
12781                 *obufp++ = intel_syntax ? 'w' : 's';
12782               used_prefixes |= (prefixes & PREFIX_DATA);
12783             }
12784           break;
12785         case 'D':
12786           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12787             break;
12788           USED_REX (REX_W);
12789           if (modrm.mod == 3)
12790             {
12791               if (rex & REX_W)
12792                 *obufp++ = 'q';
12793               else
12794                 {
12795                   if (sizeflag & DFLAG)
12796                     *obufp++ = intel_syntax ? 'd' : 'l';
12797                   else
12798                     *obufp++ = 'w';
12799                   used_prefixes |= (prefixes & PREFIX_DATA);
12800                 }
12801             }
12802           else
12803             *obufp++ = 'w';
12804           break;
12805         case 'E':               /* For jcxz/jecxz */
12806           if (address_mode == mode_64bit)
12807             {
12808               if (sizeflag & AFLAG)
12809                 *obufp++ = 'r';
12810               else
12811                 *obufp++ = 'e';
12812             }
12813           else
12814             if (sizeflag & AFLAG)
12815               *obufp++ = 'e';
12816           used_prefixes |= (prefixes & PREFIX_ADDR);
12817           break;
12818         case 'F':
12819           if (intel_syntax)
12820             break;
12821           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12822             {
12823               if (sizeflag & AFLAG)
12824                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12825               else
12826                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12827               used_prefixes |= (prefixes & PREFIX_ADDR);
12828             }
12829           break;
12830         case 'G':
12831           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12832             break;
12833           if ((rex & REX_W) || (sizeflag & DFLAG))
12834             *obufp++ = 'l';
12835           else
12836             *obufp++ = 'w';
12837           if (!(rex & REX_W))
12838             used_prefixes |= (prefixes & PREFIX_DATA);
12839           break;
12840         case 'H':
12841           if (intel_syntax)
12842             break;
12843           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12844               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12845             {
12846               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12847               *obufp++ = ',';
12848               *obufp++ = 'p';
12849               if (prefixes & PREFIX_DS)
12850                 *obufp++ = 't';
12851               else
12852                 *obufp++ = 'n';
12853             }
12854           break;
12855         case 'J':
12856           if (intel_syntax)
12857             break;
12858           *obufp++ = 'l';
12859           break;
12860         case 'K':
12861           USED_REX (REX_W);
12862           if (rex & REX_W)
12863             *obufp++ = 'q';
12864           else
12865             *obufp++ = 'd';
12866           break;
12867         case 'Z':
12868           if (l != 0 || len != 1)
12869             {
12870               if (l != 1 || len != 2 || last[0] != 'X')
12871                 {
12872                   SAVE_LAST (*p);
12873                   break;
12874                 }
12875               if (!need_vex || !vex.evex)
12876                 abort ();
12877               if (intel_syntax
12878                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12879                 break;
12880               switch (vex.length)
12881                 {
12882                 case 128:
12883                   *obufp++ = 'x';
12884                   break;
12885                 case 256:
12886                   *obufp++ = 'y';
12887                   break;
12888                 case 512:
12889                   *obufp++ = 'z';
12890                   break;
12891                 default:
12892                   abort ();
12893                 }
12894               break;
12895             }
12896           if (intel_syntax)
12897             break;
12898           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12899             {
12900               *obufp++ = 'q';
12901               break;
12902             }
12903           /* Fall through.  */
12904           goto case_L;
12905         case 'L':
12906           if (l != 0 || len != 1)
12907             {
12908               SAVE_LAST (*p);
12909               break;
12910             }
12911 case_L:
12912           if (intel_syntax)
12913             break;
12914           if (sizeflag & SUFFIX_ALWAYS)
12915             *obufp++ = 'l';
12916           break;
12917         case 'M':
12918           if (intel_mnemonic != cond)
12919             *obufp++ = 'r';
12920           break;
12921         case 'N':
12922           if ((prefixes & PREFIX_FWAIT) == 0)
12923             *obufp++ = 'n';
12924           else
12925             used_prefixes |= PREFIX_FWAIT;
12926           break;
12927         case 'O':
12928           USED_REX (REX_W);
12929           if (rex & REX_W)
12930             *obufp++ = 'o';
12931           else if (intel_syntax && (sizeflag & DFLAG))
12932             *obufp++ = 'q';
12933           else
12934             *obufp++ = 'd';
12935           if (!(rex & REX_W))
12936             used_prefixes |= (prefixes & PREFIX_DATA);
12937           break;
12938         case '&':
12939           if (!intel_syntax
12940               && address_mode == mode_64bit
12941               && isa64 == intel64)
12942             {
12943               *obufp++ = 'q';
12944               break;
12945             }
12946           /* Fall through.  */
12947         case 'T':
12948           if (!intel_syntax
12949               && address_mode == mode_64bit
12950               && ((sizeflag & DFLAG) || (rex & REX_W)))
12951             {
12952               *obufp++ = 'q';
12953               break;
12954             }
12955           /* Fall through.  */
12956           goto case_P;
12957         case 'P':
12958           if (l == 0 && len == 1)
12959             {
12960 case_P:
12961               if (intel_syntax)
12962                 {
12963                   if ((rex & REX_W) == 0
12964                       && (prefixes & PREFIX_DATA))
12965                     {
12966                       if ((sizeflag & DFLAG) == 0)
12967                         *obufp++ = 'w';
12968                       used_prefixes |= (prefixes & PREFIX_DATA);
12969                     }
12970                   break;
12971                 }
12972               if ((prefixes & PREFIX_DATA)
12973                   || (rex & REX_W)
12974                   || (sizeflag & SUFFIX_ALWAYS))
12975                 {
12976                   USED_REX (REX_W);
12977                   if (rex & REX_W)
12978                     *obufp++ = 'q';
12979                   else
12980                     {
12981                       if (sizeflag & DFLAG)
12982                         *obufp++ = 'l';
12983                       else
12984                         *obufp++ = 'w';
12985                       used_prefixes |= (prefixes & PREFIX_DATA);
12986                     }
12987                 }
12988             }
12989           else
12990             {
12991               if (l != 1 || len != 2 || last[0] != 'L')
12992                 {
12993                   SAVE_LAST (*p);
12994                   break;
12995                 }
12996
12997               if ((prefixes & PREFIX_DATA)
12998                   || (rex & REX_W)
12999                   || (sizeflag & SUFFIX_ALWAYS))
13000                 {
13001                   USED_REX (REX_W);
13002                   if (rex & REX_W)
13003                     *obufp++ = 'q';
13004                   else
13005                     {
13006                       if (sizeflag & DFLAG)
13007                         *obufp++ = intel_syntax ? 'd' : 'l';
13008                       else
13009                         *obufp++ = 'w';
13010                       used_prefixes |= (prefixes & PREFIX_DATA);
13011                     }
13012                 }
13013             }
13014           break;
13015         case 'U':
13016           if (intel_syntax)
13017             break;
13018           if (address_mode == mode_64bit
13019               && ((sizeflag & DFLAG) || (rex & REX_W)))
13020             {
13021               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13022                 *obufp++ = 'q';
13023               break;
13024             }
13025           /* Fall through.  */
13026           goto case_Q;
13027         case 'Q':
13028           if (l == 0 && len == 1)
13029             {
13030 case_Q:
13031               if (intel_syntax && !alt)
13032                 break;
13033               USED_REX (REX_W);
13034               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13035                 {
13036                   if (rex & REX_W)
13037                     *obufp++ = 'q';
13038                   else
13039                     {
13040                       if (sizeflag & DFLAG)
13041                         *obufp++ = intel_syntax ? 'd' : 'l';
13042                       else
13043                         *obufp++ = 'w';
13044                       used_prefixes |= (prefixes & PREFIX_DATA);
13045                     }
13046                 }
13047             }
13048           else
13049             {
13050               if (l != 1 || len != 2 || last[0] != 'L')
13051                 {
13052                   SAVE_LAST (*p);
13053                   break;
13054                 }
13055               if (intel_syntax
13056                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13057                 break;
13058               if ((rex & REX_W))
13059                 {
13060                   USED_REX (REX_W);
13061                   *obufp++ = 'q';
13062                 }
13063               else
13064                 *obufp++ = 'l';
13065             }
13066           break;
13067         case 'R':
13068           USED_REX (REX_W);
13069           if (rex & REX_W)
13070             *obufp++ = 'q';
13071           else if (sizeflag & DFLAG)
13072             {
13073               if (intel_syntax)
13074                   *obufp++ = 'd';
13075               else
13076                   *obufp++ = 'l';
13077             }
13078           else
13079             *obufp++ = 'w';
13080           if (intel_syntax && !p[1]
13081               && ((rex & REX_W) || (sizeflag & DFLAG)))
13082             *obufp++ = 'e';
13083           if (!(rex & REX_W))
13084             used_prefixes |= (prefixes & PREFIX_DATA);
13085           break;
13086         case 'V':
13087           if (l == 0 && len == 1)
13088             {
13089               if (intel_syntax)
13090                 break;
13091               if (address_mode == mode_64bit
13092                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13093                 {
13094                   if (sizeflag & SUFFIX_ALWAYS)
13095                     *obufp++ = 'q';
13096                   break;
13097                 }
13098             }
13099           else
13100             {
13101               if (l != 1
13102                   || len != 2
13103                   || last[0] != 'L')
13104                 {
13105                   SAVE_LAST (*p);
13106                   break;
13107                 }
13108
13109               if (rex & REX_W)
13110                 {
13111                   *obufp++ = 'a';
13112                   *obufp++ = 'b';
13113                   *obufp++ = 's';
13114                 }
13115             }
13116           /* Fall through.  */
13117           goto case_S;
13118         case 'S':
13119           if (l == 0 && len == 1)
13120             {
13121 case_S:
13122               if (intel_syntax)
13123                 break;
13124               if (sizeflag & SUFFIX_ALWAYS)
13125                 {
13126                   if (rex & REX_W)
13127                     *obufp++ = 'q';
13128                   else
13129                     {
13130                       if (sizeflag & DFLAG)
13131                         *obufp++ = 'l';
13132                       else
13133                         *obufp++ = 'w';
13134                       used_prefixes |= (prefixes & PREFIX_DATA);
13135                     }
13136                 }
13137             }
13138           else
13139             {
13140               if (l != 1
13141                   || len != 2
13142                   || last[0] != 'L')
13143                 {
13144                   SAVE_LAST (*p);
13145                   break;
13146                 }
13147
13148               if (address_mode == mode_64bit
13149                   && !(prefixes & PREFIX_ADDR))
13150                 {
13151                   *obufp++ = 'a';
13152                   *obufp++ = 'b';
13153                   *obufp++ = 's';
13154                 }
13155
13156               goto case_S;
13157             }
13158           break;
13159         case 'X':
13160           if (l != 0 || len != 1)
13161             {
13162               SAVE_LAST (*p);
13163               break;
13164             }
13165           if (need_vex && vex.prefix)
13166             {
13167               if (vex.prefix == DATA_PREFIX_OPCODE)
13168                 *obufp++ = 'd';
13169               else
13170                 *obufp++ = 's';
13171             }
13172           else
13173             {
13174               if (prefixes & PREFIX_DATA)
13175                 *obufp++ = 'd';
13176               else
13177                 *obufp++ = 's';
13178               used_prefixes |= (prefixes & PREFIX_DATA);
13179             }
13180           break;
13181         case 'Y':
13182           if (l == 0 && len == 1)
13183             abort ();
13184           else
13185             {
13186               if (l != 1 || len != 2 || last[0] != 'X')
13187                 {
13188                   SAVE_LAST (*p);
13189                   break;
13190                 }
13191               if (!need_vex)
13192                 abort ();
13193               if (intel_syntax
13194                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13195                 break;
13196               switch (vex.length)
13197                 {
13198                 case 128:
13199                   *obufp++ = 'x';
13200                   break;
13201                 case 256:
13202                   *obufp++ = 'y';
13203                   break;
13204                 case 512:
13205                   if (!vex.evex)
13206                 default:
13207                     abort ();
13208                 }
13209             }
13210           break;
13211         case 'W':
13212           if (l == 0 && len == 1)
13213             {
13214               /* operand size flag for cwtl, cbtw */
13215               USED_REX (REX_W);
13216               if (rex & REX_W)
13217                 {
13218                   if (intel_syntax)
13219                     *obufp++ = 'd';
13220                   else
13221                     *obufp++ = 'l';
13222                 }
13223               else if (sizeflag & DFLAG)
13224                 *obufp++ = 'w';
13225               else
13226                 *obufp++ = 'b';
13227               if (!(rex & REX_W))
13228                 used_prefixes |= (prefixes & PREFIX_DATA);
13229             }
13230           else
13231             {
13232               if (l != 1
13233                   || len != 2
13234                   || (last[0] != 'X'
13235                       && last[0] != 'L'))
13236                 {
13237                   SAVE_LAST (*p);
13238                   break;
13239                 }
13240               if (!need_vex)
13241                 abort ();
13242               if (last[0] == 'X')
13243                 *obufp++ = vex.w ? 'd': 's';
13244               else
13245                 *obufp++ = vex.w ? 'q': 'd';
13246             }
13247           break;
13248         case '^':
13249           if (intel_syntax)
13250             break;
13251           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13252             {
13253               if (sizeflag & DFLAG)
13254                 *obufp++ = 'l';
13255               else
13256                 *obufp++ = 'w';
13257               used_prefixes |= (prefixes & PREFIX_DATA);
13258             }
13259           break;
13260         case '@':
13261           if (intel_syntax)
13262             break;
13263           if (address_mode == mode_64bit
13264               && (isa64 == intel64
13265                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13266               *obufp++ = 'q';
13267           else if ((prefixes & PREFIX_DATA))
13268             {
13269               if (!(sizeflag & DFLAG))
13270                 *obufp++ = 'w';
13271               used_prefixes |= (prefixes & PREFIX_DATA);
13272             }
13273           break;
13274         }
13275       alt = 0;
13276     }
13277   *obufp = 0;
13278   mnemonicendp = obufp;
13279   return 0;
13280 }
13281
13282 static void
13283 oappend (const char *s)
13284 {
13285   obufp = stpcpy (obufp, s);
13286 }
13287
13288 static void
13289 append_seg (void)
13290 {
13291   /* Only print the active segment register.  */
13292   if (!active_seg_prefix)
13293     return;
13294
13295   used_prefixes |= active_seg_prefix;
13296   switch (active_seg_prefix)
13297     {
13298     case PREFIX_CS:
13299       oappend_maybe_intel ("%cs:");
13300       break;
13301     case PREFIX_DS:
13302       oappend_maybe_intel ("%ds:");
13303       break;
13304     case PREFIX_SS:
13305       oappend_maybe_intel ("%ss:");
13306       break;
13307     case PREFIX_ES:
13308       oappend_maybe_intel ("%es:");
13309       break;
13310     case PREFIX_FS:
13311       oappend_maybe_intel ("%fs:");
13312       break;
13313     case PREFIX_GS:
13314       oappend_maybe_intel ("%gs:");
13315       break;
13316     default:
13317       break;
13318     }
13319 }
13320
13321 static void
13322 OP_indirE (int bytemode, int sizeflag)
13323 {
13324   if (!intel_syntax)
13325     oappend ("*");
13326   OP_E (bytemode, sizeflag);
13327 }
13328
13329 static void
13330 print_operand_value (char *buf, int hex, bfd_vma disp)
13331 {
13332   if (address_mode == mode_64bit)
13333     {
13334       if (hex)
13335         {
13336           char tmp[30];
13337           int i;
13338           buf[0] = '0';
13339           buf[1] = 'x';
13340           sprintf_vma (tmp, disp);
13341           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13342           strcpy (buf + 2, tmp + i);
13343         }
13344       else
13345         {
13346           bfd_signed_vma v = disp;
13347           char tmp[30];
13348           int i;
13349           if (v < 0)
13350             {
13351               *(buf++) = '-';
13352               v = -disp;
13353               /* Check for possible overflow on 0x8000000000000000.  */
13354               if (v < 0)
13355                 {
13356                   strcpy (buf, "9223372036854775808");
13357                   return;
13358                 }
13359             }
13360           if (!v)
13361             {
13362               strcpy (buf, "0");
13363               return;
13364             }
13365
13366           i = 0;
13367           tmp[29] = 0;
13368           while (v)
13369             {
13370               tmp[28 - i] = (v % 10) + '0';
13371               v /= 10;
13372               i++;
13373             }
13374           strcpy (buf, tmp + 29 - i);
13375         }
13376     }
13377   else
13378     {
13379       if (hex)
13380         sprintf (buf, "0x%x", (unsigned int) disp);
13381       else
13382         sprintf (buf, "%d", (int) disp);
13383     }
13384 }
13385
13386 /* Put DISP in BUF as signed hex number.  */
13387
13388 static void
13389 print_displacement (char *buf, bfd_vma disp)
13390 {
13391   bfd_signed_vma val = disp;
13392   char tmp[30];
13393   int i, j = 0;
13394
13395   if (val < 0)
13396     {
13397       buf[j++] = '-';
13398       val = -disp;
13399
13400       /* Check for possible overflow.  */
13401       if (val < 0)
13402         {
13403           switch (address_mode)
13404             {
13405             case mode_64bit:
13406               strcpy (buf + j, "0x8000000000000000");
13407               break;
13408             case mode_32bit:
13409               strcpy (buf + j, "0x80000000");
13410               break;
13411             case mode_16bit:
13412               strcpy (buf + j, "0x8000");
13413               break;
13414             }
13415           return;
13416         }
13417     }
13418
13419   buf[j++] = '0';
13420   buf[j++] = 'x';
13421
13422   sprintf_vma (tmp, (bfd_vma) val);
13423   for (i = 0; tmp[i] == '0'; i++)
13424     continue;
13425   if (tmp[i] == '\0')
13426     i--;
13427   strcpy (buf + j, tmp + i);
13428 }
13429
13430 static void
13431 intel_operand_size (int bytemode, int sizeflag)
13432 {
13433   if (vex.evex
13434       && vex.b
13435       && (bytemode == x_mode
13436           || bytemode == evex_half_bcst_xmmq_mode))
13437     {
13438       if (vex.w)
13439         oappend ("QWORD PTR ");
13440       else
13441         oappend ("DWORD PTR ");
13442       return;
13443     }
13444   switch (bytemode)
13445     {
13446     case b_mode:
13447     case b_swap_mode:
13448     case dqb_mode:
13449     case db_mode:
13450       oappend ("BYTE PTR ");
13451       break;
13452     case w_mode:
13453     case dw_mode:
13454     case dqw_mode:
13455       oappend ("WORD PTR ");
13456       break;
13457     case indir_v_mode:
13458       if (address_mode == mode_64bit && isa64 == intel64)
13459         {
13460           oappend ("QWORD PTR ");
13461           break;
13462         }
13463       /* Fall through.  */
13464     case stack_v_mode:
13465       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13466         {
13467           oappend ("QWORD PTR ");
13468           break;
13469         }
13470       /* Fall through.  */
13471     case v_mode:
13472     case v_swap_mode:
13473     case dq_mode:
13474       USED_REX (REX_W);
13475       if (rex & REX_W)
13476         oappend ("QWORD PTR ");
13477       else
13478         {
13479           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13480             oappend ("DWORD PTR ");
13481           else
13482             oappend ("WORD PTR ");
13483           used_prefixes |= (prefixes & PREFIX_DATA);
13484         }
13485       break;
13486     case z_mode:
13487       if ((rex & REX_W) || (sizeflag & DFLAG))
13488         *obufp++ = 'D';
13489       oappend ("WORD PTR ");
13490       if (!(rex & REX_W))
13491         used_prefixes |= (prefixes & PREFIX_DATA);
13492       break;
13493     case a_mode:
13494       if (sizeflag & DFLAG)
13495         oappend ("QWORD PTR ");
13496       else
13497         oappend ("DWORD PTR ");
13498       used_prefixes |= (prefixes & PREFIX_DATA);
13499       break;
13500     case d_mode:
13501     case d_scalar_mode:
13502     case d_scalar_swap_mode:
13503     case d_swap_mode:
13504     case dqd_mode:
13505       oappend ("DWORD PTR ");
13506       break;
13507     case q_mode:
13508     case q_scalar_mode:
13509     case q_scalar_swap_mode:
13510     case q_swap_mode:
13511       oappend ("QWORD PTR ");
13512       break;
13513     case dqa_mode:
13514     case m_mode:
13515       if (address_mode == mode_64bit)
13516         oappend ("QWORD PTR ");
13517       else
13518         oappend ("DWORD PTR ");
13519       break;
13520     case f_mode:
13521       if (sizeflag & DFLAG)
13522         oappend ("FWORD PTR ");
13523       else
13524         oappend ("DWORD PTR ");
13525       used_prefixes |= (prefixes & PREFIX_DATA);
13526       break;
13527     case t_mode:
13528       oappend ("TBYTE PTR ");
13529       break;
13530     case x_mode:
13531     case x_swap_mode:
13532     case evex_x_gscat_mode:
13533     case evex_x_nobcst_mode:
13534     case b_scalar_mode:
13535     case w_scalar_mode:
13536       if (need_vex)
13537         {
13538           switch (vex.length)
13539             {
13540             case 128:
13541               oappend ("XMMWORD PTR ");
13542               break;
13543             case 256:
13544               oappend ("YMMWORD PTR ");
13545               break;
13546             case 512:
13547               oappend ("ZMMWORD PTR ");
13548               break;
13549             default:
13550               abort ();
13551             }
13552         }
13553       else
13554         oappend ("XMMWORD PTR ");
13555       break;
13556     case xmm_mode:
13557       oappend ("XMMWORD PTR ");
13558       break;
13559     case ymm_mode:
13560       oappend ("YMMWORD PTR ");
13561       break;
13562     case xmmq_mode:
13563     case evex_half_bcst_xmmq_mode:
13564       if (!need_vex)
13565         abort ();
13566
13567       switch (vex.length)
13568         {
13569         case 128:
13570           oappend ("QWORD PTR ");
13571           break;
13572         case 256:
13573           oappend ("XMMWORD PTR ");
13574           break;
13575         case 512:
13576           oappend ("YMMWORD PTR ");
13577           break;
13578         default:
13579           abort ();
13580         }
13581       break;
13582     case xmm_mb_mode:
13583       if (!need_vex)
13584         abort ();
13585
13586       switch (vex.length)
13587         {
13588         case 128:
13589         case 256:
13590         case 512:
13591           oappend ("BYTE PTR ");
13592           break;
13593         default:
13594           abort ();
13595         }
13596       break;
13597     case xmm_mw_mode:
13598       if (!need_vex)
13599         abort ();
13600
13601       switch (vex.length)
13602         {
13603         case 128:
13604         case 256:
13605         case 512:
13606           oappend ("WORD PTR ");
13607           break;
13608         default:
13609           abort ();
13610         }
13611       break;
13612     case xmm_md_mode:
13613       if (!need_vex)
13614         abort ();
13615
13616       switch (vex.length)
13617         {
13618         case 128:
13619         case 256:
13620         case 512:
13621           oappend ("DWORD PTR ");
13622           break;
13623         default:
13624           abort ();
13625         }
13626       break;
13627     case xmm_mq_mode:
13628       if (!need_vex)
13629         abort ();
13630
13631       switch (vex.length)
13632         {
13633         case 128:
13634         case 256:
13635         case 512:
13636           oappend ("QWORD PTR ");
13637           break;
13638         default:
13639           abort ();
13640         }
13641       break;
13642     case xmmdw_mode:
13643       if (!need_vex)
13644         abort ();
13645
13646       switch (vex.length)
13647         {
13648         case 128:
13649           oappend ("WORD PTR ");
13650           break;
13651         case 256:
13652           oappend ("DWORD PTR ");
13653           break;
13654         case 512:
13655           oappend ("QWORD PTR ");
13656           break;
13657         default:
13658           abort ();
13659         }
13660       break;
13661     case xmmqd_mode:
13662       if (!need_vex)
13663         abort ();
13664
13665       switch (vex.length)
13666         {
13667         case 128:
13668           oappend ("DWORD PTR ");
13669           break;
13670         case 256:
13671           oappend ("QWORD PTR ");
13672           break;
13673         case 512:
13674           oappend ("XMMWORD PTR ");
13675           break;
13676         default:
13677           abort ();
13678         }
13679       break;
13680     case ymmq_mode:
13681       if (!need_vex)
13682         abort ();
13683
13684       switch (vex.length)
13685         {
13686         case 128:
13687           oappend ("QWORD PTR ");
13688           break;
13689         case 256:
13690           oappend ("YMMWORD PTR ");
13691           break;
13692         case 512:
13693           oappend ("ZMMWORD PTR ");
13694           break;
13695         default:
13696           abort ();
13697         }
13698       break;
13699     case ymmxmm_mode:
13700       if (!need_vex)
13701         abort ();
13702
13703       switch (vex.length)
13704         {
13705         case 128:
13706         case 256:
13707           oappend ("XMMWORD PTR ");
13708           break;
13709         default:
13710           abort ();
13711         }
13712       break;
13713     case o_mode:
13714       oappend ("OWORD PTR ");
13715       break;
13716     case xmm_mdq_mode:
13717     case vex_w_dq_mode:
13718     case vex_scalar_w_dq_mode:
13719       if (!need_vex)
13720         abort ();
13721
13722       if (vex.w)
13723         oappend ("QWORD PTR ");
13724       else
13725         oappend ("DWORD PTR ");
13726       break;
13727     case vex_vsib_d_w_dq_mode:
13728     case vex_vsib_q_w_dq_mode:
13729       if (!need_vex)
13730         abort ();
13731
13732       if (!vex.evex)
13733         {
13734           if (vex.w)
13735             oappend ("QWORD PTR ");
13736           else
13737             oappend ("DWORD PTR ");
13738         }
13739       else
13740         {
13741           switch (vex.length)
13742             {
13743             case 128:
13744               oappend ("XMMWORD PTR ");
13745               break;
13746             case 256:
13747               oappend ("YMMWORD PTR ");
13748               break;
13749             case 512:
13750               oappend ("ZMMWORD PTR ");
13751               break;
13752             default:
13753               abort ();
13754             }
13755         }
13756       break;
13757     case vex_vsib_q_w_d_mode:
13758     case vex_vsib_d_w_d_mode:
13759       if (!need_vex || !vex.evex)
13760         abort ();
13761
13762       switch (vex.length)
13763         {
13764         case 128:
13765           oappend ("QWORD PTR ");
13766           break;
13767         case 256:
13768           oappend ("XMMWORD PTR ");
13769           break;
13770         case 512:
13771           oappend ("YMMWORD PTR ");
13772           break;
13773         default:
13774           abort ();
13775         }
13776
13777       break;
13778     case mask_bd_mode:
13779       if (!need_vex || vex.length != 128)
13780         abort ();
13781       if (vex.w)
13782         oappend ("DWORD PTR ");
13783       else
13784         oappend ("BYTE PTR ");
13785       break;
13786     case mask_mode:
13787       if (!need_vex)
13788         abort ();
13789       if (vex.w)
13790         oappend ("QWORD PTR ");
13791       else
13792         oappend ("WORD PTR ");
13793       break;
13794     case v_bnd_mode:
13795     case v_bndmk_mode:
13796     default:
13797       break;
13798     }
13799 }
13800
13801 static void
13802 OP_E_register (int bytemode, int sizeflag)
13803 {
13804   int reg = modrm.rm;
13805   const char **names;
13806
13807   USED_REX (REX_B);
13808   if ((rex & REX_B))
13809     reg += 8;
13810
13811   if ((sizeflag & SUFFIX_ALWAYS)
13812       && (bytemode == b_swap_mode
13813           || bytemode == bnd_swap_mode
13814           || bytemode == v_swap_mode))
13815     swap_operand ();
13816
13817   switch (bytemode)
13818     {
13819     case b_mode:
13820     case b_swap_mode:
13821       USED_REX (0);
13822       if (rex)
13823         names = names8rex;
13824       else
13825         names = names8;
13826       break;
13827     case w_mode:
13828       names = names16;
13829       break;
13830     case d_mode:
13831     case dw_mode:
13832     case db_mode:
13833       names = names32;
13834       break;
13835     case q_mode:
13836       names = names64;
13837       break;
13838     case m_mode:
13839     case v_bnd_mode:
13840       names = address_mode == mode_64bit ? names64 : names32;
13841       break;
13842     case bnd_mode:
13843     case bnd_swap_mode:
13844       if (reg > 0x3)
13845         {
13846           oappend ("(bad)");
13847           return;
13848         }
13849       names = names_bnd;
13850       break;
13851     case indir_v_mode:
13852       if (address_mode == mode_64bit && isa64 == intel64)
13853         {
13854           names = names64;
13855           break;
13856         }
13857       /* Fall through.  */
13858     case stack_v_mode:
13859       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13860         {
13861           names = names64;
13862           break;
13863         }
13864       bytemode = v_mode;
13865       /* Fall through.  */
13866     case v_mode:
13867     case v_swap_mode:
13868     case dq_mode:
13869     case dqb_mode:
13870     case dqd_mode:
13871     case dqw_mode:
13872     case dqa_mode:
13873       USED_REX (REX_W);
13874       if (rex & REX_W)
13875         names = names64;
13876       else
13877         {
13878           if ((sizeflag & DFLAG)
13879               || (bytemode != v_mode
13880                   && bytemode != v_swap_mode))
13881             names = names32;
13882           else
13883             names = names16;
13884           used_prefixes |= (prefixes & PREFIX_DATA);
13885         }
13886       break;
13887     case va_mode:
13888       names = (address_mode == mode_64bit
13889                ? names64 : names32);
13890       if (!(prefixes & PREFIX_ADDR))
13891         names = (address_mode == mode_16bit
13892                      ? names16 : names);
13893       else
13894         {
13895           /* Remove "addr16/addr32".  */
13896           all_prefixes[last_addr_prefix] = 0;
13897           names = (address_mode != mode_32bit
13898                        ? names32 : names16);
13899           used_prefixes |= PREFIX_ADDR;
13900         }
13901       break;
13902     case mask_bd_mode:
13903     case mask_mode:
13904       if (reg > 0x7)
13905         {
13906           oappend ("(bad)");
13907           return;
13908         }
13909       names = names_mask;
13910       break;
13911     case 0:
13912       return;
13913     default:
13914       oappend (INTERNAL_DISASSEMBLER_ERROR);
13915       return;
13916     }
13917   oappend (names[reg]);
13918 }
13919
13920 static void
13921 OP_E_memory (int bytemode, int sizeflag)
13922 {
13923   bfd_vma disp = 0;
13924   int add = (rex & REX_B) ? 8 : 0;
13925   int riprel = 0;
13926   int shift;
13927
13928   if (vex.evex)
13929     {
13930       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13931       if (vex.b
13932           && bytemode != x_mode
13933           && bytemode != xmmq_mode
13934           && bytemode != evex_half_bcst_xmmq_mode)
13935         {
13936           BadOp ();
13937           return;
13938         }
13939       switch (bytemode)
13940         {
13941         case dqw_mode:
13942         case dw_mode:
13943           shift = 1;
13944           break;
13945         case dqb_mode:
13946         case db_mode:
13947           shift = 0;
13948           break;
13949         case dq_mode:
13950           if (address_mode != mode_64bit)
13951             {
13952               shift = 2;
13953               break;
13954             }
13955             /* fall through */
13956         case vex_vsib_d_w_dq_mode:
13957         case vex_vsib_d_w_d_mode:
13958         case vex_vsib_q_w_dq_mode:
13959         case vex_vsib_q_w_d_mode:
13960         case evex_x_gscat_mode:
13961         case xmm_mdq_mode:
13962           shift = vex.w ? 3 : 2;
13963           break;
13964         case x_mode:
13965         case evex_half_bcst_xmmq_mode:
13966         case xmmq_mode:
13967           if (vex.b)
13968             {
13969               shift = vex.w ? 3 : 2;
13970               break;
13971             }
13972           /* Fall through.  */
13973         case xmmqd_mode:
13974         case xmmdw_mode:
13975         case ymmq_mode:
13976         case evex_x_nobcst_mode:
13977         case x_swap_mode:
13978           switch (vex.length)
13979             {
13980             case 128:
13981               shift = 4;
13982               break;
13983             case 256:
13984               shift = 5;
13985               break;
13986             case 512:
13987               shift = 6;
13988               break;
13989             default:
13990               abort ();
13991             }
13992           break;
13993         case ymm_mode:
13994           shift = 5;
13995           break;
13996         case xmm_mode:
13997           shift = 4;
13998           break;
13999         case xmm_mq_mode:
14000         case q_mode:
14001         case q_scalar_mode:
14002         case q_swap_mode:
14003         case q_scalar_swap_mode:
14004           shift = 3;
14005           break;
14006         case dqd_mode:
14007         case xmm_md_mode:
14008         case d_mode:
14009         case d_scalar_mode:
14010         case d_swap_mode:
14011         case d_scalar_swap_mode:
14012           shift = 2;
14013           break;
14014         case w_scalar_mode:
14015         case xmm_mw_mode:
14016           shift = 1;
14017           break;
14018         case b_scalar_mode:
14019         case xmm_mb_mode:
14020           shift = 0;
14021           break;
14022         case dqa_mode:
14023           shift = address_mode == mode_64bit ? 3 : 2;
14024           break;
14025         default:
14026           abort ();
14027         }
14028       /* Make necessary corrections to shift for modes that need it.
14029          For these modes we currently have shift 4, 5 or 6 depending on
14030          vex.length (it corresponds to xmmword, ymmword or zmmword
14031          operand).  We might want to make it 3, 4 or 5 (e.g. for
14032          xmmq_mode).  In case of broadcast enabled the corrections
14033          aren't needed, as element size is always 32 or 64 bits.  */
14034       if (!vex.b
14035           && (bytemode == xmmq_mode
14036               || bytemode == evex_half_bcst_xmmq_mode))
14037         shift -= 1;
14038       else if (bytemode == xmmqd_mode)
14039         shift -= 2;
14040       else if (bytemode == xmmdw_mode)
14041         shift -= 3;
14042       else if (bytemode == ymmq_mode && vex.length == 128)
14043         shift -= 1;
14044     }
14045   else
14046     shift = 0;
14047
14048   USED_REX (REX_B);
14049   if (intel_syntax)
14050     intel_operand_size (bytemode, sizeflag);
14051   append_seg ();
14052
14053   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14054     {
14055       /* 32/64 bit address mode */
14056       int havedisp;
14057       int havesib;
14058       int havebase;
14059       int haveindex;
14060       int needindex;
14061       int needaddr32;
14062       int base, rbase;
14063       int vindex = 0;
14064       int scale = 0;
14065       int addr32flag = !((sizeflag & AFLAG)
14066                          || bytemode == v_bnd_mode
14067                          || bytemode == v_bndmk_mode
14068                          || bytemode == bnd_mode
14069                          || bytemode == bnd_swap_mode);
14070       const char **indexes64 = names64;
14071       const char **indexes32 = names32;
14072
14073       havesib = 0;
14074       havebase = 1;
14075       haveindex = 0;
14076       base = modrm.rm;
14077
14078       if (base == 4)
14079         {
14080           havesib = 1;
14081           vindex = sib.index;
14082           USED_REX (REX_X);
14083           if (rex & REX_X)
14084             vindex += 8;
14085           switch (bytemode)
14086             {
14087             case vex_vsib_d_w_dq_mode:
14088             case vex_vsib_d_w_d_mode:
14089             case vex_vsib_q_w_dq_mode:
14090             case vex_vsib_q_w_d_mode:
14091               if (!need_vex)
14092                 abort ();
14093               if (vex.evex)
14094                 {
14095                   if (!vex.v)
14096                     vindex += 16;
14097                 }
14098
14099               haveindex = 1;
14100               switch (vex.length)
14101                 {
14102                 case 128:
14103                   indexes64 = indexes32 = names_xmm;
14104                   break;
14105                 case 256:
14106                   if (!vex.w
14107                       || bytemode == vex_vsib_q_w_dq_mode
14108                       || bytemode == vex_vsib_q_w_d_mode)
14109                     indexes64 = indexes32 = names_ymm;
14110                   else
14111                     indexes64 = indexes32 = names_xmm;
14112                   break;
14113                 case 512:
14114                   if (!vex.w
14115                       || bytemode == vex_vsib_q_w_dq_mode
14116                       || bytemode == vex_vsib_q_w_d_mode)
14117                     indexes64 = indexes32 = names_zmm;
14118                   else
14119                     indexes64 = indexes32 = names_ymm;
14120                   break;
14121                 default:
14122                   abort ();
14123                 }
14124               break;
14125             default:
14126               haveindex = vindex != 4;
14127               break;
14128             }
14129           scale = sib.scale;
14130           base = sib.base;
14131           codep++;
14132         }
14133       rbase = base + add;
14134
14135       switch (modrm.mod)
14136         {
14137         case 0:
14138           if (base == 5)
14139             {
14140               havebase = 0;
14141               if (address_mode == mode_64bit && !havesib)
14142                 riprel = 1;
14143               disp = get32s ();
14144               if (riprel && bytemode == v_bndmk_mode)
14145                 {
14146                   oappend ("(bad)");
14147                   return;
14148                 }
14149             }
14150           break;
14151         case 1:
14152           FETCH_DATA (the_info, codep + 1);
14153           disp = *codep++;
14154           if ((disp & 0x80) != 0)
14155             disp -= 0x100;
14156           if (vex.evex && shift > 0)
14157             disp <<= shift;
14158           break;
14159         case 2:
14160           disp = get32s ();
14161           break;
14162         }
14163
14164       needindex = 0;
14165       needaddr32 = 0;
14166       if (havesib
14167           && !havebase
14168           && !haveindex
14169           && address_mode != mode_16bit)
14170         {
14171           if (address_mode == mode_64bit)
14172             {
14173               /* Display eiz instead of addr32.  */
14174               needindex = addr32flag;
14175               needaddr32 = 1;
14176             }
14177           else
14178             {
14179               /* In 32-bit mode, we need index register to tell [offset]
14180                  from [eiz*1 + offset].  */
14181               needindex = 1;
14182             }
14183         }
14184
14185       havedisp = (havebase
14186                   || needindex
14187                   || (havesib && (haveindex || scale != 0)));
14188
14189       if (!intel_syntax)
14190         if (modrm.mod != 0 || base == 5)
14191           {
14192             if (havedisp || riprel)
14193               print_displacement (scratchbuf, disp);
14194             else
14195               print_operand_value (scratchbuf, 1, disp);
14196             oappend (scratchbuf);
14197             if (riprel)
14198               {
14199                 set_op (disp, 1);
14200                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14201               }
14202           }
14203
14204       if ((havebase || haveindex || needaddr32 || riprel)
14205           && (bytemode != v_bnd_mode)
14206           && (bytemode != v_bndmk_mode)
14207           && (bytemode != bnd_mode)
14208           && (bytemode != bnd_swap_mode))
14209         used_prefixes |= PREFIX_ADDR;
14210
14211       if (havedisp || (intel_syntax && riprel))
14212         {
14213           *obufp++ = open_char;
14214           if (intel_syntax && riprel)
14215             {
14216               set_op (disp, 1);
14217               oappend (!addr32flag ? "rip" : "eip");
14218             }
14219           *obufp = '\0';
14220           if (havebase)
14221             oappend (address_mode == mode_64bit && !addr32flag
14222                      ? names64[rbase] : names32[rbase]);
14223           if (havesib)
14224             {
14225               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14226                  print index to tell base + index from base.  */
14227               if (scale != 0
14228                   || needindex
14229                   || haveindex
14230                   || (havebase && base != ESP_REG_NUM))
14231                 {
14232                   if (!intel_syntax || havebase)
14233                     {
14234                       *obufp++ = separator_char;
14235                       *obufp = '\0';
14236                     }
14237                   if (haveindex)
14238                     oappend (address_mode == mode_64bit && !addr32flag
14239                              ? indexes64[vindex] : indexes32[vindex]);
14240                   else
14241                     oappend (address_mode == mode_64bit && !addr32flag
14242                              ? index64 : index32);
14243
14244                   *obufp++ = scale_char;
14245                   *obufp = '\0';
14246                   sprintf (scratchbuf, "%d", 1 << scale);
14247                   oappend (scratchbuf);
14248                 }
14249             }
14250           if (intel_syntax
14251               && (disp || modrm.mod != 0 || base == 5))
14252             {
14253               if (!havedisp || (bfd_signed_vma) disp >= 0)
14254                 {
14255                   *obufp++ = '+';
14256                   *obufp = '\0';
14257                 }
14258               else if (modrm.mod != 1 && disp != -disp)
14259                 {
14260                   *obufp++ = '-';
14261                   *obufp = '\0';
14262                   disp = - (bfd_signed_vma) disp;
14263                 }
14264
14265               if (havedisp)
14266                 print_displacement (scratchbuf, disp);
14267               else
14268                 print_operand_value (scratchbuf, 1, disp);
14269               oappend (scratchbuf);
14270             }
14271
14272           *obufp++ = close_char;
14273           *obufp = '\0';
14274         }
14275       else if (intel_syntax)
14276         {
14277           if (modrm.mod != 0 || base == 5)
14278             {
14279               if (!active_seg_prefix)
14280                 {
14281                   oappend (names_seg[ds_reg - es_reg]);
14282                   oappend (":");
14283                 }
14284               print_operand_value (scratchbuf, 1, disp);
14285               oappend (scratchbuf);
14286             }
14287         }
14288     }
14289   else
14290     {
14291       /* 16 bit address mode */
14292       used_prefixes |= prefixes & PREFIX_ADDR;
14293       switch (modrm.mod)
14294         {
14295         case 0:
14296           if (modrm.rm == 6)
14297             {
14298               disp = get16 ();
14299               if ((disp & 0x8000) != 0)
14300                 disp -= 0x10000;
14301             }
14302           break;
14303         case 1:
14304           FETCH_DATA (the_info, codep + 1);
14305           disp = *codep++;
14306           if ((disp & 0x80) != 0)
14307             disp -= 0x100;
14308           if (vex.evex && shift > 0)
14309             disp <<= shift;
14310           break;
14311         case 2:
14312           disp = get16 ();
14313           if ((disp & 0x8000) != 0)
14314             disp -= 0x10000;
14315           break;
14316         }
14317
14318       if (!intel_syntax)
14319         if (modrm.mod != 0 || modrm.rm == 6)
14320           {
14321             print_displacement (scratchbuf, disp);
14322             oappend (scratchbuf);
14323           }
14324
14325       if (modrm.mod != 0 || modrm.rm != 6)
14326         {
14327           *obufp++ = open_char;
14328           *obufp = '\0';
14329           oappend (index16[modrm.rm]);
14330           if (intel_syntax
14331               && (disp || modrm.mod != 0 || modrm.rm == 6))
14332             {
14333               if ((bfd_signed_vma) disp >= 0)
14334                 {
14335                   *obufp++ = '+';
14336                   *obufp = '\0';
14337                 }
14338               else if (modrm.mod != 1)
14339                 {
14340                   *obufp++ = '-';
14341                   *obufp = '\0';
14342                   disp = - (bfd_signed_vma) disp;
14343                 }
14344
14345               print_displacement (scratchbuf, disp);
14346               oappend (scratchbuf);
14347             }
14348
14349           *obufp++ = close_char;
14350           *obufp = '\0';
14351         }
14352       else if (intel_syntax)
14353         {
14354           if (!active_seg_prefix)
14355             {
14356               oappend (names_seg[ds_reg - es_reg]);
14357               oappend (":");
14358             }
14359           print_operand_value (scratchbuf, 1, disp & 0xffff);
14360           oappend (scratchbuf);
14361         }
14362     }
14363   if (vex.evex && vex.b
14364       && (bytemode == x_mode
14365           || bytemode == xmmq_mode
14366           || bytemode == evex_half_bcst_xmmq_mode))
14367     {
14368       if (vex.w
14369           || bytemode == xmmq_mode
14370           || bytemode == evex_half_bcst_xmmq_mode)
14371         {
14372           switch (vex.length)
14373             {
14374             case 128:
14375               oappend ("{1to2}");
14376               break;
14377             case 256:
14378               oappend ("{1to4}");
14379               break;
14380             case 512:
14381               oappend ("{1to8}");
14382               break;
14383             default:
14384               abort ();
14385             }
14386         }
14387       else
14388         {
14389           switch (vex.length)
14390             {
14391             case 128:
14392               oappend ("{1to4}");
14393               break;
14394             case 256:
14395               oappend ("{1to8}");
14396               break;
14397             case 512:
14398               oappend ("{1to16}");
14399               break;
14400             default:
14401               abort ();
14402             }
14403         }
14404     }
14405 }
14406
14407 static void
14408 OP_E (int bytemode, int sizeflag)
14409 {
14410   /* Skip mod/rm byte.  */
14411   MODRM_CHECK;
14412   codep++;
14413
14414   if (modrm.mod == 3)
14415     OP_E_register (bytemode, sizeflag);
14416   else
14417     OP_E_memory (bytemode, sizeflag);
14418 }
14419
14420 static void
14421 OP_G (int bytemode, int sizeflag)
14422 {
14423   int add = 0;
14424   const char **names;
14425   USED_REX (REX_R);
14426   if (rex & REX_R)
14427     add += 8;
14428   switch (bytemode)
14429     {
14430     case b_mode:
14431       USED_REX (0);
14432       if (rex)
14433         oappend (names8rex[modrm.reg + add]);
14434       else
14435         oappend (names8[modrm.reg + add]);
14436       break;
14437     case w_mode:
14438       oappend (names16[modrm.reg + add]);
14439       break;
14440     case d_mode:
14441     case db_mode:
14442     case dw_mode:
14443       oappend (names32[modrm.reg + add]);
14444       break;
14445     case q_mode:
14446       oappend (names64[modrm.reg + add]);
14447       break;
14448     case bnd_mode:
14449       if (modrm.reg > 0x3)
14450         {
14451           oappend ("(bad)");
14452           return;
14453         }
14454       oappend (names_bnd[modrm.reg]);
14455       break;
14456     case v_mode:
14457     case dq_mode:
14458     case dqb_mode:
14459     case dqd_mode:
14460     case dqw_mode:
14461       USED_REX (REX_W);
14462       if (rex & REX_W)
14463         oappend (names64[modrm.reg + add]);
14464       else
14465         {
14466           if ((sizeflag & DFLAG) || bytemode != v_mode)
14467             oappend (names32[modrm.reg + add]);
14468           else
14469             oappend (names16[modrm.reg + add]);
14470           used_prefixes |= (prefixes & PREFIX_DATA);
14471         }
14472       break;
14473     case va_mode:
14474       names = (address_mode == mode_64bit
14475                ? names64 : names32);
14476       if (!(prefixes & PREFIX_ADDR))
14477         {
14478           if (address_mode == mode_16bit)
14479             names = names16;
14480         }
14481       else
14482         {
14483           /* Remove "addr16/addr32".  */
14484           all_prefixes[last_addr_prefix] = 0;
14485           names = (address_mode != mode_32bit
14486                        ? names32 : names16);
14487           used_prefixes |= PREFIX_ADDR;
14488         }
14489       oappend (names[modrm.reg + add]);
14490       break;
14491     case m_mode:
14492       if (address_mode == mode_64bit)
14493         oappend (names64[modrm.reg + add]);
14494       else
14495         oappend (names32[modrm.reg + add]);
14496       break;
14497     case mask_bd_mode:
14498     case mask_mode:
14499       if ((modrm.reg + add) > 0x7)
14500         {
14501           oappend ("(bad)");
14502           return;
14503         }
14504       oappend (names_mask[modrm.reg + add]);
14505       break;
14506     default:
14507       oappend (INTERNAL_DISASSEMBLER_ERROR);
14508       break;
14509     }
14510 }
14511
14512 static bfd_vma
14513 get64 (void)
14514 {
14515   bfd_vma x;
14516 #ifdef BFD64
14517   unsigned int a;
14518   unsigned int b;
14519
14520   FETCH_DATA (the_info, codep + 8);
14521   a = *codep++ & 0xff;
14522   a |= (*codep++ & 0xff) << 8;
14523   a |= (*codep++ & 0xff) << 16;
14524   a |= (*codep++ & 0xffu) << 24;
14525   b = *codep++ & 0xff;
14526   b |= (*codep++ & 0xff) << 8;
14527   b |= (*codep++ & 0xff) << 16;
14528   b |= (*codep++ & 0xffu) << 24;
14529   x = a + ((bfd_vma) b << 32);
14530 #else
14531   abort ();
14532   x = 0;
14533 #endif
14534   return x;
14535 }
14536
14537 static bfd_signed_vma
14538 get32 (void)
14539 {
14540   bfd_signed_vma x = 0;
14541
14542   FETCH_DATA (the_info, codep + 4);
14543   x = *codep++ & (bfd_signed_vma) 0xff;
14544   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14545   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14546   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14547   return x;
14548 }
14549
14550 static bfd_signed_vma
14551 get32s (void)
14552 {
14553   bfd_signed_vma x = 0;
14554
14555   FETCH_DATA (the_info, codep + 4);
14556   x = *codep++ & (bfd_signed_vma) 0xff;
14557   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14558   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14559   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14560
14561   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14562
14563   return x;
14564 }
14565
14566 static int
14567 get16 (void)
14568 {
14569   int x = 0;
14570
14571   FETCH_DATA (the_info, codep + 2);
14572   x = *codep++ & 0xff;
14573   x |= (*codep++ & 0xff) << 8;
14574   return x;
14575 }
14576
14577 static void
14578 set_op (bfd_vma op, int riprel)
14579 {
14580   op_index[op_ad] = op_ad;
14581   if (address_mode == mode_64bit)
14582     {
14583       op_address[op_ad] = op;
14584       op_riprel[op_ad] = riprel;
14585     }
14586   else
14587     {
14588       /* Mask to get a 32-bit address.  */
14589       op_address[op_ad] = op & 0xffffffff;
14590       op_riprel[op_ad] = riprel & 0xffffffff;
14591     }
14592 }
14593
14594 static void
14595 OP_REG (int code, int sizeflag)
14596 {
14597   const char *s;
14598   int add;
14599
14600   switch (code)
14601     {
14602     case es_reg: case ss_reg: case cs_reg:
14603     case ds_reg: case fs_reg: case gs_reg:
14604       oappend (names_seg[code - es_reg]);
14605       return;
14606     }
14607
14608   USED_REX (REX_B);
14609   if (rex & REX_B)
14610     add = 8;
14611   else
14612     add = 0;
14613
14614   switch (code)
14615     {
14616     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14617     case sp_reg: case bp_reg: case si_reg: case di_reg:
14618       s = names16[code - ax_reg + add];
14619       break;
14620     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14621     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14622       USED_REX (0);
14623       if (rex)
14624         s = names8rex[code - al_reg + add];
14625       else
14626         s = names8[code - al_reg];
14627       break;
14628     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14629     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14630       if (address_mode == mode_64bit
14631           && ((sizeflag & DFLAG) || (rex & REX_W)))
14632         {
14633           s = names64[code - rAX_reg + add];
14634           break;
14635         }
14636       code += eAX_reg - rAX_reg;
14637       /* Fall through.  */
14638     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14639     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14640       USED_REX (REX_W);
14641       if (rex & REX_W)
14642         s = names64[code - eAX_reg + add];
14643       else
14644         {
14645           if (sizeflag & DFLAG)
14646             s = names32[code - eAX_reg + add];
14647           else
14648             s = names16[code - eAX_reg + add];
14649           used_prefixes |= (prefixes & PREFIX_DATA);
14650         }
14651       break;
14652     default:
14653       s = INTERNAL_DISASSEMBLER_ERROR;
14654       break;
14655     }
14656   oappend (s);
14657 }
14658
14659 static void
14660 OP_IMREG (int code, int sizeflag)
14661 {
14662   const char *s;
14663
14664   switch (code)
14665     {
14666     case indir_dx_reg:
14667       if (intel_syntax)
14668         s = "dx";
14669       else
14670         s = "(%dx)";
14671       break;
14672     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14673     case sp_reg: case bp_reg: case si_reg: case di_reg:
14674       s = names16[code - ax_reg];
14675       break;
14676     case es_reg: case ss_reg: case cs_reg:
14677     case ds_reg: case fs_reg: case gs_reg:
14678       s = names_seg[code - es_reg];
14679       break;
14680     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14681     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14682       USED_REX (0);
14683       if (rex)
14684         s = names8rex[code - al_reg];
14685       else
14686         s = names8[code - al_reg];
14687       break;
14688     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14689     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14690       USED_REX (REX_W);
14691       if (rex & REX_W)
14692         s = names64[code - eAX_reg];
14693       else
14694         {
14695           if (sizeflag & DFLAG)
14696             s = names32[code - eAX_reg];
14697           else
14698             s = names16[code - eAX_reg];
14699           used_prefixes |= (prefixes & PREFIX_DATA);
14700         }
14701       break;
14702     case z_mode_ax_reg:
14703       if ((rex & REX_W) || (sizeflag & DFLAG))
14704         s = *names32;
14705       else
14706         s = *names16;
14707       if (!(rex & REX_W))
14708         used_prefixes |= (prefixes & PREFIX_DATA);
14709       break;
14710     default:
14711       s = INTERNAL_DISASSEMBLER_ERROR;
14712       break;
14713     }
14714   oappend (s);
14715 }
14716
14717 static void
14718 OP_I (int bytemode, int sizeflag)
14719 {
14720   bfd_signed_vma op;
14721   bfd_signed_vma mask = -1;
14722
14723   switch (bytemode)
14724     {
14725     case b_mode:
14726       FETCH_DATA (the_info, codep + 1);
14727       op = *codep++;
14728       mask = 0xff;
14729       break;
14730     case q_mode:
14731       if (address_mode == mode_64bit)
14732         {
14733           op = get32s ();
14734           break;
14735         }
14736       /* Fall through.  */
14737     case v_mode:
14738       USED_REX (REX_W);
14739       if (rex & REX_W)
14740         op = get32s ();
14741       else
14742         {
14743           if (sizeflag & DFLAG)
14744             {
14745               op = get32 ();
14746               mask = 0xffffffff;
14747             }
14748           else
14749             {
14750               op = get16 ();
14751               mask = 0xfffff;
14752             }
14753           used_prefixes |= (prefixes & PREFIX_DATA);
14754         }
14755       break;
14756     case w_mode:
14757       mask = 0xfffff;
14758       op = get16 ();
14759       break;
14760     case const_1_mode:
14761       if (intel_syntax)
14762         oappend ("1");
14763       return;
14764     default:
14765       oappend (INTERNAL_DISASSEMBLER_ERROR);
14766       return;
14767     }
14768
14769   op &= mask;
14770   scratchbuf[0] = '$';
14771   print_operand_value (scratchbuf + 1, 1, op);
14772   oappend_maybe_intel (scratchbuf);
14773   scratchbuf[0] = '\0';
14774 }
14775
14776 static void
14777 OP_I64 (int bytemode, int sizeflag)
14778 {
14779   bfd_signed_vma op;
14780   bfd_signed_vma mask = -1;
14781
14782   if (address_mode != mode_64bit)
14783     {
14784       OP_I (bytemode, sizeflag);
14785       return;
14786     }
14787
14788   switch (bytemode)
14789     {
14790     case b_mode:
14791       FETCH_DATA (the_info, codep + 1);
14792       op = *codep++;
14793       mask = 0xff;
14794       break;
14795     case v_mode:
14796       USED_REX (REX_W);
14797       if (rex & REX_W)
14798         op = get64 ();
14799       else
14800         {
14801           if (sizeflag & DFLAG)
14802             {
14803               op = get32 ();
14804               mask = 0xffffffff;
14805             }
14806           else
14807             {
14808               op = get16 ();
14809               mask = 0xfffff;
14810             }
14811           used_prefixes |= (prefixes & PREFIX_DATA);
14812         }
14813       break;
14814     case w_mode:
14815       mask = 0xfffff;
14816       op = get16 ();
14817       break;
14818     default:
14819       oappend (INTERNAL_DISASSEMBLER_ERROR);
14820       return;
14821     }
14822
14823   op &= mask;
14824   scratchbuf[0] = '$';
14825   print_operand_value (scratchbuf + 1, 1, op);
14826   oappend_maybe_intel (scratchbuf);
14827   scratchbuf[0] = '\0';
14828 }
14829
14830 static void
14831 OP_sI (int bytemode, int sizeflag)
14832 {
14833   bfd_signed_vma op;
14834
14835   switch (bytemode)
14836     {
14837     case b_mode:
14838     case b_T_mode:
14839       FETCH_DATA (the_info, codep + 1);
14840       op = *codep++;
14841       if ((op & 0x80) != 0)
14842         op -= 0x100;
14843       if (bytemode == b_T_mode)
14844         {
14845           if (address_mode != mode_64bit
14846               || !((sizeflag & DFLAG) || (rex & REX_W)))
14847             {
14848               /* The operand-size prefix is overridden by a REX prefix.  */
14849               if ((sizeflag & DFLAG) || (rex & REX_W))
14850                 op &= 0xffffffff;
14851               else
14852                 op &= 0xffff;
14853           }
14854         }
14855       else
14856         {
14857           if (!(rex & REX_W))
14858             {
14859               if (sizeflag & DFLAG)
14860                 op &= 0xffffffff;
14861               else
14862                 op &= 0xffff;
14863             }
14864         }
14865       break;
14866     case v_mode:
14867       /* The operand-size prefix is overridden by a REX prefix.  */
14868       if ((sizeflag & DFLAG) || (rex & REX_W))
14869         op = get32s ();
14870       else
14871         op = get16 ();
14872       break;
14873     default:
14874       oappend (INTERNAL_DISASSEMBLER_ERROR);
14875       return;
14876     }
14877
14878   scratchbuf[0] = '$';
14879   print_operand_value (scratchbuf + 1, 1, op);
14880   oappend_maybe_intel (scratchbuf);
14881 }
14882
14883 static void
14884 OP_J (int bytemode, int sizeflag)
14885 {
14886   bfd_vma disp;
14887   bfd_vma mask = -1;
14888   bfd_vma segment = 0;
14889
14890   switch (bytemode)
14891     {
14892     case b_mode:
14893       FETCH_DATA (the_info, codep + 1);
14894       disp = *codep++;
14895       if ((disp & 0x80) != 0)
14896         disp -= 0x100;
14897       break;
14898     case v_mode:
14899       if (isa64 == amd64)
14900         USED_REX (REX_W);
14901       if ((sizeflag & DFLAG)
14902           || (address_mode == mode_64bit
14903               && (isa64 != amd64 || (rex & REX_W))))
14904         disp = get32s ();
14905       else
14906         {
14907           disp = get16 ();
14908           if ((disp & 0x8000) != 0)
14909             disp -= 0x10000;
14910           /* In 16bit mode, address is wrapped around at 64k within
14911              the same segment.  Otherwise, a data16 prefix on a jump
14912              instruction means that the pc is masked to 16 bits after
14913              the displacement is added!  */
14914           mask = 0xffff;
14915           if ((prefixes & PREFIX_DATA) == 0)
14916             segment = ((start_pc + (codep - start_codep))
14917                        & ~((bfd_vma) 0xffff));
14918         }
14919       if (address_mode != mode_64bit
14920           || (isa64 == amd64 && !(rex & REX_W)))
14921         used_prefixes |= (prefixes & PREFIX_DATA);
14922       break;
14923     default:
14924       oappend (INTERNAL_DISASSEMBLER_ERROR);
14925       return;
14926     }
14927   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14928   set_op (disp, 0);
14929   print_operand_value (scratchbuf, 1, disp);
14930   oappend (scratchbuf);
14931 }
14932
14933 static void
14934 OP_SEG (int bytemode, int sizeflag)
14935 {
14936   if (bytemode == w_mode)
14937     oappend (names_seg[modrm.reg]);
14938   else
14939     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14940 }
14941
14942 static void
14943 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14944 {
14945   int seg, offset;
14946
14947   if (sizeflag & DFLAG)
14948     {
14949       offset = get32 ();
14950       seg = get16 ();
14951     }
14952   else
14953     {
14954       offset = get16 ();
14955       seg = get16 ();
14956     }
14957   used_prefixes |= (prefixes & PREFIX_DATA);
14958   if (intel_syntax)
14959     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14960   else
14961     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14962   oappend (scratchbuf);
14963 }
14964
14965 static void
14966 OP_OFF (int bytemode, int sizeflag)
14967 {
14968   bfd_vma off;
14969
14970   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14971     intel_operand_size (bytemode, sizeflag);
14972   append_seg ();
14973
14974   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14975     off = get32 ();
14976   else
14977     off = get16 ();
14978
14979   if (intel_syntax)
14980     {
14981       if (!active_seg_prefix)
14982         {
14983           oappend (names_seg[ds_reg - es_reg]);
14984           oappend (":");
14985         }
14986     }
14987   print_operand_value (scratchbuf, 1, off);
14988   oappend (scratchbuf);
14989 }
14990
14991 static void
14992 OP_OFF64 (int bytemode, int sizeflag)
14993 {
14994   bfd_vma off;
14995
14996   if (address_mode != mode_64bit
14997       || (prefixes & PREFIX_ADDR))
14998     {
14999       OP_OFF (bytemode, sizeflag);
15000       return;
15001     }
15002
15003   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15004     intel_operand_size (bytemode, sizeflag);
15005   append_seg ();
15006
15007   off = get64 ();
15008
15009   if (intel_syntax)
15010     {
15011       if (!active_seg_prefix)
15012         {
15013           oappend (names_seg[ds_reg - es_reg]);
15014           oappend (":");
15015         }
15016     }
15017   print_operand_value (scratchbuf, 1, off);
15018   oappend (scratchbuf);
15019 }
15020
15021 static void
15022 ptr_reg (int code, int sizeflag)
15023 {
15024   const char *s;
15025
15026   *obufp++ = open_char;
15027   used_prefixes |= (prefixes & PREFIX_ADDR);
15028   if (address_mode == mode_64bit)
15029     {
15030       if (!(sizeflag & AFLAG))
15031         s = names32[code - eAX_reg];
15032       else
15033         s = names64[code - eAX_reg];
15034     }
15035   else if (sizeflag & AFLAG)
15036     s = names32[code - eAX_reg];
15037   else
15038     s = names16[code - eAX_reg];
15039   oappend (s);
15040   *obufp++ = close_char;
15041   *obufp = 0;
15042 }
15043
15044 static void
15045 OP_ESreg (int code, int sizeflag)
15046 {
15047   if (intel_syntax)
15048     {
15049       switch (codep[-1])
15050         {
15051         case 0x6d:      /* insw/insl */
15052           intel_operand_size (z_mode, sizeflag);
15053           break;
15054         case 0xa5:      /* movsw/movsl/movsq */
15055         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15056         case 0xab:      /* stosw/stosl */
15057         case 0xaf:      /* scasw/scasl */
15058           intel_operand_size (v_mode, sizeflag);
15059           break;
15060         default:
15061           intel_operand_size (b_mode, sizeflag);
15062         }
15063     }
15064   oappend_maybe_intel ("%es:");
15065   ptr_reg (code, sizeflag);
15066 }
15067
15068 static void
15069 OP_DSreg (int code, int sizeflag)
15070 {
15071   if (intel_syntax)
15072     {
15073       switch (codep[-1])
15074         {
15075         case 0x6f:      /* outsw/outsl */
15076           intel_operand_size (z_mode, sizeflag);
15077           break;
15078         case 0xa5:      /* movsw/movsl/movsq */
15079         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15080         case 0xad:      /* lodsw/lodsl/lodsq */
15081           intel_operand_size (v_mode, sizeflag);
15082           break;
15083         default:
15084           intel_operand_size (b_mode, sizeflag);
15085         }
15086     }
15087   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15088      default segment register DS is printed.  */
15089   if (!active_seg_prefix)
15090     active_seg_prefix = PREFIX_DS;
15091   append_seg ();
15092   ptr_reg (code, sizeflag);
15093 }
15094
15095 static void
15096 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15097 {
15098   int add;
15099   if (rex & REX_R)
15100     {
15101       USED_REX (REX_R);
15102       add = 8;
15103     }
15104   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15105     {
15106       all_prefixes[last_lock_prefix] = 0;
15107       used_prefixes |= PREFIX_LOCK;
15108       add = 8;
15109     }
15110   else
15111     add = 0;
15112   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15113   oappend_maybe_intel (scratchbuf);
15114 }
15115
15116 static void
15117 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15118 {
15119   int add;
15120   USED_REX (REX_R);
15121   if (rex & REX_R)
15122     add = 8;
15123   else
15124     add = 0;
15125   if (intel_syntax)
15126     sprintf (scratchbuf, "db%d", modrm.reg + add);
15127   else
15128     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15129   oappend (scratchbuf);
15130 }
15131
15132 static void
15133 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15134 {
15135   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15136   oappend_maybe_intel (scratchbuf);
15137 }
15138
15139 static void
15140 OP_R (int bytemode, int sizeflag)
15141 {
15142   /* Skip mod/rm byte.  */
15143   MODRM_CHECK;
15144   codep++;
15145   OP_E_register (bytemode, sizeflag);
15146 }
15147
15148 static void
15149 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15150 {
15151   int reg = modrm.reg;
15152   const char **names;
15153
15154   used_prefixes |= (prefixes & PREFIX_DATA);
15155   if (prefixes & PREFIX_DATA)
15156     {
15157       names = names_xmm;
15158       USED_REX (REX_R);
15159       if (rex & REX_R)
15160         reg += 8;
15161     }
15162   else
15163     names = names_mm;
15164   oappend (names[reg]);
15165 }
15166
15167 static void
15168 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15169 {
15170   int reg = modrm.reg;
15171   const char **names;
15172
15173   USED_REX (REX_R);
15174   if (rex & REX_R)
15175     reg += 8;
15176   if (vex.evex)
15177     {
15178       if (!vex.r)
15179         reg += 16;
15180     }
15181
15182   if (need_vex
15183       && bytemode != xmm_mode
15184       && bytemode != xmmq_mode
15185       && bytemode != evex_half_bcst_xmmq_mode
15186       && bytemode != ymm_mode
15187       && bytemode != scalar_mode)
15188     {
15189       switch (vex.length)
15190         {
15191         case 128:
15192           names = names_xmm;
15193           break;
15194         case 256:
15195           if (vex.w
15196               || (bytemode != vex_vsib_q_w_dq_mode
15197                   && bytemode != vex_vsib_q_w_d_mode))
15198             names = names_ymm;
15199           else
15200             names = names_xmm;
15201           break;
15202         case 512:
15203           names = names_zmm;
15204           break;
15205         default:
15206           abort ();
15207         }
15208     }
15209   else if (bytemode == xmmq_mode
15210            || bytemode == evex_half_bcst_xmmq_mode)
15211     {
15212       switch (vex.length)
15213         {
15214         case 128:
15215         case 256:
15216           names = names_xmm;
15217           break;
15218         case 512:
15219           names = names_ymm;
15220           break;
15221         default:
15222           abort ();
15223         }
15224     }
15225   else if (bytemode == ymm_mode)
15226     names = names_ymm;
15227   else
15228     names = names_xmm;
15229   oappend (names[reg]);
15230 }
15231
15232 static void
15233 OP_EM (int bytemode, int sizeflag)
15234 {
15235   int reg;
15236   const char **names;
15237
15238   if (modrm.mod != 3)
15239     {
15240       if (intel_syntax
15241           && (bytemode == v_mode || bytemode == v_swap_mode))
15242         {
15243           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15244           used_prefixes |= (prefixes & PREFIX_DATA);
15245         }
15246       OP_E (bytemode, sizeflag);
15247       return;
15248     }
15249
15250   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15251     swap_operand ();
15252
15253   /* Skip mod/rm byte.  */
15254   MODRM_CHECK;
15255   codep++;
15256   used_prefixes |= (prefixes & PREFIX_DATA);
15257   reg = modrm.rm;
15258   if (prefixes & PREFIX_DATA)
15259     {
15260       names = names_xmm;
15261       USED_REX (REX_B);
15262       if (rex & REX_B)
15263         reg += 8;
15264     }
15265   else
15266     names = names_mm;
15267   oappend (names[reg]);
15268 }
15269
15270 /* cvt* are the only instructions in sse2 which have
15271    both SSE and MMX operands and also have 0x66 prefix
15272    in their opcode. 0x66 was originally used to differentiate
15273    between SSE and MMX instruction(operands). So we have to handle the
15274    cvt* separately using OP_EMC and OP_MXC */
15275 static void
15276 OP_EMC (int bytemode, int sizeflag)
15277 {
15278   if (modrm.mod != 3)
15279     {
15280       if (intel_syntax && bytemode == v_mode)
15281         {
15282           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15283           used_prefixes |= (prefixes & PREFIX_DATA);
15284         }
15285       OP_E (bytemode, sizeflag);
15286       return;
15287     }
15288
15289   /* Skip mod/rm byte.  */
15290   MODRM_CHECK;
15291   codep++;
15292   used_prefixes |= (prefixes & PREFIX_DATA);
15293   oappend (names_mm[modrm.rm]);
15294 }
15295
15296 static void
15297 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15298 {
15299   used_prefixes |= (prefixes & PREFIX_DATA);
15300   oappend (names_mm[modrm.reg]);
15301 }
15302
15303 static void
15304 OP_EX (int bytemode, int sizeflag)
15305 {
15306   int reg;
15307   const char **names;
15308
15309   /* Skip mod/rm byte.  */
15310   MODRM_CHECK;
15311   codep++;
15312
15313   if (modrm.mod != 3)
15314     {
15315       OP_E_memory (bytemode, sizeflag);
15316       return;
15317     }
15318
15319   reg = modrm.rm;
15320   USED_REX (REX_B);
15321   if (rex & REX_B)
15322     reg += 8;
15323   if (vex.evex)
15324     {
15325       USED_REX (REX_X);
15326       if ((rex & REX_X))
15327         reg += 16;
15328     }
15329
15330   if ((sizeflag & SUFFIX_ALWAYS)
15331       && (bytemode == x_swap_mode
15332           || bytemode == d_swap_mode
15333           || bytemode == d_scalar_swap_mode
15334           || bytemode == q_swap_mode
15335           || bytemode == q_scalar_swap_mode))
15336     swap_operand ();
15337
15338   if (need_vex
15339       && bytemode != xmm_mode
15340       && bytemode != xmmdw_mode
15341       && bytemode != xmmqd_mode
15342       && bytemode != xmm_mb_mode
15343       && bytemode != xmm_mw_mode
15344       && bytemode != xmm_md_mode
15345       && bytemode != xmm_mq_mode
15346       && bytemode != xmm_mdq_mode
15347       && bytemode != xmmq_mode
15348       && bytemode != evex_half_bcst_xmmq_mode
15349       && bytemode != ymm_mode
15350       && bytemode != d_scalar_mode
15351       && bytemode != d_scalar_swap_mode
15352       && bytemode != q_scalar_mode
15353       && bytemode != q_scalar_swap_mode
15354       && bytemode != vex_scalar_w_dq_mode)
15355     {
15356       switch (vex.length)
15357         {
15358         case 128:
15359           names = names_xmm;
15360           break;
15361         case 256:
15362           names = names_ymm;
15363           break;
15364         case 512:
15365           names = names_zmm;
15366           break;
15367         default:
15368           abort ();
15369         }
15370     }
15371   else if (bytemode == xmmq_mode
15372            || bytemode == evex_half_bcst_xmmq_mode)
15373     {
15374       switch (vex.length)
15375         {
15376         case 128:
15377         case 256:
15378           names = names_xmm;
15379           break;
15380         case 512:
15381           names = names_ymm;
15382           break;
15383         default:
15384           abort ();
15385         }
15386     }
15387   else if (bytemode == ymm_mode)
15388     names = names_ymm;
15389   else
15390     names = names_xmm;
15391   oappend (names[reg]);
15392 }
15393
15394 static void
15395 OP_MS (int bytemode, int sizeflag)
15396 {
15397   if (modrm.mod == 3)
15398     OP_EM (bytemode, sizeflag);
15399   else
15400     BadOp ();
15401 }
15402
15403 static void
15404 OP_XS (int bytemode, int sizeflag)
15405 {
15406   if (modrm.mod == 3)
15407     OP_EX (bytemode, sizeflag);
15408   else
15409     BadOp ();
15410 }
15411
15412 static void
15413 OP_M (int bytemode, int sizeflag)
15414 {
15415   if (modrm.mod == 3)
15416     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15417     BadOp ();
15418   else
15419     OP_E (bytemode, sizeflag);
15420 }
15421
15422 static void
15423 OP_0f07 (int bytemode, int sizeflag)
15424 {
15425   if (modrm.mod != 3 || modrm.rm != 0)
15426     BadOp ();
15427   else
15428     OP_E (bytemode, sizeflag);
15429 }
15430
15431 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15432    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15433
15434 static void
15435 NOP_Fixup1 (int bytemode, int sizeflag)
15436 {
15437   if ((prefixes & PREFIX_DATA) != 0
15438       || (rex != 0
15439           && rex != 0x48
15440           && address_mode == mode_64bit))
15441     OP_REG (bytemode, sizeflag);
15442   else
15443     strcpy (obuf, "nop");
15444 }
15445
15446 static void
15447 NOP_Fixup2 (int bytemode, int sizeflag)
15448 {
15449   if ((prefixes & PREFIX_DATA) != 0
15450       || (rex != 0
15451           && rex != 0x48
15452           && address_mode == mode_64bit))
15453     OP_IMREG (bytemode, sizeflag);
15454 }
15455
15456 static const char *const Suffix3DNow[] = {
15457 /* 00 */        NULL,           NULL,           NULL,           NULL,
15458 /* 04 */        NULL,           NULL,           NULL,           NULL,
15459 /* 08 */        NULL,           NULL,           NULL,           NULL,
15460 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15461 /* 10 */        NULL,           NULL,           NULL,           NULL,
15462 /* 14 */        NULL,           NULL,           NULL,           NULL,
15463 /* 18 */        NULL,           NULL,           NULL,           NULL,
15464 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15465 /* 20 */        NULL,           NULL,           NULL,           NULL,
15466 /* 24 */        NULL,           NULL,           NULL,           NULL,
15467 /* 28 */        NULL,           NULL,           NULL,           NULL,
15468 /* 2C */        NULL,           NULL,           NULL,           NULL,
15469 /* 30 */        NULL,           NULL,           NULL,           NULL,
15470 /* 34 */        NULL,           NULL,           NULL,           NULL,
15471 /* 38 */        NULL,           NULL,           NULL,           NULL,
15472 /* 3C */        NULL,           NULL,           NULL,           NULL,
15473 /* 40 */        NULL,           NULL,           NULL,           NULL,
15474 /* 44 */        NULL,           NULL,           NULL,           NULL,
15475 /* 48 */        NULL,           NULL,           NULL,           NULL,
15476 /* 4C */        NULL,           NULL,           NULL,           NULL,
15477 /* 50 */        NULL,           NULL,           NULL,           NULL,
15478 /* 54 */        NULL,           NULL,           NULL,           NULL,
15479 /* 58 */        NULL,           NULL,           NULL,           NULL,
15480 /* 5C */        NULL,           NULL,           NULL,           NULL,
15481 /* 60 */        NULL,           NULL,           NULL,           NULL,
15482 /* 64 */        NULL,           NULL,           NULL,           NULL,
15483 /* 68 */        NULL,           NULL,           NULL,           NULL,
15484 /* 6C */        NULL,           NULL,           NULL,           NULL,
15485 /* 70 */        NULL,           NULL,           NULL,           NULL,
15486 /* 74 */        NULL,           NULL,           NULL,           NULL,
15487 /* 78 */        NULL,           NULL,           NULL,           NULL,
15488 /* 7C */        NULL,           NULL,           NULL,           NULL,
15489 /* 80 */        NULL,           NULL,           NULL,           NULL,
15490 /* 84 */        NULL,           NULL,           NULL,           NULL,
15491 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15492 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15493 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15494 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15495 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15496 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15497 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15498 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15499 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15500 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15501 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15502 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15503 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15504 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15505 /* C0 */        NULL,           NULL,           NULL,           NULL,
15506 /* C4 */        NULL,           NULL,           NULL,           NULL,
15507 /* C8 */        NULL,           NULL,           NULL,           NULL,
15508 /* CC */        NULL,           NULL,           NULL,           NULL,
15509 /* D0 */        NULL,           NULL,           NULL,           NULL,
15510 /* D4 */        NULL,           NULL,           NULL,           NULL,
15511 /* D8 */        NULL,           NULL,           NULL,           NULL,
15512 /* DC */        NULL,           NULL,           NULL,           NULL,
15513 /* E0 */        NULL,           NULL,           NULL,           NULL,
15514 /* E4 */        NULL,           NULL,           NULL,           NULL,
15515 /* E8 */        NULL,           NULL,           NULL,           NULL,
15516 /* EC */        NULL,           NULL,           NULL,           NULL,
15517 /* F0 */        NULL,           NULL,           NULL,           NULL,
15518 /* F4 */        NULL,           NULL,           NULL,           NULL,
15519 /* F8 */        NULL,           NULL,           NULL,           NULL,
15520 /* FC */        NULL,           NULL,           NULL,           NULL,
15521 };
15522
15523 static void
15524 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15525 {
15526   const char *mnemonic;
15527
15528   FETCH_DATA (the_info, codep + 1);
15529   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15530      place where an 8-bit immediate would normally go.  ie. the last
15531      byte of the instruction.  */
15532   obufp = mnemonicendp;
15533   mnemonic = Suffix3DNow[*codep++ & 0xff];
15534   if (mnemonic)
15535     oappend (mnemonic);
15536   else
15537     {
15538       /* Since a variable sized modrm/sib chunk is between the start
15539          of the opcode (0x0f0f) and the opcode suffix, we need to do
15540          all the modrm processing first, and don't know until now that
15541          we have a bad opcode.  This necessitates some cleaning up.  */
15542       op_out[0][0] = '\0';
15543       op_out[1][0] = '\0';
15544       BadOp ();
15545     }
15546   mnemonicendp = obufp;
15547 }
15548
15549 static struct op simd_cmp_op[] =
15550 {
15551   { STRING_COMMA_LEN ("eq") },
15552   { STRING_COMMA_LEN ("lt") },
15553   { STRING_COMMA_LEN ("le") },
15554   { STRING_COMMA_LEN ("unord") },
15555   { STRING_COMMA_LEN ("neq") },
15556   { STRING_COMMA_LEN ("nlt") },
15557   { STRING_COMMA_LEN ("nle") },
15558   { STRING_COMMA_LEN ("ord") }
15559 };
15560
15561 static void
15562 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15563 {
15564   unsigned int cmp_type;
15565
15566   FETCH_DATA (the_info, codep + 1);
15567   cmp_type = *codep++ & 0xff;
15568   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15569     {
15570       char suffix [3];
15571       char *p = mnemonicendp - 2;
15572       suffix[0] = p[0];
15573       suffix[1] = p[1];
15574       suffix[2] = '\0';
15575       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15576       mnemonicendp += simd_cmp_op[cmp_type].len;
15577     }
15578   else
15579     {
15580       /* We have a reserved extension byte.  Output it directly.  */
15581       scratchbuf[0] = '$';
15582       print_operand_value (scratchbuf + 1, 1, cmp_type);
15583       oappend_maybe_intel (scratchbuf);
15584       scratchbuf[0] = '\0';
15585     }
15586 }
15587
15588 static void
15589 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15590           int sizeflag ATTRIBUTE_UNUSED)
15591 {
15592   /* mwaitx %eax,%ecx,%ebx */
15593   if (!intel_syntax)
15594     {
15595       const char **names = (address_mode == mode_64bit
15596                             ? names64 : names32);
15597       strcpy (op_out[0], names[0]);
15598       strcpy (op_out[1], names[1]);
15599       strcpy (op_out[2], names[3]);
15600       two_source_ops = 1;
15601     }
15602   /* Skip mod/rm byte.  */
15603   MODRM_CHECK;
15604   codep++;
15605 }
15606
15607 static void
15608 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15609           int sizeflag ATTRIBUTE_UNUSED)
15610 {
15611   /* mwait %eax,%ecx  */
15612   if (!intel_syntax)
15613     {
15614       const char **names = (address_mode == mode_64bit
15615                             ? names64 : names32);
15616       strcpy (op_out[0], names[0]);
15617       strcpy (op_out[1], names[1]);
15618       two_source_ops = 1;
15619     }
15620   /* Skip mod/rm byte.  */
15621   MODRM_CHECK;
15622   codep++;
15623 }
15624
15625 static void
15626 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15627             int sizeflag ATTRIBUTE_UNUSED)
15628 {
15629   /* monitor %eax,%ecx,%edx"  */
15630   if (!intel_syntax)
15631     {
15632       const char **op1_names;
15633       const char **names = (address_mode == mode_64bit
15634                             ? names64 : names32);
15635
15636       if (!(prefixes & PREFIX_ADDR))
15637         op1_names = (address_mode == mode_16bit
15638                      ? names16 : names);
15639       else
15640         {
15641           /* Remove "addr16/addr32".  */
15642           all_prefixes[last_addr_prefix] = 0;
15643           op1_names = (address_mode != mode_32bit
15644                        ? names32 : names16);
15645           used_prefixes |= PREFIX_ADDR;
15646         }
15647       strcpy (op_out[0], op1_names[0]);
15648       strcpy (op_out[1], names[1]);
15649       strcpy (op_out[2], names[2]);
15650       two_source_ops = 1;
15651     }
15652   /* Skip mod/rm byte.  */
15653   MODRM_CHECK;
15654   codep++;
15655 }
15656
15657 static void
15658 BadOp (void)
15659 {
15660   /* Throw away prefixes and 1st. opcode byte.  */
15661   codep = insn_codep + 1;
15662   oappend ("(bad)");
15663 }
15664
15665 static void
15666 REP_Fixup (int bytemode, int sizeflag)
15667 {
15668   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15669      lods and stos.  */
15670   if (prefixes & PREFIX_REPZ)
15671     all_prefixes[last_repz_prefix] = REP_PREFIX;
15672
15673   switch (bytemode)
15674     {
15675     case al_reg:
15676     case eAX_reg:
15677     case indir_dx_reg:
15678       OP_IMREG (bytemode, sizeflag);
15679       break;
15680     case eDI_reg:
15681       OP_ESreg (bytemode, sizeflag);
15682       break;
15683     case eSI_reg:
15684       OP_DSreg (bytemode, sizeflag);
15685       break;
15686     default:
15687       abort ();
15688       break;
15689     }
15690 }
15691
15692 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15693    "bnd".  */
15694
15695 static void
15696 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15697 {
15698   if (prefixes & PREFIX_REPNZ)
15699     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15700 }
15701
15702 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15703    "notrack".  */
15704
15705 static void
15706 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15707                int sizeflag ATTRIBUTE_UNUSED)
15708 {
15709   if (active_seg_prefix == PREFIX_DS
15710       && (address_mode != mode_64bit || last_data_prefix < 0))
15711     {
15712       /* NOTRACK prefix is only valid on indirect branch instructions.
15713          NB: DATA prefix is unsupported for Intel64.  */
15714       active_seg_prefix = 0;
15715       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15716     }
15717 }
15718
15719 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15720    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15721  */
15722
15723 static void
15724 HLE_Fixup1 (int bytemode, int sizeflag)
15725 {
15726   if (modrm.mod != 3
15727       && (prefixes & PREFIX_LOCK) != 0)
15728     {
15729       if (prefixes & PREFIX_REPZ)
15730         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15731       if (prefixes & PREFIX_REPNZ)
15732         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15733     }
15734
15735   OP_E (bytemode, sizeflag);
15736 }
15737
15738 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15739    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15740  */
15741
15742 static void
15743 HLE_Fixup2 (int bytemode, int sizeflag)
15744 {
15745   if (modrm.mod != 3)
15746     {
15747       if (prefixes & PREFIX_REPZ)
15748         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15749       if (prefixes & PREFIX_REPNZ)
15750         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15751     }
15752
15753   OP_E (bytemode, sizeflag);
15754 }
15755
15756 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15757    "xrelease" for memory operand.  No check for LOCK prefix.   */
15758
15759 static void
15760 HLE_Fixup3 (int bytemode, int sizeflag)
15761 {
15762   if (modrm.mod != 3
15763       && last_repz_prefix > last_repnz_prefix
15764       && (prefixes & PREFIX_REPZ) != 0)
15765     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15766
15767   OP_E (bytemode, sizeflag);
15768 }
15769
15770 static void
15771 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15772 {
15773   USED_REX (REX_W);
15774   if (rex & REX_W)
15775     {
15776       /* Change cmpxchg8b to cmpxchg16b.  */
15777       char *p = mnemonicendp - 2;
15778       mnemonicendp = stpcpy (p, "16b");
15779       bytemode = o_mode;
15780     }
15781   else if ((prefixes & PREFIX_LOCK) != 0)
15782     {
15783       if (prefixes & PREFIX_REPZ)
15784         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15785       if (prefixes & PREFIX_REPNZ)
15786         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15787     }
15788
15789   OP_M (bytemode, sizeflag);
15790 }
15791
15792 static void
15793 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15794 {
15795   const char **names;
15796
15797   if (need_vex)
15798     {
15799       switch (vex.length)
15800         {
15801         case 128:
15802           names = names_xmm;
15803           break;
15804         case 256:
15805           names = names_ymm;
15806           break;
15807         default:
15808           abort ();
15809         }
15810     }
15811   else
15812     names = names_xmm;
15813   oappend (names[reg]);
15814 }
15815
15816 static void
15817 CRC32_Fixup (int bytemode, int sizeflag)
15818 {
15819   /* Add proper suffix to "crc32".  */
15820   char *p = mnemonicendp;
15821
15822   switch (bytemode)
15823     {
15824     case b_mode:
15825       if (intel_syntax)
15826         goto skip;
15827
15828       *p++ = 'b';
15829       break;
15830     case v_mode:
15831       if (intel_syntax)
15832         goto skip;
15833
15834       USED_REX (REX_W);
15835       if (rex & REX_W)
15836         *p++ = 'q';
15837       else
15838         {
15839           if (sizeflag & DFLAG)
15840             *p++ = 'l';
15841           else
15842             *p++ = 'w';
15843           used_prefixes |= (prefixes & PREFIX_DATA);
15844         }
15845       break;
15846     default:
15847       oappend (INTERNAL_DISASSEMBLER_ERROR);
15848       break;
15849     }
15850   mnemonicendp = p;
15851   *p = '\0';
15852
15853 skip:
15854   if (modrm.mod == 3)
15855     {
15856       int add;
15857
15858       /* Skip mod/rm byte.  */
15859       MODRM_CHECK;
15860       codep++;
15861
15862       USED_REX (REX_B);
15863       add = (rex & REX_B) ? 8 : 0;
15864       if (bytemode == b_mode)
15865         {
15866           USED_REX (0);
15867           if (rex)
15868             oappend (names8rex[modrm.rm + add]);
15869           else
15870             oappend (names8[modrm.rm + add]);
15871         }
15872       else
15873         {
15874           USED_REX (REX_W);
15875           if (rex & REX_W)
15876             oappend (names64[modrm.rm + add]);
15877           else if ((prefixes & PREFIX_DATA))
15878             oappend (names16[modrm.rm + add]);
15879           else
15880             oappend (names32[modrm.rm + add]);
15881         }
15882     }
15883   else
15884     OP_E (bytemode, sizeflag);
15885 }
15886
15887 static void
15888 FXSAVE_Fixup (int bytemode, int sizeflag)
15889 {
15890   /* Add proper suffix to "fxsave" and "fxrstor".  */
15891   USED_REX (REX_W);
15892   if (rex & REX_W)
15893     {
15894       char *p = mnemonicendp;
15895       *p++ = '6';
15896       *p++ = '4';
15897       *p = '\0';
15898       mnemonicendp = p;
15899     }
15900   OP_M (bytemode, sizeflag);
15901 }
15902
15903 static void
15904 PCMPESTR_Fixup (int bytemode, int sizeflag)
15905 {
15906   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15907   if (!intel_syntax)
15908     {
15909       char *p = mnemonicendp;
15910
15911       USED_REX (REX_W);
15912       if (rex & REX_W)
15913         *p++ = 'q';
15914       else if (sizeflag & SUFFIX_ALWAYS)
15915         *p++ = 'l';
15916
15917       *p = '\0';
15918       mnemonicendp = p;
15919     }
15920
15921   OP_EX (bytemode, sizeflag);
15922 }
15923
15924 /* Display the destination register operand for instructions with
15925    VEX. */
15926
15927 static void
15928 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15929 {
15930   int reg;
15931   const char **names;
15932
15933   if (!need_vex)
15934     abort ();
15935
15936   if (!need_vex_reg)
15937     return;
15938
15939   reg = vex.register_specifier;
15940   vex.register_specifier = 0;
15941   if (address_mode != mode_64bit)
15942     reg &= 7;
15943   else if (vex.evex && !vex.v)
15944     reg += 16;
15945
15946   if (bytemode == vex_scalar_mode)
15947     {
15948       oappend (names_xmm[reg]);
15949       return;
15950     }
15951
15952   switch (vex.length)
15953     {
15954     case 128:
15955       switch (bytemode)
15956         {
15957         case vex_mode:
15958         case vex128_mode:
15959         case vex_vsib_q_w_dq_mode:
15960         case vex_vsib_q_w_d_mode:
15961           names = names_xmm;
15962           break;
15963         case dq_mode:
15964           if (rex & REX_W)
15965             names = names64;
15966           else
15967             names = names32;
15968           break;
15969         case mask_bd_mode:
15970         case mask_mode:
15971           if (reg > 0x7)
15972             {
15973               oappend ("(bad)");
15974               return;
15975             }
15976           names = names_mask;
15977           break;
15978         default:
15979           abort ();
15980           return;
15981         }
15982       break;
15983     case 256:
15984       switch (bytemode)
15985         {
15986         case vex_mode:
15987         case vex256_mode:
15988           names = names_ymm;
15989           break;
15990         case vex_vsib_q_w_dq_mode:
15991         case vex_vsib_q_w_d_mode:
15992           names = vex.w ? names_ymm : names_xmm;
15993           break;
15994         case mask_bd_mode:
15995         case mask_mode:
15996           if (reg > 0x7)
15997             {
15998               oappend ("(bad)");
15999               return;
16000             }
16001           names = names_mask;
16002           break;
16003         default:
16004           /* See PR binutils/20893 for a reproducer.  */
16005           oappend ("(bad)");
16006           return;
16007         }
16008       break;
16009     case 512:
16010       names = names_zmm;
16011       break;
16012     default:
16013       abort ();
16014       break;
16015     }
16016   oappend (names[reg]);
16017 }
16018
16019 /* Get the VEX immediate byte without moving codep.  */
16020
16021 static unsigned char
16022 get_vex_imm8 (int sizeflag, int opnum)
16023 {
16024   int bytes_before_imm = 0;
16025
16026   if (modrm.mod != 3)
16027     {
16028       /* There are SIB/displacement bytes.  */
16029       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16030         {
16031           /* 32/64 bit address mode */
16032           int base = modrm.rm;
16033
16034           /* Check SIB byte.  */
16035           if (base == 4)
16036             {
16037               FETCH_DATA (the_info, codep + 1);
16038               base = *codep & 7;
16039               /* When decoding the third source, don't increase
16040                  bytes_before_imm as this has already been incremented
16041                  by one in OP_E_memory while decoding the second
16042                  source operand.  */
16043               if (opnum == 0)
16044                 bytes_before_imm++;
16045             }
16046
16047           /* Don't increase bytes_before_imm when decoding the third source,
16048              it has already been incremented by OP_E_memory while decoding
16049              the second source operand.  */
16050           if (opnum == 0)
16051             {
16052               switch (modrm.mod)
16053                 {
16054                   case 0:
16055                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16056                        SIB == 5, there is a 4 byte displacement.  */
16057                     if (base != 5)
16058                       /* No displacement. */
16059                       break;
16060                     /* Fall through.  */
16061                   case 2:
16062                     /* 4 byte displacement.  */
16063                     bytes_before_imm += 4;
16064                     break;
16065                   case 1:
16066                     /* 1 byte displacement.  */
16067                     bytes_before_imm++;
16068                     break;
16069                 }
16070             }
16071         }
16072       else
16073         {
16074           /* 16 bit address mode */
16075           /* Don't increase bytes_before_imm when decoding the third source,
16076              it has already been incremented by OP_E_memory while decoding
16077              the second source operand.  */
16078           if (opnum == 0)
16079             {
16080               switch (modrm.mod)
16081                 {
16082                 case 0:
16083                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16084                   if (modrm.rm != 6)
16085                     /* No displacement. */
16086                     break;
16087                   /* Fall through.  */
16088                 case 2:
16089                   /* 2 byte displacement.  */
16090                   bytes_before_imm += 2;
16091                   break;
16092                 case 1:
16093                   /* 1 byte displacement: when decoding the third source,
16094                      don't increase bytes_before_imm as this has already
16095                      been incremented by one in OP_E_memory while decoding
16096                      the second source operand.  */
16097                   if (opnum == 0)
16098                     bytes_before_imm++;
16099
16100                   break;
16101                 }
16102             }
16103         }
16104     }
16105
16106   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16107   return codep [bytes_before_imm];
16108 }
16109
16110 static void
16111 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16112 {
16113   const char **names;
16114
16115   if (reg == -1 && modrm.mod != 3)
16116     {
16117       OP_E_memory (bytemode, sizeflag);
16118       return;
16119     }
16120   else
16121     {
16122       if (reg == -1)
16123         {
16124           reg = modrm.rm;
16125           USED_REX (REX_B);
16126           if (rex & REX_B)
16127             reg += 8;
16128         }
16129       if (address_mode != mode_64bit)
16130         reg &= 7;
16131     }
16132
16133   switch (vex.length)
16134     {
16135     case 128:
16136       names = names_xmm;
16137       break;
16138     case 256:
16139       names = names_ymm;
16140       break;
16141     default:
16142       abort ();
16143     }
16144   oappend (names[reg]);
16145 }
16146
16147 static void
16148 OP_EX_VexImmW (int bytemode, int sizeflag)
16149 {
16150   int reg = -1;
16151   static unsigned char vex_imm8;
16152
16153   if (vex_w_done == 0)
16154     {
16155       vex_w_done = 1;
16156
16157       /* Skip mod/rm byte.  */
16158       MODRM_CHECK;
16159       codep++;
16160
16161       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16162
16163       if (vex.w)
16164           reg = vex_imm8 >> 4;
16165
16166       OP_EX_VexReg (bytemode, sizeflag, reg);
16167     }
16168   else if (vex_w_done == 1)
16169     {
16170       vex_w_done = 2;
16171
16172       if (!vex.w)
16173           reg = vex_imm8 >> 4;
16174
16175       OP_EX_VexReg (bytemode, sizeflag, reg);
16176     }
16177   else
16178     {
16179       /* Output the imm8 directly.  */
16180       scratchbuf[0] = '$';
16181       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16182       oappend_maybe_intel (scratchbuf);
16183       scratchbuf[0] = '\0';
16184       codep++;
16185     }
16186 }
16187
16188 static void
16189 OP_Vex_2src (int bytemode, int sizeflag)
16190 {
16191   if (modrm.mod == 3)
16192     {
16193       int reg = modrm.rm;
16194       USED_REX (REX_B);
16195       if (rex & REX_B)
16196         reg += 8;
16197       oappend (names_xmm[reg]);
16198     }
16199   else
16200     {
16201       if (intel_syntax
16202           && (bytemode == v_mode || bytemode == v_swap_mode))
16203         {
16204           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16205           used_prefixes |= (prefixes & PREFIX_DATA);
16206         }
16207       OP_E (bytemode, sizeflag);
16208     }
16209 }
16210
16211 static void
16212 OP_Vex_2src_1 (int bytemode, int sizeflag)
16213 {
16214   if (modrm.mod == 3)
16215     {
16216       /* Skip mod/rm byte.   */
16217       MODRM_CHECK;
16218       codep++;
16219     }
16220
16221   if (vex.w)
16222     {
16223       unsigned int reg = vex.register_specifier;
16224       vex.register_specifier = 0;
16225
16226       if (address_mode != mode_64bit)
16227         reg &= 7;
16228       oappend (names_xmm[reg]);
16229     }
16230   else
16231     OP_Vex_2src (bytemode, sizeflag);
16232 }
16233
16234 static void
16235 OP_Vex_2src_2 (int bytemode, int sizeflag)
16236 {
16237   if (vex.w)
16238     OP_Vex_2src (bytemode, sizeflag);
16239   else
16240     {
16241       unsigned int reg = vex.register_specifier;
16242       vex.register_specifier = 0;
16243
16244       if (address_mode != mode_64bit)
16245         reg &= 7;
16246       oappend (names_xmm[reg]);
16247     }
16248 }
16249
16250 static void
16251 OP_EX_VexW (int bytemode, int sizeflag)
16252 {
16253   int reg = -1;
16254
16255   if (!vex_w_done)
16256     {
16257       /* Skip mod/rm byte.  */
16258       MODRM_CHECK;
16259       codep++;
16260
16261       if (vex.w)
16262         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16263     }
16264   else
16265     {
16266       if (!vex.w)
16267         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16268     }
16269
16270   OP_EX_VexReg (bytemode, sizeflag, reg);
16271
16272   if (vex_w_done)
16273     codep++;
16274   vex_w_done = 1;
16275 }
16276
16277 static void
16278 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16279 {
16280   int reg;
16281   const char **names;
16282
16283   FETCH_DATA (the_info, codep + 1);
16284   reg = *codep++;
16285
16286   if (bytemode != x_mode)
16287     abort ();
16288
16289   reg >>= 4;
16290   if (address_mode != mode_64bit)
16291     reg &= 7;
16292
16293   switch (vex.length)
16294     {
16295     case 128:
16296       names = names_xmm;
16297       break;
16298     case 256:
16299       names = names_ymm;
16300       break;
16301     default:
16302       abort ();
16303     }
16304   oappend (names[reg]);
16305 }
16306
16307 static void
16308 OP_XMM_VexW (int bytemode, int sizeflag)
16309 {
16310   /* Turn off the REX.W bit since it is used for swapping operands
16311      now.  */
16312   rex &= ~REX_W;
16313   OP_XMM (bytemode, sizeflag);
16314 }
16315
16316 static void
16317 OP_EX_Vex (int bytemode, int sizeflag)
16318 {
16319   if (modrm.mod != 3)
16320     need_vex_reg = 0;
16321   OP_EX (bytemode, sizeflag);
16322 }
16323
16324 static void
16325 OP_XMM_Vex (int bytemode, int sizeflag)
16326 {
16327   if (modrm.mod != 3)
16328     need_vex_reg = 0;
16329   OP_XMM (bytemode, sizeflag);
16330 }
16331
16332 static struct op vex_cmp_op[] =
16333 {
16334   { STRING_COMMA_LEN ("eq") },
16335   { STRING_COMMA_LEN ("lt") },
16336   { STRING_COMMA_LEN ("le") },
16337   { STRING_COMMA_LEN ("unord") },
16338   { STRING_COMMA_LEN ("neq") },
16339   { STRING_COMMA_LEN ("nlt") },
16340   { STRING_COMMA_LEN ("nle") },
16341   { STRING_COMMA_LEN ("ord") },
16342   { STRING_COMMA_LEN ("eq_uq") },
16343   { STRING_COMMA_LEN ("nge") },
16344   { STRING_COMMA_LEN ("ngt") },
16345   { STRING_COMMA_LEN ("false") },
16346   { STRING_COMMA_LEN ("neq_oq") },
16347   { STRING_COMMA_LEN ("ge") },
16348   { STRING_COMMA_LEN ("gt") },
16349   { STRING_COMMA_LEN ("true") },
16350   { STRING_COMMA_LEN ("eq_os") },
16351   { STRING_COMMA_LEN ("lt_oq") },
16352   { STRING_COMMA_LEN ("le_oq") },
16353   { STRING_COMMA_LEN ("unord_s") },
16354   { STRING_COMMA_LEN ("neq_us") },
16355   { STRING_COMMA_LEN ("nlt_uq") },
16356   { STRING_COMMA_LEN ("nle_uq") },
16357   { STRING_COMMA_LEN ("ord_s") },
16358   { STRING_COMMA_LEN ("eq_us") },
16359   { STRING_COMMA_LEN ("nge_uq") },
16360   { STRING_COMMA_LEN ("ngt_uq") },
16361   { STRING_COMMA_LEN ("false_os") },
16362   { STRING_COMMA_LEN ("neq_os") },
16363   { STRING_COMMA_LEN ("ge_oq") },
16364   { STRING_COMMA_LEN ("gt_oq") },
16365   { STRING_COMMA_LEN ("true_us") },
16366 };
16367
16368 static void
16369 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16370 {
16371   unsigned int cmp_type;
16372
16373   FETCH_DATA (the_info, codep + 1);
16374   cmp_type = *codep++ & 0xff;
16375   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16376     {
16377       char suffix [3];
16378       char *p = mnemonicendp - 2;
16379       suffix[0] = p[0];
16380       suffix[1] = p[1];
16381       suffix[2] = '\0';
16382       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16383       mnemonicendp += vex_cmp_op[cmp_type].len;
16384     }
16385   else
16386     {
16387       /* We have a reserved extension byte.  Output it directly.  */
16388       scratchbuf[0] = '$';
16389       print_operand_value (scratchbuf + 1, 1, cmp_type);
16390       oappend_maybe_intel (scratchbuf);
16391       scratchbuf[0] = '\0';
16392     }
16393 }
16394
16395 static void
16396 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16397              int sizeflag ATTRIBUTE_UNUSED)
16398 {
16399   unsigned int cmp_type;
16400
16401   if (!vex.evex)
16402     abort ();
16403
16404   FETCH_DATA (the_info, codep + 1);
16405   cmp_type = *codep++ & 0xff;
16406   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16407      If it's the case, print suffix, otherwise - print the immediate.  */
16408   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16409       && cmp_type != 3
16410       && cmp_type != 7)
16411     {
16412       char suffix [3];
16413       char *p = mnemonicendp - 2;
16414
16415       /* vpcmp* can have both one- and two-lettered suffix.  */
16416       if (p[0] == 'p')
16417         {
16418           p++;
16419           suffix[0] = p[0];
16420           suffix[1] = '\0';
16421         }
16422       else
16423         {
16424           suffix[0] = p[0];
16425           suffix[1] = p[1];
16426           suffix[2] = '\0';
16427         }
16428
16429       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16430       mnemonicendp += simd_cmp_op[cmp_type].len;
16431     }
16432   else
16433     {
16434       /* We have a reserved extension byte.  Output it directly.  */
16435       scratchbuf[0] = '$';
16436       print_operand_value (scratchbuf + 1, 1, cmp_type);
16437       oappend_maybe_intel (scratchbuf);
16438       scratchbuf[0] = '\0';
16439     }
16440 }
16441
16442 static const struct op xop_cmp_op[] =
16443 {
16444   { STRING_COMMA_LEN ("lt") },
16445   { STRING_COMMA_LEN ("le") },
16446   { STRING_COMMA_LEN ("gt") },
16447   { STRING_COMMA_LEN ("ge") },
16448   { STRING_COMMA_LEN ("eq") },
16449   { STRING_COMMA_LEN ("neq") },
16450   { STRING_COMMA_LEN ("false") },
16451   { STRING_COMMA_LEN ("true") }
16452 };
16453
16454 static void
16455 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16456              int sizeflag ATTRIBUTE_UNUSED)
16457 {
16458   unsigned int cmp_type;
16459
16460   FETCH_DATA (the_info, codep + 1);
16461   cmp_type = *codep++ & 0xff;
16462   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16463     {
16464       char suffix[3];
16465       char *p = mnemonicendp - 2;
16466
16467       /* vpcom* can have both one- and two-lettered suffix.  */
16468       if (p[0] == 'm')
16469         {
16470           p++;
16471           suffix[0] = p[0];
16472           suffix[1] = '\0';
16473         }
16474       else
16475         {
16476           suffix[0] = p[0];
16477           suffix[1] = p[1];
16478           suffix[2] = '\0';
16479         }
16480
16481       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16482       mnemonicendp += xop_cmp_op[cmp_type].len;
16483     }
16484   else
16485     {
16486       /* We have a reserved extension byte.  Output it directly.  */
16487       scratchbuf[0] = '$';
16488       print_operand_value (scratchbuf + 1, 1, cmp_type);
16489       oappend_maybe_intel (scratchbuf);
16490       scratchbuf[0] = '\0';
16491     }
16492 }
16493
16494 static const struct op pclmul_op[] =
16495 {
16496   { STRING_COMMA_LEN ("lql") },
16497   { STRING_COMMA_LEN ("hql") },
16498   { STRING_COMMA_LEN ("lqh") },
16499   { STRING_COMMA_LEN ("hqh") }
16500 };
16501
16502 static void
16503 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16504               int sizeflag ATTRIBUTE_UNUSED)
16505 {
16506   unsigned int pclmul_type;
16507
16508   FETCH_DATA (the_info, codep + 1);
16509   pclmul_type = *codep++ & 0xff;
16510   switch (pclmul_type)
16511     {
16512     case 0x10:
16513       pclmul_type = 2;
16514       break;
16515     case 0x11:
16516       pclmul_type = 3;
16517       break;
16518     default:
16519       break;
16520     }
16521   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16522     {
16523       char suffix [4];
16524       char *p = mnemonicendp - 3;
16525       suffix[0] = p[0];
16526       suffix[1] = p[1];
16527       suffix[2] = p[2];
16528       suffix[3] = '\0';
16529       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16530       mnemonicendp += pclmul_op[pclmul_type].len;
16531     }
16532   else
16533     {
16534       /* We have a reserved extension byte.  Output it directly.  */
16535       scratchbuf[0] = '$';
16536       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16537       oappend_maybe_intel (scratchbuf);
16538       scratchbuf[0] = '\0';
16539     }
16540 }
16541
16542 static void
16543 MOVBE_Fixup (int bytemode, int sizeflag)
16544 {
16545   /* Add proper suffix to "movbe".  */
16546   char *p = mnemonicendp;
16547
16548   switch (bytemode)
16549     {
16550     case v_mode:
16551       if (intel_syntax)
16552         goto skip;
16553
16554       USED_REX (REX_W);
16555       if (sizeflag & SUFFIX_ALWAYS)
16556         {
16557           if (rex & REX_W)
16558             *p++ = 'q';
16559           else
16560             {
16561               if (sizeflag & DFLAG)
16562                 *p++ = 'l';
16563               else
16564                 *p++ = 'w';
16565               used_prefixes |= (prefixes & PREFIX_DATA);
16566             }
16567         }
16568       break;
16569     default:
16570       oappend (INTERNAL_DISASSEMBLER_ERROR);
16571       break;
16572     }
16573   mnemonicendp = p;
16574   *p = '\0';
16575
16576 skip:
16577   OP_M (bytemode, sizeflag);
16578 }
16579
16580 static void
16581 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16582 {
16583   int reg;
16584   const char **names;
16585
16586   /* Skip mod/rm byte.  */
16587   MODRM_CHECK;
16588   codep++;
16589
16590   if (rex & REX_W)
16591     names = names64;
16592   else
16593     names = names32;
16594
16595   reg = modrm.rm;
16596   USED_REX (REX_B);
16597   if (rex & REX_B)
16598     reg += 8;
16599
16600   oappend (names[reg]);
16601 }
16602
16603 static void
16604 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16605 {
16606   const char **names;
16607   unsigned int reg = vex.register_specifier;
16608   vex.register_specifier = 0;
16609
16610   if (rex & REX_W)
16611     names = names64;
16612   else
16613     names = names32;
16614
16615   if (address_mode != mode_64bit)
16616     reg &= 7;
16617   oappend (names[reg]);
16618 }
16619
16620 static void
16621 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16622 {
16623   if (!vex.evex
16624       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16625     abort ();
16626
16627   USED_REX (REX_R);
16628   if ((rex & REX_R) != 0 || !vex.r)
16629     {
16630       BadOp ();
16631       return;
16632     }
16633
16634   oappend (names_mask [modrm.reg]);
16635 }
16636
16637 static void
16638 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16639 {
16640   if (!vex.evex
16641       || (bytemode != evex_rounding_mode
16642           && bytemode != evex_rounding_64_mode
16643           && bytemode != evex_sae_mode))
16644     abort ();
16645   if (modrm.mod == 3 && vex.b)
16646     switch (bytemode)
16647       {
16648       case evex_rounding_64_mode:
16649         if (address_mode != mode_64bit)
16650           {
16651             oappend ("(bad)");
16652             break;
16653           }
16654         /* Fall through.  */
16655       case evex_rounding_mode:
16656         oappend (names_rounding[vex.ll]);
16657         break;
16658       case evex_sae_mode:
16659         oappend ("{sae}");
16660         break;
16661       default:
16662         break;
16663       }
16664 }