opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexR (int, int);
  92 static void OP_VexW (int, int);
  93 static void OP_Rounding (int, int);
  94 static void OP_REG_VexI4 (int, int);
  95 static void OP_VexI4 (int, int);
  96 static void PCLMUL_Fixup (int, int);
  97 static void VPCMP_Fixup (int, int);
  98 static void VPCOM_Fixup (int, int);
  99 static void OP_0f07 (int, int);
 100 static void OP_Monitor (int, int);
 101 static void OP_Mwait (int, int);
 102 static void NOP_Fixup1 (int, int);
 103 static void NOP_Fixup2 (int, int);
 104 static void OP_3DNowSuffix (int, int);
 105 static void CMP_Fixup (int, int);
 106 static void BadOp (void);
 107 static void REP_Fixup (int, int);
 108 static void SEP_Fixup (int, int);
 109 static void BND_Fixup (int, int);
 110 static void NOTRACK_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void FXSAVE_Fixup (int, int);
 117
 118 static void MOVSXD_Fixup (int, int);
 119
 120 static void OP_Mask (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   OPCODES_SIGJMP_BUF bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* Mark parts used in the REX prefix.  When we are testing for
 148    empty prefix (for 8bit register REX extension), just mask it
 149    out.  Otherwise test for REX bit is excuse for existence of REX
 150    only in case value is nonzero.  */
 151 #define USED_REX(value)                                 \
 152   {                                                     \
 153     if (value)                                          \
 154       {                                                 \
 155         if ((rex & value))                              \
 156           rex_used |= (value) | REX_OPCODE;             \
 157       }                                                 \
 158     else                                                \
 159       rex_used |= REX_OPCODE;                           \
 160   }
 161
 162 /* Flags for prefixes which we somehow handled when printing the
 163    current instruction.  */
 164 static int used_prefixes;
 165
 166 /* Flags stored in PREFIXES.  */
 167 #define PREFIX_REPZ 1
 168 #define PREFIX_REPNZ 2
 169 #define PREFIX_LOCK 4
 170 #define PREFIX_CS 8
 171 #define PREFIX_SS 0x10
 172 #define PREFIX_DS 0x20
 173 #define PREFIX_ES 0x40
 174 #define PREFIX_FS 0x80
 175 #define PREFIX_GS 0x100
 176 #define PREFIX_DATA 0x200
 177 #define PREFIX_ADDR 0x400
 178 #define PREFIX_FWAIT 0x800
 179
 180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 181    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 182    on error.  */
 183 #define FETCH_DATA(info, addr) \
 184   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 185    ? 1 : fetch_data ((info), (addr)))
 186
 187 static int
 188 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 189 {
 190   int status;
 191   struct dis_private *priv = (struct dis_private *) info->private_data;
 192   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 193
 194   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 195     status = (*info->read_memory_func) (start,
 196                                         priv->max_fetched,
 197                                         addr - priv->max_fetched,
 198                                         info);
 199   else
 200     status = -1;
 201   if (status != 0)
 202     {
 203       /* If we did manage to read at least one byte, then
 204          print_insn_i386 will do something sensible.  Otherwise, print
 205          an error.  We do that here because this is where we know
 206          STATUS.  */
 207       if (priv->max_fetched == priv->the_buffer)
 208         (*info->memory_error_func) (status, start, info);
 209       OPCODES_SIGLONGJMP (priv->bailout, 1);
 210     }
 211   else
 212     priv->max_fetched = addr;
 213   return 1;
 214 }
 215
 216 /* Possible values for prefix requirement.  */
 217 #define PREFIX_IGNORED_SHIFT    16
 218 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 223
 224 /* Opcode prefixes.  */
 225 #define PREFIX_OPCODE           (PREFIX_REPZ \
 226                                  | PREFIX_REPNZ \
 227                                  | PREFIX_DATA)
 228
 229 /* Prefixes ignored.  */
 230 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 231                                  | PREFIX_IGNORED_REPNZ \
 232                                  | PREFIX_IGNORED_DATA)
 233
 234 #define XX { NULL, 0 }
 235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 236
 237 #define Eb { OP_E, b_mode }
 238 #define Ebnd { OP_E, bnd_mode }
 239 #define EbS { OP_E, b_swap_mode }
 240 #define EbndS { OP_E, bnd_swap_mode }
 241 #define Ev { OP_E, v_mode }
 242 #define Eva { OP_E, va_mode }
 243 #define Ev_bnd { OP_E, v_bnd_mode }
 244 #define EvS { OP_E, v_swap_mode }
 245 #define Ed { OP_E, d_mode }
 246 #define Edq { OP_E, dq_mode }
 247 #define Edqw { OP_E, dqw_mode }
 248 #define Edqb { OP_E, dqb_mode }
 249 #define Edb { OP_E, db_mode }
 250 #define Edw { OP_E, dw_mode }
 251 #define Edqd { OP_E, dqd_mode }
 252 #define Eq { OP_E, q_mode }
 253 #define indirEv { OP_indirE, indir_v_mode }
 254 #define indirEp { OP_indirE, f_mode }
 255 #define stackEv { OP_E, stack_v_mode }
 256 #define Em { OP_E, m_mode }
 257 #define Ew { OP_E, w_mode }
 258 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 259 #define Ma { OP_M, a_mode }
 260 #define Mb { OP_M, b_mode }
 261 #define Md { OP_M, d_mode }
 262 #define Mo { OP_M, o_mode }
 263 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 264 #define Mq { OP_M, q_mode }
 265 #define Mv { OP_M, v_mode }
 266 #define Mv_bnd { OP_M, v_bndmk_mode }
 267 #define Mx { OP_M, x_mode }
 268 #define Mxmm { OP_M, xmm_mode }
 269 #define Gb { OP_G, b_mode }
 270 #define Gbnd { OP_G, bnd_mode }
 271 #define Gv { OP_G, v_mode }
 272 #define Gd { OP_G, d_mode }
 273 #define Gdq { OP_G, dq_mode }
 274 #define Gm { OP_G, m_mode }
 275 #define Gva { OP_G, va_mode }
 276 #define Gw { OP_G, w_mode }
 277 #define Rd { OP_R, d_mode }
 278 #define Rdq { OP_R, dq_mode }
 279 #define Rm { OP_R, m_mode }
 280 #define Ib { OP_I, b_mode }
 281 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 282 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 283 #define Iv { OP_I, v_mode }
 284 #define sIv { OP_sI, v_mode }
 285 #define Iv64 { OP_I64, v_mode }
 286 #define Id { OP_I, d_mode }
 287 #define Iw { OP_I, w_mode }
 288 #define I1 { OP_I, const_1_mode }
 289 #define Jb { OP_J, b_mode }
 290 #define Jv { OP_J, v_mode }
 291 #define Jdqw { OP_J, dqw_mode }
 292 #define Cm { OP_C, m_mode }
 293 #define Dm { OP_D, m_mode }
 294 #define Td { OP_T, d_mode }
 295 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 296
 297 #define RMeAX { OP_REG, eAX_reg }
 298 #define RMeBX { OP_REG, eBX_reg }
 299 #define RMeCX { OP_REG, eCX_reg }
 300 #define RMeDX { OP_REG, eDX_reg }
 301 #define RMeSP { OP_REG, eSP_reg }
 302 #define RMeBP { OP_REG, eBP_reg }
 303 #define RMeSI { OP_REG, eSI_reg }
 304 #define RMeDI { OP_REG, eDI_reg }
 305 #define RMrAX { OP_REG, rAX_reg }
 306 #define RMrBX { OP_REG, rBX_reg }
 307 #define RMrCX { OP_REG, rCX_reg }
 308 #define RMrDX { OP_REG, rDX_reg }
 309 #define RMrSP { OP_REG, rSP_reg }
 310 #define RMrBP { OP_REG, rBP_reg }
 311 #define RMrSI { OP_REG, rSI_reg }
 312 #define RMrDI { OP_REG, rDI_reg }
 313 #define RMAL { OP_REG, al_reg }
 314 #define RMCL { OP_REG, cl_reg }
 315 #define RMDL { OP_REG, dl_reg }
 316 #define RMBL { OP_REG, bl_reg }
 317 #define RMAH { OP_REG, ah_reg }
 318 #define RMCH { OP_REG, ch_reg }
 319 #define RMDH { OP_REG, dh_reg }
 320 #define RMBH { OP_REG, bh_reg }
 321 #define RMAX { OP_REG, ax_reg }
 322 #define RMDX { OP_REG, dx_reg }
 323
 324 #define eAX { OP_IMREG, eAX_reg }
 325 #define AL { OP_IMREG, al_reg }
 326 #define CL { OP_IMREG, cl_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define TMM { OP_XMM, tmm_mode }
 355 #define XMxmmq { OP_XMM, xmmq_mode }
 356 #define EM { OP_EM, v_mode }
 357 #define EMS { OP_EM, v_swap_mode }
 358 #define EMd { OP_EM, d_mode }
 359 #define EMx { OP_EM, x_mode }
 360 #define EXbwUnit { OP_EX, bw_unit_mode }
 361 #define EXw { OP_EX, w_mode }
 362 #define EXd { OP_EX, d_mode }
 363 #define EXdS { OP_EX, d_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqS { OP_EX, q_swap_mode }
 366 #define EXx { OP_EX, x_mode }
 367 #define EXxS { OP_EX, x_swap_mode }
 368 #define EXxmm { OP_EX, xmm_mode }
 369 #define EXymm { OP_EX, ymm_mode }
 370 #define EXtmm { OP_EX, tmm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmmdw { OP_EX, xmmdw_mode }
 378 #define EXxmmqd { OP_EX, xmmqd_mode }
 379 #define EXymmq { OP_EX, ymmq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define SEP { SEP_Fixup, 0 }
 389 #define CMP { CMP_Fixup, 0 }
 390 #define XMM0 { XMM_Fixup, 0 }
 391 #define FXSAVE { FXSAVE_Fixup, 0 }
 392
 393 #define Vex { OP_VEX, vex_mode }
 394 #define VexW { OP_VexW, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexScalarR { OP_VexR, vex_scalar_mode }
 397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 398 #define VexGdq { OP_VEX, dq_mode }
 399 #define VexTmm { OP_VEX, tmm_mode }
 400 #define XMVexI4 { OP_REG_VexI4, x_mode }
 401 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 402 #define VexI4 { OP_VexI4, 0 }
 403 #define PCLMUL { PCLMUL_Fixup, 0 }
 404 #define VPCMP { VPCMP_Fixup, 0 }
 405 #define VPCOM { VPCOM_Fixup, 0 }
 406
 407 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 408 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 409 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 410
 411 #define XMask { OP_Mask, mask_mode }
 412 #define MaskG { OP_G, mask_mode }
 413 #define MaskE { OP_E, mask_mode }
 414 #define MaskBDE { OP_E, mask_bd_mode }
 415 #define MaskR { OP_R, mask_mode }
 416 #define MaskVex { OP_VEX, mask_mode }
 417
 418 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 419 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 420 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 421 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 422
 423 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 424
 425 /* Used handle "rep" prefix for string instructions.  */
 426 #define Xbr { REP_Fixup, eSI_reg }
 427 #define Xvr { REP_Fixup, eSI_reg }
 428 #define Ybr { REP_Fixup, eDI_reg }
 429 #define Yvr { REP_Fixup, eDI_reg }
 430 #define Yzr { REP_Fixup, eDI_reg }
 431 #define indirDXr { REP_Fixup, indir_dx_reg }
 432 #define ALr { REP_Fixup, al_reg }
 433 #define eAXr { REP_Fixup, eAX_reg }
 434
 435 /* Used handle HLE prefix for lockable instructions.  */
 436 #define Ebh1 { HLE_Fixup1, b_mode }
 437 #define Evh1 { HLE_Fixup1, v_mode }
 438 #define Ebh2 { HLE_Fixup2, b_mode }
 439 #define Evh2 { HLE_Fixup2, v_mode }
 440 #define Ebh3 { HLE_Fixup3, b_mode }
 441 #define Evh3 { HLE_Fixup3, v_mode }
 442
 443 #define BND { BND_Fixup, 0 }
 444 #define NOTRACK { NOTRACK_Fixup, 0 }
 445
 446 #define cond_jump_flag { NULL, cond_jump_mode }
 447 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 448
 449 /* bits in sizeflag */
 450 #define SUFFIX_ALWAYS 4
 451 #define AFLAG 2
 452 #define DFLAG 1
 453
 454 enum
 455 {
 456   /* byte operand */
 457   b_mode = 1,
 458   /* byte operand with operand swapped */
 459   b_swap_mode,
 460   /* byte operand, sign extend like 'T' suffix */
 461   b_T_mode,
 462   /* operand size depends on prefixes */
 463   v_mode,
 464   /* operand size depends on prefixes with operand swapped */
 465   v_swap_mode,
 466   /* operand size depends on address prefix */
 467   va_mode,
 468   /* word operand */
 469   w_mode,
 470   /* double word operand  */
 471   d_mode,
 472   /* double word operand with operand swapped */
 473   d_swap_mode,
 474   /* quad word operand */
 475   q_mode,
 476   /* quad word operand with operand swapped */
 477   q_swap_mode,
 478   /* ten-byte operand */
 479   t_mode,
 480   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 481      broadcast enabled.  */
 482   x_mode,
 483   /* Similar to x_mode, but with different EVEX mem shifts.  */
 484   evex_x_gscat_mode,
 485   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 486   bw_unit_mode,
 487   /* Similar to x_mode, but with disabled broadcast.  */
 488   evex_x_nobcst_mode,
 489   /* Similar to x_mode, but with operands swapped and disabled broadcast
 490      in EVEX.  */
 491   x_swap_mode,
 492   /* 16-byte XMM operand */
 493   xmm_mode,
 494   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 495      memory operand (depending on vector length).  Broadcast isn't
 496      allowed.  */
 497   xmmq_mode,
 498   /* Same as xmmq_mode, but broadcast is allowed.  */
 499   evex_half_bcst_xmmq_mode,
 500   /* XMM register or byte memory operand */
 501   xmm_mb_mode,
 502   /* XMM register or word memory operand */
 503   xmm_mw_mode,
 504   /* XMM register or double word memory operand */
 505   xmm_md_mode,
 506   /* XMM register or quad word memory operand */
 507   xmm_mq_mode,
 508   /* 16-byte XMM, word, double word or quad word operand.  */
 509   xmmdw_mode,
 510   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 511   xmmqd_mode,
 512   /* 32-byte YMM operand */
 513   ymm_mode,
 514   /* quad word, ymmword or zmmword memory operand.  */
 515   ymmq_mode,
 516   /* 32-byte YMM or 16-byte word operand */
 517   ymmxmm_mode,
 518   /* TMM operand */
 519   tmm_mode,
 520   /* d_mode in 32bit, q_mode in 64bit mode.  */
 521   m_mode,
 522   /* pair of v_mode operands */
 523   a_mode,
 524   cond_jump_mode,
 525   loop_jcxz_mode,
 526   movsxd_mode,
 527   v_bnd_mode,
 528   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 529   v_bndmk_mode,
 530   /* operand size depends on REX prefixes.  */
 531   dq_mode,
 532   /* registers like dq_mode, memory like w_mode, displacements like
 533      v_mode without considering Intel64 ISA.  */
 534   dqw_mode,
 535   /* bounds operand */
 536   bnd_mode,
 537   /* bounds operand with operand swapped */
 538   bnd_swap_mode,
 539   /* 4- or 6-byte pointer operand */
 540   f_mode,
 541   const_1_mode,
 542   /* v_mode for indirect branch opcodes.  */
 543   indir_v_mode,
 544   /* v_mode for stack-related opcodes.  */
 545   stack_v_mode,
 546   /* non-quad operand size depends on prefixes */
 547   z_mode,
 548   /* 16-byte operand */
 549   o_mode,
 550   /* registers like dq_mode, memory like b_mode.  */
 551   dqb_mode,
 552   /* registers like d_mode, memory like b_mode.  */
 553   db_mode,
 554   /* registers like d_mode, memory like w_mode.  */
 555   dw_mode,
 556   /* registers like dq_mode, memory like d_mode.  */
 557   dqd_mode,
 558   /* normal vex mode */
 559   vex_mode,
 560
 561   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 562   vex_vsib_d_w_dq_mode,
 563   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 564   vex_vsib_d_w_d_mode,
 565   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 566   vex_vsib_q_w_dq_mode,
 567   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 568   vex_vsib_q_w_d_mode,
 569   /* mandatory non-vector SIB.  */
 570   vex_sibmem_mode,
 571
 572   /* scalar, ignore vector length.  */
 573   scalar_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Static rounding, 64-bit mode only.  */
 582   evex_rounding_64_mode,
 583   /* Supress all exceptions.  */
 584   evex_sae_mode,
 585
 586   /* Mask register operand.  */
 587   mask_mode,
 588   /* Mask register operand.  */
 589   mask_bd_mode,
 590
 591   es_reg,
 592   cs_reg,
 593   ss_reg,
 594   ds_reg,
 595   fs_reg,
 596   gs_reg,
 597
 598   eAX_reg,
 599   eCX_reg,
 600   eDX_reg,
 601   eBX_reg,
 602   eSP_reg,
 603   eBP_reg,
 604   eSI_reg,
 605   eDI_reg,
 606
 607   al_reg,
 608   cl_reg,
 609   dl_reg,
 610   bl_reg,
 611   ah_reg,
 612   ch_reg,
 613   dh_reg,
 614   bh_reg,
 615
 616   ax_reg,
 617   cx_reg,
 618   dx_reg,
 619   bx_reg,
 620   sp_reg,
 621   bp_reg,
 622   si_reg,
 623   di_reg,
 624
 625   rAX_reg,
 626   rCX_reg,
 627   rDX_reg,
 628   rBX_reg,
 629   rSP_reg,
 630   rBP_reg,
 631   rSI_reg,
 632   rDI_reg,
 633
 634   z_mode_ax_reg,
 635   indir_dx_reg
 636 };
 637
 638 enum
 639 {
 640   FLOATCODE = 1,
 641   USE_REG_TABLE,
 642   USE_MOD_TABLE,
 643   USE_RM_TABLE,
 644   USE_PREFIX_TABLE,
 645   USE_X86_64_TABLE,
 646   USE_3BYTE_TABLE,
 647   USE_XOP_8F_TABLE,
 648   USE_VEX_C4_TABLE,
 649   USE_VEX_C5_TABLE,
 650   USE_VEX_LEN_TABLE,
 651   USE_VEX_W_TABLE,
 652   USE_EVEX_TABLE,
 653   USE_EVEX_LEN_TABLE
 654 };
 655
 656 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 657
 658 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 659 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 660 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 661 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 662 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 663 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 664 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 665 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 666 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 667 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 668 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 669 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 670 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 671 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 672 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 673 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 674
 675 enum
 676 {
 677   REG_80 = 0,
 678   REG_81,
 679   REG_83,
 680   REG_8F,
 681   REG_C0,
 682   REG_C1,
 683   REG_C6,
 684   REG_C7,
 685   REG_D0,
 686   REG_D1,
 687   REG_D2,
 688   REG_D3,
 689   REG_F6,
 690   REG_F7,
 691   REG_FE,
 692   REG_FF,
 693   REG_0F00,
 694   REG_0F01,
 695   REG_0F0D,
 696   REG_0F18,
 697   REG_0F1C_P_0_MOD_0,
 698   REG_0F1E_P_1_MOD_3,
 699   REG_0F71,
 700   REG_0F72,
 701   REG_0F73,
 702   REG_0FA6,
 703   REG_0FA7,
 704   REG_0FAE,
 705   REG_0FBA,
 706   REG_0FC7,
 707   REG_VEX_0F71,
 708   REG_VEX_0F72,
 709   REG_VEX_0F73,
 710   REG_VEX_0FAE,
 711   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 712   REG_VEX_0F38F3,
 713
 714   REG_0FXOP_09_01_L_0,
 715   REG_0FXOP_09_02_L_0,
 716   REG_0FXOP_09_12_M_1_L_0,
 717   REG_0FXOP_0A_12_L_0,
 718
 719   REG_EVEX_0F71,
 720   REG_EVEX_0F72,
 721   REG_EVEX_0F73,
 722   REG_EVEX_0F38C6,
 723   REG_EVEX_0F38C7
 724 };
 725
 726 enum
 727 {
 728   MOD_8D = 0,
 729   MOD_C6_REG_7,
 730   MOD_C7_REG_7,
 731   MOD_FF_REG_3,
 732   MOD_FF_REG_5,
 733   MOD_0F01_REG_0,
 734   MOD_0F01_REG_1,
 735   MOD_0F01_REG_2,
 736   MOD_0F01_REG_3,
 737   MOD_0F01_REG_5,
 738   MOD_0F01_REG_7,
 739   MOD_0F12_PREFIX_0,
 740   MOD_0F12_PREFIX_2,
 741   MOD_0F13,
 742   MOD_0F16_PREFIX_0,
 743   MOD_0F16_PREFIX_2,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F1C_PREFIX_0,
 757   MOD_0F1E_PREFIX_1,
 758   MOD_0F24,
 759   MOD_0F26,
 760   MOD_0F2B_PREFIX_0,
 761   MOD_0F2B_PREFIX_1,
 762   MOD_0F2B_PREFIX_2,
 763   MOD_0F2B_PREFIX_3,
 764   MOD_0F50,
 765   MOD_0F71_REG_2,
 766   MOD_0F71_REG_4,
 767   MOD_0F71_REG_6,
 768   MOD_0F72_REG_2,
 769   MOD_0F72_REG_4,
 770   MOD_0F72_REG_6,
 771   MOD_0F73_REG_2,
 772   MOD_0F73_REG_3,
 773   MOD_0F73_REG_6,
 774   MOD_0F73_REG_7,
 775   MOD_0FAE_REG_0,
 776   MOD_0FAE_REG_1,
 777   MOD_0FAE_REG_2,
 778   MOD_0FAE_REG_3,
 779   MOD_0FAE_REG_4,
 780   MOD_0FAE_REG_5,
 781   MOD_0FAE_REG_6,
 782   MOD_0FAE_REG_7,
 783   MOD_0FB2,
 784   MOD_0FB4,
 785   MOD_0FB5,
 786   MOD_0FC3,
 787   MOD_0FC7_REG_3,
 788   MOD_0FC7_REG_4,
 789   MOD_0FC7_REG_5,
 790   MOD_0FC7_REG_6,
 791   MOD_0FC7_REG_7,
 792   MOD_0FD7,
 793   MOD_0FE7_PREFIX_2,
 794   MOD_0FF0_PREFIX_3,
 795   MOD_0F382A_PREFIX_2,
 796   MOD_VEX_0F3849_X86_64_P_0_W_0,
 797   MOD_VEX_0F3849_X86_64_P_2_W_0,
 798   MOD_VEX_0F3849_X86_64_P_3_W_0,
 799   MOD_VEX_0F384B_X86_64_P_1_W_0,
 800   MOD_VEX_0F384B_X86_64_P_2_W_0,
 801   MOD_VEX_0F384B_X86_64_P_3_W_0,
 802   MOD_VEX_0F385C_X86_64_P_1_W_0,
 803   MOD_VEX_0F385E_X86_64_P_0_W_0,
 804   MOD_VEX_0F385E_X86_64_P_1_W_0,
 805   MOD_VEX_0F385E_X86_64_P_2_W_0,
 806   MOD_VEX_0F385E_X86_64_P_3_W_0,
 807   MOD_0F38F5_PREFIX_2,
 808   MOD_0F38F6_PREFIX_0,
 809   MOD_0F38F8_PREFIX_1,
 810   MOD_0F38F8_PREFIX_2,
 811   MOD_0F38F8_PREFIX_3,
 812   MOD_0F38F9_PREFIX_0,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F12_PREFIX_2,
 818   MOD_VEX_0F13,
 819   MOD_VEX_0F16_PREFIX_0,
 820   MOD_VEX_0F16_PREFIX_2,
 821   MOD_VEX_0F17,
 822   MOD_VEX_0F2B,
 823   MOD_VEX_W_0_0F41_P_0_LEN_1,
 824   MOD_VEX_W_1_0F41_P_0_LEN_1,
 825   MOD_VEX_W_0_0F41_P_2_LEN_1,
 826   MOD_VEX_W_1_0F41_P_2_LEN_1,
 827   MOD_VEX_W_0_0F42_P_0_LEN_1,
 828   MOD_VEX_W_1_0F42_P_0_LEN_1,
 829   MOD_VEX_W_0_0F42_P_2_LEN_1,
 830   MOD_VEX_W_1_0F42_P_2_LEN_1,
 831   MOD_VEX_W_0_0F44_P_0_LEN_1,
 832   MOD_VEX_W_1_0F44_P_0_LEN_1,
 833   MOD_VEX_W_0_0F44_P_2_LEN_1,
 834   MOD_VEX_W_1_0F44_P_2_LEN_1,
 835   MOD_VEX_W_0_0F45_P_0_LEN_1,
 836   MOD_VEX_W_1_0F45_P_0_LEN_1,
 837   MOD_VEX_W_0_0F45_P_2_LEN_1,
 838   MOD_VEX_W_1_0F45_P_2_LEN_1,
 839   MOD_VEX_W_0_0F46_P_0_LEN_1,
 840   MOD_VEX_W_1_0F46_P_0_LEN_1,
 841   MOD_VEX_W_0_0F46_P_2_LEN_1,
 842   MOD_VEX_W_1_0F46_P_2_LEN_1,
 843   MOD_VEX_W_0_0F47_P_0_LEN_1,
 844   MOD_VEX_W_1_0F47_P_0_LEN_1,
 845   MOD_VEX_W_0_0F47_P_2_LEN_1,
 846   MOD_VEX_W_1_0F47_P_2_LEN_1,
 847   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 848   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 850   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 852   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 854   MOD_VEX_0F50,
 855   MOD_VEX_0F71_REG_2,
 856   MOD_VEX_0F71_REG_4,
 857   MOD_VEX_0F71_REG_6,
 858   MOD_VEX_0F72_REG_2,
 859   MOD_VEX_0F72_REG_4,
 860   MOD_VEX_0F72_REG_6,
 861   MOD_VEX_0F73_REG_2,
 862   MOD_VEX_0F73_REG_3,
 863   MOD_VEX_0F73_REG_6,
 864   MOD_VEX_0F73_REG_7,
 865   MOD_VEX_W_0_0F91_P_0_LEN_0,
 866   MOD_VEX_W_1_0F91_P_0_LEN_0,
 867   MOD_VEX_W_0_0F91_P_2_LEN_0,
 868   MOD_VEX_W_1_0F91_P_2_LEN_0,
 869   MOD_VEX_W_0_0F92_P_0_LEN_0,
 870   MOD_VEX_W_0_0F92_P_2_LEN_0,
 871   MOD_VEX_0F92_P_3_LEN_0,
 872   MOD_VEX_W_0_0F93_P_0_LEN_0,
 873   MOD_VEX_W_0_0F93_P_2_LEN_0,
 874   MOD_VEX_0F93_P_3_LEN_0,
 875   MOD_VEX_W_0_0F98_P_0_LEN_0,
 876   MOD_VEX_W_1_0F98_P_0_LEN_0,
 877   MOD_VEX_W_0_0F98_P_2_LEN_0,
 878   MOD_VEX_W_1_0F98_P_2_LEN_0,
 879   MOD_VEX_W_0_0F99_P_0_LEN_0,
 880   MOD_VEX_W_1_0F99_P_0_LEN_0,
 881   MOD_VEX_W_0_0F99_P_2_LEN_0,
 882   MOD_VEX_W_1_0F99_P_2_LEN_0,
 883   MOD_VEX_0FAE_REG_2,
 884   MOD_VEX_0FAE_REG_3,
 885   MOD_VEX_0FD7_PREFIX_2,
 886   MOD_VEX_0FE7_PREFIX_2,
 887   MOD_VEX_0FF0_PREFIX_3,
 888   MOD_VEX_0F381A_PREFIX_2,
 889   MOD_VEX_0F382A_PREFIX_2,
 890   MOD_VEX_0F382C_PREFIX_2,
 891   MOD_VEX_0F382D_PREFIX_2,
 892   MOD_VEX_0F382E_PREFIX_2,
 893   MOD_VEX_0F382F_PREFIX_2,
 894   MOD_VEX_0F385A_PREFIX_2,
 895   MOD_VEX_0F388C_PREFIX_2,
 896   MOD_VEX_0F388E_PREFIX_2,
 897   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 898   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 899   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 900   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 901   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 902   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 903   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 904   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 905
 906   MOD_VEX_0FXOP_09_12,
 907
 908   MOD_EVEX_0F12_PREFIX_0,
 909   MOD_EVEX_0F12_PREFIX_2,
 910   MOD_EVEX_0F13,
 911   MOD_EVEX_0F16_PREFIX_0,
 912   MOD_EVEX_0F16_PREFIX_2,
 913   MOD_EVEX_0F17,
 914   MOD_EVEX_0F2B,
 915   MOD_EVEX_0F381A_P_2_W_0,
 916   MOD_EVEX_0F381A_P_2_W_1,
 917   MOD_EVEX_0F381B_P_2_W_0,
 918   MOD_EVEX_0F381B_P_2_W_1,
 919   MOD_EVEX_0F385A_P_2_W_0,
 920   MOD_EVEX_0F385A_P_2_W_1,
 921   MOD_EVEX_0F385B_P_2_W_0,
 922   MOD_EVEX_0F385B_P_2_W_1,
 923   MOD_EVEX_0F38C6_REG_1,
 924   MOD_EVEX_0F38C6_REG_2,
 925   MOD_EVEX_0F38C6_REG_5,
 926   MOD_EVEX_0F38C6_REG_6,
 927   MOD_EVEX_0F38C7_REG_1,
 928   MOD_EVEX_0F38C7_REG_2,
 929   MOD_EVEX_0F38C7_REG_5,
 930   MOD_EVEX_0F38C7_REG_6
 931 };
 932
 933 enum
 934 {
 935   RM_C6_REG_7 = 0,
 936   RM_C7_REG_7,
 937   RM_0F01_REG_0,
 938   RM_0F01_REG_1,
 939   RM_0F01_REG_2,
 940   RM_0F01_REG_3,
 941   RM_0F01_REG_5_MOD_3,
 942   RM_0F01_REG_7_MOD_3,
 943   RM_0F1E_P_1_MOD_3_REG_7,
 944   RM_0FAE_REG_6_MOD_3_P_0,
 945   RM_0FAE_REG_7_MOD_3,
 946   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 947 };
 948
 949 enum
 950 {
 951   PREFIX_90 = 0,
 952   PREFIX_0F01_REG_3_RM_1,
 953   PREFIX_0F01_REG_5_MOD_0,
 954   PREFIX_0F01_REG_5_MOD_3_RM_0,
 955   PREFIX_0F01_REG_5_MOD_3_RM_1,
 956   PREFIX_0F01_REG_5_MOD_3_RM_2,
 957   PREFIX_0F01_REG_7_MOD_3_RM_2,
 958   PREFIX_0F01_REG_7_MOD_3_RM_3,
 959   PREFIX_0F09,
 960   PREFIX_0F10,
 961   PREFIX_0F11,
 962   PREFIX_0F12,
 963   PREFIX_0F16,
 964   PREFIX_0F1A,
 965   PREFIX_0F1B,
 966   PREFIX_0F1C,
 967   PREFIX_0F1E,
 968   PREFIX_0F2A,
 969   PREFIX_0F2B,
 970   PREFIX_0F2C,
 971   PREFIX_0F2D,
 972   PREFIX_0F2E,
 973   PREFIX_0F2F,
 974   PREFIX_0F51,
 975   PREFIX_0F52,
 976   PREFIX_0F53,
 977   PREFIX_0F58,
 978   PREFIX_0F59,
 979   PREFIX_0F5A,
 980   PREFIX_0F5B,
 981   PREFIX_0F5C,
 982   PREFIX_0F5D,
 983   PREFIX_0F5E,
 984   PREFIX_0F5F,
 985   PREFIX_0F60,
 986   PREFIX_0F61,
 987   PREFIX_0F62,
 988   PREFIX_0F6C,
 989   PREFIX_0F6D,
 990   PREFIX_0F6F,
 991   PREFIX_0F70,
 992   PREFIX_0F73_REG_3,
 993   PREFIX_0F73_REG_7,
 994   PREFIX_0F78,
 995   PREFIX_0F79,
 996   PREFIX_0F7C,
 997   PREFIX_0F7D,
 998   PREFIX_0F7E,
 999   PREFIX_0F7F,
1000   PREFIX_0FAE_REG_0_MOD_3,
1001   PREFIX_0FAE_REG_1_MOD_3,
1002   PREFIX_0FAE_REG_2_MOD_3,
1003   PREFIX_0FAE_REG_3_MOD_3,
1004   PREFIX_0FAE_REG_4_MOD_0,
1005   PREFIX_0FAE_REG_4_MOD_3,
1006   PREFIX_0FAE_REG_5_MOD_0,
1007   PREFIX_0FAE_REG_5_MOD_3,
1008   PREFIX_0FAE_REG_6_MOD_0,
1009   PREFIX_0FAE_REG_6_MOD_3,
1010   PREFIX_0FAE_REG_7_MOD_0,
1011   PREFIX_0FB8,
1012   PREFIX_0FBC,
1013   PREFIX_0FBD,
1014   PREFIX_0FC2,
1015   PREFIX_0FC3_MOD_0,
1016   PREFIX_0FC7_REG_6_MOD_0,
1017   PREFIX_0FC7_REG_6_MOD_3,
1018   PREFIX_0FC7_REG_7_MOD_3,
1019   PREFIX_0FD0,
1020   PREFIX_0FD6,
1021   PREFIX_0FE6,
1022   PREFIX_0FE7,
1023   PREFIX_0FF0,
1024   PREFIX_0FF7,
1025   PREFIX_0F3810,
1026   PREFIX_0F3814,
1027   PREFIX_0F3815,
1028   PREFIX_0F3817,
1029   PREFIX_0F3820,
1030   PREFIX_0F3821,
1031   PREFIX_0F3822,
1032   PREFIX_0F3823,
1033   PREFIX_0F3824,
1034   PREFIX_0F3825,
1035   PREFIX_0F3828,
1036   PREFIX_0F3829,
1037   PREFIX_0F382A,
1038   PREFIX_0F382B,
1039   PREFIX_0F3830,
1040   PREFIX_0F3831,
1041   PREFIX_0F3832,
1042   PREFIX_0F3833,
1043   PREFIX_0F3834,
1044   PREFIX_0F3835,
1045   PREFIX_0F3837,
1046   PREFIX_0F3838,
1047   PREFIX_0F3839,
1048   PREFIX_0F383A,
1049   PREFIX_0F383B,
1050   PREFIX_0F383C,
1051   PREFIX_0F383D,
1052   PREFIX_0F383E,
1053   PREFIX_0F383F,
1054   PREFIX_0F3840,
1055   PREFIX_0F3841,
1056   PREFIX_0F3880,
1057   PREFIX_0F3881,
1058   PREFIX_0F3882,
1059   PREFIX_0F38C8,
1060   PREFIX_0F38C9,
1061   PREFIX_0F38CA,
1062   PREFIX_0F38CB,
1063   PREFIX_0F38CC,
1064   PREFIX_0F38CD,
1065   PREFIX_0F38CF,
1066   PREFIX_0F38DB,
1067   PREFIX_0F38DC,
1068   PREFIX_0F38DD,
1069   PREFIX_0F38DE,
1070   PREFIX_0F38DF,
1071   PREFIX_0F38F0,
1072   PREFIX_0F38F1,
1073   PREFIX_0F38F5,
1074   PREFIX_0F38F6,
1075   PREFIX_0F38F8,
1076   PREFIX_0F38F9,
1077   PREFIX_0F3A08,
1078   PREFIX_0F3A09,
1079   PREFIX_0F3A0A,
1080   PREFIX_0F3A0B,
1081   PREFIX_0F3A0C,
1082   PREFIX_0F3A0D,
1083   PREFIX_0F3A0E,
1084   PREFIX_0F3A14,
1085   PREFIX_0F3A15,
1086   PREFIX_0F3A16,
1087   PREFIX_0F3A17,
1088   PREFIX_0F3A20,
1089   PREFIX_0F3A21,
1090   PREFIX_0F3A22,
1091   PREFIX_0F3A40,
1092   PREFIX_0F3A41,
1093   PREFIX_0F3A42,
1094   PREFIX_0F3A44,
1095   PREFIX_0F3A60,
1096   PREFIX_0F3A61,
1097   PREFIX_0F3A62,
1098   PREFIX_0F3A63,
1099   PREFIX_0F3ACC,
1100   PREFIX_0F3ACE,
1101   PREFIX_0F3ACF,
1102   PREFIX_0F3ADF,
1103   PREFIX_VEX_0F10,
1104   PREFIX_VEX_0F11,
1105   PREFIX_VEX_0F12,
1106   PREFIX_VEX_0F16,
1107   PREFIX_VEX_0F2A,
1108   PREFIX_VEX_0F2C,
1109   PREFIX_VEX_0F2D,
1110   PREFIX_VEX_0F2E,
1111   PREFIX_VEX_0F2F,
1112   PREFIX_VEX_0F41,
1113   PREFIX_VEX_0F42,
1114   PREFIX_VEX_0F44,
1115   PREFIX_VEX_0F45,
1116   PREFIX_VEX_0F46,
1117   PREFIX_VEX_0F47,
1118   PREFIX_VEX_0F4A,
1119   PREFIX_VEX_0F4B,
1120   PREFIX_VEX_0F51,
1121   PREFIX_VEX_0F52,
1122   PREFIX_VEX_0F53,
1123   PREFIX_VEX_0F58,
1124   PREFIX_VEX_0F59,
1125   PREFIX_VEX_0F5A,
1126   PREFIX_VEX_0F5B,
1127   PREFIX_VEX_0F5C,
1128   PREFIX_VEX_0F5D,
1129   PREFIX_VEX_0F5E,
1130   PREFIX_VEX_0F5F,
1131   PREFIX_VEX_0F60,
1132   PREFIX_VEX_0F61,
1133   PREFIX_VEX_0F62,
1134   PREFIX_VEX_0F63,
1135   PREFIX_VEX_0F64,
1136   PREFIX_VEX_0F65,
1137   PREFIX_VEX_0F66,
1138   PREFIX_VEX_0F67,
1139   PREFIX_VEX_0F68,
1140   PREFIX_VEX_0F69,
1141   PREFIX_VEX_0F6A,
1142   PREFIX_VEX_0F6B,
1143   PREFIX_VEX_0F6C,
1144   PREFIX_VEX_0F6D,
1145   PREFIX_VEX_0F6E,
1146   PREFIX_VEX_0F6F,
1147   PREFIX_VEX_0F70,
1148   PREFIX_VEX_0F71_REG_2,
1149   PREFIX_VEX_0F71_REG_4,
1150   PREFIX_VEX_0F71_REG_6,
1151   PREFIX_VEX_0F72_REG_2,
1152   PREFIX_VEX_0F72_REG_4,
1153   PREFIX_VEX_0F72_REG_6,
1154   PREFIX_VEX_0F73_REG_2,
1155   PREFIX_VEX_0F73_REG_3,
1156   PREFIX_VEX_0F73_REG_6,
1157   PREFIX_VEX_0F73_REG_7,
1158   PREFIX_VEX_0F74,
1159   PREFIX_VEX_0F75,
1160   PREFIX_VEX_0F76,
1161   PREFIX_VEX_0F77,
1162   PREFIX_VEX_0F7C,
1163   PREFIX_VEX_0F7D,
1164   PREFIX_VEX_0F7E,
1165   PREFIX_VEX_0F7F,
1166   PREFIX_VEX_0F90,
1167   PREFIX_VEX_0F91,
1168   PREFIX_VEX_0F92,
1169   PREFIX_VEX_0F93,
1170   PREFIX_VEX_0F98,
1171   PREFIX_VEX_0F99,
1172   PREFIX_VEX_0FC2,
1173   PREFIX_VEX_0FC4,
1174   PREFIX_VEX_0FC5,
1175   PREFIX_VEX_0FD0,
1176   PREFIX_VEX_0FD1,
1177   PREFIX_VEX_0FD2,
1178   PREFIX_VEX_0FD3,
1179   PREFIX_VEX_0FD4,
1180   PREFIX_VEX_0FD5,
1181   PREFIX_VEX_0FD6,
1182   PREFIX_VEX_0FD7,
1183   PREFIX_VEX_0FD8,
1184   PREFIX_VEX_0FD9,
1185   PREFIX_VEX_0FDA,
1186   PREFIX_VEX_0FDB,
1187   PREFIX_VEX_0FDC,
1188   PREFIX_VEX_0FDD,
1189   PREFIX_VEX_0FDE,
1190   PREFIX_VEX_0FDF,
1191   PREFIX_VEX_0FE0,
1192   PREFIX_VEX_0FE1,
1193   PREFIX_VEX_0FE2,
1194   PREFIX_VEX_0FE3,
1195   PREFIX_VEX_0FE4,
1196   PREFIX_VEX_0FE5,
1197   PREFIX_VEX_0FE6,
1198   PREFIX_VEX_0FE7,
1199   PREFIX_VEX_0FE8,
1200   PREFIX_VEX_0FE9,
1201   PREFIX_VEX_0FEA,
1202   PREFIX_VEX_0FEB,
1203   PREFIX_VEX_0FEC,
1204   PREFIX_VEX_0FED,
1205   PREFIX_VEX_0FEE,
1206   PREFIX_VEX_0FEF,
1207   PREFIX_VEX_0FF0,
1208   PREFIX_VEX_0FF1,
1209   PREFIX_VEX_0FF2,
1210   PREFIX_VEX_0FF3,
1211   PREFIX_VEX_0FF4,
1212   PREFIX_VEX_0FF5,
1213   PREFIX_VEX_0FF6,
1214   PREFIX_VEX_0FF7,
1215   PREFIX_VEX_0FF8,
1216   PREFIX_VEX_0FF9,
1217   PREFIX_VEX_0FFA,
1218   PREFIX_VEX_0FFB,
1219   PREFIX_VEX_0FFC,
1220   PREFIX_VEX_0FFD,
1221   PREFIX_VEX_0FFE,
1222   PREFIX_VEX_0F3800,
1223   PREFIX_VEX_0F3801,
1224   PREFIX_VEX_0F3802,
1225   PREFIX_VEX_0F3803,
1226   PREFIX_VEX_0F3804,
1227   PREFIX_VEX_0F3805,
1228   PREFIX_VEX_0F3806,
1229   PREFIX_VEX_0F3807,
1230   PREFIX_VEX_0F3808,
1231   PREFIX_VEX_0F3809,
1232   PREFIX_VEX_0F380A,
1233   PREFIX_VEX_0F380B,
1234   PREFIX_VEX_0F380C,
1235   PREFIX_VEX_0F380D,
1236   PREFIX_VEX_0F380E,
1237   PREFIX_VEX_0F380F,
1238   PREFIX_VEX_0F3813,
1239   PREFIX_VEX_0F3816,
1240   PREFIX_VEX_0F3817,
1241   PREFIX_VEX_0F3818,
1242   PREFIX_VEX_0F3819,
1243   PREFIX_VEX_0F381A,
1244   PREFIX_VEX_0F381C,
1245   PREFIX_VEX_0F381D,
1246   PREFIX_VEX_0F381E,
1247   PREFIX_VEX_0F3820,
1248   PREFIX_VEX_0F3821,
1249   PREFIX_VEX_0F3822,
1250   PREFIX_VEX_0F3823,
1251   PREFIX_VEX_0F3824,
1252   PREFIX_VEX_0F3825,
1253   PREFIX_VEX_0F3828,
1254   PREFIX_VEX_0F3829,
1255   PREFIX_VEX_0F382A,
1256   PREFIX_VEX_0F382B,
1257   PREFIX_VEX_0F382C,
1258   PREFIX_VEX_0F382D,
1259   PREFIX_VEX_0F382E,
1260   PREFIX_VEX_0F382F,
1261   PREFIX_VEX_0F3830,
1262   PREFIX_VEX_0F3831,
1263   PREFIX_VEX_0F3832,
1264   PREFIX_VEX_0F3833,
1265   PREFIX_VEX_0F3834,
1266   PREFIX_VEX_0F3835,
1267   PREFIX_VEX_0F3836,
1268   PREFIX_VEX_0F3837,
1269   PREFIX_VEX_0F3838,
1270   PREFIX_VEX_0F3839,
1271   PREFIX_VEX_0F383A,
1272   PREFIX_VEX_0F383B,
1273   PREFIX_VEX_0F383C,
1274   PREFIX_VEX_0F383D,
1275   PREFIX_VEX_0F383E,
1276   PREFIX_VEX_0F383F,
1277   PREFIX_VEX_0F3840,
1278   PREFIX_VEX_0F3841,
1279   PREFIX_VEX_0F3845,
1280   PREFIX_VEX_0F3846,
1281   PREFIX_VEX_0F3847,
1282   PREFIX_VEX_0F3849_X86_64,
1283   PREFIX_VEX_0F384B_X86_64,
1284   PREFIX_VEX_0F3858,
1285   PREFIX_VEX_0F3859,
1286   PREFIX_VEX_0F385A,
1287   PREFIX_VEX_0F385C_X86_64,
1288   PREFIX_VEX_0F385E_X86_64,
1289   PREFIX_VEX_0F3878,
1290   PREFIX_VEX_0F3879,
1291   PREFIX_VEX_0F388C,
1292   PREFIX_VEX_0F388E,
1293   PREFIX_VEX_0F3890,
1294   PREFIX_VEX_0F3891,
1295   PREFIX_VEX_0F3892,
1296   PREFIX_VEX_0F3893,
1297   PREFIX_VEX_0F3896,
1298   PREFIX_VEX_0F3897,
1299   PREFIX_VEX_0F3898,
1300   PREFIX_VEX_0F3899,
1301   PREFIX_VEX_0F389A,
1302   PREFIX_VEX_0F389B,
1303   PREFIX_VEX_0F389C,
1304   PREFIX_VEX_0F389D,
1305   PREFIX_VEX_0F389E,
1306   PREFIX_VEX_0F389F,
1307   PREFIX_VEX_0F38A6,
1308   PREFIX_VEX_0F38A7,
1309   PREFIX_VEX_0F38A8,
1310   PREFIX_VEX_0F38A9,
1311   PREFIX_VEX_0F38AA,
1312   PREFIX_VEX_0F38AB,
1313   PREFIX_VEX_0F38AC,
1314   PREFIX_VEX_0F38AD,
1315   PREFIX_VEX_0F38AE,
1316   PREFIX_VEX_0F38AF,
1317   PREFIX_VEX_0F38B6,
1318   PREFIX_VEX_0F38B7,
1319   PREFIX_VEX_0F38B8,
1320   PREFIX_VEX_0F38B9,
1321   PREFIX_VEX_0F38BA,
1322   PREFIX_VEX_0F38BB,
1323   PREFIX_VEX_0F38BC,
1324   PREFIX_VEX_0F38BD,
1325   PREFIX_VEX_0F38BE,
1326   PREFIX_VEX_0F38BF,
1327   PREFIX_VEX_0F38CF,
1328   PREFIX_VEX_0F38DB,
1329   PREFIX_VEX_0F38DC,
1330   PREFIX_VEX_0F38DD,
1331   PREFIX_VEX_0F38DE,
1332   PREFIX_VEX_0F38DF,
1333   PREFIX_VEX_0F38F2,
1334   PREFIX_VEX_0F38F3_REG_1,
1335   PREFIX_VEX_0F38F3_REG_2,
1336   PREFIX_VEX_0F38F3_REG_3,
1337   PREFIX_VEX_0F38F5,
1338   PREFIX_VEX_0F38F6,
1339   PREFIX_VEX_0F38F7,
1340   PREFIX_VEX_0F3A00,
1341   PREFIX_VEX_0F3A01,
1342   PREFIX_VEX_0F3A02,
1343   PREFIX_VEX_0F3A04,
1344   PREFIX_VEX_0F3A05,
1345   PREFIX_VEX_0F3A06,
1346   PREFIX_VEX_0F3A08,
1347   PREFIX_VEX_0F3A09,
1348   PREFIX_VEX_0F3A0A,
1349   PREFIX_VEX_0F3A0B,
1350   PREFIX_VEX_0F3A0C,
1351   PREFIX_VEX_0F3A0D,
1352   PREFIX_VEX_0F3A0E,
1353   PREFIX_VEX_0F3A0F,
1354   PREFIX_VEX_0F3A14,
1355   PREFIX_VEX_0F3A15,
1356   PREFIX_VEX_0F3A16,
1357   PREFIX_VEX_0F3A17,
1358   PREFIX_VEX_0F3A18,
1359   PREFIX_VEX_0F3A19,
1360   PREFIX_VEX_0F3A1D,
1361   PREFIX_VEX_0F3A20,
1362   PREFIX_VEX_0F3A21,
1363   PREFIX_VEX_0F3A22,
1364   PREFIX_VEX_0F3A30,
1365   PREFIX_VEX_0F3A31,
1366   PREFIX_VEX_0F3A32,
1367   PREFIX_VEX_0F3A33,
1368   PREFIX_VEX_0F3A38,
1369   PREFIX_VEX_0F3A39,
1370   PREFIX_VEX_0F3A40,
1371   PREFIX_VEX_0F3A41,
1372   PREFIX_VEX_0F3A42,
1373   PREFIX_VEX_0F3A44,
1374   PREFIX_VEX_0F3A46,
1375   PREFIX_VEX_0F3A48,
1376   PREFIX_VEX_0F3A49,
1377   PREFIX_VEX_0F3A4A,
1378   PREFIX_VEX_0F3A4B,
1379   PREFIX_VEX_0F3A4C,
1380   PREFIX_VEX_0F3A5C,
1381   PREFIX_VEX_0F3A5D,
1382   PREFIX_VEX_0F3A5E,
1383   PREFIX_VEX_0F3A5F,
1384   PREFIX_VEX_0F3A60,
1385   PREFIX_VEX_0F3A61,
1386   PREFIX_VEX_0F3A62,
1387   PREFIX_VEX_0F3A63,
1388   PREFIX_VEX_0F3A68,
1389   PREFIX_VEX_0F3A69,
1390   PREFIX_VEX_0F3A6A,
1391   PREFIX_VEX_0F3A6B,
1392   PREFIX_VEX_0F3A6C,
1393   PREFIX_VEX_0F3A6D,
1394   PREFIX_VEX_0F3A6E,
1395   PREFIX_VEX_0F3A6F,
1396   PREFIX_VEX_0F3A78,
1397   PREFIX_VEX_0F3A79,
1398   PREFIX_VEX_0F3A7A,
1399   PREFIX_VEX_0F3A7B,
1400   PREFIX_VEX_0F3A7C,
1401   PREFIX_VEX_0F3A7D,
1402   PREFIX_VEX_0F3A7E,
1403   PREFIX_VEX_0F3A7F,
1404   PREFIX_VEX_0F3ACE,
1405   PREFIX_VEX_0F3ACF,
1406   PREFIX_VEX_0F3ADF,
1407   PREFIX_VEX_0F3AF0,
1408
1409   PREFIX_EVEX_0F10,
1410   PREFIX_EVEX_0F11,
1411   PREFIX_EVEX_0F12,
1412   PREFIX_EVEX_0F16,
1413   PREFIX_EVEX_0F2A,
1414   PREFIX_EVEX_0F51,
1415   PREFIX_EVEX_0F58,
1416   PREFIX_EVEX_0F59,
1417   PREFIX_EVEX_0F5A,
1418   PREFIX_EVEX_0F5B,
1419   PREFIX_EVEX_0F5C,
1420   PREFIX_EVEX_0F5D,
1421   PREFIX_EVEX_0F5E,
1422   PREFIX_EVEX_0F5F,
1423   PREFIX_EVEX_0F64,
1424   PREFIX_EVEX_0F65,
1425   PREFIX_EVEX_0F66,
1426   PREFIX_EVEX_0F6E,
1427   PREFIX_EVEX_0F6F,
1428   PREFIX_EVEX_0F70,
1429   PREFIX_EVEX_0F71_REG_2,
1430   PREFIX_EVEX_0F71_REG_4,
1431   PREFIX_EVEX_0F71_REG_6,
1432   PREFIX_EVEX_0F72_REG_0,
1433   PREFIX_EVEX_0F72_REG_1,
1434   PREFIX_EVEX_0F72_REG_2,
1435   PREFIX_EVEX_0F72_REG_4,
1436   PREFIX_EVEX_0F72_REG_6,
1437   PREFIX_EVEX_0F73_REG_2,
1438   PREFIX_EVEX_0F73_REG_3,
1439   PREFIX_EVEX_0F73_REG_6,
1440   PREFIX_EVEX_0F73_REG_7,
1441   PREFIX_EVEX_0F74,
1442   PREFIX_EVEX_0F75,
1443   PREFIX_EVEX_0F76,
1444   PREFIX_EVEX_0F78,
1445   PREFIX_EVEX_0F79,
1446   PREFIX_EVEX_0F7A,
1447   PREFIX_EVEX_0F7B,
1448   PREFIX_EVEX_0F7E,
1449   PREFIX_EVEX_0F7F,
1450   PREFIX_EVEX_0FC2,
1451   PREFIX_EVEX_0FC4,
1452   PREFIX_EVEX_0FC5,
1453   PREFIX_EVEX_0FD6,
1454   PREFIX_EVEX_0FDB,
1455   PREFIX_EVEX_0FDF,
1456   PREFIX_EVEX_0FE2,
1457   PREFIX_EVEX_0FE6,
1458   PREFIX_EVEX_0FE7,
1459   PREFIX_EVEX_0FEB,
1460   PREFIX_EVEX_0FEF,
1461   PREFIX_EVEX_0F380D,
1462   PREFIX_EVEX_0F3810,
1463   PREFIX_EVEX_0F3811,
1464   PREFIX_EVEX_0F3812,
1465   PREFIX_EVEX_0F3813,
1466   PREFIX_EVEX_0F3814,
1467   PREFIX_EVEX_0F3815,
1468   PREFIX_EVEX_0F3816,
1469   PREFIX_EVEX_0F3819,
1470   PREFIX_EVEX_0F381A,
1471   PREFIX_EVEX_0F381B,
1472   PREFIX_EVEX_0F381E,
1473   PREFIX_EVEX_0F381F,
1474   PREFIX_EVEX_0F3820,
1475   PREFIX_EVEX_0F3821,
1476   PREFIX_EVEX_0F3822,
1477   PREFIX_EVEX_0F3823,
1478   PREFIX_EVEX_0F3824,
1479   PREFIX_EVEX_0F3825,
1480   PREFIX_EVEX_0F3826,
1481   PREFIX_EVEX_0F3827,
1482   PREFIX_EVEX_0F3828,
1483   PREFIX_EVEX_0F3829,
1484   PREFIX_EVEX_0F382A,
1485   PREFIX_EVEX_0F382C,
1486   PREFIX_EVEX_0F382D,
1487   PREFIX_EVEX_0F3830,
1488   PREFIX_EVEX_0F3831,
1489   PREFIX_EVEX_0F3832,
1490   PREFIX_EVEX_0F3833,
1491   PREFIX_EVEX_0F3834,
1492   PREFIX_EVEX_0F3835,
1493   PREFIX_EVEX_0F3836,
1494   PREFIX_EVEX_0F3837,
1495   PREFIX_EVEX_0F3838,
1496   PREFIX_EVEX_0F3839,
1497   PREFIX_EVEX_0F383A,
1498   PREFIX_EVEX_0F383B,
1499   PREFIX_EVEX_0F383D,
1500   PREFIX_EVEX_0F383F,
1501   PREFIX_EVEX_0F3840,
1502   PREFIX_EVEX_0F3842,
1503   PREFIX_EVEX_0F3843,
1504   PREFIX_EVEX_0F3844,
1505   PREFIX_EVEX_0F3845,
1506   PREFIX_EVEX_0F3846,
1507   PREFIX_EVEX_0F3847,
1508   PREFIX_EVEX_0F384C,
1509   PREFIX_EVEX_0F384D,
1510   PREFIX_EVEX_0F384E,
1511   PREFIX_EVEX_0F384F,
1512   PREFIX_EVEX_0F3850,
1513   PREFIX_EVEX_0F3851,
1514   PREFIX_EVEX_0F3852,
1515   PREFIX_EVEX_0F3853,
1516   PREFIX_EVEX_0F3854,
1517   PREFIX_EVEX_0F3855,
1518   PREFIX_EVEX_0F3859,
1519   PREFIX_EVEX_0F385A,
1520   PREFIX_EVEX_0F385B,
1521   PREFIX_EVEX_0F3862,
1522   PREFIX_EVEX_0F3863,
1523   PREFIX_EVEX_0F3864,
1524   PREFIX_EVEX_0F3865,
1525   PREFIX_EVEX_0F3866,
1526   PREFIX_EVEX_0F3868,
1527   PREFIX_EVEX_0F3870,
1528   PREFIX_EVEX_0F3871,
1529   PREFIX_EVEX_0F3872,
1530   PREFIX_EVEX_0F3873,
1531   PREFIX_EVEX_0F3875,
1532   PREFIX_EVEX_0F3876,
1533   PREFIX_EVEX_0F3877,
1534   PREFIX_EVEX_0F387A,
1535   PREFIX_EVEX_0F387B,
1536   PREFIX_EVEX_0F387C,
1537   PREFIX_EVEX_0F387D,
1538   PREFIX_EVEX_0F387E,
1539   PREFIX_EVEX_0F387F,
1540   PREFIX_EVEX_0F3883,
1541   PREFIX_EVEX_0F3888,
1542   PREFIX_EVEX_0F3889,
1543   PREFIX_EVEX_0F388A,
1544   PREFIX_EVEX_0F388B,
1545   PREFIX_EVEX_0F388D,
1546   PREFIX_EVEX_0F388F,
1547   PREFIX_EVEX_0F3890,
1548   PREFIX_EVEX_0F3891,
1549   PREFIX_EVEX_0F3892,
1550   PREFIX_EVEX_0F3893,
1551   PREFIX_EVEX_0F389A,
1552   PREFIX_EVEX_0F389B,
1553   PREFIX_EVEX_0F38A0,
1554   PREFIX_EVEX_0F38A1,
1555   PREFIX_EVEX_0F38A2,
1556   PREFIX_EVEX_0F38A3,
1557   PREFIX_EVEX_0F38AA,
1558   PREFIX_EVEX_0F38AB,
1559   PREFIX_EVEX_0F38B4,
1560   PREFIX_EVEX_0F38B5,
1561   PREFIX_EVEX_0F38C4,
1562   PREFIX_EVEX_0F38C6_REG_1,
1563   PREFIX_EVEX_0F38C6_REG_2,
1564   PREFIX_EVEX_0F38C6_REG_5,
1565   PREFIX_EVEX_0F38C6_REG_6,
1566   PREFIX_EVEX_0F38C7_REG_1,
1567   PREFIX_EVEX_0F38C7_REG_2,
1568   PREFIX_EVEX_0F38C7_REG_5,
1569   PREFIX_EVEX_0F38C7_REG_6,
1570   PREFIX_EVEX_0F38C8,
1571   PREFIX_EVEX_0F38CA,
1572   PREFIX_EVEX_0F38CB,
1573   PREFIX_EVEX_0F38CC,
1574   PREFIX_EVEX_0F38CD,
1575
1576   PREFIX_EVEX_0F3A00,
1577   PREFIX_EVEX_0F3A01,
1578   PREFIX_EVEX_0F3A03,
1579   PREFIX_EVEX_0F3A05,
1580   PREFIX_EVEX_0F3A08,
1581   PREFIX_EVEX_0F3A09,
1582   PREFIX_EVEX_0F3A0A,
1583   PREFIX_EVEX_0F3A0B,
1584   PREFIX_EVEX_0F3A14,
1585   PREFIX_EVEX_0F3A15,
1586   PREFIX_EVEX_0F3A16,
1587   PREFIX_EVEX_0F3A17,
1588   PREFIX_EVEX_0F3A18,
1589   PREFIX_EVEX_0F3A19,
1590   PREFIX_EVEX_0F3A1A,
1591   PREFIX_EVEX_0F3A1B,
1592   PREFIX_EVEX_0F3A1E,
1593   PREFIX_EVEX_0F3A1F,
1594   PREFIX_EVEX_0F3A20,
1595   PREFIX_EVEX_0F3A21,
1596   PREFIX_EVEX_0F3A22,
1597   PREFIX_EVEX_0F3A23,
1598   PREFIX_EVEX_0F3A25,
1599   PREFIX_EVEX_0F3A26,
1600   PREFIX_EVEX_0F3A27,
1601   PREFIX_EVEX_0F3A38,
1602   PREFIX_EVEX_0F3A39,
1603   PREFIX_EVEX_0F3A3A,
1604   PREFIX_EVEX_0F3A3B,
1605   PREFIX_EVEX_0F3A3E,
1606   PREFIX_EVEX_0F3A3F,
1607   PREFIX_EVEX_0F3A42,
1608   PREFIX_EVEX_0F3A43,
1609   PREFIX_EVEX_0F3A50,
1610   PREFIX_EVEX_0F3A51,
1611   PREFIX_EVEX_0F3A54,
1612   PREFIX_EVEX_0F3A55,
1613   PREFIX_EVEX_0F3A56,
1614   PREFIX_EVEX_0F3A57,
1615   PREFIX_EVEX_0F3A66,
1616   PREFIX_EVEX_0F3A67,
1617   PREFIX_EVEX_0F3A70,
1618   PREFIX_EVEX_0F3A71,
1619   PREFIX_EVEX_0F3A72,
1620   PREFIX_EVEX_0F3A73,
1621 };
1622
1623 enum
1624 {
1625   X86_64_06 = 0,
1626   X86_64_07,
1627   X86_64_0E,
1628   X86_64_16,
1629   X86_64_17,
1630   X86_64_1E,
1631   X86_64_1F,
1632   X86_64_27,
1633   X86_64_2F,
1634   X86_64_37,
1635   X86_64_3F,
1636   X86_64_60,
1637   X86_64_61,
1638   X86_64_62,
1639   X86_64_63,
1640   X86_64_6D,
1641   X86_64_6F,
1642   X86_64_82,
1643   X86_64_9A,
1644   X86_64_C2,
1645   X86_64_C3,
1646   X86_64_C4,
1647   X86_64_C5,
1648   X86_64_CE,
1649   X86_64_D4,
1650   X86_64_D5,
1651   X86_64_E8,
1652   X86_64_E9,
1653   X86_64_EA,
1654   X86_64_0F01_REG_0,
1655   X86_64_0F01_REG_1,
1656   X86_64_0F01_REG_2,
1657   X86_64_0F01_REG_3,
1658   X86_64_VEX_0F3849,
1659   X86_64_VEX_0F384B,
1660   X86_64_VEX_0F385C,
1661   X86_64_VEX_0F385E
1662 };
1663
1664 enum
1665 {
1666   THREE_BYTE_0F38 = 0,
1667   THREE_BYTE_0F3A
1668 };
1669
1670 enum
1671 {
1672   XOP_08 = 0,
1673   XOP_09,
1674   XOP_0A
1675 };
1676
1677 enum
1678 {
1679   VEX_0F = 0,
1680   VEX_0F38,
1681   VEX_0F3A
1682 };
1683
1684 enum
1685 {
1686   EVEX_0F = 0,
1687   EVEX_0F38,
1688   EVEX_0F3A
1689 };
1690
1691 enum
1692 {
1693   VEX_LEN_0F12_P_0_M_0 = 0,
1694   VEX_LEN_0F12_P_0_M_1,
1695 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1696   VEX_LEN_0F13_M_0,
1697   VEX_LEN_0F16_P_0_M_0,
1698   VEX_LEN_0F16_P_0_M_1,
1699 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1700   VEX_LEN_0F17_M_0,
1701   VEX_LEN_0F41_P_0,
1702   VEX_LEN_0F41_P_2,
1703   VEX_LEN_0F42_P_0,
1704   VEX_LEN_0F42_P_2,
1705   VEX_LEN_0F44_P_0,
1706   VEX_LEN_0F44_P_2,
1707   VEX_LEN_0F45_P_0,
1708   VEX_LEN_0F45_P_2,
1709   VEX_LEN_0F46_P_0,
1710   VEX_LEN_0F46_P_2,
1711   VEX_LEN_0F47_P_0,
1712   VEX_LEN_0F47_P_2,
1713   VEX_LEN_0F4A_P_0,
1714   VEX_LEN_0F4A_P_2,
1715   VEX_LEN_0F4B_P_0,
1716   VEX_LEN_0F4B_P_2,
1717   VEX_LEN_0F6E_P_2,
1718   VEX_LEN_0F77_P_0,
1719   VEX_LEN_0F7E_P_1,
1720   VEX_LEN_0F7E_P_2,
1721   VEX_LEN_0F90_P_0,
1722   VEX_LEN_0F90_P_2,
1723   VEX_LEN_0F91_P_0,
1724   VEX_LEN_0F91_P_2,
1725   VEX_LEN_0F92_P_0,
1726   VEX_LEN_0F92_P_2,
1727   VEX_LEN_0F92_P_3,
1728   VEX_LEN_0F93_P_0,
1729   VEX_LEN_0F93_P_2,
1730   VEX_LEN_0F93_P_3,
1731   VEX_LEN_0F98_P_0,
1732   VEX_LEN_0F98_P_2,
1733   VEX_LEN_0F99_P_0,
1734   VEX_LEN_0F99_P_2,
1735   VEX_LEN_0FAE_R_2_M_0,
1736   VEX_LEN_0FAE_R_3_M_0,
1737   VEX_LEN_0FC4_P_2,
1738   VEX_LEN_0FC5_P_2,
1739   VEX_LEN_0FD6_P_2,
1740   VEX_LEN_0FF7_P_2,
1741   VEX_LEN_0F3816_P_2,
1742   VEX_LEN_0F3819_P_2,
1743   VEX_LEN_0F381A_P_2_M_0,
1744   VEX_LEN_0F3836_P_2,
1745   VEX_LEN_0F3841_P_2,
1746   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1747   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1748   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1749   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1750   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1751   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1752   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1753   VEX_LEN_0F385A_P_2_M_0,
1754   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1755   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1756   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1757   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1758   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1759   VEX_LEN_0F38DB_P_2,
1760   VEX_LEN_0F38F2_P_0,
1761   VEX_LEN_0F38F3_R_1_P_0,
1762   VEX_LEN_0F38F3_R_2_P_0,
1763   VEX_LEN_0F38F3_R_3_P_0,
1764   VEX_LEN_0F38F5_P_0,
1765   VEX_LEN_0F38F5_P_1,
1766   VEX_LEN_0F38F5_P_3,
1767   VEX_LEN_0F38F6_P_3,
1768   VEX_LEN_0F38F7_P_0,
1769   VEX_LEN_0F38F7_P_1,
1770   VEX_LEN_0F38F7_P_2,
1771   VEX_LEN_0F38F7_P_3,
1772   VEX_LEN_0F3A00_P_2,
1773   VEX_LEN_0F3A01_P_2,
1774   VEX_LEN_0F3A06_P_2,
1775   VEX_LEN_0F3A14_P_2,
1776   VEX_LEN_0F3A15_P_2,
1777   VEX_LEN_0F3A16_P_2,
1778   VEX_LEN_0F3A17_P_2,
1779   VEX_LEN_0F3A18_P_2,
1780   VEX_LEN_0F3A19_P_2,
1781   VEX_LEN_0F3A20_P_2,
1782   VEX_LEN_0F3A21_P_2,
1783   VEX_LEN_0F3A22_P_2,
1784   VEX_LEN_0F3A30_P_2,
1785   VEX_LEN_0F3A31_P_2,
1786   VEX_LEN_0F3A32_P_2,
1787   VEX_LEN_0F3A33_P_2,
1788   VEX_LEN_0F3A38_P_2,
1789   VEX_LEN_0F3A39_P_2,
1790   VEX_LEN_0F3A41_P_2,
1791   VEX_LEN_0F3A46_P_2,
1792   VEX_LEN_0F3A60_P_2,
1793   VEX_LEN_0F3A61_P_2,
1794   VEX_LEN_0F3A62_P_2,
1795   VEX_LEN_0F3A63_P_2,
1796   VEX_LEN_0F3ADF_P_2,
1797   VEX_LEN_0F3AF0_P_3,
1798   VEX_LEN_0FXOP_08_85,
1799   VEX_LEN_0FXOP_08_86,
1800   VEX_LEN_0FXOP_08_87,
1801   VEX_LEN_0FXOP_08_8E,
1802   VEX_LEN_0FXOP_08_8F,
1803   VEX_LEN_0FXOP_08_95,
1804   VEX_LEN_0FXOP_08_96,
1805   VEX_LEN_0FXOP_08_97,
1806   VEX_LEN_0FXOP_08_9E,
1807   VEX_LEN_0FXOP_08_9F,
1808   VEX_LEN_0FXOP_08_A3,
1809   VEX_LEN_0FXOP_08_A6,
1810   VEX_LEN_0FXOP_08_B6,
1811   VEX_LEN_0FXOP_08_C0,
1812   VEX_LEN_0FXOP_08_C1,
1813   VEX_LEN_0FXOP_08_C2,
1814   VEX_LEN_0FXOP_08_C3,
1815   VEX_LEN_0FXOP_08_CC,
1816   VEX_LEN_0FXOP_08_CD,
1817   VEX_LEN_0FXOP_08_CE,
1818   VEX_LEN_0FXOP_08_CF,
1819   VEX_LEN_0FXOP_08_EC,
1820   VEX_LEN_0FXOP_08_ED,
1821   VEX_LEN_0FXOP_08_EE,
1822   VEX_LEN_0FXOP_08_EF,
1823   VEX_LEN_0FXOP_09_01,
1824   VEX_LEN_0FXOP_09_02,
1825   VEX_LEN_0FXOP_09_12_M_1,
1826   VEX_LEN_0FXOP_09_82_W_0,
1827   VEX_LEN_0FXOP_09_83_W_0,
1828   VEX_LEN_0FXOP_09_90,
1829   VEX_LEN_0FXOP_09_91,
1830   VEX_LEN_0FXOP_09_92,
1831   VEX_LEN_0FXOP_09_93,
1832   VEX_LEN_0FXOP_09_94,
1833   VEX_LEN_0FXOP_09_95,
1834   VEX_LEN_0FXOP_09_96,
1835   VEX_LEN_0FXOP_09_97,
1836   VEX_LEN_0FXOP_09_98,
1837   VEX_LEN_0FXOP_09_99,
1838   VEX_LEN_0FXOP_09_9A,
1839   VEX_LEN_0FXOP_09_9B,
1840   VEX_LEN_0FXOP_09_C1,
1841   VEX_LEN_0FXOP_09_C2,
1842   VEX_LEN_0FXOP_09_C3,
1843   VEX_LEN_0FXOP_09_C6,
1844   VEX_LEN_0FXOP_09_C7,
1845   VEX_LEN_0FXOP_09_CB,
1846   VEX_LEN_0FXOP_09_D1,
1847   VEX_LEN_0FXOP_09_D2,
1848   VEX_LEN_0FXOP_09_D3,
1849   VEX_LEN_0FXOP_09_D6,
1850   VEX_LEN_0FXOP_09_D7,
1851   VEX_LEN_0FXOP_09_DB,
1852   VEX_LEN_0FXOP_09_E1,
1853   VEX_LEN_0FXOP_09_E2,
1854   VEX_LEN_0FXOP_09_E3,
1855   VEX_LEN_0FXOP_0A_12,
1856 };
1857
1858 enum
1859 {
1860   EVEX_LEN_0F6E_P_2 = 0,
1861   EVEX_LEN_0F7E_P_1,
1862   EVEX_LEN_0F7E_P_2,
1863   EVEX_LEN_0FC4_P_2,
1864   EVEX_LEN_0FC5_P_2,
1865   EVEX_LEN_0FD6_P_2,
1866   EVEX_LEN_0F3816_P_2,
1867   EVEX_LEN_0F3819_P_2_W_0,
1868   EVEX_LEN_0F3819_P_2_W_1,
1869   EVEX_LEN_0F381A_P_2_W_0_M_0,
1870   EVEX_LEN_0F381A_P_2_W_1_M_0,
1871   EVEX_LEN_0F381B_P_2_W_0_M_0,
1872   EVEX_LEN_0F381B_P_2_W_1_M_0,
1873   EVEX_LEN_0F3836_P_2,
1874   EVEX_LEN_0F385A_P_2_W_0_M_0,
1875   EVEX_LEN_0F385A_P_2_W_1_M_0,
1876   EVEX_LEN_0F385B_P_2_W_0_M_0,
1877   EVEX_LEN_0F385B_P_2_W_1_M_0,
1878   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1879   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1880   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1881   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1882   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1883   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1884   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1885   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1886   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1887   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1888   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1889   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1890   EVEX_LEN_0F3A00_P_2_W_1,
1891   EVEX_LEN_0F3A01_P_2_W_1,
1892   EVEX_LEN_0F3A14_P_2,
1893   EVEX_LEN_0F3A15_P_2,
1894   EVEX_LEN_0F3A16_P_2,
1895   EVEX_LEN_0F3A17_P_2,
1896   EVEX_LEN_0F3A18_P_2_W_0,
1897   EVEX_LEN_0F3A18_P_2_W_1,
1898   EVEX_LEN_0F3A19_P_2_W_0,
1899   EVEX_LEN_0F3A19_P_2_W_1,
1900   EVEX_LEN_0F3A1A_P_2_W_0,
1901   EVEX_LEN_0F3A1A_P_2_W_1,
1902   EVEX_LEN_0F3A1B_P_2_W_0,
1903   EVEX_LEN_0F3A1B_P_2_W_1,
1904   EVEX_LEN_0F3A20_P_2,
1905   EVEX_LEN_0F3A21_P_2_W_0,
1906   EVEX_LEN_0F3A22_P_2,
1907   EVEX_LEN_0F3A23_P_2_W_0,
1908   EVEX_LEN_0F3A23_P_2_W_1,
1909   EVEX_LEN_0F3A38_P_2_W_0,
1910   EVEX_LEN_0F3A38_P_2_W_1,
1911   EVEX_LEN_0F3A39_P_2_W_0,
1912   EVEX_LEN_0F3A39_P_2_W_1,
1913   EVEX_LEN_0F3A3A_P_2_W_0,
1914   EVEX_LEN_0F3A3A_P_2_W_1,
1915   EVEX_LEN_0F3A3B_P_2_W_0,
1916   EVEX_LEN_0F3A3B_P_2_W_1,
1917   EVEX_LEN_0F3A43_P_2_W_0,
1918   EVEX_LEN_0F3A43_P_2_W_1
1919 };
1920
1921 enum
1922 {
1923   VEX_W_0F41_P_0_LEN_1 = 0,
1924   VEX_W_0F41_P_2_LEN_1,
1925   VEX_W_0F42_P_0_LEN_1,
1926   VEX_W_0F42_P_2_LEN_1,
1927   VEX_W_0F44_P_0_LEN_0,
1928   VEX_W_0F44_P_2_LEN_0,
1929   VEX_W_0F45_P_0_LEN_1,
1930   VEX_W_0F45_P_2_LEN_1,
1931   VEX_W_0F46_P_0_LEN_1,
1932   VEX_W_0F46_P_2_LEN_1,
1933   VEX_W_0F47_P_0_LEN_1,
1934   VEX_W_0F47_P_2_LEN_1,
1935   VEX_W_0F4A_P_0_LEN_1,
1936   VEX_W_0F4A_P_2_LEN_1,
1937   VEX_W_0F4B_P_0_LEN_1,
1938   VEX_W_0F4B_P_2_LEN_1,
1939   VEX_W_0F90_P_0_LEN_0,
1940   VEX_W_0F90_P_2_LEN_0,
1941   VEX_W_0F91_P_0_LEN_0,
1942   VEX_W_0F91_P_2_LEN_0,
1943   VEX_W_0F92_P_0_LEN_0,
1944   VEX_W_0F92_P_2_LEN_0,
1945   VEX_W_0F93_P_0_LEN_0,
1946   VEX_W_0F93_P_2_LEN_0,
1947   VEX_W_0F98_P_0_LEN_0,
1948   VEX_W_0F98_P_2_LEN_0,
1949   VEX_W_0F99_P_0_LEN_0,
1950   VEX_W_0F99_P_2_LEN_0,
1951   VEX_W_0F380C_P_2,
1952   VEX_W_0F380D_P_2,
1953   VEX_W_0F380E_P_2,
1954   VEX_W_0F380F_P_2,
1955   VEX_W_0F3813_P_2,
1956   VEX_W_0F3816_P_2,
1957   VEX_W_0F3818_P_2,
1958   VEX_W_0F3819_P_2,
1959   VEX_W_0F381A_P_2_M_0_L_0,
1960   VEX_W_0F382C_P_2_M_0,
1961   VEX_W_0F382D_P_2_M_0,
1962   VEX_W_0F382E_P_2_M_0,
1963   VEX_W_0F382F_P_2_M_0,
1964   VEX_W_0F3836_P_2,
1965   VEX_W_0F3846_P_2,
1966   VEX_W_0F3849_X86_64_P_0,
1967   VEX_W_0F3849_X86_64_P_2,
1968   VEX_W_0F3849_X86_64_P_3,
1969   VEX_W_0F384B_X86_64_P_1,
1970   VEX_W_0F384B_X86_64_P_2,
1971   VEX_W_0F384B_X86_64_P_3,
1972   VEX_W_0F3858_P_2,
1973   VEX_W_0F3859_P_2,
1974   VEX_W_0F385A_P_2_M_0_L_0,
1975   VEX_W_0F385C_X86_64_P_1,
1976   VEX_W_0F385E_X86_64_P_0,
1977   VEX_W_0F385E_X86_64_P_1,
1978   VEX_W_0F385E_X86_64_P_2,
1979   VEX_W_0F385E_X86_64_P_3,
1980   VEX_W_0F3878_P_2,
1981   VEX_W_0F3879_P_2,
1982   VEX_W_0F38CF_P_2,
1983   VEX_W_0F3A00_P_2,
1984   VEX_W_0F3A01_P_2,
1985   VEX_W_0F3A02_P_2,
1986   VEX_W_0F3A04_P_2,
1987   VEX_W_0F3A05_P_2,
1988   VEX_W_0F3A06_P_2_L_0,
1989   VEX_W_0F3A18_P_2_L_0,
1990   VEX_W_0F3A19_P_2_L_0,
1991   VEX_W_0F3A1D_P_2,
1992   VEX_W_0F3A30_P_2_LEN_0,
1993   VEX_W_0F3A31_P_2_LEN_0,
1994   VEX_W_0F3A32_P_2_LEN_0,
1995   VEX_W_0F3A33_P_2_LEN_0,
1996   VEX_W_0F3A38_P_2_L_0,
1997   VEX_W_0F3A39_P_2_L_0,
1998   VEX_W_0F3A46_P_2_L_0,
1999   VEX_W_0F3A4A_P_2,
2000   VEX_W_0F3A4B_P_2,
2001   VEX_W_0F3A4C_P_2,
2002   VEX_W_0F3ACE_P_2,
2003   VEX_W_0F3ACF_P_2,
2004
2005   VEX_W_0FXOP_08_85_L_0,
2006   VEX_W_0FXOP_08_86_L_0,
2007   VEX_W_0FXOP_08_87_L_0,
2008   VEX_W_0FXOP_08_8E_L_0,
2009   VEX_W_0FXOP_08_8F_L_0,
2010   VEX_W_0FXOP_08_95_L_0,
2011   VEX_W_0FXOP_08_96_L_0,
2012   VEX_W_0FXOP_08_97_L_0,
2013   VEX_W_0FXOP_08_9E_L_0,
2014   VEX_W_0FXOP_08_9F_L_0,
2015   VEX_W_0FXOP_08_A6_L_0,
2016   VEX_W_0FXOP_08_B6_L_0,
2017   VEX_W_0FXOP_08_C0_L_0,
2018   VEX_W_0FXOP_08_C1_L_0,
2019   VEX_W_0FXOP_08_C2_L_0,
2020   VEX_W_0FXOP_08_C3_L_0,
2021   VEX_W_0FXOP_08_CC_L_0,
2022   VEX_W_0FXOP_08_CD_L_0,
2023   VEX_W_0FXOP_08_CE_L_0,
2024   VEX_W_0FXOP_08_CF_L_0,
2025   VEX_W_0FXOP_08_EC_L_0,
2026   VEX_W_0FXOP_08_ED_L_0,
2027   VEX_W_0FXOP_08_EE_L_0,
2028   VEX_W_0FXOP_08_EF_L_0,
2029
2030   VEX_W_0FXOP_09_80,
2031   VEX_W_0FXOP_09_81,
2032   VEX_W_0FXOP_09_82,
2033   VEX_W_0FXOP_09_83,
2034   VEX_W_0FXOP_09_C1_L_0,
2035   VEX_W_0FXOP_09_C2_L_0,
2036   VEX_W_0FXOP_09_C3_L_0,
2037   VEX_W_0FXOP_09_C6_L_0,
2038   VEX_W_0FXOP_09_C7_L_0,
2039   VEX_W_0FXOP_09_CB_L_0,
2040   VEX_W_0FXOP_09_D1_L_0,
2041   VEX_W_0FXOP_09_D2_L_0,
2042   VEX_W_0FXOP_09_D3_L_0,
2043   VEX_W_0FXOP_09_D6_L_0,
2044   VEX_W_0FXOP_09_D7_L_0,
2045   VEX_W_0FXOP_09_DB_L_0,
2046   VEX_W_0FXOP_09_E1_L_0,
2047   VEX_W_0FXOP_09_E2_L_0,
2048   VEX_W_0FXOP_09_E3_L_0,
2049
2050   EVEX_W_0F10_P_1,
2051   EVEX_W_0F10_P_3,
2052   EVEX_W_0F11_P_1,
2053   EVEX_W_0F11_P_3,
2054   EVEX_W_0F12_P_0_M_1,
2055   EVEX_W_0F12_P_1,
2056   EVEX_W_0F12_P_3,
2057   EVEX_W_0F16_P_0_M_1,
2058   EVEX_W_0F16_P_1,
2059   EVEX_W_0F2A_P_3,
2060   EVEX_W_0F51_P_1,
2061   EVEX_W_0F51_P_3,
2062   EVEX_W_0F58_P_1,
2063   EVEX_W_0F58_P_3,
2064   EVEX_W_0F59_P_1,
2065   EVEX_W_0F59_P_3,
2066   EVEX_W_0F5A_P_0,
2067   EVEX_W_0F5A_P_1,
2068   EVEX_W_0F5A_P_2,
2069   EVEX_W_0F5A_P_3,
2070   EVEX_W_0F5B_P_0,
2071   EVEX_W_0F5B_P_1,
2072   EVEX_W_0F5B_P_2,
2073   EVEX_W_0F5C_P_1,
2074   EVEX_W_0F5C_P_3,
2075   EVEX_W_0F5D_P_1,
2076   EVEX_W_0F5D_P_3,
2077   EVEX_W_0F5E_P_1,
2078   EVEX_W_0F5E_P_3,
2079   EVEX_W_0F5F_P_1,
2080   EVEX_W_0F5F_P_3,
2081   EVEX_W_0F62,
2082   EVEX_W_0F66_P_2,
2083   EVEX_W_0F6A,
2084   EVEX_W_0F6B,
2085   EVEX_W_0F6C,
2086   EVEX_W_0F6D,
2087   EVEX_W_0F6F_P_1,
2088   EVEX_W_0F6F_P_2,
2089   EVEX_W_0F6F_P_3,
2090   EVEX_W_0F70_P_2,
2091   EVEX_W_0F72_R_2_P_2,
2092   EVEX_W_0F72_R_6_P_2,
2093   EVEX_W_0F73_R_2_P_2,
2094   EVEX_W_0F73_R_6_P_2,
2095   EVEX_W_0F76_P_2,
2096   EVEX_W_0F78_P_0,
2097   EVEX_W_0F78_P_2,
2098   EVEX_W_0F79_P_0,
2099   EVEX_W_0F79_P_2,
2100   EVEX_W_0F7A_P_1,
2101   EVEX_W_0F7A_P_2,
2102   EVEX_W_0F7A_P_3,
2103   EVEX_W_0F7B_P_2,
2104   EVEX_W_0F7B_P_3,
2105   EVEX_W_0F7E_P_1,
2106   EVEX_W_0F7F_P_1,
2107   EVEX_W_0F7F_P_2,
2108   EVEX_W_0F7F_P_3,
2109   EVEX_W_0FC2_P_1,
2110   EVEX_W_0FC2_P_3,
2111   EVEX_W_0FD2,
2112   EVEX_W_0FD3,
2113   EVEX_W_0FD4,
2114   EVEX_W_0FD6_P_2,
2115   EVEX_W_0FE6_P_1,
2116   EVEX_W_0FE6_P_2,
2117   EVEX_W_0FE6_P_3,
2118   EVEX_W_0FE7_P_2,
2119   EVEX_W_0FF2,
2120   EVEX_W_0FF3,
2121   EVEX_W_0FF4,
2122   EVEX_W_0FFA,
2123   EVEX_W_0FFB,
2124   EVEX_W_0FFE,
2125   EVEX_W_0F380D_P_2,
2126   EVEX_W_0F3810_P_1,
2127   EVEX_W_0F3810_P_2,
2128   EVEX_W_0F3811_P_1,
2129   EVEX_W_0F3811_P_2,
2130   EVEX_W_0F3812_P_1,
2131   EVEX_W_0F3812_P_2,
2132   EVEX_W_0F3813_P_1,
2133   EVEX_W_0F3813_P_2,
2134   EVEX_W_0F3814_P_1,
2135   EVEX_W_0F3815_P_1,
2136   EVEX_W_0F3819_P_2,
2137   EVEX_W_0F381A_P_2,
2138   EVEX_W_0F381B_P_2,
2139   EVEX_W_0F381E_P_2,
2140   EVEX_W_0F381F_P_2,
2141   EVEX_W_0F3820_P_1,
2142   EVEX_W_0F3821_P_1,
2143   EVEX_W_0F3822_P_1,
2144   EVEX_W_0F3823_P_1,
2145   EVEX_W_0F3824_P_1,
2146   EVEX_W_0F3825_P_1,
2147   EVEX_W_0F3825_P_2,
2148   EVEX_W_0F3828_P_2,
2149   EVEX_W_0F3829_P_2,
2150   EVEX_W_0F382A_P_1,
2151   EVEX_W_0F382A_P_2,
2152   EVEX_W_0F382B,
2153   EVEX_W_0F3830_P_1,
2154   EVEX_W_0F3831_P_1,
2155   EVEX_W_0F3832_P_1,
2156   EVEX_W_0F3833_P_1,
2157   EVEX_W_0F3834_P_1,
2158   EVEX_W_0F3835_P_1,
2159   EVEX_W_0F3835_P_2,
2160   EVEX_W_0F3837_P_2,
2161   EVEX_W_0F383A_P_1,
2162   EVEX_W_0F3852_P_1,
2163   EVEX_W_0F3859_P_2,
2164   EVEX_W_0F385A_P_2,
2165   EVEX_W_0F385B_P_2,
2166   EVEX_W_0F3870_P_2,
2167   EVEX_W_0F3872_P_1,
2168   EVEX_W_0F3872_P_2,
2169   EVEX_W_0F3872_P_3,
2170   EVEX_W_0F387A_P_2,
2171   EVEX_W_0F387B_P_2,
2172   EVEX_W_0F3883_P_2,
2173   EVEX_W_0F3891_P_2,
2174   EVEX_W_0F3893_P_2,
2175   EVEX_W_0F38A1_P_2,
2176   EVEX_W_0F38A3_P_2,
2177   EVEX_W_0F38C7_R_1_P_2,
2178   EVEX_W_0F38C7_R_2_P_2,
2179   EVEX_W_0F38C7_R_5_P_2,
2180   EVEX_W_0F38C7_R_6_P_2,
2181
2182   EVEX_W_0F3A00_P_2,
2183   EVEX_W_0F3A01_P_2,
2184   EVEX_W_0F3A05_P_2,
2185   EVEX_W_0F3A08_P_2,
2186   EVEX_W_0F3A09_P_2,
2187   EVEX_W_0F3A0A_P_2,
2188   EVEX_W_0F3A0B_P_2,
2189   EVEX_W_0F3A18_P_2,
2190   EVEX_W_0F3A19_P_2,
2191   EVEX_W_0F3A1A_P_2,
2192   EVEX_W_0F3A1B_P_2,
2193   EVEX_W_0F3A21_P_2,
2194   EVEX_W_0F3A23_P_2,
2195   EVEX_W_0F3A38_P_2,
2196   EVEX_W_0F3A39_P_2,
2197   EVEX_W_0F3A3A_P_2,
2198   EVEX_W_0F3A3B_P_2,
2199   EVEX_W_0F3A42_P_2,
2200   EVEX_W_0F3A43_P_2,
2201   EVEX_W_0F3A70_P_2,
2202   EVEX_W_0F3A72_P_2,
2203 };
2204
2205 typedef void (*op_rtn) (int bytemode, int sizeflag);
2206
2207 struct dis386 {
2208   const char *name;
2209   struct
2210     {
2211       op_rtn rtn;
2212       int bytemode;
2213     } op[MAX_OPERANDS];
2214   unsigned int prefix_requirement;
2215 };
2216
2217 /* Upper case letters in the instruction names here are macros.
2218    'A' => print 'b' if no register operands or suffix_always is true
2219    'B' => print 'b' if suffix_always is true
2220    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2221           size prefix
2222    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2223           suffix_always is true
2224    'E' => print 'e' if 32-bit form of jcxz
2225    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2226    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2227    'H' => print ",pt" or ",pn" branch hint
2228    'I' unused.
2229    'J' unused.
2230    'K' => print 'd' or 'q' if rex prefix is present.
2231    'L' => print 'l' if suffix_always is true
2232    'M' => print 'r' if intel_mnemonic is false.
2233    'N' => print 'n' if instruction has no wait "prefix"
2234    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2235    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2236           or suffix_always is true.  print 'q' if rex prefix is present.
2237    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2238           is true
2239    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2240    'S' => print 'w', 'l' or 'q' if suffix_always is true
2241    'T' => print 'q' in 64bit mode if instruction has no operand size
2242           prefix and behave as 'P' otherwise
2243    'U' => print 'q' in 64bit mode if instruction has no operand size
2244           prefix and behave as 'Q' otherwise
2245    'V' => print 'q' in 64bit mode if instruction has no operand size
2246           prefix and behave as 'S' otherwise
2247    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2248    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2249    'Y' unused.
2250    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2251    '!' => change condition from true to false or from false to true.
2252    '%' => add 1 upper case letter to the macro.
2253    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2254           prefix or suffix_always is true (lcall/ljmp).
2255    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2256           on operand size prefix.
2257    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2258           has no operand size prefix for AMD64 ISA, behave as 'P'
2259           otherwise
2260
2261    2 upper case letter macros:
2262    "XY" => print 'x' or 'y' if suffix_always is true or no register
2263            operands and no broadcast.
2264    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2265            register operands and no broadcast.
2266    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2267    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2268            being false, or no operand at all in 64bit mode, or if suffix_always
2269            is true.
2270    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2271    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2272    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2273    "DQ" => print 'd' or 'q' depending on the VEX.W bit
2274    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2275    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2276            an operand size prefix, or suffix_always is true.  print
2277            'q' if rex prefix is present.
2278
2279    Many of the above letters print nothing in Intel mode.  See "putop"
2280    for the details.
2281
2282    Braces '{' and '}', and vertical bars '|', indicate alternative
2283    mnemonic strings for AT&T and Intel.  */
2284
2285 static const struct dis386 dis386[] = {
2286   /* 00 */
2287   { "addB",             { Ebh1, Gb }, 0 },
2288   { "addS",             { Evh1, Gv }, 0 },
2289   { "addB",             { Gb, EbS }, 0 },
2290   { "addS",             { Gv, EvS }, 0 },
2291   { "addB",             { AL, Ib }, 0 },
2292   { "addS",             { eAX, Iv }, 0 },
2293   { X86_64_TABLE (X86_64_06) },
2294   { X86_64_TABLE (X86_64_07) },
2295   /* 08 */
2296   { "orB",              { Ebh1, Gb }, 0 },
2297   { "orS",              { Evh1, Gv }, 0 },
2298   { "orB",              { Gb, EbS }, 0 },
2299   { "orS",              { Gv, EvS }, 0 },
2300   { "orB",              { AL, Ib }, 0 },
2301   { "orS",              { eAX, Iv }, 0 },
2302   { X86_64_TABLE (X86_64_0E) },
2303   { Bad_Opcode },       /* 0x0f extended opcode escape */
2304   /* 10 */
2305   { "adcB",             { Ebh1, Gb }, 0 },
2306   { "adcS",             { Evh1, Gv }, 0 },
2307   { "adcB",             { Gb, EbS }, 0 },
2308   { "adcS",             { Gv, EvS }, 0 },
2309   { "adcB",             { AL, Ib }, 0 },
2310   { "adcS",             { eAX, Iv }, 0 },
2311   { X86_64_TABLE (X86_64_16) },
2312   { X86_64_TABLE (X86_64_17) },
2313   /* 18 */
2314   { "sbbB",             { Ebh1, Gb }, 0 },
2315   { "sbbS",             { Evh1, Gv }, 0 },
2316   { "sbbB",             { Gb, EbS }, 0 },
2317   { "sbbS",             { Gv, EvS }, 0 },
2318   { "sbbB",             { AL, Ib }, 0 },
2319   { "sbbS",             { eAX, Iv }, 0 },
2320   { X86_64_TABLE (X86_64_1E) },
2321   { X86_64_TABLE (X86_64_1F) },
2322   /* 20 */
2323   { "andB",             { Ebh1, Gb }, 0 },
2324   { "andS",             { Evh1, Gv }, 0 },
2325   { "andB",             { Gb, EbS }, 0 },
2326   { "andS",             { Gv, EvS }, 0 },
2327   { "andB",             { AL, Ib }, 0 },
2328   { "andS",             { eAX, Iv }, 0 },
2329   { Bad_Opcode },       /* SEG ES prefix */
2330   { X86_64_TABLE (X86_64_27) },
2331   /* 28 */
2332   { "subB",             { Ebh1, Gb }, 0 },
2333   { "subS",             { Evh1, Gv }, 0 },
2334   { "subB",             { Gb, EbS }, 0 },
2335   { "subS",             { Gv, EvS }, 0 },
2336   { "subB",             { AL, Ib }, 0 },
2337   { "subS",             { eAX, Iv }, 0 },
2338   { Bad_Opcode },       /* SEG CS prefix */
2339   { X86_64_TABLE (X86_64_2F) },
2340   /* 30 */
2341   { "xorB",             { Ebh1, Gb }, 0 },
2342   { "xorS",             { Evh1, Gv }, 0 },
2343   { "xorB",             { Gb, EbS }, 0 },
2344   { "xorS",             { Gv, EvS }, 0 },
2345   { "xorB",             { AL, Ib }, 0 },
2346   { "xorS",             { eAX, Iv }, 0 },
2347   { Bad_Opcode },       /* SEG SS prefix */
2348   { X86_64_TABLE (X86_64_37) },
2349   /* 38 */
2350   { "cmpB",             { Eb, Gb }, 0 },
2351   { "cmpS",             { Ev, Gv }, 0 },
2352   { "cmpB",             { Gb, EbS }, 0 },
2353   { "cmpS",             { Gv, EvS }, 0 },
2354   { "cmpB",             { AL, Ib }, 0 },
2355   { "cmpS",             { eAX, Iv }, 0 },
2356   { Bad_Opcode },       /* SEG DS prefix */
2357   { X86_64_TABLE (X86_64_3F) },
2358   /* 40 */
2359   { "inc{S|}",          { RMeAX }, 0 },
2360   { "inc{S|}",          { RMeCX }, 0 },
2361   { "inc{S|}",          { RMeDX }, 0 },
2362   { "inc{S|}",          { RMeBX }, 0 },
2363   { "inc{S|}",          { RMeSP }, 0 },
2364   { "inc{S|}",          { RMeBP }, 0 },
2365   { "inc{S|}",          { RMeSI }, 0 },
2366   { "inc{S|}",          { RMeDI }, 0 },
2367   /* 48 */
2368   { "dec{S|}",          { RMeAX }, 0 },
2369   { "dec{S|}",          { RMeCX }, 0 },
2370   { "dec{S|}",          { RMeDX }, 0 },
2371   { "dec{S|}",          { RMeBX }, 0 },
2372   { "dec{S|}",          { RMeSP }, 0 },
2373   { "dec{S|}",          { RMeBP }, 0 },
2374   { "dec{S|}",          { RMeSI }, 0 },
2375   { "dec{S|}",          { RMeDI }, 0 },
2376   /* 50 */
2377   { "pushV",            { RMrAX }, 0 },
2378   { "pushV",            { RMrCX }, 0 },
2379   { "pushV",            { RMrDX }, 0 },
2380   { "pushV",            { RMrBX }, 0 },
2381   { "pushV",            { RMrSP }, 0 },
2382   { "pushV",            { RMrBP }, 0 },
2383   { "pushV",            { RMrSI }, 0 },
2384   { "pushV",            { RMrDI }, 0 },
2385   /* 58 */
2386   { "popV",             { RMrAX }, 0 },
2387   { "popV",             { RMrCX }, 0 },
2388   { "popV",             { RMrDX }, 0 },
2389   { "popV",             { RMrBX }, 0 },
2390   { "popV",             { RMrSP }, 0 },
2391   { "popV",             { RMrBP }, 0 },
2392   { "popV",             { RMrSI }, 0 },
2393   { "popV",             { RMrDI }, 0 },
2394   /* 60 */
2395   { X86_64_TABLE (X86_64_60) },
2396   { X86_64_TABLE (X86_64_61) },
2397   { X86_64_TABLE (X86_64_62) },
2398   { X86_64_TABLE (X86_64_63) },
2399   { Bad_Opcode },       /* seg fs */
2400   { Bad_Opcode },       /* seg gs */
2401   { Bad_Opcode },       /* op size prefix */
2402   { Bad_Opcode },       /* adr size prefix */
2403   /* 68 */
2404   { "pushT",            { sIv }, 0 },
2405   { "imulS",            { Gv, Ev, Iv }, 0 },
2406   { "pushT",            { sIbT }, 0 },
2407   { "imulS",            { Gv, Ev, sIb }, 0 },
2408   { "ins{b|}",          { Ybr, indirDX }, 0 },
2409   { X86_64_TABLE (X86_64_6D) },
2410   { "outs{b|}",         { indirDXr, Xb }, 0 },
2411   { X86_64_TABLE (X86_64_6F) },
2412   /* 70 */
2413   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2414   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2415   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2416   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2417   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2418   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2419   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2420   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2421   /* 78 */
2422   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2423   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2424   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2425   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2426   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2427   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2428   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2429   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2430   /* 80 */
2431   { REG_TABLE (REG_80) },
2432   { REG_TABLE (REG_81) },
2433   { X86_64_TABLE (X86_64_82) },
2434   { REG_TABLE (REG_83) },
2435   { "testB",            { Eb, Gb }, 0 },
2436   { "testS",            { Ev, Gv }, 0 },
2437   { "xchgB",            { Ebh2, Gb }, 0 },
2438   { "xchgS",            { Evh2, Gv }, 0 },
2439   /* 88 */
2440   { "movB",             { Ebh3, Gb }, 0 },
2441   { "movS",             { Evh3, Gv }, 0 },
2442   { "movB",             { Gb, EbS }, 0 },
2443   { "movS",             { Gv, EvS }, 0 },
2444   { "movD",             { Sv, Sw }, 0 },
2445   { MOD_TABLE (MOD_8D) },
2446   { "movD",             { Sw, Sv }, 0 },
2447   { REG_TABLE (REG_8F) },
2448   /* 90 */
2449   { PREFIX_TABLE (PREFIX_90) },
2450   { "xchgS",            { RMeCX, eAX }, 0 },
2451   { "xchgS",            { RMeDX, eAX }, 0 },
2452   { "xchgS",            { RMeBX, eAX }, 0 },
2453   { "xchgS",            { RMeSP, eAX }, 0 },
2454   { "xchgS",            { RMeBP, eAX }, 0 },
2455   { "xchgS",            { RMeSI, eAX }, 0 },
2456   { "xchgS",            { RMeDI, eAX }, 0 },
2457   /* 98 */
2458   { "cW{t|}R",          { XX }, 0 },
2459   { "cR{t|}O",          { XX }, 0 },
2460   { X86_64_TABLE (X86_64_9A) },
2461   { Bad_Opcode },       /* fwait */
2462   { "pushfT",           { XX }, 0 },
2463   { "popfT",            { XX }, 0 },
2464   { "sahf",             { XX }, 0 },
2465   { "lahf",             { XX }, 0 },
2466   /* a0 */
2467   { "mov%LB",           { AL, Ob }, 0 },
2468   { "mov%LS",           { eAX, Ov }, 0 },
2469   { "mov%LB",           { Ob, AL }, 0 },
2470   { "mov%LS",           { Ov, eAX }, 0 },
2471   { "movs{b|}",         { Ybr, Xb }, 0 },
2472   { "movs{R|}",         { Yvr, Xv }, 0 },
2473   { "cmps{b|}",         { Xb, Yb }, 0 },
2474   { "cmps{R|}",         { Xv, Yv }, 0 },
2475   /* a8 */
2476   { "testB",            { AL, Ib }, 0 },
2477   { "testS",            { eAX, Iv }, 0 },
2478   { "stosB",            { Ybr, AL }, 0 },
2479   { "stosS",            { Yvr, eAX }, 0 },
2480   { "lodsB",            { ALr, Xb }, 0 },
2481   { "lodsS",            { eAXr, Xv }, 0 },
2482   { "scasB",            { AL, Yb }, 0 },
2483   { "scasS",            { eAX, Yv }, 0 },
2484   /* b0 */
2485   { "movB",             { RMAL, Ib }, 0 },
2486   { "movB",             { RMCL, Ib }, 0 },
2487   { "movB",             { RMDL, Ib }, 0 },
2488   { "movB",             { RMBL, Ib }, 0 },
2489   { "movB",             { RMAH, Ib }, 0 },
2490   { "movB",             { RMCH, Ib }, 0 },
2491   { "movB",             { RMDH, Ib }, 0 },
2492   { "movB",             { RMBH, Ib }, 0 },
2493   /* b8 */
2494   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2495   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2496   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2497   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2498   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2499   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2500   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2501   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2502   /* c0 */
2503   { REG_TABLE (REG_C0) },
2504   { REG_TABLE (REG_C1) },
2505   { X86_64_TABLE (X86_64_C2) },
2506   { X86_64_TABLE (X86_64_C3) },
2507   { X86_64_TABLE (X86_64_C4) },
2508   { X86_64_TABLE (X86_64_C5) },
2509   { REG_TABLE (REG_C6) },
2510   { REG_TABLE (REG_C7) },
2511   /* c8 */
2512   { "enterT",           { Iw, Ib }, 0 },
2513   { "leaveT",           { XX }, 0 },
2514   { "{l|}ret{|f}P",     { Iw }, 0 },
2515   { "{l|}ret{|f}P",     { XX }, 0 },
2516   { "int3",             { XX }, 0 },
2517   { "int",              { Ib }, 0 },
2518   { X86_64_TABLE (X86_64_CE) },
2519   { "iret%LP",          { XX }, 0 },
2520   /* d0 */
2521   { REG_TABLE (REG_D0) },
2522   { REG_TABLE (REG_D1) },
2523   { REG_TABLE (REG_D2) },
2524   { REG_TABLE (REG_D3) },
2525   { X86_64_TABLE (X86_64_D4) },
2526   { X86_64_TABLE (X86_64_D5) },
2527   { Bad_Opcode },
2528   { "xlat",             { DSBX }, 0 },
2529   /* d8 */
2530   { FLOAT },
2531   { FLOAT },
2532   { FLOAT },
2533   { FLOAT },
2534   { FLOAT },
2535   { FLOAT },
2536   { FLOAT },
2537   { FLOAT },
2538   /* e0 */
2539   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2540   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2541   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2542   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2543   { "inB",              { AL, Ib }, 0 },
2544   { "inG",              { zAX, Ib }, 0 },
2545   { "outB",             { Ib, AL }, 0 },
2546   { "outG",             { Ib, zAX }, 0 },
2547   /* e8 */
2548   { X86_64_TABLE (X86_64_E8) },
2549   { X86_64_TABLE (X86_64_E9) },
2550   { X86_64_TABLE (X86_64_EA) },
2551   { "jmp",              { Jb, BND }, 0 },
2552   { "inB",              { AL, indirDX }, 0 },
2553   { "inG",              { zAX, indirDX }, 0 },
2554   { "outB",             { indirDX, AL }, 0 },
2555   { "outG",             { indirDX, zAX }, 0 },
2556   /* f0 */
2557   { Bad_Opcode },       /* lock prefix */
2558   { "icebp",            { XX }, 0 },
2559   { Bad_Opcode },       /* repne */
2560   { Bad_Opcode },       /* repz */
2561   { "hlt",              { XX }, 0 },
2562   { "cmc",              { XX }, 0 },
2563   { REG_TABLE (REG_F6) },
2564   { REG_TABLE (REG_F7) },
2565   /* f8 */
2566   { "clc",              { XX }, 0 },
2567   { "stc",              { XX }, 0 },
2568   { "cli",              { XX }, 0 },
2569   { "sti",              { XX }, 0 },
2570   { "cld",              { XX }, 0 },
2571   { "std",              { XX }, 0 },
2572   { REG_TABLE (REG_FE) },
2573   { REG_TABLE (REG_FF) },
2574 };
2575
2576 static const struct dis386 dis386_twobyte[] = {
2577   /* 00 */
2578   { REG_TABLE (REG_0F00 ) },
2579   { REG_TABLE (REG_0F01 ) },
2580   { "larS",             { Gv, Ew }, 0 },
2581   { "lslS",             { Gv, Ew }, 0 },
2582   { Bad_Opcode },
2583   { "syscall",          { XX }, 0 },
2584   { "clts",             { XX }, 0 },
2585   { "sysret%LQ",                { XX }, 0 },
2586   /* 08 */
2587   { "invd",             { XX }, 0 },
2588   { PREFIX_TABLE (PREFIX_0F09) },
2589   { Bad_Opcode },
2590   { "ud2",              { XX }, 0 },
2591   { Bad_Opcode },
2592   { REG_TABLE (REG_0F0D) },
2593   { "femms",            { XX }, 0 },
2594   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2595   /* 10 */
2596   { PREFIX_TABLE (PREFIX_0F10) },
2597   { PREFIX_TABLE (PREFIX_0F11) },
2598   { PREFIX_TABLE (PREFIX_0F12) },
2599   { MOD_TABLE (MOD_0F13) },
2600   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2601   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2602   { PREFIX_TABLE (PREFIX_0F16) },
2603   { MOD_TABLE (MOD_0F17) },
2604   /* 18 */
2605   { REG_TABLE (REG_0F18) },
2606   { "nopQ",             { Ev }, 0 },
2607   { PREFIX_TABLE (PREFIX_0F1A) },
2608   { PREFIX_TABLE (PREFIX_0F1B) },
2609   { PREFIX_TABLE (PREFIX_0F1C) },
2610   { "nopQ",             { Ev }, 0 },
2611   { PREFIX_TABLE (PREFIX_0F1E) },
2612   { "nopQ",             { Ev }, 0 },
2613   /* 20 */
2614   { "movZ",             { Rm, Cm }, 0 },
2615   { "movZ",             { Rm, Dm }, 0 },
2616   { "movZ",             { Cm, Rm }, 0 },
2617   { "movZ",             { Dm, Rm }, 0 },
2618   { MOD_TABLE (MOD_0F24) },
2619   { Bad_Opcode },
2620   { MOD_TABLE (MOD_0F26) },
2621   { Bad_Opcode },
2622   /* 28 */
2623   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2624   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2625   { PREFIX_TABLE (PREFIX_0F2A) },
2626   { PREFIX_TABLE (PREFIX_0F2B) },
2627   { PREFIX_TABLE (PREFIX_0F2C) },
2628   { PREFIX_TABLE (PREFIX_0F2D) },
2629   { PREFIX_TABLE (PREFIX_0F2E) },
2630   { PREFIX_TABLE (PREFIX_0F2F) },
2631   /* 30 */
2632   { "wrmsr",            { XX }, 0 },
2633   { "rdtsc",            { XX }, 0 },
2634   { "rdmsr",            { XX }, 0 },
2635   { "rdpmc",            { XX }, 0 },
2636   { "sysenter",         { SEP }, 0 },
2637   { "sysexit",          { SEP }, 0 },
2638   { Bad_Opcode },
2639   { "getsec",           { XX }, 0 },
2640   /* 38 */
2641   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2642   { Bad_Opcode },
2643   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2644   { Bad_Opcode },
2645   { Bad_Opcode },
2646   { Bad_Opcode },
2647   { Bad_Opcode },
2648   { Bad_Opcode },
2649   /* 40 */
2650   { "cmovoS",           { Gv, Ev }, 0 },
2651   { "cmovnoS",          { Gv, Ev }, 0 },
2652   { "cmovbS",           { Gv, Ev }, 0 },
2653   { "cmovaeS",          { Gv, Ev }, 0 },
2654   { "cmoveS",           { Gv, Ev }, 0 },
2655   { "cmovneS",          { Gv, Ev }, 0 },
2656   { "cmovbeS",          { Gv, Ev }, 0 },
2657   { "cmovaS",           { Gv, Ev }, 0 },
2658   /* 48 */
2659   { "cmovsS",           { Gv, Ev }, 0 },
2660   { "cmovnsS",          { Gv, Ev }, 0 },
2661   { "cmovpS",           { Gv, Ev }, 0 },
2662   { "cmovnpS",          { Gv, Ev }, 0 },
2663   { "cmovlS",           { Gv, Ev }, 0 },
2664   { "cmovgeS",          { Gv, Ev }, 0 },
2665   { "cmovleS",          { Gv, Ev }, 0 },
2666   { "cmovgS",           { Gv, Ev }, 0 },
2667   /* 50 */
2668   { MOD_TABLE (MOD_0F50) },
2669   { PREFIX_TABLE (PREFIX_0F51) },
2670   { PREFIX_TABLE (PREFIX_0F52) },
2671   { PREFIX_TABLE (PREFIX_0F53) },
2672   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2673   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2674   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2675   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2676   /* 58 */
2677   { PREFIX_TABLE (PREFIX_0F58) },
2678   { PREFIX_TABLE (PREFIX_0F59) },
2679   { PREFIX_TABLE (PREFIX_0F5A) },
2680   { PREFIX_TABLE (PREFIX_0F5B) },
2681   { PREFIX_TABLE (PREFIX_0F5C) },
2682   { PREFIX_TABLE (PREFIX_0F5D) },
2683   { PREFIX_TABLE (PREFIX_0F5E) },
2684   { PREFIX_TABLE (PREFIX_0F5F) },
2685   /* 60 */
2686   { PREFIX_TABLE (PREFIX_0F60) },
2687   { PREFIX_TABLE (PREFIX_0F61) },
2688   { PREFIX_TABLE (PREFIX_0F62) },
2689   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2690   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2691   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2692   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2693   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2694   /* 68 */
2695   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2696   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2697   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2698   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2699   { PREFIX_TABLE (PREFIX_0F6C) },
2700   { PREFIX_TABLE (PREFIX_0F6D) },
2701   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2702   { PREFIX_TABLE (PREFIX_0F6F) },
2703   /* 70 */
2704   { PREFIX_TABLE (PREFIX_0F70) },
2705   { REG_TABLE (REG_0F71) },
2706   { REG_TABLE (REG_0F72) },
2707   { REG_TABLE (REG_0F73) },
2708   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2709   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2710   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2711   { "emms",             { XX }, PREFIX_OPCODE },
2712   /* 78 */
2713   { PREFIX_TABLE (PREFIX_0F78) },
2714   { PREFIX_TABLE (PREFIX_0F79) },
2715   { Bad_Opcode },
2716   { Bad_Opcode },
2717   { PREFIX_TABLE (PREFIX_0F7C) },
2718   { PREFIX_TABLE (PREFIX_0F7D) },
2719   { PREFIX_TABLE (PREFIX_0F7E) },
2720   { PREFIX_TABLE (PREFIX_0F7F) },
2721   /* 80 */
2722   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2723   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2724   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2725   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2726   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2727   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2728   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2729   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2730   /* 88 */
2731   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2732   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2733   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2734   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2735   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2736   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2737   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2738   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2739   /* 90 */
2740   { "seto",             { Eb }, 0 },
2741   { "setno",            { Eb }, 0 },
2742   { "setb",             { Eb }, 0 },
2743   { "setae",            { Eb }, 0 },
2744   { "sete",             { Eb }, 0 },
2745   { "setne",            { Eb }, 0 },
2746   { "setbe",            { Eb }, 0 },
2747   { "seta",             { Eb }, 0 },
2748   /* 98 */
2749   { "sets",             { Eb }, 0 },
2750   { "setns",            { Eb }, 0 },
2751   { "setp",             { Eb }, 0 },
2752   { "setnp",            { Eb }, 0 },
2753   { "setl",             { Eb }, 0 },
2754   { "setge",            { Eb }, 0 },
2755   { "setle",            { Eb }, 0 },
2756   { "setg",             { Eb }, 0 },
2757   /* a0 */
2758   { "pushT",            { fs }, 0 },
2759   { "popT",             { fs }, 0 },
2760   { "cpuid",            { XX }, 0 },
2761   { "btS",              { Ev, Gv }, 0 },
2762   { "shldS",            { Ev, Gv, Ib }, 0 },
2763   { "shldS",            { Ev, Gv, CL }, 0 },
2764   { REG_TABLE (REG_0FA6) },
2765   { REG_TABLE (REG_0FA7) },
2766   /* a8 */
2767   { "pushT",            { gs }, 0 },
2768   { "popT",             { gs }, 0 },
2769   { "rsm",              { XX }, 0 },
2770   { "btsS",             { Evh1, Gv }, 0 },
2771   { "shrdS",            { Ev, Gv, Ib }, 0 },
2772   { "shrdS",            { Ev, Gv, CL }, 0 },
2773   { REG_TABLE (REG_0FAE) },
2774   { "imulS",            { Gv, Ev }, 0 },
2775   /* b0 */
2776   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2777   { "cmpxchgS",         { Evh1, Gv }, 0 },
2778   { MOD_TABLE (MOD_0FB2) },
2779   { "btrS",             { Evh1, Gv }, 0 },
2780   { MOD_TABLE (MOD_0FB4) },
2781   { MOD_TABLE (MOD_0FB5) },
2782   { "movz{bR|x}",       { Gv, Eb }, 0 },
2783   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2784   /* b8 */
2785   { PREFIX_TABLE (PREFIX_0FB8) },
2786   { "ud1S",             { Gv, Ev }, 0 },
2787   { REG_TABLE (REG_0FBA) },
2788   { "btcS",             { Evh1, Gv }, 0 },
2789   { PREFIX_TABLE (PREFIX_0FBC) },
2790   { PREFIX_TABLE (PREFIX_0FBD) },
2791   { "movs{bR|x}",       { Gv, Eb }, 0 },
2792   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2793   /* c0 */
2794   { "xaddB",            { Ebh1, Gb }, 0 },
2795   { "xaddS",            { Evh1, Gv }, 0 },
2796   { PREFIX_TABLE (PREFIX_0FC2) },
2797   { MOD_TABLE (MOD_0FC3) },
2798   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2799   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2800   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2801   { REG_TABLE (REG_0FC7) },
2802   /* c8 */
2803   { "bswap",            { RMeAX }, 0 },
2804   { "bswap",            { RMeCX }, 0 },
2805   { "bswap",            { RMeDX }, 0 },
2806   { "bswap",            { RMeBX }, 0 },
2807   { "bswap",            { RMeSP }, 0 },
2808   { "bswap",            { RMeBP }, 0 },
2809   { "bswap",            { RMeSI }, 0 },
2810   { "bswap",            { RMeDI }, 0 },
2811   /* d0 */
2812   { PREFIX_TABLE (PREFIX_0FD0) },
2813   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2814   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2815   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2816   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2817   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2818   { PREFIX_TABLE (PREFIX_0FD6) },
2819   { MOD_TABLE (MOD_0FD7) },
2820   /* d8 */
2821   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2822   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2823   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2824   { "pand",             { MX, EM }, PREFIX_OPCODE },
2825   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2826   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2827   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2828   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2829   /* e0 */
2830   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2831   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2832   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2833   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2834   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2835   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2836   { PREFIX_TABLE (PREFIX_0FE6) },
2837   { PREFIX_TABLE (PREFIX_0FE7) },
2838   /* e8 */
2839   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2840   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2841   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2842   { "por",              { MX, EM }, PREFIX_OPCODE },
2843   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2844   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2845   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2846   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2847   /* f0 */
2848   { PREFIX_TABLE (PREFIX_0FF0) },
2849   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2850   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2851   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2852   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2853   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2854   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0FF7) },
2856   /* f8 */
2857   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2858   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2859   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2860   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2861   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2862   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2863   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2864   { "ud0S",             { Gv, Ev }, 0 },
2865 };
2866
2867 static const unsigned char onebyte_has_modrm[256] = {
2868   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2869   /*       -------------------------------        */
2870   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2871   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2872   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2873   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2874   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2875   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2876   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2877   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2878   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2879   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2880   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2881   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2882   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2883   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2884   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2885   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2886   /*       -------------------------------        */
2887   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2888 };
2889
2890 static const unsigned char twobyte_has_modrm[256] = {
2891   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2892   /*       -------------------------------        */
2893   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2894   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2895   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2896   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2897   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2898   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2899   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2900   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2901   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2902   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2903   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2904   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2905   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2906   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2907   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2908   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2909   /*       -------------------------------        */
2910   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2911 };
2912
2913 static char obuf[100];
2914 static char *obufp;
2915 static char *mnemonicendp;
2916 static char scratchbuf[100];
2917 static unsigned char *start_codep;
2918 static unsigned char *insn_codep;
2919 static unsigned char *codep;
2920 static unsigned char *end_codep;
2921 static int last_lock_prefix;
2922 static int last_repz_prefix;
2923 static int last_repnz_prefix;
2924 static int last_data_prefix;
2925 static int last_addr_prefix;
2926 static int last_rex_prefix;
2927 static int last_seg_prefix;
2928 static int fwait_prefix;
2929 /* The active segment register prefix.  */
2930 static int active_seg_prefix;
2931 #define MAX_CODE_LENGTH 15
2932 /* We can up to 14 prefixes since the maximum instruction length is
2933    15bytes.  */
2934 static int all_prefixes[MAX_CODE_LENGTH - 1];
2935 static disassemble_info *the_info;
2936 static struct
2937   {
2938     int mod;
2939     int reg;
2940     int rm;
2941   }
2942 modrm;
2943 static unsigned char need_modrm;
2944 static struct
2945   {
2946     int scale;
2947     int index;
2948     int base;
2949   }
2950 sib;
2951 static struct
2952   {
2953     int register_specifier;
2954     int length;
2955     int prefix;
2956     int w;
2957     int evex;
2958     int r;
2959     int v;
2960     int mask_register_specifier;
2961     int zeroing;
2962     int ll;
2963     int b;
2964   }
2965 vex;
2966 static unsigned char need_vex;
2967
2968 struct op
2969   {
2970     const char *name;
2971     unsigned int len;
2972   };
2973
2974 /* If we are accessing mod/rm/reg without need_modrm set, then the
2975    values are stale.  Hitting this abort likely indicates that you
2976    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2977 #define MODRM_CHECK  if (!need_modrm) abort ()
2978
2979 static const char **names64;
2980 static const char **names32;
2981 static const char **names16;
2982 static const char **names8;
2983 static const char **names8rex;
2984 static const char **names_seg;
2985 static const char *index64;
2986 static const char *index32;
2987 static const char **index16;
2988 static const char **names_bnd;
2989
2990 static const char *intel_names64[] = {
2991   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2992   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2993 };
2994 static const char *intel_names32[] = {
2995   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2996   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2997 };
2998 static const char *intel_names16[] = {
2999   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3000   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3001 };
3002 static const char *intel_names8[] = {
3003   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3004 };
3005 static const char *intel_names8rex[] = {
3006   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3007   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3008 };
3009 static const char *intel_names_seg[] = {
3010   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3011 };
3012 static const char *intel_index64 = "riz";
3013 static const char *intel_index32 = "eiz";
3014 static const char *intel_index16[] = {
3015   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3016 };
3017
3018 static const char *att_names64[] = {
3019   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3020   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3021 };
3022 static const char *att_names32[] = {
3023   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3024   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3025 };
3026 static const char *att_names16[] = {
3027   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3028   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3029 };
3030 static const char *att_names8[] = {
3031   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3032 };
3033 static const char *att_names8rex[] = {
3034   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3035   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3036 };
3037 static const char *att_names_seg[] = {
3038   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3039 };
3040 static const char *att_index64 = "%riz";
3041 static const char *att_index32 = "%eiz";
3042 static const char *att_index16[] = {
3043   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3044 };
3045
3046 static const char **names_mm;
3047 static const char *intel_names_mm[] = {
3048   "mm0", "mm1", "mm2", "mm3",
3049   "mm4", "mm5", "mm6", "mm7"
3050 };
3051 static const char *att_names_mm[] = {
3052   "%mm0", "%mm1", "%mm2", "%mm3",
3053   "%mm4", "%mm5", "%mm6", "%mm7"
3054 };
3055
3056 static const char *intel_names_bnd[] = {
3057   "bnd0", "bnd1", "bnd2", "bnd3"
3058 };
3059
3060 static const char *att_names_bnd[] = {
3061   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3062 };
3063
3064 static const char **names_xmm;
3065 static const char *intel_names_xmm[] = {
3066   "xmm0", "xmm1", "xmm2", "xmm3",
3067   "xmm4", "xmm5", "xmm6", "xmm7",
3068   "xmm8", "xmm9", "xmm10", "xmm11",
3069   "xmm12", "xmm13", "xmm14", "xmm15",
3070   "xmm16", "xmm17", "xmm18", "xmm19",
3071   "xmm20", "xmm21", "xmm22", "xmm23",
3072   "xmm24", "xmm25", "xmm26", "xmm27",
3073   "xmm28", "xmm29", "xmm30", "xmm31"
3074 };
3075 static const char *att_names_xmm[] = {
3076   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3077   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3078   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3079   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3080   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3081   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3082   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3083   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3084 };
3085
3086 static const char **names_ymm;
3087 static const char *intel_names_ymm[] = {
3088   "ymm0", "ymm1", "ymm2", "ymm3",
3089   "ymm4", "ymm5", "ymm6", "ymm7",
3090   "ymm8", "ymm9", "ymm10", "ymm11",
3091   "ymm12", "ymm13", "ymm14", "ymm15",
3092   "ymm16", "ymm17", "ymm18", "ymm19",
3093   "ymm20", "ymm21", "ymm22", "ymm23",
3094   "ymm24", "ymm25", "ymm26", "ymm27",
3095   "ymm28", "ymm29", "ymm30", "ymm31"
3096 };
3097 static const char *att_names_ymm[] = {
3098   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3099   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3100   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3101   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3102   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3103   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3104   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3105   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3106 };
3107
3108 static const char **names_zmm;
3109 static const char *intel_names_zmm[] = {
3110   "zmm0", "zmm1", "zmm2", "zmm3",
3111   "zmm4", "zmm5", "zmm6", "zmm7",
3112   "zmm8", "zmm9", "zmm10", "zmm11",
3113   "zmm12", "zmm13", "zmm14", "zmm15",
3114   "zmm16", "zmm17", "zmm18", "zmm19",
3115   "zmm20", "zmm21", "zmm22", "zmm23",
3116   "zmm24", "zmm25", "zmm26", "zmm27",
3117   "zmm28", "zmm29", "zmm30", "zmm31"
3118 };
3119 static const char *att_names_zmm[] = {
3120   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3121   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3122   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3123   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3124   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3125   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3126   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3127   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3128 };
3129
3130 static const char **names_tmm;
3131 static const char *intel_names_tmm[] = {
3132   "tmm0", "tmm1", "tmm2", "tmm3",
3133   "tmm4", "tmm5", "tmm6", "tmm7"
3134 };
3135 static const char *att_names_tmm[] = {
3136   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3137   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3138 };
3139
3140 static const char **names_mask;
3141 static const char *intel_names_mask[] = {
3142   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3143 };
3144 static const char *att_names_mask[] = {
3145   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3146 };
3147
3148 static const char *names_rounding[] =
3149 {
3150   "{rn-sae}",
3151   "{rd-sae}",
3152   "{ru-sae}",
3153   "{rz-sae}"
3154 };
3155
3156 static const struct dis386 reg_table[][8] = {
3157   /* REG_80 */
3158   {
3159     { "addA",   { Ebh1, Ib }, 0 },
3160     { "orA",    { Ebh1, Ib }, 0 },
3161     { "adcA",   { Ebh1, Ib }, 0 },
3162     { "sbbA",   { Ebh1, Ib }, 0 },
3163     { "andA",   { Ebh1, Ib }, 0 },
3164     { "subA",   { Ebh1, Ib }, 0 },
3165     { "xorA",   { Ebh1, Ib }, 0 },
3166     { "cmpA",   { Eb, Ib }, 0 },
3167   },
3168   /* REG_81 */
3169   {
3170     { "addQ",   { Evh1, Iv }, 0 },
3171     { "orQ",    { Evh1, Iv }, 0 },
3172     { "adcQ",   { Evh1, Iv }, 0 },
3173     { "sbbQ",   { Evh1, Iv }, 0 },
3174     { "andQ",   { Evh1, Iv }, 0 },
3175     { "subQ",   { Evh1, Iv }, 0 },
3176     { "xorQ",   { Evh1, Iv }, 0 },
3177     { "cmpQ",   { Ev, Iv }, 0 },
3178   },
3179   /* REG_83 */
3180   {
3181     { "addQ",   { Evh1, sIb }, 0 },
3182     { "orQ",    { Evh1, sIb }, 0 },
3183     { "adcQ",   { Evh1, sIb }, 0 },
3184     { "sbbQ",   { Evh1, sIb }, 0 },
3185     { "andQ",   { Evh1, sIb }, 0 },
3186     { "subQ",   { Evh1, sIb }, 0 },
3187     { "xorQ",   { Evh1, sIb }, 0 },
3188     { "cmpQ",   { Ev, sIb }, 0 },
3189   },
3190   /* REG_8F */
3191   {
3192     { "popU",   { stackEv }, 0 },
3193     { XOP_8F_TABLE (XOP_09) },
3194     { Bad_Opcode },
3195     { Bad_Opcode },
3196     { Bad_Opcode },
3197     { XOP_8F_TABLE (XOP_09) },
3198   },
3199   /* REG_C0 */
3200   {
3201     { "rolA",   { Eb, Ib }, 0 },
3202     { "rorA",   { Eb, Ib }, 0 },
3203     { "rclA",   { Eb, Ib }, 0 },
3204     { "rcrA",   { Eb, Ib }, 0 },
3205     { "shlA",   { Eb, Ib }, 0 },
3206     { "shrA",   { Eb, Ib }, 0 },
3207     { "shlA",   { Eb, Ib }, 0 },
3208     { "sarA",   { Eb, Ib }, 0 },
3209   },
3210   /* REG_C1 */
3211   {
3212     { "rolQ",   { Ev, Ib }, 0 },
3213     { "rorQ",   { Ev, Ib }, 0 },
3214     { "rclQ",   { Ev, Ib }, 0 },
3215     { "rcrQ",   { Ev, Ib }, 0 },
3216     { "shlQ",   { Ev, Ib }, 0 },
3217     { "shrQ",   { Ev, Ib }, 0 },
3218     { "shlQ",   { Ev, Ib }, 0 },
3219     { "sarQ",   { Ev, Ib }, 0 },
3220   },
3221   /* REG_C6 */
3222   {
3223     { "movA",   { Ebh3, Ib }, 0 },
3224     { Bad_Opcode },
3225     { Bad_Opcode },
3226     { Bad_Opcode },
3227     { Bad_Opcode },
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { MOD_TABLE (MOD_C6_REG_7) },
3231   },
3232   /* REG_C7 */
3233   {
3234     { "movQ",   { Evh3, Iv }, 0 },
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { MOD_TABLE (MOD_C7_REG_7) },
3242   },
3243   /* REG_D0 */
3244   {
3245     { "rolA",   { Eb, I1 }, 0 },
3246     { "rorA",   { Eb, I1 }, 0 },
3247     { "rclA",   { Eb, I1 }, 0 },
3248     { "rcrA",   { Eb, I1 }, 0 },
3249     { "shlA",   { Eb, I1 }, 0 },
3250     { "shrA",   { Eb, I1 }, 0 },
3251     { "shlA",   { Eb, I1 }, 0 },
3252     { "sarA",   { Eb, I1 }, 0 },
3253   },
3254   /* REG_D1 */
3255   {
3256     { "rolQ",   { Ev, I1 }, 0 },
3257     { "rorQ",   { Ev, I1 }, 0 },
3258     { "rclQ",   { Ev, I1 }, 0 },
3259     { "rcrQ",   { Ev, I1 }, 0 },
3260     { "shlQ",   { Ev, I1 }, 0 },
3261     { "shrQ",   { Ev, I1 }, 0 },
3262     { "shlQ",   { Ev, I1 }, 0 },
3263     { "sarQ",   { Ev, I1 }, 0 },
3264   },
3265   /* REG_D2 */
3266   {
3267     { "rolA",   { Eb, CL }, 0 },
3268     { "rorA",   { Eb, CL }, 0 },
3269     { "rclA",   { Eb, CL }, 0 },
3270     { "rcrA",   { Eb, CL }, 0 },
3271     { "shlA",   { Eb, CL }, 0 },
3272     { "shrA",   { Eb, CL }, 0 },
3273     { "shlA",   { Eb, CL }, 0 },
3274     { "sarA",   { Eb, CL }, 0 },
3275   },
3276   /* REG_D3 */
3277   {
3278     { "rolQ",   { Ev, CL }, 0 },
3279     { "rorQ",   { Ev, CL }, 0 },
3280     { "rclQ",   { Ev, CL }, 0 },
3281     { "rcrQ",   { Ev, CL }, 0 },
3282     { "shlQ",   { Ev, CL }, 0 },
3283     { "shrQ",   { Ev, CL }, 0 },
3284     { "shlQ",   { Ev, CL }, 0 },
3285     { "sarQ",   { Ev, CL }, 0 },
3286   },
3287   /* REG_F6 */
3288   {
3289     { "testA",  { Eb, Ib }, 0 },
3290     { "testA",  { Eb, Ib }, 0 },
3291     { "notA",   { Ebh1 }, 0 },
3292     { "negA",   { Ebh1 }, 0 },
3293     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3294     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3295     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3296     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3297   },
3298   /* REG_F7 */
3299   {
3300     { "testQ",  { Ev, Iv }, 0 },
3301     { "testQ",  { Ev, Iv }, 0 },
3302     { "notQ",   { Evh1 }, 0 },
3303     { "negQ",   { Evh1 }, 0 },
3304     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3305     { "imulQ",  { Ev }, 0 },
3306     { "divQ",   { Ev }, 0 },
3307     { "idivQ",  { Ev }, 0 },
3308   },
3309   /* REG_FE */
3310   {
3311     { "incA",   { Ebh1 }, 0 },
3312     { "decA",   { Ebh1 }, 0 },
3313   },
3314   /* REG_FF */
3315   {
3316     { "incQ",   { Evh1 }, 0 },
3317     { "decQ",   { Evh1 }, 0 },
3318     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3319     { MOD_TABLE (MOD_FF_REG_3) },
3320     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3321     { MOD_TABLE (MOD_FF_REG_5) },
3322     { "pushU",  { stackEv }, 0 },
3323     { Bad_Opcode },
3324   },
3325   /* REG_0F00 */
3326   {
3327     { "sldtD",  { Sv }, 0 },
3328     { "strD",   { Sv }, 0 },
3329     { "lldt",   { Ew }, 0 },
3330     { "ltr",    { Ew }, 0 },
3331     { "verr",   { Ew }, 0 },
3332     { "verw",   { Ew }, 0 },
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335   },
3336   /* REG_0F01 */
3337   {
3338     { MOD_TABLE (MOD_0F01_REG_0) },
3339     { MOD_TABLE (MOD_0F01_REG_1) },
3340     { MOD_TABLE (MOD_0F01_REG_2) },
3341     { MOD_TABLE (MOD_0F01_REG_3) },
3342     { "smswD",  { Sv }, 0 },
3343     { MOD_TABLE (MOD_0F01_REG_5) },
3344     { "lmsw",   { Ew }, 0 },
3345     { MOD_TABLE (MOD_0F01_REG_7) },
3346   },
3347   /* REG_0F0D */
3348   {
3349     { "prefetch",       { Mb }, 0 },
3350     { "prefetchw",      { Mb }, 0 },
3351     { "prefetchwt1",    { Mb }, 0 },
3352     { "prefetch",       { Mb }, 0 },
3353     { "prefetch",       { Mb }, 0 },
3354     { "prefetch",       { Mb }, 0 },
3355     { "prefetch",       { Mb }, 0 },
3356     { "prefetch",       { Mb }, 0 },
3357   },
3358   /* REG_0F18 */
3359   {
3360     { MOD_TABLE (MOD_0F18_REG_0) },
3361     { MOD_TABLE (MOD_0F18_REG_1) },
3362     { MOD_TABLE (MOD_0F18_REG_2) },
3363     { MOD_TABLE (MOD_0F18_REG_3) },
3364     { MOD_TABLE (MOD_0F18_REG_4) },
3365     { MOD_TABLE (MOD_0F18_REG_5) },
3366     { MOD_TABLE (MOD_0F18_REG_6) },
3367     { MOD_TABLE (MOD_0F18_REG_7) },
3368   },
3369   /* REG_0F1C_P_0_MOD_0 */
3370   {
3371     { "cldemote",       { Mb }, 0 },
3372     { "nopQ",           { Ev }, 0 },
3373     { "nopQ",           { Ev }, 0 },
3374     { "nopQ",           { Ev }, 0 },
3375     { "nopQ",           { Ev }, 0 },
3376     { "nopQ",           { Ev }, 0 },
3377     { "nopQ",           { Ev }, 0 },
3378     { "nopQ",           { Ev }, 0 },
3379   },
3380   /* REG_0F1E_P_1_MOD_3 */
3381   {
3382     { "nopQ",           { Ev }, 0 },
3383     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3384     { "nopQ",           { Ev }, 0 },
3385     { "nopQ",           { Ev }, 0 },
3386     { "nopQ",           { Ev }, 0 },
3387     { "nopQ",           { Ev }, 0 },
3388     { "nopQ",           { Ev }, 0 },
3389     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3390   },
3391   /* REG_0F71 */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_0F71_REG_2) },
3396     { Bad_Opcode },
3397     { MOD_TABLE (MOD_0F71_REG_4) },
3398     { Bad_Opcode },
3399     { MOD_TABLE (MOD_0F71_REG_6) },
3400   },
3401   /* REG_0F72 */
3402   {
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405     { MOD_TABLE (MOD_0F72_REG_2) },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_0F72_REG_4) },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_0F72_REG_6) },
3410   },
3411   /* REG_0F73 */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_0F73_REG_2) },
3416     { MOD_TABLE (MOD_0F73_REG_3) },
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_0F73_REG_6) },
3420     { MOD_TABLE (MOD_0F73_REG_7) },
3421   },
3422   /* REG_0FA6 */
3423   {
3424     { "montmul",        { { OP_0f07, 0 } }, 0 },
3425     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3426     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3427   },
3428   /* REG_0FA7 */
3429   {
3430     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3431     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3432     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3433     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3434     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3435     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3436   },
3437   /* REG_0FAE */
3438   {
3439     { MOD_TABLE (MOD_0FAE_REG_0) },
3440     { MOD_TABLE (MOD_0FAE_REG_1) },
3441     { MOD_TABLE (MOD_0FAE_REG_2) },
3442     { MOD_TABLE (MOD_0FAE_REG_3) },
3443     { MOD_TABLE (MOD_0FAE_REG_4) },
3444     { MOD_TABLE (MOD_0FAE_REG_5) },
3445     { MOD_TABLE (MOD_0FAE_REG_6) },
3446     { MOD_TABLE (MOD_0FAE_REG_7) },
3447   },
3448   /* REG_0FBA */
3449   {
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { "btQ",    { Ev, Ib }, 0 },
3455     { "btsQ",   { Evh1, Ib }, 0 },
3456     { "btrQ",   { Evh1, Ib }, 0 },
3457     { "btcQ",   { Evh1, Ib }, 0 },
3458   },
3459   /* REG_0FC7 */
3460   {
3461     { Bad_Opcode },
3462     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_0FC7_REG_3) },
3465     { MOD_TABLE (MOD_0FC7_REG_4) },
3466     { MOD_TABLE (MOD_0FC7_REG_5) },
3467     { MOD_TABLE (MOD_0FC7_REG_6) },
3468     { MOD_TABLE (MOD_0FC7_REG_7) },
3469   },
3470   /* REG_VEX_0F71 */
3471   {
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3479   },
3480   /* REG_VEX_0F72 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3489   },
3490   /* REG_VEX_0F73 */
3491   {
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3495     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3499     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3500   },
3501   /* REG_VEX_0FAE */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3506     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3507   },
3508   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3509   {
3510     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3511   },
3512   /* REG_VEX_0F38F3 */
3513   {
3514     { Bad_Opcode },
3515     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3516     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3517     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3518   },
3519   /* REG_0FXOP_09_01_L_0 */
3520   {
3521     { Bad_Opcode },
3522     { "blcfill",        { VexGdq, Edq }, 0 },
3523     { "blsfill",        { VexGdq, Edq }, 0 },
3524     { "blcs",   { VexGdq, Edq }, 0 },
3525     { "tzmsk",  { VexGdq, Edq }, 0 },
3526     { "blcic",  { VexGdq, Edq }, 0 },
3527     { "blsic",  { VexGdq, Edq }, 0 },
3528     { "t1mskc", { VexGdq, Edq }, 0 },
3529   },
3530   /* REG_0FXOP_09_02_L_0 */
3531   {
3532     { Bad_Opcode },
3533     { "blcmsk", { VexGdq, Edq }, 0 },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { Bad_Opcode },
3538     { "blci",   { VexGdq, Edq }, 0 },
3539   },
3540   /* REG_0FXOP_09_12_M_1_L_0 */
3541   {
3542     { "llwpcb", { Edq }, 0 },
3543     { "slwpcb", { Edq }, 0 },
3544   },
3545   /* REG_0FXOP_0A_12_L_0 */
3546   {
3547     { "lwpins", { VexGdq, Ed, Id }, 0 },
3548     { "lwpval", { VexGdq, Ed, Id }, 0 },
3549   },
3550
3551 #include "i386-dis-evex-reg.h"
3552 };
3553
3554 static const struct dis386 prefix_table[][4] = {
3555   /* PREFIX_90 */
3556   {
3557     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3558     { "pause", { XX }, 0 },
3559     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3560     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3561   },
3562
3563   /* PREFIX_0F01_REG_3_RM_1 */
3564   {
3565     { "vmmcall",        { Skip_MODRM }, 0 },
3566     { "vmgexit",        { Skip_MODRM }, 0 },
3567     { Bad_Opcode },
3568     { "vmgexit",        { Skip_MODRM }, 0 },
3569   },
3570
3571   /* PREFIX_0F01_REG_5_MOD_0 */
3572   {
3573     { Bad_Opcode },
3574     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3575   },
3576
3577   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3578   {
3579     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3580     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3581     { Bad_Opcode },
3582     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3583   },
3584
3585   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3586   {
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { Bad_Opcode },
3590     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3591   },
3592
3593   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3594   {
3595     { Bad_Opcode },
3596     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3600   {
3601     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3602     { "mcommit",        { Skip_MODRM }, 0 },
3603   },
3604
3605   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3606   {
3607     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3608   },
3609
3610   /* PREFIX_0F09 */
3611   {
3612     { "wbinvd",   { XX }, 0 },
3613     { "wbnoinvd", { XX }, 0 },
3614   },
3615
3616   /* PREFIX_0F10 */
3617   {
3618     { "movups", { XM, EXx }, PREFIX_OPCODE },
3619     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3620     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3621     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3622   },
3623
3624   /* PREFIX_0F11 */
3625   {
3626     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3627     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3628     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3629     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3630   },
3631
3632   /* PREFIX_0F12 */
3633   {
3634     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3635     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3636     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3637     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3638   },
3639
3640   /* PREFIX_0F16 */
3641   {
3642     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3643     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3644     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3645   },
3646
3647   /* PREFIX_0F1A */
3648   {
3649     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3650     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3651     { "bndmov", { Gbnd, Ebnd }, 0 },
3652     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3653   },
3654
3655   /* PREFIX_0F1B */
3656   {
3657     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3658     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3659     { "bndmov", { EbndS, Gbnd }, 0 },
3660     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3661   },
3662
3663   /* PREFIX_0F1C */
3664   {
3665     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3666     { "nopQ",   { Ev }, PREFIX_OPCODE },
3667     { "nopQ",   { Ev }, PREFIX_OPCODE },
3668     { "nopQ",   { Ev }, PREFIX_OPCODE },
3669   },
3670
3671   /* PREFIX_0F1E */
3672   {
3673     { "nopQ",   { Ev }, PREFIX_OPCODE },
3674     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3675     { "nopQ",   { Ev }, PREFIX_OPCODE },
3676     { "nopQ",   { Ev }, PREFIX_OPCODE },
3677   },
3678
3679   /* PREFIX_0F2A */
3680   {
3681     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3682     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3683     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3684     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3685   },
3686
3687   /* PREFIX_0F2B */
3688   {
3689     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3690     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3691     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3692     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3693   },
3694
3695   /* PREFIX_0F2C */
3696   {
3697     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3698     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3699     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3700     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3701   },
3702
3703   /* PREFIX_0F2D */
3704   {
3705     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3706     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3707     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3708     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3709   },
3710
3711   /* PREFIX_0F2E */
3712   {
3713     { "ucomiss",{ XM, EXd }, 0 },
3714     { Bad_Opcode },
3715     { "ucomisd",{ XM, EXq }, 0 },
3716   },
3717
3718   /* PREFIX_0F2F */
3719   {
3720     { "comiss", { XM, EXd }, 0 },
3721     { Bad_Opcode },
3722     { "comisd", { XM, EXq }, 0 },
3723   },
3724
3725   /* PREFIX_0F51 */
3726   {
3727     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3728     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3729     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3730     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3731   },
3732
3733   /* PREFIX_0F52 */
3734   {
3735     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3736     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3737   },
3738
3739   /* PREFIX_0F53 */
3740   {
3741     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3742     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_0F58 */
3746   {
3747     { "addps", { XM, EXx }, PREFIX_OPCODE },
3748     { "addss", { XM, EXd }, PREFIX_OPCODE },
3749     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3750     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F59 */
3754   {
3755     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3756     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3757     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3758     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F5A */
3762   {
3763     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3764     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3765     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3766     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F5B */
3770   {
3771     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3772     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3773     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F5C */
3777   {
3778     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3779     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3780     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3781     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3782   },
3783
3784   /* PREFIX_0F5D */
3785   {
3786     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3787     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3788     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3789     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F5E */
3793   {
3794     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3795     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3796     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3797     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3798   },
3799
3800   /* PREFIX_0F5F */
3801   {
3802     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3803     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3804     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3805     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3806   },
3807
3808   /* PREFIX_0F60 */
3809   {
3810     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3811     { Bad_Opcode },
3812     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3813   },
3814
3815   /* PREFIX_0F61 */
3816   {
3817     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3818     { Bad_Opcode },
3819     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F62 */
3823   {
3824     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3825     { Bad_Opcode },
3826     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F6C */
3830   {
3831     { Bad_Opcode },
3832     { Bad_Opcode },
3833     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F6D */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F6F */
3844   {
3845     { "movq",   { MX, EM }, PREFIX_OPCODE },
3846     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3847     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F70 */
3851   {
3852     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3853     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3854     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3855     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F73_REG_3 */
3859   {
3860     { Bad_Opcode },
3861     { Bad_Opcode },
3862     { "psrldq", { XS, Ib }, 0 },
3863   },
3864
3865   /* PREFIX_0F73_REG_7 */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { "pslldq", { XS, Ib }, 0 },
3870   },
3871
3872   /* PREFIX_0F78 */
3873   {
3874     {"vmread",  { Em, Gm }, 0 },
3875     { Bad_Opcode },
3876     {"extrq",   { XS, Ib, Ib }, 0 },
3877     {"insertq", { XM, XS, Ib, Ib }, 0 },
3878   },
3879
3880   /* PREFIX_0F79 */
3881   {
3882     {"vmwrite", { Gm, Em }, 0 },
3883     { Bad_Opcode },
3884     {"extrq",   { XM, XS }, 0 },
3885     {"insertq", { XM, XS }, 0 },
3886   },
3887
3888   /* PREFIX_0F7C */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3893     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3894   },
3895
3896   /* PREFIX_0F7D */
3897   {
3898     { Bad_Opcode },
3899     { Bad_Opcode },
3900     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3901     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F7E */
3905   {
3906     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3907     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3908     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F7F */
3912   {
3913     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3914     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3915     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3916   },
3917
3918   /* PREFIX_0FAE_REG_0_MOD_3 */
3919   {
3920     { Bad_Opcode },
3921     { "rdfsbase", { Ev }, 0 },
3922   },
3923
3924   /* PREFIX_0FAE_REG_1_MOD_3 */
3925   {
3926     { Bad_Opcode },
3927     { "rdgsbase", { Ev }, 0 },
3928   },
3929
3930   /* PREFIX_0FAE_REG_2_MOD_3 */
3931   {
3932     { Bad_Opcode },
3933     { "wrfsbase", { Ev }, 0 },
3934   },
3935
3936   /* PREFIX_0FAE_REG_3_MOD_3 */
3937   {
3938     { Bad_Opcode },
3939     { "wrgsbase", { Ev }, 0 },
3940   },
3941
3942   /* PREFIX_0FAE_REG_4_MOD_0 */
3943   {
3944     { "xsave",  { FXSAVE }, 0 },
3945     { "ptwrite{%LQ|}", { Edq }, 0 },
3946   },
3947
3948   /* PREFIX_0FAE_REG_4_MOD_3 */
3949   {
3950     { Bad_Opcode },
3951     { "ptwrite{%LQ|}", { Edq }, 0 },
3952   },
3953
3954   /* PREFIX_0FAE_REG_5_MOD_0 */
3955   {
3956     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0FAE_REG_5_MOD_3 */
3960   {
3961     { "lfence",         { Skip_MODRM }, 0 },
3962     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0FAE_REG_6_MOD_0 */
3966   {
3967     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3968     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3969     { "clwb",   { Mb }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0FAE_REG_6_MOD_3 */
3973   {
3974     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3975     { "umonitor",       { Eva }, PREFIX_OPCODE },
3976     { "tpause", { Edq }, PREFIX_OPCODE },
3977     { "umwait", { Edq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0FAE_REG_7_MOD_0 */
3981   {
3982     { "clflush",        { Mb }, 0 },
3983     { Bad_Opcode },
3984     { "clflushopt",     { Mb }, 0 },
3985   },
3986
3987   /* PREFIX_0FB8 */
3988   {
3989     { Bad_Opcode },
3990     { "popcntS", { Gv, Ev }, 0 },
3991   },
3992
3993   /* PREFIX_0FBC */
3994   {
3995     { "bsfS",   { Gv, Ev }, 0 },
3996     { "tzcntS", { Gv, Ev }, 0 },
3997     { "bsfS",   { Gv, Ev }, 0 },
3998   },
3999
4000   /* PREFIX_0FBD */
4001   {
4002     { "bsrS",   { Gv, Ev }, 0 },
4003     { "lzcntS", { Gv, Ev }, 0 },
4004     { "bsrS",   { Gv, Ev }, 0 },
4005   },
4006
4007   /* PREFIX_0FC2 */
4008   {
4009     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4010     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4011     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4012     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0FC3_MOD_0 */
4016   {
4017     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4018   },
4019
4020   /* PREFIX_0FC7_REG_6_MOD_0 */
4021   {
4022     { "vmptrld",{ Mq }, 0 },
4023     { "vmxon",  { Mq }, 0 },
4024     { "vmclear",{ Mq }, 0 },
4025   },
4026
4027   /* PREFIX_0FC7_REG_6_MOD_3 */
4028   {
4029     { "rdrand", { Ev }, 0 },
4030     { Bad_Opcode },
4031     { "rdrand", { Ev }, 0 }
4032   },
4033
4034   /* PREFIX_0FC7_REG_7_MOD_3 */
4035   {
4036     { "rdseed", { Ev }, 0 },
4037     { "rdpid",  { Em }, 0 },
4038     { "rdseed", { Ev }, 0 },
4039   },
4040
4041   /* PREFIX_0FD0 */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { "addsubpd", { XM, EXx }, 0 },
4046     { "addsubps", { XM, EXx }, 0 },
4047   },
4048
4049   /* PREFIX_0FD6 */
4050   {
4051     { Bad_Opcode },
4052     { "movq2dq",{ XM, MS }, 0 },
4053     { "movq",   { EXqS, XM }, 0 },
4054     { "movdq2q",{ MX, XS }, 0 },
4055   },
4056
4057   /* PREFIX_0FE6 */
4058   {
4059     { Bad_Opcode },
4060     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4061     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4062     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_0FE7 */
4066   {
4067     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4068     { Bad_Opcode },
4069     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4070   },
4071
4072   /* PREFIX_0FF0 */
4073   {
4074     { Bad_Opcode },
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4078   },
4079
4080   /* PREFIX_0FF7 */
4081   {
4082     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4083     { Bad_Opcode },
4084     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4085   },
4086
4087   /* PREFIX_0F3810 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4092   },
4093
4094   /* PREFIX_0F3814 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F3815 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4106   },
4107
4108   /* PREFIX_0F3817 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3820 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3821 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3822 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3823 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3824 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3825 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3828 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3829 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F382A */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4176   },
4177
4178   /* PREFIX_0F382B */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3830 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3831 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3832 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3833 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3834 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3835 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3837 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3838 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3839 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F383A */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F383B */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F383C */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F383D */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F383E */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F383F */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F3840 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F3841 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F3880 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F3881 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3882 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F38C8 */
4326   {
4327     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F38C9 */
4331   {
4332     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F38CA */
4336   {
4337     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F38CB */
4341   {
4342     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F38CC */
4346   {
4347     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F38CD */
4351   {
4352     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F38CF */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38DB */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38DC */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38DD */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38DE */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38DF */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38F0 */
4398   {
4399     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4400     { Bad_Opcode },
4401     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4402     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38F1 */
4406   {
4407     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4408     { Bad_Opcode },
4409     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4410     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38F5 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4418   },
4419
4420   /* PREFIX_0F38F6 */
4421   {
4422     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4423     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4424     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4425     { Bad_Opcode },
4426   },
4427
4428   /* PREFIX_0F38F8 */
4429   {
4430     { Bad_Opcode },
4431     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4432     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4433     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4434   },
4435
4436   /* PREFIX_0F38F9 */
4437   {
4438     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4439   },
4440
4441   /* PREFIX_0F3A08 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3A09 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3A0A */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A0B */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A0C */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A0D */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A0E */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A14 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A15 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A16 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A17 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A20 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A21 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A22 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A40 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A41 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A42 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A44 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A60 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A61 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A62 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A63 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3ACC */
4596   {
4597     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3ACE */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3ACF */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3ADF */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_VEX_0F10 */
4622   {
4623     { "vmovups",        { XM, EXx }, 0 },
4624     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
4625     { "vmovupd",        { XM, EXx }, 0 },
4626     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
4627   },
4628
4629   /* PREFIX_VEX_0F11 */
4630   {
4631     { "vmovups",        { EXxS, XM }, 0 },
4632     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
4633     { "vmovupd",        { EXxS, XM }, 0 },
4634     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
4635   },
4636
4637   /* PREFIX_VEX_0F12 */
4638   {
4639     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4640     { "vmovsldup",      { XM, EXx }, 0 },
4641     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4642     { "vmovddup",       { XM, EXymmq }, 0 },
4643   },
4644
4645   /* PREFIX_VEX_0F16 */
4646   {
4647     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4648     { "vmovshdup",      { XM, EXx }, 0 },
4649     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4650   },
4651
4652   /* PREFIX_VEX_0F2A */
4653   {
4654     { Bad_Opcode },
4655     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4656     { Bad_Opcode },
4657     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4658   },
4659
4660   /* PREFIX_VEX_0F2C */
4661   {
4662     { Bad_Opcode },
4663     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
4664     { Bad_Opcode },
4665     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
4666   },
4667
4668   /* PREFIX_VEX_0F2D */
4669   {
4670     { Bad_Opcode },
4671     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
4672     { Bad_Opcode },
4673     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
4674   },
4675
4676   /* PREFIX_VEX_0F2E */
4677   {
4678     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
4679     { Bad_Opcode },
4680     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_VEX_0F2F */
4684   {
4685     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
4686     { Bad_Opcode },
4687     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_VEX_0F41 */
4691   {
4692     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4693     { Bad_Opcode },
4694     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F42 */
4698   {
4699     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F44 */
4705   {
4706     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4707     { Bad_Opcode },
4708     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F45 */
4712   {
4713     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F46 */
4719   {
4720     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F47 */
4726   {
4727     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F4A */
4733   {
4734     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F4B */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F51 */
4747   {
4748     { "vsqrtps",        { XM, EXx }, 0 },
4749     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4750     { "vsqrtpd",        { XM, EXx }, 0 },
4751     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4752   },
4753
4754   /* PREFIX_VEX_0F52 */
4755   {
4756     { "vrsqrtps",       { XM, EXx }, 0 },
4757     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4758   },
4759
4760   /* PREFIX_VEX_0F53 */
4761   {
4762     { "vrcpps",         { XM, EXx }, 0 },
4763     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F58 */
4767   {
4768     { "vaddps",         { XM, Vex, EXx }, 0 },
4769     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4770     { "vaddpd",         { XM, Vex, EXx }, 0 },
4771     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4772   },
4773
4774   /* PREFIX_VEX_0F59 */
4775   {
4776     { "vmulps",         { XM, Vex, EXx }, 0 },
4777     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4778     { "vmulpd",         { XM, Vex, EXx }, 0 },
4779     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4780   },
4781
4782   /* PREFIX_VEX_0F5A */
4783   {
4784     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4785     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4786     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4787     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4788   },
4789
4790   /* PREFIX_VEX_0F5B */
4791   {
4792     { "vcvtdq2ps",      { XM, EXx }, 0 },
4793     { "vcvttps2dq",     { XM, EXx }, 0 },
4794     { "vcvtps2dq",      { XM, EXx }, 0 },
4795   },
4796
4797   /* PREFIX_VEX_0F5C */
4798   {
4799     { "vsubps",         { XM, Vex, EXx }, 0 },
4800     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4801     { "vsubpd",         { XM, Vex, EXx }, 0 },
4802     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4803   },
4804
4805   /* PREFIX_VEX_0F5D */
4806   {
4807     { "vminps",         { XM, Vex, EXx }, 0 },
4808     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4809     { "vminpd",         { XM, Vex, EXx }, 0 },
4810     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F5E */
4814   {
4815     { "vdivps",         { XM, Vex, EXx }, 0 },
4816     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4817     { "vdivpd",         { XM, Vex, EXx }, 0 },
4818     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4819   },
4820
4821   /* PREFIX_VEX_0F5F */
4822   {
4823     { "vmaxps",         { XM, Vex, EXx }, 0 },
4824     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4825     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4826     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4827   },
4828
4829   /* PREFIX_VEX_0F60 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4834   },
4835
4836   /* PREFIX_VEX_0F61 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F62 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F63 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F64 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4862   },
4863
4864   /* PREFIX_VEX_0F65 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F66 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F67 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F68 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F69 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F6A */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F6B */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F6C */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F6D */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F6E */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0F6F */
4935   {
4936     { Bad_Opcode },
4937     { "vmovdqu",        { XM, EXx }, 0 },
4938     { "vmovdqa",        { XM, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F70 */
4942   {
4943     { Bad_Opcode },
4944     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4945     { "vpshufd",        { XM, EXx, Ib }, 0 },
4946     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F71_REG_2 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F71_REG_4 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpsraw",         { Vex, XS, Ib }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F71_REG_6 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpsllw",         { Vex, XS, Ib }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F72_REG_2 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpsrld",         { Vex, XS, Ib }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F72_REG_4 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vpsrad",         { Vex, XS, Ib }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F72_REG_6 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vpslld",         { Vex, XS, Ib }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F73_REG_2 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F73_REG_3 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F73_REG_6 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsllq",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F73_REG_7 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpslldq",        { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F74 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F75 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F76 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F77 */
5041   {
5042     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5043   },
5044
5045   /* PREFIX_VEX_0F7C */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5050     { "vhaddps",        { XM, Vex, EXx }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F7D */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5058     { "vhsubps",        { XM, Vex, EXx }, 0 },
5059   },
5060
5061   /* PREFIX_VEX_0F7E */
5062   {
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5065     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5066   },
5067
5068   /* PREFIX_VEX_0F7F */
5069   {
5070     { Bad_Opcode },
5071     { "vmovdqu",        { EXxS, XM }, 0 },
5072     { "vmovdqa",        { EXxS, XM }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F90 */
5076   {
5077     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5078     { Bad_Opcode },
5079     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_0F91 */
5083   {
5084     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5085     { Bad_Opcode },
5086     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_0F92 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5094     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5095   },
5096
5097   /* PREFIX_VEX_0F93 */
5098   {
5099     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5102     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5103   },
5104
5105   /* PREFIX_VEX_0F98 */
5106   {
5107     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5108     { Bad_Opcode },
5109     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5110   },
5111
5112   /* PREFIX_VEX_0F99 */
5113   {
5114     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0FC2 */
5120   {
5121     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
5122     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
5123     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
5124     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
5125   },
5126
5127   /* PREFIX_VEX_0FC4 */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0FC5 */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FD0 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5146     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5147   },
5148
5149   /* PREFIX_VEX_0FD1 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5154   },
5155
5156   /* PREFIX_VEX_0FD2 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FD3 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FD4 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpaddq",         { XM, Vex, EXx }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FD5 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpmullw",        { XM, Vex, EXx }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FD6 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FD7 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5196   },
5197
5198   /* PREFIX_VEX_0FD8 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FD9 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FDA */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpminub",        { XM, Vex, EXx }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FDB */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpand",          { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FDC */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FDD */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FDE */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5245   },
5246
5247   /* PREFIX_VEX_0FDF */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpandn",         { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FE0 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpavgb",         { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FE1 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FE2 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FE3 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpavgw",         { XM, Vex, EXx }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FE4 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FE5 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FE6 */
5297   {
5298     { Bad_Opcode },
5299     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5300     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5301     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE7 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5309   },
5310
5311   /* PREFIX_VEX_0FE8 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE9 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FEA */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpminsw",        { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FEB */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpor",           { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FEC */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FED */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FEE */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FEF */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpxor",          { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FF0 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5373   },
5374
5375   /* PREFIX_VEX_0FF1 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FF2 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FF3 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FF4 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FF5 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FF6 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF7 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FF8 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsubb",         { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF9 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpsubw",         { XM, Vex, EXx }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FFA */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsubd",         { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FFB */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsubq",         { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FFC */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpaddb",         { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FFD */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpaddw",         { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FFE */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpaddd",         { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0F3800 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpshufb",        { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0F3801 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vphaddw",        { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0F3802 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vphaddd",        { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0F3803 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3804 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0F3805 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vphsubw",        { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3806 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vphsubd",        { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3807 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3808 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vpsignb",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3809 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vpsignw",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F380A */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpsignd",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F380B */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F380C */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0F380D */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0F380E */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F380F */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F3813 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F3816 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F3817 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vptest",         { XM, EXx }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F3818 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3819 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F381A */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F381C */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { "vpabsb",         { XM, EXx }, 0 },
5632   },
5633
5634   /* PREFIX_VEX_0F381D */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { "vpabsw",         { XM, EXx }, 0 },
5639   },
5640
5641   /* PREFIX_VEX_0F381E */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vpabsd",         { XM, EXx }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F3820 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F3821 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3822 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3823 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3824 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3825 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3828 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3829 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F382A */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5709   },
5710
5711   /* PREFIX_VEX_0F382B */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F382C */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F382D */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F382E */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F382F */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F3830 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F3831 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5758   },
5759
5760   /* PREFIX_VEX_0F3832 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F3833 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3834 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5779   },
5780
5781   /* PREFIX_VEX_0F3835 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3836 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3837 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3838 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpminsb",        { XM, Vex, EXx }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3839 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpminsd",        { XM, Vex, EXx }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F383A */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpminuw",        { XM, Vex, EXx }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F383B */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpminud",        { XM, Vex, EXx }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F383C */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F383D */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F383E */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F383F */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3840 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpmulld",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F3841 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5870   },
5871
5872   /* PREFIX_VEX_0F3845 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpsrlv%DQ", { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F3846 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F3847 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpsllv%DQ", { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F3849_X86_64 */
5894   {
5895     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5896     { Bad_Opcode },
5897     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5898     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5899   },
5900
5901   /* PREFIX_VEX_0F384B_X86_64 */
5902   {
5903     { Bad_Opcode },
5904     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5905     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5906     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5907   },
5908
5909   /* PREFIX_VEX_0F3858 */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F3859 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F385A */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F385C_X86_64 */
5931   {
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5934     { Bad_Opcode },
5935   },
5936
5937   /* PREFIX_VEX_0F385E_X86_64 */
5938   {
5939     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5940     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5941     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5942     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5943   },
5944
5945   /* PREFIX_VEX_0F3878 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5950   },
5951
5952   /* PREFIX_VEX_0F3879 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5957   },
5958
5959   /* PREFIX_VEX_0F388C */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5964   },
5965
5966   /* PREFIX_VEX_0F388E */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5971   },
5972
5973   /* PREFIX_VEX_0F3890 */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F3891 */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F3892 */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F3893 */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F3896 */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F3897 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F3898 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F3899 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F389A */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F389B */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F389C */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F389D */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F389E */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F389F */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F38A6 */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6076     { Bad_Opcode },
6077   },
6078
6079   /* PREFIX_VEX_0F38A7 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F38A8 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38A9 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38AA */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38AB */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38AC */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38AD */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38AE */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38AF */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38B6 */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38B7 */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38B8 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38B9 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38BA */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38BB */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F38BC */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F38BD */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F38BE */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F38BF */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F38CF */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6217   },
6218
6219   /* PREFIX_VEX_0F38DB */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6224   },
6225
6226   /* PREFIX_VEX_0F38DC */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { "vaesenc",        { XM, Vex, EXx }, 0 },
6231   },
6232
6233   /* PREFIX_VEX_0F38DD */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6238   },
6239
6240   /* PREFIX_VEX_0F38DE */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vaesdec",        { XM, Vex, EXx }, 0 },
6245   },
6246
6247   /* PREFIX_VEX_0F38DF */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F38F2 */
6255   {
6256     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6257   },
6258
6259   /* PREFIX_VEX_0F38F3_REG_1 */
6260   {
6261     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6262   },
6263
6264   /* PREFIX_VEX_0F38F3_REG_2 */
6265   {
6266     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6267   },
6268
6269   /* PREFIX_VEX_0F38F3_REG_3 */
6270   {
6271     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6272   },
6273
6274   /* PREFIX_VEX_0F38F5 */
6275   {
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6278     { Bad_Opcode },
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6280   },
6281
6282   /* PREFIX_VEX_0F38F6 */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6288   },
6289
6290   /* PREFIX_VEX_0F38F7 */
6291   {
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6296   },
6297
6298   /* PREFIX_VEX_0F3A00 */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6303   },
6304
6305   /* PREFIX_VEX_0F3A01 */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A02 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A04 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A05 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A06 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A08 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { "vroundps",       { XM, EXx, Ib }, 0 },
6345   },
6346
6347   /* PREFIX_VEX_0F3A09 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { "vroundpd",       { XM, EXx, Ib }, 0 },
6352   },
6353
6354   /* PREFIX_VEX_0F3A0A */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6359   },
6360
6361   /* PREFIX_VEX_0F3A0B */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F3A0C */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F3A0D */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6380   },
6381
6382   /* PREFIX_VEX_0F3A0E */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6387   },
6388
6389   /* PREFIX_VEX_0F3A0F */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F3A14 */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6401   },
6402
6403   /* PREFIX_VEX_0F3A15 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A16 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A17 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A18 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A19 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A1D */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A20 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A21 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A22 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A30 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A31 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A32 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A33 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A38 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A39 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A40 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6513   },
6514
6515   /* PREFIX_VEX_0F3A41 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A42 */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6527   },
6528
6529   /* PREFIX_VEX_0F3A44 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A46 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6541   },
6542
6543   /* PREFIX_VEX_0F3A48 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A49 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6555   },
6556
6557   /* PREFIX_VEX_0F3A4A */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A4B */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A4C */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A5C */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6583   },
6584
6585   /* PREFIX_VEX_0F3A5D */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6590   },
6591
6592   /* PREFIX_VEX_0F3A5E */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6597   },
6598
6599   /* PREFIX_VEX_0F3A5F */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6604   },
6605
6606   /* PREFIX_VEX_0F3A60 */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6611     { Bad_Opcode },
6612   },
6613
6614   /* PREFIX_VEX_0F3A61 */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A62 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A63 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A68 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6640   },
6641
6642   /* PREFIX_VEX_0F3A69 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6647   },
6648
6649   /* PREFIX_VEX_0F3A6A */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A6B */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A6C */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6668   },
6669
6670   /* PREFIX_VEX_0F3A6D */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6675   },
6676
6677   /* PREFIX_VEX_0F3A6E */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6682   },
6683
6684   /* PREFIX_VEX_0F3A6F */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6689   },
6690
6691   /* PREFIX_VEX_0F3A78 */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6696   },
6697
6698   /* PREFIX_VEX_0F3A79 */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6703   },
6704
6705   /* PREFIX_VEX_0F3A7A */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6710   },
6711
6712   /* PREFIX_VEX_0F3A7B */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6717   },
6718
6719   /* PREFIX_VEX_0F3A7C */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6724     { Bad_Opcode },
6725   },
6726
6727   /* PREFIX_VEX_0F3A7D */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6732   },
6733
6734   /* PREFIX_VEX_0F3A7E */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6739   },
6740
6741   /* PREFIX_VEX_0F3A7F */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6746   },
6747
6748   /* PREFIX_VEX_0F3ACE */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3ACF */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6760   },
6761
6762   /* PREFIX_VEX_0F3ADF */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6767   },
6768
6769   /* PREFIX_VEX_0F3AF0 */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6775   },
6776
6777 #include "i386-dis-evex-prefix.h"
6778 };
6779
6780 static const struct dis386 x86_64_table[][2] = {
6781   /* X86_64_06 */
6782   {
6783     { "pushP", { es }, 0 },
6784   },
6785
6786   /* X86_64_07 */
6787   {
6788     { "popP", { es }, 0 },
6789   },
6790
6791   /* X86_64_0E */
6792   {
6793     { "pushP", { cs }, 0 },
6794   },
6795
6796   /* X86_64_16 */
6797   {
6798     { "pushP", { ss }, 0 },
6799   },
6800
6801   /* X86_64_17 */
6802   {
6803     { "popP", { ss }, 0 },
6804   },
6805
6806   /* X86_64_1E */
6807   {
6808     { "pushP", { ds }, 0 },
6809   },
6810
6811   /* X86_64_1F */
6812   {
6813     { "popP", { ds }, 0 },
6814   },
6815
6816   /* X86_64_27 */
6817   {
6818     { "daa", { XX }, 0 },
6819   },
6820
6821   /* X86_64_2F */
6822   {
6823     { "das", { XX }, 0 },
6824   },
6825
6826   /* X86_64_37 */
6827   {
6828     { "aaa", { XX }, 0 },
6829   },
6830
6831   /* X86_64_3F */
6832   {
6833     { "aas", { XX }, 0 },
6834   },
6835
6836   /* X86_64_60 */
6837   {
6838     { "pushaP", { XX }, 0 },
6839   },
6840
6841   /* X86_64_61 */
6842   {
6843     { "popaP", { XX }, 0 },
6844   },
6845
6846   /* X86_64_62 */
6847   {
6848     { MOD_TABLE (MOD_62_32BIT) },
6849     { EVEX_TABLE (EVEX_0F) },
6850   },
6851
6852   /* X86_64_63 */
6853   {
6854     { "arpl", { Ew, Gw }, 0 },
6855     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6856   },
6857
6858   /* X86_64_6D */
6859   {
6860     { "ins{R|}", { Yzr, indirDX }, 0 },
6861     { "ins{G|}", { Yzr, indirDX }, 0 },
6862   },
6863
6864   /* X86_64_6F */
6865   {
6866     { "outs{R|}", { indirDXr, Xz }, 0 },
6867     { "outs{G|}", { indirDXr, Xz }, 0 },
6868   },
6869
6870   /* X86_64_82 */
6871   {
6872     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6873     { REG_TABLE (REG_80) },
6874   },
6875
6876   /* X86_64_9A */
6877   {
6878     { "{l|}call{T|}", { Ap }, 0 },
6879   },
6880
6881   /* X86_64_C2 */
6882   {
6883     { "retP",           { Iw, BND }, 0 },
6884     { "ret@",           { Iw, BND }, 0 },
6885   },
6886
6887   /* X86_64_C3 */
6888   {
6889     { "retP",           { BND }, 0 },
6890     { "ret@",           { BND }, 0 },
6891   },
6892
6893   /* X86_64_C4 */
6894   {
6895     { MOD_TABLE (MOD_C4_32BIT) },
6896     { VEX_C4_TABLE (VEX_0F) },
6897   },
6898
6899   /* X86_64_C5 */
6900   {
6901     { MOD_TABLE (MOD_C5_32BIT) },
6902     { VEX_C5_TABLE (VEX_0F) },
6903   },
6904
6905   /* X86_64_CE */
6906   {
6907     { "into", { XX }, 0 },
6908   },
6909
6910   /* X86_64_D4 */
6911   {
6912     { "aam", { Ib }, 0 },
6913   },
6914
6915   /* X86_64_D5 */
6916   {
6917     { "aad", { Ib }, 0 },
6918   },
6919
6920   /* X86_64_E8 */
6921   {
6922     { "callP",          { Jv, BND }, 0 },
6923     { "call@",          { Jv, BND }, 0 }
6924   },
6925
6926   /* X86_64_E9 */
6927   {
6928     { "jmpP",           { Jv, BND }, 0 },
6929     { "jmp@",           { Jv, BND }, 0 }
6930   },
6931
6932   /* X86_64_EA */
6933   {
6934     { "{l|}jmp{T|}", { Ap }, 0 },
6935   },
6936
6937   /* X86_64_0F01_REG_0 */
6938   {
6939     { "sgdt{Q|Q}", { M }, 0 },
6940     { "sgdt", { M }, 0 },
6941   },
6942
6943   /* X86_64_0F01_REG_1 */
6944   {
6945     { "sidt{Q|Q}", { M }, 0 },
6946     { "sidt", { M }, 0 },
6947   },
6948
6949   /* X86_64_0F01_REG_2 */
6950   {
6951     { "lgdt{Q|Q}", { M }, 0 },
6952     { "lgdt", { M }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_3 */
6956   {
6957     { "lidt{Q|Q}", { M }, 0 },
6958     { "lidt", { M }, 0 },
6959   },
6960
6961   /* X86_64_VEX_0F3849 */
6962   {
6963     { Bad_Opcode },
6964     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6965   },
6966
6967   /* X86_64_VEX_0F384B */
6968   {
6969     { Bad_Opcode },
6970     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6971   },
6972
6973   /* X86_64_VEX_0F385C */
6974   {
6975     { Bad_Opcode },
6976     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
6977   },
6978
6979   /* X86_64_VEX_0F385E */
6980   {
6981     { Bad_Opcode },
6982     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
6983   },
6984 };
6985
6986 static const struct dis386 three_byte_table[][256] = {
6987
6988   /* THREE_BYTE_0F38 */
6989   {
6990     /* 00 */
6991     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6992     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6993     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6994     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6995     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6996     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6997     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6998     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6999     /* 08 */
7000     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7001     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7002     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7003     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     /* 10 */
7009     { PREFIX_TABLE (PREFIX_0F3810) },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { PREFIX_TABLE (PREFIX_0F3814) },
7014     { PREFIX_TABLE (PREFIX_0F3815) },
7015     { Bad_Opcode },
7016     { PREFIX_TABLE (PREFIX_0F3817) },
7017     /* 18 */
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7023     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7024     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7025     { Bad_Opcode },
7026     /* 20 */
7027     { PREFIX_TABLE (PREFIX_0F3820) },
7028     { PREFIX_TABLE (PREFIX_0F3821) },
7029     { PREFIX_TABLE (PREFIX_0F3822) },
7030     { PREFIX_TABLE (PREFIX_0F3823) },
7031     { PREFIX_TABLE (PREFIX_0F3824) },
7032     { PREFIX_TABLE (PREFIX_0F3825) },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* 28 */
7036     { PREFIX_TABLE (PREFIX_0F3828) },
7037     { PREFIX_TABLE (PREFIX_0F3829) },
7038     { PREFIX_TABLE (PREFIX_0F382A) },
7039     { PREFIX_TABLE (PREFIX_0F382B) },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     /* 30 */
7045     { PREFIX_TABLE (PREFIX_0F3830) },
7046     { PREFIX_TABLE (PREFIX_0F3831) },
7047     { PREFIX_TABLE (PREFIX_0F3832) },
7048     { PREFIX_TABLE (PREFIX_0F3833) },
7049     { PREFIX_TABLE (PREFIX_0F3834) },
7050     { PREFIX_TABLE (PREFIX_0F3835) },
7051     { Bad_Opcode },
7052     { PREFIX_TABLE (PREFIX_0F3837) },
7053     /* 38 */
7054     { PREFIX_TABLE (PREFIX_0F3838) },
7055     { PREFIX_TABLE (PREFIX_0F3839) },
7056     { PREFIX_TABLE (PREFIX_0F383A) },
7057     { PREFIX_TABLE (PREFIX_0F383B) },
7058     { PREFIX_TABLE (PREFIX_0F383C) },
7059     { PREFIX_TABLE (PREFIX_0F383D) },
7060     { PREFIX_TABLE (PREFIX_0F383E) },
7061     { PREFIX_TABLE (PREFIX_0F383F) },
7062     /* 40 */
7063     { PREFIX_TABLE (PREFIX_0F3840) },
7064     { PREFIX_TABLE (PREFIX_0F3841) },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 48 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* 50 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* 58 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 60 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 68 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 70 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* 78 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* 80 */
7135     { PREFIX_TABLE (PREFIX_0F3880) },
7136     { PREFIX_TABLE (PREFIX_0F3881) },
7137     { PREFIX_TABLE (PREFIX_0F3882) },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 88 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* 90 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* 98 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* a0 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* a8 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* b0 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* b8 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* c0 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* c8 */
7216     { PREFIX_TABLE (PREFIX_0F38C8) },
7217     { PREFIX_TABLE (PREFIX_0F38C9) },
7218     { PREFIX_TABLE (PREFIX_0F38CA) },
7219     { PREFIX_TABLE (PREFIX_0F38CB) },
7220     { PREFIX_TABLE (PREFIX_0F38CC) },
7221     { PREFIX_TABLE (PREFIX_0F38CD) },
7222     { Bad_Opcode },
7223     { PREFIX_TABLE (PREFIX_0F38CF) },
7224     /* d0 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* d8 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { PREFIX_TABLE (PREFIX_0F38DB) },
7238     { PREFIX_TABLE (PREFIX_0F38DC) },
7239     { PREFIX_TABLE (PREFIX_0F38DD) },
7240     { PREFIX_TABLE (PREFIX_0F38DE) },
7241     { PREFIX_TABLE (PREFIX_0F38DF) },
7242     /* e0 */
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     /* e8 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* f0 */
7261     { PREFIX_TABLE (PREFIX_0F38F0) },
7262     { PREFIX_TABLE (PREFIX_0F38F1) },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { PREFIX_TABLE (PREFIX_0F38F5) },
7267     { PREFIX_TABLE (PREFIX_0F38F6) },
7268     { Bad_Opcode },
7269     /* f8 */
7270     { PREFIX_TABLE (PREFIX_0F38F8) },
7271     { PREFIX_TABLE (PREFIX_0F38F9) },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278   },
7279   /* THREE_BYTE_0F3A */
7280   {
7281     /* 00 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 08 */
7291     { PREFIX_TABLE (PREFIX_0F3A08) },
7292     { PREFIX_TABLE (PREFIX_0F3A09) },
7293     { PREFIX_TABLE (PREFIX_0F3A0A) },
7294     { PREFIX_TABLE (PREFIX_0F3A0B) },
7295     { PREFIX_TABLE (PREFIX_0F3A0C) },
7296     { PREFIX_TABLE (PREFIX_0F3A0D) },
7297     { PREFIX_TABLE (PREFIX_0F3A0E) },
7298     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7299     /* 10 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { PREFIX_TABLE (PREFIX_0F3A14) },
7305     { PREFIX_TABLE (PREFIX_0F3A15) },
7306     { PREFIX_TABLE (PREFIX_0F3A16) },
7307     { PREFIX_TABLE (PREFIX_0F3A17) },
7308     /* 18 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 20 */
7318     { PREFIX_TABLE (PREFIX_0F3A20) },
7319     { PREFIX_TABLE (PREFIX_0F3A21) },
7320     { PREFIX_TABLE (PREFIX_0F3A22) },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* 28 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* 30 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 38 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 40 */
7354     { PREFIX_TABLE (PREFIX_0F3A40) },
7355     { PREFIX_TABLE (PREFIX_0F3A41) },
7356     { PREFIX_TABLE (PREFIX_0F3A42) },
7357     { Bad_Opcode },
7358     { PREFIX_TABLE (PREFIX_0F3A44) },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 48 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 50 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 58 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 60 */
7390     { PREFIX_TABLE (PREFIX_0F3A60) },
7391     { PREFIX_TABLE (PREFIX_0F3A61) },
7392     { PREFIX_TABLE (PREFIX_0F3A62) },
7393     { PREFIX_TABLE (PREFIX_0F3A63) },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 68 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 70 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* 78 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 80 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 88 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* 90 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* 98 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* a0 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* a8 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* b0 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* b8 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* c0 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* c8 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { PREFIX_TABLE (PREFIX_0F3ACC) },
7512     { Bad_Opcode },
7513     { PREFIX_TABLE (PREFIX_0F3ACE) },
7514     { PREFIX_TABLE (PREFIX_0F3ACF) },
7515     /* d0 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* d8 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { PREFIX_TABLE (PREFIX_0F3ADF) },
7533     /* e0 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* e8 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* f0 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* f8 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569   },
7570 };
7571
7572 static const struct dis386 xop_table[][256] = {
7573   /* XOP_08 */
7574   {
7575     /* 00 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 08 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 10 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 18 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 20 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 28 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 30 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 38 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 40 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 48 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 50 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 58 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 60 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 68 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 70 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* 78 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 80 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7726     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7727     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7728     /* 88 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7736     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7737     /* 90 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7744     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7745     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7746     /* 98 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7754     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7755     /* a0 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7759     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7763     { Bad_Opcode },
7764     /* a8 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* b0 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7781     { Bad_Opcode },
7782     /* b8 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* c0 */
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7794     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7795     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* c8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7807     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7808     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7809     /* d0 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* d8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* e0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* e8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7842     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7843     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7844     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7845     /* f0 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* f8 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863   },
7864   /* XOP_09 */
7865   {
7866     /* 00 */
7867     { Bad_Opcode },
7868     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7869     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 08 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 10 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 18 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 20 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 28 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 30 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 38 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 40 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 48 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 50 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 58 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 60 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 68 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* 70 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* 78 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 80 */
8011     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8012     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8013     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8014     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* 88 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* 90 */
8029     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8030     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8031     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8032     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8033     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8034     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8035     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8036     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8037     /* 98 */
8038     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8039     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* a0 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* a8 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* b0 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* b8 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* c0 */
8083     { Bad_Opcode },
8084     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8085     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8086     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8090     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8091     /* c8 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* d0 */
8101     { Bad_Opcode },
8102     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8103     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8104     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8108     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8109     /* d8 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* e0 */
8119     { Bad_Opcode },
8120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8121     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8122     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* e8 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* f0 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* f8 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154   },
8155   /* XOP_0A */
8156   {
8157     /* 00 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 08 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 10 */
8176     { "bextrS", { Gdq, Edq, Id }, 0 },
8177     { Bad_Opcode },
8178     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 18 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 20 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 28 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 30 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 38 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 40 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 48 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 50 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 58 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 60 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 68 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 70 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* 78 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 80 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 88 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 90 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 98 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* a0 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* a8 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* b0 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* b8 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* c0 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* c8 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* d0 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* d8 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* e0 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* e8 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* f0 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* f8 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445   },
8446 };
8447
8448 static const struct dis386 vex_table[][256] = {
8449   /* VEX_0F */
8450   {
8451     /* 00 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 08 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 10 */
8470     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8473     { MOD_TABLE (MOD_VEX_0F13) },
8474     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8475     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8476     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8477     { MOD_TABLE (MOD_VEX_0F17) },
8478     /* 18 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 20 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 28 */
8497     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8498     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8499     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8500     { MOD_TABLE (MOD_VEX_0F2B) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8505     /* 30 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* 38 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 40 */
8524     { Bad_Opcode },
8525     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8527     { Bad_Opcode },
8528     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8532     /* 48 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* 50 */
8542     { MOD_TABLE (MOD_VEX_0F50) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8546     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8547     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8548     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8549     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8550     /* 58 */
8551     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8559     /* 60 */
8560     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8568     /* 68 */
8569     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8577     /* 70 */
8578     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8579     { REG_TABLE (REG_VEX_0F71) },
8580     { REG_TABLE (REG_VEX_0F72) },
8581     { REG_TABLE (REG_VEX_0F73) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8586     /* 78 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8595     /* 80 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 88 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* 90 */
8614     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* 98 */
8623     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* a0 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* a8 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { REG_TABLE (REG_VEX_0FAE) },
8648     { Bad_Opcode },
8649     /* b0 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* b8 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* c0 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8671     { Bad_Opcode },
8672     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8674     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8675     { Bad_Opcode },
8676     /* c8 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* d0 */
8686     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8694     /* d8 */
8695     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8703     /* e0 */
8704     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8712     /* e8 */
8713     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8721     /* f0 */
8722     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8730     /* f8 */
8731     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8738     { Bad_Opcode },
8739   },
8740   /* VEX_0F38 */
8741   {
8742     /* 00 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8751     /* 08 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8760     /* 10 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8769     /* 18 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8773     { Bad_Opcode },
8774     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8777     { Bad_Opcode },
8778     /* 20 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     /* 28 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8796     /* 30 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8805     /* 38 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8814     /* 40 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8823     /* 48 */
8824     { Bad_Opcode },
8825     { X86_64_TABLE (X86_64_VEX_0F3849) },
8826     { Bad_Opcode },
8827     { X86_64_TABLE (X86_64_VEX_0F384B) },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* 50 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* 58 */
8842     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8845     { Bad_Opcode },
8846     { X86_64_TABLE (X86_64_VEX_0F385C) },
8847     { Bad_Opcode },
8848     { X86_64_TABLE (X86_64_VEX_0F385E) },
8849     { Bad_Opcode },
8850     /* 60 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 68 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* 70 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* 78 */
8878     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     /* 80 */
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     /* 88 */
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8901     { Bad_Opcode },
8902     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8903     { Bad_Opcode },
8904     /* 90 */
8905     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8913     /* 98 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8922     /* a0 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8931     /* a8 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8940     /* b0 */
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8949     /* b8 */
8950     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8958     /* c0 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* c8 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8976     /* d0 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* d8 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8994     /* e0 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* e8 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     /* f0 */
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9016     { REG_TABLE (REG_VEX_0F38F3) },
9017     { Bad_Opcode },
9018     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9021     /* f8 */
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030   },
9031   /* VEX_0F3A */
9032   {
9033     /* 00 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9037     { Bad_Opcode },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9041     { Bad_Opcode },
9042     /* 08 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9051     /* 10 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9060     /* 18 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* 20 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* 28 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 30 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* 38 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 40 */
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9109     { Bad_Opcode },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9111     { Bad_Opcode },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9113     { Bad_Opcode },
9114     /* 48 */
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* 50 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* 58 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9141     /* 60 */
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 68 */
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9159     /* 70 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* 78 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9177     /* 80 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     /* 88 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* 90 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* 98 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* a0 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* a8 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* b0 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* b8 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* c0 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* c8 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9266     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9267     /* d0 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* d8 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9285     /* e0 */
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* e8 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     /* f0 */
9304     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     /* f8 */
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321   },
9322 };
9323
9324 #include "i386-dis-evex.h"
9325
9326 static const struct dis386 vex_len_table[][2] = {
9327   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9328   {
9329     { "vmovlpX",        { XM, Vex, EXq }, 0 },
9330   },
9331
9332   /* VEX_LEN_0F12_P_0_M_1 */
9333   {
9334     { "vmovhlps",       { XM, Vex, EXq }, 0 },
9335   },
9336
9337   /* VEX_LEN_0F13_M_0 */
9338   {
9339     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9340   },
9341
9342   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9343   {
9344     { "vmovhpX",        { XM, Vex, EXq }, 0 },
9345   },
9346
9347   /* VEX_LEN_0F16_P_0_M_1 */
9348   {
9349     { "vmovlhps",       { XM, Vex, EXq }, 0 },
9350   },
9351
9352   /* VEX_LEN_0F17_M_0 */
9353   {
9354     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9355   },
9356
9357   /* VEX_LEN_0F41_P_0 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9361   },
9362   /* VEX_LEN_0F41_P_2 */
9363   {
9364     { Bad_Opcode },
9365     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9366   },
9367   /* VEX_LEN_0F42_P_0 */
9368   {
9369     { Bad_Opcode },
9370     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9371   },
9372   /* VEX_LEN_0F42_P_2 */
9373   {
9374     { Bad_Opcode },
9375     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9376   },
9377   /* VEX_LEN_0F44_P_0 */
9378   {
9379     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9380   },
9381   /* VEX_LEN_0F44_P_2 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9384   },
9385   /* VEX_LEN_0F45_P_0 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9389   },
9390   /* VEX_LEN_0F45_P_2 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9394   },
9395   /* VEX_LEN_0F46_P_0 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9399   },
9400   /* VEX_LEN_0F46_P_2 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9404   },
9405   /* VEX_LEN_0F47_P_0 */
9406   {
9407     { Bad_Opcode },
9408     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9409   },
9410   /* VEX_LEN_0F47_P_2 */
9411   {
9412     { Bad_Opcode },
9413     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9414   },
9415   /* VEX_LEN_0F4A_P_0 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9419   },
9420   /* VEX_LEN_0F4A_P_2 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9424   },
9425   /* VEX_LEN_0F4B_P_0 */
9426   {
9427     { Bad_Opcode },
9428     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9429   },
9430   /* VEX_LEN_0F4B_P_2 */
9431   {
9432     { Bad_Opcode },
9433     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9434   },
9435
9436   /* VEX_LEN_0F6E_P_2 */
9437   {
9438     { "vmovK",          { XMScalar, Edq }, 0 },
9439   },
9440
9441   /* VEX_LEN_0F77_P_1 */
9442   {
9443     { "vzeroupper",     { XX }, 0 },
9444     { "vzeroall",       { XX }, 0 },
9445   },
9446
9447   /* VEX_LEN_0F7E_P_1 */
9448   {
9449     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9450   },
9451
9452   /* VEX_LEN_0F7E_P_2 */
9453   {
9454     { "vmovK",          { Edq, XMScalar }, 0 },
9455   },
9456
9457   /* VEX_LEN_0F90_P_0 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9460   },
9461
9462   /* VEX_LEN_0F90_P_2 */
9463   {
9464     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9465   },
9466
9467   /* VEX_LEN_0F91_P_0 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F91_P_2 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F92_P_0 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F92_P_2 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F92_P_3 */
9488   {
9489     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0F93_P_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9495   },
9496
9497   /* VEX_LEN_0F93_P_2 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9500   },
9501
9502   /* VEX_LEN_0F93_P_3 */
9503   {
9504     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9505   },
9506
9507   /* VEX_LEN_0F98_P_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9510   },
9511
9512   /* VEX_LEN_0F98_P_2 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0F99_P_0 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9520   },
9521
9522   /* VEX_LEN_0F99_P_2 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9525   },
9526
9527   /* VEX_LEN_0FAE_R_2_M_0 */
9528   {
9529     { "vldmxcsr",       { Md }, 0 },
9530   },
9531
9532   /* VEX_LEN_0FAE_R_3_M_0 */
9533   {
9534     { "vstmxcsr",       { Md }, 0 },
9535   },
9536
9537   /* VEX_LEN_0FC4_P_2 */
9538   {
9539     { "vpinsrw",        { XM, Vex, Edqw, Ib }, 0 },
9540   },
9541
9542   /* VEX_LEN_0FC5_P_2 */
9543   {
9544     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9545   },
9546
9547   /* VEX_LEN_0FD6_P_2 */
9548   {
9549     { "vmovq",          { EXqS, XMScalar }, 0 },
9550   },
9551
9552   /* VEX_LEN_0FF7_P_2 */
9553   {
9554     { "vmaskmovdqu",    { XM, XS }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F3816_P_2 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9561   },
9562
9563   /* VEX_LEN_0F3819_P_2 */
9564   {
9565     { Bad_Opcode },
9566     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9567   },
9568
9569   /* VEX_LEN_0F381A_P_2_M_0 */
9570   {
9571     { Bad_Opcode },
9572     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0) },
9573   },
9574
9575   /* VEX_LEN_0F3836_P_2 */
9576   {
9577     { Bad_Opcode },
9578     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F3841_P_2 */
9582   {
9583     { "vphminposuw",    { XM, EXx }, 0 },
9584   },
9585
9586    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9587   {
9588     { "ldtilecfg", { M }, 0 },
9589   },
9590
9591   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9592   {
9593     { "tilerelease", { Skip_MODRM }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9597   {
9598     { "sttilecfg", { M }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9602   {
9603     { "tilezero", { TMM, Skip_MODRM }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9607   {
9608     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9609   },
9610   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9611   {
9612     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9616   {
9617     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F385A_P_2_M_0 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0) },
9624   },
9625
9626   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9627   {
9628     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9632   {
9633     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9637   {
9638     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9642   {
9643     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9647   {
9648     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9649   },
9650
9651   /* VEX_LEN_0F38DB_P_2 */
9652   {
9653     { "vaesimc",        { XM, EXx }, 0 },
9654   },
9655
9656   /* VEX_LEN_0F38F2_P_0 */
9657   {
9658     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F38F3_R_1_P_0 */
9662   {
9663     { "blsrS",          { VexGdq, Edq }, 0 },
9664   },
9665
9666   /* VEX_LEN_0F38F3_R_2_P_0 */
9667   {
9668     { "blsmskS",        { VexGdq, Edq }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F38F3_R_3_P_0 */
9672   {
9673     { "blsiS",          { VexGdq, Edq }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F38F5_P_0 */
9677   {
9678     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F38F5_P_1 */
9682   {
9683     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F38F5_P_3 */
9687   {
9688     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9689   },
9690
9691   /* VEX_LEN_0F38F6_P_3 */
9692   {
9693     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F38F7_P_0 */
9697   {
9698     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9699   },
9700
9701   /* VEX_LEN_0F38F7_P_1 */
9702   {
9703     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9704   },
9705
9706   /* VEX_LEN_0F38F7_P_2 */
9707   {
9708     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9709   },
9710
9711   /* VEX_LEN_0F38F7_P_3 */
9712   {
9713     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9714   },
9715
9716   /* VEX_LEN_0F3A00_P_2 */
9717   {
9718     { Bad_Opcode },
9719     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9720   },
9721
9722   /* VEX_LEN_0F3A01_P_2 */
9723   {
9724     { Bad_Opcode },
9725     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9726   },
9727
9728   /* VEX_LEN_0F3A06_P_2 */
9729   {
9730     { Bad_Opcode },
9731     { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0) },
9732   },
9733
9734   /* VEX_LEN_0F3A14_P_2 */
9735   {
9736     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9737   },
9738
9739   /* VEX_LEN_0F3A15_P_2 */
9740   {
9741     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9742   },
9743
9744   /* VEX_LEN_0F3A16_P_2  */
9745   {
9746     { "vpextrK",        { Edq, XM, Ib }, 0 },
9747   },
9748
9749   /* VEX_LEN_0F3A17_P_2 */
9750   {
9751     { "vextractps",     { Edqd, XM, Ib }, 0 },
9752   },
9753
9754   /* VEX_LEN_0F3A18_P_2 */
9755   {
9756     { Bad_Opcode },
9757     { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0) },
9758   },
9759
9760   /* VEX_LEN_0F3A19_P_2 */
9761   {
9762     { Bad_Opcode },
9763     { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0) },
9764   },
9765
9766   /* VEX_LEN_0F3A20_P_2 */
9767   {
9768     { "vpinsrb",        { XM, Vex, Edqb, Ib }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A21_P_2 */
9772   {
9773     { "vinsertps",      { XM, Vex, EXd, Ib }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A22_P_2 */
9777   {
9778     { "vpinsrK",        { XM, Vex, Edq, Ib }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A30_P_2 */
9782   {
9783     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9784   },
9785
9786   /* VEX_LEN_0F3A31_P_2 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9789   },
9790
9791   /* VEX_LEN_0F3A32_P_2 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9794   },
9795
9796   /* VEX_LEN_0F3A33_P_2 */
9797   {
9798     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9799   },
9800
9801   /* VEX_LEN_0F3A38_P_2 */
9802   {
9803     { Bad_Opcode },
9804     { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0) },
9805   },
9806
9807   /* VEX_LEN_0F3A39_P_2 */
9808   {
9809     { Bad_Opcode },
9810     { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0) },
9811   },
9812
9813   /* VEX_LEN_0F3A41_P_2 */
9814   {
9815     { "vdppd",          { XM, Vex, EXx, Ib }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3A46_P_2 */
9819   {
9820     { Bad_Opcode },
9821     { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0) },
9822   },
9823
9824   /* VEX_LEN_0F3A60_P_2 */
9825   {
9826     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
9827   },
9828
9829   /* VEX_LEN_0F3A61_P_2 */
9830   {
9831     { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F3A62_P_2 */
9835   {
9836     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9837   },
9838
9839   /* VEX_LEN_0F3A63_P_2 */
9840   {
9841     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9842   },
9843
9844   /* VEX_LEN_0F3ADF_P_2 */
9845   {
9846     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9847   },
9848
9849   /* VEX_LEN_0F3AF0_P_3 */
9850   {
9851     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9852   },
9853
9854   /* VEX_LEN_0FXOP_08_85 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9857   },
9858
9859   /* VEX_LEN_0FXOP_08_86 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9862   },
9863
9864   /* VEX_LEN_0FXOP_08_87 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9867   },
9868
9869   /* VEX_LEN_0FXOP_08_8E */
9870   {
9871     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9872   },
9873
9874   /* VEX_LEN_0FXOP_08_8F */
9875   {
9876     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9877   },
9878
9879   /* VEX_LEN_0FXOP_08_95 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9882   },
9883
9884   /* VEX_LEN_0FXOP_08_96 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9887   },
9888
9889   /* VEX_LEN_0FXOP_08_97 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9892   },
9893
9894   /* VEX_LEN_0FXOP_08_9E */
9895   {
9896     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9897   },
9898
9899   /* VEX_LEN_0FXOP_08_9F */
9900   {
9901     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9902   },
9903
9904   /* VEX_LEN_0FXOP_08_A3 */
9905   {
9906     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9907   },
9908
9909   /* VEX_LEN_0FXOP_08_A6 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9912   },
9913
9914   /* VEX_LEN_0FXOP_08_B6 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9917   },
9918
9919   /* VEX_LEN_0FXOP_08_C0 */
9920   {
9921     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9922   },
9923
9924   /* VEX_LEN_0FXOP_08_C1 */
9925   {
9926     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9927   },
9928
9929   /* VEX_LEN_0FXOP_08_C2 */
9930   {
9931     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9932   },
9933
9934   /* VEX_LEN_0FXOP_08_C3 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9937   },
9938
9939   /* VEX_LEN_0FXOP_08_CC */
9940   {
9941     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9942   },
9943
9944   /* VEX_LEN_0FXOP_08_CD */
9945   {
9946     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9947   },
9948
9949   /* VEX_LEN_0FXOP_08_CE */
9950   {
9951     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9952   },
9953
9954   /* VEX_LEN_0FXOP_08_CF */
9955   {
9956     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9957   },
9958
9959   /* VEX_LEN_0FXOP_08_EC */
9960   {
9961     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9962   },
9963
9964   /* VEX_LEN_0FXOP_08_ED */
9965   {
9966     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9967   },
9968
9969   /* VEX_LEN_0FXOP_08_EE */
9970   {
9971     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9972   },
9973
9974   /* VEX_LEN_0FXOP_08_EF */
9975   {
9976     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
9977   },
9978
9979   /* VEX_LEN_0FXOP_09_01 */
9980   {
9981     { REG_TABLE (REG_0FXOP_09_01_L_0) },
9982   },
9983
9984   /* VEX_LEN_0FXOP_09_02 */
9985   {
9986     { REG_TABLE (REG_0FXOP_09_02_L_0) },
9987   },
9988
9989   /* VEX_LEN_0FXOP_09_12_M_1 */
9990   {
9991     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
9992   },
9993
9994   /* VEX_LEN_0FXOP_09_82_W_0 */
9995   {
9996     { "vfrczss",        { XM, EXd }, 0 },
9997   },
9998
9999   /* VEX_LEN_0FXOP_09_83_W_0 */
10000   {
10001     { "vfrczsd",        { XM, EXq }, 0 },
10002   },
10003
10004   /* VEX_LEN_0FXOP_09_90 */
10005   {
10006     { "vprotb",         { XM, EXx, VexW }, 0 },
10007   },
10008
10009   /* VEX_LEN_0FXOP_09_91 */
10010   {
10011     { "vprotw",         { XM, EXx, VexW }, 0 },
10012   },
10013
10014   /* VEX_LEN_0FXOP_09_92 */
10015   {
10016     { "vprotd",         { XM, EXx, VexW }, 0 },
10017   },
10018
10019   /* VEX_LEN_0FXOP_09_93 */
10020   {
10021     { "vprotq",         { XM, EXx, VexW }, 0 },
10022   },
10023
10024   /* VEX_LEN_0FXOP_09_94 */
10025   {
10026     { "vpshlb",         { XM, EXx, VexW }, 0 },
10027   },
10028
10029   /* VEX_LEN_0FXOP_09_95 */
10030   {
10031     { "vpshlw",         { XM, EXx, VexW }, 0 },
10032   },
10033
10034   /* VEX_LEN_0FXOP_09_96 */
10035   {
10036     { "vpshld",         { XM, EXx, VexW }, 0 },
10037   },
10038
10039   /* VEX_LEN_0FXOP_09_97 */
10040   {
10041     { "vpshlq",         { XM, EXx, VexW }, 0 },
10042   },
10043
10044   /* VEX_LEN_0FXOP_09_98 */
10045   {
10046     { "vpshab",         { XM, EXx, VexW }, 0 },
10047   },
10048
10049   /* VEX_LEN_0FXOP_09_99 */
10050   {
10051     { "vpshaw",         { XM, EXx, VexW }, 0 },
10052   },
10053
10054   /* VEX_LEN_0FXOP_09_9A */
10055   {
10056     { "vpshad",         { XM, EXx, VexW }, 0 },
10057   },
10058
10059   /* VEX_LEN_0FXOP_09_9B */
10060   {
10061     { "vpshaq",         { XM, EXx, VexW }, 0 },
10062   },
10063
10064   /* VEX_LEN_0FXOP_09_C1 */
10065   {
10066     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10067   },
10068
10069   /* VEX_LEN_0FXOP_09_C2 */
10070   {
10071     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10072   },
10073
10074   /* VEX_LEN_0FXOP_09_C3 */
10075   {
10076     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10077   },
10078
10079   /* VEX_LEN_0FXOP_09_C6 */
10080   {
10081     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10082   },
10083
10084   /* VEX_LEN_0FXOP_09_C7 */
10085   {
10086     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10087   },
10088
10089   /* VEX_LEN_0FXOP_09_CB */
10090   {
10091     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10092   },
10093
10094   /* VEX_LEN_0FXOP_09_D1 */
10095   {
10096     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10097   },
10098
10099   /* VEX_LEN_0FXOP_09_D2 */
10100   {
10101     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10102   },
10103
10104   /* VEX_LEN_0FXOP_09_D3 */
10105   {
10106     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10107   },
10108
10109   /* VEX_LEN_0FXOP_09_D6 */
10110   {
10111     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10112   },
10113
10114   /* VEX_LEN_0FXOP_09_D7 */
10115   {
10116     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10117   },
10118
10119   /* VEX_LEN_0FXOP_09_DB */
10120   {
10121     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10122   },
10123
10124   /* VEX_LEN_0FXOP_09_E1 */
10125   {
10126     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10127   },
10128
10129   /* VEX_LEN_0FXOP_09_E2 */
10130   {
10131     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10132   },
10133
10134   /* VEX_LEN_0FXOP_09_E3 */
10135   {
10136     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10137   },
10138
10139   /* VEX_LEN_0FXOP_0A_12 */
10140   {
10141     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10142   },
10143 };
10144
10145 #include "i386-dis-evex-len.h"
10146
10147 static const struct dis386 vex_w_table[][2] = {
10148   {
10149     /* VEX_W_0F41_P_0_LEN_1 */
10150     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10151     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10152   },
10153   {
10154     /* VEX_W_0F41_P_2_LEN_1 */
10155     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10156     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10157   },
10158   {
10159     /* VEX_W_0F42_P_0_LEN_1 */
10160     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10161     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10162   },
10163   {
10164     /* VEX_W_0F42_P_2_LEN_1 */
10165     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10166     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10167   },
10168   {
10169     /* VEX_W_0F44_P_0_LEN_0 */
10170     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10171     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10172   },
10173   {
10174     /* VEX_W_0F44_P_2_LEN_0 */
10175     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10176     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10177   },
10178   {
10179     /* VEX_W_0F45_P_0_LEN_1 */
10180     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10181     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10182   },
10183   {
10184     /* VEX_W_0F45_P_2_LEN_1 */
10185     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10186     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10187   },
10188   {
10189     /* VEX_W_0F46_P_0_LEN_1 */
10190     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10191     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10192   },
10193   {
10194     /* VEX_W_0F46_P_2_LEN_1 */
10195     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10196     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10197   },
10198   {
10199     /* VEX_W_0F47_P_0_LEN_1 */
10200     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10201     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10202   },
10203   {
10204     /* VEX_W_0F47_P_2_LEN_1 */
10205     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10206     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10207   },
10208   {
10209     /* VEX_W_0F4A_P_0_LEN_1 */
10210     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10211     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10212   },
10213   {
10214     /* VEX_W_0F4A_P_2_LEN_1 */
10215     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10216     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10217   },
10218   {
10219     /* VEX_W_0F4B_P_0_LEN_1 */
10220     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10221     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10222   },
10223   {
10224     /* VEX_W_0F4B_P_2_LEN_1 */
10225     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10226   },
10227   {
10228     /* VEX_W_0F90_P_0_LEN_0 */
10229     { "kmovw",          { MaskG, MaskE }, 0 },
10230     { "kmovq",          { MaskG, MaskE }, 0 },
10231   },
10232   {
10233     /* VEX_W_0F90_P_2_LEN_0 */
10234     { "kmovb",          { MaskG, MaskBDE }, 0 },
10235     { "kmovd",          { MaskG, MaskBDE }, 0 },
10236   },
10237   {
10238     /* VEX_W_0F91_P_0_LEN_0 */
10239     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10240     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10241   },
10242   {
10243     /* VEX_W_0F91_P_2_LEN_0 */
10244     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10245     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10246   },
10247   {
10248     /* VEX_W_0F92_P_0_LEN_0 */
10249     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10250   },
10251   {
10252     /* VEX_W_0F92_P_2_LEN_0 */
10253     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10254   },
10255   {
10256     /* VEX_W_0F93_P_0_LEN_0 */
10257     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10258   },
10259   {
10260     /* VEX_W_0F93_P_2_LEN_0 */
10261     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10262   },
10263   {
10264     /* VEX_W_0F98_P_0_LEN_0 */
10265     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10266     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10267   },
10268   {
10269     /* VEX_W_0F98_P_2_LEN_0 */
10270     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10271     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10272   },
10273   {
10274     /* VEX_W_0F99_P_0_LEN_0 */
10275     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10276     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10277   },
10278   {
10279     /* VEX_W_0F99_P_2_LEN_0 */
10280     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10281     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10282   },
10283   {
10284     /* VEX_W_0F380C_P_2  */
10285     { "vpermilps",      { XM, Vex, EXx }, 0 },
10286   },
10287   {
10288     /* VEX_W_0F380D_P_2  */
10289     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10290   },
10291   {
10292     /* VEX_W_0F380E_P_2  */
10293     { "vtestps",        { XM, EXx }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F380F_P_2  */
10297     { "vtestpd",        { XM, EXx }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F3813_P_2 */
10301     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F3816_P_2  */
10305     { "vpermps",        { XM, Vex, EXx }, 0 },
10306   },
10307   {
10308     /* VEX_W_0F3818_P_2 */
10309     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10310   },
10311   {
10312     /* VEX_W_0F3819_P_2 */
10313     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F381A_P_2_M_0_L_0 */
10317     { "vbroadcastf128", { XM, Mxmm }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F382C_P_2_M_0 */
10321     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F382D_P_2_M_0 */
10325     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F382E_P_2_M_0 */
10329     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F382F_P_2_M_0 */
10333     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F3836_P_2  */
10337     { "vpermd",         { XM, Vex, EXx }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F3846_P_2 */
10341     { "vpsravd",        { XM, Vex, EXx }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F3849_X86_64_P_0 */
10345     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10346   },
10347   {
10348     /* VEX_W_0F3849_X86_64_P_2 */
10349     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10350   },
10351   {
10352     /* VEX_W_0F3849_X86_64_P_3 */
10353     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10354   },
10355   {
10356     /* VEX_W_0F384B_X86_64_P_1 */
10357     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10358   },
10359   {
10360     /* VEX_W_0F384B_X86_64_P_2 */
10361     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10362   },
10363   {
10364     /* VEX_W_0F384B_X86_64_P_3 */
10365     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10366   },
10367   {
10368     /* VEX_W_0F3858_P_2 */
10369     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10370   },
10371   {
10372     /* VEX_W_0F3859_P_2 */
10373     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F385A_P_2_M_0_L_0 */
10377     { "vbroadcasti128", { XM, Mxmm }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F385C_X86_64_P_1 */
10381     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10382   },
10383   {
10384     /* VEX_W_0F385E_X86_64_P_0 */
10385     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10386   },
10387   {
10388     /* VEX_W_0F385E_X86_64_P_1 */
10389     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10390   },
10391   {
10392     /* VEX_W_0F385E_X86_64_P_2 */
10393     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10394   },
10395   {
10396     /* VEX_W_0F385E_X86_64_P_3 */
10397     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10398   },
10399   {
10400     /* VEX_W_0F3878_P_2 */
10401     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10402   },
10403   {
10404     /* VEX_W_0F3879_P_2 */
10405     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10406   },
10407   {
10408     /* VEX_W_0F38CF_P_2 */
10409     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F3A00_P_2 */
10413     { Bad_Opcode },
10414     { "vpermq",         { XM, EXx, Ib }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F3A01_P_2 */
10418     { Bad_Opcode },
10419     { "vpermpd",        { XM, EXx, Ib }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F3A02_P_2 */
10423     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F3A04_P_2 */
10427     { "vpermilps",      { XM, EXx, Ib }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F3A05_P_2 */
10431     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F3A06_P_2_L_0 */
10435     { "vperm2f128",     { XM, Vex, EXx, Ib }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F3A18_P_2_L_0 */
10439     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F3A19_P_2_L_0 */
10443     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F3A1D_P_2 */
10447     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F3A30_P_2_LEN_0 */
10451     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10452     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10453   },
10454   {
10455     /* VEX_W_0F3A31_P_2_LEN_0 */
10456     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10457     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10458   },
10459   {
10460     /* VEX_W_0F3A32_P_2_LEN_0 */
10461     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10462     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10463   },
10464   {
10465     /* VEX_W_0F3A33_P_2_LEN_0 */
10466     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10467     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10468   },
10469   {
10470     /* VEX_W_0F3A38_P_2_L_0 */
10471     { "vinserti128",    { XM, Vex, EXxmm, Ib }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F3A39_P_2_L_0 */
10475     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F3A46_P_2_L_0 */
10479     { "vperm2i128",     { XM, Vex, EXx, Ib }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F3A4A_P_2 */
10483     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F3A4B_P_2 */
10487     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F3A4C_P_2 */
10491     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F3ACE_P_2 */
10495     { Bad_Opcode },
10496     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F3ACF_P_2 */
10500     { Bad_Opcode },
10501     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10502   },
10503   /* VEX_W_0FXOP_08_85_L_0 */
10504   {
10505     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10506   },
10507   /* VEX_W_0FXOP_08_86_L_0 */
10508   {
10509     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10510   },
10511   /* VEX_W_0FXOP_08_87_L_0 */
10512   {
10513     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10514   },
10515   /* VEX_W_0FXOP_08_8E_L_0 */
10516   {
10517     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10518   },
10519   /* VEX_W_0FXOP_08_8F_L_0 */
10520   {
10521     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10522   },
10523   /* VEX_W_0FXOP_08_95_L_0 */
10524   {
10525     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10526   },
10527   /* VEX_W_0FXOP_08_96_L_0 */
10528   {
10529     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10530   },
10531   /* VEX_W_0FXOP_08_97_L_0 */
10532   {
10533     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10534   },
10535   /* VEX_W_0FXOP_08_9E_L_0 */
10536   {
10537     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10538   },
10539   /* VEX_W_0FXOP_08_9F_L_0 */
10540   {
10541     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10542   },
10543   /* VEX_W_0FXOP_08_A6_L_0 */
10544   {
10545     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10546   },
10547   /* VEX_W_0FXOP_08_B6_L_0 */
10548   {
10549     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10550   },
10551   /* VEX_W_0FXOP_08_C0_L_0 */
10552   {
10553     { "vprotb",         { XM, EXx, Ib }, 0 },
10554   },
10555   /* VEX_W_0FXOP_08_C1_L_0 */
10556   {
10557     { "vprotw",         { XM, EXx, Ib }, 0 },
10558   },
10559   /* VEX_W_0FXOP_08_C2_L_0 */
10560   {
10561     { "vprotd",         { XM, EXx, Ib }, 0 },
10562   },
10563   /* VEX_W_0FXOP_08_C3_L_0 */
10564   {
10565     { "vprotq",         { XM, EXx, Ib }, 0 },
10566   },
10567   /* VEX_W_0FXOP_08_CC_L_0 */
10568   {
10569      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
10570   },
10571   /* VEX_W_0FXOP_08_CD_L_0 */
10572   {
10573      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
10574   },
10575   /* VEX_W_0FXOP_08_CE_L_0 */
10576   {
10577      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
10578   },
10579   /* VEX_W_0FXOP_08_CF_L_0 */
10580   {
10581      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
10582   },
10583   /* VEX_W_0FXOP_08_EC_L_0 */
10584   {
10585      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
10586   },
10587   /* VEX_W_0FXOP_08_ED_L_0 */
10588   {
10589      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
10590   },
10591   /* VEX_W_0FXOP_08_EE_L_0 */
10592   {
10593      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
10594   },
10595   /* VEX_W_0FXOP_08_EF_L_0 */
10596   {
10597      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
10598   },
10599   /* VEX_W_0FXOP_09_80 */
10600   {
10601     { "vfrczps",        { XM, EXx }, 0 },
10602   },
10603   /* VEX_W_0FXOP_09_81 */
10604   {
10605     { "vfrczpd",        { XM, EXx }, 0 },
10606   },
10607   /* VEX_W_0FXOP_09_82 */
10608   {
10609     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10610   },
10611   /* VEX_W_0FXOP_09_83 */
10612   {
10613     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10614   },
10615   /* VEX_W_0FXOP_09_C1_L_0 */
10616   {
10617     { "vphaddbw",       { XM, EXxmm }, 0 },
10618   },
10619   /* VEX_W_0FXOP_09_C2_L_0 */
10620   {
10621     { "vphaddbd",       { XM, EXxmm }, 0 },
10622   },
10623   /* VEX_W_0FXOP_09_C3_L_0 */
10624   {
10625     { "vphaddbq",       { XM, EXxmm }, 0 },
10626   },
10627   /* VEX_W_0FXOP_09_C6_L_0 */
10628   {
10629     { "vphaddwd",       { XM, EXxmm }, 0 },
10630   },
10631   /* VEX_W_0FXOP_09_C7_L_0 */
10632   {
10633     { "vphaddwq",       { XM, EXxmm }, 0 },
10634   },
10635   /* VEX_W_0FXOP_09_CB_L_0 */
10636   {
10637     { "vphadddq",       { XM, EXxmm }, 0 },
10638   },
10639   /* VEX_W_0FXOP_09_D1_L_0 */
10640   {
10641     { "vphaddubw",      { XM, EXxmm }, 0 },
10642   },
10643   /* VEX_W_0FXOP_09_D2_L_0 */
10644   {
10645     { "vphaddubd",      { XM, EXxmm }, 0 },
10646   },
10647   /* VEX_W_0FXOP_09_D3_L_0 */
10648   {
10649     { "vphaddubq",      { XM, EXxmm }, 0 },
10650   },
10651   /* VEX_W_0FXOP_09_D6_L_0 */
10652   {
10653     { "vphadduwd",      { XM, EXxmm }, 0 },
10654   },
10655   /* VEX_W_0FXOP_09_D7_L_0 */
10656   {
10657     { "vphadduwq",      { XM, EXxmm }, 0 },
10658   },
10659   /* VEX_W_0FXOP_09_DB_L_0 */
10660   {
10661     { "vphaddudq",      { XM, EXxmm }, 0 },
10662   },
10663   /* VEX_W_0FXOP_09_E1_L_0 */
10664   {
10665     { "vphsubbw",       { XM, EXxmm }, 0 },
10666   },
10667   /* VEX_W_0FXOP_09_E2_L_0 */
10668   {
10669     { "vphsubwd",       { XM, EXxmm }, 0 },
10670   },
10671   /* VEX_W_0FXOP_09_E3_L_0 */
10672   {
10673     { "vphsubdq",       { XM, EXxmm }, 0 },
10674   },
10675
10676 #include "i386-dis-evex-w.h"
10677 };
10678
10679 static const struct dis386 mod_table[][2] = {
10680   {
10681     /* MOD_8D */
10682     { "leaS",           { Gv, M }, 0 },
10683   },
10684   {
10685     /* MOD_C6_REG_7 */
10686     { Bad_Opcode },
10687     { RM_TABLE (RM_C6_REG_7) },
10688   },
10689   {
10690     /* MOD_C7_REG_7 */
10691     { Bad_Opcode },
10692     { RM_TABLE (RM_C7_REG_7) },
10693   },
10694   {
10695     /* MOD_FF_REG_3 */
10696     { "{l|}call^", { indirEp }, 0 },
10697   },
10698   {
10699     /* MOD_FF_REG_5 */
10700     { "{l|}jmp^", { indirEp }, 0 },
10701   },
10702   {
10703     /* MOD_0F01_REG_0 */
10704     { X86_64_TABLE (X86_64_0F01_REG_0) },
10705     { RM_TABLE (RM_0F01_REG_0) },
10706   },
10707   {
10708     /* MOD_0F01_REG_1 */
10709     { X86_64_TABLE (X86_64_0F01_REG_1) },
10710     { RM_TABLE (RM_0F01_REG_1) },
10711   },
10712   {
10713     /* MOD_0F01_REG_2 */
10714     { X86_64_TABLE (X86_64_0F01_REG_2) },
10715     { RM_TABLE (RM_0F01_REG_2) },
10716   },
10717   {
10718     /* MOD_0F01_REG_3 */
10719     { X86_64_TABLE (X86_64_0F01_REG_3) },
10720     { RM_TABLE (RM_0F01_REG_3) },
10721   },
10722   {
10723     /* MOD_0F01_REG_5 */
10724     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10725     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10726   },
10727   {
10728     /* MOD_0F01_REG_7 */
10729     { "invlpg",         { Mb }, 0 },
10730     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10731   },
10732   {
10733     /* MOD_0F12_PREFIX_0 */
10734     { "movlpX",         { XM, EXq }, 0 },
10735     { "movhlps",        { XM, EXq }, 0 },
10736   },
10737   {
10738     /* MOD_0F12_PREFIX_2 */
10739     { "movlpX", { XM, EXq }, 0 },
10740   },
10741   {
10742     /* MOD_0F13 */
10743     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10744   },
10745   {
10746     /* MOD_0F16_PREFIX_0 */
10747     { "movhpX",         { XM, EXq }, 0 },
10748     { "movlhps",        { XM, EXq }, 0 },
10749   },
10750   {
10751     /* MOD_0F16_PREFIX_2 */
10752     { "movhpX", { XM, EXq }, 0 },
10753   },
10754   {
10755     /* MOD_0F17 */
10756     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10757   },
10758   {
10759     /* MOD_0F18_REG_0 */
10760     { "prefetchnta",    { Mb }, 0 },
10761   },
10762   {
10763     /* MOD_0F18_REG_1 */
10764     { "prefetcht0",     { Mb }, 0 },
10765   },
10766   {
10767     /* MOD_0F18_REG_2 */
10768     { "prefetcht1",     { Mb }, 0 },
10769   },
10770   {
10771     /* MOD_0F18_REG_3 */
10772     { "prefetcht2",     { Mb }, 0 },
10773   },
10774   {
10775     /* MOD_0F18_REG_4 */
10776     { "nop/reserved",   { Mb }, 0 },
10777   },
10778   {
10779     /* MOD_0F18_REG_5 */
10780     { "nop/reserved",   { Mb }, 0 },
10781   },
10782   {
10783     /* MOD_0F18_REG_6 */
10784     { "nop/reserved",   { Mb }, 0 },
10785   },
10786   {
10787     /* MOD_0F18_REG_7 */
10788     { "nop/reserved",   { Mb }, 0 },
10789   },
10790   {
10791     /* MOD_0F1A_PREFIX_0 */
10792     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10793     { "nopQ",           { Ev }, 0 },
10794   },
10795   {
10796     /* MOD_0F1B_PREFIX_0 */
10797     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10798     { "nopQ",           { Ev }, 0 },
10799   },
10800   {
10801     /* MOD_0F1B_PREFIX_1 */
10802     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10803     { "nopQ",           { Ev }, 0 },
10804   },
10805   {
10806     /* MOD_0F1C_PREFIX_0 */
10807     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10808     { "nopQ",           { Ev }, 0 },
10809   },
10810   {
10811     /* MOD_0F1E_PREFIX_1 */
10812     { "nopQ",           { Ev }, 0 },
10813     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10814   },
10815   {
10816     /* MOD_0F24 */
10817     { Bad_Opcode },
10818     { "movL",           { Rd, Td }, 0 },
10819   },
10820   {
10821     /* MOD_0F26 */
10822     { Bad_Opcode },
10823     { "movL",           { Td, Rd }, 0 },
10824   },
10825   {
10826     /* MOD_0F2B_PREFIX_0 */
10827     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10828   },
10829   {
10830     /* MOD_0F2B_PREFIX_1 */
10831     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10832   },
10833   {
10834     /* MOD_0F2B_PREFIX_2 */
10835     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10836   },
10837   {
10838     /* MOD_0F2B_PREFIX_3 */
10839     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10840   },
10841   {
10842     /* MOD_0F50 */
10843     { Bad_Opcode },
10844     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10845   },
10846   {
10847     /* MOD_0F71_REG_2 */
10848     { Bad_Opcode },
10849     { "psrlw",          { MS, Ib }, 0 },
10850   },
10851   {
10852     /* MOD_0F71_REG_4 */
10853     { Bad_Opcode },
10854     { "psraw",          { MS, Ib }, 0 },
10855   },
10856   {
10857     /* MOD_0F71_REG_6 */
10858     { Bad_Opcode },
10859     { "psllw",          { MS, Ib }, 0 },
10860   },
10861   {
10862     /* MOD_0F72_REG_2 */
10863     { Bad_Opcode },
10864     { "psrld",          { MS, Ib }, 0 },
10865   },
10866   {
10867     /* MOD_0F72_REG_4 */
10868     { Bad_Opcode },
10869     { "psrad",          { MS, Ib }, 0 },
10870   },
10871   {
10872     /* MOD_0F72_REG_6 */
10873     { Bad_Opcode },
10874     { "pslld",          { MS, Ib }, 0 },
10875   },
10876   {
10877     /* MOD_0F73_REG_2 */
10878     { Bad_Opcode },
10879     { "psrlq",          { MS, Ib }, 0 },
10880   },
10881   {
10882     /* MOD_0F73_REG_3 */
10883     { Bad_Opcode },
10884     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10885   },
10886   {
10887     /* MOD_0F73_REG_6 */
10888     { Bad_Opcode },
10889     { "psllq",          { MS, Ib }, 0 },
10890   },
10891   {
10892     /* MOD_0F73_REG_7 */
10893     { Bad_Opcode },
10894     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10895   },
10896   {
10897     /* MOD_0FAE_REG_0 */
10898     { "fxsave",         { FXSAVE }, 0 },
10899     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10900   },
10901   {
10902     /* MOD_0FAE_REG_1 */
10903     { "fxrstor",        { FXSAVE }, 0 },
10904     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10905   },
10906   {
10907     /* MOD_0FAE_REG_2 */
10908     { "ldmxcsr",        { Md }, 0 },
10909     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10910   },
10911   {
10912     /* MOD_0FAE_REG_3 */
10913     { "stmxcsr",        { Md }, 0 },
10914     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10915   },
10916   {
10917     /* MOD_0FAE_REG_4 */
10918     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10919     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10920   },
10921   {
10922     /* MOD_0FAE_REG_5 */
10923     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10924     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10925   },
10926   {
10927     /* MOD_0FAE_REG_6 */
10928     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10929     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10930   },
10931   {
10932     /* MOD_0FAE_REG_7 */
10933     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10934     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10935   },
10936   {
10937     /* MOD_0FB2 */
10938     { "lssS",           { Gv, Mp }, 0 },
10939   },
10940   {
10941     /* MOD_0FB4 */
10942     { "lfsS",           { Gv, Mp }, 0 },
10943   },
10944   {
10945     /* MOD_0FB5 */
10946     { "lgsS",           { Gv, Mp }, 0 },
10947   },
10948   {
10949     /* MOD_0FC3 */
10950     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10951   },
10952   {
10953     /* MOD_0FC7_REG_3 */
10954     { "xrstors",        { FXSAVE }, 0 },
10955   },
10956   {
10957     /* MOD_0FC7_REG_4 */
10958     { "xsavec",         { FXSAVE }, 0 },
10959   },
10960   {
10961     /* MOD_0FC7_REG_5 */
10962     { "xsaves",         { FXSAVE }, 0 },
10963   },
10964   {
10965     /* MOD_0FC7_REG_6 */
10966     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10967     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10968   },
10969   {
10970     /* MOD_0FC7_REG_7 */
10971     { "vmptrst",        { Mq }, 0 },
10972     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10973   },
10974   {
10975     /* MOD_0FD7 */
10976     { Bad_Opcode },
10977     { "pmovmskb",       { Gdq, MS }, 0 },
10978   },
10979   {
10980     /* MOD_0FE7_PREFIX_2 */
10981     { "movntdq",        { Mx, XM }, 0 },
10982   },
10983   {
10984     /* MOD_0FF0_PREFIX_3 */
10985     { "lddqu",          { XM, M }, 0 },
10986   },
10987   {
10988     /* MOD_0F382A_PREFIX_2 */
10989     { "movntdqa",       { XM, Mx }, 0 },
10990   },
10991   {
10992     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
10993     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
10994     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
10995   },
10996   {
10997     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
10998     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
10999   },
11000   {
11001     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11002     { Bad_Opcode },
11003     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11004   },
11005   {
11006     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11007     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11008   },
11009   {
11010     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11011     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11012   },
11013   {
11014     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11015     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11016   },
11017   {
11018     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11019     { Bad_Opcode },
11020     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11021   },
11022   {
11023     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11024     { Bad_Opcode },
11025     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11026   },
11027   {
11028     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11029     { Bad_Opcode },
11030     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11031   },
11032   {
11033     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11034     { Bad_Opcode },
11035     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11036   },
11037   {
11038     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11039     { Bad_Opcode },
11040     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11041   },
11042   {
11043     /* MOD_0F38F5_PREFIX_2 */
11044     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11045   },
11046   {
11047     /* MOD_0F38F6_PREFIX_0 */
11048     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11049   },
11050   {
11051     /* MOD_0F38F8_PREFIX_1 */
11052     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11053   },
11054   {
11055     /* MOD_0F38F8_PREFIX_2 */
11056     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11057   },
11058   {
11059     /* MOD_0F38F8_PREFIX_3 */
11060     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11061   },
11062   {
11063     /* MOD_0F38F9_PREFIX_0 */
11064     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11065   },
11066   {
11067     /* MOD_62_32BIT */
11068     { "bound{S|}",      { Gv, Ma }, 0 },
11069     { EVEX_TABLE (EVEX_0F) },
11070   },
11071   {
11072     /* MOD_C4_32BIT */
11073     { "lesS",           { Gv, Mp }, 0 },
11074     { VEX_C4_TABLE (VEX_0F) },
11075   },
11076   {
11077     /* MOD_C5_32BIT */
11078     { "ldsS",           { Gv, Mp }, 0 },
11079     { VEX_C5_TABLE (VEX_0F) },
11080   },
11081   {
11082     /* MOD_VEX_0F12_PREFIX_0 */
11083     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11084     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11085   },
11086   {
11087     /* MOD_VEX_0F12_PREFIX_2 */
11088     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11089   },
11090   {
11091     /* MOD_VEX_0F13 */
11092     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11093   },
11094   {
11095     /* MOD_VEX_0F16_PREFIX_0 */
11096     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11097     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11098   },
11099   {
11100     /* MOD_VEX_0F16_PREFIX_2 */
11101     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11102   },
11103   {
11104     /* MOD_VEX_0F17 */
11105     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11106   },
11107   {
11108     /* MOD_VEX_0F2B */
11109     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11110   },
11111   {
11112     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11113     { Bad_Opcode },
11114     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11115   },
11116   {
11117     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11118     { Bad_Opcode },
11119     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11120   },
11121   {
11122     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11123     { Bad_Opcode },
11124     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11125   },
11126   {
11127     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11128     { Bad_Opcode },
11129     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11130   },
11131   {
11132     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11133     { Bad_Opcode },
11134     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11135   },
11136   {
11137     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11138     { Bad_Opcode },
11139     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11140   },
11141   {
11142     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11143     { Bad_Opcode },
11144     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11145   },
11146   {
11147     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11148     { Bad_Opcode },
11149     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11150   },
11151   {
11152     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11153     { Bad_Opcode },
11154     { "knotw",          { MaskG, MaskR }, 0 },
11155   },
11156   {
11157     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11158     { Bad_Opcode },
11159     { "knotq",          { MaskG, MaskR }, 0 },
11160   },
11161   {
11162     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11163     { Bad_Opcode },
11164     { "knotb",          { MaskG, MaskR }, 0 },
11165   },
11166   {
11167     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11168     { Bad_Opcode },
11169     { "knotd",          { MaskG, MaskR }, 0 },
11170   },
11171   {
11172     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11173     { Bad_Opcode },
11174     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11175   },
11176   {
11177     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11178     { Bad_Opcode },
11179     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11180   },
11181   {
11182     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11183     { Bad_Opcode },
11184     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11185   },
11186   {
11187     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11188     { Bad_Opcode },
11189     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11190   },
11191  {
11192     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11193     { Bad_Opcode },
11194     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11195   },
11196   {
11197     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11198     { Bad_Opcode },
11199     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11200   },
11201   {
11202     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11203     { Bad_Opcode },
11204     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11205   },
11206   {
11207     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11208     { Bad_Opcode },
11209     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11210   },
11211   {
11212     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11213     { Bad_Opcode },
11214     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11215   },
11216   {
11217     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11218     { Bad_Opcode },
11219     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11220   },
11221   {
11222     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11223     { Bad_Opcode },
11224     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11225   },
11226   {
11227     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11228     { Bad_Opcode },
11229     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11230   },
11231   {
11232     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11233     { Bad_Opcode },
11234     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11235   },
11236   {
11237     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11238     { Bad_Opcode },
11239     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11240   },
11241   {
11242     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11243     { Bad_Opcode },
11244     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11245   },
11246   {
11247     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11248     { Bad_Opcode },
11249     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11250   },
11251   {
11252     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11253     { Bad_Opcode },
11254     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11255   },
11256   {
11257     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11258     { Bad_Opcode },
11259     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11260   },
11261   {
11262     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11263     { Bad_Opcode },
11264     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11265   },
11266   {
11267     /* MOD_VEX_0F50 */
11268     { Bad_Opcode },
11269     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11270   },
11271   {
11272     /* MOD_VEX_0F71_REG_2 */
11273     { Bad_Opcode },
11274     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11275   },
11276   {
11277     /* MOD_VEX_0F71_REG_4 */
11278     { Bad_Opcode },
11279     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11280   },
11281   {
11282     /* MOD_VEX_0F71_REG_6 */
11283     { Bad_Opcode },
11284     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11285   },
11286   {
11287     /* MOD_VEX_0F72_REG_2 */
11288     { Bad_Opcode },
11289     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11290   },
11291   {
11292     /* MOD_VEX_0F72_REG_4 */
11293     { Bad_Opcode },
11294     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11295   },
11296   {
11297     /* MOD_VEX_0F72_REG_6 */
11298     { Bad_Opcode },
11299     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11300   },
11301   {
11302     /* MOD_VEX_0F73_REG_2 */
11303     { Bad_Opcode },
11304     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11305   },
11306   {
11307     /* MOD_VEX_0F73_REG_3 */
11308     { Bad_Opcode },
11309     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11310   },
11311   {
11312     /* MOD_VEX_0F73_REG_6 */
11313     { Bad_Opcode },
11314     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11315   },
11316   {
11317     /* MOD_VEX_0F73_REG_7 */
11318     { Bad_Opcode },
11319     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11320   },
11321   {
11322     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11323     { "kmovw",          { Ew, MaskG }, 0 },
11324     { Bad_Opcode },
11325   },
11326   {
11327     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11328     { "kmovq",          { Eq, MaskG }, 0 },
11329     { Bad_Opcode },
11330   },
11331   {
11332     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11333     { "kmovb",          { Eb, MaskG }, 0 },
11334     { Bad_Opcode },
11335   },
11336   {
11337     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11338     { "kmovd",          { Ed, MaskG }, 0 },
11339     { Bad_Opcode },
11340   },
11341   {
11342     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11343     { Bad_Opcode },
11344     { "kmovw",          { MaskG, Rdq }, 0 },
11345   },
11346   {
11347     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11348     { Bad_Opcode },
11349     { "kmovb",          { MaskG, Rdq }, 0 },
11350   },
11351   {
11352     /* MOD_VEX_0F92_P_3_LEN_0 */
11353     { Bad_Opcode },
11354     { "kmovK",          { MaskG, Rdq }, 0 },
11355   },
11356   {
11357     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11358     { Bad_Opcode },
11359     { "kmovw",          { Gdq, MaskR }, 0 },
11360   },
11361   {
11362     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11363     { Bad_Opcode },
11364     { "kmovb",          { Gdq, MaskR }, 0 },
11365   },
11366   {
11367     /* MOD_VEX_0F93_P_3_LEN_0 */
11368     { Bad_Opcode },
11369     { "kmovK",          { Gdq, MaskR }, 0 },
11370   },
11371   {
11372     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11373     { Bad_Opcode },
11374     { "kortestw", { MaskG, MaskR }, 0 },
11375   },
11376   {
11377     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11378     { Bad_Opcode },
11379     { "kortestq", { MaskG, MaskR }, 0 },
11380   },
11381   {
11382     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11383     { Bad_Opcode },
11384     { "kortestb", { MaskG, MaskR }, 0 },
11385   },
11386   {
11387     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11388     { Bad_Opcode },
11389     { "kortestd", { MaskG, MaskR }, 0 },
11390   },
11391   {
11392     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11393     { Bad_Opcode },
11394     { "ktestw", { MaskG, MaskR }, 0 },
11395   },
11396   {
11397     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11398     { Bad_Opcode },
11399     { "ktestq", { MaskG, MaskR }, 0 },
11400   },
11401   {
11402     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11403     { Bad_Opcode },
11404     { "ktestb", { MaskG, MaskR }, 0 },
11405   },
11406   {
11407     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11408     { Bad_Opcode },
11409     { "ktestd", { MaskG, MaskR }, 0 },
11410   },
11411   {
11412     /* MOD_VEX_0FAE_REG_2 */
11413     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11414   },
11415   {
11416     /* MOD_VEX_0FAE_REG_3 */
11417     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11418   },
11419   {
11420     /* MOD_VEX_0FD7_PREFIX_2 */
11421     { Bad_Opcode },
11422     { "vpmovmskb",      { Gdq, XS }, 0 },
11423   },
11424   {
11425     /* MOD_VEX_0FE7_PREFIX_2 */
11426     { "vmovntdq",       { Mx, XM }, 0 },
11427   },
11428   {
11429     /* MOD_VEX_0FF0_PREFIX_3 */
11430     { "vlddqu",         { XM, M }, 0 },
11431   },
11432   {
11433     /* MOD_VEX_0F381A_PREFIX_2 */
11434     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11435   },
11436   {
11437     /* MOD_VEX_0F382A_PREFIX_2 */
11438     { "vmovntdqa",      { XM, Mx }, 0 },
11439   },
11440   {
11441     /* MOD_VEX_0F382C_PREFIX_2 */
11442     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11443   },
11444   {
11445     /* MOD_VEX_0F382D_PREFIX_2 */
11446     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0F382E_PREFIX_2 */
11450     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11451   },
11452   {
11453     /* MOD_VEX_0F382F_PREFIX_2 */
11454     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11455   },
11456   {
11457     /* MOD_VEX_0F385A_PREFIX_2 */
11458     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11459   },
11460   {
11461     /* MOD_VEX_0F388C_PREFIX_2 */
11462     { "vpmaskmov%DQ",   { XM, Vex, Mx }, 0 },
11463   },
11464   {
11465     /* MOD_VEX_0F388E_PREFIX_2 */
11466     { "vpmaskmov%DQ",   { Mx, Vex, XM }, 0 },
11467   },
11468   {
11469     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11470     { Bad_Opcode },
11471     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11472   },
11473   {
11474     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11475     { Bad_Opcode },
11476     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11477   },
11478   {
11479     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11480     { Bad_Opcode },
11481     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11482   },
11483   {
11484     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11485     { Bad_Opcode },
11486     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11487   },
11488   {
11489     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11490     { Bad_Opcode },
11491     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11492   },
11493   {
11494     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11495     { Bad_Opcode },
11496     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11497   },
11498   {
11499     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11500     { Bad_Opcode },
11501     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11502   },
11503   {
11504     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11505     { Bad_Opcode },
11506     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11507   },
11508   {
11509     /* MOD_VEX_0FXOP_09_12 */
11510     { Bad_Opcode },
11511     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11512   },
11513
11514 #include "i386-dis-evex-mod.h"
11515 };
11516
11517 static const struct dis386 rm_table[][8] = {
11518   {
11519     /* RM_C6_REG_7 */
11520     { "xabort",         { Skip_MODRM, Ib }, 0 },
11521   },
11522   {
11523     /* RM_C7_REG_7 */
11524     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11525   },
11526   {
11527     /* RM_0F01_REG_0 */
11528     { "enclv",          { Skip_MODRM }, 0 },
11529     { "vmcall",         { Skip_MODRM }, 0 },
11530     { "vmlaunch",       { Skip_MODRM }, 0 },
11531     { "vmresume",       { Skip_MODRM }, 0 },
11532     { "vmxoff",         { Skip_MODRM }, 0 },
11533     { "pconfig",        { Skip_MODRM }, 0 },
11534   },
11535   {
11536     /* RM_0F01_REG_1 */
11537     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11538     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11539     { "clac",           { Skip_MODRM }, 0 },
11540     { "stac",           { Skip_MODRM }, 0 },
11541     { Bad_Opcode },
11542     { Bad_Opcode },
11543     { Bad_Opcode },
11544     { "encls",          { Skip_MODRM }, 0 },
11545   },
11546   {
11547     /* RM_0F01_REG_2 */
11548     { "xgetbv",         { Skip_MODRM }, 0 },
11549     { "xsetbv",         { Skip_MODRM }, 0 },
11550     { Bad_Opcode },
11551     { Bad_Opcode },
11552     { "vmfunc",         { Skip_MODRM }, 0 },
11553     { "xend",           { Skip_MODRM }, 0 },
11554     { "xtest",          { Skip_MODRM }, 0 },
11555     { "enclu",          { Skip_MODRM }, 0 },
11556   },
11557   {
11558     /* RM_0F01_REG_3 */
11559     { "vmrun",          { Skip_MODRM }, 0 },
11560     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11561     { "vmload",         { Skip_MODRM }, 0 },
11562     { "vmsave",         { Skip_MODRM }, 0 },
11563     { "stgi",           { Skip_MODRM }, 0 },
11564     { "clgi",           { Skip_MODRM }, 0 },
11565     { "skinit",         { Skip_MODRM }, 0 },
11566     { "invlpga",        { Skip_MODRM }, 0 },
11567   },
11568   {
11569     /* RM_0F01_REG_5_MOD_3 */
11570     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11571     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11572     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11573     { Bad_Opcode },
11574     { Bad_Opcode },
11575     { Bad_Opcode },
11576     { "rdpkru",         { Skip_MODRM }, 0 },
11577     { "wrpkru",         { Skip_MODRM }, 0 },
11578   },
11579   {
11580     /* RM_0F01_REG_7_MOD_3 */
11581     { "swapgs",         { Skip_MODRM }, 0  },
11582     { "rdtscp",         { Skip_MODRM }, 0  },
11583     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11584     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11585     { "clzero",         { Skip_MODRM }, 0  },
11586     { "rdpru",          { Skip_MODRM }, 0  },
11587   },
11588   {
11589     /* RM_0F1E_P_1_MOD_3_REG_7 */
11590     { "nopQ",           { Ev }, 0 },
11591     { "nopQ",           { Ev }, 0 },
11592     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11593     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11594     { "nopQ",           { Ev }, 0 },
11595     { "nopQ",           { Ev }, 0 },
11596     { "nopQ",           { Ev }, 0 },
11597     { "nopQ",           { Ev }, 0 },
11598   },
11599   {
11600     /* RM_0FAE_REG_6_MOD_3 */
11601     { "mfence",         { Skip_MODRM }, 0 },
11602   },
11603   {
11604     /* RM_0FAE_REG_7_MOD_3 */
11605     { "sfence",         { Skip_MODRM }, 0 },
11606
11607   },
11608   {
11609     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11610     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11611   },
11612 };
11613
11614 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11615
11616 /* We use the high bit to indicate different name for the same
11617    prefix.  */
11618 #define REP_PREFIX      (0xf3 | 0x100)
11619 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11620 #define XRELEASE_PREFIX (0xf3 | 0x400)
11621 #define BND_PREFIX      (0xf2 | 0x400)
11622 #define NOTRACK_PREFIX  (0x3e | 0x100)
11623
11624 /* Remember if the current op is a jump instruction.  */
11625 static bfd_boolean op_is_jump = FALSE;
11626
11627 static int
11628 ckprefix (void)
11629 {
11630   int newrex, i, length;
11631   rex = 0;
11632   prefixes = 0;
11633   used_prefixes = 0;
11634   rex_used = 0;
11635   last_lock_prefix = -1;
11636   last_repz_prefix = -1;
11637   last_repnz_prefix = -1;
11638   last_data_prefix = -1;
11639   last_addr_prefix = -1;
11640   last_rex_prefix = -1;
11641   last_seg_prefix = -1;
11642   fwait_prefix = -1;
11643   active_seg_prefix = 0;
11644   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11645     all_prefixes[i] = 0;
11646   i = 0;
11647   length = 0;
11648   /* The maximum instruction length is 15bytes.  */
11649   while (length < MAX_CODE_LENGTH - 1)
11650     {
11651       FETCH_DATA (the_info, codep + 1);
11652       newrex = 0;
11653       switch (*codep)
11654         {
11655         /* REX prefixes family.  */
11656         case 0x40:
11657         case 0x41:
11658         case 0x42:
11659         case 0x43:
11660         case 0x44:
11661         case 0x45:
11662         case 0x46:
11663         case 0x47:
11664         case 0x48:
11665         case 0x49:
11666         case 0x4a:
11667         case 0x4b:
11668         case 0x4c:
11669         case 0x4d:
11670         case 0x4e:
11671         case 0x4f:
11672           if (address_mode == mode_64bit)
11673             newrex = *codep;
11674           else
11675             return 1;
11676           last_rex_prefix = i;
11677           break;
11678         case 0xf3:
11679           prefixes |= PREFIX_REPZ;
11680           last_repz_prefix = i;
11681           break;
11682         case 0xf2:
11683           prefixes |= PREFIX_REPNZ;
11684           last_repnz_prefix = i;
11685           break;
11686         case 0xf0:
11687           prefixes |= PREFIX_LOCK;
11688           last_lock_prefix = i;
11689           break;
11690         case 0x2e:
11691           prefixes |= PREFIX_CS;
11692           last_seg_prefix = i;
11693           active_seg_prefix = PREFIX_CS;
11694           break;
11695         case 0x36:
11696           prefixes |= PREFIX_SS;
11697           last_seg_prefix = i;
11698           active_seg_prefix = PREFIX_SS;
11699           break;
11700         case 0x3e:
11701           prefixes |= PREFIX_DS;
11702           last_seg_prefix = i;
11703           active_seg_prefix = PREFIX_DS;
11704           break;
11705         case 0x26:
11706           prefixes |= PREFIX_ES;
11707           last_seg_prefix = i;
11708           active_seg_prefix = PREFIX_ES;
11709           break;
11710         case 0x64:
11711           prefixes |= PREFIX_FS;
11712           last_seg_prefix = i;
11713           active_seg_prefix = PREFIX_FS;
11714           break;
11715         case 0x65:
11716           prefixes |= PREFIX_GS;
11717           last_seg_prefix = i;
11718           active_seg_prefix = PREFIX_GS;
11719           break;
11720         case 0x66:
11721           prefixes |= PREFIX_DATA;
11722           last_data_prefix = i;
11723           break;
11724         case 0x67:
11725           prefixes |= PREFIX_ADDR;
11726           last_addr_prefix = i;
11727           break;
11728         case FWAIT_OPCODE:
11729           /* fwait is really an instruction.  If there are prefixes
11730              before the fwait, they belong to the fwait, *not* to the
11731              following instruction.  */
11732           fwait_prefix = i;
11733           if (prefixes || rex)
11734             {
11735               prefixes |= PREFIX_FWAIT;
11736               codep++;
11737               /* This ensures that the previous REX prefixes are noticed
11738                  as unused prefixes, as in the return case below.  */
11739               rex_used = rex;
11740               return 1;
11741             }
11742           prefixes = PREFIX_FWAIT;
11743           break;
11744         default:
11745           return 1;
11746         }
11747       /* Rex is ignored when followed by another prefix.  */
11748       if (rex)
11749         {
11750           rex_used = rex;
11751           return 1;
11752         }
11753       if (*codep != FWAIT_OPCODE)
11754         all_prefixes[i++] = *codep;
11755       rex = newrex;
11756       codep++;
11757       length++;
11758     }
11759   return 0;
11760 }
11761
11762 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11763    prefix byte.  */
11764
11765 static const char *
11766 prefix_name (int pref, int sizeflag)
11767 {
11768   static const char *rexes [16] =
11769     {
11770       "rex",            /* 0x40 */
11771       "rex.B",          /* 0x41 */
11772       "rex.X",          /* 0x42 */
11773       "rex.XB",         /* 0x43 */
11774       "rex.R",          /* 0x44 */
11775       "rex.RB",         /* 0x45 */
11776       "rex.RX",         /* 0x46 */
11777       "rex.RXB",        /* 0x47 */
11778       "rex.W",          /* 0x48 */
11779       "rex.WB",         /* 0x49 */
11780       "rex.WX",         /* 0x4a */
11781       "rex.WXB",        /* 0x4b */
11782       "rex.WR",         /* 0x4c */
11783       "rex.WRB",        /* 0x4d */
11784       "rex.WRX",        /* 0x4e */
11785       "rex.WRXB",       /* 0x4f */
11786     };
11787
11788   switch (pref)
11789     {
11790     /* REX prefixes family.  */
11791     case 0x40:
11792     case 0x41:
11793     case 0x42:
11794     case 0x43:
11795     case 0x44:
11796     case 0x45:
11797     case 0x46:
11798     case 0x47:
11799     case 0x48:
11800     case 0x49:
11801     case 0x4a:
11802     case 0x4b:
11803     case 0x4c:
11804     case 0x4d:
11805     case 0x4e:
11806     case 0x4f:
11807       return rexes [pref - 0x40];
11808     case 0xf3:
11809       return "repz";
11810     case 0xf2:
11811       return "repnz";
11812     case 0xf0:
11813       return "lock";
11814     case 0x2e:
11815       return "cs";
11816     case 0x36:
11817       return "ss";
11818     case 0x3e:
11819       return "ds";
11820     case 0x26:
11821       return "es";
11822     case 0x64:
11823       return "fs";
11824     case 0x65:
11825       return "gs";
11826     case 0x66:
11827       return (sizeflag & DFLAG) ? "data16" : "data32";
11828     case 0x67:
11829       if (address_mode == mode_64bit)
11830         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11831       else
11832         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11833     case FWAIT_OPCODE:
11834       return "fwait";
11835     case REP_PREFIX:
11836       return "rep";
11837     case XACQUIRE_PREFIX:
11838       return "xacquire";
11839     case XRELEASE_PREFIX:
11840       return "xrelease";
11841     case BND_PREFIX:
11842       return "bnd";
11843     case NOTRACK_PREFIX:
11844       return "notrack";
11845     default:
11846       return NULL;
11847     }
11848 }
11849
11850 static char op_out[MAX_OPERANDS][100];
11851 static int op_ad, op_index[MAX_OPERANDS];
11852 static int two_source_ops;
11853 static bfd_vma op_address[MAX_OPERANDS];
11854 static bfd_vma op_riprel[MAX_OPERANDS];
11855 static bfd_vma start_pc;
11856
11857 /*
11858  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11859  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11860  *   section of the "Virtual 8086 Mode" chapter.)
11861  * 'pc' should be the address of this instruction, it will
11862  *   be used to print the target address if this is a relative jump or call
11863  * The function returns the length of this instruction in bytes.
11864  */
11865
11866 static char intel_syntax;
11867 static char intel_mnemonic = !SYSV386_COMPAT;
11868 static char open_char;
11869 static char close_char;
11870 static char separator_char;
11871 static char scale_char;
11872
11873 enum x86_64_isa
11874 {
11875   amd64 = 1,
11876   intel64
11877 };
11878
11879 static enum x86_64_isa isa64;
11880
11881 /* Here for backwards compatibility.  When gdb stops using
11882    print_insn_i386_att and print_insn_i386_intel these functions can
11883    disappear, and print_insn_i386 be merged into print_insn.  */
11884 int
11885 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11886 {
11887   intel_syntax = 0;
11888
11889   return print_insn (pc, info);
11890 }
11891
11892 int
11893 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11894 {
11895   intel_syntax = 1;
11896
11897   return print_insn (pc, info);
11898 }
11899
11900 int
11901 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11902 {
11903   intel_syntax = -1;
11904
11905   return print_insn (pc, info);
11906 }
11907
11908 void
11909 print_i386_disassembler_options (FILE *stream)
11910 {
11911   fprintf (stream, _("\n\
11912 The following i386/x86-64 specific disassembler options are supported for use\n\
11913 with the -M switch (multiple options should be separated by commas):\n"));
11914
11915   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11916   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11917   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11918   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11919   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11920   fprintf (stream, _("  att-mnemonic\n"
11921                      "              Display instruction in AT&T mnemonic\n"));
11922   fprintf (stream, _("  intel-mnemonic\n"
11923                      "              Display instruction in Intel mnemonic\n"));
11924   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11925   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11926   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11927   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11928   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11929   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11930   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11931   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11932 }
11933
11934 /* Bad opcode.  */
11935 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11936
11937 /* Get a pointer to struct dis386 with a valid name.  */
11938
11939 static const struct dis386 *
11940 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11941 {
11942   int vindex, vex_table_index;
11943
11944   if (dp->name != NULL)
11945     return dp;
11946
11947   switch (dp->op[0].bytemode)
11948     {
11949     case USE_REG_TABLE:
11950       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11951       break;
11952
11953     case USE_MOD_TABLE:
11954       vindex = modrm.mod == 0x3 ? 1 : 0;
11955       dp = &mod_table[dp->op[1].bytemode][vindex];
11956       break;
11957
11958     case USE_RM_TABLE:
11959       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11960       break;
11961
11962     case USE_PREFIX_TABLE:
11963       if (need_vex)
11964         {
11965           /* The prefix in VEX is implicit.  */
11966           switch (vex.prefix)
11967             {
11968             case 0:
11969               vindex = 0;
11970               break;
11971             case REPE_PREFIX_OPCODE:
11972               vindex = 1;
11973               break;
11974             case DATA_PREFIX_OPCODE:
11975               vindex = 2;
11976               break;
11977             case REPNE_PREFIX_OPCODE:
11978               vindex = 3;
11979               break;
11980             default:
11981               abort ();
11982               break;
11983             }
11984         }
11985       else
11986         {
11987           int last_prefix = -1;
11988           int prefix = 0;
11989           vindex = 0;
11990           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11991              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11992              last one wins.  */
11993           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11994             {
11995               if (last_repz_prefix > last_repnz_prefix)
11996                 {
11997                   vindex = 1;
11998                   prefix = PREFIX_REPZ;
11999                   last_prefix = last_repz_prefix;
12000                 }
12001               else
12002                 {
12003                   vindex = 3;
12004                   prefix = PREFIX_REPNZ;
12005                   last_prefix = last_repnz_prefix;
12006                 }
12007
12008               /* Check if prefix should be ignored.  */
12009               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12010                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12011                    & prefix) != 0)
12012                 vindex = 0;
12013             }
12014
12015           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12016             {
12017               vindex = 2;
12018               prefix = PREFIX_DATA;
12019               last_prefix = last_data_prefix;
12020             }
12021
12022           if (vindex != 0)
12023             {
12024               used_prefixes |= prefix;
12025               all_prefixes[last_prefix] = 0;
12026             }
12027         }
12028       dp = &prefix_table[dp->op[1].bytemode][vindex];
12029       break;
12030
12031     case USE_X86_64_TABLE:
12032       vindex = address_mode == mode_64bit ? 1 : 0;
12033       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12034       break;
12035
12036     case USE_3BYTE_TABLE:
12037       FETCH_DATA (info, codep + 2);
12038       vindex = *codep++;
12039       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12040       end_codep = codep;
12041       modrm.mod = (*codep >> 6) & 3;
12042       modrm.reg = (*codep >> 3) & 7;
12043       modrm.rm = *codep & 7;
12044       break;
12045
12046     case USE_VEX_LEN_TABLE:
12047       if (!need_vex)
12048         abort ();
12049
12050       switch (vex.length)
12051         {
12052         case 128:
12053           vindex = 0;
12054           break;
12055         case 256:
12056           vindex = 1;
12057           break;
12058         default:
12059           abort ();
12060           break;
12061         }
12062
12063       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12064       break;
12065
12066     case USE_EVEX_LEN_TABLE:
12067       if (!vex.evex)
12068         abort ();
12069
12070       switch (vex.length)
12071         {
12072         case 128:
12073           vindex = 0;
12074           break;
12075         case 256:
12076           vindex = 1;
12077           break;
12078         case 512:
12079           vindex = 2;
12080           break;
12081         default:
12082           abort ();
12083           break;
12084         }
12085
12086       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12087       break;
12088
12089     case USE_XOP_8F_TABLE:
12090       FETCH_DATA (info, codep + 3);
12091       rex = ~(*codep >> 5) & 0x7;
12092
12093       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12094       switch ((*codep & 0x1f))
12095         {
12096         default:
12097           dp = &bad_opcode;
12098           return dp;
12099         case 0x8:
12100           vex_table_index = XOP_08;
12101           break;
12102         case 0x9:
12103           vex_table_index = XOP_09;
12104           break;
12105         case 0xa:
12106           vex_table_index = XOP_0A;
12107           break;
12108         }
12109       codep++;
12110       vex.w = *codep & 0x80;
12111       if (vex.w && address_mode == mode_64bit)
12112         rex |= REX_W;
12113
12114       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12115       if (address_mode != mode_64bit)
12116         {
12117           /* In 16/32-bit mode REX_B is silently ignored.  */
12118           rex &= ~REX_B;
12119         }
12120
12121       vex.length = (*codep & 0x4) ? 256 : 128;
12122       switch ((*codep & 0x3))
12123         {
12124         case 0:
12125           break;
12126         case 1:
12127           vex.prefix = DATA_PREFIX_OPCODE;
12128           break;
12129         case 2:
12130           vex.prefix = REPE_PREFIX_OPCODE;
12131           break;
12132         case 3:
12133           vex.prefix = REPNE_PREFIX_OPCODE;
12134           break;
12135         }
12136       need_vex = 1;
12137       codep++;
12138       vindex = *codep++;
12139       dp = &xop_table[vex_table_index][vindex];
12140
12141       end_codep = codep;
12142       FETCH_DATA (info, codep + 1);
12143       modrm.mod = (*codep >> 6) & 3;
12144       modrm.reg = (*codep >> 3) & 7;
12145       modrm.rm = *codep & 7;
12146
12147       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12148          having to decode the bits for every otherwise valid encoding.  */
12149       if (vex.prefix)
12150         return &bad_opcode;
12151       break;
12152
12153     case USE_VEX_C4_TABLE:
12154       /* VEX prefix.  */
12155       FETCH_DATA (info, codep + 3);
12156       rex = ~(*codep >> 5) & 0x7;
12157       switch ((*codep & 0x1f))
12158         {
12159         default:
12160           dp = &bad_opcode;
12161           return dp;
12162         case 0x1:
12163           vex_table_index = VEX_0F;
12164           break;
12165         case 0x2:
12166           vex_table_index = VEX_0F38;
12167           break;
12168         case 0x3:
12169           vex_table_index = VEX_0F3A;
12170           break;
12171         }
12172       codep++;
12173       vex.w = *codep & 0x80;
12174       if (address_mode == mode_64bit)
12175         {
12176           if (vex.w)
12177             rex |= REX_W;
12178         }
12179       else
12180         {
12181           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12182              is ignored, other REX bits are 0 and the highest bit in
12183              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12184           rex = 0;
12185         }
12186       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12187       vex.length = (*codep & 0x4) ? 256 : 128;
12188       switch ((*codep & 0x3))
12189         {
12190         case 0:
12191           break;
12192         case 1:
12193           vex.prefix = DATA_PREFIX_OPCODE;
12194           break;
12195         case 2:
12196           vex.prefix = REPE_PREFIX_OPCODE;
12197           break;
12198         case 3:
12199           vex.prefix = REPNE_PREFIX_OPCODE;
12200           break;
12201         }
12202       need_vex = 1;
12203       codep++;
12204       vindex = *codep++;
12205       dp = &vex_table[vex_table_index][vindex];
12206       end_codep = codep;
12207       /* There is no MODRM byte for VEX0F 77.  */
12208       if (vex_table_index != VEX_0F || vindex != 0x77)
12209         {
12210           FETCH_DATA (info, codep + 1);
12211           modrm.mod = (*codep >> 6) & 3;
12212           modrm.reg = (*codep >> 3) & 7;
12213           modrm.rm = *codep & 7;
12214         }
12215       break;
12216
12217     case USE_VEX_C5_TABLE:
12218       /* VEX prefix.  */
12219       FETCH_DATA (info, codep + 2);
12220       rex = (*codep & 0x80) ? 0 : REX_R;
12221
12222       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12223          VEX.vvvv is 1.  */
12224       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12225       vex.length = (*codep & 0x4) ? 256 : 128;
12226       switch ((*codep & 0x3))
12227         {
12228         case 0:
12229           break;
12230         case 1:
12231           vex.prefix = DATA_PREFIX_OPCODE;
12232           break;
12233         case 2:
12234           vex.prefix = REPE_PREFIX_OPCODE;
12235           break;
12236         case 3:
12237           vex.prefix = REPNE_PREFIX_OPCODE;
12238           break;
12239         }
12240       need_vex = 1;
12241       codep++;
12242       vindex = *codep++;
12243       dp = &vex_table[dp->op[1].bytemode][vindex];
12244       end_codep = codep;
12245       /* There is no MODRM byte for VEX 77.  */
12246       if (vindex != 0x77)
12247         {
12248           FETCH_DATA (info, codep + 1);
12249           modrm.mod = (*codep >> 6) & 3;
12250           modrm.reg = (*codep >> 3) & 7;
12251           modrm.rm = *codep & 7;
12252         }
12253       break;
12254
12255     case USE_VEX_W_TABLE:
12256       if (!need_vex)
12257         abort ();
12258
12259       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12260       break;
12261
12262     case USE_EVEX_TABLE:
12263       two_source_ops = 0;
12264       /* EVEX prefix.  */
12265       vex.evex = 1;
12266       FETCH_DATA (info, codep + 4);
12267       /* The first byte after 0x62.  */
12268       rex = ~(*codep >> 5) & 0x7;
12269       vex.r = *codep & 0x10;
12270       switch ((*codep & 0xf))
12271         {
12272         default:
12273           return &bad_opcode;
12274         case 0x1:
12275           vex_table_index = EVEX_0F;
12276           break;
12277         case 0x2:
12278           vex_table_index = EVEX_0F38;
12279           break;
12280         case 0x3:
12281           vex_table_index = EVEX_0F3A;
12282           break;
12283         }
12284
12285       /* The second byte after 0x62.  */
12286       codep++;
12287       vex.w = *codep & 0x80;
12288       if (vex.w && address_mode == mode_64bit)
12289         rex |= REX_W;
12290
12291       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12292
12293       /* The U bit.  */
12294       if (!(*codep & 0x4))
12295         return &bad_opcode;
12296
12297       switch ((*codep & 0x3))
12298         {
12299         case 0:
12300           break;
12301         case 1:
12302           vex.prefix = DATA_PREFIX_OPCODE;
12303           break;
12304         case 2:
12305           vex.prefix = REPE_PREFIX_OPCODE;
12306           break;
12307         case 3:
12308           vex.prefix = REPNE_PREFIX_OPCODE;
12309           break;
12310         }
12311
12312       /* The third byte after 0x62.  */
12313       codep++;
12314
12315       /* Remember the static rounding bits.  */
12316       vex.ll = (*codep >> 5) & 3;
12317       vex.b = (*codep & 0x10) != 0;
12318
12319       vex.v = *codep & 0x8;
12320       vex.mask_register_specifier = *codep & 0x7;
12321       vex.zeroing = *codep & 0x80;
12322
12323       if (address_mode != mode_64bit)
12324         {
12325           /* In 16/32-bit mode silently ignore following bits.  */
12326           rex &= ~REX_B;
12327           vex.r = 1;
12328           vex.v = 1;
12329         }
12330
12331       need_vex = 1;
12332       codep++;
12333       vindex = *codep++;
12334       dp = &evex_table[vex_table_index][vindex];
12335       end_codep = codep;
12336       FETCH_DATA (info, codep + 1);
12337       modrm.mod = (*codep >> 6) & 3;
12338       modrm.reg = (*codep >> 3) & 7;
12339       modrm.rm = *codep & 7;
12340
12341       /* Set vector length.  */
12342       if (modrm.mod == 3 && vex.b)
12343         vex.length = 512;
12344       else
12345         {
12346           switch (vex.ll)
12347             {
12348             case 0x0:
12349               vex.length = 128;
12350               break;
12351             case 0x1:
12352               vex.length = 256;
12353               break;
12354             case 0x2:
12355               vex.length = 512;
12356               break;
12357             default:
12358               return &bad_opcode;
12359             }
12360         }
12361       break;
12362
12363     case 0:
12364       dp = &bad_opcode;
12365       break;
12366
12367     default:
12368       abort ();
12369     }
12370
12371   if (dp->name != NULL)
12372     return dp;
12373   else
12374     return get_valid_dis386 (dp, info);
12375 }
12376
12377 static void
12378 get_sib (disassemble_info *info, int sizeflag)
12379 {
12380   /* If modrm.mod == 3, operand must be register.  */
12381   if (need_modrm
12382       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12383       && modrm.mod != 3
12384       && modrm.rm == 4)
12385     {
12386       FETCH_DATA (info, codep + 2);
12387       sib.index = (codep [1] >> 3) & 7;
12388       sib.scale = (codep [1] >> 6) & 3;
12389       sib.base = codep [1] & 7;
12390     }
12391 }
12392
12393 static int
12394 print_insn (bfd_vma pc, disassemble_info *info)
12395 {
12396   const struct dis386 *dp;
12397   int i;
12398   char *op_txt[MAX_OPERANDS];
12399   int needcomma;
12400   int sizeflag, orig_sizeflag;
12401   const char *p;
12402   struct dis_private priv;
12403   int prefix_length;
12404
12405   priv.orig_sizeflag = AFLAG | DFLAG;
12406   if ((info->mach & bfd_mach_i386_i386) != 0)
12407     address_mode = mode_32bit;
12408   else if (info->mach == bfd_mach_i386_i8086)
12409     {
12410       address_mode = mode_16bit;
12411       priv.orig_sizeflag = 0;
12412     }
12413   else
12414     address_mode = mode_64bit;
12415
12416   if (intel_syntax == (char) -1)
12417     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12418
12419   for (p = info->disassembler_options; p != NULL; )
12420     {
12421       if (CONST_STRNEQ (p, "amd64"))
12422         isa64 = amd64;
12423       else if (CONST_STRNEQ (p, "intel64"))
12424         isa64 = intel64;
12425       else if (CONST_STRNEQ (p, "x86-64"))
12426         {
12427           address_mode = mode_64bit;
12428           priv.orig_sizeflag |= AFLAG | DFLAG;
12429         }
12430       else if (CONST_STRNEQ (p, "i386"))
12431         {
12432           address_mode = mode_32bit;
12433           priv.orig_sizeflag |= AFLAG | DFLAG;
12434         }
12435       else if (CONST_STRNEQ (p, "i8086"))
12436         {
12437           address_mode = mode_16bit;
12438           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12439         }
12440       else if (CONST_STRNEQ (p, "intel"))
12441         {
12442           intel_syntax = 1;
12443           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12444             intel_mnemonic = 1;
12445         }
12446       else if (CONST_STRNEQ (p, "att"))
12447         {
12448           intel_syntax = 0;
12449           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12450             intel_mnemonic = 0;
12451         }
12452       else if (CONST_STRNEQ (p, "addr"))
12453         {
12454           if (address_mode == mode_64bit)
12455             {
12456               if (p[4] == '3' && p[5] == '2')
12457                 priv.orig_sizeflag &= ~AFLAG;
12458               else if (p[4] == '6' && p[5] == '4')
12459                 priv.orig_sizeflag |= AFLAG;
12460             }
12461           else
12462             {
12463               if (p[4] == '1' && p[5] == '6')
12464                 priv.orig_sizeflag &= ~AFLAG;
12465               else if (p[4] == '3' && p[5] == '2')
12466                 priv.orig_sizeflag |= AFLAG;
12467             }
12468         }
12469       else if (CONST_STRNEQ (p, "data"))
12470         {
12471           if (p[4] == '1' && p[5] == '6')
12472             priv.orig_sizeflag &= ~DFLAG;
12473           else if (p[4] == '3' && p[5] == '2')
12474             priv.orig_sizeflag |= DFLAG;
12475         }
12476       else if (CONST_STRNEQ (p, "suffix"))
12477         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12478
12479       p = strchr (p, ',');
12480       if (p != NULL)
12481         p++;
12482     }
12483
12484   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12485     {
12486       (*info->fprintf_func) (info->stream,
12487                              _("64-bit address is disabled"));
12488       return -1;
12489     }
12490
12491   if (intel_syntax)
12492     {
12493       names64 = intel_names64;
12494       names32 = intel_names32;
12495       names16 = intel_names16;
12496       names8 = intel_names8;
12497       names8rex = intel_names8rex;
12498       names_seg = intel_names_seg;
12499       names_mm = intel_names_mm;
12500       names_bnd = intel_names_bnd;
12501       names_xmm = intel_names_xmm;
12502       names_ymm = intel_names_ymm;
12503       names_zmm = intel_names_zmm;
12504       names_tmm = intel_names_tmm;
12505       index64 = intel_index64;
12506       index32 = intel_index32;
12507       names_mask = intel_names_mask;
12508       index16 = intel_index16;
12509       open_char = '[';
12510       close_char = ']';
12511       separator_char = '+';
12512       scale_char = '*';
12513     }
12514   else
12515     {
12516       names64 = att_names64;
12517       names32 = att_names32;
12518       names16 = att_names16;
12519       names8 = att_names8;
12520       names8rex = att_names8rex;
12521       names_seg = att_names_seg;
12522       names_mm = att_names_mm;
12523       names_bnd = att_names_bnd;
12524       names_xmm = att_names_xmm;
12525       names_ymm = att_names_ymm;
12526       names_zmm = att_names_zmm;
12527       names_tmm = att_names_tmm;
12528       index64 = att_index64;
12529       index32 = att_index32;
12530       names_mask = att_names_mask;
12531       index16 = att_index16;
12532       open_char = '(';
12533       close_char =  ')';
12534       separator_char = ',';
12535       scale_char = ',';
12536     }
12537
12538   /* The output looks better if we put 7 bytes on a line, since that
12539      puts most long word instructions on a single line.  Use 8 bytes
12540      for Intel L1OM.  */
12541   if ((info->mach & bfd_mach_l1om) != 0)
12542     info->bytes_per_line = 8;
12543   else
12544     info->bytes_per_line = 7;
12545
12546   info->private_data = &priv;
12547   priv.max_fetched = priv.the_buffer;
12548   priv.insn_start = pc;
12549
12550   obuf[0] = 0;
12551   for (i = 0; i < MAX_OPERANDS; ++i)
12552     {
12553       op_out[i][0] = 0;
12554       op_index[i] = -1;
12555     }
12556
12557   the_info = info;
12558   start_pc = pc;
12559   start_codep = priv.the_buffer;
12560   codep = priv.the_buffer;
12561
12562   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12563     {
12564       const char *name;
12565
12566       /* Getting here means we tried for data but didn't get it.  That
12567          means we have an incomplete instruction of some sort.  Just
12568          print the first byte as a prefix or a .byte pseudo-op.  */
12569       if (codep > priv.the_buffer)
12570         {
12571           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12572           if (name != NULL)
12573             (*info->fprintf_func) (info->stream, "%s", name);
12574           else
12575             {
12576               /* Just print the first byte as a .byte instruction.  */
12577               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12578                                      (unsigned int) priv.the_buffer[0]);
12579             }
12580
12581           return 1;
12582         }
12583
12584       return -1;
12585     }
12586
12587   obufp = obuf;
12588   sizeflag = priv.orig_sizeflag;
12589
12590   if (!ckprefix () || rex_used)
12591     {
12592       /* Too many prefixes or unused REX prefixes.  */
12593       for (i = 0;
12594            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12595            i++)
12596         (*info->fprintf_func) (info->stream, "%s%s",
12597                                i == 0 ? "" : " ",
12598                                prefix_name (all_prefixes[i], sizeflag));
12599       return i;
12600     }
12601
12602   insn_codep = codep;
12603
12604   FETCH_DATA (info, codep + 1);
12605   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12606
12607   if (((prefixes & PREFIX_FWAIT)
12608        && ((*codep < 0xd8) || (*codep > 0xdf))))
12609     {
12610       /* Handle prefixes before fwait.  */
12611       for (i = 0; i < fwait_prefix && all_prefixes[i];
12612            i++)
12613         (*info->fprintf_func) (info->stream, "%s ",
12614                                prefix_name (all_prefixes[i], sizeflag));
12615       (*info->fprintf_func) (info->stream, "fwait");
12616       return i + 1;
12617     }
12618
12619   if (*codep == 0x0f)
12620     {
12621       unsigned char threebyte;
12622
12623       codep++;
12624       FETCH_DATA (info, codep + 1);
12625       threebyte = *codep;
12626       dp = &dis386_twobyte[threebyte];
12627       need_modrm = twobyte_has_modrm[*codep];
12628       codep++;
12629     }
12630   else
12631     {
12632       dp = &dis386[*codep];
12633       need_modrm = onebyte_has_modrm[*codep];
12634       codep++;
12635     }
12636
12637   /* Save sizeflag for printing the extra prefixes later before updating
12638      it for mnemonic and operand processing.  The prefix names depend
12639      only on the address mode.  */
12640   orig_sizeflag = sizeflag;
12641   if (prefixes & PREFIX_ADDR)
12642     sizeflag ^= AFLAG;
12643   if ((prefixes & PREFIX_DATA))
12644     sizeflag ^= DFLAG;
12645
12646   end_codep = codep;
12647   if (need_modrm)
12648     {
12649       FETCH_DATA (info, codep + 1);
12650       modrm.mod = (*codep >> 6) & 3;
12651       modrm.reg = (*codep >> 3) & 7;
12652       modrm.rm = *codep & 7;
12653     }
12654
12655   need_vex = 0;
12656   memset (&vex, 0, sizeof (vex));
12657
12658   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12659     {
12660       get_sib (info, sizeflag);
12661       dofloat (sizeflag);
12662     }
12663   else
12664     {
12665       dp = get_valid_dis386 (dp, info);
12666       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12667         {
12668           get_sib (info, sizeflag);
12669           for (i = 0; i < MAX_OPERANDS; ++i)
12670             {
12671               obufp = op_out[i];
12672               op_ad = MAX_OPERANDS - 1 - i;
12673               if (dp->op[i].rtn)
12674                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12675               /* For EVEX instruction after the last operand masking
12676                  should be printed.  */
12677               if (i == 0 && vex.evex)
12678                 {
12679                   /* Don't print {%k0}.  */
12680                   if (vex.mask_register_specifier)
12681                     {
12682                       oappend ("{");
12683                       oappend (names_mask[vex.mask_register_specifier]);
12684                       oappend ("}");
12685                     }
12686                   if (vex.zeroing)
12687                     oappend ("{z}");
12688                 }
12689             }
12690         }
12691     }
12692
12693   /* Clear instruction information.  */
12694   if (the_info)
12695     {
12696       the_info->insn_info_valid = 0;
12697       the_info->branch_delay_insns = 0;
12698       the_info->data_size = 0;
12699       the_info->insn_type = dis_noninsn;
12700       the_info->target = 0;
12701       the_info->target2 = 0;
12702     }
12703
12704   /* Reset jump operation indicator.  */
12705   op_is_jump = FALSE;
12706
12707   {
12708     int jump_detection = 0;
12709
12710     /* Extract flags.  */
12711     for (i = 0; i < MAX_OPERANDS; ++i)
12712       {
12713         if ((dp->op[i].rtn == OP_J)
12714             || (dp->op[i].rtn == OP_indirE))
12715           jump_detection |= 1;
12716         else if ((dp->op[i].rtn == BND_Fixup)
12717                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12718           jump_detection |= 2;
12719         else if ((dp->op[i].bytemode == cond_jump_mode)
12720                  || (dp->op[i].bytemode == loop_jcxz_mode))
12721           jump_detection |= 4;
12722       }
12723
12724     /* Determine if this is a jump or branch.  */
12725     if ((jump_detection & 0x3) == 0x3)
12726       {
12727         op_is_jump = TRUE;
12728         if (jump_detection & 0x4)
12729           the_info->insn_type = dis_condbranch;
12730         else
12731           the_info->insn_type =
12732             (dp->name && !strncmp(dp->name, "call", 4))
12733             ? dis_jsr : dis_branch;
12734       }
12735   }
12736
12737   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12738      are all 0s in inverted form.  */
12739   if (need_vex && vex.register_specifier != 0)
12740     {
12741       (*info->fprintf_func) (info->stream, "(bad)");
12742       return end_codep - priv.the_buffer;
12743     }
12744
12745   /* Check if the REX prefix is used.  */
12746   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12747     all_prefixes[last_rex_prefix] = 0;
12748
12749   /* Check if the SEG prefix is used.  */
12750   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12751                    | PREFIX_FS | PREFIX_GS)) != 0
12752       && (used_prefixes & active_seg_prefix) != 0)
12753     all_prefixes[last_seg_prefix] = 0;
12754
12755   /* Check if the ADDR prefix is used.  */
12756   if ((prefixes & PREFIX_ADDR) != 0
12757       && (used_prefixes & PREFIX_ADDR) != 0)
12758     all_prefixes[last_addr_prefix] = 0;
12759
12760   /* Check if the DATA prefix is used.  */
12761   if ((prefixes & PREFIX_DATA) != 0
12762       && (used_prefixes & PREFIX_DATA) != 0
12763       && !need_vex)
12764     all_prefixes[last_data_prefix] = 0;
12765
12766   /* Print the extra prefixes.  */
12767   prefix_length = 0;
12768   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12769     if (all_prefixes[i])
12770       {
12771         const char *name;
12772         name = prefix_name (all_prefixes[i], orig_sizeflag);
12773         if (name == NULL)
12774           abort ();
12775         prefix_length += strlen (name) + 1;
12776         (*info->fprintf_func) (info->stream, "%s ", name);
12777       }
12778
12779   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12780      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12781      used by putop and MMX/SSE operand and may be overriden by the
12782      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12783      separately.  */
12784   if (dp->prefix_requirement == PREFIX_OPCODE
12785       && (((need_vex
12786             ? vex.prefix == REPE_PREFIX_OPCODE
12787               || vex.prefix == REPNE_PREFIX_OPCODE
12788             : (prefixes
12789                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12790            && (used_prefixes
12791                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12792           || (((need_vex
12793                 ? vex.prefix == DATA_PREFIX_OPCODE
12794                 : ((prefixes
12795                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12796                    == PREFIX_DATA))
12797                && (used_prefixes & PREFIX_DATA) == 0))
12798           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12799     {
12800       (*info->fprintf_func) (info->stream, "(bad)");
12801       return end_codep - priv.the_buffer;
12802     }
12803
12804   /* Check maximum code length.  */
12805   if ((codep - start_codep) > MAX_CODE_LENGTH)
12806     {
12807       (*info->fprintf_func) (info->stream, "(bad)");
12808       return MAX_CODE_LENGTH;
12809     }
12810
12811   obufp = mnemonicendp;
12812   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12813     oappend (" ");
12814   oappend (" ");
12815   (*info->fprintf_func) (info->stream, "%s", obuf);
12816
12817   /* The enter and bound instructions are printed with operands in the same
12818      order as the intel book; everything else is printed in reverse order.  */
12819   if (intel_syntax || two_source_ops)
12820     {
12821       bfd_vma riprel;
12822
12823       for (i = 0; i < MAX_OPERANDS; ++i)
12824         op_txt[i] = op_out[i];
12825
12826       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12827           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12828         {
12829           op_txt[2] = op_out[3];
12830           op_txt[3] = op_out[2];
12831         }
12832
12833       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12834         {
12835           op_ad = op_index[i];
12836           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12837           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12838           riprel = op_riprel[i];
12839           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12840           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12841         }
12842     }
12843   else
12844     {
12845       for (i = 0; i < MAX_OPERANDS; ++i)
12846         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12847     }
12848
12849   needcomma = 0;
12850   for (i = 0; i < MAX_OPERANDS; ++i)
12851     if (*op_txt[i])
12852       {
12853         if (needcomma)
12854           (*info->fprintf_func) (info->stream, ",");
12855         if (op_index[i] != -1 && !op_riprel[i])
12856           {
12857             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12858
12859             if (the_info && op_is_jump)
12860               {
12861                 the_info->insn_info_valid = 1;
12862                 the_info->branch_delay_insns = 0;
12863                 the_info->data_size = 0;
12864                 the_info->target = target;
12865                 the_info->target2 = 0;
12866               }
12867             (*info->print_address_func) (target, info);
12868           }
12869         else
12870           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12871         needcomma = 1;
12872       }
12873
12874   for (i = 0; i < MAX_OPERANDS; i++)
12875     if (op_index[i] != -1 && op_riprel[i])
12876       {
12877         (*info->fprintf_func) (info->stream, "        # ");
12878         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12879                                                 + op_address[op_index[i]]), info);
12880         break;
12881       }
12882   return codep - priv.the_buffer;
12883 }
12884
12885 static const char *float_mem[] = {
12886   /* d8 */
12887   "fadd{s|}",
12888   "fmul{s|}",
12889   "fcom{s|}",
12890   "fcomp{s|}",
12891   "fsub{s|}",
12892   "fsubr{s|}",
12893   "fdiv{s|}",
12894   "fdivr{s|}",
12895   /* d9 */
12896   "fld{s|}",
12897   "(bad)",
12898   "fst{s|}",
12899   "fstp{s|}",
12900   "fldenv{C|C}",
12901   "fldcw",
12902   "fNstenv{C|C}",
12903   "fNstcw",
12904   /* da */
12905   "fiadd{l|}",
12906   "fimul{l|}",
12907   "ficom{l|}",
12908   "ficomp{l|}",
12909   "fisub{l|}",
12910   "fisubr{l|}",
12911   "fidiv{l|}",
12912   "fidivr{l|}",
12913   /* db */
12914   "fild{l|}",
12915   "fisttp{l|}",
12916   "fist{l|}",
12917   "fistp{l|}",
12918   "(bad)",
12919   "fld{t|}",
12920   "(bad)",
12921   "fstp{t|}",
12922   /* dc */
12923   "fadd{l|}",
12924   "fmul{l|}",
12925   "fcom{l|}",
12926   "fcomp{l|}",
12927   "fsub{l|}",
12928   "fsubr{l|}",
12929   "fdiv{l|}",
12930   "fdivr{l|}",
12931   /* dd */
12932   "fld{l|}",
12933   "fisttp{ll|}",
12934   "fst{l||}",
12935   "fstp{l|}",
12936   "frstor{C|C}",
12937   "(bad)",
12938   "fNsave{C|C}",
12939   "fNstsw",
12940   /* de */
12941   "fiadd{s|}",
12942   "fimul{s|}",
12943   "ficom{s|}",
12944   "ficomp{s|}",
12945   "fisub{s|}",
12946   "fisubr{s|}",
12947   "fidiv{s|}",
12948   "fidivr{s|}",
12949   /* df */
12950   "fild{s|}",
12951   "fisttp{s|}",
12952   "fist{s|}",
12953   "fistp{s|}",
12954   "fbld",
12955   "fild{ll|}",
12956   "fbstp",
12957   "fistp{ll|}",
12958 };
12959
12960 static const unsigned char float_mem_mode[] = {
12961   /* d8 */
12962   d_mode,
12963   d_mode,
12964   d_mode,
12965   d_mode,
12966   d_mode,
12967   d_mode,
12968   d_mode,
12969   d_mode,
12970   /* d9 */
12971   d_mode,
12972   0,
12973   d_mode,
12974   d_mode,
12975   0,
12976   w_mode,
12977   0,
12978   w_mode,
12979   /* da */
12980   d_mode,
12981   d_mode,
12982   d_mode,
12983   d_mode,
12984   d_mode,
12985   d_mode,
12986   d_mode,
12987   d_mode,
12988   /* db */
12989   d_mode,
12990   d_mode,
12991   d_mode,
12992   d_mode,
12993   0,
12994   t_mode,
12995   0,
12996   t_mode,
12997   /* dc */
12998   q_mode,
12999   q_mode,
13000   q_mode,
13001   q_mode,
13002   q_mode,
13003   q_mode,
13004   q_mode,
13005   q_mode,
13006   /* dd */
13007   q_mode,
13008   q_mode,
13009   q_mode,
13010   q_mode,
13011   0,
13012   0,
13013   0,
13014   w_mode,
13015   /* de */
13016   w_mode,
13017   w_mode,
13018   w_mode,
13019   w_mode,
13020   w_mode,
13021   w_mode,
13022   w_mode,
13023   w_mode,
13024   /* df */
13025   w_mode,
13026   w_mode,
13027   w_mode,
13028   w_mode,
13029   t_mode,
13030   q_mode,
13031   t_mode,
13032   q_mode
13033 };
13034
13035 #define ST { OP_ST, 0 }
13036 #define STi { OP_STi, 0 }
13037
13038 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13039 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13040 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13041 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13042 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13043 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13044 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13045 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13046 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13047
13048 static const struct dis386 float_reg[][8] = {
13049   /* d8 */
13050   {
13051     { "fadd",   { ST, STi }, 0 },
13052     { "fmul",   { ST, STi }, 0 },
13053     { "fcom",   { STi }, 0 },
13054     { "fcomp",  { STi }, 0 },
13055     { "fsub",   { ST, STi }, 0 },
13056     { "fsubr",  { ST, STi }, 0 },
13057     { "fdiv",   { ST, STi }, 0 },
13058     { "fdivr",  { ST, STi }, 0 },
13059   },
13060   /* d9 */
13061   {
13062     { "fld",    { STi }, 0 },
13063     { "fxch",   { STi }, 0 },
13064     { FGRPd9_2 },
13065     { Bad_Opcode },
13066     { FGRPd9_4 },
13067     { FGRPd9_5 },
13068     { FGRPd9_6 },
13069     { FGRPd9_7 },
13070   },
13071   /* da */
13072   {
13073     { "fcmovb", { ST, STi }, 0 },
13074     { "fcmove", { ST, STi }, 0 },
13075     { "fcmovbe",{ ST, STi }, 0 },
13076     { "fcmovu", { ST, STi }, 0 },
13077     { Bad_Opcode },
13078     { FGRPda_5 },
13079     { Bad_Opcode },
13080     { Bad_Opcode },
13081   },
13082   /* db */
13083   {
13084     { "fcmovnb",{ ST, STi }, 0 },
13085     { "fcmovne",{ ST, STi }, 0 },
13086     { "fcmovnbe",{ ST, STi }, 0 },
13087     { "fcmovnu",{ ST, STi }, 0 },
13088     { FGRPdb_4 },
13089     { "fucomi", { ST, STi }, 0 },
13090     { "fcomi",  { ST, STi }, 0 },
13091     { Bad_Opcode },
13092   },
13093   /* dc */
13094   {
13095     { "fadd",   { STi, ST }, 0 },
13096     { "fmul",   { STi, ST }, 0 },
13097     { Bad_Opcode },
13098     { Bad_Opcode },
13099     { "fsub{!M|r}",     { STi, ST }, 0 },
13100     { "fsub{M|}",       { STi, ST }, 0 },
13101     { "fdiv{!M|r}",     { STi, ST }, 0 },
13102     { "fdiv{M|}",       { STi, ST }, 0 },
13103   },
13104   /* dd */
13105   {
13106     { "ffree",  { STi }, 0 },
13107     { Bad_Opcode },
13108     { "fst",    { STi }, 0 },
13109     { "fstp",   { STi }, 0 },
13110     { "fucom",  { STi }, 0 },
13111     { "fucomp", { STi }, 0 },
13112     { Bad_Opcode },
13113     { Bad_Opcode },
13114   },
13115   /* de */
13116   {
13117     { "faddp",  { STi, ST }, 0 },
13118     { "fmulp",  { STi, ST }, 0 },
13119     { Bad_Opcode },
13120     { FGRPde_3 },
13121     { "fsub{!M|r}p",    { STi, ST }, 0 },
13122     { "fsub{M|}p",      { STi, ST }, 0 },
13123     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13124     { "fdiv{M|}p",      { STi, ST }, 0 },
13125   },
13126   /* df */
13127   {
13128     { "ffreep", { STi }, 0 },
13129     { Bad_Opcode },
13130     { Bad_Opcode },
13131     { Bad_Opcode },
13132     { FGRPdf_4 },
13133     { "fucomip", { ST, STi }, 0 },
13134     { "fcomip", { ST, STi }, 0 },
13135     { Bad_Opcode },
13136   },
13137 };
13138
13139 static char *fgrps[][8] = {
13140   /* Bad opcode 0 */
13141   {
13142     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13143   },
13144
13145   /* d9_2  1 */
13146   {
13147     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13148   },
13149
13150   /* d9_4  2 */
13151   {
13152     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13153   },
13154
13155   /* d9_5  3 */
13156   {
13157     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13158   },
13159
13160   /* d9_6  4 */
13161   {
13162     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13163   },
13164
13165   /* d9_7  5 */
13166   {
13167     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13168   },
13169
13170   /* da_5  6 */
13171   {
13172     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13173   },
13174
13175   /* db_4  7 */
13176   {
13177     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13178     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13179   },
13180
13181   /* de_3  8 */
13182   {
13183     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13184   },
13185
13186   /* df_4  9 */
13187   {
13188     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13189   },
13190 };
13191
13192 static void
13193 swap_operand (void)
13194 {
13195   mnemonicendp[0] = '.';
13196   mnemonicendp[1] = 's';
13197   mnemonicendp += 2;
13198 }
13199
13200 static void
13201 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13202                int sizeflag ATTRIBUTE_UNUSED)
13203 {
13204   /* Skip mod/rm byte.  */
13205   MODRM_CHECK;
13206   codep++;
13207 }
13208
13209 static void
13210 dofloat (int sizeflag)
13211 {
13212   const struct dis386 *dp;
13213   unsigned char floatop;
13214
13215   floatop = codep[-1];
13216
13217   if (modrm.mod != 3)
13218     {
13219       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13220
13221       putop (float_mem[fp_indx], sizeflag);
13222       obufp = op_out[0];
13223       op_ad = 2;
13224       OP_E (float_mem_mode[fp_indx], sizeflag);
13225       return;
13226     }
13227   /* Skip mod/rm byte.  */
13228   MODRM_CHECK;
13229   codep++;
13230
13231   dp = &float_reg[floatop - 0xd8][modrm.reg];
13232   if (dp->name == NULL)
13233     {
13234       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13235
13236       /* Instruction fnstsw is only one with strange arg.  */
13237       if (floatop == 0xdf && codep[-1] == 0xe0)
13238         strcpy (op_out[0], names16[0]);
13239     }
13240   else
13241     {
13242       putop (dp->name, sizeflag);
13243
13244       obufp = op_out[0];
13245       op_ad = 2;
13246       if (dp->op[0].rtn)
13247         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13248
13249       obufp = op_out[1];
13250       op_ad = 1;
13251       if (dp->op[1].rtn)
13252         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13253     }
13254 }
13255
13256 /* Like oappend (below), but S is a string starting with '%'.
13257    In Intel syntax, the '%' is elided.  */
13258 static void
13259 oappend_maybe_intel (const char *s)
13260 {
13261   oappend (s + intel_syntax);
13262 }
13263
13264 static void
13265 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13266 {
13267   oappend_maybe_intel ("%st");
13268 }
13269
13270 static void
13271 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13272 {
13273   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13274   oappend_maybe_intel (scratchbuf);
13275 }
13276
13277 /* Capital letters in template are macros.  */
13278 static int
13279 putop (const char *in_template, int sizeflag)
13280 {
13281   const char *p;
13282   int alt = 0;
13283   int cond = 1;
13284   unsigned int l = 0, len = 0;
13285   char last[4];
13286
13287   for (p = in_template; *p; p++)
13288     {
13289       if (len > l)
13290         {
13291           if (l >= sizeof (last) || !ISUPPER (*p))
13292             abort ();
13293           last[l++] = *p;
13294           continue;
13295         }
13296       switch (*p)
13297         {
13298         default:
13299           *obufp++ = *p;
13300           break;
13301         case '%':
13302           len++;
13303           break;
13304         case '!':
13305           cond = 0;
13306           break;
13307         case '{':
13308           if (intel_syntax)
13309             {
13310               while (*++p != '|')
13311                 if (*p == '}' || *p == '\0')
13312                   abort ();
13313               alt = 1;
13314             }
13315           break;
13316         case '|':
13317           while (*++p != '}')
13318             {
13319               if (*p == '\0')
13320                 abort ();
13321             }
13322           break;
13323         case '}':
13324           alt = 0;
13325           break;
13326         case 'A':
13327           if (intel_syntax)
13328             break;
13329           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13330             *obufp++ = 'b';
13331           break;
13332         case 'B':
13333           if (l == 0)
13334             {
13335             case_B:
13336               if (intel_syntax)
13337                 break;
13338               if (sizeflag & SUFFIX_ALWAYS)
13339                 *obufp++ = 'b';
13340             }
13341           else if (l == 1 && last[0] == 'L')
13342             {
13343               if (address_mode == mode_64bit
13344                   && !(prefixes & PREFIX_ADDR))
13345                 {
13346                   *obufp++ = 'a';
13347                   *obufp++ = 'b';
13348                   *obufp++ = 's';
13349                 }
13350
13351               goto case_B;
13352             }
13353           else
13354             abort ();
13355           break;
13356         case 'C':
13357           if (intel_syntax && !alt)
13358             break;
13359           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13360             {
13361               if (sizeflag & DFLAG)
13362                 *obufp++ = intel_syntax ? 'd' : 'l';
13363               else
13364                 *obufp++ = intel_syntax ? 'w' : 's';
13365               used_prefixes |= (prefixes & PREFIX_DATA);
13366             }
13367           break;
13368         case 'D':
13369           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13370             break;
13371           USED_REX (REX_W);
13372           if (modrm.mod == 3)
13373             {
13374               if (rex & REX_W)
13375                 *obufp++ = 'q';
13376               else
13377                 {
13378                   if (sizeflag & DFLAG)
13379                     *obufp++ = intel_syntax ? 'd' : 'l';
13380                   else
13381                     *obufp++ = 'w';
13382                   used_prefixes |= (prefixes & PREFIX_DATA);
13383                 }
13384             }
13385           else
13386             *obufp++ = 'w';
13387           break;
13388         case 'E':               /* For jcxz/jecxz */
13389           if (address_mode == mode_64bit)
13390             {
13391               if (sizeflag & AFLAG)
13392                 *obufp++ = 'r';
13393               else
13394                 *obufp++ = 'e';
13395             }
13396           else
13397             if (sizeflag & AFLAG)
13398               *obufp++ = 'e';
13399           used_prefixes |= (prefixes & PREFIX_ADDR);
13400           break;
13401         case 'F':
13402           if (intel_syntax)
13403             break;
13404           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13405             {
13406               if (sizeflag & AFLAG)
13407                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13408               else
13409                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13410               used_prefixes |= (prefixes & PREFIX_ADDR);
13411             }
13412           break;
13413         case 'G':
13414           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13415             break;
13416           if ((rex & REX_W) || (sizeflag & DFLAG))
13417             *obufp++ = 'l';
13418           else
13419             *obufp++ = 'w';
13420           if (!(rex & REX_W))
13421             used_prefixes |= (prefixes & PREFIX_DATA);
13422           break;
13423         case 'H':
13424           if (intel_syntax)
13425             break;
13426           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13427               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13428             {
13429               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13430               *obufp++ = ',';
13431               *obufp++ = 'p';
13432               if (prefixes & PREFIX_DS)
13433                 *obufp++ = 't';
13434               else
13435                 *obufp++ = 'n';
13436             }
13437           break;
13438         case 'K':
13439           USED_REX (REX_W);
13440           if (rex & REX_W)
13441             *obufp++ = 'q';
13442           else
13443             *obufp++ = 'd';
13444           break;
13445         case 'Z':
13446           if (l != 0)
13447             {
13448               if (l != 1 || last[0] != 'X')
13449                 abort ();
13450               if (!need_vex || !vex.evex)
13451                 abort ();
13452               if (intel_syntax
13453                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13454                 break;
13455               switch (vex.length)
13456                 {
13457                 case 128:
13458                   *obufp++ = 'x';
13459                   break;
13460                 case 256:
13461                   *obufp++ = 'y';
13462                   break;
13463                 case 512:
13464                   *obufp++ = 'z';
13465                   break;
13466                 default:
13467                   abort ();
13468                 }
13469               break;
13470             }
13471           if (intel_syntax)
13472             break;
13473           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13474             {
13475               *obufp++ = 'q';
13476               break;
13477             }
13478           /* Fall through.  */
13479           goto case_L;
13480         case 'L':
13481           if (l != 0)
13482             abort ();
13483         case_L:
13484           if (intel_syntax)
13485             break;
13486           if (sizeflag & SUFFIX_ALWAYS)
13487             *obufp++ = 'l';
13488           break;
13489         case 'M':
13490           if (intel_mnemonic != cond)
13491             *obufp++ = 'r';
13492           break;
13493         case 'N':
13494           if ((prefixes & PREFIX_FWAIT) == 0)
13495             *obufp++ = 'n';
13496           else
13497             used_prefixes |= PREFIX_FWAIT;
13498           break;
13499         case 'O':
13500           USED_REX (REX_W);
13501           if (rex & REX_W)
13502             *obufp++ = 'o';
13503           else if (intel_syntax && (sizeflag & DFLAG))
13504             *obufp++ = 'q';
13505           else
13506             *obufp++ = 'd';
13507           if (!(rex & REX_W))
13508             used_prefixes |= (prefixes & PREFIX_DATA);
13509           break;
13510         case '&':
13511           if (!intel_syntax
13512               && address_mode == mode_64bit
13513               && isa64 == intel64)
13514             {
13515               *obufp++ = 'q';
13516               break;
13517             }
13518           /* Fall through.  */
13519         case 'T':
13520           if (!intel_syntax
13521               && address_mode == mode_64bit
13522               && ((sizeflag & DFLAG) || (rex & REX_W)))
13523             {
13524               *obufp++ = 'q';
13525               break;
13526             }
13527           /* Fall through.  */
13528           goto case_P;
13529         case 'P':
13530           if (l == 0)
13531             {
13532             case_P:
13533               if (intel_syntax)
13534                 {
13535                   if ((rex & REX_W) == 0
13536                       && (prefixes & PREFIX_DATA))
13537                     {
13538                       if ((sizeflag & DFLAG) == 0)
13539                         *obufp++ = 'w';
13540                       used_prefixes |= (prefixes & PREFIX_DATA);
13541                     }
13542                   break;
13543                 }
13544               if ((prefixes & PREFIX_DATA)
13545                   || (rex & REX_W)
13546                   || (sizeflag & SUFFIX_ALWAYS))
13547                 {
13548                   USED_REX (REX_W);
13549                   if (rex & REX_W)
13550                     *obufp++ = 'q';
13551                   else
13552                     {
13553                       if (sizeflag & DFLAG)
13554                         *obufp++ = 'l';
13555                       else
13556                         *obufp++ = 'w';
13557                       used_prefixes |= (prefixes & PREFIX_DATA);
13558                     }
13559                 }
13560             }
13561           else if (l == 1 && last[0] == 'L')
13562             {
13563               if ((prefixes & PREFIX_DATA)
13564                   || (rex & REX_W)
13565                   || (sizeflag & SUFFIX_ALWAYS))
13566                 {
13567                   USED_REX (REX_W);
13568                   if (rex & REX_W)
13569                     *obufp++ = 'q';
13570                   else
13571                     {
13572                       if (sizeflag & DFLAG)
13573                         *obufp++ = intel_syntax ? 'd' : 'l';
13574                       else
13575                         *obufp++ = 'w';
13576                       used_prefixes |= (prefixes & PREFIX_DATA);
13577                     }
13578                 }
13579             }
13580           else
13581             abort ();
13582           break;
13583         case 'U':
13584           if (intel_syntax)
13585             break;
13586           if (address_mode == mode_64bit
13587               && ((sizeflag & DFLAG) || (rex & REX_W)))
13588             {
13589               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13590                 *obufp++ = 'q';
13591               break;
13592             }
13593           /* Fall through.  */
13594           goto case_Q;
13595         case 'Q':
13596           if (l == 0)
13597             {
13598             case_Q:
13599               if (intel_syntax && !alt)
13600                 break;
13601               USED_REX (REX_W);
13602               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13603                 {
13604                   if (rex & REX_W)
13605                     *obufp++ = 'q';
13606                   else
13607                     {
13608                       if (sizeflag & DFLAG)
13609                         *obufp++ = intel_syntax ? 'd' : 'l';
13610                       else
13611                         *obufp++ = 'w';
13612                       used_prefixes |= (prefixes & PREFIX_DATA);
13613                     }
13614                 }
13615             }
13616           else if (l == 1 && last[0] == 'D')
13617             *obufp++ = vex.w ? 'q' : 'd';
13618           else if (l == 1 && last[0] == 'L')
13619             {
13620               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
13621                        : address_mode != mode_64bit)
13622                 break;
13623               if ((rex & REX_W))
13624                 {
13625                   USED_REX (REX_W);
13626                   *obufp++ = 'q';
13627                 }
13628               else if((address_mode == mode_64bit && need_modrm && cond)
13629                       || (sizeflag & SUFFIX_ALWAYS))
13630                 *obufp++ = intel_syntax? 'd' : 'l';
13631             }
13632           else
13633             abort ();
13634           break;
13635         case 'R':
13636           USED_REX (REX_W);
13637           if (rex & REX_W)
13638             *obufp++ = 'q';
13639           else if (sizeflag & DFLAG)
13640             {
13641               if (intel_syntax)
13642                   *obufp++ = 'd';
13643               else
13644                   *obufp++ = 'l';
13645             }
13646           else
13647             *obufp++ = 'w';
13648           if (intel_syntax && !p[1]
13649               && ((rex & REX_W) || (sizeflag & DFLAG)))
13650             *obufp++ = 'e';
13651           if (!(rex & REX_W))
13652             used_prefixes |= (prefixes & PREFIX_DATA);
13653           break;
13654         case 'V':
13655           if (l == 0)
13656             {
13657               if (intel_syntax)
13658                 break;
13659               if (address_mode == mode_64bit
13660                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13661                 {
13662                   if (sizeflag & SUFFIX_ALWAYS)
13663                     *obufp++ = 'q';
13664                   break;
13665                 }
13666             }
13667           else if (l == 1 && last[0] == 'L')
13668             {
13669               if (rex & REX_W)
13670                 {
13671                   *obufp++ = 'a';
13672                   *obufp++ = 'b';
13673                   *obufp++ = 's';
13674                 }
13675             }
13676           else
13677             abort ();
13678           /* Fall through.  */
13679           goto case_S;
13680         case 'S':
13681           if (l == 0)
13682             {
13683             case_S:
13684               if (intel_syntax)
13685                 break;
13686               if (sizeflag & SUFFIX_ALWAYS)
13687                 {
13688                   if (rex & REX_W)
13689                     *obufp++ = 'q';
13690                   else
13691                     {
13692                       if (sizeflag & DFLAG)
13693                         *obufp++ = 'l';
13694                       else
13695                         *obufp++ = 'w';
13696                       used_prefixes |= (prefixes & PREFIX_DATA);
13697                     }
13698                 }
13699             }
13700           else if (l == 1 && last[0] == 'L')
13701             {
13702               if (address_mode == mode_64bit
13703                   && !(prefixes & PREFIX_ADDR))
13704                 {
13705                   *obufp++ = 'a';
13706                   *obufp++ = 'b';
13707                   *obufp++ = 's';
13708                 }
13709
13710               goto case_S;
13711             }
13712           else
13713             abort ();
13714           break;
13715         case 'X':
13716           if (l != 0)
13717             abort ();
13718           if (need_vex
13719               ? vex.prefix == DATA_PREFIX_OPCODE
13720               : prefixes & PREFIX_DATA)
13721             {
13722               *obufp++ = 'd';
13723               used_prefixes |= PREFIX_DATA;
13724             }
13725           else
13726             *obufp++ = 's';
13727           break;
13728         case 'Y':
13729           if (l == 1 && last[0] == 'X')
13730             {
13731               if (!need_vex)
13732                 abort ();
13733               if (intel_syntax
13734                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13735                 break;
13736               switch (vex.length)
13737                 {
13738                 case 128:
13739                   *obufp++ = 'x';
13740                   break;
13741                 case 256:
13742                   *obufp++ = 'y';
13743                   break;
13744                 case 512:
13745                   if (!vex.evex)
13746                 default:
13747                     abort ();
13748                 }
13749             }
13750           else
13751             abort ();
13752           break;
13753         case 'W':
13754           if (l == 0)
13755             {
13756               /* operand size flag for cwtl, cbtw */
13757               USED_REX (REX_W);
13758               if (rex & REX_W)
13759                 {
13760                   if (intel_syntax)
13761                     *obufp++ = 'd';
13762                   else
13763                     *obufp++ = 'l';
13764                 }
13765               else if (sizeflag & DFLAG)
13766                 *obufp++ = 'w';
13767               else
13768                 *obufp++ = 'b';
13769               if (!(rex & REX_W))
13770                 used_prefixes |= (prefixes & PREFIX_DATA);
13771             }
13772           else if (l == 1)
13773             {
13774               if (!need_vex)
13775                 abort ();
13776               if (last[0] == 'X')
13777                 *obufp++ = vex.w ? 'd': 's';
13778               else if (last[0] == 'B')
13779                 *obufp++ = vex.w ? 'w': 'b';
13780               else
13781                 abort ();
13782             }
13783           else
13784             abort ();
13785           break;
13786         case '^':
13787           if (intel_syntax)
13788             break;
13789           if (isa64 == intel64 && (rex & REX_W))
13790             {
13791               USED_REX (REX_W);
13792               *obufp++ = 'q';
13793               break;
13794             }
13795           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13796             {
13797               if (sizeflag & DFLAG)
13798                 *obufp++ = 'l';
13799               else
13800                 *obufp++ = 'w';
13801               used_prefixes |= (prefixes & PREFIX_DATA);
13802             }
13803           break;
13804         case '@':
13805           if (intel_syntax)
13806             break;
13807           if (address_mode == mode_64bit
13808               && (isa64 == intel64
13809                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13810               *obufp++ = 'q';
13811           else if ((prefixes & PREFIX_DATA))
13812             {
13813               if (!(sizeflag & DFLAG))
13814                 *obufp++ = 'w';
13815               used_prefixes |= (prefixes & PREFIX_DATA);
13816             }
13817           break;
13818         }
13819
13820       if (len == l)
13821         len = l = 0;
13822     }
13823   *obufp = 0;
13824   mnemonicendp = obufp;
13825   return 0;
13826 }
13827
13828 static void
13829 oappend (const char *s)
13830 {
13831   obufp = stpcpy (obufp, s);
13832 }
13833
13834 static void
13835 append_seg (void)
13836 {
13837   /* Only print the active segment register.  */
13838   if (!active_seg_prefix)
13839     return;
13840
13841   used_prefixes |= active_seg_prefix;
13842   switch (active_seg_prefix)
13843     {
13844     case PREFIX_CS:
13845       oappend_maybe_intel ("%cs:");
13846       break;
13847     case PREFIX_DS:
13848       oappend_maybe_intel ("%ds:");
13849       break;
13850     case PREFIX_SS:
13851       oappend_maybe_intel ("%ss:");
13852       break;
13853     case PREFIX_ES:
13854       oappend_maybe_intel ("%es:");
13855       break;
13856     case PREFIX_FS:
13857       oappend_maybe_intel ("%fs:");
13858       break;
13859     case PREFIX_GS:
13860       oappend_maybe_intel ("%gs:");
13861       break;
13862     default:
13863       break;
13864     }
13865 }
13866
13867 static void
13868 OP_indirE (int bytemode, int sizeflag)
13869 {
13870   if (!intel_syntax)
13871     oappend ("*");
13872   OP_E (bytemode, sizeflag);
13873 }
13874
13875 static void
13876 print_operand_value (char *buf, int hex, bfd_vma disp)
13877 {
13878   if (address_mode == mode_64bit)
13879     {
13880       if (hex)
13881         {
13882           char tmp[30];
13883           int i;
13884           buf[0] = '0';
13885           buf[1] = 'x';
13886           sprintf_vma (tmp, disp);
13887           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13888           strcpy (buf + 2, tmp + i);
13889         }
13890       else
13891         {
13892           bfd_signed_vma v = disp;
13893           char tmp[30];
13894           int i;
13895           if (v < 0)
13896             {
13897               *(buf++) = '-';
13898               v = -disp;
13899               /* Check for possible overflow on 0x8000000000000000.  */
13900               if (v < 0)
13901                 {
13902                   strcpy (buf, "9223372036854775808");
13903                   return;
13904                 }
13905             }
13906           if (!v)
13907             {
13908               strcpy (buf, "0");
13909               return;
13910             }
13911
13912           i = 0;
13913           tmp[29] = 0;
13914           while (v)
13915             {
13916               tmp[28 - i] = (v % 10) + '0';
13917               v /= 10;
13918               i++;
13919             }
13920           strcpy (buf, tmp + 29 - i);
13921         }
13922     }
13923   else
13924     {
13925       if (hex)
13926         sprintf (buf, "0x%x", (unsigned int) disp);
13927       else
13928         sprintf (buf, "%d", (int) disp);
13929     }
13930 }
13931
13932 /* Put DISP in BUF as signed hex number.  */
13933
13934 static void
13935 print_displacement (char *buf, bfd_vma disp)
13936 {
13937   bfd_signed_vma val = disp;
13938   char tmp[30];
13939   int i, j = 0;
13940
13941   if (val < 0)
13942     {
13943       buf[j++] = '-';
13944       val = -disp;
13945
13946       /* Check for possible overflow.  */
13947       if (val < 0)
13948         {
13949           switch (address_mode)
13950             {
13951             case mode_64bit:
13952               strcpy (buf + j, "0x8000000000000000");
13953               break;
13954             case mode_32bit:
13955               strcpy (buf + j, "0x80000000");
13956               break;
13957             case mode_16bit:
13958               strcpy (buf + j, "0x8000");
13959               break;
13960             }
13961           return;
13962         }
13963     }
13964
13965   buf[j++] = '0';
13966   buf[j++] = 'x';
13967
13968   sprintf_vma (tmp, (bfd_vma) val);
13969   for (i = 0; tmp[i] == '0'; i++)
13970     continue;
13971   if (tmp[i] == '\0')
13972     i--;
13973   strcpy (buf + j, tmp + i);
13974 }
13975
13976 static void
13977 intel_operand_size (int bytemode, int sizeflag)
13978 {
13979   if (vex.evex
13980       && vex.b
13981       && (bytemode == x_mode
13982           || bytemode == evex_half_bcst_xmmq_mode))
13983     {
13984       if (vex.w)
13985         oappend ("QWORD PTR ");
13986       else
13987         oappend ("DWORD PTR ");
13988       return;
13989     }
13990   switch (bytemode)
13991     {
13992     case b_mode:
13993     case b_swap_mode:
13994     case dqb_mode:
13995     case db_mode:
13996       oappend ("BYTE PTR ");
13997       break;
13998     case w_mode:
13999     case dw_mode:
14000     case dqw_mode:
14001       oappend ("WORD PTR ");
14002       break;
14003     case indir_v_mode:
14004       if (address_mode == mode_64bit && isa64 == intel64)
14005         {
14006           oappend ("QWORD PTR ");
14007           break;
14008         }
14009       /* Fall through.  */
14010     case stack_v_mode:
14011       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14012         {
14013           oappend ("QWORD PTR ");
14014           break;
14015         }
14016       /* Fall through.  */
14017     case v_mode:
14018     case v_swap_mode:
14019     case dq_mode:
14020       USED_REX (REX_W);
14021       if (rex & REX_W)
14022         oappend ("QWORD PTR ");
14023       else
14024         {
14025           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14026             oappend ("DWORD PTR ");
14027           else
14028             oappend ("WORD PTR ");
14029           used_prefixes |= (prefixes & PREFIX_DATA);
14030         }
14031       break;
14032     case z_mode:
14033       if ((rex & REX_W) || (sizeflag & DFLAG))
14034         *obufp++ = 'D';
14035       oappend ("WORD PTR ");
14036       if (!(rex & REX_W))
14037         used_prefixes |= (prefixes & PREFIX_DATA);
14038       break;
14039     case a_mode:
14040       if (sizeflag & DFLAG)
14041         oappend ("QWORD PTR ");
14042       else
14043         oappend ("DWORD PTR ");
14044       used_prefixes |= (prefixes & PREFIX_DATA);
14045       break;
14046     case movsxd_mode:
14047       if (!(sizeflag & DFLAG) && isa64 == intel64)
14048         oappend ("WORD PTR ");
14049       else
14050         oappend ("DWORD PTR ");
14051       used_prefixes |= (prefixes & PREFIX_DATA);
14052       break;
14053     case d_mode:
14054     case d_swap_mode:
14055     case dqd_mode:
14056       oappend ("DWORD PTR ");
14057       break;
14058     case q_mode:
14059     case q_swap_mode:
14060       oappend ("QWORD PTR ");
14061       break;
14062     case m_mode:
14063       if (address_mode == mode_64bit)
14064         oappend ("QWORD PTR ");
14065       else
14066         oappend ("DWORD PTR ");
14067       break;
14068     case f_mode:
14069       if (sizeflag & DFLAG)
14070         oappend ("FWORD PTR ");
14071       else
14072         oappend ("DWORD PTR ");
14073       used_prefixes |= (prefixes & PREFIX_DATA);
14074       break;
14075     case t_mode:
14076       oappend ("TBYTE PTR ");
14077       break;
14078     case x_mode:
14079     case x_swap_mode:
14080     case evex_x_gscat_mode:
14081     case evex_x_nobcst_mode:
14082     case bw_unit_mode:
14083       if (need_vex)
14084         {
14085           switch (vex.length)
14086             {
14087             case 128:
14088               oappend ("XMMWORD PTR ");
14089               break;
14090             case 256:
14091               oappend ("YMMWORD PTR ");
14092               break;
14093             case 512:
14094               oappend ("ZMMWORD PTR ");
14095               break;
14096             default:
14097               abort ();
14098             }
14099         }
14100       else
14101         oappend ("XMMWORD PTR ");
14102       break;
14103     case xmm_mode:
14104       oappend ("XMMWORD PTR ");
14105       break;
14106     case ymm_mode:
14107       oappend ("YMMWORD PTR ");
14108       break;
14109     case xmmq_mode:
14110     case evex_half_bcst_xmmq_mode:
14111       if (!need_vex)
14112         abort ();
14113
14114       switch (vex.length)
14115         {
14116         case 128:
14117           oappend ("QWORD PTR ");
14118           break;
14119         case 256:
14120           oappend ("XMMWORD PTR ");
14121           break;
14122         case 512:
14123           oappend ("YMMWORD PTR ");
14124           break;
14125         default:
14126           abort ();
14127         }
14128       break;
14129     case xmm_mb_mode:
14130       if (!need_vex)
14131         abort ();
14132
14133       switch (vex.length)
14134         {
14135         case 128:
14136         case 256:
14137         case 512:
14138           oappend ("BYTE PTR ");
14139           break;
14140         default:
14141           abort ();
14142         }
14143       break;
14144     case xmm_mw_mode:
14145       if (!need_vex)
14146         abort ();
14147
14148       switch (vex.length)
14149         {
14150         case 128:
14151         case 256:
14152         case 512:
14153           oappend ("WORD PTR ");
14154           break;
14155         default:
14156           abort ();
14157         }
14158       break;
14159     case xmm_md_mode:
14160       if (!need_vex)
14161         abort ();
14162
14163       switch (vex.length)
14164         {
14165         case 128:
14166         case 256:
14167         case 512:
14168           oappend ("DWORD PTR ");
14169           break;
14170         default:
14171           abort ();
14172         }
14173       break;
14174     case xmm_mq_mode:
14175       if (!need_vex)
14176         abort ();
14177
14178       switch (vex.length)
14179         {
14180         case 128:
14181         case 256:
14182         case 512:
14183           oappend ("QWORD PTR ");
14184           break;
14185         default:
14186           abort ();
14187         }
14188       break;
14189     case xmmdw_mode:
14190       if (!need_vex)
14191         abort ();
14192
14193       switch (vex.length)
14194         {
14195         case 128:
14196           oappend ("WORD PTR ");
14197           break;
14198         case 256:
14199           oappend ("DWORD PTR ");
14200           break;
14201         case 512:
14202           oappend ("QWORD PTR ");
14203           break;
14204         default:
14205           abort ();
14206         }
14207       break;
14208     case xmmqd_mode:
14209       if (!need_vex)
14210         abort ();
14211
14212       switch (vex.length)
14213         {
14214         case 128:
14215           oappend ("DWORD PTR ");
14216           break;
14217         case 256:
14218           oappend ("QWORD PTR ");
14219           break;
14220         case 512:
14221           oappend ("XMMWORD PTR ");
14222           break;
14223         default:
14224           abort ();
14225         }
14226       break;
14227     case ymmq_mode:
14228       if (!need_vex)
14229         abort ();
14230
14231       switch (vex.length)
14232         {
14233         case 128:
14234           oappend ("QWORD PTR ");
14235           break;
14236         case 256:
14237           oappend ("YMMWORD PTR ");
14238           break;
14239         case 512:
14240           oappend ("ZMMWORD PTR ");
14241           break;
14242         default:
14243           abort ();
14244         }
14245       break;
14246     case ymmxmm_mode:
14247       if (!need_vex)
14248         abort ();
14249
14250       switch (vex.length)
14251         {
14252         case 128:
14253         case 256:
14254           oappend ("XMMWORD PTR ");
14255           break;
14256         default:
14257           abort ();
14258         }
14259       break;
14260     case o_mode:
14261       oappend ("OWORD PTR ");
14262       break;
14263     case vex_scalar_w_dq_mode:
14264       if (!need_vex)
14265         abort ();
14266
14267       if (vex.w)
14268         oappend ("QWORD PTR ");
14269       else
14270         oappend ("DWORD PTR ");
14271       break;
14272     case vex_vsib_d_w_dq_mode:
14273     case vex_vsib_q_w_dq_mode:
14274       if (!need_vex)
14275         abort ();
14276
14277       if (!vex.evex)
14278         {
14279           if (vex.w)
14280             oappend ("QWORD PTR ");
14281           else
14282             oappend ("DWORD PTR ");
14283         }
14284       else
14285         {
14286           switch (vex.length)
14287             {
14288             case 128:
14289               oappend ("XMMWORD PTR ");
14290               break;
14291             case 256:
14292               oappend ("YMMWORD PTR ");
14293               break;
14294             case 512:
14295               oappend ("ZMMWORD PTR ");
14296               break;
14297             default:
14298               abort ();
14299             }
14300         }
14301       break;
14302     case vex_vsib_q_w_d_mode:
14303     case vex_vsib_d_w_d_mode:
14304       if (!need_vex || !vex.evex)
14305         abort ();
14306
14307       switch (vex.length)
14308         {
14309         case 128:
14310           oappend ("QWORD PTR ");
14311           break;
14312         case 256:
14313           oappend ("XMMWORD PTR ");
14314           break;
14315         case 512:
14316           oappend ("YMMWORD PTR ");
14317           break;
14318         default:
14319           abort ();
14320         }
14321
14322       break;
14323     case mask_bd_mode:
14324       if (!need_vex || vex.length != 128)
14325         abort ();
14326       if (vex.w)
14327         oappend ("DWORD PTR ");
14328       else
14329         oappend ("BYTE PTR ");
14330       break;
14331     case mask_mode:
14332       if (!need_vex)
14333         abort ();
14334       if (vex.w)
14335         oappend ("QWORD PTR ");
14336       else
14337         oappend ("WORD PTR ");
14338       break;
14339     case v_bnd_mode:
14340     case v_bndmk_mode:
14341     default:
14342       break;
14343     }
14344 }
14345
14346 static void
14347 OP_E_register (int bytemode, int sizeflag)
14348 {
14349   int reg = modrm.rm;
14350   const char **names;
14351
14352   USED_REX (REX_B);
14353   if ((rex & REX_B))
14354     reg += 8;
14355
14356   if ((sizeflag & SUFFIX_ALWAYS)
14357       && (bytemode == b_swap_mode
14358           || bytemode == bnd_swap_mode
14359           || bytemode == v_swap_mode))
14360     swap_operand ();
14361
14362   switch (bytemode)
14363     {
14364     case b_mode:
14365     case b_swap_mode:
14366       if (reg & 4)
14367         USED_REX (0);
14368       if (rex)
14369         names = names8rex;
14370       else
14371         names = names8;
14372       break;
14373     case w_mode:
14374       names = names16;
14375       break;
14376     case d_mode:
14377     case dw_mode:
14378     case db_mode:
14379       names = names32;
14380       break;
14381     case q_mode:
14382       names = names64;
14383       break;
14384     case m_mode:
14385     case v_bnd_mode:
14386       names = address_mode == mode_64bit ? names64 : names32;
14387       break;
14388     case bnd_mode:
14389     case bnd_swap_mode:
14390       if (reg > 0x3)
14391         {
14392           oappend ("(bad)");
14393           return;
14394         }
14395       names = names_bnd;
14396       break;
14397     case indir_v_mode:
14398       if (address_mode == mode_64bit && isa64 == intel64)
14399         {
14400           names = names64;
14401           break;
14402         }
14403       /* Fall through.  */
14404     case stack_v_mode:
14405       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14406         {
14407           names = names64;
14408           break;
14409         }
14410       bytemode = v_mode;
14411       /* Fall through.  */
14412     case v_mode:
14413     case v_swap_mode:
14414     case dq_mode:
14415     case dqb_mode:
14416     case dqd_mode:
14417     case dqw_mode:
14418       USED_REX (REX_W);
14419       if (rex & REX_W)
14420         names = names64;
14421       else
14422         {
14423           if ((sizeflag & DFLAG)
14424               || (bytemode != v_mode
14425                   && bytemode != v_swap_mode))
14426             names = names32;
14427           else
14428             names = names16;
14429           used_prefixes |= (prefixes & PREFIX_DATA);
14430         }
14431       break;
14432     case movsxd_mode:
14433       if (!(sizeflag & DFLAG) && isa64 == intel64)
14434         names = names16;
14435       else
14436         names = names32;
14437       used_prefixes |= (prefixes & PREFIX_DATA);
14438       break;
14439     case va_mode:
14440       names = (address_mode == mode_64bit
14441                ? names64 : names32);
14442       if (!(prefixes & PREFIX_ADDR))
14443         names = (address_mode == mode_16bit
14444                      ? names16 : names);
14445       else
14446         {
14447           /* Remove "addr16/addr32".  */
14448           all_prefixes[last_addr_prefix] = 0;
14449           names = (address_mode != mode_32bit
14450                        ? names32 : names16);
14451           used_prefixes |= PREFIX_ADDR;
14452         }
14453       break;
14454     case mask_bd_mode:
14455     case mask_mode:
14456       if (reg > 0x7)
14457         {
14458           oappend ("(bad)");
14459           return;
14460         }
14461       names = names_mask;
14462       break;
14463     case 0:
14464       return;
14465     default:
14466       oappend (INTERNAL_DISASSEMBLER_ERROR);
14467       return;
14468     }
14469   oappend (names[reg]);
14470 }
14471
14472 static void
14473 OP_E_memory (int bytemode, int sizeflag)
14474 {
14475   bfd_vma disp = 0;
14476   int add = (rex & REX_B) ? 8 : 0;
14477   int riprel = 0;
14478   int shift;
14479
14480   if (vex.evex)
14481     {
14482       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14483       if (vex.b
14484           && bytemode != x_mode
14485           && bytemode != xmmq_mode
14486           && bytemode != evex_half_bcst_xmmq_mode)
14487         {
14488           BadOp ();
14489           return;
14490         }
14491       switch (bytemode)
14492         {
14493         case dqw_mode:
14494         case dw_mode:
14495         case xmm_mw_mode:
14496           shift = 1;
14497           break;
14498         case dqb_mode:
14499         case db_mode:
14500         case xmm_mb_mode:
14501           shift = 0;
14502           break;
14503         case dq_mode:
14504           if (address_mode != mode_64bit)
14505             {
14506         case dqd_mode:
14507         case xmm_md_mode:
14508         case d_mode:
14509         case d_swap_mode:
14510               shift = 2;
14511               break;
14512             }
14513             /* fall through */
14514         case vex_scalar_w_dq_mode:
14515         case vex_vsib_d_w_dq_mode:
14516         case vex_vsib_d_w_d_mode:
14517         case vex_vsib_q_w_dq_mode:
14518         case vex_vsib_q_w_d_mode:
14519         case evex_x_gscat_mode:
14520           shift = vex.w ? 3 : 2;
14521           break;
14522         case x_mode:
14523         case evex_half_bcst_xmmq_mode:
14524         case xmmq_mode:
14525           if (vex.b)
14526             {
14527               shift = vex.w ? 3 : 2;
14528               break;
14529             }
14530           /* Fall through.  */
14531         case xmmqd_mode:
14532         case xmmdw_mode:
14533         case ymmq_mode:
14534         case evex_x_nobcst_mode:
14535         case x_swap_mode:
14536           switch (vex.length)
14537             {
14538             case 128:
14539               shift = 4;
14540               break;
14541             case 256:
14542               shift = 5;
14543               break;
14544             case 512:
14545               shift = 6;
14546               break;
14547             default:
14548               abort ();
14549             }
14550           /* Make necessary corrections to shift for modes that need it.  */
14551           if (bytemode == xmmq_mode
14552               || bytemode == evex_half_bcst_xmmq_mode
14553               || (bytemode == ymmq_mode && vex.length == 128))
14554             shift -= 1;
14555           else if (bytemode == xmmqd_mode)
14556             shift -= 2;
14557           else if (bytemode == xmmdw_mode)
14558             shift -= 3;
14559           break;
14560         case ymm_mode:
14561           shift = 5;
14562           break;
14563         case xmm_mode:
14564           shift = 4;
14565           break;
14566         case xmm_mq_mode:
14567         case q_mode:
14568         case q_swap_mode:
14569           shift = 3;
14570           break;
14571         case bw_unit_mode:
14572           shift = vex.w ? 1 : 0;
14573           break;
14574         default:
14575           abort ();
14576         }
14577     }
14578   else
14579     shift = 0;
14580
14581   USED_REX (REX_B);
14582   if (intel_syntax)
14583     intel_operand_size (bytemode, sizeflag);
14584   append_seg ();
14585
14586   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14587     {
14588       /* 32/64 bit address mode */
14589       int havedisp;
14590       int havesib;
14591       int havebase;
14592       int haveindex;
14593       int needindex;
14594       int needaddr32;
14595       int base, rbase;
14596       int vindex = 0;
14597       int scale = 0;
14598       int addr32flag = !((sizeflag & AFLAG)
14599                          || bytemode == v_bnd_mode
14600                          || bytemode == v_bndmk_mode
14601                          || bytemode == bnd_mode
14602                          || bytemode == bnd_swap_mode);
14603       const char **indexes64 = names64;
14604       const char **indexes32 = names32;
14605
14606       havesib = 0;
14607       havebase = 1;
14608       haveindex = 0;
14609       base = modrm.rm;
14610
14611       if (base == 4)
14612         {
14613           havesib = 1;
14614           vindex = sib.index;
14615           USED_REX (REX_X);
14616           if (rex & REX_X)
14617             vindex += 8;
14618           switch (bytemode)
14619             {
14620             case vex_vsib_d_w_dq_mode:
14621             case vex_vsib_d_w_d_mode:
14622             case vex_vsib_q_w_dq_mode:
14623             case vex_vsib_q_w_d_mode:
14624               if (!need_vex)
14625                 abort ();
14626               if (vex.evex)
14627                 {
14628                   if (!vex.v)
14629                     vindex += 16;
14630                 }
14631
14632               haveindex = 1;
14633               switch (vex.length)
14634                 {
14635                 case 128:
14636                   indexes64 = indexes32 = names_xmm;
14637                   break;
14638                 case 256:
14639                   if (!vex.w
14640                       || bytemode == vex_vsib_q_w_dq_mode
14641                       || bytemode == vex_vsib_q_w_d_mode)
14642                     indexes64 = indexes32 = names_ymm;
14643                   else
14644                     indexes64 = indexes32 = names_xmm;
14645                   break;
14646                 case 512:
14647                   if (!vex.w
14648                       || bytemode == vex_vsib_q_w_dq_mode
14649                       || bytemode == vex_vsib_q_w_d_mode)
14650                     indexes64 = indexes32 = names_zmm;
14651                   else
14652                     indexes64 = indexes32 = names_ymm;
14653                   break;
14654                 default:
14655                   abort ();
14656                 }
14657               break;
14658             default:
14659               haveindex = vindex != 4;
14660               break;
14661             }
14662           scale = sib.scale;
14663           base = sib.base;
14664           codep++;
14665         }
14666       else
14667         {
14668           /* mandatory non-vector SIB must have sib */
14669           if (bytemode == vex_sibmem_mode)
14670             {
14671               oappend ("(bad)");
14672               return;
14673             }
14674         }
14675       rbase = base + add;
14676
14677       switch (modrm.mod)
14678         {
14679         case 0:
14680           if (base == 5)
14681             {
14682               havebase = 0;
14683               if (address_mode == mode_64bit && !havesib)
14684                 riprel = 1;
14685               disp = get32s ();
14686               if (riprel && bytemode == v_bndmk_mode)
14687                 {
14688                   oappend ("(bad)");
14689                   return;
14690                 }
14691             }
14692           break;
14693         case 1:
14694           FETCH_DATA (the_info, codep + 1);
14695           disp = *codep++;
14696           if ((disp & 0x80) != 0)
14697             disp -= 0x100;
14698           if (vex.evex && shift > 0)
14699             disp <<= shift;
14700           break;
14701         case 2:
14702           disp = get32s ();
14703           break;
14704         }
14705
14706       needindex = 0;
14707       needaddr32 = 0;
14708       if (havesib
14709           && !havebase
14710           && !haveindex
14711           && address_mode != mode_16bit)
14712         {
14713           if (address_mode == mode_64bit)
14714             {
14715               /* Display eiz instead of addr32.  */
14716               needindex = addr32flag;
14717               needaddr32 = 1;
14718             }
14719           else
14720             {
14721               /* In 32-bit mode, we need index register to tell [offset]
14722                  from [eiz*1 + offset].  */
14723               needindex = 1;
14724             }
14725         }
14726
14727       havedisp = (havebase
14728                   || needindex
14729                   || (havesib && (haveindex || scale != 0)));
14730
14731       if (!intel_syntax)
14732         if (modrm.mod != 0 || base == 5)
14733           {
14734             if (havedisp || riprel)
14735               print_displacement (scratchbuf, disp);
14736             else
14737               print_operand_value (scratchbuf, 1, disp);
14738             oappend (scratchbuf);
14739             if (riprel)
14740               {
14741                 set_op (disp, 1);
14742                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14743               }
14744           }
14745
14746       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14747           && (address_mode != mode_64bit
14748               || ((bytemode != v_bnd_mode)
14749                   && (bytemode != v_bndmk_mode)
14750                   && (bytemode != bnd_mode)
14751                   && (bytemode != bnd_swap_mode))))
14752         used_prefixes |= PREFIX_ADDR;
14753
14754       if (havedisp || (intel_syntax && riprel))
14755         {
14756           *obufp++ = open_char;
14757           if (intel_syntax && riprel)
14758             {
14759               set_op (disp, 1);
14760               oappend (!addr32flag ? "rip" : "eip");
14761             }
14762           *obufp = '\0';
14763           if (havebase)
14764             oappend (address_mode == mode_64bit && !addr32flag
14765                      ? names64[rbase] : names32[rbase]);
14766           if (havesib)
14767             {
14768               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14769                  print index to tell base + index from base.  */
14770               if (scale != 0
14771                   || needindex
14772                   || haveindex
14773                   || (havebase && base != ESP_REG_NUM))
14774                 {
14775                   if (!intel_syntax || havebase)
14776                     {
14777                       *obufp++ = separator_char;
14778                       *obufp = '\0';
14779                     }
14780                   if (haveindex)
14781                     oappend (address_mode == mode_64bit && !addr32flag
14782                              ? indexes64[vindex] : indexes32[vindex]);
14783                   else
14784                     oappend (address_mode == mode_64bit && !addr32flag
14785                              ? index64 : index32);
14786
14787                   *obufp++ = scale_char;
14788                   *obufp = '\0';
14789                   sprintf (scratchbuf, "%d", 1 << scale);
14790                   oappend (scratchbuf);
14791                 }
14792             }
14793           if (intel_syntax
14794               && (disp || modrm.mod != 0 || base == 5))
14795             {
14796               if (!havedisp || (bfd_signed_vma) disp >= 0)
14797                 {
14798                   *obufp++ = '+';
14799                   *obufp = '\0';
14800                 }
14801               else if (modrm.mod != 1 && disp != -disp)
14802                 {
14803                   *obufp++ = '-';
14804                   *obufp = '\0';
14805                   disp = - (bfd_signed_vma) disp;
14806                 }
14807
14808               if (havedisp)
14809                 print_displacement (scratchbuf, disp);
14810               else
14811                 print_operand_value (scratchbuf, 1, disp);
14812               oappend (scratchbuf);
14813             }
14814
14815           *obufp++ = close_char;
14816           *obufp = '\0';
14817         }
14818       else if (intel_syntax)
14819         {
14820           if (modrm.mod != 0 || base == 5)
14821             {
14822               if (!active_seg_prefix)
14823                 {
14824                   oappend (names_seg[ds_reg - es_reg]);
14825                   oappend (":");
14826                 }
14827               print_operand_value (scratchbuf, 1, disp);
14828               oappend (scratchbuf);
14829             }
14830         }
14831     }
14832   else if (bytemode == v_bnd_mode
14833            || bytemode == v_bndmk_mode
14834            || bytemode == bnd_mode
14835            || bytemode == bnd_swap_mode)
14836     {
14837       oappend ("(bad)");
14838       return;
14839     }
14840   else
14841     {
14842       /* 16 bit address mode */
14843       used_prefixes |= prefixes & PREFIX_ADDR;
14844       switch (modrm.mod)
14845         {
14846         case 0:
14847           if (modrm.rm == 6)
14848             {
14849               disp = get16 ();
14850               if ((disp & 0x8000) != 0)
14851                 disp -= 0x10000;
14852             }
14853           break;
14854         case 1:
14855           FETCH_DATA (the_info, codep + 1);
14856           disp = *codep++;
14857           if ((disp & 0x80) != 0)
14858             disp -= 0x100;
14859           if (vex.evex && shift > 0)
14860             disp <<= shift;
14861           break;
14862         case 2:
14863           disp = get16 ();
14864           if ((disp & 0x8000) != 0)
14865             disp -= 0x10000;
14866           break;
14867         }
14868
14869       if (!intel_syntax)
14870         if (modrm.mod != 0 || modrm.rm == 6)
14871           {
14872             print_displacement (scratchbuf, disp);
14873             oappend (scratchbuf);
14874           }
14875
14876       if (modrm.mod != 0 || modrm.rm != 6)
14877         {
14878           *obufp++ = open_char;
14879           *obufp = '\0';
14880           oappend (index16[modrm.rm]);
14881           if (intel_syntax
14882               && (disp || modrm.mod != 0 || modrm.rm == 6))
14883             {
14884               if ((bfd_signed_vma) disp >= 0)
14885                 {
14886                   *obufp++ = '+';
14887                   *obufp = '\0';
14888                 }
14889               else if (modrm.mod != 1)
14890                 {
14891                   *obufp++ = '-';
14892                   *obufp = '\0';
14893                   disp = - (bfd_signed_vma) disp;
14894                 }
14895
14896               print_displacement (scratchbuf, disp);
14897               oappend (scratchbuf);
14898             }
14899
14900           *obufp++ = close_char;
14901           *obufp = '\0';
14902         }
14903       else if (intel_syntax)
14904         {
14905           if (!active_seg_prefix)
14906             {
14907               oappend (names_seg[ds_reg - es_reg]);
14908               oappend (":");
14909             }
14910           print_operand_value (scratchbuf, 1, disp & 0xffff);
14911           oappend (scratchbuf);
14912         }
14913     }
14914   if (vex.evex && vex.b
14915       && (bytemode == x_mode
14916           || bytemode == xmmq_mode
14917           || bytemode == evex_half_bcst_xmmq_mode))
14918     {
14919       if (vex.w
14920           || bytemode == xmmq_mode
14921           || bytemode == evex_half_bcst_xmmq_mode)
14922         {
14923           switch (vex.length)
14924             {
14925             case 128:
14926               oappend ("{1to2}");
14927               break;
14928             case 256:
14929               oappend ("{1to4}");
14930               break;
14931             case 512:
14932               oappend ("{1to8}");
14933               break;
14934             default:
14935               abort ();
14936             }
14937         }
14938       else
14939         {
14940           switch (vex.length)
14941             {
14942             case 128:
14943               oappend ("{1to4}");
14944               break;
14945             case 256:
14946               oappend ("{1to8}");
14947               break;
14948             case 512:
14949               oappend ("{1to16}");
14950               break;
14951             default:
14952               abort ();
14953             }
14954         }
14955     }
14956 }
14957
14958 static void
14959 OP_E (int bytemode, int sizeflag)
14960 {
14961   /* Skip mod/rm byte.  */
14962   MODRM_CHECK;
14963   codep++;
14964
14965   if (modrm.mod == 3)
14966     OP_E_register (bytemode, sizeflag);
14967   else
14968     OP_E_memory (bytemode, sizeflag);
14969 }
14970
14971 static void
14972 OP_G (int bytemode, int sizeflag)
14973 {
14974   int add = 0;
14975   const char **names;
14976   USED_REX (REX_R);
14977   if (rex & REX_R)
14978     add += 8;
14979   switch (bytemode)
14980     {
14981     case b_mode:
14982       if (modrm.reg & 4)
14983         USED_REX (0);
14984       if (rex)
14985         oappend (names8rex[modrm.reg + add]);
14986       else
14987         oappend (names8[modrm.reg + add]);
14988       break;
14989     case w_mode:
14990       oappend (names16[modrm.reg + add]);
14991       break;
14992     case d_mode:
14993     case db_mode:
14994     case dw_mode:
14995       oappend (names32[modrm.reg + add]);
14996       break;
14997     case q_mode:
14998       oappend (names64[modrm.reg + add]);
14999       break;
15000     case bnd_mode:
15001       if (modrm.reg > 0x3)
15002         {
15003           oappend ("(bad)");
15004           return;
15005         }
15006       oappend (names_bnd[modrm.reg]);
15007       break;
15008     case v_mode:
15009     case dq_mode:
15010     case dqb_mode:
15011     case dqd_mode:
15012     case dqw_mode:
15013     case movsxd_mode:
15014       USED_REX (REX_W);
15015       if (rex & REX_W)
15016         oappend (names64[modrm.reg + add]);
15017       else
15018         {
15019           if ((sizeflag & DFLAG)
15020               || (bytemode != v_mode && bytemode != movsxd_mode))
15021             oappend (names32[modrm.reg + add]);
15022           else
15023             oappend (names16[modrm.reg + add]);
15024           used_prefixes |= (prefixes & PREFIX_DATA);
15025         }
15026       break;
15027     case va_mode:
15028       names = (address_mode == mode_64bit
15029                ? names64 : names32);
15030       if (!(prefixes & PREFIX_ADDR))
15031         {
15032           if (address_mode == mode_16bit)
15033             names = names16;
15034         }
15035       else
15036         {
15037           /* Remove "addr16/addr32".  */
15038           all_prefixes[last_addr_prefix] = 0;
15039           names = (address_mode != mode_32bit
15040                        ? names32 : names16);
15041           used_prefixes |= PREFIX_ADDR;
15042         }
15043       oappend (names[modrm.reg + add]);
15044       break;
15045     case m_mode:
15046       if (address_mode == mode_64bit)
15047         oappend (names64[modrm.reg + add]);
15048       else
15049         oappend (names32[modrm.reg + add]);
15050       break;
15051     case mask_bd_mode:
15052     case mask_mode:
15053       if ((modrm.reg + add) > 0x7)
15054         {
15055           oappend ("(bad)");
15056           return;
15057         }
15058       oappend (names_mask[modrm.reg + add]);
15059       break;
15060     default:
15061       oappend (INTERNAL_DISASSEMBLER_ERROR);
15062       break;
15063     }
15064 }
15065
15066 static bfd_vma
15067 get64 (void)
15068 {
15069   bfd_vma x;
15070 #ifdef BFD64
15071   unsigned int a;
15072   unsigned int b;
15073
15074   FETCH_DATA (the_info, codep + 8);
15075   a = *codep++ & 0xff;
15076   a |= (*codep++ & 0xff) << 8;
15077   a |= (*codep++ & 0xff) << 16;
15078   a |= (*codep++ & 0xffu) << 24;
15079   b = *codep++ & 0xff;
15080   b |= (*codep++ & 0xff) << 8;
15081   b |= (*codep++ & 0xff) << 16;
15082   b |= (*codep++ & 0xffu) << 24;
15083   x = a + ((bfd_vma) b << 32);
15084 #else
15085   abort ();
15086   x = 0;
15087 #endif
15088   return x;
15089 }
15090
15091 static bfd_signed_vma
15092 get32 (void)
15093 {
15094   bfd_signed_vma x = 0;
15095
15096   FETCH_DATA (the_info, codep + 4);
15097   x = *codep++ & (bfd_signed_vma) 0xff;
15098   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15099   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15100   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15101   return x;
15102 }
15103
15104 static bfd_signed_vma
15105 get32s (void)
15106 {
15107   bfd_signed_vma x = 0;
15108
15109   FETCH_DATA (the_info, codep + 4);
15110   x = *codep++ & (bfd_signed_vma) 0xff;
15111   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15112   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15113   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15114
15115   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15116
15117   return x;
15118 }
15119
15120 static int
15121 get16 (void)
15122 {
15123   int x = 0;
15124
15125   FETCH_DATA (the_info, codep + 2);
15126   x = *codep++ & 0xff;
15127   x |= (*codep++ & 0xff) << 8;
15128   return x;
15129 }
15130
15131 static void
15132 set_op (bfd_vma op, int riprel)
15133 {
15134   op_index[op_ad] = op_ad;
15135   if (address_mode == mode_64bit)
15136     {
15137       op_address[op_ad] = op;
15138       op_riprel[op_ad] = riprel;
15139     }
15140   else
15141     {
15142       /* Mask to get a 32-bit address.  */
15143       op_address[op_ad] = op & 0xffffffff;
15144       op_riprel[op_ad] = riprel & 0xffffffff;
15145     }
15146 }
15147
15148 static void
15149 OP_REG (int code, int sizeflag)
15150 {
15151   const char *s;
15152   int add;
15153
15154   switch (code)
15155     {
15156     case es_reg: case ss_reg: case cs_reg:
15157     case ds_reg: case fs_reg: case gs_reg:
15158       oappend (names_seg[code - es_reg]);
15159       return;
15160     }
15161
15162   USED_REX (REX_B);
15163   if (rex & REX_B)
15164     add = 8;
15165   else
15166     add = 0;
15167
15168   switch (code)
15169     {
15170     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15171     case sp_reg: case bp_reg: case si_reg: case di_reg:
15172       s = names16[code - ax_reg + add];
15173       break;
15174     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
15175       USED_REX (0);
15176       /* Fall through.  */
15177     case al_reg: case cl_reg: case dl_reg: case bl_reg:
15178       if (rex)
15179         s = names8rex[code - al_reg + add];
15180       else
15181         s = names8[code - al_reg];
15182       break;
15183     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15184     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15185       if (address_mode == mode_64bit
15186           && ((sizeflag & DFLAG) || (rex & REX_W)))
15187         {
15188           s = names64[code - rAX_reg + add];
15189           break;
15190         }
15191       code += eAX_reg - rAX_reg;
15192       /* Fall through.  */
15193     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15194     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15195       USED_REX (REX_W);
15196       if (rex & REX_W)
15197         s = names64[code - eAX_reg + add];
15198       else
15199         {
15200           if (sizeflag & DFLAG)
15201             s = names32[code - eAX_reg + add];
15202           else
15203             s = names16[code - eAX_reg + add];
15204           used_prefixes |= (prefixes & PREFIX_DATA);
15205         }
15206       break;
15207     default:
15208       s = INTERNAL_DISASSEMBLER_ERROR;
15209       break;
15210     }
15211   oappend (s);
15212 }
15213
15214 static void
15215 OP_IMREG (int code, int sizeflag)
15216 {
15217   const char *s;
15218
15219   switch (code)
15220     {
15221     case indir_dx_reg:
15222       if (intel_syntax)
15223         s = "dx";
15224       else
15225         s = "(%dx)";
15226       break;
15227     case al_reg: case cl_reg:
15228       s = names8[code - al_reg];
15229       break;
15230     case eAX_reg:
15231       USED_REX (REX_W);
15232       if (rex & REX_W)
15233         {
15234           s = *names64;
15235           break;
15236         }
15237       /* Fall through.  */
15238     case z_mode_ax_reg:
15239       if ((rex & REX_W) || (sizeflag & DFLAG))
15240         s = *names32;
15241       else
15242         s = *names16;
15243       if (!(rex & REX_W))
15244         used_prefixes |= (prefixes & PREFIX_DATA);
15245       break;
15246     default:
15247       s = INTERNAL_DISASSEMBLER_ERROR;
15248       break;
15249     }
15250   oappend (s);
15251 }
15252
15253 static void
15254 OP_I (int bytemode, int sizeflag)
15255 {
15256   bfd_signed_vma op;
15257   bfd_signed_vma mask = -1;
15258
15259   switch (bytemode)
15260     {
15261     case b_mode:
15262       FETCH_DATA (the_info, codep + 1);
15263       op = *codep++;
15264       mask = 0xff;
15265       break;
15266     case v_mode:
15267       USED_REX (REX_W);
15268       if (rex & REX_W)
15269         op = get32s ();
15270       else
15271         {
15272           if (sizeflag & DFLAG)
15273             {
15274               op = get32 ();
15275               mask = 0xffffffff;
15276             }
15277           else
15278             {
15279               op = get16 ();
15280               mask = 0xfffff;
15281             }
15282           used_prefixes |= (prefixes & PREFIX_DATA);
15283         }
15284       break;
15285     case d_mode:
15286       mask = 0xffffffff;
15287       op = get32 ();
15288       break;
15289     case w_mode:
15290       mask = 0xfffff;
15291       op = get16 ();
15292       break;
15293     case const_1_mode:
15294       if (intel_syntax)
15295         oappend ("1");
15296       return;
15297     default:
15298       oappend (INTERNAL_DISASSEMBLER_ERROR);
15299       return;
15300     }
15301
15302   op &= mask;
15303   scratchbuf[0] = '$';
15304   print_operand_value (scratchbuf + 1, 1, op);
15305   oappend_maybe_intel (scratchbuf);
15306   scratchbuf[0] = '\0';
15307 }
15308
15309 static void
15310 OP_I64 (int bytemode, int sizeflag)
15311 {
15312   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15313     {
15314       OP_I (bytemode, sizeflag);
15315       return;
15316     }
15317
15318   USED_REX (REX_W);
15319
15320   scratchbuf[0] = '$';
15321   print_operand_value (scratchbuf + 1, 1, get64 ());
15322   oappend_maybe_intel (scratchbuf);
15323   scratchbuf[0] = '\0';
15324 }
15325
15326 static void
15327 OP_sI (int bytemode, int sizeflag)
15328 {
15329   bfd_signed_vma op;
15330
15331   switch (bytemode)
15332     {
15333     case b_mode:
15334     case b_T_mode:
15335       FETCH_DATA (the_info, codep + 1);
15336       op = *codep++;
15337       if ((op & 0x80) != 0)
15338         op -= 0x100;
15339       if (bytemode == b_T_mode)
15340         {
15341           if (address_mode != mode_64bit
15342               || !((sizeflag & DFLAG) || (rex & REX_W)))
15343             {
15344               /* The operand-size prefix is overridden by a REX prefix.  */
15345               if ((sizeflag & DFLAG) || (rex & REX_W))
15346                 op &= 0xffffffff;
15347               else
15348                 op &= 0xffff;
15349           }
15350         }
15351       else
15352         {
15353           if (!(rex & REX_W))
15354             {
15355               if (sizeflag & DFLAG)
15356                 op &= 0xffffffff;
15357               else
15358                 op &= 0xffff;
15359             }
15360         }
15361       break;
15362     case v_mode:
15363       /* The operand-size prefix is overridden by a REX prefix.  */
15364       if ((sizeflag & DFLAG) || (rex & REX_W))
15365         op = get32s ();
15366       else
15367         op = get16 ();
15368       break;
15369     default:
15370       oappend (INTERNAL_DISASSEMBLER_ERROR);
15371       return;
15372     }
15373
15374   scratchbuf[0] = '$';
15375   print_operand_value (scratchbuf + 1, 1, op);
15376   oappend_maybe_intel (scratchbuf);
15377 }
15378
15379 static void
15380 OP_J (int bytemode, int sizeflag)
15381 {
15382   bfd_vma disp;
15383   bfd_vma mask = -1;
15384   bfd_vma segment = 0;
15385
15386   switch (bytemode)
15387     {
15388     case b_mode:
15389       FETCH_DATA (the_info, codep + 1);
15390       disp = *codep++;
15391       if ((disp & 0x80) != 0)
15392         disp -= 0x100;
15393       break;
15394     case v_mode:
15395       if (isa64 != intel64)
15396     case dqw_mode:
15397         USED_REX (REX_W);
15398       if ((sizeflag & DFLAG)
15399           || (address_mode == mode_64bit
15400               && ((isa64 == intel64 && bytemode != dqw_mode)
15401                   || (rex & REX_W))))
15402         disp = get32s ();
15403       else
15404         {
15405           disp = get16 ();
15406           if ((disp & 0x8000) != 0)
15407             disp -= 0x10000;
15408           /* In 16bit mode, address is wrapped around at 64k within
15409              the same segment.  Otherwise, a data16 prefix on a jump
15410              instruction means that the pc is masked to 16 bits after
15411              the displacement is added!  */
15412           mask = 0xffff;
15413           if ((prefixes & PREFIX_DATA) == 0)
15414             segment = ((start_pc + (codep - start_codep))
15415                        & ~((bfd_vma) 0xffff));
15416         }
15417       if (address_mode != mode_64bit
15418           || (isa64 != intel64 && !(rex & REX_W)))
15419         used_prefixes |= (prefixes & PREFIX_DATA);
15420       break;
15421     default:
15422       oappend (INTERNAL_DISASSEMBLER_ERROR);
15423       return;
15424     }
15425   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15426   set_op (disp, 0);
15427   print_operand_value (scratchbuf, 1, disp);
15428   oappend (scratchbuf);
15429 }
15430
15431 static void
15432 OP_SEG (int bytemode, int sizeflag)
15433 {
15434   if (bytemode == w_mode)
15435     oappend (names_seg[modrm.reg]);
15436   else
15437     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15438 }
15439
15440 static void
15441 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15442 {
15443   int seg, offset;
15444
15445   if (sizeflag & DFLAG)
15446     {
15447       offset = get32 ();
15448       seg = get16 ();
15449     }
15450   else
15451     {
15452       offset = get16 ();
15453       seg = get16 ();
15454     }
15455   used_prefixes |= (prefixes & PREFIX_DATA);
15456   if (intel_syntax)
15457     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15458   else
15459     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15460   oappend (scratchbuf);
15461 }
15462
15463 static void
15464 OP_OFF (int bytemode, int sizeflag)
15465 {
15466   bfd_vma off;
15467
15468   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15469     intel_operand_size (bytemode, sizeflag);
15470   append_seg ();
15471
15472   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15473     off = get32 ();
15474   else
15475     off = get16 ();
15476
15477   if (intel_syntax)
15478     {
15479       if (!active_seg_prefix)
15480         {
15481           oappend (names_seg[ds_reg - es_reg]);
15482           oappend (":");
15483         }
15484     }
15485   print_operand_value (scratchbuf, 1, off);
15486   oappend (scratchbuf);
15487 }
15488
15489 static void
15490 OP_OFF64 (int bytemode, int sizeflag)
15491 {
15492   bfd_vma off;
15493
15494   if (address_mode != mode_64bit
15495       || (prefixes & PREFIX_ADDR))
15496     {
15497       OP_OFF (bytemode, sizeflag);
15498       return;
15499     }
15500
15501   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15502     intel_operand_size (bytemode, sizeflag);
15503   append_seg ();
15504
15505   off = get64 ();
15506
15507   if (intel_syntax)
15508     {
15509       if (!active_seg_prefix)
15510         {
15511           oappend (names_seg[ds_reg - es_reg]);
15512           oappend (":");
15513         }
15514     }
15515   print_operand_value (scratchbuf, 1, off);
15516   oappend (scratchbuf);
15517 }
15518
15519 static void
15520 ptr_reg (int code, int sizeflag)
15521 {
15522   const char *s;
15523
15524   *obufp++ = open_char;
15525   used_prefixes |= (prefixes & PREFIX_ADDR);
15526   if (address_mode == mode_64bit)
15527     {
15528       if (!(sizeflag & AFLAG))
15529         s = names32[code - eAX_reg];
15530       else
15531         s = names64[code - eAX_reg];
15532     }
15533   else if (sizeflag & AFLAG)
15534     s = names32[code - eAX_reg];
15535   else
15536     s = names16[code - eAX_reg];
15537   oappend (s);
15538   *obufp++ = close_char;
15539   *obufp = 0;
15540 }
15541
15542 static void
15543 OP_ESreg (int code, int sizeflag)
15544 {
15545   if (intel_syntax)
15546     {
15547       switch (codep[-1])
15548         {
15549         case 0x6d:      /* insw/insl */
15550           intel_operand_size (z_mode, sizeflag);
15551           break;
15552         case 0xa5:      /* movsw/movsl/movsq */
15553         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15554         case 0xab:      /* stosw/stosl */
15555         case 0xaf:      /* scasw/scasl */
15556           intel_operand_size (v_mode, sizeflag);
15557           break;
15558         default:
15559           intel_operand_size (b_mode, sizeflag);
15560         }
15561     }
15562   oappend_maybe_intel ("%es:");
15563   ptr_reg (code, sizeflag);
15564 }
15565
15566 static void
15567 OP_DSreg (int code, int sizeflag)
15568 {
15569   if (intel_syntax)
15570     {
15571       switch (codep[-1])
15572         {
15573         case 0x6f:      /* outsw/outsl */
15574           intel_operand_size (z_mode, sizeflag);
15575           break;
15576         case 0xa5:      /* movsw/movsl/movsq */
15577         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15578         case 0xad:      /* lodsw/lodsl/lodsq */
15579           intel_operand_size (v_mode, sizeflag);
15580           break;
15581         default:
15582           intel_operand_size (b_mode, sizeflag);
15583         }
15584     }
15585   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15586      default segment register DS is printed.  */
15587   if (!active_seg_prefix)
15588     active_seg_prefix = PREFIX_DS;
15589   append_seg ();
15590   ptr_reg (code, sizeflag);
15591 }
15592
15593 static void
15594 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15595 {
15596   int add;
15597   if (rex & REX_R)
15598     {
15599       USED_REX (REX_R);
15600       add = 8;
15601     }
15602   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15603     {
15604       all_prefixes[last_lock_prefix] = 0;
15605       used_prefixes |= PREFIX_LOCK;
15606       add = 8;
15607     }
15608   else
15609     add = 0;
15610   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15611   oappend_maybe_intel (scratchbuf);
15612 }
15613
15614 static void
15615 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15616 {
15617   int add;
15618   USED_REX (REX_R);
15619   if (rex & REX_R)
15620     add = 8;
15621   else
15622     add = 0;
15623   if (intel_syntax)
15624     sprintf (scratchbuf, "db%d", modrm.reg + add);
15625   else
15626     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15627   oappend (scratchbuf);
15628 }
15629
15630 static void
15631 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15632 {
15633   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15634   oappend_maybe_intel (scratchbuf);
15635 }
15636
15637 static void
15638 OP_R (int bytemode, int sizeflag)
15639 {
15640   /* Skip mod/rm byte.  */
15641   MODRM_CHECK;
15642   codep++;
15643   OP_E_register (bytemode, sizeflag);
15644 }
15645
15646 static void
15647 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15648 {
15649   int reg = modrm.reg;
15650   const char **names;
15651
15652   used_prefixes |= (prefixes & PREFIX_DATA);
15653   if (prefixes & PREFIX_DATA)
15654     {
15655       names = names_xmm;
15656       USED_REX (REX_R);
15657       if (rex & REX_R)
15658         reg += 8;
15659     }
15660   else
15661     names = names_mm;
15662   oappend (names[reg]);
15663 }
15664
15665 static void
15666 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15667 {
15668   int reg = modrm.reg;
15669   const char **names;
15670
15671   USED_REX (REX_R);
15672   if (rex & REX_R)
15673     reg += 8;
15674   if (vex.evex)
15675     {
15676       if (!vex.r)
15677         reg += 16;
15678     }
15679
15680   if (need_vex
15681       && bytemode != xmm_mode
15682       && bytemode != xmmq_mode
15683       && bytemode != evex_half_bcst_xmmq_mode
15684       && bytemode != ymm_mode
15685       && bytemode != tmm_mode
15686       && bytemode != scalar_mode)
15687     {
15688       switch (vex.length)
15689         {
15690         case 128:
15691           names = names_xmm;
15692           break;
15693         case 256:
15694           if (vex.w
15695               || (bytemode != vex_vsib_q_w_dq_mode
15696                   && bytemode != vex_vsib_q_w_d_mode))
15697             names = names_ymm;
15698           else
15699             names = names_xmm;
15700           break;
15701         case 512:
15702           names = names_zmm;
15703           break;
15704         default:
15705           abort ();
15706         }
15707     }
15708   else if (bytemode == xmmq_mode
15709            || bytemode == evex_half_bcst_xmmq_mode)
15710     {
15711       switch (vex.length)
15712         {
15713         case 128:
15714         case 256:
15715           names = names_xmm;
15716           break;
15717         case 512:
15718           names = names_ymm;
15719           break;
15720         default:
15721           abort ();
15722         }
15723     }
15724   else if (bytemode == tmm_mode)
15725     {
15726       modrm.reg = reg;
15727       if (reg >= 8)
15728         {
15729           oappend ("(bad)");
15730           return;
15731         }
15732       names = names_tmm;
15733     }
15734   else if (bytemode == ymm_mode)
15735     names = names_ymm;
15736   else
15737     names = names_xmm;
15738   oappend (names[reg]);
15739 }
15740
15741 static void
15742 OP_EM (int bytemode, int sizeflag)
15743 {
15744   int reg;
15745   const char **names;
15746
15747   if (modrm.mod != 3)
15748     {
15749       if (intel_syntax
15750           && (bytemode == v_mode || bytemode == v_swap_mode))
15751         {
15752           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15753           used_prefixes |= (prefixes & PREFIX_DATA);
15754         }
15755       OP_E (bytemode, sizeflag);
15756       return;
15757     }
15758
15759   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15760     swap_operand ();
15761
15762   /* Skip mod/rm byte.  */
15763   MODRM_CHECK;
15764   codep++;
15765   used_prefixes |= (prefixes & PREFIX_DATA);
15766   reg = modrm.rm;
15767   if (prefixes & PREFIX_DATA)
15768     {
15769       names = names_xmm;
15770       USED_REX (REX_B);
15771       if (rex & REX_B)
15772         reg += 8;
15773     }
15774   else
15775     names = names_mm;
15776   oappend (names[reg]);
15777 }
15778
15779 /* cvt* are the only instructions in sse2 which have
15780    both SSE and MMX operands and also have 0x66 prefix
15781    in their opcode. 0x66 was originally used to differentiate
15782    between SSE and MMX instruction(operands). So we have to handle the
15783    cvt* separately using OP_EMC and OP_MXC */
15784 static void
15785 OP_EMC (int bytemode, int sizeflag)
15786 {
15787   if (modrm.mod != 3)
15788     {
15789       if (intel_syntax && bytemode == v_mode)
15790         {
15791           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15792           used_prefixes |= (prefixes & PREFIX_DATA);
15793         }
15794       OP_E (bytemode, sizeflag);
15795       return;
15796     }
15797
15798   /* Skip mod/rm byte.  */
15799   MODRM_CHECK;
15800   codep++;
15801   used_prefixes |= (prefixes & PREFIX_DATA);
15802   oappend (names_mm[modrm.rm]);
15803 }
15804
15805 static void
15806 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15807 {
15808   used_prefixes |= (prefixes & PREFIX_DATA);
15809   oappend (names_mm[modrm.reg]);
15810 }
15811
15812 static void
15813 OP_EX (int bytemode, int sizeflag)
15814 {
15815   int reg;
15816   const char **names;
15817
15818   /* Skip mod/rm byte.  */
15819   MODRM_CHECK;
15820   codep++;
15821
15822   if (modrm.mod != 3)
15823     {
15824       OP_E_memory (bytemode, sizeflag);
15825       return;
15826     }
15827
15828   reg = modrm.rm;
15829   USED_REX (REX_B);
15830   if (rex & REX_B)
15831     reg += 8;
15832   if (vex.evex)
15833     {
15834       USED_REX (REX_X);
15835       if ((rex & REX_X))
15836         reg += 16;
15837     }
15838
15839   if ((sizeflag & SUFFIX_ALWAYS)
15840       && (bytemode == x_swap_mode
15841           || bytemode == d_swap_mode
15842           || bytemode == q_swap_mode))
15843     swap_operand ();
15844
15845   if (need_vex
15846       && bytemode != xmm_mode
15847       && bytemode != xmmdw_mode
15848       && bytemode != xmmqd_mode
15849       && bytemode != xmm_mb_mode
15850       && bytemode != xmm_mw_mode
15851       && bytemode != xmm_md_mode
15852       && bytemode != xmm_mq_mode
15853       && bytemode != xmmq_mode
15854       && bytemode != evex_half_bcst_xmmq_mode
15855       && bytemode != ymm_mode
15856       && bytemode != tmm_mode
15857       && bytemode != vex_scalar_w_dq_mode)
15858     {
15859       switch (vex.length)
15860         {
15861         case 128:
15862           names = names_xmm;
15863           break;
15864         case 256:
15865           names = names_ymm;
15866           break;
15867         case 512:
15868           names = names_zmm;
15869           break;
15870         default:
15871           abort ();
15872         }
15873     }
15874   else if (bytemode == xmmq_mode
15875            || bytemode == evex_half_bcst_xmmq_mode)
15876     {
15877       switch (vex.length)
15878         {
15879         case 128:
15880         case 256:
15881           names = names_xmm;
15882           break;
15883         case 512:
15884           names = names_ymm;
15885           break;
15886         default:
15887           abort ();
15888         }
15889     }
15890   else if (bytemode == tmm_mode)
15891     {
15892       modrm.rm = reg;
15893       if (reg >= 8)
15894         {
15895           oappend ("(bad)");
15896           return;
15897         }
15898       names = names_tmm;
15899     }
15900   else if (bytemode == ymm_mode)
15901     names = names_ymm;
15902   else
15903     names = names_xmm;
15904   oappend (names[reg]);
15905 }
15906
15907 static void
15908 OP_MS (int bytemode, int sizeflag)
15909 {
15910   if (modrm.mod == 3)
15911     OP_EM (bytemode, sizeflag);
15912   else
15913     BadOp ();
15914 }
15915
15916 static void
15917 OP_XS (int bytemode, int sizeflag)
15918 {
15919   if (modrm.mod == 3)
15920     OP_EX (bytemode, sizeflag);
15921   else
15922     BadOp ();
15923 }
15924
15925 static void
15926 OP_M (int bytemode, int sizeflag)
15927 {
15928   if (modrm.mod == 3)
15929     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15930     BadOp ();
15931   else
15932     OP_E (bytemode, sizeflag);
15933 }
15934
15935 static void
15936 OP_0f07 (int bytemode, int sizeflag)
15937 {
15938   if (modrm.mod != 3 || modrm.rm != 0)
15939     BadOp ();
15940   else
15941     OP_E (bytemode, sizeflag);
15942 }
15943
15944 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15945    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15946
15947 static void
15948 NOP_Fixup1 (int bytemode, int sizeflag)
15949 {
15950   if ((prefixes & PREFIX_DATA) != 0
15951       || (rex != 0
15952           && rex != 0x48
15953           && address_mode == mode_64bit))
15954     OP_REG (bytemode, sizeflag);
15955   else
15956     strcpy (obuf, "nop");
15957 }
15958
15959 static void
15960 NOP_Fixup2 (int bytemode, int sizeflag)
15961 {
15962   if ((prefixes & PREFIX_DATA) != 0
15963       || (rex != 0
15964           && rex != 0x48
15965           && address_mode == mode_64bit))
15966     OP_IMREG (bytemode, sizeflag);
15967 }
15968
15969 static const char *const Suffix3DNow[] = {
15970 /* 00 */        NULL,           NULL,           NULL,           NULL,
15971 /* 04 */        NULL,           NULL,           NULL,           NULL,
15972 /* 08 */        NULL,           NULL,           NULL,           NULL,
15973 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15974 /* 10 */        NULL,           NULL,           NULL,           NULL,
15975 /* 14 */        NULL,           NULL,           NULL,           NULL,
15976 /* 18 */        NULL,           NULL,           NULL,           NULL,
15977 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15978 /* 20 */        NULL,           NULL,           NULL,           NULL,
15979 /* 24 */        NULL,           NULL,           NULL,           NULL,
15980 /* 28 */        NULL,           NULL,           NULL,           NULL,
15981 /* 2C */        NULL,           NULL,           NULL,           NULL,
15982 /* 30 */        NULL,           NULL,           NULL,           NULL,
15983 /* 34 */        NULL,           NULL,           NULL,           NULL,
15984 /* 38 */        NULL,           NULL,           NULL,           NULL,
15985 /* 3C */        NULL,           NULL,           NULL,           NULL,
15986 /* 40 */        NULL,           NULL,           NULL,           NULL,
15987 /* 44 */        NULL,           NULL,           NULL,           NULL,
15988 /* 48 */        NULL,           NULL,           NULL,           NULL,
15989 /* 4C */        NULL,           NULL,           NULL,           NULL,
15990 /* 50 */        NULL,           NULL,           NULL,           NULL,
15991 /* 54 */        NULL,           NULL,           NULL,           NULL,
15992 /* 58 */        NULL,           NULL,           NULL,           NULL,
15993 /* 5C */        NULL,           NULL,           NULL,           NULL,
15994 /* 60 */        NULL,           NULL,           NULL,           NULL,
15995 /* 64 */        NULL,           NULL,           NULL,           NULL,
15996 /* 68 */        NULL,           NULL,           NULL,           NULL,
15997 /* 6C */        NULL,           NULL,           NULL,           NULL,
15998 /* 70 */        NULL,           NULL,           NULL,           NULL,
15999 /* 74 */        NULL,           NULL,           NULL,           NULL,
16000 /* 78 */        NULL,           NULL,           NULL,           NULL,
16001 /* 7C */        NULL,           NULL,           NULL,           NULL,
16002 /* 80 */        NULL,           NULL,           NULL,           NULL,
16003 /* 84 */        NULL,           NULL,           NULL,           NULL,
16004 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16005 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16006 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16007 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16008 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16009 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16010 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16011 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16012 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16013 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16014 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16015 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16016 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16017 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16018 /* C0 */        NULL,           NULL,           NULL,           NULL,
16019 /* C4 */        NULL,           NULL,           NULL,           NULL,
16020 /* C8 */        NULL,           NULL,           NULL,           NULL,
16021 /* CC */        NULL,           NULL,           NULL,           NULL,
16022 /* D0 */        NULL,           NULL,           NULL,           NULL,
16023 /* D4 */        NULL,           NULL,           NULL,           NULL,
16024 /* D8 */        NULL,           NULL,           NULL,           NULL,
16025 /* DC */        NULL,           NULL,           NULL,           NULL,
16026 /* E0 */        NULL,           NULL,           NULL,           NULL,
16027 /* E4 */        NULL,           NULL,           NULL,           NULL,
16028 /* E8 */        NULL,           NULL,           NULL,           NULL,
16029 /* EC */        NULL,           NULL,           NULL,           NULL,
16030 /* F0 */        NULL,           NULL,           NULL,           NULL,
16031 /* F4 */        NULL,           NULL,           NULL,           NULL,
16032 /* F8 */        NULL,           NULL,           NULL,           NULL,
16033 /* FC */        NULL,           NULL,           NULL,           NULL,
16034 };
16035
16036 static void
16037 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16038 {
16039   const char *mnemonic;
16040
16041   FETCH_DATA (the_info, codep + 1);
16042   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16043      place where an 8-bit immediate would normally go.  ie. the last
16044      byte of the instruction.  */
16045   obufp = mnemonicendp;
16046   mnemonic = Suffix3DNow[*codep++ & 0xff];
16047   if (mnemonic)
16048     oappend (mnemonic);
16049   else
16050     {
16051       /* Since a variable sized modrm/sib chunk is between the start
16052          of the opcode (0x0f0f) and the opcode suffix, we need to do
16053          all the modrm processing first, and don't know until now that
16054          we have a bad opcode.  This necessitates some cleaning up.  */
16055       op_out[0][0] = '\0';
16056       op_out[1][0] = '\0';
16057       BadOp ();
16058     }
16059   mnemonicendp = obufp;
16060 }
16061
16062 static const struct op simd_cmp_op[] =
16063 {
16064   { STRING_COMMA_LEN ("eq") },
16065   { STRING_COMMA_LEN ("lt") },
16066   { STRING_COMMA_LEN ("le") },
16067   { STRING_COMMA_LEN ("unord") },
16068   { STRING_COMMA_LEN ("neq") },
16069   { STRING_COMMA_LEN ("nlt") },
16070   { STRING_COMMA_LEN ("nle") },
16071   { STRING_COMMA_LEN ("ord") }
16072 };
16073
16074 static const struct op vex_cmp_op[] =
16075 {
16076   { STRING_COMMA_LEN ("eq_uq") },
16077   { STRING_COMMA_LEN ("nge") },
16078   { STRING_COMMA_LEN ("ngt") },
16079   { STRING_COMMA_LEN ("false") },
16080   { STRING_COMMA_LEN ("neq_oq") },
16081   { STRING_COMMA_LEN ("ge") },
16082   { STRING_COMMA_LEN ("gt") },
16083   { STRING_COMMA_LEN ("true") },
16084   { STRING_COMMA_LEN ("eq_os") },
16085   { STRING_COMMA_LEN ("lt_oq") },
16086   { STRING_COMMA_LEN ("le_oq") },
16087   { STRING_COMMA_LEN ("unord_s") },
16088   { STRING_COMMA_LEN ("neq_us") },
16089   { STRING_COMMA_LEN ("nlt_uq") },
16090   { STRING_COMMA_LEN ("nle_uq") },
16091   { STRING_COMMA_LEN ("ord_s") },
16092   { STRING_COMMA_LEN ("eq_us") },
16093   { STRING_COMMA_LEN ("nge_uq") },
16094   { STRING_COMMA_LEN ("ngt_uq") },
16095   { STRING_COMMA_LEN ("false_os") },
16096   { STRING_COMMA_LEN ("neq_os") },
16097   { STRING_COMMA_LEN ("ge_oq") },
16098   { STRING_COMMA_LEN ("gt_oq") },
16099   { STRING_COMMA_LEN ("true_us") },
16100 };
16101
16102 static void
16103 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16104 {
16105   unsigned int cmp_type;
16106
16107   FETCH_DATA (the_info, codep + 1);
16108   cmp_type = *codep++ & 0xff;
16109   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16110     {
16111       char suffix [3];
16112       char *p = mnemonicendp - 2;
16113       suffix[0] = p[0];
16114       suffix[1] = p[1];
16115       suffix[2] = '\0';
16116       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16117       mnemonicendp += simd_cmp_op[cmp_type].len;
16118     }
16119   else if (need_vex
16120            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
16121     {
16122       char suffix [3];
16123       char *p = mnemonicendp - 2;
16124       suffix[0] = p[0];
16125       suffix[1] = p[1];
16126       suffix[2] = '\0';
16127       cmp_type -= ARRAY_SIZE (simd_cmp_op);
16128       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16129       mnemonicendp += vex_cmp_op[cmp_type].len;
16130     }
16131   else
16132     {
16133       /* We have a reserved extension byte.  Output it directly.  */
16134       scratchbuf[0] = '$';
16135       print_operand_value (scratchbuf + 1, 1, cmp_type);
16136       oappend_maybe_intel (scratchbuf);
16137       scratchbuf[0] = '\0';
16138     }
16139 }
16140
16141 static void
16142 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16143 {
16144   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16145   if (!intel_syntax)
16146     {
16147       strcpy (op_out[0], names32[0]);
16148       strcpy (op_out[1], names32[1]);
16149       if (bytemode == eBX_reg)
16150         strcpy (op_out[2], names32[3]);
16151       two_source_ops = 1;
16152     }
16153   /* Skip mod/rm byte.  */
16154   MODRM_CHECK;
16155   codep++;
16156 }
16157
16158 static void
16159 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16160             int sizeflag ATTRIBUTE_UNUSED)
16161 {
16162   /* monitor %{e,r,}ax,%ecx,%edx"  */
16163   if (!intel_syntax)
16164     {
16165       const char **names = (address_mode == mode_64bit
16166                             ? names64 : names32);
16167
16168       if (prefixes & PREFIX_ADDR)
16169         {
16170           /* Remove "addr16/addr32".  */
16171           all_prefixes[last_addr_prefix] = 0;
16172           names = (address_mode != mode_32bit
16173                    ? names32 : names16);
16174           used_prefixes |= PREFIX_ADDR;
16175         }
16176       else if (address_mode == mode_16bit)
16177         names = names16;
16178       strcpy (op_out[0], names[0]);
16179       strcpy (op_out[1], names32[1]);
16180       strcpy (op_out[2], names32[2]);
16181       two_source_ops = 1;
16182     }
16183   /* Skip mod/rm byte.  */
16184   MODRM_CHECK;
16185   codep++;
16186 }
16187
16188 static void
16189 BadOp (void)
16190 {
16191   /* Throw away prefixes and 1st. opcode byte.  */
16192   codep = insn_codep + 1;
16193   oappend ("(bad)");
16194 }
16195
16196 static void
16197 REP_Fixup (int bytemode, int sizeflag)
16198 {
16199   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16200      lods and stos.  */
16201   if (prefixes & PREFIX_REPZ)
16202     all_prefixes[last_repz_prefix] = REP_PREFIX;
16203
16204   switch (bytemode)
16205     {
16206     case al_reg:
16207     case eAX_reg:
16208     case indir_dx_reg:
16209       OP_IMREG (bytemode, sizeflag);
16210       break;
16211     case eDI_reg:
16212       OP_ESreg (bytemode, sizeflag);
16213       break;
16214     case eSI_reg:
16215       OP_DSreg (bytemode, sizeflag);
16216       break;
16217     default:
16218       abort ();
16219       break;
16220     }
16221 }
16222
16223 static void
16224 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16225 {
16226   if ( isa64 != amd64 )
16227     return;
16228
16229   obufp = obuf;
16230   BadOp ();
16231   mnemonicendp = obufp;
16232   ++codep;
16233 }
16234
16235 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16236    "bnd".  */
16237
16238 static void
16239 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16240 {
16241   if (prefixes & PREFIX_REPNZ)
16242     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16243 }
16244
16245 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16246    "notrack".  */
16247
16248 static void
16249 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16250                int sizeflag ATTRIBUTE_UNUSED)
16251 {
16252   if (active_seg_prefix == PREFIX_DS
16253       && (address_mode != mode_64bit || last_data_prefix < 0))
16254     {
16255       /* NOTRACK prefix is only valid on indirect branch instructions.
16256          NB: DATA prefix is unsupported for Intel64.  */
16257       active_seg_prefix = 0;
16258       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16259     }
16260 }
16261
16262 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16263    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16264  */
16265
16266 static void
16267 HLE_Fixup1 (int bytemode, int sizeflag)
16268 {
16269   if (modrm.mod != 3
16270       && (prefixes & PREFIX_LOCK) != 0)
16271     {
16272       if (prefixes & PREFIX_REPZ)
16273         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16274       if (prefixes & PREFIX_REPNZ)
16275         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16276     }
16277
16278   OP_E (bytemode, sizeflag);
16279 }
16280
16281 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16282    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16283  */
16284
16285 static void
16286 HLE_Fixup2 (int bytemode, int sizeflag)
16287 {
16288   if (modrm.mod != 3)
16289     {
16290       if (prefixes & PREFIX_REPZ)
16291         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16292       if (prefixes & PREFIX_REPNZ)
16293         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16294     }
16295
16296   OP_E (bytemode, sizeflag);
16297 }
16298
16299 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16300    "xrelease" for memory operand.  No check for LOCK prefix.   */
16301
16302 static void
16303 HLE_Fixup3 (int bytemode, int sizeflag)
16304 {
16305   if (modrm.mod != 3
16306       && last_repz_prefix > last_repnz_prefix
16307       && (prefixes & PREFIX_REPZ) != 0)
16308     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16309
16310   OP_E (bytemode, sizeflag);
16311 }
16312
16313 static void
16314 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16315 {
16316   USED_REX (REX_W);
16317   if (rex & REX_W)
16318     {
16319       /* Change cmpxchg8b to cmpxchg16b.  */
16320       char *p = mnemonicendp - 2;
16321       mnemonicendp = stpcpy (p, "16b");
16322       bytemode = o_mode;
16323     }
16324   else if ((prefixes & PREFIX_LOCK) != 0)
16325     {
16326       if (prefixes & PREFIX_REPZ)
16327         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16328       if (prefixes & PREFIX_REPNZ)
16329         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16330     }
16331
16332   OP_M (bytemode, sizeflag);
16333 }
16334
16335 static void
16336 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16337 {
16338   const char **names;
16339
16340   if (need_vex)
16341     {
16342       switch (vex.length)
16343         {
16344         case 128:
16345           names = names_xmm;
16346           break;
16347         case 256:
16348           names = names_ymm;
16349           break;
16350         default:
16351           abort ();
16352         }
16353     }
16354   else
16355     names = names_xmm;
16356   oappend (names[reg]);
16357 }
16358
16359 static void
16360 FXSAVE_Fixup (int bytemode, int sizeflag)
16361 {
16362   /* Add proper suffix to "fxsave" and "fxrstor".  */
16363   USED_REX (REX_W);
16364   if (rex & REX_W)
16365     {
16366       char *p = mnemonicendp;
16367       *p++ = '6';
16368       *p++ = '4';
16369       *p = '\0';
16370       mnemonicendp = p;
16371     }
16372   OP_M (bytemode, sizeflag);
16373 }
16374
16375 /* Display the destination register operand for instructions with
16376    VEX. */
16377
16378 static void
16379 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16380 {
16381   int reg;
16382   const char **names;
16383
16384   if (!need_vex)
16385     abort ();
16386
16387   reg = vex.register_specifier;
16388   vex.register_specifier = 0;
16389   if (address_mode != mode_64bit)
16390     reg &= 7;
16391   else if (vex.evex && !vex.v)
16392     reg += 16;
16393
16394   if (bytemode == vex_scalar_mode)
16395     {
16396       oappend (names_xmm[reg]);
16397       return;
16398     }
16399
16400   if (bytemode == tmm_mode)
16401     {
16402       /* All 3 TMM registers must be distinct.  */
16403       if (reg >= 8)
16404         oappend ("(bad)");
16405       else
16406         {
16407           /* This must be the 3rd operand.  */
16408           if (obufp != op_out[2])
16409             abort ();
16410           oappend (names_tmm[reg]);
16411           if (reg == modrm.reg || reg == modrm.rm)
16412             strcpy (obufp, "/(bad)");
16413         }
16414
16415       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16416         {
16417           if (modrm.reg <= 8
16418               && (modrm.reg == modrm.rm || modrm.reg == reg))
16419             strcat (op_out[0], "/(bad)");
16420           if (modrm.rm <= 8
16421               && (modrm.rm == modrm.reg || modrm.rm == reg))
16422             strcat (op_out[1], "/(bad)");
16423         }
16424
16425       return;
16426     }
16427
16428   switch (vex.length)
16429     {
16430     case 128:
16431       switch (bytemode)
16432         {
16433         case vex_mode:
16434         case vex_vsib_q_w_dq_mode:
16435         case vex_vsib_q_w_d_mode:
16436           names = names_xmm;
16437           break;
16438         case dq_mode:
16439           if (rex & REX_W)
16440             names = names64;
16441           else
16442             names = names32;
16443           break;
16444         case mask_bd_mode:
16445         case mask_mode:
16446           if (reg > 0x7)
16447             {
16448               oappend ("(bad)");
16449               return;
16450             }
16451           names = names_mask;
16452           break;
16453         default:
16454           abort ();
16455           return;
16456         }
16457       break;
16458     case 256:
16459       switch (bytemode)
16460         {
16461         case vex_mode:
16462           names = names_ymm;
16463           break;
16464         case vex_vsib_q_w_dq_mode:
16465         case vex_vsib_q_w_d_mode:
16466           names = vex.w ? names_ymm : names_xmm;
16467           break;
16468         case mask_bd_mode:
16469         case mask_mode:
16470           if (reg > 0x7)
16471             {
16472               oappend ("(bad)");
16473               return;
16474             }
16475           names = names_mask;
16476           break;
16477         default:
16478           /* See PR binutils/20893 for a reproducer.  */
16479           oappend ("(bad)");
16480           return;
16481         }
16482       break;
16483     case 512:
16484       names = names_zmm;
16485       break;
16486     default:
16487       abort ();
16488       break;
16489     }
16490   oappend (names[reg]);
16491 }
16492
16493 static void
16494 OP_VexR (int bytemode, int sizeflag)
16495 {
16496   if (modrm.mod == 3)
16497     OP_VEX (bytemode, sizeflag);
16498 }
16499
16500 static void
16501 OP_VexW (int bytemode, int sizeflag)
16502 {
16503   OP_VEX (bytemode, sizeflag);
16504
16505   if (vex.w)
16506     {
16507       /* Swap 2nd and 3rd operands.  */
16508       strcpy (scratchbuf, op_out[2]);
16509       strcpy (op_out[2], op_out[1]);
16510       strcpy (op_out[1], scratchbuf);
16511     }
16512 }
16513
16514 static void
16515 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16516 {
16517   int reg;
16518   const char **names = names_xmm;
16519
16520   FETCH_DATA (the_info, codep + 1);
16521   reg = *codep++;
16522
16523   if (bytemode != x_mode && bytemode != scalar_mode)
16524     abort ();
16525
16526   reg >>= 4;
16527   if (address_mode != mode_64bit)
16528     reg &= 7;
16529
16530   if (bytemode == x_mode && vex.length == 256)
16531     names = names_ymm;
16532
16533   oappend (names[reg]);
16534
16535   if (vex.w)
16536     {
16537       /* Swap 3rd and 4th operands.  */
16538       strcpy (scratchbuf, op_out[3]);
16539       strcpy (op_out[3], op_out[2]);
16540       strcpy (op_out[2], scratchbuf);
16541     }
16542 }
16543
16544 static void
16545 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16546           int sizeflag ATTRIBUTE_UNUSED)
16547 {
16548   scratchbuf[0] = '$';
16549   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16550   oappend_maybe_intel (scratchbuf);
16551 }
16552
16553 static void
16554 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16555              int sizeflag ATTRIBUTE_UNUSED)
16556 {
16557   unsigned int cmp_type;
16558
16559   if (!vex.evex)
16560     abort ();
16561
16562   FETCH_DATA (the_info, codep + 1);
16563   cmp_type = *codep++ & 0xff;
16564   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16565      If it's the case, print suffix, otherwise - print the immediate.  */
16566   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16567       && cmp_type != 3
16568       && cmp_type != 7)
16569     {
16570       char suffix [3];
16571       char *p = mnemonicendp - 2;
16572
16573       /* vpcmp* can have both one- and two-lettered suffix.  */
16574       if (p[0] == 'p')
16575         {
16576           p++;
16577           suffix[0] = p[0];
16578           suffix[1] = '\0';
16579         }
16580       else
16581         {
16582           suffix[0] = p[0];
16583           suffix[1] = p[1];
16584           suffix[2] = '\0';
16585         }
16586
16587       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16588       mnemonicendp += simd_cmp_op[cmp_type].len;
16589     }
16590   else
16591     {
16592       /* We have a reserved extension byte.  Output it directly.  */
16593       scratchbuf[0] = '$';
16594       print_operand_value (scratchbuf + 1, 1, cmp_type);
16595       oappend_maybe_intel (scratchbuf);
16596       scratchbuf[0] = '\0';
16597     }
16598 }
16599
16600 static const struct op xop_cmp_op[] =
16601 {
16602   { STRING_COMMA_LEN ("lt") },
16603   { STRING_COMMA_LEN ("le") },
16604   { STRING_COMMA_LEN ("gt") },
16605   { STRING_COMMA_LEN ("ge") },
16606   { STRING_COMMA_LEN ("eq") },
16607   { STRING_COMMA_LEN ("neq") },
16608   { STRING_COMMA_LEN ("false") },
16609   { STRING_COMMA_LEN ("true") }
16610 };
16611
16612 static void
16613 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16614              int sizeflag ATTRIBUTE_UNUSED)
16615 {
16616   unsigned int cmp_type;
16617
16618   FETCH_DATA (the_info, codep + 1);
16619   cmp_type = *codep++ & 0xff;
16620   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16621     {
16622       char suffix[3];
16623       char *p = mnemonicendp - 2;
16624
16625       /* vpcom* can have both one- and two-lettered suffix.  */
16626       if (p[0] == 'm')
16627         {
16628           p++;
16629           suffix[0] = p[0];
16630           suffix[1] = '\0';
16631         }
16632       else
16633         {
16634           suffix[0] = p[0];
16635           suffix[1] = p[1];
16636           suffix[2] = '\0';
16637         }
16638
16639       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16640       mnemonicendp += xop_cmp_op[cmp_type].len;
16641     }
16642   else
16643     {
16644       /* We have a reserved extension byte.  Output it directly.  */
16645       scratchbuf[0] = '$';
16646       print_operand_value (scratchbuf + 1, 1, cmp_type);
16647       oappend_maybe_intel (scratchbuf);
16648       scratchbuf[0] = '\0';
16649     }
16650 }
16651
16652 static const struct op pclmul_op[] =
16653 {
16654   { STRING_COMMA_LEN ("lql") },
16655   { STRING_COMMA_LEN ("hql") },
16656   { STRING_COMMA_LEN ("lqh") },
16657   { STRING_COMMA_LEN ("hqh") }
16658 };
16659
16660 static void
16661 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16662               int sizeflag ATTRIBUTE_UNUSED)
16663 {
16664   unsigned int pclmul_type;
16665
16666   FETCH_DATA (the_info, codep + 1);
16667   pclmul_type = *codep++ & 0xff;
16668   switch (pclmul_type)
16669     {
16670     case 0x10:
16671       pclmul_type = 2;
16672       break;
16673     case 0x11:
16674       pclmul_type = 3;
16675       break;
16676     default:
16677       break;
16678     }
16679   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16680     {
16681       char suffix [4];
16682       char *p = mnemonicendp - 3;
16683       suffix[0] = p[0];
16684       suffix[1] = p[1];
16685       suffix[2] = p[2];
16686       suffix[3] = '\0';
16687       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16688       mnemonicendp += pclmul_op[pclmul_type].len;
16689     }
16690   else
16691     {
16692       /* We have a reserved extension byte.  Output it directly.  */
16693       scratchbuf[0] = '$';
16694       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16695       oappend_maybe_intel (scratchbuf);
16696       scratchbuf[0] = '\0';
16697     }
16698 }
16699
16700 static void
16701 MOVSXD_Fixup (int bytemode, int sizeflag)
16702 {
16703   /* Add proper suffix to "movsxd".  */
16704   char *p = mnemonicendp;
16705
16706   switch (bytemode)
16707     {
16708     case movsxd_mode:
16709       if (intel_syntax)
16710         {
16711           *p++ = 'x';
16712           *p++ = 'd';
16713           goto skip;
16714         }
16715
16716       USED_REX (REX_W);
16717       if (rex & REX_W)
16718         {
16719           *p++ = 'l';
16720           *p++ = 'q';
16721         }
16722       else
16723         {
16724           *p++ = 'x';
16725           *p++ = 'd';
16726         }
16727       break;
16728     default:
16729       oappend (INTERNAL_DISASSEMBLER_ERROR);
16730       break;
16731     }
16732
16733  skip:
16734   mnemonicendp = p;
16735   *p = '\0';
16736   OP_E (bytemode, sizeflag);
16737 }
16738
16739 static void
16740 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16741 {
16742   if (!vex.evex
16743       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16744     abort ();
16745
16746   USED_REX (REX_R);
16747   if ((rex & REX_R) != 0 || !vex.r)
16748     {
16749       BadOp ();
16750       return;
16751     }
16752
16753   oappend (names_mask [modrm.reg]);
16754 }
16755
16756 static void
16757 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16758 {
16759   if (modrm.mod == 3 && vex.b)
16760     switch (bytemode)
16761       {
16762       case evex_rounding_64_mode:
16763         if (address_mode != mode_64bit)
16764           {
16765             oappend ("(bad)");
16766             break;
16767           }
16768         /* Fall through.  */
16769       case evex_rounding_mode:
16770         oappend (names_rounding[vex.ll]);
16771         break;
16772       case evex_sae_mode:
16773         oappend ("{sae}");
16774         break;
16775       default:
16776         abort ();
16777         break;
16778       }
16779 }