opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 389 #define EXq { OP_EX, q_mode }
 390 #define EXqScalar { OP_EX, q_scalar_mode }
 391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 392 #define EXqS { OP_EX, q_swap_mode }
 393 #define EXx { OP_EX, x_mode }
 394 #define EXxS { OP_EX, x_swap_mode }
 395 #define EXxmm { OP_EX, xmm_mode }
 396 #define EXymm { OP_EX, ymm_mode }
 397 #define EXxmmq { OP_EX, xmmq_mode }
 398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 401 #define EXxmm_md { OP_EX, xmm_md_mode }
 402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440 #define VPCOM { VPCOM_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* operand size depends on address prefix */
 500   va_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 560   v_bndmk_mode,
 561   /* operand size depends on REX prefixes.  */
 562   dq_mode,
 563   /* registers like dq_mode, memory like w_mode.  */
 564   dqw_mode,
 565   /* bounds operand */
 566   bnd_mode,
 567   /* bounds operand with operand swapped */
 568   bnd_swap_mode,
 569   /* 4- or 6-byte pointer operand */
 570   f_mode,
 571   const_1_mode,
 572   /* v_mode for indirect branch opcodes.  */
 573   indir_v_mode,
 574   /* v_mode for stack-related opcodes.  */
 575   stack_v_mode,
 576   /* non-quad operand size depends on prefixes */
 577   z_mode,
 578   /* 16-byte operand */
 579   o_mode,
 580   /* registers like dq_mode, memory like b_mode.  */
 581   dqb_mode,
 582   /* registers like d_mode, memory like b_mode.  */
 583   db_mode,
 584   /* registers like d_mode, memory like w_mode.  */
 585   dw_mode,
 586   /* registers like dq_mode, memory like d_mode.  */
 587   dqd_mode,
 588   /* normal vex mode */
 589   vex_mode,
 590   /* 128bit vex mode */
 591   vex128_mode,
 592   /* 256bit vex mode */
 593   vex256_mode,
 594   /* operand size depends on the VEX.W bit.  */
 595   vex_w_dq_mode,
 596
 597   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 598   vex_vsib_d_w_dq_mode,
 599   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 600   vex_vsib_d_w_d_mode,
 601   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 602   vex_vsib_q_w_dq_mode,
 603   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 604   vex_vsib_q_w_d_mode,
 605
 606   /* scalar, ignore vector length.  */
 607   scalar_mode,
 608   /* like b_mode, ignore vector length.  */
 609   b_scalar_mode,
 610   /* like w_mode, ignore vector length.  */
 611   w_scalar_mode,
 612   /* like d_mode, ignore vector length.  */
 613   d_scalar_mode,
 614   /* like d_swap_mode, ignore vector length.  */
 615   d_scalar_swap_mode,
 616   /* like q_mode, ignore vector length.  */
 617   q_scalar_mode,
 618   /* like q_swap_mode, ignore vector length.  */
 619   q_scalar_swap_mode,
 620   /* like vex_mode, ignore vector length.  */
 621   vex_scalar_mode,
 622   /* like vex_w_dq_mode, ignore vector length.  */
 623   vex_scalar_w_dq_mode,
 624
 625   /* Static rounding.  */
 626   evex_rounding_mode,
 627   /* Static rounding, 64-bit mode only.  */
 628   evex_rounding_64_mode,
 629   /* Supress all exceptions.  */
 630   evex_sae_mode,
 631
 632   /* Mask register operand.  */
 633   mask_mode,
 634   /* Mask register operand.  */
 635   mask_bd_mode,
 636
 637   es_reg,
 638   cs_reg,
 639   ss_reg,
 640   ds_reg,
 641   fs_reg,
 642   gs_reg,
 643
 644   eAX_reg,
 645   eCX_reg,
 646   eDX_reg,
 647   eBX_reg,
 648   eSP_reg,
 649   eBP_reg,
 650   eSI_reg,
 651   eDI_reg,
 652
 653   al_reg,
 654   cl_reg,
 655   dl_reg,
 656   bl_reg,
 657   ah_reg,
 658   ch_reg,
 659   dh_reg,
 660   bh_reg,
 661
 662   ax_reg,
 663   cx_reg,
 664   dx_reg,
 665   bx_reg,
 666   sp_reg,
 667   bp_reg,
 668   si_reg,
 669   di_reg,
 670
 671   rAX_reg,
 672   rCX_reg,
 673   rDX_reg,
 674   rBX_reg,
 675   rSP_reg,
 676   rBP_reg,
 677   rSI_reg,
 678   rDI_reg,
 679
 680   z_mode_ax_reg,
 681   indir_dx_reg
 682 };
 683
 684 enum
 685 {
 686   FLOATCODE = 1,
 687   USE_REG_TABLE,
 688   USE_MOD_TABLE,
 689   USE_RM_TABLE,
 690   USE_PREFIX_TABLE,
 691   USE_X86_64_TABLE,
 692   USE_3BYTE_TABLE,
 693   USE_XOP_8F_TABLE,
 694   USE_VEX_C4_TABLE,
 695   USE_VEX_C5_TABLE,
 696   USE_VEX_LEN_TABLE,
 697   USE_VEX_W_TABLE,
 698   USE_EVEX_TABLE,
 699   USE_EVEX_LEN_TABLE
 700 };
 701
 702 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 703
 704 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 705 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 706 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 707 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 708 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 709 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 710 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 711 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 712 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 713 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 714 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 715 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 716 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 717 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 718 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 719 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 720
 721 enum
 722 {
 723   REG_80 = 0,
 724   REG_81,
 725   REG_83,
 726   REG_8F,
 727   REG_C0,
 728   REG_C1,
 729   REG_C6,
 730   REG_C7,
 731   REG_D0,
 732   REG_D1,
 733   REG_D2,
 734   REG_D3,
 735   REG_F6,
 736   REG_F7,
 737   REG_FE,
 738   REG_FF,
 739   REG_0F00,
 740   REG_0F01,
 741   REG_0F0D,
 742   REG_0F18,
 743   REG_0F1C_MOD_0,
 744   REG_0F1E_MOD_3,
 745   REG_0F71,
 746   REG_0F72,
 747   REG_0F73,
 748   REG_0FA6,
 749   REG_0FA7,
 750   REG_0FAE,
 751   REG_0FBA,
 752   REG_0FC7,
 753   REG_VEX_0F71,
 754   REG_VEX_0F72,
 755   REG_VEX_0F73,
 756   REG_VEX_0FAE,
 757   REG_VEX_0F38F3,
 758   REG_XOP_LWPCB,
 759   REG_XOP_LWP,
 760   REG_XOP_TBM_01,
 761   REG_XOP_TBM_02,
 762
 763   REG_EVEX_0F71,
 764   REG_EVEX_0F72,
 765   REG_EVEX_0F73,
 766   REG_EVEX_0F38C6,
 767   REG_EVEX_0F38C7
 768 };
 769
 770 enum
 771 {
 772   MOD_8D = 0,
 773   MOD_C6_REG_7,
 774   MOD_C7_REG_7,
 775   MOD_FF_REG_3,
 776   MOD_FF_REG_5,
 777   MOD_0F01_REG_0,
 778   MOD_0F01_REG_1,
 779   MOD_0F01_REG_2,
 780   MOD_0F01_REG_3,
 781   MOD_0F01_REG_5,
 782   MOD_0F01_REG_7,
 783   MOD_0F12_PREFIX_0,
 784   MOD_0F13,
 785   MOD_0F16_PREFIX_0,
 786   MOD_0F17,
 787   MOD_0F18_REG_0,
 788   MOD_0F18_REG_1,
 789   MOD_0F18_REG_2,
 790   MOD_0F18_REG_3,
 791   MOD_0F18_REG_4,
 792   MOD_0F18_REG_5,
 793   MOD_0F18_REG_6,
 794   MOD_0F18_REG_7,
 795   MOD_0F1A_PREFIX_0,
 796   MOD_0F1B_PREFIX_0,
 797   MOD_0F1B_PREFIX_1,
 798   MOD_0F1C_PREFIX_0,
 799   MOD_0F1E_PREFIX_1,
 800   MOD_0F24,
 801   MOD_0F26,
 802   MOD_0F2B_PREFIX_0,
 803   MOD_0F2B_PREFIX_1,
 804   MOD_0F2B_PREFIX_2,
 805   MOD_0F2B_PREFIX_3,
 806   MOD_0F51,
 807   MOD_0F71_REG_2,
 808   MOD_0F71_REG_4,
 809   MOD_0F71_REG_6,
 810   MOD_0F72_REG_2,
 811   MOD_0F72_REG_4,
 812   MOD_0F72_REG_6,
 813   MOD_0F73_REG_2,
 814   MOD_0F73_REG_3,
 815   MOD_0F73_REG_6,
 816   MOD_0F73_REG_7,
 817   MOD_0FAE_REG_0,
 818   MOD_0FAE_REG_1,
 819   MOD_0FAE_REG_2,
 820   MOD_0FAE_REG_3,
 821   MOD_0FAE_REG_4,
 822   MOD_0FAE_REG_5,
 823   MOD_0FAE_REG_6,
 824   MOD_0FAE_REG_7,
 825   MOD_0FB2,
 826   MOD_0FB4,
 827   MOD_0FB5,
 828   MOD_0FC3,
 829   MOD_0FC7_REG_3,
 830   MOD_0FC7_REG_4,
 831   MOD_0FC7_REG_5,
 832   MOD_0FC7_REG_6,
 833   MOD_0FC7_REG_7,
 834   MOD_0FD7,
 835   MOD_0FE7_PREFIX_2,
 836   MOD_0FF0_PREFIX_3,
 837   MOD_0F382A_PREFIX_2,
 838   MOD_0F38F5_PREFIX_2,
 839   MOD_0F38F6_PREFIX_0,
 840   MOD_0F38F8_PREFIX_1,
 841   MOD_0F38F8_PREFIX_2,
 842   MOD_0F38F8_PREFIX_3,
 843   MOD_0F38F9_PREFIX_0,
 844   MOD_62_32BIT,
 845   MOD_C4_32BIT,
 846   MOD_C5_32BIT,
 847   MOD_VEX_0F12_PREFIX_0,
 848   MOD_VEX_0F13,
 849   MOD_VEX_0F16_PREFIX_0,
 850   MOD_VEX_0F17,
 851   MOD_VEX_0F2B,
 852   MOD_VEX_W_0_0F41_P_0_LEN_1,
 853   MOD_VEX_W_1_0F41_P_0_LEN_1,
 854   MOD_VEX_W_0_0F41_P_2_LEN_1,
 855   MOD_VEX_W_1_0F41_P_2_LEN_1,
 856   MOD_VEX_W_0_0F42_P_0_LEN_1,
 857   MOD_VEX_W_1_0F42_P_0_LEN_1,
 858   MOD_VEX_W_0_0F42_P_2_LEN_1,
 859   MOD_VEX_W_1_0F42_P_2_LEN_1,
 860   MOD_VEX_W_0_0F44_P_0_LEN_1,
 861   MOD_VEX_W_1_0F44_P_0_LEN_1,
 862   MOD_VEX_W_0_0F44_P_2_LEN_1,
 863   MOD_VEX_W_1_0F44_P_2_LEN_1,
 864   MOD_VEX_W_0_0F45_P_0_LEN_1,
 865   MOD_VEX_W_1_0F45_P_0_LEN_1,
 866   MOD_VEX_W_0_0F45_P_2_LEN_1,
 867   MOD_VEX_W_1_0F45_P_2_LEN_1,
 868   MOD_VEX_W_0_0F46_P_0_LEN_1,
 869   MOD_VEX_W_1_0F46_P_0_LEN_1,
 870   MOD_VEX_W_0_0F46_P_2_LEN_1,
 871   MOD_VEX_W_1_0F46_P_2_LEN_1,
 872   MOD_VEX_W_0_0F47_P_0_LEN_1,
 873   MOD_VEX_W_1_0F47_P_0_LEN_1,
 874   MOD_VEX_W_0_0F47_P_2_LEN_1,
 875   MOD_VEX_W_1_0F47_P_2_LEN_1,
 876   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 878   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 880   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 882   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 883   MOD_VEX_0F50,
 884   MOD_VEX_0F71_REG_2,
 885   MOD_VEX_0F71_REG_4,
 886   MOD_VEX_0F71_REG_6,
 887   MOD_VEX_0F72_REG_2,
 888   MOD_VEX_0F72_REG_4,
 889   MOD_VEX_0F72_REG_6,
 890   MOD_VEX_0F73_REG_2,
 891   MOD_VEX_0F73_REG_3,
 892   MOD_VEX_0F73_REG_6,
 893   MOD_VEX_0F73_REG_7,
 894   MOD_VEX_W_0_0F91_P_0_LEN_0,
 895   MOD_VEX_W_1_0F91_P_0_LEN_0,
 896   MOD_VEX_W_0_0F91_P_2_LEN_0,
 897   MOD_VEX_W_1_0F91_P_2_LEN_0,
 898   MOD_VEX_W_0_0F92_P_0_LEN_0,
 899   MOD_VEX_W_0_0F92_P_2_LEN_0,
 900   MOD_VEX_0F92_P_3_LEN_0,
 901   MOD_VEX_W_0_0F93_P_0_LEN_0,
 902   MOD_VEX_W_0_0F93_P_2_LEN_0,
 903   MOD_VEX_0F93_P_3_LEN_0,
 904   MOD_VEX_W_0_0F98_P_0_LEN_0,
 905   MOD_VEX_W_1_0F98_P_0_LEN_0,
 906   MOD_VEX_W_0_0F98_P_2_LEN_0,
 907   MOD_VEX_W_1_0F98_P_2_LEN_0,
 908   MOD_VEX_W_0_0F99_P_0_LEN_0,
 909   MOD_VEX_W_1_0F99_P_0_LEN_0,
 910   MOD_VEX_W_0_0F99_P_2_LEN_0,
 911   MOD_VEX_W_1_0F99_P_2_LEN_0,
 912   MOD_VEX_0FAE_REG_2,
 913   MOD_VEX_0FAE_REG_3,
 914   MOD_VEX_0FD7_PREFIX_2,
 915   MOD_VEX_0FE7_PREFIX_2,
 916   MOD_VEX_0FF0_PREFIX_3,
 917   MOD_VEX_0F381A_PREFIX_2,
 918   MOD_VEX_0F382A_PREFIX_2,
 919   MOD_VEX_0F382C_PREFIX_2,
 920   MOD_VEX_0F382D_PREFIX_2,
 921   MOD_VEX_0F382E_PREFIX_2,
 922   MOD_VEX_0F382F_PREFIX_2,
 923   MOD_VEX_0F385A_PREFIX_2,
 924   MOD_VEX_0F388C_PREFIX_2,
 925   MOD_VEX_0F388E_PREFIX_2,
 926   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 928   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 932   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 934
 935   MOD_EVEX_0F10_PREFIX_1,
 936   MOD_EVEX_0F10_PREFIX_3,
 937   MOD_EVEX_0F11_PREFIX_1,
 938   MOD_EVEX_0F11_PREFIX_3,
 939   MOD_EVEX_0F12_PREFIX_0,
 940   MOD_EVEX_0F16_PREFIX_0,
 941   MOD_EVEX_0F38C6_REG_1,
 942   MOD_EVEX_0F38C6_REG_2,
 943   MOD_EVEX_0F38C6_REG_5,
 944   MOD_EVEX_0F38C6_REG_6,
 945   MOD_EVEX_0F38C7_REG_1,
 946   MOD_EVEX_0F38C7_REG_2,
 947   MOD_EVEX_0F38C7_REG_5,
 948   MOD_EVEX_0F38C7_REG_6
 949 };
 950
 951 enum
 952 {
 953   RM_C6_REG_7 = 0,
 954   RM_C7_REG_7,
 955   RM_0F01_REG_0,
 956   RM_0F01_REG_1,
 957   RM_0F01_REG_2,
 958   RM_0F01_REG_3,
 959   RM_0F01_REG_5,
 960   RM_0F01_REG_7,
 961   RM_0F1E_MOD_3_REG_7,
 962   RM_0FAE_REG_6,
 963   RM_0FAE_REG_7
 964 };
 965
 966 enum
 967 {
 968   PREFIX_90 = 0,
 969   PREFIX_MOD_0_0F01_REG_5,
 970   PREFIX_MOD_3_0F01_REG_5_RM_0,
 971   PREFIX_MOD_3_0F01_REG_5_RM_2,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6C,
1002   PREFIX_0F6D,
1003   PREFIX_0F6F,
1004   PREFIX_0F70,
1005   PREFIX_0F73_REG_3,
1006   PREFIX_0F73_REG_7,
1007   PREFIX_0F78,
1008   PREFIX_0F79,
1009   PREFIX_0F7C,
1010   PREFIX_0F7D,
1011   PREFIX_0F7E,
1012   PREFIX_0F7F,
1013   PREFIX_0FAE_REG_0,
1014   PREFIX_0FAE_REG_1,
1015   PREFIX_0FAE_REG_2,
1016   PREFIX_0FAE_REG_3,
1017   PREFIX_MOD_0_0FAE_REG_4,
1018   PREFIX_MOD_3_0FAE_REG_4,
1019   PREFIX_MOD_0_0FAE_REG_5,
1020   PREFIX_MOD_3_0FAE_REG_5,
1021   PREFIX_MOD_0_0FAE_REG_6,
1022   PREFIX_MOD_1_0FAE_REG_6,
1023   PREFIX_0FAE_REG_7,
1024   PREFIX_0FB8,
1025   PREFIX_0FBC,
1026   PREFIX_0FBD,
1027   PREFIX_0FC2,
1028   PREFIX_MOD_0_0FC3,
1029   PREFIX_MOD_0_0FC7_REG_6,
1030   PREFIX_MOD_3_0FC7_REG_6,
1031   PREFIX_MOD_3_0FC7_REG_7,
1032   PREFIX_0FD0,
1033   PREFIX_0FD6,
1034   PREFIX_0FE6,
1035   PREFIX_0FE7,
1036   PREFIX_0FF0,
1037   PREFIX_0FF7,
1038   PREFIX_0F3810,
1039   PREFIX_0F3814,
1040   PREFIX_0F3815,
1041   PREFIX_0F3817,
1042   PREFIX_0F3820,
1043   PREFIX_0F3821,
1044   PREFIX_0F3822,
1045   PREFIX_0F3823,
1046   PREFIX_0F3824,
1047   PREFIX_0F3825,
1048   PREFIX_0F3828,
1049   PREFIX_0F3829,
1050   PREFIX_0F382A,
1051   PREFIX_0F382B,
1052   PREFIX_0F3830,
1053   PREFIX_0F3831,
1054   PREFIX_0F3832,
1055   PREFIX_0F3833,
1056   PREFIX_0F3834,
1057   PREFIX_0F3835,
1058   PREFIX_0F3837,
1059   PREFIX_0F3838,
1060   PREFIX_0F3839,
1061   PREFIX_0F383A,
1062   PREFIX_0F383B,
1063   PREFIX_0F383C,
1064   PREFIX_0F383D,
1065   PREFIX_0F383E,
1066   PREFIX_0F383F,
1067   PREFIX_0F3840,
1068   PREFIX_0F3841,
1069   PREFIX_0F3880,
1070   PREFIX_0F3881,
1071   PREFIX_0F3882,
1072   PREFIX_0F38C8,
1073   PREFIX_0F38C9,
1074   PREFIX_0F38CA,
1075   PREFIX_0F38CB,
1076   PREFIX_0F38CC,
1077   PREFIX_0F38CD,
1078   PREFIX_0F38CF,
1079   PREFIX_0F38DB,
1080   PREFIX_0F38DC,
1081   PREFIX_0F38DD,
1082   PREFIX_0F38DE,
1083   PREFIX_0F38DF,
1084   PREFIX_0F38F0,
1085   PREFIX_0F38F1,
1086   PREFIX_0F38F5,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8,
1089   PREFIX_0F38F9,
1090   PREFIX_0F3A08,
1091   PREFIX_0F3A09,
1092   PREFIX_0F3A0A,
1093   PREFIX_0F3A0B,
1094   PREFIX_0F3A0C,
1095   PREFIX_0F3A0D,
1096   PREFIX_0F3A0E,
1097   PREFIX_0F3A14,
1098   PREFIX_0F3A15,
1099   PREFIX_0F3A16,
1100   PREFIX_0F3A17,
1101   PREFIX_0F3A20,
1102   PREFIX_0F3A21,
1103   PREFIX_0F3A22,
1104   PREFIX_0F3A40,
1105   PREFIX_0F3A41,
1106   PREFIX_0F3A42,
1107   PREFIX_0F3A44,
1108   PREFIX_0F3A60,
1109   PREFIX_0F3A61,
1110   PREFIX_0F3A62,
1111   PREFIX_0F3A63,
1112   PREFIX_0F3ACC,
1113   PREFIX_0F3ACE,
1114   PREFIX_0F3ACF,
1115   PREFIX_0F3ADF,
1116   PREFIX_VEX_0F10,
1117   PREFIX_VEX_0F11,
1118   PREFIX_VEX_0F12,
1119   PREFIX_VEX_0F16,
1120   PREFIX_VEX_0F2A,
1121   PREFIX_VEX_0F2C,
1122   PREFIX_VEX_0F2D,
1123   PREFIX_VEX_0F2E,
1124   PREFIX_VEX_0F2F,
1125   PREFIX_VEX_0F41,
1126   PREFIX_VEX_0F42,
1127   PREFIX_VEX_0F44,
1128   PREFIX_VEX_0F45,
1129   PREFIX_VEX_0F46,
1130   PREFIX_VEX_0F47,
1131   PREFIX_VEX_0F4A,
1132   PREFIX_VEX_0F4B,
1133   PREFIX_VEX_0F51,
1134   PREFIX_VEX_0F52,
1135   PREFIX_VEX_0F53,
1136   PREFIX_VEX_0F58,
1137   PREFIX_VEX_0F59,
1138   PREFIX_VEX_0F5A,
1139   PREFIX_VEX_0F5B,
1140   PREFIX_VEX_0F5C,
1141   PREFIX_VEX_0F5D,
1142   PREFIX_VEX_0F5E,
1143   PREFIX_VEX_0F5F,
1144   PREFIX_VEX_0F60,
1145   PREFIX_VEX_0F61,
1146   PREFIX_VEX_0F62,
1147   PREFIX_VEX_0F63,
1148   PREFIX_VEX_0F64,
1149   PREFIX_VEX_0F65,
1150   PREFIX_VEX_0F66,
1151   PREFIX_VEX_0F67,
1152   PREFIX_VEX_0F68,
1153   PREFIX_VEX_0F69,
1154   PREFIX_VEX_0F6A,
1155   PREFIX_VEX_0F6B,
1156   PREFIX_VEX_0F6C,
1157   PREFIX_VEX_0F6D,
1158   PREFIX_VEX_0F6E,
1159   PREFIX_VEX_0F6F,
1160   PREFIX_VEX_0F70,
1161   PREFIX_VEX_0F71_REG_2,
1162   PREFIX_VEX_0F71_REG_4,
1163   PREFIX_VEX_0F71_REG_6,
1164   PREFIX_VEX_0F72_REG_2,
1165   PREFIX_VEX_0F72_REG_4,
1166   PREFIX_VEX_0F72_REG_6,
1167   PREFIX_VEX_0F73_REG_2,
1168   PREFIX_VEX_0F73_REG_3,
1169   PREFIX_VEX_0F73_REG_6,
1170   PREFIX_VEX_0F73_REG_7,
1171   PREFIX_VEX_0F74,
1172   PREFIX_VEX_0F75,
1173   PREFIX_VEX_0F76,
1174   PREFIX_VEX_0F77,
1175   PREFIX_VEX_0F7C,
1176   PREFIX_VEX_0F7D,
1177   PREFIX_VEX_0F7E,
1178   PREFIX_VEX_0F7F,
1179   PREFIX_VEX_0F90,
1180   PREFIX_VEX_0F91,
1181   PREFIX_VEX_0F92,
1182   PREFIX_VEX_0F93,
1183   PREFIX_VEX_0F98,
1184   PREFIX_VEX_0F99,
1185   PREFIX_VEX_0FC2,
1186   PREFIX_VEX_0FC4,
1187   PREFIX_VEX_0FC5,
1188   PREFIX_VEX_0FD0,
1189   PREFIX_VEX_0FD1,
1190   PREFIX_VEX_0FD2,
1191   PREFIX_VEX_0FD3,
1192   PREFIX_VEX_0FD4,
1193   PREFIX_VEX_0FD5,
1194   PREFIX_VEX_0FD6,
1195   PREFIX_VEX_0FD7,
1196   PREFIX_VEX_0FD8,
1197   PREFIX_VEX_0FD9,
1198   PREFIX_VEX_0FDA,
1199   PREFIX_VEX_0FDB,
1200   PREFIX_VEX_0FDC,
1201   PREFIX_VEX_0FDD,
1202   PREFIX_VEX_0FDE,
1203   PREFIX_VEX_0FDF,
1204   PREFIX_VEX_0FE0,
1205   PREFIX_VEX_0FE1,
1206   PREFIX_VEX_0FE2,
1207   PREFIX_VEX_0FE3,
1208   PREFIX_VEX_0FE4,
1209   PREFIX_VEX_0FE5,
1210   PREFIX_VEX_0FE6,
1211   PREFIX_VEX_0FE7,
1212   PREFIX_VEX_0FE8,
1213   PREFIX_VEX_0FE9,
1214   PREFIX_VEX_0FEA,
1215   PREFIX_VEX_0FEB,
1216   PREFIX_VEX_0FEC,
1217   PREFIX_VEX_0FED,
1218   PREFIX_VEX_0FEE,
1219   PREFIX_VEX_0FEF,
1220   PREFIX_VEX_0FF0,
1221   PREFIX_VEX_0FF1,
1222   PREFIX_VEX_0FF2,
1223   PREFIX_VEX_0FF3,
1224   PREFIX_VEX_0FF4,
1225   PREFIX_VEX_0FF5,
1226   PREFIX_VEX_0FF6,
1227   PREFIX_VEX_0FF7,
1228   PREFIX_VEX_0FF8,
1229   PREFIX_VEX_0FF9,
1230   PREFIX_VEX_0FFA,
1231   PREFIX_VEX_0FFB,
1232   PREFIX_VEX_0FFC,
1233   PREFIX_VEX_0FFD,
1234   PREFIX_VEX_0FFE,
1235   PREFIX_VEX_0F3800,
1236   PREFIX_VEX_0F3801,
1237   PREFIX_VEX_0F3802,
1238   PREFIX_VEX_0F3803,
1239   PREFIX_VEX_0F3804,
1240   PREFIX_VEX_0F3805,
1241   PREFIX_VEX_0F3806,
1242   PREFIX_VEX_0F3807,
1243   PREFIX_VEX_0F3808,
1244   PREFIX_VEX_0F3809,
1245   PREFIX_VEX_0F380A,
1246   PREFIX_VEX_0F380B,
1247   PREFIX_VEX_0F380C,
1248   PREFIX_VEX_0F380D,
1249   PREFIX_VEX_0F380E,
1250   PREFIX_VEX_0F380F,
1251   PREFIX_VEX_0F3813,
1252   PREFIX_VEX_0F3816,
1253   PREFIX_VEX_0F3817,
1254   PREFIX_VEX_0F3818,
1255   PREFIX_VEX_0F3819,
1256   PREFIX_VEX_0F381A,
1257   PREFIX_VEX_0F381C,
1258   PREFIX_VEX_0F381D,
1259   PREFIX_VEX_0F381E,
1260   PREFIX_VEX_0F3820,
1261   PREFIX_VEX_0F3821,
1262   PREFIX_VEX_0F3822,
1263   PREFIX_VEX_0F3823,
1264   PREFIX_VEX_0F3824,
1265   PREFIX_VEX_0F3825,
1266   PREFIX_VEX_0F3828,
1267   PREFIX_VEX_0F3829,
1268   PREFIX_VEX_0F382A,
1269   PREFIX_VEX_0F382B,
1270   PREFIX_VEX_0F382C,
1271   PREFIX_VEX_0F382D,
1272   PREFIX_VEX_0F382E,
1273   PREFIX_VEX_0F382F,
1274   PREFIX_VEX_0F3830,
1275   PREFIX_VEX_0F3831,
1276   PREFIX_VEX_0F3832,
1277   PREFIX_VEX_0F3833,
1278   PREFIX_VEX_0F3834,
1279   PREFIX_VEX_0F3835,
1280   PREFIX_VEX_0F3836,
1281   PREFIX_VEX_0F3837,
1282   PREFIX_VEX_0F3838,
1283   PREFIX_VEX_0F3839,
1284   PREFIX_VEX_0F383A,
1285   PREFIX_VEX_0F383B,
1286   PREFIX_VEX_0F383C,
1287   PREFIX_VEX_0F383D,
1288   PREFIX_VEX_0F383E,
1289   PREFIX_VEX_0F383F,
1290   PREFIX_VEX_0F3840,
1291   PREFIX_VEX_0F3841,
1292   PREFIX_VEX_0F3845,
1293   PREFIX_VEX_0F3846,
1294   PREFIX_VEX_0F3847,
1295   PREFIX_VEX_0F3858,
1296   PREFIX_VEX_0F3859,
1297   PREFIX_VEX_0F385A,
1298   PREFIX_VEX_0F3878,
1299   PREFIX_VEX_0F3879,
1300   PREFIX_VEX_0F388C,
1301   PREFIX_VEX_0F388E,
1302   PREFIX_VEX_0F3890,
1303   PREFIX_VEX_0F3891,
1304   PREFIX_VEX_0F3892,
1305   PREFIX_VEX_0F3893,
1306   PREFIX_VEX_0F3896,
1307   PREFIX_VEX_0F3897,
1308   PREFIX_VEX_0F3898,
1309   PREFIX_VEX_0F3899,
1310   PREFIX_VEX_0F389A,
1311   PREFIX_VEX_0F389B,
1312   PREFIX_VEX_0F389C,
1313   PREFIX_VEX_0F389D,
1314   PREFIX_VEX_0F389E,
1315   PREFIX_VEX_0F389F,
1316   PREFIX_VEX_0F38A6,
1317   PREFIX_VEX_0F38A7,
1318   PREFIX_VEX_0F38A8,
1319   PREFIX_VEX_0F38A9,
1320   PREFIX_VEX_0F38AA,
1321   PREFIX_VEX_0F38AB,
1322   PREFIX_VEX_0F38AC,
1323   PREFIX_VEX_0F38AD,
1324   PREFIX_VEX_0F38AE,
1325   PREFIX_VEX_0F38AF,
1326   PREFIX_VEX_0F38B6,
1327   PREFIX_VEX_0F38B7,
1328   PREFIX_VEX_0F38B8,
1329   PREFIX_VEX_0F38B9,
1330   PREFIX_VEX_0F38BA,
1331   PREFIX_VEX_0F38BB,
1332   PREFIX_VEX_0F38BC,
1333   PREFIX_VEX_0F38BD,
1334   PREFIX_VEX_0F38BE,
1335   PREFIX_VEX_0F38BF,
1336   PREFIX_VEX_0F38CF,
1337   PREFIX_VEX_0F38DB,
1338   PREFIX_VEX_0F38DC,
1339   PREFIX_VEX_0F38DD,
1340   PREFIX_VEX_0F38DE,
1341   PREFIX_VEX_0F38DF,
1342   PREFIX_VEX_0F38F2,
1343   PREFIX_VEX_0F38F3_REG_1,
1344   PREFIX_VEX_0F38F3_REG_2,
1345   PREFIX_VEX_0F38F3_REG_3,
1346   PREFIX_VEX_0F38F5,
1347   PREFIX_VEX_0F38F6,
1348   PREFIX_VEX_0F38F7,
1349   PREFIX_VEX_0F3A00,
1350   PREFIX_VEX_0F3A01,
1351   PREFIX_VEX_0F3A02,
1352   PREFIX_VEX_0F3A04,
1353   PREFIX_VEX_0F3A05,
1354   PREFIX_VEX_0F3A06,
1355   PREFIX_VEX_0F3A08,
1356   PREFIX_VEX_0F3A09,
1357   PREFIX_VEX_0F3A0A,
1358   PREFIX_VEX_0F3A0B,
1359   PREFIX_VEX_0F3A0C,
1360   PREFIX_VEX_0F3A0D,
1361   PREFIX_VEX_0F3A0E,
1362   PREFIX_VEX_0F3A0F,
1363   PREFIX_VEX_0F3A14,
1364   PREFIX_VEX_0F3A15,
1365   PREFIX_VEX_0F3A16,
1366   PREFIX_VEX_0F3A17,
1367   PREFIX_VEX_0F3A18,
1368   PREFIX_VEX_0F3A19,
1369   PREFIX_VEX_0F3A1D,
1370   PREFIX_VEX_0F3A20,
1371   PREFIX_VEX_0F3A21,
1372   PREFIX_VEX_0F3A22,
1373   PREFIX_VEX_0F3A30,
1374   PREFIX_VEX_0F3A31,
1375   PREFIX_VEX_0F3A32,
1376   PREFIX_VEX_0F3A33,
1377   PREFIX_VEX_0F3A38,
1378   PREFIX_VEX_0F3A39,
1379   PREFIX_VEX_0F3A40,
1380   PREFIX_VEX_0F3A41,
1381   PREFIX_VEX_0F3A42,
1382   PREFIX_VEX_0F3A44,
1383   PREFIX_VEX_0F3A46,
1384   PREFIX_VEX_0F3A48,
1385   PREFIX_VEX_0F3A49,
1386   PREFIX_VEX_0F3A4A,
1387   PREFIX_VEX_0F3A4B,
1388   PREFIX_VEX_0F3A4C,
1389   PREFIX_VEX_0F3A5C,
1390   PREFIX_VEX_0F3A5D,
1391   PREFIX_VEX_0F3A5E,
1392   PREFIX_VEX_0F3A5F,
1393   PREFIX_VEX_0F3A60,
1394   PREFIX_VEX_0F3A61,
1395   PREFIX_VEX_0F3A62,
1396   PREFIX_VEX_0F3A63,
1397   PREFIX_VEX_0F3A68,
1398   PREFIX_VEX_0F3A69,
1399   PREFIX_VEX_0F3A6A,
1400   PREFIX_VEX_0F3A6B,
1401   PREFIX_VEX_0F3A6C,
1402   PREFIX_VEX_0F3A6D,
1403   PREFIX_VEX_0F3A6E,
1404   PREFIX_VEX_0F3A6F,
1405   PREFIX_VEX_0F3A78,
1406   PREFIX_VEX_0F3A79,
1407   PREFIX_VEX_0F3A7A,
1408   PREFIX_VEX_0F3A7B,
1409   PREFIX_VEX_0F3A7C,
1410   PREFIX_VEX_0F3A7D,
1411   PREFIX_VEX_0F3A7E,
1412   PREFIX_VEX_0F3A7F,
1413   PREFIX_VEX_0F3ACE,
1414   PREFIX_VEX_0F3ACF,
1415   PREFIX_VEX_0F3ADF,
1416   PREFIX_VEX_0F3AF0,
1417
1418   PREFIX_EVEX_0F10,
1419   PREFIX_EVEX_0F11,
1420   PREFIX_EVEX_0F12,
1421   PREFIX_EVEX_0F13,
1422   PREFIX_EVEX_0F14,
1423   PREFIX_EVEX_0F15,
1424   PREFIX_EVEX_0F16,
1425   PREFIX_EVEX_0F17,
1426   PREFIX_EVEX_0F28,
1427   PREFIX_EVEX_0F29,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2B,
1430   PREFIX_EVEX_0F2C,
1431   PREFIX_EVEX_0F2D,
1432   PREFIX_EVEX_0F2E,
1433   PREFIX_EVEX_0F2F,
1434   PREFIX_EVEX_0F51,
1435   PREFIX_EVEX_0F54,
1436   PREFIX_EVEX_0F55,
1437   PREFIX_EVEX_0F56,
1438   PREFIX_EVEX_0F57,
1439   PREFIX_EVEX_0F58,
1440   PREFIX_EVEX_0F59,
1441   PREFIX_EVEX_0F5A,
1442   PREFIX_EVEX_0F5B,
1443   PREFIX_EVEX_0F5C,
1444   PREFIX_EVEX_0F5D,
1445   PREFIX_EVEX_0F5E,
1446   PREFIX_EVEX_0F5F,
1447   PREFIX_EVEX_0F60,
1448   PREFIX_EVEX_0F61,
1449   PREFIX_EVEX_0F62,
1450   PREFIX_EVEX_0F63,
1451   PREFIX_EVEX_0F64,
1452   PREFIX_EVEX_0F65,
1453   PREFIX_EVEX_0F66,
1454   PREFIX_EVEX_0F67,
1455   PREFIX_EVEX_0F68,
1456   PREFIX_EVEX_0F69,
1457   PREFIX_EVEX_0F6A,
1458   PREFIX_EVEX_0F6B,
1459   PREFIX_EVEX_0F6C,
1460   PREFIX_EVEX_0F6D,
1461   PREFIX_EVEX_0F6E,
1462   PREFIX_EVEX_0F6F,
1463   PREFIX_EVEX_0F70,
1464   PREFIX_EVEX_0F71_REG_2,
1465   PREFIX_EVEX_0F71_REG_4,
1466   PREFIX_EVEX_0F71_REG_6,
1467   PREFIX_EVEX_0F72_REG_0,
1468   PREFIX_EVEX_0F72_REG_1,
1469   PREFIX_EVEX_0F72_REG_2,
1470   PREFIX_EVEX_0F72_REG_4,
1471   PREFIX_EVEX_0F72_REG_6,
1472   PREFIX_EVEX_0F73_REG_2,
1473   PREFIX_EVEX_0F73_REG_3,
1474   PREFIX_EVEX_0F73_REG_6,
1475   PREFIX_EVEX_0F73_REG_7,
1476   PREFIX_EVEX_0F74,
1477   PREFIX_EVEX_0F75,
1478   PREFIX_EVEX_0F76,
1479   PREFIX_EVEX_0F78,
1480   PREFIX_EVEX_0F79,
1481   PREFIX_EVEX_0F7A,
1482   PREFIX_EVEX_0F7B,
1483   PREFIX_EVEX_0F7E,
1484   PREFIX_EVEX_0F7F,
1485   PREFIX_EVEX_0FC2,
1486   PREFIX_EVEX_0FC4,
1487   PREFIX_EVEX_0FC5,
1488   PREFIX_EVEX_0FC6,
1489   PREFIX_EVEX_0FD1,
1490   PREFIX_EVEX_0FD2,
1491   PREFIX_EVEX_0FD3,
1492   PREFIX_EVEX_0FD4,
1493   PREFIX_EVEX_0FD5,
1494   PREFIX_EVEX_0FD6,
1495   PREFIX_EVEX_0FD8,
1496   PREFIX_EVEX_0FD9,
1497   PREFIX_EVEX_0FDA,
1498   PREFIX_EVEX_0FDB,
1499   PREFIX_EVEX_0FDC,
1500   PREFIX_EVEX_0FDD,
1501   PREFIX_EVEX_0FDE,
1502   PREFIX_EVEX_0FDF,
1503   PREFIX_EVEX_0FE0,
1504   PREFIX_EVEX_0FE1,
1505   PREFIX_EVEX_0FE2,
1506   PREFIX_EVEX_0FE3,
1507   PREFIX_EVEX_0FE4,
1508   PREFIX_EVEX_0FE5,
1509   PREFIX_EVEX_0FE6,
1510   PREFIX_EVEX_0FE7,
1511   PREFIX_EVEX_0FE8,
1512   PREFIX_EVEX_0FE9,
1513   PREFIX_EVEX_0FEA,
1514   PREFIX_EVEX_0FEB,
1515   PREFIX_EVEX_0FEC,
1516   PREFIX_EVEX_0FED,
1517   PREFIX_EVEX_0FEE,
1518   PREFIX_EVEX_0FEF,
1519   PREFIX_EVEX_0FF1,
1520   PREFIX_EVEX_0FF2,
1521   PREFIX_EVEX_0FF3,
1522   PREFIX_EVEX_0FF4,
1523   PREFIX_EVEX_0FF5,
1524   PREFIX_EVEX_0FF6,
1525   PREFIX_EVEX_0FF8,
1526   PREFIX_EVEX_0FF9,
1527   PREFIX_EVEX_0FFA,
1528   PREFIX_EVEX_0FFB,
1529   PREFIX_EVEX_0FFC,
1530   PREFIX_EVEX_0FFD,
1531   PREFIX_EVEX_0FFE,
1532   PREFIX_EVEX_0F3800,
1533   PREFIX_EVEX_0F3804,
1534   PREFIX_EVEX_0F380B,
1535   PREFIX_EVEX_0F380C,
1536   PREFIX_EVEX_0F380D,
1537   PREFIX_EVEX_0F3810,
1538   PREFIX_EVEX_0F3811,
1539   PREFIX_EVEX_0F3812,
1540   PREFIX_EVEX_0F3813,
1541   PREFIX_EVEX_0F3814,
1542   PREFIX_EVEX_0F3815,
1543   PREFIX_EVEX_0F3816,
1544   PREFIX_EVEX_0F3818,
1545   PREFIX_EVEX_0F3819,
1546   PREFIX_EVEX_0F381A,
1547   PREFIX_EVEX_0F381B,
1548   PREFIX_EVEX_0F381C,
1549   PREFIX_EVEX_0F381D,
1550   PREFIX_EVEX_0F381E,
1551   PREFIX_EVEX_0F381F,
1552   PREFIX_EVEX_0F3820,
1553   PREFIX_EVEX_0F3821,
1554   PREFIX_EVEX_0F3822,
1555   PREFIX_EVEX_0F3823,
1556   PREFIX_EVEX_0F3824,
1557   PREFIX_EVEX_0F3825,
1558   PREFIX_EVEX_0F3826,
1559   PREFIX_EVEX_0F3827,
1560   PREFIX_EVEX_0F3828,
1561   PREFIX_EVEX_0F3829,
1562   PREFIX_EVEX_0F382A,
1563   PREFIX_EVEX_0F382B,
1564   PREFIX_EVEX_0F382C,
1565   PREFIX_EVEX_0F382D,
1566   PREFIX_EVEX_0F3830,
1567   PREFIX_EVEX_0F3831,
1568   PREFIX_EVEX_0F3832,
1569   PREFIX_EVEX_0F3833,
1570   PREFIX_EVEX_0F3834,
1571   PREFIX_EVEX_0F3835,
1572   PREFIX_EVEX_0F3836,
1573   PREFIX_EVEX_0F3837,
1574   PREFIX_EVEX_0F3838,
1575   PREFIX_EVEX_0F3839,
1576   PREFIX_EVEX_0F383A,
1577   PREFIX_EVEX_0F383B,
1578   PREFIX_EVEX_0F383C,
1579   PREFIX_EVEX_0F383D,
1580   PREFIX_EVEX_0F383E,
1581   PREFIX_EVEX_0F383F,
1582   PREFIX_EVEX_0F3840,
1583   PREFIX_EVEX_0F3842,
1584   PREFIX_EVEX_0F3843,
1585   PREFIX_EVEX_0F3844,
1586   PREFIX_EVEX_0F3845,
1587   PREFIX_EVEX_0F3846,
1588   PREFIX_EVEX_0F3847,
1589   PREFIX_EVEX_0F384C,
1590   PREFIX_EVEX_0F384D,
1591   PREFIX_EVEX_0F384E,
1592   PREFIX_EVEX_0F384F,
1593   PREFIX_EVEX_0F3850,
1594   PREFIX_EVEX_0F3851,
1595   PREFIX_EVEX_0F3852,
1596   PREFIX_EVEX_0F3853,
1597   PREFIX_EVEX_0F3854,
1598   PREFIX_EVEX_0F3855,
1599   PREFIX_EVEX_0F3858,
1600   PREFIX_EVEX_0F3859,
1601   PREFIX_EVEX_0F385A,
1602   PREFIX_EVEX_0F385B,
1603   PREFIX_EVEX_0F3862,
1604   PREFIX_EVEX_0F3863,
1605   PREFIX_EVEX_0F3864,
1606   PREFIX_EVEX_0F3865,
1607   PREFIX_EVEX_0F3866,
1608   PREFIX_EVEX_0F3868,
1609   PREFIX_EVEX_0F3870,
1610   PREFIX_EVEX_0F3871,
1611   PREFIX_EVEX_0F3872,
1612   PREFIX_EVEX_0F3873,
1613   PREFIX_EVEX_0F3875,
1614   PREFIX_EVEX_0F3876,
1615   PREFIX_EVEX_0F3877,
1616   PREFIX_EVEX_0F3878,
1617   PREFIX_EVEX_0F3879,
1618   PREFIX_EVEX_0F387A,
1619   PREFIX_EVEX_0F387B,
1620   PREFIX_EVEX_0F387C,
1621   PREFIX_EVEX_0F387D,
1622   PREFIX_EVEX_0F387E,
1623   PREFIX_EVEX_0F387F,
1624   PREFIX_EVEX_0F3883,
1625   PREFIX_EVEX_0F3888,
1626   PREFIX_EVEX_0F3889,
1627   PREFIX_EVEX_0F388A,
1628   PREFIX_EVEX_0F388B,
1629   PREFIX_EVEX_0F388D,
1630   PREFIX_EVEX_0F388F,
1631   PREFIX_EVEX_0F3890,
1632   PREFIX_EVEX_0F3891,
1633   PREFIX_EVEX_0F3892,
1634   PREFIX_EVEX_0F3893,
1635   PREFIX_EVEX_0F3896,
1636   PREFIX_EVEX_0F3897,
1637   PREFIX_EVEX_0F3898,
1638   PREFIX_EVEX_0F3899,
1639   PREFIX_EVEX_0F389A,
1640   PREFIX_EVEX_0F389B,
1641   PREFIX_EVEX_0F389C,
1642   PREFIX_EVEX_0F389D,
1643   PREFIX_EVEX_0F389E,
1644   PREFIX_EVEX_0F389F,
1645   PREFIX_EVEX_0F38A0,
1646   PREFIX_EVEX_0F38A1,
1647   PREFIX_EVEX_0F38A2,
1648   PREFIX_EVEX_0F38A3,
1649   PREFIX_EVEX_0F38A6,
1650   PREFIX_EVEX_0F38A7,
1651   PREFIX_EVEX_0F38A8,
1652   PREFIX_EVEX_0F38A9,
1653   PREFIX_EVEX_0F38AA,
1654   PREFIX_EVEX_0F38AB,
1655   PREFIX_EVEX_0F38AC,
1656   PREFIX_EVEX_0F38AD,
1657   PREFIX_EVEX_0F38AE,
1658   PREFIX_EVEX_0F38AF,
1659   PREFIX_EVEX_0F38B4,
1660   PREFIX_EVEX_0F38B5,
1661   PREFIX_EVEX_0F38B6,
1662   PREFIX_EVEX_0F38B7,
1663   PREFIX_EVEX_0F38B8,
1664   PREFIX_EVEX_0F38B9,
1665   PREFIX_EVEX_0F38BA,
1666   PREFIX_EVEX_0F38BB,
1667   PREFIX_EVEX_0F38BC,
1668   PREFIX_EVEX_0F38BD,
1669   PREFIX_EVEX_0F38BE,
1670   PREFIX_EVEX_0F38BF,
1671   PREFIX_EVEX_0F38C4,
1672   PREFIX_EVEX_0F38C6_REG_1,
1673   PREFIX_EVEX_0F38C6_REG_2,
1674   PREFIX_EVEX_0F38C6_REG_5,
1675   PREFIX_EVEX_0F38C6_REG_6,
1676   PREFIX_EVEX_0F38C7_REG_1,
1677   PREFIX_EVEX_0F38C7_REG_2,
1678   PREFIX_EVEX_0F38C7_REG_5,
1679   PREFIX_EVEX_0F38C7_REG_6,
1680   PREFIX_EVEX_0F38C8,
1681   PREFIX_EVEX_0F38CA,
1682   PREFIX_EVEX_0F38CB,
1683   PREFIX_EVEX_0F38CC,
1684   PREFIX_EVEX_0F38CD,
1685   PREFIX_EVEX_0F38CF,
1686   PREFIX_EVEX_0F38DC,
1687   PREFIX_EVEX_0F38DD,
1688   PREFIX_EVEX_0F38DE,
1689   PREFIX_EVEX_0F38DF,
1690
1691   PREFIX_EVEX_0F3A00,
1692   PREFIX_EVEX_0F3A01,
1693   PREFIX_EVEX_0F3A03,
1694   PREFIX_EVEX_0F3A04,
1695   PREFIX_EVEX_0F3A05,
1696   PREFIX_EVEX_0F3A08,
1697   PREFIX_EVEX_0F3A09,
1698   PREFIX_EVEX_0F3A0A,
1699   PREFIX_EVEX_0F3A0B,
1700   PREFIX_EVEX_0F3A0F,
1701   PREFIX_EVEX_0F3A14,
1702   PREFIX_EVEX_0F3A15,
1703   PREFIX_EVEX_0F3A16,
1704   PREFIX_EVEX_0F3A17,
1705   PREFIX_EVEX_0F3A18,
1706   PREFIX_EVEX_0F3A19,
1707   PREFIX_EVEX_0F3A1A,
1708   PREFIX_EVEX_0F3A1B,
1709   PREFIX_EVEX_0F3A1D,
1710   PREFIX_EVEX_0F3A1E,
1711   PREFIX_EVEX_0F3A1F,
1712   PREFIX_EVEX_0F3A20,
1713   PREFIX_EVEX_0F3A21,
1714   PREFIX_EVEX_0F3A22,
1715   PREFIX_EVEX_0F3A23,
1716   PREFIX_EVEX_0F3A25,
1717   PREFIX_EVEX_0F3A26,
1718   PREFIX_EVEX_0F3A27,
1719   PREFIX_EVEX_0F3A38,
1720   PREFIX_EVEX_0F3A39,
1721   PREFIX_EVEX_0F3A3A,
1722   PREFIX_EVEX_0F3A3B,
1723   PREFIX_EVEX_0F3A3E,
1724   PREFIX_EVEX_0F3A3F,
1725   PREFIX_EVEX_0F3A42,
1726   PREFIX_EVEX_0F3A43,
1727   PREFIX_EVEX_0F3A44,
1728   PREFIX_EVEX_0F3A50,
1729   PREFIX_EVEX_0F3A51,
1730   PREFIX_EVEX_0F3A54,
1731   PREFIX_EVEX_0F3A55,
1732   PREFIX_EVEX_0F3A56,
1733   PREFIX_EVEX_0F3A57,
1734   PREFIX_EVEX_0F3A66,
1735   PREFIX_EVEX_0F3A67,
1736   PREFIX_EVEX_0F3A70,
1737   PREFIX_EVEX_0F3A71,
1738   PREFIX_EVEX_0F3A72,
1739   PREFIX_EVEX_0F3A73,
1740   PREFIX_EVEX_0F3ACE,
1741   PREFIX_EVEX_0F3ACF
1742 };
1743
1744 enum
1745 {
1746   X86_64_06 = 0,
1747   X86_64_07,
1748   X86_64_0D,
1749   X86_64_16,
1750   X86_64_17,
1751   X86_64_1E,
1752   X86_64_1F,
1753   X86_64_27,
1754   X86_64_2F,
1755   X86_64_37,
1756   X86_64_3F,
1757   X86_64_60,
1758   X86_64_61,
1759   X86_64_62,
1760   X86_64_63,
1761   X86_64_6D,
1762   X86_64_6F,
1763   X86_64_82,
1764   X86_64_9A,
1765   X86_64_C4,
1766   X86_64_C5,
1767   X86_64_CE,
1768   X86_64_D4,
1769   X86_64_D5,
1770   X86_64_E8,
1771   X86_64_E9,
1772   X86_64_EA,
1773   X86_64_0F01_REG_0,
1774   X86_64_0F01_REG_1,
1775   X86_64_0F01_REG_2,
1776   X86_64_0F01_REG_3
1777 };
1778
1779 enum
1780 {
1781   THREE_BYTE_0F38 = 0,
1782   THREE_BYTE_0F3A
1783 };
1784
1785 enum
1786 {
1787   XOP_08 = 0,
1788   XOP_09,
1789   XOP_0A
1790 };
1791
1792 enum
1793 {
1794   VEX_0F = 0,
1795   VEX_0F38,
1796   VEX_0F3A
1797 };
1798
1799 enum
1800 {
1801   EVEX_0F = 0,
1802   EVEX_0F38,
1803   EVEX_0F3A
1804 };
1805
1806 enum
1807 {
1808   VEX_LEN_0F12_P_0_M_0 = 0,
1809   VEX_LEN_0F12_P_0_M_1,
1810   VEX_LEN_0F12_P_2,
1811   VEX_LEN_0F13_M_0,
1812   VEX_LEN_0F16_P_0_M_0,
1813   VEX_LEN_0F16_P_0_M_1,
1814   VEX_LEN_0F16_P_2,
1815   VEX_LEN_0F17_M_0,
1816   VEX_LEN_0F41_P_0,
1817   VEX_LEN_0F41_P_2,
1818   VEX_LEN_0F42_P_0,
1819   VEX_LEN_0F42_P_2,
1820   VEX_LEN_0F44_P_0,
1821   VEX_LEN_0F44_P_2,
1822   VEX_LEN_0F45_P_0,
1823   VEX_LEN_0F45_P_2,
1824   VEX_LEN_0F46_P_0,
1825   VEX_LEN_0F46_P_2,
1826   VEX_LEN_0F47_P_0,
1827   VEX_LEN_0F47_P_2,
1828   VEX_LEN_0F4A_P_0,
1829   VEX_LEN_0F4A_P_2,
1830   VEX_LEN_0F4B_P_0,
1831   VEX_LEN_0F4B_P_2,
1832   VEX_LEN_0F6E_P_2,
1833   VEX_LEN_0F77_P_0,
1834   VEX_LEN_0F7E_P_1,
1835   VEX_LEN_0F7E_P_2,
1836   VEX_LEN_0F90_P_0,
1837   VEX_LEN_0F90_P_2,
1838   VEX_LEN_0F91_P_0,
1839   VEX_LEN_0F91_P_2,
1840   VEX_LEN_0F92_P_0,
1841   VEX_LEN_0F92_P_2,
1842   VEX_LEN_0F92_P_3,
1843   VEX_LEN_0F93_P_0,
1844   VEX_LEN_0F93_P_2,
1845   VEX_LEN_0F93_P_3,
1846   VEX_LEN_0F98_P_0,
1847   VEX_LEN_0F98_P_2,
1848   VEX_LEN_0F99_P_0,
1849   VEX_LEN_0F99_P_2,
1850   VEX_LEN_0FAE_R_2_M_0,
1851   VEX_LEN_0FAE_R_3_M_0,
1852   VEX_LEN_0FC4_P_2,
1853   VEX_LEN_0FC5_P_2,
1854   VEX_LEN_0FD6_P_2,
1855   VEX_LEN_0FF7_P_2,
1856   VEX_LEN_0F3816_P_2,
1857   VEX_LEN_0F3819_P_2,
1858   VEX_LEN_0F381A_P_2_M_0,
1859   VEX_LEN_0F3836_P_2,
1860   VEX_LEN_0F3841_P_2,
1861   VEX_LEN_0F385A_P_2_M_0,
1862   VEX_LEN_0F38DB_P_2,
1863   VEX_LEN_0F38F2_P_0,
1864   VEX_LEN_0F38F3_R_1_P_0,
1865   VEX_LEN_0F38F3_R_2_P_0,
1866   VEX_LEN_0F38F3_R_3_P_0,
1867   VEX_LEN_0F38F5_P_0,
1868   VEX_LEN_0F38F5_P_1,
1869   VEX_LEN_0F38F5_P_3,
1870   VEX_LEN_0F38F6_P_3,
1871   VEX_LEN_0F38F7_P_0,
1872   VEX_LEN_0F38F7_P_1,
1873   VEX_LEN_0F38F7_P_2,
1874   VEX_LEN_0F38F7_P_3,
1875   VEX_LEN_0F3A00_P_2,
1876   VEX_LEN_0F3A01_P_2,
1877   VEX_LEN_0F3A06_P_2,
1878   VEX_LEN_0F3A14_P_2,
1879   VEX_LEN_0F3A15_P_2,
1880   VEX_LEN_0F3A16_P_2,
1881   VEX_LEN_0F3A17_P_2,
1882   VEX_LEN_0F3A18_P_2,
1883   VEX_LEN_0F3A19_P_2,
1884   VEX_LEN_0F3A20_P_2,
1885   VEX_LEN_0F3A21_P_2,
1886   VEX_LEN_0F3A22_P_2,
1887   VEX_LEN_0F3A30_P_2,
1888   VEX_LEN_0F3A31_P_2,
1889   VEX_LEN_0F3A32_P_2,
1890   VEX_LEN_0F3A33_P_2,
1891   VEX_LEN_0F3A38_P_2,
1892   VEX_LEN_0F3A39_P_2,
1893   VEX_LEN_0F3A41_P_2,
1894   VEX_LEN_0F3A46_P_2,
1895   VEX_LEN_0F3A60_P_2,
1896   VEX_LEN_0F3A61_P_2,
1897   VEX_LEN_0F3A62_P_2,
1898   VEX_LEN_0F3A63_P_2,
1899   VEX_LEN_0F3A6A_P_2,
1900   VEX_LEN_0F3A6B_P_2,
1901   VEX_LEN_0F3A6E_P_2,
1902   VEX_LEN_0F3A6F_P_2,
1903   VEX_LEN_0F3A7A_P_2,
1904   VEX_LEN_0F3A7B_P_2,
1905   VEX_LEN_0F3A7E_P_2,
1906   VEX_LEN_0F3A7F_P_2,
1907   VEX_LEN_0F3ADF_P_2,
1908   VEX_LEN_0F3AF0_P_3,
1909   VEX_LEN_0FXOP_08_CC,
1910   VEX_LEN_0FXOP_08_CD,
1911   VEX_LEN_0FXOP_08_CE,
1912   VEX_LEN_0FXOP_08_CF,
1913   VEX_LEN_0FXOP_08_EC,
1914   VEX_LEN_0FXOP_08_ED,
1915   VEX_LEN_0FXOP_08_EE,
1916   VEX_LEN_0FXOP_08_EF,
1917   VEX_LEN_0FXOP_09_80,
1918   VEX_LEN_0FXOP_09_81
1919 };
1920
1921 enum
1922 {
1923   EVEX_LEN_0F6E_P_2 = 0,
1924   EVEX_LEN_0F7E_P_1,
1925   EVEX_LEN_0F7E_P_2,
1926   EVEX_LEN_0FD6_P_2,
1927   EVEX_LEN_0F3819_P_2_W_0,
1928   EVEX_LEN_0F3819_P_2_W_1,
1929   EVEX_LEN_0F381A_P_2_W_0,
1930   EVEX_LEN_0F381A_P_2_W_1,
1931   EVEX_LEN_0F381B_P_2_W_0,
1932   EVEX_LEN_0F381B_P_2_W_1,
1933   EVEX_LEN_0F385A_P_2_W_0,
1934   EVEX_LEN_0F385A_P_2_W_1,
1935   EVEX_LEN_0F385B_P_2_W_0,
1936   EVEX_LEN_0F385B_P_2_W_1,
1937   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1938   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1939   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1940   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1941   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1945   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1946   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1947   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1948   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1949   EVEX_LEN_0F3A18_P_2_W_0,
1950   EVEX_LEN_0F3A18_P_2_W_1,
1951   EVEX_LEN_0F3A19_P_2_W_0,
1952   EVEX_LEN_0F3A19_P_2_W_1,
1953   EVEX_LEN_0F3A1A_P_2_W_0,
1954   EVEX_LEN_0F3A1A_P_2_W_1,
1955   EVEX_LEN_0F3A1B_P_2_W_0,
1956   EVEX_LEN_0F3A1B_P_2_W_1,
1957   EVEX_LEN_0F3A23_P_2_W_0,
1958   EVEX_LEN_0F3A23_P_2_W_1,
1959   EVEX_LEN_0F3A38_P_2_W_0,
1960   EVEX_LEN_0F3A38_P_2_W_1,
1961   EVEX_LEN_0F3A39_P_2_W_0,
1962   EVEX_LEN_0F3A39_P_2_W_1,
1963   EVEX_LEN_0F3A3A_P_2_W_0,
1964   EVEX_LEN_0F3A3A_P_2_W_1,
1965   EVEX_LEN_0F3A3B_P_2_W_0,
1966   EVEX_LEN_0F3A3B_P_2_W_1,
1967   EVEX_LEN_0F3A43_P_2_W_0,
1968   EVEX_LEN_0F3A43_P_2_W_1
1969 };
1970
1971 enum
1972 {
1973   VEX_W_0F41_P_0_LEN_1 = 0,
1974   VEX_W_0F41_P_2_LEN_1,
1975   VEX_W_0F42_P_0_LEN_1,
1976   VEX_W_0F42_P_2_LEN_1,
1977   VEX_W_0F44_P_0_LEN_0,
1978   VEX_W_0F44_P_2_LEN_0,
1979   VEX_W_0F45_P_0_LEN_1,
1980   VEX_W_0F45_P_2_LEN_1,
1981   VEX_W_0F46_P_0_LEN_1,
1982   VEX_W_0F46_P_2_LEN_1,
1983   VEX_W_0F47_P_0_LEN_1,
1984   VEX_W_0F47_P_2_LEN_1,
1985   VEX_W_0F4A_P_0_LEN_1,
1986   VEX_W_0F4A_P_2_LEN_1,
1987   VEX_W_0F4B_P_0_LEN_1,
1988   VEX_W_0F4B_P_2_LEN_1,
1989   VEX_W_0F90_P_0_LEN_0,
1990   VEX_W_0F90_P_2_LEN_0,
1991   VEX_W_0F91_P_0_LEN_0,
1992   VEX_W_0F91_P_2_LEN_0,
1993   VEX_W_0F92_P_0_LEN_0,
1994   VEX_W_0F92_P_2_LEN_0,
1995   VEX_W_0F93_P_0_LEN_0,
1996   VEX_W_0F93_P_2_LEN_0,
1997   VEX_W_0F98_P_0_LEN_0,
1998   VEX_W_0F98_P_2_LEN_0,
1999   VEX_W_0F99_P_0_LEN_0,
2000   VEX_W_0F99_P_2_LEN_0,
2001   VEX_W_0F380C_P_2,
2002   VEX_W_0F380D_P_2,
2003   VEX_W_0F380E_P_2,
2004   VEX_W_0F380F_P_2,
2005   VEX_W_0F3816_P_2,
2006   VEX_W_0F3818_P_2,
2007   VEX_W_0F3819_P_2,
2008   VEX_W_0F381A_P_2_M_0,
2009   VEX_W_0F382C_P_2_M_0,
2010   VEX_W_0F382D_P_2_M_0,
2011   VEX_W_0F382E_P_2_M_0,
2012   VEX_W_0F382F_P_2_M_0,
2013   VEX_W_0F3836_P_2,
2014   VEX_W_0F3846_P_2,
2015   VEX_W_0F3858_P_2,
2016   VEX_W_0F3859_P_2,
2017   VEX_W_0F385A_P_2_M_0,
2018   VEX_W_0F3878_P_2,
2019   VEX_W_0F3879_P_2,
2020   VEX_W_0F38CF_P_2,
2021   VEX_W_0F3A00_P_2,
2022   VEX_W_0F3A01_P_2,
2023   VEX_W_0F3A02_P_2,
2024   VEX_W_0F3A04_P_2,
2025   VEX_W_0F3A05_P_2,
2026   VEX_W_0F3A06_P_2,
2027   VEX_W_0F3A18_P_2,
2028   VEX_W_0F3A19_P_2,
2029   VEX_W_0F3A30_P_2_LEN_0,
2030   VEX_W_0F3A31_P_2_LEN_0,
2031   VEX_W_0F3A32_P_2_LEN_0,
2032   VEX_W_0F3A33_P_2_LEN_0,
2033   VEX_W_0F3A38_P_2,
2034   VEX_W_0F3A39_P_2,
2035   VEX_W_0F3A46_P_2,
2036   VEX_W_0F3A48_P_2,
2037   VEX_W_0F3A49_P_2,
2038   VEX_W_0F3A4A_P_2,
2039   VEX_W_0F3A4B_P_2,
2040   VEX_W_0F3A4C_P_2,
2041   VEX_W_0F3ACE_P_2,
2042   VEX_W_0F3ACF_P_2,
2043
2044   EVEX_W_0F10_P_0,
2045   EVEX_W_0F10_P_1_M_0,
2046   EVEX_W_0F10_P_1_M_1,
2047   EVEX_W_0F10_P_2,
2048   EVEX_W_0F10_P_3_M_0,
2049   EVEX_W_0F10_P_3_M_1,
2050   EVEX_W_0F11_P_0,
2051   EVEX_W_0F11_P_1_M_0,
2052   EVEX_W_0F11_P_1_M_1,
2053   EVEX_W_0F11_P_2,
2054   EVEX_W_0F11_P_3_M_0,
2055   EVEX_W_0F11_P_3_M_1,
2056   EVEX_W_0F12_P_0_M_0,
2057   EVEX_W_0F12_P_0_M_1,
2058   EVEX_W_0F12_P_1,
2059   EVEX_W_0F12_P_2,
2060   EVEX_W_0F12_P_3,
2061   EVEX_W_0F13_P_0,
2062   EVEX_W_0F13_P_2,
2063   EVEX_W_0F14_P_0,
2064   EVEX_W_0F14_P_2,
2065   EVEX_W_0F15_P_0,
2066   EVEX_W_0F15_P_2,
2067   EVEX_W_0F16_P_0_M_0,
2068   EVEX_W_0F16_P_0_M_1,
2069   EVEX_W_0F16_P_1,
2070   EVEX_W_0F16_P_2,
2071   EVEX_W_0F17_P_0,
2072   EVEX_W_0F17_P_2,
2073   EVEX_W_0F28_P_0,
2074   EVEX_W_0F28_P_2,
2075   EVEX_W_0F29_P_0,
2076   EVEX_W_0F29_P_2,
2077   EVEX_W_0F2A_P_3,
2078   EVEX_W_0F2B_P_0,
2079   EVEX_W_0F2B_P_2,
2080   EVEX_W_0F2E_P_0,
2081   EVEX_W_0F2E_P_2,
2082   EVEX_W_0F2F_P_0,
2083   EVEX_W_0F2F_P_2,
2084   EVEX_W_0F51_P_0,
2085   EVEX_W_0F51_P_1,
2086   EVEX_W_0F51_P_2,
2087   EVEX_W_0F51_P_3,
2088   EVEX_W_0F54_P_0,
2089   EVEX_W_0F54_P_2,
2090   EVEX_W_0F55_P_0,
2091   EVEX_W_0F55_P_2,
2092   EVEX_W_0F56_P_0,
2093   EVEX_W_0F56_P_2,
2094   EVEX_W_0F57_P_0,
2095   EVEX_W_0F57_P_2,
2096   EVEX_W_0F58_P_0,
2097   EVEX_W_0F58_P_1,
2098   EVEX_W_0F58_P_2,
2099   EVEX_W_0F58_P_3,
2100   EVEX_W_0F59_P_0,
2101   EVEX_W_0F59_P_1,
2102   EVEX_W_0F59_P_2,
2103   EVEX_W_0F59_P_3,
2104   EVEX_W_0F5A_P_0,
2105   EVEX_W_0F5A_P_1,
2106   EVEX_W_0F5A_P_2,
2107   EVEX_W_0F5A_P_3,
2108   EVEX_W_0F5B_P_0,
2109   EVEX_W_0F5B_P_1,
2110   EVEX_W_0F5B_P_2,
2111   EVEX_W_0F5C_P_0,
2112   EVEX_W_0F5C_P_1,
2113   EVEX_W_0F5C_P_2,
2114   EVEX_W_0F5C_P_3,
2115   EVEX_W_0F5D_P_0,
2116   EVEX_W_0F5D_P_1,
2117   EVEX_W_0F5D_P_2,
2118   EVEX_W_0F5D_P_3,
2119   EVEX_W_0F5E_P_0,
2120   EVEX_W_0F5E_P_1,
2121   EVEX_W_0F5E_P_2,
2122   EVEX_W_0F5E_P_3,
2123   EVEX_W_0F5F_P_0,
2124   EVEX_W_0F5F_P_1,
2125   EVEX_W_0F5F_P_2,
2126   EVEX_W_0F5F_P_3,
2127   EVEX_W_0F62_P_2,
2128   EVEX_W_0F66_P_2,
2129   EVEX_W_0F6A_P_2,
2130   EVEX_W_0F6B_P_2,
2131   EVEX_W_0F6C_P_2,
2132   EVEX_W_0F6D_P_2,
2133   EVEX_W_0F6F_P_1,
2134   EVEX_W_0F6F_P_2,
2135   EVEX_W_0F6F_P_3,
2136   EVEX_W_0F70_P_2,
2137   EVEX_W_0F72_R_2_P_2,
2138   EVEX_W_0F72_R_6_P_2,
2139   EVEX_W_0F73_R_2_P_2,
2140   EVEX_W_0F73_R_6_P_2,
2141   EVEX_W_0F76_P_2,
2142   EVEX_W_0F78_P_0,
2143   EVEX_W_0F78_P_2,
2144   EVEX_W_0F79_P_0,
2145   EVEX_W_0F79_P_2,
2146   EVEX_W_0F7A_P_1,
2147   EVEX_W_0F7A_P_2,
2148   EVEX_W_0F7A_P_3,
2149   EVEX_W_0F7B_P_2,
2150   EVEX_W_0F7B_P_3,
2151   EVEX_W_0F7E_P_1,
2152   EVEX_W_0F7F_P_1,
2153   EVEX_W_0F7F_P_2,
2154   EVEX_W_0F7F_P_3,
2155   EVEX_W_0FC2_P_0,
2156   EVEX_W_0FC2_P_1,
2157   EVEX_W_0FC2_P_2,
2158   EVEX_W_0FC2_P_3,
2159   EVEX_W_0FC6_P_0,
2160   EVEX_W_0FC6_P_2,
2161   EVEX_W_0FD2_P_2,
2162   EVEX_W_0FD3_P_2,
2163   EVEX_W_0FD4_P_2,
2164   EVEX_W_0FD6_P_2,
2165   EVEX_W_0FE6_P_1,
2166   EVEX_W_0FE6_P_2,
2167   EVEX_W_0FE6_P_3,
2168   EVEX_W_0FE7_P_2,
2169   EVEX_W_0FF2_P_2,
2170   EVEX_W_0FF3_P_2,
2171   EVEX_W_0FF4_P_2,
2172   EVEX_W_0FFA_P_2,
2173   EVEX_W_0FFB_P_2,
2174   EVEX_W_0FFE_P_2,
2175   EVEX_W_0F380C_P_2,
2176   EVEX_W_0F380D_P_2,
2177   EVEX_W_0F3810_P_1,
2178   EVEX_W_0F3810_P_2,
2179   EVEX_W_0F3811_P_1,
2180   EVEX_W_0F3811_P_2,
2181   EVEX_W_0F3812_P_1,
2182   EVEX_W_0F3812_P_2,
2183   EVEX_W_0F3813_P_1,
2184   EVEX_W_0F3813_P_2,
2185   EVEX_W_0F3814_P_1,
2186   EVEX_W_0F3815_P_1,
2187   EVEX_W_0F3818_P_2,
2188   EVEX_W_0F3819_P_2,
2189   EVEX_W_0F381A_P_2,
2190   EVEX_W_0F381B_P_2,
2191   EVEX_W_0F381E_P_2,
2192   EVEX_W_0F381F_P_2,
2193   EVEX_W_0F3820_P_1,
2194   EVEX_W_0F3821_P_1,
2195   EVEX_W_0F3822_P_1,
2196   EVEX_W_0F3823_P_1,
2197   EVEX_W_0F3824_P_1,
2198   EVEX_W_0F3825_P_1,
2199   EVEX_W_0F3825_P_2,
2200   EVEX_W_0F3826_P_1,
2201   EVEX_W_0F3826_P_2,
2202   EVEX_W_0F3828_P_1,
2203   EVEX_W_0F3828_P_2,
2204   EVEX_W_0F3829_P_1,
2205   EVEX_W_0F3829_P_2,
2206   EVEX_W_0F382A_P_1,
2207   EVEX_W_0F382A_P_2,
2208   EVEX_W_0F382B_P_2,
2209   EVEX_W_0F3830_P_1,
2210   EVEX_W_0F3831_P_1,
2211   EVEX_W_0F3832_P_1,
2212   EVEX_W_0F3833_P_1,
2213   EVEX_W_0F3834_P_1,
2214   EVEX_W_0F3835_P_1,
2215   EVEX_W_0F3835_P_2,
2216   EVEX_W_0F3837_P_2,
2217   EVEX_W_0F3838_P_1,
2218   EVEX_W_0F3839_P_1,
2219   EVEX_W_0F383A_P_1,
2220   EVEX_W_0F3840_P_2,
2221   EVEX_W_0F3852_P_1,
2222   EVEX_W_0F3854_P_2,
2223   EVEX_W_0F3855_P_2,
2224   EVEX_W_0F3858_P_2,
2225   EVEX_W_0F3859_P_2,
2226   EVEX_W_0F385A_P_2,
2227   EVEX_W_0F385B_P_2,
2228   EVEX_W_0F3862_P_2,
2229   EVEX_W_0F3863_P_2,
2230   EVEX_W_0F3866_P_2,
2231   EVEX_W_0F3868_P_3,
2232   EVEX_W_0F3870_P_2,
2233   EVEX_W_0F3871_P_2,
2234   EVEX_W_0F3872_P_1,
2235   EVEX_W_0F3872_P_2,
2236   EVEX_W_0F3872_P_3,
2237   EVEX_W_0F3873_P_2,
2238   EVEX_W_0F3875_P_2,
2239   EVEX_W_0F3878_P_2,
2240   EVEX_W_0F3879_P_2,
2241   EVEX_W_0F387A_P_2,
2242   EVEX_W_0F387B_P_2,
2243   EVEX_W_0F387D_P_2,
2244   EVEX_W_0F3883_P_2,
2245   EVEX_W_0F388D_P_2,
2246   EVEX_W_0F3891_P_2,
2247   EVEX_W_0F3893_P_2,
2248   EVEX_W_0F38A1_P_2,
2249   EVEX_W_0F38A3_P_2,
2250   EVEX_W_0F38C7_R_1_P_2,
2251   EVEX_W_0F38C7_R_2_P_2,
2252   EVEX_W_0F38C7_R_5_P_2,
2253   EVEX_W_0F38C7_R_6_P_2,
2254
2255   EVEX_W_0F3A00_P_2,
2256   EVEX_W_0F3A01_P_2,
2257   EVEX_W_0F3A04_P_2,
2258   EVEX_W_0F3A05_P_2,
2259   EVEX_W_0F3A08_P_2,
2260   EVEX_W_0F3A09_P_2,
2261   EVEX_W_0F3A0A_P_2,
2262   EVEX_W_0F3A0B_P_2,
2263   EVEX_W_0F3A18_P_2,
2264   EVEX_W_0F3A19_P_2,
2265   EVEX_W_0F3A1A_P_2,
2266   EVEX_W_0F3A1B_P_2,
2267   EVEX_W_0F3A1D_P_2,
2268   EVEX_W_0F3A21_P_2,
2269   EVEX_W_0F3A23_P_2,
2270   EVEX_W_0F3A38_P_2,
2271   EVEX_W_0F3A39_P_2,
2272   EVEX_W_0F3A3A_P_2,
2273   EVEX_W_0F3A3B_P_2,
2274   EVEX_W_0F3A3E_P_2,
2275   EVEX_W_0F3A3F_P_2,
2276   EVEX_W_0F3A42_P_2,
2277   EVEX_W_0F3A43_P_2,
2278   EVEX_W_0F3A50_P_2,
2279   EVEX_W_0F3A51_P_2,
2280   EVEX_W_0F3A56_P_2,
2281   EVEX_W_0F3A57_P_2,
2282   EVEX_W_0F3A66_P_2,
2283   EVEX_W_0F3A67_P_2,
2284   EVEX_W_0F3A70_P_2,
2285   EVEX_W_0F3A71_P_2,
2286   EVEX_W_0F3A72_P_2,
2287   EVEX_W_0F3A73_P_2,
2288   EVEX_W_0F3ACE_P_2,
2289   EVEX_W_0F3ACF_P_2
2290 };
2291
2292 typedef void (*op_rtn) (int bytemode, int sizeflag);
2293
2294 struct dis386 {
2295   const char *name;
2296   struct
2297     {
2298       op_rtn rtn;
2299       int bytemode;
2300     } op[MAX_OPERANDS];
2301   unsigned int prefix_requirement;
2302 };
2303
2304 /* Upper case letters in the instruction names here are macros.
2305    'A' => print 'b' if no register operands or suffix_always is true
2306    'B' => print 'b' if suffix_always is true
2307    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2308           size prefix
2309    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2310           suffix_always is true
2311    'E' => print 'e' if 32-bit form of jcxz
2312    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2313    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2314    'H' => print ",pt" or ",pn" branch hint
2315    'I' => honor following macro letter even in Intel mode (implemented only
2316           for some of the macro letters)
2317    'J' => print 'l'
2318    'K' => print 'd' or 'q' if rex prefix is present.
2319    'L' => print 'l' if suffix_always is true
2320    'M' => print 'r' if intel_mnemonic is false.
2321    'N' => print 'n' if instruction has no wait "prefix"
2322    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2323    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2324           or suffix_always is true.  print 'q' if rex prefix is present.
2325    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2326           is true
2327    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2328    'S' => print 'w', 'l' or 'q' if suffix_always is true
2329    'T' => print 'q' in 64bit mode if instruction has no operand size
2330           prefix and behave as 'P' otherwise
2331    'U' => print 'q' in 64bit mode if instruction has no operand size
2332           prefix and behave as 'Q' otherwise
2333    'V' => print 'q' in 64bit mode if instruction has no operand size
2334           prefix and behave as 'S' otherwise
2335    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2336    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2337    'Y' unused.
2338    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2339    '!' => change condition from true to false or from false to true.
2340    '%' => add 1 upper case letter to the macro.
2341    '^' => print 'w' or 'l' depending on operand size prefix or
2342           suffix_always is true (lcall/ljmp).
2343    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2344           on operand size prefix.
2345    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2346           has no operand size prefix for AMD64 ISA, behave as 'P'
2347           otherwise
2348
2349    2 upper case letter macros:
2350    "XY" => print 'x' or 'y' if suffix_always is true or no register
2351            operands and no broadcast.
2352    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2353            register operands and no broadcast.
2354    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2355    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2356            or suffix_always is true
2357    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2358    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2359    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2360    "LW" => print 'd', 'q' depending on the VEX.W bit
2361    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2362            an operand size prefix, or suffix_always is true.  print
2363            'q' if rex prefix is present.
2364
2365    Many of the above letters print nothing in Intel mode.  See "putop"
2366    for the details.
2367
2368    Braces '{' and '}', and vertical bars '|', indicate alternative
2369    mnemonic strings for AT&T and Intel.  */
2370
2371 static const struct dis386 dis386[] = {
2372   /* 00 */
2373   { "addB",             { Ebh1, Gb }, 0 },
2374   { "addS",             { Evh1, Gv }, 0 },
2375   { "addB",             { Gb, EbS }, 0 },
2376   { "addS",             { Gv, EvS }, 0 },
2377   { "addB",             { AL, Ib }, 0 },
2378   { "addS",             { eAX, Iv }, 0 },
2379   { X86_64_TABLE (X86_64_06) },
2380   { X86_64_TABLE (X86_64_07) },
2381   /* 08 */
2382   { "orB",              { Ebh1, Gb }, 0 },
2383   { "orS",              { Evh1, Gv }, 0 },
2384   { "orB",              { Gb, EbS }, 0 },
2385   { "orS",              { Gv, EvS }, 0 },
2386   { "orB",              { AL, Ib }, 0 },
2387   { "orS",              { eAX, Iv }, 0 },
2388   { X86_64_TABLE (X86_64_0D) },
2389   { Bad_Opcode },       /* 0x0f extended opcode escape */
2390   /* 10 */
2391   { "adcB",             { Ebh1, Gb }, 0 },
2392   { "adcS",             { Evh1, Gv }, 0 },
2393   { "adcB",             { Gb, EbS }, 0 },
2394   { "adcS",             { Gv, EvS }, 0 },
2395   { "adcB",             { AL, Ib }, 0 },
2396   { "adcS",             { eAX, Iv }, 0 },
2397   { X86_64_TABLE (X86_64_16) },
2398   { X86_64_TABLE (X86_64_17) },
2399   /* 18 */
2400   { "sbbB",             { Ebh1, Gb }, 0 },
2401   { "sbbS",             { Evh1, Gv }, 0 },
2402   { "sbbB",             { Gb, EbS }, 0 },
2403   { "sbbS",             { Gv, EvS }, 0 },
2404   { "sbbB",             { AL, Ib }, 0 },
2405   { "sbbS",             { eAX, Iv }, 0 },
2406   { X86_64_TABLE (X86_64_1E) },
2407   { X86_64_TABLE (X86_64_1F) },
2408   /* 20 */
2409   { "andB",             { Ebh1, Gb }, 0 },
2410   { "andS",             { Evh1, Gv }, 0 },
2411   { "andB",             { Gb, EbS }, 0 },
2412   { "andS",             { Gv, EvS }, 0 },
2413   { "andB",             { AL, Ib }, 0 },
2414   { "andS",             { eAX, Iv }, 0 },
2415   { Bad_Opcode },       /* SEG ES prefix */
2416   { X86_64_TABLE (X86_64_27) },
2417   /* 28 */
2418   { "subB",             { Ebh1, Gb }, 0 },
2419   { "subS",             { Evh1, Gv }, 0 },
2420   { "subB",             { Gb, EbS }, 0 },
2421   { "subS",             { Gv, EvS }, 0 },
2422   { "subB",             { AL, Ib }, 0 },
2423   { "subS",             { eAX, Iv }, 0 },
2424   { Bad_Opcode },       /* SEG CS prefix */
2425   { X86_64_TABLE (X86_64_2F) },
2426   /* 30 */
2427   { "xorB",             { Ebh1, Gb }, 0 },
2428   { "xorS",             { Evh1, Gv }, 0 },
2429   { "xorB",             { Gb, EbS }, 0 },
2430   { "xorS",             { Gv, EvS }, 0 },
2431   { "xorB",             { AL, Ib }, 0 },
2432   { "xorS",             { eAX, Iv }, 0 },
2433   { Bad_Opcode },       /* SEG SS prefix */
2434   { X86_64_TABLE (X86_64_37) },
2435   /* 38 */
2436   { "cmpB",             { Eb, Gb }, 0 },
2437   { "cmpS",             { Ev, Gv }, 0 },
2438   { "cmpB",             { Gb, EbS }, 0 },
2439   { "cmpS",             { Gv, EvS }, 0 },
2440   { "cmpB",             { AL, Ib }, 0 },
2441   { "cmpS",             { eAX, Iv }, 0 },
2442   { Bad_Opcode },       /* SEG DS prefix */
2443   { X86_64_TABLE (X86_64_3F) },
2444   /* 40 */
2445   { "inc{S|}",          { RMeAX }, 0 },
2446   { "inc{S|}",          { RMeCX }, 0 },
2447   { "inc{S|}",          { RMeDX }, 0 },
2448   { "inc{S|}",          { RMeBX }, 0 },
2449   { "inc{S|}",          { RMeSP }, 0 },
2450   { "inc{S|}",          { RMeBP }, 0 },
2451   { "inc{S|}",          { RMeSI }, 0 },
2452   { "inc{S|}",          { RMeDI }, 0 },
2453   /* 48 */
2454   { "dec{S|}",          { RMeAX }, 0 },
2455   { "dec{S|}",          { RMeCX }, 0 },
2456   { "dec{S|}",          { RMeDX }, 0 },
2457   { "dec{S|}",          { RMeBX }, 0 },
2458   { "dec{S|}",          { RMeSP }, 0 },
2459   { "dec{S|}",          { RMeBP }, 0 },
2460   { "dec{S|}",          { RMeSI }, 0 },
2461   { "dec{S|}",          { RMeDI }, 0 },
2462   /* 50 */
2463   { "pushV",            { RMrAX }, 0 },
2464   { "pushV",            { RMrCX }, 0 },
2465   { "pushV",            { RMrDX }, 0 },
2466   { "pushV",            { RMrBX }, 0 },
2467   { "pushV",            { RMrSP }, 0 },
2468   { "pushV",            { RMrBP }, 0 },
2469   { "pushV",            { RMrSI }, 0 },
2470   { "pushV",            { RMrDI }, 0 },
2471   /* 58 */
2472   { "popV",             { RMrAX }, 0 },
2473   { "popV",             { RMrCX }, 0 },
2474   { "popV",             { RMrDX }, 0 },
2475   { "popV",             { RMrBX }, 0 },
2476   { "popV",             { RMrSP }, 0 },
2477   { "popV",             { RMrBP }, 0 },
2478   { "popV",             { RMrSI }, 0 },
2479   { "popV",             { RMrDI }, 0 },
2480   /* 60 */
2481   { X86_64_TABLE (X86_64_60) },
2482   { X86_64_TABLE (X86_64_61) },
2483   { X86_64_TABLE (X86_64_62) },
2484   { X86_64_TABLE (X86_64_63) },
2485   { Bad_Opcode },       /* seg fs */
2486   { Bad_Opcode },       /* seg gs */
2487   { Bad_Opcode },       /* op size prefix */
2488   { Bad_Opcode },       /* adr size prefix */
2489   /* 68 */
2490   { "pushT",            { sIv }, 0 },
2491   { "imulS",            { Gv, Ev, Iv }, 0 },
2492   { "pushT",            { sIbT }, 0 },
2493   { "imulS",            { Gv, Ev, sIb }, 0 },
2494   { "ins{b|}",          { Ybr, indirDX }, 0 },
2495   { X86_64_TABLE (X86_64_6D) },
2496   { "outs{b|}",         { indirDXr, Xb }, 0 },
2497   { X86_64_TABLE (X86_64_6F) },
2498   /* 70 */
2499   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2500   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2501   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2507   /* 78 */
2508   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2509   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2511   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2512   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2513   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2514   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2515   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2516   /* 80 */
2517   { REG_TABLE (REG_80) },
2518   { REG_TABLE (REG_81) },
2519   { X86_64_TABLE (X86_64_82) },
2520   { REG_TABLE (REG_83) },
2521   { "testB",            { Eb, Gb }, 0 },
2522   { "testS",            { Ev, Gv }, 0 },
2523   { "xchgB",            { Ebh2, Gb }, 0 },
2524   { "xchgS",            { Evh2, Gv }, 0 },
2525   /* 88 */
2526   { "movB",             { Ebh3, Gb }, 0 },
2527   { "movS",             { Evh3, Gv }, 0 },
2528   { "movB",             { Gb, EbS }, 0 },
2529   { "movS",             { Gv, EvS }, 0 },
2530   { "movD",             { Sv, Sw }, 0 },
2531   { MOD_TABLE (MOD_8D) },
2532   { "movD",             { Sw, Sv }, 0 },
2533   { REG_TABLE (REG_8F) },
2534   /* 90 */
2535   { PREFIX_TABLE (PREFIX_90) },
2536   { "xchgS",            { RMeCX, eAX }, 0 },
2537   { "xchgS",            { RMeDX, eAX }, 0 },
2538   { "xchgS",            { RMeBX, eAX }, 0 },
2539   { "xchgS",            { RMeSP, eAX }, 0 },
2540   { "xchgS",            { RMeBP, eAX }, 0 },
2541   { "xchgS",            { RMeSI, eAX }, 0 },
2542   { "xchgS",            { RMeDI, eAX }, 0 },
2543   /* 98 */
2544   { "cW{t|}R",          { XX }, 0 },
2545   { "cR{t|}O",          { XX }, 0 },
2546   { X86_64_TABLE (X86_64_9A) },
2547   { Bad_Opcode },       /* fwait */
2548   { "pushfT",           { XX }, 0 },
2549   { "popfT",            { XX }, 0 },
2550   { "sahf",             { XX }, 0 },
2551   { "lahf",             { XX }, 0 },
2552   /* a0 */
2553   { "mov%LB",           { AL, Ob }, 0 },
2554   { "mov%LS",           { eAX, Ov }, 0 },
2555   { "mov%LB",           { Ob, AL }, 0 },
2556   { "mov%LS",           { Ov, eAX }, 0 },
2557   { "movs{b|}",         { Ybr, Xb }, 0 },
2558   { "movs{R|}",         { Yvr, Xv }, 0 },
2559   { "cmps{b|}",         { Xb, Yb }, 0 },
2560   { "cmps{R|}",         { Xv, Yv }, 0 },
2561   /* a8 */
2562   { "testB",            { AL, Ib }, 0 },
2563   { "testS",            { eAX, Iv }, 0 },
2564   { "stosB",            { Ybr, AL }, 0 },
2565   { "stosS",            { Yvr, eAX }, 0 },
2566   { "lodsB",            { ALr, Xb }, 0 },
2567   { "lodsS",            { eAXr, Xv }, 0 },
2568   { "scasB",            { AL, Yb }, 0 },
2569   { "scasS",            { eAX, Yv }, 0 },
2570   /* b0 */
2571   { "movB",             { RMAL, Ib }, 0 },
2572   { "movB",             { RMCL, Ib }, 0 },
2573   { "movB",             { RMDL, Ib }, 0 },
2574   { "movB",             { RMBL, Ib }, 0 },
2575   { "movB",             { RMAH, Ib }, 0 },
2576   { "movB",             { RMCH, Ib }, 0 },
2577   { "movB",             { RMDH, Ib }, 0 },
2578   { "movB",             { RMBH, Ib }, 0 },
2579   /* b8 */
2580   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2581   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2582   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2583   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2584   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2585   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2586   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2587   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2588   /* c0 */
2589   { REG_TABLE (REG_C0) },
2590   { REG_TABLE (REG_C1) },
2591   { "retT",             { Iw, BND }, 0 },
2592   { "retT",             { BND }, 0 },
2593   { X86_64_TABLE (X86_64_C4) },
2594   { X86_64_TABLE (X86_64_C5) },
2595   { REG_TABLE (REG_C6) },
2596   { REG_TABLE (REG_C7) },
2597   /* c8 */
2598   { "enterT",           { Iw, Ib }, 0 },
2599   { "leaveT",           { XX }, 0 },
2600   { "Jret{|f}P",        { Iw }, 0 },
2601   { "Jret{|f}P",        { XX }, 0 },
2602   { "int3",             { XX }, 0 },
2603   { "int",              { Ib }, 0 },
2604   { X86_64_TABLE (X86_64_CE) },
2605   { "iret%LP",          { XX }, 0 },
2606   /* d0 */
2607   { REG_TABLE (REG_D0) },
2608   { REG_TABLE (REG_D1) },
2609   { REG_TABLE (REG_D2) },
2610   { REG_TABLE (REG_D3) },
2611   { X86_64_TABLE (X86_64_D4) },
2612   { X86_64_TABLE (X86_64_D5) },
2613   { Bad_Opcode },
2614   { "xlat",             { DSBX }, 0 },
2615   /* d8 */
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   { FLOAT },
2621   { FLOAT },
2622   { FLOAT },
2623   { FLOAT },
2624   /* e0 */
2625   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2626   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2627   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2628   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2629   { "inB",              { AL, Ib }, 0 },
2630   { "inG",              { zAX, Ib }, 0 },
2631   { "outB",             { Ib, AL }, 0 },
2632   { "outG",             { Ib, zAX }, 0 },
2633   /* e8 */
2634   { X86_64_TABLE (X86_64_E8) },
2635   { X86_64_TABLE (X86_64_E9) },
2636   { X86_64_TABLE (X86_64_EA) },
2637   { "jmp",              { Jb, BND }, 0 },
2638   { "inB",              { AL, indirDX }, 0 },
2639   { "inG",              { zAX, indirDX }, 0 },
2640   { "outB",             { indirDX, AL }, 0 },
2641   { "outG",             { indirDX, zAX }, 0 },
2642   /* f0 */
2643   { Bad_Opcode },       /* lock prefix */
2644   { "icebp",            { XX }, 0 },
2645   { Bad_Opcode },       /* repne */
2646   { Bad_Opcode },       /* repz */
2647   { "hlt",              { XX }, 0 },
2648   { "cmc",              { XX }, 0 },
2649   { REG_TABLE (REG_F6) },
2650   { REG_TABLE (REG_F7) },
2651   /* f8 */
2652   { "clc",              { XX }, 0 },
2653   { "stc",              { XX }, 0 },
2654   { "cli",              { XX }, 0 },
2655   { "sti",              { XX }, 0 },
2656   { "cld",              { XX }, 0 },
2657   { "std",              { XX }, 0 },
2658   { REG_TABLE (REG_FE) },
2659   { REG_TABLE (REG_FF) },
2660 };
2661
2662 static const struct dis386 dis386_twobyte[] = {
2663   /* 00 */
2664   { REG_TABLE (REG_0F00 ) },
2665   { REG_TABLE (REG_0F01 ) },
2666   { "larS",             { Gv, Ew }, 0 },
2667   { "lslS",             { Gv, Ew }, 0 },
2668   { Bad_Opcode },
2669   { "syscall",          { XX }, 0 },
2670   { "clts",             { XX }, 0 },
2671   { "sysret%LP",                { XX }, 0 },
2672   /* 08 */
2673   { "invd",             { XX }, 0 },
2674   { PREFIX_TABLE (PREFIX_0F09) },
2675   { Bad_Opcode },
2676   { "ud2",              { XX }, 0 },
2677   { Bad_Opcode },
2678   { REG_TABLE (REG_0F0D) },
2679   { "femms",            { XX }, 0 },
2680   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2681   /* 10 */
2682   { PREFIX_TABLE (PREFIX_0F10) },
2683   { PREFIX_TABLE (PREFIX_0F11) },
2684   { PREFIX_TABLE (PREFIX_0F12) },
2685   { MOD_TABLE (MOD_0F13) },
2686   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2687   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2688   { PREFIX_TABLE (PREFIX_0F16) },
2689   { MOD_TABLE (MOD_0F17) },
2690   /* 18 */
2691   { REG_TABLE (REG_0F18) },
2692   { "nopQ",             { Ev }, 0 },
2693   { PREFIX_TABLE (PREFIX_0F1A) },
2694   { PREFIX_TABLE (PREFIX_0F1B) },
2695   { PREFIX_TABLE (PREFIX_0F1C) },
2696   { "nopQ",             { Ev }, 0 },
2697   { PREFIX_TABLE (PREFIX_0F1E) },
2698   { "nopQ",             { Ev }, 0 },
2699   /* 20 */
2700   { "movZ",             { Rm, Cm }, 0 },
2701   { "movZ",             { Rm, Dm }, 0 },
2702   { "movZ",             { Cm, Rm }, 0 },
2703   { "movZ",             { Dm, Rm }, 0 },
2704   { MOD_TABLE (MOD_0F24) },
2705   { Bad_Opcode },
2706   { MOD_TABLE (MOD_0F26) },
2707   { Bad_Opcode },
2708   /* 28 */
2709   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2710   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2711   { PREFIX_TABLE (PREFIX_0F2A) },
2712   { PREFIX_TABLE (PREFIX_0F2B) },
2713   { PREFIX_TABLE (PREFIX_0F2C) },
2714   { PREFIX_TABLE (PREFIX_0F2D) },
2715   { PREFIX_TABLE (PREFIX_0F2E) },
2716   { PREFIX_TABLE (PREFIX_0F2F) },
2717   /* 30 */
2718   { "wrmsr",            { XX }, 0 },
2719   { "rdtsc",            { XX }, 0 },
2720   { "rdmsr",            { XX }, 0 },
2721   { "rdpmc",            { XX }, 0 },
2722   { "sysenter",         { XX }, 0 },
2723   { "sysexit",          { XX }, 0 },
2724   { Bad_Opcode },
2725   { "getsec",           { XX }, 0 },
2726   /* 38 */
2727   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2728   { Bad_Opcode },
2729   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2730   { Bad_Opcode },
2731   { Bad_Opcode },
2732   { Bad_Opcode },
2733   { Bad_Opcode },
2734   { Bad_Opcode },
2735   /* 40 */
2736   { "cmovoS",           { Gv, Ev }, 0 },
2737   { "cmovnoS",          { Gv, Ev }, 0 },
2738   { "cmovbS",           { Gv, Ev }, 0 },
2739   { "cmovaeS",          { Gv, Ev }, 0 },
2740   { "cmoveS",           { Gv, Ev }, 0 },
2741   { "cmovneS",          { Gv, Ev }, 0 },
2742   { "cmovbeS",          { Gv, Ev }, 0 },
2743   { "cmovaS",           { Gv, Ev }, 0 },
2744   /* 48 */
2745   { "cmovsS",           { Gv, Ev }, 0 },
2746   { "cmovnsS",          { Gv, Ev }, 0 },
2747   { "cmovpS",           { Gv, Ev }, 0 },
2748   { "cmovnpS",          { Gv, Ev }, 0 },
2749   { "cmovlS",           { Gv, Ev }, 0 },
2750   { "cmovgeS",          { Gv, Ev }, 0 },
2751   { "cmovleS",          { Gv, Ev }, 0 },
2752   { "cmovgS",           { Gv, Ev }, 0 },
2753   /* 50 */
2754   { MOD_TABLE (MOD_0F51) },
2755   { PREFIX_TABLE (PREFIX_0F51) },
2756   { PREFIX_TABLE (PREFIX_0F52) },
2757   { PREFIX_TABLE (PREFIX_0F53) },
2758   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2759   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2760   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2761   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2762   /* 58 */
2763   { PREFIX_TABLE (PREFIX_0F58) },
2764   { PREFIX_TABLE (PREFIX_0F59) },
2765   { PREFIX_TABLE (PREFIX_0F5A) },
2766   { PREFIX_TABLE (PREFIX_0F5B) },
2767   { PREFIX_TABLE (PREFIX_0F5C) },
2768   { PREFIX_TABLE (PREFIX_0F5D) },
2769   { PREFIX_TABLE (PREFIX_0F5E) },
2770   { PREFIX_TABLE (PREFIX_0F5F) },
2771   /* 60 */
2772   { PREFIX_TABLE (PREFIX_0F60) },
2773   { PREFIX_TABLE (PREFIX_0F61) },
2774   { PREFIX_TABLE (PREFIX_0F62) },
2775   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2776   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2777   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2778   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2779   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2780   /* 68 */
2781   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2782   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2783   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2784   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2785   { PREFIX_TABLE (PREFIX_0F6C) },
2786   { PREFIX_TABLE (PREFIX_0F6D) },
2787   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2788   { PREFIX_TABLE (PREFIX_0F6F) },
2789   /* 70 */
2790   { PREFIX_TABLE (PREFIX_0F70) },
2791   { REG_TABLE (REG_0F71) },
2792   { REG_TABLE (REG_0F72) },
2793   { REG_TABLE (REG_0F73) },
2794   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2795   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2796   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2797   { "emms",             { XX }, PREFIX_OPCODE },
2798   /* 78 */
2799   { PREFIX_TABLE (PREFIX_0F78) },
2800   { PREFIX_TABLE (PREFIX_0F79) },
2801   { Bad_Opcode },
2802   { Bad_Opcode },
2803   { PREFIX_TABLE (PREFIX_0F7C) },
2804   { PREFIX_TABLE (PREFIX_0F7D) },
2805   { PREFIX_TABLE (PREFIX_0F7E) },
2806   { PREFIX_TABLE (PREFIX_0F7F) },
2807   /* 80 */
2808   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2809   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2810   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2816   /* 88 */
2817   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2818   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2820   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2821   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2822   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2823   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2824   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2825   /* 90 */
2826   { "seto",             { Eb }, 0 },
2827   { "setno",            { Eb }, 0 },
2828   { "setb",             { Eb }, 0 },
2829   { "setae",            { Eb }, 0 },
2830   { "sete",             { Eb }, 0 },
2831   { "setne",            { Eb }, 0 },
2832   { "setbe",            { Eb }, 0 },
2833   { "seta",             { Eb }, 0 },
2834   /* 98 */
2835   { "sets",             { Eb }, 0 },
2836   { "setns",            { Eb }, 0 },
2837   { "setp",             { Eb }, 0 },
2838   { "setnp",            { Eb }, 0 },
2839   { "setl",             { Eb }, 0 },
2840   { "setge",            { Eb }, 0 },
2841   { "setle",            { Eb }, 0 },
2842   { "setg",             { Eb }, 0 },
2843   /* a0 */
2844   { "pushT",            { fs }, 0 },
2845   { "popT",             { fs }, 0 },
2846   { "cpuid",            { XX }, 0 },
2847   { "btS",              { Ev, Gv }, 0 },
2848   { "shldS",            { Ev, Gv, Ib }, 0 },
2849   { "shldS",            { Ev, Gv, CL }, 0 },
2850   { REG_TABLE (REG_0FA6) },
2851   { REG_TABLE (REG_0FA7) },
2852   /* a8 */
2853   { "pushT",            { gs }, 0 },
2854   { "popT",             { gs }, 0 },
2855   { "rsm",              { XX }, 0 },
2856   { "btsS",             { Evh1, Gv }, 0 },
2857   { "shrdS",            { Ev, Gv, Ib }, 0 },
2858   { "shrdS",            { Ev, Gv, CL }, 0 },
2859   { REG_TABLE (REG_0FAE) },
2860   { "imulS",            { Gv, Ev }, 0 },
2861   /* b0 */
2862   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2863   { "cmpxchgS",         { Evh1, Gv }, 0 },
2864   { MOD_TABLE (MOD_0FB2) },
2865   { "btrS",             { Evh1, Gv }, 0 },
2866   { MOD_TABLE (MOD_0FB4) },
2867   { MOD_TABLE (MOD_0FB5) },
2868   { "movz{bR|x}",       { Gv, Eb }, 0 },
2869   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2870   /* b8 */
2871   { PREFIX_TABLE (PREFIX_0FB8) },
2872   { "ud1S",             { Gv, Ev }, 0 },
2873   { REG_TABLE (REG_0FBA) },
2874   { "btcS",             { Evh1, Gv }, 0 },
2875   { PREFIX_TABLE (PREFIX_0FBC) },
2876   { PREFIX_TABLE (PREFIX_0FBD) },
2877   { "movs{bR|x}",       { Gv, Eb }, 0 },
2878   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2879   /* c0 */
2880   { "xaddB",            { Ebh1, Gb }, 0 },
2881   { "xaddS",            { Evh1, Gv }, 0 },
2882   { PREFIX_TABLE (PREFIX_0FC2) },
2883   { MOD_TABLE (MOD_0FC3) },
2884   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2885   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2886   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2887   { REG_TABLE (REG_0FC7) },
2888   /* c8 */
2889   { "bswap",            { RMeAX }, 0 },
2890   { "bswap",            { RMeCX }, 0 },
2891   { "bswap",            { RMeDX }, 0 },
2892   { "bswap",            { RMeBX }, 0 },
2893   { "bswap",            { RMeSP }, 0 },
2894   { "bswap",            { RMeBP }, 0 },
2895   { "bswap",            { RMeSI }, 0 },
2896   { "bswap",            { RMeDI }, 0 },
2897   /* d0 */
2898   { PREFIX_TABLE (PREFIX_0FD0) },
2899   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2900   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2901   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2902   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2903   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2904   { PREFIX_TABLE (PREFIX_0FD6) },
2905   { MOD_TABLE (MOD_0FD7) },
2906   /* d8 */
2907   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2908   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2909   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2910   { "pand",             { MX, EM }, PREFIX_OPCODE },
2911   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2912   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2914   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2915   /* e0 */
2916   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2917   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2918   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2919   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2920   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2921   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2922   { PREFIX_TABLE (PREFIX_0FE6) },
2923   { PREFIX_TABLE (PREFIX_0FE7) },
2924   /* e8 */
2925   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2926   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2927   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2928   { "por",              { MX, EM }, PREFIX_OPCODE },
2929   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2930   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2931   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2932   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2933   /* f0 */
2934   { PREFIX_TABLE (PREFIX_0FF0) },
2935   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2936   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2937   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2938   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2939   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2940   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2941   { PREFIX_TABLE (PREFIX_0FF7) },
2942   /* f8 */
2943   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2944   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2945   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2946   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2947   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2948   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2949   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2950   { "ud0S",             { Gv, Ev }, 0 },
2951 };
2952
2953 static const unsigned char onebyte_has_modrm[256] = {
2954   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2955   /*       -------------------------------        */
2956   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2957   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2958   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2959   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2960   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2961   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2962   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2963   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2964   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2965   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2966   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2967   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2968   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2969   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2970   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2971   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2972   /*       -------------------------------        */
2973   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2974 };
2975
2976 static const unsigned char twobyte_has_modrm[256] = {
2977   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2978   /*       -------------------------------        */
2979   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2980   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2981   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2982   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2983   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2984   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2985   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2986   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2987   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2988   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2989   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2990   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2991   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2992   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2993   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2994   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2995   /*       -------------------------------        */
2996   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2997 };
2998
2999 static char obuf[100];
3000 static char *obufp;
3001 static char *mnemonicendp;
3002 static char scratchbuf[100];
3003 static unsigned char *start_codep;
3004 static unsigned char *insn_codep;
3005 static unsigned char *codep;
3006 static unsigned char *end_codep;
3007 static int last_lock_prefix;
3008 static int last_repz_prefix;
3009 static int last_repnz_prefix;
3010 static int last_data_prefix;
3011 static int last_addr_prefix;
3012 static int last_rex_prefix;
3013 static int last_seg_prefix;
3014 static int fwait_prefix;
3015 /* The active segment register prefix.  */
3016 static int active_seg_prefix;
3017 #define MAX_CODE_LENGTH 15
3018 /* We can up to 14 prefixes since the maximum instruction length is
3019    15bytes.  */
3020 static int all_prefixes[MAX_CODE_LENGTH - 1];
3021 static disassemble_info *the_info;
3022 static struct
3023   {
3024     int mod;
3025     int reg;
3026     int rm;
3027   }
3028 modrm;
3029 static unsigned char need_modrm;
3030 static struct
3031   {
3032     int scale;
3033     int index;
3034     int base;
3035   }
3036 sib;
3037 static struct
3038   {
3039     int register_specifier;
3040     int length;
3041     int prefix;
3042     int w;
3043     int evex;
3044     int r;
3045     int v;
3046     int mask_register_specifier;
3047     int zeroing;
3048     int ll;
3049     int b;
3050   }
3051 vex;
3052 static unsigned char need_vex;
3053 static unsigned char need_vex_reg;
3054 static unsigned char vex_w_done;
3055
3056 struct op
3057   {
3058     const char *name;
3059     unsigned int len;
3060   };
3061
3062 /* If we are accessing mod/rm/reg without need_modrm set, then the
3063    values are stale.  Hitting this abort likely indicates that you
3064    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3065 #define MODRM_CHECK  if (!need_modrm) abort ()
3066
3067 static const char **names64;
3068 static const char **names32;
3069 static const char **names16;
3070 static const char **names8;
3071 static const char **names8rex;
3072 static const char **names_seg;
3073 static const char *index64;
3074 static const char *index32;
3075 static const char **index16;
3076 static const char **names_bnd;
3077
3078 static const char *intel_names64[] = {
3079   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3080   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3081 };
3082 static const char *intel_names32[] = {
3083   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3084   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3085 };
3086 static const char *intel_names16[] = {
3087   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3088   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3089 };
3090 static const char *intel_names8[] = {
3091   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3092 };
3093 static const char *intel_names8rex[] = {
3094   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3095   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3096 };
3097 static const char *intel_names_seg[] = {
3098   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3099 };
3100 static const char *intel_index64 = "riz";
3101 static const char *intel_index32 = "eiz";
3102 static const char *intel_index16[] = {
3103   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3104 };
3105
3106 static const char *att_names64[] = {
3107   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3108   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3109 };
3110 static const char *att_names32[] = {
3111   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3112   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3113 };
3114 static const char *att_names16[] = {
3115   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3116   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3117 };
3118 static const char *att_names8[] = {
3119   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3120 };
3121 static const char *att_names8rex[] = {
3122   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3123   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3124 };
3125 static const char *att_names_seg[] = {
3126   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3127 };
3128 static const char *att_index64 = "%riz";
3129 static const char *att_index32 = "%eiz";
3130 static const char *att_index16[] = {
3131   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3132 };
3133
3134 static const char **names_mm;
3135 static const char *intel_names_mm[] = {
3136   "mm0", "mm1", "mm2", "mm3",
3137   "mm4", "mm5", "mm6", "mm7"
3138 };
3139 static const char *att_names_mm[] = {
3140   "%mm0", "%mm1", "%mm2", "%mm3",
3141   "%mm4", "%mm5", "%mm6", "%mm7"
3142 };
3143
3144 static const char *intel_names_bnd[] = {
3145   "bnd0", "bnd1", "bnd2", "bnd3"
3146 };
3147
3148 static const char *att_names_bnd[] = {
3149   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3150 };
3151
3152 static const char **names_xmm;
3153 static const char *intel_names_xmm[] = {
3154   "xmm0", "xmm1", "xmm2", "xmm3",
3155   "xmm4", "xmm5", "xmm6", "xmm7",
3156   "xmm8", "xmm9", "xmm10", "xmm11",
3157   "xmm12", "xmm13", "xmm14", "xmm15",
3158   "xmm16", "xmm17", "xmm18", "xmm19",
3159   "xmm20", "xmm21", "xmm22", "xmm23",
3160   "xmm24", "xmm25", "xmm26", "xmm27",
3161   "xmm28", "xmm29", "xmm30", "xmm31"
3162 };
3163 static const char *att_names_xmm[] = {
3164   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3165   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3166   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3167   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3168   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3169   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3170   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3171   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3172 };
3173
3174 static const char **names_ymm;
3175 static const char *intel_names_ymm[] = {
3176   "ymm0", "ymm1", "ymm2", "ymm3",
3177   "ymm4", "ymm5", "ymm6", "ymm7",
3178   "ymm8", "ymm9", "ymm10", "ymm11",
3179   "ymm12", "ymm13", "ymm14", "ymm15",
3180   "ymm16", "ymm17", "ymm18", "ymm19",
3181   "ymm20", "ymm21", "ymm22", "ymm23",
3182   "ymm24", "ymm25", "ymm26", "ymm27",
3183   "ymm28", "ymm29", "ymm30", "ymm31"
3184 };
3185 static const char *att_names_ymm[] = {
3186   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3187   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3188   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3189   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3190   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3191   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3192   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3193   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3194 };
3195
3196 static const char **names_zmm;
3197 static const char *intel_names_zmm[] = {
3198   "zmm0", "zmm1", "zmm2", "zmm3",
3199   "zmm4", "zmm5", "zmm6", "zmm7",
3200   "zmm8", "zmm9", "zmm10", "zmm11",
3201   "zmm12", "zmm13", "zmm14", "zmm15",
3202   "zmm16", "zmm17", "zmm18", "zmm19",
3203   "zmm20", "zmm21", "zmm22", "zmm23",
3204   "zmm24", "zmm25", "zmm26", "zmm27",
3205   "zmm28", "zmm29", "zmm30", "zmm31"
3206 };
3207 static const char *att_names_zmm[] = {
3208   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3209   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3210   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3211   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3212   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3213   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3214   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3215   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3216 };
3217
3218 static const char **names_mask;
3219 static const char *intel_names_mask[] = {
3220   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3221 };
3222 static const char *att_names_mask[] = {
3223   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3224 };
3225
3226 static const char *names_rounding[] =
3227 {
3228   "{rn-sae}",
3229   "{rd-sae}",
3230   "{ru-sae}",
3231   "{rz-sae}"
3232 };
3233
3234 static const struct dis386 reg_table[][8] = {
3235   /* REG_80 */
3236   {
3237     { "addA",   { Ebh1, Ib }, 0 },
3238     { "orA",    { Ebh1, Ib }, 0 },
3239     { "adcA",   { Ebh1, Ib }, 0 },
3240     { "sbbA",   { Ebh1, Ib }, 0 },
3241     { "andA",   { Ebh1, Ib }, 0 },
3242     { "subA",   { Ebh1, Ib }, 0 },
3243     { "xorA",   { Ebh1, Ib }, 0 },
3244     { "cmpA",   { Eb, Ib }, 0 },
3245   },
3246   /* REG_81 */
3247   {
3248     { "addQ",   { Evh1, Iv }, 0 },
3249     { "orQ",    { Evh1, Iv }, 0 },
3250     { "adcQ",   { Evh1, Iv }, 0 },
3251     { "sbbQ",   { Evh1, Iv }, 0 },
3252     { "andQ",   { Evh1, Iv }, 0 },
3253     { "subQ",   { Evh1, Iv }, 0 },
3254     { "xorQ",   { Evh1, Iv }, 0 },
3255     { "cmpQ",   { Ev, Iv }, 0 },
3256   },
3257   /* REG_83 */
3258   {
3259     { "addQ",   { Evh1, sIb }, 0 },
3260     { "orQ",    { Evh1, sIb }, 0 },
3261     { "adcQ",   { Evh1, sIb }, 0 },
3262     { "sbbQ",   { Evh1, sIb }, 0 },
3263     { "andQ",   { Evh1, sIb }, 0 },
3264     { "subQ",   { Evh1, sIb }, 0 },
3265     { "xorQ",   { Evh1, sIb }, 0 },
3266     { "cmpQ",   { Ev, sIb }, 0 },
3267   },
3268   /* REG_8F */
3269   {
3270     { "popU",   { stackEv }, 0 },
3271     { XOP_8F_TABLE (XOP_09) },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { XOP_8F_TABLE (XOP_09) },
3276   },
3277   /* REG_C0 */
3278   {
3279     { "rolA",   { Eb, Ib }, 0 },
3280     { "rorA",   { Eb, Ib }, 0 },
3281     { "rclA",   { Eb, Ib }, 0 },
3282     { "rcrA",   { Eb, Ib }, 0 },
3283     { "shlA",   { Eb, Ib }, 0 },
3284     { "shrA",   { Eb, Ib }, 0 },
3285     { "shlA",   { Eb, Ib }, 0 },
3286     { "sarA",   { Eb, Ib }, 0 },
3287   },
3288   /* REG_C1 */
3289   {
3290     { "rolQ",   { Ev, Ib }, 0 },
3291     { "rorQ",   { Ev, Ib }, 0 },
3292     { "rclQ",   { Ev, Ib }, 0 },
3293     { "rcrQ",   { Ev, Ib }, 0 },
3294     { "shlQ",   { Ev, Ib }, 0 },
3295     { "shrQ",   { Ev, Ib }, 0 },
3296     { "shlQ",   { Ev, Ib }, 0 },
3297     { "sarQ",   { Ev, Ib }, 0 },
3298   },
3299   /* REG_C6 */
3300   {
3301     { "movA",   { Ebh3, Ib }, 0 },
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_C6_REG_7) },
3309   },
3310   /* REG_C7 */
3311   {
3312     { "movQ",   { Evh3, Iv }, 0 },
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { Bad_Opcode },
3319     { MOD_TABLE (MOD_C7_REG_7) },
3320   },
3321   /* REG_D0 */
3322   {
3323     { "rolA",   { Eb, I1 }, 0 },
3324     { "rorA",   { Eb, I1 }, 0 },
3325     { "rclA",   { Eb, I1 }, 0 },
3326     { "rcrA",   { Eb, I1 }, 0 },
3327     { "shlA",   { Eb, I1 }, 0 },
3328     { "shrA",   { Eb, I1 }, 0 },
3329     { "shlA",   { Eb, I1 }, 0 },
3330     { "sarA",   { Eb, I1 }, 0 },
3331   },
3332   /* REG_D1 */
3333   {
3334     { "rolQ",   { Ev, I1 }, 0 },
3335     { "rorQ",   { Ev, I1 }, 0 },
3336     { "rclQ",   { Ev, I1 }, 0 },
3337     { "rcrQ",   { Ev, I1 }, 0 },
3338     { "shlQ",   { Ev, I1 }, 0 },
3339     { "shrQ",   { Ev, I1 }, 0 },
3340     { "shlQ",   { Ev, I1 }, 0 },
3341     { "sarQ",   { Ev, I1 }, 0 },
3342   },
3343   /* REG_D2 */
3344   {
3345     { "rolA",   { Eb, CL }, 0 },
3346     { "rorA",   { Eb, CL }, 0 },
3347     { "rclA",   { Eb, CL }, 0 },
3348     { "rcrA",   { Eb, CL }, 0 },
3349     { "shlA",   { Eb, CL }, 0 },
3350     { "shrA",   { Eb, CL }, 0 },
3351     { "shlA",   { Eb, CL }, 0 },
3352     { "sarA",   { Eb, CL }, 0 },
3353   },
3354   /* REG_D3 */
3355   {
3356     { "rolQ",   { Ev, CL }, 0 },
3357     { "rorQ",   { Ev, CL }, 0 },
3358     { "rclQ",   { Ev, CL }, 0 },
3359     { "rcrQ",   { Ev, CL }, 0 },
3360     { "shlQ",   { Ev, CL }, 0 },
3361     { "shrQ",   { Ev, CL }, 0 },
3362     { "shlQ",   { Ev, CL }, 0 },
3363     { "sarQ",   { Ev, CL }, 0 },
3364   },
3365   /* REG_F6 */
3366   {
3367     { "testA",  { Eb, Ib }, 0 },
3368     { "testA",  { Eb, Ib }, 0 },
3369     { "notA",   { Ebh1 }, 0 },
3370     { "negA",   { Ebh1 }, 0 },
3371     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3372     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3373     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3374     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3375   },
3376   /* REG_F7 */
3377   {
3378     { "testQ",  { Ev, Iv }, 0 },
3379     { "testQ",  { Ev, Iv }, 0 },
3380     { "notQ",   { Evh1 }, 0 },
3381     { "negQ",   { Evh1 }, 0 },
3382     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3383     { "imulQ",  { Ev }, 0 },
3384     { "divQ",   { Ev }, 0 },
3385     { "idivQ",  { Ev }, 0 },
3386   },
3387   /* REG_FE */
3388   {
3389     { "incA",   { Ebh1 }, 0 },
3390     { "decA",   { Ebh1 }, 0 },
3391   },
3392   /* REG_FF */
3393   {
3394     { "incQ",   { Evh1 }, 0 },
3395     { "decQ",   { Evh1 }, 0 },
3396     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3397     { MOD_TABLE (MOD_FF_REG_3) },
3398     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3399     { MOD_TABLE (MOD_FF_REG_5) },
3400     { "pushU",  { stackEv }, 0 },
3401     { Bad_Opcode },
3402   },
3403   /* REG_0F00 */
3404   {
3405     { "sldtD",  { Sv }, 0 },
3406     { "strD",   { Sv }, 0 },
3407     { "lldt",   { Ew }, 0 },
3408     { "ltr",    { Ew }, 0 },
3409     { "verr",   { Ew }, 0 },
3410     { "verw",   { Ew }, 0 },
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413   },
3414   /* REG_0F01 */
3415   {
3416     { MOD_TABLE (MOD_0F01_REG_0) },
3417     { MOD_TABLE (MOD_0F01_REG_1) },
3418     { MOD_TABLE (MOD_0F01_REG_2) },
3419     { MOD_TABLE (MOD_0F01_REG_3) },
3420     { "smswD",  { Sv }, 0 },
3421     { MOD_TABLE (MOD_0F01_REG_5) },
3422     { "lmsw",   { Ew }, 0 },
3423     { MOD_TABLE (MOD_0F01_REG_7) },
3424   },
3425   /* REG_0F0D */
3426   {
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetchw",      { Mb }, 0 },
3429     { "prefetchwt1",    { Mb }, 0 },
3430     { "prefetch",       { Mb }, 0 },
3431     { "prefetch",       { Mb }, 0 },
3432     { "prefetch",       { Mb }, 0 },
3433     { "prefetch",       { Mb }, 0 },
3434     { "prefetch",       { Mb }, 0 },
3435   },
3436   /* REG_0F18 */
3437   {
3438     { MOD_TABLE (MOD_0F18_REG_0) },
3439     { MOD_TABLE (MOD_0F18_REG_1) },
3440     { MOD_TABLE (MOD_0F18_REG_2) },
3441     { MOD_TABLE (MOD_0F18_REG_3) },
3442     { MOD_TABLE (MOD_0F18_REG_4) },
3443     { MOD_TABLE (MOD_0F18_REG_5) },
3444     { MOD_TABLE (MOD_0F18_REG_6) },
3445     { MOD_TABLE (MOD_0F18_REG_7) },
3446   },
3447   /* REG_0F1C_MOD_0 */
3448   {
3449     { "cldemote",       { Mb }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452     { "nopQ",           { Ev }, 0 },
3453     { "nopQ",           { Ev }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457   },
3458   /* REG_0F1E_MOD_3 */
3459   {
3460     { "nopQ",           { Ev }, 0 },
3461     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3462     { "nopQ",           { Ev }, 0 },
3463     { "nopQ",           { Ev }, 0 },
3464     { "nopQ",           { Ev }, 0 },
3465     { "nopQ",           { Ev }, 0 },
3466     { "nopQ",           { Ev }, 0 },
3467     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3468   },
3469   /* REG_0F71 */
3470   {
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { MOD_TABLE (MOD_0F71_REG_2) },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0F71_REG_4) },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F71_REG_6) },
3478   },
3479   /* REG_0F72 */
3480   {
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483     { MOD_TABLE (MOD_0F72_REG_2) },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_0F72_REG_4) },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F72_REG_6) },
3488   },
3489   /* REG_0F73 */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { MOD_TABLE (MOD_0F73_REG_2) },
3494     { MOD_TABLE (MOD_0F73_REG_3) },
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_0F73_REG_6) },
3498     { MOD_TABLE (MOD_0F73_REG_7) },
3499   },
3500   /* REG_0FA6 */
3501   {
3502     { "montmul",        { { OP_0f07, 0 } }, 0 },
3503     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3504     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3505   },
3506   /* REG_0FA7 */
3507   {
3508     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3509     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3510     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3511     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3512     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3513     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3514   },
3515   /* REG_0FAE */
3516   {
3517     { MOD_TABLE (MOD_0FAE_REG_0) },
3518     { MOD_TABLE (MOD_0FAE_REG_1) },
3519     { MOD_TABLE (MOD_0FAE_REG_2) },
3520     { MOD_TABLE (MOD_0FAE_REG_3) },
3521     { MOD_TABLE (MOD_0FAE_REG_4) },
3522     { MOD_TABLE (MOD_0FAE_REG_5) },
3523     { MOD_TABLE (MOD_0FAE_REG_6) },
3524     { MOD_TABLE (MOD_0FAE_REG_7) },
3525   },
3526   /* REG_0FBA */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { "btQ",    { Ev, Ib }, 0 },
3533     { "btsQ",   { Evh1, Ib }, 0 },
3534     { "btrQ",   { Evh1, Ib }, 0 },
3535     { "btcQ",   { Evh1, Ib }, 0 },
3536   },
3537   /* REG_0FC7 */
3538   {
3539     { Bad_Opcode },
3540     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_0FC7_REG_3) },
3543     { MOD_TABLE (MOD_0FC7_REG_4) },
3544     { MOD_TABLE (MOD_0FC7_REG_5) },
3545     { MOD_TABLE (MOD_0FC7_REG_6) },
3546     { MOD_TABLE (MOD_0FC7_REG_7) },
3547   },
3548   /* REG_VEX_0F71 */
3549   {
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3557   },
3558   /* REG_VEX_0F72 */
3559   {
3560     { Bad_Opcode },
3561     { Bad_Opcode },
3562     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3567   },
3568   /* REG_VEX_0F73 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3573     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3578   },
3579   /* REG_VEX_0FAE */
3580   {
3581     { Bad_Opcode },
3582     { Bad_Opcode },
3583     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3584     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3585   },
3586   /* REG_VEX_0F38F3 */
3587   {
3588     { Bad_Opcode },
3589     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3590     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3591     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3592   },
3593   /* REG_XOP_LWPCB */
3594   {
3595     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3596     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3597   },
3598   /* REG_XOP_LWP */
3599   {
3600     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3601     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3602   },
3603   /* REG_XOP_TBM_01 */
3604   {
3605     { Bad_Opcode },
3606     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3607     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3608     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3609     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3610     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3611     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3612     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3613   },
3614   /* REG_XOP_TBM_02 */
3615   {
3616     { Bad_Opcode },
3617     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3623   },
3624
3625 #include "i386-dis-evex-reg.h"
3626 };
3627
3628 static const struct dis386 prefix_table[][4] = {
3629   /* PREFIX_90 */
3630   {
3631     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3632     { "pause", { XX }, 0 },
3633     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3634     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3635   },
3636
3637   /* PREFIX_MOD_0_0F01_REG_5 */
3638   {
3639     { Bad_Opcode },
3640     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3641   },
3642
3643   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3644   {
3645     { Bad_Opcode },
3646     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3647   },
3648
3649   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3650   {
3651     { Bad_Opcode },
3652     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3653   },
3654
3655   /* PREFIX_0F09 */
3656   {
3657     { "wbinvd",   { XX }, 0 },
3658     { "wbnoinvd", { XX }, 0 },
3659   },
3660
3661   /* PREFIX_0F10 */
3662   {
3663     { "movups", { XM, EXx }, PREFIX_OPCODE },
3664     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3665     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3666     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3667   },
3668
3669   /* PREFIX_0F11 */
3670   {
3671     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3672     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3673     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3674     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3675   },
3676
3677   /* PREFIX_0F12 */
3678   {
3679     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3680     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3681     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3682     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F16 */
3686   {
3687     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3688     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3689     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3690   },
3691
3692   /* PREFIX_0F1A */
3693   {
3694     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3695     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3696     { "bndmov", { Gbnd, Ebnd }, 0 },
3697     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3698   },
3699
3700   /* PREFIX_0F1B */
3701   {
3702     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3703     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3704     { "bndmov", { EbndS, Gbnd }, 0 },
3705     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3706   },
3707
3708   /* PREFIX_0F1C */
3709   {
3710     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3711     { "nopQ",   { Ev }, PREFIX_OPCODE },
3712     { "nopQ",   { Ev }, PREFIX_OPCODE },
3713     { "nopQ",   { Ev }, PREFIX_OPCODE },
3714   },
3715
3716   /* PREFIX_0F1E */
3717   {
3718     { "nopQ",   { Ev }, PREFIX_OPCODE },
3719     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3720     { "nopQ",   { Ev }, PREFIX_OPCODE },
3721     { "nopQ",   { Ev }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F2A */
3725   {
3726     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3727     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3728     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3729     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3730   },
3731
3732   /* PREFIX_0F2B */
3733   {
3734     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3737     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3738   },
3739
3740   /* PREFIX_0F2C */
3741   {
3742     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3743     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3744     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3745     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3746   },
3747
3748   /* PREFIX_0F2D */
3749   {
3750     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3751     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3752     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3753     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3754   },
3755
3756   /* PREFIX_0F2E */
3757   {
3758     { "ucomiss",{ XM, EXd }, 0 },
3759     { Bad_Opcode },
3760     { "ucomisd",{ XM, EXq }, 0 },
3761   },
3762
3763   /* PREFIX_0F2F */
3764   {
3765     { "comiss", { XM, EXd }, 0 },
3766     { Bad_Opcode },
3767     { "comisd", { XM, EXq }, 0 },
3768   },
3769
3770   /* PREFIX_0F51 */
3771   {
3772     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3773     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3774     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3775     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3776   },
3777
3778   /* PREFIX_0F52 */
3779   {
3780     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3781     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3782   },
3783
3784   /* PREFIX_0F53 */
3785   {
3786     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3787     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F58 */
3791   {
3792     { "addps", { XM, EXx }, PREFIX_OPCODE },
3793     { "addss", { XM, EXd }, PREFIX_OPCODE },
3794     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3795     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F59 */
3799   {
3800     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3801     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3802     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3803     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F5A */
3807   {
3808     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3809     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3810     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3811     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F5B */
3815   {
3816     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3817     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3818     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3819   },
3820
3821   /* PREFIX_0F5C */
3822   {
3823     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3824     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3825     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3826     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F5D */
3830   {
3831     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3832     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3833     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3834     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_0F5E */
3838   {
3839     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3840     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3841     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3842     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F5F */
3846   {
3847     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3848     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3849     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3850     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F60 */
3854   {
3855     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3856     { Bad_Opcode },
3857     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3858   },
3859
3860   /* PREFIX_0F61 */
3861   {
3862     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3863     { Bad_Opcode },
3864     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F62 */
3868   {
3869     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3870     { Bad_Opcode },
3871     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F6C */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F6D */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3886   },
3887
3888   /* PREFIX_0F6F */
3889   {
3890     { "movq",   { MX, EM }, PREFIX_OPCODE },
3891     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3892     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F70 */
3896   {
3897     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3898     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3899     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3900     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0F73_REG_3 */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "psrldq", { XS, Ib }, 0 },
3908   },
3909
3910   /* PREFIX_0F73_REG_7 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { "pslldq", { XS, Ib }, 0 },
3915   },
3916
3917   /* PREFIX_0F78 */
3918   {
3919     {"vmread",  { Em, Gm }, 0 },
3920     { Bad_Opcode },
3921     {"extrq",   { XS, Ib, Ib }, 0 },
3922     {"insertq", { XM, XS, Ib, Ib }, 0 },
3923   },
3924
3925   /* PREFIX_0F79 */
3926   {
3927     {"vmwrite", { Gm, Em }, 0 },
3928     { Bad_Opcode },
3929     {"extrq",   { XM, XS }, 0 },
3930     {"insertq", { XM, XS }, 0 },
3931   },
3932
3933   /* PREFIX_0F7C */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3938     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3939   },
3940
3941   /* PREFIX_0F7D */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3946     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F7E */
3950   {
3951     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3952     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3953     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0F7F */
3957   {
3958     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3959     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3960     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0FAE_REG_0 */
3964   {
3965     { Bad_Opcode },
3966     { "rdfsbase", { Ev }, 0 },
3967   },
3968
3969   /* PREFIX_0FAE_REG_1 */
3970   {
3971     { Bad_Opcode },
3972     { "rdgsbase", { Ev }, 0 },
3973   },
3974
3975   /* PREFIX_0FAE_REG_2 */
3976   {
3977     { Bad_Opcode },
3978     { "wrfsbase", { Ev }, 0 },
3979   },
3980
3981   /* PREFIX_0FAE_REG_3 */
3982   {
3983     { Bad_Opcode },
3984     { "wrgsbase", { Ev }, 0 },
3985   },
3986
3987   /* PREFIX_MOD_0_0FAE_REG_4 */
3988   {
3989     { "xsave",  { FXSAVE }, 0 },
3990     { "ptwrite%LQ", { Edq }, 0 },
3991   },
3992
3993   /* PREFIX_MOD_3_0FAE_REG_4 */
3994   {
3995     { Bad_Opcode },
3996     { "ptwrite%LQ", { Edq }, 0 },
3997   },
3998
3999   /* PREFIX_MOD_0_0FAE_REG_5 */
4000   {
4001     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4002   },
4003
4004   /* PREFIX_MOD_3_0FAE_REG_5 */
4005   {
4006     { "lfence",         { Skip_MODRM }, 0 },
4007     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_MOD_0_0FAE_REG_6 */
4011   {
4012     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4013     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4014     { "clwb",   { Mb }, PREFIX_OPCODE },
4015   },
4016
4017   /* PREFIX_MOD_1_0FAE_REG_6 */
4018   {
4019     { RM_TABLE (RM_0FAE_REG_6) },
4020     { "umonitor",       { Eva }, PREFIX_OPCODE },
4021     { "tpause", { Edq }, PREFIX_OPCODE },
4022     { "umwait", { Edq }, PREFIX_OPCODE },
4023   },
4024
4025   /* PREFIX_0FAE_REG_7 */
4026   {
4027     { "clflush",        { Mb }, 0 },
4028     { Bad_Opcode },
4029     { "clflushopt",     { Mb }, 0 },
4030   },
4031
4032   /* PREFIX_0FB8 */
4033   {
4034     { Bad_Opcode },
4035     { "popcntS", { Gv, Ev }, 0 },
4036   },
4037
4038   /* PREFIX_0FBC */
4039   {
4040     { "bsfS",   { Gv, Ev }, 0 },
4041     { "tzcntS", { Gv, Ev }, 0 },
4042     { "bsfS",   { Gv, Ev }, 0 },
4043   },
4044
4045   /* PREFIX_0FBD */
4046   {
4047     { "bsrS",   { Gv, Ev }, 0 },
4048     { "lzcntS", { Gv, Ev }, 0 },
4049     { "bsrS",   { Gv, Ev }, 0 },
4050   },
4051
4052   /* PREFIX_0FC2 */
4053   {
4054     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4055     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4056     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4057     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4058   },
4059
4060   /* PREFIX_MOD_0_0FC3 */
4061   {
4062     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_MOD_0_0FC7_REG_6 */
4066   {
4067     { "vmptrld",{ Mq }, 0 },
4068     { "vmxon",  { Mq }, 0 },
4069     { "vmclear",{ Mq }, 0 },
4070   },
4071
4072   /* PREFIX_MOD_3_0FC7_REG_6 */
4073   {
4074     { "rdrand", { Ev }, 0 },
4075     { Bad_Opcode },
4076     { "rdrand", { Ev }, 0 }
4077   },
4078
4079   /* PREFIX_MOD_3_0FC7_REG_7 */
4080   {
4081     { "rdseed", { Ev }, 0 },
4082     { "rdpid",  { Em }, 0 },
4083     { "rdseed", { Ev }, 0 },
4084   },
4085
4086   /* PREFIX_0FD0 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { "addsubpd", { XM, EXx }, 0 },
4091     { "addsubps", { XM, EXx }, 0 },
4092   },
4093
4094   /* PREFIX_0FD6 */
4095   {
4096     { Bad_Opcode },
4097     { "movq2dq",{ XM, MS }, 0 },
4098     { "movq",   { EXqS, XM }, 0 },
4099     { "movdq2q",{ MX, XS }, 0 },
4100   },
4101
4102   /* PREFIX_0FE6 */
4103   {
4104     { Bad_Opcode },
4105     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4106     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4107     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4108   },
4109
4110   /* PREFIX_0FE7 */
4111   {
4112     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4113     { Bad_Opcode },
4114     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4115   },
4116
4117   /* PREFIX_0FF0 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4123   },
4124
4125   /* PREFIX_0FF7 */
4126   {
4127     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4128     { Bad_Opcode },
4129     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_0F3810 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0F3814 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_0F3815 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4151   },
4152
4153   /* PREFIX_0F3817 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4158   },
4159
4160   /* PREFIX_0F3820 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F3821 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F3822 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0F3823 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_0F3824 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0F3825 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4200   },
4201
4202   /* PREFIX_0F3828 */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4207   },
4208
4209   /* PREFIX_0F3829 */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4214   },
4215
4216   /* PREFIX_0F382A */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4221   },
4222
4223   /* PREFIX_0F382B */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4228   },
4229
4230   /* PREFIX_0F3830 */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0F3831 */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F3832 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F3833 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3834 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3835 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3837 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3838 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F3839 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F383A */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F383B */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F383C */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F383D */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F383E */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F383F */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F3840 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3841 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3880 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3881 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3882 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F38C8 */
4371   {
4372     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38C9 */
4376   {
4377     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38CA */
4381   {
4382     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38CB */
4386   {
4387     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38CC */
4391   {
4392     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38CD */
4396   {
4397     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38CF */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F38DB */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F38DC */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F38DD */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38DE */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F38DF */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F38F0 */
4443   {
4444     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4445     { Bad_Opcode },
4446     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4447     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F38F1 */
4451   {
4452     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4453     { Bad_Opcode },
4454     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4455     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F38F5 */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4463   },
4464
4465   /* PREFIX_0F38F6 */
4466   {
4467     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4468     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4469     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4470     { Bad_Opcode },
4471   },
4472
4473   /* PREFIX_0F38F8 */
4474   {
4475     { Bad_Opcode },
4476     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4477     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4478     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4479   },
4480
4481   /* PREFIX_0F38F9 */
4482   {
4483     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4484   },
4485
4486   /* PREFIX_0F3A08 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3A09 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A0A */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A0B */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A0C */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A0D */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A0E */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A14 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A15 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A16 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A17 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A20 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3A21 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3A22 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3A40 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F3A41 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F3A42 */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F3A44 */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F3A60 */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F3A61 */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3A62 */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_0F3A63 */
4634   {
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4638   },
4639
4640   /* PREFIX_0F3ACC */
4641   {
4642     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3ACE */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F3ACF */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_0F3ADF */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4664   },
4665
4666   /* PREFIX_VEX_0F10 */
4667   {
4668     { "vmovups",        { XM, EXx }, 0 },
4669     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4670     { "vmovupd",        { XM, EXx }, 0 },
4671     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4672   },
4673
4674   /* PREFIX_VEX_0F11 */
4675   {
4676     { "vmovups",        { EXxS, XM }, 0 },
4677     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4678     { "vmovupd",        { EXxS, XM }, 0 },
4679     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4680   },
4681
4682   /* PREFIX_VEX_0F12 */
4683   {
4684     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4685     { "vmovsldup",      { XM, EXx }, 0 },
4686     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4687     { "vmovddup",       { XM, EXymmq }, 0 },
4688   },
4689
4690   /* PREFIX_VEX_0F16 */
4691   {
4692     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4693     { "vmovshdup",      { XM, EXx }, 0 },
4694     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F2A */
4698   {
4699     { Bad_Opcode },
4700     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4701     { Bad_Opcode },
4702     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4703   },
4704
4705   /* PREFIX_VEX_0F2C */
4706   {
4707     { Bad_Opcode },
4708     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4709     { Bad_Opcode },
4710     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4711   },
4712
4713   /* PREFIX_VEX_0F2D */
4714   {
4715     { Bad_Opcode },
4716     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4717     { Bad_Opcode },
4718     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4719   },
4720
4721   /* PREFIX_VEX_0F2E */
4722   {
4723     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4724     { Bad_Opcode },
4725     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4726   },
4727
4728   /* PREFIX_VEX_0F2F */
4729   {
4730     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4731     { Bad_Opcode },
4732     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4733   },
4734
4735   /* PREFIX_VEX_0F41 */
4736   {
4737     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F42 */
4743   {
4744     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4745     { Bad_Opcode },
4746     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F44 */
4750   {
4751     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4752     { Bad_Opcode },
4753     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F45 */
4757   {
4758     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4759     { Bad_Opcode },
4760     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F46 */
4764   {
4765     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4766     { Bad_Opcode },
4767     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4768   },
4769
4770   /* PREFIX_VEX_0F47 */
4771   {
4772     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4773     { Bad_Opcode },
4774     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4775   },
4776
4777   /* PREFIX_VEX_0F4A */
4778   {
4779     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4780     { Bad_Opcode },
4781     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F4B */
4785   {
4786     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4787     { Bad_Opcode },
4788     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4789   },
4790
4791   /* PREFIX_VEX_0F51 */
4792   {
4793     { "vsqrtps",        { XM, EXx }, 0 },
4794     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4795     { "vsqrtpd",        { XM, EXx }, 0 },
4796     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4797   },
4798
4799   /* PREFIX_VEX_0F52 */
4800   {
4801     { "vrsqrtps",       { XM, EXx }, 0 },
4802     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4803   },
4804
4805   /* PREFIX_VEX_0F53 */
4806   {
4807     { "vrcpps",         { XM, EXx }, 0 },
4808     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4809   },
4810
4811   /* PREFIX_VEX_0F58 */
4812   {
4813     { "vaddps",         { XM, Vex, EXx }, 0 },
4814     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4815     { "vaddpd",         { XM, Vex, EXx }, 0 },
4816     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F59 */
4820   {
4821     { "vmulps",         { XM, Vex, EXx }, 0 },
4822     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4823     { "vmulpd",         { XM, Vex, EXx }, 0 },
4824     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F5A */
4828   {
4829     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4830     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4831     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4832     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F5B */
4836   {
4837     { "vcvtdq2ps",      { XM, EXx }, 0 },
4838     { "vcvttps2dq",     { XM, EXx }, 0 },
4839     { "vcvtps2dq",      { XM, EXx }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F5C */
4843   {
4844     { "vsubps",         { XM, Vex, EXx }, 0 },
4845     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4846     { "vsubpd",         { XM, Vex, EXx }, 0 },
4847     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F5D */
4851   {
4852     { "vminps",         { XM, Vex, EXx }, 0 },
4853     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4854     { "vminpd",         { XM, Vex, EXx }, 0 },
4855     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F5E */
4859   {
4860     { "vdivps",         { XM, Vex, EXx }, 0 },
4861     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4862     { "vdivpd",         { XM, Vex, EXx }, 0 },
4863     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4864   },
4865
4866   /* PREFIX_VEX_0F5F */
4867   {
4868     { "vmaxps",         { XM, Vex, EXx }, 0 },
4869     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4870     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4871     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F60 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F61 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F62 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F63 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F64 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4907   },
4908
4909   /* PREFIX_VEX_0F65 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F66 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4921   },
4922
4923   /* PREFIX_VEX_0F67 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4928   },
4929
4930   /* PREFIX_VEX_0F68 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4935   },
4936
4937   /* PREFIX_VEX_0F69 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4942   },
4943
4944   /* PREFIX_VEX_0F6A */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4949   },
4950
4951   /* PREFIX_VEX_0F6B */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4956   },
4957
4958   /* PREFIX_VEX_0F6C */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4963   },
4964
4965   /* PREFIX_VEX_0F6D */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4970   },
4971
4972   /* PREFIX_VEX_0F6E */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0F6F */
4980   {
4981     { Bad_Opcode },
4982     { "vmovdqu",        { XM, EXx }, 0 },
4983     { "vmovdqa",        { XM, EXx }, 0 },
4984   },
4985
4986   /* PREFIX_VEX_0F70 */
4987   {
4988     { Bad_Opcode },
4989     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4990     { "vpshufd",        { XM, EXx, Ib }, 0 },
4991     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4992   },
4993
4994   /* PREFIX_VEX_0F71_REG_2 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4999   },
5000
5001   /* PREFIX_VEX_0F71_REG_4 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { "vpsraw",         { Vex, XS, Ib }, 0 },
5006   },
5007
5008   /* PREFIX_VEX_0F71_REG_6 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { "vpsllw",         { Vex, XS, Ib }, 0 },
5013   },
5014
5015   /* PREFIX_VEX_0F72_REG_2 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { "vpsrld",         { Vex, XS, Ib }, 0 },
5020   },
5021
5022   /* PREFIX_VEX_0F72_REG_4 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { "vpsrad",         { Vex, XS, Ib }, 0 },
5027   },
5028
5029   /* PREFIX_VEX_0F72_REG_6 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { "vpslld",         { Vex, XS, Ib }, 0 },
5034   },
5035
5036   /* PREFIX_VEX_0F73_REG_2 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5041   },
5042
5043   /* PREFIX_VEX_0F73_REG_3 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5048   },
5049
5050   /* PREFIX_VEX_0F73_REG_6 */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { "vpsllq",         { Vex, XS, Ib }, 0 },
5055   },
5056
5057   /* PREFIX_VEX_0F73_REG_7 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vpslldq",        { Vex, XS, Ib }, 0 },
5062   },
5063
5064   /* PREFIX_VEX_0F74 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5069   },
5070
5071   /* PREFIX_VEX_0F75 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5076   },
5077
5078   /* PREFIX_VEX_0F76 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5083   },
5084
5085   /* PREFIX_VEX_0F77 */
5086   {
5087     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5088   },
5089
5090   /* PREFIX_VEX_0F7C */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5095     { "vhaddps",        { XM, Vex, EXx }, 0 },
5096   },
5097
5098   /* PREFIX_VEX_0F7D */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5103     { "vhsubps",        { XM, Vex, EXx }, 0 },
5104   },
5105
5106   /* PREFIX_VEX_0F7E */
5107   {
5108     { Bad_Opcode },
5109     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5110     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0F7F */
5114   {
5115     { Bad_Opcode },
5116     { "vmovdqu",        { EXxS, XM }, 0 },
5117     { "vmovdqa",        { EXxS, XM }, 0 },
5118   },
5119
5120   /* PREFIX_VEX_0F90 */
5121   {
5122     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5123     { Bad_Opcode },
5124     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0F91 */
5128   {
5129     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0F92 */
5135   {
5136     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5139     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5140   },
5141
5142   /* PREFIX_VEX_0F93 */
5143   {
5144     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5147     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5148   },
5149
5150   /* PREFIX_VEX_0F98 */
5151   {
5152     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F99 */
5158   {
5159     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5160     { Bad_Opcode },
5161     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0FC2 */
5165   {
5166     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5167     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5168     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5169     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5170   },
5171
5172   /* PREFIX_VEX_0FC4 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0FC5 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_0FD0 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5191     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5192   },
5193
5194   /* PREFIX_VEX_0FD1 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5199   },
5200
5201   /* PREFIX_VEX_0FD2 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5206   },
5207
5208   /* PREFIX_VEX_0FD3 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5213   },
5214
5215   /* PREFIX_VEX_0FD4 */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vpaddq",         { XM, Vex, EXx }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FD5 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vpmullw",        { XM, Vex, EXx }, 0 },
5227   },
5228
5229   /* PREFIX_VEX_0FD6 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0FD7 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5241   },
5242
5243   /* PREFIX_VEX_0FD8 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5248   },
5249
5250   /* PREFIX_VEX_0FD9 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FDA */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpminub",        { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FDB */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpand",          { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FDC */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5276   },
5277
5278   /* PREFIX_VEX_0FDD */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5283   },
5284
5285   /* PREFIX_VEX_0FDE */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5290   },
5291
5292   /* PREFIX_VEX_0FDF */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { "vpandn",         { XM, Vex, EXx }, 0 },
5297   },
5298
5299   /* PREFIX_VEX_0FE0 */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { "vpavgb",         { XM, Vex, EXx }, 0 },
5304   },
5305
5306   /* PREFIX_VEX_0FE1 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5311   },
5312
5313   /* PREFIX_VEX_0FE2 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5318   },
5319
5320   /* PREFIX_VEX_0FE3 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { "vpavgw",         { XM, Vex, EXx }, 0 },
5325   },
5326
5327   /* PREFIX_VEX_0FE4 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5332   },
5333
5334   /* PREFIX_VEX_0FE5 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5339   },
5340
5341   /* PREFIX_VEX_0FE6 */
5342   {
5343     { Bad_Opcode },
5344     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5345     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5346     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5347   },
5348
5349   /* PREFIX_VEX_0FE7 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FE8 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5361   },
5362
5363   /* PREFIX_VEX_0FE9 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5368   },
5369
5370   /* PREFIX_VEX_0FEA */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { "vpminsw",        { XM, Vex, EXx }, 0 },
5375   },
5376
5377   /* PREFIX_VEX_0FEB */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { "vpor",           { XM, Vex, EXx }, 0 },
5382   },
5383
5384   /* PREFIX_VEX_0FEC */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5389   },
5390
5391   /* PREFIX_VEX_0FED */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5396   },
5397
5398   /* PREFIX_VEX_0FEE */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5403   },
5404
5405   /* PREFIX_VEX_0FEF */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { "vpxor",          { XM, Vex, EXx }, 0 },
5410   },
5411
5412   /* PREFIX_VEX_0FF0 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5418   },
5419
5420   /* PREFIX_VEX_0FF1 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5425   },
5426
5427   /* PREFIX_VEX_0FF2 */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5432   },
5433
5434   /* PREFIX_VEX_0FF3 */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5439   },
5440
5441   /* PREFIX_VEX_0FF4 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5446   },
5447
5448   /* PREFIX_VEX_0FF5 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5453   },
5454
5455   /* PREFIX_VEX_0FF6 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5460   },
5461
5462   /* PREFIX_VEX_0FF7 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0FF8 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { "vpsubb",         { XM, Vex, EXx }, 0 },
5474   },
5475
5476   /* PREFIX_VEX_0FF9 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { "vpsubw",         { XM, Vex, EXx }, 0 },
5481   },
5482
5483   /* PREFIX_VEX_0FFA */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { "vpsubd",         { XM, Vex, EXx }, 0 },
5488   },
5489
5490   /* PREFIX_VEX_0FFB */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { "vpsubq",         { XM, Vex, EXx }, 0 },
5495   },
5496
5497   /* PREFIX_VEX_0FFC */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { "vpaddb",         { XM, Vex, EXx }, 0 },
5502   },
5503
5504   /* PREFIX_VEX_0FFD */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { "vpaddw",         { XM, Vex, EXx }, 0 },
5509   },
5510
5511   /* PREFIX_VEX_0FFE */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { "vpaddd",         { XM, Vex, EXx }, 0 },
5516   },
5517
5518   /* PREFIX_VEX_0F3800 */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { "vpshufb",        { XM, Vex, EXx }, 0 },
5523   },
5524
5525   /* PREFIX_VEX_0F3801 */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { "vphaddw",        { XM, Vex, EXx }, 0 },
5530   },
5531
5532   /* PREFIX_VEX_0F3802 */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { "vphaddd",        { XM, Vex, EXx }, 0 },
5537   },
5538
5539   /* PREFIX_VEX_0F3803 */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5544   },
5545
5546   /* PREFIX_VEX_0F3804 */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5551   },
5552
5553   /* PREFIX_VEX_0F3805 */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { "vphsubw",        { XM, Vex, EXx }, 0 },
5558   },
5559
5560   /* PREFIX_VEX_0F3806 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { "vphsubd",        { XM, Vex, EXx }, 0 },
5565   },
5566
5567   /* PREFIX_VEX_0F3807 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5572   },
5573
5574   /* PREFIX_VEX_0F3808 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { "vpsignb",        { XM, Vex, EXx }, 0 },
5579   },
5580
5581   /* PREFIX_VEX_0F3809 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { "vpsignw",        { XM, Vex, EXx }, 0 },
5586   },
5587
5588   /* PREFIX_VEX_0F380A */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { "vpsignd",        { XM, Vex, EXx }, 0 },
5593   },
5594
5595   /* PREFIX_VEX_0F380B */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5600   },
5601
5602   /* PREFIX_VEX_0F380C */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0F380D */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F380E */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F380F */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5628   },
5629
5630   /* PREFIX_VEX_0F3813 */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5635   },
5636
5637   /* PREFIX_VEX_0F3816 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5642   },
5643
5644   /* PREFIX_VEX_0F3817 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { "vptest",         { XM, EXx }, 0 },
5649   },
5650
5651   /* PREFIX_VEX_0F3818 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0F3819 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F381A */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F381C */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { "vpabsb",         { XM, EXx }, 0 },
5677   },
5678
5679   /* PREFIX_VEX_0F381D */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { "vpabsw",         { XM, EXx }, 0 },
5684   },
5685
5686   /* PREFIX_VEX_0F381E */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { "vpabsd",         { XM, EXx }, 0 },
5691   },
5692
5693   /* PREFIX_VEX_0F3820 */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5698   },
5699
5700   /* PREFIX_VEX_0F3821 */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5705   },
5706
5707   /* PREFIX_VEX_0F3822 */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5712   },
5713
5714   /* PREFIX_VEX_0F3823 */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5719   },
5720
5721   /* PREFIX_VEX_0F3824 */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5726   },
5727
5728   /* PREFIX_VEX_0F3825 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5733   },
5734
5735   /* PREFIX_VEX_0F3828 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5740   },
5741
5742   /* PREFIX_VEX_0F3829 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5747   },
5748
5749   /* PREFIX_VEX_0F382A */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5754   },
5755
5756   /* PREFIX_VEX_0F382B */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5761   },
5762
5763   /* PREFIX_VEX_0F382C */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F382D */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F382E */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F382F */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F3830 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5796   },
5797
5798   /* PREFIX_VEX_0F3831 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5803   },
5804
5805   /* PREFIX_VEX_0F3832 */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5810   },
5811
5812   /* PREFIX_VEX_0F3833 */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5817   },
5818
5819   /* PREFIX_VEX_0F3834 */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5824   },
5825
5826   /* PREFIX_VEX_0F3835 */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5831   },
5832
5833   /* PREFIX_VEX_0F3836 */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5838   },
5839
5840   /* PREFIX_VEX_0F3837 */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5845   },
5846
5847   /* PREFIX_VEX_0F3838 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vpminsb",        { XM, Vex, EXx }, 0 },
5852   },
5853
5854   /* PREFIX_VEX_0F3839 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { "vpminsd",        { XM, Vex, EXx }, 0 },
5859   },
5860
5861   /* PREFIX_VEX_0F383A */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { "vpminuw",        { XM, Vex, EXx }, 0 },
5866   },
5867
5868   /* PREFIX_VEX_0F383B */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { "vpminud",        { XM, Vex, EXx }, 0 },
5873   },
5874
5875   /* PREFIX_VEX_0F383C */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5880   },
5881
5882   /* PREFIX_VEX_0F383D */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5887   },
5888
5889   /* PREFIX_VEX_0F383E */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5894   },
5895
5896   /* PREFIX_VEX_0F383F */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5901   },
5902
5903   /* PREFIX_VEX_0F3840 */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { "vpmulld",        { XM, Vex, EXx }, 0 },
5908   },
5909
5910   /* PREFIX_VEX_0F3841 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5915   },
5916
5917   /* PREFIX_VEX_0F3845 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5922   },
5923
5924   /* PREFIX_VEX_0F3846 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5929   },
5930
5931   /* PREFIX_VEX_0F3847 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5936   },
5937
5938   /* PREFIX_VEX_0F3858 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5943   },
5944
5945   /* PREFIX_VEX_0F3859 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5950   },
5951
5952   /* PREFIX_VEX_0F385A */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5957   },
5958
5959   /* PREFIX_VEX_0F3878 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5964   },
5965
5966   /* PREFIX_VEX_0F3879 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5971   },
5972
5973   /* PREFIX_VEX_0F388C */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5978   },
5979
5980   /* PREFIX_VEX_0F388E */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5985   },
5986
5987   /* PREFIX_VEX_0F3890 */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F3891 */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F3892 */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F3893 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F3896 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F3897 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F3898 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F3899 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F389A */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F389B */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F389C */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F389D */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F389E */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F389F */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6083   },
6084
6085   /* PREFIX_VEX_0F38A6 */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6090     { Bad_Opcode },
6091   },
6092
6093   /* PREFIX_VEX_0F38A7 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38A8 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38A9 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38AA */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38AB */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38AC */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38AD */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38AE */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38AF */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38B6 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38B7 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38B8 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38B9 */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F38BA */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F38BB */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F38BC */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F38BD */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F38BE */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6217   },
6218
6219   /* PREFIX_VEX_0F38BF */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6224   },
6225
6226   /* PREFIX_VEX_0F38CF */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6231   },
6232
6233   /* PREFIX_VEX_0F38DB */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6238   },
6239
6240   /* PREFIX_VEX_0F38DC */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vaesenc",        { XM, Vex, EXx }, 0 },
6245   },
6246
6247   /* PREFIX_VEX_0F38DD */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F38DE */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { "vaesdec",        { XM, Vex, EXx }, 0 },
6259   },
6260
6261   /* PREFIX_VEX_0F38DF */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6266   },
6267
6268   /* PREFIX_VEX_0F38F2 */
6269   {
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6271   },
6272
6273   /* PREFIX_VEX_0F38F3_REG_1 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F3_REG_2 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6281   },
6282
6283   /* PREFIX_VEX_0F38F3_REG_3 */
6284   {
6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6286   },
6287
6288   /* PREFIX_VEX_0F38F5 */
6289   {
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6292     { Bad_Opcode },
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6294   },
6295
6296   /* PREFIX_VEX_0F38F6 */
6297   {
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6302   },
6303
6304   /* PREFIX_VEX_0F38F7 */
6305   {
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A00 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A01 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A02 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A04 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A05 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A06 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A08 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vroundps",       { XM, EXx, Ib }, 0 },
6359   },
6360
6361   /* PREFIX_VEX_0F3A09 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vroundpd",       { XM, EXx, Ib }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F3A0A */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F3A0B */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6380   },
6381
6382   /* PREFIX_VEX_0F3A0C */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6387   },
6388
6389   /* PREFIX_VEX_0F3A0D */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F3A0E */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6401   },
6402
6403   /* PREFIX_VEX_0F3A0F */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6408   },
6409
6410   /* PREFIX_VEX_0F3A14 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A15 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A16 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A17 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A18 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A19 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A1D */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6457   },
6458
6459   /* PREFIX_VEX_0F3A20 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A21 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A22 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A30 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A31 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A32 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A33 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A38 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A39 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A40 */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6527   },
6528
6529   /* PREFIX_VEX_0F3A41 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6534   },
6535
6536   /* PREFIX_VEX_0F3A42 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A44 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A46 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6555   },
6556
6557   /* PREFIX_VEX_0F3A48 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A49 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A4A */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A4B */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A4C */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6590   },
6591
6592   /* PREFIX_VEX_0F3A5C */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6597   },
6598
6599   /* PREFIX_VEX_0F3A5D */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6604   },
6605
6606   /* PREFIX_VEX_0F3A5E */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611   },
6612
6613   /* PREFIX_VEX_0F3A5F */
6614   {
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6618   },
6619
6620   /* PREFIX_VEX_0F3A60 */
6621   {
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6625     { Bad_Opcode },
6626   },
6627
6628   /* PREFIX_VEX_0F3A61 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A62 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A63 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A68 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A69 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A6A */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A6B */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A6C */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6682   },
6683
6684   /* PREFIX_VEX_0F3A6D */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6689   },
6690
6691   /* PREFIX_VEX_0F3A6E */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6696   },
6697
6698   /* PREFIX_VEX_0F3A6F */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6703   },
6704
6705   /* PREFIX_VEX_0F3A78 */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6710   },
6711
6712   /* PREFIX_VEX_0F3A79 */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6717   },
6718
6719   /* PREFIX_VEX_0F3A7A */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6724   },
6725
6726   /* PREFIX_VEX_0F3A7B */
6727   {
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6731   },
6732
6733   /* PREFIX_VEX_0F3A7C */
6734   {
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6738     { Bad_Opcode },
6739   },
6740
6741   /* PREFIX_VEX_0F3A7D */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6746   },
6747
6748   /* PREFIX_VEX_0F3A7E */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3A7F */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6760   },
6761
6762   /* PREFIX_VEX_0F3ACE */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6767   },
6768
6769   /* PREFIX_VEX_0F3ACF */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6774   },
6775
6776   /* PREFIX_VEX_0F3ADF */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6781   },
6782
6783   /* PREFIX_VEX_0F3AF0 */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6789   },
6790
6791 #include "i386-dis-evex-prefix.h"
6792 };
6793
6794 static const struct dis386 x86_64_table[][2] = {
6795   /* X86_64_06 */
6796   {
6797     { "pushP", { es }, 0 },
6798   },
6799
6800   /* X86_64_07 */
6801   {
6802     { "popP", { es }, 0 },
6803   },
6804
6805   /* X86_64_0D */
6806   {
6807     { "pushP", { cs }, 0 },
6808   },
6809
6810   /* X86_64_16 */
6811   {
6812     { "pushP", { ss }, 0 },
6813   },
6814
6815   /* X86_64_17 */
6816   {
6817     { "popP", { ss }, 0 },
6818   },
6819
6820   /* X86_64_1E */
6821   {
6822     { "pushP", { ds }, 0 },
6823   },
6824
6825   /* X86_64_1F */
6826   {
6827     { "popP", { ds }, 0 },
6828   },
6829
6830   /* X86_64_27 */
6831   {
6832     { "daa", { XX }, 0 },
6833   },
6834
6835   /* X86_64_2F */
6836   {
6837     { "das", { XX }, 0 },
6838   },
6839
6840   /* X86_64_37 */
6841   {
6842     { "aaa", { XX }, 0 },
6843   },
6844
6845   /* X86_64_3F */
6846   {
6847     { "aas", { XX }, 0 },
6848   },
6849
6850   /* X86_64_60 */
6851   {
6852     { "pushaP", { XX }, 0 },
6853   },
6854
6855   /* X86_64_61 */
6856   {
6857     { "popaP", { XX }, 0 },
6858   },
6859
6860   /* X86_64_62 */
6861   {
6862     { MOD_TABLE (MOD_62_32BIT) },
6863     { EVEX_TABLE (EVEX_0F) },
6864   },
6865
6866   /* X86_64_63 */
6867   {
6868     { "arpl", { Ew, Gw }, 0 },
6869     { "movs{lq|xd}", { Gv, Ed }, 0 },
6870   },
6871
6872   /* X86_64_6D */
6873   {
6874     { "ins{R|}", { Yzr, indirDX }, 0 },
6875     { "ins{G|}", { Yzr, indirDX }, 0 },
6876   },
6877
6878   /* X86_64_6F */
6879   {
6880     { "outs{R|}", { indirDXr, Xz }, 0 },
6881     { "outs{G|}", { indirDXr, Xz }, 0 },
6882   },
6883
6884   /* X86_64_82 */
6885   {
6886     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6887     { REG_TABLE (REG_80) },
6888   },
6889
6890   /* X86_64_9A */
6891   {
6892     { "Jcall{T|}", { Ap }, 0 },
6893   },
6894
6895   /* X86_64_C4 */
6896   {
6897     { MOD_TABLE (MOD_C4_32BIT) },
6898     { VEX_C4_TABLE (VEX_0F) },
6899   },
6900
6901   /* X86_64_C5 */
6902   {
6903     { MOD_TABLE (MOD_C5_32BIT) },
6904     { VEX_C5_TABLE (VEX_0F) },
6905   },
6906
6907   /* X86_64_CE */
6908   {
6909     { "into", { XX }, 0 },
6910   },
6911
6912   /* X86_64_D4 */
6913   {
6914     { "aam", { Ib }, 0 },
6915   },
6916
6917   /* X86_64_D5 */
6918   {
6919     { "aad", { Ib }, 0 },
6920   },
6921
6922   /* X86_64_E8 */
6923   {
6924     { "callP",          { Jv, BND }, 0 },
6925     { "call@",          { Jv, BND }, 0 }
6926   },
6927
6928   /* X86_64_E9 */
6929   {
6930     { "jmpP",           { Jv, BND }, 0 },
6931     { "jmp@",           { Jv, BND }, 0 }
6932   },
6933
6934   /* X86_64_EA */
6935   {
6936     { "Jjmp{T|}", { Ap }, 0 },
6937   },
6938
6939   /* X86_64_0F01_REG_0 */
6940   {
6941     { "sgdt{Q|IQ}", { M }, 0 },
6942     { "sgdt", { M }, 0 },
6943   },
6944
6945   /* X86_64_0F01_REG_1 */
6946   {
6947     { "sidt{Q|IQ}", { M }, 0 },
6948     { "sidt", { M }, 0 },
6949   },
6950
6951   /* X86_64_0F01_REG_2 */
6952   {
6953     { "lgdt{Q|Q}", { M }, 0 },
6954     { "lgdt", { M }, 0 },
6955   },
6956
6957   /* X86_64_0F01_REG_3 */
6958   {
6959     { "lidt{Q|Q}", { M }, 0 },
6960     { "lidt", { M }, 0 },
6961   },
6962 };
6963
6964 static const struct dis386 three_byte_table[][256] = {
6965
6966   /* THREE_BYTE_0F38 */
6967   {
6968     /* 00 */
6969     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6970     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6971     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6972     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6973     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6974     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6975     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6976     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6977     /* 08 */
6978     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6979     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6980     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6981     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* 10 */
6987     { PREFIX_TABLE (PREFIX_0F3810) },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { PREFIX_TABLE (PREFIX_0F3814) },
6992     { PREFIX_TABLE (PREFIX_0F3815) },
6993     { Bad_Opcode },
6994     { PREFIX_TABLE (PREFIX_0F3817) },
6995     /* 18 */
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7001     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7002     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7003     { Bad_Opcode },
7004     /* 20 */
7005     { PREFIX_TABLE (PREFIX_0F3820) },
7006     { PREFIX_TABLE (PREFIX_0F3821) },
7007     { PREFIX_TABLE (PREFIX_0F3822) },
7008     { PREFIX_TABLE (PREFIX_0F3823) },
7009     { PREFIX_TABLE (PREFIX_0F3824) },
7010     { PREFIX_TABLE (PREFIX_0F3825) },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* 28 */
7014     { PREFIX_TABLE (PREFIX_0F3828) },
7015     { PREFIX_TABLE (PREFIX_0F3829) },
7016     { PREFIX_TABLE (PREFIX_0F382A) },
7017     { PREFIX_TABLE (PREFIX_0F382B) },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 30 */
7023     { PREFIX_TABLE (PREFIX_0F3830) },
7024     { PREFIX_TABLE (PREFIX_0F3831) },
7025     { PREFIX_TABLE (PREFIX_0F3832) },
7026     { PREFIX_TABLE (PREFIX_0F3833) },
7027     { PREFIX_TABLE (PREFIX_0F3834) },
7028     { PREFIX_TABLE (PREFIX_0F3835) },
7029     { Bad_Opcode },
7030     { PREFIX_TABLE (PREFIX_0F3837) },
7031     /* 38 */
7032     { PREFIX_TABLE (PREFIX_0F3838) },
7033     { PREFIX_TABLE (PREFIX_0F3839) },
7034     { PREFIX_TABLE (PREFIX_0F383A) },
7035     { PREFIX_TABLE (PREFIX_0F383B) },
7036     { PREFIX_TABLE (PREFIX_0F383C) },
7037     { PREFIX_TABLE (PREFIX_0F383D) },
7038     { PREFIX_TABLE (PREFIX_0F383E) },
7039     { PREFIX_TABLE (PREFIX_0F383F) },
7040     /* 40 */
7041     { PREFIX_TABLE (PREFIX_0F3840) },
7042     { PREFIX_TABLE (PREFIX_0F3841) },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 48 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 50 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* 58 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* 60 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 68 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 70 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* 78 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 80 */
7113     { PREFIX_TABLE (PREFIX_0F3880) },
7114     { PREFIX_TABLE (PREFIX_0F3881) },
7115     { PREFIX_TABLE (PREFIX_0F3882) },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 88 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* 90 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* 98 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* a0 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* a8 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* b0 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* b8 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* c0 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* c8 */
7194     { PREFIX_TABLE (PREFIX_0F38C8) },
7195     { PREFIX_TABLE (PREFIX_0F38C9) },
7196     { PREFIX_TABLE (PREFIX_0F38CA) },
7197     { PREFIX_TABLE (PREFIX_0F38CB) },
7198     { PREFIX_TABLE (PREFIX_0F38CC) },
7199     { PREFIX_TABLE (PREFIX_0F38CD) },
7200     { Bad_Opcode },
7201     { PREFIX_TABLE (PREFIX_0F38CF) },
7202     /* d0 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* d8 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { PREFIX_TABLE (PREFIX_0F38DB) },
7216     { PREFIX_TABLE (PREFIX_0F38DC) },
7217     { PREFIX_TABLE (PREFIX_0F38DD) },
7218     { PREFIX_TABLE (PREFIX_0F38DE) },
7219     { PREFIX_TABLE (PREFIX_0F38DF) },
7220     /* e0 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* e8 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* f0 */
7239     { PREFIX_TABLE (PREFIX_0F38F0) },
7240     { PREFIX_TABLE (PREFIX_0F38F1) },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { PREFIX_TABLE (PREFIX_0F38F5) },
7245     { PREFIX_TABLE (PREFIX_0F38F6) },
7246     { Bad_Opcode },
7247     /* f8 */
7248     { PREFIX_TABLE (PREFIX_0F38F8) },
7249     { PREFIX_TABLE (PREFIX_0F38F9) },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256   },
7257   /* THREE_BYTE_0F3A */
7258   {
7259     /* 00 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 08 */
7269     { PREFIX_TABLE (PREFIX_0F3A08) },
7270     { PREFIX_TABLE (PREFIX_0F3A09) },
7271     { PREFIX_TABLE (PREFIX_0F3A0A) },
7272     { PREFIX_TABLE (PREFIX_0F3A0B) },
7273     { PREFIX_TABLE (PREFIX_0F3A0C) },
7274     { PREFIX_TABLE (PREFIX_0F3A0D) },
7275     { PREFIX_TABLE (PREFIX_0F3A0E) },
7276     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7277     /* 10 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { PREFIX_TABLE (PREFIX_0F3A14) },
7283     { PREFIX_TABLE (PREFIX_0F3A15) },
7284     { PREFIX_TABLE (PREFIX_0F3A16) },
7285     { PREFIX_TABLE (PREFIX_0F3A17) },
7286     /* 18 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 20 */
7296     { PREFIX_TABLE (PREFIX_0F3A20) },
7297     { PREFIX_TABLE (PREFIX_0F3A21) },
7298     { PREFIX_TABLE (PREFIX_0F3A22) },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 28 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 30 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 38 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 40 */
7332     { PREFIX_TABLE (PREFIX_0F3A40) },
7333     { PREFIX_TABLE (PREFIX_0F3A41) },
7334     { PREFIX_TABLE (PREFIX_0F3A42) },
7335     { Bad_Opcode },
7336     { PREFIX_TABLE (PREFIX_0F3A44) },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 48 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 50 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 58 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 60 */
7368     { PREFIX_TABLE (PREFIX_0F3A60) },
7369     { PREFIX_TABLE (PREFIX_0F3A61) },
7370     { PREFIX_TABLE (PREFIX_0F3A62) },
7371     { PREFIX_TABLE (PREFIX_0F3A63) },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 68 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 70 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 78 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 80 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* 88 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* 90 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 98 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* a0 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* a8 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* b0 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* b8 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* c0 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* c8 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { PREFIX_TABLE (PREFIX_0F3ACC) },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_0F3ACE) },
7492     { PREFIX_TABLE (PREFIX_0F3ACF) },
7493     /* d0 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* d8 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { PREFIX_TABLE (PREFIX_0F3ADF) },
7511     /* e0 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* e8 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* f0 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* f8 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547   },
7548 };
7549
7550 static const struct dis386 xop_table[][256] = {
7551   /* XOP_08 */
7552   {
7553     /* 00 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 08 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 10 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 18 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 20 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 28 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 30 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 38 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 40 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 48 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 50 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 58 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 60 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 68 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* 70 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* 78 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* 80 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     /* 88 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     /* 90 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7723     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7724     /* 98 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7732     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7733     /* a0 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { Bad_Opcode },
7742     /* a8 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* b0 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7759     { Bad_Opcode },
7760     /* b8 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* c0 */
7770     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7771     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7772     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7773     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* c8 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7784     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7785     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7786     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7787     /* d0 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* d8 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* e0 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* e8 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7823     /* f0 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* f8 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841   },
7842   /* XOP_09 */
7843   {
7844     /* 00 */
7845     { Bad_Opcode },
7846     { REG_TABLE (REG_XOP_TBM_01) },
7847     { REG_TABLE (REG_XOP_TBM_02) },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 08 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 10 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { REG_TABLE (REG_XOP_LWPCB) },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 18 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 20 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 28 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 30 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 38 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 40 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     /* 48 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 50 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* 58 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 60 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 68 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 70 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 78 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* 80 */
7989     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7990     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7991     { "vfrczss",        { XM, EXd }, 0 },
7992     { "vfrczsd",        { XM, EXq }, 0 },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* 88 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* 90 */
8007     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8008     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8009     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8010     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     /* 98 */
8016     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* a0 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* a8 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* b0 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* b8 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* c0 */
8061     { Bad_Opcode },
8062     { "vphaddbw",       { XM, EXxmm }, 0 },
8063     { "vphaddbd",       { XM, EXxmm }, 0 },
8064     { "vphaddbq",       { XM, EXxmm }, 0 },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { "vphaddwd",       { XM, EXxmm }, 0 },
8068     { "vphaddwq",       { XM, EXxmm }, 0 },
8069     /* c8 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { "vphadddq",       { XM, EXxmm }, 0 },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* d0 */
8079     { Bad_Opcode },
8080     { "vphaddubw",      { XM, EXxmm }, 0 },
8081     { "vphaddubd",      { XM, EXxmm }, 0 },
8082     { "vphaddubq",      { XM, EXxmm }, 0 },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { "vphadduwd",      { XM, EXxmm }, 0 },
8086     { "vphadduwq",      { XM, EXxmm }, 0 },
8087     /* d8 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { "vphaddudq",      { XM, EXxmm }, 0 },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* e0 */
8097     { Bad_Opcode },
8098     { "vphsubbw",       { XM, EXxmm }, 0 },
8099     { "vphsubwd",       { XM, EXxmm }, 0 },
8100     { "vphsubdq",       { XM, EXxmm }, 0 },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* e8 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* f0 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* f8 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132   },
8133   /* XOP_0A */
8134   {
8135     /* 00 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 08 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 10 */
8154     { "bextrS", { Gdq, Edq, Id }, 0 },
8155     { Bad_Opcode },
8156     { REG_TABLE (REG_XOP_LWP) },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 18 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 20 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 28 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 30 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 38 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 40 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 48 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 50 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* 58 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 60 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 68 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 70 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 78 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 80 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* 88 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* 90 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* 98 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* a0 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* a8 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* b0 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* b8 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* c0 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* c8 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* d0 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* d8 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* e0 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* e8 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* f0 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* f8 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423   },
8424 };
8425
8426 static const struct dis386 vex_table[][256] = {
8427   /* VEX_0F */
8428   {
8429     /* 00 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 08 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 10 */
8448     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8451     { MOD_TABLE (MOD_VEX_0F13) },
8452     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8453     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8454     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8455     { MOD_TABLE (MOD_VEX_0F17) },
8456     /* 18 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 20 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 28 */
8475     { "vmovapX",        { XM, EXx }, 0 },
8476     { "vmovapX",        { EXxS, XM }, 0 },
8477     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8478     { MOD_TABLE (MOD_VEX_0F2B) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8483     /* 30 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* 38 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* 40 */
8502     { Bad_Opcode },
8503     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8505     { Bad_Opcode },
8506     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8510     /* 48 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* 50 */
8520     { MOD_TABLE (MOD_VEX_0F50) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8524     { "vandpX",         { XM, Vex, EXx }, 0 },
8525     { "vandnpX",        { XM, Vex, EXx }, 0 },
8526     { "vorpX",          { XM, Vex, EXx }, 0 },
8527     { "vxorpX",         { XM, Vex, EXx }, 0 },
8528     /* 58 */
8529     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8537     /* 60 */
8538     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8546     /* 68 */
8547     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8555     /* 70 */
8556     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8557     { REG_TABLE (REG_VEX_0F71) },
8558     { REG_TABLE (REG_VEX_0F72) },
8559     { REG_TABLE (REG_VEX_0F73) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8564     /* 78 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8573     /* 80 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* 88 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* 90 */
8592     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* 98 */
8601     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* a0 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* a8 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { REG_TABLE (REG_VEX_0FAE) },
8626     { Bad_Opcode },
8627     /* b0 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* b8 */
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     /* c0 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8649     { Bad_Opcode },
8650     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8652     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8653     { Bad_Opcode },
8654     /* c8 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* d0 */
8664     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8672     /* d8 */
8673     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8681     /* e0 */
8682     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8690     /* e8 */
8691     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8699     /* f0 */
8700     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8708     /* f8 */
8709     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8716     { Bad_Opcode },
8717   },
8718   /* VEX_0F38 */
8719   {
8720     /* 00 */
8721     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8729     /* 08 */
8730     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8738     /* 10 */
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8747     /* 18 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8751     { Bad_Opcode },
8752     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8755     { Bad_Opcode },
8756     /* 20 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     /* 28 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8774     /* 30 */
8775     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8783     /* 38 */
8784     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8792     /* 40 */
8793     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8801     /* 48 */
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* 50 */
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* 58 */
8820     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* 60 */
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* 68 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* 70 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     /* 78 */
8856     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* 80 */
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     /* 88 */
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8879     { Bad_Opcode },
8880     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8881     { Bad_Opcode },
8882     /* 90 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8891     /* 98 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8900     /* a0 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8909     /* a8 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8918     /* b0 */
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8927     /* b8 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8936     /* c0 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* c8 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8954     /* d0 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* d8 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8972     /* e0 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* e8 */
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* f0 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8994     { REG_TABLE (REG_VEX_0F38F3) },
8995     { Bad_Opcode },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8999     /* f8 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008   },
9009   /* VEX_0F3A */
9010   {
9011     /* 00 */
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9019     { Bad_Opcode },
9020     /* 08 */
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9029     /* 10 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9038     /* 18 */
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 20 */
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 28 */
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     /* 30 */
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     /* 38 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     /* 40 */
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9087     { Bad_Opcode },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9091     { Bad_Opcode },
9092     /* 48 */
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     /* 50 */
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     /* 58 */
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9119     /* 60 */
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     /* 68 */
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9137     /* 70 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* 78 */
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9155     /* 80 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* 88 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     /* 90 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* 98 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     /* a0 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* a8 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* b0 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* b8 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* c0 */
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     /* c8 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9244     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9245     /* d0 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     /* d8 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9263     /* e0 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* e8 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     /* f0 */
9282     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* f8 */
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299   },
9300 };
9301
9302 #include "i386-dis-evex.h"
9303
9304 static const struct dis386 vex_len_table[][2] = {
9305   /* VEX_LEN_0F12_P_0_M_0 */
9306   {
9307     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9308   },
9309
9310   /* VEX_LEN_0F12_P_0_M_1 */
9311   {
9312     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9313   },
9314
9315   /* VEX_LEN_0F12_P_2 */
9316   {
9317     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9318   },
9319
9320   /* VEX_LEN_0F13_M_0 */
9321   {
9322     { "vmovlpX",        { EXq, XM }, 0 },
9323   },
9324
9325   /* VEX_LEN_0F16_P_0_M_0 */
9326   {
9327     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9328   },
9329
9330   /* VEX_LEN_0F16_P_0_M_1 */
9331   {
9332     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F16_P_2 */
9336   {
9337     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F17_M_0 */
9341   {
9342     { "vmovhpX",        { EXq, XM }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F41_P_0 */
9346   {
9347     { Bad_Opcode },
9348     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9349   },
9350   /* VEX_LEN_0F41_P_2 */
9351   {
9352     { Bad_Opcode },
9353     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9354   },
9355   /* VEX_LEN_0F42_P_0 */
9356   {
9357     { Bad_Opcode },
9358     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9359   },
9360   /* VEX_LEN_0F42_P_2 */
9361   {
9362     { Bad_Opcode },
9363     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9364   },
9365   /* VEX_LEN_0F44_P_0 */
9366   {
9367     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9368   },
9369   /* VEX_LEN_0F44_P_2 */
9370   {
9371     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9372   },
9373   /* VEX_LEN_0F45_P_0 */
9374   {
9375     { Bad_Opcode },
9376     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9377   },
9378   /* VEX_LEN_0F45_P_2 */
9379   {
9380     { Bad_Opcode },
9381     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9382   },
9383   /* VEX_LEN_0F46_P_0 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9387   },
9388   /* VEX_LEN_0F46_P_2 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9392   },
9393   /* VEX_LEN_0F47_P_0 */
9394   {
9395     { Bad_Opcode },
9396     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9397   },
9398   /* VEX_LEN_0F47_P_2 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9402   },
9403   /* VEX_LEN_0F4A_P_0 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9407   },
9408   /* VEX_LEN_0F4A_P_2 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9412   },
9413   /* VEX_LEN_0F4B_P_0 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9417   },
9418   /* VEX_LEN_0F4B_P_2 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9422   },
9423
9424   /* VEX_LEN_0F6E_P_2 */
9425   {
9426     { "vmovK",          { XMScalar, Edq }, 0 },
9427   },
9428
9429   /* VEX_LEN_0F77_P_1 */
9430   {
9431     { "vzeroupper",     { XX }, 0 },
9432     { "vzeroall",       { XX }, 0 },
9433   },
9434
9435   /* VEX_LEN_0F7E_P_1 */
9436   {
9437     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9438   },
9439
9440   /* VEX_LEN_0F7E_P_2 */
9441   {
9442     { "vmovK",          { Edq, XMScalar }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F90_P_0 */
9446   {
9447     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9448   },
9449
9450   /* VEX_LEN_0F90_P_2 */
9451   {
9452     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9453   },
9454
9455   /* VEX_LEN_0F91_P_0 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9458   },
9459
9460   /* VEX_LEN_0F91_P_2 */
9461   {
9462     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9463   },
9464
9465   /* VEX_LEN_0F92_P_0 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9468   },
9469
9470   /* VEX_LEN_0F92_P_2 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F92_P_3 */
9476   {
9477     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F93_P_0 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F93_P_2 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F93_P_3 */
9491   {
9492     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F98_P_0 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F98_P_2 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F99_P_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F99_P_2 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0FAE_R_2_M_0 */
9516   {
9517     { "vldmxcsr",       { Md }, 0 },
9518   },
9519
9520   /* VEX_LEN_0FAE_R_3_M_0 */
9521   {
9522     { "vstmxcsr",       { Md }, 0 },
9523   },
9524
9525   /* VEX_LEN_0FC4_P_2 */
9526   {
9527     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9528   },
9529
9530   /* VEX_LEN_0FC5_P_2 */
9531   {
9532     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9533   },
9534
9535   /* VEX_LEN_0FD6_P_2 */
9536   {
9537     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9538   },
9539
9540   /* VEX_LEN_0FF7_P_2 */
9541   {
9542     { "vmaskmovdqu",    { XM, XS }, 0 },
9543   },
9544
9545   /* VEX_LEN_0F3816_P_2 */
9546   {
9547     { Bad_Opcode },
9548     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9549   },
9550
9551   /* VEX_LEN_0F3819_P_2 */
9552   {
9553     { Bad_Opcode },
9554     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9555   },
9556
9557   /* VEX_LEN_0F381A_P_2_M_0 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9561   },
9562
9563   /* VEX_LEN_0F3836_P_2 */
9564   {
9565     { Bad_Opcode },
9566     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9567   },
9568
9569   /* VEX_LEN_0F3841_P_2 */
9570   {
9571     { "vphminposuw",    { XM, EXx }, 0 },
9572   },
9573
9574   /* VEX_LEN_0F385A_P_2_M_0 */
9575   {
9576     { Bad_Opcode },
9577     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9578   },
9579
9580   /* VEX_LEN_0F38DB_P_2 */
9581   {
9582     { "vaesimc",        { XM, EXx }, 0 },
9583   },
9584
9585   /* VEX_LEN_0F38F2_P_0 */
9586   {
9587     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F38F3_R_1_P_0 */
9591   {
9592     { "blsrS",          { VexGdq, Edq }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F38F3_R_2_P_0 */
9596   {
9597     { "blsmskS",        { VexGdq, Edq }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F38F3_R_3_P_0 */
9601   {
9602     { "blsiS",          { VexGdq, Edq }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F38F5_P_0 */
9606   {
9607     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F5_P_1 */
9611   {
9612     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F38F5_P_3 */
9616   {
9617     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F6_P_3 */
9621   {
9622     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F7_P_0 */
9626   {
9627     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F7_P_1 */
9631   {
9632     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F7_P_2 */
9636   {
9637     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F7_P_3 */
9641   {
9642     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F3A00_P_2 */
9646   {
9647     { Bad_Opcode },
9648     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9649   },
9650
9651   /* VEX_LEN_0F3A01_P_2 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9655   },
9656
9657   /* VEX_LEN_0F3A06_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F3A14_P_2 */
9664   {
9665     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F3A15_P_2 */
9669   {
9670     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F3A16_P_2  */
9674   {
9675     { "vpextrK",        { Edq, XM, Ib }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F3A17_P_2 */
9679   {
9680     { "vextractps",     { Edqd, XM, Ib }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F3A18_P_2 */
9684   {
9685     { Bad_Opcode },
9686     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9687   },
9688
9689   /* VEX_LEN_0F3A19_P_2 */
9690   {
9691     { Bad_Opcode },
9692     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9693   },
9694
9695   /* VEX_LEN_0F3A20_P_2 */
9696   {
9697     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9698   },
9699
9700   /* VEX_LEN_0F3A21_P_2 */
9701   {
9702     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F3A22_P_2 */
9706   {
9707     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F3A30_P_2 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9713   },
9714
9715   /* VEX_LEN_0F3A31_P_2 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9718   },
9719
9720   /* VEX_LEN_0F3A32_P_2 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9723   },
9724
9725   /* VEX_LEN_0F3A33_P_2 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9728   },
9729
9730   /* VEX_LEN_0F3A38_P_2 */
9731   {
9732     { Bad_Opcode },
9733     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9734   },
9735
9736   /* VEX_LEN_0F3A39_P_2 */
9737   {
9738     { Bad_Opcode },
9739     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9740   },
9741
9742   /* VEX_LEN_0F3A41_P_2 */
9743   {
9744     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9745   },
9746
9747   /* VEX_LEN_0F3A46_P_2 */
9748   {
9749     { Bad_Opcode },
9750     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9751   },
9752
9753   /* VEX_LEN_0F3A60_P_2 */
9754   {
9755     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9756   },
9757
9758   /* VEX_LEN_0F3A61_P_2 */
9759   {
9760     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9761   },
9762
9763   /* VEX_LEN_0F3A62_P_2 */
9764   {
9765     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9766   },
9767
9768   /* VEX_LEN_0F3A63_P_2 */
9769   {
9770     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9771   },
9772
9773   /* VEX_LEN_0F3A6A_P_2 */
9774   {
9775     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F3A6B_P_2 */
9779   {
9780     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A6E_P_2 */
9784   {
9785     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A6F_P_2 */
9789   {
9790     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A7A_P_2 */
9794   {
9795     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A7B_P_2 */
9799   {
9800     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A7E_P_2 */
9804   {
9805     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A7F_P_2 */
9809   {
9810     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3ADF_P_2 */
9814   {
9815     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3AF0_P_3 */
9819   {
9820     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9821   },
9822
9823   /* VEX_LEN_0FXOP_08_CC */
9824   {
9825      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9826   },
9827
9828   /* VEX_LEN_0FXOP_08_CD */
9829   {
9830      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9831   },
9832
9833   /* VEX_LEN_0FXOP_08_CE */
9834   {
9835      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9836   },
9837
9838   /* VEX_LEN_0FXOP_08_CF */
9839   {
9840      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9841   },
9842
9843   /* VEX_LEN_0FXOP_08_EC */
9844   {
9845      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9846   },
9847
9848   /* VEX_LEN_0FXOP_08_ED */
9849   {
9850      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_EE */
9854   {
9855      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_EF */
9859   {
9860      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_09_80 */
9864   {
9865     { "vfrczps",        { XM, EXxmm }, 0 },
9866     { "vfrczps",        { XM, EXymmq }, 0 },
9867   },
9868
9869   /* VEX_LEN_0FXOP_09_81 */
9870   {
9871     { "vfrczpd",        { XM, EXxmm }, 0 },
9872     { "vfrczpd",        { XM, EXymmq }, 0 },
9873   },
9874 };
9875
9876 #include "i386-dis-evex-len.h"
9877
9878 static const struct dis386 vex_w_table[][2] = {
9879   {
9880     /* VEX_W_0F41_P_0_LEN_1 */
9881     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9882     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9883   },
9884   {
9885     /* VEX_W_0F41_P_2_LEN_1 */
9886     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9887     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9888   },
9889   {
9890     /* VEX_W_0F42_P_0_LEN_1 */
9891     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9892     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9893   },
9894   {
9895     /* VEX_W_0F42_P_2_LEN_1 */
9896     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9897     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9898   },
9899   {
9900     /* VEX_W_0F44_P_0_LEN_0 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F44_P_2_LEN_0 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F45_P_0_LEN_1 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F45_P_2_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F46_P_0_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F46_P_2_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F47_P_0_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F47_P_2_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F4A_P_0_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F4A_P_2_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F4B_P_0_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F4B_P_2_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9957   },
9958   {
9959     /* VEX_W_0F90_P_0_LEN_0 */
9960     { "kmovw",          { MaskG, MaskE }, 0 },
9961     { "kmovq",          { MaskG, MaskE }, 0 },
9962   },
9963   {
9964     /* VEX_W_0F90_P_2_LEN_0 */
9965     { "kmovb",          { MaskG, MaskBDE }, 0 },
9966     { "kmovd",          { MaskG, MaskBDE }, 0 },
9967   },
9968   {
9969     /* VEX_W_0F91_P_0_LEN_0 */
9970     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9971     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9972   },
9973   {
9974     /* VEX_W_0F91_P_2_LEN_0 */
9975     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9976     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9977   },
9978   {
9979     /* VEX_W_0F92_P_0_LEN_0 */
9980     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9981   },
9982   {
9983     /* VEX_W_0F92_P_2_LEN_0 */
9984     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9985   },
9986   {
9987     /* VEX_W_0F93_P_0_LEN_0 */
9988     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9989   },
9990   {
9991     /* VEX_W_0F93_P_2_LEN_0 */
9992     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9993   },
9994   {
9995     /* VEX_W_0F98_P_0_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9997     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9998   },
9999   {
10000     /* VEX_W_0F98_P_2_LEN_0 */
10001     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10002     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F99_P_0_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10007     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F99_P_2_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F380C_P_2  */
10016     { "vpermilps",      { XM, Vex, EXx }, 0 },
10017   },
10018   {
10019     /* VEX_W_0F380D_P_2  */
10020     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10021   },
10022   {
10023     /* VEX_W_0F380E_P_2  */
10024     { "vtestps",        { XM, EXx }, 0 },
10025   },
10026   {
10027     /* VEX_W_0F380F_P_2  */
10028     { "vtestpd",        { XM, EXx }, 0 },
10029   },
10030   {
10031     /* VEX_W_0F3816_P_2  */
10032     { "vpermps",        { XM, Vex, EXx }, 0 },
10033   },
10034   {
10035     /* VEX_W_0F3818_P_2 */
10036     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10037   },
10038   {
10039     /* VEX_W_0F3819_P_2 */
10040     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F381A_P_2_M_0 */
10044     { "vbroadcastf128", { XM, Mxmm }, 0 },
10045   },
10046   {
10047     /* VEX_W_0F382C_P_2_M_0 */
10048     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10049   },
10050   {
10051     /* VEX_W_0F382D_P_2_M_0 */
10052     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F382E_P_2_M_0 */
10056     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F382F_P_2_M_0 */
10060     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F3836_P_2  */
10064     { "vpermd",         { XM, Vex, EXx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F3846_P_2 */
10068     { "vpsravd",        { XM, Vex, EXx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3858_P_2 */
10072     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3859_P_2 */
10076     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F385A_P_2_M_0 */
10080     { "vbroadcasti128", { XM, Mxmm }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3878_P_2 */
10084     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3879_P_2 */
10088     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F38CF_P_2 */
10092     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F3A00_P_2 */
10096     { Bad_Opcode },
10097     { "vpermq",         { XM, EXx, Ib }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3A01_P_2 */
10101     { Bad_Opcode },
10102     { "vpermpd",        { XM, EXx, Ib }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F3A02_P_2 */
10106     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10107   },
10108   {
10109     /* VEX_W_0F3A04_P_2 */
10110     { "vpermilps",      { XM, EXx, Ib }, 0 },
10111   },
10112   {
10113     /* VEX_W_0F3A05_P_2 */
10114     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10115   },
10116   {
10117     /* VEX_W_0F3A06_P_2 */
10118     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A18_P_2 */
10122     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A19_P_2 */
10126     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10127   },
10128   {
10129     /* VEX_W_0F3A30_P_2_LEN_0 */
10130     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10131     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10132   },
10133   {
10134     /* VEX_W_0F3A31_P_2_LEN_0 */
10135     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10136     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10137   },
10138   {
10139     /* VEX_W_0F3A32_P_2_LEN_0 */
10140     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10141     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10142   },
10143   {
10144     /* VEX_W_0F3A33_P_2_LEN_0 */
10145     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10146     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10147   },
10148   {
10149     /* VEX_W_0F3A38_P_2 */
10150     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F3A39_P_2 */
10154     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F3A46_P_2 */
10158     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10159   },
10160   {
10161     /* VEX_W_0F3A48_P_2 */
10162     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10163     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A49_P_2 */
10167     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10168     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F3A4A_P_2 */
10172     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10173   },
10174   {
10175     /* VEX_W_0F3A4B_P_2 */
10176     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F3A4C_P_2 */
10180     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10181   },
10182   {
10183     /* VEX_W_0F3ACE_P_2 */
10184     { Bad_Opcode },
10185     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F3ACF_P_2 */
10189     { Bad_Opcode },
10190     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10191   },
10192
10193 #include "i386-dis-evex-w.h"
10194 };
10195
10196 static const struct dis386 mod_table[][2] = {
10197   {
10198     /* MOD_8D */
10199     { "leaS",           { Gv, M }, 0 },
10200   },
10201   {
10202     /* MOD_C6_REG_7 */
10203     { Bad_Opcode },
10204     { RM_TABLE (RM_C6_REG_7) },
10205   },
10206   {
10207     /* MOD_C7_REG_7 */
10208     { Bad_Opcode },
10209     { RM_TABLE (RM_C7_REG_7) },
10210   },
10211   {
10212     /* MOD_FF_REG_3 */
10213     { "Jcall^", { indirEp }, 0 },
10214   },
10215   {
10216     /* MOD_FF_REG_5 */
10217     { "Jjmp^", { indirEp }, 0 },
10218   },
10219   {
10220     /* MOD_0F01_REG_0 */
10221     { X86_64_TABLE (X86_64_0F01_REG_0) },
10222     { RM_TABLE (RM_0F01_REG_0) },
10223   },
10224   {
10225     /* MOD_0F01_REG_1 */
10226     { X86_64_TABLE (X86_64_0F01_REG_1) },
10227     { RM_TABLE (RM_0F01_REG_1) },
10228   },
10229   {
10230     /* MOD_0F01_REG_2 */
10231     { X86_64_TABLE (X86_64_0F01_REG_2) },
10232     { RM_TABLE (RM_0F01_REG_2) },
10233   },
10234   {
10235     /* MOD_0F01_REG_3 */
10236     { X86_64_TABLE (X86_64_0F01_REG_3) },
10237     { RM_TABLE (RM_0F01_REG_3) },
10238   },
10239   {
10240     /* MOD_0F01_REG_5 */
10241     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10242     { RM_TABLE (RM_0F01_REG_5) },
10243   },
10244   {
10245     /* MOD_0F01_REG_7 */
10246     { "invlpg",         { Mb }, 0 },
10247     { RM_TABLE (RM_0F01_REG_7) },
10248   },
10249   {
10250     /* MOD_0F12_PREFIX_0 */
10251     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10252     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10253   },
10254   {
10255     /* MOD_0F13 */
10256     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10257   },
10258   {
10259     /* MOD_0F16_PREFIX_0 */
10260     { "movhps",         { XM, EXq }, 0 },
10261     { "movlhps",        { XM, EXq }, 0 },
10262   },
10263   {
10264     /* MOD_0F17 */
10265     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10266   },
10267   {
10268     /* MOD_0F18_REG_0 */
10269     { "prefetchnta",    { Mb }, 0 },
10270   },
10271   {
10272     /* MOD_0F18_REG_1 */
10273     { "prefetcht0",     { Mb }, 0 },
10274   },
10275   {
10276     /* MOD_0F18_REG_2 */
10277     { "prefetcht1",     { Mb }, 0 },
10278   },
10279   {
10280     /* MOD_0F18_REG_3 */
10281     { "prefetcht2",     { Mb }, 0 },
10282   },
10283   {
10284     /* MOD_0F18_REG_4 */
10285     { "nop/reserved",   { Mb }, 0 },
10286   },
10287   {
10288     /* MOD_0F18_REG_5 */
10289     { "nop/reserved",   { Mb }, 0 },
10290   },
10291   {
10292     /* MOD_0F18_REG_6 */
10293     { "nop/reserved",   { Mb }, 0 },
10294   },
10295   {
10296     /* MOD_0F18_REG_7 */
10297     { "nop/reserved",   { Mb }, 0 },
10298   },
10299   {
10300     /* MOD_0F1A_PREFIX_0 */
10301     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10302     { "nopQ",           { Ev }, 0 },
10303   },
10304   {
10305     /* MOD_0F1B_PREFIX_0 */
10306     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10307     { "nopQ",           { Ev }, 0 },
10308   },
10309   {
10310     /* MOD_0F1B_PREFIX_1 */
10311     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10312     { "nopQ",           { Ev }, 0 },
10313   },
10314   {
10315     /* MOD_0F1C_PREFIX_0 */
10316     { REG_TABLE (REG_0F1C_MOD_0) },
10317     { "nopQ",           { Ev }, 0 },
10318   },
10319   {
10320     /* MOD_0F1E_PREFIX_1 */
10321     { "nopQ",           { Ev }, 0 },
10322     { REG_TABLE (REG_0F1E_MOD_3) },
10323   },
10324   {
10325     /* MOD_0F24 */
10326     { Bad_Opcode },
10327     { "movL",           { Rd, Td }, 0 },
10328   },
10329   {
10330     /* MOD_0F26 */
10331     { Bad_Opcode },
10332     { "movL",           { Td, Rd }, 0 },
10333   },
10334   {
10335     /* MOD_0F2B_PREFIX_0 */
10336     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10337   },
10338   {
10339     /* MOD_0F2B_PREFIX_1 */
10340     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10341   },
10342   {
10343     /* MOD_0F2B_PREFIX_2 */
10344     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10345   },
10346   {
10347     /* MOD_0F2B_PREFIX_3 */
10348     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10349   },
10350   {
10351     /* MOD_0F51 */
10352     { Bad_Opcode },
10353     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10354   },
10355   {
10356     /* MOD_0F71_REG_2 */
10357     { Bad_Opcode },
10358     { "psrlw",          { MS, Ib }, 0 },
10359   },
10360   {
10361     /* MOD_0F71_REG_4 */
10362     { Bad_Opcode },
10363     { "psraw",          { MS, Ib }, 0 },
10364   },
10365   {
10366     /* MOD_0F71_REG_6 */
10367     { Bad_Opcode },
10368     { "psllw",          { MS, Ib }, 0 },
10369   },
10370   {
10371     /* MOD_0F72_REG_2 */
10372     { Bad_Opcode },
10373     { "psrld",          { MS, Ib }, 0 },
10374   },
10375   {
10376     /* MOD_0F72_REG_4 */
10377     { Bad_Opcode },
10378     { "psrad",          { MS, Ib }, 0 },
10379   },
10380   {
10381     /* MOD_0F72_REG_6 */
10382     { Bad_Opcode },
10383     { "pslld",          { MS, Ib }, 0 },
10384   },
10385   {
10386     /* MOD_0F73_REG_2 */
10387     { Bad_Opcode },
10388     { "psrlq",          { MS, Ib }, 0 },
10389   },
10390   {
10391     /* MOD_0F73_REG_3 */
10392     { Bad_Opcode },
10393     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10394   },
10395   {
10396     /* MOD_0F73_REG_6 */
10397     { Bad_Opcode },
10398     { "psllq",          { MS, Ib }, 0 },
10399   },
10400   {
10401     /* MOD_0F73_REG_7 */
10402     { Bad_Opcode },
10403     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10404   },
10405   {
10406     /* MOD_0FAE_REG_0 */
10407     { "fxsave",         { FXSAVE }, 0 },
10408     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10409   },
10410   {
10411     /* MOD_0FAE_REG_1 */
10412     { "fxrstor",        { FXSAVE }, 0 },
10413     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10414   },
10415   {
10416     /* MOD_0FAE_REG_2 */
10417     { "ldmxcsr",        { Md }, 0 },
10418     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10419   },
10420   {
10421     /* MOD_0FAE_REG_3 */
10422     { "stmxcsr",        { Md }, 0 },
10423     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10424   },
10425   {
10426     /* MOD_0FAE_REG_4 */
10427     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10428     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10429   },
10430   {
10431     /* MOD_0FAE_REG_5 */
10432     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10433     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10434   },
10435   {
10436     /* MOD_0FAE_REG_6 */
10437     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10438     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_7 */
10442     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10443     { RM_TABLE (RM_0FAE_REG_7) },
10444   },
10445   {
10446     /* MOD_0FB2 */
10447     { "lssS",           { Gv, Mp }, 0 },
10448   },
10449   {
10450     /* MOD_0FB4 */
10451     { "lfsS",           { Gv, Mp }, 0 },
10452   },
10453   {
10454     /* MOD_0FB5 */
10455     { "lgsS",           { Gv, Mp }, 0 },
10456   },
10457   {
10458     /* MOD_0FC3 */
10459     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10460   },
10461   {
10462     /* MOD_0FC7_REG_3 */
10463     { "xrstors",        { FXSAVE }, 0 },
10464   },
10465   {
10466     /* MOD_0FC7_REG_4 */
10467     { "xsavec",         { FXSAVE }, 0 },
10468   },
10469   {
10470     /* MOD_0FC7_REG_5 */
10471     { "xsaves",         { FXSAVE }, 0 },
10472   },
10473   {
10474     /* MOD_0FC7_REG_6 */
10475     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10476     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10477   },
10478   {
10479     /* MOD_0FC7_REG_7 */
10480     { "vmptrst",        { Mq }, 0 },
10481     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10482   },
10483   {
10484     /* MOD_0FD7 */
10485     { Bad_Opcode },
10486     { "pmovmskb",       { Gdq, MS }, 0 },
10487   },
10488   {
10489     /* MOD_0FE7_PREFIX_2 */
10490     { "movntdq",        { Mx, XM }, 0 },
10491   },
10492   {
10493     /* MOD_0FF0_PREFIX_3 */
10494     { "lddqu",          { XM, M }, 0 },
10495   },
10496   {
10497     /* MOD_0F382A_PREFIX_2 */
10498     { "movntdqa",       { XM, Mx }, 0 },
10499   },
10500   {
10501     /* MOD_0F38F5_PREFIX_2 */
10502     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10503   },
10504   {
10505     /* MOD_0F38F6_PREFIX_0 */
10506     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10507   },
10508   {
10509     /* MOD_0F38F8_PREFIX_1 */
10510     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10511   },
10512   {
10513     /* MOD_0F38F8_PREFIX_2 */
10514     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10515   },
10516   {
10517     /* MOD_0F38F8_PREFIX_3 */
10518     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10519   },
10520   {
10521     /* MOD_0F38F9_PREFIX_0 */
10522     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10523   },
10524   {
10525     /* MOD_62_32BIT */
10526     { "bound{S|}",      { Gv, Ma }, 0 },
10527     { EVEX_TABLE (EVEX_0F) },
10528   },
10529   {
10530     /* MOD_C4_32BIT */
10531     { "lesS",           { Gv, Mp }, 0 },
10532     { VEX_C4_TABLE (VEX_0F) },
10533   },
10534   {
10535     /* MOD_C5_32BIT */
10536     { "ldsS",           { Gv, Mp }, 0 },
10537     { VEX_C5_TABLE (VEX_0F) },
10538   },
10539   {
10540     /* MOD_VEX_0F12_PREFIX_0 */
10541     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10542     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10543   },
10544   {
10545     /* MOD_VEX_0F13 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10547   },
10548   {
10549     /* MOD_VEX_0F16_PREFIX_0 */
10550     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10551     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10552   },
10553   {
10554     /* MOD_VEX_0F17 */
10555     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10556   },
10557   {
10558     /* MOD_VEX_0F2B */
10559     { "vmovntpX",       { Mx, XM }, 0 },
10560   },
10561   {
10562     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10563     { Bad_Opcode },
10564     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10573     { Bad_Opcode },
10574     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10583     { Bad_Opcode },
10584     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10603     { Bad_Opcode },
10604     { "knotw",          { MaskG, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10608     { Bad_Opcode },
10609     { "knotq",          { MaskG, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10613     { Bad_Opcode },
10614     { "knotb",          { MaskG, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10618     { Bad_Opcode },
10619     { "knotd",          { MaskG, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10623     { Bad_Opcode },
10624     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10633     { Bad_Opcode },
10634     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641  {
10642     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10643     { Bad_Opcode },
10644     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10653     { Bad_Opcode },
10654     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10663     { Bad_Opcode },
10664     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10683     { Bad_Opcode },
10684     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10693     { Bad_Opcode },
10694     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10703     { Bad_Opcode },
10704     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10713     { Bad_Opcode },
10714     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_0F50 */
10718     { Bad_Opcode },
10719     { "vmovmskpX",      { Gdq, XS }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_0F71_REG_2 */
10723     { Bad_Opcode },
10724     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10725   },
10726   {
10727     /* MOD_VEX_0F71_REG_4 */
10728     { Bad_Opcode },
10729     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10730   },
10731   {
10732     /* MOD_VEX_0F71_REG_6 */
10733     { Bad_Opcode },
10734     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10735   },
10736   {
10737     /* MOD_VEX_0F72_REG_2 */
10738     { Bad_Opcode },
10739     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10740   },
10741   {
10742     /* MOD_VEX_0F72_REG_4 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10745   },
10746   {
10747     /* MOD_VEX_0F72_REG_6 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10750   },
10751   {
10752     /* MOD_VEX_0F73_REG_2 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10755   },
10756   {
10757     /* MOD_VEX_0F73_REG_3 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10760   },
10761   {
10762     /* MOD_VEX_0F73_REG_6 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10765   },
10766   {
10767     /* MOD_VEX_0F73_REG_7 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10770   },
10771   {
10772     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10773     { "kmovw",          { Ew, MaskG }, 0 },
10774     { Bad_Opcode },
10775   },
10776   {
10777     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778     { "kmovq",          { Eq, MaskG }, 0 },
10779     { Bad_Opcode },
10780   },
10781   {
10782     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10783     { "kmovb",          { Eb, MaskG }, 0 },
10784     { Bad_Opcode },
10785   },
10786   {
10787     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788     { "kmovd",          { Ed, MaskG }, 0 },
10789     { Bad_Opcode },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10793     { Bad_Opcode },
10794     { "kmovw",          { MaskG, Rdq }, 0 },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10798     { Bad_Opcode },
10799     { "kmovb",          { MaskG, Rdq }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_0F92_P_3_LEN_0 */
10803     { Bad_Opcode },
10804     { "kmovK",          { MaskG, Rdq }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10808     { Bad_Opcode },
10809     { "kmovw",          { Gdq, MaskR }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10813     { Bad_Opcode },
10814     { "kmovb",          { Gdq, MaskR }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_0F93_P_3_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovK",          { Gdq, MaskR }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10823     { Bad_Opcode },
10824     { "kortestw", { MaskG, MaskR }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kortestq", { MaskG, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "kortestb", { MaskG, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kortestd", { MaskG, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10843     { Bad_Opcode },
10844     { "ktestw", { MaskG, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "ktestq", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10853     { Bad_Opcode },
10854     { "ktestb", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "ktestd", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_0FAE_REG_2 */
10863     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10864   },
10865   {
10866     /* MOD_VEX_0FAE_REG_3 */
10867     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10868   },
10869   {
10870     /* MOD_VEX_0FD7_PREFIX_2 */
10871     { Bad_Opcode },
10872     { "vpmovmskb",      { Gdq, XS }, 0 },
10873   },
10874   {
10875     /* MOD_VEX_0FE7_PREFIX_2 */
10876     { "vmovntdq",       { Mx, XM }, 0 },
10877   },
10878   {
10879     /* MOD_VEX_0FF0_PREFIX_3 */
10880     { "vlddqu",         { XM, M }, 0 },
10881   },
10882   {
10883     /* MOD_VEX_0F381A_PREFIX_2 */
10884     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10885   },
10886   {
10887     /* MOD_VEX_0F382A_PREFIX_2 */
10888     { "vmovntdqa",      { XM, Mx }, 0 },
10889   },
10890   {
10891     /* MOD_VEX_0F382C_PREFIX_2 */
10892     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10893   },
10894   {
10895     /* MOD_VEX_0F382D_PREFIX_2 */
10896     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10897   },
10898   {
10899     /* MOD_VEX_0F382E_PREFIX_2 */
10900     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10901   },
10902   {
10903     /* MOD_VEX_0F382F_PREFIX_2 */
10904     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10905   },
10906   {
10907     /* MOD_VEX_0F385A_PREFIX_2 */
10908     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10909   },
10910   {
10911     /* MOD_VEX_0F388C_PREFIX_2 */
10912     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_0F388E_PREFIX_2 */
10916     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10917   },
10918   {
10919     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10920     { Bad_Opcode },
10921     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10925     { Bad_Opcode },
10926     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10927   },
10928   {
10929     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10930     { Bad_Opcode },
10931     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10935     { Bad_Opcode },
10936     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10940     { Bad_Opcode },
10941     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958
10959 #include "i386-dis-evex-mod.h"
10960 };
10961
10962 static const struct dis386 rm_table[][8] = {
10963   {
10964     /* RM_C6_REG_7 */
10965     { "xabort",         { Skip_MODRM, Ib }, 0 },
10966   },
10967   {
10968     /* RM_C7_REG_7 */
10969     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10970   },
10971   {
10972     /* RM_0F01_REG_0 */
10973     { "enclv",          { Skip_MODRM }, 0 },
10974     { "vmcall",         { Skip_MODRM }, 0 },
10975     { "vmlaunch",       { Skip_MODRM }, 0 },
10976     { "vmresume",       { Skip_MODRM }, 0 },
10977     { "vmxoff",         { Skip_MODRM }, 0 },
10978     { "pconfig",        { Skip_MODRM }, 0 },
10979   },
10980   {
10981     /* RM_0F01_REG_1 */
10982     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10983     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10984     { "clac",           { Skip_MODRM }, 0 },
10985     { "stac",           { Skip_MODRM }, 0 },
10986     { Bad_Opcode },
10987     { Bad_Opcode },
10988     { Bad_Opcode },
10989     { "encls",          { Skip_MODRM }, 0 },
10990   },
10991   {
10992     /* RM_0F01_REG_2 */
10993     { "xgetbv",         { Skip_MODRM }, 0 },
10994     { "xsetbv",         { Skip_MODRM }, 0 },
10995     { Bad_Opcode },
10996     { Bad_Opcode },
10997     { "vmfunc",         { Skip_MODRM }, 0 },
10998     { "xend",           { Skip_MODRM }, 0 },
10999     { "xtest",          { Skip_MODRM }, 0 },
11000     { "enclu",          { Skip_MODRM }, 0 },
11001   },
11002   {
11003     /* RM_0F01_REG_3 */
11004     { "vmrun",          { Skip_MODRM }, 0 },
11005     { "vmmcall",        { Skip_MODRM }, 0 },
11006     { "vmload",         { Skip_MODRM }, 0 },
11007     { "vmsave",         { Skip_MODRM }, 0 },
11008     { "stgi",           { Skip_MODRM }, 0 },
11009     { "clgi",           { Skip_MODRM }, 0 },
11010     { "skinit",         { Skip_MODRM }, 0 },
11011     { "invlpga",        { Skip_MODRM }, 0 },
11012   },
11013   {
11014     /* RM_0F01_REG_5 */
11015     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11016     { Bad_Opcode },
11017     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11018     { Bad_Opcode },
11019     { Bad_Opcode },
11020     { Bad_Opcode },
11021     { "rdpkru",         { Skip_MODRM }, 0 },
11022     { "wrpkru",         { Skip_MODRM }, 0 },
11023   },
11024   {
11025     /* RM_0F01_REG_7 */
11026     { "swapgs",         { Skip_MODRM }, 0  },
11027     { "rdtscp",         { Skip_MODRM }, 0  },
11028     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11029     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11030     { "clzero",         { Skip_MODRM }, 0  },
11031   },
11032   {
11033     /* RM_0F1E_MOD_3_REG_7 */
11034     { "nopQ",           { Ev }, 0 },
11035     { "nopQ",           { Ev }, 0 },
11036     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11037     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11038     { "nopQ",           { Ev }, 0 },
11039     { "nopQ",           { Ev }, 0 },
11040     { "nopQ",           { Ev }, 0 },
11041     { "nopQ",           { Ev }, 0 },
11042   },
11043   {
11044     /* RM_0FAE_REG_6 */
11045     { "mfence",         { Skip_MODRM }, 0 },
11046   },
11047   {
11048     /* RM_0FAE_REG_7 */
11049     { "sfence",         { Skip_MODRM }, 0 },
11050
11051   },
11052 };
11053
11054 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11055
11056 /* We use the high bit to indicate different name for the same
11057    prefix.  */
11058 #define REP_PREFIX      (0xf3 | 0x100)
11059 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11060 #define XRELEASE_PREFIX (0xf3 | 0x400)
11061 #define BND_PREFIX      (0xf2 | 0x400)
11062 #define NOTRACK_PREFIX  (0x3e | 0x100)
11063
11064 static int
11065 ckprefix (void)
11066 {
11067   int newrex, i, length;
11068   rex = 0;
11069   rex_ignored = 0;
11070   prefixes = 0;
11071   used_prefixes = 0;
11072   rex_used = 0;
11073   last_lock_prefix = -1;
11074   last_repz_prefix = -1;
11075   last_repnz_prefix = -1;
11076   last_data_prefix = -1;
11077   last_addr_prefix = -1;
11078   last_rex_prefix = -1;
11079   last_seg_prefix = -1;
11080   fwait_prefix = -1;
11081   active_seg_prefix = 0;
11082   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11083     all_prefixes[i] = 0;
11084   i = 0;
11085   length = 0;
11086   /* The maximum instruction length is 15bytes.  */
11087   while (length < MAX_CODE_LENGTH - 1)
11088     {
11089       FETCH_DATA (the_info, codep + 1);
11090       newrex = 0;
11091       switch (*codep)
11092         {
11093         /* REX prefixes family.  */
11094         case 0x40:
11095         case 0x41:
11096         case 0x42:
11097         case 0x43:
11098         case 0x44:
11099         case 0x45:
11100         case 0x46:
11101         case 0x47:
11102         case 0x48:
11103         case 0x49:
11104         case 0x4a:
11105         case 0x4b:
11106         case 0x4c:
11107         case 0x4d:
11108         case 0x4e:
11109         case 0x4f:
11110           if (address_mode == mode_64bit)
11111             newrex = *codep;
11112           else
11113             return 1;
11114           last_rex_prefix = i;
11115           break;
11116         case 0xf3:
11117           prefixes |= PREFIX_REPZ;
11118           last_repz_prefix = i;
11119           break;
11120         case 0xf2:
11121           prefixes |= PREFIX_REPNZ;
11122           last_repnz_prefix = i;
11123           break;
11124         case 0xf0:
11125           prefixes |= PREFIX_LOCK;
11126           last_lock_prefix = i;
11127           break;
11128         case 0x2e:
11129           prefixes |= PREFIX_CS;
11130           last_seg_prefix = i;
11131           active_seg_prefix = PREFIX_CS;
11132           break;
11133         case 0x36:
11134           prefixes |= PREFIX_SS;
11135           last_seg_prefix = i;
11136           active_seg_prefix = PREFIX_SS;
11137           break;
11138         case 0x3e:
11139           prefixes |= PREFIX_DS;
11140           last_seg_prefix = i;
11141           active_seg_prefix = PREFIX_DS;
11142           break;
11143         case 0x26:
11144           prefixes |= PREFIX_ES;
11145           last_seg_prefix = i;
11146           active_seg_prefix = PREFIX_ES;
11147           break;
11148         case 0x64:
11149           prefixes |= PREFIX_FS;
11150           last_seg_prefix = i;
11151           active_seg_prefix = PREFIX_FS;
11152           break;
11153         case 0x65:
11154           prefixes |= PREFIX_GS;
11155           last_seg_prefix = i;
11156           active_seg_prefix = PREFIX_GS;
11157           break;
11158         case 0x66:
11159           prefixes |= PREFIX_DATA;
11160           last_data_prefix = i;
11161           break;
11162         case 0x67:
11163           prefixes |= PREFIX_ADDR;
11164           last_addr_prefix = i;
11165           break;
11166         case FWAIT_OPCODE:
11167           /* fwait is really an instruction.  If there are prefixes
11168              before the fwait, they belong to the fwait, *not* to the
11169              following instruction.  */
11170           fwait_prefix = i;
11171           if (prefixes || rex)
11172             {
11173               prefixes |= PREFIX_FWAIT;
11174               codep++;
11175               /* This ensures that the previous REX prefixes are noticed
11176                  as unused prefixes, as in the return case below.  */
11177               rex_used = rex;
11178               return 1;
11179             }
11180           prefixes = PREFIX_FWAIT;
11181           break;
11182         default:
11183           return 1;
11184         }
11185       /* Rex is ignored when followed by another prefix.  */
11186       if (rex)
11187         {
11188           rex_used = rex;
11189           return 1;
11190         }
11191       if (*codep != FWAIT_OPCODE)
11192         all_prefixes[i++] = *codep;
11193       rex = newrex;
11194       codep++;
11195       length++;
11196     }
11197   return 0;
11198 }
11199
11200 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11201    prefix byte.  */
11202
11203 static const char *
11204 prefix_name (int pref, int sizeflag)
11205 {
11206   static const char *rexes [16] =
11207     {
11208       "rex",            /* 0x40 */
11209       "rex.B",          /* 0x41 */
11210       "rex.X",          /* 0x42 */
11211       "rex.XB",         /* 0x43 */
11212       "rex.R",          /* 0x44 */
11213       "rex.RB",         /* 0x45 */
11214       "rex.RX",         /* 0x46 */
11215       "rex.RXB",        /* 0x47 */
11216       "rex.W",          /* 0x48 */
11217       "rex.WB",         /* 0x49 */
11218       "rex.WX",         /* 0x4a */
11219       "rex.WXB",        /* 0x4b */
11220       "rex.WR",         /* 0x4c */
11221       "rex.WRB",        /* 0x4d */
11222       "rex.WRX",        /* 0x4e */
11223       "rex.WRXB",       /* 0x4f */
11224     };
11225
11226   switch (pref)
11227     {
11228     /* REX prefixes family.  */
11229     case 0x40:
11230     case 0x41:
11231     case 0x42:
11232     case 0x43:
11233     case 0x44:
11234     case 0x45:
11235     case 0x46:
11236     case 0x47:
11237     case 0x48:
11238     case 0x49:
11239     case 0x4a:
11240     case 0x4b:
11241     case 0x4c:
11242     case 0x4d:
11243     case 0x4e:
11244     case 0x4f:
11245       return rexes [pref - 0x40];
11246     case 0xf3:
11247       return "repz";
11248     case 0xf2:
11249       return "repnz";
11250     case 0xf0:
11251       return "lock";
11252     case 0x2e:
11253       return "cs";
11254     case 0x36:
11255       return "ss";
11256     case 0x3e:
11257       return "ds";
11258     case 0x26:
11259       return "es";
11260     case 0x64:
11261       return "fs";
11262     case 0x65:
11263       return "gs";
11264     case 0x66:
11265       return (sizeflag & DFLAG) ? "data16" : "data32";
11266     case 0x67:
11267       if (address_mode == mode_64bit)
11268         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11269       else
11270         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11271     case FWAIT_OPCODE:
11272       return "fwait";
11273     case REP_PREFIX:
11274       return "rep";
11275     case XACQUIRE_PREFIX:
11276       return "xacquire";
11277     case XRELEASE_PREFIX:
11278       return "xrelease";
11279     case BND_PREFIX:
11280       return "bnd";
11281     case NOTRACK_PREFIX:
11282       return "notrack";
11283     default:
11284       return NULL;
11285     }
11286 }
11287
11288 static char op_out[MAX_OPERANDS][100];
11289 static int op_ad, op_index[MAX_OPERANDS];
11290 static int two_source_ops;
11291 static bfd_vma op_address[MAX_OPERANDS];
11292 static bfd_vma op_riprel[MAX_OPERANDS];
11293 static bfd_vma start_pc;
11294
11295 /*
11296  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11297  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11298  *   section of the "Virtual 8086 Mode" chapter.)
11299  * 'pc' should be the address of this instruction, it will
11300  *   be used to print the target address if this is a relative jump or call
11301  * The function returns the length of this instruction in bytes.
11302  */
11303
11304 static char intel_syntax;
11305 static char intel_mnemonic = !SYSV386_COMPAT;
11306 static char open_char;
11307 static char close_char;
11308 static char separator_char;
11309 static char scale_char;
11310
11311 enum x86_64_isa
11312 {
11313   amd64 = 0,
11314   intel64
11315 };
11316
11317 static enum x86_64_isa isa64;
11318
11319 /* Here for backwards compatibility.  When gdb stops using
11320    print_insn_i386_att and print_insn_i386_intel these functions can
11321    disappear, and print_insn_i386 be merged into print_insn.  */
11322 int
11323 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11324 {
11325   intel_syntax = 0;
11326
11327   return print_insn (pc, info);
11328 }
11329
11330 int
11331 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11332 {
11333   intel_syntax = 1;
11334
11335   return print_insn (pc, info);
11336 }
11337
11338 int
11339 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11340 {
11341   intel_syntax = -1;
11342
11343   return print_insn (pc, info);
11344 }
11345
11346 void
11347 print_i386_disassembler_options (FILE *stream)
11348 {
11349   fprintf (stream, _("\n\
11350 The following i386/x86-64 specific disassembler options are supported for use\n\
11351 with the -M switch (multiple options should be separated by commas):\n"));
11352
11353   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11354   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11355   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11356   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11357   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11358   fprintf (stream, _("  att-mnemonic\n"
11359                      "              Display instruction in AT&T mnemonic\n"));
11360   fprintf (stream, _("  intel-mnemonic\n"
11361                      "              Display instruction in Intel mnemonic\n"));
11362   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11363   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11364   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11365   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11366   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11367   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11368   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11369   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11370 }
11371
11372 /* Bad opcode.  */
11373 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11374
11375 /* Get a pointer to struct dis386 with a valid name.  */
11376
11377 static const struct dis386 *
11378 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11379 {
11380   int vindex, vex_table_index;
11381
11382   if (dp->name != NULL)
11383     return dp;
11384
11385   switch (dp->op[0].bytemode)
11386     {
11387     case USE_REG_TABLE:
11388       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11389       break;
11390
11391     case USE_MOD_TABLE:
11392       vindex = modrm.mod == 0x3 ? 1 : 0;
11393       dp = &mod_table[dp->op[1].bytemode][vindex];
11394       break;
11395
11396     case USE_RM_TABLE:
11397       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11398       break;
11399
11400     case USE_PREFIX_TABLE:
11401       if (need_vex)
11402         {
11403           /* The prefix in VEX is implicit.  */
11404           switch (vex.prefix)
11405             {
11406             case 0:
11407               vindex = 0;
11408               break;
11409             case REPE_PREFIX_OPCODE:
11410               vindex = 1;
11411               break;
11412             case DATA_PREFIX_OPCODE:
11413               vindex = 2;
11414               break;
11415             case REPNE_PREFIX_OPCODE:
11416               vindex = 3;
11417               break;
11418             default:
11419               abort ();
11420               break;
11421             }
11422         }
11423       else
11424         {
11425           int last_prefix = -1;
11426           int prefix = 0;
11427           vindex = 0;
11428           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11429              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11430              last one wins.  */
11431           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11432             {
11433               if (last_repz_prefix > last_repnz_prefix)
11434                 {
11435                   vindex = 1;
11436                   prefix = PREFIX_REPZ;
11437                   last_prefix = last_repz_prefix;
11438                 }
11439               else
11440                 {
11441                   vindex = 3;
11442                   prefix = PREFIX_REPNZ;
11443                   last_prefix = last_repnz_prefix;
11444                 }
11445
11446               /* Check if prefix should be ignored.  */
11447               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11448                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11449                    & prefix) != 0)
11450                 vindex = 0;
11451             }
11452
11453           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11454             {
11455               vindex = 2;
11456               prefix = PREFIX_DATA;
11457               last_prefix = last_data_prefix;
11458             }
11459
11460           if (vindex != 0)
11461             {
11462               used_prefixes |= prefix;
11463               all_prefixes[last_prefix] = 0;
11464             }
11465         }
11466       dp = &prefix_table[dp->op[1].bytemode][vindex];
11467       break;
11468
11469     case USE_X86_64_TABLE:
11470       vindex = address_mode == mode_64bit ? 1 : 0;
11471       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11472       break;
11473
11474     case USE_3BYTE_TABLE:
11475       FETCH_DATA (info, codep + 2);
11476       vindex = *codep++;
11477       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11478       end_codep = codep;
11479       modrm.mod = (*codep >> 6) & 3;
11480       modrm.reg = (*codep >> 3) & 7;
11481       modrm.rm = *codep & 7;
11482       break;
11483
11484     case USE_VEX_LEN_TABLE:
11485       if (!need_vex)
11486         abort ();
11487
11488       switch (vex.length)
11489         {
11490         case 128:
11491           vindex = 0;
11492           break;
11493         case 256:
11494           vindex = 1;
11495           break;
11496         default:
11497           abort ();
11498           break;
11499         }
11500
11501       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11502       break;
11503
11504     case USE_EVEX_LEN_TABLE:
11505       if (!vex.evex)
11506         abort ();
11507
11508       switch (vex.length)
11509         {
11510         case 128:
11511           vindex = 0;
11512           break;
11513         case 256:
11514           vindex = 1;
11515           break;
11516         case 512:
11517           vindex = 2;
11518           break;
11519         default:
11520           abort ();
11521           break;
11522         }
11523
11524       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11525       break;
11526
11527     case USE_XOP_8F_TABLE:
11528       FETCH_DATA (info, codep + 3);
11529       /* All bits in the REX prefix are ignored.  */
11530       rex_ignored = rex;
11531       rex = ~(*codep >> 5) & 0x7;
11532
11533       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11534       switch ((*codep & 0x1f))
11535         {
11536         default:
11537           dp = &bad_opcode;
11538           return dp;
11539         case 0x8:
11540           vex_table_index = XOP_08;
11541           break;
11542         case 0x9:
11543           vex_table_index = XOP_09;
11544           break;
11545         case 0xa:
11546           vex_table_index = XOP_0A;
11547           break;
11548         }
11549       codep++;
11550       vex.w = *codep & 0x80;
11551       if (vex.w && address_mode == mode_64bit)
11552         rex |= REX_W;
11553
11554       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11555       if (address_mode != mode_64bit)
11556         {
11557           /* In 16/32-bit mode REX_B is silently ignored.  */
11558           rex &= ~REX_B;
11559         }
11560
11561       vex.length = (*codep & 0x4) ? 256 : 128;
11562       switch ((*codep & 0x3))
11563         {
11564         case 0:
11565           break;
11566         case 1:
11567           vex.prefix = DATA_PREFIX_OPCODE;
11568           break;
11569         case 2:
11570           vex.prefix = REPE_PREFIX_OPCODE;
11571           break;
11572         case 3:
11573           vex.prefix = REPNE_PREFIX_OPCODE;
11574           break;
11575         }
11576       need_vex = 1;
11577       need_vex_reg = 1;
11578       codep++;
11579       vindex = *codep++;
11580       dp = &xop_table[vex_table_index][vindex];
11581
11582       end_codep = codep;
11583       FETCH_DATA (info, codep + 1);
11584       modrm.mod = (*codep >> 6) & 3;
11585       modrm.reg = (*codep >> 3) & 7;
11586       modrm.rm = *codep & 7;
11587       break;
11588
11589     case USE_VEX_C4_TABLE:
11590       /* VEX prefix.  */
11591       FETCH_DATA (info, codep + 3);
11592       /* All bits in the REX prefix are ignored.  */
11593       rex_ignored = rex;
11594       rex = ~(*codep >> 5) & 0x7;
11595       switch ((*codep & 0x1f))
11596         {
11597         default:
11598           dp = &bad_opcode;
11599           return dp;
11600         case 0x1:
11601           vex_table_index = VEX_0F;
11602           break;
11603         case 0x2:
11604           vex_table_index = VEX_0F38;
11605           break;
11606         case 0x3:
11607           vex_table_index = VEX_0F3A;
11608           break;
11609         }
11610       codep++;
11611       vex.w = *codep & 0x80;
11612       if (address_mode == mode_64bit)
11613         {
11614           if (vex.w)
11615             rex |= REX_W;
11616         }
11617       else
11618         {
11619           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11620              is ignored, other REX bits are 0 and the highest bit in
11621              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11622           rex = 0;
11623         }
11624       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11625       vex.length = (*codep & 0x4) ? 256 : 128;
11626       switch ((*codep & 0x3))
11627         {
11628         case 0:
11629           break;
11630         case 1:
11631           vex.prefix = DATA_PREFIX_OPCODE;
11632           break;
11633         case 2:
11634           vex.prefix = REPE_PREFIX_OPCODE;
11635           break;
11636         case 3:
11637           vex.prefix = REPNE_PREFIX_OPCODE;
11638           break;
11639         }
11640       need_vex = 1;
11641       need_vex_reg = 1;
11642       codep++;
11643       vindex = *codep++;
11644       dp = &vex_table[vex_table_index][vindex];
11645       end_codep = codep;
11646       /* There is no MODRM byte for VEX0F 77.  */
11647       if (vex_table_index != VEX_0F || vindex != 0x77)
11648         {
11649           FETCH_DATA (info, codep + 1);
11650           modrm.mod = (*codep >> 6) & 3;
11651           modrm.reg = (*codep >> 3) & 7;
11652           modrm.rm = *codep & 7;
11653         }
11654       break;
11655
11656     case USE_VEX_C5_TABLE:
11657       /* VEX prefix.  */
11658       FETCH_DATA (info, codep + 2);
11659       /* All bits in the REX prefix are ignored.  */
11660       rex_ignored = rex;
11661       rex = (*codep & 0x80) ? 0 : REX_R;
11662
11663       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11664          VEX.vvvv is 1.  */
11665       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11666       vex.length = (*codep & 0x4) ? 256 : 128;
11667       switch ((*codep & 0x3))
11668         {
11669         case 0:
11670           break;
11671         case 1:
11672           vex.prefix = DATA_PREFIX_OPCODE;
11673           break;
11674         case 2:
11675           vex.prefix = REPE_PREFIX_OPCODE;
11676           break;
11677         case 3:
11678           vex.prefix = REPNE_PREFIX_OPCODE;
11679           break;
11680         }
11681       need_vex = 1;
11682       need_vex_reg = 1;
11683       codep++;
11684       vindex = *codep++;
11685       dp = &vex_table[dp->op[1].bytemode][vindex];
11686       end_codep = codep;
11687       /* There is no MODRM byte for VEX 77.  */
11688       if (vindex != 0x77)
11689         {
11690           FETCH_DATA (info, codep + 1);
11691           modrm.mod = (*codep >> 6) & 3;
11692           modrm.reg = (*codep >> 3) & 7;
11693           modrm.rm = *codep & 7;
11694         }
11695       break;
11696
11697     case USE_VEX_W_TABLE:
11698       if (!need_vex)
11699         abort ();
11700
11701       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11702       break;
11703
11704     case USE_EVEX_TABLE:
11705       two_source_ops = 0;
11706       /* EVEX prefix.  */
11707       vex.evex = 1;
11708       FETCH_DATA (info, codep + 4);
11709       /* All bits in the REX prefix are ignored.  */
11710       rex_ignored = rex;
11711       /* The first byte after 0x62.  */
11712       rex = ~(*codep >> 5) & 0x7;
11713       vex.r = *codep & 0x10;
11714       switch ((*codep & 0xf))
11715         {
11716         default:
11717           return &bad_opcode;
11718         case 0x1:
11719           vex_table_index = EVEX_0F;
11720           break;
11721         case 0x2:
11722           vex_table_index = EVEX_0F38;
11723           break;
11724         case 0x3:
11725           vex_table_index = EVEX_0F3A;
11726           break;
11727         }
11728
11729       /* The second byte after 0x62.  */
11730       codep++;
11731       vex.w = *codep & 0x80;
11732       if (vex.w && address_mode == mode_64bit)
11733         rex |= REX_W;
11734
11735       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11736
11737       /* The U bit.  */
11738       if (!(*codep & 0x4))
11739         return &bad_opcode;
11740
11741       switch ((*codep & 0x3))
11742         {
11743         case 0:
11744           break;
11745         case 1:
11746           vex.prefix = DATA_PREFIX_OPCODE;
11747           break;
11748         case 2:
11749           vex.prefix = REPE_PREFIX_OPCODE;
11750           break;
11751         case 3:
11752           vex.prefix = REPNE_PREFIX_OPCODE;
11753           break;
11754         }
11755
11756       /* The third byte after 0x62.  */
11757       codep++;
11758
11759       /* Remember the static rounding bits.  */
11760       vex.ll = (*codep >> 5) & 3;
11761       vex.b = (*codep & 0x10) != 0;
11762
11763       vex.v = *codep & 0x8;
11764       vex.mask_register_specifier = *codep & 0x7;
11765       vex.zeroing = *codep & 0x80;
11766
11767       if (address_mode != mode_64bit)
11768         {
11769           /* In 16/32-bit mode silently ignore following bits.  */
11770           rex &= ~REX_B;
11771           vex.r = 1;
11772           vex.v = 1;
11773         }
11774
11775       need_vex = 1;
11776       need_vex_reg = 1;
11777       codep++;
11778       vindex = *codep++;
11779       dp = &evex_table[vex_table_index][vindex];
11780       end_codep = codep;
11781       FETCH_DATA (info, codep + 1);
11782       modrm.mod = (*codep >> 6) & 3;
11783       modrm.reg = (*codep >> 3) & 7;
11784       modrm.rm = *codep & 7;
11785
11786       /* Set vector length.  */
11787       if (modrm.mod == 3 && vex.b)
11788         vex.length = 512;
11789       else
11790         {
11791           switch (vex.ll)
11792             {
11793             case 0x0:
11794               vex.length = 128;
11795               break;
11796             case 0x1:
11797               vex.length = 256;
11798               break;
11799             case 0x2:
11800               vex.length = 512;
11801               break;
11802             default:
11803               return &bad_opcode;
11804             }
11805         }
11806       break;
11807
11808     case 0:
11809       dp = &bad_opcode;
11810       break;
11811
11812     default:
11813       abort ();
11814     }
11815
11816   if (dp->name != NULL)
11817     return dp;
11818   else
11819     return get_valid_dis386 (dp, info);
11820 }
11821
11822 static void
11823 get_sib (disassemble_info *info, int sizeflag)
11824 {
11825   /* If modrm.mod == 3, operand must be register.  */
11826   if (need_modrm
11827       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11828       && modrm.mod != 3
11829       && modrm.rm == 4)
11830     {
11831       FETCH_DATA (info, codep + 2);
11832       sib.index = (codep [1] >> 3) & 7;
11833       sib.scale = (codep [1] >> 6) & 3;
11834       sib.base = codep [1] & 7;
11835     }
11836 }
11837
11838 static int
11839 print_insn (bfd_vma pc, disassemble_info *info)
11840 {
11841   const struct dis386 *dp;
11842   int i;
11843   char *op_txt[MAX_OPERANDS];
11844   int needcomma;
11845   int sizeflag, orig_sizeflag;
11846   const char *p;
11847   struct dis_private priv;
11848   int prefix_length;
11849
11850   priv.orig_sizeflag = AFLAG | DFLAG;
11851   if ((info->mach & bfd_mach_i386_i386) != 0)
11852     address_mode = mode_32bit;
11853   else if (info->mach == bfd_mach_i386_i8086)
11854     {
11855       address_mode = mode_16bit;
11856       priv.orig_sizeflag = 0;
11857     }
11858   else
11859     address_mode = mode_64bit;
11860
11861   if (intel_syntax == (char) -1)
11862     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11863
11864   for (p = info->disassembler_options; p != NULL; )
11865     {
11866       if (CONST_STRNEQ (p, "amd64"))
11867         isa64 = amd64;
11868       else if (CONST_STRNEQ (p, "intel64"))
11869         isa64 = intel64;
11870       else if (CONST_STRNEQ (p, "x86-64"))
11871         {
11872           address_mode = mode_64bit;
11873           priv.orig_sizeflag = AFLAG | DFLAG;
11874         }
11875       else if (CONST_STRNEQ (p, "i386"))
11876         {
11877           address_mode = mode_32bit;
11878           priv.orig_sizeflag = AFLAG | DFLAG;
11879         }
11880       else if (CONST_STRNEQ (p, "i8086"))
11881         {
11882           address_mode = mode_16bit;
11883           priv.orig_sizeflag = 0;
11884         }
11885       else if (CONST_STRNEQ (p, "intel"))
11886         {
11887           intel_syntax = 1;
11888           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11889             intel_mnemonic = 1;
11890         }
11891       else if (CONST_STRNEQ (p, "att"))
11892         {
11893           intel_syntax = 0;
11894           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11895             intel_mnemonic = 0;
11896         }
11897       else if (CONST_STRNEQ (p, "addr"))
11898         {
11899           if (address_mode == mode_64bit)
11900             {
11901               if (p[4] == '3' && p[5] == '2')
11902                 priv.orig_sizeflag &= ~AFLAG;
11903               else if (p[4] == '6' && p[5] == '4')
11904                 priv.orig_sizeflag |= AFLAG;
11905             }
11906           else
11907             {
11908               if (p[4] == '1' && p[5] == '6')
11909                 priv.orig_sizeflag &= ~AFLAG;
11910               else if (p[4] == '3' && p[5] == '2')
11911                 priv.orig_sizeflag |= AFLAG;
11912             }
11913         }
11914       else if (CONST_STRNEQ (p, "data"))
11915         {
11916           if (p[4] == '1' && p[5] == '6')
11917             priv.orig_sizeflag &= ~DFLAG;
11918           else if (p[4] == '3' && p[5] == '2')
11919             priv.orig_sizeflag |= DFLAG;
11920         }
11921       else if (CONST_STRNEQ (p, "suffix"))
11922         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11923
11924       p = strchr (p, ',');
11925       if (p != NULL)
11926         p++;
11927     }
11928
11929   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11930     {
11931       (*info->fprintf_func) (info->stream,
11932                              _("64-bit address is disabled"));
11933       return -1;
11934     }
11935
11936   if (intel_syntax)
11937     {
11938       names64 = intel_names64;
11939       names32 = intel_names32;
11940       names16 = intel_names16;
11941       names8 = intel_names8;
11942       names8rex = intel_names8rex;
11943       names_seg = intel_names_seg;
11944       names_mm = intel_names_mm;
11945       names_bnd = intel_names_bnd;
11946       names_xmm = intel_names_xmm;
11947       names_ymm = intel_names_ymm;
11948       names_zmm = intel_names_zmm;
11949       index64 = intel_index64;
11950       index32 = intel_index32;
11951       names_mask = intel_names_mask;
11952       index16 = intel_index16;
11953       open_char = '[';
11954       close_char = ']';
11955       separator_char = '+';
11956       scale_char = '*';
11957     }
11958   else
11959     {
11960       names64 = att_names64;
11961       names32 = att_names32;
11962       names16 = att_names16;
11963       names8 = att_names8;
11964       names8rex = att_names8rex;
11965       names_seg = att_names_seg;
11966       names_mm = att_names_mm;
11967       names_bnd = att_names_bnd;
11968       names_xmm = att_names_xmm;
11969       names_ymm = att_names_ymm;
11970       names_zmm = att_names_zmm;
11971       index64 = att_index64;
11972       index32 = att_index32;
11973       names_mask = att_names_mask;
11974       index16 = att_index16;
11975       open_char = '(';
11976       close_char =  ')';
11977       separator_char = ',';
11978       scale_char = ',';
11979     }
11980
11981   /* The output looks better if we put 7 bytes on a line, since that
11982      puts most long word instructions on a single line.  Use 8 bytes
11983      for Intel L1OM.  */
11984   if ((info->mach & bfd_mach_l1om) != 0)
11985     info->bytes_per_line = 8;
11986   else
11987     info->bytes_per_line = 7;
11988
11989   info->private_data = &priv;
11990   priv.max_fetched = priv.the_buffer;
11991   priv.insn_start = pc;
11992
11993   obuf[0] = 0;
11994   for (i = 0; i < MAX_OPERANDS; ++i)
11995     {
11996       op_out[i][0] = 0;
11997       op_index[i] = -1;
11998     }
11999
12000   the_info = info;
12001   start_pc = pc;
12002   start_codep = priv.the_buffer;
12003   codep = priv.the_buffer;
12004
12005   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12006     {
12007       const char *name;
12008
12009       /* Getting here means we tried for data but didn't get it.  That
12010          means we have an incomplete instruction of some sort.  Just
12011          print the first byte as a prefix or a .byte pseudo-op.  */
12012       if (codep > priv.the_buffer)
12013         {
12014           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12015           if (name != NULL)
12016             (*info->fprintf_func) (info->stream, "%s", name);
12017           else
12018             {
12019               /* Just print the first byte as a .byte instruction.  */
12020               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12021                                      (unsigned int) priv.the_buffer[0]);
12022             }
12023
12024           return 1;
12025         }
12026
12027       return -1;
12028     }
12029
12030   obufp = obuf;
12031   sizeflag = priv.orig_sizeflag;
12032
12033   if (!ckprefix () || rex_used)
12034     {
12035       /* Too many prefixes or unused REX prefixes.  */
12036       for (i = 0;
12037            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12038            i++)
12039         (*info->fprintf_func) (info->stream, "%s%s",
12040                                i == 0 ? "" : " ",
12041                                prefix_name (all_prefixes[i], sizeflag));
12042       return i;
12043     }
12044
12045   insn_codep = codep;
12046
12047   FETCH_DATA (info, codep + 1);
12048   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12049
12050   if (((prefixes & PREFIX_FWAIT)
12051        && ((*codep < 0xd8) || (*codep > 0xdf))))
12052     {
12053       /* Handle prefixes before fwait.  */
12054       for (i = 0; i < fwait_prefix && all_prefixes[i];
12055            i++)
12056         (*info->fprintf_func) (info->stream, "%s ",
12057                                prefix_name (all_prefixes[i], sizeflag));
12058       (*info->fprintf_func) (info->stream, "fwait");
12059       return i + 1;
12060     }
12061
12062   if (*codep == 0x0f)
12063     {
12064       unsigned char threebyte;
12065
12066       codep++;
12067       FETCH_DATA (info, codep + 1);
12068       threebyte = *codep;
12069       dp = &dis386_twobyte[threebyte];
12070       need_modrm = twobyte_has_modrm[*codep];
12071       codep++;
12072     }
12073   else
12074     {
12075       dp = &dis386[*codep];
12076       need_modrm = onebyte_has_modrm[*codep];
12077       codep++;
12078     }
12079
12080   /* Save sizeflag for printing the extra prefixes later before updating
12081      it for mnemonic and operand processing.  The prefix names depend
12082      only on the address mode.  */
12083   orig_sizeflag = sizeflag;
12084   if (prefixes & PREFIX_ADDR)
12085     sizeflag ^= AFLAG;
12086   if ((prefixes & PREFIX_DATA))
12087     sizeflag ^= DFLAG;
12088
12089   end_codep = codep;
12090   if (need_modrm)
12091     {
12092       FETCH_DATA (info, codep + 1);
12093       modrm.mod = (*codep >> 6) & 3;
12094       modrm.reg = (*codep >> 3) & 7;
12095       modrm.rm = *codep & 7;
12096     }
12097
12098   need_vex = 0;
12099   need_vex_reg = 0;
12100   vex_w_done = 0;
12101   memset (&vex, 0, sizeof (vex));
12102
12103   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12104     {
12105       get_sib (info, sizeflag);
12106       dofloat (sizeflag);
12107     }
12108   else
12109     {
12110       dp = get_valid_dis386 (dp, info);
12111       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12112         {
12113           get_sib (info, sizeflag);
12114           for (i = 0; i < MAX_OPERANDS; ++i)
12115             {
12116               obufp = op_out[i];
12117               op_ad = MAX_OPERANDS - 1 - i;
12118               if (dp->op[i].rtn)
12119                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12120               /* For EVEX instruction after the last operand masking
12121                  should be printed.  */
12122               if (i == 0 && vex.evex)
12123                 {
12124                   /* Don't print {%k0}.  */
12125                   if (vex.mask_register_specifier)
12126                     {
12127                       oappend ("{");
12128                       oappend (names_mask[vex.mask_register_specifier]);
12129                       oappend ("}");
12130                     }
12131                   if (vex.zeroing)
12132                     oappend ("{z}");
12133                 }
12134             }
12135         }
12136     }
12137
12138   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12139      are all 0s in inverted form.  */
12140   if (need_vex && vex.register_specifier != 0)
12141     {
12142       (*info->fprintf_func) (info->stream, "(bad)");
12143       return end_codep - priv.the_buffer;
12144     }
12145
12146   /* Check if the REX prefix is used.  */
12147   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12148     all_prefixes[last_rex_prefix] = 0;
12149
12150   /* Check if the SEG prefix is used.  */
12151   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12152                    | PREFIX_FS | PREFIX_GS)) != 0
12153       && (used_prefixes & active_seg_prefix) != 0)
12154     all_prefixes[last_seg_prefix] = 0;
12155
12156   /* Check if the ADDR prefix is used.  */
12157   if ((prefixes & PREFIX_ADDR) != 0
12158       && (used_prefixes & PREFIX_ADDR) != 0)
12159     all_prefixes[last_addr_prefix] = 0;
12160
12161   /* Check if the DATA prefix is used.  */
12162   if ((prefixes & PREFIX_DATA) != 0
12163       && (used_prefixes & PREFIX_DATA) != 0)
12164     all_prefixes[last_data_prefix] = 0;
12165
12166   /* Print the extra prefixes.  */
12167   prefix_length = 0;
12168   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12169     if (all_prefixes[i])
12170       {
12171         const char *name;
12172         name = prefix_name (all_prefixes[i], orig_sizeflag);
12173         if (name == NULL)
12174           abort ();
12175         prefix_length += strlen (name) + 1;
12176         (*info->fprintf_func) (info->stream, "%s ", name);
12177       }
12178
12179   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12180      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12181      used by putop and MMX/SSE operand and may be overriden by the
12182      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12183      separately.  */
12184   if (dp->prefix_requirement == PREFIX_OPCODE
12185       && dp != &bad_opcode
12186       && (((prefixes
12187             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12188            && (used_prefixes
12189                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12190           || ((((prefixes
12191                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12192                 == PREFIX_DATA)
12193                && (used_prefixes & PREFIX_DATA) == 0))))
12194     {
12195       (*info->fprintf_func) (info->stream, "(bad)");
12196       return end_codep - priv.the_buffer;
12197     }
12198
12199   /* Check maximum code length.  */
12200   if ((codep - start_codep) > MAX_CODE_LENGTH)
12201     {
12202       (*info->fprintf_func) (info->stream, "(bad)");
12203       return MAX_CODE_LENGTH;
12204     }
12205
12206   obufp = mnemonicendp;
12207   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12208     oappend (" ");
12209   oappend (" ");
12210   (*info->fprintf_func) (info->stream, "%s", obuf);
12211
12212   /* The enter and bound instructions are printed with operands in the same
12213      order as the intel book; everything else is printed in reverse order.  */
12214   if (intel_syntax || two_source_ops)
12215     {
12216       bfd_vma riprel;
12217
12218       for (i = 0; i < MAX_OPERANDS; ++i)
12219         op_txt[i] = op_out[i];
12220
12221       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12222           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12223         {
12224           op_txt[2] = op_out[3];
12225           op_txt[3] = op_out[2];
12226         }
12227
12228       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12229         {
12230           op_ad = op_index[i];
12231           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12232           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12233           riprel = op_riprel[i];
12234           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12235           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12236         }
12237     }
12238   else
12239     {
12240       for (i = 0; i < MAX_OPERANDS; ++i)
12241         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12242     }
12243
12244   needcomma = 0;
12245   for (i = 0; i < MAX_OPERANDS; ++i)
12246     if (*op_txt[i])
12247       {
12248         if (needcomma)
12249           (*info->fprintf_func) (info->stream, ",");
12250         if (op_index[i] != -1 && !op_riprel[i])
12251           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12252         else
12253           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12254         needcomma = 1;
12255       }
12256
12257   for (i = 0; i < MAX_OPERANDS; i++)
12258     if (op_index[i] != -1 && op_riprel[i])
12259       {
12260         (*info->fprintf_func) (info->stream, "        # ");
12261         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12262                                                 + op_address[op_index[i]]), info);
12263         break;
12264       }
12265   return codep - priv.the_buffer;
12266 }
12267
12268 static const char *float_mem[] = {
12269   /* d8 */
12270   "fadd{s|}",
12271   "fmul{s|}",
12272   "fcom{s|}",
12273   "fcomp{s|}",
12274   "fsub{s|}",
12275   "fsubr{s|}",
12276   "fdiv{s|}",
12277   "fdivr{s|}",
12278   /* d9 */
12279   "fld{s|}",
12280   "(bad)",
12281   "fst{s|}",
12282   "fstp{s|}",
12283   "fldenvIC",
12284   "fldcw",
12285   "fNstenvIC",
12286   "fNstcw",
12287   /* da */
12288   "fiadd{l|}",
12289   "fimul{l|}",
12290   "ficom{l|}",
12291   "ficomp{l|}",
12292   "fisub{l|}",
12293   "fisubr{l|}",
12294   "fidiv{l|}",
12295   "fidivr{l|}",
12296   /* db */
12297   "fild{l|}",
12298   "fisttp{l|}",
12299   "fist{l|}",
12300   "fistp{l|}",
12301   "(bad)",
12302   "fld{t||t|}",
12303   "(bad)",
12304   "fstp{t||t|}",
12305   /* dc */
12306   "fadd{l|}",
12307   "fmul{l|}",
12308   "fcom{l|}",
12309   "fcomp{l|}",
12310   "fsub{l|}",
12311   "fsubr{l|}",
12312   "fdiv{l|}",
12313   "fdivr{l|}",
12314   /* dd */
12315   "fld{l|}",
12316   "fisttp{ll|}",
12317   "fst{l||}",
12318   "fstp{l|}",
12319   "frstorIC",
12320   "(bad)",
12321   "fNsaveIC",
12322   "fNstsw",
12323   /* de */
12324   "fiadd{s|}",
12325   "fimul{s|}",
12326   "ficom{s|}",
12327   "ficomp{s|}",
12328   "fisub{s|}",
12329   "fisubr{s|}",
12330   "fidiv{s|}",
12331   "fidivr{s|}",
12332   /* df */
12333   "fild{s|}",
12334   "fisttp{s|}",
12335   "fist{s|}",
12336   "fistp{s|}",
12337   "fbld",
12338   "fild{ll|}",
12339   "fbstp",
12340   "fistp{ll|}",
12341 };
12342
12343 static const unsigned char float_mem_mode[] = {
12344   /* d8 */
12345   d_mode,
12346   d_mode,
12347   d_mode,
12348   d_mode,
12349   d_mode,
12350   d_mode,
12351   d_mode,
12352   d_mode,
12353   /* d9 */
12354   d_mode,
12355   0,
12356   d_mode,
12357   d_mode,
12358   0,
12359   w_mode,
12360   0,
12361   w_mode,
12362   /* da */
12363   d_mode,
12364   d_mode,
12365   d_mode,
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   /* db */
12372   d_mode,
12373   d_mode,
12374   d_mode,
12375   d_mode,
12376   0,
12377   t_mode,
12378   0,
12379   t_mode,
12380   /* dc */
12381   q_mode,
12382   q_mode,
12383   q_mode,
12384   q_mode,
12385   q_mode,
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   /* dd */
12390   q_mode,
12391   q_mode,
12392   q_mode,
12393   q_mode,
12394   0,
12395   0,
12396   0,
12397   w_mode,
12398   /* de */
12399   w_mode,
12400   w_mode,
12401   w_mode,
12402   w_mode,
12403   w_mode,
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   /* df */
12408   w_mode,
12409   w_mode,
12410   w_mode,
12411   w_mode,
12412   t_mode,
12413   q_mode,
12414   t_mode,
12415   q_mode
12416 };
12417
12418 #define ST { OP_ST, 0 }
12419 #define STi { OP_STi, 0 }
12420
12421 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12422 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12423 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12424 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12425 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12426 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12427 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12428 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12429 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12430
12431 static const struct dis386 float_reg[][8] = {
12432   /* d8 */
12433   {
12434     { "fadd",   { ST, STi }, 0 },
12435     { "fmul",   { ST, STi }, 0 },
12436     { "fcom",   { STi }, 0 },
12437     { "fcomp",  { STi }, 0 },
12438     { "fsub",   { ST, STi }, 0 },
12439     { "fsubr",  { ST, STi }, 0 },
12440     { "fdiv",   { ST, STi }, 0 },
12441     { "fdivr",  { ST, STi }, 0 },
12442   },
12443   /* d9 */
12444   {
12445     { "fld",    { STi }, 0 },
12446     { "fxch",   { STi }, 0 },
12447     { FGRPd9_2 },
12448     { Bad_Opcode },
12449     { FGRPd9_4 },
12450     { FGRPd9_5 },
12451     { FGRPd9_6 },
12452     { FGRPd9_7 },
12453   },
12454   /* da */
12455   {
12456     { "fcmovb", { ST, STi }, 0 },
12457     { "fcmove", { ST, STi }, 0 },
12458     { "fcmovbe",{ ST, STi }, 0 },
12459     { "fcmovu", { ST, STi }, 0 },
12460     { Bad_Opcode },
12461     { FGRPda_5 },
12462     { Bad_Opcode },
12463     { Bad_Opcode },
12464   },
12465   /* db */
12466   {
12467     { "fcmovnb",{ ST, STi }, 0 },
12468     { "fcmovne",{ ST, STi }, 0 },
12469     { "fcmovnbe",{ ST, STi }, 0 },
12470     { "fcmovnu",{ ST, STi }, 0 },
12471     { FGRPdb_4 },
12472     { "fucomi", { ST, STi }, 0 },
12473     { "fcomi",  { ST, STi }, 0 },
12474     { Bad_Opcode },
12475   },
12476   /* dc */
12477   {
12478     { "fadd",   { STi, ST }, 0 },
12479     { "fmul",   { STi, ST }, 0 },
12480     { Bad_Opcode },
12481     { Bad_Opcode },
12482     { "fsub{!M|r}",     { STi, ST }, 0 },
12483     { "fsub{M|}",       { STi, ST }, 0 },
12484     { "fdiv{!M|r}",     { STi, ST }, 0 },
12485     { "fdiv{M|}",       { STi, ST }, 0 },
12486   },
12487   /* dd */
12488   {
12489     { "ffree",  { STi }, 0 },
12490     { Bad_Opcode },
12491     { "fst",    { STi }, 0 },
12492     { "fstp",   { STi }, 0 },
12493     { "fucom",  { STi }, 0 },
12494     { "fucomp", { STi }, 0 },
12495     { Bad_Opcode },
12496     { Bad_Opcode },
12497   },
12498   /* de */
12499   {
12500     { "faddp",  { STi, ST }, 0 },
12501     { "fmulp",  { STi, ST }, 0 },
12502     { Bad_Opcode },
12503     { FGRPde_3 },
12504     { "fsub{!M|r}p",    { STi, ST }, 0 },
12505     { "fsub{M|}p",      { STi, ST }, 0 },
12506     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12507     { "fdiv{M|}p",      { STi, ST }, 0 },
12508   },
12509   /* df */
12510   {
12511     { "ffreep", { STi }, 0 },
12512     { Bad_Opcode },
12513     { Bad_Opcode },
12514     { Bad_Opcode },
12515     { FGRPdf_4 },
12516     { "fucomip", { ST, STi }, 0 },
12517     { "fcomip", { ST, STi }, 0 },
12518     { Bad_Opcode },
12519   },
12520 };
12521
12522 static char *fgrps[][8] = {
12523   /* Bad opcode 0 */
12524   {
12525     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12526   },
12527
12528   /* d9_2  1 */
12529   {
12530     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12531   },
12532
12533   /* d9_4  2 */
12534   {
12535     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12536   },
12537
12538   /* d9_5  3 */
12539   {
12540     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12541   },
12542
12543   /* d9_6  4 */
12544   {
12545     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12546   },
12547
12548   /* d9_7  5 */
12549   {
12550     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12551   },
12552
12553   /* da_5  6 */
12554   {
12555     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12556   },
12557
12558   /* db_4  7 */
12559   {
12560     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12561     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12562   },
12563
12564   /* de_3  8 */
12565   {
12566     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12567   },
12568
12569   /* df_4  9 */
12570   {
12571     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12572   },
12573 };
12574
12575 static void
12576 swap_operand (void)
12577 {
12578   mnemonicendp[0] = '.';
12579   mnemonicendp[1] = 's';
12580   mnemonicendp += 2;
12581 }
12582
12583 static void
12584 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12585                int sizeflag ATTRIBUTE_UNUSED)
12586 {
12587   /* Skip mod/rm byte.  */
12588   MODRM_CHECK;
12589   codep++;
12590 }
12591
12592 static void
12593 dofloat (int sizeflag)
12594 {
12595   const struct dis386 *dp;
12596   unsigned char floatop;
12597
12598   floatop = codep[-1];
12599
12600   if (modrm.mod != 3)
12601     {
12602       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12603
12604       putop (float_mem[fp_indx], sizeflag);
12605       obufp = op_out[0];
12606       op_ad = 2;
12607       OP_E (float_mem_mode[fp_indx], sizeflag);
12608       return;
12609     }
12610   /* Skip mod/rm byte.  */
12611   MODRM_CHECK;
12612   codep++;
12613
12614   dp = &float_reg[floatop - 0xd8][modrm.reg];
12615   if (dp->name == NULL)
12616     {
12617       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12618
12619       /* Instruction fnstsw is only one with strange arg.  */
12620       if (floatop == 0xdf && codep[-1] == 0xe0)
12621         strcpy (op_out[0], names16[0]);
12622     }
12623   else
12624     {
12625       putop (dp->name, sizeflag);
12626
12627       obufp = op_out[0];
12628       op_ad = 2;
12629       if (dp->op[0].rtn)
12630         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12631
12632       obufp = op_out[1];
12633       op_ad = 1;
12634       if (dp->op[1].rtn)
12635         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12636     }
12637 }
12638
12639 /* Like oappend (below), but S is a string starting with '%'.
12640    In Intel syntax, the '%' is elided.  */
12641 static void
12642 oappend_maybe_intel (const char *s)
12643 {
12644   oappend (s + intel_syntax);
12645 }
12646
12647 static void
12648 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12649 {
12650   oappend_maybe_intel ("%st");
12651 }
12652
12653 static void
12654 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12655 {
12656   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12657   oappend_maybe_intel (scratchbuf);
12658 }
12659
12660 /* Capital letters in template are macros.  */
12661 static int
12662 putop (const char *in_template, int sizeflag)
12663 {
12664   const char *p;
12665   int alt = 0;
12666   int cond = 1;
12667   unsigned int l = 0, len = 1;
12668   char last[4];
12669
12670 #define SAVE_LAST(c)                    \
12671   if (l < len && l < sizeof (last))     \
12672     last[l++] = c;                      \
12673   else                                  \
12674     abort ();
12675
12676   for (p = in_template; *p; p++)
12677     {
12678       switch (*p)
12679         {
12680         default:
12681           *obufp++ = *p;
12682           break;
12683         case '%':
12684           len++;
12685           break;
12686         case '!':
12687           cond = 0;
12688           break;
12689         case '{':
12690           if (intel_syntax)
12691             {
12692               while (*++p != '|')
12693                 if (*p == '}' || *p == '\0')
12694                   abort ();
12695             }
12696           /* Fall through.  */
12697         case 'I':
12698           alt = 1;
12699           continue;
12700         case '|':
12701           while (*++p != '}')
12702             {
12703               if (*p == '\0')
12704                 abort ();
12705             }
12706           break;
12707         case '}':
12708           break;
12709         case 'A':
12710           if (intel_syntax)
12711             break;
12712           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12713             *obufp++ = 'b';
12714           break;
12715         case 'B':
12716           if (l == 0 && len == 1)
12717             {
12718 case_B:
12719               if (intel_syntax)
12720                 break;
12721               if (sizeflag & SUFFIX_ALWAYS)
12722                 *obufp++ = 'b';
12723             }
12724           else
12725             {
12726               if (l != 1
12727                   || len != 2
12728                   || last[0] != 'L')
12729                 {
12730                   SAVE_LAST (*p);
12731                   break;
12732                 }
12733
12734               if (address_mode == mode_64bit
12735                   && !(prefixes & PREFIX_ADDR))
12736                 {
12737                   *obufp++ = 'a';
12738                   *obufp++ = 'b';
12739                   *obufp++ = 's';
12740                 }
12741
12742               goto case_B;
12743             }
12744           break;
12745         case 'C':
12746           if (intel_syntax && !alt)
12747             break;
12748           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12749             {
12750               if (sizeflag & DFLAG)
12751                 *obufp++ = intel_syntax ? 'd' : 'l';
12752               else
12753                 *obufp++ = intel_syntax ? 'w' : 's';
12754               used_prefixes |= (prefixes & PREFIX_DATA);
12755             }
12756           break;
12757         case 'D':
12758           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12759             break;
12760           USED_REX (REX_W);
12761           if (modrm.mod == 3)
12762             {
12763               if (rex & REX_W)
12764                 *obufp++ = 'q';
12765               else
12766                 {
12767                   if (sizeflag & DFLAG)
12768                     *obufp++ = intel_syntax ? 'd' : 'l';
12769                   else
12770                     *obufp++ = 'w';
12771                   used_prefixes |= (prefixes & PREFIX_DATA);
12772                 }
12773             }
12774           else
12775             *obufp++ = 'w';
12776           break;
12777         case 'E':               /* For jcxz/jecxz */
12778           if (address_mode == mode_64bit)
12779             {
12780               if (sizeflag & AFLAG)
12781                 *obufp++ = 'r';
12782               else
12783                 *obufp++ = 'e';
12784             }
12785           else
12786             if (sizeflag & AFLAG)
12787               *obufp++ = 'e';
12788           used_prefixes |= (prefixes & PREFIX_ADDR);
12789           break;
12790         case 'F':
12791           if (intel_syntax)
12792             break;
12793           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12794             {
12795               if (sizeflag & AFLAG)
12796                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12797               else
12798                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12799               used_prefixes |= (prefixes & PREFIX_ADDR);
12800             }
12801           break;
12802         case 'G':
12803           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12804             break;
12805           if ((rex & REX_W) || (sizeflag & DFLAG))
12806             *obufp++ = 'l';
12807           else
12808             *obufp++ = 'w';
12809           if (!(rex & REX_W))
12810             used_prefixes |= (prefixes & PREFIX_DATA);
12811           break;
12812         case 'H':
12813           if (intel_syntax)
12814             break;
12815           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12816               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12817             {
12818               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12819               *obufp++ = ',';
12820               *obufp++ = 'p';
12821               if (prefixes & PREFIX_DS)
12822                 *obufp++ = 't';
12823               else
12824                 *obufp++ = 'n';
12825             }
12826           break;
12827         case 'J':
12828           if (intel_syntax)
12829             break;
12830           *obufp++ = 'l';
12831           break;
12832         case 'K':
12833           USED_REX (REX_W);
12834           if (rex & REX_W)
12835             *obufp++ = 'q';
12836           else
12837             *obufp++ = 'd';
12838           break;
12839         case 'Z':
12840           if (l != 0 || len != 1)
12841             {
12842               if (l != 1 || len != 2 || last[0] != 'X')
12843                 {
12844                   SAVE_LAST (*p);
12845                   break;
12846                 }
12847               if (!need_vex || !vex.evex)
12848                 abort ();
12849               if (intel_syntax
12850                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12851                 break;
12852               switch (vex.length)
12853                 {
12854                 case 128:
12855                   *obufp++ = 'x';
12856                   break;
12857                 case 256:
12858                   *obufp++ = 'y';
12859                   break;
12860                 case 512:
12861                   *obufp++ = 'z';
12862                   break;
12863                 default:
12864                   abort ();
12865                 }
12866               break;
12867             }
12868           if (intel_syntax)
12869             break;
12870           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12871             {
12872               *obufp++ = 'q';
12873               break;
12874             }
12875           /* Fall through.  */
12876           goto case_L;
12877         case 'L':
12878           if (l != 0 || len != 1)
12879             {
12880               SAVE_LAST (*p);
12881               break;
12882             }
12883 case_L:
12884           if (intel_syntax)
12885             break;
12886           if (sizeflag & SUFFIX_ALWAYS)
12887             *obufp++ = 'l';
12888           break;
12889         case 'M':
12890           if (intel_mnemonic != cond)
12891             *obufp++ = 'r';
12892           break;
12893         case 'N':
12894           if ((prefixes & PREFIX_FWAIT) == 0)
12895             *obufp++ = 'n';
12896           else
12897             used_prefixes |= PREFIX_FWAIT;
12898           break;
12899         case 'O':
12900           USED_REX (REX_W);
12901           if (rex & REX_W)
12902             *obufp++ = 'o';
12903           else if (intel_syntax && (sizeflag & DFLAG))
12904             *obufp++ = 'q';
12905           else
12906             *obufp++ = 'd';
12907           if (!(rex & REX_W))
12908             used_prefixes |= (prefixes & PREFIX_DATA);
12909           break;
12910         case '&':
12911           if (!intel_syntax
12912               && address_mode == mode_64bit
12913               && isa64 == intel64)
12914             {
12915               *obufp++ = 'q';
12916               break;
12917             }
12918           /* Fall through.  */
12919         case 'T':
12920           if (!intel_syntax
12921               && address_mode == mode_64bit
12922               && ((sizeflag & DFLAG) || (rex & REX_W)))
12923             {
12924               *obufp++ = 'q';
12925               break;
12926             }
12927           /* Fall through.  */
12928           goto case_P;
12929         case 'P':
12930           if (l == 0 && len == 1)
12931             {
12932 case_P:
12933               if (intel_syntax)
12934                 {
12935                   if ((rex & REX_W) == 0
12936                       && (prefixes & PREFIX_DATA))
12937                     {
12938                       if ((sizeflag & DFLAG) == 0)
12939                         *obufp++ = 'w';
12940                       used_prefixes |= (prefixes & PREFIX_DATA);
12941                     }
12942                   break;
12943                 }
12944               if ((prefixes & PREFIX_DATA)
12945                   || (rex & REX_W)
12946                   || (sizeflag & SUFFIX_ALWAYS))
12947                 {
12948                   USED_REX (REX_W);
12949                   if (rex & REX_W)
12950                     *obufp++ = 'q';
12951                   else
12952                     {
12953                       if (sizeflag & DFLAG)
12954                         *obufp++ = 'l';
12955                       else
12956                         *obufp++ = 'w';
12957                       used_prefixes |= (prefixes & PREFIX_DATA);
12958                     }
12959                 }
12960             }
12961           else
12962             {
12963               if (l != 1 || len != 2 || last[0] != 'L')
12964                 {
12965                   SAVE_LAST (*p);
12966                   break;
12967                 }
12968
12969               if ((prefixes & PREFIX_DATA)
12970                   || (rex & REX_W)
12971                   || (sizeflag & SUFFIX_ALWAYS))
12972                 {
12973                   USED_REX (REX_W);
12974                   if (rex & REX_W)
12975                     *obufp++ = 'q';
12976                   else
12977                     {
12978                       if (sizeflag & DFLAG)
12979                         *obufp++ = intel_syntax ? 'd' : 'l';
12980                       else
12981                         *obufp++ = 'w';
12982                       used_prefixes |= (prefixes & PREFIX_DATA);
12983                     }
12984                 }
12985             }
12986           break;
12987         case 'U':
12988           if (intel_syntax)
12989             break;
12990           if (address_mode == mode_64bit
12991               && ((sizeflag & DFLAG) || (rex & REX_W)))
12992             {
12993               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12994                 *obufp++ = 'q';
12995               break;
12996             }
12997           /* Fall through.  */
12998           goto case_Q;
12999         case 'Q':
13000           if (l == 0 && len == 1)
13001             {
13002 case_Q:
13003               if (intel_syntax && !alt)
13004                 break;
13005               USED_REX (REX_W);
13006               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13007                 {
13008                   if (rex & REX_W)
13009                     *obufp++ = 'q';
13010                   else
13011                     {
13012                       if (sizeflag & DFLAG)
13013                         *obufp++ = intel_syntax ? 'd' : 'l';
13014                       else
13015                         *obufp++ = 'w';
13016                       used_prefixes |= (prefixes & PREFIX_DATA);
13017                     }
13018                 }
13019             }
13020           else
13021             {
13022               if (l != 1 || len != 2 || last[0] != 'L')
13023                 {
13024                   SAVE_LAST (*p);
13025                   break;
13026                 }
13027               if (intel_syntax
13028                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13029                 break;
13030               if ((rex & REX_W))
13031                 {
13032                   USED_REX (REX_W);
13033                   *obufp++ = 'q';
13034                 }
13035               else
13036                 *obufp++ = 'l';
13037             }
13038           break;
13039         case 'R':
13040           USED_REX (REX_W);
13041           if (rex & REX_W)
13042             *obufp++ = 'q';
13043           else if (sizeflag & DFLAG)
13044             {
13045               if (intel_syntax)
13046                   *obufp++ = 'd';
13047               else
13048                   *obufp++ = 'l';
13049             }
13050           else
13051             *obufp++ = 'w';
13052           if (intel_syntax && !p[1]
13053               && ((rex & REX_W) || (sizeflag & DFLAG)))
13054             *obufp++ = 'e';
13055           if (!(rex & REX_W))
13056             used_prefixes |= (prefixes & PREFIX_DATA);
13057           break;
13058         case 'V':
13059           if (l == 0 && len == 1)
13060             {
13061               if (intel_syntax)
13062                 break;
13063               if (address_mode == mode_64bit
13064                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13065                 {
13066                   if (sizeflag & SUFFIX_ALWAYS)
13067                     *obufp++ = 'q';
13068                   break;
13069                 }
13070             }
13071           else
13072             {
13073               if (l != 1
13074                   || len != 2
13075                   || last[0] != 'L')
13076                 {
13077                   SAVE_LAST (*p);
13078                   break;
13079                 }
13080
13081               if (rex & REX_W)
13082                 {
13083                   *obufp++ = 'a';
13084                   *obufp++ = 'b';
13085                   *obufp++ = 's';
13086                 }
13087             }
13088           /* Fall through.  */
13089           goto case_S;
13090         case 'S':
13091           if (l == 0 && len == 1)
13092             {
13093 case_S:
13094               if (intel_syntax)
13095                 break;
13096               if (sizeflag & SUFFIX_ALWAYS)
13097                 {
13098                   if (rex & REX_W)
13099                     *obufp++ = 'q';
13100                   else
13101                     {
13102                       if (sizeflag & DFLAG)
13103                         *obufp++ = 'l';
13104                       else
13105                         *obufp++ = 'w';
13106                       used_prefixes |= (prefixes & PREFIX_DATA);
13107                     }
13108                 }
13109             }
13110           else
13111             {
13112               if (l != 1
13113                   || len != 2
13114                   || last[0] != 'L')
13115                 {
13116                   SAVE_LAST (*p);
13117                   break;
13118                 }
13119
13120               if (address_mode == mode_64bit
13121                   && !(prefixes & PREFIX_ADDR))
13122                 {
13123                   *obufp++ = 'a';
13124                   *obufp++ = 'b';
13125                   *obufp++ = 's';
13126                 }
13127
13128               goto case_S;
13129             }
13130           break;
13131         case 'X':
13132           if (l != 0 || len != 1)
13133             {
13134               SAVE_LAST (*p);
13135               break;
13136             }
13137           if (need_vex && vex.prefix)
13138             {
13139               if (vex.prefix == DATA_PREFIX_OPCODE)
13140                 *obufp++ = 'd';
13141               else
13142                 *obufp++ = 's';
13143             }
13144           else
13145             {
13146               if (prefixes & PREFIX_DATA)
13147                 *obufp++ = 'd';
13148               else
13149                 *obufp++ = 's';
13150               used_prefixes |= (prefixes & PREFIX_DATA);
13151             }
13152           break;
13153         case 'Y':
13154           if (l == 0 && len == 1)
13155             abort ();
13156           else
13157             {
13158               if (l != 1 || len != 2 || last[0] != 'X')
13159                 {
13160                   SAVE_LAST (*p);
13161                   break;
13162                 }
13163               if (!need_vex)
13164                 abort ();
13165               if (intel_syntax
13166                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13167                 break;
13168               switch (vex.length)
13169                 {
13170                 case 128:
13171                   *obufp++ = 'x';
13172                   break;
13173                 case 256:
13174                   *obufp++ = 'y';
13175                   break;
13176                 case 512:
13177                   if (!vex.evex)
13178                 default:
13179                     abort ();
13180                 }
13181             }
13182           break;
13183         case 'W':
13184           if (l == 0 && len == 1)
13185             {
13186               /* operand size flag for cwtl, cbtw */
13187               USED_REX (REX_W);
13188               if (rex & REX_W)
13189                 {
13190                   if (intel_syntax)
13191                     *obufp++ = 'd';
13192                   else
13193                     *obufp++ = 'l';
13194                 }
13195               else if (sizeflag & DFLAG)
13196                 *obufp++ = 'w';
13197               else
13198                 *obufp++ = 'b';
13199               if (!(rex & REX_W))
13200                 used_prefixes |= (prefixes & PREFIX_DATA);
13201             }
13202           else
13203             {
13204               if (l != 1
13205                   || len != 2
13206                   || (last[0] != 'X'
13207                       && last[0] != 'L'))
13208                 {
13209                   SAVE_LAST (*p);
13210                   break;
13211                 }
13212               if (!need_vex)
13213                 abort ();
13214               if (last[0] == 'X')
13215                 *obufp++ = vex.w ? 'd': 's';
13216               else
13217                 *obufp++ = vex.w ? 'q': 'd';
13218             }
13219           break;
13220         case '^':
13221           if (intel_syntax)
13222             break;
13223           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13224             {
13225               if (sizeflag & DFLAG)
13226                 *obufp++ = 'l';
13227               else
13228                 *obufp++ = 'w';
13229               used_prefixes |= (prefixes & PREFIX_DATA);
13230             }
13231           break;
13232         case '@':
13233           if (intel_syntax)
13234             break;
13235           if (address_mode == mode_64bit
13236               && (isa64 == intel64
13237                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13238               *obufp++ = 'q';
13239           else if ((prefixes & PREFIX_DATA))
13240             {
13241               if (!(sizeflag & DFLAG))
13242                 *obufp++ = 'w';
13243               used_prefixes |= (prefixes & PREFIX_DATA);
13244             }
13245           break;
13246         }
13247       alt = 0;
13248     }
13249   *obufp = 0;
13250   mnemonicendp = obufp;
13251   return 0;
13252 }
13253
13254 static void
13255 oappend (const char *s)
13256 {
13257   obufp = stpcpy (obufp, s);
13258 }
13259
13260 static void
13261 append_seg (void)
13262 {
13263   /* Only print the active segment register.  */
13264   if (!active_seg_prefix)
13265     return;
13266
13267   used_prefixes |= active_seg_prefix;
13268   switch (active_seg_prefix)
13269     {
13270     case PREFIX_CS:
13271       oappend_maybe_intel ("%cs:");
13272       break;
13273     case PREFIX_DS:
13274       oappend_maybe_intel ("%ds:");
13275       break;
13276     case PREFIX_SS:
13277       oappend_maybe_intel ("%ss:");
13278       break;
13279     case PREFIX_ES:
13280       oappend_maybe_intel ("%es:");
13281       break;
13282     case PREFIX_FS:
13283       oappend_maybe_intel ("%fs:");
13284       break;
13285     case PREFIX_GS:
13286       oappend_maybe_intel ("%gs:");
13287       break;
13288     default:
13289       break;
13290     }
13291 }
13292
13293 static void
13294 OP_indirE (int bytemode, int sizeflag)
13295 {
13296   if (!intel_syntax)
13297     oappend ("*");
13298   OP_E (bytemode, sizeflag);
13299 }
13300
13301 static void
13302 print_operand_value (char *buf, int hex, bfd_vma disp)
13303 {
13304   if (address_mode == mode_64bit)
13305     {
13306       if (hex)
13307         {
13308           char tmp[30];
13309           int i;
13310           buf[0] = '0';
13311           buf[1] = 'x';
13312           sprintf_vma (tmp, disp);
13313           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13314           strcpy (buf + 2, tmp + i);
13315         }
13316       else
13317         {
13318           bfd_signed_vma v = disp;
13319           char tmp[30];
13320           int i;
13321           if (v < 0)
13322             {
13323               *(buf++) = '-';
13324               v = -disp;
13325               /* Check for possible overflow on 0x8000000000000000.  */
13326               if (v < 0)
13327                 {
13328                   strcpy (buf, "9223372036854775808");
13329                   return;
13330                 }
13331             }
13332           if (!v)
13333             {
13334               strcpy (buf, "0");
13335               return;
13336             }
13337
13338           i = 0;
13339           tmp[29] = 0;
13340           while (v)
13341             {
13342               tmp[28 - i] = (v % 10) + '0';
13343               v /= 10;
13344               i++;
13345             }
13346           strcpy (buf, tmp + 29 - i);
13347         }
13348     }
13349   else
13350     {
13351       if (hex)
13352         sprintf (buf, "0x%x", (unsigned int) disp);
13353       else
13354         sprintf (buf, "%d", (int) disp);
13355     }
13356 }
13357
13358 /* Put DISP in BUF as signed hex number.  */
13359
13360 static void
13361 print_displacement (char *buf, bfd_vma disp)
13362 {
13363   bfd_signed_vma val = disp;
13364   char tmp[30];
13365   int i, j = 0;
13366
13367   if (val < 0)
13368     {
13369       buf[j++] = '-';
13370       val = -disp;
13371
13372       /* Check for possible overflow.  */
13373       if (val < 0)
13374         {
13375           switch (address_mode)
13376             {
13377             case mode_64bit:
13378               strcpy (buf + j, "0x8000000000000000");
13379               break;
13380             case mode_32bit:
13381               strcpy (buf + j, "0x80000000");
13382               break;
13383             case mode_16bit:
13384               strcpy (buf + j, "0x8000");
13385               break;
13386             }
13387           return;
13388         }
13389     }
13390
13391   buf[j++] = '0';
13392   buf[j++] = 'x';
13393
13394   sprintf_vma (tmp, (bfd_vma) val);
13395   for (i = 0; tmp[i] == '0'; i++)
13396     continue;
13397   if (tmp[i] == '\0')
13398     i--;
13399   strcpy (buf + j, tmp + i);
13400 }
13401
13402 static void
13403 intel_operand_size (int bytemode, int sizeflag)
13404 {
13405   if (vex.evex
13406       && vex.b
13407       && (bytemode == x_mode
13408           || bytemode == evex_half_bcst_xmmq_mode))
13409     {
13410       if (vex.w)
13411         oappend ("QWORD PTR ");
13412       else
13413         oappend ("DWORD PTR ");
13414       return;
13415     }
13416   switch (bytemode)
13417     {
13418     case b_mode:
13419     case b_swap_mode:
13420     case dqb_mode:
13421     case db_mode:
13422       oappend ("BYTE PTR ");
13423       break;
13424     case w_mode:
13425     case dw_mode:
13426     case dqw_mode:
13427       oappend ("WORD PTR ");
13428       break;
13429     case indir_v_mode:
13430       if (address_mode == mode_64bit && isa64 == intel64)
13431         {
13432           oappend ("QWORD PTR ");
13433           break;
13434         }
13435       /* Fall through.  */
13436     case stack_v_mode:
13437       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13438         {
13439           oappend ("QWORD PTR ");
13440           break;
13441         }
13442       /* Fall through.  */
13443     case v_mode:
13444     case v_swap_mode:
13445     case dq_mode:
13446       USED_REX (REX_W);
13447       if (rex & REX_W)
13448         oappend ("QWORD PTR ");
13449       else
13450         {
13451           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13452             oappend ("DWORD PTR ");
13453           else
13454             oappend ("WORD PTR ");
13455           used_prefixes |= (prefixes & PREFIX_DATA);
13456         }
13457       break;
13458     case z_mode:
13459       if ((rex & REX_W) || (sizeflag & DFLAG))
13460         *obufp++ = 'D';
13461       oappend ("WORD PTR ");
13462       if (!(rex & REX_W))
13463         used_prefixes |= (prefixes & PREFIX_DATA);
13464       break;
13465     case a_mode:
13466       if (sizeflag & DFLAG)
13467         oappend ("QWORD PTR ");
13468       else
13469         oappend ("DWORD PTR ");
13470       used_prefixes |= (prefixes & PREFIX_DATA);
13471       break;
13472     case d_mode:
13473     case d_scalar_mode:
13474     case d_scalar_swap_mode:
13475     case d_swap_mode:
13476     case dqd_mode:
13477       oappend ("DWORD PTR ");
13478       break;
13479     case q_mode:
13480     case q_scalar_mode:
13481     case q_scalar_swap_mode:
13482     case q_swap_mode:
13483       oappend ("QWORD PTR ");
13484       break;
13485     case m_mode:
13486       if (address_mode == mode_64bit)
13487         oappend ("QWORD PTR ");
13488       else
13489         oappend ("DWORD PTR ");
13490       break;
13491     case f_mode:
13492       if (sizeflag & DFLAG)
13493         oappend ("FWORD PTR ");
13494       else
13495         oappend ("DWORD PTR ");
13496       used_prefixes |= (prefixes & PREFIX_DATA);
13497       break;
13498     case t_mode:
13499       oappend ("TBYTE PTR ");
13500       break;
13501     case x_mode:
13502     case x_swap_mode:
13503     case evex_x_gscat_mode:
13504     case evex_x_nobcst_mode:
13505     case b_scalar_mode:
13506     case w_scalar_mode:
13507       if (need_vex)
13508         {
13509           switch (vex.length)
13510             {
13511             case 128:
13512               oappend ("XMMWORD PTR ");
13513               break;
13514             case 256:
13515               oappend ("YMMWORD PTR ");
13516               break;
13517             case 512:
13518               oappend ("ZMMWORD PTR ");
13519               break;
13520             default:
13521               abort ();
13522             }
13523         }
13524       else
13525         oappend ("XMMWORD PTR ");
13526       break;
13527     case xmm_mode:
13528       oappend ("XMMWORD PTR ");
13529       break;
13530     case ymm_mode:
13531       oappend ("YMMWORD PTR ");
13532       break;
13533     case xmmq_mode:
13534     case evex_half_bcst_xmmq_mode:
13535       if (!need_vex)
13536         abort ();
13537
13538       switch (vex.length)
13539         {
13540         case 128:
13541           oappend ("QWORD PTR ");
13542           break;
13543         case 256:
13544           oappend ("XMMWORD PTR ");
13545           break;
13546         case 512:
13547           oappend ("YMMWORD PTR ");
13548           break;
13549         default:
13550           abort ();
13551         }
13552       break;
13553     case xmm_mb_mode:
13554       if (!need_vex)
13555         abort ();
13556
13557       switch (vex.length)
13558         {
13559         case 128:
13560         case 256:
13561         case 512:
13562           oappend ("BYTE PTR ");
13563           break;
13564         default:
13565           abort ();
13566         }
13567       break;
13568     case xmm_mw_mode:
13569       if (!need_vex)
13570         abort ();
13571
13572       switch (vex.length)
13573         {
13574         case 128:
13575         case 256:
13576         case 512:
13577           oappend ("WORD PTR ");
13578           break;
13579         default:
13580           abort ();
13581         }
13582       break;
13583     case xmm_md_mode:
13584       if (!need_vex)
13585         abort ();
13586
13587       switch (vex.length)
13588         {
13589         case 128:
13590         case 256:
13591         case 512:
13592           oappend ("DWORD PTR ");
13593           break;
13594         default:
13595           abort ();
13596         }
13597       break;
13598     case xmm_mq_mode:
13599       if (!need_vex)
13600         abort ();
13601
13602       switch (vex.length)
13603         {
13604         case 128:
13605         case 256:
13606         case 512:
13607           oappend ("QWORD PTR ");
13608           break;
13609         default:
13610           abort ();
13611         }
13612       break;
13613     case xmmdw_mode:
13614       if (!need_vex)
13615         abort ();
13616
13617       switch (vex.length)
13618         {
13619         case 128:
13620           oappend ("WORD PTR ");
13621           break;
13622         case 256:
13623           oappend ("DWORD PTR ");
13624           break;
13625         case 512:
13626           oappend ("QWORD PTR ");
13627           break;
13628         default:
13629           abort ();
13630         }
13631       break;
13632     case xmmqd_mode:
13633       if (!need_vex)
13634         abort ();
13635
13636       switch (vex.length)
13637         {
13638         case 128:
13639           oappend ("DWORD PTR ");
13640           break;
13641         case 256:
13642           oappend ("QWORD PTR ");
13643           break;
13644         case 512:
13645           oappend ("XMMWORD PTR ");
13646           break;
13647         default:
13648           abort ();
13649         }
13650       break;
13651     case ymmq_mode:
13652       if (!need_vex)
13653         abort ();
13654
13655       switch (vex.length)
13656         {
13657         case 128:
13658           oappend ("QWORD PTR ");
13659           break;
13660         case 256:
13661           oappend ("YMMWORD PTR ");
13662           break;
13663         case 512:
13664           oappend ("ZMMWORD PTR ");
13665           break;
13666         default:
13667           abort ();
13668         }
13669       break;
13670     case ymmxmm_mode:
13671       if (!need_vex)
13672         abort ();
13673
13674       switch (vex.length)
13675         {
13676         case 128:
13677         case 256:
13678           oappend ("XMMWORD PTR ");
13679           break;
13680         default:
13681           abort ();
13682         }
13683       break;
13684     case o_mode:
13685       oappend ("OWORD PTR ");
13686       break;
13687     case xmm_mdq_mode:
13688     case vex_w_dq_mode:
13689     case vex_scalar_w_dq_mode:
13690       if (!need_vex)
13691         abort ();
13692
13693       if (vex.w)
13694         oappend ("QWORD PTR ");
13695       else
13696         oappend ("DWORD PTR ");
13697       break;
13698     case vex_vsib_d_w_dq_mode:
13699     case vex_vsib_q_w_dq_mode:
13700       if (!need_vex)
13701         abort ();
13702
13703       if (!vex.evex)
13704         {
13705           if (vex.w)
13706             oappend ("QWORD PTR ");
13707           else
13708             oappend ("DWORD PTR ");
13709         }
13710       else
13711         {
13712           switch (vex.length)
13713             {
13714             case 128:
13715               oappend ("XMMWORD PTR ");
13716               break;
13717             case 256:
13718               oappend ("YMMWORD PTR ");
13719               break;
13720             case 512:
13721               oappend ("ZMMWORD PTR ");
13722               break;
13723             default:
13724               abort ();
13725             }
13726         }
13727       break;
13728     case vex_vsib_q_w_d_mode:
13729     case vex_vsib_d_w_d_mode:
13730       if (!need_vex || !vex.evex)
13731         abort ();
13732
13733       switch (vex.length)
13734         {
13735         case 128:
13736           oappend ("QWORD PTR ");
13737           break;
13738         case 256:
13739           oappend ("XMMWORD PTR ");
13740           break;
13741         case 512:
13742           oappend ("YMMWORD PTR ");
13743           break;
13744         default:
13745           abort ();
13746         }
13747
13748       break;
13749     case mask_bd_mode:
13750       if (!need_vex || vex.length != 128)
13751         abort ();
13752       if (vex.w)
13753         oappend ("DWORD PTR ");
13754       else
13755         oappend ("BYTE PTR ");
13756       break;
13757     case mask_mode:
13758       if (!need_vex)
13759         abort ();
13760       if (vex.w)
13761         oappend ("QWORD PTR ");
13762       else
13763         oappend ("WORD PTR ");
13764       break;
13765     case v_bnd_mode:
13766     case v_bndmk_mode:
13767     default:
13768       break;
13769     }
13770 }
13771
13772 static void
13773 OP_E_register (int bytemode, int sizeflag)
13774 {
13775   int reg = modrm.rm;
13776   const char **names;
13777
13778   USED_REX (REX_B);
13779   if ((rex & REX_B))
13780     reg += 8;
13781
13782   if ((sizeflag & SUFFIX_ALWAYS)
13783       && (bytemode == b_swap_mode
13784           || bytemode == bnd_swap_mode
13785           || bytemode == v_swap_mode))
13786     swap_operand ();
13787
13788   switch (bytemode)
13789     {
13790     case b_mode:
13791     case b_swap_mode:
13792       USED_REX (0);
13793       if (rex)
13794         names = names8rex;
13795       else
13796         names = names8;
13797       break;
13798     case w_mode:
13799       names = names16;
13800       break;
13801     case d_mode:
13802     case dw_mode:
13803     case db_mode:
13804       names = names32;
13805       break;
13806     case q_mode:
13807       names = names64;
13808       break;
13809     case m_mode:
13810     case v_bnd_mode:
13811       names = address_mode == mode_64bit ? names64 : names32;
13812       break;
13813     case bnd_mode:
13814     case bnd_swap_mode:
13815       if (reg > 0x3)
13816         {
13817           oappend ("(bad)");
13818           return;
13819         }
13820       names = names_bnd;
13821       break;
13822     case indir_v_mode:
13823       if (address_mode == mode_64bit && isa64 == intel64)
13824         {
13825           names = names64;
13826           break;
13827         }
13828       /* Fall through.  */
13829     case stack_v_mode:
13830       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13831         {
13832           names = names64;
13833           break;
13834         }
13835       bytemode = v_mode;
13836       /* Fall through.  */
13837     case v_mode:
13838     case v_swap_mode:
13839     case dq_mode:
13840     case dqb_mode:
13841     case dqd_mode:
13842     case dqw_mode:
13843       USED_REX (REX_W);
13844       if (rex & REX_W)
13845         names = names64;
13846       else
13847         {
13848           if ((sizeflag & DFLAG)
13849               || (bytemode != v_mode
13850                   && bytemode != v_swap_mode))
13851             names = names32;
13852           else
13853             names = names16;
13854           used_prefixes |= (prefixes & PREFIX_DATA);
13855         }
13856       break;
13857     case va_mode:
13858       names = (address_mode == mode_64bit
13859                ? names64 : names32);
13860       if (!(prefixes & PREFIX_ADDR))
13861         names = (address_mode == mode_16bit
13862                      ? names16 : names);
13863       else
13864         {
13865           /* Remove "addr16/addr32".  */
13866           all_prefixes[last_addr_prefix] = 0;
13867           names = (address_mode != mode_32bit
13868                        ? names32 : names16);
13869           used_prefixes |= PREFIX_ADDR;
13870         }
13871       break;
13872     case mask_bd_mode:
13873     case mask_mode:
13874       if (reg > 0x7)
13875         {
13876           oappend ("(bad)");
13877           return;
13878         }
13879       names = names_mask;
13880       break;
13881     case 0:
13882       return;
13883     default:
13884       oappend (INTERNAL_DISASSEMBLER_ERROR);
13885       return;
13886     }
13887   oappend (names[reg]);
13888 }
13889
13890 static void
13891 OP_E_memory (int bytemode, int sizeflag)
13892 {
13893   bfd_vma disp = 0;
13894   int add = (rex & REX_B) ? 8 : 0;
13895   int riprel = 0;
13896   int shift;
13897
13898   if (vex.evex)
13899     {
13900       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13901       if (vex.b
13902           && bytemode != x_mode
13903           && bytemode != xmmq_mode
13904           && bytemode != evex_half_bcst_xmmq_mode)
13905         {
13906           BadOp ();
13907           return;
13908         }
13909       switch (bytemode)
13910         {
13911         case dqw_mode:
13912         case dw_mode:
13913           shift = 1;
13914           break;
13915         case dqb_mode:
13916         case db_mode:
13917           shift = 0;
13918           break;
13919         case dq_mode:
13920           if (address_mode != mode_64bit)
13921             {
13922               shift = 2;
13923               break;
13924             }
13925             /* fall through */
13926         case vex_vsib_d_w_dq_mode:
13927         case vex_vsib_d_w_d_mode:
13928         case vex_vsib_q_w_dq_mode:
13929         case vex_vsib_q_w_d_mode:
13930         case evex_x_gscat_mode:
13931         case xmm_mdq_mode:
13932           shift = vex.w ? 3 : 2;
13933           break;
13934         case x_mode:
13935         case evex_half_bcst_xmmq_mode:
13936         case xmmq_mode:
13937           if (vex.b)
13938             {
13939               shift = vex.w ? 3 : 2;
13940               break;
13941             }
13942           /* Fall through.  */
13943         case xmmqd_mode:
13944         case xmmdw_mode:
13945         case ymmq_mode:
13946         case evex_x_nobcst_mode:
13947         case x_swap_mode:
13948           switch (vex.length)
13949             {
13950             case 128:
13951               shift = 4;
13952               break;
13953             case 256:
13954               shift = 5;
13955               break;
13956             case 512:
13957               shift = 6;
13958               break;
13959             default:
13960               abort ();
13961             }
13962           break;
13963         case ymm_mode:
13964           shift = 5;
13965           break;
13966         case xmm_mode:
13967           shift = 4;
13968           break;
13969         case xmm_mq_mode:
13970         case q_mode:
13971         case q_scalar_mode:
13972         case q_swap_mode:
13973         case q_scalar_swap_mode:
13974           shift = 3;
13975           break;
13976         case dqd_mode:
13977         case xmm_md_mode:
13978         case d_mode:
13979         case d_scalar_mode:
13980         case d_swap_mode:
13981         case d_scalar_swap_mode:
13982           shift = 2;
13983           break;
13984         case w_scalar_mode:
13985         case xmm_mw_mode:
13986           shift = 1;
13987           break;
13988         case b_scalar_mode:
13989         case xmm_mb_mode:
13990           shift = 0;
13991           break;
13992         default:
13993           abort ();
13994         }
13995       /* Make necessary corrections to shift for modes that need it.
13996          For these modes we currently have shift 4, 5 or 6 depending on
13997          vex.length (it corresponds to xmmword, ymmword or zmmword
13998          operand).  We might want to make it 3, 4 or 5 (e.g. for
13999          xmmq_mode).  In case of broadcast enabled the corrections
14000          aren't needed, as element size is always 32 or 64 bits.  */
14001       if (!vex.b
14002           && (bytemode == xmmq_mode
14003               || bytemode == evex_half_bcst_xmmq_mode))
14004         shift -= 1;
14005       else if (bytemode == xmmqd_mode)
14006         shift -= 2;
14007       else if (bytemode == xmmdw_mode)
14008         shift -= 3;
14009       else if (bytemode == ymmq_mode && vex.length == 128)
14010         shift -= 1;
14011     }
14012   else
14013     shift = 0;
14014
14015   USED_REX (REX_B);
14016   if (intel_syntax)
14017     intel_operand_size (bytemode, sizeflag);
14018   append_seg ();
14019
14020   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14021     {
14022       /* 32/64 bit address mode */
14023       int havedisp;
14024       int havesib;
14025       int havebase;
14026       int haveindex;
14027       int needindex;
14028       int needaddr32;
14029       int base, rbase;
14030       int vindex = 0;
14031       int scale = 0;
14032       int addr32flag = !((sizeflag & AFLAG)
14033                          || bytemode == v_bnd_mode
14034                          || bytemode == v_bndmk_mode
14035                          || bytemode == bnd_mode
14036                          || bytemode == bnd_swap_mode);
14037       const char **indexes64 = names64;
14038       const char **indexes32 = names32;
14039
14040       havesib = 0;
14041       havebase = 1;
14042       haveindex = 0;
14043       base = modrm.rm;
14044
14045       if (base == 4)
14046         {
14047           havesib = 1;
14048           vindex = sib.index;
14049           USED_REX (REX_X);
14050           if (rex & REX_X)
14051             vindex += 8;
14052           switch (bytemode)
14053             {
14054             case vex_vsib_d_w_dq_mode:
14055             case vex_vsib_d_w_d_mode:
14056             case vex_vsib_q_w_dq_mode:
14057             case vex_vsib_q_w_d_mode:
14058               if (!need_vex)
14059                 abort ();
14060               if (vex.evex)
14061                 {
14062                   if (!vex.v)
14063                     vindex += 16;
14064                 }
14065
14066               haveindex = 1;
14067               switch (vex.length)
14068                 {
14069                 case 128:
14070                   indexes64 = indexes32 = names_xmm;
14071                   break;
14072                 case 256:
14073                   if (!vex.w
14074                       || bytemode == vex_vsib_q_w_dq_mode
14075                       || bytemode == vex_vsib_q_w_d_mode)
14076                     indexes64 = indexes32 = names_ymm;
14077                   else
14078                     indexes64 = indexes32 = names_xmm;
14079                   break;
14080                 case 512:
14081                   if (!vex.w
14082                       || bytemode == vex_vsib_q_w_dq_mode
14083                       || bytemode == vex_vsib_q_w_d_mode)
14084                     indexes64 = indexes32 = names_zmm;
14085                   else
14086                     indexes64 = indexes32 = names_ymm;
14087                   break;
14088                 default:
14089                   abort ();
14090                 }
14091               break;
14092             default:
14093               haveindex = vindex != 4;
14094               break;
14095             }
14096           scale = sib.scale;
14097           base = sib.base;
14098           codep++;
14099         }
14100       rbase = base + add;
14101
14102       switch (modrm.mod)
14103         {
14104         case 0:
14105           if (base == 5)
14106             {
14107               havebase = 0;
14108               if (address_mode == mode_64bit && !havesib)
14109                 riprel = 1;
14110               disp = get32s ();
14111               if (riprel && bytemode == v_bndmk_mode)
14112                 {
14113                   oappend ("(bad)");
14114                   return;
14115                 }
14116             }
14117           break;
14118         case 1:
14119           FETCH_DATA (the_info, codep + 1);
14120           disp = *codep++;
14121           if ((disp & 0x80) != 0)
14122             disp -= 0x100;
14123           if (vex.evex && shift > 0)
14124             disp <<= shift;
14125           break;
14126         case 2:
14127           disp = get32s ();
14128           break;
14129         }
14130
14131       needindex = 0;
14132       needaddr32 = 0;
14133       if (havesib
14134           && !havebase
14135           && !haveindex
14136           && address_mode != mode_16bit)
14137         {
14138           if (address_mode == mode_64bit)
14139             {
14140               /* Display eiz instead of addr32.  */
14141               needindex = addr32flag;
14142               needaddr32 = 1;
14143             }
14144           else
14145             {
14146               /* In 32-bit mode, we need index register to tell [offset]
14147                  from [eiz*1 + offset].  */
14148               needindex = 1;
14149             }
14150         }
14151
14152       havedisp = (havebase
14153                   || needindex
14154                   || (havesib && (haveindex || scale != 0)));
14155
14156       if (!intel_syntax)
14157         if (modrm.mod != 0 || base == 5)
14158           {
14159             if (havedisp || riprel)
14160               print_displacement (scratchbuf, disp);
14161             else
14162               print_operand_value (scratchbuf, 1, disp);
14163             oappend (scratchbuf);
14164             if (riprel)
14165               {
14166                 set_op (disp, 1);
14167                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14168               }
14169           }
14170
14171       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14172           && (bytemode != v_bnd_mode)
14173           && (bytemode != v_bndmk_mode)
14174           && (bytemode != bnd_mode)
14175           && (bytemode != bnd_swap_mode))
14176         used_prefixes |= PREFIX_ADDR;
14177
14178       if (havedisp || (intel_syntax && riprel))
14179         {
14180           *obufp++ = open_char;
14181           if (intel_syntax && riprel)
14182             {
14183               set_op (disp, 1);
14184               oappend (!addr32flag ? "rip" : "eip");
14185             }
14186           *obufp = '\0';
14187           if (havebase)
14188             oappend (address_mode == mode_64bit && !addr32flag
14189                      ? names64[rbase] : names32[rbase]);
14190           if (havesib)
14191             {
14192               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14193                  print index to tell base + index from base.  */
14194               if (scale != 0
14195                   || needindex
14196                   || haveindex
14197                   || (havebase && base != ESP_REG_NUM))
14198                 {
14199                   if (!intel_syntax || havebase)
14200                     {
14201                       *obufp++ = separator_char;
14202                       *obufp = '\0';
14203                     }
14204                   if (haveindex)
14205                     oappend (address_mode == mode_64bit && !addr32flag
14206                              ? indexes64[vindex] : indexes32[vindex]);
14207                   else
14208                     oappend (address_mode == mode_64bit && !addr32flag
14209                              ? index64 : index32);
14210
14211                   *obufp++ = scale_char;
14212                   *obufp = '\0';
14213                   sprintf (scratchbuf, "%d", 1 << scale);
14214                   oappend (scratchbuf);
14215                 }
14216             }
14217           if (intel_syntax
14218               && (disp || modrm.mod != 0 || base == 5))
14219             {
14220               if (!havedisp || (bfd_signed_vma) disp >= 0)
14221                 {
14222                   *obufp++ = '+';
14223                   *obufp = '\0';
14224                 }
14225               else if (modrm.mod != 1 && disp != -disp)
14226                 {
14227                   *obufp++ = '-';
14228                   *obufp = '\0';
14229                   disp = - (bfd_signed_vma) disp;
14230                 }
14231
14232               if (havedisp)
14233                 print_displacement (scratchbuf, disp);
14234               else
14235                 print_operand_value (scratchbuf, 1, disp);
14236               oappend (scratchbuf);
14237             }
14238
14239           *obufp++ = close_char;
14240           *obufp = '\0';
14241         }
14242       else if (intel_syntax)
14243         {
14244           if (modrm.mod != 0 || base == 5)
14245             {
14246               if (!active_seg_prefix)
14247                 {
14248                   oappend (names_seg[ds_reg - es_reg]);
14249                   oappend (":");
14250                 }
14251               print_operand_value (scratchbuf, 1, disp);
14252               oappend (scratchbuf);
14253             }
14254         }
14255     }
14256   else
14257     {
14258       /* 16 bit address mode */
14259       used_prefixes |= prefixes & PREFIX_ADDR;
14260       switch (modrm.mod)
14261         {
14262         case 0:
14263           if (modrm.rm == 6)
14264             {
14265               disp = get16 ();
14266               if ((disp & 0x8000) != 0)
14267                 disp -= 0x10000;
14268             }
14269           break;
14270         case 1:
14271           FETCH_DATA (the_info, codep + 1);
14272           disp = *codep++;
14273           if ((disp & 0x80) != 0)
14274             disp -= 0x100;
14275           if (vex.evex && shift > 0)
14276             disp <<= shift;
14277           break;
14278         case 2:
14279           disp = get16 ();
14280           if ((disp & 0x8000) != 0)
14281             disp -= 0x10000;
14282           break;
14283         }
14284
14285       if (!intel_syntax)
14286         if (modrm.mod != 0 || modrm.rm == 6)
14287           {
14288             print_displacement (scratchbuf, disp);
14289             oappend (scratchbuf);
14290           }
14291
14292       if (modrm.mod != 0 || modrm.rm != 6)
14293         {
14294           *obufp++ = open_char;
14295           *obufp = '\0';
14296           oappend (index16[modrm.rm]);
14297           if (intel_syntax
14298               && (disp || modrm.mod != 0 || modrm.rm == 6))
14299             {
14300               if ((bfd_signed_vma) disp >= 0)
14301                 {
14302                   *obufp++ = '+';
14303                   *obufp = '\0';
14304                 }
14305               else if (modrm.mod != 1)
14306                 {
14307                   *obufp++ = '-';
14308                   *obufp = '\0';
14309                   disp = - (bfd_signed_vma) disp;
14310                 }
14311
14312               print_displacement (scratchbuf, disp);
14313               oappend (scratchbuf);
14314             }
14315
14316           *obufp++ = close_char;
14317           *obufp = '\0';
14318         }
14319       else if (intel_syntax)
14320         {
14321           if (!active_seg_prefix)
14322             {
14323               oappend (names_seg[ds_reg - es_reg]);
14324               oappend (":");
14325             }
14326           print_operand_value (scratchbuf, 1, disp & 0xffff);
14327           oappend (scratchbuf);
14328         }
14329     }
14330   if (vex.evex && vex.b
14331       && (bytemode == x_mode
14332           || bytemode == xmmq_mode
14333           || bytemode == evex_half_bcst_xmmq_mode))
14334     {
14335       if (vex.w
14336           || bytemode == xmmq_mode
14337           || bytemode == evex_half_bcst_xmmq_mode)
14338         {
14339           switch (vex.length)
14340             {
14341             case 128:
14342               oappend ("{1to2}");
14343               break;
14344             case 256:
14345               oappend ("{1to4}");
14346               break;
14347             case 512:
14348               oappend ("{1to8}");
14349               break;
14350             default:
14351               abort ();
14352             }
14353         }
14354       else
14355         {
14356           switch (vex.length)
14357             {
14358             case 128:
14359               oappend ("{1to4}");
14360               break;
14361             case 256:
14362               oappend ("{1to8}");
14363               break;
14364             case 512:
14365               oappend ("{1to16}");
14366               break;
14367             default:
14368               abort ();
14369             }
14370         }
14371     }
14372 }
14373
14374 static void
14375 OP_E (int bytemode, int sizeflag)
14376 {
14377   /* Skip mod/rm byte.  */
14378   MODRM_CHECK;
14379   codep++;
14380
14381   if (modrm.mod == 3)
14382     OP_E_register (bytemode, sizeflag);
14383   else
14384     OP_E_memory (bytemode, sizeflag);
14385 }
14386
14387 static void
14388 OP_G (int bytemode, int sizeflag)
14389 {
14390   int add = 0;
14391   const char **names;
14392   USED_REX (REX_R);
14393   if (rex & REX_R)
14394     add += 8;
14395   switch (bytemode)
14396     {
14397     case b_mode:
14398       USED_REX (0);
14399       if (rex)
14400         oappend (names8rex[modrm.reg + add]);
14401       else
14402         oappend (names8[modrm.reg + add]);
14403       break;
14404     case w_mode:
14405       oappend (names16[modrm.reg + add]);
14406       break;
14407     case d_mode:
14408     case db_mode:
14409     case dw_mode:
14410       oappend (names32[modrm.reg + add]);
14411       break;
14412     case q_mode:
14413       oappend (names64[modrm.reg + add]);
14414       break;
14415     case bnd_mode:
14416       if (modrm.reg > 0x3)
14417         {
14418           oappend ("(bad)");
14419           return;
14420         }
14421       oappend (names_bnd[modrm.reg]);
14422       break;
14423     case v_mode:
14424     case dq_mode:
14425     case dqb_mode:
14426     case dqd_mode:
14427     case dqw_mode:
14428       USED_REX (REX_W);
14429       if (rex & REX_W)
14430         oappend (names64[modrm.reg + add]);
14431       else
14432         {
14433           if ((sizeflag & DFLAG) || bytemode != v_mode)
14434             oappend (names32[modrm.reg + add]);
14435           else
14436             oappend (names16[modrm.reg + add]);
14437           used_prefixes |= (prefixes & PREFIX_DATA);
14438         }
14439       break;
14440     case va_mode:
14441       names = (address_mode == mode_64bit
14442                ? names64 : names32);
14443       if (!(prefixes & PREFIX_ADDR))
14444         {
14445           if (address_mode == mode_16bit)
14446             names = names16;
14447         }
14448       else
14449         {
14450           /* Remove "addr16/addr32".  */
14451           all_prefixes[last_addr_prefix] = 0;
14452           names = (address_mode != mode_32bit
14453                        ? names32 : names16);
14454           used_prefixes |= PREFIX_ADDR;
14455         }
14456       oappend (names[modrm.reg + add]);
14457       break;
14458     case m_mode:
14459       if (address_mode == mode_64bit)
14460         oappend (names64[modrm.reg + add]);
14461       else
14462         oappend (names32[modrm.reg + add]);
14463       break;
14464     case mask_bd_mode:
14465     case mask_mode:
14466       if ((modrm.reg + add) > 0x7)
14467         {
14468           oappend ("(bad)");
14469           return;
14470         }
14471       oappend (names_mask[modrm.reg + add]);
14472       break;
14473     default:
14474       oappend (INTERNAL_DISASSEMBLER_ERROR);
14475       break;
14476     }
14477 }
14478
14479 static bfd_vma
14480 get64 (void)
14481 {
14482   bfd_vma x;
14483 #ifdef BFD64
14484   unsigned int a;
14485   unsigned int b;
14486
14487   FETCH_DATA (the_info, codep + 8);
14488   a = *codep++ & 0xff;
14489   a |= (*codep++ & 0xff) << 8;
14490   a |= (*codep++ & 0xff) << 16;
14491   a |= (*codep++ & 0xffu) << 24;
14492   b = *codep++ & 0xff;
14493   b |= (*codep++ & 0xff) << 8;
14494   b |= (*codep++ & 0xff) << 16;
14495   b |= (*codep++ & 0xffu) << 24;
14496   x = a + ((bfd_vma) b << 32);
14497 #else
14498   abort ();
14499   x = 0;
14500 #endif
14501   return x;
14502 }
14503
14504 static bfd_signed_vma
14505 get32 (void)
14506 {
14507   bfd_signed_vma x = 0;
14508
14509   FETCH_DATA (the_info, codep + 4);
14510   x = *codep++ & (bfd_signed_vma) 0xff;
14511   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14512   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14513   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14514   return x;
14515 }
14516
14517 static bfd_signed_vma
14518 get32s (void)
14519 {
14520   bfd_signed_vma x = 0;
14521
14522   FETCH_DATA (the_info, codep + 4);
14523   x = *codep++ & (bfd_signed_vma) 0xff;
14524   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14525   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14526   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14527
14528   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14529
14530   return x;
14531 }
14532
14533 static int
14534 get16 (void)
14535 {
14536   int x = 0;
14537
14538   FETCH_DATA (the_info, codep + 2);
14539   x = *codep++ & 0xff;
14540   x |= (*codep++ & 0xff) << 8;
14541   return x;
14542 }
14543
14544 static void
14545 set_op (bfd_vma op, int riprel)
14546 {
14547   op_index[op_ad] = op_ad;
14548   if (address_mode == mode_64bit)
14549     {
14550       op_address[op_ad] = op;
14551       op_riprel[op_ad] = riprel;
14552     }
14553   else
14554     {
14555       /* Mask to get a 32-bit address.  */
14556       op_address[op_ad] = op & 0xffffffff;
14557       op_riprel[op_ad] = riprel & 0xffffffff;
14558     }
14559 }
14560
14561 static void
14562 OP_REG (int code, int sizeflag)
14563 {
14564   const char *s;
14565   int add;
14566
14567   switch (code)
14568     {
14569     case es_reg: case ss_reg: case cs_reg:
14570     case ds_reg: case fs_reg: case gs_reg:
14571       oappend (names_seg[code - es_reg]);
14572       return;
14573     }
14574
14575   USED_REX (REX_B);
14576   if (rex & REX_B)
14577     add = 8;
14578   else
14579     add = 0;
14580
14581   switch (code)
14582     {
14583     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14584     case sp_reg: case bp_reg: case si_reg: case di_reg:
14585       s = names16[code - ax_reg + add];
14586       break;
14587     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14588     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14589       USED_REX (0);
14590       if (rex)
14591         s = names8rex[code - al_reg + add];
14592       else
14593         s = names8[code - al_reg];
14594       break;
14595     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14596     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14597       if (address_mode == mode_64bit
14598           && ((sizeflag & DFLAG) || (rex & REX_W)))
14599         {
14600           s = names64[code - rAX_reg + add];
14601           break;
14602         }
14603       code += eAX_reg - rAX_reg;
14604       /* Fall through.  */
14605     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14606     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14607       USED_REX (REX_W);
14608       if (rex & REX_W)
14609         s = names64[code - eAX_reg + add];
14610       else
14611         {
14612           if (sizeflag & DFLAG)
14613             s = names32[code - eAX_reg + add];
14614           else
14615             s = names16[code - eAX_reg + add];
14616           used_prefixes |= (prefixes & PREFIX_DATA);
14617         }
14618       break;
14619     default:
14620       s = INTERNAL_DISASSEMBLER_ERROR;
14621       break;
14622     }
14623   oappend (s);
14624 }
14625
14626 static void
14627 OP_IMREG (int code, int sizeflag)
14628 {
14629   const char *s;
14630
14631   switch (code)
14632     {
14633     case indir_dx_reg:
14634       if (intel_syntax)
14635         s = "dx";
14636       else
14637         s = "(%dx)";
14638       break;
14639     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14640     case sp_reg: case bp_reg: case si_reg: case di_reg:
14641       s = names16[code - ax_reg];
14642       break;
14643     case es_reg: case ss_reg: case cs_reg:
14644     case ds_reg: case fs_reg: case gs_reg:
14645       s = names_seg[code - es_reg];
14646       break;
14647     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14648     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14649       USED_REX (0);
14650       if (rex)
14651         s = names8rex[code - al_reg];
14652       else
14653         s = names8[code - al_reg];
14654       break;
14655     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14656     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14657       USED_REX (REX_W);
14658       if (rex & REX_W)
14659         s = names64[code - eAX_reg];
14660       else
14661         {
14662           if (sizeflag & DFLAG)
14663             s = names32[code - eAX_reg];
14664           else
14665             s = names16[code - eAX_reg];
14666           used_prefixes |= (prefixes & PREFIX_DATA);
14667         }
14668       break;
14669     case z_mode_ax_reg:
14670       if ((rex & REX_W) || (sizeflag & DFLAG))
14671         s = *names32;
14672       else
14673         s = *names16;
14674       if (!(rex & REX_W))
14675         used_prefixes |= (prefixes & PREFIX_DATA);
14676       break;
14677     default:
14678       s = INTERNAL_DISASSEMBLER_ERROR;
14679       break;
14680     }
14681   oappend (s);
14682 }
14683
14684 static void
14685 OP_I (int bytemode, int sizeflag)
14686 {
14687   bfd_signed_vma op;
14688   bfd_signed_vma mask = -1;
14689
14690   switch (bytemode)
14691     {
14692     case b_mode:
14693       FETCH_DATA (the_info, codep + 1);
14694       op = *codep++;
14695       mask = 0xff;
14696       break;
14697     case v_mode:
14698       USED_REX (REX_W);
14699       if (rex & REX_W)
14700         op = get32s ();
14701       else
14702         {
14703           if (sizeflag & DFLAG)
14704             {
14705               op = get32 ();
14706               mask = 0xffffffff;
14707             }
14708           else
14709             {
14710               op = get16 ();
14711               mask = 0xfffff;
14712             }
14713           used_prefixes |= (prefixes & PREFIX_DATA);
14714         }
14715       break;
14716     case d_mode:
14717       mask = 0xffffffff;
14718       op = get32 ();
14719       break;
14720     case w_mode:
14721       mask = 0xfffff;
14722       op = get16 ();
14723       break;
14724     case const_1_mode:
14725       if (intel_syntax)
14726         oappend ("1");
14727       return;
14728     default:
14729       oappend (INTERNAL_DISASSEMBLER_ERROR);
14730       return;
14731     }
14732
14733   op &= mask;
14734   scratchbuf[0] = '$';
14735   print_operand_value (scratchbuf + 1, 1, op);
14736   oappend_maybe_intel (scratchbuf);
14737   scratchbuf[0] = '\0';
14738 }
14739
14740 static void
14741 OP_I64 (int bytemode, int sizeflag)
14742 {
14743   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14744     {
14745       OP_I (bytemode, sizeflag);
14746       return;
14747     }
14748
14749   USED_REX (REX_W);
14750
14751   scratchbuf[0] = '$';
14752   print_operand_value (scratchbuf + 1, 1, get64 ());
14753   oappend_maybe_intel (scratchbuf);
14754   scratchbuf[0] = '\0';
14755 }
14756
14757 static void
14758 OP_sI (int bytemode, int sizeflag)
14759 {
14760   bfd_signed_vma op;
14761
14762   switch (bytemode)
14763     {
14764     case b_mode:
14765     case b_T_mode:
14766       FETCH_DATA (the_info, codep + 1);
14767       op = *codep++;
14768       if ((op & 0x80) != 0)
14769         op -= 0x100;
14770       if (bytemode == b_T_mode)
14771         {
14772           if (address_mode != mode_64bit
14773               || !((sizeflag & DFLAG) || (rex & REX_W)))
14774             {
14775               /* The operand-size prefix is overridden by a REX prefix.  */
14776               if ((sizeflag & DFLAG) || (rex & REX_W))
14777                 op &= 0xffffffff;
14778               else
14779                 op &= 0xffff;
14780           }
14781         }
14782       else
14783         {
14784           if (!(rex & REX_W))
14785             {
14786               if (sizeflag & DFLAG)
14787                 op &= 0xffffffff;
14788               else
14789                 op &= 0xffff;
14790             }
14791         }
14792       break;
14793     case v_mode:
14794       /* The operand-size prefix is overridden by a REX prefix.  */
14795       if ((sizeflag & DFLAG) || (rex & REX_W))
14796         op = get32s ();
14797       else
14798         op = get16 ();
14799       break;
14800     default:
14801       oappend (INTERNAL_DISASSEMBLER_ERROR);
14802       return;
14803     }
14804
14805   scratchbuf[0] = '$';
14806   print_operand_value (scratchbuf + 1, 1, op);
14807   oappend_maybe_intel (scratchbuf);
14808 }
14809
14810 static void
14811 OP_J (int bytemode, int sizeflag)
14812 {
14813   bfd_vma disp;
14814   bfd_vma mask = -1;
14815   bfd_vma segment = 0;
14816
14817   switch (bytemode)
14818     {
14819     case b_mode:
14820       FETCH_DATA (the_info, codep + 1);
14821       disp = *codep++;
14822       if ((disp & 0x80) != 0)
14823         disp -= 0x100;
14824       break;
14825     case v_mode:
14826       if (isa64 == amd64)
14827         USED_REX (REX_W);
14828       if ((sizeflag & DFLAG)
14829           || (address_mode == mode_64bit
14830               && (isa64 != amd64 || (rex & REX_W))))
14831         disp = get32s ();
14832       else
14833         {
14834           disp = get16 ();
14835           if ((disp & 0x8000) != 0)
14836             disp -= 0x10000;
14837           /* In 16bit mode, address is wrapped around at 64k within
14838              the same segment.  Otherwise, a data16 prefix on a jump
14839              instruction means that the pc is masked to 16 bits after
14840              the displacement is added!  */
14841           mask = 0xffff;
14842           if ((prefixes & PREFIX_DATA) == 0)
14843             segment = ((start_pc + (codep - start_codep))
14844                        & ~((bfd_vma) 0xffff));
14845         }
14846       if (address_mode != mode_64bit
14847           || (isa64 == amd64 && !(rex & REX_W)))
14848         used_prefixes |= (prefixes & PREFIX_DATA);
14849       break;
14850     default:
14851       oappend (INTERNAL_DISASSEMBLER_ERROR);
14852       return;
14853     }
14854   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14855   set_op (disp, 0);
14856   print_operand_value (scratchbuf, 1, disp);
14857   oappend (scratchbuf);
14858 }
14859
14860 static void
14861 OP_SEG (int bytemode, int sizeflag)
14862 {
14863   if (bytemode == w_mode)
14864     oappend (names_seg[modrm.reg]);
14865   else
14866     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14867 }
14868
14869 static void
14870 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14871 {
14872   int seg, offset;
14873
14874   if (sizeflag & DFLAG)
14875     {
14876       offset = get32 ();
14877       seg = get16 ();
14878     }
14879   else
14880     {
14881       offset = get16 ();
14882       seg = get16 ();
14883     }
14884   used_prefixes |= (prefixes & PREFIX_DATA);
14885   if (intel_syntax)
14886     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14887   else
14888     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14889   oappend (scratchbuf);
14890 }
14891
14892 static void
14893 OP_OFF (int bytemode, int sizeflag)
14894 {
14895   bfd_vma off;
14896
14897   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14898     intel_operand_size (bytemode, sizeflag);
14899   append_seg ();
14900
14901   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14902     off = get32 ();
14903   else
14904     off = get16 ();
14905
14906   if (intel_syntax)
14907     {
14908       if (!active_seg_prefix)
14909         {
14910           oappend (names_seg[ds_reg - es_reg]);
14911           oappend (":");
14912         }
14913     }
14914   print_operand_value (scratchbuf, 1, off);
14915   oappend (scratchbuf);
14916 }
14917
14918 static void
14919 OP_OFF64 (int bytemode, int sizeflag)
14920 {
14921   bfd_vma off;
14922
14923   if (address_mode != mode_64bit
14924       || (prefixes & PREFIX_ADDR))
14925     {
14926       OP_OFF (bytemode, sizeflag);
14927       return;
14928     }
14929
14930   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14931     intel_operand_size (bytemode, sizeflag);
14932   append_seg ();
14933
14934   off = get64 ();
14935
14936   if (intel_syntax)
14937     {
14938       if (!active_seg_prefix)
14939         {
14940           oappend (names_seg[ds_reg - es_reg]);
14941           oappend (":");
14942         }
14943     }
14944   print_operand_value (scratchbuf, 1, off);
14945   oappend (scratchbuf);
14946 }
14947
14948 static void
14949 ptr_reg (int code, int sizeflag)
14950 {
14951   const char *s;
14952
14953   *obufp++ = open_char;
14954   used_prefixes |= (prefixes & PREFIX_ADDR);
14955   if (address_mode == mode_64bit)
14956     {
14957       if (!(sizeflag & AFLAG))
14958         s = names32[code - eAX_reg];
14959       else
14960         s = names64[code - eAX_reg];
14961     }
14962   else if (sizeflag & AFLAG)
14963     s = names32[code - eAX_reg];
14964   else
14965     s = names16[code - eAX_reg];
14966   oappend (s);
14967   *obufp++ = close_char;
14968   *obufp = 0;
14969 }
14970
14971 static void
14972 OP_ESreg (int code, int sizeflag)
14973 {
14974   if (intel_syntax)
14975     {
14976       switch (codep[-1])
14977         {
14978         case 0x6d:      /* insw/insl */
14979           intel_operand_size (z_mode, sizeflag);
14980           break;
14981         case 0xa5:      /* movsw/movsl/movsq */
14982         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14983         case 0xab:      /* stosw/stosl */
14984         case 0xaf:      /* scasw/scasl */
14985           intel_operand_size (v_mode, sizeflag);
14986           break;
14987         default:
14988           intel_operand_size (b_mode, sizeflag);
14989         }
14990     }
14991   oappend_maybe_intel ("%es:");
14992   ptr_reg (code, sizeflag);
14993 }
14994
14995 static void
14996 OP_DSreg (int code, int sizeflag)
14997 {
14998   if (intel_syntax)
14999     {
15000       switch (codep[-1])
15001         {
15002         case 0x6f:      /* outsw/outsl */
15003           intel_operand_size (z_mode, sizeflag);
15004           break;
15005         case 0xa5:      /* movsw/movsl/movsq */
15006         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15007         case 0xad:      /* lodsw/lodsl/lodsq */
15008           intel_operand_size (v_mode, sizeflag);
15009           break;
15010         default:
15011           intel_operand_size (b_mode, sizeflag);
15012         }
15013     }
15014   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15015      default segment register DS is printed.  */
15016   if (!active_seg_prefix)
15017     active_seg_prefix = PREFIX_DS;
15018   append_seg ();
15019   ptr_reg (code, sizeflag);
15020 }
15021
15022 static void
15023 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15024 {
15025   int add;
15026   if (rex & REX_R)
15027     {
15028       USED_REX (REX_R);
15029       add = 8;
15030     }
15031   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15032     {
15033       all_prefixes[last_lock_prefix] = 0;
15034       used_prefixes |= PREFIX_LOCK;
15035       add = 8;
15036     }
15037   else
15038     add = 0;
15039   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15040   oappend_maybe_intel (scratchbuf);
15041 }
15042
15043 static void
15044 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15045 {
15046   int add;
15047   USED_REX (REX_R);
15048   if (rex & REX_R)
15049     add = 8;
15050   else
15051     add = 0;
15052   if (intel_syntax)
15053     sprintf (scratchbuf, "db%d", modrm.reg + add);
15054   else
15055     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15056   oappend (scratchbuf);
15057 }
15058
15059 static void
15060 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15061 {
15062   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15063   oappend_maybe_intel (scratchbuf);
15064 }
15065
15066 static void
15067 OP_R (int bytemode, int sizeflag)
15068 {
15069   /* Skip mod/rm byte.  */
15070   MODRM_CHECK;
15071   codep++;
15072   OP_E_register (bytemode, sizeflag);
15073 }
15074
15075 static void
15076 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15077 {
15078   int reg = modrm.reg;
15079   const char **names;
15080
15081   used_prefixes |= (prefixes & PREFIX_DATA);
15082   if (prefixes & PREFIX_DATA)
15083     {
15084       names = names_xmm;
15085       USED_REX (REX_R);
15086       if (rex & REX_R)
15087         reg += 8;
15088     }
15089   else
15090     names = names_mm;
15091   oappend (names[reg]);
15092 }
15093
15094 static void
15095 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15096 {
15097   int reg = modrm.reg;
15098   const char **names;
15099
15100   USED_REX (REX_R);
15101   if (rex & REX_R)
15102     reg += 8;
15103   if (vex.evex)
15104     {
15105       if (!vex.r)
15106         reg += 16;
15107     }
15108
15109   if (need_vex
15110       && bytemode != xmm_mode
15111       && bytemode != xmmq_mode
15112       && bytemode != evex_half_bcst_xmmq_mode
15113       && bytemode != ymm_mode
15114       && bytemode != scalar_mode)
15115     {
15116       switch (vex.length)
15117         {
15118         case 128:
15119           names = names_xmm;
15120           break;
15121         case 256:
15122           if (vex.w
15123               || (bytemode != vex_vsib_q_w_dq_mode
15124                   && bytemode != vex_vsib_q_w_d_mode))
15125             names = names_ymm;
15126           else
15127             names = names_xmm;
15128           break;
15129         case 512:
15130           names = names_zmm;
15131           break;
15132         default:
15133           abort ();
15134         }
15135     }
15136   else if (bytemode == xmmq_mode
15137            || bytemode == evex_half_bcst_xmmq_mode)
15138     {
15139       switch (vex.length)
15140         {
15141         case 128:
15142         case 256:
15143           names = names_xmm;
15144           break;
15145         case 512:
15146           names = names_ymm;
15147           break;
15148         default:
15149           abort ();
15150         }
15151     }
15152   else if (bytemode == ymm_mode)
15153     names = names_ymm;
15154   else
15155     names = names_xmm;
15156   oappend (names[reg]);
15157 }
15158
15159 static void
15160 OP_EM (int bytemode, int sizeflag)
15161 {
15162   int reg;
15163   const char **names;
15164
15165   if (modrm.mod != 3)
15166     {
15167       if (intel_syntax
15168           && (bytemode == v_mode || bytemode == v_swap_mode))
15169         {
15170           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15171           used_prefixes |= (prefixes & PREFIX_DATA);
15172         }
15173       OP_E (bytemode, sizeflag);
15174       return;
15175     }
15176
15177   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15178     swap_operand ();
15179
15180   /* Skip mod/rm byte.  */
15181   MODRM_CHECK;
15182   codep++;
15183   used_prefixes |= (prefixes & PREFIX_DATA);
15184   reg = modrm.rm;
15185   if (prefixes & PREFIX_DATA)
15186     {
15187       names = names_xmm;
15188       USED_REX (REX_B);
15189       if (rex & REX_B)
15190         reg += 8;
15191     }
15192   else
15193     names = names_mm;
15194   oappend (names[reg]);
15195 }
15196
15197 /* cvt* are the only instructions in sse2 which have
15198    both SSE and MMX operands and also have 0x66 prefix
15199    in their opcode. 0x66 was originally used to differentiate
15200    between SSE and MMX instruction(operands). So we have to handle the
15201    cvt* separately using OP_EMC and OP_MXC */
15202 static void
15203 OP_EMC (int bytemode, int sizeflag)
15204 {
15205   if (modrm.mod != 3)
15206     {
15207       if (intel_syntax && bytemode == v_mode)
15208         {
15209           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15210           used_prefixes |= (prefixes & PREFIX_DATA);
15211         }
15212       OP_E (bytemode, sizeflag);
15213       return;
15214     }
15215
15216   /* Skip mod/rm byte.  */
15217   MODRM_CHECK;
15218   codep++;
15219   used_prefixes |= (prefixes & PREFIX_DATA);
15220   oappend (names_mm[modrm.rm]);
15221 }
15222
15223 static void
15224 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15225 {
15226   used_prefixes |= (prefixes & PREFIX_DATA);
15227   oappend (names_mm[modrm.reg]);
15228 }
15229
15230 static void
15231 OP_EX (int bytemode, int sizeflag)
15232 {
15233   int reg;
15234   const char **names;
15235
15236   /* Skip mod/rm byte.  */
15237   MODRM_CHECK;
15238   codep++;
15239
15240   if (modrm.mod != 3)
15241     {
15242       OP_E_memory (bytemode, sizeflag);
15243       return;
15244     }
15245
15246   reg = modrm.rm;
15247   USED_REX (REX_B);
15248   if (rex & REX_B)
15249     reg += 8;
15250   if (vex.evex)
15251     {
15252       USED_REX (REX_X);
15253       if ((rex & REX_X))
15254         reg += 16;
15255     }
15256
15257   if ((sizeflag & SUFFIX_ALWAYS)
15258       && (bytemode == x_swap_mode
15259           || bytemode == d_swap_mode
15260           || bytemode == d_scalar_swap_mode
15261           || bytemode == q_swap_mode
15262           || bytemode == q_scalar_swap_mode))
15263     swap_operand ();
15264
15265   if (need_vex
15266       && bytemode != xmm_mode
15267       && bytemode != xmmdw_mode
15268       && bytemode != xmmqd_mode
15269       && bytemode != xmm_mb_mode
15270       && bytemode != xmm_mw_mode
15271       && bytemode != xmm_md_mode
15272       && bytemode != xmm_mq_mode
15273       && bytemode != xmm_mdq_mode
15274       && bytemode != xmmq_mode
15275       && bytemode != evex_half_bcst_xmmq_mode
15276       && bytemode != ymm_mode
15277       && bytemode != d_scalar_mode
15278       && bytemode != d_scalar_swap_mode
15279       && bytemode != q_scalar_mode
15280       && bytemode != q_scalar_swap_mode
15281       && bytemode != vex_scalar_w_dq_mode)
15282     {
15283       switch (vex.length)
15284         {
15285         case 128:
15286           names = names_xmm;
15287           break;
15288         case 256:
15289           names = names_ymm;
15290           break;
15291         case 512:
15292           names = names_zmm;
15293           break;
15294         default:
15295           abort ();
15296         }
15297     }
15298   else if (bytemode == xmmq_mode
15299            || bytemode == evex_half_bcst_xmmq_mode)
15300     {
15301       switch (vex.length)
15302         {
15303         case 128:
15304         case 256:
15305           names = names_xmm;
15306           break;
15307         case 512:
15308           names = names_ymm;
15309           break;
15310         default:
15311           abort ();
15312         }
15313     }
15314   else if (bytemode == ymm_mode)
15315     names = names_ymm;
15316   else
15317     names = names_xmm;
15318   oappend (names[reg]);
15319 }
15320
15321 static void
15322 OP_MS (int bytemode, int sizeflag)
15323 {
15324   if (modrm.mod == 3)
15325     OP_EM (bytemode, sizeflag);
15326   else
15327     BadOp ();
15328 }
15329
15330 static void
15331 OP_XS (int bytemode, int sizeflag)
15332 {
15333   if (modrm.mod == 3)
15334     OP_EX (bytemode, sizeflag);
15335   else
15336     BadOp ();
15337 }
15338
15339 static void
15340 OP_M (int bytemode, int sizeflag)
15341 {
15342   if (modrm.mod == 3)
15343     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15344     BadOp ();
15345   else
15346     OP_E (bytemode, sizeflag);
15347 }
15348
15349 static void
15350 OP_0f07 (int bytemode, int sizeflag)
15351 {
15352   if (modrm.mod != 3 || modrm.rm != 0)
15353     BadOp ();
15354   else
15355     OP_E (bytemode, sizeflag);
15356 }
15357
15358 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15359    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15360
15361 static void
15362 NOP_Fixup1 (int bytemode, int sizeflag)
15363 {
15364   if ((prefixes & PREFIX_DATA) != 0
15365       || (rex != 0
15366           && rex != 0x48
15367           && address_mode == mode_64bit))
15368     OP_REG (bytemode, sizeflag);
15369   else
15370     strcpy (obuf, "nop");
15371 }
15372
15373 static void
15374 NOP_Fixup2 (int bytemode, int sizeflag)
15375 {
15376   if ((prefixes & PREFIX_DATA) != 0
15377       || (rex != 0
15378           && rex != 0x48
15379           && address_mode == mode_64bit))
15380     OP_IMREG (bytemode, sizeflag);
15381 }
15382
15383 static const char *const Suffix3DNow[] = {
15384 /* 00 */        NULL,           NULL,           NULL,           NULL,
15385 /* 04 */        NULL,           NULL,           NULL,           NULL,
15386 /* 08 */        NULL,           NULL,           NULL,           NULL,
15387 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15388 /* 10 */        NULL,           NULL,           NULL,           NULL,
15389 /* 14 */        NULL,           NULL,           NULL,           NULL,
15390 /* 18 */        NULL,           NULL,           NULL,           NULL,
15391 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15392 /* 20 */        NULL,           NULL,           NULL,           NULL,
15393 /* 24 */        NULL,           NULL,           NULL,           NULL,
15394 /* 28 */        NULL,           NULL,           NULL,           NULL,
15395 /* 2C */        NULL,           NULL,           NULL,           NULL,
15396 /* 30 */        NULL,           NULL,           NULL,           NULL,
15397 /* 34 */        NULL,           NULL,           NULL,           NULL,
15398 /* 38 */        NULL,           NULL,           NULL,           NULL,
15399 /* 3C */        NULL,           NULL,           NULL,           NULL,
15400 /* 40 */        NULL,           NULL,           NULL,           NULL,
15401 /* 44 */        NULL,           NULL,           NULL,           NULL,
15402 /* 48 */        NULL,           NULL,           NULL,           NULL,
15403 /* 4C */        NULL,           NULL,           NULL,           NULL,
15404 /* 50 */        NULL,           NULL,           NULL,           NULL,
15405 /* 54 */        NULL,           NULL,           NULL,           NULL,
15406 /* 58 */        NULL,           NULL,           NULL,           NULL,
15407 /* 5C */        NULL,           NULL,           NULL,           NULL,
15408 /* 60 */        NULL,           NULL,           NULL,           NULL,
15409 /* 64 */        NULL,           NULL,           NULL,           NULL,
15410 /* 68 */        NULL,           NULL,           NULL,           NULL,
15411 /* 6C */        NULL,           NULL,           NULL,           NULL,
15412 /* 70 */        NULL,           NULL,           NULL,           NULL,
15413 /* 74 */        NULL,           NULL,           NULL,           NULL,
15414 /* 78 */        NULL,           NULL,           NULL,           NULL,
15415 /* 7C */        NULL,           NULL,           NULL,           NULL,
15416 /* 80 */        NULL,           NULL,           NULL,           NULL,
15417 /* 84 */        NULL,           NULL,           NULL,           NULL,
15418 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15419 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15420 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15421 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15422 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15423 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15424 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15425 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15426 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15427 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15428 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15429 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15430 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15431 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15432 /* C0 */        NULL,           NULL,           NULL,           NULL,
15433 /* C4 */        NULL,           NULL,           NULL,           NULL,
15434 /* C8 */        NULL,           NULL,           NULL,           NULL,
15435 /* CC */        NULL,           NULL,           NULL,           NULL,
15436 /* D0 */        NULL,           NULL,           NULL,           NULL,
15437 /* D4 */        NULL,           NULL,           NULL,           NULL,
15438 /* D8 */        NULL,           NULL,           NULL,           NULL,
15439 /* DC */        NULL,           NULL,           NULL,           NULL,
15440 /* E0 */        NULL,           NULL,           NULL,           NULL,
15441 /* E4 */        NULL,           NULL,           NULL,           NULL,
15442 /* E8 */        NULL,           NULL,           NULL,           NULL,
15443 /* EC */        NULL,           NULL,           NULL,           NULL,
15444 /* F0 */        NULL,           NULL,           NULL,           NULL,
15445 /* F4 */        NULL,           NULL,           NULL,           NULL,
15446 /* F8 */        NULL,           NULL,           NULL,           NULL,
15447 /* FC */        NULL,           NULL,           NULL,           NULL,
15448 };
15449
15450 static void
15451 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15452 {
15453   const char *mnemonic;
15454
15455   FETCH_DATA (the_info, codep + 1);
15456   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15457      place where an 8-bit immediate would normally go.  ie. the last
15458      byte of the instruction.  */
15459   obufp = mnemonicendp;
15460   mnemonic = Suffix3DNow[*codep++ & 0xff];
15461   if (mnemonic)
15462     oappend (mnemonic);
15463   else
15464     {
15465       /* Since a variable sized modrm/sib chunk is between the start
15466          of the opcode (0x0f0f) and the opcode suffix, we need to do
15467          all the modrm processing first, and don't know until now that
15468          we have a bad opcode.  This necessitates some cleaning up.  */
15469       op_out[0][0] = '\0';
15470       op_out[1][0] = '\0';
15471       BadOp ();
15472     }
15473   mnemonicendp = obufp;
15474 }
15475
15476 static struct op simd_cmp_op[] =
15477 {
15478   { STRING_COMMA_LEN ("eq") },
15479   { STRING_COMMA_LEN ("lt") },
15480   { STRING_COMMA_LEN ("le") },
15481   { STRING_COMMA_LEN ("unord") },
15482   { STRING_COMMA_LEN ("neq") },
15483   { STRING_COMMA_LEN ("nlt") },
15484   { STRING_COMMA_LEN ("nle") },
15485   { STRING_COMMA_LEN ("ord") }
15486 };
15487
15488 static void
15489 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15490 {
15491   unsigned int cmp_type;
15492
15493   FETCH_DATA (the_info, codep + 1);
15494   cmp_type = *codep++ & 0xff;
15495   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15496     {
15497       char suffix [3];
15498       char *p = mnemonicendp - 2;
15499       suffix[0] = p[0];
15500       suffix[1] = p[1];
15501       suffix[2] = '\0';
15502       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15503       mnemonicendp += simd_cmp_op[cmp_type].len;
15504     }
15505   else
15506     {
15507       /* We have a reserved extension byte.  Output it directly.  */
15508       scratchbuf[0] = '$';
15509       print_operand_value (scratchbuf + 1, 1, cmp_type);
15510       oappend_maybe_intel (scratchbuf);
15511       scratchbuf[0] = '\0';
15512     }
15513 }
15514
15515 static void
15516 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15517           int sizeflag ATTRIBUTE_UNUSED)
15518 {
15519   /* mwaitx %eax,%ecx,%ebx */
15520   if (!intel_syntax)
15521     {
15522       const char **names = (address_mode == mode_64bit
15523                             ? names64 : names32);
15524       strcpy (op_out[0], names[0]);
15525       strcpy (op_out[1], names[1]);
15526       strcpy (op_out[2], names[3]);
15527       two_source_ops = 1;
15528     }
15529   /* Skip mod/rm byte.  */
15530   MODRM_CHECK;
15531   codep++;
15532 }
15533
15534 static void
15535 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15536           int sizeflag ATTRIBUTE_UNUSED)
15537 {
15538   /* mwait %eax,%ecx  */
15539   if (!intel_syntax)
15540     {
15541       const char **names = (address_mode == mode_64bit
15542                             ? names64 : names32);
15543       strcpy (op_out[0], names[0]);
15544       strcpy (op_out[1], names[1]);
15545       two_source_ops = 1;
15546     }
15547   /* Skip mod/rm byte.  */
15548   MODRM_CHECK;
15549   codep++;
15550 }
15551
15552 static void
15553 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15554             int sizeflag ATTRIBUTE_UNUSED)
15555 {
15556   /* monitor %eax,%ecx,%edx"  */
15557   if (!intel_syntax)
15558     {
15559       const char **op1_names;
15560       const char **names = (address_mode == mode_64bit
15561                             ? names64 : names32);
15562
15563       if (!(prefixes & PREFIX_ADDR))
15564         op1_names = (address_mode == mode_16bit
15565                      ? names16 : names);
15566       else
15567         {
15568           /* Remove "addr16/addr32".  */
15569           all_prefixes[last_addr_prefix] = 0;
15570           op1_names = (address_mode != mode_32bit
15571                        ? names32 : names16);
15572           used_prefixes |= PREFIX_ADDR;
15573         }
15574       strcpy (op_out[0], op1_names[0]);
15575       strcpy (op_out[1], names[1]);
15576       strcpy (op_out[2], names[2]);
15577       two_source_ops = 1;
15578     }
15579   /* Skip mod/rm byte.  */
15580   MODRM_CHECK;
15581   codep++;
15582 }
15583
15584 static void
15585 BadOp (void)
15586 {
15587   /* Throw away prefixes and 1st. opcode byte.  */
15588   codep = insn_codep + 1;
15589   oappend ("(bad)");
15590 }
15591
15592 static void
15593 REP_Fixup (int bytemode, int sizeflag)
15594 {
15595   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15596      lods and stos.  */
15597   if (prefixes & PREFIX_REPZ)
15598     all_prefixes[last_repz_prefix] = REP_PREFIX;
15599
15600   switch (bytemode)
15601     {
15602     case al_reg:
15603     case eAX_reg:
15604     case indir_dx_reg:
15605       OP_IMREG (bytemode, sizeflag);
15606       break;
15607     case eDI_reg:
15608       OP_ESreg (bytemode, sizeflag);
15609       break;
15610     case eSI_reg:
15611       OP_DSreg (bytemode, sizeflag);
15612       break;
15613     default:
15614       abort ();
15615       break;
15616     }
15617 }
15618
15619 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15620    "bnd".  */
15621
15622 static void
15623 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15624 {
15625   if (prefixes & PREFIX_REPNZ)
15626     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15627 }
15628
15629 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15630    "notrack".  */
15631
15632 static void
15633 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15634                int sizeflag ATTRIBUTE_UNUSED)
15635 {
15636   if (active_seg_prefix == PREFIX_DS
15637       && (address_mode != mode_64bit || last_data_prefix < 0))
15638     {
15639       /* NOTRACK prefix is only valid on indirect branch instructions.
15640          NB: DATA prefix is unsupported for Intel64.  */
15641       active_seg_prefix = 0;
15642       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15643     }
15644 }
15645
15646 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15647    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15648  */
15649
15650 static void
15651 HLE_Fixup1 (int bytemode, int sizeflag)
15652 {
15653   if (modrm.mod != 3
15654       && (prefixes & PREFIX_LOCK) != 0)
15655     {
15656       if (prefixes & PREFIX_REPZ)
15657         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15658       if (prefixes & PREFIX_REPNZ)
15659         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15660     }
15661
15662   OP_E (bytemode, sizeflag);
15663 }
15664
15665 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15666    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15667  */
15668
15669 static void
15670 HLE_Fixup2 (int bytemode, int sizeflag)
15671 {
15672   if (modrm.mod != 3)
15673     {
15674       if (prefixes & PREFIX_REPZ)
15675         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15676       if (prefixes & PREFIX_REPNZ)
15677         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15678     }
15679
15680   OP_E (bytemode, sizeflag);
15681 }
15682
15683 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15684    "xrelease" for memory operand.  No check for LOCK prefix.   */
15685
15686 static void
15687 HLE_Fixup3 (int bytemode, int sizeflag)
15688 {
15689   if (modrm.mod != 3
15690       && last_repz_prefix > last_repnz_prefix
15691       && (prefixes & PREFIX_REPZ) != 0)
15692     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15693
15694   OP_E (bytemode, sizeflag);
15695 }
15696
15697 static void
15698 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15699 {
15700   USED_REX (REX_W);
15701   if (rex & REX_W)
15702     {
15703       /* Change cmpxchg8b to cmpxchg16b.  */
15704       char *p = mnemonicendp - 2;
15705       mnemonicendp = stpcpy (p, "16b");
15706       bytemode = o_mode;
15707     }
15708   else if ((prefixes & PREFIX_LOCK) != 0)
15709     {
15710       if (prefixes & PREFIX_REPZ)
15711         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15712       if (prefixes & PREFIX_REPNZ)
15713         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15714     }
15715
15716   OP_M (bytemode, sizeflag);
15717 }
15718
15719 static void
15720 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15721 {
15722   const char **names;
15723
15724   if (need_vex)
15725     {
15726       switch (vex.length)
15727         {
15728         case 128:
15729           names = names_xmm;
15730           break;
15731         case 256:
15732           names = names_ymm;
15733           break;
15734         default:
15735           abort ();
15736         }
15737     }
15738   else
15739     names = names_xmm;
15740   oappend (names[reg]);
15741 }
15742
15743 static void
15744 CRC32_Fixup (int bytemode, int sizeflag)
15745 {
15746   /* Add proper suffix to "crc32".  */
15747   char *p = mnemonicendp;
15748
15749   switch (bytemode)
15750     {
15751     case b_mode:
15752       if (intel_syntax)
15753         goto skip;
15754
15755       *p++ = 'b';
15756       break;
15757     case v_mode:
15758       if (intel_syntax)
15759         goto skip;
15760
15761       USED_REX (REX_W);
15762       if (rex & REX_W)
15763         *p++ = 'q';
15764       else
15765         {
15766           if (sizeflag & DFLAG)
15767             *p++ = 'l';
15768           else
15769             *p++ = 'w';
15770           used_prefixes |= (prefixes & PREFIX_DATA);
15771         }
15772       break;
15773     default:
15774       oappend (INTERNAL_DISASSEMBLER_ERROR);
15775       break;
15776     }
15777   mnemonicendp = p;
15778   *p = '\0';
15779
15780 skip:
15781   if (modrm.mod == 3)
15782     {
15783       int add;
15784
15785       /* Skip mod/rm byte.  */
15786       MODRM_CHECK;
15787       codep++;
15788
15789       USED_REX (REX_B);
15790       add = (rex & REX_B) ? 8 : 0;
15791       if (bytemode == b_mode)
15792         {
15793           USED_REX (0);
15794           if (rex)
15795             oappend (names8rex[modrm.rm + add]);
15796           else
15797             oappend (names8[modrm.rm + add]);
15798         }
15799       else
15800         {
15801           USED_REX (REX_W);
15802           if (rex & REX_W)
15803             oappend (names64[modrm.rm + add]);
15804           else if ((prefixes & PREFIX_DATA))
15805             oappend (names16[modrm.rm + add]);
15806           else
15807             oappend (names32[modrm.rm + add]);
15808         }
15809     }
15810   else
15811     OP_E (bytemode, sizeflag);
15812 }
15813
15814 static void
15815 FXSAVE_Fixup (int bytemode, int sizeflag)
15816 {
15817   /* Add proper suffix to "fxsave" and "fxrstor".  */
15818   USED_REX (REX_W);
15819   if (rex & REX_W)
15820     {
15821       char *p = mnemonicendp;
15822       *p++ = '6';
15823       *p++ = '4';
15824       *p = '\0';
15825       mnemonicendp = p;
15826     }
15827   OP_M (bytemode, sizeflag);
15828 }
15829
15830 static void
15831 PCMPESTR_Fixup (int bytemode, int sizeflag)
15832 {
15833   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15834   if (!intel_syntax)
15835     {
15836       char *p = mnemonicendp;
15837
15838       USED_REX (REX_W);
15839       if (rex & REX_W)
15840         *p++ = 'q';
15841       else if (sizeflag & SUFFIX_ALWAYS)
15842         *p++ = 'l';
15843
15844       *p = '\0';
15845       mnemonicendp = p;
15846     }
15847
15848   OP_EX (bytemode, sizeflag);
15849 }
15850
15851 /* Display the destination register operand for instructions with
15852    VEX. */
15853
15854 static void
15855 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15856 {
15857   int reg;
15858   const char **names;
15859
15860   if (!need_vex)
15861     abort ();
15862
15863   if (!need_vex_reg)
15864     return;
15865
15866   reg = vex.register_specifier;
15867   vex.register_specifier = 0;
15868   if (address_mode != mode_64bit)
15869     reg &= 7;
15870   else if (vex.evex && !vex.v)
15871     reg += 16;
15872
15873   if (bytemode == vex_scalar_mode)
15874     {
15875       oappend (names_xmm[reg]);
15876       return;
15877     }
15878
15879   switch (vex.length)
15880     {
15881     case 128:
15882       switch (bytemode)
15883         {
15884         case vex_mode:
15885         case vex128_mode:
15886         case vex_vsib_q_w_dq_mode:
15887         case vex_vsib_q_w_d_mode:
15888           names = names_xmm;
15889           break;
15890         case dq_mode:
15891           if (rex & REX_W)
15892             names = names64;
15893           else
15894             names = names32;
15895           break;
15896         case mask_bd_mode:
15897         case mask_mode:
15898           if (reg > 0x7)
15899             {
15900               oappend ("(bad)");
15901               return;
15902             }
15903           names = names_mask;
15904           break;
15905         default:
15906           abort ();
15907           return;
15908         }
15909       break;
15910     case 256:
15911       switch (bytemode)
15912         {
15913         case vex_mode:
15914         case vex256_mode:
15915           names = names_ymm;
15916           break;
15917         case vex_vsib_q_w_dq_mode:
15918         case vex_vsib_q_w_d_mode:
15919           names = vex.w ? names_ymm : names_xmm;
15920           break;
15921         case mask_bd_mode:
15922         case mask_mode:
15923           if (reg > 0x7)
15924             {
15925               oappend ("(bad)");
15926               return;
15927             }
15928           names = names_mask;
15929           break;
15930         default:
15931           /* See PR binutils/20893 for a reproducer.  */
15932           oappend ("(bad)");
15933           return;
15934         }
15935       break;
15936     case 512:
15937       names = names_zmm;
15938       break;
15939     default:
15940       abort ();
15941       break;
15942     }
15943   oappend (names[reg]);
15944 }
15945
15946 /* Get the VEX immediate byte without moving codep.  */
15947
15948 static unsigned char
15949 get_vex_imm8 (int sizeflag, int opnum)
15950 {
15951   int bytes_before_imm = 0;
15952
15953   if (modrm.mod != 3)
15954     {
15955       /* There are SIB/displacement bytes.  */
15956       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15957         {
15958           /* 32/64 bit address mode */
15959           int base = modrm.rm;
15960
15961           /* Check SIB byte.  */
15962           if (base == 4)
15963             {
15964               FETCH_DATA (the_info, codep + 1);
15965               base = *codep & 7;
15966               /* When decoding the third source, don't increase
15967                  bytes_before_imm as this has already been incremented
15968                  by one in OP_E_memory while decoding the second
15969                  source operand.  */
15970               if (opnum == 0)
15971                 bytes_before_imm++;
15972             }
15973
15974           /* Don't increase bytes_before_imm when decoding the third source,
15975              it has already been incremented by OP_E_memory while decoding
15976              the second source operand.  */
15977           if (opnum == 0)
15978             {
15979               switch (modrm.mod)
15980                 {
15981                   case 0:
15982                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15983                        SIB == 5, there is a 4 byte displacement.  */
15984                     if (base != 5)
15985                       /* No displacement. */
15986                       break;
15987                     /* Fall through.  */
15988                   case 2:
15989                     /* 4 byte displacement.  */
15990                     bytes_before_imm += 4;
15991                     break;
15992                   case 1:
15993                     /* 1 byte displacement.  */
15994                     bytes_before_imm++;
15995                     break;
15996                 }
15997             }
15998         }
15999       else
16000         {
16001           /* 16 bit address mode */
16002           /* Don't increase bytes_before_imm when decoding the third source,
16003              it has already been incremented by OP_E_memory while decoding
16004              the second source operand.  */
16005           if (opnum == 0)
16006             {
16007               switch (modrm.mod)
16008                 {
16009                 case 0:
16010                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16011                   if (modrm.rm != 6)
16012                     /* No displacement. */
16013                     break;
16014                   /* Fall through.  */
16015                 case 2:
16016                   /* 2 byte displacement.  */
16017                   bytes_before_imm += 2;
16018                   break;
16019                 case 1:
16020                   /* 1 byte displacement: when decoding the third source,
16021                      don't increase bytes_before_imm as this has already
16022                      been incremented by one in OP_E_memory while decoding
16023                      the second source operand.  */
16024                   if (opnum == 0)
16025                     bytes_before_imm++;
16026
16027                   break;
16028                 }
16029             }
16030         }
16031     }
16032
16033   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16034   return codep [bytes_before_imm];
16035 }
16036
16037 static void
16038 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16039 {
16040   const char **names;
16041
16042   if (reg == -1 && modrm.mod != 3)
16043     {
16044       OP_E_memory (bytemode, sizeflag);
16045       return;
16046     }
16047   else
16048     {
16049       if (reg == -1)
16050         {
16051           reg = modrm.rm;
16052           USED_REX (REX_B);
16053           if (rex & REX_B)
16054             reg += 8;
16055         }
16056       if (address_mode != mode_64bit)
16057         reg &= 7;
16058     }
16059
16060   switch (vex.length)
16061     {
16062     case 128:
16063       names = names_xmm;
16064       break;
16065     case 256:
16066       names = names_ymm;
16067       break;
16068     default:
16069       abort ();
16070     }
16071   oappend (names[reg]);
16072 }
16073
16074 static void
16075 OP_EX_VexImmW (int bytemode, int sizeflag)
16076 {
16077   int reg = -1;
16078   static unsigned char vex_imm8;
16079
16080   if (vex_w_done == 0)
16081     {
16082       vex_w_done = 1;
16083
16084       /* Skip mod/rm byte.  */
16085       MODRM_CHECK;
16086       codep++;
16087
16088       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16089
16090       if (vex.w)
16091           reg = vex_imm8 >> 4;
16092
16093       OP_EX_VexReg (bytemode, sizeflag, reg);
16094     }
16095   else if (vex_w_done == 1)
16096     {
16097       vex_w_done = 2;
16098
16099       if (!vex.w)
16100           reg = vex_imm8 >> 4;
16101
16102       OP_EX_VexReg (bytemode, sizeflag, reg);
16103     }
16104   else
16105     {
16106       /* Output the imm8 directly.  */
16107       scratchbuf[0] = '$';
16108       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16109       oappend_maybe_intel (scratchbuf);
16110       scratchbuf[0] = '\0';
16111       codep++;
16112     }
16113 }
16114
16115 static void
16116 OP_Vex_2src (int bytemode, int sizeflag)
16117 {
16118   if (modrm.mod == 3)
16119     {
16120       int reg = modrm.rm;
16121       USED_REX (REX_B);
16122       if (rex & REX_B)
16123         reg += 8;
16124       oappend (names_xmm[reg]);
16125     }
16126   else
16127     {
16128       if (intel_syntax
16129           && (bytemode == v_mode || bytemode == v_swap_mode))
16130         {
16131           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16132           used_prefixes |= (prefixes & PREFIX_DATA);
16133         }
16134       OP_E (bytemode, sizeflag);
16135     }
16136 }
16137
16138 static void
16139 OP_Vex_2src_1 (int bytemode, int sizeflag)
16140 {
16141   if (modrm.mod == 3)
16142     {
16143       /* Skip mod/rm byte.   */
16144       MODRM_CHECK;
16145       codep++;
16146     }
16147
16148   if (vex.w)
16149     {
16150       unsigned int reg = vex.register_specifier;
16151       vex.register_specifier = 0;
16152
16153       if (address_mode != mode_64bit)
16154         reg &= 7;
16155       oappend (names_xmm[reg]);
16156     }
16157   else
16158     OP_Vex_2src (bytemode, sizeflag);
16159 }
16160
16161 static void
16162 OP_Vex_2src_2 (int bytemode, int sizeflag)
16163 {
16164   if (vex.w)
16165     OP_Vex_2src (bytemode, sizeflag);
16166   else
16167     {
16168       unsigned int reg = vex.register_specifier;
16169       vex.register_specifier = 0;
16170
16171       if (address_mode != mode_64bit)
16172         reg &= 7;
16173       oappend (names_xmm[reg]);
16174     }
16175 }
16176
16177 static void
16178 OP_EX_VexW (int bytemode, int sizeflag)
16179 {
16180   int reg = -1;
16181
16182   if (!vex_w_done)
16183     {
16184       /* Skip mod/rm byte.  */
16185       MODRM_CHECK;
16186       codep++;
16187
16188       if (vex.w)
16189         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16190     }
16191   else
16192     {
16193       if (!vex.w)
16194         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16195     }
16196
16197   OP_EX_VexReg (bytemode, sizeflag, reg);
16198
16199   if (vex_w_done)
16200     codep++;
16201   vex_w_done = 1;
16202 }
16203
16204 static void
16205 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16206 {
16207   int reg;
16208   const char **names;
16209
16210   FETCH_DATA (the_info, codep + 1);
16211   reg = *codep++;
16212
16213   if (bytemode != x_mode)
16214     abort ();
16215
16216   reg >>= 4;
16217   if (address_mode != mode_64bit)
16218     reg &= 7;
16219
16220   switch (vex.length)
16221     {
16222     case 128:
16223       names = names_xmm;
16224       break;
16225     case 256:
16226       names = names_ymm;
16227       break;
16228     default:
16229       abort ();
16230     }
16231   oappend (names[reg]);
16232 }
16233
16234 static void
16235 OP_XMM_VexW (int bytemode, int sizeflag)
16236 {
16237   /* Turn off the REX.W bit since it is used for swapping operands
16238      now.  */
16239   rex &= ~REX_W;
16240   OP_XMM (bytemode, sizeflag);
16241 }
16242
16243 static void
16244 OP_EX_Vex (int bytemode, int sizeflag)
16245 {
16246   if (modrm.mod != 3)
16247     need_vex_reg = 0;
16248   OP_EX (bytemode, sizeflag);
16249 }
16250
16251 static void
16252 OP_XMM_Vex (int bytemode, int sizeflag)
16253 {
16254   if (modrm.mod != 3)
16255     need_vex_reg = 0;
16256   OP_XMM (bytemode, sizeflag);
16257 }
16258
16259 static struct op vex_cmp_op[] =
16260 {
16261   { STRING_COMMA_LEN ("eq") },
16262   { STRING_COMMA_LEN ("lt") },
16263   { STRING_COMMA_LEN ("le") },
16264   { STRING_COMMA_LEN ("unord") },
16265   { STRING_COMMA_LEN ("neq") },
16266   { STRING_COMMA_LEN ("nlt") },
16267   { STRING_COMMA_LEN ("nle") },
16268   { STRING_COMMA_LEN ("ord") },
16269   { STRING_COMMA_LEN ("eq_uq") },
16270   { STRING_COMMA_LEN ("nge") },
16271   { STRING_COMMA_LEN ("ngt") },
16272   { STRING_COMMA_LEN ("false") },
16273   { STRING_COMMA_LEN ("neq_oq") },
16274   { STRING_COMMA_LEN ("ge") },
16275   { STRING_COMMA_LEN ("gt") },
16276   { STRING_COMMA_LEN ("true") },
16277   { STRING_COMMA_LEN ("eq_os") },
16278   { STRING_COMMA_LEN ("lt_oq") },
16279   { STRING_COMMA_LEN ("le_oq") },
16280   { STRING_COMMA_LEN ("unord_s") },
16281   { STRING_COMMA_LEN ("neq_us") },
16282   { STRING_COMMA_LEN ("nlt_uq") },
16283   { STRING_COMMA_LEN ("nle_uq") },
16284   { STRING_COMMA_LEN ("ord_s") },
16285   { STRING_COMMA_LEN ("eq_us") },
16286   { STRING_COMMA_LEN ("nge_uq") },
16287   { STRING_COMMA_LEN ("ngt_uq") },
16288   { STRING_COMMA_LEN ("false_os") },
16289   { STRING_COMMA_LEN ("neq_os") },
16290   { STRING_COMMA_LEN ("ge_oq") },
16291   { STRING_COMMA_LEN ("gt_oq") },
16292   { STRING_COMMA_LEN ("true_us") },
16293 };
16294
16295 static void
16296 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16297 {
16298   unsigned int cmp_type;
16299
16300   FETCH_DATA (the_info, codep + 1);
16301   cmp_type = *codep++ & 0xff;
16302   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16303     {
16304       char suffix [3];
16305       char *p = mnemonicendp - 2;
16306       suffix[0] = p[0];
16307       suffix[1] = p[1];
16308       suffix[2] = '\0';
16309       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16310       mnemonicendp += vex_cmp_op[cmp_type].len;
16311     }
16312   else
16313     {
16314       /* We have a reserved extension byte.  Output it directly.  */
16315       scratchbuf[0] = '$';
16316       print_operand_value (scratchbuf + 1, 1, cmp_type);
16317       oappend_maybe_intel (scratchbuf);
16318       scratchbuf[0] = '\0';
16319     }
16320 }
16321
16322 static void
16323 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16324              int sizeflag ATTRIBUTE_UNUSED)
16325 {
16326   unsigned int cmp_type;
16327
16328   if (!vex.evex)
16329     abort ();
16330
16331   FETCH_DATA (the_info, codep + 1);
16332   cmp_type = *codep++ & 0xff;
16333   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16334      If it's the case, print suffix, otherwise - print the immediate.  */
16335   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16336       && cmp_type != 3
16337       && cmp_type != 7)
16338     {
16339       char suffix [3];
16340       char *p = mnemonicendp - 2;
16341
16342       /* vpcmp* can have both one- and two-lettered suffix.  */
16343       if (p[0] == 'p')
16344         {
16345           p++;
16346           suffix[0] = p[0];
16347           suffix[1] = '\0';
16348         }
16349       else
16350         {
16351           suffix[0] = p[0];
16352           suffix[1] = p[1];
16353           suffix[2] = '\0';
16354         }
16355
16356       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16357       mnemonicendp += simd_cmp_op[cmp_type].len;
16358     }
16359   else
16360     {
16361       /* We have a reserved extension byte.  Output it directly.  */
16362       scratchbuf[0] = '$';
16363       print_operand_value (scratchbuf + 1, 1, cmp_type);
16364       oappend_maybe_intel (scratchbuf);
16365       scratchbuf[0] = '\0';
16366     }
16367 }
16368
16369 static const struct op xop_cmp_op[] =
16370 {
16371   { STRING_COMMA_LEN ("lt") },
16372   { STRING_COMMA_LEN ("le") },
16373   { STRING_COMMA_LEN ("gt") },
16374   { STRING_COMMA_LEN ("ge") },
16375   { STRING_COMMA_LEN ("eq") },
16376   { STRING_COMMA_LEN ("neq") },
16377   { STRING_COMMA_LEN ("false") },
16378   { STRING_COMMA_LEN ("true") }
16379 };
16380
16381 static void
16382 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16383              int sizeflag ATTRIBUTE_UNUSED)
16384 {
16385   unsigned int cmp_type;
16386
16387   FETCH_DATA (the_info, codep + 1);
16388   cmp_type = *codep++ & 0xff;
16389   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16390     {
16391       char suffix[3];
16392       char *p = mnemonicendp - 2;
16393
16394       /* vpcom* can have both one- and two-lettered suffix.  */
16395       if (p[0] == 'm')
16396         {
16397           p++;
16398           suffix[0] = p[0];
16399           suffix[1] = '\0';
16400         }
16401       else
16402         {
16403           suffix[0] = p[0];
16404           suffix[1] = p[1];
16405           suffix[2] = '\0';
16406         }
16407
16408       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16409       mnemonicendp += xop_cmp_op[cmp_type].len;
16410     }
16411   else
16412     {
16413       /* We have a reserved extension byte.  Output it directly.  */
16414       scratchbuf[0] = '$';
16415       print_operand_value (scratchbuf + 1, 1, cmp_type);
16416       oappend_maybe_intel (scratchbuf);
16417       scratchbuf[0] = '\0';
16418     }
16419 }
16420
16421 static const struct op pclmul_op[] =
16422 {
16423   { STRING_COMMA_LEN ("lql") },
16424   { STRING_COMMA_LEN ("hql") },
16425   { STRING_COMMA_LEN ("lqh") },
16426   { STRING_COMMA_LEN ("hqh") }
16427 };
16428
16429 static void
16430 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16431               int sizeflag ATTRIBUTE_UNUSED)
16432 {
16433   unsigned int pclmul_type;
16434
16435   FETCH_DATA (the_info, codep + 1);
16436   pclmul_type = *codep++ & 0xff;
16437   switch (pclmul_type)
16438     {
16439     case 0x10:
16440       pclmul_type = 2;
16441       break;
16442     case 0x11:
16443       pclmul_type = 3;
16444       break;
16445     default:
16446       break;
16447     }
16448   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16449     {
16450       char suffix [4];
16451       char *p = mnemonicendp - 3;
16452       suffix[0] = p[0];
16453       suffix[1] = p[1];
16454       suffix[2] = p[2];
16455       suffix[3] = '\0';
16456       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16457       mnemonicendp += pclmul_op[pclmul_type].len;
16458     }
16459   else
16460     {
16461       /* We have a reserved extension byte.  Output it directly.  */
16462       scratchbuf[0] = '$';
16463       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16464       oappend_maybe_intel (scratchbuf);
16465       scratchbuf[0] = '\0';
16466     }
16467 }
16468
16469 static void
16470 MOVBE_Fixup (int bytemode, int sizeflag)
16471 {
16472   /* Add proper suffix to "movbe".  */
16473   char *p = mnemonicendp;
16474
16475   switch (bytemode)
16476     {
16477     case v_mode:
16478       if (intel_syntax)
16479         goto skip;
16480
16481       USED_REX (REX_W);
16482       if (sizeflag & SUFFIX_ALWAYS)
16483         {
16484           if (rex & REX_W)
16485             *p++ = 'q';
16486           else
16487             {
16488               if (sizeflag & DFLAG)
16489                 *p++ = 'l';
16490               else
16491                 *p++ = 'w';
16492               used_prefixes |= (prefixes & PREFIX_DATA);
16493             }
16494         }
16495       break;
16496     default:
16497       oappend (INTERNAL_DISASSEMBLER_ERROR);
16498       break;
16499     }
16500   mnemonicendp = p;
16501   *p = '\0';
16502
16503 skip:
16504   OP_M (bytemode, sizeflag);
16505 }
16506
16507 static void
16508 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16509 {
16510   int reg;
16511   const char **names;
16512
16513   /* Skip mod/rm byte.  */
16514   MODRM_CHECK;
16515   codep++;
16516
16517   if (rex & REX_W)
16518     names = names64;
16519   else
16520     names = names32;
16521
16522   reg = modrm.rm;
16523   USED_REX (REX_B);
16524   if (rex & REX_B)
16525     reg += 8;
16526
16527   oappend (names[reg]);
16528 }
16529
16530 static void
16531 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16532 {
16533   const char **names;
16534   unsigned int reg = vex.register_specifier;
16535   vex.register_specifier = 0;
16536
16537   if (rex & REX_W)
16538     names = names64;
16539   else
16540     names = names32;
16541
16542   if (address_mode != mode_64bit)
16543     reg &= 7;
16544   oappend (names[reg]);
16545 }
16546
16547 static void
16548 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16549 {
16550   if (!vex.evex
16551       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16552     abort ();
16553
16554   USED_REX (REX_R);
16555   if ((rex & REX_R) != 0 || !vex.r)
16556     {
16557       BadOp ();
16558       return;
16559     }
16560
16561   oappend (names_mask [modrm.reg]);
16562 }
16563
16564 static void
16565 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16566 {
16567   if (!vex.evex
16568       || (bytemode != evex_rounding_mode
16569           && bytemode != evex_rounding_64_mode
16570           && bytemode != evex_sae_mode))
16571     abort ();
16572   if (modrm.mod == 3 && vex.b)
16573     switch (bytemode)
16574       {
16575       case evex_rounding_64_mode:
16576         if (address_mode != mode_64bit)
16577           {
16578             oappend ("(bad)");
16579             break;
16580           }
16581         /* Fall through.  */
16582       case evex_rounding_mode:
16583         oappend (names_rounding[vex.ll]);
16584         break;
16585       case evex_sae_mode:
16586         oappend ("{sae}");
16587         break;
16588       default:
16589         break;
16590       }
16591 }