opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VCMP { VCMP_Fixup, 0 }
 438 #define VPCMP { VPCMP_Fixup, 0 }
 439 #define VPCOM { VPCOM_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476 #define NOTRACK { NOTRACK_Fixup, 0 }
 477
 478 #define cond_jump_flag { NULL, cond_jump_mode }
 479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 480
 481 /* bits in sizeflag */
 482 #define SUFFIX_ALWAYS 4
 483 #define AFLAG 2
 484 #define DFLAG 1
 485
 486 enum
 487 {
 488   /* byte operand */
 489   b_mode = 1,
 490   /* byte operand with operand swapped */
 491   b_swap_mode,
 492   /* byte operand, sign extend like 'T' suffix */
 493   b_T_mode,
 494   /* operand size depends on prefixes */
 495   v_mode,
 496   /* operand size depends on prefixes with operand swapped */
 497   v_swap_mode,
 498   /* operand size depends on address prefix */
 499   va_mode,
 500   /* word operand */
 501   w_mode,
 502   /* double word operand  */
 503   d_mode,
 504   /* double word operand with operand swapped */
 505   d_swap_mode,
 506   /* quad word operand */
 507   q_mode,
 508   /* quad word operand with operand swapped */
 509   q_swap_mode,
 510   /* ten-byte operand */
 511   t_mode,
 512   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 513      broadcast enabled.  */
 514   x_mode,
 515   /* Similar to x_mode, but with different EVEX mem shifts.  */
 516   evex_x_gscat_mode,
 517   /* Similar to x_mode, but with disabled broadcast.  */
 518   evex_x_nobcst_mode,
 519   /* Similar to x_mode, but with operands swapped and disabled broadcast
 520      in EVEX.  */
 521   x_swap_mode,
 522   /* 16-byte XMM operand */
 523   xmm_mode,
 524   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 525      memory operand (depending on vector length).  Broadcast isn't
 526      allowed.  */
 527   xmmq_mode,
 528   /* Same as xmmq_mode, but broadcast is allowed.  */
 529   evex_half_bcst_xmmq_mode,
 530   /* XMM register or byte memory operand */
 531   xmm_mb_mode,
 532   /* XMM register or word memory operand */
 533   xmm_mw_mode,
 534   /* XMM register or double word memory operand */
 535   xmm_md_mode,
 536   /* XMM register or quad word memory operand */
 537   xmm_mq_mode,
 538   /* XMM register or double/quad word memory operand, depending on
 539      VEX.W.  */
 540   xmm_mdq_mode,
 541   /* 16-byte XMM, word, double word or quad word operand.  */
 542   xmmdw_mode,
 543   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 544   xmmqd_mode,
 545   /* 32-byte YMM operand */
 546   ymm_mode,
 547   /* quad word, ymmword or zmmword memory operand.  */
 548   ymmq_mode,
 549   /* 32-byte YMM or 16-byte word operand */
 550   ymmxmm_mode,
 551   /* d_mode in 32bit, q_mode in 64bit mode.  */
 552   m_mode,
 553   /* pair of v_mode operands */
 554   a_mode,
 555   cond_jump_mode,
 556   loop_jcxz_mode,
 557   v_bnd_mode,
 558   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 559   v_bndmk_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593   /* operand size depends on the VEX.W bit.  */
 594   vex_w_dq_mode,
 595
 596   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 597   vex_vsib_d_w_dq_mode,
 598   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 599   vex_vsib_d_w_d_mode,
 600   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 601   vex_vsib_q_w_dq_mode,
 602   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 603   vex_vsib_q_w_d_mode,
 604
 605   /* scalar, ignore vector length.  */
 606   scalar_mode,
 607   /* like b_mode, ignore vector length.  */
 608   b_scalar_mode,
 609   /* like w_mode, ignore vector length.  */
 610   w_scalar_mode,
 611   /* like d_mode, ignore vector length.  */
 612   d_scalar_mode,
 613   /* like d_swap_mode, ignore vector length.  */
 614   d_scalar_swap_mode,
 615   /* like q_mode, ignore vector length.  */
 616   q_scalar_mode,
 617   /* like q_swap_mode, ignore vector length.  */
 618   q_scalar_swap_mode,
 619   /* like vex_mode, ignore vector length.  */
 620   vex_scalar_mode,
 621   /* like vex_w_dq_mode, ignore vector length.  */
 622   vex_scalar_w_dq_mode,
 623
 624   /* Static rounding.  */
 625   evex_rounding_mode,
 626   /* Static rounding, 64-bit mode only.  */
 627   evex_rounding_64_mode,
 628   /* Supress all exceptions.  */
 629   evex_sae_mode,
 630
 631   /* Mask register operand.  */
 632   mask_mode,
 633   /* Mask register operand.  */
 634   mask_bd_mode,
 635
 636   es_reg,
 637   cs_reg,
 638   ss_reg,
 639   ds_reg,
 640   fs_reg,
 641   gs_reg,
 642
 643   eAX_reg,
 644   eCX_reg,
 645   eDX_reg,
 646   eBX_reg,
 647   eSP_reg,
 648   eBP_reg,
 649   eSI_reg,
 650   eDI_reg,
 651
 652   al_reg,
 653   cl_reg,
 654   dl_reg,
 655   bl_reg,
 656   ah_reg,
 657   ch_reg,
 658   dh_reg,
 659   bh_reg,
 660
 661   ax_reg,
 662   cx_reg,
 663   dx_reg,
 664   bx_reg,
 665   sp_reg,
 666   bp_reg,
 667   si_reg,
 668   di_reg,
 669
 670   rAX_reg,
 671   rCX_reg,
 672   rDX_reg,
 673   rBX_reg,
 674   rSP_reg,
 675   rBP_reg,
 676   rSI_reg,
 677   rDI_reg,
 678
 679   z_mode_ax_reg,
 680   indir_dx_reg
 681 };
 682
 683 enum
 684 {
 685   FLOATCODE = 1,
 686   USE_REG_TABLE,
 687   USE_MOD_TABLE,
 688   USE_RM_TABLE,
 689   USE_PREFIX_TABLE,
 690   USE_X86_64_TABLE,
 691   USE_3BYTE_TABLE,
 692   USE_XOP_8F_TABLE,
 693   USE_VEX_C4_TABLE,
 694   USE_VEX_C5_TABLE,
 695   USE_VEX_LEN_TABLE,
 696   USE_VEX_W_TABLE,
 697   USE_EVEX_TABLE,
 698   USE_EVEX_LEN_TABLE
 699 };
 700
 701 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 702
 703 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 704 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 705 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 706 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 707 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 708 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 709 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 710 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 711 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 712 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 713 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 714 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 715 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 716 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 717 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 718 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 719
 720 enum
 721 {
 722   REG_80 = 0,
 723   REG_81,
 724   REG_83,
 725   REG_8F,
 726   REG_C0,
 727   REG_C1,
 728   REG_C6,
 729   REG_C7,
 730   REG_D0,
 731   REG_D1,
 732   REG_D2,
 733   REG_D3,
 734   REG_F6,
 735   REG_F7,
 736   REG_FE,
 737   REG_FF,
 738   REG_0F00,
 739   REG_0F01,
 740   REG_0F0D,
 741   REG_0F18,
 742   REG_0F1C_P_0_MOD_0,
 743   REG_0F1E_P_1_MOD_3,
 744   REG_0F71,
 745   REG_0F72,
 746   REG_0F73,
 747   REG_0FA6,
 748   REG_0FA7,
 749   REG_0FAE,
 750   REG_0FBA,
 751   REG_0FC7,
 752   REG_VEX_0F71,
 753   REG_VEX_0F72,
 754   REG_VEX_0F73,
 755   REG_VEX_0FAE,
 756   REG_VEX_0F38F3,
 757   REG_XOP_LWPCB,
 758   REG_XOP_LWP,
 759   REG_XOP_TBM_01,
 760   REG_XOP_TBM_02,
 761
 762   REG_EVEX_0F71,
 763   REG_EVEX_0F72,
 764   REG_EVEX_0F73,
 765   REG_EVEX_0F38C6,
 766   REG_EVEX_0F38C7
 767 };
 768
 769 enum
 770 {
 771   MOD_8D = 0,
 772   MOD_C6_REG_7,
 773   MOD_C7_REG_7,
 774   MOD_FF_REG_3,
 775   MOD_FF_REG_5,
 776   MOD_0F01_REG_0,
 777   MOD_0F01_REG_1,
 778   MOD_0F01_REG_2,
 779   MOD_0F01_REG_3,
 780   MOD_0F01_REG_5,
 781   MOD_0F01_REG_7,
 782   MOD_0F12_PREFIX_0,
 783   MOD_0F13,
 784   MOD_0F16_PREFIX_0,
 785   MOD_0F17,
 786   MOD_0F18_REG_0,
 787   MOD_0F18_REG_1,
 788   MOD_0F18_REG_2,
 789   MOD_0F18_REG_3,
 790   MOD_0F18_REG_4,
 791   MOD_0F18_REG_5,
 792   MOD_0F18_REG_6,
 793   MOD_0F18_REG_7,
 794   MOD_0F1A_PREFIX_0,
 795   MOD_0F1B_PREFIX_0,
 796   MOD_0F1B_PREFIX_1,
 797   MOD_0F1C_PREFIX_0,
 798   MOD_0F1E_PREFIX_1,
 799   MOD_0F24,
 800   MOD_0F26,
 801   MOD_0F2B_PREFIX_0,
 802   MOD_0F2B_PREFIX_1,
 803   MOD_0F2B_PREFIX_2,
 804   MOD_0F2B_PREFIX_3,
 805   MOD_0F51,
 806   MOD_0F71_REG_2,
 807   MOD_0F71_REG_4,
 808   MOD_0F71_REG_6,
 809   MOD_0F72_REG_2,
 810   MOD_0F72_REG_4,
 811   MOD_0F72_REG_6,
 812   MOD_0F73_REG_2,
 813   MOD_0F73_REG_3,
 814   MOD_0F73_REG_6,
 815   MOD_0F73_REG_7,
 816   MOD_0FAE_REG_0,
 817   MOD_0FAE_REG_1,
 818   MOD_0FAE_REG_2,
 819   MOD_0FAE_REG_3,
 820   MOD_0FAE_REG_4,
 821   MOD_0FAE_REG_5,
 822   MOD_0FAE_REG_6,
 823   MOD_0FAE_REG_7,
 824   MOD_0FB2,
 825   MOD_0FB4,
 826   MOD_0FB5,
 827   MOD_0FC3,
 828   MOD_0FC7_REG_3,
 829   MOD_0FC7_REG_4,
 830   MOD_0FC7_REG_5,
 831   MOD_0FC7_REG_6,
 832   MOD_0FC7_REG_7,
 833   MOD_0FD7,
 834   MOD_0FE7_PREFIX_2,
 835   MOD_0FF0_PREFIX_3,
 836   MOD_0F382A_PREFIX_2,
 837   MOD_0F38F5_PREFIX_2,
 838   MOD_0F38F6_PREFIX_0,
 839   MOD_0F38F8_PREFIX_1,
 840   MOD_0F38F8_PREFIX_2,
 841   MOD_0F38F8_PREFIX_3,
 842   MOD_0F38F9_PREFIX_0,
 843   MOD_62_32BIT,
 844   MOD_C4_32BIT,
 845   MOD_C5_32BIT,
 846   MOD_VEX_0F12_PREFIX_0,
 847   MOD_VEX_0F13,
 848   MOD_VEX_0F16_PREFIX_0,
 849   MOD_VEX_0F17,
 850   MOD_VEX_0F2B,
 851   MOD_VEX_W_0_0F41_P_0_LEN_1,
 852   MOD_VEX_W_1_0F41_P_0_LEN_1,
 853   MOD_VEX_W_0_0F41_P_2_LEN_1,
 854   MOD_VEX_W_1_0F41_P_2_LEN_1,
 855   MOD_VEX_W_0_0F42_P_0_LEN_1,
 856   MOD_VEX_W_1_0F42_P_0_LEN_1,
 857   MOD_VEX_W_0_0F42_P_2_LEN_1,
 858   MOD_VEX_W_1_0F42_P_2_LEN_1,
 859   MOD_VEX_W_0_0F44_P_0_LEN_1,
 860   MOD_VEX_W_1_0F44_P_0_LEN_1,
 861   MOD_VEX_W_0_0F44_P_2_LEN_1,
 862   MOD_VEX_W_1_0F44_P_2_LEN_1,
 863   MOD_VEX_W_0_0F45_P_0_LEN_1,
 864   MOD_VEX_W_1_0F45_P_0_LEN_1,
 865   MOD_VEX_W_0_0F45_P_2_LEN_1,
 866   MOD_VEX_W_1_0F45_P_2_LEN_1,
 867   MOD_VEX_W_0_0F46_P_0_LEN_1,
 868   MOD_VEX_W_1_0F46_P_0_LEN_1,
 869   MOD_VEX_W_0_0F46_P_2_LEN_1,
 870   MOD_VEX_W_1_0F46_P_2_LEN_1,
 871   MOD_VEX_W_0_0F47_P_0_LEN_1,
 872   MOD_VEX_W_1_0F47_P_0_LEN_1,
 873   MOD_VEX_W_0_0F47_P_2_LEN_1,
 874   MOD_VEX_W_1_0F47_P_2_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 878   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 880   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 882   MOD_VEX_0F50,
 883   MOD_VEX_0F71_REG_2,
 884   MOD_VEX_0F71_REG_4,
 885   MOD_VEX_0F71_REG_6,
 886   MOD_VEX_0F72_REG_2,
 887   MOD_VEX_0F72_REG_4,
 888   MOD_VEX_0F72_REG_6,
 889   MOD_VEX_0F73_REG_2,
 890   MOD_VEX_0F73_REG_3,
 891   MOD_VEX_0F73_REG_6,
 892   MOD_VEX_0F73_REG_7,
 893   MOD_VEX_W_0_0F91_P_0_LEN_0,
 894   MOD_VEX_W_1_0F91_P_0_LEN_0,
 895   MOD_VEX_W_0_0F91_P_2_LEN_0,
 896   MOD_VEX_W_1_0F91_P_2_LEN_0,
 897   MOD_VEX_W_0_0F92_P_0_LEN_0,
 898   MOD_VEX_W_0_0F92_P_2_LEN_0,
 899   MOD_VEX_0F92_P_3_LEN_0,
 900   MOD_VEX_W_0_0F93_P_0_LEN_0,
 901   MOD_VEX_W_0_0F93_P_2_LEN_0,
 902   MOD_VEX_0F93_P_3_LEN_0,
 903   MOD_VEX_W_0_0F98_P_0_LEN_0,
 904   MOD_VEX_W_1_0F98_P_0_LEN_0,
 905   MOD_VEX_W_0_0F98_P_2_LEN_0,
 906   MOD_VEX_W_1_0F98_P_2_LEN_0,
 907   MOD_VEX_W_0_0F99_P_0_LEN_0,
 908   MOD_VEX_W_1_0F99_P_0_LEN_0,
 909   MOD_VEX_W_0_0F99_P_2_LEN_0,
 910   MOD_VEX_W_1_0F99_P_2_LEN_0,
 911   MOD_VEX_0FAE_REG_2,
 912   MOD_VEX_0FAE_REG_3,
 913   MOD_VEX_0FD7_PREFIX_2,
 914   MOD_VEX_0FE7_PREFIX_2,
 915   MOD_VEX_0FF0_PREFIX_3,
 916   MOD_VEX_0F381A_PREFIX_2,
 917   MOD_VEX_0F382A_PREFIX_2,
 918   MOD_VEX_0F382C_PREFIX_2,
 919   MOD_VEX_0F382D_PREFIX_2,
 920   MOD_VEX_0F382E_PREFIX_2,
 921   MOD_VEX_0F382F_PREFIX_2,
 922   MOD_VEX_0F385A_PREFIX_2,
 923   MOD_VEX_0F388C_PREFIX_2,
 924   MOD_VEX_0F388E_PREFIX_2,
 925   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 931   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 933
 934   MOD_EVEX_0F12_PREFIX_0,
 935   MOD_EVEX_0F16_PREFIX_0,
 936   MOD_EVEX_0F38C6_REG_1,
 937   MOD_EVEX_0F38C6_REG_2,
 938   MOD_EVEX_0F38C6_REG_5,
 939   MOD_EVEX_0F38C6_REG_6,
 940   MOD_EVEX_0F38C7_REG_1,
 941   MOD_EVEX_0F38C7_REG_2,
 942   MOD_EVEX_0F38C7_REG_5,
 943   MOD_EVEX_0F38C7_REG_6
 944 };
 945
 946 enum
 947 {
 948   RM_C6_REG_7 = 0,
 949   RM_C7_REG_7,
 950   RM_0F01_REG_0,
 951   RM_0F01_REG_1,
 952   RM_0F01_REG_2,
 953   RM_0F01_REG_3,
 954   RM_0F01_REG_5_MOD_3,
 955   RM_0F01_REG_7_MOD_3,
 956   RM_0F1E_P_1_MOD_3_REG_7,
 957   RM_0FAE_REG_6_MOD_3_P_0,
 958   RM_0FAE_REG_7_MOD_3,
 959 };
 960
 961 enum
 962 {
 963   PREFIX_90 = 0,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_2,
 967   PREFIX_0F01_REG_7_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_3,
 969   PREFIX_0F09,
 970   PREFIX_0F10,
 971   PREFIX_0F11,
 972   PREFIX_0F12,
 973   PREFIX_0F16,
 974   PREFIX_0F1A,
 975   PREFIX_0F1B,
 976   PREFIX_0F1C,
 977   PREFIX_0F1E,
 978   PREFIX_0F2A,
 979   PREFIX_0F2B,
 980   PREFIX_0F2C,
 981   PREFIX_0F2D,
 982   PREFIX_0F2E,
 983   PREFIX_0F2F,
 984   PREFIX_0F51,
 985   PREFIX_0F52,
 986   PREFIX_0F53,
 987   PREFIX_0F58,
 988   PREFIX_0F59,
 989   PREFIX_0F5A,
 990   PREFIX_0F5B,
 991   PREFIX_0F5C,
 992   PREFIX_0F5D,
 993   PREFIX_0F5E,
 994   PREFIX_0F5F,
 995   PREFIX_0F60,
 996   PREFIX_0F61,
 997   PREFIX_0F62,
 998   PREFIX_0F6C,
 999   PREFIX_0F6D,
1000   PREFIX_0F6F,
1001   PREFIX_0F70,
1002   PREFIX_0F73_REG_3,
1003   PREFIX_0F73_REG_7,
1004   PREFIX_0F78,
1005   PREFIX_0F79,
1006   PREFIX_0F7C,
1007   PREFIX_0F7D,
1008   PREFIX_0F7E,
1009   PREFIX_0F7F,
1010   PREFIX_0FAE_REG_0_MOD_3,
1011   PREFIX_0FAE_REG_1_MOD_3,
1012   PREFIX_0FAE_REG_2_MOD_3,
1013   PREFIX_0FAE_REG_3_MOD_3,
1014   PREFIX_0FAE_REG_4_MOD_0,
1015   PREFIX_0FAE_REG_4_MOD_3,
1016   PREFIX_0FAE_REG_5_MOD_0,
1017   PREFIX_0FAE_REG_5_MOD_3,
1018   PREFIX_0FAE_REG_6_MOD_0,
1019   PREFIX_0FAE_REG_6_MOD_3,
1020   PREFIX_0FAE_REG_7_MOD_0,
1021   PREFIX_0FB8,
1022   PREFIX_0FBC,
1023   PREFIX_0FBD,
1024   PREFIX_0FC2,
1025   PREFIX_0FC3_MOD_0,
1026   PREFIX_0FC7_REG_6_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_3,
1028   PREFIX_0FC7_REG_7_MOD_3,
1029   PREFIX_0FD0,
1030   PREFIX_0FD6,
1031   PREFIX_0FE6,
1032   PREFIX_0FE7,
1033   PREFIX_0FF0,
1034   PREFIX_0FF7,
1035   PREFIX_0F3810,
1036   PREFIX_0F3814,
1037   PREFIX_0F3815,
1038   PREFIX_0F3817,
1039   PREFIX_0F3820,
1040   PREFIX_0F3821,
1041   PREFIX_0F3822,
1042   PREFIX_0F3823,
1043   PREFIX_0F3824,
1044   PREFIX_0F3825,
1045   PREFIX_0F3828,
1046   PREFIX_0F3829,
1047   PREFIX_0F382A,
1048   PREFIX_0F382B,
1049   PREFIX_0F3830,
1050   PREFIX_0F3831,
1051   PREFIX_0F3832,
1052   PREFIX_0F3833,
1053   PREFIX_0F3834,
1054   PREFIX_0F3835,
1055   PREFIX_0F3837,
1056   PREFIX_0F3838,
1057   PREFIX_0F3839,
1058   PREFIX_0F383A,
1059   PREFIX_0F383B,
1060   PREFIX_0F383C,
1061   PREFIX_0F383D,
1062   PREFIX_0F383E,
1063   PREFIX_0F383F,
1064   PREFIX_0F3840,
1065   PREFIX_0F3841,
1066   PREFIX_0F3880,
1067   PREFIX_0F3881,
1068   PREFIX_0F3882,
1069   PREFIX_0F38C8,
1070   PREFIX_0F38C9,
1071   PREFIX_0F38CA,
1072   PREFIX_0F38CB,
1073   PREFIX_0F38CC,
1074   PREFIX_0F38CD,
1075   PREFIX_0F38CF,
1076   PREFIX_0F38DB,
1077   PREFIX_0F38DC,
1078   PREFIX_0F38DD,
1079   PREFIX_0F38DE,
1080   PREFIX_0F38DF,
1081   PREFIX_0F38F0,
1082   PREFIX_0F38F1,
1083   PREFIX_0F38F5,
1084   PREFIX_0F38F6,
1085   PREFIX_0F38F8,
1086   PREFIX_0F38F9,
1087   PREFIX_0F3A08,
1088   PREFIX_0F3A09,
1089   PREFIX_0F3A0A,
1090   PREFIX_0F3A0B,
1091   PREFIX_0F3A0C,
1092   PREFIX_0F3A0D,
1093   PREFIX_0F3A0E,
1094   PREFIX_0F3A14,
1095   PREFIX_0F3A15,
1096   PREFIX_0F3A16,
1097   PREFIX_0F3A17,
1098   PREFIX_0F3A20,
1099   PREFIX_0F3A21,
1100   PREFIX_0F3A22,
1101   PREFIX_0F3A40,
1102   PREFIX_0F3A41,
1103   PREFIX_0F3A42,
1104   PREFIX_0F3A44,
1105   PREFIX_0F3A60,
1106   PREFIX_0F3A61,
1107   PREFIX_0F3A62,
1108   PREFIX_0F3A63,
1109   PREFIX_0F3ACC,
1110   PREFIX_0F3ACE,
1111   PREFIX_0F3ACF,
1112   PREFIX_0F3ADF,
1113   PREFIX_VEX_0F10,
1114   PREFIX_VEX_0F11,
1115   PREFIX_VEX_0F12,
1116   PREFIX_VEX_0F16,
1117   PREFIX_VEX_0F2A,
1118   PREFIX_VEX_0F2C,
1119   PREFIX_VEX_0F2D,
1120   PREFIX_VEX_0F2E,
1121   PREFIX_VEX_0F2F,
1122   PREFIX_VEX_0F41,
1123   PREFIX_VEX_0F42,
1124   PREFIX_VEX_0F44,
1125   PREFIX_VEX_0F45,
1126   PREFIX_VEX_0F46,
1127   PREFIX_VEX_0F47,
1128   PREFIX_VEX_0F4A,
1129   PREFIX_VEX_0F4B,
1130   PREFIX_VEX_0F51,
1131   PREFIX_VEX_0F52,
1132   PREFIX_VEX_0F53,
1133   PREFIX_VEX_0F58,
1134   PREFIX_VEX_0F59,
1135   PREFIX_VEX_0F5A,
1136   PREFIX_VEX_0F5B,
1137   PREFIX_VEX_0F5C,
1138   PREFIX_VEX_0F5D,
1139   PREFIX_VEX_0F5E,
1140   PREFIX_VEX_0F5F,
1141   PREFIX_VEX_0F60,
1142   PREFIX_VEX_0F61,
1143   PREFIX_VEX_0F62,
1144   PREFIX_VEX_0F63,
1145   PREFIX_VEX_0F64,
1146   PREFIX_VEX_0F65,
1147   PREFIX_VEX_0F66,
1148   PREFIX_VEX_0F67,
1149   PREFIX_VEX_0F68,
1150   PREFIX_VEX_0F69,
1151   PREFIX_VEX_0F6A,
1152   PREFIX_VEX_0F6B,
1153   PREFIX_VEX_0F6C,
1154   PREFIX_VEX_0F6D,
1155   PREFIX_VEX_0F6E,
1156   PREFIX_VEX_0F6F,
1157   PREFIX_VEX_0F70,
1158   PREFIX_VEX_0F71_REG_2,
1159   PREFIX_VEX_0F71_REG_4,
1160   PREFIX_VEX_0F71_REG_6,
1161   PREFIX_VEX_0F72_REG_2,
1162   PREFIX_VEX_0F72_REG_4,
1163   PREFIX_VEX_0F72_REG_6,
1164   PREFIX_VEX_0F73_REG_2,
1165   PREFIX_VEX_0F73_REG_3,
1166   PREFIX_VEX_0F73_REG_6,
1167   PREFIX_VEX_0F73_REG_7,
1168   PREFIX_VEX_0F74,
1169   PREFIX_VEX_0F75,
1170   PREFIX_VEX_0F76,
1171   PREFIX_VEX_0F77,
1172   PREFIX_VEX_0F7C,
1173   PREFIX_VEX_0F7D,
1174   PREFIX_VEX_0F7E,
1175   PREFIX_VEX_0F7F,
1176   PREFIX_VEX_0F90,
1177   PREFIX_VEX_0F91,
1178   PREFIX_VEX_0F92,
1179   PREFIX_VEX_0F93,
1180   PREFIX_VEX_0F98,
1181   PREFIX_VEX_0F99,
1182   PREFIX_VEX_0FC2,
1183   PREFIX_VEX_0FC4,
1184   PREFIX_VEX_0FC5,
1185   PREFIX_VEX_0FD0,
1186   PREFIX_VEX_0FD1,
1187   PREFIX_VEX_0FD2,
1188   PREFIX_VEX_0FD3,
1189   PREFIX_VEX_0FD4,
1190   PREFIX_VEX_0FD5,
1191   PREFIX_VEX_0FD6,
1192   PREFIX_VEX_0FD7,
1193   PREFIX_VEX_0FD8,
1194   PREFIX_VEX_0FD9,
1195   PREFIX_VEX_0FDA,
1196   PREFIX_VEX_0FDB,
1197   PREFIX_VEX_0FDC,
1198   PREFIX_VEX_0FDD,
1199   PREFIX_VEX_0FDE,
1200   PREFIX_VEX_0FDF,
1201   PREFIX_VEX_0FE0,
1202   PREFIX_VEX_0FE1,
1203   PREFIX_VEX_0FE2,
1204   PREFIX_VEX_0FE3,
1205   PREFIX_VEX_0FE4,
1206   PREFIX_VEX_0FE5,
1207   PREFIX_VEX_0FE6,
1208   PREFIX_VEX_0FE7,
1209   PREFIX_VEX_0FE8,
1210   PREFIX_VEX_0FE9,
1211   PREFIX_VEX_0FEA,
1212   PREFIX_VEX_0FEB,
1213   PREFIX_VEX_0FEC,
1214   PREFIX_VEX_0FED,
1215   PREFIX_VEX_0FEE,
1216   PREFIX_VEX_0FEF,
1217   PREFIX_VEX_0FF0,
1218   PREFIX_VEX_0FF1,
1219   PREFIX_VEX_0FF2,
1220   PREFIX_VEX_0FF3,
1221   PREFIX_VEX_0FF4,
1222   PREFIX_VEX_0FF5,
1223   PREFIX_VEX_0FF6,
1224   PREFIX_VEX_0FF7,
1225   PREFIX_VEX_0FF8,
1226   PREFIX_VEX_0FF9,
1227   PREFIX_VEX_0FFA,
1228   PREFIX_VEX_0FFB,
1229   PREFIX_VEX_0FFC,
1230   PREFIX_VEX_0FFD,
1231   PREFIX_VEX_0FFE,
1232   PREFIX_VEX_0F3800,
1233   PREFIX_VEX_0F3801,
1234   PREFIX_VEX_0F3802,
1235   PREFIX_VEX_0F3803,
1236   PREFIX_VEX_0F3804,
1237   PREFIX_VEX_0F3805,
1238   PREFIX_VEX_0F3806,
1239   PREFIX_VEX_0F3807,
1240   PREFIX_VEX_0F3808,
1241   PREFIX_VEX_0F3809,
1242   PREFIX_VEX_0F380A,
1243   PREFIX_VEX_0F380B,
1244   PREFIX_VEX_0F380C,
1245   PREFIX_VEX_0F380D,
1246   PREFIX_VEX_0F380E,
1247   PREFIX_VEX_0F380F,
1248   PREFIX_VEX_0F3813,
1249   PREFIX_VEX_0F3816,
1250   PREFIX_VEX_0F3817,
1251   PREFIX_VEX_0F3818,
1252   PREFIX_VEX_0F3819,
1253   PREFIX_VEX_0F381A,
1254   PREFIX_VEX_0F381C,
1255   PREFIX_VEX_0F381D,
1256   PREFIX_VEX_0F381E,
1257   PREFIX_VEX_0F3820,
1258   PREFIX_VEX_0F3821,
1259   PREFIX_VEX_0F3822,
1260   PREFIX_VEX_0F3823,
1261   PREFIX_VEX_0F3824,
1262   PREFIX_VEX_0F3825,
1263   PREFIX_VEX_0F3828,
1264   PREFIX_VEX_0F3829,
1265   PREFIX_VEX_0F382A,
1266   PREFIX_VEX_0F382B,
1267   PREFIX_VEX_0F382C,
1268   PREFIX_VEX_0F382D,
1269   PREFIX_VEX_0F382E,
1270   PREFIX_VEX_0F382F,
1271   PREFIX_VEX_0F3830,
1272   PREFIX_VEX_0F3831,
1273   PREFIX_VEX_0F3832,
1274   PREFIX_VEX_0F3833,
1275   PREFIX_VEX_0F3834,
1276   PREFIX_VEX_0F3835,
1277   PREFIX_VEX_0F3836,
1278   PREFIX_VEX_0F3837,
1279   PREFIX_VEX_0F3838,
1280   PREFIX_VEX_0F3839,
1281   PREFIX_VEX_0F383A,
1282   PREFIX_VEX_0F383B,
1283   PREFIX_VEX_0F383C,
1284   PREFIX_VEX_0F383D,
1285   PREFIX_VEX_0F383E,
1286   PREFIX_VEX_0F383F,
1287   PREFIX_VEX_0F3840,
1288   PREFIX_VEX_0F3841,
1289   PREFIX_VEX_0F3845,
1290   PREFIX_VEX_0F3846,
1291   PREFIX_VEX_0F3847,
1292   PREFIX_VEX_0F3858,
1293   PREFIX_VEX_0F3859,
1294   PREFIX_VEX_0F385A,
1295   PREFIX_VEX_0F3878,
1296   PREFIX_VEX_0F3879,
1297   PREFIX_VEX_0F388C,
1298   PREFIX_VEX_0F388E,
1299   PREFIX_VEX_0F3890,
1300   PREFIX_VEX_0F3891,
1301   PREFIX_VEX_0F3892,
1302   PREFIX_VEX_0F3893,
1303   PREFIX_VEX_0F3896,
1304   PREFIX_VEX_0F3897,
1305   PREFIX_VEX_0F3898,
1306   PREFIX_VEX_0F3899,
1307   PREFIX_VEX_0F389A,
1308   PREFIX_VEX_0F389B,
1309   PREFIX_VEX_0F389C,
1310   PREFIX_VEX_0F389D,
1311   PREFIX_VEX_0F389E,
1312   PREFIX_VEX_0F389F,
1313   PREFIX_VEX_0F38A6,
1314   PREFIX_VEX_0F38A7,
1315   PREFIX_VEX_0F38A8,
1316   PREFIX_VEX_0F38A9,
1317   PREFIX_VEX_0F38AA,
1318   PREFIX_VEX_0F38AB,
1319   PREFIX_VEX_0F38AC,
1320   PREFIX_VEX_0F38AD,
1321   PREFIX_VEX_0F38AE,
1322   PREFIX_VEX_0F38AF,
1323   PREFIX_VEX_0F38B6,
1324   PREFIX_VEX_0F38B7,
1325   PREFIX_VEX_0F38B8,
1326   PREFIX_VEX_0F38B9,
1327   PREFIX_VEX_0F38BA,
1328   PREFIX_VEX_0F38BB,
1329   PREFIX_VEX_0F38BC,
1330   PREFIX_VEX_0F38BD,
1331   PREFIX_VEX_0F38BE,
1332   PREFIX_VEX_0F38BF,
1333   PREFIX_VEX_0F38CF,
1334   PREFIX_VEX_0F38DB,
1335   PREFIX_VEX_0F38DC,
1336   PREFIX_VEX_0F38DD,
1337   PREFIX_VEX_0F38DE,
1338   PREFIX_VEX_0F38DF,
1339   PREFIX_VEX_0F38F2,
1340   PREFIX_VEX_0F38F3_REG_1,
1341   PREFIX_VEX_0F38F3_REG_2,
1342   PREFIX_VEX_0F38F3_REG_3,
1343   PREFIX_VEX_0F38F5,
1344   PREFIX_VEX_0F38F6,
1345   PREFIX_VEX_0F38F7,
1346   PREFIX_VEX_0F3A00,
1347   PREFIX_VEX_0F3A01,
1348   PREFIX_VEX_0F3A02,
1349   PREFIX_VEX_0F3A04,
1350   PREFIX_VEX_0F3A05,
1351   PREFIX_VEX_0F3A06,
1352   PREFIX_VEX_0F3A08,
1353   PREFIX_VEX_0F3A09,
1354   PREFIX_VEX_0F3A0A,
1355   PREFIX_VEX_0F3A0B,
1356   PREFIX_VEX_0F3A0C,
1357   PREFIX_VEX_0F3A0D,
1358   PREFIX_VEX_0F3A0E,
1359   PREFIX_VEX_0F3A0F,
1360   PREFIX_VEX_0F3A14,
1361   PREFIX_VEX_0F3A15,
1362   PREFIX_VEX_0F3A16,
1363   PREFIX_VEX_0F3A17,
1364   PREFIX_VEX_0F3A18,
1365   PREFIX_VEX_0F3A19,
1366   PREFIX_VEX_0F3A1D,
1367   PREFIX_VEX_0F3A20,
1368   PREFIX_VEX_0F3A21,
1369   PREFIX_VEX_0F3A22,
1370   PREFIX_VEX_0F3A30,
1371   PREFIX_VEX_0F3A31,
1372   PREFIX_VEX_0F3A32,
1373   PREFIX_VEX_0F3A33,
1374   PREFIX_VEX_0F3A38,
1375   PREFIX_VEX_0F3A39,
1376   PREFIX_VEX_0F3A40,
1377   PREFIX_VEX_0F3A41,
1378   PREFIX_VEX_0F3A42,
1379   PREFIX_VEX_0F3A44,
1380   PREFIX_VEX_0F3A46,
1381   PREFIX_VEX_0F3A48,
1382   PREFIX_VEX_0F3A49,
1383   PREFIX_VEX_0F3A4A,
1384   PREFIX_VEX_0F3A4B,
1385   PREFIX_VEX_0F3A4C,
1386   PREFIX_VEX_0F3A5C,
1387   PREFIX_VEX_0F3A5D,
1388   PREFIX_VEX_0F3A5E,
1389   PREFIX_VEX_0F3A5F,
1390   PREFIX_VEX_0F3A60,
1391   PREFIX_VEX_0F3A61,
1392   PREFIX_VEX_0F3A62,
1393   PREFIX_VEX_0F3A63,
1394   PREFIX_VEX_0F3A68,
1395   PREFIX_VEX_0F3A69,
1396   PREFIX_VEX_0F3A6A,
1397   PREFIX_VEX_0F3A6B,
1398   PREFIX_VEX_0F3A6C,
1399   PREFIX_VEX_0F3A6D,
1400   PREFIX_VEX_0F3A6E,
1401   PREFIX_VEX_0F3A6F,
1402   PREFIX_VEX_0F3A78,
1403   PREFIX_VEX_0F3A79,
1404   PREFIX_VEX_0F3A7A,
1405   PREFIX_VEX_0F3A7B,
1406   PREFIX_VEX_0F3A7C,
1407   PREFIX_VEX_0F3A7D,
1408   PREFIX_VEX_0F3A7E,
1409   PREFIX_VEX_0F3A7F,
1410   PREFIX_VEX_0F3ACE,
1411   PREFIX_VEX_0F3ACF,
1412   PREFIX_VEX_0F3ADF,
1413   PREFIX_VEX_0F3AF0,
1414
1415   PREFIX_EVEX_0F10,
1416   PREFIX_EVEX_0F11,
1417   PREFIX_EVEX_0F12,
1418   PREFIX_EVEX_0F13,
1419   PREFIX_EVEX_0F14,
1420   PREFIX_EVEX_0F15,
1421   PREFIX_EVEX_0F16,
1422   PREFIX_EVEX_0F17,
1423   PREFIX_EVEX_0F28,
1424   PREFIX_EVEX_0F29,
1425   PREFIX_EVEX_0F2A,
1426   PREFIX_EVEX_0F2B,
1427   PREFIX_EVEX_0F2C,
1428   PREFIX_EVEX_0F2D,
1429   PREFIX_EVEX_0F2E,
1430   PREFIX_EVEX_0F2F,
1431   PREFIX_EVEX_0F51,
1432   PREFIX_EVEX_0F54,
1433   PREFIX_EVEX_0F55,
1434   PREFIX_EVEX_0F56,
1435   PREFIX_EVEX_0F57,
1436   PREFIX_EVEX_0F58,
1437   PREFIX_EVEX_0F59,
1438   PREFIX_EVEX_0F5A,
1439   PREFIX_EVEX_0F5B,
1440   PREFIX_EVEX_0F5C,
1441   PREFIX_EVEX_0F5D,
1442   PREFIX_EVEX_0F5E,
1443   PREFIX_EVEX_0F5F,
1444   PREFIX_EVEX_0F60,
1445   PREFIX_EVEX_0F61,
1446   PREFIX_EVEX_0F62,
1447   PREFIX_EVEX_0F63,
1448   PREFIX_EVEX_0F64,
1449   PREFIX_EVEX_0F65,
1450   PREFIX_EVEX_0F66,
1451   PREFIX_EVEX_0F67,
1452   PREFIX_EVEX_0F68,
1453   PREFIX_EVEX_0F69,
1454   PREFIX_EVEX_0F6A,
1455   PREFIX_EVEX_0F6B,
1456   PREFIX_EVEX_0F6C,
1457   PREFIX_EVEX_0F6D,
1458   PREFIX_EVEX_0F6E,
1459   PREFIX_EVEX_0F6F,
1460   PREFIX_EVEX_0F70,
1461   PREFIX_EVEX_0F71_REG_2,
1462   PREFIX_EVEX_0F71_REG_4,
1463   PREFIX_EVEX_0F71_REG_6,
1464   PREFIX_EVEX_0F72_REG_0,
1465   PREFIX_EVEX_0F72_REG_1,
1466   PREFIX_EVEX_0F72_REG_2,
1467   PREFIX_EVEX_0F72_REG_4,
1468   PREFIX_EVEX_0F72_REG_6,
1469   PREFIX_EVEX_0F73_REG_2,
1470   PREFIX_EVEX_0F73_REG_3,
1471   PREFIX_EVEX_0F73_REG_6,
1472   PREFIX_EVEX_0F73_REG_7,
1473   PREFIX_EVEX_0F74,
1474   PREFIX_EVEX_0F75,
1475   PREFIX_EVEX_0F76,
1476   PREFIX_EVEX_0F78,
1477   PREFIX_EVEX_0F79,
1478   PREFIX_EVEX_0F7A,
1479   PREFIX_EVEX_0F7B,
1480   PREFIX_EVEX_0F7E,
1481   PREFIX_EVEX_0F7F,
1482   PREFIX_EVEX_0FC2,
1483   PREFIX_EVEX_0FC4,
1484   PREFIX_EVEX_0FC5,
1485   PREFIX_EVEX_0FC6,
1486   PREFIX_EVEX_0FD1,
1487   PREFIX_EVEX_0FD2,
1488   PREFIX_EVEX_0FD3,
1489   PREFIX_EVEX_0FD4,
1490   PREFIX_EVEX_0FD5,
1491   PREFIX_EVEX_0FD6,
1492   PREFIX_EVEX_0FD8,
1493   PREFIX_EVEX_0FD9,
1494   PREFIX_EVEX_0FDA,
1495   PREFIX_EVEX_0FDB,
1496   PREFIX_EVEX_0FDC,
1497   PREFIX_EVEX_0FDD,
1498   PREFIX_EVEX_0FDE,
1499   PREFIX_EVEX_0FDF,
1500   PREFIX_EVEX_0FE0,
1501   PREFIX_EVEX_0FE1,
1502   PREFIX_EVEX_0FE2,
1503   PREFIX_EVEX_0FE3,
1504   PREFIX_EVEX_0FE4,
1505   PREFIX_EVEX_0FE5,
1506   PREFIX_EVEX_0FE6,
1507   PREFIX_EVEX_0FE7,
1508   PREFIX_EVEX_0FE8,
1509   PREFIX_EVEX_0FE9,
1510   PREFIX_EVEX_0FEA,
1511   PREFIX_EVEX_0FEB,
1512   PREFIX_EVEX_0FEC,
1513   PREFIX_EVEX_0FED,
1514   PREFIX_EVEX_0FEE,
1515   PREFIX_EVEX_0FEF,
1516   PREFIX_EVEX_0FF1,
1517   PREFIX_EVEX_0FF2,
1518   PREFIX_EVEX_0FF3,
1519   PREFIX_EVEX_0FF4,
1520   PREFIX_EVEX_0FF5,
1521   PREFIX_EVEX_0FF6,
1522   PREFIX_EVEX_0FF8,
1523   PREFIX_EVEX_0FF9,
1524   PREFIX_EVEX_0FFA,
1525   PREFIX_EVEX_0FFB,
1526   PREFIX_EVEX_0FFC,
1527   PREFIX_EVEX_0FFD,
1528   PREFIX_EVEX_0FFE,
1529   PREFIX_EVEX_0F3800,
1530   PREFIX_EVEX_0F3804,
1531   PREFIX_EVEX_0F380B,
1532   PREFIX_EVEX_0F380C,
1533   PREFIX_EVEX_0F380D,
1534   PREFIX_EVEX_0F3810,
1535   PREFIX_EVEX_0F3811,
1536   PREFIX_EVEX_0F3812,
1537   PREFIX_EVEX_0F3813,
1538   PREFIX_EVEX_0F3814,
1539   PREFIX_EVEX_0F3815,
1540   PREFIX_EVEX_0F3816,
1541   PREFIX_EVEX_0F3818,
1542   PREFIX_EVEX_0F3819,
1543   PREFIX_EVEX_0F381A,
1544   PREFIX_EVEX_0F381B,
1545   PREFIX_EVEX_0F381C,
1546   PREFIX_EVEX_0F381D,
1547   PREFIX_EVEX_0F381E,
1548   PREFIX_EVEX_0F381F,
1549   PREFIX_EVEX_0F3820,
1550   PREFIX_EVEX_0F3821,
1551   PREFIX_EVEX_0F3822,
1552   PREFIX_EVEX_0F3823,
1553   PREFIX_EVEX_0F3824,
1554   PREFIX_EVEX_0F3825,
1555   PREFIX_EVEX_0F3826,
1556   PREFIX_EVEX_0F3827,
1557   PREFIX_EVEX_0F3828,
1558   PREFIX_EVEX_0F3829,
1559   PREFIX_EVEX_0F382A,
1560   PREFIX_EVEX_0F382B,
1561   PREFIX_EVEX_0F382C,
1562   PREFIX_EVEX_0F382D,
1563   PREFIX_EVEX_0F3830,
1564   PREFIX_EVEX_0F3831,
1565   PREFIX_EVEX_0F3832,
1566   PREFIX_EVEX_0F3833,
1567   PREFIX_EVEX_0F3834,
1568   PREFIX_EVEX_0F3835,
1569   PREFIX_EVEX_0F3836,
1570   PREFIX_EVEX_0F3837,
1571   PREFIX_EVEX_0F3838,
1572   PREFIX_EVEX_0F3839,
1573   PREFIX_EVEX_0F383A,
1574   PREFIX_EVEX_0F383B,
1575   PREFIX_EVEX_0F383C,
1576   PREFIX_EVEX_0F383D,
1577   PREFIX_EVEX_0F383E,
1578   PREFIX_EVEX_0F383F,
1579   PREFIX_EVEX_0F3840,
1580   PREFIX_EVEX_0F3842,
1581   PREFIX_EVEX_0F3843,
1582   PREFIX_EVEX_0F3844,
1583   PREFIX_EVEX_0F3845,
1584   PREFIX_EVEX_0F3846,
1585   PREFIX_EVEX_0F3847,
1586   PREFIX_EVEX_0F384C,
1587   PREFIX_EVEX_0F384D,
1588   PREFIX_EVEX_0F384E,
1589   PREFIX_EVEX_0F384F,
1590   PREFIX_EVEX_0F3850,
1591   PREFIX_EVEX_0F3851,
1592   PREFIX_EVEX_0F3852,
1593   PREFIX_EVEX_0F3853,
1594   PREFIX_EVEX_0F3854,
1595   PREFIX_EVEX_0F3855,
1596   PREFIX_EVEX_0F3858,
1597   PREFIX_EVEX_0F3859,
1598   PREFIX_EVEX_0F385A,
1599   PREFIX_EVEX_0F385B,
1600   PREFIX_EVEX_0F3862,
1601   PREFIX_EVEX_0F3863,
1602   PREFIX_EVEX_0F3864,
1603   PREFIX_EVEX_0F3865,
1604   PREFIX_EVEX_0F3866,
1605   PREFIX_EVEX_0F3868,
1606   PREFIX_EVEX_0F3870,
1607   PREFIX_EVEX_0F3871,
1608   PREFIX_EVEX_0F3872,
1609   PREFIX_EVEX_0F3873,
1610   PREFIX_EVEX_0F3875,
1611   PREFIX_EVEX_0F3876,
1612   PREFIX_EVEX_0F3877,
1613   PREFIX_EVEX_0F3878,
1614   PREFIX_EVEX_0F3879,
1615   PREFIX_EVEX_0F387A,
1616   PREFIX_EVEX_0F387B,
1617   PREFIX_EVEX_0F387C,
1618   PREFIX_EVEX_0F387D,
1619   PREFIX_EVEX_0F387E,
1620   PREFIX_EVEX_0F387F,
1621   PREFIX_EVEX_0F3883,
1622   PREFIX_EVEX_0F3888,
1623   PREFIX_EVEX_0F3889,
1624   PREFIX_EVEX_0F388A,
1625   PREFIX_EVEX_0F388B,
1626   PREFIX_EVEX_0F388D,
1627   PREFIX_EVEX_0F388F,
1628   PREFIX_EVEX_0F3890,
1629   PREFIX_EVEX_0F3891,
1630   PREFIX_EVEX_0F3892,
1631   PREFIX_EVEX_0F3893,
1632   PREFIX_EVEX_0F3896,
1633   PREFIX_EVEX_0F3897,
1634   PREFIX_EVEX_0F3898,
1635   PREFIX_EVEX_0F3899,
1636   PREFIX_EVEX_0F389A,
1637   PREFIX_EVEX_0F389B,
1638   PREFIX_EVEX_0F389C,
1639   PREFIX_EVEX_0F389D,
1640   PREFIX_EVEX_0F389E,
1641   PREFIX_EVEX_0F389F,
1642   PREFIX_EVEX_0F38A0,
1643   PREFIX_EVEX_0F38A1,
1644   PREFIX_EVEX_0F38A2,
1645   PREFIX_EVEX_0F38A3,
1646   PREFIX_EVEX_0F38A6,
1647   PREFIX_EVEX_0F38A7,
1648   PREFIX_EVEX_0F38A8,
1649   PREFIX_EVEX_0F38A9,
1650   PREFIX_EVEX_0F38AA,
1651   PREFIX_EVEX_0F38AB,
1652   PREFIX_EVEX_0F38AC,
1653   PREFIX_EVEX_0F38AD,
1654   PREFIX_EVEX_0F38AE,
1655   PREFIX_EVEX_0F38AF,
1656   PREFIX_EVEX_0F38B4,
1657   PREFIX_EVEX_0F38B5,
1658   PREFIX_EVEX_0F38B6,
1659   PREFIX_EVEX_0F38B7,
1660   PREFIX_EVEX_0F38B8,
1661   PREFIX_EVEX_0F38B9,
1662   PREFIX_EVEX_0F38BA,
1663   PREFIX_EVEX_0F38BB,
1664   PREFIX_EVEX_0F38BC,
1665   PREFIX_EVEX_0F38BD,
1666   PREFIX_EVEX_0F38BE,
1667   PREFIX_EVEX_0F38BF,
1668   PREFIX_EVEX_0F38C4,
1669   PREFIX_EVEX_0F38C6_REG_1,
1670   PREFIX_EVEX_0F38C6_REG_2,
1671   PREFIX_EVEX_0F38C6_REG_5,
1672   PREFIX_EVEX_0F38C6_REG_6,
1673   PREFIX_EVEX_0F38C7_REG_1,
1674   PREFIX_EVEX_0F38C7_REG_2,
1675   PREFIX_EVEX_0F38C7_REG_5,
1676   PREFIX_EVEX_0F38C7_REG_6,
1677   PREFIX_EVEX_0F38C8,
1678   PREFIX_EVEX_0F38CA,
1679   PREFIX_EVEX_0F38CB,
1680   PREFIX_EVEX_0F38CC,
1681   PREFIX_EVEX_0F38CD,
1682   PREFIX_EVEX_0F38CF,
1683   PREFIX_EVEX_0F38DC,
1684   PREFIX_EVEX_0F38DD,
1685   PREFIX_EVEX_0F38DE,
1686   PREFIX_EVEX_0F38DF,
1687
1688   PREFIX_EVEX_0F3A00,
1689   PREFIX_EVEX_0F3A01,
1690   PREFIX_EVEX_0F3A03,
1691   PREFIX_EVEX_0F3A04,
1692   PREFIX_EVEX_0F3A05,
1693   PREFIX_EVEX_0F3A08,
1694   PREFIX_EVEX_0F3A09,
1695   PREFIX_EVEX_0F3A0A,
1696   PREFIX_EVEX_0F3A0B,
1697   PREFIX_EVEX_0F3A0F,
1698   PREFIX_EVEX_0F3A14,
1699   PREFIX_EVEX_0F3A15,
1700   PREFIX_EVEX_0F3A16,
1701   PREFIX_EVEX_0F3A17,
1702   PREFIX_EVEX_0F3A18,
1703   PREFIX_EVEX_0F3A19,
1704   PREFIX_EVEX_0F3A1A,
1705   PREFIX_EVEX_0F3A1B,
1706   PREFIX_EVEX_0F3A1D,
1707   PREFIX_EVEX_0F3A1E,
1708   PREFIX_EVEX_0F3A1F,
1709   PREFIX_EVEX_0F3A20,
1710   PREFIX_EVEX_0F3A21,
1711   PREFIX_EVEX_0F3A22,
1712   PREFIX_EVEX_0F3A23,
1713   PREFIX_EVEX_0F3A25,
1714   PREFIX_EVEX_0F3A26,
1715   PREFIX_EVEX_0F3A27,
1716   PREFIX_EVEX_0F3A38,
1717   PREFIX_EVEX_0F3A39,
1718   PREFIX_EVEX_0F3A3A,
1719   PREFIX_EVEX_0F3A3B,
1720   PREFIX_EVEX_0F3A3E,
1721   PREFIX_EVEX_0F3A3F,
1722   PREFIX_EVEX_0F3A42,
1723   PREFIX_EVEX_0F3A43,
1724   PREFIX_EVEX_0F3A44,
1725   PREFIX_EVEX_0F3A50,
1726   PREFIX_EVEX_0F3A51,
1727   PREFIX_EVEX_0F3A54,
1728   PREFIX_EVEX_0F3A55,
1729   PREFIX_EVEX_0F3A56,
1730   PREFIX_EVEX_0F3A57,
1731   PREFIX_EVEX_0F3A66,
1732   PREFIX_EVEX_0F3A67,
1733   PREFIX_EVEX_0F3A70,
1734   PREFIX_EVEX_0F3A71,
1735   PREFIX_EVEX_0F3A72,
1736   PREFIX_EVEX_0F3A73,
1737   PREFIX_EVEX_0F3ACE,
1738   PREFIX_EVEX_0F3ACF
1739 };
1740
1741 enum
1742 {
1743   X86_64_06 = 0,
1744   X86_64_07,
1745   X86_64_0D,
1746   X86_64_16,
1747   X86_64_17,
1748   X86_64_1E,
1749   X86_64_1F,
1750   X86_64_27,
1751   X86_64_2F,
1752   X86_64_37,
1753   X86_64_3F,
1754   X86_64_60,
1755   X86_64_61,
1756   X86_64_62,
1757   X86_64_63,
1758   X86_64_6D,
1759   X86_64_6F,
1760   X86_64_82,
1761   X86_64_9A,
1762   X86_64_C4,
1763   X86_64_C5,
1764   X86_64_CE,
1765   X86_64_D4,
1766   X86_64_D5,
1767   X86_64_E8,
1768   X86_64_E9,
1769   X86_64_EA,
1770   X86_64_0F01_REG_0,
1771   X86_64_0F01_REG_1,
1772   X86_64_0F01_REG_2,
1773   X86_64_0F01_REG_3
1774 };
1775
1776 enum
1777 {
1778   THREE_BYTE_0F38 = 0,
1779   THREE_BYTE_0F3A
1780 };
1781
1782 enum
1783 {
1784   XOP_08 = 0,
1785   XOP_09,
1786   XOP_0A
1787 };
1788
1789 enum
1790 {
1791   VEX_0F = 0,
1792   VEX_0F38,
1793   VEX_0F3A
1794 };
1795
1796 enum
1797 {
1798   EVEX_0F = 0,
1799   EVEX_0F38,
1800   EVEX_0F3A
1801 };
1802
1803 enum
1804 {
1805   VEX_LEN_0F12_P_0_M_0 = 0,
1806   VEX_LEN_0F12_P_0_M_1,
1807   VEX_LEN_0F12_P_2,
1808   VEX_LEN_0F13_M_0,
1809   VEX_LEN_0F16_P_0_M_0,
1810   VEX_LEN_0F16_P_0_M_1,
1811   VEX_LEN_0F16_P_2,
1812   VEX_LEN_0F17_M_0,
1813   VEX_LEN_0F41_P_0,
1814   VEX_LEN_0F41_P_2,
1815   VEX_LEN_0F42_P_0,
1816   VEX_LEN_0F42_P_2,
1817   VEX_LEN_0F44_P_0,
1818   VEX_LEN_0F44_P_2,
1819   VEX_LEN_0F45_P_0,
1820   VEX_LEN_0F45_P_2,
1821   VEX_LEN_0F46_P_0,
1822   VEX_LEN_0F46_P_2,
1823   VEX_LEN_0F47_P_0,
1824   VEX_LEN_0F47_P_2,
1825   VEX_LEN_0F4A_P_0,
1826   VEX_LEN_0F4A_P_2,
1827   VEX_LEN_0F4B_P_0,
1828   VEX_LEN_0F4B_P_2,
1829   VEX_LEN_0F6E_P_2,
1830   VEX_LEN_0F77_P_0,
1831   VEX_LEN_0F7E_P_1,
1832   VEX_LEN_0F7E_P_2,
1833   VEX_LEN_0F90_P_0,
1834   VEX_LEN_0F90_P_2,
1835   VEX_LEN_0F91_P_0,
1836   VEX_LEN_0F91_P_2,
1837   VEX_LEN_0F92_P_0,
1838   VEX_LEN_0F92_P_2,
1839   VEX_LEN_0F92_P_3,
1840   VEX_LEN_0F93_P_0,
1841   VEX_LEN_0F93_P_2,
1842   VEX_LEN_0F93_P_3,
1843   VEX_LEN_0F98_P_0,
1844   VEX_LEN_0F98_P_2,
1845   VEX_LEN_0F99_P_0,
1846   VEX_LEN_0F99_P_2,
1847   VEX_LEN_0FAE_R_2_M_0,
1848   VEX_LEN_0FAE_R_3_M_0,
1849   VEX_LEN_0FC4_P_2,
1850   VEX_LEN_0FC5_P_2,
1851   VEX_LEN_0FD6_P_2,
1852   VEX_LEN_0FF7_P_2,
1853   VEX_LEN_0F3816_P_2,
1854   VEX_LEN_0F3819_P_2,
1855   VEX_LEN_0F381A_P_2_M_0,
1856   VEX_LEN_0F3836_P_2,
1857   VEX_LEN_0F3841_P_2,
1858   VEX_LEN_0F385A_P_2_M_0,
1859   VEX_LEN_0F38DB_P_2,
1860   VEX_LEN_0F38F2_P_0,
1861   VEX_LEN_0F38F3_R_1_P_0,
1862   VEX_LEN_0F38F3_R_2_P_0,
1863   VEX_LEN_0F38F3_R_3_P_0,
1864   VEX_LEN_0F38F5_P_0,
1865   VEX_LEN_0F38F5_P_1,
1866   VEX_LEN_0F38F5_P_3,
1867   VEX_LEN_0F38F6_P_3,
1868   VEX_LEN_0F38F7_P_0,
1869   VEX_LEN_0F38F7_P_1,
1870   VEX_LEN_0F38F7_P_2,
1871   VEX_LEN_0F38F7_P_3,
1872   VEX_LEN_0F3A00_P_2,
1873   VEX_LEN_0F3A01_P_2,
1874   VEX_LEN_0F3A06_P_2,
1875   VEX_LEN_0F3A14_P_2,
1876   VEX_LEN_0F3A15_P_2,
1877   VEX_LEN_0F3A16_P_2,
1878   VEX_LEN_0F3A17_P_2,
1879   VEX_LEN_0F3A18_P_2,
1880   VEX_LEN_0F3A19_P_2,
1881   VEX_LEN_0F3A20_P_2,
1882   VEX_LEN_0F3A21_P_2,
1883   VEX_LEN_0F3A22_P_2,
1884   VEX_LEN_0F3A30_P_2,
1885   VEX_LEN_0F3A31_P_2,
1886   VEX_LEN_0F3A32_P_2,
1887   VEX_LEN_0F3A33_P_2,
1888   VEX_LEN_0F3A38_P_2,
1889   VEX_LEN_0F3A39_P_2,
1890   VEX_LEN_0F3A41_P_2,
1891   VEX_LEN_0F3A46_P_2,
1892   VEX_LEN_0F3A60_P_2,
1893   VEX_LEN_0F3A61_P_2,
1894   VEX_LEN_0F3A62_P_2,
1895   VEX_LEN_0F3A63_P_2,
1896   VEX_LEN_0F3A6A_P_2,
1897   VEX_LEN_0F3A6B_P_2,
1898   VEX_LEN_0F3A6E_P_2,
1899   VEX_LEN_0F3A6F_P_2,
1900   VEX_LEN_0F3A7A_P_2,
1901   VEX_LEN_0F3A7B_P_2,
1902   VEX_LEN_0F3A7E_P_2,
1903   VEX_LEN_0F3A7F_P_2,
1904   VEX_LEN_0F3ADF_P_2,
1905   VEX_LEN_0F3AF0_P_3,
1906   VEX_LEN_0FXOP_08_CC,
1907   VEX_LEN_0FXOP_08_CD,
1908   VEX_LEN_0FXOP_08_CE,
1909   VEX_LEN_0FXOP_08_CF,
1910   VEX_LEN_0FXOP_08_EC,
1911   VEX_LEN_0FXOP_08_ED,
1912   VEX_LEN_0FXOP_08_EE,
1913   VEX_LEN_0FXOP_08_EF,
1914   VEX_LEN_0FXOP_09_80,
1915   VEX_LEN_0FXOP_09_81
1916 };
1917
1918 enum
1919 {
1920   EVEX_LEN_0F6E_P_2 = 0,
1921   EVEX_LEN_0F7E_P_1,
1922   EVEX_LEN_0F7E_P_2,
1923   EVEX_LEN_0FD6_P_2,
1924   EVEX_LEN_0F3819_P_2_W_0,
1925   EVEX_LEN_0F3819_P_2_W_1,
1926   EVEX_LEN_0F381A_P_2_W_0,
1927   EVEX_LEN_0F381A_P_2_W_1,
1928   EVEX_LEN_0F381B_P_2_W_0,
1929   EVEX_LEN_0F381B_P_2_W_1,
1930   EVEX_LEN_0F385A_P_2_W_0,
1931   EVEX_LEN_0F385A_P_2_W_1,
1932   EVEX_LEN_0F385B_P_2_W_0,
1933   EVEX_LEN_0F385B_P_2_W_1,
1934   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1937   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1938   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1939   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1940   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1941   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1942   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1943   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1944   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1945   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1946   EVEX_LEN_0F3A18_P_2_W_0,
1947   EVEX_LEN_0F3A18_P_2_W_1,
1948   EVEX_LEN_0F3A19_P_2_W_0,
1949   EVEX_LEN_0F3A19_P_2_W_1,
1950   EVEX_LEN_0F3A1A_P_2_W_0,
1951   EVEX_LEN_0F3A1A_P_2_W_1,
1952   EVEX_LEN_0F3A1B_P_2_W_0,
1953   EVEX_LEN_0F3A1B_P_2_W_1,
1954   EVEX_LEN_0F3A23_P_2_W_0,
1955   EVEX_LEN_0F3A23_P_2_W_1,
1956   EVEX_LEN_0F3A38_P_2_W_0,
1957   EVEX_LEN_0F3A38_P_2_W_1,
1958   EVEX_LEN_0F3A39_P_2_W_0,
1959   EVEX_LEN_0F3A39_P_2_W_1,
1960   EVEX_LEN_0F3A3A_P_2_W_0,
1961   EVEX_LEN_0F3A3A_P_2_W_1,
1962   EVEX_LEN_0F3A3B_P_2_W_0,
1963   EVEX_LEN_0F3A3B_P_2_W_1,
1964   EVEX_LEN_0F3A43_P_2_W_0,
1965   EVEX_LEN_0F3A43_P_2_W_1
1966 };
1967
1968 enum
1969 {
1970   VEX_W_0F41_P_0_LEN_1 = 0,
1971   VEX_W_0F41_P_2_LEN_1,
1972   VEX_W_0F42_P_0_LEN_1,
1973   VEX_W_0F42_P_2_LEN_1,
1974   VEX_W_0F44_P_0_LEN_0,
1975   VEX_W_0F44_P_2_LEN_0,
1976   VEX_W_0F45_P_0_LEN_1,
1977   VEX_W_0F45_P_2_LEN_1,
1978   VEX_W_0F46_P_0_LEN_1,
1979   VEX_W_0F46_P_2_LEN_1,
1980   VEX_W_0F47_P_0_LEN_1,
1981   VEX_W_0F47_P_2_LEN_1,
1982   VEX_W_0F4A_P_0_LEN_1,
1983   VEX_W_0F4A_P_2_LEN_1,
1984   VEX_W_0F4B_P_0_LEN_1,
1985   VEX_W_0F4B_P_2_LEN_1,
1986   VEX_W_0F90_P_0_LEN_0,
1987   VEX_W_0F90_P_2_LEN_0,
1988   VEX_W_0F91_P_0_LEN_0,
1989   VEX_W_0F91_P_2_LEN_0,
1990   VEX_W_0F92_P_0_LEN_0,
1991   VEX_W_0F92_P_2_LEN_0,
1992   VEX_W_0F93_P_0_LEN_0,
1993   VEX_W_0F93_P_2_LEN_0,
1994   VEX_W_0F98_P_0_LEN_0,
1995   VEX_W_0F98_P_2_LEN_0,
1996   VEX_W_0F99_P_0_LEN_0,
1997   VEX_W_0F99_P_2_LEN_0,
1998   VEX_W_0F380C_P_2,
1999   VEX_W_0F380D_P_2,
2000   VEX_W_0F380E_P_2,
2001   VEX_W_0F380F_P_2,
2002   VEX_W_0F3816_P_2,
2003   VEX_W_0F3818_P_2,
2004   VEX_W_0F3819_P_2,
2005   VEX_W_0F381A_P_2_M_0,
2006   VEX_W_0F382C_P_2_M_0,
2007   VEX_W_0F382D_P_2_M_0,
2008   VEX_W_0F382E_P_2_M_0,
2009   VEX_W_0F382F_P_2_M_0,
2010   VEX_W_0F3836_P_2,
2011   VEX_W_0F3846_P_2,
2012   VEX_W_0F3858_P_2,
2013   VEX_W_0F3859_P_2,
2014   VEX_W_0F385A_P_2_M_0,
2015   VEX_W_0F3878_P_2,
2016   VEX_W_0F3879_P_2,
2017   VEX_W_0F38CF_P_2,
2018   VEX_W_0F3A00_P_2,
2019   VEX_W_0F3A01_P_2,
2020   VEX_W_0F3A02_P_2,
2021   VEX_W_0F3A04_P_2,
2022   VEX_W_0F3A05_P_2,
2023   VEX_W_0F3A06_P_2,
2024   VEX_W_0F3A18_P_2,
2025   VEX_W_0F3A19_P_2,
2026   VEX_W_0F3A30_P_2_LEN_0,
2027   VEX_W_0F3A31_P_2_LEN_0,
2028   VEX_W_0F3A32_P_2_LEN_0,
2029   VEX_W_0F3A33_P_2_LEN_0,
2030   VEX_W_0F3A38_P_2,
2031   VEX_W_0F3A39_P_2,
2032   VEX_W_0F3A46_P_2,
2033   VEX_W_0F3A48_P_2,
2034   VEX_W_0F3A49_P_2,
2035   VEX_W_0F3A4A_P_2,
2036   VEX_W_0F3A4B_P_2,
2037   VEX_W_0F3A4C_P_2,
2038   VEX_W_0F3ACE_P_2,
2039   VEX_W_0F3ACF_P_2,
2040
2041   EVEX_W_0F10_P_0,
2042   EVEX_W_0F10_P_1,
2043   EVEX_W_0F10_P_2,
2044   EVEX_W_0F10_P_3,
2045   EVEX_W_0F11_P_0,
2046   EVEX_W_0F11_P_1,
2047   EVEX_W_0F11_P_2,
2048   EVEX_W_0F11_P_3,
2049   EVEX_W_0F12_P_0_M_0,
2050   EVEX_W_0F12_P_0_M_1,
2051   EVEX_W_0F12_P_1,
2052   EVEX_W_0F12_P_2,
2053   EVEX_W_0F12_P_3,
2054   EVEX_W_0F13_P_0,
2055   EVEX_W_0F13_P_2,
2056   EVEX_W_0F14_P_0,
2057   EVEX_W_0F14_P_2,
2058   EVEX_W_0F15_P_0,
2059   EVEX_W_0F15_P_2,
2060   EVEX_W_0F16_P_0_M_0,
2061   EVEX_W_0F16_P_0_M_1,
2062   EVEX_W_0F16_P_1,
2063   EVEX_W_0F16_P_2,
2064   EVEX_W_0F17_P_0,
2065   EVEX_W_0F17_P_2,
2066   EVEX_W_0F28_P_0,
2067   EVEX_W_0F28_P_2,
2068   EVEX_W_0F29_P_0,
2069   EVEX_W_0F29_P_2,
2070   EVEX_W_0F2A_P_3,
2071   EVEX_W_0F2B_P_0,
2072   EVEX_W_0F2B_P_2,
2073   EVEX_W_0F2E_P_0,
2074   EVEX_W_0F2E_P_2,
2075   EVEX_W_0F2F_P_0,
2076   EVEX_W_0F2F_P_2,
2077   EVEX_W_0F51_P_0,
2078   EVEX_W_0F51_P_1,
2079   EVEX_W_0F51_P_2,
2080   EVEX_W_0F51_P_3,
2081   EVEX_W_0F54_P_0,
2082   EVEX_W_0F54_P_2,
2083   EVEX_W_0F55_P_0,
2084   EVEX_W_0F55_P_2,
2085   EVEX_W_0F56_P_0,
2086   EVEX_W_0F56_P_2,
2087   EVEX_W_0F57_P_0,
2088   EVEX_W_0F57_P_2,
2089   EVEX_W_0F58_P_0,
2090   EVEX_W_0F58_P_1,
2091   EVEX_W_0F58_P_2,
2092   EVEX_W_0F58_P_3,
2093   EVEX_W_0F59_P_0,
2094   EVEX_W_0F59_P_1,
2095   EVEX_W_0F59_P_2,
2096   EVEX_W_0F59_P_3,
2097   EVEX_W_0F5A_P_0,
2098   EVEX_W_0F5A_P_1,
2099   EVEX_W_0F5A_P_2,
2100   EVEX_W_0F5A_P_3,
2101   EVEX_W_0F5B_P_0,
2102   EVEX_W_0F5B_P_1,
2103   EVEX_W_0F5B_P_2,
2104   EVEX_W_0F5C_P_0,
2105   EVEX_W_0F5C_P_1,
2106   EVEX_W_0F5C_P_2,
2107   EVEX_W_0F5C_P_3,
2108   EVEX_W_0F5D_P_0,
2109   EVEX_W_0F5D_P_1,
2110   EVEX_W_0F5D_P_2,
2111   EVEX_W_0F5D_P_3,
2112   EVEX_W_0F5E_P_0,
2113   EVEX_W_0F5E_P_1,
2114   EVEX_W_0F5E_P_2,
2115   EVEX_W_0F5E_P_3,
2116   EVEX_W_0F5F_P_0,
2117   EVEX_W_0F5F_P_1,
2118   EVEX_W_0F5F_P_2,
2119   EVEX_W_0F5F_P_3,
2120   EVEX_W_0F62_P_2,
2121   EVEX_W_0F66_P_2,
2122   EVEX_W_0F6A_P_2,
2123   EVEX_W_0F6B_P_2,
2124   EVEX_W_0F6C_P_2,
2125   EVEX_W_0F6D_P_2,
2126   EVEX_W_0F6F_P_1,
2127   EVEX_W_0F6F_P_2,
2128   EVEX_W_0F6F_P_3,
2129   EVEX_W_0F70_P_2,
2130   EVEX_W_0F72_R_2_P_2,
2131   EVEX_W_0F72_R_6_P_2,
2132   EVEX_W_0F73_R_2_P_2,
2133   EVEX_W_0F73_R_6_P_2,
2134   EVEX_W_0F76_P_2,
2135   EVEX_W_0F78_P_0,
2136   EVEX_W_0F78_P_2,
2137   EVEX_W_0F79_P_0,
2138   EVEX_W_0F79_P_2,
2139   EVEX_W_0F7A_P_1,
2140   EVEX_W_0F7A_P_2,
2141   EVEX_W_0F7A_P_3,
2142   EVEX_W_0F7B_P_2,
2143   EVEX_W_0F7B_P_3,
2144   EVEX_W_0F7E_P_1,
2145   EVEX_W_0F7F_P_1,
2146   EVEX_W_0F7F_P_2,
2147   EVEX_W_0F7F_P_3,
2148   EVEX_W_0FC2_P_0,
2149   EVEX_W_0FC2_P_1,
2150   EVEX_W_0FC2_P_2,
2151   EVEX_W_0FC2_P_3,
2152   EVEX_W_0FC6_P_0,
2153   EVEX_W_0FC6_P_2,
2154   EVEX_W_0FD2_P_2,
2155   EVEX_W_0FD3_P_2,
2156   EVEX_W_0FD4_P_2,
2157   EVEX_W_0FD6_P_2,
2158   EVEX_W_0FE6_P_1,
2159   EVEX_W_0FE6_P_2,
2160   EVEX_W_0FE6_P_3,
2161   EVEX_W_0FE7_P_2,
2162   EVEX_W_0FF2_P_2,
2163   EVEX_W_0FF3_P_2,
2164   EVEX_W_0FF4_P_2,
2165   EVEX_W_0FFA_P_2,
2166   EVEX_W_0FFB_P_2,
2167   EVEX_W_0FFE_P_2,
2168   EVEX_W_0F380C_P_2,
2169   EVEX_W_0F380D_P_2,
2170   EVEX_W_0F3810_P_1,
2171   EVEX_W_0F3810_P_2,
2172   EVEX_W_0F3811_P_1,
2173   EVEX_W_0F3811_P_2,
2174   EVEX_W_0F3812_P_1,
2175   EVEX_W_0F3812_P_2,
2176   EVEX_W_0F3813_P_1,
2177   EVEX_W_0F3813_P_2,
2178   EVEX_W_0F3814_P_1,
2179   EVEX_W_0F3815_P_1,
2180   EVEX_W_0F3818_P_2,
2181   EVEX_W_0F3819_P_2,
2182   EVEX_W_0F381A_P_2,
2183   EVEX_W_0F381B_P_2,
2184   EVEX_W_0F381E_P_2,
2185   EVEX_W_0F381F_P_2,
2186   EVEX_W_0F3820_P_1,
2187   EVEX_W_0F3821_P_1,
2188   EVEX_W_0F3822_P_1,
2189   EVEX_W_0F3823_P_1,
2190   EVEX_W_0F3824_P_1,
2191   EVEX_W_0F3825_P_1,
2192   EVEX_W_0F3825_P_2,
2193   EVEX_W_0F3826_P_1,
2194   EVEX_W_0F3826_P_2,
2195   EVEX_W_0F3828_P_1,
2196   EVEX_W_0F3828_P_2,
2197   EVEX_W_0F3829_P_1,
2198   EVEX_W_0F3829_P_2,
2199   EVEX_W_0F382A_P_1,
2200   EVEX_W_0F382A_P_2,
2201   EVEX_W_0F382B_P_2,
2202   EVEX_W_0F3830_P_1,
2203   EVEX_W_0F3831_P_1,
2204   EVEX_W_0F3832_P_1,
2205   EVEX_W_0F3833_P_1,
2206   EVEX_W_0F3834_P_1,
2207   EVEX_W_0F3835_P_1,
2208   EVEX_W_0F3835_P_2,
2209   EVEX_W_0F3837_P_2,
2210   EVEX_W_0F3838_P_1,
2211   EVEX_W_0F3839_P_1,
2212   EVEX_W_0F383A_P_1,
2213   EVEX_W_0F3840_P_2,
2214   EVEX_W_0F3852_P_1,
2215   EVEX_W_0F3854_P_2,
2216   EVEX_W_0F3855_P_2,
2217   EVEX_W_0F3858_P_2,
2218   EVEX_W_0F3859_P_2,
2219   EVEX_W_0F385A_P_2,
2220   EVEX_W_0F385B_P_2,
2221   EVEX_W_0F3862_P_2,
2222   EVEX_W_0F3863_P_2,
2223   EVEX_W_0F3866_P_2,
2224   EVEX_W_0F3868_P_3,
2225   EVEX_W_0F3870_P_2,
2226   EVEX_W_0F3871_P_2,
2227   EVEX_W_0F3872_P_1,
2228   EVEX_W_0F3872_P_2,
2229   EVEX_W_0F3872_P_3,
2230   EVEX_W_0F3873_P_2,
2231   EVEX_W_0F3875_P_2,
2232   EVEX_W_0F3878_P_2,
2233   EVEX_W_0F3879_P_2,
2234   EVEX_W_0F387A_P_2,
2235   EVEX_W_0F387B_P_2,
2236   EVEX_W_0F387D_P_2,
2237   EVEX_W_0F3883_P_2,
2238   EVEX_W_0F388D_P_2,
2239   EVEX_W_0F3891_P_2,
2240   EVEX_W_0F3893_P_2,
2241   EVEX_W_0F38A1_P_2,
2242   EVEX_W_0F38A3_P_2,
2243   EVEX_W_0F38C7_R_1_P_2,
2244   EVEX_W_0F38C7_R_2_P_2,
2245   EVEX_W_0F38C7_R_5_P_2,
2246   EVEX_W_0F38C7_R_6_P_2,
2247
2248   EVEX_W_0F3A00_P_2,
2249   EVEX_W_0F3A01_P_2,
2250   EVEX_W_0F3A04_P_2,
2251   EVEX_W_0F3A05_P_2,
2252   EVEX_W_0F3A08_P_2,
2253   EVEX_W_0F3A09_P_2,
2254   EVEX_W_0F3A0A_P_2,
2255   EVEX_W_0F3A0B_P_2,
2256   EVEX_W_0F3A18_P_2,
2257   EVEX_W_0F3A19_P_2,
2258   EVEX_W_0F3A1A_P_2,
2259   EVEX_W_0F3A1B_P_2,
2260   EVEX_W_0F3A1D_P_2,
2261   EVEX_W_0F3A21_P_2,
2262   EVEX_W_0F3A23_P_2,
2263   EVEX_W_0F3A38_P_2,
2264   EVEX_W_0F3A39_P_2,
2265   EVEX_W_0F3A3A_P_2,
2266   EVEX_W_0F3A3B_P_2,
2267   EVEX_W_0F3A3E_P_2,
2268   EVEX_W_0F3A3F_P_2,
2269   EVEX_W_0F3A42_P_2,
2270   EVEX_W_0F3A43_P_2,
2271   EVEX_W_0F3A50_P_2,
2272   EVEX_W_0F3A51_P_2,
2273   EVEX_W_0F3A56_P_2,
2274   EVEX_W_0F3A57_P_2,
2275   EVEX_W_0F3A66_P_2,
2276   EVEX_W_0F3A67_P_2,
2277   EVEX_W_0F3A70_P_2,
2278   EVEX_W_0F3A71_P_2,
2279   EVEX_W_0F3A72_P_2,
2280   EVEX_W_0F3A73_P_2,
2281   EVEX_W_0F3ACE_P_2,
2282   EVEX_W_0F3ACF_P_2
2283 };
2284
2285 typedef void (*op_rtn) (int bytemode, int sizeflag);
2286
2287 struct dis386 {
2288   const char *name;
2289   struct
2290     {
2291       op_rtn rtn;
2292       int bytemode;
2293     } op[MAX_OPERANDS];
2294   unsigned int prefix_requirement;
2295 };
2296
2297 /* Upper case letters in the instruction names here are macros.
2298    'A' => print 'b' if no register operands or suffix_always is true
2299    'B' => print 'b' if suffix_always is true
2300    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2301           size prefix
2302    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2303           suffix_always is true
2304    'E' => print 'e' if 32-bit form of jcxz
2305    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2306    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2307    'H' => print ",pt" or ",pn" branch hint
2308    'I' => honor following macro letter even in Intel mode (implemented only
2309           for some of the macro letters)
2310    'J' => print 'l'
2311    'K' => print 'd' or 'q' if rex prefix is present.
2312    'L' => print 'l' if suffix_always is true
2313    'M' => print 'r' if intel_mnemonic is false.
2314    'N' => print 'n' if instruction has no wait "prefix"
2315    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2316    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2317           or suffix_always is true.  print 'q' if rex prefix is present.
2318    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2319           is true
2320    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2321    'S' => print 'w', 'l' or 'q' if suffix_always is true
2322    'T' => print 'q' in 64bit mode if instruction has no operand size
2323           prefix and behave as 'P' otherwise
2324    'U' => print 'q' in 64bit mode if instruction has no operand size
2325           prefix and behave as 'Q' otherwise
2326    'V' => print 'q' in 64bit mode if instruction has no operand size
2327           prefix and behave as 'S' otherwise
2328    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2329    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2330    'Y' unused.
2331    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2332    '!' => change condition from true to false or from false to true.
2333    '%' => add 1 upper case letter to the macro.
2334    '^' => print 'w' or 'l' depending on operand size prefix or
2335           suffix_always is true (lcall/ljmp).
2336    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2337           on operand size prefix.
2338    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2339           has no operand size prefix for AMD64 ISA, behave as 'P'
2340           otherwise
2341
2342    2 upper case letter macros:
2343    "XY" => print 'x' or 'y' if suffix_always is true or no register
2344            operands and no broadcast.
2345    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2346            register operands and no broadcast.
2347    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2348    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2349            or suffix_always is true
2350    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2351    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2352    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2353    "LW" => print 'd', 'q' depending on the VEX.W bit
2354    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2355            an operand size prefix, or suffix_always is true.  print
2356            'q' if rex prefix is present.
2357
2358    Many of the above letters print nothing in Intel mode.  See "putop"
2359    for the details.
2360
2361    Braces '{' and '}', and vertical bars '|', indicate alternative
2362    mnemonic strings for AT&T and Intel.  */
2363
2364 static const struct dis386 dis386[] = {
2365   /* 00 */
2366   { "addB",             { Ebh1, Gb }, 0 },
2367   { "addS",             { Evh1, Gv }, 0 },
2368   { "addB",             { Gb, EbS }, 0 },
2369   { "addS",             { Gv, EvS }, 0 },
2370   { "addB",             { AL, Ib }, 0 },
2371   { "addS",             { eAX, Iv }, 0 },
2372   { X86_64_TABLE (X86_64_06) },
2373   { X86_64_TABLE (X86_64_07) },
2374   /* 08 */
2375   { "orB",              { Ebh1, Gb }, 0 },
2376   { "orS",              { Evh1, Gv }, 0 },
2377   { "orB",              { Gb, EbS }, 0 },
2378   { "orS",              { Gv, EvS }, 0 },
2379   { "orB",              { AL, Ib }, 0 },
2380   { "orS",              { eAX, Iv }, 0 },
2381   { X86_64_TABLE (X86_64_0D) },
2382   { Bad_Opcode },       /* 0x0f extended opcode escape */
2383   /* 10 */
2384   { "adcB",             { Ebh1, Gb }, 0 },
2385   { "adcS",             { Evh1, Gv }, 0 },
2386   { "adcB",             { Gb, EbS }, 0 },
2387   { "adcS",             { Gv, EvS }, 0 },
2388   { "adcB",             { AL, Ib }, 0 },
2389   { "adcS",             { eAX, Iv }, 0 },
2390   { X86_64_TABLE (X86_64_16) },
2391   { X86_64_TABLE (X86_64_17) },
2392   /* 18 */
2393   { "sbbB",             { Ebh1, Gb }, 0 },
2394   { "sbbS",             { Evh1, Gv }, 0 },
2395   { "sbbB",             { Gb, EbS }, 0 },
2396   { "sbbS",             { Gv, EvS }, 0 },
2397   { "sbbB",             { AL, Ib }, 0 },
2398   { "sbbS",             { eAX, Iv }, 0 },
2399   { X86_64_TABLE (X86_64_1E) },
2400   { X86_64_TABLE (X86_64_1F) },
2401   /* 20 */
2402   { "andB",             { Ebh1, Gb }, 0 },
2403   { "andS",             { Evh1, Gv }, 0 },
2404   { "andB",             { Gb, EbS }, 0 },
2405   { "andS",             { Gv, EvS }, 0 },
2406   { "andB",             { AL, Ib }, 0 },
2407   { "andS",             { eAX, Iv }, 0 },
2408   { Bad_Opcode },       /* SEG ES prefix */
2409   { X86_64_TABLE (X86_64_27) },
2410   /* 28 */
2411   { "subB",             { Ebh1, Gb }, 0 },
2412   { "subS",             { Evh1, Gv }, 0 },
2413   { "subB",             { Gb, EbS }, 0 },
2414   { "subS",             { Gv, EvS }, 0 },
2415   { "subB",             { AL, Ib }, 0 },
2416   { "subS",             { eAX, Iv }, 0 },
2417   { Bad_Opcode },       /* SEG CS prefix */
2418   { X86_64_TABLE (X86_64_2F) },
2419   /* 30 */
2420   { "xorB",             { Ebh1, Gb }, 0 },
2421   { "xorS",             { Evh1, Gv }, 0 },
2422   { "xorB",             { Gb, EbS }, 0 },
2423   { "xorS",             { Gv, EvS }, 0 },
2424   { "xorB",             { AL, Ib }, 0 },
2425   { "xorS",             { eAX, Iv }, 0 },
2426   { Bad_Opcode },       /* SEG SS prefix */
2427   { X86_64_TABLE (X86_64_37) },
2428   /* 38 */
2429   { "cmpB",             { Eb, Gb }, 0 },
2430   { "cmpS",             { Ev, Gv }, 0 },
2431   { "cmpB",             { Gb, EbS }, 0 },
2432   { "cmpS",             { Gv, EvS }, 0 },
2433   { "cmpB",             { AL, Ib }, 0 },
2434   { "cmpS",             { eAX, Iv }, 0 },
2435   { Bad_Opcode },       /* SEG DS prefix */
2436   { X86_64_TABLE (X86_64_3F) },
2437   /* 40 */
2438   { "inc{S|}",          { RMeAX }, 0 },
2439   { "inc{S|}",          { RMeCX }, 0 },
2440   { "inc{S|}",          { RMeDX }, 0 },
2441   { "inc{S|}",          { RMeBX }, 0 },
2442   { "inc{S|}",          { RMeSP }, 0 },
2443   { "inc{S|}",          { RMeBP }, 0 },
2444   { "inc{S|}",          { RMeSI }, 0 },
2445   { "inc{S|}",          { RMeDI }, 0 },
2446   /* 48 */
2447   { "dec{S|}",          { RMeAX }, 0 },
2448   { "dec{S|}",          { RMeCX }, 0 },
2449   { "dec{S|}",          { RMeDX }, 0 },
2450   { "dec{S|}",          { RMeBX }, 0 },
2451   { "dec{S|}",          { RMeSP }, 0 },
2452   { "dec{S|}",          { RMeBP }, 0 },
2453   { "dec{S|}",          { RMeSI }, 0 },
2454   { "dec{S|}",          { RMeDI }, 0 },
2455   /* 50 */
2456   { "pushV",            { RMrAX }, 0 },
2457   { "pushV",            { RMrCX }, 0 },
2458   { "pushV",            { RMrDX }, 0 },
2459   { "pushV",            { RMrBX }, 0 },
2460   { "pushV",            { RMrSP }, 0 },
2461   { "pushV",            { RMrBP }, 0 },
2462   { "pushV",            { RMrSI }, 0 },
2463   { "pushV",            { RMrDI }, 0 },
2464   /* 58 */
2465   { "popV",             { RMrAX }, 0 },
2466   { "popV",             { RMrCX }, 0 },
2467   { "popV",             { RMrDX }, 0 },
2468   { "popV",             { RMrBX }, 0 },
2469   { "popV",             { RMrSP }, 0 },
2470   { "popV",             { RMrBP }, 0 },
2471   { "popV",             { RMrSI }, 0 },
2472   { "popV",             { RMrDI }, 0 },
2473   /* 60 */
2474   { X86_64_TABLE (X86_64_60) },
2475   { X86_64_TABLE (X86_64_61) },
2476   { X86_64_TABLE (X86_64_62) },
2477   { X86_64_TABLE (X86_64_63) },
2478   { Bad_Opcode },       /* seg fs */
2479   { Bad_Opcode },       /* seg gs */
2480   { Bad_Opcode },       /* op size prefix */
2481   { Bad_Opcode },       /* adr size prefix */
2482   /* 68 */
2483   { "pushT",            { sIv }, 0 },
2484   { "imulS",            { Gv, Ev, Iv }, 0 },
2485   { "pushT",            { sIbT }, 0 },
2486   { "imulS",            { Gv, Ev, sIb }, 0 },
2487   { "ins{b|}",          { Ybr, indirDX }, 0 },
2488   { X86_64_TABLE (X86_64_6D) },
2489   { "outs{b|}",         { indirDXr, Xb }, 0 },
2490   { X86_64_TABLE (X86_64_6F) },
2491   /* 70 */
2492   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2497   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2500   /* 78 */
2501   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2509   /* 80 */
2510   { REG_TABLE (REG_80) },
2511   { REG_TABLE (REG_81) },
2512   { X86_64_TABLE (X86_64_82) },
2513   { REG_TABLE (REG_83) },
2514   { "testB",            { Eb, Gb }, 0 },
2515   { "testS",            { Ev, Gv }, 0 },
2516   { "xchgB",            { Ebh2, Gb }, 0 },
2517   { "xchgS",            { Evh2, Gv }, 0 },
2518   /* 88 */
2519   { "movB",             { Ebh3, Gb }, 0 },
2520   { "movS",             { Evh3, Gv }, 0 },
2521   { "movB",             { Gb, EbS }, 0 },
2522   { "movS",             { Gv, EvS }, 0 },
2523   { "movD",             { Sv, Sw }, 0 },
2524   { MOD_TABLE (MOD_8D) },
2525   { "movD",             { Sw, Sv }, 0 },
2526   { REG_TABLE (REG_8F) },
2527   /* 90 */
2528   { PREFIX_TABLE (PREFIX_90) },
2529   { "xchgS",            { RMeCX, eAX }, 0 },
2530   { "xchgS",            { RMeDX, eAX }, 0 },
2531   { "xchgS",            { RMeBX, eAX }, 0 },
2532   { "xchgS",            { RMeSP, eAX }, 0 },
2533   { "xchgS",            { RMeBP, eAX }, 0 },
2534   { "xchgS",            { RMeSI, eAX }, 0 },
2535   { "xchgS",            { RMeDI, eAX }, 0 },
2536   /* 98 */
2537   { "cW{t|}R",          { XX }, 0 },
2538   { "cR{t|}O",          { XX }, 0 },
2539   { X86_64_TABLE (X86_64_9A) },
2540   { Bad_Opcode },       /* fwait */
2541   { "pushfT",           { XX }, 0 },
2542   { "popfT",            { XX }, 0 },
2543   { "sahf",             { XX }, 0 },
2544   { "lahf",             { XX }, 0 },
2545   /* a0 */
2546   { "mov%LB",           { AL, Ob }, 0 },
2547   { "mov%LS",           { eAX, Ov }, 0 },
2548   { "mov%LB",           { Ob, AL }, 0 },
2549   { "mov%LS",           { Ov, eAX }, 0 },
2550   { "movs{b|}",         { Ybr, Xb }, 0 },
2551   { "movs{R|}",         { Yvr, Xv }, 0 },
2552   { "cmps{b|}",         { Xb, Yb }, 0 },
2553   { "cmps{R|}",         { Xv, Yv }, 0 },
2554   /* a8 */
2555   { "testB",            { AL, Ib }, 0 },
2556   { "testS",            { eAX, Iv }, 0 },
2557   { "stosB",            { Ybr, AL }, 0 },
2558   { "stosS",            { Yvr, eAX }, 0 },
2559   { "lodsB",            { ALr, Xb }, 0 },
2560   { "lodsS",            { eAXr, Xv }, 0 },
2561   { "scasB",            { AL, Yb }, 0 },
2562   { "scasS",            { eAX, Yv }, 0 },
2563   /* b0 */
2564   { "movB",             { RMAL, Ib }, 0 },
2565   { "movB",             { RMCL, Ib }, 0 },
2566   { "movB",             { RMDL, Ib }, 0 },
2567   { "movB",             { RMBL, Ib }, 0 },
2568   { "movB",             { RMAH, Ib }, 0 },
2569   { "movB",             { RMCH, Ib }, 0 },
2570   { "movB",             { RMDH, Ib }, 0 },
2571   { "movB",             { RMBH, Ib }, 0 },
2572   /* b8 */
2573   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2578   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2579   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2580   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2581   /* c0 */
2582   { REG_TABLE (REG_C0) },
2583   { REG_TABLE (REG_C1) },
2584   { "retT",             { Iw, BND }, 0 },
2585   { "retT",             { BND }, 0 },
2586   { X86_64_TABLE (X86_64_C4) },
2587   { X86_64_TABLE (X86_64_C5) },
2588   { REG_TABLE (REG_C6) },
2589   { REG_TABLE (REG_C7) },
2590   /* c8 */
2591   { "enterT",           { Iw, Ib }, 0 },
2592   { "leaveT",           { XX }, 0 },
2593   { "Jret{|f}P",        { Iw }, 0 },
2594   { "Jret{|f}P",        { XX }, 0 },
2595   { "int3",             { XX }, 0 },
2596   { "int",              { Ib }, 0 },
2597   { X86_64_TABLE (X86_64_CE) },
2598   { "iret%LP",          { XX }, 0 },
2599   /* d0 */
2600   { REG_TABLE (REG_D0) },
2601   { REG_TABLE (REG_D1) },
2602   { REG_TABLE (REG_D2) },
2603   { REG_TABLE (REG_D3) },
2604   { X86_64_TABLE (X86_64_D4) },
2605   { X86_64_TABLE (X86_64_D5) },
2606   { Bad_Opcode },
2607   { "xlat",             { DSBX }, 0 },
2608   /* d8 */
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   /* e0 */
2618   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "inB",              { AL, Ib }, 0 },
2623   { "inG",              { zAX, Ib }, 0 },
2624   { "outB",             { Ib, AL }, 0 },
2625   { "outG",             { Ib, zAX }, 0 },
2626   /* e8 */
2627   { X86_64_TABLE (X86_64_E8) },
2628   { X86_64_TABLE (X86_64_E9) },
2629   { X86_64_TABLE (X86_64_EA) },
2630   { "jmp",              { Jb, BND }, 0 },
2631   { "inB",              { AL, indirDX }, 0 },
2632   { "inG",              { zAX, indirDX }, 0 },
2633   { "outB",             { indirDX, AL }, 0 },
2634   { "outG",             { indirDX, zAX }, 0 },
2635   /* f0 */
2636   { Bad_Opcode },       /* lock prefix */
2637   { "icebp",            { XX }, 0 },
2638   { Bad_Opcode },       /* repne */
2639   { Bad_Opcode },       /* repz */
2640   { "hlt",              { XX }, 0 },
2641   { "cmc",              { XX }, 0 },
2642   { REG_TABLE (REG_F6) },
2643   { REG_TABLE (REG_F7) },
2644   /* f8 */
2645   { "clc",              { XX }, 0 },
2646   { "stc",              { XX }, 0 },
2647   { "cli",              { XX }, 0 },
2648   { "sti",              { XX }, 0 },
2649   { "cld",              { XX }, 0 },
2650   { "std",              { XX }, 0 },
2651   { REG_TABLE (REG_FE) },
2652   { REG_TABLE (REG_FF) },
2653 };
2654
2655 static const struct dis386 dis386_twobyte[] = {
2656   /* 00 */
2657   { REG_TABLE (REG_0F00 ) },
2658   { REG_TABLE (REG_0F01 ) },
2659   { "larS",             { Gv, Ew }, 0 },
2660   { "lslS",             { Gv, Ew }, 0 },
2661   { Bad_Opcode },
2662   { "syscall",          { XX }, 0 },
2663   { "clts",             { XX }, 0 },
2664   { "sysret%LP",                { XX }, 0 },
2665   /* 08 */
2666   { "invd",             { XX }, 0 },
2667   { PREFIX_TABLE (PREFIX_0F09) },
2668   { Bad_Opcode },
2669   { "ud2",              { XX }, 0 },
2670   { Bad_Opcode },
2671   { REG_TABLE (REG_0F0D) },
2672   { "femms",            { XX }, 0 },
2673   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2674   /* 10 */
2675   { PREFIX_TABLE (PREFIX_0F10) },
2676   { PREFIX_TABLE (PREFIX_0F11) },
2677   { PREFIX_TABLE (PREFIX_0F12) },
2678   { MOD_TABLE (MOD_0F13) },
2679   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2680   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2681   { PREFIX_TABLE (PREFIX_0F16) },
2682   { MOD_TABLE (MOD_0F17) },
2683   /* 18 */
2684   { REG_TABLE (REG_0F18) },
2685   { "nopQ",             { Ev }, 0 },
2686   { PREFIX_TABLE (PREFIX_0F1A) },
2687   { PREFIX_TABLE (PREFIX_0F1B) },
2688   { PREFIX_TABLE (PREFIX_0F1C) },
2689   { "nopQ",             { Ev }, 0 },
2690   { PREFIX_TABLE (PREFIX_0F1E) },
2691   { "nopQ",             { Ev }, 0 },
2692   /* 20 */
2693   { "movZ",             { Rm, Cm }, 0 },
2694   { "movZ",             { Rm, Dm }, 0 },
2695   { "movZ",             { Cm, Rm }, 0 },
2696   { "movZ",             { Dm, Rm }, 0 },
2697   { MOD_TABLE (MOD_0F24) },
2698   { Bad_Opcode },
2699   { MOD_TABLE (MOD_0F26) },
2700   { Bad_Opcode },
2701   /* 28 */
2702   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2703   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2704   { PREFIX_TABLE (PREFIX_0F2A) },
2705   { PREFIX_TABLE (PREFIX_0F2B) },
2706   { PREFIX_TABLE (PREFIX_0F2C) },
2707   { PREFIX_TABLE (PREFIX_0F2D) },
2708   { PREFIX_TABLE (PREFIX_0F2E) },
2709   { PREFIX_TABLE (PREFIX_0F2F) },
2710   /* 30 */
2711   { "wrmsr",            { XX }, 0 },
2712   { "rdtsc",            { XX }, 0 },
2713   { "rdmsr",            { XX }, 0 },
2714   { "rdpmc",            { XX }, 0 },
2715   { "sysenter",         { XX }, 0 },
2716   { "sysexit",          { XX }, 0 },
2717   { Bad_Opcode },
2718   { "getsec",           { XX }, 0 },
2719   /* 38 */
2720   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2721   { Bad_Opcode },
2722   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   /* 40 */
2729   { "cmovoS",           { Gv, Ev }, 0 },
2730   { "cmovnoS",          { Gv, Ev }, 0 },
2731   { "cmovbS",           { Gv, Ev }, 0 },
2732   { "cmovaeS",          { Gv, Ev }, 0 },
2733   { "cmoveS",           { Gv, Ev }, 0 },
2734   { "cmovneS",          { Gv, Ev }, 0 },
2735   { "cmovbeS",          { Gv, Ev }, 0 },
2736   { "cmovaS",           { Gv, Ev }, 0 },
2737   /* 48 */
2738   { "cmovsS",           { Gv, Ev }, 0 },
2739   { "cmovnsS",          { Gv, Ev }, 0 },
2740   { "cmovpS",           { Gv, Ev }, 0 },
2741   { "cmovnpS",          { Gv, Ev }, 0 },
2742   { "cmovlS",           { Gv, Ev }, 0 },
2743   { "cmovgeS",          { Gv, Ev }, 0 },
2744   { "cmovleS",          { Gv, Ev }, 0 },
2745   { "cmovgS",           { Gv, Ev }, 0 },
2746   /* 50 */
2747   { MOD_TABLE (MOD_0F51) },
2748   { PREFIX_TABLE (PREFIX_0F51) },
2749   { PREFIX_TABLE (PREFIX_0F52) },
2750   { PREFIX_TABLE (PREFIX_0F53) },
2751   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2752   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2753   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2754   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2755   /* 58 */
2756   { PREFIX_TABLE (PREFIX_0F58) },
2757   { PREFIX_TABLE (PREFIX_0F59) },
2758   { PREFIX_TABLE (PREFIX_0F5A) },
2759   { PREFIX_TABLE (PREFIX_0F5B) },
2760   { PREFIX_TABLE (PREFIX_0F5C) },
2761   { PREFIX_TABLE (PREFIX_0F5D) },
2762   { PREFIX_TABLE (PREFIX_0F5E) },
2763   { PREFIX_TABLE (PREFIX_0F5F) },
2764   /* 60 */
2765   { PREFIX_TABLE (PREFIX_0F60) },
2766   { PREFIX_TABLE (PREFIX_0F61) },
2767   { PREFIX_TABLE (PREFIX_0F62) },
2768   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2772   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2773   /* 68 */
2774   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2775   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2776   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2777   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2778   { PREFIX_TABLE (PREFIX_0F6C) },
2779   { PREFIX_TABLE (PREFIX_0F6D) },
2780   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F6F) },
2782   /* 70 */
2783   { PREFIX_TABLE (PREFIX_0F70) },
2784   { REG_TABLE (REG_0F71) },
2785   { REG_TABLE (REG_0F72) },
2786   { REG_TABLE (REG_0F73) },
2787   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2788   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2789   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2790   { "emms",             { XX }, PREFIX_OPCODE },
2791   /* 78 */
2792   { PREFIX_TABLE (PREFIX_0F78) },
2793   { PREFIX_TABLE (PREFIX_0F79) },
2794   { Bad_Opcode },
2795   { Bad_Opcode },
2796   { PREFIX_TABLE (PREFIX_0F7C) },
2797   { PREFIX_TABLE (PREFIX_0F7D) },
2798   { PREFIX_TABLE (PREFIX_0F7E) },
2799   { PREFIX_TABLE (PREFIX_0F7F) },
2800   /* 80 */
2801   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2806   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2809   /* 88 */
2810   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2818   /* 90 */
2819   { "seto",             { Eb }, 0 },
2820   { "setno",            { Eb }, 0 },
2821   { "setb",             { Eb }, 0 },
2822   { "setae",            { Eb }, 0 },
2823   { "sete",             { Eb }, 0 },
2824   { "setne",            { Eb }, 0 },
2825   { "setbe",            { Eb }, 0 },
2826   { "seta",             { Eb }, 0 },
2827   /* 98 */
2828   { "sets",             { Eb }, 0 },
2829   { "setns",            { Eb }, 0 },
2830   { "setp",             { Eb }, 0 },
2831   { "setnp",            { Eb }, 0 },
2832   { "setl",             { Eb }, 0 },
2833   { "setge",            { Eb }, 0 },
2834   { "setle",            { Eb }, 0 },
2835   { "setg",             { Eb }, 0 },
2836   /* a0 */
2837   { "pushT",            { fs }, 0 },
2838   { "popT",             { fs }, 0 },
2839   { "cpuid",            { XX }, 0 },
2840   { "btS",              { Ev, Gv }, 0 },
2841   { "shldS",            { Ev, Gv, Ib }, 0 },
2842   { "shldS",            { Ev, Gv, CL }, 0 },
2843   { REG_TABLE (REG_0FA6) },
2844   { REG_TABLE (REG_0FA7) },
2845   /* a8 */
2846   { "pushT",            { gs }, 0 },
2847   { "popT",             { gs }, 0 },
2848   { "rsm",              { XX }, 0 },
2849   { "btsS",             { Evh1, Gv }, 0 },
2850   { "shrdS",            { Ev, Gv, Ib }, 0 },
2851   { "shrdS",            { Ev, Gv, CL }, 0 },
2852   { REG_TABLE (REG_0FAE) },
2853   { "imulS",            { Gv, Ev }, 0 },
2854   /* b0 */
2855   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2856   { "cmpxchgS",         { Evh1, Gv }, 0 },
2857   { MOD_TABLE (MOD_0FB2) },
2858   { "btrS",             { Evh1, Gv }, 0 },
2859   { MOD_TABLE (MOD_0FB4) },
2860   { MOD_TABLE (MOD_0FB5) },
2861   { "movz{bR|x}",       { Gv, Eb }, 0 },
2862   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2863   /* b8 */
2864   { PREFIX_TABLE (PREFIX_0FB8) },
2865   { "ud1S",             { Gv, Ev }, 0 },
2866   { REG_TABLE (REG_0FBA) },
2867   { "btcS",             { Evh1, Gv }, 0 },
2868   { PREFIX_TABLE (PREFIX_0FBC) },
2869   { PREFIX_TABLE (PREFIX_0FBD) },
2870   { "movs{bR|x}",       { Gv, Eb }, 0 },
2871   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2872   /* c0 */
2873   { "xaddB",            { Ebh1, Gb }, 0 },
2874   { "xaddS",            { Evh1, Gv }, 0 },
2875   { PREFIX_TABLE (PREFIX_0FC2) },
2876   { MOD_TABLE (MOD_0FC3) },
2877   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2878   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2879   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2880   { REG_TABLE (REG_0FC7) },
2881   /* c8 */
2882   { "bswap",            { RMeAX }, 0 },
2883   { "bswap",            { RMeCX }, 0 },
2884   { "bswap",            { RMeDX }, 0 },
2885   { "bswap",            { RMeBX }, 0 },
2886   { "bswap",            { RMeSP }, 0 },
2887   { "bswap",            { RMeBP }, 0 },
2888   { "bswap",            { RMeSI }, 0 },
2889   { "bswap",            { RMeDI }, 0 },
2890   /* d0 */
2891   { PREFIX_TABLE (PREFIX_0FD0) },
2892   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2893   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2894   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2895   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2896   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2897   { PREFIX_TABLE (PREFIX_0FD6) },
2898   { MOD_TABLE (MOD_0FD7) },
2899   /* d8 */
2900   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2901   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2902   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2903   { "pand",             { MX, EM }, PREFIX_OPCODE },
2904   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2905   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2906   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2907   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2908   /* e0 */
2909   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2910   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2911   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2912   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2913   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2914   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2915   { PREFIX_TABLE (PREFIX_0FE6) },
2916   { PREFIX_TABLE (PREFIX_0FE7) },
2917   /* e8 */
2918   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2919   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2920   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2921   { "por",              { MX, EM }, PREFIX_OPCODE },
2922   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2923   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2926   /* f0 */
2927   { PREFIX_TABLE (PREFIX_0FF0) },
2928   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2929   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2930   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2931   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2932   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2933   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2934   { PREFIX_TABLE (PREFIX_0FF7) },
2935   /* f8 */
2936   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2943   { "ud0S",             { Gv, Ev }, 0 },
2944 };
2945
2946 static const unsigned char onebyte_has_modrm[256] = {
2947   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2948   /*       -------------------------------        */
2949   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2950   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2951   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2952   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2953   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2954   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2955   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2956   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2957   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2958   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2959   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2960   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2961   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2962   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2963   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2964   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2965   /*       -------------------------------        */
2966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2967 };
2968
2969 static const unsigned char twobyte_has_modrm[256] = {
2970   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2971   /*       -------------------------------        */
2972   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2973   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2974   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2975   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2976   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2977   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2978   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2979   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2980   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2981   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2982   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2983   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2984   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2985   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2986   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2987   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2988   /*       -------------------------------        */
2989   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2990 };
2991
2992 static char obuf[100];
2993 static char *obufp;
2994 static char *mnemonicendp;
2995 static char scratchbuf[100];
2996 static unsigned char *start_codep;
2997 static unsigned char *insn_codep;
2998 static unsigned char *codep;
2999 static unsigned char *end_codep;
3000 static int last_lock_prefix;
3001 static int last_repz_prefix;
3002 static int last_repnz_prefix;
3003 static int last_data_prefix;
3004 static int last_addr_prefix;
3005 static int last_rex_prefix;
3006 static int last_seg_prefix;
3007 static int fwait_prefix;
3008 /* The active segment register prefix.  */
3009 static int active_seg_prefix;
3010 #define MAX_CODE_LENGTH 15
3011 /* We can up to 14 prefixes since the maximum instruction length is
3012    15bytes.  */
3013 static int all_prefixes[MAX_CODE_LENGTH - 1];
3014 static disassemble_info *the_info;
3015 static struct
3016   {
3017     int mod;
3018     int reg;
3019     int rm;
3020   }
3021 modrm;
3022 static unsigned char need_modrm;
3023 static struct
3024   {
3025     int scale;
3026     int index;
3027     int base;
3028   }
3029 sib;
3030 static struct
3031   {
3032     int register_specifier;
3033     int length;
3034     int prefix;
3035     int w;
3036     int evex;
3037     int r;
3038     int v;
3039     int mask_register_specifier;
3040     int zeroing;
3041     int ll;
3042     int b;
3043   }
3044 vex;
3045 static unsigned char need_vex;
3046 static unsigned char need_vex_reg;
3047 static unsigned char vex_w_done;
3048
3049 struct op
3050   {
3051     const char *name;
3052     unsigned int len;
3053   };
3054
3055 /* If we are accessing mod/rm/reg without need_modrm set, then the
3056    values are stale.  Hitting this abort likely indicates that you
3057    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3058 #define MODRM_CHECK  if (!need_modrm) abort ()
3059
3060 static const char **names64;
3061 static const char **names32;
3062 static const char **names16;
3063 static const char **names8;
3064 static const char **names8rex;
3065 static const char **names_seg;
3066 static const char *index64;
3067 static const char *index32;
3068 static const char **index16;
3069 static const char **names_bnd;
3070
3071 static const char *intel_names64[] = {
3072   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3073   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3074 };
3075 static const char *intel_names32[] = {
3076   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3077   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3078 };
3079 static const char *intel_names16[] = {
3080   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3081   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3082 };
3083 static const char *intel_names8[] = {
3084   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3085 };
3086 static const char *intel_names8rex[] = {
3087   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3088   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3089 };
3090 static const char *intel_names_seg[] = {
3091   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3092 };
3093 static const char *intel_index64 = "riz";
3094 static const char *intel_index32 = "eiz";
3095 static const char *intel_index16[] = {
3096   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3097 };
3098
3099 static const char *att_names64[] = {
3100   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3101   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3102 };
3103 static const char *att_names32[] = {
3104   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3105   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3106 };
3107 static const char *att_names16[] = {
3108   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3109   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3110 };
3111 static const char *att_names8[] = {
3112   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3113 };
3114 static const char *att_names8rex[] = {
3115   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3116   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3117 };
3118 static const char *att_names_seg[] = {
3119   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3120 };
3121 static const char *att_index64 = "%riz";
3122 static const char *att_index32 = "%eiz";
3123 static const char *att_index16[] = {
3124   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3125 };
3126
3127 static const char **names_mm;
3128 static const char *intel_names_mm[] = {
3129   "mm0", "mm1", "mm2", "mm3",
3130   "mm4", "mm5", "mm6", "mm7"
3131 };
3132 static const char *att_names_mm[] = {
3133   "%mm0", "%mm1", "%mm2", "%mm3",
3134   "%mm4", "%mm5", "%mm6", "%mm7"
3135 };
3136
3137 static const char *intel_names_bnd[] = {
3138   "bnd0", "bnd1", "bnd2", "bnd3"
3139 };
3140
3141 static const char *att_names_bnd[] = {
3142   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3143 };
3144
3145 static const char **names_xmm;
3146 static const char *intel_names_xmm[] = {
3147   "xmm0", "xmm1", "xmm2", "xmm3",
3148   "xmm4", "xmm5", "xmm6", "xmm7",
3149   "xmm8", "xmm9", "xmm10", "xmm11",
3150   "xmm12", "xmm13", "xmm14", "xmm15",
3151   "xmm16", "xmm17", "xmm18", "xmm19",
3152   "xmm20", "xmm21", "xmm22", "xmm23",
3153   "xmm24", "xmm25", "xmm26", "xmm27",
3154   "xmm28", "xmm29", "xmm30", "xmm31"
3155 };
3156 static const char *att_names_xmm[] = {
3157   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3158   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3159   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3160   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3161   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3162   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3163   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3164   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3165 };
3166
3167 static const char **names_ymm;
3168 static const char *intel_names_ymm[] = {
3169   "ymm0", "ymm1", "ymm2", "ymm3",
3170   "ymm4", "ymm5", "ymm6", "ymm7",
3171   "ymm8", "ymm9", "ymm10", "ymm11",
3172   "ymm12", "ymm13", "ymm14", "ymm15",
3173   "ymm16", "ymm17", "ymm18", "ymm19",
3174   "ymm20", "ymm21", "ymm22", "ymm23",
3175   "ymm24", "ymm25", "ymm26", "ymm27",
3176   "ymm28", "ymm29", "ymm30", "ymm31"
3177 };
3178 static const char *att_names_ymm[] = {
3179   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3180   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3181   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3182   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3183   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3184   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3185   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3186   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3187 };
3188
3189 static const char **names_zmm;
3190 static const char *intel_names_zmm[] = {
3191   "zmm0", "zmm1", "zmm2", "zmm3",
3192   "zmm4", "zmm5", "zmm6", "zmm7",
3193   "zmm8", "zmm9", "zmm10", "zmm11",
3194   "zmm12", "zmm13", "zmm14", "zmm15",
3195   "zmm16", "zmm17", "zmm18", "zmm19",
3196   "zmm20", "zmm21", "zmm22", "zmm23",
3197   "zmm24", "zmm25", "zmm26", "zmm27",
3198   "zmm28", "zmm29", "zmm30", "zmm31"
3199 };
3200 static const char *att_names_zmm[] = {
3201   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3202   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3203   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3204   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3205   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3206   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3207   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3208   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3209 };
3210
3211 static const char **names_mask;
3212 static const char *intel_names_mask[] = {
3213   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3214 };
3215 static const char *att_names_mask[] = {
3216   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3217 };
3218
3219 static const char *names_rounding[] =
3220 {
3221   "{rn-sae}",
3222   "{rd-sae}",
3223   "{ru-sae}",
3224   "{rz-sae}"
3225 };
3226
3227 static const struct dis386 reg_table[][8] = {
3228   /* REG_80 */
3229   {
3230     { "addA",   { Ebh1, Ib }, 0 },
3231     { "orA",    { Ebh1, Ib }, 0 },
3232     { "adcA",   { Ebh1, Ib }, 0 },
3233     { "sbbA",   { Ebh1, Ib }, 0 },
3234     { "andA",   { Ebh1, Ib }, 0 },
3235     { "subA",   { Ebh1, Ib }, 0 },
3236     { "xorA",   { Ebh1, Ib }, 0 },
3237     { "cmpA",   { Eb, Ib }, 0 },
3238   },
3239   /* REG_81 */
3240   {
3241     { "addQ",   { Evh1, Iv }, 0 },
3242     { "orQ",    { Evh1, Iv }, 0 },
3243     { "adcQ",   { Evh1, Iv }, 0 },
3244     { "sbbQ",   { Evh1, Iv }, 0 },
3245     { "andQ",   { Evh1, Iv }, 0 },
3246     { "subQ",   { Evh1, Iv }, 0 },
3247     { "xorQ",   { Evh1, Iv }, 0 },
3248     { "cmpQ",   { Ev, Iv }, 0 },
3249   },
3250   /* REG_83 */
3251   {
3252     { "addQ",   { Evh1, sIb }, 0 },
3253     { "orQ",    { Evh1, sIb }, 0 },
3254     { "adcQ",   { Evh1, sIb }, 0 },
3255     { "sbbQ",   { Evh1, sIb }, 0 },
3256     { "andQ",   { Evh1, sIb }, 0 },
3257     { "subQ",   { Evh1, sIb }, 0 },
3258     { "xorQ",   { Evh1, sIb }, 0 },
3259     { "cmpQ",   { Ev, sIb }, 0 },
3260   },
3261   /* REG_8F */
3262   {
3263     { "popU",   { stackEv }, 0 },
3264     { XOP_8F_TABLE (XOP_09) },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { XOP_8F_TABLE (XOP_09) },
3269   },
3270   /* REG_C0 */
3271   {
3272     { "rolA",   { Eb, Ib }, 0 },
3273     { "rorA",   { Eb, Ib }, 0 },
3274     { "rclA",   { Eb, Ib }, 0 },
3275     { "rcrA",   { Eb, Ib }, 0 },
3276     { "shlA",   { Eb, Ib }, 0 },
3277     { "shrA",   { Eb, Ib }, 0 },
3278     { "shlA",   { Eb, Ib }, 0 },
3279     { "sarA",   { Eb, Ib }, 0 },
3280   },
3281   /* REG_C1 */
3282   {
3283     { "rolQ",   { Ev, Ib }, 0 },
3284     { "rorQ",   { Ev, Ib }, 0 },
3285     { "rclQ",   { Ev, Ib }, 0 },
3286     { "rcrQ",   { Ev, Ib }, 0 },
3287     { "shlQ",   { Ev, Ib }, 0 },
3288     { "shrQ",   { Ev, Ib }, 0 },
3289     { "shlQ",   { Ev, Ib }, 0 },
3290     { "sarQ",   { Ev, Ib }, 0 },
3291   },
3292   /* REG_C6 */
3293   {
3294     { "movA",   { Ebh3, Ib }, 0 },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { MOD_TABLE (MOD_C6_REG_7) },
3302   },
3303   /* REG_C7 */
3304   {
3305     { "movQ",   { Evh3, Iv }, 0 },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_C7_REG_7) },
3313   },
3314   /* REG_D0 */
3315   {
3316     { "rolA",   { Eb, I1 }, 0 },
3317     { "rorA",   { Eb, I1 }, 0 },
3318     { "rclA",   { Eb, I1 }, 0 },
3319     { "rcrA",   { Eb, I1 }, 0 },
3320     { "shlA",   { Eb, I1 }, 0 },
3321     { "shrA",   { Eb, I1 }, 0 },
3322     { "shlA",   { Eb, I1 }, 0 },
3323     { "sarA",   { Eb, I1 }, 0 },
3324   },
3325   /* REG_D1 */
3326   {
3327     { "rolQ",   { Ev, I1 }, 0 },
3328     { "rorQ",   { Ev, I1 }, 0 },
3329     { "rclQ",   { Ev, I1 }, 0 },
3330     { "rcrQ",   { Ev, I1 }, 0 },
3331     { "shlQ",   { Ev, I1 }, 0 },
3332     { "shrQ",   { Ev, I1 }, 0 },
3333     { "shlQ",   { Ev, I1 }, 0 },
3334     { "sarQ",   { Ev, I1 }, 0 },
3335   },
3336   /* REG_D2 */
3337   {
3338     { "rolA",   { Eb, CL }, 0 },
3339     { "rorA",   { Eb, CL }, 0 },
3340     { "rclA",   { Eb, CL }, 0 },
3341     { "rcrA",   { Eb, CL }, 0 },
3342     { "shlA",   { Eb, CL }, 0 },
3343     { "shrA",   { Eb, CL }, 0 },
3344     { "shlA",   { Eb, CL }, 0 },
3345     { "sarA",   { Eb, CL }, 0 },
3346   },
3347   /* REG_D3 */
3348   {
3349     { "rolQ",   { Ev, CL }, 0 },
3350     { "rorQ",   { Ev, CL }, 0 },
3351     { "rclQ",   { Ev, CL }, 0 },
3352     { "rcrQ",   { Ev, CL }, 0 },
3353     { "shlQ",   { Ev, CL }, 0 },
3354     { "shrQ",   { Ev, CL }, 0 },
3355     { "shlQ",   { Ev, CL }, 0 },
3356     { "sarQ",   { Ev, CL }, 0 },
3357   },
3358   /* REG_F6 */
3359   {
3360     { "testA",  { Eb, Ib }, 0 },
3361     { "testA",  { Eb, Ib }, 0 },
3362     { "notA",   { Ebh1 }, 0 },
3363     { "negA",   { Ebh1 }, 0 },
3364     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3365     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3366     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3367     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3368   },
3369   /* REG_F7 */
3370   {
3371     { "testQ",  { Ev, Iv }, 0 },
3372     { "testQ",  { Ev, Iv }, 0 },
3373     { "notQ",   { Evh1 }, 0 },
3374     { "negQ",   { Evh1 }, 0 },
3375     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3376     { "imulQ",  { Ev }, 0 },
3377     { "divQ",   { Ev }, 0 },
3378     { "idivQ",  { Ev }, 0 },
3379   },
3380   /* REG_FE */
3381   {
3382     { "incA",   { Ebh1 }, 0 },
3383     { "decA",   { Ebh1 }, 0 },
3384   },
3385   /* REG_FF */
3386   {
3387     { "incQ",   { Evh1 }, 0 },
3388     { "decQ",   { Evh1 }, 0 },
3389     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3390     { MOD_TABLE (MOD_FF_REG_3) },
3391     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3392     { MOD_TABLE (MOD_FF_REG_5) },
3393     { "pushU",  { stackEv }, 0 },
3394     { Bad_Opcode },
3395   },
3396   /* REG_0F00 */
3397   {
3398     { "sldtD",  { Sv }, 0 },
3399     { "strD",   { Sv }, 0 },
3400     { "lldt",   { Ew }, 0 },
3401     { "ltr",    { Ew }, 0 },
3402     { "verr",   { Ew }, 0 },
3403     { "verw",   { Ew }, 0 },
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406   },
3407   /* REG_0F01 */
3408   {
3409     { MOD_TABLE (MOD_0F01_REG_0) },
3410     { MOD_TABLE (MOD_0F01_REG_1) },
3411     { MOD_TABLE (MOD_0F01_REG_2) },
3412     { MOD_TABLE (MOD_0F01_REG_3) },
3413     { "smswD",  { Sv }, 0 },
3414     { MOD_TABLE (MOD_0F01_REG_5) },
3415     { "lmsw",   { Ew }, 0 },
3416     { MOD_TABLE (MOD_0F01_REG_7) },
3417   },
3418   /* REG_0F0D */
3419   {
3420     { "prefetch",       { Mb }, 0 },
3421     { "prefetchw",      { Mb }, 0 },
3422     { "prefetchwt1",    { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428   },
3429   /* REG_0F18 */
3430   {
3431     { MOD_TABLE (MOD_0F18_REG_0) },
3432     { MOD_TABLE (MOD_0F18_REG_1) },
3433     { MOD_TABLE (MOD_0F18_REG_2) },
3434     { MOD_TABLE (MOD_0F18_REG_3) },
3435     { MOD_TABLE (MOD_0F18_REG_4) },
3436     { MOD_TABLE (MOD_0F18_REG_5) },
3437     { MOD_TABLE (MOD_0F18_REG_6) },
3438     { MOD_TABLE (MOD_0F18_REG_7) },
3439   },
3440   /* REG_0F1C_P_0_MOD_0 */
3441   {
3442     { "cldemote",       { Mb }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450   },
3451   /* REG_0F1E_P_1_MOD_3 */
3452   {
3453     { "nopQ",           { Ev }, 0 },
3454     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3461   },
3462   /* REG_0F71 */
3463   {
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F71_REG_2) },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0F71_REG_4) },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F71_REG_6) },
3471   },
3472   /* REG_0F72 */
3473   {
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F72_REG_2) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F72_REG_4) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F72_REG_6) },
3481   },
3482   /* REG_0F73 */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_0F73_REG_2) },
3487     { MOD_TABLE (MOD_0F73_REG_3) },
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F73_REG_6) },
3491     { MOD_TABLE (MOD_0F73_REG_7) },
3492   },
3493   /* REG_0FA6 */
3494   {
3495     { "montmul",        { { OP_0f07, 0 } }, 0 },
3496     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3497     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3498   },
3499   /* REG_0FA7 */
3500   {
3501     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3507   },
3508   /* REG_0FAE */
3509   {
3510     { MOD_TABLE (MOD_0FAE_REG_0) },
3511     { MOD_TABLE (MOD_0FAE_REG_1) },
3512     { MOD_TABLE (MOD_0FAE_REG_2) },
3513     { MOD_TABLE (MOD_0FAE_REG_3) },
3514     { MOD_TABLE (MOD_0FAE_REG_4) },
3515     { MOD_TABLE (MOD_0FAE_REG_5) },
3516     { MOD_TABLE (MOD_0FAE_REG_6) },
3517     { MOD_TABLE (MOD_0FAE_REG_7) },
3518   },
3519   /* REG_0FBA */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { "btQ",    { Ev, Ib }, 0 },
3526     { "btsQ",   { Evh1, Ib }, 0 },
3527     { "btrQ",   { Evh1, Ib }, 0 },
3528     { "btcQ",   { Evh1, Ib }, 0 },
3529   },
3530   /* REG_0FC7 */
3531   {
3532     { Bad_Opcode },
3533     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0FC7_REG_3) },
3536     { MOD_TABLE (MOD_0FC7_REG_4) },
3537     { MOD_TABLE (MOD_0FC7_REG_5) },
3538     { MOD_TABLE (MOD_0FC7_REG_6) },
3539     { MOD_TABLE (MOD_0FC7_REG_7) },
3540   },
3541   /* REG_VEX_0F71 */
3542   {
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3550   },
3551   /* REG_VEX_0F72 */
3552   {
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3560   },
3561   /* REG_VEX_0F73 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3566     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3571   },
3572   /* REG_VEX_0FAE */
3573   {
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3577     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3578   },
3579   /* REG_VEX_0F38F3 */
3580   {
3581     { Bad_Opcode },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3585   },
3586   /* REG_XOP_LWPCB */
3587   {
3588     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3589     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3590   },
3591   /* REG_XOP_LWP */
3592   {
3593     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3594     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3595   },
3596   /* REG_XOP_TBM_01 */
3597   {
3598     { Bad_Opcode },
3599     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3606   },
3607   /* REG_XOP_TBM_02 */
3608   {
3609     { Bad_Opcode },
3610     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3616   },
3617
3618 #include "i386-dis-evex-reg.h"
3619 };
3620
3621 static const struct dis386 prefix_table[][4] = {
3622   /* PREFIX_90 */
3623   {
3624     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3625     { "pause", { XX }, 0 },
3626     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3627     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3628   },
3629
3630   /* PREFIX_0F01_REG_5_MOD_0 */
3631   {
3632     { Bad_Opcode },
3633     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3637   {
3638     { Bad_Opcode },
3639     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3643   {
3644     { Bad_Opcode },
3645     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3649   {
3650     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3651   },
3652
3653   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3654   {
3655     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
3656   },
3657
3658   /* PREFIX_0F09 */
3659   {
3660     { "wbinvd",   { XX }, 0 },
3661     { "wbnoinvd", { XX }, 0 },
3662   },
3663
3664   /* PREFIX_0F10 */
3665   {
3666     { "movups", { XM, EXx }, PREFIX_OPCODE },
3667     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3668     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3669     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3670   },
3671
3672   /* PREFIX_0F11 */
3673   {
3674     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3675     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3676     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3677     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_0F12 */
3681   {
3682     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3683     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3684     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3685     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F16 */
3689   {
3690     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3691     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3692     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3693   },
3694
3695   /* PREFIX_0F1A */
3696   {
3697     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3698     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3699     { "bndmov", { Gbnd, Ebnd }, 0 },
3700     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3701   },
3702
3703   /* PREFIX_0F1B */
3704   {
3705     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3706     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3707     { "bndmov", { EbndS, Gbnd }, 0 },
3708     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3709   },
3710
3711   /* PREFIX_0F1C */
3712   {
3713     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3714     { "nopQ",   { Ev }, PREFIX_OPCODE },
3715     { "nopQ",   { Ev }, PREFIX_OPCODE },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F1E */
3720   {
3721     { "nopQ",   { Ev }, PREFIX_OPCODE },
3722     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725   },
3726
3727   /* PREFIX_0F2A */
3728   {
3729     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3730     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3731     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3733   },
3734
3735   /* PREFIX_0F2B */
3736   {
3737     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3741   },
3742
3743   /* PREFIX_0F2C */
3744   {
3745     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3746     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3747     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3748     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F2D */
3752   {
3753     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3755     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F2E */
3760   {
3761     { "ucomiss",{ XM, EXd }, 0 },
3762     { Bad_Opcode },
3763     { "ucomisd",{ XM, EXq }, 0 },
3764   },
3765
3766   /* PREFIX_0F2F */
3767   {
3768     { "comiss", { XM, EXd }, 0 },
3769     { Bad_Opcode },
3770     { "comisd", { XM, EXq }, 0 },
3771   },
3772
3773   /* PREFIX_0F51 */
3774   {
3775     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3776     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3777     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F52 */
3782   {
3783     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3784     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F53 */
3788   {
3789     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3790     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3791   },
3792
3793   /* PREFIX_0F58 */
3794   {
3795     { "addps", { XM, EXx }, PREFIX_OPCODE },
3796     { "addss", { XM, EXd }, PREFIX_OPCODE },
3797     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3798     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F59 */
3802   {
3803     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3804     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3805     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F5A */
3810   {
3811     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3812     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3813     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3814     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F5B */
3818   {
3819     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3820     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3821     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3822   },
3823
3824   /* PREFIX_0F5C */
3825   {
3826     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3827     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3828     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F5D */
3833   {
3834     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3835     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3836     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F5E */
3841   {
3842     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3843     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3844     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F5F */
3849   {
3850     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3851     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3852     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F60 */
3857   {
3858     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3859     { Bad_Opcode },
3860     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F61 */
3864   {
3865     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3866     { Bad_Opcode },
3867     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F62 */
3871   {
3872     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3873     { Bad_Opcode },
3874     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F6C */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F6D */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F6F */
3892   {
3893     { "movq",   { MX, EM }, PREFIX_OPCODE },
3894     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3895     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F70 */
3899   {
3900     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3901     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3902     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3903     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F73_REG_3 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "psrldq", { XS, Ib }, 0 },
3911   },
3912
3913   /* PREFIX_0F73_REG_7 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { "pslldq", { XS, Ib }, 0 },
3918   },
3919
3920   /* PREFIX_0F78 */
3921   {
3922     {"vmread",  { Em, Gm }, 0 },
3923     { Bad_Opcode },
3924     {"extrq",   { XS, Ib, Ib }, 0 },
3925     {"insertq", { XM, XS, Ib, Ib }, 0 },
3926   },
3927
3928   /* PREFIX_0F79 */
3929   {
3930     {"vmwrite", { Gm, Em }, 0 },
3931     { Bad_Opcode },
3932     {"extrq",   { XM, XS }, 0 },
3933     {"insertq", { XM, XS }, 0 },
3934   },
3935
3936   /* PREFIX_0F7C */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3941     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F7D */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F7E */
3953   {
3954     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3955     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3956     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F7F */
3960   {
3961     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3962     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3963     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0FAE_REG_0_MOD_3 */
3967   {
3968     { Bad_Opcode },
3969     { "rdfsbase", { Ev }, 0 },
3970   },
3971
3972   /* PREFIX_0FAE_REG_1_MOD_3 */
3973   {
3974     { Bad_Opcode },
3975     { "rdgsbase", { Ev }, 0 },
3976   },
3977
3978   /* PREFIX_0FAE_REG_2_MOD_3 */
3979   {
3980     { Bad_Opcode },
3981     { "wrfsbase", { Ev }, 0 },
3982   },
3983
3984   /* PREFIX_0FAE_REG_3_MOD_3 */
3985   {
3986     { Bad_Opcode },
3987     { "wrgsbase", { Ev }, 0 },
3988   },
3989
3990   /* PREFIX_0FAE_REG_4_MOD_0 */
3991   {
3992     { "xsave",  { FXSAVE }, 0 },
3993     { "ptwrite%LQ", { Edq }, 0 },
3994   },
3995
3996   /* PREFIX_0FAE_REG_4_MOD_3 */
3997   {
3998     { Bad_Opcode },
3999     { "ptwrite%LQ", { Edq }, 0 },
4000   },
4001
4002   /* PREFIX_0FAE_REG_5_MOD_0 */
4003   {
4004     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4005   },
4006
4007   /* PREFIX_0FAE_REG_5_MOD_3 */
4008   {
4009     { "lfence",         { Skip_MODRM }, 0 },
4010     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0FAE_REG_6_MOD_0 */
4014   {
4015     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4016     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4017     { "clwb",   { Mb }, PREFIX_OPCODE },
4018   },
4019
4020   /* PREFIX_0FAE_REG_6_MOD_3 */
4021   {
4022     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4023     { "umonitor",       { Eva }, PREFIX_OPCODE },
4024     { "tpause", { Edq }, PREFIX_OPCODE },
4025     { "umwait", { Edq }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0FAE_REG_7_MOD_0 */
4029   {
4030     { "clflush",        { Mb }, 0 },
4031     { Bad_Opcode },
4032     { "clflushopt",     { Mb }, 0 },
4033   },
4034
4035   /* PREFIX_0FB8 */
4036   {
4037     { Bad_Opcode },
4038     { "popcntS", { Gv, Ev }, 0 },
4039   },
4040
4041   /* PREFIX_0FBC */
4042   {
4043     { "bsfS",   { Gv, Ev }, 0 },
4044     { "tzcntS", { Gv, Ev }, 0 },
4045     { "bsfS",   { Gv, Ev }, 0 },
4046   },
4047
4048   /* PREFIX_0FBD */
4049   {
4050     { "bsrS",   { Gv, Ev }, 0 },
4051     { "lzcntS", { Gv, Ev }, 0 },
4052     { "bsrS",   { Gv, Ev }, 0 },
4053   },
4054
4055   /* PREFIX_0FC2 */
4056   {
4057     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4058     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4059     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4060     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0FC3_MOD_0 */
4064   {
4065     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0FC7_REG_6_MOD_0 */
4069   {
4070     { "vmptrld",{ Mq }, 0 },
4071     { "vmxon",  { Mq }, 0 },
4072     { "vmclear",{ Mq }, 0 },
4073   },
4074
4075   /* PREFIX_0FC7_REG_6_MOD_3 */
4076   {
4077     { "rdrand", { Ev }, 0 },
4078     { Bad_Opcode },
4079     { "rdrand", { Ev }, 0 }
4080   },
4081
4082   /* PREFIX_0FC7_REG_7_MOD_3 */
4083   {
4084     { "rdseed", { Ev }, 0 },
4085     { "rdpid",  { Em }, 0 },
4086     { "rdseed", { Ev }, 0 },
4087   },
4088
4089   /* PREFIX_0FD0 */
4090   {
4091     { Bad_Opcode },
4092     { Bad_Opcode },
4093     { "addsubpd", { XM, EXx }, 0 },
4094     { "addsubps", { XM, EXx }, 0 },
4095   },
4096
4097   /* PREFIX_0FD6 */
4098   {
4099     { Bad_Opcode },
4100     { "movq2dq",{ XM, MS }, 0 },
4101     { "movq",   { EXqS, XM }, 0 },
4102     { "movdq2q",{ MX, XS }, 0 },
4103   },
4104
4105   /* PREFIX_0FE6 */
4106   {
4107     { Bad_Opcode },
4108     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4109     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4110     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0FE7 */
4114   {
4115     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4116     { Bad_Opcode },
4117     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4118   },
4119
4120   /* PREFIX_0FF0 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4126   },
4127
4128   /* PREFIX_0FF7 */
4129   {
4130     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4131     { Bad_Opcode },
4132     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3810 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3814 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3815 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3817 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3820 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3821 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3822 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F3823 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F3824 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3825 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3828 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3829 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F382A */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4224   },
4225
4226   /* PREFIX_0F382B */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3830 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3831 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3832 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3833 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3834 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3835 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F3837 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F3838 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F3839 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383A */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F383B */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F383C */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F383D */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F383E */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F383F */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F3840 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F3841 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F3880 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F3881 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3882 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38C8 */
4374   {
4375     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38C9 */
4379   {
4380     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38CA */
4384   {
4385     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38CB */
4389   {
4390     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38CC */
4394   {
4395     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38CD */
4399   {
4400     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38CF */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38DB */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38DC */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38DD */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38DE */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F38DF */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F38F0 */
4446   {
4447     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4448     { Bad_Opcode },
4449     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F38F1 */
4454   {
4455     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4456     { Bad_Opcode },
4457     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F38F5 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4466   },
4467
4468   /* PREFIX_0F38F6 */
4469   {
4470     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4471     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4472     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4473     { Bad_Opcode },
4474   },
4475
4476   /* PREFIX_0F38F8 */
4477   {
4478     { Bad_Opcode },
4479     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4480     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4482   },
4483
4484   /* PREFIX_0F38F9 */
4485   {
4486     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4487   },
4488
4489   /* PREFIX_0F3A08 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A09 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A0A */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A0B */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A0C */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A0D */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A0E */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A14 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A15 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A16 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A17 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A20 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A21 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A22 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A40 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A41 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A42 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A44 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A60 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A61 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A62 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A63 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3ACC */
4644   {
4645     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3ACE */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4653   },
4654
4655   /* PREFIX_0F3ACF */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4660   },
4661
4662   /* PREFIX_0F3ADF */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_VEX_0F10 */
4670   {
4671     { "vmovups",        { XM, EXx }, 0 },
4672     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4673     { "vmovupd",        { XM, EXx }, 0 },
4674     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4675   },
4676
4677   /* PREFIX_VEX_0F11 */
4678   {
4679     { "vmovups",        { EXxS, XM }, 0 },
4680     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4681     { "vmovupd",        { EXxS, XM }, 0 },
4682     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4683   },
4684
4685   /* PREFIX_VEX_0F12 */
4686   {
4687     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4688     { "vmovsldup",      { XM, EXx }, 0 },
4689     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4690     { "vmovddup",       { XM, EXymmq }, 0 },
4691   },
4692
4693   /* PREFIX_VEX_0F16 */
4694   {
4695     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4696     { "vmovshdup",      { XM, EXx }, 0 },
4697     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F2A */
4701   {
4702     { Bad_Opcode },
4703     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4704     { Bad_Opcode },
4705     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F2C */
4709   {
4710     { Bad_Opcode },
4711     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4712     { Bad_Opcode },
4713     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4714   },
4715
4716   /* PREFIX_VEX_0F2D */
4717   {
4718     { Bad_Opcode },
4719     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4720     { Bad_Opcode },
4721     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4722   },
4723
4724   /* PREFIX_VEX_0F2E */
4725   {
4726     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4727     { Bad_Opcode },
4728     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4729   },
4730
4731   /* PREFIX_VEX_0F2F */
4732   {
4733     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4734     { Bad_Opcode },
4735     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4736   },
4737
4738   /* PREFIX_VEX_0F41 */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F42 */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F44 */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F45 */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F46 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F47 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F4A */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F4B */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F51 */
4795   {
4796     { "vsqrtps",        { XM, EXx }, 0 },
4797     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4798     { "vsqrtpd",        { XM, EXx }, 0 },
4799     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F52 */
4803   {
4804     { "vrsqrtps",       { XM, EXx }, 0 },
4805     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F53 */
4809   {
4810     { "vrcpps",         { XM, EXx }, 0 },
4811     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4812   },
4813
4814   /* PREFIX_VEX_0F58 */
4815   {
4816     { "vaddps",         { XM, Vex, EXx }, 0 },
4817     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4818     { "vaddpd",         { XM, Vex, EXx }, 0 },
4819     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F59 */
4823   {
4824     { "vmulps",         { XM, Vex, EXx }, 0 },
4825     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4826     { "vmulpd",         { XM, Vex, EXx }, 0 },
4827     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4828   },
4829
4830   /* PREFIX_VEX_0F5A */
4831   {
4832     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4833     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4834     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4835     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4836   },
4837
4838   /* PREFIX_VEX_0F5B */
4839   {
4840     { "vcvtdq2ps",      { XM, EXx }, 0 },
4841     { "vcvttps2dq",     { XM, EXx }, 0 },
4842     { "vcvtps2dq",      { XM, EXx }, 0 },
4843   },
4844
4845   /* PREFIX_VEX_0F5C */
4846   {
4847     { "vsubps",         { XM, Vex, EXx }, 0 },
4848     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4849     { "vsubpd",         { XM, Vex, EXx }, 0 },
4850     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4851   },
4852
4853   /* PREFIX_VEX_0F5D */
4854   {
4855     { "vminps",         { XM, Vex, EXx }, 0 },
4856     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4857     { "vminpd",         { XM, Vex, EXx }, 0 },
4858     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F5E */
4862   {
4863     { "vdivps",         { XM, Vex, EXx }, 0 },
4864     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4865     { "vdivpd",         { XM, Vex, EXx }, 0 },
4866     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F5F */
4870   {
4871     { "vmaxps",         { XM, Vex, EXx }, 0 },
4872     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4873     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4874     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F60 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F61 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F62 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F63 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F64 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F65 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F66 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F67 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F68 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F69 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F6A */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F6B */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F6C */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F6D */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F6E */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F6F */
4983   {
4984     { Bad_Opcode },
4985     { "vmovdqu",        { XM, EXx }, 0 },
4986     { "vmovdqa",        { XM, EXx }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F70 */
4990   {
4991     { Bad_Opcode },
4992     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4993     { "vpshufd",        { XM, EXx, Ib }, 0 },
4994     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F71_REG_2 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F71_REG_4 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpsraw",         { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F71_REG_6 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpsllw",         { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F72_REG_2 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsrld",         { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F72_REG_4 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpsrad",         { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F72_REG_6 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpslld",         { Vex, XS, Ib }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F73_REG_2 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F73_REG_3 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F73_REG_6 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpsllq",         { Vex, XS, Ib }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F73_REG_7 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vpslldq",        { Vex, XS, Ib }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F74 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0F75 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F76 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0F77 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5091   },
5092
5093   /* PREFIX_VEX_0F7C */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5098     { "vhaddps",        { XM, Vex, EXx }, 0 },
5099   },
5100
5101   /* PREFIX_VEX_0F7D */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5106     { "vhsubps",        { XM, Vex, EXx }, 0 },
5107   },
5108
5109   /* PREFIX_VEX_0F7E */
5110   {
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5113     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F7F */
5117   {
5118     { Bad_Opcode },
5119     { "vmovdqu",        { EXxS, XM }, 0 },
5120     { "vmovdqa",        { EXxS, XM }, 0 },
5121   },
5122
5123   /* PREFIX_VEX_0F90 */
5124   {
5125     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F91 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F92 */
5138   {
5139     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5140     { Bad_Opcode },
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5142     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5143   },
5144
5145   /* PREFIX_VEX_0F93 */
5146   {
5147     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5150     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5151   },
5152
5153   /* PREFIX_VEX_0F98 */
5154   {
5155     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5156     { Bad_Opcode },
5157     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0F99 */
5161   {
5162     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0FC2 */
5168   {
5169     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5170     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5171     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5172     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FC4 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0FC5 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0FD0 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5194     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FD1 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5202   },
5203
5204   /* PREFIX_VEX_0FD2 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FD3 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FD4 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpaddq",         { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FD5 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpmullw",        { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FD6 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FD7 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD8 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FD9 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FDA */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpminub",        { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FDB */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpand",          { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FDC */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FDD */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FDE */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FDF */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpandn",         { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE0 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpavgb",         { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FE1 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE2 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5321   },
5322
5323   /* PREFIX_VEX_0FE3 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpavgw",         { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE4 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FE5 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FE6 */
5345   {
5346     { Bad_Opcode },
5347     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5348     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5349     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FE7 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5357   },
5358
5359   /* PREFIX_VEX_0FE8 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FE9 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FEA */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpminsw",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FEB */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpor",           { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0FEC */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FED */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0FEE */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FEF */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpxor",          { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FF0 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5421   },
5422
5423   /* PREFIX_VEX_0FF1 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5428   },
5429
5430   /* PREFIX_VEX_0FF2 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5435   },
5436
5437   /* PREFIX_VEX_0FF3 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5442   },
5443
5444   /* PREFIX_VEX_0FF4 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FF5 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FF6 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FF7 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF8 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpsubb",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FF9 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpsubw",         { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0FFA */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vpsubd",         { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0FFB */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vpsubq",         { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0FFC */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vpaddb",         { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0FFD */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vpaddw",         { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0FFE */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vpaddd",         { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3800 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vpshufb",        { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3801 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vphaddw",        { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3802 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vphaddd",        { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3803 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3804 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F3805 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vphsubw",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F3806 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vphsubd",        { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F3807 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F3808 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vpsignb",        { XM, Vex, EXx }, 0 },
5582   },
5583
5584   /* PREFIX_VEX_0F3809 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { "vpsignw",        { XM, Vex, EXx }, 0 },
5589   },
5590
5591   /* PREFIX_VEX_0F380A */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { "vpsignd",        { XM, Vex, EXx }, 0 },
5596   },
5597
5598   /* PREFIX_VEX_0F380B */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5603   },
5604
5605   /* PREFIX_VEX_0F380C */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F380D */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F380E */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F380F */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3813 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5638   },
5639
5640   /* PREFIX_VEX_0F3816 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3817 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vptest",         { XM, EXx }, 0 },
5652   },
5653
5654   /* PREFIX_VEX_0F3818 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3819 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F381A */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F381C */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpabsb",         { XM, EXx }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F381D */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpabsw",         { XM, EXx }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F381E */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpabsd",         { XM, EXx }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3820 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3821 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F3822 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F3823 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F3824 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5729   },
5730
5731   /* PREFIX_VEX_0F3825 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5736   },
5737
5738   /* PREFIX_VEX_0F3828 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5743   },
5744
5745   /* PREFIX_VEX_0F3829 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5750   },
5751
5752   /* PREFIX_VEX_0F382A */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F382B */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5764   },
5765
5766   /* PREFIX_VEX_0F382C */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F382D */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382E */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F382F */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3830 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3831 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5806   },
5807
5808   /* PREFIX_VEX_0F3832 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5813   },
5814
5815   /* PREFIX_VEX_0F3833 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F3834 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F3835 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F3836 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3837 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F3838 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpminsb",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F3839 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpminsd",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F383A */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpminuw",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F383B */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpminud",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F383C */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F383D */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5890   },
5891
5892   /* PREFIX_VEX_0F383E */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5897   },
5898
5899   /* PREFIX_VEX_0F383F */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5904   },
5905
5906   /* PREFIX_VEX_0F3840 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { "vpmulld",        { XM, Vex, EXx }, 0 },
5911   },
5912
5913   /* PREFIX_VEX_0F3841 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3845 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5925   },
5926
5927   /* PREFIX_VEX_0F3846 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3847 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5939   },
5940
5941   /* PREFIX_VEX_0F3858 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3859 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F385A */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3878 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3879 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F388C */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F388E */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3890 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F3891 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F3892 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F3893 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F3896 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3897 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3898 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3899 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F389A */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F389B */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F389C */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F389D */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389E */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389F */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38A6 */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6093     { Bad_Opcode },
6094   },
6095
6096   /* PREFIX_VEX_0F38A7 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38A8 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38A9 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38AA */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38AB */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38AC */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38AD */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AE */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AF */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38B6 */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38B7 */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38B8 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38B9 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38BA */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38BB */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38BC */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38BD */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BE */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BF */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38CF */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6234   },
6235
6236   /* PREFIX_VEX_0F38DB */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6241   },
6242
6243   /* PREFIX_VEX_0F38DC */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vaesenc",        { XM, Vex, EXx }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38DD */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6255   },
6256
6257   /* PREFIX_VEX_0F38DE */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { "vaesdec",        { XM, Vex, EXx }, 0 },
6262   },
6263
6264   /* PREFIX_VEX_0F38DF */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F38F2 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F3_REG_1 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F3_REG_2 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_3 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F5 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F6 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F7 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A00 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A01 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A02 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A04 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A05 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A06 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A08 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vroundps",       { XM, EXx, Ib }, 0 },
6362   },
6363
6364   /* PREFIX_VEX_0F3A09 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vroundpd",       { XM, EXx, Ib }, 0 },
6369   },
6370
6371   /* PREFIX_VEX_0F3A0A */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6376   },
6377
6378   /* PREFIX_VEX_0F3A0B */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6383   },
6384
6385   /* PREFIX_VEX_0F3A0C */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0D */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0E */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0F */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6411   },
6412
6413   /* PREFIX_VEX_0F3A14 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A15 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A16 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A17 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A18 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A19 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A1D */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6460   },
6461
6462   /* PREFIX_VEX_0F3A20 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A21 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A22 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A30 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A31 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A32 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A33 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A38 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A39 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A40 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A41 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A42 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6544   },
6545
6546   /* PREFIX_VEX_0F3A44 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A46 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A48 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A49 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A4A */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A4B */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A4C */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A5C */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6600   },
6601
6602   /* PREFIX_VEX_0F3A5D */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6607   },
6608
6609   /* PREFIX_VEX_0F3A5E */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5F */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A60 */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6628     { Bad_Opcode },
6629   },
6630
6631   /* PREFIX_VEX_0F3A61 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A62 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A63 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A68 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A69 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6664   },
6665
6666   /* PREFIX_VEX_0F3A6A */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A6B */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6678   },
6679
6680   /* PREFIX_VEX_0F3A6C */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6D */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6E */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6F */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3A78 */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A79 */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6720   },
6721
6722   /* PREFIX_VEX_0F3A7A */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3A7B */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6734   },
6735
6736   /* PREFIX_VEX_0F3A7C */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6741     { Bad_Opcode },
6742   },
6743
6744   /* PREFIX_VEX_0F3A7D */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6749   },
6750
6751   /* PREFIX_VEX_0F3A7E */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6756   },
6757
6758   /* PREFIX_VEX_0F3A7F */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6763   },
6764
6765   /* PREFIX_VEX_0F3ACE */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6770   },
6771
6772   /* PREFIX_VEX_0F3ACF */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3ADF */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3AF0 */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6792   },
6793
6794 #include "i386-dis-evex-prefix.h"
6795 };
6796
6797 static const struct dis386 x86_64_table[][2] = {
6798   /* X86_64_06 */
6799   {
6800     { "pushP", { es }, 0 },
6801   },
6802
6803   /* X86_64_07 */
6804   {
6805     { "popP", { es }, 0 },
6806   },
6807
6808   /* X86_64_0D */
6809   {
6810     { "pushP", { cs }, 0 },
6811   },
6812
6813   /* X86_64_16 */
6814   {
6815     { "pushP", { ss }, 0 },
6816   },
6817
6818   /* X86_64_17 */
6819   {
6820     { "popP", { ss }, 0 },
6821   },
6822
6823   /* X86_64_1E */
6824   {
6825     { "pushP", { ds }, 0 },
6826   },
6827
6828   /* X86_64_1F */
6829   {
6830     { "popP", { ds }, 0 },
6831   },
6832
6833   /* X86_64_27 */
6834   {
6835     { "daa", { XX }, 0 },
6836   },
6837
6838   /* X86_64_2F */
6839   {
6840     { "das", { XX }, 0 },
6841   },
6842
6843   /* X86_64_37 */
6844   {
6845     { "aaa", { XX }, 0 },
6846   },
6847
6848   /* X86_64_3F */
6849   {
6850     { "aas", { XX }, 0 },
6851   },
6852
6853   /* X86_64_60 */
6854   {
6855     { "pushaP", { XX }, 0 },
6856   },
6857
6858   /* X86_64_61 */
6859   {
6860     { "popaP", { XX }, 0 },
6861   },
6862
6863   /* X86_64_62 */
6864   {
6865     { MOD_TABLE (MOD_62_32BIT) },
6866     { EVEX_TABLE (EVEX_0F) },
6867   },
6868
6869   /* X86_64_63 */
6870   {
6871     { "arpl", { Ew, Gw }, 0 },
6872     { "movs{lq|xd}", { Gv, Ed }, 0 },
6873   },
6874
6875   /* X86_64_6D */
6876   {
6877     { "ins{R|}", { Yzr, indirDX }, 0 },
6878     { "ins{G|}", { Yzr, indirDX }, 0 },
6879   },
6880
6881   /* X86_64_6F */
6882   {
6883     { "outs{R|}", { indirDXr, Xz }, 0 },
6884     { "outs{G|}", { indirDXr, Xz }, 0 },
6885   },
6886
6887   /* X86_64_82 */
6888   {
6889     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6890     { REG_TABLE (REG_80) },
6891   },
6892
6893   /* X86_64_9A */
6894   {
6895     { "Jcall{T|}", { Ap }, 0 },
6896   },
6897
6898   /* X86_64_C4 */
6899   {
6900     { MOD_TABLE (MOD_C4_32BIT) },
6901     { VEX_C4_TABLE (VEX_0F) },
6902   },
6903
6904   /* X86_64_C5 */
6905   {
6906     { MOD_TABLE (MOD_C5_32BIT) },
6907     { VEX_C5_TABLE (VEX_0F) },
6908   },
6909
6910   /* X86_64_CE */
6911   {
6912     { "into", { XX }, 0 },
6913   },
6914
6915   /* X86_64_D4 */
6916   {
6917     { "aam", { Ib }, 0 },
6918   },
6919
6920   /* X86_64_D5 */
6921   {
6922     { "aad", { Ib }, 0 },
6923   },
6924
6925   /* X86_64_E8 */
6926   {
6927     { "callP",          { Jv, BND }, 0 },
6928     { "call@",          { Jv, BND }, 0 }
6929   },
6930
6931   /* X86_64_E9 */
6932   {
6933     { "jmpP",           { Jv, BND }, 0 },
6934     { "jmp@",           { Jv, BND }, 0 }
6935   },
6936
6937   /* X86_64_EA */
6938   {
6939     { "Jjmp{T|}", { Ap }, 0 },
6940   },
6941
6942   /* X86_64_0F01_REG_0 */
6943   {
6944     { "sgdt{Q|IQ}", { M }, 0 },
6945     { "sgdt", { M }, 0 },
6946   },
6947
6948   /* X86_64_0F01_REG_1 */
6949   {
6950     { "sidt{Q|IQ}", { M }, 0 },
6951     { "sidt", { M }, 0 },
6952   },
6953
6954   /* X86_64_0F01_REG_2 */
6955   {
6956     { "lgdt{Q|Q}", { M }, 0 },
6957     { "lgdt", { M }, 0 },
6958   },
6959
6960   /* X86_64_0F01_REG_3 */
6961   {
6962     { "lidt{Q|Q}", { M }, 0 },
6963     { "lidt", { M }, 0 },
6964   },
6965 };
6966
6967 static const struct dis386 three_byte_table[][256] = {
6968
6969   /* THREE_BYTE_0F38 */
6970   {
6971     /* 00 */
6972     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6973     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6974     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6976     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6977     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6978     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6979     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6980     /* 08 */
6981     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6982     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6983     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6984     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 10 */
6990     { PREFIX_TABLE (PREFIX_0F3810) },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { PREFIX_TABLE (PREFIX_0F3814) },
6995     { PREFIX_TABLE (PREFIX_0F3815) },
6996     { Bad_Opcode },
6997     { PREFIX_TABLE (PREFIX_0F3817) },
6998     /* 18 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7004     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7005     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7006     { Bad_Opcode },
7007     /* 20 */
7008     { PREFIX_TABLE (PREFIX_0F3820) },
7009     { PREFIX_TABLE (PREFIX_0F3821) },
7010     { PREFIX_TABLE (PREFIX_0F3822) },
7011     { PREFIX_TABLE (PREFIX_0F3823) },
7012     { PREFIX_TABLE (PREFIX_0F3824) },
7013     { PREFIX_TABLE (PREFIX_0F3825) },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 28 */
7017     { PREFIX_TABLE (PREFIX_0F3828) },
7018     { PREFIX_TABLE (PREFIX_0F3829) },
7019     { PREFIX_TABLE (PREFIX_0F382A) },
7020     { PREFIX_TABLE (PREFIX_0F382B) },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 30 */
7026     { PREFIX_TABLE (PREFIX_0F3830) },
7027     { PREFIX_TABLE (PREFIX_0F3831) },
7028     { PREFIX_TABLE (PREFIX_0F3832) },
7029     { PREFIX_TABLE (PREFIX_0F3833) },
7030     { PREFIX_TABLE (PREFIX_0F3834) },
7031     { PREFIX_TABLE (PREFIX_0F3835) },
7032     { Bad_Opcode },
7033     { PREFIX_TABLE (PREFIX_0F3837) },
7034     /* 38 */
7035     { PREFIX_TABLE (PREFIX_0F3838) },
7036     { PREFIX_TABLE (PREFIX_0F3839) },
7037     { PREFIX_TABLE (PREFIX_0F383A) },
7038     { PREFIX_TABLE (PREFIX_0F383B) },
7039     { PREFIX_TABLE (PREFIX_0F383C) },
7040     { PREFIX_TABLE (PREFIX_0F383D) },
7041     { PREFIX_TABLE (PREFIX_0F383E) },
7042     { PREFIX_TABLE (PREFIX_0F383F) },
7043     /* 40 */
7044     { PREFIX_TABLE (PREFIX_0F3840) },
7045     { PREFIX_TABLE (PREFIX_0F3841) },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 48 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 50 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 58 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 60 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 68 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 70 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 78 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 80 */
7116     { PREFIX_TABLE (PREFIX_0F3880) },
7117     { PREFIX_TABLE (PREFIX_0F3881) },
7118     { PREFIX_TABLE (PREFIX_0F3882) },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 88 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 90 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 98 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* a0 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* a8 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* b0 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* b8 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* c0 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* c8 */
7197     { PREFIX_TABLE (PREFIX_0F38C8) },
7198     { PREFIX_TABLE (PREFIX_0F38C9) },
7199     { PREFIX_TABLE (PREFIX_0F38CA) },
7200     { PREFIX_TABLE (PREFIX_0F38CB) },
7201     { PREFIX_TABLE (PREFIX_0F38CC) },
7202     { PREFIX_TABLE (PREFIX_0F38CD) },
7203     { Bad_Opcode },
7204     { PREFIX_TABLE (PREFIX_0F38CF) },
7205     /* d0 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* d8 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { PREFIX_TABLE (PREFIX_0F38DB) },
7219     { PREFIX_TABLE (PREFIX_0F38DC) },
7220     { PREFIX_TABLE (PREFIX_0F38DD) },
7221     { PREFIX_TABLE (PREFIX_0F38DE) },
7222     { PREFIX_TABLE (PREFIX_0F38DF) },
7223     /* e0 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* e8 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* f0 */
7242     { PREFIX_TABLE (PREFIX_0F38F0) },
7243     { PREFIX_TABLE (PREFIX_0F38F1) },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { PREFIX_TABLE (PREFIX_0F38F5) },
7248     { PREFIX_TABLE (PREFIX_0F38F6) },
7249     { Bad_Opcode },
7250     /* f8 */
7251     { PREFIX_TABLE (PREFIX_0F38F8) },
7252     { PREFIX_TABLE (PREFIX_0F38F9) },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259   },
7260   /* THREE_BYTE_0F3A */
7261   {
7262     /* 00 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 08 */
7272     { PREFIX_TABLE (PREFIX_0F3A08) },
7273     { PREFIX_TABLE (PREFIX_0F3A09) },
7274     { PREFIX_TABLE (PREFIX_0F3A0A) },
7275     { PREFIX_TABLE (PREFIX_0F3A0B) },
7276     { PREFIX_TABLE (PREFIX_0F3A0C) },
7277     { PREFIX_TABLE (PREFIX_0F3A0D) },
7278     { PREFIX_TABLE (PREFIX_0F3A0E) },
7279     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7280     /* 10 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { PREFIX_TABLE (PREFIX_0F3A14) },
7286     { PREFIX_TABLE (PREFIX_0F3A15) },
7287     { PREFIX_TABLE (PREFIX_0F3A16) },
7288     { PREFIX_TABLE (PREFIX_0F3A17) },
7289     /* 18 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 20 */
7299     { PREFIX_TABLE (PREFIX_0F3A20) },
7300     { PREFIX_TABLE (PREFIX_0F3A21) },
7301     { PREFIX_TABLE (PREFIX_0F3A22) },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 28 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 30 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 38 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 40 */
7335     { PREFIX_TABLE (PREFIX_0F3A40) },
7336     { PREFIX_TABLE (PREFIX_0F3A41) },
7337     { PREFIX_TABLE (PREFIX_0F3A42) },
7338     { Bad_Opcode },
7339     { PREFIX_TABLE (PREFIX_0F3A44) },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 48 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 50 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 58 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 60 */
7371     { PREFIX_TABLE (PREFIX_0F3A60) },
7372     { PREFIX_TABLE (PREFIX_0F3A61) },
7373     { PREFIX_TABLE (PREFIX_0F3A62) },
7374     { PREFIX_TABLE (PREFIX_0F3A63) },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 68 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 70 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 78 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 80 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 88 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 90 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 98 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* a0 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* a8 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* b0 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* b8 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* c0 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* c8 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { PREFIX_TABLE (PREFIX_0F3ACC) },
7493     { Bad_Opcode },
7494     { PREFIX_TABLE (PREFIX_0F3ACE) },
7495     { PREFIX_TABLE (PREFIX_0F3ACF) },
7496     /* d0 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* d8 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { PREFIX_TABLE (PREFIX_0F3ADF) },
7514     /* e0 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* e8 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* f0 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* f8 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550   },
7551 };
7552
7553 static const struct dis386 xop_table[][256] = {
7554   /* XOP_08 */
7555   {
7556     /* 00 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 08 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 10 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 18 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 20 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 28 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 30 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 38 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 40 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 48 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 50 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 58 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 60 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 68 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 70 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 78 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 80 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     /* 88 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     /* 90 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     /* 98 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7735     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736     /* a0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     { Bad_Opcode },
7745     /* a8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* b0 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7762     { Bad_Opcode },
7763     /* b8 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* c0 */
7773     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7774     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7775     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* c8 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7787     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7790     /* d0 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* d8 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* e0 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* e8 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7826     /* f0 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* f8 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844   },
7845   /* XOP_09 */
7846   {
7847     /* 00 */
7848     { Bad_Opcode },
7849     { REG_TABLE (REG_XOP_TBM_01) },
7850     { REG_TABLE (REG_XOP_TBM_02) },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 08 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 10 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { REG_TABLE (REG_XOP_LWPCB) },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 18 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 20 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 28 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 30 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 38 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 40 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 48 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 50 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 58 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 60 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 68 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 70 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 78 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 80 */
7992     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7994     { "vfrczss",        { XM, EXd }, 0 },
7995     { "vfrczsd",        { XM, EXq }, 0 },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 88 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* 90 */
8010     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     /* 98 */
8019     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* a0 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* a8 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* b0 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* b8 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* c0 */
8064     { Bad_Opcode },
8065     { "vphaddbw",       { XM, EXxmm }, 0 },
8066     { "vphaddbd",       { XM, EXxmm }, 0 },
8067     { "vphaddbq",       { XM, EXxmm }, 0 },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { "vphaddwd",       { XM, EXxmm }, 0 },
8071     { "vphaddwq",       { XM, EXxmm }, 0 },
8072     /* c8 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { "vphadddq",       { XM, EXxmm }, 0 },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* d0 */
8082     { Bad_Opcode },
8083     { "vphaddubw",      { XM, EXxmm }, 0 },
8084     { "vphaddubd",      { XM, EXxmm }, 0 },
8085     { "vphaddubq",      { XM, EXxmm }, 0 },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { "vphadduwd",      { XM, EXxmm }, 0 },
8089     { "vphadduwq",      { XM, EXxmm }, 0 },
8090     /* d8 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { "vphaddudq",      { XM, EXxmm }, 0 },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* e0 */
8100     { Bad_Opcode },
8101     { "vphsubbw",       { XM, EXxmm }, 0 },
8102     { "vphsubwd",       { XM, EXxmm }, 0 },
8103     { "vphsubdq",       { XM, EXxmm }, 0 },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* e8 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* f0 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* f8 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135   },
8136   /* XOP_0A */
8137   {
8138     /* 00 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 08 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 10 */
8157     { "bextrS", { Gdq, Edq, Id }, 0 },
8158     { Bad_Opcode },
8159     { REG_TABLE (REG_XOP_LWP) },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 18 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 20 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 28 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 30 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 38 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 40 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 48 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 50 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 58 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 60 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* 68 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 70 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* 78 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 80 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 88 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 90 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 98 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* a0 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* a8 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* b0 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* b8 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* c0 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* c8 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* d0 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* d8 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* e0 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* e8 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* f0 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* f8 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426   },
8427 };
8428
8429 static const struct dis386 vex_table[][256] = {
8430   /* VEX_0F */
8431   {
8432     /* 00 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 08 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 10 */
8451     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8454     { MOD_TABLE (MOD_VEX_0F13) },
8455     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8456     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8457     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8458     { MOD_TABLE (MOD_VEX_0F17) },
8459     /* 18 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 20 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 28 */
8478     { "vmovapX",        { XM, EXx }, 0 },
8479     { "vmovapX",        { EXxS, XM }, 0 },
8480     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8481     { MOD_TABLE (MOD_VEX_0F2B) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8486     /* 30 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 38 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 40 */
8505     { Bad_Opcode },
8506     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8508     { Bad_Opcode },
8509     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8513     /* 48 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 50 */
8523     { MOD_TABLE (MOD_VEX_0F50) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8527     { "vandpX",         { XM, Vex, EXx }, 0 },
8528     { "vandnpX",        { XM, Vex, EXx }, 0 },
8529     { "vorpX",          { XM, Vex, EXx }, 0 },
8530     { "vxorpX",         { XM, Vex, EXx }, 0 },
8531     /* 58 */
8532     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8540     /* 60 */
8541     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8549     /* 68 */
8550     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8558     /* 70 */
8559     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8560     { REG_TABLE (REG_VEX_0F71) },
8561     { REG_TABLE (REG_VEX_0F72) },
8562     { REG_TABLE (REG_VEX_0F73) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8567     /* 78 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8576     /* 80 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* 88 */
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* 90 */
8595     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* 98 */
8604     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* a0 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* a8 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { REG_TABLE (REG_VEX_0FAE) },
8629     { Bad_Opcode },
8630     /* b0 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* b8 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* c0 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8652     { Bad_Opcode },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8655     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8656     { Bad_Opcode },
8657     /* c8 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* d0 */
8667     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8675     /* d8 */
8676     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8684     /* e0 */
8685     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8693     /* e8 */
8694     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8702     /* f0 */
8703     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8711     /* f8 */
8712     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8719     { Bad_Opcode },
8720   },
8721   /* VEX_0F38 */
8722   {
8723     /* 00 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8732     /* 08 */
8733     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8741     /* 10 */
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8750     /* 18 */
8751     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8754     { Bad_Opcode },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8758     { Bad_Opcode },
8759     /* 20 */
8760     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* 28 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8777     /* 30 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8786     /* 38 */
8787     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8795     /* 40 */
8796     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8804     /* 48 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* 50 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     /* 58 */
8823     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* 60 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* 68 */
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     /* 70 */
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* 78 */
8859     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     /* 80 */
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     /* 88 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8884     { Bad_Opcode },
8885     /* 90 */
8886     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8894     /* 98 */
8895     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8903     /* a0 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8912     /* a8 */
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8921     /* b0 */
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8930     /* b8 */
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8939     /* c0 */
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     /* c8 */
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8957     /* d0 */
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     /* d8 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8975     /* e0 */
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     /* e8 */
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     /* f0 */
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8997     { REG_TABLE (REG_VEX_0F38F3) },
8998     { Bad_Opcode },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9002     /* f8 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011   },
9012   /* VEX_0F3A */
9013   {
9014     /* 00 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9022     { Bad_Opcode },
9023     /* 08 */
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9032     /* 10 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9041     /* 18 */
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 20 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* 28 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 30 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     /* 38 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* 40 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9090     { Bad_Opcode },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9094     { Bad_Opcode },
9095     /* 48 */
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     /* 50 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* 58 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9122     /* 60 */
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* 68 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9140     /* 70 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* 78 */
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9158     /* 80 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* 88 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* 90 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     /* 98 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* a0 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     /* a8 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* b0 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     /* b8 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     /* c0 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* c8 */
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9247     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9248     /* d0 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* d8 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9266     /* e0 */
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* e8 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* f0 */
9285     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     /* f8 */
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302   },
9303 };
9304
9305 #include "i386-dis-evex.h"
9306
9307 static const struct dis386 vex_len_table[][2] = {
9308   /* VEX_LEN_0F12_P_0_M_0 */
9309   {
9310     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F12_P_0_M_1 */
9314   {
9315     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F12_P_2 */
9319   {
9320     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F13_M_0 */
9324   {
9325     { "vmovlpX",        { EXq, XM }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F16_P_0_M_0 */
9329   {
9330     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F16_P_0_M_1 */
9334   {
9335     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9336   },
9337
9338   /* VEX_LEN_0F16_P_2 */
9339   {
9340     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9341   },
9342
9343   /* VEX_LEN_0F17_M_0 */
9344   {
9345     { "vmovhpX",        { EXq, XM }, 0 },
9346   },
9347
9348   /* VEX_LEN_0F41_P_0 */
9349   {
9350     { Bad_Opcode },
9351     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9352   },
9353   /* VEX_LEN_0F41_P_2 */
9354   {
9355     { Bad_Opcode },
9356     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9357   },
9358   /* VEX_LEN_0F42_P_0 */
9359   {
9360     { Bad_Opcode },
9361     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9362   },
9363   /* VEX_LEN_0F42_P_2 */
9364   {
9365     { Bad_Opcode },
9366     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9367   },
9368   /* VEX_LEN_0F44_P_0 */
9369   {
9370     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9371   },
9372   /* VEX_LEN_0F44_P_2 */
9373   {
9374     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9375   },
9376   /* VEX_LEN_0F45_P_0 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9380   },
9381   /* VEX_LEN_0F45_P_2 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9385   },
9386   /* VEX_LEN_0F46_P_0 */
9387   {
9388     { Bad_Opcode },
9389     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9390   },
9391   /* VEX_LEN_0F46_P_2 */
9392   {
9393     { Bad_Opcode },
9394     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9395   },
9396   /* VEX_LEN_0F47_P_0 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9400   },
9401   /* VEX_LEN_0F47_P_2 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9405   },
9406   /* VEX_LEN_0F4A_P_0 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9410   },
9411   /* VEX_LEN_0F4A_P_2 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9415   },
9416   /* VEX_LEN_0F4B_P_0 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9420   },
9421   /* VEX_LEN_0F4B_P_2 */
9422   {
9423     { Bad_Opcode },
9424     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9425   },
9426
9427   /* VEX_LEN_0F6E_P_2 */
9428   {
9429     { "vmovK",          { XMScalar, Edq }, 0 },
9430   },
9431
9432   /* VEX_LEN_0F77_P_1 */
9433   {
9434     { "vzeroupper",     { XX }, 0 },
9435     { "vzeroall",       { XX }, 0 },
9436   },
9437
9438   /* VEX_LEN_0F7E_P_1 */
9439   {
9440     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9441   },
9442
9443   /* VEX_LEN_0F7E_P_2 */
9444   {
9445     { "vmovK",          { Edq, XMScalar }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F90_P_0 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9451   },
9452
9453   /* VEX_LEN_0F90_P_2 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9456   },
9457
9458   /* VEX_LEN_0F91_P_0 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9461   },
9462
9463   /* VEX_LEN_0F91_P_2 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9466   },
9467
9468   /* VEX_LEN_0F92_P_0 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F92_P_2 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0F92_P_3 */
9479   {
9480     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F93_P_0 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F93_P_2 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F93_P_3 */
9494   {
9495     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F98_P_0 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F98_P_2 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0F99_P_0 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9511   },
9512
9513   /* VEX_LEN_0F99_P_2 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0FAE_R_2_M_0 */
9519   {
9520     { "vldmxcsr",       { Md }, 0 },
9521   },
9522
9523   /* VEX_LEN_0FAE_R_3_M_0 */
9524   {
9525     { "vstmxcsr",       { Md }, 0 },
9526   },
9527
9528   /* VEX_LEN_0FC4_P_2 */
9529   {
9530     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9531   },
9532
9533   /* VEX_LEN_0FC5_P_2 */
9534   {
9535     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9536   },
9537
9538   /* VEX_LEN_0FD6_P_2 */
9539   {
9540     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9541   },
9542
9543   /* VEX_LEN_0FF7_P_2 */
9544   {
9545     { "vmaskmovdqu",    { XM, XS }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F3816_P_2 */
9549   {
9550     { Bad_Opcode },
9551     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9552   },
9553
9554   /* VEX_LEN_0F3819_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F381A_P_2_M_0 */
9561   {
9562     { Bad_Opcode },
9563     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9564   },
9565
9566   /* VEX_LEN_0F3836_P_2 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9570   },
9571
9572   /* VEX_LEN_0F3841_P_2 */
9573   {
9574     { "vphminposuw",    { XM, EXx }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F385A_P_2_M_0 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9581   },
9582
9583   /* VEX_LEN_0F38DB_P_2 */
9584   {
9585     { "vaesimc",        { XM, EXx }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F38F2_P_0 */
9589   {
9590     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F38F3_R_1_P_0 */
9594   {
9595     { "blsrS",          { VexGdq, Edq }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F38F3_R_2_P_0 */
9599   {
9600     { "blsmskS",        { VexGdq, Edq }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F38F3_R_3_P_0 */
9604   {
9605     { "blsiS",          { VexGdq, Edq }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F38F5_P_0 */
9609   {
9610     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F38F5_P_1 */
9614   {
9615     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F38F5_P_3 */
9619   {
9620     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F38F6_P_3 */
9624   {
9625     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F38F7_P_0 */
9629   {
9630     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F38F7_P_1 */
9634   {
9635     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F38F7_P_2 */
9639   {
9640     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F38F7_P_3 */
9644   {
9645     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F3A00_P_2 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9652   },
9653
9654   /* VEX_LEN_0F3A01_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9658   },
9659
9660   /* VEX_LEN_0F3A06_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9664   },
9665
9666   /* VEX_LEN_0F3A14_P_2 */
9667   {
9668     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F3A15_P_2 */
9672   {
9673     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A16_P_2  */
9677   {
9678     { "vpextrK",        { Edq, XM, Ib }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A17_P_2 */
9682   {
9683     { "vextractps",     { Edqd, XM, Ib }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F3A18_P_2 */
9687   {
9688     { Bad_Opcode },
9689     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A19_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9696   },
9697
9698   /* VEX_LEN_0F3A20_P_2 */
9699   {
9700     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A21_P_2 */
9704   {
9705     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A22_P_2 */
9709   {
9710     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F3A30_P_2 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9716   },
9717
9718   /* VEX_LEN_0F3A31_P_2 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9721   },
9722
9723   /* VEX_LEN_0F3A32_P_2 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9726   },
9727
9728   /* VEX_LEN_0F3A33_P_2 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9731   },
9732
9733   /* VEX_LEN_0F3A38_P_2 */
9734   {
9735     { Bad_Opcode },
9736     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9737   },
9738
9739   /* VEX_LEN_0F3A39_P_2 */
9740   {
9741     { Bad_Opcode },
9742     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9743   },
9744
9745   /* VEX_LEN_0F3A41_P_2 */
9746   {
9747     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9748   },
9749
9750   /* VEX_LEN_0F3A46_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A60_P_2 */
9757   {
9758     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A61_P_2 */
9762   {
9763     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A62_P_2 */
9767   {
9768     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A63_P_2 */
9772   {
9773     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A6A_P_2 */
9777   {
9778     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A6B_P_2 */
9782   {
9783     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F3A6E_P_2 */
9787   {
9788     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A6F_P_2 */
9792   {
9793     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9794   },
9795
9796   /* VEX_LEN_0F3A7A_P_2 */
9797   {
9798     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F3A7B_P_2 */
9802   {
9803     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9804   },
9805
9806   /* VEX_LEN_0F3A7E_P_2 */
9807   {
9808     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9809   },
9810
9811   /* VEX_LEN_0F3A7F_P_2 */
9812   {
9813     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9814   },
9815
9816   /* VEX_LEN_0F3ADF_P_2 */
9817   {
9818     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9819   },
9820
9821   /* VEX_LEN_0F3AF0_P_3 */
9822   {
9823     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9824   },
9825
9826   /* VEX_LEN_0FXOP_08_CC */
9827   {
9828      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9829   },
9830
9831   /* VEX_LEN_0FXOP_08_CD */
9832   {
9833      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9834   },
9835
9836   /* VEX_LEN_0FXOP_08_CE */
9837   {
9838      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9839   },
9840
9841   /* VEX_LEN_0FXOP_08_CF */
9842   {
9843      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9844   },
9845
9846   /* VEX_LEN_0FXOP_08_EC */
9847   {
9848      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_ED */
9852   {
9853      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9854   },
9855
9856   /* VEX_LEN_0FXOP_08_EE */
9857   {
9858      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9859   },
9860
9861   /* VEX_LEN_0FXOP_08_EF */
9862   {
9863      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9864   },
9865
9866   /* VEX_LEN_0FXOP_09_80 */
9867   {
9868     { "vfrczps",        { XM, EXxmm }, 0 },
9869     { "vfrczps",        { XM, EXymmq }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_09_81 */
9873   {
9874     { "vfrczpd",        { XM, EXxmm }, 0 },
9875     { "vfrczpd",        { XM, EXymmq }, 0 },
9876   },
9877 };
9878
9879 #include "i386-dis-evex-len.h"
9880
9881 static const struct dis386 vex_w_table[][2] = {
9882   {
9883     /* VEX_W_0F41_P_0_LEN_1 */
9884     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9885     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9886   },
9887   {
9888     /* VEX_W_0F41_P_2_LEN_1 */
9889     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9890     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9891   },
9892   {
9893     /* VEX_W_0F42_P_0_LEN_1 */
9894     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9895     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9896   },
9897   {
9898     /* VEX_W_0F42_P_2_LEN_1 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9901   },
9902   {
9903     /* VEX_W_0F44_P_0_LEN_0 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F44_P_2_LEN_0 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9911   },
9912   {
9913     /* VEX_W_0F45_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F45_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F46_P_0_LEN_1 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F46_P_2_LEN_1 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F47_P_0_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F47_P_2_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F4A_P_0_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F4A_P_2_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F4B_P_0_LEN_1 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F4B_P_2_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9960   },
9961   {
9962     /* VEX_W_0F90_P_0_LEN_0 */
9963     { "kmovw",          { MaskG, MaskE }, 0 },
9964     { "kmovq",          { MaskG, MaskE }, 0 },
9965   },
9966   {
9967     /* VEX_W_0F90_P_2_LEN_0 */
9968     { "kmovb",          { MaskG, MaskBDE }, 0 },
9969     { "kmovd",          { MaskG, MaskBDE }, 0 },
9970   },
9971   {
9972     /* VEX_W_0F91_P_0_LEN_0 */
9973     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9974     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9975   },
9976   {
9977     /* VEX_W_0F91_P_2_LEN_0 */
9978     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9979     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9980   },
9981   {
9982     /* VEX_W_0F92_P_0_LEN_0 */
9983     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F92_P_2_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F93_P_0_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9992   },
9993   {
9994     /* VEX_W_0F93_P_2_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9996   },
9997   {
9998     /* VEX_W_0F98_P_0_LEN_0 */
9999     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10000     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F98_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10005     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F99_P_0_LEN_0 */
10009     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10010     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10011   },
10012   {
10013     /* VEX_W_0F99_P_2_LEN_0 */
10014     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10015     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F380C_P_2  */
10019     { "vpermilps",      { XM, Vex, EXx }, 0 },
10020   },
10021   {
10022     /* VEX_W_0F380D_P_2  */
10023     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F380E_P_2  */
10027     { "vtestps",        { XM, EXx }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F380F_P_2  */
10031     { "vtestpd",        { XM, EXx }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3816_P_2  */
10035     { "vpermps",        { XM, Vex, EXx }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3818_P_2 */
10039     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F3819_P_2 */
10043     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F381A_P_2_M_0 */
10047     { "vbroadcastf128", { XM, Mxmm }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F382C_P_2_M_0 */
10051     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F382D_P_2_M_0 */
10055     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F382E_P_2_M_0 */
10059     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F382F_P_2_M_0 */
10063     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F3836_P_2  */
10067     { "vpermd",         { XM, Vex, EXx }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F3846_P_2 */
10071     { "vpsravd",        { XM, Vex, EXx }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F3858_P_2 */
10075     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F3859_P_2 */
10079     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F385A_P_2_M_0 */
10083     { "vbroadcasti128", { XM, Mxmm }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F3878_P_2 */
10087     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10088   },
10089   {
10090     /* VEX_W_0F3879_P_2 */
10091     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F38CF_P_2 */
10095     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F3A00_P_2 */
10099     { Bad_Opcode },
10100     { "vpermq",         { XM, EXx, Ib }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3A01_P_2 */
10104     { Bad_Opcode },
10105     { "vpermpd",        { XM, EXx, Ib }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3A02_P_2 */
10109     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3A04_P_2 */
10113     { "vpermilps",      { XM, EXx, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A05_P_2 */
10117     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A06_P_2 */
10121     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3A18_P_2 */
10125     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3A19_P_2 */
10129     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F3A30_P_2_LEN_0 */
10133     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10134     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10135   },
10136   {
10137     /* VEX_W_0F3A31_P_2_LEN_0 */
10138     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10139     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10140   },
10141   {
10142     /* VEX_W_0F3A32_P_2_LEN_0 */
10143     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10144     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10145   },
10146   {
10147     /* VEX_W_0F3A33_P_2_LEN_0 */
10148     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10149     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10150   },
10151   {
10152     /* VEX_W_0F3A38_P_2 */
10153     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10154   },
10155   {
10156     /* VEX_W_0F3A39_P_2 */
10157     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10158   },
10159   {
10160     /* VEX_W_0F3A46_P_2 */
10161     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F3A48_P_2 */
10165     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10166     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A49_P_2 */
10170     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10171     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10172   },
10173   {
10174     /* VEX_W_0F3A4A_P_2 */
10175     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A4B_P_2 */
10179     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A4C_P_2 */
10183     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F3ACE_P_2 */
10187     { Bad_Opcode },
10188     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3ACF_P_2 */
10192     { Bad_Opcode },
10193     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10194   },
10195
10196 #include "i386-dis-evex-w.h"
10197 };
10198
10199 static const struct dis386 mod_table[][2] = {
10200   {
10201     /* MOD_8D */
10202     { "leaS",           { Gv, M }, 0 },
10203   },
10204   {
10205     /* MOD_C6_REG_7 */
10206     { Bad_Opcode },
10207     { RM_TABLE (RM_C6_REG_7) },
10208   },
10209   {
10210     /* MOD_C7_REG_7 */
10211     { Bad_Opcode },
10212     { RM_TABLE (RM_C7_REG_7) },
10213   },
10214   {
10215     /* MOD_FF_REG_3 */
10216     { "Jcall^", { indirEp }, 0 },
10217   },
10218   {
10219     /* MOD_FF_REG_5 */
10220     { "Jjmp^", { indirEp }, 0 },
10221   },
10222   {
10223     /* MOD_0F01_REG_0 */
10224     { X86_64_TABLE (X86_64_0F01_REG_0) },
10225     { RM_TABLE (RM_0F01_REG_0) },
10226   },
10227   {
10228     /* MOD_0F01_REG_1 */
10229     { X86_64_TABLE (X86_64_0F01_REG_1) },
10230     { RM_TABLE (RM_0F01_REG_1) },
10231   },
10232   {
10233     /* MOD_0F01_REG_2 */
10234     { X86_64_TABLE (X86_64_0F01_REG_2) },
10235     { RM_TABLE (RM_0F01_REG_2) },
10236   },
10237   {
10238     /* MOD_0F01_REG_3 */
10239     { X86_64_TABLE (X86_64_0F01_REG_3) },
10240     { RM_TABLE (RM_0F01_REG_3) },
10241   },
10242   {
10243     /* MOD_0F01_REG_5 */
10244     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10245     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10246   },
10247   {
10248     /* MOD_0F01_REG_7 */
10249     { "invlpg",         { Mb }, 0 },
10250     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10251   },
10252   {
10253     /* MOD_0F12_PREFIX_0 */
10254     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10255     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10256   },
10257   {
10258     /* MOD_0F13 */
10259     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10260   },
10261   {
10262     /* MOD_0F16_PREFIX_0 */
10263     { "movhps",         { XM, EXq }, 0 },
10264     { "movlhps",        { XM, EXq }, 0 },
10265   },
10266   {
10267     /* MOD_0F17 */
10268     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10269   },
10270   {
10271     /* MOD_0F18_REG_0 */
10272     { "prefetchnta",    { Mb }, 0 },
10273   },
10274   {
10275     /* MOD_0F18_REG_1 */
10276     { "prefetcht0",     { Mb }, 0 },
10277   },
10278   {
10279     /* MOD_0F18_REG_2 */
10280     { "prefetcht1",     { Mb }, 0 },
10281   },
10282   {
10283     /* MOD_0F18_REG_3 */
10284     { "prefetcht2",     { Mb }, 0 },
10285   },
10286   {
10287     /* MOD_0F18_REG_4 */
10288     { "nop/reserved",   { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F18_REG_5 */
10292     { "nop/reserved",   { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_6 */
10296     { "nop/reserved",   { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_7 */
10300     { "nop/reserved",   { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F1A_PREFIX_0 */
10304     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10305     { "nopQ",           { Ev }, 0 },
10306   },
10307   {
10308     /* MOD_0F1B_PREFIX_0 */
10309     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10310     { "nopQ",           { Ev }, 0 },
10311   },
10312   {
10313     /* MOD_0F1B_PREFIX_1 */
10314     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10315     { "nopQ",           { Ev }, 0 },
10316   },
10317   {
10318     /* MOD_0F1C_PREFIX_0 */
10319     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10320     { "nopQ",           { Ev }, 0 },
10321   },
10322   {
10323     /* MOD_0F1E_PREFIX_1 */
10324     { "nopQ",           { Ev }, 0 },
10325     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10326   },
10327   {
10328     /* MOD_0F24 */
10329     { Bad_Opcode },
10330     { "movL",           { Rd, Td }, 0 },
10331   },
10332   {
10333     /* MOD_0F26 */
10334     { Bad_Opcode },
10335     { "movL",           { Td, Rd }, 0 },
10336   },
10337   {
10338     /* MOD_0F2B_PREFIX_0 */
10339     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10340   },
10341   {
10342     /* MOD_0F2B_PREFIX_1 */
10343     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10344   },
10345   {
10346     /* MOD_0F2B_PREFIX_2 */
10347     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10348   },
10349   {
10350     /* MOD_0F2B_PREFIX_3 */
10351     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10352   },
10353   {
10354     /* MOD_0F51 */
10355     { Bad_Opcode },
10356     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10357   },
10358   {
10359     /* MOD_0F71_REG_2 */
10360     { Bad_Opcode },
10361     { "psrlw",          { MS, Ib }, 0 },
10362   },
10363   {
10364     /* MOD_0F71_REG_4 */
10365     { Bad_Opcode },
10366     { "psraw",          { MS, Ib }, 0 },
10367   },
10368   {
10369     /* MOD_0F71_REG_6 */
10370     { Bad_Opcode },
10371     { "psllw",          { MS, Ib }, 0 },
10372   },
10373   {
10374     /* MOD_0F72_REG_2 */
10375     { Bad_Opcode },
10376     { "psrld",          { MS, Ib }, 0 },
10377   },
10378   {
10379     /* MOD_0F72_REG_4 */
10380     { Bad_Opcode },
10381     { "psrad",          { MS, Ib }, 0 },
10382   },
10383   {
10384     /* MOD_0F72_REG_6 */
10385     { Bad_Opcode },
10386     { "pslld",          { MS, Ib }, 0 },
10387   },
10388   {
10389     /* MOD_0F73_REG_2 */
10390     { Bad_Opcode },
10391     { "psrlq",          { MS, Ib }, 0 },
10392   },
10393   {
10394     /* MOD_0F73_REG_3 */
10395     { Bad_Opcode },
10396     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10397   },
10398   {
10399     /* MOD_0F73_REG_6 */
10400     { Bad_Opcode },
10401     { "psllq",          { MS, Ib }, 0 },
10402   },
10403   {
10404     /* MOD_0F73_REG_7 */
10405     { Bad_Opcode },
10406     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10407   },
10408   {
10409     /* MOD_0FAE_REG_0 */
10410     { "fxsave",         { FXSAVE }, 0 },
10411     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10412   },
10413   {
10414     /* MOD_0FAE_REG_1 */
10415     { "fxrstor",        { FXSAVE }, 0 },
10416     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10417   },
10418   {
10419     /* MOD_0FAE_REG_2 */
10420     { "ldmxcsr",        { Md }, 0 },
10421     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10422   },
10423   {
10424     /* MOD_0FAE_REG_3 */
10425     { "stmxcsr",        { Md }, 0 },
10426     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10427   },
10428   {
10429     /* MOD_0FAE_REG_4 */
10430     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10431     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10432   },
10433   {
10434     /* MOD_0FAE_REG_5 */
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10436     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10437   },
10438   {
10439     /* MOD_0FAE_REG_6 */
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10441     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10442   },
10443   {
10444     /* MOD_0FAE_REG_7 */
10445     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10446     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10447   },
10448   {
10449     /* MOD_0FB2 */
10450     { "lssS",           { Gv, Mp }, 0 },
10451   },
10452   {
10453     /* MOD_0FB4 */
10454     { "lfsS",           { Gv, Mp }, 0 },
10455   },
10456   {
10457     /* MOD_0FB5 */
10458     { "lgsS",           { Gv, Mp }, 0 },
10459   },
10460   {
10461     /* MOD_0FC3 */
10462     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10463   },
10464   {
10465     /* MOD_0FC7_REG_3 */
10466     { "xrstors",        { FXSAVE }, 0 },
10467   },
10468   {
10469     /* MOD_0FC7_REG_4 */
10470     { "xsavec",         { FXSAVE }, 0 },
10471   },
10472   {
10473     /* MOD_0FC7_REG_5 */
10474     { "xsaves",         { FXSAVE }, 0 },
10475   },
10476   {
10477     /* MOD_0FC7_REG_6 */
10478     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10479     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10480   },
10481   {
10482     /* MOD_0FC7_REG_7 */
10483     { "vmptrst",        { Mq }, 0 },
10484     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10485   },
10486   {
10487     /* MOD_0FD7 */
10488     { Bad_Opcode },
10489     { "pmovmskb",       { Gdq, MS }, 0 },
10490   },
10491   {
10492     /* MOD_0FE7_PREFIX_2 */
10493     { "movntdq",        { Mx, XM }, 0 },
10494   },
10495   {
10496     /* MOD_0FF0_PREFIX_3 */
10497     { "lddqu",          { XM, M }, 0 },
10498   },
10499   {
10500     /* MOD_0F382A_PREFIX_2 */
10501     { "movntdqa",       { XM, Mx }, 0 },
10502   },
10503   {
10504     /* MOD_0F38F5_PREFIX_2 */
10505     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10506   },
10507   {
10508     /* MOD_0F38F6_PREFIX_0 */
10509     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10510   },
10511   {
10512     /* MOD_0F38F8_PREFIX_1 */
10513     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10514   },
10515   {
10516     /* MOD_0F38F8_PREFIX_2 */
10517     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10518   },
10519   {
10520     /* MOD_0F38F8_PREFIX_3 */
10521     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10522   },
10523   {
10524     /* MOD_0F38F9_PREFIX_0 */
10525     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_62_32BIT */
10529     { "bound{S|}",      { Gv, Ma }, 0 },
10530     { EVEX_TABLE (EVEX_0F) },
10531   },
10532   {
10533     /* MOD_C4_32BIT */
10534     { "lesS",           { Gv, Mp }, 0 },
10535     { VEX_C4_TABLE (VEX_0F) },
10536   },
10537   {
10538     /* MOD_C5_32BIT */
10539     { "ldsS",           { Gv, Mp }, 0 },
10540     { VEX_C5_TABLE (VEX_0F) },
10541   },
10542   {
10543     /* MOD_VEX_0F12_PREFIX_0 */
10544     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10545     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10546   },
10547   {
10548     /* MOD_VEX_0F13 */
10549     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10550   },
10551   {
10552     /* MOD_VEX_0F16_PREFIX_0 */
10553     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10554     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10555   },
10556   {
10557     /* MOD_VEX_0F17 */
10558     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10559   },
10560   {
10561     /* MOD_VEX_0F2B */
10562     { "vmovntpX",       { Mx, XM }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10566     { Bad_Opcode },
10567     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10571     { Bad_Opcode },
10572     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10576     { Bad_Opcode },
10577     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10581     { Bad_Opcode },
10582     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10586     { Bad_Opcode },
10587     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10591     { Bad_Opcode },
10592     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10596     { Bad_Opcode },
10597     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10601     { Bad_Opcode },
10602     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10606     { Bad_Opcode },
10607     { "knotw",          { MaskG, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10611     { Bad_Opcode },
10612     { "knotq",          { MaskG, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10616     { Bad_Opcode },
10617     { "knotb",          { MaskG, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10621     { Bad_Opcode },
10622     { "knotd",          { MaskG, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10626     { Bad_Opcode },
10627     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10628   },
10629   {
10630     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10631     { Bad_Opcode },
10632     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10633   },
10634   {
10635     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10636     { Bad_Opcode },
10637     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10638   },
10639   {
10640     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10641     { Bad_Opcode },
10642     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10643   },
10644  {
10645     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10646     { Bad_Opcode },
10647     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10648   },
10649   {
10650     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10651     { Bad_Opcode },
10652     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10656     { Bad_Opcode },
10657     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10658   },
10659   {
10660     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10661     { Bad_Opcode },
10662     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10663   },
10664   {
10665     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10666     { Bad_Opcode },
10667     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10668   },
10669   {
10670     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10671     { Bad_Opcode },
10672     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10676     { Bad_Opcode },
10677     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10681     { Bad_Opcode },
10682     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10686     { Bad_Opcode },
10687     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10691     { Bad_Opcode },
10692     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10696     { Bad_Opcode },
10697     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10701     { Bad_Opcode },
10702     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10706     { Bad_Opcode },
10707     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10711     { Bad_Opcode },
10712     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10716     { Bad_Opcode },
10717     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_0F50 */
10721     { Bad_Opcode },
10722     { "vmovmskpX",      { Gdq, XS }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_0F71_REG_2 */
10726     { Bad_Opcode },
10727     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10728   },
10729   {
10730     /* MOD_VEX_0F71_REG_4 */
10731     { Bad_Opcode },
10732     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10733   },
10734   {
10735     /* MOD_VEX_0F71_REG_6 */
10736     { Bad_Opcode },
10737     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10738   },
10739   {
10740     /* MOD_VEX_0F72_REG_2 */
10741     { Bad_Opcode },
10742     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10743   },
10744   {
10745     /* MOD_VEX_0F72_REG_4 */
10746     { Bad_Opcode },
10747     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10748   },
10749   {
10750     /* MOD_VEX_0F72_REG_6 */
10751     { Bad_Opcode },
10752     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10753   },
10754   {
10755     /* MOD_VEX_0F73_REG_2 */
10756     { Bad_Opcode },
10757     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10758   },
10759   {
10760     /* MOD_VEX_0F73_REG_3 */
10761     { Bad_Opcode },
10762     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10763   },
10764   {
10765     /* MOD_VEX_0F73_REG_6 */
10766     { Bad_Opcode },
10767     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10768   },
10769   {
10770     /* MOD_VEX_0F73_REG_7 */
10771     { Bad_Opcode },
10772     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10773   },
10774   {
10775     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10776     { "kmovw",          { Ew, MaskG }, 0 },
10777     { Bad_Opcode },
10778   },
10779   {
10780     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10781     { "kmovq",          { Eq, MaskG }, 0 },
10782     { Bad_Opcode },
10783   },
10784   {
10785     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10786     { "kmovb",          { Eb, MaskG }, 0 },
10787     { Bad_Opcode },
10788   },
10789   {
10790     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10791     { "kmovd",          { Ed, MaskG }, 0 },
10792     { Bad_Opcode },
10793   },
10794   {
10795     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10796     { Bad_Opcode },
10797     { "kmovw",          { MaskG, Rdq }, 0 },
10798   },
10799   {
10800     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10801     { Bad_Opcode },
10802     { "kmovb",          { MaskG, Rdq }, 0 },
10803   },
10804   {
10805     /* MOD_VEX_0F92_P_3_LEN_0 */
10806     { Bad_Opcode },
10807     { "kmovK",          { MaskG, Rdq }, 0 },
10808   },
10809   {
10810     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10811     { Bad_Opcode },
10812     { "kmovw",          { Gdq, MaskR }, 0 },
10813   },
10814   {
10815     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10816     { Bad_Opcode },
10817     { "kmovb",          { Gdq, MaskR }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_0F93_P_3_LEN_0 */
10821     { Bad_Opcode },
10822     { "kmovK",          { Gdq, MaskR }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10826     { Bad_Opcode },
10827     { "kortestw", { MaskG, MaskR }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10831     { Bad_Opcode },
10832     { "kortestq", { MaskG, MaskR }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10836     { Bad_Opcode },
10837     { "kortestb", { MaskG, MaskR }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10841     { Bad_Opcode },
10842     { "kortestd", { MaskG, MaskR }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10846     { Bad_Opcode },
10847     { "ktestw", { MaskG, MaskR }, 0 },
10848   },
10849   {
10850     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10851     { Bad_Opcode },
10852     { "ktestq", { MaskG, MaskR }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10856     { Bad_Opcode },
10857     { "ktestb", { MaskG, MaskR }, 0 },
10858   },
10859   {
10860     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10861     { Bad_Opcode },
10862     { "ktestd", { MaskG, MaskR }, 0 },
10863   },
10864   {
10865     /* MOD_VEX_0FAE_REG_2 */
10866     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10867   },
10868   {
10869     /* MOD_VEX_0FAE_REG_3 */
10870     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10871   },
10872   {
10873     /* MOD_VEX_0FD7_PREFIX_2 */
10874     { Bad_Opcode },
10875     { "vpmovmskb",      { Gdq, XS }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_0FE7_PREFIX_2 */
10879     { "vmovntdq",       { Mx, XM }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0FF0_PREFIX_3 */
10883     { "vlddqu",         { XM, M }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_0F381A_PREFIX_2 */
10887     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F382A_PREFIX_2 */
10891     { "vmovntdqa",      { XM, Mx }, 0 },
10892   },
10893   {
10894     /* MOD_VEX_0F382C_PREFIX_2 */
10895     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10896   },
10897   {
10898     /* MOD_VEX_0F382D_PREFIX_2 */
10899     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0F382E_PREFIX_2 */
10903     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0F382F_PREFIX_2 */
10907     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0F385A_PREFIX_2 */
10911     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F388C_PREFIX_2 */
10915     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0F388E_PREFIX_2 */
10919     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10920   },
10921   {
10922     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10923     { Bad_Opcode },
10924     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10925   },
10926   {
10927     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10928     { Bad_Opcode },
10929     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10930   },
10931   {
10932     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10933     { Bad_Opcode },
10934     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10935   },
10936   {
10937     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10938     { Bad_Opcode },
10939     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10943     { Bad_Opcode },
10944     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10948     { Bad_Opcode },
10949     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10950   },
10951   {
10952     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10953     { Bad_Opcode },
10954     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10955   },
10956   {
10957     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10958     { Bad_Opcode },
10959     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10960   },
10961
10962 #include "i386-dis-evex-mod.h"
10963 };
10964
10965 static const struct dis386 rm_table[][8] = {
10966   {
10967     /* RM_C6_REG_7 */
10968     { "xabort",         { Skip_MODRM, Ib }, 0 },
10969   },
10970   {
10971     /* RM_C7_REG_7 */
10972     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10973   },
10974   {
10975     /* RM_0F01_REG_0 */
10976     { "enclv",          { Skip_MODRM }, 0 },
10977     { "vmcall",         { Skip_MODRM }, 0 },
10978     { "vmlaunch",       { Skip_MODRM }, 0 },
10979     { "vmresume",       { Skip_MODRM }, 0 },
10980     { "vmxoff",         { Skip_MODRM }, 0 },
10981     { "pconfig",        { Skip_MODRM }, 0 },
10982   },
10983   {
10984     /* RM_0F01_REG_1 */
10985     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10986     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10987     { "clac",           { Skip_MODRM }, 0 },
10988     { "stac",           { Skip_MODRM }, 0 },
10989     { Bad_Opcode },
10990     { Bad_Opcode },
10991     { Bad_Opcode },
10992     { "encls",          { Skip_MODRM }, 0 },
10993   },
10994   {
10995     /* RM_0F01_REG_2 */
10996     { "xgetbv",         { Skip_MODRM }, 0 },
10997     { "xsetbv",         { Skip_MODRM }, 0 },
10998     { Bad_Opcode },
10999     { Bad_Opcode },
11000     { "vmfunc",         { Skip_MODRM }, 0 },
11001     { "xend",           { Skip_MODRM }, 0 },
11002     { "xtest",          { Skip_MODRM }, 0 },
11003     { "enclu",          { Skip_MODRM }, 0 },
11004   },
11005   {
11006     /* RM_0F01_REG_3 */
11007     { "vmrun",          { Skip_MODRM }, 0 },
11008     { "vmmcall",        { Skip_MODRM }, 0 },
11009     { "vmload",         { Skip_MODRM }, 0 },
11010     { "vmsave",         { Skip_MODRM }, 0 },
11011     { "stgi",           { Skip_MODRM }, 0 },
11012     { "clgi",           { Skip_MODRM }, 0 },
11013     { "skinit",         { Skip_MODRM }, 0 },
11014     { "invlpga",        { Skip_MODRM }, 0 },
11015   },
11016   {
11017     /* RM_0F01_REG_5_MOD_3 */
11018     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11019     { Bad_Opcode },
11020     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11021     { Bad_Opcode },
11022     { Bad_Opcode },
11023     { Bad_Opcode },
11024     { "rdpkru",         { Skip_MODRM }, 0 },
11025     { "wrpkru",         { Skip_MODRM }, 0 },
11026   },
11027   {
11028     /* RM_0F01_REG_7_MOD_3 */
11029     { "swapgs",         { Skip_MODRM }, 0  },
11030     { "rdtscp",         { Skip_MODRM }, 0  },
11031     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11032     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11033     { "clzero",         { Skip_MODRM }, 0  },
11034   },
11035   {
11036     /* RM_0F1E_P_1_MOD_3_REG_7 */
11037     { "nopQ",           { Ev }, 0 },
11038     { "nopQ",           { Ev }, 0 },
11039     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11040     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11041     { "nopQ",           { Ev }, 0 },
11042     { "nopQ",           { Ev }, 0 },
11043     { "nopQ",           { Ev }, 0 },
11044     { "nopQ",           { Ev }, 0 },
11045   },
11046   {
11047     /* RM_0FAE_REG_6_MOD_3 */
11048     { "mfence",         { Skip_MODRM }, 0 },
11049   },
11050   {
11051     /* RM_0FAE_REG_7_MOD_3 */
11052     { "sfence",         { Skip_MODRM }, 0 },
11053
11054   },
11055 };
11056
11057 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11058
11059 /* We use the high bit to indicate different name for the same
11060    prefix.  */
11061 #define REP_PREFIX      (0xf3 | 0x100)
11062 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11063 #define XRELEASE_PREFIX (0xf3 | 0x400)
11064 #define BND_PREFIX      (0xf2 | 0x400)
11065 #define NOTRACK_PREFIX  (0x3e | 0x100)
11066
11067 static int
11068 ckprefix (void)
11069 {
11070   int newrex, i, length;
11071   rex = 0;
11072   rex_ignored = 0;
11073   prefixes = 0;
11074   used_prefixes = 0;
11075   rex_used = 0;
11076   last_lock_prefix = -1;
11077   last_repz_prefix = -1;
11078   last_repnz_prefix = -1;
11079   last_data_prefix = -1;
11080   last_addr_prefix = -1;
11081   last_rex_prefix = -1;
11082   last_seg_prefix = -1;
11083   fwait_prefix = -1;
11084   active_seg_prefix = 0;
11085   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11086     all_prefixes[i] = 0;
11087   i = 0;
11088   length = 0;
11089   /* The maximum instruction length is 15bytes.  */
11090   while (length < MAX_CODE_LENGTH - 1)
11091     {
11092       FETCH_DATA (the_info, codep + 1);
11093       newrex = 0;
11094       switch (*codep)
11095         {
11096         /* REX prefixes family.  */
11097         case 0x40:
11098         case 0x41:
11099         case 0x42:
11100         case 0x43:
11101         case 0x44:
11102         case 0x45:
11103         case 0x46:
11104         case 0x47:
11105         case 0x48:
11106         case 0x49:
11107         case 0x4a:
11108         case 0x4b:
11109         case 0x4c:
11110         case 0x4d:
11111         case 0x4e:
11112         case 0x4f:
11113           if (address_mode == mode_64bit)
11114             newrex = *codep;
11115           else
11116             return 1;
11117           last_rex_prefix = i;
11118           break;
11119         case 0xf3:
11120           prefixes |= PREFIX_REPZ;
11121           last_repz_prefix = i;
11122           break;
11123         case 0xf2:
11124           prefixes |= PREFIX_REPNZ;
11125           last_repnz_prefix = i;
11126           break;
11127         case 0xf0:
11128           prefixes |= PREFIX_LOCK;
11129           last_lock_prefix = i;
11130           break;
11131         case 0x2e:
11132           prefixes |= PREFIX_CS;
11133           last_seg_prefix = i;
11134           active_seg_prefix = PREFIX_CS;
11135           break;
11136         case 0x36:
11137           prefixes |= PREFIX_SS;
11138           last_seg_prefix = i;
11139           active_seg_prefix = PREFIX_SS;
11140           break;
11141         case 0x3e:
11142           prefixes |= PREFIX_DS;
11143           last_seg_prefix = i;
11144           active_seg_prefix = PREFIX_DS;
11145           break;
11146         case 0x26:
11147           prefixes |= PREFIX_ES;
11148           last_seg_prefix = i;
11149           active_seg_prefix = PREFIX_ES;
11150           break;
11151         case 0x64:
11152           prefixes |= PREFIX_FS;
11153           last_seg_prefix = i;
11154           active_seg_prefix = PREFIX_FS;
11155           break;
11156         case 0x65:
11157           prefixes |= PREFIX_GS;
11158           last_seg_prefix = i;
11159           active_seg_prefix = PREFIX_GS;
11160           break;
11161         case 0x66:
11162           prefixes |= PREFIX_DATA;
11163           last_data_prefix = i;
11164           break;
11165         case 0x67:
11166           prefixes |= PREFIX_ADDR;
11167           last_addr_prefix = i;
11168           break;
11169         case FWAIT_OPCODE:
11170           /* fwait is really an instruction.  If there are prefixes
11171              before the fwait, they belong to the fwait, *not* to the
11172              following instruction.  */
11173           fwait_prefix = i;
11174           if (prefixes || rex)
11175             {
11176               prefixes |= PREFIX_FWAIT;
11177               codep++;
11178               /* This ensures that the previous REX prefixes are noticed
11179                  as unused prefixes, as in the return case below.  */
11180               rex_used = rex;
11181               return 1;
11182             }
11183           prefixes = PREFIX_FWAIT;
11184           break;
11185         default:
11186           return 1;
11187         }
11188       /* Rex is ignored when followed by another prefix.  */
11189       if (rex)
11190         {
11191           rex_used = rex;
11192           return 1;
11193         }
11194       if (*codep != FWAIT_OPCODE)
11195         all_prefixes[i++] = *codep;
11196       rex = newrex;
11197       codep++;
11198       length++;
11199     }
11200   return 0;
11201 }
11202
11203 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11204    prefix byte.  */
11205
11206 static const char *
11207 prefix_name (int pref, int sizeflag)
11208 {
11209   static const char *rexes [16] =
11210     {
11211       "rex",            /* 0x40 */
11212       "rex.B",          /* 0x41 */
11213       "rex.X",          /* 0x42 */
11214       "rex.XB",         /* 0x43 */
11215       "rex.R",          /* 0x44 */
11216       "rex.RB",         /* 0x45 */
11217       "rex.RX",         /* 0x46 */
11218       "rex.RXB",        /* 0x47 */
11219       "rex.W",          /* 0x48 */
11220       "rex.WB",         /* 0x49 */
11221       "rex.WX",         /* 0x4a */
11222       "rex.WXB",        /* 0x4b */
11223       "rex.WR",         /* 0x4c */
11224       "rex.WRB",        /* 0x4d */
11225       "rex.WRX",        /* 0x4e */
11226       "rex.WRXB",       /* 0x4f */
11227     };
11228
11229   switch (pref)
11230     {
11231     /* REX prefixes family.  */
11232     case 0x40:
11233     case 0x41:
11234     case 0x42:
11235     case 0x43:
11236     case 0x44:
11237     case 0x45:
11238     case 0x46:
11239     case 0x47:
11240     case 0x48:
11241     case 0x49:
11242     case 0x4a:
11243     case 0x4b:
11244     case 0x4c:
11245     case 0x4d:
11246     case 0x4e:
11247     case 0x4f:
11248       return rexes [pref - 0x40];
11249     case 0xf3:
11250       return "repz";
11251     case 0xf2:
11252       return "repnz";
11253     case 0xf0:
11254       return "lock";
11255     case 0x2e:
11256       return "cs";
11257     case 0x36:
11258       return "ss";
11259     case 0x3e:
11260       return "ds";
11261     case 0x26:
11262       return "es";
11263     case 0x64:
11264       return "fs";
11265     case 0x65:
11266       return "gs";
11267     case 0x66:
11268       return (sizeflag & DFLAG) ? "data16" : "data32";
11269     case 0x67:
11270       if (address_mode == mode_64bit)
11271         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11272       else
11273         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11274     case FWAIT_OPCODE:
11275       return "fwait";
11276     case REP_PREFIX:
11277       return "rep";
11278     case XACQUIRE_PREFIX:
11279       return "xacquire";
11280     case XRELEASE_PREFIX:
11281       return "xrelease";
11282     case BND_PREFIX:
11283       return "bnd";
11284     case NOTRACK_PREFIX:
11285       return "notrack";
11286     default:
11287       return NULL;
11288     }
11289 }
11290
11291 static char op_out[MAX_OPERANDS][100];
11292 static int op_ad, op_index[MAX_OPERANDS];
11293 static int two_source_ops;
11294 static bfd_vma op_address[MAX_OPERANDS];
11295 static bfd_vma op_riprel[MAX_OPERANDS];
11296 static bfd_vma start_pc;
11297
11298 /*
11299  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11300  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11301  *   section of the "Virtual 8086 Mode" chapter.)
11302  * 'pc' should be the address of this instruction, it will
11303  *   be used to print the target address if this is a relative jump or call
11304  * The function returns the length of this instruction in bytes.
11305  */
11306
11307 static char intel_syntax;
11308 static char intel_mnemonic = !SYSV386_COMPAT;
11309 static char open_char;
11310 static char close_char;
11311 static char separator_char;
11312 static char scale_char;
11313
11314 enum x86_64_isa
11315 {
11316   amd64 = 0,
11317   intel64
11318 };
11319
11320 static enum x86_64_isa isa64;
11321
11322 /* Here for backwards compatibility.  When gdb stops using
11323    print_insn_i386_att and print_insn_i386_intel these functions can
11324    disappear, and print_insn_i386 be merged into print_insn.  */
11325 int
11326 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11327 {
11328   intel_syntax = 0;
11329
11330   return print_insn (pc, info);
11331 }
11332
11333 int
11334 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11335 {
11336   intel_syntax = 1;
11337
11338   return print_insn (pc, info);
11339 }
11340
11341 int
11342 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11343 {
11344   intel_syntax = -1;
11345
11346   return print_insn (pc, info);
11347 }
11348
11349 void
11350 print_i386_disassembler_options (FILE *stream)
11351 {
11352   fprintf (stream, _("\n\
11353 The following i386/x86-64 specific disassembler options are supported for use\n\
11354 with the -M switch (multiple options should be separated by commas):\n"));
11355
11356   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11357   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11358   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11359   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11360   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11361   fprintf (stream, _("  att-mnemonic\n"
11362                      "              Display instruction in AT&T mnemonic\n"));
11363   fprintf (stream, _("  intel-mnemonic\n"
11364                      "              Display instruction in Intel mnemonic\n"));
11365   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11366   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11367   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11368   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11369   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11370   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11371   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11372   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11373 }
11374
11375 /* Bad opcode.  */
11376 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11377
11378 /* Get a pointer to struct dis386 with a valid name.  */
11379
11380 static const struct dis386 *
11381 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11382 {
11383   int vindex, vex_table_index;
11384
11385   if (dp->name != NULL)
11386     return dp;
11387
11388   switch (dp->op[0].bytemode)
11389     {
11390     case USE_REG_TABLE:
11391       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11392       break;
11393
11394     case USE_MOD_TABLE:
11395       vindex = modrm.mod == 0x3 ? 1 : 0;
11396       dp = &mod_table[dp->op[1].bytemode][vindex];
11397       break;
11398
11399     case USE_RM_TABLE:
11400       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11401       break;
11402
11403     case USE_PREFIX_TABLE:
11404       if (need_vex)
11405         {
11406           /* The prefix in VEX is implicit.  */
11407           switch (vex.prefix)
11408             {
11409             case 0:
11410               vindex = 0;
11411               break;
11412             case REPE_PREFIX_OPCODE:
11413               vindex = 1;
11414               break;
11415             case DATA_PREFIX_OPCODE:
11416               vindex = 2;
11417               break;
11418             case REPNE_PREFIX_OPCODE:
11419               vindex = 3;
11420               break;
11421             default:
11422               abort ();
11423               break;
11424             }
11425         }
11426       else
11427         {
11428           int last_prefix = -1;
11429           int prefix = 0;
11430           vindex = 0;
11431           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11432              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11433              last one wins.  */
11434           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11435             {
11436               if (last_repz_prefix > last_repnz_prefix)
11437                 {
11438                   vindex = 1;
11439                   prefix = PREFIX_REPZ;
11440                   last_prefix = last_repz_prefix;
11441                 }
11442               else
11443                 {
11444                   vindex = 3;
11445                   prefix = PREFIX_REPNZ;
11446                   last_prefix = last_repnz_prefix;
11447                 }
11448
11449               /* Check if prefix should be ignored.  */
11450               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11451                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11452                    & prefix) != 0)
11453                 vindex = 0;
11454             }
11455
11456           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11457             {
11458               vindex = 2;
11459               prefix = PREFIX_DATA;
11460               last_prefix = last_data_prefix;
11461             }
11462
11463           if (vindex != 0)
11464             {
11465               used_prefixes |= prefix;
11466               all_prefixes[last_prefix] = 0;
11467             }
11468         }
11469       dp = &prefix_table[dp->op[1].bytemode][vindex];
11470       break;
11471
11472     case USE_X86_64_TABLE:
11473       vindex = address_mode == mode_64bit ? 1 : 0;
11474       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11475       break;
11476
11477     case USE_3BYTE_TABLE:
11478       FETCH_DATA (info, codep + 2);
11479       vindex = *codep++;
11480       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11481       end_codep = codep;
11482       modrm.mod = (*codep >> 6) & 3;
11483       modrm.reg = (*codep >> 3) & 7;
11484       modrm.rm = *codep & 7;
11485       break;
11486
11487     case USE_VEX_LEN_TABLE:
11488       if (!need_vex)
11489         abort ();
11490
11491       switch (vex.length)
11492         {
11493         case 128:
11494           vindex = 0;
11495           break;
11496         case 256:
11497           vindex = 1;
11498           break;
11499         default:
11500           abort ();
11501           break;
11502         }
11503
11504       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11505       break;
11506
11507     case USE_EVEX_LEN_TABLE:
11508       if (!vex.evex)
11509         abort ();
11510
11511       switch (vex.length)
11512         {
11513         case 128:
11514           vindex = 0;
11515           break;
11516         case 256:
11517           vindex = 1;
11518           break;
11519         case 512:
11520           vindex = 2;
11521           break;
11522         default:
11523           abort ();
11524           break;
11525         }
11526
11527       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11528       break;
11529
11530     case USE_XOP_8F_TABLE:
11531       FETCH_DATA (info, codep + 3);
11532       /* All bits in the REX prefix are ignored.  */
11533       rex_ignored = rex;
11534       rex = ~(*codep >> 5) & 0x7;
11535
11536       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11537       switch ((*codep & 0x1f))
11538         {
11539         default:
11540           dp = &bad_opcode;
11541           return dp;
11542         case 0x8:
11543           vex_table_index = XOP_08;
11544           break;
11545         case 0x9:
11546           vex_table_index = XOP_09;
11547           break;
11548         case 0xa:
11549           vex_table_index = XOP_0A;
11550           break;
11551         }
11552       codep++;
11553       vex.w = *codep & 0x80;
11554       if (vex.w && address_mode == mode_64bit)
11555         rex |= REX_W;
11556
11557       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11558       if (address_mode != mode_64bit)
11559         {
11560           /* In 16/32-bit mode REX_B is silently ignored.  */
11561           rex &= ~REX_B;
11562         }
11563
11564       vex.length = (*codep & 0x4) ? 256 : 128;
11565       switch ((*codep & 0x3))
11566         {
11567         case 0:
11568           break;
11569         case 1:
11570           vex.prefix = DATA_PREFIX_OPCODE;
11571           break;
11572         case 2:
11573           vex.prefix = REPE_PREFIX_OPCODE;
11574           break;
11575         case 3:
11576           vex.prefix = REPNE_PREFIX_OPCODE;
11577           break;
11578         }
11579       need_vex = 1;
11580       need_vex_reg = 1;
11581       codep++;
11582       vindex = *codep++;
11583       dp = &xop_table[vex_table_index][vindex];
11584
11585       end_codep = codep;
11586       FETCH_DATA (info, codep + 1);
11587       modrm.mod = (*codep >> 6) & 3;
11588       modrm.reg = (*codep >> 3) & 7;
11589       modrm.rm = *codep & 7;
11590       break;
11591
11592     case USE_VEX_C4_TABLE:
11593       /* VEX prefix.  */
11594       FETCH_DATA (info, codep + 3);
11595       /* All bits in the REX prefix are ignored.  */
11596       rex_ignored = rex;
11597       rex = ~(*codep >> 5) & 0x7;
11598       switch ((*codep & 0x1f))
11599         {
11600         default:
11601           dp = &bad_opcode;
11602           return dp;
11603         case 0x1:
11604           vex_table_index = VEX_0F;
11605           break;
11606         case 0x2:
11607           vex_table_index = VEX_0F38;
11608           break;
11609         case 0x3:
11610           vex_table_index = VEX_0F3A;
11611           break;
11612         }
11613       codep++;
11614       vex.w = *codep & 0x80;
11615       if (address_mode == mode_64bit)
11616         {
11617           if (vex.w)
11618             rex |= REX_W;
11619         }
11620       else
11621         {
11622           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11623              is ignored, other REX bits are 0 and the highest bit in
11624              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11625           rex = 0;
11626         }
11627       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11628       vex.length = (*codep & 0x4) ? 256 : 128;
11629       switch ((*codep & 0x3))
11630         {
11631         case 0:
11632           break;
11633         case 1:
11634           vex.prefix = DATA_PREFIX_OPCODE;
11635           break;
11636         case 2:
11637           vex.prefix = REPE_PREFIX_OPCODE;
11638           break;
11639         case 3:
11640           vex.prefix = REPNE_PREFIX_OPCODE;
11641           break;
11642         }
11643       need_vex = 1;
11644       need_vex_reg = 1;
11645       codep++;
11646       vindex = *codep++;
11647       dp = &vex_table[vex_table_index][vindex];
11648       end_codep = codep;
11649       /* There is no MODRM byte for VEX0F 77.  */
11650       if (vex_table_index != VEX_0F || vindex != 0x77)
11651         {
11652           FETCH_DATA (info, codep + 1);
11653           modrm.mod = (*codep >> 6) & 3;
11654           modrm.reg = (*codep >> 3) & 7;
11655           modrm.rm = *codep & 7;
11656         }
11657       break;
11658
11659     case USE_VEX_C5_TABLE:
11660       /* VEX prefix.  */
11661       FETCH_DATA (info, codep + 2);
11662       /* All bits in the REX prefix are ignored.  */
11663       rex_ignored = rex;
11664       rex = (*codep & 0x80) ? 0 : REX_R;
11665
11666       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11667          VEX.vvvv is 1.  */
11668       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11669       vex.length = (*codep & 0x4) ? 256 : 128;
11670       switch ((*codep & 0x3))
11671         {
11672         case 0:
11673           break;
11674         case 1:
11675           vex.prefix = DATA_PREFIX_OPCODE;
11676           break;
11677         case 2:
11678           vex.prefix = REPE_PREFIX_OPCODE;
11679           break;
11680         case 3:
11681           vex.prefix = REPNE_PREFIX_OPCODE;
11682           break;
11683         }
11684       need_vex = 1;
11685       need_vex_reg = 1;
11686       codep++;
11687       vindex = *codep++;
11688       dp = &vex_table[dp->op[1].bytemode][vindex];
11689       end_codep = codep;
11690       /* There is no MODRM byte for VEX 77.  */
11691       if (vindex != 0x77)
11692         {
11693           FETCH_DATA (info, codep + 1);
11694           modrm.mod = (*codep >> 6) & 3;
11695           modrm.reg = (*codep >> 3) & 7;
11696           modrm.rm = *codep & 7;
11697         }
11698       break;
11699
11700     case USE_VEX_W_TABLE:
11701       if (!need_vex)
11702         abort ();
11703
11704       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11705       break;
11706
11707     case USE_EVEX_TABLE:
11708       two_source_ops = 0;
11709       /* EVEX prefix.  */
11710       vex.evex = 1;
11711       FETCH_DATA (info, codep + 4);
11712       /* All bits in the REX prefix are ignored.  */
11713       rex_ignored = rex;
11714       /* The first byte after 0x62.  */
11715       rex = ~(*codep >> 5) & 0x7;
11716       vex.r = *codep & 0x10;
11717       switch ((*codep & 0xf))
11718         {
11719         default:
11720           return &bad_opcode;
11721         case 0x1:
11722           vex_table_index = EVEX_0F;
11723           break;
11724         case 0x2:
11725           vex_table_index = EVEX_0F38;
11726           break;
11727         case 0x3:
11728           vex_table_index = EVEX_0F3A;
11729           break;
11730         }
11731
11732       /* The second byte after 0x62.  */
11733       codep++;
11734       vex.w = *codep & 0x80;
11735       if (vex.w && address_mode == mode_64bit)
11736         rex |= REX_W;
11737
11738       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11739
11740       /* The U bit.  */
11741       if (!(*codep & 0x4))
11742         return &bad_opcode;
11743
11744       switch ((*codep & 0x3))
11745         {
11746         case 0:
11747           break;
11748         case 1:
11749           vex.prefix = DATA_PREFIX_OPCODE;
11750           break;
11751         case 2:
11752           vex.prefix = REPE_PREFIX_OPCODE;
11753           break;
11754         case 3:
11755           vex.prefix = REPNE_PREFIX_OPCODE;
11756           break;
11757         }
11758
11759       /* The third byte after 0x62.  */
11760       codep++;
11761
11762       /* Remember the static rounding bits.  */
11763       vex.ll = (*codep >> 5) & 3;
11764       vex.b = (*codep & 0x10) != 0;
11765
11766       vex.v = *codep & 0x8;
11767       vex.mask_register_specifier = *codep & 0x7;
11768       vex.zeroing = *codep & 0x80;
11769
11770       if (address_mode != mode_64bit)
11771         {
11772           /* In 16/32-bit mode silently ignore following bits.  */
11773           rex &= ~REX_B;
11774           vex.r = 1;
11775           vex.v = 1;
11776         }
11777
11778       need_vex = 1;
11779       need_vex_reg = 1;
11780       codep++;
11781       vindex = *codep++;
11782       dp = &evex_table[vex_table_index][vindex];
11783       end_codep = codep;
11784       FETCH_DATA (info, codep + 1);
11785       modrm.mod = (*codep >> 6) & 3;
11786       modrm.reg = (*codep >> 3) & 7;
11787       modrm.rm = *codep & 7;
11788
11789       /* Set vector length.  */
11790       if (modrm.mod == 3 && vex.b)
11791         vex.length = 512;
11792       else
11793         {
11794           switch (vex.ll)
11795             {
11796             case 0x0:
11797               vex.length = 128;
11798               break;
11799             case 0x1:
11800               vex.length = 256;
11801               break;
11802             case 0x2:
11803               vex.length = 512;
11804               break;
11805             default:
11806               return &bad_opcode;
11807             }
11808         }
11809       break;
11810
11811     case 0:
11812       dp = &bad_opcode;
11813       break;
11814
11815     default:
11816       abort ();
11817     }
11818
11819   if (dp->name != NULL)
11820     return dp;
11821   else
11822     return get_valid_dis386 (dp, info);
11823 }
11824
11825 static void
11826 get_sib (disassemble_info *info, int sizeflag)
11827 {
11828   /* If modrm.mod == 3, operand must be register.  */
11829   if (need_modrm
11830       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11831       && modrm.mod != 3
11832       && modrm.rm == 4)
11833     {
11834       FETCH_DATA (info, codep + 2);
11835       sib.index = (codep [1] >> 3) & 7;
11836       sib.scale = (codep [1] >> 6) & 3;
11837       sib.base = codep [1] & 7;
11838     }
11839 }
11840
11841 static int
11842 print_insn (bfd_vma pc, disassemble_info *info)
11843 {
11844   const struct dis386 *dp;
11845   int i;
11846   char *op_txt[MAX_OPERANDS];
11847   int needcomma;
11848   int sizeflag, orig_sizeflag;
11849   const char *p;
11850   struct dis_private priv;
11851   int prefix_length;
11852
11853   priv.orig_sizeflag = AFLAG | DFLAG;
11854   if ((info->mach & bfd_mach_i386_i386) != 0)
11855     address_mode = mode_32bit;
11856   else if (info->mach == bfd_mach_i386_i8086)
11857     {
11858       address_mode = mode_16bit;
11859       priv.orig_sizeflag = 0;
11860     }
11861   else
11862     address_mode = mode_64bit;
11863
11864   if (intel_syntax == (char) -1)
11865     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11866
11867   for (p = info->disassembler_options; p != NULL; )
11868     {
11869       if (CONST_STRNEQ (p, "amd64"))
11870         isa64 = amd64;
11871       else if (CONST_STRNEQ (p, "intel64"))
11872         isa64 = intel64;
11873       else if (CONST_STRNEQ (p, "x86-64"))
11874         {
11875           address_mode = mode_64bit;
11876           priv.orig_sizeflag = AFLAG | DFLAG;
11877         }
11878       else if (CONST_STRNEQ (p, "i386"))
11879         {
11880           address_mode = mode_32bit;
11881           priv.orig_sizeflag = AFLAG | DFLAG;
11882         }
11883       else if (CONST_STRNEQ (p, "i8086"))
11884         {
11885           address_mode = mode_16bit;
11886           priv.orig_sizeflag = 0;
11887         }
11888       else if (CONST_STRNEQ (p, "intel"))
11889         {
11890           intel_syntax = 1;
11891           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11892             intel_mnemonic = 1;
11893         }
11894       else if (CONST_STRNEQ (p, "att"))
11895         {
11896           intel_syntax = 0;
11897           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11898             intel_mnemonic = 0;
11899         }
11900       else if (CONST_STRNEQ (p, "addr"))
11901         {
11902           if (address_mode == mode_64bit)
11903             {
11904               if (p[4] == '3' && p[5] == '2')
11905                 priv.orig_sizeflag &= ~AFLAG;
11906               else if (p[4] == '6' && p[5] == '4')
11907                 priv.orig_sizeflag |= AFLAG;
11908             }
11909           else
11910             {
11911               if (p[4] == '1' && p[5] == '6')
11912                 priv.orig_sizeflag &= ~AFLAG;
11913               else if (p[4] == '3' && p[5] == '2')
11914                 priv.orig_sizeflag |= AFLAG;
11915             }
11916         }
11917       else if (CONST_STRNEQ (p, "data"))
11918         {
11919           if (p[4] == '1' && p[5] == '6')
11920             priv.orig_sizeflag &= ~DFLAG;
11921           else if (p[4] == '3' && p[5] == '2')
11922             priv.orig_sizeflag |= DFLAG;
11923         }
11924       else if (CONST_STRNEQ (p, "suffix"))
11925         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11926
11927       p = strchr (p, ',');
11928       if (p != NULL)
11929         p++;
11930     }
11931
11932   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11933     {
11934       (*info->fprintf_func) (info->stream,
11935                              _("64-bit address is disabled"));
11936       return -1;
11937     }
11938
11939   if (intel_syntax)
11940     {
11941       names64 = intel_names64;
11942       names32 = intel_names32;
11943       names16 = intel_names16;
11944       names8 = intel_names8;
11945       names8rex = intel_names8rex;
11946       names_seg = intel_names_seg;
11947       names_mm = intel_names_mm;
11948       names_bnd = intel_names_bnd;
11949       names_xmm = intel_names_xmm;
11950       names_ymm = intel_names_ymm;
11951       names_zmm = intel_names_zmm;
11952       index64 = intel_index64;
11953       index32 = intel_index32;
11954       names_mask = intel_names_mask;
11955       index16 = intel_index16;
11956       open_char = '[';
11957       close_char = ']';
11958       separator_char = '+';
11959       scale_char = '*';
11960     }
11961   else
11962     {
11963       names64 = att_names64;
11964       names32 = att_names32;
11965       names16 = att_names16;
11966       names8 = att_names8;
11967       names8rex = att_names8rex;
11968       names_seg = att_names_seg;
11969       names_mm = att_names_mm;
11970       names_bnd = att_names_bnd;
11971       names_xmm = att_names_xmm;
11972       names_ymm = att_names_ymm;
11973       names_zmm = att_names_zmm;
11974       index64 = att_index64;
11975       index32 = att_index32;
11976       names_mask = att_names_mask;
11977       index16 = att_index16;
11978       open_char = '(';
11979       close_char =  ')';
11980       separator_char = ',';
11981       scale_char = ',';
11982     }
11983
11984   /* The output looks better if we put 7 bytes on a line, since that
11985      puts most long word instructions on a single line.  Use 8 bytes
11986      for Intel L1OM.  */
11987   if ((info->mach & bfd_mach_l1om) != 0)
11988     info->bytes_per_line = 8;
11989   else
11990     info->bytes_per_line = 7;
11991
11992   info->private_data = &priv;
11993   priv.max_fetched = priv.the_buffer;
11994   priv.insn_start = pc;
11995
11996   obuf[0] = 0;
11997   for (i = 0; i < MAX_OPERANDS; ++i)
11998     {
11999       op_out[i][0] = 0;
12000       op_index[i] = -1;
12001     }
12002
12003   the_info = info;
12004   start_pc = pc;
12005   start_codep = priv.the_buffer;
12006   codep = priv.the_buffer;
12007
12008   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12009     {
12010       const char *name;
12011
12012       /* Getting here means we tried for data but didn't get it.  That
12013          means we have an incomplete instruction of some sort.  Just
12014          print the first byte as a prefix or a .byte pseudo-op.  */
12015       if (codep > priv.the_buffer)
12016         {
12017           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12018           if (name != NULL)
12019             (*info->fprintf_func) (info->stream, "%s", name);
12020           else
12021             {
12022               /* Just print the first byte as a .byte instruction.  */
12023               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12024                                      (unsigned int) priv.the_buffer[0]);
12025             }
12026
12027           return 1;
12028         }
12029
12030       return -1;
12031     }
12032
12033   obufp = obuf;
12034   sizeflag = priv.orig_sizeflag;
12035
12036   if (!ckprefix () || rex_used)
12037     {
12038       /* Too many prefixes or unused REX prefixes.  */
12039       for (i = 0;
12040            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12041            i++)
12042         (*info->fprintf_func) (info->stream, "%s%s",
12043                                i == 0 ? "" : " ",
12044                                prefix_name (all_prefixes[i], sizeflag));
12045       return i;
12046     }
12047
12048   insn_codep = codep;
12049
12050   FETCH_DATA (info, codep + 1);
12051   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12052
12053   if (((prefixes & PREFIX_FWAIT)
12054        && ((*codep < 0xd8) || (*codep > 0xdf))))
12055     {
12056       /* Handle prefixes before fwait.  */
12057       for (i = 0; i < fwait_prefix && all_prefixes[i];
12058            i++)
12059         (*info->fprintf_func) (info->stream, "%s ",
12060                                prefix_name (all_prefixes[i], sizeflag));
12061       (*info->fprintf_func) (info->stream, "fwait");
12062       return i + 1;
12063     }
12064
12065   if (*codep == 0x0f)
12066     {
12067       unsigned char threebyte;
12068
12069       codep++;
12070       FETCH_DATA (info, codep + 1);
12071       threebyte = *codep;
12072       dp = &dis386_twobyte[threebyte];
12073       need_modrm = twobyte_has_modrm[*codep];
12074       codep++;
12075     }
12076   else
12077     {
12078       dp = &dis386[*codep];
12079       need_modrm = onebyte_has_modrm[*codep];
12080       codep++;
12081     }
12082
12083   /* Save sizeflag for printing the extra prefixes later before updating
12084      it for mnemonic and operand processing.  The prefix names depend
12085      only on the address mode.  */
12086   orig_sizeflag = sizeflag;
12087   if (prefixes & PREFIX_ADDR)
12088     sizeflag ^= AFLAG;
12089   if ((prefixes & PREFIX_DATA))
12090     sizeflag ^= DFLAG;
12091
12092   end_codep = codep;
12093   if (need_modrm)
12094     {
12095       FETCH_DATA (info, codep + 1);
12096       modrm.mod = (*codep >> 6) & 3;
12097       modrm.reg = (*codep >> 3) & 7;
12098       modrm.rm = *codep & 7;
12099     }
12100
12101   need_vex = 0;
12102   need_vex_reg = 0;
12103   vex_w_done = 0;
12104   memset (&vex, 0, sizeof (vex));
12105
12106   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12107     {
12108       get_sib (info, sizeflag);
12109       dofloat (sizeflag);
12110     }
12111   else
12112     {
12113       dp = get_valid_dis386 (dp, info);
12114       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12115         {
12116           get_sib (info, sizeflag);
12117           for (i = 0; i < MAX_OPERANDS; ++i)
12118             {
12119               obufp = op_out[i];
12120               op_ad = MAX_OPERANDS - 1 - i;
12121               if (dp->op[i].rtn)
12122                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12123               /* For EVEX instruction after the last operand masking
12124                  should be printed.  */
12125               if (i == 0 && vex.evex)
12126                 {
12127                   /* Don't print {%k0}.  */
12128                   if (vex.mask_register_specifier)
12129                     {
12130                       oappend ("{");
12131                       oappend (names_mask[vex.mask_register_specifier]);
12132                       oappend ("}");
12133                     }
12134                   if (vex.zeroing)
12135                     oappend ("{z}");
12136                 }
12137             }
12138         }
12139     }
12140
12141   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12142      are all 0s in inverted form.  */
12143   if (need_vex && vex.register_specifier != 0)
12144     {
12145       (*info->fprintf_func) (info->stream, "(bad)");
12146       return end_codep - priv.the_buffer;
12147     }
12148
12149   /* Check if the REX prefix is used.  */
12150   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12151     all_prefixes[last_rex_prefix] = 0;
12152
12153   /* Check if the SEG prefix is used.  */
12154   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12155                    | PREFIX_FS | PREFIX_GS)) != 0
12156       && (used_prefixes & active_seg_prefix) != 0)
12157     all_prefixes[last_seg_prefix] = 0;
12158
12159   /* Check if the ADDR prefix is used.  */
12160   if ((prefixes & PREFIX_ADDR) != 0
12161       && (used_prefixes & PREFIX_ADDR) != 0)
12162     all_prefixes[last_addr_prefix] = 0;
12163
12164   /* Check if the DATA prefix is used.  */
12165   if ((prefixes & PREFIX_DATA) != 0
12166       && (used_prefixes & PREFIX_DATA) != 0)
12167     all_prefixes[last_data_prefix] = 0;
12168
12169   /* Print the extra prefixes.  */
12170   prefix_length = 0;
12171   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12172     if (all_prefixes[i])
12173       {
12174         const char *name;
12175         name = prefix_name (all_prefixes[i], orig_sizeflag);
12176         if (name == NULL)
12177           abort ();
12178         prefix_length += strlen (name) + 1;
12179         (*info->fprintf_func) (info->stream, "%s ", name);
12180       }
12181
12182   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12183      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12184      used by putop and MMX/SSE operand and may be overriden by the
12185      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12186      separately.  */
12187   if (dp->prefix_requirement == PREFIX_OPCODE
12188       && dp != &bad_opcode
12189       && (((prefixes
12190             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12191            && (used_prefixes
12192                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12193           || ((((prefixes
12194                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12195                 == PREFIX_DATA)
12196                && (used_prefixes & PREFIX_DATA) == 0))))
12197     {
12198       (*info->fprintf_func) (info->stream, "(bad)");
12199       return end_codep - priv.the_buffer;
12200     }
12201
12202   /* Check maximum code length.  */
12203   if ((codep - start_codep) > MAX_CODE_LENGTH)
12204     {
12205       (*info->fprintf_func) (info->stream, "(bad)");
12206       return MAX_CODE_LENGTH;
12207     }
12208
12209   obufp = mnemonicendp;
12210   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12211     oappend (" ");
12212   oappend (" ");
12213   (*info->fprintf_func) (info->stream, "%s", obuf);
12214
12215   /* The enter and bound instructions are printed with operands in the same
12216      order as the intel book; everything else is printed in reverse order.  */
12217   if (intel_syntax || two_source_ops)
12218     {
12219       bfd_vma riprel;
12220
12221       for (i = 0; i < MAX_OPERANDS; ++i)
12222         op_txt[i] = op_out[i];
12223
12224       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12225           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12226         {
12227           op_txt[2] = op_out[3];
12228           op_txt[3] = op_out[2];
12229         }
12230
12231       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12232         {
12233           op_ad = op_index[i];
12234           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12235           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12236           riprel = op_riprel[i];
12237           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12238           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12239         }
12240     }
12241   else
12242     {
12243       for (i = 0; i < MAX_OPERANDS; ++i)
12244         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12245     }
12246
12247   needcomma = 0;
12248   for (i = 0; i < MAX_OPERANDS; ++i)
12249     if (*op_txt[i])
12250       {
12251         if (needcomma)
12252           (*info->fprintf_func) (info->stream, ",");
12253         if (op_index[i] != -1 && !op_riprel[i])
12254           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12255         else
12256           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12257         needcomma = 1;
12258       }
12259
12260   for (i = 0; i < MAX_OPERANDS; i++)
12261     if (op_index[i] != -1 && op_riprel[i])
12262       {
12263         (*info->fprintf_func) (info->stream, "        # ");
12264         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12265                                                 + op_address[op_index[i]]), info);
12266         break;
12267       }
12268   return codep - priv.the_buffer;
12269 }
12270
12271 static const char *float_mem[] = {
12272   /* d8 */
12273   "fadd{s|}",
12274   "fmul{s|}",
12275   "fcom{s|}",
12276   "fcomp{s|}",
12277   "fsub{s|}",
12278   "fsubr{s|}",
12279   "fdiv{s|}",
12280   "fdivr{s|}",
12281   /* d9 */
12282   "fld{s|}",
12283   "(bad)",
12284   "fst{s|}",
12285   "fstp{s|}",
12286   "fldenvIC",
12287   "fldcw",
12288   "fNstenvIC",
12289   "fNstcw",
12290   /* da */
12291   "fiadd{l|}",
12292   "fimul{l|}",
12293   "ficom{l|}",
12294   "ficomp{l|}",
12295   "fisub{l|}",
12296   "fisubr{l|}",
12297   "fidiv{l|}",
12298   "fidivr{l|}",
12299   /* db */
12300   "fild{l|}",
12301   "fisttp{l|}",
12302   "fist{l|}",
12303   "fistp{l|}",
12304   "(bad)",
12305   "fld{t||t|}",
12306   "(bad)",
12307   "fstp{t||t|}",
12308   /* dc */
12309   "fadd{l|}",
12310   "fmul{l|}",
12311   "fcom{l|}",
12312   "fcomp{l|}",
12313   "fsub{l|}",
12314   "fsubr{l|}",
12315   "fdiv{l|}",
12316   "fdivr{l|}",
12317   /* dd */
12318   "fld{l|}",
12319   "fisttp{ll|}",
12320   "fst{l||}",
12321   "fstp{l|}",
12322   "frstorIC",
12323   "(bad)",
12324   "fNsaveIC",
12325   "fNstsw",
12326   /* de */
12327   "fiadd{s|}",
12328   "fimul{s|}",
12329   "ficom{s|}",
12330   "ficomp{s|}",
12331   "fisub{s|}",
12332   "fisubr{s|}",
12333   "fidiv{s|}",
12334   "fidivr{s|}",
12335   /* df */
12336   "fild{s|}",
12337   "fisttp{s|}",
12338   "fist{s|}",
12339   "fistp{s|}",
12340   "fbld",
12341   "fild{ll|}",
12342   "fbstp",
12343   "fistp{ll|}",
12344 };
12345
12346 static const unsigned char float_mem_mode[] = {
12347   /* d8 */
12348   d_mode,
12349   d_mode,
12350   d_mode,
12351   d_mode,
12352   d_mode,
12353   d_mode,
12354   d_mode,
12355   d_mode,
12356   /* d9 */
12357   d_mode,
12358   0,
12359   d_mode,
12360   d_mode,
12361   0,
12362   w_mode,
12363   0,
12364   w_mode,
12365   /* da */
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   /* db */
12375   d_mode,
12376   d_mode,
12377   d_mode,
12378   d_mode,
12379   0,
12380   t_mode,
12381   0,
12382   t_mode,
12383   /* dc */
12384   q_mode,
12385   q_mode,
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   q_mode,
12392   /* dd */
12393   q_mode,
12394   q_mode,
12395   q_mode,
12396   q_mode,
12397   0,
12398   0,
12399   0,
12400   w_mode,
12401   /* de */
12402   w_mode,
12403   w_mode,
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   w_mode,
12410   /* df */
12411   w_mode,
12412   w_mode,
12413   w_mode,
12414   w_mode,
12415   t_mode,
12416   q_mode,
12417   t_mode,
12418   q_mode
12419 };
12420
12421 #define ST { OP_ST, 0 }
12422 #define STi { OP_STi, 0 }
12423
12424 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12425 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12426 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12427 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12428 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12429 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12430 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12431 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12432 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12433
12434 static const struct dis386 float_reg[][8] = {
12435   /* d8 */
12436   {
12437     { "fadd",   { ST, STi }, 0 },
12438     { "fmul",   { ST, STi }, 0 },
12439     { "fcom",   { STi }, 0 },
12440     { "fcomp",  { STi }, 0 },
12441     { "fsub",   { ST, STi }, 0 },
12442     { "fsubr",  { ST, STi }, 0 },
12443     { "fdiv",   { ST, STi }, 0 },
12444     { "fdivr",  { ST, STi }, 0 },
12445   },
12446   /* d9 */
12447   {
12448     { "fld",    { STi }, 0 },
12449     { "fxch",   { STi }, 0 },
12450     { FGRPd9_2 },
12451     { Bad_Opcode },
12452     { FGRPd9_4 },
12453     { FGRPd9_5 },
12454     { FGRPd9_6 },
12455     { FGRPd9_7 },
12456   },
12457   /* da */
12458   {
12459     { "fcmovb", { ST, STi }, 0 },
12460     { "fcmove", { ST, STi }, 0 },
12461     { "fcmovbe",{ ST, STi }, 0 },
12462     { "fcmovu", { ST, STi }, 0 },
12463     { Bad_Opcode },
12464     { FGRPda_5 },
12465     { Bad_Opcode },
12466     { Bad_Opcode },
12467   },
12468   /* db */
12469   {
12470     { "fcmovnb",{ ST, STi }, 0 },
12471     { "fcmovne",{ ST, STi }, 0 },
12472     { "fcmovnbe",{ ST, STi }, 0 },
12473     { "fcmovnu",{ ST, STi }, 0 },
12474     { FGRPdb_4 },
12475     { "fucomi", { ST, STi }, 0 },
12476     { "fcomi",  { ST, STi }, 0 },
12477     { Bad_Opcode },
12478   },
12479   /* dc */
12480   {
12481     { "fadd",   { STi, ST }, 0 },
12482     { "fmul",   { STi, ST }, 0 },
12483     { Bad_Opcode },
12484     { Bad_Opcode },
12485     { "fsub{!M|r}",     { STi, ST }, 0 },
12486     { "fsub{M|}",       { STi, ST }, 0 },
12487     { "fdiv{!M|r}",     { STi, ST }, 0 },
12488     { "fdiv{M|}",       { STi, ST }, 0 },
12489   },
12490   /* dd */
12491   {
12492     { "ffree",  { STi }, 0 },
12493     { Bad_Opcode },
12494     { "fst",    { STi }, 0 },
12495     { "fstp",   { STi }, 0 },
12496     { "fucom",  { STi }, 0 },
12497     { "fucomp", { STi }, 0 },
12498     { Bad_Opcode },
12499     { Bad_Opcode },
12500   },
12501   /* de */
12502   {
12503     { "faddp",  { STi, ST }, 0 },
12504     { "fmulp",  { STi, ST }, 0 },
12505     { Bad_Opcode },
12506     { FGRPde_3 },
12507     { "fsub{!M|r}p",    { STi, ST }, 0 },
12508     { "fsub{M|}p",      { STi, ST }, 0 },
12509     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12510     { "fdiv{M|}p",      { STi, ST }, 0 },
12511   },
12512   /* df */
12513   {
12514     { "ffreep", { STi }, 0 },
12515     { Bad_Opcode },
12516     { Bad_Opcode },
12517     { Bad_Opcode },
12518     { FGRPdf_4 },
12519     { "fucomip", { ST, STi }, 0 },
12520     { "fcomip", { ST, STi }, 0 },
12521     { Bad_Opcode },
12522   },
12523 };
12524
12525 static char *fgrps[][8] = {
12526   /* Bad opcode 0 */
12527   {
12528     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12529   },
12530
12531   /* d9_2  1 */
12532   {
12533     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12534   },
12535
12536   /* d9_4  2 */
12537   {
12538     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12539   },
12540
12541   /* d9_5  3 */
12542   {
12543     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12544   },
12545
12546   /* d9_6  4 */
12547   {
12548     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12549   },
12550
12551   /* d9_7  5 */
12552   {
12553     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12554   },
12555
12556   /* da_5  6 */
12557   {
12558     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12559   },
12560
12561   /* db_4  7 */
12562   {
12563     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12564     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12565   },
12566
12567   /* de_3  8 */
12568   {
12569     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12570   },
12571
12572   /* df_4  9 */
12573   {
12574     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12575   },
12576 };
12577
12578 static void
12579 swap_operand (void)
12580 {
12581   mnemonicendp[0] = '.';
12582   mnemonicendp[1] = 's';
12583   mnemonicendp += 2;
12584 }
12585
12586 static void
12587 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12588                int sizeflag ATTRIBUTE_UNUSED)
12589 {
12590   /* Skip mod/rm byte.  */
12591   MODRM_CHECK;
12592   codep++;
12593 }
12594
12595 static void
12596 dofloat (int sizeflag)
12597 {
12598   const struct dis386 *dp;
12599   unsigned char floatop;
12600
12601   floatop = codep[-1];
12602
12603   if (modrm.mod != 3)
12604     {
12605       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12606
12607       putop (float_mem[fp_indx], sizeflag);
12608       obufp = op_out[0];
12609       op_ad = 2;
12610       OP_E (float_mem_mode[fp_indx], sizeflag);
12611       return;
12612     }
12613   /* Skip mod/rm byte.  */
12614   MODRM_CHECK;
12615   codep++;
12616
12617   dp = &float_reg[floatop - 0xd8][modrm.reg];
12618   if (dp->name == NULL)
12619     {
12620       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12621
12622       /* Instruction fnstsw is only one with strange arg.  */
12623       if (floatop == 0xdf && codep[-1] == 0xe0)
12624         strcpy (op_out[0], names16[0]);
12625     }
12626   else
12627     {
12628       putop (dp->name, sizeflag);
12629
12630       obufp = op_out[0];
12631       op_ad = 2;
12632       if (dp->op[0].rtn)
12633         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12634
12635       obufp = op_out[1];
12636       op_ad = 1;
12637       if (dp->op[1].rtn)
12638         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12639     }
12640 }
12641
12642 /* Like oappend (below), but S is a string starting with '%'.
12643    In Intel syntax, the '%' is elided.  */
12644 static void
12645 oappend_maybe_intel (const char *s)
12646 {
12647   oappend (s + intel_syntax);
12648 }
12649
12650 static void
12651 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12652 {
12653   oappend_maybe_intel ("%st");
12654 }
12655
12656 static void
12657 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12658 {
12659   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12660   oappend_maybe_intel (scratchbuf);
12661 }
12662
12663 /* Capital letters in template are macros.  */
12664 static int
12665 putop (const char *in_template, int sizeflag)
12666 {
12667   const char *p;
12668   int alt = 0;
12669   int cond = 1;
12670   unsigned int l = 0, len = 1;
12671   char last[4];
12672
12673 #define SAVE_LAST(c)                    \
12674   if (l < len && l < sizeof (last))     \
12675     last[l++] = c;                      \
12676   else                                  \
12677     abort ();
12678
12679   for (p = in_template; *p; p++)
12680     {
12681       switch (*p)
12682         {
12683         default:
12684           *obufp++ = *p;
12685           break;
12686         case '%':
12687           len++;
12688           break;
12689         case '!':
12690           cond = 0;
12691           break;
12692         case '{':
12693           if (intel_syntax)
12694             {
12695               while (*++p != '|')
12696                 if (*p == '}' || *p == '\0')
12697                   abort ();
12698             }
12699           /* Fall through.  */
12700         case 'I':
12701           alt = 1;
12702           continue;
12703         case '|':
12704           while (*++p != '}')
12705             {
12706               if (*p == '\0')
12707                 abort ();
12708             }
12709           break;
12710         case '}':
12711           break;
12712         case 'A':
12713           if (intel_syntax)
12714             break;
12715           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12716             *obufp++ = 'b';
12717           break;
12718         case 'B':
12719           if (l == 0 && len == 1)
12720             {
12721 case_B:
12722               if (intel_syntax)
12723                 break;
12724               if (sizeflag & SUFFIX_ALWAYS)
12725                 *obufp++ = 'b';
12726             }
12727           else
12728             {
12729               if (l != 1
12730                   || len != 2
12731                   || last[0] != 'L')
12732                 {
12733                   SAVE_LAST (*p);
12734                   break;
12735                 }
12736
12737               if (address_mode == mode_64bit
12738                   && !(prefixes & PREFIX_ADDR))
12739                 {
12740                   *obufp++ = 'a';
12741                   *obufp++ = 'b';
12742                   *obufp++ = 's';
12743                 }
12744
12745               goto case_B;
12746             }
12747           break;
12748         case 'C':
12749           if (intel_syntax && !alt)
12750             break;
12751           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12752             {
12753               if (sizeflag & DFLAG)
12754                 *obufp++ = intel_syntax ? 'd' : 'l';
12755               else
12756                 *obufp++ = intel_syntax ? 'w' : 's';
12757               used_prefixes |= (prefixes & PREFIX_DATA);
12758             }
12759           break;
12760         case 'D':
12761           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12762             break;
12763           USED_REX (REX_W);
12764           if (modrm.mod == 3)
12765             {
12766               if (rex & REX_W)
12767                 *obufp++ = 'q';
12768               else
12769                 {
12770                   if (sizeflag & DFLAG)
12771                     *obufp++ = intel_syntax ? 'd' : 'l';
12772                   else
12773                     *obufp++ = 'w';
12774                   used_prefixes |= (prefixes & PREFIX_DATA);
12775                 }
12776             }
12777           else
12778             *obufp++ = 'w';
12779           break;
12780         case 'E':               /* For jcxz/jecxz */
12781           if (address_mode == mode_64bit)
12782             {
12783               if (sizeflag & AFLAG)
12784                 *obufp++ = 'r';
12785               else
12786                 *obufp++ = 'e';
12787             }
12788           else
12789             if (sizeflag & AFLAG)
12790               *obufp++ = 'e';
12791           used_prefixes |= (prefixes & PREFIX_ADDR);
12792           break;
12793         case 'F':
12794           if (intel_syntax)
12795             break;
12796           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12797             {
12798               if (sizeflag & AFLAG)
12799                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12800               else
12801                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12802               used_prefixes |= (prefixes & PREFIX_ADDR);
12803             }
12804           break;
12805         case 'G':
12806           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12807             break;
12808           if ((rex & REX_W) || (sizeflag & DFLAG))
12809             *obufp++ = 'l';
12810           else
12811             *obufp++ = 'w';
12812           if (!(rex & REX_W))
12813             used_prefixes |= (prefixes & PREFIX_DATA);
12814           break;
12815         case 'H':
12816           if (intel_syntax)
12817             break;
12818           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12819               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12820             {
12821               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12822               *obufp++ = ',';
12823               *obufp++ = 'p';
12824               if (prefixes & PREFIX_DS)
12825                 *obufp++ = 't';
12826               else
12827                 *obufp++ = 'n';
12828             }
12829           break;
12830         case 'J':
12831           if (intel_syntax)
12832             break;
12833           *obufp++ = 'l';
12834           break;
12835         case 'K':
12836           USED_REX (REX_W);
12837           if (rex & REX_W)
12838             *obufp++ = 'q';
12839           else
12840             *obufp++ = 'd';
12841           break;
12842         case 'Z':
12843           if (l != 0 || len != 1)
12844             {
12845               if (l != 1 || len != 2 || last[0] != 'X')
12846                 {
12847                   SAVE_LAST (*p);
12848                   break;
12849                 }
12850               if (!need_vex || !vex.evex)
12851                 abort ();
12852               if (intel_syntax
12853                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12854                 break;
12855               switch (vex.length)
12856                 {
12857                 case 128:
12858                   *obufp++ = 'x';
12859                   break;
12860                 case 256:
12861                   *obufp++ = 'y';
12862                   break;
12863                 case 512:
12864                   *obufp++ = 'z';
12865                   break;
12866                 default:
12867                   abort ();
12868                 }
12869               break;
12870             }
12871           if (intel_syntax)
12872             break;
12873           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12874             {
12875               *obufp++ = 'q';
12876               break;
12877             }
12878           /* Fall through.  */
12879           goto case_L;
12880         case 'L':
12881           if (l != 0 || len != 1)
12882             {
12883               SAVE_LAST (*p);
12884               break;
12885             }
12886 case_L:
12887           if (intel_syntax)
12888             break;
12889           if (sizeflag & SUFFIX_ALWAYS)
12890             *obufp++ = 'l';
12891           break;
12892         case 'M':
12893           if (intel_mnemonic != cond)
12894             *obufp++ = 'r';
12895           break;
12896         case 'N':
12897           if ((prefixes & PREFIX_FWAIT) == 0)
12898             *obufp++ = 'n';
12899           else
12900             used_prefixes |= PREFIX_FWAIT;
12901           break;
12902         case 'O':
12903           USED_REX (REX_W);
12904           if (rex & REX_W)
12905             *obufp++ = 'o';
12906           else if (intel_syntax && (sizeflag & DFLAG))
12907             *obufp++ = 'q';
12908           else
12909             *obufp++ = 'd';
12910           if (!(rex & REX_W))
12911             used_prefixes |= (prefixes & PREFIX_DATA);
12912           break;
12913         case '&':
12914           if (!intel_syntax
12915               && address_mode == mode_64bit
12916               && isa64 == intel64)
12917             {
12918               *obufp++ = 'q';
12919               break;
12920             }
12921           /* Fall through.  */
12922         case 'T':
12923           if (!intel_syntax
12924               && address_mode == mode_64bit
12925               && ((sizeflag & DFLAG) || (rex & REX_W)))
12926             {
12927               *obufp++ = 'q';
12928               break;
12929             }
12930           /* Fall through.  */
12931           goto case_P;
12932         case 'P':
12933           if (l == 0 && len == 1)
12934             {
12935 case_P:
12936               if (intel_syntax)
12937                 {
12938                   if ((rex & REX_W) == 0
12939                       && (prefixes & PREFIX_DATA))
12940                     {
12941                       if ((sizeflag & DFLAG) == 0)
12942                         *obufp++ = 'w';
12943                       used_prefixes |= (prefixes & PREFIX_DATA);
12944                     }
12945                   break;
12946                 }
12947               if ((prefixes & PREFIX_DATA)
12948                   || (rex & REX_W)
12949                   || (sizeflag & SUFFIX_ALWAYS))
12950                 {
12951                   USED_REX (REX_W);
12952                   if (rex & REX_W)
12953                     *obufp++ = 'q';
12954                   else
12955                     {
12956                       if (sizeflag & DFLAG)
12957                         *obufp++ = 'l';
12958                       else
12959                         *obufp++ = 'w';
12960                       used_prefixes |= (prefixes & PREFIX_DATA);
12961                     }
12962                 }
12963             }
12964           else
12965             {
12966               if (l != 1 || len != 2 || last[0] != 'L')
12967                 {
12968                   SAVE_LAST (*p);
12969                   break;
12970                 }
12971
12972               if ((prefixes & PREFIX_DATA)
12973                   || (rex & REX_W)
12974                   || (sizeflag & SUFFIX_ALWAYS))
12975                 {
12976                   USED_REX (REX_W);
12977                   if (rex & REX_W)
12978                     *obufp++ = 'q';
12979                   else
12980                     {
12981                       if (sizeflag & DFLAG)
12982                         *obufp++ = intel_syntax ? 'd' : 'l';
12983                       else
12984                         *obufp++ = 'w';
12985                       used_prefixes |= (prefixes & PREFIX_DATA);
12986                     }
12987                 }
12988             }
12989           break;
12990         case 'U':
12991           if (intel_syntax)
12992             break;
12993           if (address_mode == mode_64bit
12994               && ((sizeflag & DFLAG) || (rex & REX_W)))
12995             {
12996               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12997                 *obufp++ = 'q';
12998               break;
12999             }
13000           /* Fall through.  */
13001           goto case_Q;
13002         case 'Q':
13003           if (l == 0 && len == 1)
13004             {
13005 case_Q:
13006               if (intel_syntax && !alt)
13007                 break;
13008               USED_REX (REX_W);
13009               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13010                 {
13011                   if (rex & REX_W)
13012                     *obufp++ = 'q';
13013                   else
13014                     {
13015                       if (sizeflag & DFLAG)
13016                         *obufp++ = intel_syntax ? 'd' : 'l';
13017                       else
13018                         *obufp++ = 'w';
13019                       used_prefixes |= (prefixes & PREFIX_DATA);
13020                     }
13021                 }
13022             }
13023           else
13024             {
13025               if (l != 1 || len != 2 || last[0] != 'L')
13026                 {
13027                   SAVE_LAST (*p);
13028                   break;
13029                 }
13030               if (intel_syntax
13031                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13032                 break;
13033               if ((rex & REX_W))
13034                 {
13035                   USED_REX (REX_W);
13036                   *obufp++ = 'q';
13037                 }
13038               else
13039                 *obufp++ = 'l';
13040             }
13041           break;
13042         case 'R':
13043           USED_REX (REX_W);
13044           if (rex & REX_W)
13045             *obufp++ = 'q';
13046           else if (sizeflag & DFLAG)
13047             {
13048               if (intel_syntax)
13049                   *obufp++ = 'd';
13050               else
13051                   *obufp++ = 'l';
13052             }
13053           else
13054             *obufp++ = 'w';
13055           if (intel_syntax && !p[1]
13056               && ((rex & REX_W) || (sizeflag & DFLAG)))
13057             *obufp++ = 'e';
13058           if (!(rex & REX_W))
13059             used_prefixes |= (prefixes & PREFIX_DATA);
13060           break;
13061         case 'V':
13062           if (l == 0 && len == 1)
13063             {
13064               if (intel_syntax)
13065                 break;
13066               if (address_mode == mode_64bit
13067                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13068                 {
13069                   if (sizeflag & SUFFIX_ALWAYS)
13070                     *obufp++ = 'q';
13071                   break;
13072                 }
13073             }
13074           else
13075             {
13076               if (l != 1
13077                   || len != 2
13078                   || last[0] != 'L')
13079                 {
13080                   SAVE_LAST (*p);
13081                   break;
13082                 }
13083
13084               if (rex & REX_W)
13085                 {
13086                   *obufp++ = 'a';
13087                   *obufp++ = 'b';
13088                   *obufp++ = 's';
13089                 }
13090             }
13091           /* Fall through.  */
13092           goto case_S;
13093         case 'S':
13094           if (l == 0 && len == 1)
13095             {
13096 case_S:
13097               if (intel_syntax)
13098                 break;
13099               if (sizeflag & SUFFIX_ALWAYS)
13100                 {
13101                   if (rex & REX_W)
13102                     *obufp++ = 'q';
13103                   else
13104                     {
13105                       if (sizeflag & DFLAG)
13106                         *obufp++ = 'l';
13107                       else
13108                         *obufp++ = 'w';
13109                       used_prefixes |= (prefixes & PREFIX_DATA);
13110                     }
13111                 }
13112             }
13113           else
13114             {
13115               if (l != 1
13116                   || len != 2
13117                   || last[0] != 'L')
13118                 {
13119                   SAVE_LAST (*p);
13120                   break;
13121                 }
13122
13123               if (address_mode == mode_64bit
13124                   && !(prefixes & PREFIX_ADDR))
13125                 {
13126                   *obufp++ = 'a';
13127                   *obufp++ = 'b';
13128                   *obufp++ = 's';
13129                 }
13130
13131               goto case_S;
13132             }
13133           break;
13134         case 'X':
13135           if (l != 0 || len != 1)
13136             {
13137               SAVE_LAST (*p);
13138               break;
13139             }
13140           if (need_vex && vex.prefix)
13141             {
13142               if (vex.prefix == DATA_PREFIX_OPCODE)
13143                 *obufp++ = 'd';
13144               else
13145                 *obufp++ = 's';
13146             }
13147           else
13148             {
13149               if (prefixes & PREFIX_DATA)
13150                 *obufp++ = 'd';
13151               else
13152                 *obufp++ = 's';
13153               used_prefixes |= (prefixes & PREFIX_DATA);
13154             }
13155           break;
13156         case 'Y':
13157           if (l == 0 && len == 1)
13158             abort ();
13159           else
13160             {
13161               if (l != 1 || len != 2 || last[0] != 'X')
13162                 {
13163                   SAVE_LAST (*p);
13164                   break;
13165                 }
13166               if (!need_vex)
13167                 abort ();
13168               if (intel_syntax
13169                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13170                 break;
13171               switch (vex.length)
13172                 {
13173                 case 128:
13174                   *obufp++ = 'x';
13175                   break;
13176                 case 256:
13177                   *obufp++ = 'y';
13178                   break;
13179                 case 512:
13180                   if (!vex.evex)
13181                 default:
13182                     abort ();
13183                 }
13184             }
13185           break;
13186         case 'W':
13187           if (l == 0 && len == 1)
13188             {
13189               /* operand size flag for cwtl, cbtw */
13190               USED_REX (REX_W);
13191               if (rex & REX_W)
13192                 {
13193                   if (intel_syntax)
13194                     *obufp++ = 'd';
13195                   else
13196                     *obufp++ = 'l';
13197                 }
13198               else if (sizeflag & DFLAG)
13199                 *obufp++ = 'w';
13200               else
13201                 *obufp++ = 'b';
13202               if (!(rex & REX_W))
13203                 used_prefixes |= (prefixes & PREFIX_DATA);
13204             }
13205           else
13206             {
13207               if (l != 1
13208                   || len != 2
13209                   || (last[0] != 'X'
13210                       && last[0] != 'L'))
13211                 {
13212                   SAVE_LAST (*p);
13213                   break;
13214                 }
13215               if (!need_vex)
13216                 abort ();
13217               if (last[0] == 'X')
13218                 *obufp++ = vex.w ? 'd': 's';
13219               else
13220                 *obufp++ = vex.w ? 'q': 'd';
13221             }
13222           break;
13223         case '^':
13224           if (intel_syntax)
13225             break;
13226           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13227             {
13228               if (sizeflag & DFLAG)
13229                 *obufp++ = 'l';
13230               else
13231                 *obufp++ = 'w';
13232               used_prefixes |= (prefixes & PREFIX_DATA);
13233             }
13234           break;
13235         case '@':
13236           if (intel_syntax)
13237             break;
13238           if (address_mode == mode_64bit
13239               && (isa64 == intel64
13240                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13241               *obufp++ = 'q';
13242           else if ((prefixes & PREFIX_DATA))
13243             {
13244               if (!(sizeflag & DFLAG))
13245                 *obufp++ = 'w';
13246               used_prefixes |= (prefixes & PREFIX_DATA);
13247             }
13248           break;
13249         }
13250       alt = 0;
13251     }
13252   *obufp = 0;
13253   mnemonicendp = obufp;
13254   return 0;
13255 }
13256
13257 static void
13258 oappend (const char *s)
13259 {
13260   obufp = stpcpy (obufp, s);
13261 }
13262
13263 static void
13264 append_seg (void)
13265 {
13266   /* Only print the active segment register.  */
13267   if (!active_seg_prefix)
13268     return;
13269
13270   used_prefixes |= active_seg_prefix;
13271   switch (active_seg_prefix)
13272     {
13273     case PREFIX_CS:
13274       oappend_maybe_intel ("%cs:");
13275       break;
13276     case PREFIX_DS:
13277       oappend_maybe_intel ("%ds:");
13278       break;
13279     case PREFIX_SS:
13280       oappend_maybe_intel ("%ss:");
13281       break;
13282     case PREFIX_ES:
13283       oappend_maybe_intel ("%es:");
13284       break;
13285     case PREFIX_FS:
13286       oappend_maybe_intel ("%fs:");
13287       break;
13288     case PREFIX_GS:
13289       oappend_maybe_intel ("%gs:");
13290       break;
13291     default:
13292       break;
13293     }
13294 }
13295
13296 static void
13297 OP_indirE (int bytemode, int sizeflag)
13298 {
13299   if (!intel_syntax)
13300     oappend ("*");
13301   OP_E (bytemode, sizeflag);
13302 }
13303
13304 static void
13305 print_operand_value (char *buf, int hex, bfd_vma disp)
13306 {
13307   if (address_mode == mode_64bit)
13308     {
13309       if (hex)
13310         {
13311           char tmp[30];
13312           int i;
13313           buf[0] = '0';
13314           buf[1] = 'x';
13315           sprintf_vma (tmp, disp);
13316           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13317           strcpy (buf + 2, tmp + i);
13318         }
13319       else
13320         {
13321           bfd_signed_vma v = disp;
13322           char tmp[30];
13323           int i;
13324           if (v < 0)
13325             {
13326               *(buf++) = '-';
13327               v = -disp;
13328               /* Check for possible overflow on 0x8000000000000000.  */
13329               if (v < 0)
13330                 {
13331                   strcpy (buf, "9223372036854775808");
13332                   return;
13333                 }
13334             }
13335           if (!v)
13336             {
13337               strcpy (buf, "0");
13338               return;
13339             }
13340
13341           i = 0;
13342           tmp[29] = 0;
13343           while (v)
13344             {
13345               tmp[28 - i] = (v % 10) + '0';
13346               v /= 10;
13347               i++;
13348             }
13349           strcpy (buf, tmp + 29 - i);
13350         }
13351     }
13352   else
13353     {
13354       if (hex)
13355         sprintf (buf, "0x%x", (unsigned int) disp);
13356       else
13357         sprintf (buf, "%d", (int) disp);
13358     }
13359 }
13360
13361 /* Put DISP in BUF as signed hex number.  */
13362
13363 static void
13364 print_displacement (char *buf, bfd_vma disp)
13365 {
13366   bfd_signed_vma val = disp;
13367   char tmp[30];
13368   int i, j = 0;
13369
13370   if (val < 0)
13371     {
13372       buf[j++] = '-';
13373       val = -disp;
13374
13375       /* Check for possible overflow.  */
13376       if (val < 0)
13377         {
13378           switch (address_mode)
13379             {
13380             case mode_64bit:
13381               strcpy (buf + j, "0x8000000000000000");
13382               break;
13383             case mode_32bit:
13384               strcpy (buf + j, "0x80000000");
13385               break;
13386             case mode_16bit:
13387               strcpy (buf + j, "0x8000");
13388               break;
13389             }
13390           return;
13391         }
13392     }
13393
13394   buf[j++] = '0';
13395   buf[j++] = 'x';
13396
13397   sprintf_vma (tmp, (bfd_vma) val);
13398   for (i = 0; tmp[i] == '0'; i++)
13399     continue;
13400   if (tmp[i] == '\0')
13401     i--;
13402   strcpy (buf + j, tmp + i);
13403 }
13404
13405 static void
13406 intel_operand_size (int bytemode, int sizeflag)
13407 {
13408   if (vex.evex
13409       && vex.b
13410       && (bytemode == x_mode
13411           || bytemode == evex_half_bcst_xmmq_mode))
13412     {
13413       if (vex.w)
13414         oappend ("QWORD PTR ");
13415       else
13416         oappend ("DWORD PTR ");
13417       return;
13418     }
13419   switch (bytemode)
13420     {
13421     case b_mode:
13422     case b_swap_mode:
13423     case dqb_mode:
13424     case db_mode:
13425       oappend ("BYTE PTR ");
13426       break;
13427     case w_mode:
13428     case dw_mode:
13429     case dqw_mode:
13430       oappend ("WORD PTR ");
13431       break;
13432     case indir_v_mode:
13433       if (address_mode == mode_64bit && isa64 == intel64)
13434         {
13435           oappend ("QWORD PTR ");
13436           break;
13437         }
13438       /* Fall through.  */
13439     case stack_v_mode:
13440       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13441         {
13442           oappend ("QWORD PTR ");
13443           break;
13444         }
13445       /* Fall through.  */
13446     case v_mode:
13447     case v_swap_mode:
13448     case dq_mode:
13449       USED_REX (REX_W);
13450       if (rex & REX_W)
13451         oappend ("QWORD PTR ");
13452       else
13453         {
13454           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13455             oappend ("DWORD PTR ");
13456           else
13457             oappend ("WORD PTR ");
13458           used_prefixes |= (prefixes & PREFIX_DATA);
13459         }
13460       break;
13461     case z_mode:
13462       if ((rex & REX_W) || (sizeflag & DFLAG))
13463         *obufp++ = 'D';
13464       oappend ("WORD PTR ");
13465       if (!(rex & REX_W))
13466         used_prefixes |= (prefixes & PREFIX_DATA);
13467       break;
13468     case a_mode:
13469       if (sizeflag & DFLAG)
13470         oappend ("QWORD PTR ");
13471       else
13472         oappend ("DWORD PTR ");
13473       used_prefixes |= (prefixes & PREFIX_DATA);
13474       break;
13475     case d_mode:
13476     case d_scalar_mode:
13477     case d_scalar_swap_mode:
13478     case d_swap_mode:
13479     case dqd_mode:
13480       oappend ("DWORD PTR ");
13481       break;
13482     case q_mode:
13483     case q_scalar_mode:
13484     case q_scalar_swap_mode:
13485     case q_swap_mode:
13486       oappend ("QWORD PTR ");
13487       break;
13488     case m_mode:
13489       if (address_mode == mode_64bit)
13490         oappend ("QWORD PTR ");
13491       else
13492         oappend ("DWORD PTR ");
13493       break;
13494     case f_mode:
13495       if (sizeflag & DFLAG)
13496         oappend ("FWORD PTR ");
13497       else
13498         oappend ("DWORD PTR ");
13499       used_prefixes |= (prefixes & PREFIX_DATA);
13500       break;
13501     case t_mode:
13502       oappend ("TBYTE PTR ");
13503       break;
13504     case x_mode:
13505     case x_swap_mode:
13506     case evex_x_gscat_mode:
13507     case evex_x_nobcst_mode:
13508     case b_scalar_mode:
13509     case w_scalar_mode:
13510       if (need_vex)
13511         {
13512           switch (vex.length)
13513             {
13514             case 128:
13515               oappend ("XMMWORD PTR ");
13516               break;
13517             case 256:
13518               oappend ("YMMWORD PTR ");
13519               break;
13520             case 512:
13521               oappend ("ZMMWORD PTR ");
13522               break;
13523             default:
13524               abort ();
13525             }
13526         }
13527       else
13528         oappend ("XMMWORD PTR ");
13529       break;
13530     case xmm_mode:
13531       oappend ("XMMWORD PTR ");
13532       break;
13533     case ymm_mode:
13534       oappend ("YMMWORD PTR ");
13535       break;
13536     case xmmq_mode:
13537     case evex_half_bcst_xmmq_mode:
13538       if (!need_vex)
13539         abort ();
13540
13541       switch (vex.length)
13542         {
13543         case 128:
13544           oappend ("QWORD PTR ");
13545           break;
13546         case 256:
13547           oappend ("XMMWORD PTR ");
13548           break;
13549         case 512:
13550           oappend ("YMMWORD PTR ");
13551           break;
13552         default:
13553           abort ();
13554         }
13555       break;
13556     case xmm_mb_mode:
13557       if (!need_vex)
13558         abort ();
13559
13560       switch (vex.length)
13561         {
13562         case 128:
13563         case 256:
13564         case 512:
13565           oappend ("BYTE PTR ");
13566           break;
13567         default:
13568           abort ();
13569         }
13570       break;
13571     case xmm_mw_mode:
13572       if (!need_vex)
13573         abort ();
13574
13575       switch (vex.length)
13576         {
13577         case 128:
13578         case 256:
13579         case 512:
13580           oappend ("WORD PTR ");
13581           break;
13582         default:
13583           abort ();
13584         }
13585       break;
13586     case xmm_md_mode:
13587       if (!need_vex)
13588         abort ();
13589
13590       switch (vex.length)
13591         {
13592         case 128:
13593         case 256:
13594         case 512:
13595           oappend ("DWORD PTR ");
13596           break;
13597         default:
13598           abort ();
13599         }
13600       break;
13601     case xmm_mq_mode:
13602       if (!need_vex)
13603         abort ();
13604
13605       switch (vex.length)
13606         {
13607         case 128:
13608         case 256:
13609         case 512:
13610           oappend ("QWORD PTR ");
13611           break;
13612         default:
13613           abort ();
13614         }
13615       break;
13616     case xmmdw_mode:
13617       if (!need_vex)
13618         abort ();
13619
13620       switch (vex.length)
13621         {
13622         case 128:
13623           oappend ("WORD PTR ");
13624           break;
13625         case 256:
13626           oappend ("DWORD PTR ");
13627           break;
13628         case 512:
13629           oappend ("QWORD PTR ");
13630           break;
13631         default:
13632           abort ();
13633         }
13634       break;
13635     case xmmqd_mode:
13636       if (!need_vex)
13637         abort ();
13638
13639       switch (vex.length)
13640         {
13641         case 128:
13642           oappend ("DWORD PTR ");
13643           break;
13644         case 256:
13645           oappend ("QWORD PTR ");
13646           break;
13647         case 512:
13648           oappend ("XMMWORD PTR ");
13649           break;
13650         default:
13651           abort ();
13652         }
13653       break;
13654     case ymmq_mode:
13655       if (!need_vex)
13656         abort ();
13657
13658       switch (vex.length)
13659         {
13660         case 128:
13661           oappend ("QWORD PTR ");
13662           break;
13663         case 256:
13664           oappend ("YMMWORD PTR ");
13665           break;
13666         case 512:
13667           oappend ("ZMMWORD PTR ");
13668           break;
13669         default:
13670           abort ();
13671         }
13672       break;
13673     case ymmxmm_mode:
13674       if (!need_vex)
13675         abort ();
13676
13677       switch (vex.length)
13678         {
13679         case 128:
13680         case 256:
13681           oappend ("XMMWORD PTR ");
13682           break;
13683         default:
13684           abort ();
13685         }
13686       break;
13687     case o_mode:
13688       oappend ("OWORD PTR ");
13689       break;
13690     case xmm_mdq_mode:
13691     case vex_w_dq_mode:
13692     case vex_scalar_w_dq_mode:
13693       if (!need_vex)
13694         abort ();
13695
13696       if (vex.w)
13697         oappend ("QWORD PTR ");
13698       else
13699         oappend ("DWORD PTR ");
13700       break;
13701     case vex_vsib_d_w_dq_mode:
13702     case vex_vsib_q_w_dq_mode:
13703       if (!need_vex)
13704         abort ();
13705
13706       if (!vex.evex)
13707         {
13708           if (vex.w)
13709             oappend ("QWORD PTR ");
13710           else
13711             oappend ("DWORD PTR ");
13712         }
13713       else
13714         {
13715           switch (vex.length)
13716             {
13717             case 128:
13718               oappend ("XMMWORD PTR ");
13719               break;
13720             case 256:
13721               oappend ("YMMWORD PTR ");
13722               break;
13723             case 512:
13724               oappend ("ZMMWORD PTR ");
13725               break;
13726             default:
13727               abort ();
13728             }
13729         }
13730       break;
13731     case vex_vsib_q_w_d_mode:
13732     case vex_vsib_d_w_d_mode:
13733       if (!need_vex || !vex.evex)
13734         abort ();
13735
13736       switch (vex.length)
13737         {
13738         case 128:
13739           oappend ("QWORD PTR ");
13740           break;
13741         case 256:
13742           oappend ("XMMWORD PTR ");
13743           break;
13744         case 512:
13745           oappend ("YMMWORD PTR ");
13746           break;
13747         default:
13748           abort ();
13749         }
13750
13751       break;
13752     case mask_bd_mode:
13753       if (!need_vex || vex.length != 128)
13754         abort ();
13755       if (vex.w)
13756         oappend ("DWORD PTR ");
13757       else
13758         oappend ("BYTE PTR ");
13759       break;
13760     case mask_mode:
13761       if (!need_vex)
13762         abort ();
13763       if (vex.w)
13764         oappend ("QWORD PTR ");
13765       else
13766         oappend ("WORD PTR ");
13767       break;
13768     case v_bnd_mode:
13769     case v_bndmk_mode:
13770     default:
13771       break;
13772     }
13773 }
13774
13775 static void
13776 OP_E_register (int bytemode, int sizeflag)
13777 {
13778   int reg = modrm.rm;
13779   const char **names;
13780
13781   USED_REX (REX_B);
13782   if ((rex & REX_B))
13783     reg += 8;
13784
13785   if ((sizeflag & SUFFIX_ALWAYS)
13786       && (bytemode == b_swap_mode
13787           || bytemode == bnd_swap_mode
13788           || bytemode == v_swap_mode))
13789     swap_operand ();
13790
13791   switch (bytemode)
13792     {
13793     case b_mode:
13794     case b_swap_mode:
13795       USED_REX (0);
13796       if (rex)
13797         names = names8rex;
13798       else
13799         names = names8;
13800       break;
13801     case w_mode:
13802       names = names16;
13803       break;
13804     case d_mode:
13805     case dw_mode:
13806     case db_mode:
13807       names = names32;
13808       break;
13809     case q_mode:
13810       names = names64;
13811       break;
13812     case m_mode:
13813     case v_bnd_mode:
13814       names = address_mode == mode_64bit ? names64 : names32;
13815       break;
13816     case bnd_mode:
13817     case bnd_swap_mode:
13818       if (reg > 0x3)
13819         {
13820           oappend ("(bad)");
13821           return;
13822         }
13823       names = names_bnd;
13824       break;
13825     case indir_v_mode:
13826       if (address_mode == mode_64bit && isa64 == intel64)
13827         {
13828           names = names64;
13829           break;
13830         }
13831       /* Fall through.  */
13832     case stack_v_mode:
13833       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13834         {
13835           names = names64;
13836           break;
13837         }
13838       bytemode = v_mode;
13839       /* Fall through.  */
13840     case v_mode:
13841     case v_swap_mode:
13842     case dq_mode:
13843     case dqb_mode:
13844     case dqd_mode:
13845     case dqw_mode:
13846       USED_REX (REX_W);
13847       if (rex & REX_W)
13848         names = names64;
13849       else
13850         {
13851           if ((sizeflag & DFLAG)
13852               || (bytemode != v_mode
13853                   && bytemode != v_swap_mode))
13854             names = names32;
13855           else
13856             names = names16;
13857           used_prefixes |= (prefixes & PREFIX_DATA);
13858         }
13859       break;
13860     case va_mode:
13861       names = (address_mode == mode_64bit
13862                ? names64 : names32);
13863       if (!(prefixes & PREFIX_ADDR))
13864         names = (address_mode == mode_16bit
13865                      ? names16 : names);
13866       else
13867         {
13868           /* Remove "addr16/addr32".  */
13869           all_prefixes[last_addr_prefix] = 0;
13870           names = (address_mode != mode_32bit
13871                        ? names32 : names16);
13872           used_prefixes |= PREFIX_ADDR;
13873         }
13874       break;
13875     case mask_bd_mode:
13876     case mask_mode:
13877       if (reg > 0x7)
13878         {
13879           oappend ("(bad)");
13880           return;
13881         }
13882       names = names_mask;
13883       break;
13884     case 0:
13885       return;
13886     default:
13887       oappend (INTERNAL_DISASSEMBLER_ERROR);
13888       return;
13889     }
13890   oappend (names[reg]);
13891 }
13892
13893 static void
13894 OP_E_memory (int bytemode, int sizeflag)
13895 {
13896   bfd_vma disp = 0;
13897   int add = (rex & REX_B) ? 8 : 0;
13898   int riprel = 0;
13899   int shift;
13900
13901   if (vex.evex)
13902     {
13903       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13904       if (vex.b
13905           && bytemode != x_mode
13906           && bytemode != xmmq_mode
13907           && bytemode != evex_half_bcst_xmmq_mode)
13908         {
13909           BadOp ();
13910           return;
13911         }
13912       switch (bytemode)
13913         {
13914         case dqw_mode:
13915         case dw_mode:
13916           shift = 1;
13917           break;
13918         case dqb_mode:
13919         case db_mode:
13920           shift = 0;
13921           break;
13922         case dq_mode:
13923           if (address_mode != mode_64bit)
13924             {
13925               shift = 2;
13926               break;
13927             }
13928             /* fall through */
13929         case vex_vsib_d_w_dq_mode:
13930         case vex_vsib_d_w_d_mode:
13931         case vex_vsib_q_w_dq_mode:
13932         case vex_vsib_q_w_d_mode:
13933         case evex_x_gscat_mode:
13934         case xmm_mdq_mode:
13935           shift = vex.w ? 3 : 2;
13936           break;
13937         case x_mode:
13938         case evex_half_bcst_xmmq_mode:
13939         case xmmq_mode:
13940           if (vex.b)
13941             {
13942               shift = vex.w ? 3 : 2;
13943               break;
13944             }
13945           /* Fall through.  */
13946         case xmmqd_mode:
13947         case xmmdw_mode:
13948         case ymmq_mode:
13949         case evex_x_nobcst_mode:
13950         case x_swap_mode:
13951           switch (vex.length)
13952             {
13953             case 128:
13954               shift = 4;
13955               break;
13956             case 256:
13957               shift = 5;
13958               break;
13959             case 512:
13960               shift = 6;
13961               break;
13962             default:
13963               abort ();
13964             }
13965           break;
13966         case ymm_mode:
13967           shift = 5;
13968           break;
13969         case xmm_mode:
13970           shift = 4;
13971           break;
13972         case xmm_mq_mode:
13973         case q_mode:
13974         case q_scalar_mode:
13975         case q_swap_mode:
13976         case q_scalar_swap_mode:
13977           shift = 3;
13978           break;
13979         case dqd_mode:
13980         case xmm_md_mode:
13981         case d_mode:
13982         case d_scalar_mode:
13983         case d_swap_mode:
13984         case d_scalar_swap_mode:
13985           shift = 2;
13986           break;
13987         case w_scalar_mode:
13988         case xmm_mw_mode:
13989           shift = 1;
13990           break;
13991         case b_scalar_mode:
13992         case xmm_mb_mode:
13993           shift = 0;
13994           break;
13995         default:
13996           abort ();
13997         }
13998       /* Make necessary corrections to shift for modes that need it.
13999          For these modes we currently have shift 4, 5 or 6 depending on
14000          vex.length (it corresponds to xmmword, ymmword or zmmword
14001          operand).  We might want to make it 3, 4 or 5 (e.g. for
14002          xmmq_mode).  In case of broadcast enabled the corrections
14003          aren't needed, as element size is always 32 or 64 bits.  */
14004       if (!vex.b
14005           && (bytemode == xmmq_mode
14006               || bytemode == evex_half_bcst_xmmq_mode))
14007         shift -= 1;
14008       else if (bytemode == xmmqd_mode)
14009         shift -= 2;
14010       else if (bytemode == xmmdw_mode)
14011         shift -= 3;
14012       else if (bytemode == ymmq_mode && vex.length == 128)
14013         shift -= 1;
14014     }
14015   else
14016     shift = 0;
14017
14018   USED_REX (REX_B);
14019   if (intel_syntax)
14020     intel_operand_size (bytemode, sizeflag);
14021   append_seg ();
14022
14023   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14024     {
14025       /* 32/64 bit address mode */
14026       int havedisp;
14027       int havesib;
14028       int havebase;
14029       int haveindex;
14030       int needindex;
14031       int needaddr32;
14032       int base, rbase;
14033       int vindex = 0;
14034       int scale = 0;
14035       int addr32flag = !((sizeflag & AFLAG)
14036                          || bytemode == v_bnd_mode
14037                          || bytemode == v_bndmk_mode
14038                          || bytemode == bnd_mode
14039                          || bytemode == bnd_swap_mode);
14040       const char **indexes64 = names64;
14041       const char **indexes32 = names32;
14042
14043       havesib = 0;
14044       havebase = 1;
14045       haveindex = 0;
14046       base = modrm.rm;
14047
14048       if (base == 4)
14049         {
14050           havesib = 1;
14051           vindex = sib.index;
14052           USED_REX (REX_X);
14053           if (rex & REX_X)
14054             vindex += 8;
14055           switch (bytemode)
14056             {
14057             case vex_vsib_d_w_dq_mode:
14058             case vex_vsib_d_w_d_mode:
14059             case vex_vsib_q_w_dq_mode:
14060             case vex_vsib_q_w_d_mode:
14061               if (!need_vex)
14062                 abort ();
14063               if (vex.evex)
14064                 {
14065                   if (!vex.v)
14066                     vindex += 16;
14067                 }
14068
14069               haveindex = 1;
14070               switch (vex.length)
14071                 {
14072                 case 128:
14073                   indexes64 = indexes32 = names_xmm;
14074                   break;
14075                 case 256:
14076                   if (!vex.w
14077                       || bytemode == vex_vsib_q_w_dq_mode
14078                       || bytemode == vex_vsib_q_w_d_mode)
14079                     indexes64 = indexes32 = names_ymm;
14080                   else
14081                     indexes64 = indexes32 = names_xmm;
14082                   break;
14083                 case 512:
14084                   if (!vex.w
14085                       || bytemode == vex_vsib_q_w_dq_mode
14086                       || bytemode == vex_vsib_q_w_d_mode)
14087                     indexes64 = indexes32 = names_zmm;
14088                   else
14089                     indexes64 = indexes32 = names_ymm;
14090                   break;
14091                 default:
14092                   abort ();
14093                 }
14094               break;
14095             default:
14096               haveindex = vindex != 4;
14097               break;
14098             }
14099           scale = sib.scale;
14100           base = sib.base;
14101           codep++;
14102         }
14103       rbase = base + add;
14104
14105       switch (modrm.mod)
14106         {
14107         case 0:
14108           if (base == 5)
14109             {
14110               havebase = 0;
14111               if (address_mode == mode_64bit && !havesib)
14112                 riprel = 1;
14113               disp = get32s ();
14114               if (riprel && bytemode == v_bndmk_mode)
14115                 {
14116                   oappend ("(bad)");
14117                   return;
14118                 }
14119             }
14120           break;
14121         case 1:
14122           FETCH_DATA (the_info, codep + 1);
14123           disp = *codep++;
14124           if ((disp & 0x80) != 0)
14125             disp -= 0x100;
14126           if (vex.evex && shift > 0)
14127             disp <<= shift;
14128           break;
14129         case 2:
14130           disp = get32s ();
14131           break;
14132         }
14133
14134       needindex = 0;
14135       needaddr32 = 0;
14136       if (havesib
14137           && !havebase
14138           && !haveindex
14139           && address_mode != mode_16bit)
14140         {
14141           if (address_mode == mode_64bit)
14142             {
14143               /* Display eiz instead of addr32.  */
14144               needindex = addr32flag;
14145               needaddr32 = 1;
14146             }
14147           else
14148             {
14149               /* In 32-bit mode, we need index register to tell [offset]
14150                  from [eiz*1 + offset].  */
14151               needindex = 1;
14152             }
14153         }
14154
14155       havedisp = (havebase
14156                   || needindex
14157                   || (havesib && (haveindex || scale != 0)));
14158
14159       if (!intel_syntax)
14160         if (modrm.mod != 0 || base == 5)
14161           {
14162             if (havedisp || riprel)
14163               print_displacement (scratchbuf, disp);
14164             else
14165               print_operand_value (scratchbuf, 1, disp);
14166             oappend (scratchbuf);
14167             if (riprel)
14168               {
14169                 set_op (disp, 1);
14170                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14171               }
14172           }
14173
14174       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14175           && (bytemode != v_bnd_mode)
14176           && (bytemode != v_bndmk_mode)
14177           && (bytemode != bnd_mode)
14178           && (bytemode != bnd_swap_mode))
14179         used_prefixes |= PREFIX_ADDR;
14180
14181       if (havedisp || (intel_syntax && riprel))
14182         {
14183           *obufp++ = open_char;
14184           if (intel_syntax && riprel)
14185             {
14186               set_op (disp, 1);
14187               oappend (!addr32flag ? "rip" : "eip");
14188             }
14189           *obufp = '\0';
14190           if (havebase)
14191             oappend (address_mode == mode_64bit && !addr32flag
14192                      ? names64[rbase] : names32[rbase]);
14193           if (havesib)
14194             {
14195               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14196                  print index to tell base + index from base.  */
14197               if (scale != 0
14198                   || needindex
14199                   || haveindex
14200                   || (havebase && base != ESP_REG_NUM))
14201                 {
14202                   if (!intel_syntax || havebase)
14203                     {
14204                       *obufp++ = separator_char;
14205                       *obufp = '\0';
14206                     }
14207                   if (haveindex)
14208                     oappend (address_mode == mode_64bit && !addr32flag
14209                              ? indexes64[vindex] : indexes32[vindex]);
14210                   else
14211                     oappend (address_mode == mode_64bit && !addr32flag
14212                              ? index64 : index32);
14213
14214                   *obufp++ = scale_char;
14215                   *obufp = '\0';
14216                   sprintf (scratchbuf, "%d", 1 << scale);
14217                   oappend (scratchbuf);
14218                 }
14219             }
14220           if (intel_syntax
14221               && (disp || modrm.mod != 0 || base == 5))
14222             {
14223               if (!havedisp || (bfd_signed_vma) disp >= 0)
14224                 {
14225                   *obufp++ = '+';
14226                   *obufp = '\0';
14227                 }
14228               else if (modrm.mod != 1 && disp != -disp)
14229                 {
14230                   *obufp++ = '-';
14231                   *obufp = '\0';
14232                   disp = - (bfd_signed_vma) disp;
14233                 }
14234
14235               if (havedisp)
14236                 print_displacement (scratchbuf, disp);
14237               else
14238                 print_operand_value (scratchbuf, 1, disp);
14239               oappend (scratchbuf);
14240             }
14241
14242           *obufp++ = close_char;
14243           *obufp = '\0';
14244         }
14245       else if (intel_syntax)
14246         {
14247           if (modrm.mod != 0 || base == 5)
14248             {
14249               if (!active_seg_prefix)
14250                 {
14251                   oappend (names_seg[ds_reg - es_reg]);
14252                   oappend (":");
14253                 }
14254               print_operand_value (scratchbuf, 1, disp);
14255               oappend (scratchbuf);
14256             }
14257         }
14258     }
14259   else
14260     {
14261       /* 16 bit address mode */
14262       used_prefixes |= prefixes & PREFIX_ADDR;
14263       switch (modrm.mod)
14264         {
14265         case 0:
14266           if (modrm.rm == 6)
14267             {
14268               disp = get16 ();
14269               if ((disp & 0x8000) != 0)
14270                 disp -= 0x10000;
14271             }
14272           break;
14273         case 1:
14274           FETCH_DATA (the_info, codep + 1);
14275           disp = *codep++;
14276           if ((disp & 0x80) != 0)
14277             disp -= 0x100;
14278           if (vex.evex && shift > 0)
14279             disp <<= shift;
14280           break;
14281         case 2:
14282           disp = get16 ();
14283           if ((disp & 0x8000) != 0)
14284             disp -= 0x10000;
14285           break;
14286         }
14287
14288       if (!intel_syntax)
14289         if (modrm.mod != 0 || modrm.rm == 6)
14290           {
14291             print_displacement (scratchbuf, disp);
14292             oappend (scratchbuf);
14293           }
14294
14295       if (modrm.mod != 0 || modrm.rm != 6)
14296         {
14297           *obufp++ = open_char;
14298           *obufp = '\0';
14299           oappend (index16[modrm.rm]);
14300           if (intel_syntax
14301               && (disp || modrm.mod != 0 || modrm.rm == 6))
14302             {
14303               if ((bfd_signed_vma) disp >= 0)
14304                 {
14305                   *obufp++ = '+';
14306                   *obufp = '\0';
14307                 }
14308               else if (modrm.mod != 1)
14309                 {
14310                   *obufp++ = '-';
14311                   *obufp = '\0';
14312                   disp = - (bfd_signed_vma) disp;
14313                 }
14314
14315               print_displacement (scratchbuf, disp);
14316               oappend (scratchbuf);
14317             }
14318
14319           *obufp++ = close_char;
14320           *obufp = '\0';
14321         }
14322       else if (intel_syntax)
14323         {
14324           if (!active_seg_prefix)
14325             {
14326               oappend (names_seg[ds_reg - es_reg]);
14327               oappend (":");
14328             }
14329           print_operand_value (scratchbuf, 1, disp & 0xffff);
14330           oappend (scratchbuf);
14331         }
14332     }
14333   if (vex.evex && vex.b
14334       && (bytemode == x_mode
14335           || bytemode == xmmq_mode
14336           || bytemode == evex_half_bcst_xmmq_mode))
14337     {
14338       if (vex.w
14339           || bytemode == xmmq_mode
14340           || bytemode == evex_half_bcst_xmmq_mode)
14341         {
14342           switch (vex.length)
14343             {
14344             case 128:
14345               oappend ("{1to2}");
14346               break;
14347             case 256:
14348               oappend ("{1to4}");
14349               break;
14350             case 512:
14351               oappend ("{1to8}");
14352               break;
14353             default:
14354               abort ();
14355             }
14356         }
14357       else
14358         {
14359           switch (vex.length)
14360             {
14361             case 128:
14362               oappend ("{1to4}");
14363               break;
14364             case 256:
14365               oappend ("{1to8}");
14366               break;
14367             case 512:
14368               oappend ("{1to16}");
14369               break;
14370             default:
14371               abort ();
14372             }
14373         }
14374     }
14375 }
14376
14377 static void
14378 OP_E (int bytemode, int sizeflag)
14379 {
14380   /* Skip mod/rm byte.  */
14381   MODRM_CHECK;
14382   codep++;
14383
14384   if (modrm.mod == 3)
14385     OP_E_register (bytemode, sizeflag);
14386   else
14387     OP_E_memory (bytemode, sizeflag);
14388 }
14389
14390 static void
14391 OP_G (int bytemode, int sizeflag)
14392 {
14393   int add = 0;
14394   const char **names;
14395   USED_REX (REX_R);
14396   if (rex & REX_R)
14397     add += 8;
14398   switch (bytemode)
14399     {
14400     case b_mode:
14401       USED_REX (0);
14402       if (rex)
14403         oappend (names8rex[modrm.reg + add]);
14404       else
14405         oappend (names8[modrm.reg + add]);
14406       break;
14407     case w_mode:
14408       oappend (names16[modrm.reg + add]);
14409       break;
14410     case d_mode:
14411     case db_mode:
14412     case dw_mode:
14413       oappend (names32[modrm.reg + add]);
14414       break;
14415     case q_mode:
14416       oappend (names64[modrm.reg + add]);
14417       break;
14418     case bnd_mode:
14419       if (modrm.reg > 0x3)
14420         {
14421           oappend ("(bad)");
14422           return;
14423         }
14424       oappend (names_bnd[modrm.reg]);
14425       break;
14426     case v_mode:
14427     case dq_mode:
14428     case dqb_mode:
14429     case dqd_mode:
14430     case dqw_mode:
14431       USED_REX (REX_W);
14432       if (rex & REX_W)
14433         oappend (names64[modrm.reg + add]);
14434       else
14435         {
14436           if ((sizeflag & DFLAG) || bytemode != v_mode)
14437             oappend (names32[modrm.reg + add]);
14438           else
14439             oappend (names16[modrm.reg + add]);
14440           used_prefixes |= (prefixes & PREFIX_DATA);
14441         }
14442       break;
14443     case va_mode:
14444       names = (address_mode == mode_64bit
14445                ? names64 : names32);
14446       if (!(prefixes & PREFIX_ADDR))
14447         {
14448           if (address_mode == mode_16bit)
14449             names = names16;
14450         }
14451       else
14452         {
14453           /* Remove "addr16/addr32".  */
14454           all_prefixes[last_addr_prefix] = 0;
14455           names = (address_mode != mode_32bit
14456                        ? names32 : names16);
14457           used_prefixes |= PREFIX_ADDR;
14458         }
14459       oappend (names[modrm.reg + add]);
14460       break;
14461     case m_mode:
14462       if (address_mode == mode_64bit)
14463         oappend (names64[modrm.reg + add]);
14464       else
14465         oappend (names32[modrm.reg + add]);
14466       break;
14467     case mask_bd_mode:
14468     case mask_mode:
14469       if ((modrm.reg + add) > 0x7)
14470         {
14471           oappend ("(bad)");
14472           return;
14473         }
14474       oappend (names_mask[modrm.reg + add]);
14475       break;
14476     default:
14477       oappend (INTERNAL_DISASSEMBLER_ERROR);
14478       break;
14479     }
14480 }
14481
14482 static bfd_vma
14483 get64 (void)
14484 {
14485   bfd_vma x;
14486 #ifdef BFD64
14487   unsigned int a;
14488   unsigned int b;
14489
14490   FETCH_DATA (the_info, codep + 8);
14491   a = *codep++ & 0xff;
14492   a |= (*codep++ & 0xff) << 8;
14493   a |= (*codep++ & 0xff) << 16;
14494   a |= (*codep++ & 0xffu) << 24;
14495   b = *codep++ & 0xff;
14496   b |= (*codep++ & 0xff) << 8;
14497   b |= (*codep++ & 0xff) << 16;
14498   b |= (*codep++ & 0xffu) << 24;
14499   x = a + ((bfd_vma) b << 32);
14500 #else
14501   abort ();
14502   x = 0;
14503 #endif
14504   return x;
14505 }
14506
14507 static bfd_signed_vma
14508 get32 (void)
14509 {
14510   bfd_signed_vma x = 0;
14511
14512   FETCH_DATA (the_info, codep + 4);
14513   x = *codep++ & (bfd_signed_vma) 0xff;
14514   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14515   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14516   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14517   return x;
14518 }
14519
14520 static bfd_signed_vma
14521 get32s (void)
14522 {
14523   bfd_signed_vma x = 0;
14524
14525   FETCH_DATA (the_info, codep + 4);
14526   x = *codep++ & (bfd_signed_vma) 0xff;
14527   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14528   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14529   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14530
14531   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14532
14533   return x;
14534 }
14535
14536 static int
14537 get16 (void)
14538 {
14539   int x = 0;
14540
14541   FETCH_DATA (the_info, codep + 2);
14542   x = *codep++ & 0xff;
14543   x |= (*codep++ & 0xff) << 8;
14544   return x;
14545 }
14546
14547 static void
14548 set_op (bfd_vma op, int riprel)
14549 {
14550   op_index[op_ad] = op_ad;
14551   if (address_mode == mode_64bit)
14552     {
14553       op_address[op_ad] = op;
14554       op_riprel[op_ad] = riprel;
14555     }
14556   else
14557     {
14558       /* Mask to get a 32-bit address.  */
14559       op_address[op_ad] = op & 0xffffffff;
14560       op_riprel[op_ad] = riprel & 0xffffffff;
14561     }
14562 }
14563
14564 static void
14565 OP_REG (int code, int sizeflag)
14566 {
14567   const char *s;
14568   int add;
14569
14570   switch (code)
14571     {
14572     case es_reg: case ss_reg: case cs_reg:
14573     case ds_reg: case fs_reg: case gs_reg:
14574       oappend (names_seg[code - es_reg]);
14575       return;
14576     }
14577
14578   USED_REX (REX_B);
14579   if (rex & REX_B)
14580     add = 8;
14581   else
14582     add = 0;
14583
14584   switch (code)
14585     {
14586     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14587     case sp_reg: case bp_reg: case si_reg: case di_reg:
14588       s = names16[code - ax_reg + add];
14589       break;
14590     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14591     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14592       USED_REX (0);
14593       if (rex)
14594         s = names8rex[code - al_reg + add];
14595       else
14596         s = names8[code - al_reg];
14597       break;
14598     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14599     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14600       if (address_mode == mode_64bit
14601           && ((sizeflag & DFLAG) || (rex & REX_W)))
14602         {
14603           s = names64[code - rAX_reg + add];
14604           break;
14605         }
14606       code += eAX_reg - rAX_reg;
14607       /* Fall through.  */
14608     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14609     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14610       USED_REX (REX_W);
14611       if (rex & REX_W)
14612         s = names64[code - eAX_reg + add];
14613       else
14614         {
14615           if (sizeflag & DFLAG)
14616             s = names32[code - eAX_reg + add];
14617           else
14618             s = names16[code - eAX_reg + add];
14619           used_prefixes |= (prefixes & PREFIX_DATA);
14620         }
14621       break;
14622     default:
14623       s = INTERNAL_DISASSEMBLER_ERROR;
14624       break;
14625     }
14626   oappend (s);
14627 }
14628
14629 static void
14630 OP_IMREG (int code, int sizeflag)
14631 {
14632   const char *s;
14633
14634   switch (code)
14635     {
14636     case indir_dx_reg:
14637       if (intel_syntax)
14638         s = "dx";
14639       else
14640         s = "(%dx)";
14641       break;
14642     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14643     case sp_reg: case bp_reg: case si_reg: case di_reg:
14644       s = names16[code - ax_reg];
14645       break;
14646     case es_reg: case ss_reg: case cs_reg:
14647     case ds_reg: case fs_reg: case gs_reg:
14648       s = names_seg[code - es_reg];
14649       break;
14650     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14651     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14652       USED_REX (0);
14653       if (rex)
14654         s = names8rex[code - al_reg];
14655       else
14656         s = names8[code - al_reg];
14657       break;
14658     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14659     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14660       USED_REX (REX_W);
14661       if (rex & REX_W)
14662         s = names64[code - eAX_reg];
14663       else
14664         {
14665           if (sizeflag & DFLAG)
14666             s = names32[code - eAX_reg];
14667           else
14668             s = names16[code - eAX_reg];
14669           used_prefixes |= (prefixes & PREFIX_DATA);
14670         }
14671       break;
14672     case z_mode_ax_reg:
14673       if ((rex & REX_W) || (sizeflag & DFLAG))
14674         s = *names32;
14675       else
14676         s = *names16;
14677       if (!(rex & REX_W))
14678         used_prefixes |= (prefixes & PREFIX_DATA);
14679       break;
14680     default:
14681       s = INTERNAL_DISASSEMBLER_ERROR;
14682       break;
14683     }
14684   oappend (s);
14685 }
14686
14687 static void
14688 OP_I (int bytemode, int sizeflag)
14689 {
14690   bfd_signed_vma op;
14691   bfd_signed_vma mask = -1;
14692
14693   switch (bytemode)
14694     {
14695     case b_mode:
14696       FETCH_DATA (the_info, codep + 1);
14697       op = *codep++;
14698       mask = 0xff;
14699       break;
14700     case v_mode:
14701       USED_REX (REX_W);
14702       if (rex & REX_W)
14703         op = get32s ();
14704       else
14705         {
14706           if (sizeflag & DFLAG)
14707             {
14708               op = get32 ();
14709               mask = 0xffffffff;
14710             }
14711           else
14712             {
14713               op = get16 ();
14714               mask = 0xfffff;
14715             }
14716           used_prefixes |= (prefixes & PREFIX_DATA);
14717         }
14718       break;
14719     case d_mode:
14720       mask = 0xffffffff;
14721       op = get32 ();
14722       break;
14723     case w_mode:
14724       mask = 0xfffff;
14725       op = get16 ();
14726       break;
14727     case const_1_mode:
14728       if (intel_syntax)
14729         oappend ("1");
14730       return;
14731     default:
14732       oappend (INTERNAL_DISASSEMBLER_ERROR);
14733       return;
14734     }
14735
14736   op &= mask;
14737   scratchbuf[0] = '$';
14738   print_operand_value (scratchbuf + 1, 1, op);
14739   oappend_maybe_intel (scratchbuf);
14740   scratchbuf[0] = '\0';
14741 }
14742
14743 static void
14744 OP_I64 (int bytemode, int sizeflag)
14745 {
14746   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14747     {
14748       OP_I (bytemode, sizeflag);
14749       return;
14750     }
14751
14752   USED_REX (REX_W);
14753
14754   scratchbuf[0] = '$';
14755   print_operand_value (scratchbuf + 1, 1, get64 ());
14756   oappend_maybe_intel (scratchbuf);
14757   scratchbuf[0] = '\0';
14758 }
14759
14760 static void
14761 OP_sI (int bytemode, int sizeflag)
14762 {
14763   bfd_signed_vma op;
14764
14765   switch (bytemode)
14766     {
14767     case b_mode:
14768     case b_T_mode:
14769       FETCH_DATA (the_info, codep + 1);
14770       op = *codep++;
14771       if ((op & 0x80) != 0)
14772         op -= 0x100;
14773       if (bytemode == b_T_mode)
14774         {
14775           if (address_mode != mode_64bit
14776               || !((sizeflag & DFLAG) || (rex & REX_W)))
14777             {
14778               /* The operand-size prefix is overridden by a REX prefix.  */
14779               if ((sizeflag & DFLAG) || (rex & REX_W))
14780                 op &= 0xffffffff;
14781               else
14782                 op &= 0xffff;
14783           }
14784         }
14785       else
14786         {
14787           if (!(rex & REX_W))
14788             {
14789               if (sizeflag & DFLAG)
14790                 op &= 0xffffffff;
14791               else
14792                 op &= 0xffff;
14793             }
14794         }
14795       break;
14796     case v_mode:
14797       /* The operand-size prefix is overridden by a REX prefix.  */
14798       if ((sizeflag & DFLAG) || (rex & REX_W))
14799         op = get32s ();
14800       else
14801         op = get16 ();
14802       break;
14803     default:
14804       oappend (INTERNAL_DISASSEMBLER_ERROR);
14805       return;
14806     }
14807
14808   scratchbuf[0] = '$';
14809   print_operand_value (scratchbuf + 1, 1, op);
14810   oappend_maybe_intel (scratchbuf);
14811 }
14812
14813 static void
14814 OP_J (int bytemode, int sizeflag)
14815 {
14816   bfd_vma disp;
14817   bfd_vma mask = -1;
14818   bfd_vma segment = 0;
14819
14820   switch (bytemode)
14821     {
14822     case b_mode:
14823       FETCH_DATA (the_info, codep + 1);
14824       disp = *codep++;
14825       if ((disp & 0x80) != 0)
14826         disp -= 0x100;
14827       break;
14828     case v_mode:
14829       if (isa64 == amd64)
14830         USED_REX (REX_W);
14831       if ((sizeflag & DFLAG)
14832           || (address_mode == mode_64bit
14833               && (isa64 != amd64 || (rex & REX_W))))
14834         disp = get32s ();
14835       else
14836         {
14837           disp = get16 ();
14838           if ((disp & 0x8000) != 0)
14839             disp -= 0x10000;
14840           /* In 16bit mode, address is wrapped around at 64k within
14841              the same segment.  Otherwise, a data16 prefix on a jump
14842              instruction means that the pc is masked to 16 bits after
14843              the displacement is added!  */
14844           mask = 0xffff;
14845           if ((prefixes & PREFIX_DATA) == 0)
14846             segment = ((start_pc + (codep - start_codep))
14847                        & ~((bfd_vma) 0xffff));
14848         }
14849       if (address_mode != mode_64bit
14850           || (isa64 == amd64 && !(rex & REX_W)))
14851         used_prefixes |= (prefixes & PREFIX_DATA);
14852       break;
14853     default:
14854       oappend (INTERNAL_DISASSEMBLER_ERROR);
14855       return;
14856     }
14857   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14858   set_op (disp, 0);
14859   print_operand_value (scratchbuf, 1, disp);
14860   oappend (scratchbuf);
14861 }
14862
14863 static void
14864 OP_SEG (int bytemode, int sizeflag)
14865 {
14866   if (bytemode == w_mode)
14867     oappend (names_seg[modrm.reg]);
14868   else
14869     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14870 }
14871
14872 static void
14873 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14874 {
14875   int seg, offset;
14876
14877   if (sizeflag & DFLAG)
14878     {
14879       offset = get32 ();
14880       seg = get16 ();
14881     }
14882   else
14883     {
14884       offset = get16 ();
14885       seg = get16 ();
14886     }
14887   used_prefixes |= (prefixes & PREFIX_DATA);
14888   if (intel_syntax)
14889     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14890   else
14891     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14892   oappend (scratchbuf);
14893 }
14894
14895 static void
14896 OP_OFF (int bytemode, int sizeflag)
14897 {
14898   bfd_vma off;
14899
14900   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14901     intel_operand_size (bytemode, sizeflag);
14902   append_seg ();
14903
14904   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14905     off = get32 ();
14906   else
14907     off = get16 ();
14908
14909   if (intel_syntax)
14910     {
14911       if (!active_seg_prefix)
14912         {
14913           oappend (names_seg[ds_reg - es_reg]);
14914           oappend (":");
14915         }
14916     }
14917   print_operand_value (scratchbuf, 1, off);
14918   oappend (scratchbuf);
14919 }
14920
14921 static void
14922 OP_OFF64 (int bytemode, int sizeflag)
14923 {
14924   bfd_vma off;
14925
14926   if (address_mode != mode_64bit
14927       || (prefixes & PREFIX_ADDR))
14928     {
14929       OP_OFF (bytemode, sizeflag);
14930       return;
14931     }
14932
14933   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14934     intel_operand_size (bytemode, sizeflag);
14935   append_seg ();
14936
14937   off = get64 ();
14938
14939   if (intel_syntax)
14940     {
14941       if (!active_seg_prefix)
14942         {
14943           oappend (names_seg[ds_reg - es_reg]);
14944           oappend (":");
14945         }
14946     }
14947   print_operand_value (scratchbuf, 1, off);
14948   oappend (scratchbuf);
14949 }
14950
14951 static void
14952 ptr_reg (int code, int sizeflag)
14953 {
14954   const char *s;
14955
14956   *obufp++ = open_char;
14957   used_prefixes |= (prefixes & PREFIX_ADDR);
14958   if (address_mode == mode_64bit)
14959     {
14960       if (!(sizeflag & AFLAG))
14961         s = names32[code - eAX_reg];
14962       else
14963         s = names64[code - eAX_reg];
14964     }
14965   else if (sizeflag & AFLAG)
14966     s = names32[code - eAX_reg];
14967   else
14968     s = names16[code - eAX_reg];
14969   oappend (s);
14970   *obufp++ = close_char;
14971   *obufp = 0;
14972 }
14973
14974 static void
14975 OP_ESreg (int code, int sizeflag)
14976 {
14977   if (intel_syntax)
14978     {
14979       switch (codep[-1])
14980         {
14981         case 0x6d:      /* insw/insl */
14982           intel_operand_size (z_mode, sizeflag);
14983           break;
14984         case 0xa5:      /* movsw/movsl/movsq */
14985         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14986         case 0xab:      /* stosw/stosl */
14987         case 0xaf:      /* scasw/scasl */
14988           intel_operand_size (v_mode, sizeflag);
14989           break;
14990         default:
14991           intel_operand_size (b_mode, sizeflag);
14992         }
14993     }
14994   oappend_maybe_intel ("%es:");
14995   ptr_reg (code, sizeflag);
14996 }
14997
14998 static void
14999 OP_DSreg (int code, int sizeflag)
15000 {
15001   if (intel_syntax)
15002     {
15003       switch (codep[-1])
15004         {
15005         case 0x6f:      /* outsw/outsl */
15006           intel_operand_size (z_mode, sizeflag);
15007           break;
15008         case 0xa5:      /* movsw/movsl/movsq */
15009         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15010         case 0xad:      /* lodsw/lodsl/lodsq */
15011           intel_operand_size (v_mode, sizeflag);
15012           break;
15013         default:
15014           intel_operand_size (b_mode, sizeflag);
15015         }
15016     }
15017   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15018      default segment register DS is printed.  */
15019   if (!active_seg_prefix)
15020     active_seg_prefix = PREFIX_DS;
15021   append_seg ();
15022   ptr_reg (code, sizeflag);
15023 }
15024
15025 static void
15026 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15027 {
15028   int add;
15029   if (rex & REX_R)
15030     {
15031       USED_REX (REX_R);
15032       add = 8;
15033     }
15034   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15035     {
15036       all_prefixes[last_lock_prefix] = 0;
15037       used_prefixes |= PREFIX_LOCK;
15038       add = 8;
15039     }
15040   else
15041     add = 0;
15042   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15043   oappend_maybe_intel (scratchbuf);
15044 }
15045
15046 static void
15047 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15048 {
15049   int add;
15050   USED_REX (REX_R);
15051   if (rex & REX_R)
15052     add = 8;
15053   else
15054     add = 0;
15055   if (intel_syntax)
15056     sprintf (scratchbuf, "db%d", modrm.reg + add);
15057   else
15058     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15059   oappend (scratchbuf);
15060 }
15061
15062 static void
15063 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15064 {
15065   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15066   oappend_maybe_intel (scratchbuf);
15067 }
15068
15069 static void
15070 OP_R (int bytemode, int sizeflag)
15071 {
15072   /* Skip mod/rm byte.  */
15073   MODRM_CHECK;
15074   codep++;
15075   OP_E_register (bytemode, sizeflag);
15076 }
15077
15078 static void
15079 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15080 {
15081   int reg = modrm.reg;
15082   const char **names;
15083
15084   used_prefixes |= (prefixes & PREFIX_DATA);
15085   if (prefixes & PREFIX_DATA)
15086     {
15087       names = names_xmm;
15088       USED_REX (REX_R);
15089       if (rex & REX_R)
15090         reg += 8;
15091     }
15092   else
15093     names = names_mm;
15094   oappend (names[reg]);
15095 }
15096
15097 static void
15098 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15099 {
15100   int reg = modrm.reg;
15101   const char **names;
15102
15103   USED_REX (REX_R);
15104   if (rex & REX_R)
15105     reg += 8;
15106   if (vex.evex)
15107     {
15108       if (!vex.r)
15109         reg += 16;
15110     }
15111
15112   if (need_vex
15113       && bytemode != xmm_mode
15114       && bytemode != xmmq_mode
15115       && bytemode != evex_half_bcst_xmmq_mode
15116       && bytemode != ymm_mode
15117       && bytemode != scalar_mode)
15118     {
15119       switch (vex.length)
15120         {
15121         case 128:
15122           names = names_xmm;
15123           break;
15124         case 256:
15125           if (vex.w
15126               || (bytemode != vex_vsib_q_w_dq_mode
15127                   && bytemode != vex_vsib_q_w_d_mode))
15128             names = names_ymm;
15129           else
15130             names = names_xmm;
15131           break;
15132         case 512:
15133           names = names_zmm;
15134           break;
15135         default:
15136           abort ();
15137         }
15138     }
15139   else if (bytemode == xmmq_mode
15140            || bytemode == evex_half_bcst_xmmq_mode)
15141     {
15142       switch (vex.length)
15143         {
15144         case 128:
15145         case 256:
15146           names = names_xmm;
15147           break;
15148         case 512:
15149           names = names_ymm;
15150           break;
15151         default:
15152           abort ();
15153         }
15154     }
15155   else if (bytemode == ymm_mode)
15156     names = names_ymm;
15157   else
15158     names = names_xmm;
15159   oappend (names[reg]);
15160 }
15161
15162 static void
15163 OP_EM (int bytemode, int sizeflag)
15164 {
15165   int reg;
15166   const char **names;
15167
15168   if (modrm.mod != 3)
15169     {
15170       if (intel_syntax
15171           && (bytemode == v_mode || bytemode == v_swap_mode))
15172         {
15173           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15174           used_prefixes |= (prefixes & PREFIX_DATA);
15175         }
15176       OP_E (bytemode, sizeflag);
15177       return;
15178     }
15179
15180   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15181     swap_operand ();
15182
15183   /* Skip mod/rm byte.  */
15184   MODRM_CHECK;
15185   codep++;
15186   used_prefixes |= (prefixes & PREFIX_DATA);
15187   reg = modrm.rm;
15188   if (prefixes & PREFIX_DATA)
15189     {
15190       names = names_xmm;
15191       USED_REX (REX_B);
15192       if (rex & REX_B)
15193         reg += 8;
15194     }
15195   else
15196     names = names_mm;
15197   oappend (names[reg]);
15198 }
15199
15200 /* cvt* are the only instructions in sse2 which have
15201    both SSE and MMX operands and also have 0x66 prefix
15202    in their opcode. 0x66 was originally used to differentiate
15203    between SSE and MMX instruction(operands). So we have to handle the
15204    cvt* separately using OP_EMC and OP_MXC */
15205 static void
15206 OP_EMC (int bytemode, int sizeflag)
15207 {
15208   if (modrm.mod != 3)
15209     {
15210       if (intel_syntax && bytemode == v_mode)
15211         {
15212           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15213           used_prefixes |= (prefixes & PREFIX_DATA);
15214         }
15215       OP_E (bytemode, sizeflag);
15216       return;
15217     }
15218
15219   /* Skip mod/rm byte.  */
15220   MODRM_CHECK;
15221   codep++;
15222   used_prefixes |= (prefixes & PREFIX_DATA);
15223   oappend (names_mm[modrm.rm]);
15224 }
15225
15226 static void
15227 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15228 {
15229   used_prefixes |= (prefixes & PREFIX_DATA);
15230   oappend (names_mm[modrm.reg]);
15231 }
15232
15233 static void
15234 OP_EX (int bytemode, int sizeflag)
15235 {
15236   int reg;
15237   const char **names;
15238
15239   /* Skip mod/rm byte.  */
15240   MODRM_CHECK;
15241   codep++;
15242
15243   if (modrm.mod != 3)
15244     {
15245       OP_E_memory (bytemode, sizeflag);
15246       return;
15247     }
15248
15249   reg = modrm.rm;
15250   USED_REX (REX_B);
15251   if (rex & REX_B)
15252     reg += 8;
15253   if (vex.evex)
15254     {
15255       USED_REX (REX_X);
15256       if ((rex & REX_X))
15257         reg += 16;
15258     }
15259
15260   if ((sizeflag & SUFFIX_ALWAYS)
15261       && (bytemode == x_swap_mode
15262           || bytemode == d_swap_mode
15263           || bytemode == d_scalar_swap_mode
15264           || bytemode == q_swap_mode
15265           || bytemode == q_scalar_swap_mode))
15266     swap_operand ();
15267
15268   if (need_vex
15269       && bytemode != xmm_mode
15270       && bytemode != xmmdw_mode
15271       && bytemode != xmmqd_mode
15272       && bytemode != xmm_mb_mode
15273       && bytemode != xmm_mw_mode
15274       && bytemode != xmm_md_mode
15275       && bytemode != xmm_mq_mode
15276       && bytemode != xmm_mdq_mode
15277       && bytemode != xmmq_mode
15278       && bytemode != evex_half_bcst_xmmq_mode
15279       && bytemode != ymm_mode
15280       && bytemode != d_scalar_mode
15281       && bytemode != d_scalar_swap_mode
15282       && bytemode != q_scalar_mode
15283       && bytemode != q_scalar_swap_mode
15284       && bytemode != vex_scalar_w_dq_mode)
15285     {
15286       switch (vex.length)
15287         {
15288         case 128:
15289           names = names_xmm;
15290           break;
15291         case 256:
15292           names = names_ymm;
15293           break;
15294         case 512:
15295           names = names_zmm;
15296           break;
15297         default:
15298           abort ();
15299         }
15300     }
15301   else if (bytemode == xmmq_mode
15302            || bytemode == evex_half_bcst_xmmq_mode)
15303     {
15304       switch (vex.length)
15305         {
15306         case 128:
15307         case 256:
15308           names = names_xmm;
15309           break;
15310         case 512:
15311           names = names_ymm;
15312           break;
15313         default:
15314           abort ();
15315         }
15316     }
15317   else if (bytemode == ymm_mode)
15318     names = names_ymm;
15319   else
15320     names = names_xmm;
15321   oappend (names[reg]);
15322 }
15323
15324 static void
15325 OP_MS (int bytemode, int sizeflag)
15326 {
15327   if (modrm.mod == 3)
15328     OP_EM (bytemode, sizeflag);
15329   else
15330     BadOp ();
15331 }
15332
15333 static void
15334 OP_XS (int bytemode, int sizeflag)
15335 {
15336   if (modrm.mod == 3)
15337     OP_EX (bytemode, sizeflag);
15338   else
15339     BadOp ();
15340 }
15341
15342 static void
15343 OP_M (int bytemode, int sizeflag)
15344 {
15345   if (modrm.mod == 3)
15346     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15347     BadOp ();
15348   else
15349     OP_E (bytemode, sizeflag);
15350 }
15351
15352 static void
15353 OP_0f07 (int bytemode, int sizeflag)
15354 {
15355   if (modrm.mod != 3 || modrm.rm != 0)
15356     BadOp ();
15357   else
15358     OP_E (bytemode, sizeflag);
15359 }
15360
15361 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15362    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15363
15364 static void
15365 NOP_Fixup1 (int bytemode, int sizeflag)
15366 {
15367   if ((prefixes & PREFIX_DATA) != 0
15368       || (rex != 0
15369           && rex != 0x48
15370           && address_mode == mode_64bit))
15371     OP_REG (bytemode, sizeflag);
15372   else
15373     strcpy (obuf, "nop");
15374 }
15375
15376 static void
15377 NOP_Fixup2 (int bytemode, int sizeflag)
15378 {
15379   if ((prefixes & PREFIX_DATA) != 0
15380       || (rex != 0
15381           && rex != 0x48
15382           && address_mode == mode_64bit))
15383     OP_IMREG (bytemode, sizeflag);
15384 }
15385
15386 static const char *const Suffix3DNow[] = {
15387 /* 00 */        NULL,           NULL,           NULL,           NULL,
15388 /* 04 */        NULL,           NULL,           NULL,           NULL,
15389 /* 08 */        NULL,           NULL,           NULL,           NULL,
15390 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15391 /* 10 */        NULL,           NULL,           NULL,           NULL,
15392 /* 14 */        NULL,           NULL,           NULL,           NULL,
15393 /* 18 */        NULL,           NULL,           NULL,           NULL,
15394 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15395 /* 20 */        NULL,           NULL,           NULL,           NULL,
15396 /* 24 */        NULL,           NULL,           NULL,           NULL,
15397 /* 28 */        NULL,           NULL,           NULL,           NULL,
15398 /* 2C */        NULL,           NULL,           NULL,           NULL,
15399 /* 30 */        NULL,           NULL,           NULL,           NULL,
15400 /* 34 */        NULL,           NULL,           NULL,           NULL,
15401 /* 38 */        NULL,           NULL,           NULL,           NULL,
15402 /* 3C */        NULL,           NULL,           NULL,           NULL,
15403 /* 40 */        NULL,           NULL,           NULL,           NULL,
15404 /* 44 */        NULL,           NULL,           NULL,           NULL,
15405 /* 48 */        NULL,           NULL,           NULL,           NULL,
15406 /* 4C */        NULL,           NULL,           NULL,           NULL,
15407 /* 50 */        NULL,           NULL,           NULL,           NULL,
15408 /* 54 */        NULL,           NULL,           NULL,           NULL,
15409 /* 58 */        NULL,           NULL,           NULL,           NULL,
15410 /* 5C */        NULL,           NULL,           NULL,           NULL,
15411 /* 60 */        NULL,           NULL,           NULL,           NULL,
15412 /* 64 */        NULL,           NULL,           NULL,           NULL,
15413 /* 68 */        NULL,           NULL,           NULL,           NULL,
15414 /* 6C */        NULL,           NULL,           NULL,           NULL,
15415 /* 70 */        NULL,           NULL,           NULL,           NULL,
15416 /* 74 */        NULL,           NULL,           NULL,           NULL,
15417 /* 78 */        NULL,           NULL,           NULL,           NULL,
15418 /* 7C */        NULL,           NULL,           NULL,           NULL,
15419 /* 80 */        NULL,           NULL,           NULL,           NULL,
15420 /* 84 */        NULL,           NULL,           NULL,           NULL,
15421 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15422 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15423 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15424 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15425 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15426 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15427 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15428 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15429 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15430 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15431 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15432 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15433 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15434 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15435 /* C0 */        NULL,           NULL,           NULL,           NULL,
15436 /* C4 */        NULL,           NULL,           NULL,           NULL,
15437 /* C8 */        NULL,           NULL,           NULL,           NULL,
15438 /* CC */        NULL,           NULL,           NULL,           NULL,
15439 /* D0 */        NULL,           NULL,           NULL,           NULL,
15440 /* D4 */        NULL,           NULL,           NULL,           NULL,
15441 /* D8 */        NULL,           NULL,           NULL,           NULL,
15442 /* DC */        NULL,           NULL,           NULL,           NULL,
15443 /* E0 */        NULL,           NULL,           NULL,           NULL,
15444 /* E4 */        NULL,           NULL,           NULL,           NULL,
15445 /* E8 */        NULL,           NULL,           NULL,           NULL,
15446 /* EC */        NULL,           NULL,           NULL,           NULL,
15447 /* F0 */        NULL,           NULL,           NULL,           NULL,
15448 /* F4 */        NULL,           NULL,           NULL,           NULL,
15449 /* F8 */        NULL,           NULL,           NULL,           NULL,
15450 /* FC */        NULL,           NULL,           NULL,           NULL,
15451 };
15452
15453 static void
15454 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15455 {
15456   const char *mnemonic;
15457
15458   FETCH_DATA (the_info, codep + 1);
15459   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15460      place where an 8-bit immediate would normally go.  ie. the last
15461      byte of the instruction.  */
15462   obufp = mnemonicendp;
15463   mnemonic = Suffix3DNow[*codep++ & 0xff];
15464   if (mnemonic)
15465     oappend (mnemonic);
15466   else
15467     {
15468       /* Since a variable sized modrm/sib chunk is between the start
15469          of the opcode (0x0f0f) and the opcode suffix, we need to do
15470          all the modrm processing first, and don't know until now that
15471          we have a bad opcode.  This necessitates some cleaning up.  */
15472       op_out[0][0] = '\0';
15473       op_out[1][0] = '\0';
15474       BadOp ();
15475     }
15476   mnemonicendp = obufp;
15477 }
15478
15479 static struct op simd_cmp_op[] =
15480 {
15481   { STRING_COMMA_LEN ("eq") },
15482   { STRING_COMMA_LEN ("lt") },
15483   { STRING_COMMA_LEN ("le") },
15484   { STRING_COMMA_LEN ("unord") },
15485   { STRING_COMMA_LEN ("neq") },
15486   { STRING_COMMA_LEN ("nlt") },
15487   { STRING_COMMA_LEN ("nle") },
15488   { STRING_COMMA_LEN ("ord") }
15489 };
15490
15491 static void
15492 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15493 {
15494   unsigned int cmp_type;
15495
15496   FETCH_DATA (the_info, codep + 1);
15497   cmp_type = *codep++ & 0xff;
15498   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15499     {
15500       char suffix [3];
15501       char *p = mnemonicendp - 2;
15502       suffix[0] = p[0];
15503       suffix[1] = p[1];
15504       suffix[2] = '\0';
15505       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15506       mnemonicendp += simd_cmp_op[cmp_type].len;
15507     }
15508   else
15509     {
15510       /* We have a reserved extension byte.  Output it directly.  */
15511       scratchbuf[0] = '$';
15512       print_operand_value (scratchbuf + 1, 1, cmp_type);
15513       oappend_maybe_intel (scratchbuf);
15514       scratchbuf[0] = '\0';
15515     }
15516 }
15517
15518 static void
15519 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15520           int sizeflag ATTRIBUTE_UNUSED)
15521 {
15522   /* mwaitx %eax,%ecx,%ebx */
15523   if (!intel_syntax)
15524     {
15525       const char **names = (address_mode == mode_64bit
15526                             ? names64 : names32);
15527       strcpy (op_out[0], names[0]);
15528       strcpy (op_out[1], names[1]);
15529       strcpy (op_out[2], names[3]);
15530       two_source_ops = 1;
15531     }
15532   /* Skip mod/rm byte.  */
15533   MODRM_CHECK;
15534   codep++;
15535 }
15536
15537 static void
15538 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15539           int sizeflag ATTRIBUTE_UNUSED)
15540 {
15541   /* mwait %eax,%ecx  */
15542   if (!intel_syntax)
15543     {
15544       const char **names = (address_mode == mode_64bit
15545                             ? names64 : names32);
15546       strcpy (op_out[0], names[0]);
15547       strcpy (op_out[1], names[1]);
15548       two_source_ops = 1;
15549     }
15550   /* Skip mod/rm byte.  */
15551   MODRM_CHECK;
15552   codep++;
15553 }
15554
15555 static void
15556 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15557             int sizeflag ATTRIBUTE_UNUSED)
15558 {
15559   /* monitor %eax,%ecx,%edx"  */
15560   if (!intel_syntax)
15561     {
15562       const char **op1_names;
15563       const char **names = (address_mode == mode_64bit
15564                             ? names64 : names32);
15565
15566       if (!(prefixes & PREFIX_ADDR))
15567         op1_names = (address_mode == mode_16bit
15568                      ? names16 : names);
15569       else
15570         {
15571           /* Remove "addr16/addr32".  */
15572           all_prefixes[last_addr_prefix] = 0;
15573           op1_names = (address_mode != mode_32bit
15574                        ? names32 : names16);
15575           used_prefixes |= PREFIX_ADDR;
15576         }
15577       strcpy (op_out[0], op1_names[0]);
15578       strcpy (op_out[1], names[1]);
15579       strcpy (op_out[2], names[2]);
15580       two_source_ops = 1;
15581     }
15582   /* Skip mod/rm byte.  */
15583   MODRM_CHECK;
15584   codep++;
15585 }
15586
15587 static void
15588 BadOp (void)
15589 {
15590   /* Throw away prefixes and 1st. opcode byte.  */
15591   codep = insn_codep + 1;
15592   oappend ("(bad)");
15593 }
15594
15595 static void
15596 REP_Fixup (int bytemode, int sizeflag)
15597 {
15598   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15599      lods and stos.  */
15600   if (prefixes & PREFIX_REPZ)
15601     all_prefixes[last_repz_prefix] = REP_PREFIX;
15602
15603   switch (bytemode)
15604     {
15605     case al_reg:
15606     case eAX_reg:
15607     case indir_dx_reg:
15608       OP_IMREG (bytemode, sizeflag);
15609       break;
15610     case eDI_reg:
15611       OP_ESreg (bytemode, sizeflag);
15612       break;
15613     case eSI_reg:
15614       OP_DSreg (bytemode, sizeflag);
15615       break;
15616     default:
15617       abort ();
15618       break;
15619     }
15620 }
15621
15622 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15623    "bnd".  */
15624
15625 static void
15626 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15627 {
15628   if (prefixes & PREFIX_REPNZ)
15629     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15630 }
15631
15632 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15633    "notrack".  */
15634
15635 static void
15636 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15637                int sizeflag ATTRIBUTE_UNUSED)
15638 {
15639   if (active_seg_prefix == PREFIX_DS
15640       && (address_mode != mode_64bit || last_data_prefix < 0))
15641     {
15642       /* NOTRACK prefix is only valid on indirect branch instructions.
15643          NB: DATA prefix is unsupported for Intel64.  */
15644       active_seg_prefix = 0;
15645       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15646     }
15647 }
15648
15649 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15650    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15651  */
15652
15653 static void
15654 HLE_Fixup1 (int bytemode, int sizeflag)
15655 {
15656   if (modrm.mod != 3
15657       && (prefixes & PREFIX_LOCK) != 0)
15658     {
15659       if (prefixes & PREFIX_REPZ)
15660         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15661       if (prefixes & PREFIX_REPNZ)
15662         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15663     }
15664
15665   OP_E (bytemode, sizeflag);
15666 }
15667
15668 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15669    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15670  */
15671
15672 static void
15673 HLE_Fixup2 (int bytemode, int sizeflag)
15674 {
15675   if (modrm.mod != 3)
15676     {
15677       if (prefixes & PREFIX_REPZ)
15678         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15679       if (prefixes & PREFIX_REPNZ)
15680         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15681     }
15682
15683   OP_E (bytemode, sizeflag);
15684 }
15685
15686 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15687    "xrelease" for memory operand.  No check for LOCK prefix.   */
15688
15689 static void
15690 HLE_Fixup3 (int bytemode, int sizeflag)
15691 {
15692   if (modrm.mod != 3
15693       && last_repz_prefix > last_repnz_prefix
15694       && (prefixes & PREFIX_REPZ) != 0)
15695     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15696
15697   OP_E (bytemode, sizeflag);
15698 }
15699
15700 static void
15701 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15702 {
15703   USED_REX (REX_W);
15704   if (rex & REX_W)
15705     {
15706       /* Change cmpxchg8b to cmpxchg16b.  */
15707       char *p = mnemonicendp - 2;
15708       mnemonicendp = stpcpy (p, "16b");
15709       bytemode = o_mode;
15710     }
15711   else if ((prefixes & PREFIX_LOCK) != 0)
15712     {
15713       if (prefixes & PREFIX_REPZ)
15714         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15715       if (prefixes & PREFIX_REPNZ)
15716         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15717     }
15718
15719   OP_M (bytemode, sizeflag);
15720 }
15721
15722 static void
15723 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15724 {
15725   const char **names;
15726
15727   if (need_vex)
15728     {
15729       switch (vex.length)
15730         {
15731         case 128:
15732           names = names_xmm;
15733           break;
15734         case 256:
15735           names = names_ymm;
15736           break;
15737         default:
15738           abort ();
15739         }
15740     }
15741   else
15742     names = names_xmm;
15743   oappend (names[reg]);
15744 }
15745
15746 static void
15747 CRC32_Fixup (int bytemode, int sizeflag)
15748 {
15749   /* Add proper suffix to "crc32".  */
15750   char *p = mnemonicendp;
15751
15752   switch (bytemode)
15753     {
15754     case b_mode:
15755       if (intel_syntax)
15756         goto skip;
15757
15758       *p++ = 'b';
15759       break;
15760     case v_mode:
15761       if (intel_syntax)
15762         goto skip;
15763
15764       USED_REX (REX_W);
15765       if (rex & REX_W)
15766         *p++ = 'q';
15767       else
15768         {
15769           if (sizeflag & DFLAG)
15770             *p++ = 'l';
15771           else
15772             *p++ = 'w';
15773           used_prefixes |= (prefixes & PREFIX_DATA);
15774         }
15775       break;
15776     default:
15777       oappend (INTERNAL_DISASSEMBLER_ERROR);
15778       break;
15779     }
15780   mnemonicendp = p;
15781   *p = '\0';
15782
15783 skip:
15784   if (modrm.mod == 3)
15785     {
15786       int add;
15787
15788       /* Skip mod/rm byte.  */
15789       MODRM_CHECK;
15790       codep++;
15791
15792       USED_REX (REX_B);
15793       add = (rex & REX_B) ? 8 : 0;
15794       if (bytemode == b_mode)
15795         {
15796           USED_REX (0);
15797           if (rex)
15798             oappend (names8rex[modrm.rm + add]);
15799           else
15800             oappend (names8[modrm.rm + add]);
15801         }
15802       else
15803         {
15804           USED_REX (REX_W);
15805           if (rex & REX_W)
15806             oappend (names64[modrm.rm + add]);
15807           else if ((prefixes & PREFIX_DATA))
15808             oappend (names16[modrm.rm + add]);
15809           else
15810             oappend (names32[modrm.rm + add]);
15811         }
15812     }
15813   else
15814     OP_E (bytemode, sizeflag);
15815 }
15816
15817 static void
15818 FXSAVE_Fixup (int bytemode, int sizeflag)
15819 {
15820   /* Add proper suffix to "fxsave" and "fxrstor".  */
15821   USED_REX (REX_W);
15822   if (rex & REX_W)
15823     {
15824       char *p = mnemonicendp;
15825       *p++ = '6';
15826       *p++ = '4';
15827       *p = '\0';
15828       mnemonicendp = p;
15829     }
15830   OP_M (bytemode, sizeflag);
15831 }
15832
15833 static void
15834 PCMPESTR_Fixup (int bytemode, int sizeflag)
15835 {
15836   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15837   if (!intel_syntax)
15838     {
15839       char *p = mnemonicendp;
15840
15841       USED_REX (REX_W);
15842       if (rex & REX_W)
15843         *p++ = 'q';
15844       else if (sizeflag & SUFFIX_ALWAYS)
15845         *p++ = 'l';
15846
15847       *p = '\0';
15848       mnemonicendp = p;
15849     }
15850
15851   OP_EX (bytemode, sizeflag);
15852 }
15853
15854 /* Display the destination register operand for instructions with
15855    VEX. */
15856
15857 static void
15858 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15859 {
15860   int reg;
15861   const char **names;
15862
15863   if (!need_vex)
15864     abort ();
15865
15866   if (!need_vex_reg)
15867     return;
15868
15869   reg = vex.register_specifier;
15870   vex.register_specifier = 0;
15871   if (address_mode != mode_64bit)
15872     reg &= 7;
15873   else if (vex.evex && !vex.v)
15874     reg += 16;
15875
15876   if (bytemode == vex_scalar_mode)
15877     {
15878       oappend (names_xmm[reg]);
15879       return;
15880     }
15881
15882   switch (vex.length)
15883     {
15884     case 128:
15885       switch (bytemode)
15886         {
15887         case vex_mode:
15888         case vex128_mode:
15889         case vex_vsib_q_w_dq_mode:
15890         case vex_vsib_q_w_d_mode:
15891           names = names_xmm;
15892           break;
15893         case dq_mode:
15894           if (rex & REX_W)
15895             names = names64;
15896           else
15897             names = names32;
15898           break;
15899         case mask_bd_mode:
15900         case mask_mode:
15901           if (reg > 0x7)
15902             {
15903               oappend ("(bad)");
15904               return;
15905             }
15906           names = names_mask;
15907           break;
15908         default:
15909           abort ();
15910           return;
15911         }
15912       break;
15913     case 256:
15914       switch (bytemode)
15915         {
15916         case vex_mode:
15917         case vex256_mode:
15918           names = names_ymm;
15919           break;
15920         case vex_vsib_q_w_dq_mode:
15921         case vex_vsib_q_w_d_mode:
15922           names = vex.w ? names_ymm : names_xmm;
15923           break;
15924         case mask_bd_mode:
15925         case mask_mode:
15926           if (reg > 0x7)
15927             {
15928               oappend ("(bad)");
15929               return;
15930             }
15931           names = names_mask;
15932           break;
15933         default:
15934           /* See PR binutils/20893 for a reproducer.  */
15935           oappend ("(bad)");
15936           return;
15937         }
15938       break;
15939     case 512:
15940       names = names_zmm;
15941       break;
15942     default:
15943       abort ();
15944       break;
15945     }
15946   oappend (names[reg]);
15947 }
15948
15949 /* Get the VEX immediate byte without moving codep.  */
15950
15951 static unsigned char
15952 get_vex_imm8 (int sizeflag, int opnum)
15953 {
15954   int bytes_before_imm = 0;
15955
15956   if (modrm.mod != 3)
15957     {
15958       /* There are SIB/displacement bytes.  */
15959       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15960         {
15961           /* 32/64 bit address mode */
15962           int base = modrm.rm;
15963
15964           /* Check SIB byte.  */
15965           if (base == 4)
15966             {
15967               FETCH_DATA (the_info, codep + 1);
15968               base = *codep & 7;
15969               /* When decoding the third source, don't increase
15970                  bytes_before_imm as this has already been incremented
15971                  by one in OP_E_memory while decoding the second
15972                  source operand.  */
15973               if (opnum == 0)
15974                 bytes_before_imm++;
15975             }
15976
15977           /* Don't increase bytes_before_imm when decoding the third source,
15978              it has already been incremented by OP_E_memory while decoding
15979              the second source operand.  */
15980           if (opnum == 0)
15981             {
15982               switch (modrm.mod)
15983                 {
15984                   case 0:
15985                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15986                        SIB == 5, there is a 4 byte displacement.  */
15987                     if (base != 5)
15988                       /* No displacement. */
15989                       break;
15990                     /* Fall through.  */
15991                   case 2:
15992                     /* 4 byte displacement.  */
15993                     bytes_before_imm += 4;
15994                     break;
15995                   case 1:
15996                     /* 1 byte displacement.  */
15997                     bytes_before_imm++;
15998                     break;
15999                 }
16000             }
16001         }
16002       else
16003         {
16004           /* 16 bit address mode */
16005           /* Don't increase bytes_before_imm when decoding the third source,
16006              it has already been incremented by OP_E_memory while decoding
16007              the second source operand.  */
16008           if (opnum == 0)
16009             {
16010               switch (modrm.mod)
16011                 {
16012                 case 0:
16013                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16014                   if (modrm.rm != 6)
16015                     /* No displacement. */
16016                     break;
16017                   /* Fall through.  */
16018                 case 2:
16019                   /* 2 byte displacement.  */
16020                   bytes_before_imm += 2;
16021                   break;
16022                 case 1:
16023                   /* 1 byte displacement: when decoding the third source,
16024                      don't increase bytes_before_imm as this has already
16025                      been incremented by one in OP_E_memory while decoding
16026                      the second source operand.  */
16027                   if (opnum == 0)
16028                     bytes_before_imm++;
16029
16030                   break;
16031                 }
16032             }
16033         }
16034     }
16035
16036   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16037   return codep [bytes_before_imm];
16038 }
16039
16040 static void
16041 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16042 {
16043   const char **names;
16044
16045   if (reg == -1 && modrm.mod != 3)
16046     {
16047       OP_E_memory (bytemode, sizeflag);
16048       return;
16049     }
16050   else
16051     {
16052       if (reg == -1)
16053         {
16054           reg = modrm.rm;
16055           USED_REX (REX_B);
16056           if (rex & REX_B)
16057             reg += 8;
16058         }
16059       if (address_mode != mode_64bit)
16060         reg &= 7;
16061     }
16062
16063   switch (vex.length)
16064     {
16065     case 128:
16066       names = names_xmm;
16067       break;
16068     case 256:
16069       names = names_ymm;
16070       break;
16071     default:
16072       abort ();
16073     }
16074   oappend (names[reg]);
16075 }
16076
16077 static void
16078 OP_EX_VexImmW (int bytemode, int sizeflag)
16079 {
16080   int reg = -1;
16081   static unsigned char vex_imm8;
16082
16083   if (vex_w_done == 0)
16084     {
16085       vex_w_done = 1;
16086
16087       /* Skip mod/rm byte.  */
16088       MODRM_CHECK;
16089       codep++;
16090
16091       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16092
16093       if (vex.w)
16094           reg = vex_imm8 >> 4;
16095
16096       OP_EX_VexReg (bytemode, sizeflag, reg);
16097     }
16098   else if (vex_w_done == 1)
16099     {
16100       vex_w_done = 2;
16101
16102       if (!vex.w)
16103           reg = vex_imm8 >> 4;
16104
16105       OP_EX_VexReg (bytemode, sizeflag, reg);
16106     }
16107   else
16108     {
16109       /* Output the imm8 directly.  */
16110       scratchbuf[0] = '$';
16111       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16112       oappend_maybe_intel (scratchbuf);
16113       scratchbuf[0] = '\0';
16114       codep++;
16115     }
16116 }
16117
16118 static void
16119 OP_Vex_2src (int bytemode, int sizeflag)
16120 {
16121   if (modrm.mod == 3)
16122     {
16123       int reg = modrm.rm;
16124       USED_REX (REX_B);
16125       if (rex & REX_B)
16126         reg += 8;
16127       oappend (names_xmm[reg]);
16128     }
16129   else
16130     {
16131       if (intel_syntax
16132           && (bytemode == v_mode || bytemode == v_swap_mode))
16133         {
16134           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16135           used_prefixes |= (prefixes & PREFIX_DATA);
16136         }
16137       OP_E (bytemode, sizeflag);
16138     }
16139 }
16140
16141 static void
16142 OP_Vex_2src_1 (int bytemode, int sizeflag)
16143 {
16144   if (modrm.mod == 3)
16145     {
16146       /* Skip mod/rm byte.   */
16147       MODRM_CHECK;
16148       codep++;
16149     }
16150
16151   if (vex.w)
16152     {
16153       unsigned int reg = vex.register_specifier;
16154       vex.register_specifier = 0;
16155
16156       if (address_mode != mode_64bit)
16157         reg &= 7;
16158       oappend (names_xmm[reg]);
16159     }
16160   else
16161     OP_Vex_2src (bytemode, sizeflag);
16162 }
16163
16164 static void
16165 OP_Vex_2src_2 (int bytemode, int sizeflag)
16166 {
16167   if (vex.w)
16168     OP_Vex_2src (bytemode, sizeflag);
16169   else
16170     {
16171       unsigned int reg = vex.register_specifier;
16172       vex.register_specifier = 0;
16173
16174       if (address_mode != mode_64bit)
16175         reg &= 7;
16176       oappend (names_xmm[reg]);
16177     }
16178 }
16179
16180 static void
16181 OP_EX_VexW (int bytemode, int sizeflag)
16182 {
16183   int reg = -1;
16184
16185   if (!vex_w_done)
16186     {
16187       /* Skip mod/rm byte.  */
16188       MODRM_CHECK;
16189       codep++;
16190
16191       if (vex.w)
16192         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16193     }
16194   else
16195     {
16196       if (!vex.w)
16197         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16198     }
16199
16200   OP_EX_VexReg (bytemode, sizeflag, reg);
16201
16202   if (vex_w_done)
16203     codep++;
16204   vex_w_done = 1;
16205 }
16206
16207 static void
16208 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16209 {
16210   int reg;
16211   const char **names;
16212
16213   FETCH_DATA (the_info, codep + 1);
16214   reg = *codep++;
16215
16216   if (bytemode != x_mode)
16217     abort ();
16218
16219   reg >>= 4;
16220   if (address_mode != mode_64bit)
16221     reg &= 7;
16222
16223   switch (vex.length)
16224     {
16225     case 128:
16226       names = names_xmm;
16227       break;
16228     case 256:
16229       names = names_ymm;
16230       break;
16231     default:
16232       abort ();
16233     }
16234   oappend (names[reg]);
16235 }
16236
16237 static void
16238 OP_XMM_VexW (int bytemode, int sizeflag)
16239 {
16240   /* Turn off the REX.W bit since it is used for swapping operands
16241      now.  */
16242   rex &= ~REX_W;
16243   OP_XMM (bytemode, sizeflag);
16244 }
16245
16246 static void
16247 OP_EX_Vex (int bytemode, int sizeflag)
16248 {
16249   if (modrm.mod != 3)
16250     need_vex_reg = 0;
16251   OP_EX (bytemode, sizeflag);
16252 }
16253
16254 static void
16255 OP_XMM_Vex (int bytemode, int sizeflag)
16256 {
16257   if (modrm.mod != 3)
16258     need_vex_reg = 0;
16259   OP_XMM (bytemode, sizeflag);
16260 }
16261
16262 static struct op vex_cmp_op[] =
16263 {
16264   { STRING_COMMA_LEN ("eq") },
16265   { STRING_COMMA_LEN ("lt") },
16266   { STRING_COMMA_LEN ("le") },
16267   { STRING_COMMA_LEN ("unord") },
16268   { STRING_COMMA_LEN ("neq") },
16269   { STRING_COMMA_LEN ("nlt") },
16270   { STRING_COMMA_LEN ("nle") },
16271   { STRING_COMMA_LEN ("ord") },
16272   { STRING_COMMA_LEN ("eq_uq") },
16273   { STRING_COMMA_LEN ("nge") },
16274   { STRING_COMMA_LEN ("ngt") },
16275   { STRING_COMMA_LEN ("false") },
16276   { STRING_COMMA_LEN ("neq_oq") },
16277   { STRING_COMMA_LEN ("ge") },
16278   { STRING_COMMA_LEN ("gt") },
16279   { STRING_COMMA_LEN ("true") },
16280   { STRING_COMMA_LEN ("eq_os") },
16281   { STRING_COMMA_LEN ("lt_oq") },
16282   { STRING_COMMA_LEN ("le_oq") },
16283   { STRING_COMMA_LEN ("unord_s") },
16284   { STRING_COMMA_LEN ("neq_us") },
16285   { STRING_COMMA_LEN ("nlt_uq") },
16286   { STRING_COMMA_LEN ("nle_uq") },
16287   { STRING_COMMA_LEN ("ord_s") },
16288   { STRING_COMMA_LEN ("eq_us") },
16289   { STRING_COMMA_LEN ("nge_uq") },
16290   { STRING_COMMA_LEN ("ngt_uq") },
16291   { STRING_COMMA_LEN ("false_os") },
16292   { STRING_COMMA_LEN ("neq_os") },
16293   { STRING_COMMA_LEN ("ge_oq") },
16294   { STRING_COMMA_LEN ("gt_oq") },
16295   { STRING_COMMA_LEN ("true_us") },
16296 };
16297
16298 static void
16299 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16300 {
16301   unsigned int cmp_type;
16302
16303   FETCH_DATA (the_info, codep + 1);
16304   cmp_type = *codep++ & 0xff;
16305   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16306     {
16307       char suffix [3];
16308       char *p = mnemonicendp - 2;
16309       suffix[0] = p[0];
16310       suffix[1] = p[1];
16311       suffix[2] = '\0';
16312       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16313       mnemonicendp += vex_cmp_op[cmp_type].len;
16314     }
16315   else
16316     {
16317       /* We have a reserved extension byte.  Output it directly.  */
16318       scratchbuf[0] = '$';
16319       print_operand_value (scratchbuf + 1, 1, cmp_type);
16320       oappend_maybe_intel (scratchbuf);
16321       scratchbuf[0] = '\0';
16322     }
16323 }
16324
16325 static void
16326 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16327              int sizeflag ATTRIBUTE_UNUSED)
16328 {
16329   unsigned int cmp_type;
16330
16331   if (!vex.evex)
16332     abort ();
16333
16334   FETCH_DATA (the_info, codep + 1);
16335   cmp_type = *codep++ & 0xff;
16336   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16337      If it's the case, print suffix, otherwise - print the immediate.  */
16338   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16339       && cmp_type != 3
16340       && cmp_type != 7)
16341     {
16342       char suffix [3];
16343       char *p = mnemonicendp - 2;
16344
16345       /* vpcmp* can have both one- and two-lettered suffix.  */
16346       if (p[0] == 'p')
16347         {
16348           p++;
16349           suffix[0] = p[0];
16350           suffix[1] = '\0';
16351         }
16352       else
16353         {
16354           suffix[0] = p[0];
16355           suffix[1] = p[1];
16356           suffix[2] = '\0';
16357         }
16358
16359       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16360       mnemonicendp += simd_cmp_op[cmp_type].len;
16361     }
16362   else
16363     {
16364       /* We have a reserved extension byte.  Output it directly.  */
16365       scratchbuf[0] = '$';
16366       print_operand_value (scratchbuf + 1, 1, cmp_type);
16367       oappend_maybe_intel (scratchbuf);
16368       scratchbuf[0] = '\0';
16369     }
16370 }
16371
16372 static const struct op xop_cmp_op[] =
16373 {
16374   { STRING_COMMA_LEN ("lt") },
16375   { STRING_COMMA_LEN ("le") },
16376   { STRING_COMMA_LEN ("gt") },
16377   { STRING_COMMA_LEN ("ge") },
16378   { STRING_COMMA_LEN ("eq") },
16379   { STRING_COMMA_LEN ("neq") },
16380   { STRING_COMMA_LEN ("false") },
16381   { STRING_COMMA_LEN ("true") }
16382 };
16383
16384 static void
16385 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16386              int sizeflag ATTRIBUTE_UNUSED)
16387 {
16388   unsigned int cmp_type;
16389
16390   FETCH_DATA (the_info, codep + 1);
16391   cmp_type = *codep++ & 0xff;
16392   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16393     {
16394       char suffix[3];
16395       char *p = mnemonicendp - 2;
16396
16397       /* vpcom* can have both one- and two-lettered suffix.  */
16398       if (p[0] == 'm')
16399         {
16400           p++;
16401           suffix[0] = p[0];
16402           suffix[1] = '\0';
16403         }
16404       else
16405         {
16406           suffix[0] = p[0];
16407           suffix[1] = p[1];
16408           suffix[2] = '\0';
16409         }
16410
16411       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16412       mnemonicendp += xop_cmp_op[cmp_type].len;
16413     }
16414   else
16415     {
16416       /* We have a reserved extension byte.  Output it directly.  */
16417       scratchbuf[0] = '$';
16418       print_operand_value (scratchbuf + 1, 1, cmp_type);
16419       oappend_maybe_intel (scratchbuf);
16420       scratchbuf[0] = '\0';
16421     }
16422 }
16423
16424 static const struct op pclmul_op[] =
16425 {
16426   { STRING_COMMA_LEN ("lql") },
16427   { STRING_COMMA_LEN ("hql") },
16428   { STRING_COMMA_LEN ("lqh") },
16429   { STRING_COMMA_LEN ("hqh") }
16430 };
16431
16432 static void
16433 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16434               int sizeflag ATTRIBUTE_UNUSED)
16435 {
16436   unsigned int pclmul_type;
16437
16438   FETCH_DATA (the_info, codep + 1);
16439   pclmul_type = *codep++ & 0xff;
16440   switch (pclmul_type)
16441     {
16442     case 0x10:
16443       pclmul_type = 2;
16444       break;
16445     case 0x11:
16446       pclmul_type = 3;
16447       break;
16448     default:
16449       break;
16450     }
16451   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16452     {
16453       char suffix [4];
16454       char *p = mnemonicendp - 3;
16455       suffix[0] = p[0];
16456       suffix[1] = p[1];
16457       suffix[2] = p[2];
16458       suffix[3] = '\0';
16459       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16460       mnemonicendp += pclmul_op[pclmul_type].len;
16461     }
16462   else
16463     {
16464       /* We have a reserved extension byte.  Output it directly.  */
16465       scratchbuf[0] = '$';
16466       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16467       oappend_maybe_intel (scratchbuf);
16468       scratchbuf[0] = '\0';
16469     }
16470 }
16471
16472 static void
16473 MOVBE_Fixup (int bytemode, int sizeflag)
16474 {
16475   /* Add proper suffix to "movbe".  */
16476   char *p = mnemonicendp;
16477
16478   switch (bytemode)
16479     {
16480     case v_mode:
16481       if (intel_syntax)
16482         goto skip;
16483
16484       USED_REX (REX_W);
16485       if (sizeflag & SUFFIX_ALWAYS)
16486         {
16487           if (rex & REX_W)
16488             *p++ = 'q';
16489           else
16490             {
16491               if (sizeflag & DFLAG)
16492                 *p++ = 'l';
16493               else
16494                 *p++ = 'w';
16495               used_prefixes |= (prefixes & PREFIX_DATA);
16496             }
16497         }
16498       break;
16499     default:
16500       oappend (INTERNAL_DISASSEMBLER_ERROR);
16501       break;
16502     }
16503   mnemonicendp = p;
16504   *p = '\0';
16505
16506 skip:
16507   OP_M (bytemode, sizeflag);
16508 }
16509
16510 static void
16511 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16512 {
16513   int reg;
16514   const char **names;
16515
16516   /* Skip mod/rm byte.  */
16517   MODRM_CHECK;
16518   codep++;
16519
16520   if (rex & REX_W)
16521     names = names64;
16522   else
16523     names = names32;
16524
16525   reg = modrm.rm;
16526   USED_REX (REX_B);
16527   if (rex & REX_B)
16528     reg += 8;
16529
16530   oappend (names[reg]);
16531 }
16532
16533 static void
16534 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16535 {
16536   const char **names;
16537   unsigned int reg = vex.register_specifier;
16538   vex.register_specifier = 0;
16539
16540   if (rex & REX_W)
16541     names = names64;
16542   else
16543     names = names32;
16544
16545   if (address_mode != mode_64bit)
16546     reg &= 7;
16547   oappend (names[reg]);
16548 }
16549
16550 static void
16551 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16552 {
16553   if (!vex.evex
16554       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16555     abort ();
16556
16557   USED_REX (REX_R);
16558   if ((rex & REX_R) != 0 || !vex.r)
16559     {
16560       BadOp ();
16561       return;
16562     }
16563
16564   oappend (names_mask [modrm.reg]);
16565 }
16566
16567 static void
16568 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16569 {
16570   if (!vex.evex
16571       || (bytemode != evex_rounding_mode
16572           && bytemode != evex_rounding_64_mode
16573           && bytemode != evex_sae_mode))
16574     abort ();
16575   if (modrm.mod == 3 && vex.b)
16576     switch (bytemode)
16577       {
16578       case evex_rounding_64_mode:
16579         if (address_mode != mode_64bit)
16580           {
16581             oappend ("(bad)");
16582             break;
16583           }
16584         /* Fall through.  */
16585       case evex_rounding_mode:
16586         oappend (names_rounding[vex.ll]);
16587         break;
16588       case evex_sae_mode:
16589         oappend ("{sae}");
16590         break;
16591       default:
16592         break;
16593       }
16594 }