1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
134 OPCODES_SIGJMP_BUF bailout
;
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode
,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode
,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode
,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode
,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
796 MOD_VEX_0F12_PREFIX_0
,
798 MOD_VEX_0F16_PREFIX_0
,
814 MOD_VEX_0FD7_PREFIX_2
,
815 MOD_VEX_0FE7_PREFIX_2
,
816 MOD_VEX_0FF0_PREFIX_3
,
817 MOD_VEX_0F381A_PREFIX_2
,
818 MOD_VEX_0F382A_PREFIX_2
,
819 MOD_VEX_0F382C_PREFIX_2
,
820 MOD_VEX_0F382D_PREFIX_2
,
821 MOD_VEX_0F382E_PREFIX_2
,
822 MOD_VEX_0F382F_PREFIX_2
,
823 MOD_VEX_0F385A_PREFIX_2
,
824 MOD_VEX_0F388C_PREFIX_2
,
825 MOD_VEX_0F388E_PREFIX_2
,
827 MOD_EVEX_0F10_PREFIX_1
,
828 MOD_EVEX_0F10_PREFIX_3
,
829 MOD_EVEX_0F11_PREFIX_1
,
830 MOD_EVEX_0F11_PREFIX_3
,
831 MOD_EVEX_0F12_PREFIX_0
,
832 MOD_EVEX_0F16_PREFIX_0
,
833 MOD_EVEX_0F38C6_REG_1
,
834 MOD_EVEX_0F38C6_REG_2
,
835 MOD_EVEX_0F38C6_REG_5
,
836 MOD_EVEX_0F38C6_REG_6
,
837 MOD_EVEX_0F38C7_REG_1
,
838 MOD_EVEX_0F38C7_REG_2
,
839 MOD_EVEX_0F38C7_REG_5
,
840 MOD_EVEX_0F38C7_REG_6
904 PREFIX_RM_0_0FAE_REG_7
,
1034 PREFIX_VEX_0F71_REG_2
,
1035 PREFIX_VEX_0F71_REG_4
,
1036 PREFIX_VEX_0F71_REG_6
,
1037 PREFIX_VEX_0F72_REG_2
,
1038 PREFIX_VEX_0F72_REG_4
,
1039 PREFIX_VEX_0F72_REG_6
,
1040 PREFIX_VEX_0F73_REG_2
,
1041 PREFIX_VEX_0F73_REG_3
,
1042 PREFIX_VEX_0F73_REG_6
,
1043 PREFIX_VEX_0F73_REG_7
,
1215 PREFIX_VEX_0F38F3_REG_1
,
1216 PREFIX_VEX_0F38F3_REG_2
,
1217 PREFIX_VEX_0F38F3_REG_3
,
1334 PREFIX_EVEX_0F71_REG_2
,
1335 PREFIX_EVEX_0F71_REG_4
,
1336 PREFIX_EVEX_0F71_REG_6
,
1337 PREFIX_EVEX_0F72_REG_0
,
1338 PREFIX_EVEX_0F72_REG_1
,
1339 PREFIX_EVEX_0F72_REG_2
,
1340 PREFIX_EVEX_0F72_REG_4
,
1341 PREFIX_EVEX_0F72_REG_6
,
1342 PREFIX_EVEX_0F73_REG_2
,
1343 PREFIX_EVEX_0F73_REG_3
,
1344 PREFIX_EVEX_0F73_REG_6
,
1345 PREFIX_EVEX_0F73_REG_7
,
1527 PREFIX_EVEX_0F38C6_REG_1
,
1528 PREFIX_EVEX_0F38C6_REG_2
,
1529 PREFIX_EVEX_0F38C6_REG_5
,
1530 PREFIX_EVEX_0F38C6_REG_6
,
1531 PREFIX_EVEX_0F38C7_REG_1
,
1532 PREFIX_EVEX_0F38C7_REG_2
,
1533 PREFIX_EVEX_0F38C7_REG_5
,
1534 PREFIX_EVEX_0F38C7_REG_6
,
1621 THREE_BYTE_0F38
= 0,
1649 VEX_LEN_0F10_P_1
= 0,
1653 VEX_LEN_0F12_P_0_M_0
,
1654 VEX_LEN_0F12_P_0_M_1
,
1657 VEX_LEN_0F16_P_0_M_0
,
1658 VEX_LEN_0F16_P_0_M_1
,
1722 VEX_LEN_0FAE_R_2_M_0
,
1723 VEX_LEN_0FAE_R_3_M_0
,
1732 VEX_LEN_0F381A_P_2_M_0
,
1735 VEX_LEN_0F385A_P_2_M_0
,
1742 VEX_LEN_0F38F3_R_1_P_0
,
1743 VEX_LEN_0F38F3_R_2_P_0
,
1744 VEX_LEN_0F38F3_R_3_P_0
,
1790 VEX_LEN_0FXOP_08_CC
,
1791 VEX_LEN_0FXOP_08_CD
,
1792 VEX_LEN_0FXOP_08_CE
,
1793 VEX_LEN_0FXOP_08_CF
,
1794 VEX_LEN_0FXOP_08_EC
,
1795 VEX_LEN_0FXOP_08_ED
,
1796 VEX_LEN_0FXOP_08_EE
,
1797 VEX_LEN_0FXOP_08_EF
,
1798 VEX_LEN_0FXOP_09_80
,
1832 VEX_W_0F41_P_0_LEN_1
,
1833 VEX_W_0F41_P_2_LEN_1
,
1834 VEX_W_0F42_P_0_LEN_1
,
1835 VEX_W_0F42_P_2_LEN_1
,
1836 VEX_W_0F44_P_0_LEN_0
,
1837 VEX_W_0F44_P_2_LEN_0
,
1838 VEX_W_0F45_P_0_LEN_1
,
1839 VEX_W_0F45_P_2_LEN_1
,
1840 VEX_W_0F46_P_0_LEN_1
,
1841 VEX_W_0F46_P_2_LEN_1
,
1842 VEX_W_0F47_P_0_LEN_1
,
1843 VEX_W_0F47_P_2_LEN_1
,
1844 VEX_W_0F4A_P_0_LEN_1
,
1845 VEX_W_0F4A_P_2_LEN_1
,
1846 VEX_W_0F4B_P_0_LEN_1
,
1847 VEX_W_0F4B_P_2_LEN_1
,
1927 VEX_W_0F90_P_0_LEN_0
,
1928 VEX_W_0F90_P_2_LEN_0
,
1929 VEX_W_0F91_P_0_LEN_0
,
1930 VEX_W_0F91_P_2_LEN_0
,
1931 VEX_W_0F92_P_0_LEN_0
,
1932 VEX_W_0F92_P_2_LEN_0
,
1933 VEX_W_0F92_P_3_LEN_0
,
1934 VEX_W_0F93_P_0_LEN_0
,
1935 VEX_W_0F93_P_2_LEN_0
,
1936 VEX_W_0F93_P_3_LEN_0
,
1937 VEX_W_0F98_P_0_LEN_0
,
1938 VEX_W_0F98_P_2_LEN_0
,
1939 VEX_W_0F99_P_0_LEN_0
,
1940 VEX_W_0F99_P_2_LEN_0
,
2019 VEX_W_0F381A_P_2_M_0
,
2031 VEX_W_0F382A_P_2_M_0
,
2033 VEX_W_0F382C_P_2_M_0
,
2034 VEX_W_0F382D_P_2_M_0
,
2035 VEX_W_0F382E_P_2_M_0
,
2036 VEX_W_0F382F_P_2_M_0
,
2058 VEX_W_0F385A_P_2_M_0
,
2086 VEX_W_0F3A30_P_2_LEN_0
,
2087 VEX_W_0F3A31_P_2_LEN_0
,
2088 VEX_W_0F3A32_P_2_LEN_0
,
2089 VEX_W_0F3A33_P_2_LEN_0
,
2109 EVEX_W_0F10_P_1_M_0
,
2110 EVEX_W_0F10_P_1_M_1
,
2112 EVEX_W_0F10_P_3_M_0
,
2113 EVEX_W_0F10_P_3_M_1
,
2115 EVEX_W_0F11_P_1_M_0
,
2116 EVEX_W_0F11_P_1_M_1
,
2118 EVEX_W_0F11_P_3_M_0
,
2119 EVEX_W_0F11_P_3_M_1
,
2120 EVEX_W_0F12_P_0_M_0
,
2121 EVEX_W_0F12_P_0_M_1
,
2131 EVEX_W_0F16_P_0_M_0
,
2132 EVEX_W_0F16_P_0_M_1
,
2203 EVEX_W_0F72_R_2_P_2
,
2204 EVEX_W_0F72_R_6_P_2
,
2205 EVEX_W_0F73_R_2_P_2
,
2206 EVEX_W_0F73_R_6_P_2
,
2305 EVEX_W_0F38C7_R_1_P_2
,
2306 EVEX_W_0F38C7_R_2_P_2
,
2307 EVEX_W_0F38C7_R_5_P_2
,
2308 EVEX_W_0F38C7_R_6_P_2
,
2343 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2354 /* Upper case letters in the instruction names here are macros.
2355 'A' => print 'b' if no register operands or suffix_always is true
2356 'B' => print 'b' if suffix_always is true
2357 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2359 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2360 suffix_always is true
2361 'E' => print 'e' if 32-bit form of jcxz
2362 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2363 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2364 'H' => print ",pt" or ",pn" branch hint
2365 'I' => honor following macro letter even in Intel mode (implemented only
2366 for some of the macro letters)
2368 'K' => print 'd' or 'q' if rex prefix is present.
2369 'L' => print 'l' if suffix_always is true
2370 'M' => print 'r' if intel_mnemonic is false.
2371 'N' => print 'n' if instruction has no wait "prefix"
2372 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2373 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2374 or suffix_always is true. print 'q' if rex prefix is present.
2375 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2377 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2378 'S' => print 'w', 'l' or 'q' if suffix_always is true
2379 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2380 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2381 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2382 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2383 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2384 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2385 suffix_always is true.
2386 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2387 '!' => change condition from true to false or from false to true.
2388 '%' => add 1 upper case letter to the macro.
2390 2 upper case letter macros:
2391 "XY" => print 'x' or 'y' if no register operands or suffix_always
2393 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2394 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2395 or suffix_always is true
2396 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2397 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2398 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2399 "LW" => print 'd', 'q' depending on the VEX.W bit
2400 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2401 an operand size prefix, or suffix_always is true. print
2402 'q' if rex prefix is present.
2404 Many of the above letters print nothing in Intel mode. See "putop"
2407 Braces '{' and '}', and vertical bars '|', indicate alternative
2408 mnemonic strings for AT&T and Intel. */
2410 static const struct dis386 dis386
[] = {
2412 { "addB", { Ebh1
, Gb
} },
2413 { "addS", { Evh1
, Gv
} },
2414 { "addB", { Gb
, EbS
} },
2415 { "addS", { Gv
, EvS
} },
2416 { "addB", { AL
, Ib
} },
2417 { "addS", { eAX
, Iv
} },
2418 { X86_64_TABLE (X86_64_06
) },
2419 { X86_64_TABLE (X86_64_07
) },
2421 { "orB", { Ebh1
, Gb
} },
2422 { "orS", { Evh1
, Gv
} },
2423 { "orB", { Gb
, EbS
} },
2424 { "orS", { Gv
, EvS
} },
2425 { "orB", { AL
, Ib
} },
2426 { "orS", { eAX
, Iv
} },
2427 { X86_64_TABLE (X86_64_0D
) },
2428 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2430 { "adcB", { Ebh1
, Gb
} },
2431 { "adcS", { Evh1
, Gv
} },
2432 { "adcB", { Gb
, EbS
} },
2433 { "adcS", { Gv
, EvS
} },
2434 { "adcB", { AL
, Ib
} },
2435 { "adcS", { eAX
, Iv
} },
2436 { X86_64_TABLE (X86_64_16
) },
2437 { X86_64_TABLE (X86_64_17
) },
2439 { "sbbB", { Ebh1
, Gb
} },
2440 { "sbbS", { Evh1
, Gv
} },
2441 { "sbbB", { Gb
, EbS
} },
2442 { "sbbS", { Gv
, EvS
} },
2443 { "sbbB", { AL
, Ib
} },
2444 { "sbbS", { eAX
, Iv
} },
2445 { X86_64_TABLE (X86_64_1E
) },
2446 { X86_64_TABLE (X86_64_1F
) },
2448 { "andB", { Ebh1
, Gb
} },
2449 { "andS", { Evh1
, Gv
} },
2450 { "andB", { Gb
, EbS
} },
2451 { "andS", { Gv
, EvS
} },
2452 { "andB", { AL
, Ib
} },
2453 { "andS", { eAX
, Iv
} },
2454 { Bad_Opcode
}, /* SEG ES prefix */
2455 { X86_64_TABLE (X86_64_27
) },
2457 { "subB", { Ebh1
, Gb
} },
2458 { "subS", { Evh1
, Gv
} },
2459 { "subB", { Gb
, EbS
} },
2460 { "subS", { Gv
, EvS
} },
2461 { "subB", { AL
, Ib
} },
2462 { "subS", { eAX
, Iv
} },
2463 { Bad_Opcode
}, /* SEG CS prefix */
2464 { X86_64_TABLE (X86_64_2F
) },
2466 { "xorB", { Ebh1
, Gb
} },
2467 { "xorS", { Evh1
, Gv
} },
2468 { "xorB", { Gb
, EbS
} },
2469 { "xorS", { Gv
, EvS
} },
2470 { "xorB", { AL
, Ib
} },
2471 { "xorS", { eAX
, Iv
} },
2472 { Bad_Opcode
}, /* SEG SS prefix */
2473 { X86_64_TABLE (X86_64_37
) },
2475 { "cmpB", { Eb
, Gb
} },
2476 { "cmpS", { Ev
, Gv
} },
2477 { "cmpB", { Gb
, EbS
} },
2478 { "cmpS", { Gv
, EvS
} },
2479 { "cmpB", { AL
, Ib
} },
2480 { "cmpS", { eAX
, Iv
} },
2481 { Bad_Opcode
}, /* SEG DS prefix */
2482 { X86_64_TABLE (X86_64_3F
) },
2484 { "inc{S|}", { RMeAX
} },
2485 { "inc{S|}", { RMeCX
} },
2486 { "inc{S|}", { RMeDX
} },
2487 { "inc{S|}", { RMeBX
} },
2488 { "inc{S|}", { RMeSP
} },
2489 { "inc{S|}", { RMeBP
} },
2490 { "inc{S|}", { RMeSI
} },
2491 { "inc{S|}", { RMeDI
} },
2493 { "dec{S|}", { RMeAX
} },
2494 { "dec{S|}", { RMeCX
} },
2495 { "dec{S|}", { RMeDX
} },
2496 { "dec{S|}", { RMeBX
} },
2497 { "dec{S|}", { RMeSP
} },
2498 { "dec{S|}", { RMeBP
} },
2499 { "dec{S|}", { RMeSI
} },
2500 { "dec{S|}", { RMeDI
} },
2502 { "pushV", { RMrAX
} },
2503 { "pushV", { RMrCX
} },
2504 { "pushV", { RMrDX
} },
2505 { "pushV", { RMrBX
} },
2506 { "pushV", { RMrSP
} },
2507 { "pushV", { RMrBP
} },
2508 { "pushV", { RMrSI
} },
2509 { "pushV", { RMrDI
} },
2511 { "popV", { RMrAX
} },
2512 { "popV", { RMrCX
} },
2513 { "popV", { RMrDX
} },
2514 { "popV", { RMrBX
} },
2515 { "popV", { RMrSP
} },
2516 { "popV", { RMrBP
} },
2517 { "popV", { RMrSI
} },
2518 { "popV", { RMrDI
} },
2520 { X86_64_TABLE (X86_64_60
) },
2521 { X86_64_TABLE (X86_64_61
) },
2522 { X86_64_TABLE (X86_64_62
) },
2523 { X86_64_TABLE (X86_64_63
) },
2524 { Bad_Opcode
}, /* seg fs */
2525 { Bad_Opcode
}, /* seg gs */
2526 { Bad_Opcode
}, /* op size prefix */
2527 { Bad_Opcode
}, /* adr size prefix */
2529 { "pushT", { sIv
} },
2530 { "imulS", { Gv
, Ev
, Iv
} },
2531 { "pushT", { sIbT
} },
2532 { "imulS", { Gv
, Ev
, sIb
} },
2533 { "ins{b|}", { Ybr
, indirDX
} },
2534 { X86_64_TABLE (X86_64_6D
) },
2535 { "outs{b|}", { indirDXr
, Xb
} },
2536 { X86_64_TABLE (X86_64_6F
) },
2538 { "joH", { Jb
, BND
, cond_jump_flag
} },
2539 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2540 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2541 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2542 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2543 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2544 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2545 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2547 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2548 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2549 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2550 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2551 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2552 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2553 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2554 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2556 { REG_TABLE (REG_80
) },
2557 { REG_TABLE (REG_81
) },
2559 { REG_TABLE (REG_82
) },
2560 { "testB", { Eb
, Gb
} },
2561 { "testS", { Ev
, Gv
} },
2562 { "xchgB", { Ebh2
, Gb
} },
2563 { "xchgS", { Evh2
, Gv
} },
2565 { "movB", { Ebh3
, Gb
} },
2566 { "movS", { Evh3
, Gv
} },
2567 { "movB", { Gb
, EbS
} },
2568 { "movS", { Gv
, EvS
} },
2569 { "movD", { Sv
, Sw
} },
2570 { MOD_TABLE (MOD_8D
) },
2571 { "movD", { Sw
, Sv
} },
2572 { REG_TABLE (REG_8F
) },
2574 { PREFIX_TABLE (PREFIX_90
) },
2575 { "xchgS", { RMeCX
, eAX
} },
2576 { "xchgS", { RMeDX
, eAX
} },
2577 { "xchgS", { RMeBX
, eAX
} },
2578 { "xchgS", { RMeSP
, eAX
} },
2579 { "xchgS", { RMeBP
, eAX
} },
2580 { "xchgS", { RMeSI
, eAX
} },
2581 { "xchgS", { RMeDI
, eAX
} },
2583 { "cW{t|}R", { XX
} },
2584 { "cR{t|}O", { XX
} },
2585 { X86_64_TABLE (X86_64_9A
) },
2586 { Bad_Opcode
}, /* fwait */
2587 { "pushfT", { XX
} },
2588 { "popfT", { XX
} },
2592 { "mov%LB", { AL
, Ob
} },
2593 { "mov%LS", { eAX
, Ov
} },
2594 { "mov%LB", { Ob
, AL
} },
2595 { "mov%LS", { Ov
, eAX
} },
2596 { "movs{b|}", { Ybr
, Xb
} },
2597 { "movs{R|}", { Yvr
, Xv
} },
2598 { "cmps{b|}", { Xb
, Yb
} },
2599 { "cmps{R|}", { Xv
, Yv
} },
2601 { "testB", { AL
, Ib
} },
2602 { "testS", { eAX
, Iv
} },
2603 { "stosB", { Ybr
, AL
} },
2604 { "stosS", { Yvr
, eAX
} },
2605 { "lodsB", { ALr
, Xb
} },
2606 { "lodsS", { eAXr
, Xv
} },
2607 { "scasB", { AL
, Yb
} },
2608 { "scasS", { eAX
, Yv
} },
2610 { "movB", { RMAL
, Ib
} },
2611 { "movB", { RMCL
, Ib
} },
2612 { "movB", { RMDL
, Ib
} },
2613 { "movB", { RMBL
, Ib
} },
2614 { "movB", { RMAH
, Ib
} },
2615 { "movB", { RMCH
, Ib
} },
2616 { "movB", { RMDH
, Ib
} },
2617 { "movB", { RMBH
, Ib
} },
2619 { "mov%LV", { RMeAX
, Iv64
} },
2620 { "mov%LV", { RMeCX
, Iv64
} },
2621 { "mov%LV", { RMeDX
, Iv64
} },
2622 { "mov%LV", { RMeBX
, Iv64
} },
2623 { "mov%LV", { RMeSP
, Iv64
} },
2624 { "mov%LV", { RMeBP
, Iv64
} },
2625 { "mov%LV", { RMeSI
, Iv64
} },
2626 { "mov%LV", { RMeDI
, Iv64
} },
2628 { REG_TABLE (REG_C0
) },
2629 { REG_TABLE (REG_C1
) },
2630 { "retT", { Iw
, BND
} },
2631 { "retT", { BND
} },
2632 { X86_64_TABLE (X86_64_C4
) },
2633 { X86_64_TABLE (X86_64_C5
) },
2634 { REG_TABLE (REG_C6
) },
2635 { REG_TABLE (REG_C7
) },
2637 { "enterT", { Iw
, Ib
} },
2638 { "leaveT", { XX
} },
2639 { "Jret{|f}P", { Iw
} },
2640 { "Jret{|f}P", { XX
} },
2643 { X86_64_TABLE (X86_64_CE
) },
2644 { "iret%LP", { XX
} },
2646 { REG_TABLE (REG_D0
) },
2647 { REG_TABLE (REG_D1
) },
2648 { REG_TABLE (REG_D2
) },
2649 { REG_TABLE (REG_D3
) },
2650 { X86_64_TABLE (X86_64_D4
) },
2651 { X86_64_TABLE (X86_64_D5
) },
2653 { "xlat", { DSBX
} },
2664 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2665 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2666 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2667 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2668 { "inB", { AL
, Ib
} },
2669 { "inG", { zAX
, Ib
} },
2670 { "outB", { Ib
, AL
} },
2671 { "outG", { Ib
, zAX
} },
2673 { "callT", { Jv
, BND
} },
2674 { "jmpT", { Jv
, BND
} },
2675 { X86_64_TABLE (X86_64_EA
) },
2676 { "jmp", { Jb
, BND
} },
2677 { "inB", { AL
, indirDX
} },
2678 { "inG", { zAX
, indirDX
} },
2679 { "outB", { indirDX
, AL
} },
2680 { "outG", { indirDX
, zAX
} },
2682 { Bad_Opcode
}, /* lock prefix */
2683 { "icebp", { XX
} },
2684 { Bad_Opcode
}, /* repne */
2685 { Bad_Opcode
}, /* repz */
2688 { REG_TABLE (REG_F6
) },
2689 { REG_TABLE (REG_F7
) },
2697 { REG_TABLE (REG_FE
) },
2698 { REG_TABLE (REG_FF
) },
2701 static const struct dis386 dis386_twobyte
[] = {
2703 { REG_TABLE (REG_0F00
) },
2704 { REG_TABLE (REG_0F01
) },
2705 { "larS", { Gv
, Ew
} },
2706 { "lslS", { Gv
, Ew
} },
2708 { "syscall", { XX
} },
2710 { "sysret%LP", { XX
} },
2713 { "wbinvd", { XX
} },
2717 { REG_TABLE (REG_0F0D
) },
2718 { "femms", { XX
} },
2719 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2721 { PREFIX_TABLE (PREFIX_0F10
) },
2722 { PREFIX_TABLE (PREFIX_0F11
) },
2723 { PREFIX_TABLE (PREFIX_0F12
) },
2724 { MOD_TABLE (MOD_0F13
) },
2725 { "unpcklpX", { XM
, EXx
} },
2726 { "unpckhpX", { XM
, EXx
} },
2727 { PREFIX_TABLE (PREFIX_0F16
) },
2728 { MOD_TABLE (MOD_0F17
) },
2730 { REG_TABLE (REG_0F18
) },
2732 { PREFIX_TABLE (PREFIX_0F1A
) },
2733 { PREFIX_TABLE (PREFIX_0F1B
) },
2739 { "movZ", { Rm
, Cm
} },
2740 { "movZ", { Rm
, Dm
} },
2741 { "movZ", { Cm
, Rm
} },
2742 { "movZ", { Dm
, Rm
} },
2743 { MOD_TABLE (MOD_0F24
) },
2745 { MOD_TABLE (MOD_0F26
) },
2748 { "movapX", { XM
, EXx
} },
2749 { "movapX", { EXxS
, XM
} },
2750 { PREFIX_TABLE (PREFIX_0F2A
) },
2751 { PREFIX_TABLE (PREFIX_0F2B
) },
2752 { PREFIX_TABLE (PREFIX_0F2C
) },
2753 { PREFIX_TABLE (PREFIX_0F2D
) },
2754 { PREFIX_TABLE (PREFIX_0F2E
) },
2755 { PREFIX_TABLE (PREFIX_0F2F
) },
2757 { "wrmsr", { XX
} },
2758 { "rdtsc", { XX
} },
2759 { "rdmsr", { XX
} },
2760 { "rdpmc", { XX
} },
2761 { "sysenter", { XX
} },
2762 { "sysexit", { XX
} },
2764 { "getsec", { XX
} },
2766 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2768 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2775 { "cmovoS", { Gv
, Ev
} },
2776 { "cmovnoS", { Gv
, Ev
} },
2777 { "cmovbS", { Gv
, Ev
} },
2778 { "cmovaeS", { Gv
, Ev
} },
2779 { "cmoveS", { Gv
, Ev
} },
2780 { "cmovneS", { Gv
, Ev
} },
2781 { "cmovbeS", { Gv
, Ev
} },
2782 { "cmovaS", { Gv
, Ev
} },
2784 { "cmovsS", { Gv
, Ev
} },
2785 { "cmovnsS", { Gv
, Ev
} },
2786 { "cmovpS", { Gv
, Ev
} },
2787 { "cmovnpS", { Gv
, Ev
} },
2788 { "cmovlS", { Gv
, Ev
} },
2789 { "cmovgeS", { Gv
, Ev
} },
2790 { "cmovleS", { Gv
, Ev
} },
2791 { "cmovgS", { Gv
, Ev
} },
2793 { MOD_TABLE (MOD_0F51
) },
2794 { PREFIX_TABLE (PREFIX_0F51
) },
2795 { PREFIX_TABLE (PREFIX_0F52
) },
2796 { PREFIX_TABLE (PREFIX_0F53
) },
2797 { "andpX", { XM
, EXx
} },
2798 { "andnpX", { XM
, EXx
} },
2799 { "orpX", { XM
, EXx
} },
2800 { "xorpX", { XM
, EXx
} },
2802 { PREFIX_TABLE (PREFIX_0F58
) },
2803 { PREFIX_TABLE (PREFIX_0F59
) },
2804 { PREFIX_TABLE (PREFIX_0F5A
) },
2805 { PREFIX_TABLE (PREFIX_0F5B
) },
2806 { PREFIX_TABLE (PREFIX_0F5C
) },
2807 { PREFIX_TABLE (PREFIX_0F5D
) },
2808 { PREFIX_TABLE (PREFIX_0F5E
) },
2809 { PREFIX_TABLE (PREFIX_0F5F
) },
2811 { PREFIX_TABLE (PREFIX_0F60
) },
2812 { PREFIX_TABLE (PREFIX_0F61
) },
2813 { PREFIX_TABLE (PREFIX_0F62
) },
2814 { "packsswb", { MX
, EM
} },
2815 { "pcmpgtb", { MX
, EM
} },
2816 { "pcmpgtw", { MX
, EM
} },
2817 { "pcmpgtd", { MX
, EM
} },
2818 { "packuswb", { MX
, EM
} },
2820 { "punpckhbw", { MX
, EM
} },
2821 { "punpckhwd", { MX
, EM
} },
2822 { "punpckhdq", { MX
, EM
} },
2823 { "packssdw", { MX
, EM
} },
2824 { PREFIX_TABLE (PREFIX_0F6C
) },
2825 { PREFIX_TABLE (PREFIX_0F6D
) },
2826 { "movK", { MX
, Edq
} },
2827 { PREFIX_TABLE (PREFIX_0F6F
) },
2829 { PREFIX_TABLE (PREFIX_0F70
) },
2830 { REG_TABLE (REG_0F71
) },
2831 { REG_TABLE (REG_0F72
) },
2832 { REG_TABLE (REG_0F73
) },
2833 { "pcmpeqb", { MX
, EM
} },
2834 { "pcmpeqw", { MX
, EM
} },
2835 { "pcmpeqd", { MX
, EM
} },
2838 { PREFIX_TABLE (PREFIX_0F78
) },
2839 { PREFIX_TABLE (PREFIX_0F79
) },
2840 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2842 { PREFIX_TABLE (PREFIX_0F7C
) },
2843 { PREFIX_TABLE (PREFIX_0F7D
) },
2844 { PREFIX_TABLE (PREFIX_0F7E
) },
2845 { PREFIX_TABLE (PREFIX_0F7F
) },
2847 { "joH", { Jv
, BND
, cond_jump_flag
} },
2848 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2849 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2850 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2851 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2852 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2853 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2854 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2856 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2857 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2858 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2859 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2860 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2861 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2862 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2863 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2866 { "setno", { Eb
} },
2868 { "setae", { Eb
} },
2870 { "setne", { Eb
} },
2871 { "setbe", { Eb
} },
2875 { "setns", { Eb
} },
2877 { "setnp", { Eb
} },
2879 { "setge", { Eb
} },
2880 { "setle", { Eb
} },
2883 { "pushT", { fs
} },
2885 { "cpuid", { XX
} },
2886 { "btS", { Ev
, Gv
} },
2887 { "shldS", { Ev
, Gv
, Ib
} },
2888 { "shldS", { Ev
, Gv
, CL
} },
2889 { REG_TABLE (REG_0FA6
) },
2890 { REG_TABLE (REG_0FA7
) },
2892 { "pushT", { gs
} },
2895 { "btsS", { Evh1
, Gv
} },
2896 { "shrdS", { Ev
, Gv
, Ib
} },
2897 { "shrdS", { Ev
, Gv
, CL
} },
2898 { REG_TABLE (REG_0FAE
) },
2899 { "imulS", { Gv
, Ev
} },
2901 { "cmpxchgB", { Ebh1
, Gb
} },
2902 { "cmpxchgS", { Evh1
, Gv
} },
2903 { MOD_TABLE (MOD_0FB2
) },
2904 { "btrS", { Evh1
, Gv
} },
2905 { MOD_TABLE (MOD_0FB4
) },
2906 { MOD_TABLE (MOD_0FB5
) },
2907 { "movz{bR|x}", { Gv
, Eb
} },
2908 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2910 { PREFIX_TABLE (PREFIX_0FB8
) },
2912 { REG_TABLE (REG_0FBA
) },
2913 { "btcS", { Evh1
, Gv
} },
2914 { PREFIX_TABLE (PREFIX_0FBC
) },
2915 { PREFIX_TABLE (PREFIX_0FBD
) },
2916 { "movs{bR|x}", { Gv
, Eb
} },
2917 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2919 { "xaddB", { Ebh1
, Gb
} },
2920 { "xaddS", { Evh1
, Gv
} },
2921 { PREFIX_TABLE (PREFIX_0FC2
) },
2922 { PREFIX_TABLE (PREFIX_0FC3
) },
2923 { "pinsrw", { MX
, Edqw
, Ib
} },
2924 { "pextrw", { Gdq
, MS
, Ib
} },
2925 { "shufpX", { XM
, EXx
, Ib
} },
2926 { REG_TABLE (REG_0FC7
) },
2928 { "bswap", { RMeAX
} },
2929 { "bswap", { RMeCX
} },
2930 { "bswap", { RMeDX
} },
2931 { "bswap", { RMeBX
} },
2932 { "bswap", { RMeSP
} },
2933 { "bswap", { RMeBP
} },
2934 { "bswap", { RMeSI
} },
2935 { "bswap", { RMeDI
} },
2937 { PREFIX_TABLE (PREFIX_0FD0
) },
2938 { "psrlw", { MX
, EM
} },
2939 { "psrld", { MX
, EM
} },
2940 { "psrlq", { MX
, EM
} },
2941 { "paddq", { MX
, EM
} },
2942 { "pmullw", { MX
, EM
} },
2943 { PREFIX_TABLE (PREFIX_0FD6
) },
2944 { MOD_TABLE (MOD_0FD7
) },
2946 { "psubusb", { MX
, EM
} },
2947 { "psubusw", { MX
, EM
} },
2948 { "pminub", { MX
, EM
} },
2949 { "pand", { MX
, EM
} },
2950 { "paddusb", { MX
, EM
} },
2951 { "paddusw", { MX
, EM
} },
2952 { "pmaxub", { MX
, EM
} },
2953 { "pandn", { MX
, EM
} },
2955 { "pavgb", { MX
, EM
} },
2956 { "psraw", { MX
, EM
} },
2957 { "psrad", { MX
, EM
} },
2958 { "pavgw", { MX
, EM
} },
2959 { "pmulhuw", { MX
, EM
} },
2960 { "pmulhw", { MX
, EM
} },
2961 { PREFIX_TABLE (PREFIX_0FE6
) },
2962 { PREFIX_TABLE (PREFIX_0FE7
) },
2964 { "psubsb", { MX
, EM
} },
2965 { "psubsw", { MX
, EM
} },
2966 { "pminsw", { MX
, EM
} },
2967 { "por", { MX
, EM
} },
2968 { "paddsb", { MX
, EM
} },
2969 { "paddsw", { MX
, EM
} },
2970 { "pmaxsw", { MX
, EM
} },
2971 { "pxor", { MX
, EM
} },
2973 { PREFIX_TABLE (PREFIX_0FF0
) },
2974 { "psllw", { MX
, EM
} },
2975 { "pslld", { MX
, EM
} },
2976 { "psllq", { MX
, EM
} },
2977 { "pmuludq", { MX
, EM
} },
2978 { "pmaddwd", { MX
, EM
} },
2979 { "psadbw", { MX
, EM
} },
2980 { PREFIX_TABLE (PREFIX_0FF7
) },
2982 { "psubb", { MX
, EM
} },
2983 { "psubw", { MX
, EM
} },
2984 { "psubd", { MX
, EM
} },
2985 { "psubq", { MX
, EM
} },
2986 { "paddb", { MX
, EM
} },
2987 { "paddw", { MX
, EM
} },
2988 { "paddd", { MX
, EM
} },
2992 static const unsigned char onebyte_has_modrm
[256] = {
2993 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2994 /* ------------------------------- */
2995 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2996 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2997 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2998 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2999 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3000 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3001 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3002 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3003 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3004 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3005 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3006 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3007 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3008 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3009 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3010 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3011 /* ------------------------------- */
3012 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3015 static const unsigned char twobyte_has_modrm
[256] = {
3016 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3017 /* ------------------------------- */
3018 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3019 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3020 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3021 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3022 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3023 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3024 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3025 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3026 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3027 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3028 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3029 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3030 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3031 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3032 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3033 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3034 /* ------------------------------- */
3035 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3038 static const unsigned char twobyte_has_mandatory_prefix
[256] = {
3039 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3040 /* ------------------------------- */
3041 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3042 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3043 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3044 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3045 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3046 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3047 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3048 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3049 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3050 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3051 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3052 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3053 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3054 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3055 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3056 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3057 /* ------------------------------- */
3058 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3061 static char obuf
[100];
3063 static char *mnemonicendp
;
3064 static char scratchbuf
[100];
3065 static unsigned char *start_codep
;
3066 static unsigned char *insn_codep
;
3067 static unsigned char *codep
;
3068 static unsigned char *end_codep
;
3069 static int last_lock_prefix
;
3070 static int last_repz_prefix
;
3071 static int last_repnz_prefix
;
3072 static int last_data_prefix
;
3073 static int last_addr_prefix
;
3074 static int last_rex_prefix
;
3075 static int last_seg_prefix
;
3076 static int fwait_prefix
;
3077 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3078 static int mandatory_prefix
;
3079 /* The active segment register prefix. */
3080 static int active_seg_prefix
;
3081 #define MAX_CODE_LENGTH 15
3082 /* We can up to 14 prefixes since the maximum instruction length is
3084 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3085 static disassemble_info
*the_info
;
3093 static unsigned char need_modrm
;
3103 int register_specifier
;
3110 int mask_register_specifier
;
3116 static unsigned char need_vex
;
3117 static unsigned char need_vex_reg
;
3118 static unsigned char vex_w_done
;
3126 /* If we are accessing mod/rm/reg without need_modrm set, then the
3127 values are stale. Hitting this abort likely indicates that you
3128 need to update onebyte_has_modrm or twobyte_has_modrm. */
3129 #define MODRM_CHECK if (!need_modrm) abort ()
3131 static const char **names64
;
3132 static const char **names32
;
3133 static const char **names16
;
3134 static const char **names8
;
3135 static const char **names8rex
;
3136 static const char **names_seg
;
3137 static const char *index64
;
3138 static const char *index32
;
3139 static const char **index16
;
3140 static const char **names_bnd
;
3142 static const char *intel_names64
[] = {
3143 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3146 static const char *intel_names32
[] = {
3147 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3148 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3150 static const char *intel_names16
[] = {
3151 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3152 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3154 static const char *intel_names8
[] = {
3155 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3157 static const char *intel_names8rex
[] = {
3158 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3159 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3161 static const char *intel_names_seg
[] = {
3162 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3164 static const char *intel_index64
= "riz";
3165 static const char *intel_index32
= "eiz";
3166 static const char *intel_index16
[] = {
3167 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3170 static const char *att_names64
[] = {
3171 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3172 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3174 static const char *att_names32
[] = {
3175 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3176 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3178 static const char *att_names16
[] = {
3179 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3180 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3182 static const char *att_names8
[] = {
3183 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3185 static const char *att_names8rex
[] = {
3186 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3187 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3189 static const char *att_names_seg
[] = {
3190 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3192 static const char *att_index64
= "%riz";
3193 static const char *att_index32
= "%eiz";
3194 static const char *att_index16
[] = {
3195 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3198 static const char **names_mm
;
3199 static const char *intel_names_mm
[] = {
3200 "mm0", "mm1", "mm2", "mm3",
3201 "mm4", "mm5", "mm6", "mm7"
3203 static const char *att_names_mm
[] = {
3204 "%mm0", "%mm1", "%mm2", "%mm3",
3205 "%mm4", "%mm5", "%mm6", "%mm7"
3208 static const char *intel_names_bnd
[] = {
3209 "bnd0", "bnd1", "bnd2", "bnd3"
3212 static const char *att_names_bnd
[] = {
3213 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3216 static const char **names_xmm
;
3217 static const char *intel_names_xmm
[] = {
3218 "xmm0", "xmm1", "xmm2", "xmm3",
3219 "xmm4", "xmm5", "xmm6", "xmm7",
3220 "xmm8", "xmm9", "xmm10", "xmm11",
3221 "xmm12", "xmm13", "xmm14", "xmm15",
3222 "xmm16", "xmm17", "xmm18", "xmm19",
3223 "xmm20", "xmm21", "xmm22", "xmm23",
3224 "xmm24", "xmm25", "xmm26", "xmm27",
3225 "xmm28", "xmm29", "xmm30", "xmm31"
3227 static const char *att_names_xmm
[] = {
3228 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3229 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3230 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3231 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3232 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3233 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3234 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3235 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3238 static const char **names_ymm
;
3239 static const char *intel_names_ymm
[] = {
3240 "ymm0", "ymm1", "ymm2", "ymm3",
3241 "ymm4", "ymm5", "ymm6", "ymm7",
3242 "ymm8", "ymm9", "ymm10", "ymm11",
3243 "ymm12", "ymm13", "ymm14", "ymm15",
3244 "ymm16", "ymm17", "ymm18", "ymm19",
3245 "ymm20", "ymm21", "ymm22", "ymm23",
3246 "ymm24", "ymm25", "ymm26", "ymm27",
3247 "ymm28", "ymm29", "ymm30", "ymm31"
3249 static const char *att_names_ymm
[] = {
3250 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3251 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3252 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3253 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3254 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3255 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3256 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3257 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3260 static const char **names_zmm
;
3261 static const char *intel_names_zmm
[] = {
3262 "zmm0", "zmm1", "zmm2", "zmm3",
3263 "zmm4", "zmm5", "zmm6", "zmm7",
3264 "zmm8", "zmm9", "zmm10", "zmm11",
3265 "zmm12", "zmm13", "zmm14", "zmm15",
3266 "zmm16", "zmm17", "zmm18", "zmm19",
3267 "zmm20", "zmm21", "zmm22", "zmm23",
3268 "zmm24", "zmm25", "zmm26", "zmm27",
3269 "zmm28", "zmm29", "zmm30", "zmm31"
3271 static const char *att_names_zmm
[] = {
3272 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3273 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3274 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3275 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3276 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3277 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3278 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3279 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3282 static const char **names_mask
;
3283 static const char *intel_names_mask
[] = {
3284 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3286 static const char *att_names_mask
[] = {
3287 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3290 static const char *names_rounding
[] =
3298 static const struct dis386 reg_table
[][8] = {
3301 { "addA", { Ebh1
, Ib
} },
3302 { "orA", { Ebh1
, Ib
} },
3303 { "adcA", { Ebh1
, Ib
} },
3304 { "sbbA", { Ebh1
, Ib
} },
3305 { "andA", { Ebh1
, Ib
} },
3306 { "subA", { Ebh1
, Ib
} },
3307 { "xorA", { Ebh1
, Ib
} },
3308 { "cmpA", { Eb
, Ib
} },
3312 { "addQ", { Evh1
, Iv
} },
3313 { "orQ", { Evh1
, Iv
} },
3314 { "adcQ", { Evh1
, Iv
} },
3315 { "sbbQ", { Evh1
, Iv
} },
3316 { "andQ", { Evh1
, Iv
} },
3317 { "subQ", { Evh1
, Iv
} },
3318 { "xorQ", { Evh1
, Iv
} },
3319 { "cmpQ", { Ev
, Iv
} },
3323 { "addQ", { Evh1
, sIb
} },
3324 { "orQ", { Evh1
, sIb
} },
3325 { "adcQ", { Evh1
, sIb
} },
3326 { "sbbQ", { Evh1
, sIb
} },
3327 { "andQ", { Evh1
, sIb
} },
3328 { "subQ", { Evh1
, sIb
} },
3329 { "xorQ", { Evh1
, sIb
} },
3330 { "cmpQ", { Ev
, sIb
} },
3334 { "popU", { stackEv
} },
3335 { XOP_8F_TABLE (XOP_09
) },
3339 { XOP_8F_TABLE (XOP_09
) },
3343 { "rolA", { Eb
, Ib
} },
3344 { "rorA", { Eb
, Ib
} },
3345 { "rclA", { Eb
, Ib
} },
3346 { "rcrA", { Eb
, Ib
} },
3347 { "shlA", { Eb
, Ib
} },
3348 { "shrA", { Eb
, Ib
} },
3350 { "sarA", { Eb
, Ib
} },
3354 { "rolQ", { Ev
, Ib
} },
3355 { "rorQ", { Ev
, Ib
} },
3356 { "rclQ", { Ev
, Ib
} },
3357 { "rcrQ", { Ev
, Ib
} },
3358 { "shlQ", { Ev
, Ib
} },
3359 { "shrQ", { Ev
, Ib
} },
3361 { "sarQ", { Ev
, Ib
} },
3365 { "movA", { Ebh3
, Ib
} },
3372 { MOD_TABLE (MOD_C6_REG_7
) },
3376 { "movQ", { Evh3
, Iv
} },
3383 { MOD_TABLE (MOD_C7_REG_7
) },
3387 { "rolA", { Eb
, I1
} },
3388 { "rorA", { Eb
, I1
} },
3389 { "rclA", { Eb
, I1
} },
3390 { "rcrA", { Eb
, I1
} },
3391 { "shlA", { Eb
, I1
} },
3392 { "shrA", { Eb
, I1
} },
3394 { "sarA", { Eb
, I1
} },
3398 { "rolQ", { Ev
, I1
} },
3399 { "rorQ", { Ev
, I1
} },
3400 { "rclQ", { Ev
, I1
} },
3401 { "rcrQ", { Ev
, I1
} },
3402 { "shlQ", { Ev
, I1
} },
3403 { "shrQ", { Ev
, I1
} },
3405 { "sarQ", { Ev
, I1
} },
3409 { "rolA", { Eb
, CL
} },
3410 { "rorA", { Eb
, CL
} },
3411 { "rclA", { Eb
, CL
} },
3412 { "rcrA", { Eb
, CL
} },
3413 { "shlA", { Eb
, CL
} },
3414 { "shrA", { Eb
, CL
} },
3416 { "sarA", { Eb
, CL
} },
3420 { "rolQ", { Ev
, CL
} },
3421 { "rorQ", { Ev
, CL
} },
3422 { "rclQ", { Ev
, CL
} },
3423 { "rcrQ", { Ev
, CL
} },
3424 { "shlQ", { Ev
, CL
} },
3425 { "shrQ", { Ev
, CL
} },
3427 { "sarQ", { Ev
, CL
} },
3431 { "testA", { Eb
, Ib
} },
3433 { "notA", { Ebh1
} },
3434 { "negA", { Ebh1
} },
3435 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3436 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3437 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3438 { "idivA", { Eb
} }, /* and idiv for consistency. */
3442 { "testQ", { Ev
, Iv
} },
3444 { "notQ", { Evh1
} },
3445 { "negQ", { Evh1
} },
3446 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3447 { "imulQ", { Ev
} },
3449 { "idivQ", { Ev
} },
3453 { "incA", { Ebh1
} },
3454 { "decA", { Ebh1
} },
3458 { "incQ", { Evh1
} },
3459 { "decQ", { Evh1
} },
3460 { "call{T|}", { indirEv
, BND
} },
3461 { MOD_TABLE (MOD_FF_REG_3
) },
3462 { "jmp{T|}", { indirEv
, BND
} },
3463 { MOD_TABLE (MOD_FF_REG_5
) },
3464 { "pushU", { stackEv
} },
3469 { "sldtD", { Sv
} },
3480 { MOD_TABLE (MOD_0F01_REG_0
) },
3481 { MOD_TABLE (MOD_0F01_REG_1
) },
3482 { MOD_TABLE (MOD_0F01_REG_2
) },
3483 { MOD_TABLE (MOD_0F01_REG_3
) },
3484 { "smswD", { Sv
} },
3487 { MOD_TABLE (MOD_0F01_REG_7
) },
3491 { "prefetch", { Mb
} },
3492 { "prefetchw", { Mb
} },
3493 { "prefetchwt1", { Mb
} },
3494 { "prefetch", { Mb
} },
3495 { "prefetch", { Mb
} },
3496 { "prefetch", { Mb
} },
3497 { "prefetch", { Mb
} },
3498 { "prefetch", { Mb
} },
3502 { MOD_TABLE (MOD_0F18_REG_0
) },
3503 { MOD_TABLE (MOD_0F18_REG_1
) },
3504 { MOD_TABLE (MOD_0F18_REG_2
) },
3505 { MOD_TABLE (MOD_0F18_REG_3
) },
3506 { MOD_TABLE (MOD_0F18_REG_4
) },
3507 { MOD_TABLE (MOD_0F18_REG_5
) },
3508 { MOD_TABLE (MOD_0F18_REG_6
) },
3509 { MOD_TABLE (MOD_0F18_REG_7
) },
3515 { MOD_TABLE (MOD_0F71_REG_2
) },
3517 { MOD_TABLE (MOD_0F71_REG_4
) },
3519 { MOD_TABLE (MOD_0F71_REG_6
) },
3525 { MOD_TABLE (MOD_0F72_REG_2
) },
3527 { MOD_TABLE (MOD_0F72_REG_4
) },
3529 { MOD_TABLE (MOD_0F72_REG_6
) },
3535 { MOD_TABLE (MOD_0F73_REG_2
) },
3536 { MOD_TABLE (MOD_0F73_REG_3
) },
3539 { MOD_TABLE (MOD_0F73_REG_6
) },
3540 { MOD_TABLE (MOD_0F73_REG_7
) },
3544 { "montmul", { { OP_0f07
, 0 } } },
3545 { "xsha1", { { OP_0f07
, 0 } } },
3546 { "xsha256", { { OP_0f07
, 0 } } },
3550 { "xstore-rng", { { OP_0f07
, 0 } } },
3551 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3552 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3553 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3554 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3555 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3559 { MOD_TABLE (MOD_0FAE_REG_0
) },
3560 { MOD_TABLE (MOD_0FAE_REG_1
) },
3561 { MOD_TABLE (MOD_0FAE_REG_2
) },
3562 { MOD_TABLE (MOD_0FAE_REG_3
) },
3563 { MOD_TABLE (MOD_0FAE_REG_4
) },
3564 { MOD_TABLE (MOD_0FAE_REG_5
) },
3565 { MOD_TABLE (MOD_0FAE_REG_6
) },
3566 { MOD_TABLE (MOD_0FAE_REG_7
) },
3574 { "btQ", { Ev
, Ib
} },
3575 { "btsQ", { Evh1
, Ib
} },
3576 { "btrQ", { Evh1
, Ib
} },
3577 { "btcQ", { Evh1
, Ib
} },
3582 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3584 { MOD_TABLE (MOD_0FC7_REG_3
) },
3585 { MOD_TABLE (MOD_0FC7_REG_4
) },
3586 { MOD_TABLE (MOD_0FC7_REG_5
) },
3587 { MOD_TABLE (MOD_0FC7_REG_6
) },
3588 { MOD_TABLE (MOD_0FC7_REG_7
) },
3594 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3596 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3598 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3604 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3606 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3608 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3614 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3615 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3618 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3619 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3625 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3626 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3628 /* REG_VEX_0F38F3 */
3631 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3632 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3633 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3637 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3638 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3642 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3643 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3645 /* REG_XOP_TBM_01 */
3648 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3649 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3650 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3651 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3652 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3653 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3654 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3656 /* REG_XOP_TBM_02 */
3659 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3664 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3666 #define NEED_REG_TABLE
3667 #include "i386-dis-evex.h"
3668 #undef NEED_REG_TABLE
3671 static const struct dis386 prefix_table
[][4] = {
3674 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3675 { "pause", { XX
} },
3676 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3681 { "movups", { XM
, EXx
} },
3682 { "movss", { XM
, EXd
} },
3683 { "movupd", { XM
, EXx
} },
3684 { "movsd", { XM
, EXq
} },
3689 { "movups", { EXxS
, XM
} },
3690 { "movss", { EXdS
, XM
} },
3691 { "movupd", { EXxS
, XM
} },
3692 { "movsd", { EXqS
, XM
} },
3697 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3698 { "movsldup", { XM
, EXx
} },
3699 { "movlpd", { XM
, EXq
} },
3700 { "movddup", { XM
, EXq
} },
3705 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3706 { "movshdup", { XM
, EXx
} },
3707 { "movhpd", { XM
, EXq
} },
3712 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3713 { "bndcl", { Gbnd
, Ev_bnd
} },
3714 { "bndmov", { Gbnd
, Ebnd
} },
3715 { "bndcu", { Gbnd
, Ev_bnd
} },
3720 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3721 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3722 { "bndmov", { Ebnd
, Gbnd
} },
3723 { "bndcn", { Gbnd
, Ev_bnd
} },
3728 { "cvtpi2ps", { XM
, EMCq
} },
3729 { "cvtsi2ss%LQ", { XM
, Ev
} },
3730 { "cvtpi2pd", { XM
, EMCq
} },
3731 { "cvtsi2sd%LQ", { XM
, Ev
} },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3744 { "cvttps2pi", { MXC
, EXq
} },
3745 { "cvttss2siY", { Gv
, EXd
} },
3746 { "cvttpd2pi", { MXC
, EXx
} },
3747 { "cvttsd2siY", { Gv
, EXq
} },
3752 { "cvtps2pi", { MXC
, EXq
} },
3753 { "cvtss2siY", { Gv
, EXd
} },
3754 { "cvtpd2pi", { MXC
, EXx
} },
3755 { "cvtsd2siY", { Gv
, EXq
} },
3760 { "ucomiss",{ XM
, EXd
} },
3762 { "ucomisd",{ XM
, EXq
} },
3767 { "comiss", { XM
, EXd
} },
3769 { "comisd", { XM
, EXq
} },
3774 { "sqrtps", { XM
, EXx
} },
3775 { "sqrtss", { XM
, EXd
} },
3776 { "sqrtpd", { XM
, EXx
} },
3777 { "sqrtsd", { XM
, EXq
} },
3782 { "rsqrtps",{ XM
, EXx
} },
3783 { "rsqrtss",{ XM
, EXd
} },
3788 { "rcpps", { XM
, EXx
} },
3789 { "rcpss", { XM
, EXd
} },
3794 { "addps", { XM
, EXx
} },
3795 { "addss", { XM
, EXd
} },
3796 { "addpd", { XM
, EXx
} },
3797 { "addsd", { XM
, EXq
} },
3802 { "mulps", { XM
, EXx
} },
3803 { "mulss", { XM
, EXd
} },
3804 { "mulpd", { XM
, EXx
} },
3805 { "mulsd", { XM
, EXq
} },
3810 { "cvtps2pd", { XM
, EXq
} },
3811 { "cvtss2sd", { XM
, EXd
} },
3812 { "cvtpd2ps", { XM
, EXx
} },
3813 { "cvtsd2ss", { XM
, EXq
} },
3818 { "cvtdq2ps", { XM
, EXx
} },
3819 { "cvttps2dq", { XM
, EXx
} },
3820 { "cvtps2dq", { XM
, EXx
} },
3825 { "subps", { XM
, EXx
} },
3826 { "subss", { XM
, EXd
} },
3827 { "subpd", { XM
, EXx
} },
3828 { "subsd", { XM
, EXq
} },
3833 { "minps", { XM
, EXx
} },
3834 { "minss", { XM
, EXd
} },
3835 { "minpd", { XM
, EXx
} },
3836 { "minsd", { XM
, EXq
} },
3841 { "divps", { XM
, EXx
} },
3842 { "divss", { XM
, EXd
} },
3843 { "divpd", { XM
, EXx
} },
3844 { "divsd", { XM
, EXq
} },
3849 { "maxps", { XM
, EXx
} },
3850 { "maxss", { XM
, EXd
} },
3851 { "maxpd", { XM
, EXx
} },
3852 { "maxsd", { XM
, EXq
} },
3857 { "punpcklbw",{ MX
, EMd
} },
3859 { "punpcklbw",{ MX
, EMx
} },
3864 { "punpcklwd",{ MX
, EMd
} },
3866 { "punpcklwd",{ MX
, EMx
} },
3871 { "punpckldq",{ MX
, EMd
} },
3873 { "punpckldq",{ MX
, EMx
} },
3880 { "punpcklqdq", { XM
, EXx
} },
3887 { "punpckhqdq", { XM
, EXx
} },
3892 { "movq", { MX
, EM
} },
3893 { "movdqu", { XM
, EXx
} },
3894 { "movdqa", { XM
, EXx
} },
3899 { "pshufw", { MX
, EM
, Ib
} },
3900 { "pshufhw",{ XM
, EXx
, Ib
} },
3901 { "pshufd", { XM
, EXx
, Ib
} },
3902 { "pshuflw",{ XM
, EXx
, Ib
} },
3905 /* PREFIX_0F73_REG_3 */
3909 { "psrldq", { XS
, Ib
} },
3912 /* PREFIX_0F73_REG_7 */
3916 { "pslldq", { XS
, Ib
} },
3921 {"vmread", { Em
, Gm
} },
3923 {"extrq", { XS
, Ib
, Ib
} },
3924 {"insertq", { XM
, XS
, Ib
, Ib
} },
3929 {"vmwrite", { Gm
, Em
} },
3931 {"extrq", { XM
, XS
} },
3932 {"insertq", { XM
, XS
} },
3939 { "haddpd", { XM
, EXx
} },
3940 { "haddps", { XM
, EXx
} },
3947 { "hsubpd", { XM
, EXx
} },
3948 { "hsubps", { XM
, EXx
} },
3953 { "movK", { Edq
, MX
} },
3954 { "movq", { XM
, EXq
} },
3955 { "movK", { Edq
, XM
} },
3960 { "movq", { EMS
, MX
} },
3961 { "movdqu", { EXxS
, XM
} },
3962 { "movdqa", { EXxS
, XM
} },
3965 /* PREFIX_0FAE_REG_0 */
3968 { "rdfsbase", { Ev
} },
3971 /* PREFIX_0FAE_REG_1 */
3974 { "rdgsbase", { Ev
} },
3977 /* PREFIX_0FAE_REG_2 */
3980 { "wrfsbase", { Ev
} },
3983 /* PREFIX_0FAE_REG_3 */
3986 { "wrgsbase", { Ev
} },
3989 /* PREFIX_0FAE_REG_6 */
3991 { "xsaveopt", { FXSAVE
} },
3996 /* PREFIX_0FAE_REG_7 */
3998 { "clflush", { Mb
} },
4000 { "clflushopt", { Mb
} },
4003 /* PREFIX_RM_0_0FAE_REG_7 */
4005 { "sfence", { Skip_MODRM
} },
4007 { "pcommit", { Skip_MODRM
} },
4013 { "popcntS", { Gv
, Ev
} },
4018 { "bsfS", { Gv
, Ev
} },
4019 { "tzcntS", { Gv
, Ev
} },
4020 { "bsfS", { Gv
, Ev
} },
4025 { "bsrS", { Gv
, Ev
} },
4026 { "lzcntS", { Gv
, Ev
} },
4027 { "bsrS", { Gv
, Ev
} },
4032 { "cmpps", { XM
, EXx
, CMP
} },
4033 { "cmpss", { XM
, EXd
, CMP
} },
4034 { "cmppd", { XM
, EXx
, CMP
} },
4035 { "cmpsd", { XM
, EXq
, CMP
} },
4040 { "movntiS", { Ma
, Gv
} },
4043 /* PREFIX_0FC7_REG_6 */
4045 { "vmptrld",{ Mq
} },
4046 { "vmxon", { Mq
} },
4047 { "vmclear",{ Mq
} },
4054 { "addsubpd", { XM
, EXx
} },
4055 { "addsubps", { XM
, EXx
} },
4061 { "movq2dq",{ XM
, MS
} },
4062 { "movq", { EXqS
, XM
} },
4063 { "movdq2q",{ MX
, XS
} },
4069 { "cvtdq2pd", { XM
, EXq
} },
4070 { "cvttpd2dq", { XM
, EXx
} },
4071 { "cvtpd2dq", { XM
, EXx
} },
4076 { "movntq", { Mq
, MX
} },
4078 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4086 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4091 { "maskmovq", { MX
, MS
} },
4093 { "maskmovdqu", { XM
, XS
} },
4100 { "pblendvb", { XM
, EXx
, XMM0
} },
4107 { "blendvps", { XM
, EXx
, XMM0
} },
4114 { "blendvpd", { XM
, EXx
, XMM0
} },
4121 { "ptest", { XM
, EXx
} },
4128 { "pmovsxbw", { XM
, EXq
} },
4135 { "pmovsxbd", { XM
, EXd
} },
4142 { "pmovsxbq", { XM
, EXw
} },
4149 { "pmovsxwd", { XM
, EXq
} },
4156 { "pmovsxwq", { XM
, EXd
} },
4163 { "pmovsxdq", { XM
, EXq
} },
4170 { "pmuldq", { XM
, EXx
} },
4177 { "pcmpeqq", { XM
, EXx
} },
4184 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4191 { "packusdw", { XM
, EXx
} },
4198 { "pmovzxbw", { XM
, EXq
} },
4205 { "pmovzxbd", { XM
, EXd
} },
4212 { "pmovzxbq", { XM
, EXw
} },
4219 { "pmovzxwd", { XM
, EXq
} },
4226 { "pmovzxwq", { XM
, EXd
} },
4233 { "pmovzxdq", { XM
, EXq
} },
4240 { "pcmpgtq", { XM
, EXx
} },
4247 { "pminsb", { XM
, EXx
} },
4254 { "pminsd", { XM
, EXx
} },
4261 { "pminuw", { XM
, EXx
} },
4268 { "pminud", { XM
, EXx
} },
4275 { "pmaxsb", { XM
, EXx
} },
4282 { "pmaxsd", { XM
, EXx
} },
4289 { "pmaxuw", { XM
, EXx
} },
4296 { "pmaxud", { XM
, EXx
} },
4303 { "pmulld", { XM
, EXx
} },
4310 { "phminposuw", { XM
, EXx
} },
4317 { "invept", { Gm
, Mo
} },
4324 { "invvpid", { Gm
, Mo
} },
4331 { "invpcid", { Gm
, M
} },
4336 { "sha1nexte", { XM
, EXxmm
} },
4341 { "sha1msg1", { XM
, EXxmm
} },
4346 { "sha1msg2", { XM
, EXxmm
} },
4351 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4356 { "sha256msg1", { XM
, EXxmm
} },
4361 { "sha256msg2", { XM
, EXxmm
} },
4368 { "aesimc", { XM
, EXx
} },
4375 { "aesenc", { XM
, EXx
} },
4382 { "aesenclast", { XM
, EXx
} },
4389 { "aesdec", { XM
, EXx
} },
4396 { "aesdeclast", { XM
, EXx
} },
4401 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4403 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4404 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4409 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4411 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4412 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4418 { "adoxS", { Gdq
, Edq
} },
4419 { "adcxS", { Gdq
, Edq
} },
4427 { "roundps", { XM
, EXx
, Ib
} },
4434 { "roundpd", { XM
, EXx
, Ib
} },
4441 { "roundss", { XM
, EXd
, Ib
} },
4448 { "roundsd", { XM
, EXq
, Ib
} },
4455 { "blendps", { XM
, EXx
, Ib
} },
4462 { "blendpd", { XM
, EXx
, Ib
} },
4469 { "pblendw", { XM
, EXx
, Ib
} },
4476 { "pextrb", { Edqb
, XM
, Ib
} },
4483 { "pextrw", { Edqw
, XM
, Ib
} },
4490 { "pextrK", { Edq
, XM
, Ib
} },
4497 { "extractps", { Edqd
, XM
, Ib
} },
4504 { "pinsrb", { XM
, Edqb
, Ib
} },
4511 { "insertps", { XM
, EXd
, Ib
} },
4518 { "pinsrK", { XM
, Edq
, Ib
} },
4525 { "dpps", { XM
, EXx
, Ib
} },
4532 { "dppd", { XM
, EXx
, Ib
} },
4539 { "mpsadbw", { XM
, EXx
, Ib
} },
4546 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4553 { "pcmpestrm", { XM
, EXx
, Ib
} },
4560 { "pcmpestri", { XM
, EXx
, Ib
} },
4567 { "pcmpistrm", { XM
, EXx
, Ib
} },
4574 { "pcmpistri", { XM
, EXx
, Ib
} },
4579 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4586 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4589 /* PREFIX_VEX_0F10 */
4591 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4592 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4593 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4594 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4597 /* PREFIX_VEX_0F11 */
4599 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4600 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4601 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4602 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4605 /* PREFIX_VEX_0F12 */
4607 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4608 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4609 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4610 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4613 /* PREFIX_VEX_0F16 */
4615 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4616 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4617 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4620 /* PREFIX_VEX_0F2A */
4623 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4625 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4628 /* PREFIX_VEX_0F2C */
4631 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4633 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4636 /* PREFIX_VEX_0F2D */
4639 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4641 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4644 /* PREFIX_VEX_0F2E */
4646 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4648 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4651 /* PREFIX_VEX_0F2F */
4653 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4655 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4658 /* PREFIX_VEX_0F41 */
4660 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4662 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4665 /* PREFIX_VEX_0F42 */
4667 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4669 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4672 /* PREFIX_VEX_0F44 */
4674 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4676 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4679 /* PREFIX_VEX_0F45 */
4681 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4686 /* PREFIX_VEX_0F46 */
4688 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4690 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4693 /* PREFIX_VEX_0F47 */
4695 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4697 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4700 /* PREFIX_VEX_0F4A */
4702 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4704 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4707 /* PREFIX_VEX_0F4B */
4709 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4711 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4714 /* PREFIX_VEX_0F51 */
4716 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4718 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4722 /* PREFIX_VEX_0F52 */
4724 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4728 /* PREFIX_VEX_0F53 */
4730 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4731 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4734 /* PREFIX_VEX_0F58 */
4736 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4737 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4738 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4742 /* PREFIX_VEX_0F59 */
4744 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4745 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4746 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4750 /* PREFIX_VEX_0F5A */
4752 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4753 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4754 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4755 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4758 /* PREFIX_VEX_0F5B */
4760 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4761 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4762 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4765 /* PREFIX_VEX_0F5C */
4767 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4768 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4769 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4773 /* PREFIX_VEX_0F5D */
4775 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4777 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4781 /* PREFIX_VEX_0F5E */
4783 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4785 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4789 /* PREFIX_VEX_0F5F */
4791 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4793 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4794 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4797 /* PREFIX_VEX_0F60 */
4801 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4804 /* PREFIX_VEX_0F61 */
4808 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4811 /* PREFIX_VEX_0F62 */
4815 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4818 /* PREFIX_VEX_0F63 */
4822 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4825 /* PREFIX_VEX_0F64 */
4829 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4832 /* PREFIX_VEX_0F65 */
4836 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4839 /* PREFIX_VEX_0F66 */
4843 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4846 /* PREFIX_VEX_0F67 */
4850 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4853 /* PREFIX_VEX_0F68 */
4857 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4860 /* PREFIX_VEX_0F69 */
4864 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4867 /* PREFIX_VEX_0F6A */
4871 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4874 /* PREFIX_VEX_0F6B */
4878 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4881 /* PREFIX_VEX_0F6C */
4885 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4888 /* PREFIX_VEX_0F6D */
4892 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4895 /* PREFIX_VEX_0F6E */
4899 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4902 /* PREFIX_VEX_0F6F */
4905 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4906 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4909 /* PREFIX_VEX_0F70 */
4912 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4913 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4914 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4917 /* PREFIX_VEX_0F71_REG_2 */
4921 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4924 /* PREFIX_VEX_0F71_REG_4 */
4928 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4931 /* PREFIX_VEX_0F71_REG_6 */
4935 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4938 /* PREFIX_VEX_0F72_REG_2 */
4942 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4945 /* PREFIX_VEX_0F72_REG_4 */
4949 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4952 /* PREFIX_VEX_0F72_REG_6 */
4956 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4959 /* PREFIX_VEX_0F73_REG_2 */
4963 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4966 /* PREFIX_VEX_0F73_REG_3 */
4970 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4973 /* PREFIX_VEX_0F73_REG_6 */
4977 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4980 /* PREFIX_VEX_0F73_REG_7 */
4984 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4987 /* PREFIX_VEX_0F74 */
4991 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4994 /* PREFIX_VEX_0F75 */
4998 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5001 /* PREFIX_VEX_0F76 */
5005 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5008 /* PREFIX_VEX_0F77 */
5010 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5013 /* PREFIX_VEX_0F7C */
5017 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5018 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5021 /* PREFIX_VEX_0F7D */
5025 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5026 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5029 /* PREFIX_VEX_0F7E */
5032 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5033 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5036 /* PREFIX_VEX_0F7F */
5039 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5040 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5043 /* PREFIX_VEX_0F90 */
5045 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5047 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5050 /* PREFIX_VEX_0F91 */
5052 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5054 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5057 /* PREFIX_VEX_0F92 */
5059 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5061 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5062 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5065 /* PREFIX_VEX_0F93 */
5067 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5070 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5073 /* PREFIX_VEX_0F98 */
5075 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5080 /* PREFIX_VEX_0F99 */
5082 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5084 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5087 /* PREFIX_VEX_0FC2 */
5089 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5090 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5091 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5092 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5095 /* PREFIX_VEX_0FC4 */
5099 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5102 /* PREFIX_VEX_0FC5 */
5106 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5109 /* PREFIX_VEX_0FD0 */
5113 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5114 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5117 /* PREFIX_VEX_0FD1 */
5121 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5124 /* PREFIX_VEX_0FD2 */
5128 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5131 /* PREFIX_VEX_0FD3 */
5135 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5138 /* PREFIX_VEX_0FD4 */
5142 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5145 /* PREFIX_VEX_0FD5 */
5149 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5152 /* PREFIX_VEX_0FD6 */
5156 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5159 /* PREFIX_VEX_0FD7 */
5163 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5166 /* PREFIX_VEX_0FD8 */
5170 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5173 /* PREFIX_VEX_0FD9 */
5177 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5180 /* PREFIX_VEX_0FDA */
5184 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5187 /* PREFIX_VEX_0FDB */
5191 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5194 /* PREFIX_VEX_0FDC */
5198 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5201 /* PREFIX_VEX_0FDD */
5205 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5208 /* PREFIX_VEX_0FDE */
5212 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5215 /* PREFIX_VEX_0FDF */
5219 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5222 /* PREFIX_VEX_0FE0 */
5226 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5229 /* PREFIX_VEX_0FE1 */
5233 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5236 /* PREFIX_VEX_0FE2 */
5240 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5243 /* PREFIX_VEX_0FE3 */
5247 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5250 /* PREFIX_VEX_0FE4 */
5254 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5257 /* PREFIX_VEX_0FE5 */
5261 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5264 /* PREFIX_VEX_0FE6 */
5267 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5268 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5269 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5272 /* PREFIX_VEX_0FE7 */
5276 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5279 /* PREFIX_VEX_0FE8 */
5283 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5286 /* PREFIX_VEX_0FE9 */
5290 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5293 /* PREFIX_VEX_0FEA */
5297 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5300 /* PREFIX_VEX_0FEB */
5304 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5307 /* PREFIX_VEX_0FEC */
5311 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5314 /* PREFIX_VEX_0FED */
5318 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5321 /* PREFIX_VEX_0FEE */
5325 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5328 /* PREFIX_VEX_0FEF */
5332 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5335 /* PREFIX_VEX_0FF0 */
5340 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5343 /* PREFIX_VEX_0FF1 */
5347 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5350 /* PREFIX_VEX_0FF2 */
5354 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5357 /* PREFIX_VEX_0FF3 */
5361 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5364 /* PREFIX_VEX_0FF4 */
5368 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5371 /* PREFIX_VEX_0FF5 */
5375 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5378 /* PREFIX_VEX_0FF6 */
5382 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5385 /* PREFIX_VEX_0FF7 */
5389 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5392 /* PREFIX_VEX_0FF8 */
5396 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5399 /* PREFIX_VEX_0FF9 */
5403 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5406 /* PREFIX_VEX_0FFA */
5410 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5413 /* PREFIX_VEX_0FFB */
5417 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5420 /* PREFIX_VEX_0FFC */
5424 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5427 /* PREFIX_VEX_0FFD */
5431 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5434 /* PREFIX_VEX_0FFE */
5438 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5441 /* PREFIX_VEX_0F3800 */
5445 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5448 /* PREFIX_VEX_0F3801 */
5452 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5455 /* PREFIX_VEX_0F3802 */
5459 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5462 /* PREFIX_VEX_0F3803 */
5466 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5469 /* PREFIX_VEX_0F3804 */
5473 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5476 /* PREFIX_VEX_0F3805 */
5480 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5483 /* PREFIX_VEX_0F3806 */
5487 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5490 /* PREFIX_VEX_0F3807 */
5494 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5497 /* PREFIX_VEX_0F3808 */
5501 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5504 /* PREFIX_VEX_0F3809 */
5508 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5511 /* PREFIX_VEX_0F380A */
5515 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5518 /* PREFIX_VEX_0F380B */
5522 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5525 /* PREFIX_VEX_0F380C */
5529 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5532 /* PREFIX_VEX_0F380D */
5536 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5539 /* PREFIX_VEX_0F380E */
5543 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5546 /* PREFIX_VEX_0F380F */
5550 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5553 /* PREFIX_VEX_0F3813 */
5557 { "vcvtph2ps", { XM
, EXxmmq
} },
5560 /* PREFIX_VEX_0F3816 */
5564 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5567 /* PREFIX_VEX_0F3817 */
5571 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5574 /* PREFIX_VEX_0F3818 */
5578 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5581 /* PREFIX_VEX_0F3819 */
5585 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5588 /* PREFIX_VEX_0F381A */
5592 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5595 /* PREFIX_VEX_0F381C */
5599 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5602 /* PREFIX_VEX_0F381D */
5606 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5609 /* PREFIX_VEX_0F381E */
5613 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5616 /* PREFIX_VEX_0F3820 */
5620 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5623 /* PREFIX_VEX_0F3821 */
5627 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5630 /* PREFIX_VEX_0F3822 */
5634 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5637 /* PREFIX_VEX_0F3823 */
5641 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5644 /* PREFIX_VEX_0F3824 */
5648 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5651 /* PREFIX_VEX_0F3825 */
5655 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5658 /* PREFIX_VEX_0F3828 */
5662 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5665 /* PREFIX_VEX_0F3829 */
5669 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5672 /* PREFIX_VEX_0F382A */
5676 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5679 /* PREFIX_VEX_0F382B */
5683 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5686 /* PREFIX_VEX_0F382C */
5690 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5693 /* PREFIX_VEX_0F382D */
5697 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5700 /* PREFIX_VEX_0F382E */
5704 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5707 /* PREFIX_VEX_0F382F */
5711 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5714 /* PREFIX_VEX_0F3830 */
5718 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5721 /* PREFIX_VEX_0F3831 */
5725 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5728 /* PREFIX_VEX_0F3832 */
5732 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5735 /* PREFIX_VEX_0F3833 */
5739 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5742 /* PREFIX_VEX_0F3834 */
5746 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5749 /* PREFIX_VEX_0F3835 */
5753 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5756 /* PREFIX_VEX_0F3836 */
5760 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5763 /* PREFIX_VEX_0F3837 */
5767 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5770 /* PREFIX_VEX_0F3838 */
5774 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5777 /* PREFIX_VEX_0F3839 */
5781 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5784 /* PREFIX_VEX_0F383A */
5788 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5791 /* PREFIX_VEX_0F383B */
5795 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5798 /* PREFIX_VEX_0F383C */
5802 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5805 /* PREFIX_VEX_0F383D */
5809 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5812 /* PREFIX_VEX_0F383E */
5816 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5819 /* PREFIX_VEX_0F383F */
5823 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5826 /* PREFIX_VEX_0F3840 */
5830 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5833 /* PREFIX_VEX_0F3841 */
5837 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5840 /* PREFIX_VEX_0F3845 */
5844 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5847 /* PREFIX_VEX_0F3846 */
5851 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5854 /* PREFIX_VEX_0F3847 */
5858 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5861 /* PREFIX_VEX_0F3858 */
5865 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5868 /* PREFIX_VEX_0F3859 */
5872 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5875 /* PREFIX_VEX_0F385A */
5879 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5882 /* PREFIX_VEX_0F3878 */
5886 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5889 /* PREFIX_VEX_0F3879 */
5893 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5896 /* PREFIX_VEX_0F388C */
5900 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5903 /* PREFIX_VEX_0F388E */
5907 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5910 /* PREFIX_VEX_0F3890 */
5914 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5917 /* PREFIX_VEX_0F3891 */
5921 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5924 /* PREFIX_VEX_0F3892 */
5928 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5931 /* PREFIX_VEX_0F3893 */
5935 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5938 /* PREFIX_VEX_0F3896 */
5942 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5945 /* PREFIX_VEX_0F3897 */
5949 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5952 /* PREFIX_VEX_0F3898 */
5956 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5959 /* PREFIX_VEX_0F3899 */
5963 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5966 /* PREFIX_VEX_0F389A */
5970 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5973 /* PREFIX_VEX_0F389B */
5977 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5980 /* PREFIX_VEX_0F389C */
5984 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5987 /* PREFIX_VEX_0F389D */
5991 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5994 /* PREFIX_VEX_0F389E */
5998 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
6001 /* PREFIX_VEX_0F389F */
6005 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6008 /* PREFIX_VEX_0F38A6 */
6012 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
6016 /* PREFIX_VEX_0F38A7 */
6020 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
6023 /* PREFIX_VEX_0F38A8 */
6027 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
6030 /* PREFIX_VEX_0F38A9 */
6034 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6037 /* PREFIX_VEX_0F38AA */
6041 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
6044 /* PREFIX_VEX_0F38AB */
6048 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6051 /* PREFIX_VEX_0F38AC */
6055 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
6058 /* PREFIX_VEX_0F38AD */
6062 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6065 /* PREFIX_VEX_0F38AE */
6069 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
6072 /* PREFIX_VEX_0F38AF */
6076 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6079 /* PREFIX_VEX_0F38B6 */
6083 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
6086 /* PREFIX_VEX_0F38B7 */
6090 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
6093 /* PREFIX_VEX_0F38B8 */
6097 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
6100 /* PREFIX_VEX_0F38B9 */
6104 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6107 /* PREFIX_VEX_0F38BA */
6111 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
6114 /* PREFIX_VEX_0F38BB */
6118 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6121 /* PREFIX_VEX_0F38BC */
6125 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
6128 /* PREFIX_VEX_0F38BD */
6132 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6135 /* PREFIX_VEX_0F38BE */
6139 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
6142 /* PREFIX_VEX_0F38BF */
6146 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6149 /* PREFIX_VEX_0F38DB */
6153 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6156 /* PREFIX_VEX_0F38DC */
6160 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6163 /* PREFIX_VEX_0F38DD */
6167 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6170 /* PREFIX_VEX_0F38DE */
6174 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6177 /* PREFIX_VEX_0F38DF */
6181 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6184 /* PREFIX_VEX_0F38F2 */
6186 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6189 /* PREFIX_VEX_0F38F3_REG_1 */
6191 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6194 /* PREFIX_VEX_0F38F3_REG_2 */
6196 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6199 /* PREFIX_VEX_0F38F3_REG_3 */
6201 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6204 /* PREFIX_VEX_0F38F5 */
6206 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6207 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6209 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6212 /* PREFIX_VEX_0F38F6 */
6217 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6220 /* PREFIX_VEX_0F38F7 */
6222 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6223 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6225 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6228 /* PREFIX_VEX_0F3A00 */
6232 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6235 /* PREFIX_VEX_0F3A01 */
6239 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6242 /* PREFIX_VEX_0F3A02 */
6246 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6249 /* PREFIX_VEX_0F3A04 */
6253 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6256 /* PREFIX_VEX_0F3A05 */
6260 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6263 /* PREFIX_VEX_0F3A06 */
6267 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6270 /* PREFIX_VEX_0F3A08 */
6274 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6277 /* PREFIX_VEX_0F3A09 */
6281 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6284 /* PREFIX_VEX_0F3A0A */
6288 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6291 /* PREFIX_VEX_0F3A0B */
6295 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6298 /* PREFIX_VEX_0F3A0C */
6302 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6305 /* PREFIX_VEX_0F3A0D */
6309 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6312 /* PREFIX_VEX_0F3A0E */
6316 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6319 /* PREFIX_VEX_0F3A0F */
6323 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6326 /* PREFIX_VEX_0F3A14 */
6330 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6333 /* PREFIX_VEX_0F3A15 */
6337 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6340 /* PREFIX_VEX_0F3A16 */
6344 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6347 /* PREFIX_VEX_0F3A17 */
6351 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6354 /* PREFIX_VEX_0F3A18 */
6358 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6361 /* PREFIX_VEX_0F3A19 */
6365 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6368 /* PREFIX_VEX_0F3A1D */
6372 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6375 /* PREFIX_VEX_0F3A20 */
6379 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6382 /* PREFIX_VEX_0F3A21 */
6386 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6389 /* PREFIX_VEX_0F3A22 */
6393 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6396 /* PREFIX_VEX_0F3A30 */
6400 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6403 /* PREFIX_VEX_0F3A31 */
6407 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6410 /* PREFIX_VEX_0F3A32 */
6414 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6417 /* PREFIX_VEX_0F3A33 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6424 /* PREFIX_VEX_0F3A38 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6431 /* PREFIX_VEX_0F3A39 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6438 /* PREFIX_VEX_0F3A40 */
6442 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6445 /* PREFIX_VEX_0F3A41 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6452 /* PREFIX_VEX_0F3A42 */
6456 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6459 /* PREFIX_VEX_0F3A44 */
6463 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6466 /* PREFIX_VEX_0F3A46 */
6470 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6473 /* PREFIX_VEX_0F3A48 */
6477 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6480 /* PREFIX_VEX_0F3A49 */
6484 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6487 /* PREFIX_VEX_0F3A4A */
6491 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6494 /* PREFIX_VEX_0F3A4B */
6498 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6501 /* PREFIX_VEX_0F3A4C */
6505 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6508 /* PREFIX_VEX_0F3A5C */
6512 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6515 /* PREFIX_VEX_0F3A5D */
6519 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6522 /* PREFIX_VEX_0F3A5E */
6526 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6529 /* PREFIX_VEX_0F3A5F */
6533 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6536 /* PREFIX_VEX_0F3A60 */
6540 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6544 /* PREFIX_VEX_0F3A61 */
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6551 /* PREFIX_VEX_0F3A62 */
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6558 /* PREFIX_VEX_0F3A63 */
6562 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6565 /* PREFIX_VEX_0F3A68 */
6569 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6572 /* PREFIX_VEX_0F3A69 */
6576 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6579 /* PREFIX_VEX_0F3A6A */
6583 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6586 /* PREFIX_VEX_0F3A6B */
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6593 /* PREFIX_VEX_0F3A6C */
6597 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6600 /* PREFIX_VEX_0F3A6D */
6604 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6607 /* PREFIX_VEX_0F3A6E */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6614 /* PREFIX_VEX_0F3A6F */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6621 /* PREFIX_VEX_0F3A78 */
6625 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6628 /* PREFIX_VEX_0F3A79 */
6632 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6635 /* PREFIX_VEX_0F3A7A */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6642 /* PREFIX_VEX_0F3A7B */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6649 /* PREFIX_VEX_0F3A7C */
6653 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6657 /* PREFIX_VEX_0F3A7D */
6661 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6664 /* PREFIX_VEX_0F3A7E */
6668 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6671 /* PREFIX_VEX_0F3A7F */
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6678 /* PREFIX_VEX_0F3ADF */
6682 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6685 /* PREFIX_VEX_0F3AF0 */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6693 #define NEED_PREFIX_TABLE
6694 #include "i386-dis-evex.h"
6695 #undef NEED_PREFIX_TABLE
6698 static const struct dis386 x86_64_table
[][2] = {
6701 { "pushP", { es
} },
6711 { "pushP", { cs
} },
6716 { "pushP", { ss
} },
6726 { "pushP", { ds
} },
6756 { "pushaP", { XX
} },
6761 { "popaP", { XX
} },
6766 { MOD_TABLE (MOD_62_32BIT
) },
6767 { EVEX_TABLE (EVEX_0F
) },
6772 { "arpl", { Ew
, Gw
} },
6773 { "movs{lq|xd}", { Gv
, Ed
} },
6778 { "ins{R|}", { Yzr
, indirDX
} },
6779 { "ins{G|}", { Yzr
, indirDX
} },
6784 { "outs{R|}", { indirDXr
, Xz
} },
6785 { "outs{G|}", { indirDXr
, Xz
} },
6790 { "Jcall{T|}", { Ap
} },
6795 { MOD_TABLE (MOD_C4_32BIT
) },
6796 { VEX_C4_TABLE (VEX_0F
) },
6801 { MOD_TABLE (MOD_C5_32BIT
) },
6802 { VEX_C5_TABLE (VEX_0F
) },
6822 { "Jjmp{T|}", { Ap
} },
6825 /* X86_64_0F01_REG_0 */
6827 { "sgdt{Q|IQ}", { M
} },
6831 /* X86_64_0F01_REG_1 */
6833 { "sidt{Q|IQ}", { M
} },
6837 /* X86_64_0F01_REG_2 */
6839 { "lgdt{Q|Q}", { M
} },
6843 /* X86_64_0F01_REG_3 */
6845 { "lidt{Q|Q}", { M
} },
6850 static const struct dis386 three_byte_table
[][256] = {
6852 /* THREE_BYTE_0F38 */
6855 { "pshufb", { MX
, EM
} },
6856 { "phaddw", { MX
, EM
} },
6857 { "phaddd", { MX
, EM
} },
6858 { "phaddsw", { MX
, EM
} },
6859 { "pmaddubsw", { MX
, EM
} },
6860 { "phsubw", { MX
, EM
} },
6861 { "phsubd", { MX
, EM
} },
6862 { "phsubsw", { MX
, EM
} },
6864 { "psignb", { MX
, EM
} },
6865 { "psignw", { MX
, EM
} },
6866 { "psignd", { MX
, EM
} },
6867 { "pmulhrsw", { MX
, EM
} },
6873 { PREFIX_TABLE (PREFIX_0F3810
) },
6877 { PREFIX_TABLE (PREFIX_0F3814
) },
6878 { PREFIX_TABLE (PREFIX_0F3815
) },
6880 { PREFIX_TABLE (PREFIX_0F3817
) },
6886 { "pabsb", { MX
, EM
} },
6887 { "pabsw", { MX
, EM
} },
6888 { "pabsd", { MX
, EM
} },
6891 { PREFIX_TABLE (PREFIX_0F3820
) },
6892 { PREFIX_TABLE (PREFIX_0F3821
) },
6893 { PREFIX_TABLE (PREFIX_0F3822
) },
6894 { PREFIX_TABLE (PREFIX_0F3823
) },
6895 { PREFIX_TABLE (PREFIX_0F3824
) },
6896 { PREFIX_TABLE (PREFIX_0F3825
) },
6900 { PREFIX_TABLE (PREFIX_0F3828
) },
6901 { PREFIX_TABLE (PREFIX_0F3829
) },
6902 { PREFIX_TABLE (PREFIX_0F382A
) },
6903 { PREFIX_TABLE (PREFIX_0F382B
) },
6909 { PREFIX_TABLE (PREFIX_0F3830
) },
6910 { PREFIX_TABLE (PREFIX_0F3831
) },
6911 { PREFIX_TABLE (PREFIX_0F3832
) },
6912 { PREFIX_TABLE (PREFIX_0F3833
) },
6913 { PREFIX_TABLE (PREFIX_0F3834
) },
6914 { PREFIX_TABLE (PREFIX_0F3835
) },
6916 { PREFIX_TABLE (PREFIX_0F3837
) },
6918 { PREFIX_TABLE (PREFIX_0F3838
) },
6919 { PREFIX_TABLE (PREFIX_0F3839
) },
6920 { PREFIX_TABLE (PREFIX_0F383A
) },
6921 { PREFIX_TABLE (PREFIX_0F383B
) },
6922 { PREFIX_TABLE (PREFIX_0F383C
) },
6923 { PREFIX_TABLE (PREFIX_0F383D
) },
6924 { PREFIX_TABLE (PREFIX_0F383E
) },
6925 { PREFIX_TABLE (PREFIX_0F383F
) },
6927 { PREFIX_TABLE (PREFIX_0F3840
) },
6928 { PREFIX_TABLE (PREFIX_0F3841
) },
6999 { PREFIX_TABLE (PREFIX_0F3880
) },
7000 { PREFIX_TABLE (PREFIX_0F3881
) },
7001 { PREFIX_TABLE (PREFIX_0F3882
) },
7080 { PREFIX_TABLE (PREFIX_0F38C8
) },
7081 { PREFIX_TABLE (PREFIX_0F38C9
) },
7082 { PREFIX_TABLE (PREFIX_0F38CA
) },
7083 { PREFIX_TABLE (PREFIX_0F38CB
) },
7084 { PREFIX_TABLE (PREFIX_0F38CC
) },
7085 { PREFIX_TABLE (PREFIX_0F38CD
) },
7101 { PREFIX_TABLE (PREFIX_0F38DB
) },
7102 { PREFIX_TABLE (PREFIX_0F38DC
) },
7103 { PREFIX_TABLE (PREFIX_0F38DD
) },
7104 { PREFIX_TABLE (PREFIX_0F38DE
) },
7105 { PREFIX_TABLE (PREFIX_0F38DF
) },
7125 { PREFIX_TABLE (PREFIX_0F38F0
) },
7126 { PREFIX_TABLE (PREFIX_0F38F1
) },
7131 { PREFIX_TABLE (PREFIX_0F38F6
) },
7143 /* THREE_BYTE_0F3A */
7155 { PREFIX_TABLE (PREFIX_0F3A08
) },
7156 { PREFIX_TABLE (PREFIX_0F3A09
) },
7157 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7158 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7159 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7160 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7161 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7162 { "palignr", { MX
, EM
, Ib
} },
7168 { PREFIX_TABLE (PREFIX_0F3A14
) },
7169 { PREFIX_TABLE (PREFIX_0F3A15
) },
7170 { PREFIX_TABLE (PREFIX_0F3A16
) },
7171 { PREFIX_TABLE (PREFIX_0F3A17
) },
7182 { PREFIX_TABLE (PREFIX_0F3A20
) },
7183 { PREFIX_TABLE (PREFIX_0F3A21
) },
7184 { PREFIX_TABLE (PREFIX_0F3A22
) },
7218 { PREFIX_TABLE (PREFIX_0F3A40
) },
7219 { PREFIX_TABLE (PREFIX_0F3A41
) },
7220 { PREFIX_TABLE (PREFIX_0F3A42
) },
7222 { PREFIX_TABLE (PREFIX_0F3A44
) },
7254 { PREFIX_TABLE (PREFIX_0F3A60
) },
7255 { PREFIX_TABLE (PREFIX_0F3A61
) },
7256 { PREFIX_TABLE (PREFIX_0F3A62
) },
7257 { PREFIX_TABLE (PREFIX_0F3A63
) },
7375 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7396 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7435 /* THREE_BYTE_0F7A */
7474 { "ptest", { XX
} },
7511 { "phaddbw", { XM
, EXq
} },
7512 { "phaddbd", { XM
, EXq
} },
7513 { "phaddbq", { XM
, EXq
} },
7516 { "phaddwd", { XM
, EXq
} },
7517 { "phaddwq", { XM
, EXq
} },
7522 { "phadddq", { XM
, EXq
} },
7529 { "phaddubw", { XM
, EXq
} },
7530 { "phaddubd", { XM
, EXq
} },
7531 { "phaddubq", { XM
, EXq
} },
7534 { "phadduwd", { XM
, EXq
} },
7535 { "phadduwq", { XM
, EXq
} },
7540 { "phaddudq", { XM
, EXq
} },
7547 { "phsubbw", { XM
, EXq
} },
7548 { "phsubbd", { XM
, EXq
} },
7549 { "phsubbq", { XM
, EXq
} },
7728 static const struct dis386 xop_table
[][256] = {
7881 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7882 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7883 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7891 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7892 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7899 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7900 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7901 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7909 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7910 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7914 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7915 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7918 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7936 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7948 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7949 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7950 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7951 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7961 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7963 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7964 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8024 { REG_TABLE (REG_XOP_TBM_01
) },
8025 { REG_TABLE (REG_XOP_TBM_02
) },
8043 { REG_TABLE (REG_XOP_LWPCB
) },
8167 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8168 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8169 { "vfrczss", { XM
, EXd
} },
8170 { "vfrczsd", { XM
, EXq
} },
8185 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8186 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8187 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
8188 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8189 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8190 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8191 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
8192 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8194 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
8195 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8196 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
8197 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8240 { "vphaddbw", { XM
, EXxmm
} },
8241 { "vphaddbd", { XM
, EXxmm
} },
8242 { "vphaddbq", { XM
, EXxmm
} },
8245 { "vphaddwd", { XM
, EXxmm
} },
8246 { "vphaddwq", { XM
, EXxmm
} },
8251 { "vphadddq", { XM
, EXxmm
} },
8258 { "vphaddubw", { XM
, EXxmm
} },
8259 { "vphaddubd", { XM
, EXxmm
} },
8260 { "vphaddubq", { XM
, EXxmm
} },
8263 { "vphadduwd", { XM
, EXxmm
} },
8264 { "vphadduwq", { XM
, EXxmm
} },
8269 { "vphaddudq", { XM
, EXxmm
} },
8276 { "vphsubbw", { XM
, EXxmm
} },
8277 { "vphsubwd", { XM
, EXxmm
} },
8278 { "vphsubdq", { XM
, EXxmm
} },
8332 { "bextr", { Gv
, Ev
, Iq
} },
8334 { REG_TABLE (REG_XOP_LWP
) },
8604 static const struct dis386 vex_table
[][256] = {
8626 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8629 { MOD_TABLE (MOD_VEX_0F13
) },
8630 { VEX_W_TABLE (VEX_W_0F14
) },
8631 { VEX_W_TABLE (VEX_W_0F15
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8633 { MOD_TABLE (MOD_VEX_0F17
) },
8653 { VEX_W_TABLE (VEX_W_0F28
) },
8654 { VEX_W_TABLE (VEX_W_0F29
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8656 { MOD_TABLE (MOD_VEX_0F2B
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8698 { MOD_TABLE (MOD_VEX_0F50
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8702 { "vandpX", { XM
, Vex
, EXx
} },
8703 { "vandnpX", { XM
, Vex
, EXx
} },
8704 { "vorpX", { XM
, Vex
, EXx
} },
8705 { "vxorpX", { XM
, Vex
, EXx
} },
8707 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8735 { REG_TABLE (REG_VEX_0F71
) },
8736 { REG_TABLE (REG_VEX_0F72
) },
8737 { REG_TABLE (REG_VEX_0F73
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8803 { REG_TABLE (REG_VEX_0FAE
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8830 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8842 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9172 { REG_TABLE (REG_VEX_0F38F3
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9263 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9440 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9460 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9480 #define NEED_OPCODE_TABLE
9481 #include "i386-dis-evex.h"
9482 #undef NEED_OPCODE_TABLE
9483 static const struct dis386 vex_len_table
[][2] = {
9484 /* VEX_LEN_0F10_P_1 */
9486 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9487 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9490 /* VEX_LEN_0F10_P_3 */
9492 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9493 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9496 /* VEX_LEN_0F11_P_1 */
9498 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9499 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9502 /* VEX_LEN_0F11_P_3 */
9504 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9505 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9508 /* VEX_LEN_0F12_P_0_M_0 */
9510 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9513 /* VEX_LEN_0F12_P_0_M_1 */
9515 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9518 /* VEX_LEN_0F12_P_2 */
9520 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9523 /* VEX_LEN_0F13_M_0 */
9525 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9528 /* VEX_LEN_0F16_P_0_M_0 */
9530 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9533 /* VEX_LEN_0F16_P_0_M_1 */
9535 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9538 /* VEX_LEN_0F16_P_2 */
9540 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9543 /* VEX_LEN_0F17_M_0 */
9545 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9548 /* VEX_LEN_0F2A_P_1 */
9550 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9551 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9554 /* VEX_LEN_0F2A_P_3 */
9556 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9557 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9560 /* VEX_LEN_0F2C_P_1 */
9562 { "vcvttss2siY", { Gv
, EXdScalar
} },
9563 { "vcvttss2siY", { Gv
, EXdScalar
} },
9566 /* VEX_LEN_0F2C_P_3 */
9568 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9569 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9572 /* VEX_LEN_0F2D_P_1 */
9574 { "vcvtss2siY", { Gv
, EXdScalar
} },
9575 { "vcvtss2siY", { Gv
, EXdScalar
} },
9578 /* VEX_LEN_0F2D_P_3 */
9580 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9581 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9584 /* VEX_LEN_0F2E_P_0 */
9586 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9587 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9590 /* VEX_LEN_0F2E_P_2 */
9592 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9593 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9596 /* VEX_LEN_0F2F_P_0 */
9598 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9599 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9602 /* VEX_LEN_0F2F_P_2 */
9604 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9605 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9608 /* VEX_LEN_0F41_P_0 */
9611 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9613 /* VEX_LEN_0F41_P_2 */
9616 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9618 /* VEX_LEN_0F42_P_0 */
9621 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9623 /* VEX_LEN_0F42_P_2 */
9626 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9628 /* VEX_LEN_0F44_P_0 */
9630 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9632 /* VEX_LEN_0F44_P_2 */
9634 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9636 /* VEX_LEN_0F45_P_0 */
9639 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9641 /* VEX_LEN_0F45_P_2 */
9644 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9646 /* VEX_LEN_0F46_P_0 */
9649 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9651 /* VEX_LEN_0F46_P_2 */
9654 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9656 /* VEX_LEN_0F47_P_0 */
9659 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9661 /* VEX_LEN_0F47_P_2 */
9664 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9666 /* VEX_LEN_0F4A_P_0 */
9669 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9671 /* VEX_LEN_0F4A_P_2 */
9674 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9676 /* VEX_LEN_0F4B_P_0 */
9679 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9681 /* VEX_LEN_0F4B_P_2 */
9684 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9687 /* VEX_LEN_0F51_P_1 */
9689 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9690 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9693 /* VEX_LEN_0F51_P_3 */
9695 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9696 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9699 /* VEX_LEN_0F52_P_1 */
9701 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9702 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9705 /* VEX_LEN_0F53_P_1 */
9707 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9708 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9711 /* VEX_LEN_0F58_P_1 */
9713 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9714 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9717 /* VEX_LEN_0F58_P_3 */
9719 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9720 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9723 /* VEX_LEN_0F59_P_1 */
9725 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9726 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9729 /* VEX_LEN_0F59_P_3 */
9731 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9732 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9735 /* VEX_LEN_0F5A_P_1 */
9737 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9738 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9741 /* VEX_LEN_0F5A_P_3 */
9743 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9744 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9747 /* VEX_LEN_0F5C_P_1 */
9749 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9750 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9753 /* VEX_LEN_0F5C_P_3 */
9755 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9756 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9759 /* VEX_LEN_0F5D_P_1 */
9761 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9762 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9765 /* VEX_LEN_0F5D_P_3 */
9767 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9768 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9771 /* VEX_LEN_0F5E_P_1 */
9773 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9774 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9777 /* VEX_LEN_0F5E_P_3 */
9779 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9780 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9783 /* VEX_LEN_0F5F_P_1 */
9785 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9786 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9789 /* VEX_LEN_0F5F_P_3 */
9791 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9792 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9795 /* VEX_LEN_0F6E_P_2 */
9797 { "vmovK", { XMScalar
, Edq
} },
9798 { "vmovK", { XMScalar
, Edq
} },
9801 /* VEX_LEN_0F7E_P_1 */
9803 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9804 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9807 /* VEX_LEN_0F7E_P_2 */
9809 { "vmovK", { Edq
, XMScalar
} },
9810 { "vmovK", { Edq
, XMScalar
} },
9813 /* VEX_LEN_0F90_P_0 */
9815 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9818 /* VEX_LEN_0F90_P_2 */
9820 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9823 /* VEX_LEN_0F91_P_0 */
9825 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9828 /* VEX_LEN_0F91_P_2 */
9830 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9833 /* VEX_LEN_0F92_P_0 */
9835 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9838 /* VEX_LEN_0F92_P_2 */
9840 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9843 /* VEX_LEN_0F92_P_3 */
9845 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9848 /* VEX_LEN_0F93_P_0 */
9850 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9853 /* VEX_LEN_0F93_P_2 */
9855 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9858 /* VEX_LEN_0F93_P_3 */
9860 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9863 /* VEX_LEN_0F98_P_0 */
9865 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9868 /* VEX_LEN_0F98_P_2 */
9870 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9873 /* VEX_LEN_0F99_P_0 */
9875 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9878 /* VEX_LEN_0F99_P_2 */
9880 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9883 /* VEX_LEN_0FAE_R_2_M_0 */
9885 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9888 /* VEX_LEN_0FAE_R_3_M_0 */
9890 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9893 /* VEX_LEN_0FC2_P_1 */
9895 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9896 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9899 /* VEX_LEN_0FC2_P_3 */
9901 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9902 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9905 /* VEX_LEN_0FC4_P_2 */
9907 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9910 /* VEX_LEN_0FC5_P_2 */
9912 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9915 /* VEX_LEN_0FD6_P_2 */
9917 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9918 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9921 /* VEX_LEN_0FF7_P_2 */
9923 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9926 /* VEX_LEN_0F3816_P_2 */
9929 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9932 /* VEX_LEN_0F3819_P_2 */
9935 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9938 /* VEX_LEN_0F381A_P_2_M_0 */
9941 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9944 /* VEX_LEN_0F3836_P_2 */
9947 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9950 /* VEX_LEN_0F3841_P_2 */
9952 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9955 /* VEX_LEN_0F385A_P_2_M_0 */
9958 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9961 /* VEX_LEN_0F38DB_P_2 */
9963 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9966 /* VEX_LEN_0F38DC_P_2 */
9968 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9971 /* VEX_LEN_0F38DD_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9976 /* VEX_LEN_0F38DE_P_2 */
9978 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9981 /* VEX_LEN_0F38DF_P_2 */
9983 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9986 /* VEX_LEN_0F38F2_P_0 */
9988 { "andnS", { Gdq
, VexGdq
, Edq
} },
9991 /* VEX_LEN_0F38F3_R_1_P_0 */
9993 { "blsrS", { VexGdq
, Edq
} },
9996 /* VEX_LEN_0F38F3_R_2_P_0 */
9998 { "blsmskS", { VexGdq
, Edq
} },
10001 /* VEX_LEN_0F38F3_R_3_P_0 */
10003 { "blsiS", { VexGdq
, Edq
} },
10006 /* VEX_LEN_0F38F5_P_0 */
10008 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
10011 /* VEX_LEN_0F38F5_P_1 */
10013 { "pextS", { Gdq
, VexGdq
, Edq
} },
10016 /* VEX_LEN_0F38F5_P_3 */
10018 { "pdepS", { Gdq
, VexGdq
, Edq
} },
10021 /* VEX_LEN_0F38F6_P_3 */
10023 { "mulxS", { Gdq
, VexGdq
, Edq
} },
10026 /* VEX_LEN_0F38F7_P_0 */
10028 { "bextrS", { Gdq
, Edq
, VexGdq
} },
10031 /* VEX_LEN_0F38F7_P_1 */
10033 { "sarxS", { Gdq
, Edq
, VexGdq
} },
10036 /* VEX_LEN_0F38F7_P_2 */
10038 { "shlxS", { Gdq
, Edq
, VexGdq
} },
10041 /* VEX_LEN_0F38F7_P_3 */
10043 { "shrxS", { Gdq
, Edq
, VexGdq
} },
10046 /* VEX_LEN_0F3A00_P_2 */
10049 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10052 /* VEX_LEN_0F3A01_P_2 */
10055 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10058 /* VEX_LEN_0F3A06_P_2 */
10061 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10064 /* VEX_LEN_0F3A0A_P_2 */
10066 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10067 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10070 /* VEX_LEN_0F3A0B_P_2 */
10072 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10073 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10076 /* VEX_LEN_0F3A14_P_2 */
10078 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10081 /* VEX_LEN_0F3A15_P_2 */
10083 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10086 /* VEX_LEN_0F3A16_P_2 */
10088 { "vpextrK", { Edq
, XM
, Ib
} },
10091 /* VEX_LEN_0F3A17_P_2 */
10093 { "vextractps", { Edqd
, XM
, Ib
} },
10096 /* VEX_LEN_0F3A18_P_2 */
10099 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10102 /* VEX_LEN_0F3A19_P_2 */
10105 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10108 /* VEX_LEN_0F3A20_P_2 */
10110 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10113 /* VEX_LEN_0F3A21_P_2 */
10115 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10118 /* VEX_LEN_0F3A22_P_2 */
10120 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
10123 /* VEX_LEN_0F3A30_P_2 */
10125 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10128 /* VEX_LEN_0F3A31_P_2 */
10130 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10133 /* VEX_LEN_0F3A32_P_2 */
10135 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10138 /* VEX_LEN_0F3A33_P_2 */
10140 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10143 /* VEX_LEN_0F3A38_P_2 */
10146 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10149 /* VEX_LEN_0F3A39_P_2 */
10152 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10155 /* VEX_LEN_0F3A41_P_2 */
10157 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10160 /* VEX_LEN_0F3A44_P_2 */
10162 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10165 /* VEX_LEN_0F3A46_P_2 */
10168 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10171 /* VEX_LEN_0F3A60_P_2 */
10173 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10176 /* VEX_LEN_0F3A61_P_2 */
10178 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10181 /* VEX_LEN_0F3A62_P_2 */
10183 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10186 /* VEX_LEN_0F3A63_P_2 */
10188 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10191 /* VEX_LEN_0F3A6A_P_2 */
10193 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10196 /* VEX_LEN_0F3A6B_P_2 */
10198 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10201 /* VEX_LEN_0F3A6E_P_2 */
10203 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10206 /* VEX_LEN_0F3A6F_P_2 */
10208 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10211 /* VEX_LEN_0F3A7A_P_2 */
10213 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10216 /* VEX_LEN_0F3A7B_P_2 */
10218 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10221 /* VEX_LEN_0F3A7E_P_2 */
10223 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10226 /* VEX_LEN_0F3A7F_P_2 */
10228 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10231 /* VEX_LEN_0F3ADF_P_2 */
10233 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10236 /* VEX_LEN_0F3AF0_P_3 */
10238 { "rorxS", { Gdq
, Edq
, Ib
} },
10241 /* VEX_LEN_0FXOP_08_CC */
10243 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
10246 /* VEX_LEN_0FXOP_08_CD */
10248 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
10251 /* VEX_LEN_0FXOP_08_CE */
10253 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
10256 /* VEX_LEN_0FXOP_08_CF */
10258 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
10261 /* VEX_LEN_0FXOP_08_EC */
10263 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
10266 /* VEX_LEN_0FXOP_08_ED */
10268 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
10271 /* VEX_LEN_0FXOP_08_EE */
10273 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
10276 /* VEX_LEN_0FXOP_08_EF */
10278 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
10281 /* VEX_LEN_0FXOP_09_80 */
10283 { "vfrczps", { XM
, EXxmm
} },
10284 { "vfrczps", { XM
, EXymmq
} },
10287 /* VEX_LEN_0FXOP_09_81 */
10289 { "vfrczpd", { XM
, EXxmm
} },
10290 { "vfrczpd", { XM
, EXymmq
} },
10294 static const struct dis386 vex_w_table
[][2] = {
10296 /* VEX_W_0F10_P_0 */
10297 { "vmovups", { XM
, EXx
} },
10300 /* VEX_W_0F10_P_1 */
10301 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
10304 /* VEX_W_0F10_P_2 */
10305 { "vmovupd", { XM
, EXx
} },
10308 /* VEX_W_0F10_P_3 */
10309 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
10312 /* VEX_W_0F11_P_0 */
10313 { "vmovups", { EXxS
, XM
} },
10316 /* VEX_W_0F11_P_1 */
10317 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
10320 /* VEX_W_0F11_P_2 */
10321 { "vmovupd", { EXxS
, XM
} },
10324 /* VEX_W_0F11_P_3 */
10325 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
10328 /* VEX_W_0F12_P_0_M_0 */
10329 { "vmovlps", { XM
, Vex128
, EXq
} },
10332 /* VEX_W_0F12_P_0_M_1 */
10333 { "vmovhlps", { XM
, Vex128
, EXq
} },
10336 /* VEX_W_0F12_P_1 */
10337 { "vmovsldup", { XM
, EXx
} },
10340 /* VEX_W_0F12_P_2 */
10341 { "vmovlpd", { XM
, Vex128
, EXq
} },
10344 /* VEX_W_0F12_P_3 */
10345 { "vmovddup", { XM
, EXymmq
} },
10348 /* VEX_W_0F13_M_0 */
10349 { "vmovlpX", { EXq
, XM
} },
10353 { "vunpcklpX", { XM
, Vex
, EXx
} },
10357 { "vunpckhpX", { XM
, Vex
, EXx
} },
10360 /* VEX_W_0F16_P_0_M_0 */
10361 { "vmovhps", { XM
, Vex128
, EXq
} },
10364 /* VEX_W_0F16_P_0_M_1 */
10365 { "vmovlhps", { XM
, Vex128
, EXq
} },
10368 /* VEX_W_0F16_P_1 */
10369 { "vmovshdup", { XM
, EXx
} },
10372 /* VEX_W_0F16_P_2 */
10373 { "vmovhpd", { XM
, Vex128
, EXq
} },
10376 /* VEX_W_0F17_M_0 */
10377 { "vmovhpX", { EXq
, XM
} },
10381 { "vmovapX", { XM
, EXx
} },
10385 { "vmovapX", { EXxS
, XM
} },
10388 /* VEX_W_0F2B_M_0 */
10389 { "vmovntpX", { Mx
, XM
} },
10392 /* VEX_W_0F2E_P_0 */
10393 { "vucomiss", { XMScalar
, EXdScalar
} },
10396 /* VEX_W_0F2E_P_2 */
10397 { "vucomisd", { XMScalar
, EXqScalar
} },
10400 /* VEX_W_0F2F_P_0 */
10401 { "vcomiss", { XMScalar
, EXdScalar
} },
10404 /* VEX_W_0F2F_P_2 */
10405 { "vcomisd", { XMScalar
, EXqScalar
} },
10408 /* VEX_W_0F41_P_0_LEN_1 */
10409 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10410 { "kandq", { MaskG
, MaskVex
, MaskR
} },
10413 /* VEX_W_0F41_P_2_LEN_1 */
10414 { "kandb", { MaskG
, MaskVex
, MaskR
} },
10415 { "kandd", { MaskG
, MaskVex
, MaskR
} },
10418 /* VEX_W_0F42_P_0_LEN_1 */
10419 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10420 { "kandnq", { MaskG
, MaskVex
, MaskR
} },
10423 /* VEX_W_0F42_P_2_LEN_1 */
10424 { "kandnb", { MaskG
, MaskVex
, MaskR
} },
10425 { "kandnd", { MaskG
, MaskVex
, MaskR
} },
10428 /* VEX_W_0F44_P_0_LEN_0 */
10429 { "knotw", { MaskG
, MaskR
} },
10430 { "knotq", { MaskG
, MaskR
} },
10433 /* VEX_W_0F44_P_2_LEN_0 */
10434 { "knotb", { MaskG
, MaskR
} },
10435 { "knotd", { MaskG
, MaskR
} },
10438 /* VEX_W_0F45_P_0_LEN_1 */
10439 { "korw", { MaskG
, MaskVex
, MaskR
} },
10440 { "korq", { MaskG
, MaskVex
, MaskR
} },
10443 /* VEX_W_0F45_P_2_LEN_1 */
10444 { "korb", { MaskG
, MaskVex
, MaskR
} },
10445 { "kord", { MaskG
, MaskVex
, MaskR
} },
10448 /* VEX_W_0F46_P_0_LEN_1 */
10449 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10450 { "kxnorq", { MaskG
, MaskVex
, MaskR
} },
10453 /* VEX_W_0F46_P_2_LEN_1 */
10454 { "kxnorb", { MaskG
, MaskVex
, MaskR
} },
10455 { "kxnord", { MaskG
, MaskVex
, MaskR
} },
10458 /* VEX_W_0F47_P_0_LEN_1 */
10459 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10460 { "kxorq", { MaskG
, MaskVex
, MaskR
} },
10463 /* VEX_W_0F47_P_2_LEN_1 */
10464 { "kxorb", { MaskG
, MaskVex
, MaskR
} },
10465 { "kxord", { MaskG
, MaskVex
, MaskR
} },
10468 /* VEX_W_0F4A_P_0_LEN_1 */
10469 { "kaddw", { MaskG
, MaskVex
, MaskR
} },
10470 { "kaddq", { MaskG
, MaskVex
, MaskR
} },
10473 /* VEX_W_0F4A_P_2_LEN_1 */
10474 { "kaddb", { MaskG
, MaskVex
, MaskR
} },
10475 { "kaddd", { MaskG
, MaskVex
, MaskR
} },
10478 /* VEX_W_0F4B_P_0_LEN_1 */
10479 { "kunpckwd", { MaskG
, MaskVex
, MaskR
} },
10480 { "kunpckdq", { MaskG
, MaskVex
, MaskR
} },
10483 /* VEX_W_0F4B_P_2_LEN_1 */
10484 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10487 /* VEX_W_0F50_M_0 */
10488 { "vmovmskpX", { Gdq
, XS
} },
10491 /* VEX_W_0F51_P_0 */
10492 { "vsqrtps", { XM
, EXx
} },
10495 /* VEX_W_0F51_P_1 */
10496 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10499 /* VEX_W_0F51_P_2 */
10500 { "vsqrtpd", { XM
, EXx
} },
10503 /* VEX_W_0F51_P_3 */
10504 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10507 /* VEX_W_0F52_P_0 */
10508 { "vrsqrtps", { XM
, EXx
} },
10511 /* VEX_W_0F52_P_1 */
10512 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10515 /* VEX_W_0F53_P_0 */
10516 { "vrcpps", { XM
, EXx
} },
10519 /* VEX_W_0F53_P_1 */
10520 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10523 /* VEX_W_0F58_P_0 */
10524 { "vaddps", { XM
, Vex
, EXx
} },
10527 /* VEX_W_0F58_P_1 */
10528 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10531 /* VEX_W_0F58_P_2 */
10532 { "vaddpd", { XM
, Vex
, EXx
} },
10535 /* VEX_W_0F58_P_3 */
10536 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10539 /* VEX_W_0F59_P_0 */
10540 { "vmulps", { XM
, Vex
, EXx
} },
10543 /* VEX_W_0F59_P_1 */
10544 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10547 /* VEX_W_0F59_P_2 */
10548 { "vmulpd", { XM
, Vex
, EXx
} },
10551 /* VEX_W_0F59_P_3 */
10552 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10555 /* VEX_W_0F5A_P_0 */
10556 { "vcvtps2pd", { XM
, EXxmmq
} },
10559 /* VEX_W_0F5A_P_1 */
10560 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10563 /* VEX_W_0F5A_P_3 */
10564 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10567 /* VEX_W_0F5B_P_0 */
10568 { "vcvtdq2ps", { XM
, EXx
} },
10571 /* VEX_W_0F5B_P_1 */
10572 { "vcvttps2dq", { XM
, EXx
} },
10575 /* VEX_W_0F5B_P_2 */
10576 { "vcvtps2dq", { XM
, EXx
} },
10579 /* VEX_W_0F5C_P_0 */
10580 { "vsubps", { XM
, Vex
, EXx
} },
10583 /* VEX_W_0F5C_P_1 */
10584 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10587 /* VEX_W_0F5C_P_2 */
10588 { "vsubpd", { XM
, Vex
, EXx
} },
10591 /* VEX_W_0F5C_P_3 */
10592 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10595 /* VEX_W_0F5D_P_0 */
10596 { "vminps", { XM
, Vex
, EXx
} },
10599 /* VEX_W_0F5D_P_1 */
10600 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10603 /* VEX_W_0F5D_P_2 */
10604 { "vminpd", { XM
, Vex
, EXx
} },
10607 /* VEX_W_0F5D_P_3 */
10608 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10611 /* VEX_W_0F5E_P_0 */
10612 { "vdivps", { XM
, Vex
, EXx
} },
10615 /* VEX_W_0F5E_P_1 */
10616 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10619 /* VEX_W_0F5E_P_2 */
10620 { "vdivpd", { XM
, Vex
, EXx
} },
10623 /* VEX_W_0F5E_P_3 */
10624 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10627 /* VEX_W_0F5F_P_0 */
10628 { "vmaxps", { XM
, Vex
, EXx
} },
10631 /* VEX_W_0F5F_P_1 */
10632 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10635 /* VEX_W_0F5F_P_2 */
10636 { "vmaxpd", { XM
, Vex
, EXx
} },
10639 /* VEX_W_0F5F_P_3 */
10640 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10643 /* VEX_W_0F60_P_2 */
10644 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10647 /* VEX_W_0F61_P_2 */
10648 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10651 /* VEX_W_0F62_P_2 */
10652 { "vpunpckldq", { XM
, Vex
, EXx
} },
10655 /* VEX_W_0F63_P_2 */
10656 { "vpacksswb", { XM
, Vex
, EXx
} },
10659 /* VEX_W_0F64_P_2 */
10660 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10663 /* VEX_W_0F65_P_2 */
10664 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10667 /* VEX_W_0F66_P_2 */
10668 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10671 /* VEX_W_0F67_P_2 */
10672 { "vpackuswb", { XM
, Vex
, EXx
} },
10675 /* VEX_W_0F68_P_2 */
10676 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10679 /* VEX_W_0F69_P_2 */
10680 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10683 /* VEX_W_0F6A_P_2 */
10684 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10687 /* VEX_W_0F6B_P_2 */
10688 { "vpackssdw", { XM
, Vex
, EXx
} },
10691 /* VEX_W_0F6C_P_2 */
10692 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10695 /* VEX_W_0F6D_P_2 */
10696 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10699 /* VEX_W_0F6F_P_1 */
10700 { "vmovdqu", { XM
, EXx
} },
10703 /* VEX_W_0F6F_P_2 */
10704 { "vmovdqa", { XM
, EXx
} },
10707 /* VEX_W_0F70_P_1 */
10708 { "vpshufhw", { XM
, EXx
, Ib
} },
10711 /* VEX_W_0F70_P_2 */
10712 { "vpshufd", { XM
, EXx
, Ib
} },
10715 /* VEX_W_0F70_P_3 */
10716 { "vpshuflw", { XM
, EXx
, Ib
} },
10719 /* VEX_W_0F71_R_2_P_2 */
10720 { "vpsrlw", { Vex
, XS
, Ib
} },
10723 /* VEX_W_0F71_R_4_P_2 */
10724 { "vpsraw", { Vex
, XS
, Ib
} },
10727 /* VEX_W_0F71_R_6_P_2 */
10728 { "vpsllw", { Vex
, XS
, Ib
} },
10731 /* VEX_W_0F72_R_2_P_2 */
10732 { "vpsrld", { Vex
, XS
, Ib
} },
10735 /* VEX_W_0F72_R_4_P_2 */
10736 { "vpsrad", { Vex
, XS
, Ib
} },
10739 /* VEX_W_0F72_R_6_P_2 */
10740 { "vpslld", { Vex
, XS
, Ib
} },
10743 /* VEX_W_0F73_R_2_P_2 */
10744 { "vpsrlq", { Vex
, XS
, Ib
} },
10747 /* VEX_W_0F73_R_3_P_2 */
10748 { "vpsrldq", { Vex
, XS
, Ib
} },
10751 /* VEX_W_0F73_R_6_P_2 */
10752 { "vpsllq", { Vex
, XS
, Ib
} },
10755 /* VEX_W_0F73_R_7_P_2 */
10756 { "vpslldq", { Vex
, XS
, Ib
} },
10759 /* VEX_W_0F74_P_2 */
10760 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10763 /* VEX_W_0F75_P_2 */
10764 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10767 /* VEX_W_0F76_P_2 */
10768 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10771 /* VEX_W_0F77_P_0 */
10775 /* VEX_W_0F7C_P_2 */
10776 { "vhaddpd", { XM
, Vex
, EXx
} },
10779 /* VEX_W_0F7C_P_3 */
10780 { "vhaddps", { XM
, Vex
, EXx
} },
10783 /* VEX_W_0F7D_P_2 */
10784 { "vhsubpd", { XM
, Vex
, EXx
} },
10787 /* VEX_W_0F7D_P_3 */
10788 { "vhsubps", { XM
, Vex
, EXx
} },
10791 /* VEX_W_0F7E_P_1 */
10792 { "vmovq", { XMScalar
, EXqScalar
} },
10795 /* VEX_W_0F7F_P_1 */
10796 { "vmovdqu", { EXxS
, XM
} },
10799 /* VEX_W_0F7F_P_2 */
10800 { "vmovdqa", { EXxS
, XM
} },
10803 /* VEX_W_0F90_P_0_LEN_0 */
10804 { "kmovw", { MaskG
, MaskE
} },
10805 { "kmovq", { MaskG
, MaskE
} },
10808 /* VEX_W_0F90_P_2_LEN_0 */
10809 { "kmovb", { MaskG
, MaskBDE
} },
10810 { "kmovd", { MaskG
, MaskBDE
} },
10813 /* VEX_W_0F91_P_0_LEN_0 */
10814 { "kmovw", { Ew
, MaskG
} },
10815 { "kmovq", { Eq
, MaskG
} },
10818 /* VEX_W_0F91_P_2_LEN_0 */
10819 { "kmovb", { Eb
, MaskG
} },
10820 { "kmovd", { Ed
, MaskG
} },
10823 /* VEX_W_0F92_P_0_LEN_0 */
10824 { "kmovw", { MaskG
, Rdq
} },
10827 /* VEX_W_0F92_P_2_LEN_0 */
10828 { "kmovb", { MaskG
, Rdq
} },
10831 /* VEX_W_0F92_P_3_LEN_0 */
10832 { "kmovd", { MaskG
, Rdq
} },
10833 { "kmovq", { MaskG
, Rdq
} },
10836 /* VEX_W_0F93_P_0_LEN_0 */
10837 { "kmovw", { Gdq
, MaskR
} },
10840 /* VEX_W_0F93_P_2_LEN_0 */
10841 { "kmovb", { Gdq
, MaskR
} },
10844 /* VEX_W_0F93_P_3_LEN_0 */
10845 { "kmovd", { Gdq
, MaskR
} },
10846 { "kmovq", { Gdq
, MaskR
} },
10849 /* VEX_W_0F98_P_0_LEN_0 */
10850 { "kortestw", { MaskG
, MaskR
} },
10851 { "kortestq", { MaskG
, MaskR
} },
10854 /* VEX_W_0F98_P_2_LEN_0 */
10855 { "kortestb", { MaskG
, MaskR
} },
10856 { "kortestd", { MaskG
, MaskR
} },
10859 /* VEX_W_0F99_P_0_LEN_0 */
10860 { "ktestw", { MaskG
, MaskR
} },
10861 { "ktestq", { MaskG
, MaskR
} },
10864 /* VEX_W_0F99_P_2_LEN_0 */
10865 { "ktestb", { MaskG
, MaskR
} },
10866 { "ktestd", { MaskG
, MaskR
} },
10869 /* VEX_W_0FAE_R_2_M_0 */
10870 { "vldmxcsr", { Md
} },
10873 /* VEX_W_0FAE_R_3_M_0 */
10874 { "vstmxcsr", { Md
} },
10877 /* VEX_W_0FC2_P_0 */
10878 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10881 /* VEX_W_0FC2_P_1 */
10882 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10885 /* VEX_W_0FC2_P_2 */
10886 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10889 /* VEX_W_0FC2_P_3 */
10890 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10893 /* VEX_W_0FC4_P_2 */
10894 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10897 /* VEX_W_0FC5_P_2 */
10898 { "vpextrw", { Gdq
, XS
, Ib
} },
10901 /* VEX_W_0FD0_P_2 */
10902 { "vaddsubpd", { XM
, Vex
, EXx
} },
10905 /* VEX_W_0FD0_P_3 */
10906 { "vaddsubps", { XM
, Vex
, EXx
} },
10909 /* VEX_W_0FD1_P_2 */
10910 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10913 /* VEX_W_0FD2_P_2 */
10914 { "vpsrld", { XM
, Vex
, EXxmm
} },
10917 /* VEX_W_0FD3_P_2 */
10918 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10921 /* VEX_W_0FD4_P_2 */
10922 { "vpaddq", { XM
, Vex
, EXx
} },
10925 /* VEX_W_0FD5_P_2 */
10926 { "vpmullw", { XM
, Vex
, EXx
} },
10929 /* VEX_W_0FD6_P_2 */
10930 { "vmovq", { EXqScalarS
, XMScalar
} },
10933 /* VEX_W_0FD7_P_2_M_1 */
10934 { "vpmovmskb", { Gdq
, XS
} },
10937 /* VEX_W_0FD8_P_2 */
10938 { "vpsubusb", { XM
, Vex
, EXx
} },
10941 /* VEX_W_0FD9_P_2 */
10942 { "vpsubusw", { XM
, Vex
, EXx
} },
10945 /* VEX_W_0FDA_P_2 */
10946 { "vpminub", { XM
, Vex
, EXx
} },
10949 /* VEX_W_0FDB_P_2 */
10950 { "vpand", { XM
, Vex
, EXx
} },
10953 /* VEX_W_0FDC_P_2 */
10954 { "vpaddusb", { XM
, Vex
, EXx
} },
10957 /* VEX_W_0FDD_P_2 */
10958 { "vpaddusw", { XM
, Vex
, EXx
} },
10961 /* VEX_W_0FDE_P_2 */
10962 { "vpmaxub", { XM
, Vex
, EXx
} },
10965 /* VEX_W_0FDF_P_2 */
10966 { "vpandn", { XM
, Vex
, EXx
} },
10969 /* VEX_W_0FE0_P_2 */
10970 { "vpavgb", { XM
, Vex
, EXx
} },
10973 /* VEX_W_0FE1_P_2 */
10974 { "vpsraw", { XM
, Vex
, EXxmm
} },
10977 /* VEX_W_0FE2_P_2 */
10978 { "vpsrad", { XM
, Vex
, EXxmm
} },
10981 /* VEX_W_0FE3_P_2 */
10982 { "vpavgw", { XM
, Vex
, EXx
} },
10985 /* VEX_W_0FE4_P_2 */
10986 { "vpmulhuw", { XM
, Vex
, EXx
} },
10989 /* VEX_W_0FE5_P_2 */
10990 { "vpmulhw", { XM
, Vex
, EXx
} },
10993 /* VEX_W_0FE6_P_1 */
10994 { "vcvtdq2pd", { XM
, EXxmmq
} },
10997 /* VEX_W_0FE6_P_2 */
10998 { "vcvttpd2dq%XY", { XMM
, EXx
} },
11001 /* VEX_W_0FE6_P_3 */
11002 { "vcvtpd2dq%XY", { XMM
, EXx
} },
11005 /* VEX_W_0FE7_P_2_M_0 */
11006 { "vmovntdq", { Mx
, XM
} },
11009 /* VEX_W_0FE8_P_2 */
11010 { "vpsubsb", { XM
, Vex
, EXx
} },
11013 /* VEX_W_0FE9_P_2 */
11014 { "vpsubsw", { XM
, Vex
, EXx
} },
11017 /* VEX_W_0FEA_P_2 */
11018 { "vpminsw", { XM
, Vex
, EXx
} },
11021 /* VEX_W_0FEB_P_2 */
11022 { "vpor", { XM
, Vex
, EXx
} },
11025 /* VEX_W_0FEC_P_2 */
11026 { "vpaddsb", { XM
, Vex
, EXx
} },
11029 /* VEX_W_0FED_P_2 */
11030 { "vpaddsw", { XM
, Vex
, EXx
} },
11033 /* VEX_W_0FEE_P_2 */
11034 { "vpmaxsw", { XM
, Vex
, EXx
} },
11037 /* VEX_W_0FEF_P_2 */
11038 { "vpxor", { XM
, Vex
, EXx
} },
11041 /* VEX_W_0FF0_P_3_M_0 */
11042 { "vlddqu", { XM
, M
} },
11045 /* VEX_W_0FF1_P_2 */
11046 { "vpsllw", { XM
, Vex
, EXxmm
} },
11049 /* VEX_W_0FF2_P_2 */
11050 { "vpslld", { XM
, Vex
, EXxmm
} },
11053 /* VEX_W_0FF3_P_2 */
11054 { "vpsllq", { XM
, Vex
, EXxmm
} },
11057 /* VEX_W_0FF4_P_2 */
11058 { "vpmuludq", { XM
, Vex
, EXx
} },
11061 /* VEX_W_0FF5_P_2 */
11062 { "vpmaddwd", { XM
, Vex
, EXx
} },
11065 /* VEX_W_0FF6_P_2 */
11066 { "vpsadbw", { XM
, Vex
, EXx
} },
11069 /* VEX_W_0FF7_P_2 */
11070 { "vmaskmovdqu", { XM
, XS
} },
11073 /* VEX_W_0FF8_P_2 */
11074 { "vpsubb", { XM
, Vex
, EXx
} },
11077 /* VEX_W_0FF9_P_2 */
11078 { "vpsubw", { XM
, Vex
, EXx
} },
11081 /* VEX_W_0FFA_P_2 */
11082 { "vpsubd", { XM
, Vex
, EXx
} },
11085 /* VEX_W_0FFB_P_2 */
11086 { "vpsubq", { XM
, Vex
, EXx
} },
11089 /* VEX_W_0FFC_P_2 */
11090 { "vpaddb", { XM
, Vex
, EXx
} },
11093 /* VEX_W_0FFD_P_2 */
11094 { "vpaddw", { XM
, Vex
, EXx
} },
11097 /* VEX_W_0FFE_P_2 */
11098 { "vpaddd", { XM
, Vex
, EXx
} },
11101 /* VEX_W_0F3800_P_2 */
11102 { "vpshufb", { XM
, Vex
, EXx
} },
11105 /* VEX_W_0F3801_P_2 */
11106 { "vphaddw", { XM
, Vex
, EXx
} },
11109 /* VEX_W_0F3802_P_2 */
11110 { "vphaddd", { XM
, Vex
, EXx
} },
11113 /* VEX_W_0F3803_P_2 */
11114 { "vphaddsw", { XM
, Vex
, EXx
} },
11117 /* VEX_W_0F3804_P_2 */
11118 { "vpmaddubsw", { XM
, Vex
, EXx
} },
11121 /* VEX_W_0F3805_P_2 */
11122 { "vphsubw", { XM
, Vex
, EXx
} },
11125 /* VEX_W_0F3806_P_2 */
11126 { "vphsubd", { XM
, Vex
, EXx
} },
11129 /* VEX_W_0F3807_P_2 */
11130 { "vphsubsw", { XM
, Vex
, EXx
} },
11133 /* VEX_W_0F3808_P_2 */
11134 { "vpsignb", { XM
, Vex
, EXx
} },
11137 /* VEX_W_0F3809_P_2 */
11138 { "vpsignw", { XM
, Vex
, EXx
} },
11141 /* VEX_W_0F380A_P_2 */
11142 { "vpsignd", { XM
, Vex
, EXx
} },
11145 /* VEX_W_0F380B_P_2 */
11146 { "vpmulhrsw", { XM
, Vex
, EXx
} },
11149 /* VEX_W_0F380C_P_2 */
11150 { "vpermilps", { XM
, Vex
, EXx
} },
11153 /* VEX_W_0F380D_P_2 */
11154 { "vpermilpd", { XM
, Vex
, EXx
} },
11157 /* VEX_W_0F380E_P_2 */
11158 { "vtestps", { XM
, EXx
} },
11161 /* VEX_W_0F380F_P_2 */
11162 { "vtestpd", { XM
, EXx
} },
11165 /* VEX_W_0F3816_P_2 */
11166 { "vpermps", { XM
, Vex
, EXx
} },
11169 /* VEX_W_0F3817_P_2 */
11170 { "vptest", { XM
, EXx
} },
11173 /* VEX_W_0F3818_P_2 */
11174 { "vbroadcastss", { XM
, EXxmm_md
} },
11177 /* VEX_W_0F3819_P_2 */
11178 { "vbroadcastsd", { XM
, EXxmm_mq
} },
11181 /* VEX_W_0F381A_P_2_M_0 */
11182 { "vbroadcastf128", { XM
, Mxmm
} },
11185 /* VEX_W_0F381C_P_2 */
11186 { "vpabsb", { XM
, EXx
} },
11189 /* VEX_W_0F381D_P_2 */
11190 { "vpabsw", { XM
, EXx
} },
11193 /* VEX_W_0F381E_P_2 */
11194 { "vpabsd", { XM
, EXx
} },
11197 /* VEX_W_0F3820_P_2 */
11198 { "vpmovsxbw", { XM
, EXxmmq
} },
11201 /* VEX_W_0F3821_P_2 */
11202 { "vpmovsxbd", { XM
, EXxmmqd
} },
11205 /* VEX_W_0F3822_P_2 */
11206 { "vpmovsxbq", { XM
, EXxmmdw
} },
11209 /* VEX_W_0F3823_P_2 */
11210 { "vpmovsxwd", { XM
, EXxmmq
} },
11213 /* VEX_W_0F3824_P_2 */
11214 { "vpmovsxwq", { XM
, EXxmmqd
} },
11217 /* VEX_W_0F3825_P_2 */
11218 { "vpmovsxdq", { XM
, EXxmmq
} },
11221 /* VEX_W_0F3828_P_2 */
11222 { "vpmuldq", { XM
, Vex
, EXx
} },
11225 /* VEX_W_0F3829_P_2 */
11226 { "vpcmpeqq", { XM
, Vex
, EXx
} },
11229 /* VEX_W_0F382A_P_2_M_0 */
11230 { "vmovntdqa", { XM
, Mx
} },
11233 /* VEX_W_0F382B_P_2 */
11234 { "vpackusdw", { XM
, Vex
, EXx
} },
11237 /* VEX_W_0F382C_P_2_M_0 */
11238 { "vmaskmovps", { XM
, Vex
, Mx
} },
11241 /* VEX_W_0F382D_P_2_M_0 */
11242 { "vmaskmovpd", { XM
, Vex
, Mx
} },
11245 /* VEX_W_0F382E_P_2_M_0 */
11246 { "vmaskmovps", { Mx
, Vex
, XM
} },
11249 /* VEX_W_0F382F_P_2_M_0 */
11250 { "vmaskmovpd", { Mx
, Vex
, XM
} },
11253 /* VEX_W_0F3830_P_2 */
11254 { "vpmovzxbw", { XM
, EXxmmq
} },
11257 /* VEX_W_0F3831_P_2 */
11258 { "vpmovzxbd", { XM
, EXxmmqd
} },
11261 /* VEX_W_0F3832_P_2 */
11262 { "vpmovzxbq", { XM
, EXxmmdw
} },
11265 /* VEX_W_0F3833_P_2 */
11266 { "vpmovzxwd", { XM
, EXxmmq
} },
11269 /* VEX_W_0F3834_P_2 */
11270 { "vpmovzxwq", { XM
, EXxmmqd
} },
11273 /* VEX_W_0F3835_P_2 */
11274 { "vpmovzxdq", { XM
, EXxmmq
} },
11277 /* VEX_W_0F3836_P_2 */
11278 { "vpermd", { XM
, Vex
, EXx
} },
11281 /* VEX_W_0F3837_P_2 */
11282 { "vpcmpgtq", { XM
, Vex
, EXx
} },
11285 /* VEX_W_0F3838_P_2 */
11286 { "vpminsb", { XM
, Vex
, EXx
} },
11289 /* VEX_W_0F3839_P_2 */
11290 { "vpminsd", { XM
, Vex
, EXx
} },
11293 /* VEX_W_0F383A_P_2 */
11294 { "vpminuw", { XM
, Vex
, EXx
} },
11297 /* VEX_W_0F383B_P_2 */
11298 { "vpminud", { XM
, Vex
, EXx
} },
11301 /* VEX_W_0F383C_P_2 */
11302 { "vpmaxsb", { XM
, Vex
, EXx
} },
11305 /* VEX_W_0F383D_P_2 */
11306 { "vpmaxsd", { XM
, Vex
, EXx
} },
11309 /* VEX_W_0F383E_P_2 */
11310 { "vpmaxuw", { XM
, Vex
, EXx
} },
11313 /* VEX_W_0F383F_P_2 */
11314 { "vpmaxud", { XM
, Vex
, EXx
} },
11317 /* VEX_W_0F3840_P_2 */
11318 { "vpmulld", { XM
, Vex
, EXx
} },
11321 /* VEX_W_0F3841_P_2 */
11322 { "vphminposuw", { XM
, EXx
} },
11325 /* VEX_W_0F3846_P_2 */
11326 { "vpsravd", { XM
, Vex
, EXx
} },
11329 /* VEX_W_0F3858_P_2 */
11330 { "vpbroadcastd", { XM
, EXxmm_md
} },
11333 /* VEX_W_0F3859_P_2 */
11334 { "vpbroadcastq", { XM
, EXxmm_mq
} },
11337 /* VEX_W_0F385A_P_2_M_0 */
11338 { "vbroadcasti128", { XM
, Mxmm
} },
11341 /* VEX_W_0F3878_P_2 */
11342 { "vpbroadcastb", { XM
, EXxmm_mb
} },
11345 /* VEX_W_0F3879_P_2 */
11346 { "vpbroadcastw", { XM
, EXxmm_mw
} },
11349 /* VEX_W_0F38DB_P_2 */
11350 { "vaesimc", { XM
, EXx
} },
11353 /* VEX_W_0F38DC_P_2 */
11354 { "vaesenc", { XM
, Vex128
, EXx
} },
11357 /* VEX_W_0F38DD_P_2 */
11358 { "vaesenclast", { XM
, Vex128
, EXx
} },
11361 /* VEX_W_0F38DE_P_2 */
11362 { "vaesdec", { XM
, Vex128
, EXx
} },
11365 /* VEX_W_0F38DF_P_2 */
11366 { "vaesdeclast", { XM
, Vex128
, EXx
} },
11369 /* VEX_W_0F3A00_P_2 */
11371 { "vpermq", { XM
, EXx
, Ib
} },
11374 /* VEX_W_0F3A01_P_2 */
11376 { "vpermpd", { XM
, EXx
, Ib
} },
11379 /* VEX_W_0F3A02_P_2 */
11380 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
11383 /* VEX_W_0F3A04_P_2 */
11384 { "vpermilps", { XM
, EXx
, Ib
} },
11387 /* VEX_W_0F3A05_P_2 */
11388 { "vpermilpd", { XM
, EXx
, Ib
} },
11391 /* VEX_W_0F3A06_P_2 */
11392 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
11395 /* VEX_W_0F3A08_P_2 */
11396 { "vroundps", { XM
, EXx
, Ib
} },
11399 /* VEX_W_0F3A09_P_2 */
11400 { "vroundpd", { XM
, EXx
, Ib
} },
11403 /* VEX_W_0F3A0A_P_2 */
11404 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
11407 /* VEX_W_0F3A0B_P_2 */
11408 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
11411 /* VEX_W_0F3A0C_P_2 */
11412 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
11415 /* VEX_W_0F3A0D_P_2 */
11416 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
11419 /* VEX_W_0F3A0E_P_2 */
11420 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
11423 /* VEX_W_0F3A0F_P_2 */
11424 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
11427 /* VEX_W_0F3A14_P_2 */
11428 { "vpextrb", { Edqb
, XM
, Ib
} },
11431 /* VEX_W_0F3A15_P_2 */
11432 { "vpextrw", { Edqw
, XM
, Ib
} },
11435 /* VEX_W_0F3A18_P_2 */
11436 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
11439 /* VEX_W_0F3A19_P_2 */
11440 { "vextractf128", { EXxmm
, XM
, Ib
} },
11443 /* VEX_W_0F3A20_P_2 */
11444 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
11447 /* VEX_W_0F3A21_P_2 */
11448 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
11451 /* VEX_W_0F3A30_P_2_LEN_0 */
11452 { "kshiftrb", { MaskG
, MaskR
, Ib
} },
11453 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
11456 /* VEX_W_0F3A31_P_2_LEN_0 */
11457 { "kshiftrd", { MaskG
, MaskR
, Ib
} },
11458 { "kshiftrq", { MaskG
, MaskR
, Ib
} },
11461 /* VEX_W_0F3A32_P_2_LEN_0 */
11462 { "kshiftlb", { MaskG
, MaskR
, Ib
} },
11463 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
11466 /* VEX_W_0F3A33_P_2_LEN_0 */
11467 { "kshiftld", { MaskG
, MaskR
, Ib
} },
11468 { "kshiftlq", { MaskG
, MaskR
, Ib
} },
11471 /* VEX_W_0F3A38_P_2 */
11472 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
11475 /* VEX_W_0F3A39_P_2 */
11476 { "vextracti128", { EXxmm
, XM
, Ib
} },
11479 /* VEX_W_0F3A40_P_2 */
11480 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
11483 /* VEX_W_0F3A41_P_2 */
11484 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
11487 /* VEX_W_0F3A42_P_2 */
11488 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
11491 /* VEX_W_0F3A44_P_2 */
11492 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11495 /* VEX_W_0F3A46_P_2 */
11496 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11499 /* VEX_W_0F3A48_P_2 */
11500 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11501 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11504 /* VEX_W_0F3A49_P_2 */
11505 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11506 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11509 /* VEX_W_0F3A4A_P_2 */
11510 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11513 /* VEX_W_0F3A4B_P_2 */
11514 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11517 /* VEX_W_0F3A4C_P_2 */
11518 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11521 /* VEX_W_0F3A60_P_2 */
11522 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11525 /* VEX_W_0F3A61_P_2 */
11526 { "vpcmpestri", { XM
, EXx
, Ib
} },
11529 /* VEX_W_0F3A62_P_2 */
11530 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11533 /* VEX_W_0F3A63_P_2 */
11534 { "vpcmpistri", { XM
, EXx
, Ib
} },
11537 /* VEX_W_0F3ADF_P_2 */
11538 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11540 #define NEED_VEX_W_TABLE
11541 #include "i386-dis-evex.h"
11542 #undef NEED_VEX_W_TABLE
11545 static const struct dis386 mod_table
[][2] = {
11548 { "leaS", { Gv
, M
} },
11553 { RM_TABLE (RM_C6_REG_7
) },
11558 { RM_TABLE (RM_C7_REG_7
) },
11562 { "Jcall{T|}", { indirEp
} },
11566 { "Jjmp{T|}", { indirEp
} },
11569 /* MOD_0F01_REG_0 */
11570 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11571 { RM_TABLE (RM_0F01_REG_0
) },
11574 /* MOD_0F01_REG_1 */
11575 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11576 { RM_TABLE (RM_0F01_REG_1
) },
11579 /* MOD_0F01_REG_2 */
11580 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11581 { RM_TABLE (RM_0F01_REG_2
) },
11584 /* MOD_0F01_REG_3 */
11585 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11586 { RM_TABLE (RM_0F01_REG_3
) },
11589 /* MOD_0F01_REG_7 */
11590 { "invlpg", { Mb
} },
11591 { RM_TABLE (RM_0F01_REG_7
) },
11594 /* MOD_0F12_PREFIX_0 */
11595 { "movlps", { XM
, EXq
} },
11596 { "movhlps", { XM
, EXq
} },
11600 { "movlpX", { EXq
, XM
} },
11603 /* MOD_0F16_PREFIX_0 */
11604 { "movhps", { XM
, EXq
} },
11605 { "movlhps", { XM
, EXq
} },
11609 { "movhpX", { EXq
, XM
} },
11612 /* MOD_0F18_REG_0 */
11613 { "prefetchnta", { Mb
} },
11616 /* MOD_0F18_REG_1 */
11617 { "prefetcht0", { Mb
} },
11620 /* MOD_0F18_REG_2 */
11621 { "prefetcht1", { Mb
} },
11624 /* MOD_0F18_REG_3 */
11625 { "prefetcht2", { Mb
} },
11628 /* MOD_0F18_REG_4 */
11629 { "nop/reserved", { Mb
} },
11632 /* MOD_0F18_REG_5 */
11633 { "nop/reserved", { Mb
} },
11636 /* MOD_0F18_REG_6 */
11637 { "nop/reserved", { Mb
} },
11640 /* MOD_0F18_REG_7 */
11641 { "nop/reserved", { Mb
} },
11644 /* MOD_0F1A_PREFIX_0 */
11645 { "bndldx", { Gbnd
, Ev_bnd
} },
11646 { "nopQ", { Ev
} },
11649 /* MOD_0F1B_PREFIX_0 */
11650 { "bndstx", { Ev_bnd
, Gbnd
} },
11651 { "nopQ", { Ev
} },
11654 /* MOD_0F1B_PREFIX_1 */
11655 { "bndmk", { Gbnd
, Ev_bnd
} },
11656 { "nopQ", { Ev
} },
11661 { "movL", { Rd
, Td
} },
11666 { "movL", { Td
, Rd
} },
11669 /* MOD_0F2B_PREFIX_0 */
11670 {"movntps", { Mx
, XM
} },
11673 /* MOD_0F2B_PREFIX_1 */
11674 {"movntss", { Md
, XM
} },
11677 /* MOD_0F2B_PREFIX_2 */
11678 {"movntpd", { Mx
, XM
} },
11681 /* MOD_0F2B_PREFIX_3 */
11682 {"movntsd", { Mq
, XM
} },
11687 { "movmskpX", { Gdq
, XS
} },
11690 /* MOD_0F71_REG_2 */
11692 { "psrlw", { MS
, Ib
} },
11695 /* MOD_0F71_REG_4 */
11697 { "psraw", { MS
, Ib
} },
11700 /* MOD_0F71_REG_6 */
11702 { "psllw", { MS
, Ib
} },
11705 /* MOD_0F72_REG_2 */
11707 { "psrld", { MS
, Ib
} },
11710 /* MOD_0F72_REG_4 */
11712 { "psrad", { MS
, Ib
} },
11715 /* MOD_0F72_REG_6 */
11717 { "pslld", { MS
, Ib
} },
11720 /* MOD_0F73_REG_2 */
11722 { "psrlq", { MS
, Ib
} },
11725 /* MOD_0F73_REG_3 */
11727 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11730 /* MOD_0F73_REG_6 */
11732 { "psllq", { MS
, Ib
} },
11735 /* MOD_0F73_REG_7 */
11737 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11740 /* MOD_0FAE_REG_0 */
11741 { "fxsave", { FXSAVE
} },
11742 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11745 /* MOD_0FAE_REG_1 */
11746 { "fxrstor", { FXSAVE
} },
11747 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11750 /* MOD_0FAE_REG_2 */
11751 { "ldmxcsr", { Md
} },
11752 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11755 /* MOD_0FAE_REG_3 */
11756 { "stmxcsr", { Md
} },
11757 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11760 /* MOD_0FAE_REG_4 */
11761 { "xsave", { FXSAVE
} },
11764 /* MOD_0FAE_REG_5 */
11765 { "xrstor", { FXSAVE
} },
11766 { RM_TABLE (RM_0FAE_REG_5
) },
11769 /* MOD_0FAE_REG_6 */
11770 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11771 { RM_TABLE (RM_0FAE_REG_6
) },
11774 /* MOD_0FAE_REG_7 */
11775 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11776 { RM_TABLE (RM_0FAE_REG_7
) },
11780 { "lssS", { Gv
, Mp
} },
11784 { "lfsS", { Gv
, Mp
} },
11788 { "lgsS", { Gv
, Mp
} },
11791 /* MOD_0FC7_REG_3 */
11792 { "xrstors", { FXSAVE
} },
11795 /* MOD_0FC7_REG_4 */
11796 { "xsavec", { FXSAVE
} },
11799 /* MOD_0FC7_REG_5 */
11800 { "xsaves", { FXSAVE
} },
11803 /* MOD_0FC7_REG_6 */
11804 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11805 { "rdrand", { Ev
} },
11808 /* MOD_0FC7_REG_7 */
11809 { "vmptrst", { Mq
} },
11810 { "rdseed", { Ev
} },
11815 { "pmovmskb", { Gdq
, MS
} },
11818 /* MOD_0FE7_PREFIX_2 */
11819 { "movntdq", { Mx
, XM
} },
11822 /* MOD_0FF0_PREFIX_3 */
11823 { "lddqu", { XM
, M
} },
11826 /* MOD_0F382A_PREFIX_2 */
11827 { "movntdqa", { XM
, Mx
} },
11831 { "bound{S|}", { Gv
, Ma
} },
11832 { EVEX_TABLE (EVEX_0F
) },
11836 { "lesS", { Gv
, Mp
} },
11837 { VEX_C4_TABLE (VEX_0F
) },
11841 { "ldsS", { Gv
, Mp
} },
11842 { VEX_C5_TABLE (VEX_0F
) },
11845 /* MOD_VEX_0F12_PREFIX_0 */
11846 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11847 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11851 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11854 /* MOD_VEX_0F16_PREFIX_0 */
11855 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11856 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11860 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11864 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11869 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11872 /* MOD_VEX_0F71_REG_2 */
11874 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11877 /* MOD_VEX_0F71_REG_4 */
11879 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11882 /* MOD_VEX_0F71_REG_6 */
11884 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11887 /* MOD_VEX_0F72_REG_2 */
11889 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11892 /* MOD_VEX_0F72_REG_4 */
11894 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11897 /* MOD_VEX_0F72_REG_6 */
11899 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11902 /* MOD_VEX_0F73_REG_2 */
11904 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11907 /* MOD_VEX_0F73_REG_3 */
11909 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11912 /* MOD_VEX_0F73_REG_6 */
11914 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11917 /* MOD_VEX_0F73_REG_7 */
11919 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11922 /* MOD_VEX_0FAE_REG_2 */
11923 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11926 /* MOD_VEX_0FAE_REG_3 */
11927 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11930 /* MOD_VEX_0FD7_PREFIX_2 */
11932 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11935 /* MOD_VEX_0FE7_PREFIX_2 */
11936 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11939 /* MOD_VEX_0FF0_PREFIX_3 */
11940 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11943 /* MOD_VEX_0F381A_PREFIX_2 */
11944 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11947 /* MOD_VEX_0F382A_PREFIX_2 */
11948 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11951 /* MOD_VEX_0F382C_PREFIX_2 */
11952 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11955 /* MOD_VEX_0F382D_PREFIX_2 */
11956 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11959 /* MOD_VEX_0F382E_PREFIX_2 */
11960 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11963 /* MOD_VEX_0F382F_PREFIX_2 */
11964 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11967 /* MOD_VEX_0F385A_PREFIX_2 */
11968 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11971 /* MOD_VEX_0F388C_PREFIX_2 */
11972 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11975 /* MOD_VEX_0F388E_PREFIX_2 */
11976 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11978 #define NEED_MOD_TABLE
11979 #include "i386-dis-evex.h"
11980 #undef NEED_MOD_TABLE
11983 static const struct dis386 rm_table
[][8] = {
11986 { "xabort", { Skip_MODRM
, Ib
} },
11990 { "xbeginT", { Skip_MODRM
, Jv
} },
11993 /* RM_0F01_REG_0 */
11995 { "vmcall", { Skip_MODRM
} },
11996 { "vmlaunch", { Skip_MODRM
} },
11997 { "vmresume", { Skip_MODRM
} },
11998 { "vmxoff", { Skip_MODRM
} },
12001 /* RM_0F01_REG_1 */
12002 { "monitor", { { OP_Monitor
, 0 } } },
12003 { "mwait", { { OP_Mwait
, 0 } } },
12004 { "clac", { Skip_MODRM
} },
12005 { "stac", { Skip_MODRM
} },
12009 { "encls", { Skip_MODRM
} },
12012 /* RM_0F01_REG_2 */
12013 { "xgetbv", { Skip_MODRM
} },
12014 { "xsetbv", { Skip_MODRM
} },
12017 { "vmfunc", { Skip_MODRM
} },
12018 { "xend", { Skip_MODRM
} },
12019 { "xtest", { Skip_MODRM
} },
12020 { "enclu", { Skip_MODRM
} },
12023 /* RM_0F01_REG_3 */
12024 { "vmrun", { Skip_MODRM
} },
12025 { "vmmcall", { Skip_MODRM
} },
12026 { "vmload", { Skip_MODRM
} },
12027 { "vmsave", { Skip_MODRM
} },
12028 { "stgi", { Skip_MODRM
} },
12029 { "clgi", { Skip_MODRM
} },
12030 { "skinit", { Skip_MODRM
} },
12031 { "invlpga", { Skip_MODRM
} },
12034 /* RM_0F01_REG_7 */
12035 { "swapgs", { Skip_MODRM
} },
12036 { "rdtscp", { Skip_MODRM
} },
12039 /* RM_0FAE_REG_5 */
12040 { "lfence", { Skip_MODRM
} },
12043 /* RM_0FAE_REG_6 */
12044 { "mfence", { Skip_MODRM
} },
12047 /* RM_0FAE_REG_7 */
12048 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12052 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12054 /* We use the high bit to indicate different name for the same
12056 #define REP_PREFIX (0xf3 | 0x100)
12057 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12058 #define XRELEASE_PREFIX (0xf3 | 0x400)
12059 #define BND_PREFIX (0xf2 | 0x400)
12064 int newrex
, i
, length
;
12070 last_lock_prefix
= -1;
12071 last_repz_prefix
= -1;
12072 last_repnz_prefix
= -1;
12073 last_data_prefix
= -1;
12074 last_addr_prefix
= -1;
12075 last_rex_prefix
= -1;
12076 last_seg_prefix
= -1;
12078 active_seg_prefix
= 0;
12079 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12080 all_prefixes
[i
] = 0;
12083 /* The maximum instruction length is 15bytes. */
12084 while (length
< MAX_CODE_LENGTH
- 1)
12086 FETCH_DATA (the_info
, codep
+ 1);
12090 /* REX prefixes family. */
12107 if (address_mode
== mode_64bit
)
12111 last_rex_prefix
= i
;
12114 prefixes
|= PREFIX_REPZ
;
12115 last_repz_prefix
= i
;
12118 prefixes
|= PREFIX_REPNZ
;
12119 last_repnz_prefix
= i
;
12122 prefixes
|= PREFIX_LOCK
;
12123 last_lock_prefix
= i
;
12126 prefixes
|= PREFIX_CS
;
12127 last_seg_prefix
= i
;
12128 active_seg_prefix
= PREFIX_CS
;
12131 prefixes
|= PREFIX_SS
;
12132 last_seg_prefix
= i
;
12133 active_seg_prefix
= PREFIX_SS
;
12136 prefixes
|= PREFIX_DS
;
12137 last_seg_prefix
= i
;
12138 active_seg_prefix
= PREFIX_DS
;
12141 prefixes
|= PREFIX_ES
;
12142 last_seg_prefix
= i
;
12143 active_seg_prefix
= PREFIX_ES
;
12146 prefixes
|= PREFIX_FS
;
12147 last_seg_prefix
= i
;
12148 active_seg_prefix
= PREFIX_FS
;
12151 prefixes
|= PREFIX_GS
;
12152 last_seg_prefix
= i
;
12153 active_seg_prefix
= PREFIX_GS
;
12156 prefixes
|= PREFIX_DATA
;
12157 last_data_prefix
= i
;
12160 prefixes
|= PREFIX_ADDR
;
12161 last_addr_prefix
= i
;
12164 /* fwait is really an instruction. If there are prefixes
12165 before the fwait, they belong to the fwait, *not* to the
12166 following instruction. */
12168 if (prefixes
|| rex
)
12170 prefixes
|= PREFIX_FWAIT
;
12172 /* This ensures that the previous REX prefixes are noticed
12173 as unused prefixes, as in the return case below. */
12177 prefixes
= PREFIX_FWAIT
;
12182 /* Rex is ignored when followed by another prefix. */
12188 if (*codep
!= FWAIT_OPCODE
)
12189 all_prefixes
[i
++] = *codep
;
12197 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12200 static const char *
12201 prefix_name (int pref
, int sizeflag
)
12203 static const char *rexes
[16] =
12206 "rex.B", /* 0x41 */
12207 "rex.X", /* 0x42 */
12208 "rex.XB", /* 0x43 */
12209 "rex.R", /* 0x44 */
12210 "rex.RB", /* 0x45 */
12211 "rex.RX", /* 0x46 */
12212 "rex.RXB", /* 0x47 */
12213 "rex.W", /* 0x48 */
12214 "rex.WB", /* 0x49 */
12215 "rex.WX", /* 0x4a */
12216 "rex.WXB", /* 0x4b */
12217 "rex.WR", /* 0x4c */
12218 "rex.WRB", /* 0x4d */
12219 "rex.WRX", /* 0x4e */
12220 "rex.WRXB", /* 0x4f */
12225 /* REX prefixes family. */
12242 return rexes
[pref
- 0x40];
12262 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12264 if (address_mode
== mode_64bit
)
12265 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12267 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12272 case XACQUIRE_PREFIX
:
12274 case XRELEASE_PREFIX
:
12283 static char op_out
[MAX_OPERANDS
][100];
12284 static int op_ad
, op_index
[MAX_OPERANDS
];
12285 static int two_source_ops
;
12286 static bfd_vma op_address
[MAX_OPERANDS
];
12287 static bfd_vma op_riprel
[MAX_OPERANDS
];
12288 static bfd_vma start_pc
;
12291 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12292 * (see topic "Redundant prefixes" in the "Differences from 8086"
12293 * section of the "Virtual 8086 Mode" chapter.)
12294 * 'pc' should be the address of this instruction, it will
12295 * be used to print the target address if this is a relative jump or call
12296 * The function returns the length of this instruction in bytes.
12299 static char intel_syntax
;
12300 static char intel_mnemonic
= !SYSV386_COMPAT
;
12301 static char open_char
;
12302 static char close_char
;
12303 static char separator_char
;
12304 static char scale_char
;
12306 /* Here for backwards compatibility. When gdb stops using
12307 print_insn_i386_att and print_insn_i386_intel these functions can
12308 disappear, and print_insn_i386 be merged into print_insn. */
12310 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12314 return print_insn (pc
, info
);
12318 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12322 return print_insn (pc
, info
);
12326 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12330 return print_insn (pc
, info
);
12334 print_i386_disassembler_options (FILE *stream
)
12336 fprintf (stream
, _("\n\
12337 The following i386/x86-64 specific disassembler options are supported for use\n\
12338 with the -M switch (multiple options should be separated by commas):\n"));
12340 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12341 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12342 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12343 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12344 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12345 fprintf (stream
, _(" att-mnemonic\n"
12346 " Display instruction in AT&T mnemonic\n"));
12347 fprintf (stream
, _(" intel-mnemonic\n"
12348 " Display instruction in Intel mnemonic\n"));
12349 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12350 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12351 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12352 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12353 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12354 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12358 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
12360 /* Get a pointer to struct dis386 with a valid name. */
12362 static const struct dis386
*
12363 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12365 int vindex
, vex_table_index
;
12367 if (dp
->name
!= NULL
)
12370 switch (dp
->op
[0].bytemode
)
12372 case USE_REG_TABLE
:
12373 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12376 case USE_MOD_TABLE
:
12377 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12378 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12382 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12385 case USE_PREFIX_TABLE
:
12388 /* The prefix in VEX is implicit. */
12389 switch (vex
.prefix
)
12394 case REPE_PREFIX_OPCODE
:
12397 case DATA_PREFIX_OPCODE
:
12400 case REPNE_PREFIX_OPCODE
:
12410 int last_prefix
= -1;
12413 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12414 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12416 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12418 if (last_repz_prefix
> last_repnz_prefix
)
12421 prefix
= PREFIX_REPZ
;
12422 last_prefix
= last_repz_prefix
;
12427 prefix
= PREFIX_REPNZ
;
12428 last_prefix
= last_repnz_prefix
;
12431 /* Ignore the invalid index if it isn't mandatory. */
12432 if (!mandatory_prefix
12433 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].name
12435 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].op
[0].bytemode
12440 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12443 prefix
= PREFIX_DATA
;
12444 last_prefix
= last_data_prefix
;
12449 used_prefixes
|= prefix
;
12450 all_prefixes
[last_prefix
] = 0;
12453 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12456 case USE_X86_64_TABLE
:
12457 vindex
= address_mode
== mode_64bit
? 1 : 0;
12458 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12461 case USE_3BYTE_TABLE
:
12462 FETCH_DATA (info
, codep
+ 2);
12464 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12466 modrm
.mod
= (*codep
>> 6) & 3;
12467 modrm
.reg
= (*codep
>> 3) & 7;
12468 modrm
.rm
= *codep
& 7;
12471 case USE_VEX_LEN_TABLE
:
12475 switch (vex
.length
)
12488 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12491 case USE_XOP_8F_TABLE
:
12492 FETCH_DATA (info
, codep
+ 3);
12493 /* All bits in the REX prefix are ignored. */
12495 rex
= ~(*codep
>> 5) & 0x7;
12497 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12498 switch ((*codep
& 0x1f))
12504 vex_table_index
= XOP_08
;
12507 vex_table_index
= XOP_09
;
12510 vex_table_index
= XOP_0A
;
12514 vex
.w
= *codep
& 0x80;
12515 if (vex
.w
&& address_mode
== mode_64bit
)
12518 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12519 if (address_mode
!= mode_64bit
12520 && vex
.register_specifier
> 0x7)
12526 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12527 switch ((*codep
& 0x3))
12533 vex
.prefix
= DATA_PREFIX_OPCODE
;
12536 vex
.prefix
= REPE_PREFIX_OPCODE
;
12539 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12546 dp
= &xop_table
[vex_table_index
][vindex
];
12549 FETCH_DATA (info
, codep
+ 1);
12550 modrm
.mod
= (*codep
>> 6) & 3;
12551 modrm
.reg
= (*codep
>> 3) & 7;
12552 modrm
.rm
= *codep
& 7;
12555 case USE_VEX_C4_TABLE
:
12557 FETCH_DATA (info
, codep
+ 3);
12558 /* All bits in the REX prefix are ignored. */
12560 rex
= ~(*codep
>> 5) & 0x7;
12561 switch ((*codep
& 0x1f))
12567 vex_table_index
= VEX_0F
;
12570 vex_table_index
= VEX_0F38
;
12573 vex_table_index
= VEX_0F3A
;
12577 vex
.w
= *codep
& 0x80;
12578 if (vex
.w
&& address_mode
== mode_64bit
)
12581 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12582 if (address_mode
!= mode_64bit
12583 && vex
.register_specifier
> 0x7)
12589 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12590 switch ((*codep
& 0x3))
12596 vex
.prefix
= DATA_PREFIX_OPCODE
;
12599 vex
.prefix
= REPE_PREFIX_OPCODE
;
12602 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12609 dp
= &vex_table
[vex_table_index
][vindex
];
12611 /* There is no MODRM byte for VEX [82|77]. */
12612 if (vindex
!= 0x77 && vindex
!= 0x82)
12614 FETCH_DATA (info
, codep
+ 1);
12615 modrm
.mod
= (*codep
>> 6) & 3;
12616 modrm
.reg
= (*codep
>> 3) & 7;
12617 modrm
.rm
= *codep
& 7;
12621 case USE_VEX_C5_TABLE
:
12623 FETCH_DATA (info
, codep
+ 2);
12624 /* All bits in the REX prefix are ignored. */
12626 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12628 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12629 if (address_mode
!= mode_64bit
12630 && vex
.register_specifier
> 0x7)
12638 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12639 switch ((*codep
& 0x3))
12645 vex
.prefix
= DATA_PREFIX_OPCODE
;
12648 vex
.prefix
= REPE_PREFIX_OPCODE
;
12651 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12658 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12660 /* There is no MODRM byte for VEX [82|77]. */
12661 if (vindex
!= 0x77 && vindex
!= 0x82)
12663 FETCH_DATA (info
, codep
+ 1);
12664 modrm
.mod
= (*codep
>> 6) & 3;
12665 modrm
.reg
= (*codep
>> 3) & 7;
12666 modrm
.rm
= *codep
& 7;
12670 case USE_VEX_W_TABLE
:
12674 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12677 case USE_EVEX_TABLE
:
12678 two_source_ops
= 0;
12681 FETCH_DATA (info
, codep
+ 4);
12682 /* All bits in the REX prefix are ignored. */
12684 /* The first byte after 0x62. */
12685 rex
= ~(*codep
>> 5) & 0x7;
12686 vex
.r
= *codep
& 0x10;
12687 switch ((*codep
& 0xf))
12690 return &bad_opcode
;
12692 vex_table_index
= EVEX_0F
;
12695 vex_table_index
= EVEX_0F38
;
12698 vex_table_index
= EVEX_0F3A
;
12702 /* The second byte after 0x62. */
12704 vex
.w
= *codep
& 0x80;
12705 if (vex
.w
&& address_mode
== mode_64bit
)
12708 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12709 if (address_mode
!= mode_64bit
)
12711 /* In 16/32-bit mode silently ignore following bits. */
12715 vex
.register_specifier
&= 0x7;
12719 if (!(*codep
& 0x4))
12720 return &bad_opcode
;
12722 switch ((*codep
& 0x3))
12728 vex
.prefix
= DATA_PREFIX_OPCODE
;
12731 vex
.prefix
= REPE_PREFIX_OPCODE
;
12734 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12738 /* The third byte after 0x62. */
12741 /* Remember the static rounding bits. */
12742 vex
.ll
= (*codep
>> 5) & 3;
12743 vex
.b
= (*codep
& 0x10) != 0;
12745 vex
.v
= *codep
& 0x8;
12746 vex
.mask_register_specifier
= *codep
& 0x7;
12747 vex
.zeroing
= *codep
& 0x80;
12753 dp
= &evex_table
[vex_table_index
][vindex
];
12755 FETCH_DATA (info
, codep
+ 1);
12756 modrm
.mod
= (*codep
>> 6) & 3;
12757 modrm
.reg
= (*codep
>> 3) & 7;
12758 modrm
.rm
= *codep
& 7;
12760 /* Set vector length. */
12761 if (modrm
.mod
== 3 && vex
.b
)
12777 return &bad_opcode
;
12790 if (dp
->name
!= NULL
)
12793 return get_valid_dis386 (dp
, info
);
12797 get_sib (disassemble_info
*info
, int sizeflag
)
12799 /* If modrm.mod == 3, operand must be register. */
12801 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12805 FETCH_DATA (info
, codep
+ 2);
12806 sib
.index
= (codep
[1] >> 3) & 7;
12807 sib
.scale
= (codep
[1] >> 6) & 3;
12808 sib
.base
= codep
[1] & 7;
12813 print_insn (bfd_vma pc
, disassemble_info
*info
)
12815 const struct dis386
*dp
;
12817 char *op_txt
[MAX_OPERANDS
];
12819 int sizeflag
, orig_sizeflag
;
12821 struct dis_private priv
;
12824 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12825 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12826 address_mode
= mode_32bit
;
12827 else if (info
->mach
== bfd_mach_i386_i8086
)
12829 address_mode
= mode_16bit
;
12830 priv
.orig_sizeflag
= 0;
12833 address_mode
= mode_64bit
;
12835 if (intel_syntax
== (char) -1)
12836 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12838 for (p
= info
->disassembler_options
; p
!= NULL
; )
12840 if (CONST_STRNEQ (p
, "x86-64"))
12842 address_mode
= mode_64bit
;
12843 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12845 else if (CONST_STRNEQ (p
, "i386"))
12847 address_mode
= mode_32bit
;
12848 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12850 else if (CONST_STRNEQ (p
, "i8086"))
12852 address_mode
= mode_16bit
;
12853 priv
.orig_sizeflag
= 0;
12855 else if (CONST_STRNEQ (p
, "intel"))
12858 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12859 intel_mnemonic
= 1;
12861 else if (CONST_STRNEQ (p
, "att"))
12864 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12865 intel_mnemonic
= 0;
12867 else if (CONST_STRNEQ (p
, "addr"))
12869 if (address_mode
== mode_64bit
)
12871 if (p
[4] == '3' && p
[5] == '2')
12872 priv
.orig_sizeflag
&= ~AFLAG
;
12873 else if (p
[4] == '6' && p
[5] == '4')
12874 priv
.orig_sizeflag
|= AFLAG
;
12878 if (p
[4] == '1' && p
[5] == '6')
12879 priv
.orig_sizeflag
&= ~AFLAG
;
12880 else if (p
[4] == '3' && p
[5] == '2')
12881 priv
.orig_sizeflag
|= AFLAG
;
12884 else if (CONST_STRNEQ (p
, "data"))
12886 if (p
[4] == '1' && p
[5] == '6')
12887 priv
.orig_sizeflag
&= ~DFLAG
;
12888 else if (p
[4] == '3' && p
[5] == '2')
12889 priv
.orig_sizeflag
|= DFLAG
;
12891 else if (CONST_STRNEQ (p
, "suffix"))
12892 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12894 p
= strchr (p
, ',');
12901 names64
= intel_names64
;
12902 names32
= intel_names32
;
12903 names16
= intel_names16
;
12904 names8
= intel_names8
;
12905 names8rex
= intel_names8rex
;
12906 names_seg
= intel_names_seg
;
12907 names_mm
= intel_names_mm
;
12908 names_bnd
= intel_names_bnd
;
12909 names_xmm
= intel_names_xmm
;
12910 names_ymm
= intel_names_ymm
;
12911 names_zmm
= intel_names_zmm
;
12912 index64
= intel_index64
;
12913 index32
= intel_index32
;
12914 names_mask
= intel_names_mask
;
12915 index16
= intel_index16
;
12918 separator_char
= '+';
12923 names64
= att_names64
;
12924 names32
= att_names32
;
12925 names16
= att_names16
;
12926 names8
= att_names8
;
12927 names8rex
= att_names8rex
;
12928 names_seg
= att_names_seg
;
12929 names_mm
= att_names_mm
;
12930 names_bnd
= att_names_bnd
;
12931 names_xmm
= att_names_xmm
;
12932 names_ymm
= att_names_ymm
;
12933 names_zmm
= att_names_zmm
;
12934 index64
= att_index64
;
12935 index32
= att_index32
;
12936 names_mask
= att_names_mask
;
12937 index16
= att_index16
;
12940 separator_char
= ',';
12944 /* The output looks better if we put 7 bytes on a line, since that
12945 puts most long word instructions on a single line. Use 8 bytes
12947 if ((info
->mach
& bfd_mach_l1om
) != 0)
12948 info
->bytes_per_line
= 8;
12950 info
->bytes_per_line
= 7;
12952 info
->private_data
= &priv
;
12953 priv
.max_fetched
= priv
.the_buffer
;
12954 priv
.insn_start
= pc
;
12957 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12965 start_codep
= priv
.the_buffer
;
12966 codep
= priv
.the_buffer
;
12968 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12972 /* Getting here means we tried for data but didn't get it. That
12973 means we have an incomplete instruction of some sort. Just
12974 print the first byte as a prefix or a .byte pseudo-op. */
12975 if (codep
> priv
.the_buffer
)
12977 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12979 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12982 /* Just print the first byte as a .byte instruction. */
12983 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12984 (unsigned int) priv
.the_buffer
[0]);
12994 sizeflag
= priv
.orig_sizeflag
;
12996 if (!ckprefix () || rex_used
)
12998 /* Too many prefixes or unused REX prefixes. */
13000 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13002 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13004 prefix_name (all_prefixes
[i
], sizeflag
));
13008 insn_codep
= codep
;
13010 FETCH_DATA (info
, codep
+ 1);
13011 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13013 if (((prefixes
& PREFIX_FWAIT
)
13014 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13016 /* Handle prefixes before fwait. */
13017 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13019 (*info
->fprintf_func
) (info
->stream
, "%s ",
13020 prefix_name (all_prefixes
[i
], sizeflag
));
13021 (*info
->fprintf_func
) (info
->stream
, "fwait");
13025 if (*codep
== 0x0f)
13027 unsigned char threebyte
;
13028 FETCH_DATA (info
, codep
+ 2);
13029 threebyte
= *++codep
;
13030 dp
= &dis386_twobyte
[threebyte
];
13031 need_modrm
= twobyte_has_modrm
[*codep
];
13032 mandatory_prefix
= twobyte_has_mandatory_prefix
[*codep
];
13037 dp
= &dis386
[*codep
];
13038 need_modrm
= onebyte_has_modrm
[*codep
];
13039 mandatory_prefix
= 0;
13043 /* Save sizeflag for printing the extra prefixes later before updating
13044 it for mnemonic and operand processing. The prefix names depend
13045 only on the address mode. */
13046 orig_sizeflag
= sizeflag
;
13047 if (prefixes
& PREFIX_ADDR
)
13049 if ((prefixes
& PREFIX_DATA
))
13055 FETCH_DATA (info
, codep
+ 1);
13056 modrm
.mod
= (*codep
>> 6) & 3;
13057 modrm
.reg
= (*codep
>> 3) & 7;
13058 modrm
.rm
= *codep
& 7;
13066 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13068 get_sib (info
, sizeflag
);
13069 dofloat (sizeflag
);
13073 dp
= get_valid_dis386 (dp
, info
);
13074 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13076 get_sib (info
, sizeflag
);
13077 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13080 op_ad
= MAX_OPERANDS
- 1 - i
;
13082 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13083 /* For EVEX instruction after the last operand masking
13084 should be printed. */
13085 if (i
== 0 && vex
.evex
)
13087 /* Don't print {%k0}. */
13088 if (vex
.mask_register_specifier
)
13091 oappend (names_mask
[vex
.mask_register_specifier
]);
13101 /* Check if the REX prefix is used. */
13102 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13103 all_prefixes
[last_rex_prefix
] = 0;
13105 /* Check if the SEG prefix is used. */
13106 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13107 | PREFIX_FS
| PREFIX_GS
)) != 0
13108 && (used_prefixes
& active_seg_prefix
) != 0)
13109 all_prefixes
[last_seg_prefix
] = 0;
13111 /* Check if the ADDR prefix is used. */
13112 if ((prefixes
& PREFIX_ADDR
) != 0
13113 && (used_prefixes
& PREFIX_ADDR
) != 0)
13114 all_prefixes
[last_addr_prefix
] = 0;
13116 /* Check if the DATA prefix is used. */
13117 if ((prefixes
& PREFIX_DATA
) != 0
13118 && (used_prefixes
& PREFIX_DATA
) != 0)
13119 all_prefixes
[last_data_prefix
] = 0;
13121 /* Print the extra prefixes. */
13123 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13124 if (all_prefixes
[i
])
13127 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13130 prefix_length
+= strlen (name
) + 1;
13131 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13134 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13135 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13136 used by putop and MMX/SSE operand and may be overriden by the
13137 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13139 if (mandatory_prefix
13140 && dp
!= &bad_opcode
13142 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13144 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13146 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13148 && (used_prefixes
& PREFIX_DATA
) == 0))))
13150 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13151 return end_codep
- priv
.the_buffer
;
13154 /* Check maximum code length. */
13155 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13157 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13158 return MAX_CODE_LENGTH
;
13161 obufp
= mnemonicendp
;
13162 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13165 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13167 /* The enter and bound instructions are printed with operands in the same
13168 order as the intel book; everything else is printed in reverse order. */
13169 if (intel_syntax
|| two_source_ops
)
13173 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13174 op_txt
[i
] = op_out
[i
];
13176 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13178 op_ad
= op_index
[i
];
13179 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13180 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13181 riprel
= op_riprel
[i
];
13182 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13183 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13188 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13189 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13193 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13197 (*info
->fprintf_func
) (info
->stream
, ",");
13198 if (op_index
[i
] != -1 && !op_riprel
[i
])
13199 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13201 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13205 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13206 if (op_index
[i
] != -1 && op_riprel
[i
])
13208 (*info
->fprintf_func
) (info
->stream
, " # ");
13209 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13210 + op_address
[op_index
[i
]]), info
);
13213 return codep
- priv
.the_buffer
;
13216 static const char *float_mem
[] = {
13291 static const unsigned char float_mem_mode
[] = {
13366 #define ST { OP_ST, 0 }
13367 #define STi { OP_STi, 0 }
13369 #define FGRPd9_2 NULL, { { NULL, 0 } }
13370 #define FGRPd9_4 NULL, { { NULL, 1 } }
13371 #define FGRPd9_5 NULL, { { NULL, 2 } }
13372 #define FGRPd9_6 NULL, { { NULL, 3 } }
13373 #define FGRPd9_7 NULL, { { NULL, 4 } }
13374 #define FGRPda_5 NULL, { { NULL, 5 } }
13375 #define FGRPdb_4 NULL, { { NULL, 6 } }
13376 #define FGRPde_3 NULL, { { NULL, 7 } }
13377 #define FGRPdf_4 NULL, { { NULL, 8 } }
13379 static const struct dis386 float_reg
[][8] = {
13382 { "fadd", { ST
, STi
} },
13383 { "fmul", { ST
, STi
} },
13384 { "fcom", { STi
} },
13385 { "fcomp", { STi
} },
13386 { "fsub", { ST
, STi
} },
13387 { "fsubr", { ST
, STi
} },
13388 { "fdiv", { ST
, STi
} },
13389 { "fdivr", { ST
, STi
} },
13393 { "fld", { STi
} },
13394 { "fxch", { STi
} },
13404 { "fcmovb", { ST
, STi
} },
13405 { "fcmove", { ST
, STi
} },
13406 { "fcmovbe",{ ST
, STi
} },
13407 { "fcmovu", { ST
, STi
} },
13415 { "fcmovnb",{ ST
, STi
} },
13416 { "fcmovne",{ ST
, STi
} },
13417 { "fcmovnbe",{ ST
, STi
} },
13418 { "fcmovnu",{ ST
, STi
} },
13420 { "fucomi", { ST
, STi
} },
13421 { "fcomi", { ST
, STi
} },
13426 { "fadd", { STi
, ST
} },
13427 { "fmul", { STi
, ST
} },
13430 { "fsub!M", { STi
, ST
} },
13431 { "fsubM", { STi
, ST
} },
13432 { "fdiv!M", { STi
, ST
} },
13433 { "fdivM", { STi
, ST
} },
13437 { "ffree", { STi
} },
13439 { "fst", { STi
} },
13440 { "fstp", { STi
} },
13441 { "fucom", { STi
} },
13442 { "fucomp", { STi
} },
13448 { "faddp", { STi
, ST
} },
13449 { "fmulp", { STi
, ST
} },
13452 { "fsub!Mp", { STi
, ST
} },
13453 { "fsubMp", { STi
, ST
} },
13454 { "fdiv!Mp", { STi
, ST
} },
13455 { "fdivMp", { STi
, ST
} },
13459 { "ffreep", { STi
} },
13464 { "fucomip", { ST
, STi
} },
13465 { "fcomip", { ST
, STi
} },
13470 static char *fgrps
[][8] = {
13473 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13478 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13483 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13488 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13493 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13498 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13503 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13504 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13509 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13514 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13519 swap_operand (void)
13521 mnemonicendp
[0] = '.';
13522 mnemonicendp
[1] = 's';
13527 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13528 int sizeflag ATTRIBUTE_UNUSED
)
13530 /* Skip mod/rm byte. */
13536 dofloat (int sizeflag
)
13538 const struct dis386
*dp
;
13539 unsigned char floatop
;
13541 floatop
= codep
[-1];
13543 if (modrm
.mod
!= 3)
13545 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13547 putop (float_mem
[fp_indx
], sizeflag
);
13550 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13553 /* Skip mod/rm byte. */
13557 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13558 if (dp
->name
== NULL
)
13560 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13562 /* Instruction fnstsw is only one with strange arg. */
13563 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13564 strcpy (op_out
[0], names16
[0]);
13568 putop (dp
->name
, sizeflag
);
13573 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13578 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13582 /* Like oappend (below), but S is a string starting with '%'.
13583 In Intel syntax, the '%' is elided. */
13585 oappend_maybe_intel (const char *s
)
13587 oappend (s
+ intel_syntax
);
13591 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13593 oappend_maybe_intel ("%st");
13597 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13599 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13600 oappend_maybe_intel (scratchbuf
);
13603 /* Capital letters in template are macros. */
13605 putop (const char *in_template
, int sizeflag
)
13610 unsigned int l
= 0, len
= 1;
13613 #define SAVE_LAST(c) \
13614 if (l < len && l < sizeof (last)) \
13619 for (p
= in_template
; *p
; p
++)
13636 while (*++p
!= '|')
13637 if (*p
== '}' || *p
== '\0')
13640 /* Fall through. */
13645 while (*++p
!= '}')
13656 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13660 if (l
== 0 && len
== 1)
13665 if (sizeflag
& SUFFIX_ALWAYS
)
13678 if (address_mode
== mode_64bit
13679 && !(prefixes
& PREFIX_ADDR
))
13690 if (intel_syntax
&& !alt
)
13692 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13694 if (sizeflag
& DFLAG
)
13695 *obufp
++ = intel_syntax
? 'd' : 'l';
13697 *obufp
++ = intel_syntax
? 'w' : 's';
13698 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13702 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13705 if (modrm
.mod
== 3)
13711 if (sizeflag
& DFLAG
)
13712 *obufp
++ = intel_syntax
? 'd' : 'l';
13715 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13721 case 'E': /* For jcxz/jecxz */
13722 if (address_mode
== mode_64bit
)
13724 if (sizeflag
& AFLAG
)
13730 if (sizeflag
& AFLAG
)
13732 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13737 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13739 if (sizeflag
& AFLAG
)
13740 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13742 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13743 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13747 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13749 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13753 if (!(rex
& REX_W
))
13754 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13759 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13760 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13762 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13765 if (prefixes
& PREFIX_DS
)
13786 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13791 /* Fall through. */
13794 if (l
!= 0 || len
!= 1)
13802 if (sizeflag
& SUFFIX_ALWAYS
)
13806 if (intel_mnemonic
!= cond
)
13810 if ((prefixes
& PREFIX_FWAIT
) == 0)
13813 used_prefixes
|= PREFIX_FWAIT
;
13819 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13823 if (!(rex
& REX_W
))
13824 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13828 && address_mode
== mode_64bit
13829 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13834 /* Fall through. */
13837 if (l
== 0 && len
== 1)
13842 if ((rex
& REX_W
) == 0
13843 && (prefixes
& PREFIX_DATA
))
13845 if ((sizeflag
& DFLAG
) == 0)
13847 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13851 if ((prefixes
& PREFIX_DATA
)
13853 || (sizeflag
& SUFFIX_ALWAYS
))
13860 if (sizeflag
& DFLAG
)
13864 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13870 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13876 if ((prefixes
& PREFIX_DATA
)
13878 || (sizeflag
& SUFFIX_ALWAYS
))
13885 if (sizeflag
& DFLAG
)
13886 *obufp
++ = intel_syntax
? 'd' : 'l';
13889 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13897 if (address_mode
== mode_64bit
13898 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13900 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13904 /* Fall through. */
13907 if (l
== 0 && len
== 1)
13910 if (intel_syntax
&& !alt
)
13913 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13919 if (sizeflag
& DFLAG
)
13920 *obufp
++ = intel_syntax
? 'd' : 'l';
13923 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13929 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13935 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13950 else if (sizeflag
& DFLAG
)
13959 if (intel_syntax
&& !p
[1]
13960 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13962 if (!(rex
& REX_W
))
13963 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13966 if (l
== 0 && len
== 1)
13970 if (address_mode
== mode_64bit
13971 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13973 if (sizeflag
& SUFFIX_ALWAYS
)
13995 /* Fall through. */
13998 if (l
== 0 && len
== 1)
14003 if (sizeflag
& SUFFIX_ALWAYS
)
14009 if (sizeflag
& DFLAG
)
14013 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14027 if (address_mode
== mode_64bit
14028 && !(prefixes
& PREFIX_ADDR
))
14039 if (l
!= 0 || len
!= 1)
14044 if (need_vex
&& vex
.prefix
)
14046 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14053 if (prefixes
& PREFIX_DATA
)
14057 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14061 if (l
== 0 && len
== 1)
14063 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14074 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14082 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14084 switch (vex
.length
)
14098 if (l
== 0 && len
== 1)
14100 /* operand size flag for cwtl, cbtw */
14109 else if (sizeflag
& DFLAG
)
14113 if (!(rex
& REX_W
))
14114 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14121 && last
[0] != 'L'))
14128 if (last
[0] == 'X')
14129 *obufp
++ = vex
.w
? 'd': 's';
14131 *obufp
++ = vex
.w
? 'q': 'd';
14138 mnemonicendp
= obufp
;
14143 oappend (const char *s
)
14145 obufp
= stpcpy (obufp
, s
);
14151 /* Only print the active segment register. */
14152 if (!active_seg_prefix
)
14155 used_prefixes
|= active_seg_prefix
;
14156 switch (active_seg_prefix
)
14159 oappend_maybe_intel ("%cs:");
14162 oappend_maybe_intel ("%ds:");
14165 oappend_maybe_intel ("%ss:");
14168 oappend_maybe_intel ("%es:");
14171 oappend_maybe_intel ("%fs:");
14174 oappend_maybe_intel ("%gs:");
14182 OP_indirE (int bytemode
, int sizeflag
)
14186 OP_E (bytemode
, sizeflag
);
14190 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14192 if (address_mode
== mode_64bit
)
14200 sprintf_vma (tmp
, disp
);
14201 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14202 strcpy (buf
+ 2, tmp
+ i
);
14206 bfd_signed_vma v
= disp
;
14213 /* Check for possible overflow on 0x8000000000000000. */
14216 strcpy (buf
, "9223372036854775808");
14230 tmp
[28 - i
] = (v
% 10) + '0';
14234 strcpy (buf
, tmp
+ 29 - i
);
14240 sprintf (buf
, "0x%x", (unsigned int) disp
);
14242 sprintf (buf
, "%d", (int) disp
);
14246 /* Put DISP in BUF as signed hex number. */
14249 print_displacement (char *buf
, bfd_vma disp
)
14251 bfd_signed_vma val
= disp
;
14260 /* Check for possible overflow. */
14263 switch (address_mode
)
14266 strcpy (buf
+ j
, "0x8000000000000000");
14269 strcpy (buf
+ j
, "0x80000000");
14272 strcpy (buf
+ j
, "0x8000");
14282 sprintf_vma (tmp
, (bfd_vma
) val
);
14283 for (i
= 0; tmp
[i
] == '0'; i
++)
14285 if (tmp
[i
] == '\0')
14287 strcpy (buf
+ j
, tmp
+ i
);
14291 intel_operand_size (int bytemode
, int sizeflag
)
14295 && (bytemode
== x_mode
14296 || bytemode
== evex_half_bcst_xmmq_mode
))
14299 oappend ("QWORD PTR ");
14301 oappend ("DWORD PTR ");
14310 oappend ("BYTE PTR ");
14315 case dqw_swap_mode
:
14316 oappend ("WORD PTR ");
14319 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14321 oappend ("QWORD PTR ");
14330 oappend ("QWORD PTR ");
14333 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14334 oappend ("DWORD PTR ");
14336 oappend ("WORD PTR ");
14337 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14341 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14343 oappend ("WORD PTR ");
14344 if (!(rex
& REX_W
))
14345 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14348 if (sizeflag
& DFLAG
)
14349 oappend ("QWORD PTR ");
14351 oappend ("DWORD PTR ");
14352 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14355 case d_scalar_mode
:
14356 case d_scalar_swap_mode
:
14359 oappend ("DWORD PTR ");
14362 case q_scalar_mode
:
14363 case q_scalar_swap_mode
:
14365 oappend ("QWORD PTR ");
14368 if (address_mode
== mode_64bit
)
14369 oappend ("QWORD PTR ");
14371 oappend ("DWORD PTR ");
14374 if (sizeflag
& DFLAG
)
14375 oappend ("FWORD PTR ");
14377 oappend ("DWORD PTR ");
14378 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14381 oappend ("TBYTE PTR ");
14385 case evex_x_gscat_mode
:
14386 case evex_x_nobcst_mode
:
14389 switch (vex
.length
)
14392 oappend ("XMMWORD PTR ");
14395 oappend ("YMMWORD PTR ");
14398 oappend ("ZMMWORD PTR ");
14405 oappend ("XMMWORD PTR ");
14408 oappend ("XMMWORD PTR ");
14411 oappend ("YMMWORD PTR ");
14414 case evex_half_bcst_xmmq_mode
:
14418 switch (vex
.length
)
14421 oappend ("QWORD PTR ");
14424 oappend ("XMMWORD PTR ");
14427 oappend ("YMMWORD PTR ");
14437 switch (vex
.length
)
14442 oappend ("BYTE PTR ");
14452 switch (vex
.length
)
14457 oappend ("WORD PTR ");
14467 switch (vex
.length
)
14472 oappend ("DWORD PTR ");
14482 switch (vex
.length
)
14487 oappend ("QWORD PTR ");
14497 switch (vex
.length
)
14500 oappend ("WORD PTR ");
14503 oappend ("DWORD PTR ");
14506 oappend ("QWORD PTR ");
14516 switch (vex
.length
)
14519 oappend ("DWORD PTR ");
14522 oappend ("QWORD PTR ");
14525 oappend ("XMMWORD PTR ");
14535 switch (vex
.length
)
14538 oappend ("QWORD PTR ");
14541 oappend ("YMMWORD PTR ");
14544 oappend ("ZMMWORD PTR ");
14554 switch (vex
.length
)
14558 oappend ("XMMWORD PTR ");
14565 oappend ("OWORD PTR ");
14568 case vex_w_dq_mode
:
14569 case vex_scalar_w_dq_mode
:
14574 oappend ("QWORD PTR ");
14576 oappend ("DWORD PTR ");
14578 case vex_vsib_d_w_dq_mode
:
14579 case vex_vsib_q_w_dq_mode
:
14586 oappend ("QWORD PTR ");
14588 oappend ("DWORD PTR ");
14592 switch (vex
.length
)
14595 oappend ("XMMWORD PTR ");
14598 oappend ("YMMWORD PTR ");
14601 oappend ("ZMMWORD PTR ");
14608 case vex_vsib_q_w_d_mode
:
14609 case vex_vsib_d_w_d_mode
:
14610 if (!need_vex
|| !vex
.evex
)
14613 switch (vex
.length
)
14616 oappend ("QWORD PTR ");
14619 oappend ("XMMWORD PTR ");
14622 oappend ("YMMWORD PTR ");
14630 if (!need_vex
|| vex
.length
!= 128)
14633 oappend ("DWORD PTR ");
14635 oappend ("BYTE PTR ");
14641 oappend ("QWORD PTR ");
14643 oappend ("WORD PTR ");
14652 OP_E_register (int bytemode
, int sizeflag
)
14654 int reg
= modrm
.rm
;
14655 const char **names
;
14661 if ((sizeflag
& SUFFIX_ALWAYS
)
14662 && (bytemode
== b_swap_mode
14663 || bytemode
== v_swap_mode
14664 || bytemode
== dqw_swap_mode
))
14690 names
= address_mode
== mode_64bit
? names64
: names32
;
14696 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14709 case dqw_swap_mode
:
14715 if ((sizeflag
& DFLAG
)
14716 || (bytemode
!= v_mode
14717 && bytemode
!= v_swap_mode
))
14721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14726 names
= names_mask
;
14731 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14734 oappend (names
[reg
]);
14738 OP_E_memory (int bytemode
, int sizeflag
)
14741 int add
= (rex
& REX_B
) ? 8 : 0;
14747 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14749 && bytemode
!= x_mode
14750 && bytemode
!= xmmq_mode
14751 && bytemode
!= evex_half_bcst_xmmq_mode
)
14760 case dqw_swap_mode
:
14767 case vex_vsib_d_w_dq_mode
:
14768 case vex_vsib_d_w_d_mode
:
14769 case vex_vsib_q_w_dq_mode
:
14770 case vex_vsib_q_w_d_mode
:
14771 case evex_x_gscat_mode
:
14773 shift
= vex
.w
? 3 : 2;
14776 case evex_half_bcst_xmmq_mode
:
14780 shift
= vex
.w
? 3 : 2;
14783 /* Fall through if vex.b == 0. */
14787 case evex_x_nobcst_mode
:
14789 switch (vex
.length
)
14812 case q_scalar_mode
:
14814 case q_scalar_swap_mode
:
14820 case d_scalar_mode
:
14822 case d_scalar_swap_mode
:
14834 /* Make necessary corrections to shift for modes that need it.
14835 For these modes we currently have shift 4, 5 or 6 depending on
14836 vex.length (it corresponds to xmmword, ymmword or zmmword
14837 operand). We might want to make it 3, 4 or 5 (e.g. for
14838 xmmq_mode). In case of broadcast enabled the corrections
14839 aren't needed, as element size is always 32 or 64 bits. */
14841 && (bytemode
== xmmq_mode
14842 || bytemode
== evex_half_bcst_xmmq_mode
))
14844 else if (bytemode
== xmmqd_mode
)
14846 else if (bytemode
== xmmdw_mode
)
14848 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14856 intel_operand_size (bytemode
, sizeflag
);
14859 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14861 /* 32/64 bit address mode */
14870 int addr32flag
= !((sizeflag
& AFLAG
)
14871 || bytemode
== v_bnd_mode
14872 || bytemode
== bnd_mode
);
14873 const char **indexes64
= names64
;
14874 const char **indexes32
= names32
;
14884 vindex
= sib
.index
;
14890 case vex_vsib_d_w_dq_mode
:
14891 case vex_vsib_d_w_d_mode
:
14892 case vex_vsib_q_w_dq_mode
:
14893 case vex_vsib_q_w_d_mode
:
14903 switch (vex
.length
)
14906 indexes64
= indexes32
= names_xmm
;
14910 || bytemode
== vex_vsib_q_w_dq_mode
14911 || bytemode
== vex_vsib_q_w_d_mode
)
14912 indexes64
= indexes32
= names_ymm
;
14914 indexes64
= indexes32
= names_xmm
;
14918 || bytemode
== vex_vsib_q_w_dq_mode
14919 || bytemode
== vex_vsib_q_w_d_mode
)
14920 indexes64
= indexes32
= names_zmm
;
14922 indexes64
= indexes32
= names_ymm
;
14929 haveindex
= vindex
!= 4;
14936 rbase
= base
+ add
;
14944 if (address_mode
== mode_64bit
&& !havesib
)
14950 FETCH_DATA (the_info
, codep
+ 1);
14952 if ((disp
& 0x80) != 0)
14954 if (vex
.evex
&& shift
> 0)
14962 /* In 32bit mode, we need index register to tell [offset] from
14963 [eiz*1 + offset]. */
14964 needindex
= (havesib
14967 && address_mode
== mode_32bit
);
14968 havedisp
= (havebase
14970 || (havesib
&& (haveindex
|| scale
!= 0)));
14973 if (modrm
.mod
!= 0 || base
== 5)
14975 if (havedisp
|| riprel
)
14976 print_displacement (scratchbuf
, disp
);
14978 print_operand_value (scratchbuf
, 1, disp
);
14979 oappend (scratchbuf
);
14983 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14987 if ((havebase
|| haveindex
|| riprel
)
14988 && (bytemode
!= v_bnd_mode
)
14989 && (bytemode
!= bnd_mode
))
14990 used_prefixes
|= PREFIX_ADDR
;
14992 if (havedisp
|| (intel_syntax
&& riprel
))
14994 *obufp
++ = open_char
;
14995 if (intel_syntax
&& riprel
)
14998 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15002 oappend (address_mode
== mode_64bit
&& !addr32flag
15003 ? names64
[rbase
] : names32
[rbase
]);
15006 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15007 print index to tell base + index from base. */
15011 || (havebase
&& base
!= ESP_REG_NUM
))
15013 if (!intel_syntax
|| havebase
)
15015 *obufp
++ = separator_char
;
15019 oappend (address_mode
== mode_64bit
&& !addr32flag
15020 ? indexes64
[vindex
] : indexes32
[vindex
]);
15022 oappend (address_mode
== mode_64bit
&& !addr32flag
15023 ? index64
: index32
);
15025 *obufp
++ = scale_char
;
15027 sprintf (scratchbuf
, "%d", 1 << scale
);
15028 oappend (scratchbuf
);
15032 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15034 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15039 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15043 disp
= - (bfd_signed_vma
) disp
;
15047 print_displacement (scratchbuf
, disp
);
15049 print_operand_value (scratchbuf
, 1, disp
);
15050 oappend (scratchbuf
);
15053 *obufp
++ = close_char
;
15056 else if (intel_syntax
)
15058 if (modrm
.mod
!= 0 || base
== 5)
15060 if (!active_seg_prefix
)
15062 oappend (names_seg
[ds_reg
- es_reg
]);
15065 print_operand_value (scratchbuf
, 1, disp
);
15066 oappend (scratchbuf
);
15072 /* 16 bit address mode */
15073 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15080 if ((disp
& 0x8000) != 0)
15085 FETCH_DATA (the_info
, codep
+ 1);
15087 if ((disp
& 0x80) != 0)
15092 if ((disp
& 0x8000) != 0)
15098 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15100 print_displacement (scratchbuf
, disp
);
15101 oappend (scratchbuf
);
15104 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15106 *obufp
++ = open_char
;
15108 oappend (index16
[modrm
.rm
]);
15110 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15112 if ((bfd_signed_vma
) disp
>= 0)
15117 else if (modrm
.mod
!= 1)
15121 disp
= - (bfd_signed_vma
) disp
;
15124 print_displacement (scratchbuf
, disp
);
15125 oappend (scratchbuf
);
15128 *obufp
++ = close_char
;
15131 else if (intel_syntax
)
15133 if (!active_seg_prefix
)
15135 oappend (names_seg
[ds_reg
- es_reg
]);
15138 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15139 oappend (scratchbuf
);
15142 if (vex
.evex
&& vex
.b
15143 && (bytemode
== x_mode
15144 || bytemode
== xmmq_mode
15145 || bytemode
== evex_half_bcst_xmmq_mode
))
15148 || bytemode
== xmmq_mode
15149 || bytemode
== evex_half_bcst_xmmq_mode
)
15151 switch (vex
.length
)
15154 oappend ("{1to2}");
15157 oappend ("{1to4}");
15160 oappend ("{1to8}");
15168 switch (vex
.length
)
15171 oappend ("{1to4}");
15174 oappend ("{1to8}");
15177 oappend ("{1to16}");
15187 OP_E (int bytemode
, int sizeflag
)
15189 /* Skip mod/rm byte. */
15193 if (modrm
.mod
== 3)
15194 OP_E_register (bytemode
, sizeflag
);
15196 OP_E_memory (bytemode
, sizeflag
);
15200 OP_G (int bytemode
, int sizeflag
)
15211 oappend (names8rex
[modrm
.reg
+ add
]);
15213 oappend (names8
[modrm
.reg
+ add
]);
15216 oappend (names16
[modrm
.reg
+ add
]);
15221 oappend (names32
[modrm
.reg
+ add
]);
15224 oappend (names64
[modrm
.reg
+ add
]);
15227 oappend (names_bnd
[modrm
.reg
]);
15234 case dqw_swap_mode
:
15237 oappend (names64
[modrm
.reg
+ add
]);
15240 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15241 oappend (names32
[modrm
.reg
+ add
]);
15243 oappend (names16
[modrm
.reg
+ add
]);
15244 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15248 if (address_mode
== mode_64bit
)
15249 oappend (names64
[modrm
.reg
+ add
]);
15251 oappend (names32
[modrm
.reg
+ add
]);
15255 oappend (names_mask
[modrm
.reg
+ add
]);
15258 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15271 FETCH_DATA (the_info
, codep
+ 8);
15272 a
= *codep
++ & 0xff;
15273 a
|= (*codep
++ & 0xff) << 8;
15274 a
|= (*codep
++ & 0xff) << 16;
15275 a
|= (*codep
++ & 0xff) << 24;
15276 b
= *codep
++ & 0xff;
15277 b
|= (*codep
++ & 0xff) << 8;
15278 b
|= (*codep
++ & 0xff) << 16;
15279 b
|= (*codep
++ & 0xff) << 24;
15280 x
= a
+ ((bfd_vma
) b
<< 32);
15288 static bfd_signed_vma
15291 bfd_signed_vma x
= 0;
15293 FETCH_DATA (the_info
, codep
+ 4);
15294 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15295 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15296 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15297 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15301 static bfd_signed_vma
15304 bfd_signed_vma x
= 0;
15306 FETCH_DATA (the_info
, codep
+ 4);
15307 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15308 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15309 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15310 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15312 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15322 FETCH_DATA (the_info
, codep
+ 2);
15323 x
= *codep
++ & 0xff;
15324 x
|= (*codep
++ & 0xff) << 8;
15329 set_op (bfd_vma op
, int riprel
)
15331 op_index
[op_ad
] = op_ad
;
15332 if (address_mode
== mode_64bit
)
15334 op_address
[op_ad
] = op
;
15335 op_riprel
[op_ad
] = riprel
;
15339 /* Mask to get a 32-bit address. */
15340 op_address
[op_ad
] = op
& 0xffffffff;
15341 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15346 OP_REG (int code
, int sizeflag
)
15353 case es_reg
: case ss_reg
: case cs_reg
:
15354 case ds_reg
: case fs_reg
: case gs_reg
:
15355 oappend (names_seg
[code
- es_reg
]);
15367 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15368 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15369 s
= names16
[code
- ax_reg
+ add
];
15371 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15372 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15375 s
= names8rex
[code
- al_reg
+ add
];
15377 s
= names8
[code
- al_reg
];
15379 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15380 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15381 if (address_mode
== mode_64bit
15382 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15384 s
= names64
[code
- rAX_reg
+ add
];
15387 code
+= eAX_reg
- rAX_reg
;
15388 /* Fall through. */
15389 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15390 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15393 s
= names64
[code
- eAX_reg
+ add
];
15396 if (sizeflag
& DFLAG
)
15397 s
= names32
[code
- eAX_reg
+ add
];
15399 s
= names16
[code
- eAX_reg
+ add
];
15400 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15404 s
= INTERNAL_DISASSEMBLER_ERROR
;
15411 OP_IMREG (int code
, int sizeflag
)
15423 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15424 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15425 s
= names16
[code
- ax_reg
];
15427 case es_reg
: case ss_reg
: case cs_reg
:
15428 case ds_reg
: case fs_reg
: case gs_reg
:
15429 s
= names_seg
[code
- es_reg
];
15431 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15432 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15435 s
= names8rex
[code
- al_reg
];
15437 s
= names8
[code
- al_reg
];
15439 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15440 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15443 s
= names64
[code
- eAX_reg
];
15446 if (sizeflag
& DFLAG
)
15447 s
= names32
[code
- eAX_reg
];
15449 s
= names16
[code
- eAX_reg
];
15450 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15453 case z_mode_ax_reg
:
15454 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15458 if (!(rex
& REX_W
))
15459 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15462 s
= INTERNAL_DISASSEMBLER_ERROR
;
15469 OP_I (int bytemode
, int sizeflag
)
15472 bfd_signed_vma mask
= -1;
15477 FETCH_DATA (the_info
, codep
+ 1);
15482 if (address_mode
== mode_64bit
)
15487 /* Fall through. */
15494 if (sizeflag
& DFLAG
)
15504 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15516 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15521 scratchbuf
[0] = '$';
15522 print_operand_value (scratchbuf
+ 1, 1, op
);
15523 oappend_maybe_intel (scratchbuf
);
15524 scratchbuf
[0] = '\0';
15528 OP_I64 (int bytemode
, int sizeflag
)
15531 bfd_signed_vma mask
= -1;
15533 if (address_mode
!= mode_64bit
)
15535 OP_I (bytemode
, sizeflag
);
15542 FETCH_DATA (the_info
, codep
+ 1);
15552 if (sizeflag
& DFLAG
)
15562 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15570 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15575 scratchbuf
[0] = '$';
15576 print_operand_value (scratchbuf
+ 1, 1, op
);
15577 oappend_maybe_intel (scratchbuf
);
15578 scratchbuf
[0] = '\0';
15582 OP_sI (int bytemode
, int sizeflag
)
15590 FETCH_DATA (the_info
, codep
+ 1);
15592 if ((op
& 0x80) != 0)
15594 if (bytemode
== b_T_mode
)
15596 if (address_mode
!= mode_64bit
15597 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15599 /* The operand-size prefix is overridden by a REX prefix. */
15600 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15608 if (!(rex
& REX_W
))
15610 if (sizeflag
& DFLAG
)
15618 /* The operand-size prefix is overridden by a REX prefix. */
15619 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15625 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15629 scratchbuf
[0] = '$';
15630 print_operand_value (scratchbuf
+ 1, 1, op
);
15631 oappend_maybe_intel (scratchbuf
);
15635 OP_J (int bytemode
, int sizeflag
)
15639 bfd_vma segment
= 0;
15644 FETCH_DATA (the_info
, codep
+ 1);
15646 if ((disp
& 0x80) != 0)
15651 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15656 if ((disp
& 0x8000) != 0)
15658 /* In 16bit mode, address is wrapped around at 64k within
15659 the same segment. Otherwise, a data16 prefix on a jump
15660 instruction means that the pc is masked to 16 bits after
15661 the displacement is added! */
15663 if ((prefixes
& PREFIX_DATA
) == 0)
15664 segment
= ((start_pc
+ codep
- start_codep
)
15665 & ~((bfd_vma
) 0xffff));
15667 if (!(rex
& REX_W
))
15668 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15671 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15674 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15676 print_operand_value (scratchbuf
, 1, disp
);
15677 oappend (scratchbuf
);
15681 OP_SEG (int bytemode
, int sizeflag
)
15683 if (bytemode
== w_mode
)
15684 oappend (names_seg
[modrm
.reg
]);
15686 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15690 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15694 if (sizeflag
& DFLAG
)
15704 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15706 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15708 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15709 oappend (scratchbuf
);
15713 OP_OFF (int bytemode
, int sizeflag
)
15717 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15718 intel_operand_size (bytemode
, sizeflag
);
15721 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15728 if (!active_seg_prefix
)
15730 oappend (names_seg
[ds_reg
- es_reg
]);
15734 print_operand_value (scratchbuf
, 1, off
);
15735 oappend (scratchbuf
);
15739 OP_OFF64 (int bytemode
, int sizeflag
)
15743 if (address_mode
!= mode_64bit
15744 || (prefixes
& PREFIX_ADDR
))
15746 OP_OFF (bytemode
, sizeflag
);
15750 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15751 intel_operand_size (bytemode
, sizeflag
);
15758 if (!active_seg_prefix
)
15760 oappend (names_seg
[ds_reg
- es_reg
]);
15764 print_operand_value (scratchbuf
, 1, off
);
15765 oappend (scratchbuf
);
15769 ptr_reg (int code
, int sizeflag
)
15773 *obufp
++ = open_char
;
15774 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15775 if (address_mode
== mode_64bit
)
15777 if (!(sizeflag
& AFLAG
))
15778 s
= names32
[code
- eAX_reg
];
15780 s
= names64
[code
- eAX_reg
];
15782 else if (sizeflag
& AFLAG
)
15783 s
= names32
[code
- eAX_reg
];
15785 s
= names16
[code
- eAX_reg
];
15787 *obufp
++ = close_char
;
15792 OP_ESreg (int code
, int sizeflag
)
15798 case 0x6d: /* insw/insl */
15799 intel_operand_size (z_mode
, sizeflag
);
15801 case 0xa5: /* movsw/movsl/movsq */
15802 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15803 case 0xab: /* stosw/stosl */
15804 case 0xaf: /* scasw/scasl */
15805 intel_operand_size (v_mode
, sizeflag
);
15808 intel_operand_size (b_mode
, sizeflag
);
15811 oappend_maybe_intel ("%es:");
15812 ptr_reg (code
, sizeflag
);
15816 OP_DSreg (int code
, int sizeflag
)
15822 case 0x6f: /* outsw/outsl */
15823 intel_operand_size (z_mode
, sizeflag
);
15825 case 0xa5: /* movsw/movsl/movsq */
15826 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15827 case 0xad: /* lodsw/lodsl/lodsq */
15828 intel_operand_size (v_mode
, sizeflag
);
15831 intel_operand_size (b_mode
, sizeflag
);
15834 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15835 default segment register DS is printed. */
15836 if (!active_seg_prefix
)
15837 active_seg_prefix
= PREFIX_DS
;
15839 ptr_reg (code
, sizeflag
);
15843 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15851 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15853 all_prefixes
[last_lock_prefix
] = 0;
15854 used_prefixes
|= PREFIX_LOCK
;
15859 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15860 oappend_maybe_intel (scratchbuf
);
15864 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15873 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15875 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15876 oappend (scratchbuf
);
15880 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15882 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15883 oappend_maybe_intel (scratchbuf
);
15887 OP_R (int bytemode
, int sizeflag
)
15889 /* Skip mod/rm byte. */
15892 OP_E_register (bytemode
, sizeflag
);
15896 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15898 int reg
= modrm
.reg
;
15899 const char **names
;
15901 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15902 if (prefixes
& PREFIX_DATA
)
15911 oappend (names
[reg
]);
15915 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15917 int reg
= modrm
.reg
;
15918 const char **names
;
15930 && bytemode
!= xmm_mode
15931 && bytemode
!= xmmq_mode
15932 && bytemode
!= evex_half_bcst_xmmq_mode
15933 && bytemode
!= ymm_mode
15934 && bytemode
!= scalar_mode
)
15936 switch (vex
.length
)
15943 || (bytemode
!= vex_vsib_q_w_dq_mode
15944 && bytemode
!= vex_vsib_q_w_d_mode
))
15956 else if (bytemode
== xmmq_mode
15957 || bytemode
== evex_half_bcst_xmmq_mode
)
15959 switch (vex
.length
)
15972 else if (bytemode
== ymm_mode
)
15976 oappend (names
[reg
]);
15980 OP_EM (int bytemode
, int sizeflag
)
15983 const char **names
;
15985 if (modrm
.mod
!= 3)
15988 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15990 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15991 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15993 OP_E (bytemode
, sizeflag
);
15997 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16000 /* Skip mod/rm byte. */
16003 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16005 if (prefixes
& PREFIX_DATA
)
16014 oappend (names
[reg
]);
16017 /* cvt* are the only instructions in sse2 which have
16018 both SSE and MMX operands and also have 0x66 prefix
16019 in their opcode. 0x66 was originally used to differentiate
16020 between SSE and MMX instruction(operands). So we have to handle the
16021 cvt* separately using OP_EMC and OP_MXC */
16023 OP_EMC (int bytemode
, int sizeflag
)
16025 if (modrm
.mod
!= 3)
16027 if (intel_syntax
&& bytemode
== v_mode
)
16029 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16030 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16032 OP_E (bytemode
, sizeflag
);
16036 /* Skip mod/rm byte. */
16039 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16040 oappend (names_mm
[modrm
.rm
]);
16044 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16046 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16047 oappend (names_mm
[modrm
.reg
]);
16051 OP_EX (int bytemode
, int sizeflag
)
16054 const char **names
;
16056 /* Skip mod/rm byte. */
16060 if (modrm
.mod
!= 3)
16062 OP_E_memory (bytemode
, sizeflag
);
16077 if ((sizeflag
& SUFFIX_ALWAYS
)
16078 && (bytemode
== x_swap_mode
16079 || bytemode
== d_swap_mode
16080 || bytemode
== dqw_swap_mode
16081 || bytemode
== d_scalar_swap_mode
16082 || bytemode
== q_swap_mode
16083 || bytemode
== q_scalar_swap_mode
))
16087 && bytemode
!= xmm_mode
16088 && bytemode
!= xmmdw_mode
16089 && bytemode
!= xmmqd_mode
16090 && bytemode
!= xmm_mb_mode
16091 && bytemode
!= xmm_mw_mode
16092 && bytemode
!= xmm_md_mode
16093 && bytemode
!= xmm_mq_mode
16094 && bytemode
!= xmm_mdq_mode
16095 && bytemode
!= xmmq_mode
16096 && bytemode
!= evex_half_bcst_xmmq_mode
16097 && bytemode
!= ymm_mode
16098 && bytemode
!= d_scalar_mode
16099 && bytemode
!= d_scalar_swap_mode
16100 && bytemode
!= q_scalar_mode
16101 && bytemode
!= q_scalar_swap_mode
16102 && bytemode
!= vex_scalar_w_dq_mode
)
16104 switch (vex
.length
)
16119 else if (bytemode
== xmmq_mode
16120 || bytemode
== evex_half_bcst_xmmq_mode
)
16122 switch (vex
.length
)
16135 else if (bytemode
== ymm_mode
)
16139 oappend (names
[reg
]);
16143 OP_MS (int bytemode
, int sizeflag
)
16145 if (modrm
.mod
== 3)
16146 OP_EM (bytemode
, sizeflag
);
16152 OP_XS (int bytemode
, int sizeflag
)
16154 if (modrm
.mod
== 3)
16155 OP_EX (bytemode
, sizeflag
);
16161 OP_M (int bytemode
, int sizeflag
)
16163 if (modrm
.mod
== 3)
16164 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16167 OP_E (bytemode
, sizeflag
);
16171 OP_0f07 (int bytemode
, int sizeflag
)
16173 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16176 OP_E (bytemode
, sizeflag
);
16179 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16180 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16183 NOP_Fixup1 (int bytemode
, int sizeflag
)
16185 if ((prefixes
& PREFIX_DATA
) != 0
16188 && address_mode
== mode_64bit
))
16189 OP_REG (bytemode
, sizeflag
);
16191 strcpy (obuf
, "nop");
16195 NOP_Fixup2 (int bytemode
, int sizeflag
)
16197 if ((prefixes
& PREFIX_DATA
) != 0
16200 && address_mode
== mode_64bit
))
16201 OP_IMREG (bytemode
, sizeflag
);
16204 static const char *const Suffix3DNow
[] = {
16205 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16206 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16207 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16208 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16209 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16210 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16211 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16212 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16213 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16214 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16215 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16216 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16217 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16218 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16219 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16220 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16221 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16222 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16223 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16224 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16225 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16226 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16227 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16228 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16229 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16230 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16231 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16232 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16233 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16234 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16235 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16236 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16237 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16238 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16239 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16240 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16241 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16242 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16243 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16244 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16245 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16246 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16247 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16248 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16249 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16250 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16251 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16252 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16253 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16254 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16255 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16256 /* CC */ NULL
, NULL
, NULL
, NULL
,
16257 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16258 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16259 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16260 /* DC */ NULL
, NULL
, NULL
, NULL
,
16261 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16262 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16263 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16264 /* EC */ NULL
, NULL
, NULL
, NULL
,
16265 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16266 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16267 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16268 /* FC */ NULL
, NULL
, NULL
, NULL
,
16272 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16274 const char *mnemonic
;
16276 FETCH_DATA (the_info
, codep
+ 1);
16277 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16278 place where an 8-bit immediate would normally go. ie. the last
16279 byte of the instruction. */
16280 obufp
= mnemonicendp
;
16281 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16283 oappend (mnemonic
);
16286 /* Since a variable sized modrm/sib chunk is between the start
16287 of the opcode (0x0f0f) and the opcode suffix, we need to do
16288 all the modrm processing first, and don't know until now that
16289 we have a bad opcode. This necessitates some cleaning up. */
16290 op_out
[0][0] = '\0';
16291 op_out
[1][0] = '\0';
16294 mnemonicendp
= obufp
;
16297 static struct op simd_cmp_op
[] =
16299 { STRING_COMMA_LEN ("eq") },
16300 { STRING_COMMA_LEN ("lt") },
16301 { STRING_COMMA_LEN ("le") },
16302 { STRING_COMMA_LEN ("unord") },
16303 { STRING_COMMA_LEN ("neq") },
16304 { STRING_COMMA_LEN ("nlt") },
16305 { STRING_COMMA_LEN ("nle") },
16306 { STRING_COMMA_LEN ("ord") }
16310 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16312 unsigned int cmp_type
;
16314 FETCH_DATA (the_info
, codep
+ 1);
16315 cmp_type
= *codep
++ & 0xff;
16316 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16319 char *p
= mnemonicendp
- 2;
16323 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16324 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16328 /* We have a reserved extension byte. Output it directly. */
16329 scratchbuf
[0] = '$';
16330 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16331 oappend_maybe_intel (scratchbuf
);
16332 scratchbuf
[0] = '\0';
16337 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16338 int sizeflag ATTRIBUTE_UNUSED
)
16340 /* mwait %eax,%ecx */
16343 const char **names
= (address_mode
== mode_64bit
16344 ? names64
: names32
);
16345 strcpy (op_out
[0], names
[0]);
16346 strcpy (op_out
[1], names
[1]);
16347 two_source_ops
= 1;
16349 /* Skip mod/rm byte. */
16355 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16356 int sizeflag ATTRIBUTE_UNUSED
)
16358 /* monitor %eax,%ecx,%edx" */
16361 const char **op1_names
;
16362 const char **names
= (address_mode
== mode_64bit
16363 ? names64
: names32
);
16365 if (!(prefixes
& PREFIX_ADDR
))
16366 op1_names
= (address_mode
== mode_16bit
16367 ? names16
: names
);
16370 /* Remove "addr16/addr32". */
16371 all_prefixes
[last_addr_prefix
] = 0;
16372 op1_names
= (address_mode
!= mode_32bit
16373 ? names32
: names16
);
16374 used_prefixes
|= PREFIX_ADDR
;
16376 strcpy (op_out
[0], op1_names
[0]);
16377 strcpy (op_out
[1], names
[1]);
16378 strcpy (op_out
[2], names
[2]);
16379 two_source_ops
= 1;
16381 /* Skip mod/rm byte. */
16389 /* Throw away prefixes and 1st. opcode byte. */
16390 codep
= insn_codep
+ 1;
16395 REP_Fixup (int bytemode
, int sizeflag
)
16397 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16399 if (prefixes
& PREFIX_REPZ
)
16400 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16407 OP_IMREG (bytemode
, sizeflag
);
16410 OP_ESreg (bytemode
, sizeflag
);
16413 OP_DSreg (bytemode
, sizeflag
);
16421 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16425 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16427 if (prefixes
& PREFIX_REPNZ
)
16428 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16431 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16432 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16436 HLE_Fixup1 (int bytemode
, int sizeflag
)
16439 && (prefixes
& PREFIX_LOCK
) != 0)
16441 if (prefixes
& PREFIX_REPZ
)
16442 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16443 if (prefixes
& PREFIX_REPNZ
)
16444 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16447 OP_E (bytemode
, sizeflag
);
16450 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16451 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16455 HLE_Fixup2 (int bytemode
, int sizeflag
)
16457 if (modrm
.mod
!= 3)
16459 if (prefixes
& PREFIX_REPZ
)
16460 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16461 if (prefixes
& PREFIX_REPNZ
)
16462 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16465 OP_E (bytemode
, sizeflag
);
16468 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16469 "xrelease" for memory operand. No check for LOCK prefix. */
16472 HLE_Fixup3 (int bytemode
, int sizeflag
)
16475 && last_repz_prefix
> last_repnz_prefix
16476 && (prefixes
& PREFIX_REPZ
) != 0)
16477 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16479 OP_E (bytemode
, sizeflag
);
16483 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16488 /* Change cmpxchg8b to cmpxchg16b. */
16489 char *p
= mnemonicendp
- 2;
16490 mnemonicendp
= stpcpy (p
, "16b");
16493 else if ((prefixes
& PREFIX_LOCK
) != 0)
16495 if (prefixes
& PREFIX_REPZ
)
16496 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16497 if (prefixes
& PREFIX_REPNZ
)
16498 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16501 OP_M (bytemode
, sizeflag
);
16505 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16507 const char **names
;
16511 switch (vex
.length
)
16525 oappend (names
[reg
]);
16529 CRC32_Fixup (int bytemode
, int sizeflag
)
16531 /* Add proper suffix to "crc32". */
16532 char *p
= mnemonicendp
;
16551 if (sizeflag
& DFLAG
)
16555 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16559 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16566 if (modrm
.mod
== 3)
16570 /* Skip mod/rm byte. */
16575 add
= (rex
& REX_B
) ? 8 : 0;
16576 if (bytemode
== b_mode
)
16580 oappend (names8rex
[modrm
.rm
+ add
]);
16582 oappend (names8
[modrm
.rm
+ add
]);
16588 oappend (names64
[modrm
.rm
+ add
]);
16589 else if ((prefixes
& PREFIX_DATA
))
16590 oappend (names16
[modrm
.rm
+ add
]);
16592 oappend (names32
[modrm
.rm
+ add
]);
16596 OP_E (bytemode
, sizeflag
);
16600 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16602 /* Add proper suffix to "fxsave" and "fxrstor". */
16606 char *p
= mnemonicendp
;
16612 OP_M (bytemode
, sizeflag
);
16615 /* Display the destination register operand for instructions with
16619 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16622 const char **names
;
16630 reg
= vex
.register_specifier
;
16637 if (bytemode
== vex_scalar_mode
)
16639 oappend (names_xmm
[reg
]);
16643 switch (vex
.length
)
16650 case vex_vsib_q_w_dq_mode
:
16651 case vex_vsib_q_w_d_mode
:
16662 names
= names_mask
;
16676 case vex_vsib_q_w_dq_mode
:
16677 case vex_vsib_q_w_d_mode
:
16678 names
= vex
.w
? names_ymm
: names_xmm
;
16682 names
= names_mask
;
16696 oappend (names
[reg
]);
16699 /* Get the VEX immediate byte without moving codep. */
16701 static unsigned char
16702 get_vex_imm8 (int sizeflag
, int opnum
)
16704 int bytes_before_imm
= 0;
16706 if (modrm
.mod
!= 3)
16708 /* There are SIB/displacement bytes. */
16709 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16711 /* 32/64 bit address mode */
16712 int base
= modrm
.rm
;
16714 /* Check SIB byte. */
16717 FETCH_DATA (the_info
, codep
+ 1);
16719 /* When decoding the third source, don't increase
16720 bytes_before_imm as this has already been incremented
16721 by one in OP_E_memory while decoding the second
16724 bytes_before_imm
++;
16727 /* Don't increase bytes_before_imm when decoding the third source,
16728 it has already been incremented by OP_E_memory while decoding
16729 the second source operand. */
16735 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16736 SIB == 5, there is a 4 byte displacement. */
16738 /* No displacement. */
16741 /* 4 byte displacement. */
16742 bytes_before_imm
+= 4;
16745 /* 1 byte displacement. */
16746 bytes_before_imm
++;
16753 /* 16 bit address mode */
16754 /* Don't increase bytes_before_imm when decoding the third source,
16755 it has already been incremented by OP_E_memory while decoding
16756 the second source operand. */
16762 /* When modrm.rm == 6, there is a 2 byte displacement. */
16764 /* No displacement. */
16767 /* 2 byte displacement. */
16768 bytes_before_imm
+= 2;
16771 /* 1 byte displacement: when decoding the third source,
16772 don't increase bytes_before_imm as this has already
16773 been incremented by one in OP_E_memory while decoding
16774 the second source operand. */
16776 bytes_before_imm
++;
16784 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16785 return codep
[bytes_before_imm
];
16789 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16791 const char **names
;
16793 if (reg
== -1 && modrm
.mod
!= 3)
16795 OP_E_memory (bytemode
, sizeflag
);
16807 else if (reg
> 7 && address_mode
!= mode_64bit
)
16811 switch (vex
.length
)
16822 oappend (names
[reg
]);
16826 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16829 static unsigned char vex_imm8
;
16831 if (vex_w_done
== 0)
16835 /* Skip mod/rm byte. */
16839 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16842 reg
= vex_imm8
>> 4;
16844 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16846 else if (vex_w_done
== 1)
16851 reg
= vex_imm8
>> 4;
16853 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16857 /* Output the imm8 directly. */
16858 scratchbuf
[0] = '$';
16859 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16860 oappend_maybe_intel (scratchbuf
);
16861 scratchbuf
[0] = '\0';
16867 OP_Vex_2src (int bytemode
, int sizeflag
)
16869 if (modrm
.mod
== 3)
16871 int reg
= modrm
.rm
;
16875 oappend (names_xmm
[reg
]);
16880 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16882 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16883 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16885 OP_E (bytemode
, sizeflag
);
16890 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16892 if (modrm
.mod
== 3)
16894 /* Skip mod/rm byte. */
16900 oappend (names_xmm
[vex
.register_specifier
]);
16902 OP_Vex_2src (bytemode
, sizeflag
);
16906 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16909 OP_Vex_2src (bytemode
, sizeflag
);
16911 oappend (names_xmm
[vex
.register_specifier
]);
16915 OP_EX_VexW (int bytemode
, int sizeflag
)
16923 /* Skip mod/rm byte. */
16928 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16933 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16936 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16940 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16941 int sizeflag ATTRIBUTE_UNUSED
)
16943 /* Skip the immediate byte and check for invalid bits. */
16944 FETCH_DATA (the_info
, codep
+ 1);
16945 if (*codep
++ & 0xf)
16950 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16953 const char **names
;
16955 FETCH_DATA (the_info
, codep
+ 1);
16958 if (bytemode
!= x_mode
)
16965 if (reg
> 7 && address_mode
!= mode_64bit
)
16968 switch (vex
.length
)
16979 oappend (names
[reg
]);
16983 OP_XMM_VexW (int bytemode
, int sizeflag
)
16985 /* Turn off the REX.W bit since it is used for swapping operands
16988 OP_XMM (bytemode
, sizeflag
);
16992 OP_EX_Vex (int bytemode
, int sizeflag
)
16994 if (modrm
.mod
!= 3)
16996 if (vex
.register_specifier
!= 0)
17000 OP_EX (bytemode
, sizeflag
);
17004 OP_XMM_Vex (int bytemode
, int sizeflag
)
17006 if (modrm
.mod
!= 3)
17008 if (vex
.register_specifier
!= 0)
17012 OP_XMM (bytemode
, sizeflag
);
17016 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17018 switch (vex
.length
)
17021 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17024 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17031 static struct op vex_cmp_op
[] =
17033 { STRING_COMMA_LEN ("eq") },
17034 { STRING_COMMA_LEN ("lt") },
17035 { STRING_COMMA_LEN ("le") },
17036 { STRING_COMMA_LEN ("unord") },
17037 { STRING_COMMA_LEN ("neq") },
17038 { STRING_COMMA_LEN ("nlt") },
17039 { STRING_COMMA_LEN ("nle") },
17040 { STRING_COMMA_LEN ("ord") },
17041 { STRING_COMMA_LEN ("eq_uq") },
17042 { STRING_COMMA_LEN ("nge") },
17043 { STRING_COMMA_LEN ("ngt") },
17044 { STRING_COMMA_LEN ("false") },
17045 { STRING_COMMA_LEN ("neq_oq") },
17046 { STRING_COMMA_LEN ("ge") },
17047 { STRING_COMMA_LEN ("gt") },
17048 { STRING_COMMA_LEN ("true") },
17049 { STRING_COMMA_LEN ("eq_os") },
17050 { STRING_COMMA_LEN ("lt_oq") },
17051 { STRING_COMMA_LEN ("le_oq") },
17052 { STRING_COMMA_LEN ("unord_s") },
17053 { STRING_COMMA_LEN ("neq_us") },
17054 { STRING_COMMA_LEN ("nlt_uq") },
17055 { STRING_COMMA_LEN ("nle_uq") },
17056 { STRING_COMMA_LEN ("ord_s") },
17057 { STRING_COMMA_LEN ("eq_us") },
17058 { STRING_COMMA_LEN ("nge_uq") },
17059 { STRING_COMMA_LEN ("ngt_uq") },
17060 { STRING_COMMA_LEN ("false_os") },
17061 { STRING_COMMA_LEN ("neq_os") },
17062 { STRING_COMMA_LEN ("ge_oq") },
17063 { STRING_COMMA_LEN ("gt_oq") },
17064 { STRING_COMMA_LEN ("true_us") },
17068 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17070 unsigned int cmp_type
;
17072 FETCH_DATA (the_info
, codep
+ 1);
17073 cmp_type
= *codep
++ & 0xff;
17074 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17077 char *p
= mnemonicendp
- 2;
17081 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17082 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17086 /* We have a reserved extension byte. Output it directly. */
17087 scratchbuf
[0] = '$';
17088 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17089 oappend_maybe_intel (scratchbuf
);
17090 scratchbuf
[0] = '\0';
17095 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17096 int sizeflag ATTRIBUTE_UNUSED
)
17098 unsigned int cmp_type
;
17103 FETCH_DATA (the_info
, codep
+ 1);
17104 cmp_type
= *codep
++ & 0xff;
17105 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17106 If it's the case, print suffix, otherwise - print the immediate. */
17107 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17112 char *p
= mnemonicendp
- 2;
17114 /* vpcmp* can have both one- and two-lettered suffix. */
17128 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17129 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17133 /* We have a reserved extension byte. Output it directly. */
17134 scratchbuf
[0] = '$';
17135 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17136 oappend_maybe_intel (scratchbuf
);
17137 scratchbuf
[0] = '\0';
17141 static const struct op pclmul_op
[] =
17143 { STRING_COMMA_LEN ("lql") },
17144 { STRING_COMMA_LEN ("hql") },
17145 { STRING_COMMA_LEN ("lqh") },
17146 { STRING_COMMA_LEN ("hqh") }
17150 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17151 int sizeflag ATTRIBUTE_UNUSED
)
17153 unsigned int pclmul_type
;
17155 FETCH_DATA (the_info
, codep
+ 1);
17156 pclmul_type
= *codep
++ & 0xff;
17157 switch (pclmul_type
)
17168 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17171 char *p
= mnemonicendp
- 3;
17176 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17177 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17181 /* We have a reserved extension byte. Output it directly. */
17182 scratchbuf
[0] = '$';
17183 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17184 oappend_maybe_intel (scratchbuf
);
17185 scratchbuf
[0] = '\0';
17190 MOVBE_Fixup (int bytemode
, int sizeflag
)
17192 /* Add proper suffix to "movbe". */
17193 char *p
= mnemonicendp
;
17202 if (sizeflag
& SUFFIX_ALWAYS
)
17208 if (sizeflag
& DFLAG
)
17212 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17217 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17224 OP_M (bytemode
, sizeflag
);
17228 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17231 const char **names
;
17233 /* Skip mod/rm byte. */
17247 oappend (names
[reg
]);
17251 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17253 const char **names
;
17260 oappend (names
[vex
.register_specifier
]);
17264 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17267 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17271 if ((rex
& REX_R
) != 0 || !vex
.r
)
17277 oappend (names_mask
[modrm
.reg
]);
17281 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17284 || (bytemode
!= evex_rounding_mode
17285 && bytemode
!= evex_sae_mode
))
17287 if (modrm
.mod
== 3 && vex
.b
)
17290 case evex_rounding_mode
:
17291 oappend (names_rounding
[vex
.ll
]);
17293 case evex_sae_mode
: