opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iq { OP_I, q_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 389 #define EXq { OP_EX, q_mode }
 390 #define EXqScalar { OP_EX, q_scalar_mode }
 391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 392 #define EXqS { OP_EX, q_swap_mode }
 393 #define EXx { OP_EX, x_mode }
 394 #define EXxS { OP_EX, x_swap_mode }
 395 #define EXxmm { OP_EX, xmm_mode }
 396 #define EXymm { OP_EX, ymm_mode }
 397 #define EXxmmq { OP_EX, xmmq_mode }
 398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 401 #define EXxmm_md { OP_EX, xmm_md_mode }
 402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVex { OP_EX_Vex, d_mode }
 429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVex { OP_EX_Vex, q_mode }
 432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 434 #define EXVexW { OP_EX_VexW, x_mode }
 435 #define EXdVexW { OP_EX_VexW, d_mode }
 436 #define EXqVexW { OP_EX_VexW, q_mode }
 437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 438 #define XMVex { OP_XMM_Vex, 0 }
 439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 440 #define XMVexW { OP_XMM_VexW, 0 }
 441 #define XMVexI4 { OP_REG_VexI4, x_mode }
 442 #define PCLMUL { PCLMUL_Fixup, 0 }
 443 #define VCMP { VCMP_Fixup, 0 }
 444 #define VPCMP { VPCMP_Fixup, 0 }
 445 #define VPCOM { VPCOM_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 449 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 450
 451 #define XMask { OP_Mask, mask_mode }
 452 #define MaskG { OP_G, mask_mode }
 453 #define MaskE { OP_E, mask_mode }
 454 #define MaskBDE { OP_E, mask_bd_mode }
 455 #define MaskR { OP_R, mask_mode }
 456 #define MaskVex { OP_VEX, mask_mode }
 457
 458 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 459 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 460 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 461 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 462
 463 /* Used handle "rep" prefix for string instructions.  */
 464 #define Xbr { REP_Fixup, eSI_reg }
 465 #define Xvr { REP_Fixup, eSI_reg }
 466 #define Ybr { REP_Fixup, eDI_reg }
 467 #define Yvr { REP_Fixup, eDI_reg }
 468 #define Yzr { REP_Fixup, eDI_reg }
 469 #define indirDXr { REP_Fixup, indir_dx_reg }
 470 #define ALr { REP_Fixup, al_reg }
 471 #define eAXr { REP_Fixup, eAX_reg }
 472
 473 /* Used handle HLE prefix for lockable instructions.  */
 474 #define Ebh1 { HLE_Fixup1, b_mode }
 475 #define Evh1 { HLE_Fixup1, v_mode }
 476 #define Ebh2 { HLE_Fixup2, b_mode }
 477 #define Evh2 { HLE_Fixup2, v_mode }
 478 #define Ebh3 { HLE_Fixup3, b_mode }
 479 #define Evh3 { HLE_Fixup3, v_mode }
 480
 481 #define BND { BND_Fixup, 0 }
 482 #define NOTRACK { NOTRACK_Fixup, 0 }
 483
 484 #define cond_jump_flag { NULL, cond_jump_mode }
 485 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 486
 487 /* bits in sizeflag */
 488 #define SUFFIX_ALWAYS 4
 489 #define AFLAG 2
 490 #define DFLAG 1
 491
 492 enum
 493 {
 494   /* byte operand */
 495   b_mode = 1,
 496   /* byte operand with operand swapped */
 497   b_swap_mode,
 498   /* byte operand, sign extend like 'T' suffix */
 499   b_T_mode,
 500   /* operand size depends on prefixes */
 501   v_mode,
 502   /* operand size depends on prefixes with operand swapped */
 503   v_swap_mode,
 504   /* operand size depends on address prefix */
 505   va_mode,
 506   /* word operand */
 507   w_mode,
 508   /* double word operand  */
 509   d_mode,
 510   /* double word operand with operand swapped */
 511   d_swap_mode,
 512   /* quad word operand */
 513   q_mode,
 514   /* quad word operand with operand swapped */
 515   q_swap_mode,
 516   /* ten-byte operand */
 517   t_mode,
 518   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 519      broadcast enabled.  */
 520   x_mode,
 521   /* Similar to x_mode, but with different EVEX mem shifts.  */
 522   evex_x_gscat_mode,
 523   /* Similar to x_mode, but with disabled broadcast.  */
 524   evex_x_nobcst_mode,
 525   /* Similar to x_mode, but with operands swapped and disabled broadcast
 526      in EVEX.  */
 527   x_swap_mode,
 528   /* 16-byte XMM operand */
 529   xmm_mode,
 530   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 531      memory operand (depending on vector length).  Broadcast isn't
 532      allowed.  */
 533   xmmq_mode,
 534   /* Same as xmmq_mode, but broadcast is allowed.  */
 535   evex_half_bcst_xmmq_mode,
 536   /* XMM register or byte memory operand */
 537   xmm_mb_mode,
 538   /* XMM register or word memory operand */
 539   xmm_mw_mode,
 540   /* XMM register or double word memory operand */
 541   xmm_md_mode,
 542   /* XMM register or quad word memory operand */
 543   xmm_mq_mode,
 544   /* XMM register or double/quad word memory operand, depending on
 545      VEX.W.  */
 546   xmm_mdq_mode,
 547   /* 16-byte XMM, word, double word or quad word operand.  */
 548   xmmdw_mode,
 549   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 550   xmmqd_mode,
 551   /* 32-byte YMM operand */
 552   ymm_mode,
 553   /* quad word, ymmword or zmmword memory operand.  */
 554   ymmq_mode,
 555   /* 32-byte YMM or 16-byte word operand */
 556   ymmxmm_mode,
 557   /* d_mode in 32bit, q_mode in 64bit mode.  */
 558   m_mode,
 559   /* pair of v_mode operands */
 560   a_mode,
 561   cond_jump_mode,
 562   loop_jcxz_mode,
 563   v_bnd_mode,
 564   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 565   v_bndmk_mode,
 566   /* operand size depends on REX prefixes.  */
 567   dq_mode,
 568   /* registers like dq_mode, memory like w_mode.  */
 569   dqw_mode,
 570   /* bounds operand */
 571   bnd_mode,
 572   /* bounds operand with operand swapped */
 573   bnd_swap_mode,
 574   /* 4- or 6-byte pointer operand */
 575   f_mode,
 576   const_1_mode,
 577   /* v_mode for indirect branch opcodes.  */
 578   indir_v_mode,
 579   /* v_mode for stack-related opcodes.  */
 580   stack_v_mode,
 581   /* non-quad operand size depends on prefixes */
 582   z_mode,
 583   /* 16-byte operand */
 584   o_mode,
 585   /* registers like dq_mode, memory like b_mode.  */
 586   dqb_mode,
 587   /* registers like d_mode, memory like b_mode.  */
 588   db_mode,
 589   /* registers like d_mode, memory like w_mode.  */
 590   dw_mode,
 591   /* registers like dq_mode, memory like d_mode.  */
 592   dqd_mode,
 593   /* normal vex mode */
 594   vex_mode,
 595   /* 128bit vex mode */
 596   vex128_mode,
 597   /* 256bit vex mode */
 598   vex256_mode,
 599   /* operand size depends on the VEX.W bit.  */
 600   vex_w_dq_mode,
 601
 602   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 603   vex_vsib_d_w_dq_mode,
 604   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 605   vex_vsib_d_w_d_mode,
 606   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 607   vex_vsib_q_w_dq_mode,
 608   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 609   vex_vsib_q_w_d_mode,
 610
 611   /* scalar, ignore vector length.  */
 612   scalar_mode,
 613   /* like b_mode, ignore vector length.  */
 614   b_scalar_mode,
 615   /* like w_mode, ignore vector length.  */
 616   w_scalar_mode,
 617   /* like d_mode, ignore vector length.  */
 618   d_scalar_mode,
 619   /* like d_swap_mode, ignore vector length.  */
 620   d_scalar_swap_mode,
 621   /* like q_mode, ignore vector length.  */
 622   q_scalar_mode,
 623   /* like q_swap_mode, ignore vector length.  */
 624   q_scalar_swap_mode,
 625   /* like vex_mode, ignore vector length.  */
 626   vex_scalar_mode,
 627   /* like vex_w_dq_mode, ignore vector length.  */
 628   vex_scalar_w_dq_mode,
 629
 630   /* Static rounding.  */
 631   evex_rounding_mode,
 632   /* Static rounding, 64-bit mode only.  */
 633   evex_rounding_64_mode,
 634   /* Supress all exceptions.  */
 635   evex_sae_mode,
 636
 637   /* Mask register operand.  */
 638   mask_mode,
 639   /* Mask register operand.  */
 640   mask_bd_mode,
 641
 642   es_reg,
 643   cs_reg,
 644   ss_reg,
 645   ds_reg,
 646   fs_reg,
 647   gs_reg,
 648
 649   eAX_reg,
 650   eCX_reg,
 651   eDX_reg,
 652   eBX_reg,
 653   eSP_reg,
 654   eBP_reg,
 655   eSI_reg,
 656   eDI_reg,
 657
 658   al_reg,
 659   cl_reg,
 660   dl_reg,
 661   bl_reg,
 662   ah_reg,
 663   ch_reg,
 664   dh_reg,
 665   bh_reg,
 666
 667   ax_reg,
 668   cx_reg,
 669   dx_reg,
 670   bx_reg,
 671   sp_reg,
 672   bp_reg,
 673   si_reg,
 674   di_reg,
 675
 676   rAX_reg,
 677   rCX_reg,
 678   rDX_reg,
 679   rBX_reg,
 680   rSP_reg,
 681   rBP_reg,
 682   rSI_reg,
 683   rDI_reg,
 684
 685   z_mode_ax_reg,
 686   indir_dx_reg
 687 };
 688
 689 enum
 690 {
 691   FLOATCODE = 1,
 692   USE_REG_TABLE,
 693   USE_MOD_TABLE,
 694   USE_RM_TABLE,
 695   USE_PREFIX_TABLE,
 696   USE_X86_64_TABLE,
 697   USE_3BYTE_TABLE,
 698   USE_XOP_8F_TABLE,
 699   USE_VEX_C4_TABLE,
 700   USE_VEX_C5_TABLE,
 701   USE_VEX_LEN_TABLE,
 702   USE_VEX_W_TABLE,
 703   USE_EVEX_TABLE,
 704   USE_EVEX_LEN_TABLE
 705 };
 706
 707 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 708
 709 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 710 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 711 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 712 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 713 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 714 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 715 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 716 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 717 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 718 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 719 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 720 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 721 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 722 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 723 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 724 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 725
 726 enum
 727 {
 728   REG_80 = 0,
 729   REG_81,
 730   REG_83,
 731   REG_8F,
 732   REG_C0,
 733   REG_C1,
 734   REG_C6,
 735   REG_C7,
 736   REG_D0,
 737   REG_D1,
 738   REG_D2,
 739   REG_D3,
 740   REG_F6,
 741   REG_F7,
 742   REG_FE,
 743   REG_FF,
 744   REG_0F00,
 745   REG_0F01,
 746   REG_0F0D,
 747   REG_0F18,
 748   REG_0F1C_MOD_0,
 749   REG_0F1E_MOD_3,
 750   REG_0F71,
 751   REG_0F72,
 752   REG_0F73,
 753   REG_0FA6,
 754   REG_0FA7,
 755   REG_0FAE,
 756   REG_0FBA,
 757   REG_0FC7,
 758   REG_VEX_0F71,
 759   REG_VEX_0F72,
 760   REG_VEX_0F73,
 761   REG_VEX_0FAE,
 762   REG_VEX_0F38F3,
 763   REG_XOP_LWPCB,
 764   REG_XOP_LWP,
 765   REG_XOP_TBM_01,
 766   REG_XOP_TBM_02,
 767
 768   REG_EVEX_0F71,
 769   REG_EVEX_0F72,
 770   REG_EVEX_0F73,
 771   REG_EVEX_0F38C6,
 772   REG_EVEX_0F38C7
 773 };
 774
 775 enum
 776 {
 777   MOD_8D = 0,
 778   MOD_C6_REG_7,
 779   MOD_C7_REG_7,
 780   MOD_FF_REG_3,
 781   MOD_FF_REG_5,
 782   MOD_0F01_REG_0,
 783   MOD_0F01_REG_1,
 784   MOD_0F01_REG_2,
 785   MOD_0F01_REG_3,
 786   MOD_0F01_REG_5,
 787   MOD_0F01_REG_7,
 788   MOD_0F12_PREFIX_0,
 789   MOD_0F13,
 790   MOD_0F16_PREFIX_0,
 791   MOD_0F17,
 792   MOD_0F18_REG_0,
 793   MOD_0F18_REG_1,
 794   MOD_0F18_REG_2,
 795   MOD_0F18_REG_3,
 796   MOD_0F18_REG_4,
 797   MOD_0F18_REG_5,
 798   MOD_0F18_REG_6,
 799   MOD_0F18_REG_7,
 800   MOD_0F1A_PREFIX_0,
 801   MOD_0F1B_PREFIX_0,
 802   MOD_0F1B_PREFIX_1,
 803   MOD_0F1C_PREFIX_0,
 804   MOD_0F1E_PREFIX_1,
 805   MOD_0F24,
 806   MOD_0F26,
 807   MOD_0F2B_PREFIX_0,
 808   MOD_0F2B_PREFIX_1,
 809   MOD_0F2B_PREFIX_2,
 810   MOD_0F2B_PREFIX_3,
 811   MOD_0F51,
 812   MOD_0F71_REG_2,
 813   MOD_0F71_REG_4,
 814   MOD_0F71_REG_6,
 815   MOD_0F72_REG_2,
 816   MOD_0F72_REG_4,
 817   MOD_0F72_REG_6,
 818   MOD_0F73_REG_2,
 819   MOD_0F73_REG_3,
 820   MOD_0F73_REG_6,
 821   MOD_0F73_REG_7,
 822   MOD_0FAE_REG_0,
 823   MOD_0FAE_REG_1,
 824   MOD_0FAE_REG_2,
 825   MOD_0FAE_REG_3,
 826   MOD_0FAE_REG_4,
 827   MOD_0FAE_REG_5,
 828   MOD_0FAE_REG_6,
 829   MOD_0FAE_REG_7,
 830   MOD_0FB2,
 831   MOD_0FB4,
 832   MOD_0FB5,
 833   MOD_0FC3,
 834   MOD_0FC7_REG_3,
 835   MOD_0FC7_REG_4,
 836   MOD_0FC7_REG_5,
 837   MOD_0FC7_REG_6,
 838   MOD_0FC7_REG_7,
 839   MOD_0FD7,
 840   MOD_0FE7_PREFIX_2,
 841   MOD_0FF0_PREFIX_3,
 842   MOD_0F382A_PREFIX_2,
 843   MOD_0F38F5_PREFIX_2,
 844   MOD_0F38F6_PREFIX_0,
 845   MOD_0F38F8_PREFIX_1,
 846   MOD_0F38F8_PREFIX_2,
 847   MOD_0F38F8_PREFIX_3,
 848   MOD_0F38F9_PREFIX_0,
 849   MOD_62_32BIT,
 850   MOD_C4_32BIT,
 851   MOD_C5_32BIT,
 852   MOD_VEX_0F12_PREFIX_0,
 853   MOD_VEX_0F13,
 854   MOD_VEX_0F16_PREFIX_0,
 855   MOD_VEX_0F17,
 856   MOD_VEX_0F2B,
 857   MOD_VEX_W_0_0F41_P_0_LEN_1,
 858   MOD_VEX_W_1_0F41_P_0_LEN_1,
 859   MOD_VEX_W_0_0F41_P_2_LEN_1,
 860   MOD_VEX_W_1_0F41_P_2_LEN_1,
 861   MOD_VEX_W_0_0F42_P_0_LEN_1,
 862   MOD_VEX_W_1_0F42_P_0_LEN_1,
 863   MOD_VEX_W_0_0F42_P_2_LEN_1,
 864   MOD_VEX_W_1_0F42_P_2_LEN_1,
 865   MOD_VEX_W_0_0F44_P_0_LEN_1,
 866   MOD_VEX_W_1_0F44_P_0_LEN_1,
 867   MOD_VEX_W_0_0F44_P_2_LEN_1,
 868   MOD_VEX_W_1_0F44_P_2_LEN_1,
 869   MOD_VEX_W_0_0F45_P_0_LEN_1,
 870   MOD_VEX_W_1_0F45_P_0_LEN_1,
 871   MOD_VEX_W_0_0F45_P_2_LEN_1,
 872   MOD_VEX_W_1_0F45_P_2_LEN_1,
 873   MOD_VEX_W_0_0F46_P_0_LEN_1,
 874   MOD_VEX_W_1_0F46_P_0_LEN_1,
 875   MOD_VEX_W_0_0F46_P_2_LEN_1,
 876   MOD_VEX_W_1_0F46_P_2_LEN_1,
 877   MOD_VEX_W_0_0F47_P_0_LEN_1,
 878   MOD_VEX_W_1_0F47_P_0_LEN_1,
 879   MOD_VEX_W_0_0F47_P_2_LEN_1,
 880   MOD_VEX_W_1_0F47_P_2_LEN_1,
 881   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 882   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 884   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 886   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 888   MOD_VEX_0F50,
 889   MOD_VEX_0F71_REG_2,
 890   MOD_VEX_0F71_REG_4,
 891   MOD_VEX_0F71_REG_6,
 892   MOD_VEX_0F72_REG_2,
 893   MOD_VEX_0F72_REG_4,
 894   MOD_VEX_0F72_REG_6,
 895   MOD_VEX_0F73_REG_2,
 896   MOD_VEX_0F73_REG_3,
 897   MOD_VEX_0F73_REG_6,
 898   MOD_VEX_0F73_REG_7,
 899   MOD_VEX_W_0_0F91_P_0_LEN_0,
 900   MOD_VEX_W_1_0F91_P_0_LEN_0,
 901   MOD_VEX_W_0_0F91_P_2_LEN_0,
 902   MOD_VEX_W_1_0F91_P_2_LEN_0,
 903   MOD_VEX_W_0_0F92_P_0_LEN_0,
 904   MOD_VEX_W_0_0F92_P_2_LEN_0,
 905   MOD_VEX_0F92_P_3_LEN_0,
 906   MOD_VEX_W_0_0F93_P_0_LEN_0,
 907   MOD_VEX_W_0_0F93_P_2_LEN_0,
 908   MOD_VEX_0F93_P_3_LEN_0,
 909   MOD_VEX_W_0_0F98_P_0_LEN_0,
 910   MOD_VEX_W_1_0F98_P_0_LEN_0,
 911   MOD_VEX_W_0_0F98_P_2_LEN_0,
 912   MOD_VEX_W_1_0F98_P_2_LEN_0,
 913   MOD_VEX_W_0_0F99_P_0_LEN_0,
 914   MOD_VEX_W_1_0F99_P_0_LEN_0,
 915   MOD_VEX_W_0_0F99_P_2_LEN_0,
 916   MOD_VEX_W_1_0F99_P_2_LEN_0,
 917   MOD_VEX_0FAE_REG_2,
 918   MOD_VEX_0FAE_REG_3,
 919   MOD_VEX_0FD7_PREFIX_2,
 920   MOD_VEX_0FE7_PREFIX_2,
 921   MOD_VEX_0FF0_PREFIX_3,
 922   MOD_VEX_0F381A_PREFIX_2,
 923   MOD_VEX_0F382A_PREFIX_2,
 924   MOD_VEX_0F382C_PREFIX_2,
 925   MOD_VEX_0F382D_PREFIX_2,
 926   MOD_VEX_0F382E_PREFIX_2,
 927   MOD_VEX_0F382F_PREFIX_2,
 928   MOD_VEX_0F385A_PREFIX_2,
 929   MOD_VEX_0F388C_PREFIX_2,
 930   MOD_VEX_0F388E_PREFIX_2,
 931   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 936   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 938   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 939
 940   MOD_EVEX_0F10_PREFIX_1,
 941   MOD_EVEX_0F10_PREFIX_3,
 942   MOD_EVEX_0F11_PREFIX_1,
 943   MOD_EVEX_0F11_PREFIX_3,
 944   MOD_EVEX_0F12_PREFIX_0,
 945   MOD_EVEX_0F16_PREFIX_0,
 946   MOD_EVEX_0F38C6_REG_1,
 947   MOD_EVEX_0F38C6_REG_2,
 948   MOD_EVEX_0F38C6_REG_5,
 949   MOD_EVEX_0F38C6_REG_6,
 950   MOD_EVEX_0F38C7_REG_1,
 951   MOD_EVEX_0F38C7_REG_2,
 952   MOD_EVEX_0F38C7_REG_5,
 953   MOD_EVEX_0F38C7_REG_6
 954 };
 955
 956 enum
 957 {
 958   RM_C6_REG_7 = 0,
 959   RM_C7_REG_7,
 960   RM_0F01_REG_0,
 961   RM_0F01_REG_1,
 962   RM_0F01_REG_2,
 963   RM_0F01_REG_3,
 964   RM_0F01_REG_5,
 965   RM_0F01_REG_7,
 966   RM_0F1E_MOD_3_REG_7,
 967   RM_0FAE_REG_6,
 968   RM_0FAE_REG_7
 969 };
 970
 971 enum
 972 {
 973   PREFIX_90 = 0,
 974   PREFIX_MOD_0_0F01_REG_5,
 975   PREFIX_MOD_3_0F01_REG_5_RM_0,
 976   PREFIX_MOD_3_0F01_REG_5_RM_2,
 977   PREFIX_0F09,
 978   PREFIX_0F10,
 979   PREFIX_0F11,
 980   PREFIX_0F12,
 981   PREFIX_0F16,
 982   PREFIX_0F1A,
 983   PREFIX_0F1B,
 984   PREFIX_0F1C,
 985   PREFIX_0F1E,
 986   PREFIX_0F2A,
 987   PREFIX_0F2B,
 988   PREFIX_0F2C,
 989   PREFIX_0F2D,
 990   PREFIX_0F2E,
 991   PREFIX_0F2F,
 992   PREFIX_0F51,
 993   PREFIX_0F52,
 994   PREFIX_0F53,
 995   PREFIX_0F58,
 996   PREFIX_0F59,
 997   PREFIX_0F5A,
 998   PREFIX_0F5B,
 999   PREFIX_0F5C,
1000   PREFIX_0F5D,
1001   PREFIX_0F5E,
1002   PREFIX_0F5F,
1003   PREFIX_0F60,
1004   PREFIX_0F61,
1005   PREFIX_0F62,
1006   PREFIX_0F6C,
1007   PREFIX_0F6D,
1008   PREFIX_0F6F,
1009   PREFIX_0F70,
1010   PREFIX_0F73_REG_3,
1011   PREFIX_0F73_REG_7,
1012   PREFIX_0F78,
1013   PREFIX_0F79,
1014   PREFIX_0F7C,
1015   PREFIX_0F7D,
1016   PREFIX_0F7E,
1017   PREFIX_0F7F,
1018   PREFIX_0FAE_REG_0,
1019   PREFIX_0FAE_REG_1,
1020   PREFIX_0FAE_REG_2,
1021   PREFIX_0FAE_REG_3,
1022   PREFIX_MOD_0_0FAE_REG_4,
1023   PREFIX_MOD_3_0FAE_REG_4,
1024   PREFIX_MOD_0_0FAE_REG_5,
1025   PREFIX_MOD_3_0FAE_REG_5,
1026   PREFIX_MOD_0_0FAE_REG_6,
1027   PREFIX_MOD_1_0FAE_REG_6,
1028   PREFIX_0FAE_REG_7,
1029   PREFIX_0FB8,
1030   PREFIX_0FBC,
1031   PREFIX_0FBD,
1032   PREFIX_0FC2,
1033   PREFIX_MOD_0_0FC3,
1034   PREFIX_MOD_0_0FC7_REG_6,
1035   PREFIX_MOD_3_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_7,
1037   PREFIX_0FD0,
1038   PREFIX_0FD6,
1039   PREFIX_0FE6,
1040   PREFIX_0FE7,
1041   PREFIX_0FF0,
1042   PREFIX_0FF7,
1043   PREFIX_0F3810,
1044   PREFIX_0F3814,
1045   PREFIX_0F3815,
1046   PREFIX_0F3817,
1047   PREFIX_0F3820,
1048   PREFIX_0F3821,
1049   PREFIX_0F3822,
1050   PREFIX_0F3823,
1051   PREFIX_0F3824,
1052   PREFIX_0F3825,
1053   PREFIX_0F3828,
1054   PREFIX_0F3829,
1055   PREFIX_0F382A,
1056   PREFIX_0F382B,
1057   PREFIX_0F3830,
1058   PREFIX_0F3831,
1059   PREFIX_0F3832,
1060   PREFIX_0F3833,
1061   PREFIX_0F3834,
1062   PREFIX_0F3835,
1063   PREFIX_0F3837,
1064   PREFIX_0F3838,
1065   PREFIX_0F3839,
1066   PREFIX_0F383A,
1067   PREFIX_0F383B,
1068   PREFIX_0F383C,
1069   PREFIX_0F383D,
1070   PREFIX_0F383E,
1071   PREFIX_0F383F,
1072   PREFIX_0F3840,
1073   PREFIX_0F3841,
1074   PREFIX_0F3880,
1075   PREFIX_0F3881,
1076   PREFIX_0F3882,
1077   PREFIX_0F38C8,
1078   PREFIX_0F38C9,
1079   PREFIX_0F38CA,
1080   PREFIX_0F38CB,
1081   PREFIX_0F38CC,
1082   PREFIX_0F38CD,
1083   PREFIX_0F38CF,
1084   PREFIX_0F38DB,
1085   PREFIX_0F38DC,
1086   PREFIX_0F38DD,
1087   PREFIX_0F38DE,
1088   PREFIX_0F38DF,
1089   PREFIX_0F38F0,
1090   PREFIX_0F38F1,
1091   PREFIX_0F38F5,
1092   PREFIX_0F38F6,
1093   PREFIX_0F38F8,
1094   PREFIX_0F38F9,
1095   PREFIX_0F3A08,
1096   PREFIX_0F3A09,
1097   PREFIX_0F3A0A,
1098   PREFIX_0F3A0B,
1099   PREFIX_0F3A0C,
1100   PREFIX_0F3A0D,
1101   PREFIX_0F3A0E,
1102   PREFIX_0F3A14,
1103   PREFIX_0F3A15,
1104   PREFIX_0F3A16,
1105   PREFIX_0F3A17,
1106   PREFIX_0F3A20,
1107   PREFIX_0F3A21,
1108   PREFIX_0F3A22,
1109   PREFIX_0F3A40,
1110   PREFIX_0F3A41,
1111   PREFIX_0F3A42,
1112   PREFIX_0F3A44,
1113   PREFIX_0F3A60,
1114   PREFIX_0F3A61,
1115   PREFIX_0F3A62,
1116   PREFIX_0F3A63,
1117   PREFIX_0F3ACC,
1118   PREFIX_0F3ACE,
1119   PREFIX_0F3ACF,
1120   PREFIX_0F3ADF,
1121   PREFIX_VEX_0F10,
1122   PREFIX_VEX_0F11,
1123   PREFIX_VEX_0F12,
1124   PREFIX_VEX_0F16,
1125   PREFIX_VEX_0F2A,
1126   PREFIX_VEX_0F2C,
1127   PREFIX_VEX_0F2D,
1128   PREFIX_VEX_0F2E,
1129   PREFIX_VEX_0F2F,
1130   PREFIX_VEX_0F41,
1131   PREFIX_VEX_0F42,
1132   PREFIX_VEX_0F44,
1133   PREFIX_VEX_0F45,
1134   PREFIX_VEX_0F46,
1135   PREFIX_VEX_0F47,
1136   PREFIX_VEX_0F4A,
1137   PREFIX_VEX_0F4B,
1138   PREFIX_VEX_0F51,
1139   PREFIX_VEX_0F52,
1140   PREFIX_VEX_0F53,
1141   PREFIX_VEX_0F58,
1142   PREFIX_VEX_0F59,
1143   PREFIX_VEX_0F5A,
1144   PREFIX_VEX_0F5B,
1145   PREFIX_VEX_0F5C,
1146   PREFIX_VEX_0F5D,
1147   PREFIX_VEX_0F5E,
1148   PREFIX_VEX_0F5F,
1149   PREFIX_VEX_0F60,
1150   PREFIX_VEX_0F61,
1151   PREFIX_VEX_0F62,
1152   PREFIX_VEX_0F63,
1153   PREFIX_VEX_0F64,
1154   PREFIX_VEX_0F65,
1155   PREFIX_VEX_0F66,
1156   PREFIX_VEX_0F67,
1157   PREFIX_VEX_0F68,
1158   PREFIX_VEX_0F69,
1159   PREFIX_VEX_0F6A,
1160   PREFIX_VEX_0F6B,
1161   PREFIX_VEX_0F6C,
1162   PREFIX_VEX_0F6D,
1163   PREFIX_VEX_0F6E,
1164   PREFIX_VEX_0F6F,
1165   PREFIX_VEX_0F70,
1166   PREFIX_VEX_0F71_REG_2,
1167   PREFIX_VEX_0F71_REG_4,
1168   PREFIX_VEX_0F71_REG_6,
1169   PREFIX_VEX_0F72_REG_2,
1170   PREFIX_VEX_0F72_REG_4,
1171   PREFIX_VEX_0F72_REG_6,
1172   PREFIX_VEX_0F73_REG_2,
1173   PREFIX_VEX_0F73_REG_3,
1174   PREFIX_VEX_0F73_REG_6,
1175   PREFIX_VEX_0F73_REG_7,
1176   PREFIX_VEX_0F74,
1177   PREFIX_VEX_0F75,
1178   PREFIX_VEX_0F76,
1179   PREFIX_VEX_0F77,
1180   PREFIX_VEX_0F7C,
1181   PREFIX_VEX_0F7D,
1182   PREFIX_VEX_0F7E,
1183   PREFIX_VEX_0F7F,
1184   PREFIX_VEX_0F90,
1185   PREFIX_VEX_0F91,
1186   PREFIX_VEX_0F92,
1187   PREFIX_VEX_0F93,
1188   PREFIX_VEX_0F98,
1189   PREFIX_VEX_0F99,
1190   PREFIX_VEX_0FC2,
1191   PREFIX_VEX_0FC4,
1192   PREFIX_VEX_0FC5,
1193   PREFIX_VEX_0FD0,
1194   PREFIX_VEX_0FD1,
1195   PREFIX_VEX_0FD2,
1196   PREFIX_VEX_0FD3,
1197   PREFIX_VEX_0FD4,
1198   PREFIX_VEX_0FD5,
1199   PREFIX_VEX_0FD6,
1200   PREFIX_VEX_0FD7,
1201   PREFIX_VEX_0FD8,
1202   PREFIX_VEX_0FD9,
1203   PREFIX_VEX_0FDA,
1204   PREFIX_VEX_0FDB,
1205   PREFIX_VEX_0FDC,
1206   PREFIX_VEX_0FDD,
1207   PREFIX_VEX_0FDE,
1208   PREFIX_VEX_0FDF,
1209   PREFIX_VEX_0FE0,
1210   PREFIX_VEX_0FE1,
1211   PREFIX_VEX_0FE2,
1212   PREFIX_VEX_0FE3,
1213   PREFIX_VEX_0FE4,
1214   PREFIX_VEX_0FE5,
1215   PREFIX_VEX_0FE6,
1216   PREFIX_VEX_0FE7,
1217   PREFIX_VEX_0FE8,
1218   PREFIX_VEX_0FE9,
1219   PREFIX_VEX_0FEA,
1220   PREFIX_VEX_0FEB,
1221   PREFIX_VEX_0FEC,
1222   PREFIX_VEX_0FED,
1223   PREFIX_VEX_0FEE,
1224   PREFIX_VEX_0FEF,
1225   PREFIX_VEX_0FF0,
1226   PREFIX_VEX_0FF1,
1227   PREFIX_VEX_0FF2,
1228   PREFIX_VEX_0FF3,
1229   PREFIX_VEX_0FF4,
1230   PREFIX_VEX_0FF5,
1231   PREFIX_VEX_0FF6,
1232   PREFIX_VEX_0FF7,
1233   PREFIX_VEX_0FF8,
1234   PREFIX_VEX_0FF9,
1235   PREFIX_VEX_0FFA,
1236   PREFIX_VEX_0FFB,
1237   PREFIX_VEX_0FFC,
1238   PREFIX_VEX_0FFD,
1239   PREFIX_VEX_0FFE,
1240   PREFIX_VEX_0F3800,
1241   PREFIX_VEX_0F3801,
1242   PREFIX_VEX_0F3802,
1243   PREFIX_VEX_0F3803,
1244   PREFIX_VEX_0F3804,
1245   PREFIX_VEX_0F3805,
1246   PREFIX_VEX_0F3806,
1247   PREFIX_VEX_0F3807,
1248   PREFIX_VEX_0F3808,
1249   PREFIX_VEX_0F3809,
1250   PREFIX_VEX_0F380A,
1251   PREFIX_VEX_0F380B,
1252   PREFIX_VEX_0F380C,
1253   PREFIX_VEX_0F380D,
1254   PREFIX_VEX_0F380E,
1255   PREFIX_VEX_0F380F,
1256   PREFIX_VEX_0F3813,
1257   PREFIX_VEX_0F3816,
1258   PREFIX_VEX_0F3817,
1259   PREFIX_VEX_0F3818,
1260   PREFIX_VEX_0F3819,
1261   PREFIX_VEX_0F381A,
1262   PREFIX_VEX_0F381C,
1263   PREFIX_VEX_0F381D,
1264   PREFIX_VEX_0F381E,
1265   PREFIX_VEX_0F3820,
1266   PREFIX_VEX_0F3821,
1267   PREFIX_VEX_0F3822,
1268   PREFIX_VEX_0F3823,
1269   PREFIX_VEX_0F3824,
1270   PREFIX_VEX_0F3825,
1271   PREFIX_VEX_0F3828,
1272   PREFIX_VEX_0F3829,
1273   PREFIX_VEX_0F382A,
1274   PREFIX_VEX_0F382B,
1275   PREFIX_VEX_0F382C,
1276   PREFIX_VEX_0F382D,
1277   PREFIX_VEX_0F382E,
1278   PREFIX_VEX_0F382F,
1279   PREFIX_VEX_0F3830,
1280   PREFIX_VEX_0F3831,
1281   PREFIX_VEX_0F3832,
1282   PREFIX_VEX_0F3833,
1283   PREFIX_VEX_0F3834,
1284   PREFIX_VEX_0F3835,
1285   PREFIX_VEX_0F3836,
1286   PREFIX_VEX_0F3837,
1287   PREFIX_VEX_0F3838,
1288   PREFIX_VEX_0F3839,
1289   PREFIX_VEX_0F383A,
1290   PREFIX_VEX_0F383B,
1291   PREFIX_VEX_0F383C,
1292   PREFIX_VEX_0F383D,
1293   PREFIX_VEX_0F383E,
1294   PREFIX_VEX_0F383F,
1295   PREFIX_VEX_0F3840,
1296   PREFIX_VEX_0F3841,
1297   PREFIX_VEX_0F3845,
1298   PREFIX_VEX_0F3846,
1299   PREFIX_VEX_0F3847,
1300   PREFIX_VEX_0F3858,
1301   PREFIX_VEX_0F3859,
1302   PREFIX_VEX_0F385A,
1303   PREFIX_VEX_0F3878,
1304   PREFIX_VEX_0F3879,
1305   PREFIX_VEX_0F388C,
1306   PREFIX_VEX_0F388E,
1307   PREFIX_VEX_0F3890,
1308   PREFIX_VEX_0F3891,
1309   PREFIX_VEX_0F3892,
1310   PREFIX_VEX_0F3893,
1311   PREFIX_VEX_0F3896,
1312   PREFIX_VEX_0F3897,
1313   PREFIX_VEX_0F3898,
1314   PREFIX_VEX_0F3899,
1315   PREFIX_VEX_0F389A,
1316   PREFIX_VEX_0F389B,
1317   PREFIX_VEX_0F389C,
1318   PREFIX_VEX_0F389D,
1319   PREFIX_VEX_0F389E,
1320   PREFIX_VEX_0F389F,
1321   PREFIX_VEX_0F38A6,
1322   PREFIX_VEX_0F38A7,
1323   PREFIX_VEX_0F38A8,
1324   PREFIX_VEX_0F38A9,
1325   PREFIX_VEX_0F38AA,
1326   PREFIX_VEX_0F38AB,
1327   PREFIX_VEX_0F38AC,
1328   PREFIX_VEX_0F38AD,
1329   PREFIX_VEX_0F38AE,
1330   PREFIX_VEX_0F38AF,
1331   PREFIX_VEX_0F38B6,
1332   PREFIX_VEX_0F38B7,
1333   PREFIX_VEX_0F38B8,
1334   PREFIX_VEX_0F38B9,
1335   PREFIX_VEX_0F38BA,
1336   PREFIX_VEX_0F38BB,
1337   PREFIX_VEX_0F38BC,
1338   PREFIX_VEX_0F38BD,
1339   PREFIX_VEX_0F38BE,
1340   PREFIX_VEX_0F38BF,
1341   PREFIX_VEX_0F38CF,
1342   PREFIX_VEX_0F38DB,
1343   PREFIX_VEX_0F38DC,
1344   PREFIX_VEX_0F38DD,
1345   PREFIX_VEX_0F38DE,
1346   PREFIX_VEX_0F38DF,
1347   PREFIX_VEX_0F38F2,
1348   PREFIX_VEX_0F38F3_REG_1,
1349   PREFIX_VEX_0F38F3_REG_2,
1350   PREFIX_VEX_0F38F3_REG_3,
1351   PREFIX_VEX_0F38F5,
1352   PREFIX_VEX_0F38F6,
1353   PREFIX_VEX_0F38F7,
1354   PREFIX_VEX_0F3A00,
1355   PREFIX_VEX_0F3A01,
1356   PREFIX_VEX_0F3A02,
1357   PREFIX_VEX_0F3A04,
1358   PREFIX_VEX_0F3A05,
1359   PREFIX_VEX_0F3A06,
1360   PREFIX_VEX_0F3A08,
1361   PREFIX_VEX_0F3A09,
1362   PREFIX_VEX_0F3A0A,
1363   PREFIX_VEX_0F3A0B,
1364   PREFIX_VEX_0F3A0C,
1365   PREFIX_VEX_0F3A0D,
1366   PREFIX_VEX_0F3A0E,
1367   PREFIX_VEX_0F3A0F,
1368   PREFIX_VEX_0F3A14,
1369   PREFIX_VEX_0F3A15,
1370   PREFIX_VEX_0F3A16,
1371   PREFIX_VEX_0F3A17,
1372   PREFIX_VEX_0F3A18,
1373   PREFIX_VEX_0F3A19,
1374   PREFIX_VEX_0F3A1D,
1375   PREFIX_VEX_0F3A20,
1376   PREFIX_VEX_0F3A21,
1377   PREFIX_VEX_0F3A22,
1378   PREFIX_VEX_0F3A30,
1379   PREFIX_VEX_0F3A31,
1380   PREFIX_VEX_0F3A32,
1381   PREFIX_VEX_0F3A33,
1382   PREFIX_VEX_0F3A38,
1383   PREFIX_VEX_0F3A39,
1384   PREFIX_VEX_0F3A40,
1385   PREFIX_VEX_0F3A41,
1386   PREFIX_VEX_0F3A42,
1387   PREFIX_VEX_0F3A44,
1388   PREFIX_VEX_0F3A46,
1389   PREFIX_VEX_0F3A48,
1390   PREFIX_VEX_0F3A49,
1391   PREFIX_VEX_0F3A4A,
1392   PREFIX_VEX_0F3A4B,
1393   PREFIX_VEX_0F3A4C,
1394   PREFIX_VEX_0F3A5C,
1395   PREFIX_VEX_0F3A5D,
1396   PREFIX_VEX_0F3A5E,
1397   PREFIX_VEX_0F3A5F,
1398   PREFIX_VEX_0F3A60,
1399   PREFIX_VEX_0F3A61,
1400   PREFIX_VEX_0F3A62,
1401   PREFIX_VEX_0F3A63,
1402   PREFIX_VEX_0F3A68,
1403   PREFIX_VEX_0F3A69,
1404   PREFIX_VEX_0F3A6A,
1405   PREFIX_VEX_0F3A6B,
1406   PREFIX_VEX_0F3A6C,
1407   PREFIX_VEX_0F3A6D,
1408   PREFIX_VEX_0F3A6E,
1409   PREFIX_VEX_0F3A6F,
1410   PREFIX_VEX_0F3A78,
1411   PREFIX_VEX_0F3A79,
1412   PREFIX_VEX_0F3A7A,
1413   PREFIX_VEX_0F3A7B,
1414   PREFIX_VEX_0F3A7C,
1415   PREFIX_VEX_0F3A7D,
1416   PREFIX_VEX_0F3A7E,
1417   PREFIX_VEX_0F3A7F,
1418   PREFIX_VEX_0F3ACE,
1419   PREFIX_VEX_0F3ACF,
1420   PREFIX_VEX_0F3ADF,
1421   PREFIX_VEX_0F3AF0,
1422
1423   PREFIX_EVEX_0F10,
1424   PREFIX_EVEX_0F11,
1425   PREFIX_EVEX_0F12,
1426   PREFIX_EVEX_0F13,
1427   PREFIX_EVEX_0F14,
1428   PREFIX_EVEX_0F15,
1429   PREFIX_EVEX_0F16,
1430   PREFIX_EVEX_0F17,
1431   PREFIX_EVEX_0F28,
1432   PREFIX_EVEX_0F29,
1433   PREFIX_EVEX_0F2A,
1434   PREFIX_EVEX_0F2B,
1435   PREFIX_EVEX_0F2C,
1436   PREFIX_EVEX_0F2D,
1437   PREFIX_EVEX_0F2E,
1438   PREFIX_EVEX_0F2F,
1439   PREFIX_EVEX_0F51,
1440   PREFIX_EVEX_0F54,
1441   PREFIX_EVEX_0F55,
1442   PREFIX_EVEX_0F56,
1443   PREFIX_EVEX_0F57,
1444   PREFIX_EVEX_0F58,
1445   PREFIX_EVEX_0F59,
1446   PREFIX_EVEX_0F5A,
1447   PREFIX_EVEX_0F5B,
1448   PREFIX_EVEX_0F5C,
1449   PREFIX_EVEX_0F5D,
1450   PREFIX_EVEX_0F5E,
1451   PREFIX_EVEX_0F5F,
1452   PREFIX_EVEX_0F60,
1453   PREFIX_EVEX_0F61,
1454   PREFIX_EVEX_0F62,
1455   PREFIX_EVEX_0F63,
1456   PREFIX_EVEX_0F64,
1457   PREFIX_EVEX_0F65,
1458   PREFIX_EVEX_0F66,
1459   PREFIX_EVEX_0F67,
1460   PREFIX_EVEX_0F68,
1461   PREFIX_EVEX_0F69,
1462   PREFIX_EVEX_0F6A,
1463   PREFIX_EVEX_0F6B,
1464   PREFIX_EVEX_0F6C,
1465   PREFIX_EVEX_0F6D,
1466   PREFIX_EVEX_0F6E,
1467   PREFIX_EVEX_0F6F,
1468   PREFIX_EVEX_0F70,
1469   PREFIX_EVEX_0F71_REG_2,
1470   PREFIX_EVEX_0F71_REG_4,
1471   PREFIX_EVEX_0F71_REG_6,
1472   PREFIX_EVEX_0F72_REG_0,
1473   PREFIX_EVEX_0F72_REG_1,
1474   PREFIX_EVEX_0F72_REG_2,
1475   PREFIX_EVEX_0F72_REG_4,
1476   PREFIX_EVEX_0F72_REG_6,
1477   PREFIX_EVEX_0F73_REG_2,
1478   PREFIX_EVEX_0F73_REG_3,
1479   PREFIX_EVEX_0F73_REG_6,
1480   PREFIX_EVEX_0F73_REG_7,
1481   PREFIX_EVEX_0F74,
1482   PREFIX_EVEX_0F75,
1483   PREFIX_EVEX_0F76,
1484   PREFIX_EVEX_0F78,
1485   PREFIX_EVEX_0F79,
1486   PREFIX_EVEX_0F7A,
1487   PREFIX_EVEX_0F7B,
1488   PREFIX_EVEX_0F7E,
1489   PREFIX_EVEX_0F7F,
1490   PREFIX_EVEX_0FC2,
1491   PREFIX_EVEX_0FC4,
1492   PREFIX_EVEX_0FC5,
1493   PREFIX_EVEX_0FC6,
1494   PREFIX_EVEX_0FD1,
1495   PREFIX_EVEX_0FD2,
1496   PREFIX_EVEX_0FD3,
1497   PREFIX_EVEX_0FD4,
1498   PREFIX_EVEX_0FD5,
1499   PREFIX_EVEX_0FD6,
1500   PREFIX_EVEX_0FD8,
1501   PREFIX_EVEX_0FD9,
1502   PREFIX_EVEX_0FDA,
1503   PREFIX_EVEX_0FDB,
1504   PREFIX_EVEX_0FDC,
1505   PREFIX_EVEX_0FDD,
1506   PREFIX_EVEX_0FDE,
1507   PREFIX_EVEX_0FDF,
1508   PREFIX_EVEX_0FE0,
1509   PREFIX_EVEX_0FE1,
1510   PREFIX_EVEX_0FE2,
1511   PREFIX_EVEX_0FE3,
1512   PREFIX_EVEX_0FE4,
1513   PREFIX_EVEX_0FE5,
1514   PREFIX_EVEX_0FE6,
1515   PREFIX_EVEX_0FE7,
1516   PREFIX_EVEX_0FE8,
1517   PREFIX_EVEX_0FE9,
1518   PREFIX_EVEX_0FEA,
1519   PREFIX_EVEX_0FEB,
1520   PREFIX_EVEX_0FEC,
1521   PREFIX_EVEX_0FED,
1522   PREFIX_EVEX_0FEE,
1523   PREFIX_EVEX_0FEF,
1524   PREFIX_EVEX_0FF1,
1525   PREFIX_EVEX_0FF2,
1526   PREFIX_EVEX_0FF3,
1527   PREFIX_EVEX_0FF4,
1528   PREFIX_EVEX_0FF5,
1529   PREFIX_EVEX_0FF6,
1530   PREFIX_EVEX_0FF8,
1531   PREFIX_EVEX_0FF9,
1532   PREFIX_EVEX_0FFA,
1533   PREFIX_EVEX_0FFB,
1534   PREFIX_EVEX_0FFC,
1535   PREFIX_EVEX_0FFD,
1536   PREFIX_EVEX_0FFE,
1537   PREFIX_EVEX_0F3800,
1538   PREFIX_EVEX_0F3804,
1539   PREFIX_EVEX_0F380B,
1540   PREFIX_EVEX_0F380C,
1541   PREFIX_EVEX_0F380D,
1542   PREFIX_EVEX_0F3810,
1543   PREFIX_EVEX_0F3811,
1544   PREFIX_EVEX_0F3812,
1545   PREFIX_EVEX_0F3813,
1546   PREFIX_EVEX_0F3814,
1547   PREFIX_EVEX_0F3815,
1548   PREFIX_EVEX_0F3816,
1549   PREFIX_EVEX_0F3818,
1550   PREFIX_EVEX_0F3819,
1551   PREFIX_EVEX_0F381A,
1552   PREFIX_EVEX_0F381B,
1553   PREFIX_EVEX_0F381C,
1554   PREFIX_EVEX_0F381D,
1555   PREFIX_EVEX_0F381E,
1556   PREFIX_EVEX_0F381F,
1557   PREFIX_EVEX_0F3820,
1558   PREFIX_EVEX_0F3821,
1559   PREFIX_EVEX_0F3822,
1560   PREFIX_EVEX_0F3823,
1561   PREFIX_EVEX_0F3824,
1562   PREFIX_EVEX_0F3825,
1563   PREFIX_EVEX_0F3826,
1564   PREFIX_EVEX_0F3827,
1565   PREFIX_EVEX_0F3828,
1566   PREFIX_EVEX_0F3829,
1567   PREFIX_EVEX_0F382A,
1568   PREFIX_EVEX_0F382B,
1569   PREFIX_EVEX_0F382C,
1570   PREFIX_EVEX_0F382D,
1571   PREFIX_EVEX_0F3830,
1572   PREFIX_EVEX_0F3831,
1573   PREFIX_EVEX_0F3832,
1574   PREFIX_EVEX_0F3833,
1575   PREFIX_EVEX_0F3834,
1576   PREFIX_EVEX_0F3835,
1577   PREFIX_EVEX_0F3836,
1578   PREFIX_EVEX_0F3837,
1579   PREFIX_EVEX_0F3838,
1580   PREFIX_EVEX_0F3839,
1581   PREFIX_EVEX_0F383A,
1582   PREFIX_EVEX_0F383B,
1583   PREFIX_EVEX_0F383C,
1584   PREFIX_EVEX_0F383D,
1585   PREFIX_EVEX_0F383E,
1586   PREFIX_EVEX_0F383F,
1587   PREFIX_EVEX_0F3840,
1588   PREFIX_EVEX_0F3842,
1589   PREFIX_EVEX_0F3843,
1590   PREFIX_EVEX_0F3844,
1591   PREFIX_EVEX_0F3845,
1592   PREFIX_EVEX_0F3846,
1593   PREFIX_EVEX_0F3847,
1594   PREFIX_EVEX_0F384C,
1595   PREFIX_EVEX_0F384D,
1596   PREFIX_EVEX_0F384E,
1597   PREFIX_EVEX_0F384F,
1598   PREFIX_EVEX_0F3850,
1599   PREFIX_EVEX_0F3851,
1600   PREFIX_EVEX_0F3852,
1601   PREFIX_EVEX_0F3853,
1602   PREFIX_EVEX_0F3854,
1603   PREFIX_EVEX_0F3855,
1604   PREFIX_EVEX_0F3858,
1605   PREFIX_EVEX_0F3859,
1606   PREFIX_EVEX_0F385A,
1607   PREFIX_EVEX_0F385B,
1608   PREFIX_EVEX_0F3862,
1609   PREFIX_EVEX_0F3863,
1610   PREFIX_EVEX_0F3864,
1611   PREFIX_EVEX_0F3865,
1612   PREFIX_EVEX_0F3866,
1613   PREFIX_EVEX_0F3868,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F2A_P_1,
1822   VEX_LEN_0F2A_P_3,
1823   VEX_LEN_0F2C_P_1,
1824   VEX_LEN_0F2C_P_3,
1825   VEX_LEN_0F2D_P_1,
1826   VEX_LEN_0F2D_P_3,
1827   VEX_LEN_0F41_P_0,
1828   VEX_LEN_0F41_P_2,
1829   VEX_LEN_0F42_P_0,
1830   VEX_LEN_0F42_P_2,
1831   VEX_LEN_0F44_P_0,
1832   VEX_LEN_0F44_P_2,
1833   VEX_LEN_0F45_P_0,
1834   VEX_LEN_0F45_P_2,
1835   VEX_LEN_0F46_P_0,
1836   VEX_LEN_0F46_P_2,
1837   VEX_LEN_0F47_P_0,
1838   VEX_LEN_0F47_P_2,
1839   VEX_LEN_0F4A_P_0,
1840   VEX_LEN_0F4A_P_2,
1841   VEX_LEN_0F4B_P_0,
1842   VEX_LEN_0F4B_P_2,
1843   VEX_LEN_0F6E_P_2,
1844   VEX_LEN_0F77_P_0,
1845   VEX_LEN_0F7E_P_1,
1846   VEX_LEN_0F7E_P_2,
1847   VEX_LEN_0F90_P_0,
1848   VEX_LEN_0F90_P_2,
1849   VEX_LEN_0F91_P_0,
1850   VEX_LEN_0F91_P_2,
1851   VEX_LEN_0F92_P_0,
1852   VEX_LEN_0F92_P_2,
1853   VEX_LEN_0F92_P_3,
1854   VEX_LEN_0F93_P_0,
1855   VEX_LEN_0F93_P_2,
1856   VEX_LEN_0F93_P_3,
1857   VEX_LEN_0F98_P_0,
1858   VEX_LEN_0F98_P_2,
1859   VEX_LEN_0F99_P_0,
1860   VEX_LEN_0F99_P_2,
1861   VEX_LEN_0FAE_R_2_M_0,
1862   VEX_LEN_0FAE_R_3_M_0,
1863   VEX_LEN_0FC4_P_2,
1864   VEX_LEN_0FC5_P_2,
1865   VEX_LEN_0FD6_P_2,
1866   VEX_LEN_0FF7_P_2,
1867   VEX_LEN_0F3816_P_2,
1868   VEX_LEN_0F3819_P_2,
1869   VEX_LEN_0F381A_P_2_M_0,
1870   VEX_LEN_0F3836_P_2,
1871   VEX_LEN_0F3841_P_2,
1872   VEX_LEN_0F385A_P_2_M_0,
1873   VEX_LEN_0F38DB_P_2,
1874   VEX_LEN_0F38F2_P_0,
1875   VEX_LEN_0F38F3_R_1_P_0,
1876   VEX_LEN_0F38F3_R_2_P_0,
1877   VEX_LEN_0F38F3_R_3_P_0,
1878   VEX_LEN_0F38F5_P_0,
1879   VEX_LEN_0F38F5_P_1,
1880   VEX_LEN_0F38F5_P_3,
1881   VEX_LEN_0F38F6_P_3,
1882   VEX_LEN_0F38F7_P_0,
1883   VEX_LEN_0F38F7_P_1,
1884   VEX_LEN_0F38F7_P_2,
1885   VEX_LEN_0F38F7_P_3,
1886   VEX_LEN_0F3A00_P_2,
1887   VEX_LEN_0F3A01_P_2,
1888   VEX_LEN_0F3A06_P_2,
1889   VEX_LEN_0F3A14_P_2,
1890   VEX_LEN_0F3A15_P_2,
1891   VEX_LEN_0F3A16_P_2,
1892   VEX_LEN_0F3A17_P_2,
1893   VEX_LEN_0F3A18_P_2,
1894   VEX_LEN_0F3A19_P_2,
1895   VEX_LEN_0F3A20_P_2,
1896   VEX_LEN_0F3A21_P_2,
1897   VEX_LEN_0F3A22_P_2,
1898   VEX_LEN_0F3A30_P_2,
1899   VEX_LEN_0F3A31_P_2,
1900   VEX_LEN_0F3A32_P_2,
1901   VEX_LEN_0F3A33_P_2,
1902   VEX_LEN_0F3A38_P_2,
1903   VEX_LEN_0F3A39_P_2,
1904   VEX_LEN_0F3A41_P_2,
1905   VEX_LEN_0F3A46_P_2,
1906   VEX_LEN_0F3A60_P_2,
1907   VEX_LEN_0F3A61_P_2,
1908   VEX_LEN_0F3A62_P_2,
1909   VEX_LEN_0F3A63_P_2,
1910   VEX_LEN_0F3A6A_P_2,
1911   VEX_LEN_0F3A6B_P_2,
1912   VEX_LEN_0F3A6E_P_2,
1913   VEX_LEN_0F3A6F_P_2,
1914   VEX_LEN_0F3A7A_P_2,
1915   VEX_LEN_0F3A7B_P_2,
1916   VEX_LEN_0F3A7E_P_2,
1917   VEX_LEN_0F3A7F_P_2,
1918   VEX_LEN_0F3ADF_P_2,
1919   VEX_LEN_0F3AF0_P_3,
1920   VEX_LEN_0FXOP_08_CC,
1921   VEX_LEN_0FXOP_08_CD,
1922   VEX_LEN_0FXOP_08_CE,
1923   VEX_LEN_0FXOP_08_CF,
1924   VEX_LEN_0FXOP_08_EC,
1925   VEX_LEN_0FXOP_08_ED,
1926   VEX_LEN_0FXOP_08_EE,
1927   VEX_LEN_0FXOP_08_EF,
1928   VEX_LEN_0FXOP_09_80,
1929   VEX_LEN_0FXOP_09_81
1930 };
1931
1932 enum
1933 {
1934   EVEX_LEN_0F6E_P_2 = 0,
1935   EVEX_LEN_0F7E_P_1,
1936   EVEX_LEN_0F7E_P_2,
1937   EVEX_LEN_0FD6_P_2,
1938   EVEX_LEN_0F3819_P_2_W_0,
1939   EVEX_LEN_0F3819_P_2_W_1,
1940   EVEX_LEN_0F381A_P_2_W_0,
1941   EVEX_LEN_0F381A_P_2_W_1,
1942   EVEX_LEN_0F381B_P_2_W_0,
1943   EVEX_LEN_0F381B_P_2_W_1,
1944   EVEX_LEN_0F385A_P_2_W_0,
1945   EVEX_LEN_0F385A_P_2_W_1,
1946   EVEX_LEN_0F385B_P_2_W_0,
1947   EVEX_LEN_0F385B_P_2_W_1,
1948   EVEX_LEN_0F3A18_P_2_W_0,
1949   EVEX_LEN_0F3A18_P_2_W_1,
1950   EVEX_LEN_0F3A19_P_2_W_0,
1951   EVEX_LEN_0F3A19_P_2_W_1,
1952   EVEX_LEN_0F3A1A_P_2_W_0,
1953   EVEX_LEN_0F3A1A_P_2_W_1,
1954   EVEX_LEN_0F3A1B_P_2_W_0,
1955   EVEX_LEN_0F3A1B_P_2_W_1,
1956   EVEX_LEN_0F3A23_P_2_W_0,
1957   EVEX_LEN_0F3A23_P_2_W_1,
1958   EVEX_LEN_0F3A38_P_2_W_0,
1959   EVEX_LEN_0F3A38_P_2_W_1,
1960   EVEX_LEN_0F3A39_P_2_W_0,
1961   EVEX_LEN_0F3A39_P_2_W_1,
1962   EVEX_LEN_0F3A3A_P_2_W_0,
1963   EVEX_LEN_0F3A3A_P_2_W_1,
1964   EVEX_LEN_0F3A3B_P_2_W_0,
1965   EVEX_LEN_0F3A3B_P_2_W_1,
1966   EVEX_LEN_0F3A43_P_2_W_0,
1967   EVEX_LEN_0F3A43_P_2_W_1
1968 };
1969
1970 enum
1971 {
1972   VEX_W_0F41_P_0_LEN_1 = 0,
1973   VEX_W_0F41_P_2_LEN_1,
1974   VEX_W_0F42_P_0_LEN_1,
1975   VEX_W_0F42_P_2_LEN_1,
1976   VEX_W_0F44_P_0_LEN_0,
1977   VEX_W_0F44_P_2_LEN_0,
1978   VEX_W_0F45_P_0_LEN_1,
1979   VEX_W_0F45_P_2_LEN_1,
1980   VEX_W_0F46_P_0_LEN_1,
1981   VEX_W_0F46_P_2_LEN_1,
1982   VEX_W_0F47_P_0_LEN_1,
1983   VEX_W_0F47_P_2_LEN_1,
1984   VEX_W_0F4A_P_0_LEN_1,
1985   VEX_W_0F4A_P_2_LEN_1,
1986   VEX_W_0F4B_P_0_LEN_1,
1987   VEX_W_0F4B_P_2_LEN_1,
1988   VEX_W_0F90_P_0_LEN_0,
1989   VEX_W_0F90_P_2_LEN_0,
1990   VEX_W_0F91_P_0_LEN_0,
1991   VEX_W_0F91_P_2_LEN_0,
1992   VEX_W_0F92_P_0_LEN_0,
1993   VEX_W_0F92_P_2_LEN_0,
1994   VEX_W_0F93_P_0_LEN_0,
1995   VEX_W_0F93_P_2_LEN_0,
1996   VEX_W_0F98_P_0_LEN_0,
1997   VEX_W_0F98_P_2_LEN_0,
1998   VEX_W_0F99_P_0_LEN_0,
1999   VEX_W_0F99_P_2_LEN_0,
2000   VEX_W_0F380C_P_2,
2001   VEX_W_0F380D_P_2,
2002   VEX_W_0F380E_P_2,
2003   VEX_W_0F380F_P_2,
2004   VEX_W_0F3816_P_2,
2005   VEX_W_0F3818_P_2,
2006   VEX_W_0F3819_P_2,
2007   VEX_W_0F381A_P_2_M_0,
2008   VEX_W_0F382C_P_2_M_0,
2009   VEX_W_0F382D_P_2_M_0,
2010   VEX_W_0F382E_P_2_M_0,
2011   VEX_W_0F382F_P_2_M_0,
2012   VEX_W_0F3836_P_2,
2013   VEX_W_0F3846_P_2,
2014   VEX_W_0F3858_P_2,
2015   VEX_W_0F3859_P_2,
2016   VEX_W_0F385A_P_2_M_0,
2017   VEX_W_0F3878_P_2,
2018   VEX_W_0F3879_P_2,
2019   VEX_W_0F38CF_P_2,
2020   VEX_W_0F3A00_P_2,
2021   VEX_W_0F3A01_P_2,
2022   VEX_W_0F3A02_P_2,
2023   VEX_W_0F3A04_P_2,
2024   VEX_W_0F3A05_P_2,
2025   VEX_W_0F3A06_P_2,
2026   VEX_W_0F3A18_P_2,
2027   VEX_W_0F3A19_P_2,
2028   VEX_W_0F3A30_P_2_LEN_0,
2029   VEX_W_0F3A31_P_2_LEN_0,
2030   VEX_W_0F3A32_P_2_LEN_0,
2031   VEX_W_0F3A33_P_2_LEN_0,
2032   VEX_W_0F3A38_P_2,
2033   VEX_W_0F3A39_P_2,
2034   VEX_W_0F3A46_P_2,
2035   VEX_W_0F3A48_P_2,
2036   VEX_W_0F3A49_P_2,
2037   VEX_W_0F3A4A_P_2,
2038   VEX_W_0F3A4B_P_2,
2039   VEX_W_0F3A4C_P_2,
2040   VEX_W_0F3ACE_P_2,
2041   VEX_W_0F3ACF_P_2,
2042
2043   EVEX_W_0F10_P_0,
2044   EVEX_W_0F10_P_1_M_0,
2045   EVEX_W_0F10_P_1_M_1,
2046   EVEX_W_0F10_P_2,
2047   EVEX_W_0F10_P_3_M_0,
2048   EVEX_W_0F10_P_3_M_1,
2049   EVEX_W_0F11_P_0,
2050   EVEX_W_0F11_P_1_M_0,
2051   EVEX_W_0F11_P_1_M_1,
2052   EVEX_W_0F11_P_2,
2053   EVEX_W_0F11_P_3_M_0,
2054   EVEX_W_0F11_P_3_M_1,
2055   EVEX_W_0F12_P_0_M_0,
2056   EVEX_W_0F12_P_0_M_1,
2057   EVEX_W_0F12_P_1,
2058   EVEX_W_0F12_P_2,
2059   EVEX_W_0F12_P_3,
2060   EVEX_W_0F13_P_0,
2061   EVEX_W_0F13_P_2,
2062   EVEX_W_0F14_P_0,
2063   EVEX_W_0F14_P_2,
2064   EVEX_W_0F15_P_0,
2065   EVEX_W_0F15_P_2,
2066   EVEX_W_0F16_P_0_M_0,
2067   EVEX_W_0F16_P_0_M_1,
2068   EVEX_W_0F16_P_1,
2069   EVEX_W_0F16_P_2,
2070   EVEX_W_0F17_P_0,
2071   EVEX_W_0F17_P_2,
2072   EVEX_W_0F28_P_0,
2073   EVEX_W_0F28_P_2,
2074   EVEX_W_0F29_P_0,
2075   EVEX_W_0F29_P_2,
2076   EVEX_W_0F2A_P_3,
2077   EVEX_W_0F2B_P_0,
2078   EVEX_W_0F2B_P_2,
2079   EVEX_W_0F2E_P_0,
2080   EVEX_W_0F2E_P_2,
2081   EVEX_W_0F2F_P_0,
2082   EVEX_W_0F2F_P_2,
2083   EVEX_W_0F51_P_0,
2084   EVEX_W_0F51_P_1,
2085   EVEX_W_0F51_P_2,
2086   EVEX_W_0F51_P_3,
2087   EVEX_W_0F54_P_0,
2088   EVEX_W_0F54_P_2,
2089   EVEX_W_0F55_P_0,
2090   EVEX_W_0F55_P_2,
2091   EVEX_W_0F56_P_0,
2092   EVEX_W_0F56_P_2,
2093   EVEX_W_0F57_P_0,
2094   EVEX_W_0F57_P_2,
2095   EVEX_W_0F58_P_0,
2096   EVEX_W_0F58_P_1,
2097   EVEX_W_0F58_P_2,
2098   EVEX_W_0F58_P_3,
2099   EVEX_W_0F59_P_0,
2100   EVEX_W_0F59_P_1,
2101   EVEX_W_0F59_P_2,
2102   EVEX_W_0F59_P_3,
2103   EVEX_W_0F5A_P_0,
2104   EVEX_W_0F5A_P_1,
2105   EVEX_W_0F5A_P_2,
2106   EVEX_W_0F5A_P_3,
2107   EVEX_W_0F5B_P_0,
2108   EVEX_W_0F5B_P_1,
2109   EVEX_W_0F5B_P_2,
2110   EVEX_W_0F5C_P_0,
2111   EVEX_W_0F5C_P_1,
2112   EVEX_W_0F5C_P_2,
2113   EVEX_W_0F5C_P_3,
2114   EVEX_W_0F5D_P_0,
2115   EVEX_W_0F5D_P_1,
2116   EVEX_W_0F5D_P_2,
2117   EVEX_W_0F5D_P_3,
2118   EVEX_W_0F5E_P_0,
2119   EVEX_W_0F5E_P_1,
2120   EVEX_W_0F5E_P_2,
2121   EVEX_W_0F5E_P_3,
2122   EVEX_W_0F5F_P_0,
2123   EVEX_W_0F5F_P_1,
2124   EVEX_W_0F5F_P_2,
2125   EVEX_W_0F5F_P_3,
2126   EVEX_W_0F62_P_2,
2127   EVEX_W_0F66_P_2,
2128   EVEX_W_0F6A_P_2,
2129   EVEX_W_0F6B_P_2,
2130   EVEX_W_0F6C_P_2,
2131   EVEX_W_0F6D_P_2,
2132   EVEX_W_0F6F_P_1,
2133   EVEX_W_0F6F_P_2,
2134   EVEX_W_0F6F_P_3,
2135   EVEX_W_0F70_P_2,
2136   EVEX_W_0F72_R_2_P_2,
2137   EVEX_W_0F72_R_6_P_2,
2138   EVEX_W_0F73_R_2_P_2,
2139   EVEX_W_0F73_R_6_P_2,
2140   EVEX_W_0F76_P_2,
2141   EVEX_W_0F78_P_0,
2142   EVEX_W_0F78_P_2,
2143   EVEX_W_0F79_P_0,
2144   EVEX_W_0F79_P_2,
2145   EVEX_W_0F7A_P_1,
2146   EVEX_W_0F7A_P_2,
2147   EVEX_W_0F7A_P_3,
2148   EVEX_W_0F7B_P_2,
2149   EVEX_W_0F7B_P_3,
2150   EVEX_W_0F7E_P_1,
2151   EVEX_W_0F7F_P_1,
2152   EVEX_W_0F7F_P_2,
2153   EVEX_W_0F7F_P_3,
2154   EVEX_W_0FC2_P_0,
2155   EVEX_W_0FC2_P_1,
2156   EVEX_W_0FC2_P_2,
2157   EVEX_W_0FC2_P_3,
2158   EVEX_W_0FC6_P_0,
2159   EVEX_W_0FC6_P_2,
2160   EVEX_W_0FD2_P_2,
2161   EVEX_W_0FD3_P_2,
2162   EVEX_W_0FD4_P_2,
2163   EVEX_W_0FD6_P_2,
2164   EVEX_W_0FE6_P_1,
2165   EVEX_W_0FE6_P_2,
2166   EVEX_W_0FE6_P_3,
2167   EVEX_W_0FE7_P_2,
2168   EVEX_W_0FF2_P_2,
2169   EVEX_W_0FF3_P_2,
2170   EVEX_W_0FF4_P_2,
2171   EVEX_W_0FFA_P_2,
2172   EVEX_W_0FFB_P_2,
2173   EVEX_W_0FFE_P_2,
2174   EVEX_W_0F380C_P_2,
2175   EVEX_W_0F380D_P_2,
2176   EVEX_W_0F3810_P_1,
2177   EVEX_W_0F3810_P_2,
2178   EVEX_W_0F3811_P_1,
2179   EVEX_W_0F3811_P_2,
2180   EVEX_W_0F3812_P_1,
2181   EVEX_W_0F3812_P_2,
2182   EVEX_W_0F3813_P_1,
2183   EVEX_W_0F3813_P_2,
2184   EVEX_W_0F3814_P_1,
2185   EVEX_W_0F3815_P_1,
2186   EVEX_W_0F3818_P_2,
2187   EVEX_W_0F3819_P_2,
2188   EVEX_W_0F381A_P_2,
2189   EVEX_W_0F381B_P_2,
2190   EVEX_W_0F381E_P_2,
2191   EVEX_W_0F381F_P_2,
2192   EVEX_W_0F3820_P_1,
2193   EVEX_W_0F3821_P_1,
2194   EVEX_W_0F3822_P_1,
2195   EVEX_W_0F3823_P_1,
2196   EVEX_W_0F3824_P_1,
2197   EVEX_W_0F3825_P_1,
2198   EVEX_W_0F3825_P_2,
2199   EVEX_W_0F3826_P_1,
2200   EVEX_W_0F3826_P_2,
2201   EVEX_W_0F3828_P_1,
2202   EVEX_W_0F3828_P_2,
2203   EVEX_W_0F3829_P_1,
2204   EVEX_W_0F3829_P_2,
2205   EVEX_W_0F382A_P_1,
2206   EVEX_W_0F382A_P_2,
2207   EVEX_W_0F382B_P_2,
2208   EVEX_W_0F3830_P_1,
2209   EVEX_W_0F3831_P_1,
2210   EVEX_W_0F3832_P_1,
2211   EVEX_W_0F3833_P_1,
2212   EVEX_W_0F3834_P_1,
2213   EVEX_W_0F3835_P_1,
2214   EVEX_W_0F3835_P_2,
2215   EVEX_W_0F3837_P_2,
2216   EVEX_W_0F3838_P_1,
2217   EVEX_W_0F3839_P_1,
2218   EVEX_W_0F383A_P_1,
2219   EVEX_W_0F3840_P_2,
2220   EVEX_W_0F3852_P_1,
2221   EVEX_W_0F3854_P_2,
2222   EVEX_W_0F3855_P_2,
2223   EVEX_W_0F3858_P_2,
2224   EVEX_W_0F3859_P_2,
2225   EVEX_W_0F385A_P_2,
2226   EVEX_W_0F385B_P_2,
2227   EVEX_W_0F3862_P_2,
2228   EVEX_W_0F3863_P_2,
2229   EVEX_W_0F3866_P_2,
2230   EVEX_W_0F3868_P_3,
2231   EVEX_W_0F3870_P_2,
2232   EVEX_W_0F3871_P_2,
2233   EVEX_W_0F3872_P_1,
2234   EVEX_W_0F3872_P_2,
2235   EVEX_W_0F3872_P_3,
2236   EVEX_W_0F3873_P_2,
2237   EVEX_W_0F3875_P_2,
2238   EVEX_W_0F3878_P_2,
2239   EVEX_W_0F3879_P_2,
2240   EVEX_W_0F387A_P_2,
2241   EVEX_W_0F387B_P_2,
2242   EVEX_W_0F387D_P_2,
2243   EVEX_W_0F3883_P_2,
2244   EVEX_W_0F388D_P_2,
2245   EVEX_W_0F3891_P_2,
2246   EVEX_W_0F3893_P_2,
2247   EVEX_W_0F38A1_P_2,
2248   EVEX_W_0F38A3_P_2,
2249   EVEX_W_0F38C7_R_1_P_2,
2250   EVEX_W_0F38C7_R_2_P_2,
2251   EVEX_W_0F38C7_R_5_P_2,
2252   EVEX_W_0F38C7_R_6_P_2,
2253
2254   EVEX_W_0F3A00_P_2,
2255   EVEX_W_0F3A01_P_2,
2256   EVEX_W_0F3A04_P_2,
2257   EVEX_W_0F3A05_P_2,
2258   EVEX_W_0F3A08_P_2,
2259   EVEX_W_0F3A09_P_2,
2260   EVEX_W_0F3A0A_P_2,
2261   EVEX_W_0F3A0B_P_2,
2262   EVEX_W_0F3A18_P_2,
2263   EVEX_W_0F3A19_P_2,
2264   EVEX_W_0F3A1A_P_2,
2265   EVEX_W_0F3A1B_P_2,
2266   EVEX_W_0F3A1D_P_2,
2267   EVEX_W_0F3A21_P_2,
2268   EVEX_W_0F3A23_P_2,
2269   EVEX_W_0F3A38_P_2,
2270   EVEX_W_0F3A39_P_2,
2271   EVEX_W_0F3A3A_P_2,
2272   EVEX_W_0F3A3B_P_2,
2273   EVEX_W_0F3A3E_P_2,
2274   EVEX_W_0F3A3F_P_2,
2275   EVEX_W_0F3A42_P_2,
2276   EVEX_W_0F3A43_P_2,
2277   EVEX_W_0F3A50_P_2,
2278   EVEX_W_0F3A51_P_2,
2279   EVEX_W_0F3A56_P_2,
2280   EVEX_W_0F3A57_P_2,
2281   EVEX_W_0F3A66_P_2,
2282   EVEX_W_0F3A67_P_2,
2283   EVEX_W_0F3A70_P_2,
2284   EVEX_W_0F3A71_P_2,
2285   EVEX_W_0F3A72_P_2,
2286   EVEX_W_0F3A73_P_2,
2287   EVEX_W_0F3ACE_P_2,
2288   EVEX_W_0F3ACF_P_2
2289 };
2290
2291 typedef void (*op_rtn) (int bytemode, int sizeflag);
2292
2293 struct dis386 {
2294   const char *name;
2295   struct
2296     {
2297       op_rtn rtn;
2298       int bytemode;
2299     } op[MAX_OPERANDS];
2300   unsigned int prefix_requirement;
2301 };
2302
2303 /* Upper case letters in the instruction names here are macros.
2304    'A' => print 'b' if no register operands or suffix_always is true
2305    'B' => print 'b' if suffix_always is true
2306    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2307           size prefix
2308    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2309           suffix_always is true
2310    'E' => print 'e' if 32-bit form of jcxz
2311    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2312    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2313    'H' => print ",pt" or ",pn" branch hint
2314    'I' => honor following macro letter even in Intel mode (implemented only
2315           for some of the macro letters)
2316    'J' => print 'l'
2317    'K' => print 'd' or 'q' if rex prefix is present.
2318    'L' => print 'l' if suffix_always is true
2319    'M' => print 'r' if intel_mnemonic is false.
2320    'N' => print 'n' if instruction has no wait "prefix"
2321    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2322    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2323           or suffix_always is true.  print 'q' if rex prefix is present.
2324    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2325           is true
2326    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2327    'S' => print 'w', 'l' or 'q' if suffix_always is true
2328    'T' => print 'q' in 64bit mode if instruction has no operand size
2329           prefix and behave as 'P' otherwise
2330    'U' => print 'q' in 64bit mode if instruction has no operand size
2331           prefix and behave as 'Q' otherwise
2332    'V' => print 'q' in 64bit mode if instruction has no operand size
2333           prefix and behave as 'S' otherwise
2334    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2335    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2336    'Y' unused.
2337    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2338    '!' => change condition from true to false or from false to true.
2339    '%' => add 1 upper case letter to the macro.
2340    '^' => print 'w' or 'l' depending on operand size prefix or
2341           suffix_always is true (lcall/ljmp).
2342    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2343           on operand size prefix.
2344    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2345           has no operand size prefix for AMD64 ISA, behave as 'P'
2346           otherwise
2347
2348    2 upper case letter macros:
2349    "XY" => print 'x' or 'y' if suffix_always is true or no register
2350            operands and no broadcast.
2351    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2352            register operands and no broadcast.
2353    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2354    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2355            or suffix_always is true
2356    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2357    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2358    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2359    "LW" => print 'd', 'q' depending on the VEX.W bit
2360    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2361            an operand size prefix, or suffix_always is true.  print
2362            'q' if rex prefix is present.
2363
2364    Many of the above letters print nothing in Intel mode.  See "putop"
2365    for the details.
2366
2367    Braces '{' and '}', and vertical bars '|', indicate alternative
2368    mnemonic strings for AT&T and Intel.  */
2369
2370 static const struct dis386 dis386[] = {
2371   /* 00 */
2372   { "addB",             { Ebh1, Gb }, 0 },
2373   { "addS",             { Evh1, Gv }, 0 },
2374   { "addB",             { Gb, EbS }, 0 },
2375   { "addS",             { Gv, EvS }, 0 },
2376   { "addB",             { AL, Ib }, 0 },
2377   { "addS",             { eAX, Iv }, 0 },
2378   { X86_64_TABLE (X86_64_06) },
2379   { X86_64_TABLE (X86_64_07) },
2380   /* 08 */
2381   { "orB",              { Ebh1, Gb }, 0 },
2382   { "orS",              { Evh1, Gv }, 0 },
2383   { "orB",              { Gb, EbS }, 0 },
2384   { "orS",              { Gv, EvS }, 0 },
2385   { "orB",              { AL, Ib }, 0 },
2386   { "orS",              { eAX, Iv }, 0 },
2387   { X86_64_TABLE (X86_64_0D) },
2388   { Bad_Opcode },       /* 0x0f extended opcode escape */
2389   /* 10 */
2390   { "adcB",             { Ebh1, Gb }, 0 },
2391   { "adcS",             { Evh1, Gv }, 0 },
2392   { "adcB",             { Gb, EbS }, 0 },
2393   { "adcS",             { Gv, EvS }, 0 },
2394   { "adcB",             { AL, Ib }, 0 },
2395   { "adcS",             { eAX, Iv }, 0 },
2396   { X86_64_TABLE (X86_64_16) },
2397   { X86_64_TABLE (X86_64_17) },
2398   /* 18 */
2399   { "sbbB",             { Ebh1, Gb }, 0 },
2400   { "sbbS",             { Evh1, Gv }, 0 },
2401   { "sbbB",             { Gb, EbS }, 0 },
2402   { "sbbS",             { Gv, EvS }, 0 },
2403   { "sbbB",             { AL, Ib }, 0 },
2404   { "sbbS",             { eAX, Iv }, 0 },
2405   { X86_64_TABLE (X86_64_1E) },
2406   { X86_64_TABLE (X86_64_1F) },
2407   /* 20 */
2408   { "andB",             { Ebh1, Gb }, 0 },
2409   { "andS",             { Evh1, Gv }, 0 },
2410   { "andB",             { Gb, EbS }, 0 },
2411   { "andS",             { Gv, EvS }, 0 },
2412   { "andB",             { AL, Ib }, 0 },
2413   { "andS",             { eAX, Iv }, 0 },
2414   { Bad_Opcode },       /* SEG ES prefix */
2415   { X86_64_TABLE (X86_64_27) },
2416   /* 28 */
2417   { "subB",             { Ebh1, Gb }, 0 },
2418   { "subS",             { Evh1, Gv }, 0 },
2419   { "subB",             { Gb, EbS }, 0 },
2420   { "subS",             { Gv, EvS }, 0 },
2421   { "subB",             { AL, Ib }, 0 },
2422   { "subS",             { eAX, Iv }, 0 },
2423   { Bad_Opcode },       /* SEG CS prefix */
2424   { X86_64_TABLE (X86_64_2F) },
2425   /* 30 */
2426   { "xorB",             { Ebh1, Gb }, 0 },
2427   { "xorS",             { Evh1, Gv }, 0 },
2428   { "xorB",             { Gb, EbS }, 0 },
2429   { "xorS",             { Gv, EvS }, 0 },
2430   { "xorB",             { AL, Ib }, 0 },
2431   { "xorS",             { eAX, Iv }, 0 },
2432   { Bad_Opcode },       /* SEG SS prefix */
2433   { X86_64_TABLE (X86_64_37) },
2434   /* 38 */
2435   { "cmpB",             { Eb, Gb }, 0 },
2436   { "cmpS",             { Ev, Gv }, 0 },
2437   { "cmpB",             { Gb, EbS }, 0 },
2438   { "cmpS",             { Gv, EvS }, 0 },
2439   { "cmpB",             { AL, Ib }, 0 },
2440   { "cmpS",             { eAX, Iv }, 0 },
2441   { Bad_Opcode },       /* SEG DS prefix */
2442   { X86_64_TABLE (X86_64_3F) },
2443   /* 40 */
2444   { "inc{S|}",          { RMeAX }, 0 },
2445   { "inc{S|}",          { RMeCX }, 0 },
2446   { "inc{S|}",          { RMeDX }, 0 },
2447   { "inc{S|}",          { RMeBX }, 0 },
2448   { "inc{S|}",          { RMeSP }, 0 },
2449   { "inc{S|}",          { RMeBP }, 0 },
2450   { "inc{S|}",          { RMeSI }, 0 },
2451   { "inc{S|}",          { RMeDI }, 0 },
2452   /* 48 */
2453   { "dec{S|}",          { RMeAX }, 0 },
2454   { "dec{S|}",          { RMeCX }, 0 },
2455   { "dec{S|}",          { RMeDX }, 0 },
2456   { "dec{S|}",          { RMeBX }, 0 },
2457   { "dec{S|}",          { RMeSP }, 0 },
2458   { "dec{S|}",          { RMeBP }, 0 },
2459   { "dec{S|}",          { RMeSI }, 0 },
2460   { "dec{S|}",          { RMeDI }, 0 },
2461   /* 50 */
2462   { "pushV",            { RMrAX }, 0 },
2463   { "pushV",            { RMrCX }, 0 },
2464   { "pushV",            { RMrDX }, 0 },
2465   { "pushV",            { RMrBX }, 0 },
2466   { "pushV",            { RMrSP }, 0 },
2467   { "pushV",            { RMrBP }, 0 },
2468   { "pushV",            { RMrSI }, 0 },
2469   { "pushV",            { RMrDI }, 0 },
2470   /* 58 */
2471   { "popV",             { RMrAX }, 0 },
2472   { "popV",             { RMrCX }, 0 },
2473   { "popV",             { RMrDX }, 0 },
2474   { "popV",             { RMrBX }, 0 },
2475   { "popV",             { RMrSP }, 0 },
2476   { "popV",             { RMrBP }, 0 },
2477   { "popV",             { RMrSI }, 0 },
2478   { "popV",             { RMrDI }, 0 },
2479   /* 60 */
2480   { X86_64_TABLE (X86_64_60) },
2481   { X86_64_TABLE (X86_64_61) },
2482   { X86_64_TABLE (X86_64_62) },
2483   { X86_64_TABLE (X86_64_63) },
2484   { Bad_Opcode },       /* seg fs */
2485   { Bad_Opcode },       /* seg gs */
2486   { Bad_Opcode },       /* op size prefix */
2487   { Bad_Opcode },       /* adr size prefix */
2488   /* 68 */
2489   { "pushT",            { sIv }, 0 },
2490   { "imulS",            { Gv, Ev, Iv }, 0 },
2491   { "pushT",            { sIbT }, 0 },
2492   { "imulS",            { Gv, Ev, sIb }, 0 },
2493   { "ins{b|}",          { Ybr, indirDX }, 0 },
2494   { X86_64_TABLE (X86_64_6D) },
2495   { "outs{b|}",         { indirDXr, Xb }, 0 },
2496   { X86_64_TABLE (X86_64_6F) },
2497   /* 70 */
2498   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2499   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2500   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2501   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2502   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2503   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2504   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2506   /* 78 */
2507   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2508   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2510   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2511   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2512   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2513   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2514   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2515   /* 80 */
2516   { REG_TABLE (REG_80) },
2517   { REG_TABLE (REG_81) },
2518   { X86_64_TABLE (X86_64_82) },
2519   { REG_TABLE (REG_83) },
2520   { "testB",            { Eb, Gb }, 0 },
2521   { "testS",            { Ev, Gv }, 0 },
2522   { "xchgB",            { Ebh2, Gb }, 0 },
2523   { "xchgS",            { Evh2, Gv }, 0 },
2524   /* 88 */
2525   { "movB",             { Ebh3, Gb }, 0 },
2526   { "movS",             { Evh3, Gv }, 0 },
2527   { "movB",             { Gb, EbS }, 0 },
2528   { "movS",             { Gv, EvS }, 0 },
2529   { "movD",             { Sv, Sw }, 0 },
2530   { MOD_TABLE (MOD_8D) },
2531   { "movD",             { Sw, Sv }, 0 },
2532   { REG_TABLE (REG_8F) },
2533   /* 90 */
2534   { PREFIX_TABLE (PREFIX_90) },
2535   { "xchgS",            { RMeCX, eAX }, 0 },
2536   { "xchgS",            { RMeDX, eAX }, 0 },
2537   { "xchgS",            { RMeBX, eAX }, 0 },
2538   { "xchgS",            { RMeSP, eAX }, 0 },
2539   { "xchgS",            { RMeBP, eAX }, 0 },
2540   { "xchgS",            { RMeSI, eAX }, 0 },
2541   { "xchgS",            { RMeDI, eAX }, 0 },
2542   /* 98 */
2543   { "cW{t|}R",          { XX }, 0 },
2544   { "cR{t|}O",          { XX }, 0 },
2545   { X86_64_TABLE (X86_64_9A) },
2546   { Bad_Opcode },       /* fwait */
2547   { "pushfT",           { XX }, 0 },
2548   { "popfT",            { XX }, 0 },
2549   { "sahf",             { XX }, 0 },
2550   { "lahf",             { XX }, 0 },
2551   /* a0 */
2552   { "mov%LB",           { AL, Ob }, 0 },
2553   { "mov%LS",           { eAX, Ov }, 0 },
2554   { "mov%LB",           { Ob, AL }, 0 },
2555   { "mov%LS",           { Ov, eAX }, 0 },
2556   { "movs{b|}",         { Ybr, Xb }, 0 },
2557   { "movs{R|}",         { Yvr, Xv }, 0 },
2558   { "cmps{b|}",         { Xb, Yb }, 0 },
2559   { "cmps{R|}",         { Xv, Yv }, 0 },
2560   /* a8 */
2561   { "testB",            { AL, Ib }, 0 },
2562   { "testS",            { eAX, Iv }, 0 },
2563   { "stosB",            { Ybr, AL }, 0 },
2564   { "stosS",            { Yvr, eAX }, 0 },
2565   { "lodsB",            { ALr, Xb }, 0 },
2566   { "lodsS",            { eAXr, Xv }, 0 },
2567   { "scasB",            { AL, Yb }, 0 },
2568   { "scasS",            { eAX, Yv }, 0 },
2569   /* b0 */
2570   { "movB",             { RMAL, Ib }, 0 },
2571   { "movB",             { RMCL, Ib }, 0 },
2572   { "movB",             { RMDL, Ib }, 0 },
2573   { "movB",             { RMBL, Ib }, 0 },
2574   { "movB",             { RMAH, Ib }, 0 },
2575   { "movB",             { RMCH, Ib }, 0 },
2576   { "movB",             { RMDH, Ib }, 0 },
2577   { "movB",             { RMBH, Ib }, 0 },
2578   /* b8 */
2579   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2580   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2581   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2582   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2583   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2584   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2585   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2586   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2587   /* c0 */
2588   { REG_TABLE (REG_C0) },
2589   { REG_TABLE (REG_C1) },
2590   { "retT",             { Iw, BND }, 0 },
2591   { "retT",             { BND }, 0 },
2592   { X86_64_TABLE (X86_64_C4) },
2593   { X86_64_TABLE (X86_64_C5) },
2594   { REG_TABLE (REG_C6) },
2595   { REG_TABLE (REG_C7) },
2596   /* c8 */
2597   { "enterT",           { Iw, Ib }, 0 },
2598   { "leaveT",           { XX }, 0 },
2599   { "Jret{|f}P",        { Iw }, 0 },
2600   { "Jret{|f}P",        { XX }, 0 },
2601   { "int3",             { XX }, 0 },
2602   { "int",              { Ib }, 0 },
2603   { X86_64_TABLE (X86_64_CE) },
2604   { "iret%LP",          { XX }, 0 },
2605   /* d0 */
2606   { REG_TABLE (REG_D0) },
2607   { REG_TABLE (REG_D1) },
2608   { REG_TABLE (REG_D2) },
2609   { REG_TABLE (REG_D3) },
2610   { X86_64_TABLE (X86_64_D4) },
2611   { X86_64_TABLE (X86_64_D5) },
2612   { Bad_Opcode },
2613   { "xlat",             { DSBX }, 0 },
2614   /* d8 */
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   { FLOAT },
2621   { FLOAT },
2622   { FLOAT },
2623   /* e0 */
2624   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2625   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2626   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2627   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2628   { "inB",              { AL, Ib }, 0 },
2629   { "inG",              { zAX, Ib }, 0 },
2630   { "outB",             { Ib, AL }, 0 },
2631   { "outG",             { Ib, zAX }, 0 },
2632   /* e8 */
2633   { X86_64_TABLE (X86_64_E8) },
2634   { X86_64_TABLE (X86_64_E9) },
2635   { X86_64_TABLE (X86_64_EA) },
2636   { "jmp",              { Jb, BND }, 0 },
2637   { "inB",              { AL, indirDX }, 0 },
2638   { "inG",              { zAX, indirDX }, 0 },
2639   { "outB",             { indirDX, AL }, 0 },
2640   { "outG",             { indirDX, zAX }, 0 },
2641   /* f0 */
2642   { Bad_Opcode },       /* lock prefix */
2643   { "icebp",            { XX }, 0 },
2644   { Bad_Opcode },       /* repne */
2645   { Bad_Opcode },       /* repz */
2646   { "hlt",              { XX }, 0 },
2647   { "cmc",              { XX }, 0 },
2648   { REG_TABLE (REG_F6) },
2649   { REG_TABLE (REG_F7) },
2650   /* f8 */
2651   { "clc",              { XX }, 0 },
2652   { "stc",              { XX }, 0 },
2653   { "cli",              { XX }, 0 },
2654   { "sti",              { XX }, 0 },
2655   { "cld",              { XX }, 0 },
2656   { "std",              { XX }, 0 },
2657   { REG_TABLE (REG_FE) },
2658   { REG_TABLE (REG_FF) },
2659 };
2660
2661 static const struct dis386 dis386_twobyte[] = {
2662   /* 00 */
2663   { REG_TABLE (REG_0F00 ) },
2664   { REG_TABLE (REG_0F01 ) },
2665   { "larS",             { Gv, Ew }, 0 },
2666   { "lslS",             { Gv, Ew }, 0 },
2667   { Bad_Opcode },
2668   { "syscall",          { XX }, 0 },
2669   { "clts",             { XX }, 0 },
2670   { "sysret%LP",                { XX }, 0 },
2671   /* 08 */
2672   { "invd",             { XX }, 0 },
2673   { PREFIX_TABLE (PREFIX_0F09) },
2674   { Bad_Opcode },
2675   { "ud2",              { XX }, 0 },
2676   { Bad_Opcode },
2677   { REG_TABLE (REG_0F0D) },
2678   { "femms",            { XX }, 0 },
2679   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2680   /* 10 */
2681   { PREFIX_TABLE (PREFIX_0F10) },
2682   { PREFIX_TABLE (PREFIX_0F11) },
2683   { PREFIX_TABLE (PREFIX_0F12) },
2684   { MOD_TABLE (MOD_0F13) },
2685   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2686   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2687   { PREFIX_TABLE (PREFIX_0F16) },
2688   { MOD_TABLE (MOD_0F17) },
2689   /* 18 */
2690   { REG_TABLE (REG_0F18) },
2691   { "nopQ",             { Ev }, 0 },
2692   { PREFIX_TABLE (PREFIX_0F1A) },
2693   { PREFIX_TABLE (PREFIX_0F1B) },
2694   { PREFIX_TABLE (PREFIX_0F1C) },
2695   { "nopQ",             { Ev }, 0 },
2696   { PREFIX_TABLE (PREFIX_0F1E) },
2697   { "nopQ",             { Ev }, 0 },
2698   /* 20 */
2699   { "movZ",             { Rm, Cm }, 0 },
2700   { "movZ",             { Rm, Dm }, 0 },
2701   { "movZ",             { Cm, Rm }, 0 },
2702   { "movZ",             { Dm, Rm }, 0 },
2703   { MOD_TABLE (MOD_0F24) },
2704   { Bad_Opcode },
2705   { MOD_TABLE (MOD_0F26) },
2706   { Bad_Opcode },
2707   /* 28 */
2708   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2709   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2710   { PREFIX_TABLE (PREFIX_0F2A) },
2711   { PREFIX_TABLE (PREFIX_0F2B) },
2712   { PREFIX_TABLE (PREFIX_0F2C) },
2713   { PREFIX_TABLE (PREFIX_0F2D) },
2714   { PREFIX_TABLE (PREFIX_0F2E) },
2715   { PREFIX_TABLE (PREFIX_0F2F) },
2716   /* 30 */
2717   { "wrmsr",            { XX }, 0 },
2718   { "rdtsc",            { XX }, 0 },
2719   { "rdmsr",            { XX }, 0 },
2720   { "rdpmc",            { XX }, 0 },
2721   { "sysenter",         { XX }, 0 },
2722   { "sysexit",          { XX }, 0 },
2723   { Bad_Opcode },
2724   { "getsec",           { XX }, 0 },
2725   /* 38 */
2726   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2727   { Bad_Opcode },
2728   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2729   { Bad_Opcode },
2730   { Bad_Opcode },
2731   { Bad_Opcode },
2732   { Bad_Opcode },
2733   { Bad_Opcode },
2734   /* 40 */
2735   { "cmovoS",           { Gv, Ev }, 0 },
2736   { "cmovnoS",          { Gv, Ev }, 0 },
2737   { "cmovbS",           { Gv, Ev }, 0 },
2738   { "cmovaeS",          { Gv, Ev }, 0 },
2739   { "cmoveS",           { Gv, Ev }, 0 },
2740   { "cmovneS",          { Gv, Ev }, 0 },
2741   { "cmovbeS",          { Gv, Ev }, 0 },
2742   { "cmovaS",           { Gv, Ev }, 0 },
2743   /* 48 */
2744   { "cmovsS",           { Gv, Ev }, 0 },
2745   { "cmovnsS",          { Gv, Ev }, 0 },
2746   { "cmovpS",           { Gv, Ev }, 0 },
2747   { "cmovnpS",          { Gv, Ev }, 0 },
2748   { "cmovlS",           { Gv, Ev }, 0 },
2749   { "cmovgeS",          { Gv, Ev }, 0 },
2750   { "cmovleS",          { Gv, Ev }, 0 },
2751   { "cmovgS",           { Gv, Ev }, 0 },
2752   /* 50 */
2753   { MOD_TABLE (MOD_0F51) },
2754   { PREFIX_TABLE (PREFIX_0F51) },
2755   { PREFIX_TABLE (PREFIX_0F52) },
2756   { PREFIX_TABLE (PREFIX_0F53) },
2757   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2758   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2759   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2760   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2761   /* 58 */
2762   { PREFIX_TABLE (PREFIX_0F58) },
2763   { PREFIX_TABLE (PREFIX_0F59) },
2764   { PREFIX_TABLE (PREFIX_0F5A) },
2765   { PREFIX_TABLE (PREFIX_0F5B) },
2766   { PREFIX_TABLE (PREFIX_0F5C) },
2767   { PREFIX_TABLE (PREFIX_0F5D) },
2768   { PREFIX_TABLE (PREFIX_0F5E) },
2769   { PREFIX_TABLE (PREFIX_0F5F) },
2770   /* 60 */
2771   { PREFIX_TABLE (PREFIX_0F60) },
2772   { PREFIX_TABLE (PREFIX_0F61) },
2773   { PREFIX_TABLE (PREFIX_0F62) },
2774   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2775   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2776   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2777   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2778   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2779   /* 68 */
2780   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2781   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2782   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2783   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2784   { PREFIX_TABLE (PREFIX_0F6C) },
2785   { PREFIX_TABLE (PREFIX_0F6D) },
2786   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2787   { PREFIX_TABLE (PREFIX_0F6F) },
2788   /* 70 */
2789   { PREFIX_TABLE (PREFIX_0F70) },
2790   { REG_TABLE (REG_0F71) },
2791   { REG_TABLE (REG_0F72) },
2792   { REG_TABLE (REG_0F73) },
2793   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2794   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2795   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2796   { "emms",             { XX }, PREFIX_OPCODE },
2797   /* 78 */
2798   { PREFIX_TABLE (PREFIX_0F78) },
2799   { PREFIX_TABLE (PREFIX_0F79) },
2800   { Bad_Opcode },
2801   { Bad_Opcode },
2802   { PREFIX_TABLE (PREFIX_0F7C) },
2803   { PREFIX_TABLE (PREFIX_0F7D) },
2804   { PREFIX_TABLE (PREFIX_0F7E) },
2805   { PREFIX_TABLE (PREFIX_0F7F) },
2806   /* 80 */
2807   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2808   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2809   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2810   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2811   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2812   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2813   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2815   /* 88 */
2816   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2817   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2819   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2820   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2821   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2822   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2823   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2824   /* 90 */
2825   { "seto",             { Eb }, 0 },
2826   { "setno",            { Eb }, 0 },
2827   { "setb",             { Eb }, 0 },
2828   { "setae",            { Eb }, 0 },
2829   { "sete",             { Eb }, 0 },
2830   { "setne",            { Eb }, 0 },
2831   { "setbe",            { Eb }, 0 },
2832   { "seta",             { Eb }, 0 },
2833   /* 98 */
2834   { "sets",             { Eb }, 0 },
2835   { "setns",            { Eb }, 0 },
2836   { "setp",             { Eb }, 0 },
2837   { "setnp",            { Eb }, 0 },
2838   { "setl",             { Eb }, 0 },
2839   { "setge",            { Eb }, 0 },
2840   { "setle",            { Eb }, 0 },
2841   { "setg",             { Eb }, 0 },
2842   /* a0 */
2843   { "pushT",            { fs }, 0 },
2844   { "popT",             { fs }, 0 },
2845   { "cpuid",            { XX }, 0 },
2846   { "btS",              { Ev, Gv }, 0 },
2847   { "shldS",            { Ev, Gv, Ib }, 0 },
2848   { "shldS",            { Ev, Gv, CL }, 0 },
2849   { REG_TABLE (REG_0FA6) },
2850   { REG_TABLE (REG_0FA7) },
2851   /* a8 */
2852   { "pushT",            { gs }, 0 },
2853   { "popT",             { gs }, 0 },
2854   { "rsm",              { XX }, 0 },
2855   { "btsS",             { Evh1, Gv }, 0 },
2856   { "shrdS",            { Ev, Gv, Ib }, 0 },
2857   { "shrdS",            { Ev, Gv, CL }, 0 },
2858   { REG_TABLE (REG_0FAE) },
2859   { "imulS",            { Gv, Ev }, 0 },
2860   /* b0 */
2861   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2862   { "cmpxchgS",         { Evh1, Gv }, 0 },
2863   { MOD_TABLE (MOD_0FB2) },
2864   { "btrS",             { Evh1, Gv }, 0 },
2865   { MOD_TABLE (MOD_0FB4) },
2866   { MOD_TABLE (MOD_0FB5) },
2867   { "movz{bR|x}",       { Gv, Eb }, 0 },
2868   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2869   /* b8 */
2870   { PREFIX_TABLE (PREFIX_0FB8) },
2871   { "ud1S",             { Gv, Ev }, 0 },
2872   { REG_TABLE (REG_0FBA) },
2873   { "btcS",             { Evh1, Gv }, 0 },
2874   { PREFIX_TABLE (PREFIX_0FBC) },
2875   { PREFIX_TABLE (PREFIX_0FBD) },
2876   { "movs{bR|x}",       { Gv, Eb }, 0 },
2877   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2878   /* c0 */
2879   { "xaddB",            { Ebh1, Gb }, 0 },
2880   { "xaddS",            { Evh1, Gv }, 0 },
2881   { PREFIX_TABLE (PREFIX_0FC2) },
2882   { MOD_TABLE (MOD_0FC3) },
2883   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2884   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2885   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2886   { REG_TABLE (REG_0FC7) },
2887   /* c8 */
2888   { "bswap",            { RMeAX }, 0 },
2889   { "bswap",            { RMeCX }, 0 },
2890   { "bswap",            { RMeDX }, 0 },
2891   { "bswap",            { RMeBX }, 0 },
2892   { "bswap",            { RMeSP }, 0 },
2893   { "bswap",            { RMeBP }, 0 },
2894   { "bswap",            { RMeSI }, 0 },
2895   { "bswap",            { RMeDI }, 0 },
2896   /* d0 */
2897   { PREFIX_TABLE (PREFIX_0FD0) },
2898   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2899   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2900   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2901   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2902   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2903   { PREFIX_TABLE (PREFIX_0FD6) },
2904   { MOD_TABLE (MOD_0FD7) },
2905   /* d8 */
2906   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2907   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2908   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2909   { "pand",             { MX, EM }, PREFIX_OPCODE },
2910   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2911   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2912   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2913   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2914   /* e0 */
2915   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2916   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2917   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2918   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2919   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2920   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2921   { PREFIX_TABLE (PREFIX_0FE6) },
2922   { PREFIX_TABLE (PREFIX_0FE7) },
2923   /* e8 */
2924   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2925   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2926   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2927   { "por",              { MX, EM }, PREFIX_OPCODE },
2928   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2929   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2930   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2931   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2932   /* f0 */
2933   { PREFIX_TABLE (PREFIX_0FF0) },
2934   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2935   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2936   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2937   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2938   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2939   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2940   { PREFIX_TABLE (PREFIX_0FF7) },
2941   /* f8 */
2942   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2943   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2944   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2945   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2946   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2947   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2948   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2949   { "ud0S",             { Gv, Ev }, 0 },
2950 };
2951
2952 static const unsigned char onebyte_has_modrm[256] = {
2953   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2954   /*       -------------------------------        */
2955   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2956   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2957   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2958   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2959   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2960   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2961   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2962   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2963   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2964   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2965   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2966   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2967   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2968   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2969   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2970   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2971   /*       -------------------------------        */
2972   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2973 };
2974
2975 static const unsigned char twobyte_has_modrm[256] = {
2976   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2977   /*       -------------------------------        */
2978   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2979   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2980   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2981   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2982   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2983   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2984   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2985   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2986   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2987   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2988   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2989   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2990   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2991   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2992   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2993   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2994   /*       -------------------------------        */
2995   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2996 };
2997
2998 static char obuf[100];
2999 static char *obufp;
3000 static char *mnemonicendp;
3001 static char scratchbuf[100];
3002 static unsigned char *start_codep;
3003 static unsigned char *insn_codep;
3004 static unsigned char *codep;
3005 static unsigned char *end_codep;
3006 static int last_lock_prefix;
3007 static int last_repz_prefix;
3008 static int last_repnz_prefix;
3009 static int last_data_prefix;
3010 static int last_addr_prefix;
3011 static int last_rex_prefix;
3012 static int last_seg_prefix;
3013 static int fwait_prefix;
3014 /* The active segment register prefix.  */
3015 static int active_seg_prefix;
3016 #define MAX_CODE_LENGTH 15
3017 /* We can up to 14 prefixes since the maximum instruction length is
3018    15bytes.  */
3019 static int all_prefixes[MAX_CODE_LENGTH - 1];
3020 static disassemble_info *the_info;
3021 static struct
3022   {
3023     int mod;
3024     int reg;
3025     int rm;
3026   }
3027 modrm;
3028 static unsigned char need_modrm;
3029 static struct
3030   {
3031     int scale;
3032     int index;
3033     int base;
3034   }
3035 sib;
3036 static struct
3037   {
3038     int register_specifier;
3039     int length;
3040     int prefix;
3041     int w;
3042     int evex;
3043     int r;
3044     int v;
3045     int mask_register_specifier;
3046     int zeroing;
3047     int ll;
3048     int b;
3049   }
3050 vex;
3051 static unsigned char need_vex;
3052 static unsigned char need_vex_reg;
3053 static unsigned char vex_w_done;
3054
3055 struct op
3056   {
3057     const char *name;
3058     unsigned int len;
3059   };
3060
3061 /* If we are accessing mod/rm/reg without need_modrm set, then the
3062    values are stale.  Hitting this abort likely indicates that you
3063    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3064 #define MODRM_CHECK  if (!need_modrm) abort ()
3065
3066 static const char **names64;
3067 static const char **names32;
3068 static const char **names16;
3069 static const char **names8;
3070 static const char **names8rex;
3071 static const char **names_seg;
3072 static const char *index64;
3073 static const char *index32;
3074 static const char **index16;
3075 static const char **names_bnd;
3076
3077 static const char *intel_names64[] = {
3078   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3079   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3080 };
3081 static const char *intel_names32[] = {
3082   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3083   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3084 };
3085 static const char *intel_names16[] = {
3086   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3087   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3088 };
3089 static const char *intel_names8[] = {
3090   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3091 };
3092 static const char *intel_names8rex[] = {
3093   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3094   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3095 };
3096 static const char *intel_names_seg[] = {
3097   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3098 };
3099 static const char *intel_index64 = "riz";
3100 static const char *intel_index32 = "eiz";
3101 static const char *intel_index16[] = {
3102   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3103 };
3104
3105 static const char *att_names64[] = {
3106   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3107   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3108 };
3109 static const char *att_names32[] = {
3110   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3111   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3112 };
3113 static const char *att_names16[] = {
3114   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3115   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3116 };
3117 static const char *att_names8[] = {
3118   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3119 };
3120 static const char *att_names8rex[] = {
3121   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3122   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3123 };
3124 static const char *att_names_seg[] = {
3125   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3126 };
3127 static const char *att_index64 = "%riz";
3128 static const char *att_index32 = "%eiz";
3129 static const char *att_index16[] = {
3130   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3131 };
3132
3133 static const char **names_mm;
3134 static const char *intel_names_mm[] = {
3135   "mm0", "mm1", "mm2", "mm3",
3136   "mm4", "mm5", "mm6", "mm7"
3137 };
3138 static const char *att_names_mm[] = {
3139   "%mm0", "%mm1", "%mm2", "%mm3",
3140   "%mm4", "%mm5", "%mm6", "%mm7"
3141 };
3142
3143 static const char *intel_names_bnd[] = {
3144   "bnd0", "bnd1", "bnd2", "bnd3"
3145 };
3146
3147 static const char *att_names_bnd[] = {
3148   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3149 };
3150
3151 static const char **names_xmm;
3152 static const char *intel_names_xmm[] = {
3153   "xmm0", "xmm1", "xmm2", "xmm3",
3154   "xmm4", "xmm5", "xmm6", "xmm7",
3155   "xmm8", "xmm9", "xmm10", "xmm11",
3156   "xmm12", "xmm13", "xmm14", "xmm15",
3157   "xmm16", "xmm17", "xmm18", "xmm19",
3158   "xmm20", "xmm21", "xmm22", "xmm23",
3159   "xmm24", "xmm25", "xmm26", "xmm27",
3160   "xmm28", "xmm29", "xmm30", "xmm31"
3161 };
3162 static const char *att_names_xmm[] = {
3163   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3164   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3165   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3166   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3167   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3168   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3169   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3170   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3171 };
3172
3173 static const char **names_ymm;
3174 static const char *intel_names_ymm[] = {
3175   "ymm0", "ymm1", "ymm2", "ymm3",
3176   "ymm4", "ymm5", "ymm6", "ymm7",
3177   "ymm8", "ymm9", "ymm10", "ymm11",
3178   "ymm12", "ymm13", "ymm14", "ymm15",
3179   "ymm16", "ymm17", "ymm18", "ymm19",
3180   "ymm20", "ymm21", "ymm22", "ymm23",
3181   "ymm24", "ymm25", "ymm26", "ymm27",
3182   "ymm28", "ymm29", "ymm30", "ymm31"
3183 };
3184 static const char *att_names_ymm[] = {
3185   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3186   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3187   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3188   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3189   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3190   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3191   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3192   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3193 };
3194
3195 static const char **names_zmm;
3196 static const char *intel_names_zmm[] = {
3197   "zmm0", "zmm1", "zmm2", "zmm3",
3198   "zmm4", "zmm5", "zmm6", "zmm7",
3199   "zmm8", "zmm9", "zmm10", "zmm11",
3200   "zmm12", "zmm13", "zmm14", "zmm15",
3201   "zmm16", "zmm17", "zmm18", "zmm19",
3202   "zmm20", "zmm21", "zmm22", "zmm23",
3203   "zmm24", "zmm25", "zmm26", "zmm27",
3204   "zmm28", "zmm29", "zmm30", "zmm31"
3205 };
3206 static const char *att_names_zmm[] = {
3207   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3208   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3209   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3210   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3211   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3212   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3213   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3214   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3215 };
3216
3217 static const char **names_mask;
3218 static const char *intel_names_mask[] = {
3219   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3220 };
3221 static const char *att_names_mask[] = {
3222   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3223 };
3224
3225 static const char *names_rounding[] =
3226 {
3227   "{rn-sae}",
3228   "{rd-sae}",
3229   "{ru-sae}",
3230   "{rz-sae}"
3231 };
3232
3233 static const struct dis386 reg_table[][8] = {
3234   /* REG_80 */
3235   {
3236     { "addA",   { Ebh1, Ib }, 0 },
3237     { "orA",    { Ebh1, Ib }, 0 },
3238     { "adcA",   { Ebh1, Ib }, 0 },
3239     { "sbbA",   { Ebh1, Ib }, 0 },
3240     { "andA",   { Ebh1, Ib }, 0 },
3241     { "subA",   { Ebh1, Ib }, 0 },
3242     { "xorA",   { Ebh1, Ib }, 0 },
3243     { "cmpA",   { Eb, Ib }, 0 },
3244   },
3245   /* REG_81 */
3246   {
3247     { "addQ",   { Evh1, Iv }, 0 },
3248     { "orQ",    { Evh1, Iv }, 0 },
3249     { "adcQ",   { Evh1, Iv }, 0 },
3250     { "sbbQ",   { Evh1, Iv }, 0 },
3251     { "andQ",   { Evh1, Iv }, 0 },
3252     { "subQ",   { Evh1, Iv }, 0 },
3253     { "xorQ",   { Evh1, Iv }, 0 },
3254     { "cmpQ",   { Ev, Iv }, 0 },
3255   },
3256   /* REG_83 */
3257   {
3258     { "addQ",   { Evh1, sIb }, 0 },
3259     { "orQ",    { Evh1, sIb }, 0 },
3260     { "adcQ",   { Evh1, sIb }, 0 },
3261     { "sbbQ",   { Evh1, sIb }, 0 },
3262     { "andQ",   { Evh1, sIb }, 0 },
3263     { "subQ",   { Evh1, sIb }, 0 },
3264     { "xorQ",   { Evh1, sIb }, 0 },
3265     { "cmpQ",   { Ev, sIb }, 0 },
3266   },
3267   /* REG_8F */
3268   {
3269     { "popU",   { stackEv }, 0 },
3270     { XOP_8F_TABLE (XOP_09) },
3271     { Bad_Opcode },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { XOP_8F_TABLE (XOP_09) },
3275   },
3276   /* REG_C0 */
3277   {
3278     { "rolA",   { Eb, Ib }, 0 },
3279     { "rorA",   { Eb, Ib }, 0 },
3280     { "rclA",   { Eb, Ib }, 0 },
3281     { "rcrA",   { Eb, Ib }, 0 },
3282     { "shlA",   { Eb, Ib }, 0 },
3283     { "shrA",   { Eb, Ib }, 0 },
3284     { "shlA",   { Eb, Ib }, 0 },
3285     { "sarA",   { Eb, Ib }, 0 },
3286   },
3287   /* REG_C1 */
3288   {
3289     { "rolQ",   { Ev, Ib }, 0 },
3290     { "rorQ",   { Ev, Ib }, 0 },
3291     { "rclQ",   { Ev, Ib }, 0 },
3292     { "rcrQ",   { Ev, Ib }, 0 },
3293     { "shlQ",   { Ev, Ib }, 0 },
3294     { "shrQ",   { Ev, Ib }, 0 },
3295     { "shlQ",   { Ev, Ib }, 0 },
3296     { "sarQ",   { Ev, Ib }, 0 },
3297   },
3298   /* REG_C6 */
3299   {
3300     { "movA",   { Ebh3, Ib }, 0 },
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { MOD_TABLE (MOD_C6_REG_7) },
3308   },
3309   /* REG_C7 */
3310   {
3311     { "movQ",   { Evh3, Iv }, 0 },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { MOD_TABLE (MOD_C7_REG_7) },
3319   },
3320   /* REG_D0 */
3321   {
3322     { "rolA",   { Eb, I1 }, 0 },
3323     { "rorA",   { Eb, I1 }, 0 },
3324     { "rclA",   { Eb, I1 }, 0 },
3325     { "rcrA",   { Eb, I1 }, 0 },
3326     { "shlA",   { Eb, I1 }, 0 },
3327     { "shrA",   { Eb, I1 }, 0 },
3328     { "shlA",   { Eb, I1 }, 0 },
3329     { "sarA",   { Eb, I1 }, 0 },
3330   },
3331   /* REG_D1 */
3332   {
3333     { "rolQ",   { Ev, I1 }, 0 },
3334     { "rorQ",   { Ev, I1 }, 0 },
3335     { "rclQ",   { Ev, I1 }, 0 },
3336     { "rcrQ",   { Ev, I1 }, 0 },
3337     { "shlQ",   { Ev, I1 }, 0 },
3338     { "shrQ",   { Ev, I1 }, 0 },
3339     { "shlQ",   { Ev, I1 }, 0 },
3340     { "sarQ",   { Ev, I1 }, 0 },
3341   },
3342   /* REG_D2 */
3343   {
3344     { "rolA",   { Eb, CL }, 0 },
3345     { "rorA",   { Eb, CL }, 0 },
3346     { "rclA",   { Eb, CL }, 0 },
3347     { "rcrA",   { Eb, CL }, 0 },
3348     { "shlA",   { Eb, CL }, 0 },
3349     { "shrA",   { Eb, CL }, 0 },
3350     { "shlA",   { Eb, CL }, 0 },
3351     { "sarA",   { Eb, CL }, 0 },
3352   },
3353   /* REG_D3 */
3354   {
3355     { "rolQ",   { Ev, CL }, 0 },
3356     { "rorQ",   { Ev, CL }, 0 },
3357     { "rclQ",   { Ev, CL }, 0 },
3358     { "rcrQ",   { Ev, CL }, 0 },
3359     { "shlQ",   { Ev, CL }, 0 },
3360     { "shrQ",   { Ev, CL }, 0 },
3361     { "shlQ",   { Ev, CL }, 0 },
3362     { "sarQ",   { Ev, CL }, 0 },
3363   },
3364   /* REG_F6 */
3365   {
3366     { "testA",  { Eb, Ib }, 0 },
3367     { "testA",  { Eb, Ib }, 0 },
3368     { "notA",   { Ebh1 }, 0 },
3369     { "negA",   { Ebh1 }, 0 },
3370     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3371     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3372     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3373     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3374   },
3375   /* REG_F7 */
3376   {
3377     { "testQ",  { Ev, Iv }, 0 },
3378     { "testQ",  { Ev, Iv }, 0 },
3379     { "notQ",   { Evh1 }, 0 },
3380     { "negQ",   { Evh1 }, 0 },
3381     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3382     { "imulQ",  { Ev }, 0 },
3383     { "divQ",   { Ev }, 0 },
3384     { "idivQ",  { Ev }, 0 },
3385   },
3386   /* REG_FE */
3387   {
3388     { "incA",   { Ebh1 }, 0 },
3389     { "decA",   { Ebh1 }, 0 },
3390   },
3391   /* REG_FF */
3392   {
3393     { "incQ",   { Evh1 }, 0 },
3394     { "decQ",   { Evh1 }, 0 },
3395     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3396     { MOD_TABLE (MOD_FF_REG_3) },
3397     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3398     { MOD_TABLE (MOD_FF_REG_5) },
3399     { "pushU",  { stackEv }, 0 },
3400     { Bad_Opcode },
3401   },
3402   /* REG_0F00 */
3403   {
3404     { "sldtD",  { Sv }, 0 },
3405     { "strD",   { Sv }, 0 },
3406     { "lldt",   { Ew }, 0 },
3407     { "ltr",    { Ew }, 0 },
3408     { "verr",   { Ew }, 0 },
3409     { "verw",   { Ew }, 0 },
3410     { Bad_Opcode },
3411     { Bad_Opcode },
3412   },
3413   /* REG_0F01 */
3414   {
3415     { MOD_TABLE (MOD_0F01_REG_0) },
3416     { MOD_TABLE (MOD_0F01_REG_1) },
3417     { MOD_TABLE (MOD_0F01_REG_2) },
3418     { MOD_TABLE (MOD_0F01_REG_3) },
3419     { "smswD",  { Sv }, 0 },
3420     { MOD_TABLE (MOD_0F01_REG_5) },
3421     { "lmsw",   { Ew }, 0 },
3422     { MOD_TABLE (MOD_0F01_REG_7) },
3423   },
3424   /* REG_0F0D */
3425   {
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetchw",      { Mb }, 0 },
3428     { "prefetchwt1",    { Mb }, 0 },
3429     { "prefetch",       { Mb }, 0 },
3430     { "prefetch",       { Mb }, 0 },
3431     { "prefetch",       { Mb }, 0 },
3432     { "prefetch",       { Mb }, 0 },
3433     { "prefetch",       { Mb }, 0 },
3434   },
3435   /* REG_0F18 */
3436   {
3437     { MOD_TABLE (MOD_0F18_REG_0) },
3438     { MOD_TABLE (MOD_0F18_REG_1) },
3439     { MOD_TABLE (MOD_0F18_REG_2) },
3440     { MOD_TABLE (MOD_0F18_REG_3) },
3441     { MOD_TABLE (MOD_0F18_REG_4) },
3442     { MOD_TABLE (MOD_0F18_REG_5) },
3443     { MOD_TABLE (MOD_0F18_REG_6) },
3444     { MOD_TABLE (MOD_0F18_REG_7) },
3445   },
3446   /* REG_0F1C_MOD_0 */
3447   {
3448     { "cldemote",       { Mb }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452     { "nopQ",           { Ev }, 0 },
3453     { "nopQ",           { Ev }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456   },
3457   /* REG_0F1E_MOD_3 */
3458   {
3459     { "nopQ",           { Ev }, 0 },
3460     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3461     { "nopQ",           { Ev }, 0 },
3462     { "nopQ",           { Ev }, 0 },
3463     { "nopQ",           { Ev }, 0 },
3464     { "nopQ",           { Ev }, 0 },
3465     { "nopQ",           { Ev }, 0 },
3466     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3467   },
3468   /* REG_0F71 */
3469   {
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { MOD_TABLE (MOD_0F71_REG_2) },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0F71_REG_4) },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F71_REG_6) },
3477   },
3478   /* REG_0F72 */
3479   {
3480     { Bad_Opcode },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0F72_REG_2) },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_0F72_REG_4) },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_0F72_REG_6) },
3487   },
3488   /* REG_0F73 */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_0F73_REG_2) },
3493     { MOD_TABLE (MOD_0F73_REG_3) },
3494     { Bad_Opcode },
3495     { Bad_Opcode },
3496     { MOD_TABLE (MOD_0F73_REG_6) },
3497     { MOD_TABLE (MOD_0F73_REG_7) },
3498   },
3499   /* REG_0FA6 */
3500   {
3501     { "montmul",        { { OP_0f07, 0 } }, 0 },
3502     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3503     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3504   },
3505   /* REG_0FA7 */
3506   {
3507     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3508     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3509     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3510     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3511     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3512     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3513   },
3514   /* REG_0FAE */
3515   {
3516     { MOD_TABLE (MOD_0FAE_REG_0) },
3517     { MOD_TABLE (MOD_0FAE_REG_1) },
3518     { MOD_TABLE (MOD_0FAE_REG_2) },
3519     { MOD_TABLE (MOD_0FAE_REG_3) },
3520     { MOD_TABLE (MOD_0FAE_REG_4) },
3521     { MOD_TABLE (MOD_0FAE_REG_5) },
3522     { MOD_TABLE (MOD_0FAE_REG_6) },
3523     { MOD_TABLE (MOD_0FAE_REG_7) },
3524   },
3525   /* REG_0FBA */
3526   {
3527     { Bad_Opcode },
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { "btQ",    { Ev, Ib }, 0 },
3532     { "btsQ",   { Evh1, Ib }, 0 },
3533     { "btrQ",   { Evh1, Ib }, 0 },
3534     { "btcQ",   { Evh1, Ib }, 0 },
3535   },
3536   /* REG_0FC7 */
3537   {
3538     { Bad_Opcode },
3539     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3540     { Bad_Opcode },
3541     { MOD_TABLE (MOD_0FC7_REG_3) },
3542     { MOD_TABLE (MOD_0FC7_REG_4) },
3543     { MOD_TABLE (MOD_0FC7_REG_5) },
3544     { MOD_TABLE (MOD_0FC7_REG_6) },
3545     { MOD_TABLE (MOD_0FC7_REG_7) },
3546   },
3547   /* REG_VEX_0F71 */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3556   },
3557   /* REG_VEX_0F72 */
3558   {
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3562     { Bad_Opcode },
3563     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3566   },
3567   /* REG_VEX_0F73 */
3568   {
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3572     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3576     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3577   },
3578   /* REG_VEX_0FAE */
3579   {
3580     { Bad_Opcode },
3581     { Bad_Opcode },
3582     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3583     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3584   },
3585   /* REG_VEX_0F38F3 */
3586   {
3587     { Bad_Opcode },
3588     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3589     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3590     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3591   },
3592   /* REG_XOP_LWPCB */
3593   {
3594     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3595     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3596   },
3597   /* REG_XOP_LWP */
3598   {
3599     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3600     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3601   },
3602   /* REG_XOP_TBM_01 */
3603   {
3604     { Bad_Opcode },
3605     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3606     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3607     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3608     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3609     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3610     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3611     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3612   },
3613   /* REG_XOP_TBM_02 */
3614   {
3615     { Bad_Opcode },
3616     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3617     { Bad_Opcode },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3622   },
3623
3624 #include "i386-dis-evex-reg.h"
3625 };
3626
3627 static const struct dis386 prefix_table[][4] = {
3628   /* PREFIX_90 */
3629   {
3630     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3631     { "pause", { XX }, 0 },
3632     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3633     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3634   },
3635
3636   /* PREFIX_MOD_0_0F01_REG_5 */
3637   {
3638     { Bad_Opcode },
3639     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3643   {
3644     { Bad_Opcode },
3645     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3649   {
3650     { Bad_Opcode },
3651     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F09 */
3655   {
3656     { "wbinvd",   { XX }, 0 },
3657     { "wbnoinvd", { XX }, 0 },
3658   },
3659
3660   /* PREFIX_0F10 */
3661   {
3662     { "movups", { XM, EXx }, PREFIX_OPCODE },
3663     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3664     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3665     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3666   },
3667
3668   /* PREFIX_0F11 */
3669   {
3670     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3671     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3672     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3673     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3674   },
3675
3676   /* PREFIX_0F12 */
3677   {
3678     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3679     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3680     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3681     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3682   },
3683
3684   /* PREFIX_0F16 */
3685   {
3686     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3687     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3688     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3689   },
3690
3691   /* PREFIX_0F1A */
3692   {
3693     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3694     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3695     { "bndmov", { Gbnd, Ebnd }, 0 },
3696     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3697   },
3698
3699   /* PREFIX_0F1B */
3700   {
3701     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3702     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3703     { "bndmov", { EbndS, Gbnd }, 0 },
3704     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3705   },
3706
3707   /* PREFIX_0F1C */
3708   {
3709     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3710     { "nopQ",   { Ev }, PREFIX_OPCODE },
3711     { "nopQ",   { Ev }, PREFIX_OPCODE },
3712     { "nopQ",   { Ev }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F1E */
3716   {
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3719     { "nopQ",   { Ev }, PREFIX_OPCODE },
3720     { "nopQ",   { Ev }, PREFIX_OPCODE },
3721   },
3722
3723   /* PREFIX_0F2A */
3724   {
3725     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3726     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3727     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3728     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3729   },
3730
3731   /* PREFIX_0F2B */
3732   {
3733     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3734     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3737   },
3738
3739   /* PREFIX_0F2C */
3740   {
3741     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3742     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3743     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3744     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3745   },
3746
3747   /* PREFIX_0F2D */
3748   {
3749     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3750     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3751     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3752     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3753   },
3754
3755   /* PREFIX_0F2E */
3756   {
3757     { "ucomiss",{ XM, EXd }, 0 },
3758     { Bad_Opcode },
3759     { "ucomisd",{ XM, EXq }, 0 },
3760   },
3761
3762   /* PREFIX_0F2F */
3763   {
3764     { "comiss", { XM, EXd }, 0 },
3765     { Bad_Opcode },
3766     { "comisd", { XM, EXq }, 0 },
3767   },
3768
3769   /* PREFIX_0F51 */
3770   {
3771     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3772     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3773     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3774     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F52 */
3778   {
3779     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3780     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F53 */
3784   {
3785     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3786     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F58 */
3790   {
3791     { "addps", { XM, EXx }, PREFIX_OPCODE },
3792     { "addss", { XM, EXd }, PREFIX_OPCODE },
3793     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3794     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F59 */
3798   {
3799     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3800     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3801     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3802     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F5A */
3806   {
3807     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3808     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3809     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3810     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F5B */
3814   {
3815     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3816     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3817     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F5C */
3821   {
3822     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3823     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3824     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3825     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F5D */
3829   {
3830     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3831     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3832     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3833     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F5E */
3837   {
3838     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3839     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3840     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3841     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F5F */
3845   {
3846     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3847     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3848     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3849     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3850   },
3851
3852   /* PREFIX_0F60 */
3853   {
3854     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3855     { Bad_Opcode },
3856     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F61 */
3860   {
3861     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3862     { Bad_Opcode },
3863     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0F62 */
3867   {
3868     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3869     { Bad_Opcode },
3870     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F6C */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3878   },
3879
3880   /* PREFIX_0F6D */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3885   },
3886
3887   /* PREFIX_0F6F */
3888   {
3889     { "movq",   { MX, EM }, PREFIX_OPCODE },
3890     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3891     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3892   },
3893
3894   /* PREFIX_0F70 */
3895   {
3896     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3897     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3898     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3899     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3900   },
3901
3902   /* PREFIX_0F73_REG_3 */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "psrldq", { XS, Ib }, 0 },
3907   },
3908
3909   /* PREFIX_0F73_REG_7 */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "pslldq", { XS, Ib }, 0 },
3914   },
3915
3916   /* PREFIX_0F78 */
3917   {
3918     {"vmread",  { Em, Gm }, 0 },
3919     { Bad_Opcode },
3920     {"extrq",   { XS, Ib, Ib }, 0 },
3921     {"insertq", { XM, XS, Ib, Ib }, 0 },
3922   },
3923
3924   /* PREFIX_0F79 */
3925   {
3926     {"vmwrite", { Gm, Em }, 0 },
3927     { Bad_Opcode },
3928     {"extrq",   { XM, XS }, 0 },
3929     {"insertq", { XM, XS }, 0 },
3930   },
3931
3932   /* PREFIX_0F7C */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3937     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0F7D */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3945     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3946   },
3947
3948   /* PREFIX_0F7E */
3949   {
3950     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3951     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3952     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3953   },
3954
3955   /* PREFIX_0F7F */
3956   {
3957     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3958     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3959     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3960   },
3961
3962   /* PREFIX_0FAE_REG_0 */
3963   {
3964     { Bad_Opcode },
3965     { "rdfsbase", { Ev }, 0 },
3966   },
3967
3968   /* PREFIX_0FAE_REG_1 */
3969   {
3970     { Bad_Opcode },
3971     { "rdgsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_2 */
3975   {
3976     { Bad_Opcode },
3977     { "wrfsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_3 */
3981   {
3982     { Bad_Opcode },
3983     { "wrgsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_MOD_0_0FAE_REG_4 */
3987   {
3988     { "xsave",  { FXSAVE }, 0 },
3989     { "ptwrite%LQ", { Edq }, 0 },
3990   },
3991
3992   /* PREFIX_MOD_3_0FAE_REG_4 */
3993   {
3994     { Bad_Opcode },
3995     { "ptwrite%LQ", { Edq }, 0 },
3996   },
3997
3998   /* PREFIX_MOD_0_0FAE_REG_5 */
3999   {
4000     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4001   },
4002
4003   /* PREFIX_MOD_3_0FAE_REG_5 */
4004   {
4005     { "lfence",         { Skip_MODRM }, 0 },
4006     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_MOD_0_0FAE_REG_6 */
4010   {
4011     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4012     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4013     { "clwb",   { Mb }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_MOD_1_0FAE_REG_6 */
4017   {
4018     { RM_TABLE (RM_0FAE_REG_6) },
4019     { "umonitor",       { Eva }, PREFIX_OPCODE },
4020     { "tpause", { Edq }, PREFIX_OPCODE },
4021     { "umwait", { Edq }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0FAE_REG_7 */
4025   {
4026     { "clflush",        { Mb }, 0 },
4027     { Bad_Opcode },
4028     { "clflushopt",     { Mb }, 0 },
4029   },
4030
4031   /* PREFIX_0FB8 */
4032   {
4033     { Bad_Opcode },
4034     { "popcntS", { Gv, Ev }, 0 },
4035   },
4036
4037   /* PREFIX_0FBC */
4038   {
4039     { "bsfS",   { Gv, Ev }, 0 },
4040     { "tzcntS", { Gv, Ev }, 0 },
4041     { "bsfS",   { Gv, Ev }, 0 },
4042   },
4043
4044   /* PREFIX_0FBD */
4045   {
4046     { "bsrS",   { Gv, Ev }, 0 },
4047     { "lzcntS", { Gv, Ev }, 0 },
4048     { "bsrS",   { Gv, Ev }, 0 },
4049   },
4050
4051   /* PREFIX_0FC2 */
4052   {
4053     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4054     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4055     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4056     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4057   },
4058
4059   /* PREFIX_MOD_0_0FC3 */
4060   {
4061     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_MOD_0_0FC7_REG_6 */
4065   {
4066     { "vmptrld",{ Mq }, 0 },
4067     { "vmxon",  { Mq }, 0 },
4068     { "vmclear",{ Mq }, 0 },
4069   },
4070
4071   /* PREFIX_MOD_3_0FC7_REG_6 */
4072   {
4073     { "rdrand", { Ev }, 0 },
4074     { Bad_Opcode },
4075     { "rdrand", { Ev }, 0 }
4076   },
4077
4078   /* PREFIX_MOD_3_0FC7_REG_7 */
4079   {
4080     { "rdseed", { Ev }, 0 },
4081     { "rdpid",  { Em }, 0 },
4082     { "rdseed", { Ev }, 0 },
4083   },
4084
4085   /* PREFIX_0FD0 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { "addsubpd", { XM, EXx }, 0 },
4090     { "addsubps", { XM, EXx }, 0 },
4091   },
4092
4093   /* PREFIX_0FD6 */
4094   {
4095     { Bad_Opcode },
4096     { "movq2dq",{ XM, MS }, 0 },
4097     { "movq",   { EXqS, XM }, 0 },
4098     { "movdq2q",{ MX, XS }, 0 },
4099   },
4100
4101   /* PREFIX_0FE6 */
4102   {
4103     { Bad_Opcode },
4104     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4105     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4106     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4107   },
4108
4109   /* PREFIX_0FE7 */
4110   {
4111     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4112     { Bad_Opcode },
4113     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4114   },
4115
4116   /* PREFIX_0FF0 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4122   },
4123
4124   /* PREFIX_0FF7 */
4125   {
4126     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4127     { Bad_Opcode },
4128     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3810 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3814 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3815 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3817 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3820 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F3821 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F3822 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F3823 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F3824 */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F3825 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F3828 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F3829 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F382A */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4220   },
4221
4222   /* PREFIX_0F382B */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F3830 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F3831 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F3832 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F3833 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F3834 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F3835 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F3837 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F3838 */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F3839 */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F383A */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F383B */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F383C */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4311   },
4312
4313   /* PREFIX_0F383D */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F383E */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F383F */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F3840 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F3841 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3880 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F3881 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F3882 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38C8 */
4370   {
4371     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38C9 */
4375   {
4376     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F38CA */
4380   {
4381     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F38CB */
4385   {
4386     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38CC */
4390   {
4391     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38CD */
4395   {
4396     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38CF */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F38DB */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38DC */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38DD */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F38DE */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F38DF */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38F0 */
4442   {
4443     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4444     { Bad_Opcode },
4445     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4446     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F38F1 */
4450   {
4451     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4452     { Bad_Opcode },
4453     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4454     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F38F5 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4462   },
4463
4464   /* PREFIX_0F38F6 */
4465   {
4466     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4467     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4468     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4469     { Bad_Opcode },
4470   },
4471
4472   /* PREFIX_0F38F8 */
4473   {
4474     { Bad_Opcode },
4475     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4476     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4477     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4478   },
4479
4480   /* PREFIX_0F38F9 */
4481   {
4482     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4483   },
4484
4485   /* PREFIX_0F3A08 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F3A09 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F3A0A */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4504   },
4505
4506   /* PREFIX_0F3A0B */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4511   },
4512
4513   /* PREFIX_0F3A0C */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4518   },
4519
4520   /* PREFIX_0F3A0D */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4525   },
4526
4527   /* PREFIX_0F3A0E */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4532   },
4533
4534   /* PREFIX_0F3A14 */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4539   },
4540
4541   /* PREFIX_0F3A15 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F3A16 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4553   },
4554
4555   /* PREFIX_0F3A17 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F3A20 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4567   },
4568
4569   /* PREFIX_0F3A21 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4574   },
4575
4576   /* PREFIX_0F3A22 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4581   },
4582
4583   /* PREFIX_0F3A40 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4588   },
4589
4590   /* PREFIX_0F3A41 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4595   },
4596
4597   /* PREFIX_0F3A42 */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F3A44 */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4609   },
4610
4611   /* PREFIX_0F3A60 */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F3A61 */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3A62 */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3A63 */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_0F3ACC */
4640   {
4641     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3ACE */
4645   {
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4649   },
4650
4651   /* PREFIX_0F3ACF */
4652   {
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4656   },
4657
4658   /* PREFIX_0F3ADF */
4659   {
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4663   },
4664
4665   /* PREFIX_VEX_0F10 */
4666   {
4667     { "vmovups",        { XM, EXx }, 0 },
4668     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4669     { "vmovupd",        { XM, EXx }, 0 },
4670     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4671   },
4672
4673   /* PREFIX_VEX_0F11 */
4674   {
4675     { "vmovups",        { EXxS, XM }, 0 },
4676     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4677     { "vmovupd",        { EXxS, XM }, 0 },
4678     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4679   },
4680
4681   /* PREFIX_VEX_0F12 */
4682   {
4683     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4684     { "vmovsldup",      { XM, EXx }, 0 },
4685     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4686     { "vmovddup",       { XM, EXymmq }, 0 },
4687   },
4688
4689   /* PREFIX_VEX_0F16 */
4690   {
4691     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4692     { "vmovshdup",      { XM, EXx }, 0 },
4693     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F2A */
4697   {
4698     { Bad_Opcode },
4699     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4702   },
4703
4704   /* PREFIX_VEX_0F2C */
4705   {
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4710   },
4711
4712   /* PREFIX_VEX_0F2D */
4713   {
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4716     { Bad_Opcode },
4717     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4718   },
4719
4720   /* PREFIX_VEX_0F2E */
4721   {
4722     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4723     { Bad_Opcode },
4724     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4725   },
4726
4727   /* PREFIX_VEX_0F2F */
4728   {
4729     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4730     { Bad_Opcode },
4731     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4732   },
4733
4734   /* PREFIX_VEX_0F41 */
4735   {
4736     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4737     { Bad_Opcode },
4738     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4739   },
4740
4741   /* PREFIX_VEX_0F42 */
4742   {
4743     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4744     { Bad_Opcode },
4745     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4746   },
4747
4748   /* PREFIX_VEX_0F44 */
4749   {
4750     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4751     { Bad_Opcode },
4752     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4753   },
4754
4755   /* PREFIX_VEX_0F45 */
4756   {
4757     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4758     { Bad_Opcode },
4759     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4760   },
4761
4762   /* PREFIX_VEX_0F46 */
4763   {
4764     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4765     { Bad_Opcode },
4766     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4767   },
4768
4769   /* PREFIX_VEX_0F47 */
4770   {
4771     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4772     { Bad_Opcode },
4773     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4774   },
4775
4776   /* PREFIX_VEX_0F4A */
4777   {
4778     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4779     { Bad_Opcode },
4780     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4781   },
4782
4783   /* PREFIX_VEX_0F4B */
4784   {
4785     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4786     { Bad_Opcode },
4787     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4788   },
4789
4790   /* PREFIX_VEX_0F51 */
4791   {
4792     { "vsqrtps",        { XM, EXx }, 0 },
4793     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4794     { "vsqrtpd",        { XM, EXx }, 0 },
4795     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4796   },
4797
4798   /* PREFIX_VEX_0F52 */
4799   {
4800     { "vrsqrtps",       { XM, EXx }, 0 },
4801     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F53 */
4805   {
4806     { "vrcpps",         { XM, EXx }, 0 },
4807     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F58 */
4811   {
4812     { "vaddps",         { XM, Vex, EXx }, 0 },
4813     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814     { "vaddpd",         { XM, Vex, EXx }, 0 },
4815     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F59 */
4819   {
4820     { "vmulps",         { XM, Vex, EXx }, 0 },
4821     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4822     { "vmulpd",         { XM, Vex, EXx }, 0 },
4823     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4824   },
4825
4826   /* PREFIX_VEX_0F5A */
4827   {
4828     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4829     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4830     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4831     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4832   },
4833
4834   /* PREFIX_VEX_0F5B */
4835   {
4836     { "vcvtdq2ps",      { XM, EXx }, 0 },
4837     { "vcvttps2dq",     { XM, EXx }, 0 },
4838     { "vcvtps2dq",      { XM, EXx }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F5C */
4842   {
4843     { "vsubps",         { XM, Vex, EXx }, 0 },
4844     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4845     { "vsubpd",         { XM, Vex, EXx }, 0 },
4846     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F5D */
4850   {
4851     { "vminps",         { XM, Vex, EXx }, 0 },
4852     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4853     { "vminpd",         { XM, Vex, EXx }, 0 },
4854     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F5E */
4858   {
4859     { "vdivps",         { XM, Vex, EXx }, 0 },
4860     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4861     { "vdivpd",         { XM, Vex, EXx }, 0 },
4862     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F5F */
4866   {
4867     { "vmaxps",         { XM, Vex, EXx }, 0 },
4868     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4869     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4870     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4871   },
4872
4873   /* PREFIX_VEX_0F60 */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4878   },
4879
4880   /* PREFIX_VEX_0F61 */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4885   },
4886
4887   /* PREFIX_VEX_0F62 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4892   },
4893
4894   /* PREFIX_VEX_0F63 */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4899   },
4900
4901   /* PREFIX_VEX_0F64 */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4906   },
4907
4908   /* PREFIX_VEX_0F65 */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4913   },
4914
4915   /* PREFIX_VEX_0F66 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4920   },
4921
4922   /* PREFIX_VEX_0F67 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4927   },
4928
4929   /* PREFIX_VEX_0F68 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4934   },
4935
4936   /* PREFIX_VEX_0F69 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4941   },
4942
4943   /* PREFIX_VEX_0F6A */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4948   },
4949
4950   /* PREFIX_VEX_0F6B */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4955   },
4956
4957   /* PREFIX_VEX_0F6C */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4962   },
4963
4964   /* PREFIX_VEX_0F6D */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4969   },
4970
4971   /* PREFIX_VEX_0F6E */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4976   },
4977
4978   /* PREFIX_VEX_0F6F */
4979   {
4980     { Bad_Opcode },
4981     { "vmovdqu",        { XM, EXx }, 0 },
4982     { "vmovdqa",        { XM, EXx }, 0 },
4983   },
4984
4985   /* PREFIX_VEX_0F70 */
4986   {
4987     { Bad_Opcode },
4988     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4989     { "vpshufd",        { XM, EXx, Ib }, 0 },
4990     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4991   },
4992
4993   /* PREFIX_VEX_0F71_REG_2 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4998   },
4999
5000   /* PREFIX_VEX_0F71_REG_4 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { "vpsraw",         { Vex, XS, Ib }, 0 },
5005   },
5006
5007   /* PREFIX_VEX_0F71_REG_6 */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { "vpsllw",         { Vex, XS, Ib }, 0 },
5012   },
5013
5014   /* PREFIX_VEX_0F72_REG_2 */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { "vpsrld",         { Vex, XS, Ib }, 0 },
5019   },
5020
5021   /* PREFIX_VEX_0F72_REG_4 */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { "vpsrad",         { Vex, XS, Ib }, 0 },
5026   },
5027
5028   /* PREFIX_VEX_0F72_REG_6 */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { "vpslld",         { Vex, XS, Ib }, 0 },
5033   },
5034
5035   /* PREFIX_VEX_0F73_REG_2 */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5040   },
5041
5042   /* PREFIX_VEX_0F73_REG_3 */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5047   },
5048
5049   /* PREFIX_VEX_0F73_REG_6 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vpsllq",         { Vex, XS, Ib }, 0 },
5054   },
5055
5056   /* PREFIX_VEX_0F73_REG_7 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vpslldq",        { Vex, XS, Ib }, 0 },
5061   },
5062
5063   /* PREFIX_VEX_0F74 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5068   },
5069
5070   /* PREFIX_VEX_0F75 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5075   },
5076
5077   /* PREFIX_VEX_0F76 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5082   },
5083
5084   /* PREFIX_VEX_0F77 */
5085   {
5086     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5087   },
5088
5089   /* PREFIX_VEX_0F7C */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5094     { "vhaddps",        { XM, Vex, EXx }, 0 },
5095   },
5096
5097   /* PREFIX_VEX_0F7D */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5102     { "vhsubps",        { XM, Vex, EXx }, 0 },
5103   },
5104
5105   /* PREFIX_VEX_0F7E */
5106   {
5107     { Bad_Opcode },
5108     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5109     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5110   },
5111
5112   /* PREFIX_VEX_0F7F */
5113   {
5114     { Bad_Opcode },
5115     { "vmovdqu",        { EXxS, XM }, 0 },
5116     { "vmovdqa",        { EXxS, XM }, 0 },
5117   },
5118
5119   /* PREFIX_VEX_0F90 */
5120   {
5121     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F91 */
5127   {
5128     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0F92 */
5134   {
5135     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5138     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5139   },
5140
5141   /* PREFIX_VEX_0F93 */
5142   {
5143     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5146     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5147   },
5148
5149   /* PREFIX_VEX_0F98 */
5150   {
5151     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5152     { Bad_Opcode },
5153     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0F99 */
5157   {
5158     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5159     { Bad_Opcode },
5160     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0FC2 */
5164   {
5165     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5166     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5167     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5168     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5169   },
5170
5171   /* PREFIX_VEX_0FC4 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0FC5 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0FD0 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5190     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5191   },
5192
5193   /* PREFIX_VEX_0FD1 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5198   },
5199
5200   /* PREFIX_VEX_0FD2 */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5205   },
5206
5207   /* PREFIX_VEX_0FD3 */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5212   },
5213
5214   /* PREFIX_VEX_0FD4 */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { "vpaddq",         { XM, Vex, EXx }, 0 },
5219   },
5220
5221   /* PREFIX_VEX_0FD5 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { "vpmullw",        { XM, Vex, EXx }, 0 },
5226   },
5227
5228   /* PREFIX_VEX_0FD6 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5233   },
5234
5235   /* PREFIX_VEX_0FD7 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5240   },
5241
5242   /* PREFIX_VEX_0FD8 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5247   },
5248
5249   /* PREFIX_VEX_0FD9 */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5254   },
5255
5256   /* PREFIX_VEX_0FDA */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { "vpminub",        { XM, Vex, EXx }, 0 },
5261   },
5262
5263   /* PREFIX_VEX_0FDB */
5264   {
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { "vpand",          { XM, Vex, EXx }, 0 },
5268   },
5269
5270   /* PREFIX_VEX_0FDC */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5275   },
5276
5277   /* PREFIX_VEX_0FDD */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5282   },
5283
5284   /* PREFIX_VEX_0FDE */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5289   },
5290
5291   /* PREFIX_VEX_0FDF */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { "vpandn",         { XM, Vex, EXx }, 0 },
5296   },
5297
5298   /* PREFIX_VEX_0FE0 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { "vpavgb",         { XM, Vex, EXx }, 0 },
5303   },
5304
5305   /* PREFIX_VEX_0FE1 */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5310   },
5311
5312   /* PREFIX_VEX_0FE2 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5317   },
5318
5319   /* PREFIX_VEX_0FE3 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { "vpavgw",         { XM, Vex, EXx }, 0 },
5324   },
5325
5326   /* PREFIX_VEX_0FE4 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5331   },
5332
5333   /* PREFIX_VEX_0FE5 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FE6 */
5341   {
5342     { Bad_Opcode },
5343     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5344     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5345     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5346   },
5347
5348   /* PREFIX_VEX_0FE7 */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5353   },
5354
5355   /* PREFIX_VEX_0FE8 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5360   },
5361
5362   /* PREFIX_VEX_0FE9 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5367   },
5368
5369   /* PREFIX_VEX_0FEA */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { "vpminsw",        { XM, Vex, EXx }, 0 },
5374   },
5375
5376   /* PREFIX_VEX_0FEB */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { "vpor",           { XM, Vex, EXx }, 0 },
5381   },
5382
5383   /* PREFIX_VEX_0FEC */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5388   },
5389
5390   /* PREFIX_VEX_0FED */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5395   },
5396
5397   /* PREFIX_VEX_0FEE */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5402   },
5403
5404   /* PREFIX_VEX_0FEF */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { "vpxor",          { XM, Vex, EXx }, 0 },
5409   },
5410
5411   /* PREFIX_VEX_0FF0 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5417   },
5418
5419   /* PREFIX_VEX_0FF1 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5424   },
5425
5426   /* PREFIX_VEX_0FF2 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5431   },
5432
5433   /* PREFIX_VEX_0FF3 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5438   },
5439
5440   /* PREFIX_VEX_0FF4 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5445   },
5446
5447   /* PREFIX_VEX_0FF5 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5452   },
5453
5454   /* PREFIX_VEX_0FF6 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5459   },
5460
5461   /* PREFIX_VEX_0FF7 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0FF8 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { "vpsubb",         { XM, Vex, EXx }, 0 },
5473   },
5474
5475   /* PREFIX_VEX_0FF9 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { "vpsubw",         { XM, Vex, EXx }, 0 },
5480   },
5481
5482   /* PREFIX_VEX_0FFA */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { "vpsubd",         { XM, Vex, EXx }, 0 },
5487   },
5488
5489   /* PREFIX_VEX_0FFB */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { "vpsubq",         { XM, Vex, EXx }, 0 },
5494   },
5495
5496   /* PREFIX_VEX_0FFC */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { "vpaddb",         { XM, Vex, EXx }, 0 },
5501   },
5502
5503   /* PREFIX_VEX_0FFD */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { "vpaddw",         { XM, Vex, EXx }, 0 },
5508   },
5509
5510   /* PREFIX_VEX_0FFE */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { "vpaddd",         { XM, Vex, EXx }, 0 },
5515   },
5516
5517   /* PREFIX_VEX_0F3800 */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { "vpshufb",        { XM, Vex, EXx }, 0 },
5522   },
5523
5524   /* PREFIX_VEX_0F3801 */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { "vphaddw",        { XM, Vex, EXx }, 0 },
5529   },
5530
5531   /* PREFIX_VEX_0F3802 */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { "vphaddd",        { XM, Vex, EXx }, 0 },
5536   },
5537
5538   /* PREFIX_VEX_0F3803 */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5543   },
5544
5545   /* PREFIX_VEX_0F3804 */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5550   },
5551
5552   /* PREFIX_VEX_0F3805 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vphsubw",        { XM, Vex, EXx }, 0 },
5557   },
5558
5559   /* PREFIX_VEX_0F3806 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { "vphsubd",        { XM, Vex, EXx }, 0 },
5564   },
5565
5566   /* PREFIX_VEX_0F3807 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5571   },
5572
5573   /* PREFIX_VEX_0F3808 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { "vpsignb",        { XM, Vex, EXx }, 0 },
5578   },
5579
5580   /* PREFIX_VEX_0F3809 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { "vpsignw",        { XM, Vex, EXx }, 0 },
5585   },
5586
5587   /* PREFIX_VEX_0F380A */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { "vpsignd",        { XM, Vex, EXx }, 0 },
5592   },
5593
5594   /* PREFIX_VEX_0F380B */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5599   },
5600
5601   /* PREFIX_VEX_0F380C */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0F380D */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0F380E */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0F380F */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0F3813 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5634   },
5635
5636   /* PREFIX_VEX_0F3816 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F3817 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { "vptest",         { XM, EXx }, 0 },
5648   },
5649
5650   /* PREFIX_VEX_0F3818 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0F3819 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0F381A */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5669   },
5670
5671   /* PREFIX_VEX_0F381C */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { "vpabsb",         { XM, EXx }, 0 },
5676   },
5677
5678   /* PREFIX_VEX_0F381D */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { "vpabsw",         { XM, EXx }, 0 },
5683   },
5684
5685   /* PREFIX_VEX_0F381E */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { "vpabsd",         { XM, EXx }, 0 },
5690   },
5691
5692   /* PREFIX_VEX_0F3820 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5697   },
5698
5699   /* PREFIX_VEX_0F3821 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5704   },
5705
5706   /* PREFIX_VEX_0F3822 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5711   },
5712
5713   /* PREFIX_VEX_0F3823 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5718   },
5719
5720   /* PREFIX_VEX_0F3824 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5725   },
5726
5727   /* PREFIX_VEX_0F3825 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5732   },
5733
5734   /* PREFIX_VEX_0F3828 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5739   },
5740
5741   /* PREFIX_VEX_0F3829 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5746   },
5747
5748   /* PREFIX_VEX_0F382A */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F382B */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5760   },
5761
5762   /* PREFIX_VEX_0F382C */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F382D */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F382E */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F382F */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3830 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5795   },
5796
5797   /* PREFIX_VEX_0F3831 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5802   },
5803
5804   /* PREFIX_VEX_0F3832 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5809   },
5810
5811   /* PREFIX_VEX_0F3833 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5816   },
5817
5818   /* PREFIX_VEX_0F3834 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5823   },
5824
5825   /* PREFIX_VEX_0F3835 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5830   },
5831
5832   /* PREFIX_VEX_0F3836 */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F3837 */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5844   },
5845
5846   /* PREFIX_VEX_0F3838 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { "vpminsb",        { XM, Vex, EXx }, 0 },
5851   },
5852
5853   /* PREFIX_VEX_0F3839 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vpminsd",        { XM, Vex, EXx }, 0 },
5858   },
5859
5860   /* PREFIX_VEX_0F383A */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { "vpminuw",        { XM, Vex, EXx }, 0 },
5865   },
5866
5867   /* PREFIX_VEX_0F383B */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { "vpminud",        { XM, Vex, EXx }, 0 },
5872   },
5873
5874   /* PREFIX_VEX_0F383C */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5879   },
5880
5881   /* PREFIX_VEX_0F383D */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5886   },
5887
5888   /* PREFIX_VEX_0F383E */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5893   },
5894
5895   /* PREFIX_VEX_0F383F */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5900   },
5901
5902   /* PREFIX_VEX_0F3840 */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { "vpmulld",        { XM, Vex, EXx }, 0 },
5907   },
5908
5909   /* PREFIX_VEX_0F3841 */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F3845 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5921   },
5922
5923   /* PREFIX_VEX_0F3846 */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F3847 */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5935   },
5936
5937   /* PREFIX_VEX_0F3858 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F3859 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F385A */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3878 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3879 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F388C */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F388E */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F3890 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5991   },
5992
5993   /* PREFIX_VEX_0F3891 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5998   },
5999
6000   /* PREFIX_VEX_0F3892 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6005   },
6006
6007   /* PREFIX_VEX_0F3893 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6012   },
6013
6014   /* PREFIX_VEX_0F3896 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6019   },
6020
6021   /* PREFIX_VEX_0F3897 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6026   },
6027
6028   /* PREFIX_VEX_0F3898 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6033   },
6034
6035   /* PREFIX_VEX_0F3899 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6040   },
6041
6042   /* PREFIX_VEX_0F389A */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6047   },
6048
6049   /* PREFIX_VEX_0F389B */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F389C */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6061   },
6062
6063   /* PREFIX_VEX_0F389D */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F389E */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F389F */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F38A6 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6089     { Bad_Opcode },
6090   },
6091
6092   /* PREFIX_VEX_0F38A7 */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6097   },
6098
6099   /* PREFIX_VEX_0F38A8 */
6100   {
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6104   },
6105
6106   /* PREFIX_VEX_0F38A9 */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6111   },
6112
6113   /* PREFIX_VEX_0F38AA */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38AB */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38AC */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6132   },
6133
6134   /* PREFIX_VEX_0F38AD */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F38AE */
6142   {
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6146   },
6147
6148   /* PREFIX_VEX_0F38AF */
6149   {
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6153   },
6154
6155   /* PREFIX_VEX_0F38B6 */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6160   },
6161
6162   /* PREFIX_VEX_0F38B7 */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6167   },
6168
6169   /* PREFIX_VEX_0F38B8 */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6174   },
6175
6176   /* PREFIX_VEX_0F38B9 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6181   },
6182
6183   /* PREFIX_VEX_0F38BA */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6188   },
6189
6190   /* PREFIX_VEX_0F38BB */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6195   },
6196
6197   /* PREFIX_VEX_0F38BC */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6202   },
6203
6204   /* PREFIX_VEX_0F38BD */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6209   },
6210
6211   /* PREFIX_VEX_0F38BE */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F38BF */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F38CF */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6230   },
6231
6232   /* PREFIX_VEX_0F38DB */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6237   },
6238
6239   /* PREFIX_VEX_0F38DC */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { "vaesenc",        { XM, Vex, EXx }, 0 },
6244   },
6245
6246   /* PREFIX_VEX_0F38DD */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F38DE */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vaesdec",        { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38DF */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38F2 */
6268   {
6269     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6270   },
6271
6272   /* PREFIX_VEX_0F38F3_REG_1 */
6273   {
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6275   },
6276
6277   /* PREFIX_VEX_0F38F3_REG_2 */
6278   {
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6280   },
6281
6282   /* PREFIX_VEX_0F38F3_REG_3 */
6283   {
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F5 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6293   },
6294
6295   /* PREFIX_VEX_0F38F6 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6301   },
6302
6303   /* PREFIX_VEX_0F38F7 */
6304   {
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6309   },
6310
6311   /* PREFIX_VEX_0F3A00 */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6316   },
6317
6318   /* PREFIX_VEX_0F3A01 */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A02 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A04 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A05 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A06 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A08 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { "vroundps",       { XM, EXx, Ib }, 0 },
6358   },
6359
6360   /* PREFIX_VEX_0F3A09 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { "vroundpd",       { XM, EXx, Ib }, 0 },
6365   },
6366
6367   /* PREFIX_VEX_0F3A0A */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F3A0B */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6379   },
6380
6381   /* PREFIX_VEX_0F3A0C */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6386   },
6387
6388   /* PREFIX_VEX_0F3A0D */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6393   },
6394
6395   /* PREFIX_VEX_0F3A0E */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F3A0F */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F3A14 */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6414   },
6415
6416   /* PREFIX_VEX_0F3A15 */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6421   },
6422
6423   /* PREFIX_VEX_0F3A16 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A17 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A18 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A19 */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A1D */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6456   },
6457
6458   /* PREFIX_VEX_0F3A20 */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A21 */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A22 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A30 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A31 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A32 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A33 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A38 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A39 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A40 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6526   },
6527
6528   /* PREFIX_VEX_0F3A41 */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A42 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6540   },
6541
6542   /* PREFIX_VEX_0F3A44 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6547   },
6548
6549   /* PREFIX_VEX_0F3A46 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A48 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A49 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A4A */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A4B */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A4C */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A5C */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6596   },
6597
6598   /* PREFIX_VEX_0F3A5D */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6603   },
6604
6605   /* PREFIX_VEX_0F3A5E */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6610   },
6611
6612   /* PREFIX_VEX_0F3A5F */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6617   },
6618
6619   /* PREFIX_VEX_0F3A60 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6624     { Bad_Opcode },
6625   },
6626
6627   /* PREFIX_VEX_0F3A61 */
6628   {
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6632   },
6633
6634   /* PREFIX_VEX_0F3A62 */
6635   {
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6639   },
6640
6641   /* PREFIX_VEX_0F3A63 */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3A68 */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6653   },
6654
6655   /* PREFIX_VEX_0F3A69 */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6660   },
6661
6662   /* PREFIX_VEX_0F3A6A */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6667   },
6668
6669   /* PREFIX_VEX_0F3A6B */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6674   },
6675
6676   /* PREFIX_VEX_0F3A6C */
6677   {
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6681   },
6682
6683   /* PREFIX_VEX_0F3A6D */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6688   },
6689
6690   /* PREFIX_VEX_0F3A6E */
6691   {
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6695   },
6696
6697   /* PREFIX_VEX_0F3A6F */
6698   {
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6702   },
6703
6704   /* PREFIX_VEX_0F3A78 */
6705   {
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6709   },
6710
6711   /* PREFIX_VEX_0F3A79 */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6716   },
6717
6718   /* PREFIX_VEX_0F3A7A */
6719   {
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6723   },
6724
6725   /* PREFIX_VEX_0F3A7B */
6726   {
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6730   },
6731
6732   /* PREFIX_VEX_0F3A7C */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6737     { Bad_Opcode },
6738   },
6739
6740   /* PREFIX_VEX_0F3A7D */
6741   {
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6745   },
6746
6747   /* PREFIX_VEX_0F3A7E */
6748   {
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6752   },
6753
6754   /* PREFIX_VEX_0F3A7F */
6755   {
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6759   },
6760
6761   /* PREFIX_VEX_0F3ACE */
6762   {
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6766   },
6767
6768   /* PREFIX_VEX_0F3ACF */
6769   {
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6773   },
6774
6775   /* PREFIX_VEX_0F3ADF */
6776   {
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6780   },
6781
6782   /* PREFIX_VEX_0F3AF0 */
6783   {
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6788   },
6789
6790 #include "i386-dis-evex-prefix.h"
6791 };
6792
6793 static const struct dis386 x86_64_table[][2] = {
6794   /* X86_64_06 */
6795   {
6796     { "pushP", { es }, 0 },
6797   },
6798
6799   /* X86_64_07 */
6800   {
6801     { "popP", { es }, 0 },
6802   },
6803
6804   /* X86_64_0D */
6805   {
6806     { "pushP", { cs }, 0 },
6807   },
6808
6809   /* X86_64_16 */
6810   {
6811     { "pushP", { ss }, 0 },
6812   },
6813
6814   /* X86_64_17 */
6815   {
6816     { "popP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_1E */
6820   {
6821     { "pushP", { ds }, 0 },
6822   },
6823
6824   /* X86_64_1F */
6825   {
6826     { "popP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_27 */
6830   {
6831     { "daa", { XX }, 0 },
6832   },
6833
6834   /* X86_64_2F */
6835   {
6836     { "das", { XX }, 0 },
6837   },
6838
6839   /* X86_64_37 */
6840   {
6841     { "aaa", { XX }, 0 },
6842   },
6843
6844   /* X86_64_3F */
6845   {
6846     { "aas", { XX }, 0 },
6847   },
6848
6849   /* X86_64_60 */
6850   {
6851     { "pushaP", { XX }, 0 },
6852   },
6853
6854   /* X86_64_61 */
6855   {
6856     { "popaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_62 */
6860   {
6861     { MOD_TABLE (MOD_62_32BIT) },
6862     { EVEX_TABLE (EVEX_0F) },
6863   },
6864
6865   /* X86_64_63 */
6866   {
6867     { "arpl", { Ew, Gw }, 0 },
6868     { "movs{lq|xd}", { Gv, Ed }, 0 },
6869   },
6870
6871   /* X86_64_6D */
6872   {
6873     { "ins{R|}", { Yzr, indirDX }, 0 },
6874     { "ins{G|}", { Yzr, indirDX }, 0 },
6875   },
6876
6877   /* X86_64_6F */
6878   {
6879     { "outs{R|}", { indirDXr, Xz }, 0 },
6880     { "outs{G|}", { indirDXr, Xz }, 0 },
6881   },
6882
6883   /* X86_64_82 */
6884   {
6885     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6886     { REG_TABLE (REG_80) },
6887   },
6888
6889   /* X86_64_9A */
6890   {
6891     { "Jcall{T|}", { Ap }, 0 },
6892   },
6893
6894   /* X86_64_C4 */
6895   {
6896     { MOD_TABLE (MOD_C4_32BIT) },
6897     { VEX_C4_TABLE (VEX_0F) },
6898   },
6899
6900   /* X86_64_C5 */
6901   {
6902     { MOD_TABLE (MOD_C5_32BIT) },
6903     { VEX_C5_TABLE (VEX_0F) },
6904   },
6905
6906   /* X86_64_CE */
6907   {
6908     { "into", { XX }, 0 },
6909   },
6910
6911   /* X86_64_D4 */
6912   {
6913     { "aam", { Ib }, 0 },
6914   },
6915
6916   /* X86_64_D5 */
6917   {
6918     { "aad", { Ib }, 0 },
6919   },
6920
6921   /* X86_64_E8 */
6922   {
6923     { "callP",          { Jv, BND }, 0 },
6924     { "call@",          { Jv, BND }, 0 }
6925   },
6926
6927   /* X86_64_E9 */
6928   {
6929     { "jmpP",           { Jv, BND }, 0 },
6930     { "jmp@",           { Jv, BND }, 0 }
6931   },
6932
6933   /* X86_64_EA */
6934   {
6935     { "Jjmp{T|}", { Ap }, 0 },
6936   },
6937
6938   /* X86_64_0F01_REG_0 */
6939   {
6940     { "sgdt{Q|IQ}", { M }, 0 },
6941     { "sgdt", { M }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_1 */
6945   {
6946     { "sidt{Q|IQ}", { M }, 0 },
6947     { "sidt", { M }, 0 },
6948   },
6949
6950   /* X86_64_0F01_REG_2 */
6951   {
6952     { "lgdt{Q|Q}", { M }, 0 },
6953     { "lgdt", { M }, 0 },
6954   },
6955
6956   /* X86_64_0F01_REG_3 */
6957   {
6958     { "lidt{Q|Q}", { M }, 0 },
6959     { "lidt", { M }, 0 },
6960   },
6961 };
6962
6963 static const struct dis386 three_byte_table[][256] = {
6964
6965   /* THREE_BYTE_0F38 */
6966   {
6967     /* 00 */
6968     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6969     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6970     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6971     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6972     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6973     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6974     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6975     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6976     /* 08 */
6977     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6978     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6979     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6980     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 10 */
6986     { PREFIX_TABLE (PREFIX_0F3810) },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { PREFIX_TABLE (PREFIX_0F3814) },
6991     { PREFIX_TABLE (PREFIX_0F3815) },
6992     { Bad_Opcode },
6993     { PREFIX_TABLE (PREFIX_0F3817) },
6994     /* 18 */
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7000     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7001     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7002     { Bad_Opcode },
7003     /* 20 */
7004     { PREFIX_TABLE (PREFIX_0F3820) },
7005     { PREFIX_TABLE (PREFIX_0F3821) },
7006     { PREFIX_TABLE (PREFIX_0F3822) },
7007     { PREFIX_TABLE (PREFIX_0F3823) },
7008     { PREFIX_TABLE (PREFIX_0F3824) },
7009     { PREFIX_TABLE (PREFIX_0F3825) },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 28 */
7013     { PREFIX_TABLE (PREFIX_0F3828) },
7014     { PREFIX_TABLE (PREFIX_0F3829) },
7015     { PREFIX_TABLE (PREFIX_0F382A) },
7016     { PREFIX_TABLE (PREFIX_0F382B) },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 30 */
7022     { PREFIX_TABLE (PREFIX_0F3830) },
7023     { PREFIX_TABLE (PREFIX_0F3831) },
7024     { PREFIX_TABLE (PREFIX_0F3832) },
7025     { PREFIX_TABLE (PREFIX_0F3833) },
7026     { PREFIX_TABLE (PREFIX_0F3834) },
7027     { PREFIX_TABLE (PREFIX_0F3835) },
7028     { Bad_Opcode },
7029     { PREFIX_TABLE (PREFIX_0F3837) },
7030     /* 38 */
7031     { PREFIX_TABLE (PREFIX_0F3838) },
7032     { PREFIX_TABLE (PREFIX_0F3839) },
7033     { PREFIX_TABLE (PREFIX_0F383A) },
7034     { PREFIX_TABLE (PREFIX_0F383B) },
7035     { PREFIX_TABLE (PREFIX_0F383C) },
7036     { PREFIX_TABLE (PREFIX_0F383D) },
7037     { PREFIX_TABLE (PREFIX_0F383E) },
7038     { PREFIX_TABLE (PREFIX_0F383F) },
7039     /* 40 */
7040     { PREFIX_TABLE (PREFIX_0F3840) },
7041     { PREFIX_TABLE (PREFIX_0F3841) },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 48 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 50 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 58 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 60 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 68 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 70 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 78 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 80 */
7112     { PREFIX_TABLE (PREFIX_0F3880) },
7113     { PREFIX_TABLE (PREFIX_0F3881) },
7114     { PREFIX_TABLE (PREFIX_0F3882) },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* 88 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* 90 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* 98 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* a0 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* a8 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* b0 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* b8 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* c0 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* c8 */
7193     { PREFIX_TABLE (PREFIX_0F38C8) },
7194     { PREFIX_TABLE (PREFIX_0F38C9) },
7195     { PREFIX_TABLE (PREFIX_0F38CA) },
7196     { PREFIX_TABLE (PREFIX_0F38CB) },
7197     { PREFIX_TABLE (PREFIX_0F38CC) },
7198     { PREFIX_TABLE (PREFIX_0F38CD) },
7199     { Bad_Opcode },
7200     { PREFIX_TABLE (PREFIX_0F38CF) },
7201     /* d0 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* d8 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { PREFIX_TABLE (PREFIX_0F38DB) },
7215     { PREFIX_TABLE (PREFIX_0F38DC) },
7216     { PREFIX_TABLE (PREFIX_0F38DD) },
7217     { PREFIX_TABLE (PREFIX_0F38DE) },
7218     { PREFIX_TABLE (PREFIX_0F38DF) },
7219     /* e0 */
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     /* e8 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* f0 */
7238     { PREFIX_TABLE (PREFIX_0F38F0) },
7239     { PREFIX_TABLE (PREFIX_0F38F1) },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { PREFIX_TABLE (PREFIX_0F38F5) },
7244     { PREFIX_TABLE (PREFIX_0F38F6) },
7245     { Bad_Opcode },
7246     /* f8 */
7247     { PREFIX_TABLE (PREFIX_0F38F8) },
7248     { PREFIX_TABLE (PREFIX_0F38F9) },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255   },
7256   /* THREE_BYTE_0F3A */
7257   {
7258     /* 00 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* 08 */
7268     { PREFIX_TABLE (PREFIX_0F3A08) },
7269     { PREFIX_TABLE (PREFIX_0F3A09) },
7270     { PREFIX_TABLE (PREFIX_0F3A0A) },
7271     { PREFIX_TABLE (PREFIX_0F3A0B) },
7272     { PREFIX_TABLE (PREFIX_0F3A0C) },
7273     { PREFIX_TABLE (PREFIX_0F3A0D) },
7274     { PREFIX_TABLE (PREFIX_0F3A0E) },
7275     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7276     /* 10 */
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { PREFIX_TABLE (PREFIX_0F3A14) },
7282     { PREFIX_TABLE (PREFIX_0F3A15) },
7283     { PREFIX_TABLE (PREFIX_0F3A16) },
7284     { PREFIX_TABLE (PREFIX_0F3A17) },
7285     /* 18 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 20 */
7295     { PREFIX_TABLE (PREFIX_0F3A20) },
7296     { PREFIX_TABLE (PREFIX_0F3A21) },
7297     { PREFIX_TABLE (PREFIX_0F3A22) },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* 28 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* 30 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 38 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 40 */
7331     { PREFIX_TABLE (PREFIX_0F3A40) },
7332     { PREFIX_TABLE (PREFIX_0F3A41) },
7333     { PREFIX_TABLE (PREFIX_0F3A42) },
7334     { Bad_Opcode },
7335     { PREFIX_TABLE (PREFIX_0F3A44) },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 48 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* 50 */
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* 58 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* 60 */
7367     { PREFIX_TABLE (PREFIX_0F3A60) },
7368     { PREFIX_TABLE (PREFIX_0F3A61) },
7369     { PREFIX_TABLE (PREFIX_0F3A62) },
7370     { PREFIX_TABLE (PREFIX_0F3A63) },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* 68 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* 70 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* 78 */
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* 80 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* 88 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     /* 90 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* 98 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* a0 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* a8 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* b0 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* b8 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* c0 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* c8 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { PREFIX_TABLE (PREFIX_0F3ACC) },
7489     { Bad_Opcode },
7490     { PREFIX_TABLE (PREFIX_0F3ACE) },
7491     { PREFIX_TABLE (PREFIX_0F3ACF) },
7492     /* d0 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* d8 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { PREFIX_TABLE (PREFIX_0F3ADF) },
7510     /* e0 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* e8 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* f0 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* f8 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546   },
7547 };
7548
7549 static const struct dis386 xop_table[][256] = {
7550   /* XOP_08 */
7551   {
7552     /* 00 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* 08 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     /* 10 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* 18 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 20 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 28 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 30 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 38 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 40 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 48 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* 50 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* 58 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* 60 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* 68 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     /* 70 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     /* 78 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     /* 80 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7703     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     /* 88 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     /* 90 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7723     /* 98 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7732     /* a0 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { Bad_Opcode },
7741     /* a8 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* b0 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7758     { Bad_Opcode },
7759     /* b8 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     /* c0 */
7769     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7770     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7771     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7772     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* c8 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7783     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7784     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7785     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7786     /* d0 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* d8 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     /* e0 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     /* e8 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7822     /* f0 */
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     /* f8 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840   },
7841   /* XOP_09 */
7842   {
7843     /* 00 */
7844     { Bad_Opcode },
7845     { REG_TABLE (REG_XOP_TBM_01) },
7846     { REG_TABLE (REG_XOP_TBM_02) },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 08 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 10 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { REG_TABLE (REG_XOP_LWPCB) },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 18 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 20 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 28 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 30 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 38 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 40 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 48 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 50 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 58 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 60 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 68 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 70 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 78 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 80 */
7988     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7989     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7990     { "vfrczss",        { XM, EXd }, 0 },
7991     { "vfrczsd",        { XM, EXq }, 0 },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* 88 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* 90 */
8006     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8007     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8008     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8009     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8010     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     /* 98 */
8015     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* a0 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* a8 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* b0 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* b8 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* c0 */
8060     { Bad_Opcode },
8061     { "vphaddbw",       { XM, EXxmm }, 0 },
8062     { "vphaddbd",       { XM, EXxmm }, 0 },
8063     { "vphaddbq",       { XM, EXxmm }, 0 },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { "vphaddwd",       { XM, EXxmm }, 0 },
8067     { "vphaddwq",       { XM, EXxmm }, 0 },
8068     /* c8 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { "vphadddq",       { XM, EXxmm }, 0 },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* d0 */
8078     { Bad_Opcode },
8079     { "vphaddubw",      { XM, EXxmm }, 0 },
8080     { "vphaddubd",      { XM, EXxmm }, 0 },
8081     { "vphaddubq",      { XM, EXxmm }, 0 },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { "vphadduwd",      { XM, EXxmm }, 0 },
8085     { "vphadduwq",      { XM, EXxmm }, 0 },
8086     /* d8 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { "vphaddudq",      { XM, EXxmm }, 0 },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* e0 */
8096     { Bad_Opcode },
8097     { "vphsubbw",       { XM, EXxmm }, 0 },
8098     { "vphsubwd",       { XM, EXxmm }, 0 },
8099     { "vphsubdq",       { XM, EXxmm }, 0 },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* e8 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* f0 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* f8 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131   },
8132   /* XOP_0A */
8133   {
8134     /* 00 */
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 08 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 10 */
8153     { "bextr",  { Gv, Ev, Iq }, 0 },
8154     { Bad_Opcode },
8155     { REG_TABLE (REG_XOP_LWP) },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 18 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 20 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 28 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 30 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 38 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 40 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 48 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 50 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 58 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 60 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 68 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 70 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 78 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 80 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 88 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* 90 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* 98 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* a0 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* a8 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* b0 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* b8 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* c0 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* c8 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* d0 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* d8 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* e0 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* e8 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* f0 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* f8 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422   },
8423 };
8424
8425 static const struct dis386 vex_table[][256] = {
8426   /* VEX_0F */
8427   {
8428     /* 00 */
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     /* 08 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     /* 10 */
8447     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8450     { MOD_TABLE (MOD_VEX_0F13) },
8451     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8452     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8453     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8454     { MOD_TABLE (MOD_VEX_0F17) },
8455     /* 18 */
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     /* 20 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     /* 28 */
8474     { "vmovapX",        { XM, EXx }, 0 },
8475     { "vmovapX",        { EXxS, XM }, 0 },
8476     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8477     { MOD_TABLE (MOD_VEX_0F2B) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8482     /* 30 */
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     /* 38 */
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     /* 40 */
8501     { Bad_Opcode },
8502     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8504     { Bad_Opcode },
8505     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8509     /* 48 */
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     /* 50 */
8519     { MOD_TABLE (MOD_VEX_0F50) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8523     { "vandpX",         { XM, Vex, EXx }, 0 },
8524     { "vandnpX",        { XM, Vex, EXx }, 0 },
8525     { "vorpX",          { XM, Vex, EXx }, 0 },
8526     { "vxorpX",         { XM, Vex, EXx }, 0 },
8527     /* 58 */
8528     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8536     /* 60 */
8537     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8545     /* 68 */
8546     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8554     /* 70 */
8555     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8556     { REG_TABLE (REG_VEX_0F71) },
8557     { REG_TABLE (REG_VEX_0F72) },
8558     { REG_TABLE (REG_VEX_0F73) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8563     /* 78 */
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8572     /* 80 */
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     /* 88 */
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     /* 90 */
8591     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     /* 98 */
8600     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     /* a0 */
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     /* a8 */
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { REG_TABLE (REG_VEX_0FAE) },
8625     { Bad_Opcode },
8626     /* b0 */
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     /* b8 */
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     /* c0 */
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8648     { Bad_Opcode },
8649     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8651     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8652     { Bad_Opcode },
8653     /* c8 */
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     /* d0 */
8663     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8671     /* d8 */
8672     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8680     /* e0 */
8681     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8689     /* e8 */
8690     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8698     /* f0 */
8699     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8707     /* f8 */
8708     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8715     { Bad_Opcode },
8716   },
8717   /* VEX_0F38 */
8718   {
8719     /* 00 */
8720     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8728     /* 08 */
8729     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8737     /* 10 */
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8746     /* 18 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8750     { Bad_Opcode },
8751     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8754     { Bad_Opcode },
8755     /* 20 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     /* 28 */
8765     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8773     /* 30 */
8774     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8782     /* 38 */
8783     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8791     /* 40 */
8792     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8800     /* 48 */
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     /* 50 */
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* 58 */
8819     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     /* 60 */
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     /* 68 */
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     /* 70 */
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     /* 78 */
8855     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     /* 80 */
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     /* 88 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8878     { Bad_Opcode },
8879     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8880     { Bad_Opcode },
8881     /* 90 */
8882     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8890     /* 98 */
8891     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8899     /* a0 */
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8908     /* a8 */
8909     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8917     /* b0 */
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8926     /* b8 */
8927     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8935     /* c0 */
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     /* c8 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8953     /* d0 */
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     /* d8 */
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8971     /* e0 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     /* e8 */
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     /* f0 */
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8993     { REG_TABLE (REG_VEX_0F38F3) },
8994     { Bad_Opcode },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8998     /* f8 */
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007   },
9008   /* VEX_0F3A */
9009   {
9010     /* 00 */
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9014     { Bad_Opcode },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9018     { Bad_Opcode },
9019     /* 08 */
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9028     /* 10 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9037     /* 18 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     /* 20 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* 28 */
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     /* 30 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     /* 38 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     /* 40 */
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9086     { Bad_Opcode },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9088     { Bad_Opcode },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9090     { Bad_Opcode },
9091     /* 48 */
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     /* 50 */
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     /* 58 */
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9118     /* 60 */
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     /* 68 */
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9136     /* 70 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* 78 */
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9154     /* 80 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* 88 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* 90 */
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     /* 98 */
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     /* a0 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     /* a8 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* b0 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     /* b8 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     /* c0 */
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     /* c8 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9243     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9244     /* d0 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* d8 */
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9262     /* e0 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     /* e8 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     /* f0 */
9281     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     /* f8 */
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298   },
9299 };
9300
9301 #include "i386-dis-evex.h"
9302
9303 static const struct dis386 vex_len_table[][2] = {
9304   /* VEX_LEN_0F12_P_0_M_0 */
9305   {
9306     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9307   },
9308
9309   /* VEX_LEN_0F12_P_0_M_1 */
9310   {
9311     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9312   },
9313
9314   /* VEX_LEN_0F12_P_2 */
9315   {
9316     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9317   },
9318
9319   /* VEX_LEN_0F13_M_0 */
9320   {
9321     { "vmovlpX",        { EXq, XM }, 0 },
9322   },
9323
9324   /* VEX_LEN_0F16_P_0_M_0 */
9325   {
9326     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9327   },
9328
9329   /* VEX_LEN_0F16_P_0_M_1 */
9330   {
9331     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9332   },
9333
9334   /* VEX_LEN_0F16_P_2 */
9335   {
9336     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9337   },
9338
9339   /* VEX_LEN_0F17_M_0 */
9340   {
9341     { "vmovhpX",        { EXq, XM }, 0 },
9342   },
9343
9344   /* VEX_LEN_0F2A_P_1 */
9345   {
9346     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9347     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F2A_P_3 */
9351   {
9352     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9353     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9354   },
9355
9356   /* VEX_LEN_0F2C_P_1 */
9357   {
9358     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9359     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9360   },
9361
9362   /* VEX_LEN_0F2C_P_3 */
9363   {
9364     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9365     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9366   },
9367
9368   /* VEX_LEN_0F2D_P_1 */
9369   {
9370     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9371     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9372   },
9373
9374   /* VEX_LEN_0F2D_P_3 */
9375   {
9376     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9377     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9378   },
9379
9380   /* VEX_LEN_0F41_P_0 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9384   },
9385   /* VEX_LEN_0F41_P_2 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9389   },
9390   /* VEX_LEN_0F42_P_0 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9394   },
9395   /* VEX_LEN_0F42_P_2 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9399   },
9400   /* VEX_LEN_0F44_P_0 */
9401   {
9402     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9403   },
9404   /* VEX_LEN_0F44_P_2 */
9405   {
9406     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9407   },
9408   /* VEX_LEN_0F45_P_0 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9412   },
9413   /* VEX_LEN_0F45_P_2 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9417   },
9418   /* VEX_LEN_0F46_P_0 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9422   },
9423   /* VEX_LEN_0F46_P_2 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9427   },
9428   /* VEX_LEN_0F47_P_0 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9432   },
9433   /* VEX_LEN_0F47_P_2 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9437   },
9438   /* VEX_LEN_0F4A_P_0 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9442   },
9443   /* VEX_LEN_0F4A_P_2 */
9444   {
9445     { Bad_Opcode },
9446     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9447   },
9448   /* VEX_LEN_0F4B_P_0 */
9449   {
9450     { Bad_Opcode },
9451     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9452   },
9453   /* VEX_LEN_0F4B_P_2 */
9454   {
9455     { Bad_Opcode },
9456     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9457   },
9458
9459   /* VEX_LEN_0F6E_P_2 */
9460   {
9461     { "vmovK",          { XMScalar, Edq }, 0 },
9462   },
9463
9464   /* VEX_LEN_0F77_P_1 */
9465   {
9466     { "vzeroupper",     { XX }, 0 },
9467     { "vzeroall",       { XX }, 0 },
9468   },
9469
9470   /* VEX_LEN_0F7E_P_1 */
9471   {
9472     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F7E_P_2 */
9476   {
9477     { "vmovK",          { Edq, XMScalar }, 0 },
9478   },
9479
9480   /* VEX_LEN_0F90_P_0 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F90_P_2 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F91_P_0 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F91_P_2 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F92_P_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F92_P_2 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F92_P_3 */
9511   {
9512     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F93_P_0 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0F93_P_2 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9523   },
9524
9525   /* VEX_LEN_0F93_P_3 */
9526   {
9527     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9528   },
9529
9530   /* VEX_LEN_0F98_P_0 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9533   },
9534
9535   /* VEX_LEN_0F98_P_2 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9538   },
9539
9540   /* VEX_LEN_0F99_P_0 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9543   },
9544
9545   /* VEX_LEN_0F99_P_2 */
9546   {
9547     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9548   },
9549
9550   /* VEX_LEN_0FAE_R_2_M_0 */
9551   {
9552     { "vldmxcsr",       { Md }, 0 },
9553   },
9554
9555   /* VEX_LEN_0FAE_R_3_M_0 */
9556   {
9557     { "vstmxcsr",       { Md }, 0 },
9558   },
9559
9560   /* VEX_LEN_0FC4_P_2 */
9561   {
9562     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9563   },
9564
9565   /* VEX_LEN_0FC5_P_2 */
9566   {
9567     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9568   },
9569
9570   /* VEX_LEN_0FD6_P_2 */
9571   {
9572     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9573   },
9574
9575   /* VEX_LEN_0FF7_P_2 */
9576   {
9577     { "vmaskmovdqu",    { XM, XS }, 0 },
9578   },
9579
9580   /* VEX_LEN_0F3816_P_2 */
9581   {
9582     { Bad_Opcode },
9583     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9584   },
9585
9586   /* VEX_LEN_0F3819_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F381A_P_2_M_0 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9596   },
9597
9598   /* VEX_LEN_0F3836_P_2 */
9599   {
9600     { Bad_Opcode },
9601     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9602   },
9603
9604   /* VEX_LEN_0F3841_P_2 */
9605   {
9606     { "vphminposuw",    { XM, EXx }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F385A_P_2_M_0 */
9610   {
9611     { Bad_Opcode },
9612     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9613   },
9614
9615   /* VEX_LEN_0F38DB_P_2 */
9616   {
9617     { "vaesimc",        { XM, EXx }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F2_P_0 */
9621   {
9622     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F3_R_1_P_0 */
9626   {
9627     { "blsrS",          { VexGdq, Edq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F3_R_2_P_0 */
9631   {
9632     { "blsmskS",        { VexGdq, Edq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F3_R_3_P_0 */
9636   {
9637     { "blsiS",          { VexGdq, Edq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F5_P_0 */
9641   {
9642     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F5_P_1 */
9646   {
9647     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F38F5_P_3 */
9651   {
9652     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F38F6_P_3 */
9656   {
9657     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F38F7_P_0 */
9661   {
9662     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F38F7_P_1 */
9666   {
9667     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F38F7_P_2 */
9671   {
9672     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F38F7_P_3 */
9676   {
9677     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F3A00_P_2 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9684   },
9685
9686   /* VEX_LEN_0F3A01_P_2 */
9687   {
9688     { Bad_Opcode },
9689     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A06_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9696   },
9697
9698   /* VEX_LEN_0F3A14_P_2 */
9699   {
9700     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A15_P_2 */
9704   {
9705     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A16_P_2  */
9709   {
9710     { "vpextrK",        { Edq, XM, Ib }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F3A17_P_2 */
9714   {
9715     { "vextractps",     { Edqd, XM, Ib }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F3A18_P_2 */
9719   {
9720     { Bad_Opcode },
9721     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A19_P_2 */
9725   {
9726     { Bad_Opcode },
9727     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9728   },
9729
9730   /* VEX_LEN_0F3A20_P_2 */
9731   {
9732     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9733   },
9734
9735   /* VEX_LEN_0F3A21_P_2 */
9736   {
9737     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9738   },
9739
9740   /* VEX_LEN_0F3A22_P_2 */
9741   {
9742     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9743   },
9744
9745   /* VEX_LEN_0F3A30_P_2 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9748   },
9749
9750   /* VEX_LEN_0F3A31_P_2 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9753   },
9754
9755   /* VEX_LEN_0F3A32_P_2 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9758   },
9759
9760   /* VEX_LEN_0F3A33_P_2 */
9761   {
9762     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9763   },
9764
9765   /* VEX_LEN_0F3A38_P_2 */
9766   {
9767     { Bad_Opcode },
9768     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9769   },
9770
9771   /* VEX_LEN_0F3A39_P_2 */
9772   {
9773     { Bad_Opcode },
9774     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9775   },
9776
9777   /* VEX_LEN_0F3A41_P_2 */
9778   {
9779     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9780   },
9781
9782   /* VEX_LEN_0F3A46_P_2 */
9783   {
9784     { Bad_Opcode },
9785     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9786   },
9787
9788   /* VEX_LEN_0F3A60_P_2 */
9789   {
9790     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A61_P_2 */
9794   {
9795     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A62_P_2 */
9799   {
9800     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A63_P_2 */
9804   {
9805     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A6A_P_2 */
9809   {
9810     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A6B_P_2 */
9814   {
9815     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3A6E_P_2 */
9819   {
9820     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3A6F_P_2 */
9824   {
9825     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F3A7A_P_2 */
9829   {
9830     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F3A7B_P_2 */
9834   {
9835     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F3A7E_P_2 */
9839   {
9840     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9841   },
9842
9843   /* VEX_LEN_0F3A7F_P_2 */
9844   {
9845     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9846   },
9847
9848   /* VEX_LEN_0F3ADF_P_2 */
9849   {
9850     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9851   },
9852
9853   /* VEX_LEN_0F3AF0_P_3 */
9854   {
9855     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_CC */
9859   {
9860      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_CD */
9864   {
9865      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_CE */
9869   {
9870      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_CF */
9874   {
9875      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_EC */
9879   {
9880      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9881   },
9882
9883   /* VEX_LEN_0FXOP_08_ED */
9884   {
9885      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9886   },
9887
9888   /* VEX_LEN_0FXOP_08_EE */
9889   {
9890      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9891   },
9892
9893   /* VEX_LEN_0FXOP_08_EF */
9894   {
9895      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9896   },
9897
9898   /* VEX_LEN_0FXOP_09_80 */
9899   {
9900     { "vfrczps",        { XM, EXxmm }, 0 },
9901     { "vfrczps",        { XM, EXymmq }, 0 },
9902   },
9903
9904   /* VEX_LEN_0FXOP_09_81 */
9905   {
9906     { "vfrczpd",        { XM, EXxmm }, 0 },
9907     { "vfrczpd",        { XM, EXymmq }, 0 },
9908   },
9909 };
9910
9911 #include "i386-dis-evex-len.h"
9912
9913 static const struct dis386 vex_w_table[][2] = {
9914   {
9915     /* VEX_W_0F41_P_0_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F41_P_2_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9923   },
9924   {
9925     /* VEX_W_0F42_P_0_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F42_P_2_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F44_P_0_LEN_0 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F44_P_2_LEN_0 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F45_P_0_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F45_P_2_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F46_P_0_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F46_P_2_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9963   },
9964   {
9965     /* VEX_W_0F47_P_0_LEN_1 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9968   },
9969   {
9970     /* VEX_W_0F47_P_2_LEN_1 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9972     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F4A_P_0_LEN_1 */
9976     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9977     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9978   },
9979   {
9980     /* VEX_W_0F4A_P_2_LEN_1 */
9981     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9982     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9983   },
9984   {
9985     /* VEX_W_0F4B_P_0_LEN_1 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9987     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9988   },
9989   {
9990     /* VEX_W_0F4B_P_2_LEN_1 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9992   },
9993   {
9994     /* VEX_W_0F90_P_0_LEN_0 */
9995     { "kmovw",          { MaskG, MaskE }, 0 },
9996     { "kmovq",          { MaskG, MaskE }, 0 },
9997   },
9998   {
9999     /* VEX_W_0F90_P_2_LEN_0 */
10000     { "kmovb",          { MaskG, MaskBDE }, 0 },
10001     { "kmovd",          { MaskG, MaskBDE }, 0 },
10002   },
10003   {
10004     /* VEX_W_0F91_P_0_LEN_0 */
10005     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10006     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10007   },
10008   {
10009     /* VEX_W_0F91_P_2_LEN_0 */
10010     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10011     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10012   },
10013   {
10014     /* VEX_W_0F92_P_0_LEN_0 */
10015     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F92_P_2_LEN_0 */
10019     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10020   },
10021   {
10022     /* VEX_W_0F93_P_0_LEN_0 */
10023     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F93_P_2_LEN_0 */
10027     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10028   },
10029   {
10030     /* VEX_W_0F98_P_0_LEN_0 */
10031     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10032     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F98_P_2_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10037     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10038   },
10039   {
10040     /* VEX_W_0F99_P_0_LEN_0 */
10041     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10042     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10043   },
10044   {
10045     /* VEX_W_0F99_P_2_LEN_0 */
10046     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10047     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10048   },
10049   {
10050     /* VEX_W_0F380C_P_2  */
10051     { "vpermilps",      { XM, Vex, EXx }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F380D_P_2  */
10055     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F380E_P_2  */
10059     { "vtestps",        { XM, EXx }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F380F_P_2  */
10063     { "vtestpd",        { XM, EXx }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F3816_P_2  */
10067     { "vpermps",        { XM, Vex, EXx }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F3818_P_2 */
10071     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F3819_P_2 */
10075     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F381A_P_2_M_0 */
10079     { "vbroadcastf128", { XM, Mxmm }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F382C_P_2_M_0 */
10083     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F382D_P_2_M_0 */
10087     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10088   },
10089   {
10090     /* VEX_W_0F382E_P_2_M_0 */
10091     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F382F_P_2_M_0 */
10095     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F3836_P_2  */
10099     { "vpermd",         { XM, Vex, EXx }, 0 },
10100   },
10101   {
10102     /* VEX_W_0F3846_P_2 */
10103     { "vpsravd",        { XM, Vex, EXx }, 0 },
10104   },
10105   {
10106     /* VEX_W_0F3858_P_2 */
10107     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3859_P_2 */
10111     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10112   },
10113   {
10114     /* VEX_W_0F385A_P_2_M_0 */
10115     { "vbroadcasti128", { XM, Mxmm }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3878_P_2 */
10119     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10120   },
10121   {
10122     /* VEX_W_0F3879_P_2 */
10123     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F38CF_P_2 */
10127     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A00_P_2 */
10131     { Bad_Opcode },
10132     { "vpermq",         { XM, EXx, Ib }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A01_P_2 */
10136     { Bad_Opcode },
10137     { "vpermpd",        { XM, EXx, Ib }, 0 },
10138   },
10139   {
10140     /* VEX_W_0F3A02_P_2 */
10141     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10142   },
10143   {
10144     /* VEX_W_0F3A04_P_2 */
10145     { "vpermilps",      { XM, EXx, Ib }, 0 },
10146   },
10147   {
10148     /* VEX_W_0F3A05_P_2 */
10149     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10150   },
10151   {
10152     /* VEX_W_0F3A06_P_2 */
10153     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10154   },
10155   {
10156     /* VEX_W_0F3A18_P_2 */
10157     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10158   },
10159   {
10160     /* VEX_W_0F3A19_P_2 */
10161     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F3A30_P_2_LEN_0 */
10165     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10166     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10167   },
10168   {
10169     /* VEX_W_0F3A31_P_2_LEN_0 */
10170     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10171     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10172   },
10173   {
10174     /* VEX_W_0F3A32_P_2_LEN_0 */
10175     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10176     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10177   },
10178   {
10179     /* VEX_W_0F3A33_P_2_LEN_0 */
10180     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10181     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10182   },
10183   {
10184     /* VEX_W_0F3A38_P_2 */
10185     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F3A39_P_2 */
10189     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10190   },
10191   {
10192     /* VEX_W_0F3A46_P_2 */
10193     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10194   },
10195   {
10196     /* VEX_W_0F3A48_P_2 */
10197     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10198     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3A49_P_2 */
10202     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10203     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F3A4A_P_2 */
10207     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10208   },
10209   {
10210     /* VEX_W_0F3A4B_P_2 */
10211     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F3A4C_P_2 */
10215     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10216   },
10217   {
10218     /* VEX_W_0F3ACE_P_2 */
10219     { Bad_Opcode },
10220     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F3ACF_P_2 */
10224     { Bad_Opcode },
10225     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10226   },
10227
10228 #include "i386-dis-evex-w.h"
10229 };
10230
10231 static const struct dis386 mod_table[][2] = {
10232   {
10233     /* MOD_8D */
10234     { "leaS",           { Gv, M }, 0 },
10235   },
10236   {
10237     /* MOD_C6_REG_7 */
10238     { Bad_Opcode },
10239     { RM_TABLE (RM_C6_REG_7) },
10240   },
10241   {
10242     /* MOD_C7_REG_7 */
10243     { Bad_Opcode },
10244     { RM_TABLE (RM_C7_REG_7) },
10245   },
10246   {
10247     /* MOD_FF_REG_3 */
10248     { "Jcall^", { indirEp }, 0 },
10249   },
10250   {
10251     /* MOD_FF_REG_5 */
10252     { "Jjmp^", { indirEp }, 0 },
10253   },
10254   {
10255     /* MOD_0F01_REG_0 */
10256     { X86_64_TABLE (X86_64_0F01_REG_0) },
10257     { RM_TABLE (RM_0F01_REG_0) },
10258   },
10259   {
10260     /* MOD_0F01_REG_1 */
10261     { X86_64_TABLE (X86_64_0F01_REG_1) },
10262     { RM_TABLE (RM_0F01_REG_1) },
10263   },
10264   {
10265     /* MOD_0F01_REG_2 */
10266     { X86_64_TABLE (X86_64_0F01_REG_2) },
10267     { RM_TABLE (RM_0F01_REG_2) },
10268   },
10269   {
10270     /* MOD_0F01_REG_3 */
10271     { X86_64_TABLE (X86_64_0F01_REG_3) },
10272     { RM_TABLE (RM_0F01_REG_3) },
10273   },
10274   {
10275     /* MOD_0F01_REG_5 */
10276     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10277     { RM_TABLE (RM_0F01_REG_5) },
10278   },
10279   {
10280     /* MOD_0F01_REG_7 */
10281     { "invlpg",         { Mb }, 0 },
10282     { RM_TABLE (RM_0F01_REG_7) },
10283   },
10284   {
10285     /* MOD_0F12_PREFIX_0 */
10286     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10287     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10288   },
10289   {
10290     /* MOD_0F13 */
10291     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10292   },
10293   {
10294     /* MOD_0F16_PREFIX_0 */
10295     { "movhps",         { XM, EXq }, 0 },
10296     { "movlhps",        { XM, EXq }, 0 },
10297   },
10298   {
10299     /* MOD_0F17 */
10300     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10301   },
10302   {
10303     /* MOD_0F18_REG_0 */
10304     { "prefetchnta",    { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_1 */
10308     { "prefetcht0",     { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F18_REG_2 */
10312     { "prefetcht1",     { Mb }, 0 },
10313   },
10314   {
10315     /* MOD_0F18_REG_3 */
10316     { "prefetcht2",     { Mb }, 0 },
10317   },
10318   {
10319     /* MOD_0F18_REG_4 */
10320     { "nop/reserved",   { Mb }, 0 },
10321   },
10322   {
10323     /* MOD_0F18_REG_5 */
10324     { "nop/reserved",   { Mb }, 0 },
10325   },
10326   {
10327     /* MOD_0F18_REG_6 */
10328     { "nop/reserved",   { Mb }, 0 },
10329   },
10330   {
10331     /* MOD_0F18_REG_7 */
10332     { "nop/reserved",   { Mb }, 0 },
10333   },
10334   {
10335     /* MOD_0F1A_PREFIX_0 */
10336     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10337     { "nopQ",           { Ev }, 0 },
10338   },
10339   {
10340     /* MOD_0F1B_PREFIX_0 */
10341     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10342     { "nopQ",           { Ev }, 0 },
10343   },
10344   {
10345     /* MOD_0F1B_PREFIX_1 */
10346     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10347     { "nopQ",           { Ev }, 0 },
10348   },
10349   {
10350     /* MOD_0F1C_PREFIX_0 */
10351     { REG_TABLE (REG_0F1C_MOD_0) },
10352     { "nopQ",           { Ev }, 0 },
10353   },
10354   {
10355     /* MOD_0F1E_PREFIX_1 */
10356     { "nopQ",           { Ev }, 0 },
10357     { REG_TABLE (REG_0F1E_MOD_3) },
10358   },
10359   {
10360     /* MOD_0F24 */
10361     { Bad_Opcode },
10362     { "movL",           { Rd, Td }, 0 },
10363   },
10364   {
10365     /* MOD_0F26 */
10366     { Bad_Opcode },
10367     { "movL",           { Td, Rd }, 0 },
10368   },
10369   {
10370     /* MOD_0F2B_PREFIX_0 */
10371     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10372   },
10373   {
10374     /* MOD_0F2B_PREFIX_1 */
10375     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10376   },
10377   {
10378     /* MOD_0F2B_PREFIX_2 */
10379     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10380   },
10381   {
10382     /* MOD_0F2B_PREFIX_3 */
10383     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10384   },
10385   {
10386     /* MOD_0F51 */
10387     { Bad_Opcode },
10388     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10389   },
10390   {
10391     /* MOD_0F71_REG_2 */
10392     { Bad_Opcode },
10393     { "psrlw",          { MS, Ib }, 0 },
10394   },
10395   {
10396     /* MOD_0F71_REG_4 */
10397     { Bad_Opcode },
10398     { "psraw",          { MS, Ib }, 0 },
10399   },
10400   {
10401     /* MOD_0F71_REG_6 */
10402     { Bad_Opcode },
10403     { "psllw",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F72_REG_2 */
10407     { Bad_Opcode },
10408     { "psrld",          { MS, Ib }, 0 },
10409   },
10410   {
10411     /* MOD_0F72_REG_4 */
10412     { Bad_Opcode },
10413     { "psrad",          { MS, Ib }, 0 },
10414   },
10415   {
10416     /* MOD_0F72_REG_6 */
10417     { Bad_Opcode },
10418     { "pslld",          { MS, Ib }, 0 },
10419   },
10420   {
10421     /* MOD_0F73_REG_2 */
10422     { Bad_Opcode },
10423     { "psrlq",          { MS, Ib }, 0 },
10424   },
10425   {
10426     /* MOD_0F73_REG_3 */
10427     { Bad_Opcode },
10428     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10429   },
10430   {
10431     /* MOD_0F73_REG_6 */
10432     { Bad_Opcode },
10433     { "psllq",          { MS, Ib }, 0 },
10434   },
10435   {
10436     /* MOD_0F73_REG_7 */
10437     { Bad_Opcode },
10438     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_0 */
10442     { "fxsave",         { FXSAVE }, 0 },
10443     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_1 */
10447     { "fxrstor",        { FXSAVE }, 0 },
10448     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10449   },
10450   {
10451     /* MOD_0FAE_REG_2 */
10452     { "ldmxcsr",        { Md }, 0 },
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10454   },
10455   {
10456     /* MOD_0FAE_REG_3 */
10457     { "stmxcsr",        { Md }, 0 },
10458     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10459   },
10460   {
10461     /* MOD_0FAE_REG_4 */
10462     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10463     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10464   },
10465   {
10466     /* MOD_0FAE_REG_5 */
10467     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10468     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10469   },
10470   {
10471     /* MOD_0FAE_REG_6 */
10472     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10473     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10474   },
10475   {
10476     /* MOD_0FAE_REG_7 */
10477     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10478     { RM_TABLE (RM_0FAE_REG_7) },
10479   },
10480   {
10481     /* MOD_0FB2 */
10482     { "lssS",           { Gv, Mp }, 0 },
10483   },
10484   {
10485     /* MOD_0FB4 */
10486     { "lfsS",           { Gv, Mp }, 0 },
10487   },
10488   {
10489     /* MOD_0FB5 */
10490     { "lgsS",           { Gv, Mp }, 0 },
10491   },
10492   {
10493     /* MOD_0FC3 */
10494     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10495   },
10496   {
10497     /* MOD_0FC7_REG_3 */
10498     { "xrstors",        { FXSAVE }, 0 },
10499   },
10500   {
10501     /* MOD_0FC7_REG_4 */
10502     { "xsavec",         { FXSAVE }, 0 },
10503   },
10504   {
10505     /* MOD_0FC7_REG_5 */
10506     { "xsaves",         { FXSAVE }, 0 },
10507   },
10508   {
10509     /* MOD_0FC7_REG_6 */
10510     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10511     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10512   },
10513   {
10514     /* MOD_0FC7_REG_7 */
10515     { "vmptrst",        { Mq }, 0 },
10516     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10517   },
10518   {
10519     /* MOD_0FD7 */
10520     { Bad_Opcode },
10521     { "pmovmskb",       { Gdq, MS }, 0 },
10522   },
10523   {
10524     /* MOD_0FE7_PREFIX_2 */
10525     { "movntdq",        { Mx, XM }, 0 },
10526   },
10527   {
10528     /* MOD_0FF0_PREFIX_3 */
10529     { "lddqu",          { XM, M }, 0 },
10530   },
10531   {
10532     /* MOD_0F382A_PREFIX_2 */
10533     { "movntdqa",       { XM, Mx }, 0 },
10534   },
10535   {
10536     /* MOD_0F38F5_PREFIX_2 */
10537     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10538   },
10539   {
10540     /* MOD_0F38F6_PREFIX_0 */
10541     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10542   },
10543   {
10544     /* MOD_0F38F8_PREFIX_1 */
10545     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10546   },
10547   {
10548     /* MOD_0F38F8_PREFIX_2 */
10549     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10550   },
10551   {
10552     /* MOD_0F38F8_PREFIX_3 */
10553     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10554   },
10555   {
10556     /* MOD_0F38F9_PREFIX_0 */
10557     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10558   },
10559   {
10560     /* MOD_62_32BIT */
10561     { "bound{S|}",      { Gv, Ma }, 0 },
10562     { EVEX_TABLE (EVEX_0F) },
10563   },
10564   {
10565     /* MOD_C4_32BIT */
10566     { "lesS",           { Gv, Mp }, 0 },
10567     { VEX_C4_TABLE (VEX_0F) },
10568   },
10569   {
10570     /* MOD_C5_32BIT */
10571     { "ldsS",           { Gv, Mp }, 0 },
10572     { VEX_C5_TABLE (VEX_0F) },
10573   },
10574   {
10575     /* MOD_VEX_0F12_PREFIX_0 */
10576     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10577     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10578   },
10579   {
10580     /* MOD_VEX_0F13 */
10581     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10582   },
10583   {
10584     /* MOD_VEX_0F16_PREFIX_0 */
10585     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10586     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10587   },
10588   {
10589     /* MOD_VEX_0F17 */
10590     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10591   },
10592   {
10593     /* MOD_VEX_0F2B */
10594     { "vmovntpX",       { Mx, XM }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10608     { Bad_Opcode },
10609     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10613     { Bad_Opcode },
10614     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10618     { Bad_Opcode },
10619     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10623     { Bad_Opcode },
10624     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10628     { Bad_Opcode },
10629     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10633     { Bad_Opcode },
10634     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10638     { Bad_Opcode },
10639     { "knotw",          { MaskG, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10643     { Bad_Opcode },
10644     { "knotq",          { MaskG, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10648     { Bad_Opcode },
10649     { "knotb",          { MaskG, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10653     { Bad_Opcode },
10654     { "knotd",          { MaskG, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10658     { Bad_Opcode },
10659     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10663     { Bad_Opcode },
10664     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10668     { Bad_Opcode },
10669     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10673     { Bad_Opcode },
10674     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676  {
10677     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10688     { Bad_Opcode },
10689     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10693     { Bad_Opcode },
10694     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10698     { Bad_Opcode },
10699     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10703     { Bad_Opcode },
10704     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10708     { Bad_Opcode },
10709     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10713     { Bad_Opcode },
10714     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10718     { Bad_Opcode },
10719     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10723     { Bad_Opcode },
10724     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10728     { Bad_Opcode },
10729     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10733     { Bad_Opcode },
10734     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10738     { Bad_Opcode },
10739     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10743     { Bad_Opcode },
10744     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10745   },
10746   {
10747     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10748     { Bad_Opcode },
10749     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10750   },
10751   {
10752     /* MOD_VEX_0F50 */
10753     { Bad_Opcode },
10754     { "vmovmskpX",      { Gdq, XS }, 0 },
10755   },
10756   {
10757     /* MOD_VEX_0F71_REG_2 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10760   },
10761   {
10762     /* MOD_VEX_0F71_REG_4 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10765   },
10766   {
10767     /* MOD_VEX_0F71_REG_6 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10770   },
10771   {
10772     /* MOD_VEX_0F72_REG_2 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10775   },
10776   {
10777     /* MOD_VEX_0F72_REG_4 */
10778     { Bad_Opcode },
10779     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10780   },
10781   {
10782     /* MOD_VEX_0F72_REG_6 */
10783     { Bad_Opcode },
10784     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10785   },
10786   {
10787     /* MOD_VEX_0F73_REG_2 */
10788     { Bad_Opcode },
10789     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10790   },
10791   {
10792     /* MOD_VEX_0F73_REG_3 */
10793     { Bad_Opcode },
10794     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10795   },
10796   {
10797     /* MOD_VEX_0F73_REG_6 */
10798     { Bad_Opcode },
10799     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10800   },
10801   {
10802     /* MOD_VEX_0F73_REG_7 */
10803     { Bad_Opcode },
10804     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10808     { "kmovw",          { Ew, MaskG }, 0 },
10809     { Bad_Opcode },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10813     { "kmovq",          { Eq, MaskG }, 0 },
10814     { Bad_Opcode },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10818     { "kmovb",          { Eb, MaskG }, 0 },
10819     { Bad_Opcode },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10823     { "kmovd",          { Ed, MaskG }, 0 },
10824     { Bad_Opcode },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kmovw",          { MaskG, Rdq }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "kmovb",          { MaskG, Rdq }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_0F92_P_3_LEN_0 */
10838     { Bad_Opcode },
10839     { "kmovK",          { MaskG, Rdq }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10843     { Bad_Opcode },
10844     { "kmovw",          { Gdq, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10848     { Bad_Opcode },
10849     { "kmovb",          { Gdq, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_0F93_P_3_LEN_0 */
10853     { Bad_Opcode },
10854     { "kmovK",          { Gdq, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10858     { Bad_Opcode },
10859     { "kortestw", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10863     { Bad_Opcode },
10864     { "kortestq", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10868     { Bad_Opcode },
10869     { "kortestb", { MaskG, MaskR }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10873     { Bad_Opcode },
10874     { "kortestd", { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10878     { Bad_Opcode },
10879     { "ktestw", { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10883     { Bad_Opcode },
10884     { "ktestq", { MaskG, MaskR }, 0 },
10885   },
10886   {
10887     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10888     { Bad_Opcode },
10889     { "ktestb", { MaskG, MaskR }, 0 },
10890   },
10891   {
10892     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10893     { Bad_Opcode },
10894     { "ktestd", { MaskG, MaskR }, 0 },
10895   },
10896   {
10897     /* MOD_VEX_0FAE_REG_2 */
10898     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10899   },
10900   {
10901     /* MOD_VEX_0FAE_REG_3 */
10902     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10903   },
10904   {
10905     /* MOD_VEX_0FD7_PREFIX_2 */
10906     { Bad_Opcode },
10907     { "vpmovmskb",      { Gdq, XS }, 0 },
10908   },
10909   {
10910     /* MOD_VEX_0FE7_PREFIX_2 */
10911     { "vmovntdq",       { Mx, XM }, 0 },
10912   },
10913   {
10914     /* MOD_VEX_0FF0_PREFIX_3 */
10915     { "vlddqu",         { XM, M }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0F381A_PREFIX_2 */
10919     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10920   },
10921   {
10922     /* MOD_VEX_0F382A_PREFIX_2 */
10923     { "vmovntdqa",      { XM, Mx }, 0 },
10924   },
10925   {
10926     /* MOD_VEX_0F382C_PREFIX_2 */
10927     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10928   },
10929   {
10930     /* MOD_VEX_0F382D_PREFIX_2 */
10931     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10932   },
10933   {
10934     /* MOD_VEX_0F382E_PREFIX_2 */
10935     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10936   },
10937   {
10938     /* MOD_VEX_0F382F_PREFIX_2 */
10939     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10940   },
10941   {
10942     /* MOD_VEX_0F385A_PREFIX_2 */
10943     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10944   },
10945   {
10946     /* MOD_VEX_0F388C_PREFIX_2 */
10947     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10948   },
10949   {
10950     /* MOD_VEX_0F388E_PREFIX_2 */
10951     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10965     { Bad_Opcode },
10966     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10967   },
10968   {
10969     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10970     { Bad_Opcode },
10971     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10972   },
10973   {
10974     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10975     { Bad_Opcode },
10976     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10977   },
10978   {
10979     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10980     { Bad_Opcode },
10981     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10982   },
10983   {
10984     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10985     { Bad_Opcode },
10986     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10987   },
10988   {
10989     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10990     { Bad_Opcode },
10991     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10992   },
10993
10994 #include "i386-dis-evex-mod.h"
10995 };
10996
10997 static const struct dis386 rm_table[][8] = {
10998   {
10999     /* RM_C6_REG_7 */
11000     { "xabort",         { Skip_MODRM, Ib }, 0 },
11001   },
11002   {
11003     /* RM_C7_REG_7 */
11004     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11005   },
11006   {
11007     /* RM_0F01_REG_0 */
11008     { "enclv",          { Skip_MODRM }, 0 },
11009     { "vmcall",         { Skip_MODRM }, 0 },
11010     { "vmlaunch",       { Skip_MODRM }, 0 },
11011     { "vmresume",       { Skip_MODRM }, 0 },
11012     { "vmxoff",         { Skip_MODRM }, 0 },
11013     { "pconfig",        { Skip_MODRM }, 0 },
11014   },
11015   {
11016     /* RM_0F01_REG_1 */
11017     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11018     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11019     { "clac",           { Skip_MODRM }, 0 },
11020     { "stac",           { Skip_MODRM }, 0 },
11021     { Bad_Opcode },
11022     { Bad_Opcode },
11023     { Bad_Opcode },
11024     { "encls",          { Skip_MODRM }, 0 },
11025   },
11026   {
11027     /* RM_0F01_REG_2 */
11028     { "xgetbv",         { Skip_MODRM }, 0 },
11029     { "xsetbv",         { Skip_MODRM }, 0 },
11030     { Bad_Opcode },
11031     { Bad_Opcode },
11032     { "vmfunc",         { Skip_MODRM }, 0 },
11033     { "xend",           { Skip_MODRM }, 0 },
11034     { "xtest",          { Skip_MODRM }, 0 },
11035     { "enclu",          { Skip_MODRM }, 0 },
11036   },
11037   {
11038     /* RM_0F01_REG_3 */
11039     { "vmrun",          { Skip_MODRM }, 0 },
11040     { "vmmcall",        { Skip_MODRM }, 0 },
11041     { "vmload",         { Skip_MODRM }, 0 },
11042     { "vmsave",         { Skip_MODRM }, 0 },
11043     { "stgi",           { Skip_MODRM }, 0 },
11044     { "clgi",           { Skip_MODRM }, 0 },
11045     { "skinit",         { Skip_MODRM }, 0 },
11046     { "invlpga",        { Skip_MODRM }, 0 },
11047   },
11048   {
11049     /* RM_0F01_REG_5 */
11050     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11051     { Bad_Opcode },
11052     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11053     { Bad_Opcode },
11054     { Bad_Opcode },
11055     { Bad_Opcode },
11056     { "rdpkru",         { Skip_MODRM }, 0 },
11057     { "wrpkru",         { Skip_MODRM }, 0 },
11058   },
11059   {
11060     /* RM_0F01_REG_7 */
11061     { "swapgs",         { Skip_MODRM }, 0  },
11062     { "rdtscp",         { Skip_MODRM }, 0  },
11063     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11064     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11065     { "clzero",         { Skip_MODRM }, 0  },
11066   },
11067   {
11068     /* RM_0F1E_MOD_3_REG_7 */
11069     { "nopQ",           { Ev }, 0 },
11070     { "nopQ",           { Ev }, 0 },
11071     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11072     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11073     { "nopQ",           { Ev }, 0 },
11074     { "nopQ",           { Ev }, 0 },
11075     { "nopQ",           { Ev }, 0 },
11076     { "nopQ",           { Ev }, 0 },
11077   },
11078   {
11079     /* RM_0FAE_REG_6 */
11080     { "mfence",         { Skip_MODRM }, 0 },
11081   },
11082   {
11083     /* RM_0FAE_REG_7 */
11084     { "sfence",         { Skip_MODRM }, 0 },
11085
11086   },
11087 };
11088
11089 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11090
11091 /* We use the high bit to indicate different name for the same
11092    prefix.  */
11093 #define REP_PREFIX      (0xf3 | 0x100)
11094 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11095 #define XRELEASE_PREFIX (0xf3 | 0x400)
11096 #define BND_PREFIX      (0xf2 | 0x400)
11097 #define NOTRACK_PREFIX  (0x3e | 0x100)
11098
11099 static int
11100 ckprefix (void)
11101 {
11102   int newrex, i, length;
11103   rex = 0;
11104   rex_ignored = 0;
11105   prefixes = 0;
11106   used_prefixes = 0;
11107   rex_used = 0;
11108   last_lock_prefix = -1;
11109   last_repz_prefix = -1;
11110   last_repnz_prefix = -1;
11111   last_data_prefix = -1;
11112   last_addr_prefix = -1;
11113   last_rex_prefix = -1;
11114   last_seg_prefix = -1;
11115   fwait_prefix = -1;
11116   active_seg_prefix = 0;
11117   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11118     all_prefixes[i] = 0;
11119   i = 0;
11120   length = 0;
11121   /* The maximum instruction length is 15bytes.  */
11122   while (length < MAX_CODE_LENGTH - 1)
11123     {
11124       FETCH_DATA (the_info, codep + 1);
11125       newrex = 0;
11126       switch (*codep)
11127         {
11128         /* REX prefixes family.  */
11129         case 0x40:
11130         case 0x41:
11131         case 0x42:
11132         case 0x43:
11133         case 0x44:
11134         case 0x45:
11135         case 0x46:
11136         case 0x47:
11137         case 0x48:
11138         case 0x49:
11139         case 0x4a:
11140         case 0x4b:
11141         case 0x4c:
11142         case 0x4d:
11143         case 0x4e:
11144         case 0x4f:
11145           if (address_mode == mode_64bit)
11146             newrex = *codep;
11147           else
11148             return 1;
11149           last_rex_prefix = i;
11150           break;
11151         case 0xf3:
11152           prefixes |= PREFIX_REPZ;
11153           last_repz_prefix = i;
11154           break;
11155         case 0xf2:
11156           prefixes |= PREFIX_REPNZ;
11157           last_repnz_prefix = i;
11158           break;
11159         case 0xf0:
11160           prefixes |= PREFIX_LOCK;
11161           last_lock_prefix = i;
11162           break;
11163         case 0x2e:
11164           prefixes |= PREFIX_CS;
11165           last_seg_prefix = i;
11166           active_seg_prefix = PREFIX_CS;
11167           break;
11168         case 0x36:
11169           prefixes |= PREFIX_SS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_SS;
11172           break;
11173         case 0x3e:
11174           prefixes |= PREFIX_DS;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_DS;
11177           break;
11178         case 0x26:
11179           prefixes |= PREFIX_ES;
11180           last_seg_prefix = i;
11181           active_seg_prefix = PREFIX_ES;
11182           break;
11183         case 0x64:
11184           prefixes |= PREFIX_FS;
11185           last_seg_prefix = i;
11186           active_seg_prefix = PREFIX_FS;
11187           break;
11188         case 0x65:
11189           prefixes |= PREFIX_GS;
11190           last_seg_prefix = i;
11191           active_seg_prefix = PREFIX_GS;
11192           break;
11193         case 0x66:
11194           prefixes |= PREFIX_DATA;
11195           last_data_prefix = i;
11196           break;
11197         case 0x67:
11198           prefixes |= PREFIX_ADDR;
11199           last_addr_prefix = i;
11200           break;
11201         case FWAIT_OPCODE:
11202           /* fwait is really an instruction.  If there are prefixes
11203              before the fwait, they belong to the fwait, *not* to the
11204              following instruction.  */
11205           fwait_prefix = i;
11206           if (prefixes || rex)
11207             {
11208               prefixes |= PREFIX_FWAIT;
11209               codep++;
11210               /* This ensures that the previous REX prefixes are noticed
11211                  as unused prefixes, as in the return case below.  */
11212               rex_used = rex;
11213               return 1;
11214             }
11215           prefixes = PREFIX_FWAIT;
11216           break;
11217         default:
11218           return 1;
11219         }
11220       /* Rex is ignored when followed by another prefix.  */
11221       if (rex)
11222         {
11223           rex_used = rex;
11224           return 1;
11225         }
11226       if (*codep != FWAIT_OPCODE)
11227         all_prefixes[i++] = *codep;
11228       rex = newrex;
11229       codep++;
11230       length++;
11231     }
11232   return 0;
11233 }
11234
11235 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11236    prefix byte.  */
11237
11238 static const char *
11239 prefix_name (int pref, int sizeflag)
11240 {
11241   static const char *rexes [16] =
11242     {
11243       "rex",            /* 0x40 */
11244       "rex.B",          /* 0x41 */
11245       "rex.X",          /* 0x42 */
11246       "rex.XB",         /* 0x43 */
11247       "rex.R",          /* 0x44 */
11248       "rex.RB",         /* 0x45 */
11249       "rex.RX",         /* 0x46 */
11250       "rex.RXB",        /* 0x47 */
11251       "rex.W",          /* 0x48 */
11252       "rex.WB",         /* 0x49 */
11253       "rex.WX",         /* 0x4a */
11254       "rex.WXB",        /* 0x4b */
11255       "rex.WR",         /* 0x4c */
11256       "rex.WRB",        /* 0x4d */
11257       "rex.WRX",        /* 0x4e */
11258       "rex.WRXB",       /* 0x4f */
11259     };
11260
11261   switch (pref)
11262     {
11263     /* REX prefixes family.  */
11264     case 0x40:
11265     case 0x41:
11266     case 0x42:
11267     case 0x43:
11268     case 0x44:
11269     case 0x45:
11270     case 0x46:
11271     case 0x47:
11272     case 0x48:
11273     case 0x49:
11274     case 0x4a:
11275     case 0x4b:
11276     case 0x4c:
11277     case 0x4d:
11278     case 0x4e:
11279     case 0x4f:
11280       return rexes [pref - 0x40];
11281     case 0xf3:
11282       return "repz";
11283     case 0xf2:
11284       return "repnz";
11285     case 0xf0:
11286       return "lock";
11287     case 0x2e:
11288       return "cs";
11289     case 0x36:
11290       return "ss";
11291     case 0x3e:
11292       return "ds";
11293     case 0x26:
11294       return "es";
11295     case 0x64:
11296       return "fs";
11297     case 0x65:
11298       return "gs";
11299     case 0x66:
11300       return (sizeflag & DFLAG) ? "data16" : "data32";
11301     case 0x67:
11302       if (address_mode == mode_64bit)
11303         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11304       else
11305         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11306     case FWAIT_OPCODE:
11307       return "fwait";
11308     case REP_PREFIX:
11309       return "rep";
11310     case XACQUIRE_PREFIX:
11311       return "xacquire";
11312     case XRELEASE_PREFIX:
11313       return "xrelease";
11314     case BND_PREFIX:
11315       return "bnd";
11316     case NOTRACK_PREFIX:
11317       return "notrack";
11318     default:
11319       return NULL;
11320     }
11321 }
11322
11323 static char op_out[MAX_OPERANDS][100];
11324 static int op_ad, op_index[MAX_OPERANDS];
11325 static int two_source_ops;
11326 static bfd_vma op_address[MAX_OPERANDS];
11327 static bfd_vma op_riprel[MAX_OPERANDS];
11328 static bfd_vma start_pc;
11329
11330 /*
11331  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11332  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11333  *   section of the "Virtual 8086 Mode" chapter.)
11334  * 'pc' should be the address of this instruction, it will
11335  *   be used to print the target address if this is a relative jump or call
11336  * The function returns the length of this instruction in bytes.
11337  */
11338
11339 static char intel_syntax;
11340 static char intel_mnemonic = !SYSV386_COMPAT;
11341 static char open_char;
11342 static char close_char;
11343 static char separator_char;
11344 static char scale_char;
11345
11346 enum x86_64_isa
11347 {
11348   amd64 = 0,
11349   intel64
11350 };
11351
11352 static enum x86_64_isa isa64;
11353
11354 /* Here for backwards compatibility.  When gdb stops using
11355    print_insn_i386_att and print_insn_i386_intel these functions can
11356    disappear, and print_insn_i386 be merged into print_insn.  */
11357 int
11358 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11359 {
11360   intel_syntax = 0;
11361
11362   return print_insn (pc, info);
11363 }
11364
11365 int
11366 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11367 {
11368   intel_syntax = 1;
11369
11370   return print_insn (pc, info);
11371 }
11372
11373 int
11374 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11375 {
11376   intel_syntax = -1;
11377
11378   return print_insn (pc, info);
11379 }
11380
11381 void
11382 print_i386_disassembler_options (FILE *stream)
11383 {
11384   fprintf (stream, _("\n\
11385 The following i386/x86-64 specific disassembler options are supported for use\n\
11386 with the -M switch (multiple options should be separated by commas):\n"));
11387
11388   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11389   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11390   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11391   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11392   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11393   fprintf (stream, _("  att-mnemonic\n"
11394                      "              Display instruction in AT&T mnemonic\n"));
11395   fprintf (stream, _("  intel-mnemonic\n"
11396                      "              Display instruction in Intel mnemonic\n"));
11397   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11398   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11399   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11400   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11401   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11402   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11403   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11404   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11405 }
11406
11407 /* Bad opcode.  */
11408 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11409
11410 /* Get a pointer to struct dis386 with a valid name.  */
11411
11412 static const struct dis386 *
11413 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11414 {
11415   int vindex, vex_table_index;
11416
11417   if (dp->name != NULL)
11418     return dp;
11419
11420   switch (dp->op[0].bytemode)
11421     {
11422     case USE_REG_TABLE:
11423       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11424       break;
11425
11426     case USE_MOD_TABLE:
11427       vindex = modrm.mod == 0x3 ? 1 : 0;
11428       dp = &mod_table[dp->op[1].bytemode][vindex];
11429       break;
11430
11431     case USE_RM_TABLE:
11432       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11433       break;
11434
11435     case USE_PREFIX_TABLE:
11436       if (need_vex)
11437         {
11438           /* The prefix in VEX is implicit.  */
11439           switch (vex.prefix)
11440             {
11441             case 0:
11442               vindex = 0;
11443               break;
11444             case REPE_PREFIX_OPCODE:
11445               vindex = 1;
11446               break;
11447             case DATA_PREFIX_OPCODE:
11448               vindex = 2;
11449               break;
11450             case REPNE_PREFIX_OPCODE:
11451               vindex = 3;
11452               break;
11453             default:
11454               abort ();
11455               break;
11456             }
11457         }
11458       else
11459         {
11460           int last_prefix = -1;
11461           int prefix = 0;
11462           vindex = 0;
11463           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11464              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11465              last one wins.  */
11466           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11467             {
11468               if (last_repz_prefix > last_repnz_prefix)
11469                 {
11470                   vindex = 1;
11471                   prefix = PREFIX_REPZ;
11472                   last_prefix = last_repz_prefix;
11473                 }
11474               else
11475                 {
11476                   vindex = 3;
11477                   prefix = PREFIX_REPNZ;
11478                   last_prefix = last_repnz_prefix;
11479                 }
11480
11481               /* Check if prefix should be ignored.  */
11482               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11483                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11484                    & prefix) != 0)
11485                 vindex = 0;
11486             }
11487
11488           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11489             {
11490               vindex = 2;
11491               prefix = PREFIX_DATA;
11492               last_prefix = last_data_prefix;
11493             }
11494
11495           if (vindex != 0)
11496             {
11497               used_prefixes |= prefix;
11498               all_prefixes[last_prefix] = 0;
11499             }
11500         }
11501       dp = &prefix_table[dp->op[1].bytemode][vindex];
11502       break;
11503
11504     case USE_X86_64_TABLE:
11505       vindex = address_mode == mode_64bit ? 1 : 0;
11506       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11507       break;
11508
11509     case USE_3BYTE_TABLE:
11510       FETCH_DATA (info, codep + 2);
11511       vindex = *codep++;
11512       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11513       end_codep = codep;
11514       modrm.mod = (*codep >> 6) & 3;
11515       modrm.reg = (*codep >> 3) & 7;
11516       modrm.rm = *codep & 7;
11517       break;
11518
11519     case USE_VEX_LEN_TABLE:
11520       if (!need_vex)
11521         abort ();
11522
11523       switch (vex.length)
11524         {
11525         case 128:
11526           vindex = 0;
11527           break;
11528         case 256:
11529           vindex = 1;
11530           break;
11531         default:
11532           abort ();
11533           break;
11534         }
11535
11536       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11537       break;
11538
11539     case USE_EVEX_LEN_TABLE:
11540       if (!vex.evex)
11541         abort ();
11542
11543       switch (vex.length)
11544         {
11545         case 128:
11546           vindex = 0;
11547           break;
11548         case 256:
11549           vindex = 1;
11550           break;
11551         case 512:
11552           vindex = 2;
11553           break;
11554         default:
11555           abort ();
11556           break;
11557         }
11558
11559       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11560       break;
11561
11562     case USE_XOP_8F_TABLE:
11563       FETCH_DATA (info, codep + 3);
11564       /* All bits in the REX prefix are ignored.  */
11565       rex_ignored = rex;
11566       rex = ~(*codep >> 5) & 0x7;
11567
11568       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11569       switch ((*codep & 0x1f))
11570         {
11571         default:
11572           dp = &bad_opcode;
11573           return dp;
11574         case 0x8:
11575           vex_table_index = XOP_08;
11576           break;
11577         case 0x9:
11578           vex_table_index = XOP_09;
11579           break;
11580         case 0xa:
11581           vex_table_index = XOP_0A;
11582           break;
11583         }
11584       codep++;
11585       vex.w = *codep & 0x80;
11586       if (vex.w && address_mode == mode_64bit)
11587         rex |= REX_W;
11588
11589       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11590       if (address_mode != mode_64bit)
11591         {
11592           /* In 16/32-bit mode REX_B is silently ignored.  */
11593           rex &= ~REX_B;
11594         }
11595
11596       vex.length = (*codep & 0x4) ? 256 : 128;
11597       switch ((*codep & 0x3))
11598         {
11599         case 0:
11600           break;
11601         case 1:
11602           vex.prefix = DATA_PREFIX_OPCODE;
11603           break;
11604         case 2:
11605           vex.prefix = REPE_PREFIX_OPCODE;
11606           break;
11607         case 3:
11608           vex.prefix = REPNE_PREFIX_OPCODE;
11609           break;
11610         }
11611       need_vex = 1;
11612       need_vex_reg = 1;
11613       codep++;
11614       vindex = *codep++;
11615       dp = &xop_table[vex_table_index][vindex];
11616
11617       end_codep = codep;
11618       FETCH_DATA (info, codep + 1);
11619       modrm.mod = (*codep >> 6) & 3;
11620       modrm.reg = (*codep >> 3) & 7;
11621       modrm.rm = *codep & 7;
11622       break;
11623
11624     case USE_VEX_C4_TABLE:
11625       /* VEX prefix.  */
11626       FETCH_DATA (info, codep + 3);
11627       /* All bits in the REX prefix are ignored.  */
11628       rex_ignored = rex;
11629       rex = ~(*codep >> 5) & 0x7;
11630       switch ((*codep & 0x1f))
11631         {
11632         default:
11633           dp = &bad_opcode;
11634           return dp;
11635         case 0x1:
11636           vex_table_index = VEX_0F;
11637           break;
11638         case 0x2:
11639           vex_table_index = VEX_0F38;
11640           break;
11641         case 0x3:
11642           vex_table_index = VEX_0F3A;
11643           break;
11644         }
11645       codep++;
11646       vex.w = *codep & 0x80;
11647       if (address_mode == mode_64bit)
11648         {
11649           if (vex.w)
11650             rex |= REX_W;
11651         }
11652       else
11653         {
11654           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11655              is ignored, other REX bits are 0 and the highest bit in
11656              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11657           rex = 0;
11658         }
11659       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11660       vex.length = (*codep & 0x4) ? 256 : 128;
11661       switch ((*codep & 0x3))
11662         {
11663         case 0:
11664           break;
11665         case 1:
11666           vex.prefix = DATA_PREFIX_OPCODE;
11667           break;
11668         case 2:
11669           vex.prefix = REPE_PREFIX_OPCODE;
11670           break;
11671         case 3:
11672           vex.prefix = REPNE_PREFIX_OPCODE;
11673           break;
11674         }
11675       need_vex = 1;
11676       need_vex_reg = 1;
11677       codep++;
11678       vindex = *codep++;
11679       dp = &vex_table[vex_table_index][vindex];
11680       end_codep = codep;
11681       /* There is no MODRM byte for VEX0F 77.  */
11682       if (vex_table_index != VEX_0F || vindex != 0x77)
11683         {
11684           FETCH_DATA (info, codep + 1);
11685           modrm.mod = (*codep >> 6) & 3;
11686           modrm.reg = (*codep >> 3) & 7;
11687           modrm.rm = *codep & 7;
11688         }
11689       break;
11690
11691     case USE_VEX_C5_TABLE:
11692       /* VEX prefix.  */
11693       FETCH_DATA (info, codep + 2);
11694       /* All bits in the REX prefix are ignored.  */
11695       rex_ignored = rex;
11696       rex = (*codep & 0x80) ? 0 : REX_R;
11697
11698       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11699          VEX.vvvv is 1.  */
11700       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11701       vex.length = (*codep & 0x4) ? 256 : 128;
11702       switch ((*codep & 0x3))
11703         {
11704         case 0:
11705           break;
11706         case 1:
11707           vex.prefix = DATA_PREFIX_OPCODE;
11708           break;
11709         case 2:
11710           vex.prefix = REPE_PREFIX_OPCODE;
11711           break;
11712         case 3:
11713           vex.prefix = REPNE_PREFIX_OPCODE;
11714           break;
11715         }
11716       need_vex = 1;
11717       need_vex_reg = 1;
11718       codep++;
11719       vindex = *codep++;
11720       dp = &vex_table[dp->op[1].bytemode][vindex];
11721       end_codep = codep;
11722       /* There is no MODRM byte for VEX 77.  */
11723       if (vindex != 0x77)
11724         {
11725           FETCH_DATA (info, codep + 1);
11726           modrm.mod = (*codep >> 6) & 3;
11727           modrm.reg = (*codep >> 3) & 7;
11728           modrm.rm = *codep & 7;
11729         }
11730       break;
11731
11732     case USE_VEX_W_TABLE:
11733       if (!need_vex)
11734         abort ();
11735
11736       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11737       break;
11738
11739     case USE_EVEX_TABLE:
11740       two_source_ops = 0;
11741       /* EVEX prefix.  */
11742       vex.evex = 1;
11743       FETCH_DATA (info, codep + 4);
11744       /* All bits in the REX prefix are ignored.  */
11745       rex_ignored = rex;
11746       /* The first byte after 0x62.  */
11747       rex = ~(*codep >> 5) & 0x7;
11748       vex.r = *codep & 0x10;
11749       switch ((*codep & 0xf))
11750         {
11751         default:
11752           return &bad_opcode;
11753         case 0x1:
11754           vex_table_index = EVEX_0F;
11755           break;
11756         case 0x2:
11757           vex_table_index = EVEX_0F38;
11758           break;
11759         case 0x3:
11760           vex_table_index = EVEX_0F3A;
11761           break;
11762         }
11763
11764       /* The second byte after 0x62.  */
11765       codep++;
11766       vex.w = *codep & 0x80;
11767       if (vex.w && address_mode == mode_64bit)
11768         rex |= REX_W;
11769
11770       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11771
11772       /* The U bit.  */
11773       if (!(*codep & 0x4))
11774         return &bad_opcode;
11775
11776       switch ((*codep & 0x3))
11777         {
11778         case 0:
11779           break;
11780         case 1:
11781           vex.prefix = DATA_PREFIX_OPCODE;
11782           break;
11783         case 2:
11784           vex.prefix = REPE_PREFIX_OPCODE;
11785           break;
11786         case 3:
11787           vex.prefix = REPNE_PREFIX_OPCODE;
11788           break;
11789         }
11790
11791       /* The third byte after 0x62.  */
11792       codep++;
11793
11794       /* Remember the static rounding bits.  */
11795       vex.ll = (*codep >> 5) & 3;
11796       vex.b = (*codep & 0x10) != 0;
11797
11798       vex.v = *codep & 0x8;
11799       vex.mask_register_specifier = *codep & 0x7;
11800       vex.zeroing = *codep & 0x80;
11801
11802       if (address_mode != mode_64bit)
11803         {
11804           /* In 16/32-bit mode silently ignore following bits.  */
11805           rex &= ~REX_B;
11806           vex.r = 1;
11807           vex.v = 1;
11808         }
11809
11810       need_vex = 1;
11811       need_vex_reg = 1;
11812       codep++;
11813       vindex = *codep++;
11814       dp = &evex_table[vex_table_index][vindex];
11815       end_codep = codep;
11816       FETCH_DATA (info, codep + 1);
11817       modrm.mod = (*codep >> 6) & 3;
11818       modrm.reg = (*codep >> 3) & 7;
11819       modrm.rm = *codep & 7;
11820
11821       /* Set vector length.  */
11822       if (modrm.mod == 3 && vex.b)
11823         vex.length = 512;
11824       else
11825         {
11826           switch (vex.ll)
11827             {
11828             case 0x0:
11829               vex.length = 128;
11830               break;
11831             case 0x1:
11832               vex.length = 256;
11833               break;
11834             case 0x2:
11835               vex.length = 512;
11836               break;
11837             default:
11838               return &bad_opcode;
11839             }
11840         }
11841       break;
11842
11843     case 0:
11844       dp = &bad_opcode;
11845       break;
11846
11847     default:
11848       abort ();
11849     }
11850
11851   if (dp->name != NULL)
11852     return dp;
11853   else
11854     return get_valid_dis386 (dp, info);
11855 }
11856
11857 static void
11858 get_sib (disassemble_info *info, int sizeflag)
11859 {
11860   /* If modrm.mod == 3, operand must be register.  */
11861   if (need_modrm
11862       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11863       && modrm.mod != 3
11864       && modrm.rm == 4)
11865     {
11866       FETCH_DATA (info, codep + 2);
11867       sib.index = (codep [1] >> 3) & 7;
11868       sib.scale = (codep [1] >> 6) & 3;
11869       sib.base = codep [1] & 7;
11870     }
11871 }
11872
11873 static int
11874 print_insn (bfd_vma pc, disassemble_info *info)
11875 {
11876   const struct dis386 *dp;
11877   int i;
11878   char *op_txt[MAX_OPERANDS];
11879   int needcomma;
11880   int sizeflag, orig_sizeflag;
11881   const char *p;
11882   struct dis_private priv;
11883   int prefix_length;
11884
11885   priv.orig_sizeflag = AFLAG | DFLAG;
11886   if ((info->mach & bfd_mach_i386_i386) != 0)
11887     address_mode = mode_32bit;
11888   else if (info->mach == bfd_mach_i386_i8086)
11889     {
11890       address_mode = mode_16bit;
11891       priv.orig_sizeflag = 0;
11892     }
11893   else
11894     address_mode = mode_64bit;
11895
11896   if (intel_syntax == (char) -1)
11897     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11898
11899   for (p = info->disassembler_options; p != NULL; )
11900     {
11901       if (CONST_STRNEQ (p, "amd64"))
11902         isa64 = amd64;
11903       else if (CONST_STRNEQ (p, "intel64"))
11904         isa64 = intel64;
11905       else if (CONST_STRNEQ (p, "x86-64"))
11906         {
11907           address_mode = mode_64bit;
11908           priv.orig_sizeflag = AFLAG | DFLAG;
11909         }
11910       else if (CONST_STRNEQ (p, "i386"))
11911         {
11912           address_mode = mode_32bit;
11913           priv.orig_sizeflag = AFLAG | DFLAG;
11914         }
11915       else if (CONST_STRNEQ (p, "i8086"))
11916         {
11917           address_mode = mode_16bit;
11918           priv.orig_sizeflag = 0;
11919         }
11920       else if (CONST_STRNEQ (p, "intel"))
11921         {
11922           intel_syntax = 1;
11923           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11924             intel_mnemonic = 1;
11925         }
11926       else if (CONST_STRNEQ (p, "att"))
11927         {
11928           intel_syntax = 0;
11929           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11930             intel_mnemonic = 0;
11931         }
11932       else if (CONST_STRNEQ (p, "addr"))
11933         {
11934           if (address_mode == mode_64bit)
11935             {
11936               if (p[4] == '3' && p[5] == '2')
11937                 priv.orig_sizeflag &= ~AFLAG;
11938               else if (p[4] == '6' && p[5] == '4')
11939                 priv.orig_sizeflag |= AFLAG;
11940             }
11941           else
11942             {
11943               if (p[4] == '1' && p[5] == '6')
11944                 priv.orig_sizeflag &= ~AFLAG;
11945               else if (p[4] == '3' && p[5] == '2')
11946                 priv.orig_sizeflag |= AFLAG;
11947             }
11948         }
11949       else if (CONST_STRNEQ (p, "data"))
11950         {
11951           if (p[4] == '1' && p[5] == '6')
11952             priv.orig_sizeflag &= ~DFLAG;
11953           else if (p[4] == '3' && p[5] == '2')
11954             priv.orig_sizeflag |= DFLAG;
11955         }
11956       else if (CONST_STRNEQ (p, "suffix"))
11957         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11958
11959       p = strchr (p, ',');
11960       if (p != NULL)
11961         p++;
11962     }
11963
11964   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11965     {
11966       (*info->fprintf_func) (info->stream,
11967                              _("64-bit address is disabled"));
11968       return -1;
11969     }
11970
11971   if (intel_syntax)
11972     {
11973       names64 = intel_names64;
11974       names32 = intel_names32;
11975       names16 = intel_names16;
11976       names8 = intel_names8;
11977       names8rex = intel_names8rex;
11978       names_seg = intel_names_seg;
11979       names_mm = intel_names_mm;
11980       names_bnd = intel_names_bnd;
11981       names_xmm = intel_names_xmm;
11982       names_ymm = intel_names_ymm;
11983       names_zmm = intel_names_zmm;
11984       index64 = intel_index64;
11985       index32 = intel_index32;
11986       names_mask = intel_names_mask;
11987       index16 = intel_index16;
11988       open_char = '[';
11989       close_char = ']';
11990       separator_char = '+';
11991       scale_char = '*';
11992     }
11993   else
11994     {
11995       names64 = att_names64;
11996       names32 = att_names32;
11997       names16 = att_names16;
11998       names8 = att_names8;
11999       names8rex = att_names8rex;
12000       names_seg = att_names_seg;
12001       names_mm = att_names_mm;
12002       names_bnd = att_names_bnd;
12003       names_xmm = att_names_xmm;
12004       names_ymm = att_names_ymm;
12005       names_zmm = att_names_zmm;
12006       index64 = att_index64;
12007       index32 = att_index32;
12008       names_mask = att_names_mask;
12009       index16 = att_index16;
12010       open_char = '(';
12011       close_char =  ')';
12012       separator_char = ',';
12013       scale_char = ',';
12014     }
12015
12016   /* The output looks better if we put 7 bytes on a line, since that
12017      puts most long word instructions on a single line.  Use 8 bytes
12018      for Intel L1OM.  */
12019   if ((info->mach & bfd_mach_l1om) != 0)
12020     info->bytes_per_line = 8;
12021   else
12022     info->bytes_per_line = 7;
12023
12024   info->private_data = &priv;
12025   priv.max_fetched = priv.the_buffer;
12026   priv.insn_start = pc;
12027
12028   obuf[0] = 0;
12029   for (i = 0; i < MAX_OPERANDS; ++i)
12030     {
12031       op_out[i][0] = 0;
12032       op_index[i] = -1;
12033     }
12034
12035   the_info = info;
12036   start_pc = pc;
12037   start_codep = priv.the_buffer;
12038   codep = priv.the_buffer;
12039
12040   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12041     {
12042       const char *name;
12043
12044       /* Getting here means we tried for data but didn't get it.  That
12045          means we have an incomplete instruction of some sort.  Just
12046          print the first byte as a prefix or a .byte pseudo-op.  */
12047       if (codep > priv.the_buffer)
12048         {
12049           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12050           if (name != NULL)
12051             (*info->fprintf_func) (info->stream, "%s", name);
12052           else
12053             {
12054               /* Just print the first byte as a .byte instruction.  */
12055               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12056                                      (unsigned int) priv.the_buffer[0]);
12057             }
12058
12059           return 1;
12060         }
12061
12062       return -1;
12063     }
12064
12065   obufp = obuf;
12066   sizeflag = priv.orig_sizeflag;
12067
12068   if (!ckprefix () || rex_used)
12069     {
12070       /* Too many prefixes or unused REX prefixes.  */
12071       for (i = 0;
12072            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12073            i++)
12074         (*info->fprintf_func) (info->stream, "%s%s",
12075                                i == 0 ? "" : " ",
12076                                prefix_name (all_prefixes[i], sizeflag));
12077       return i;
12078     }
12079
12080   insn_codep = codep;
12081
12082   FETCH_DATA (info, codep + 1);
12083   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12084
12085   if (((prefixes & PREFIX_FWAIT)
12086        && ((*codep < 0xd8) || (*codep > 0xdf))))
12087     {
12088       /* Handle prefixes before fwait.  */
12089       for (i = 0; i < fwait_prefix && all_prefixes[i];
12090            i++)
12091         (*info->fprintf_func) (info->stream, "%s ",
12092                                prefix_name (all_prefixes[i], sizeflag));
12093       (*info->fprintf_func) (info->stream, "fwait");
12094       return i + 1;
12095     }
12096
12097   if (*codep == 0x0f)
12098     {
12099       unsigned char threebyte;
12100
12101       codep++;
12102       FETCH_DATA (info, codep + 1);
12103       threebyte = *codep;
12104       dp = &dis386_twobyte[threebyte];
12105       need_modrm = twobyte_has_modrm[*codep];
12106       codep++;
12107     }
12108   else
12109     {
12110       dp = &dis386[*codep];
12111       need_modrm = onebyte_has_modrm[*codep];
12112       codep++;
12113     }
12114
12115   /* Save sizeflag for printing the extra prefixes later before updating
12116      it for mnemonic and operand processing.  The prefix names depend
12117      only on the address mode.  */
12118   orig_sizeflag = sizeflag;
12119   if (prefixes & PREFIX_ADDR)
12120     sizeflag ^= AFLAG;
12121   if ((prefixes & PREFIX_DATA))
12122     sizeflag ^= DFLAG;
12123
12124   end_codep = codep;
12125   if (need_modrm)
12126     {
12127       FETCH_DATA (info, codep + 1);
12128       modrm.mod = (*codep >> 6) & 3;
12129       modrm.reg = (*codep >> 3) & 7;
12130       modrm.rm = *codep & 7;
12131     }
12132
12133   need_vex = 0;
12134   need_vex_reg = 0;
12135   vex_w_done = 0;
12136   memset (&vex, 0, sizeof (vex));
12137
12138   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12139     {
12140       get_sib (info, sizeflag);
12141       dofloat (sizeflag);
12142     }
12143   else
12144     {
12145       dp = get_valid_dis386 (dp, info);
12146       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12147         {
12148           get_sib (info, sizeflag);
12149           for (i = 0; i < MAX_OPERANDS; ++i)
12150             {
12151               obufp = op_out[i];
12152               op_ad = MAX_OPERANDS - 1 - i;
12153               if (dp->op[i].rtn)
12154                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12155               /* For EVEX instruction after the last operand masking
12156                  should be printed.  */
12157               if (i == 0 && vex.evex)
12158                 {
12159                   /* Don't print {%k0}.  */
12160                   if (vex.mask_register_specifier)
12161                     {
12162                       oappend ("{");
12163                       oappend (names_mask[vex.mask_register_specifier]);
12164                       oappend ("}");
12165                     }
12166                   if (vex.zeroing)
12167                     oappend ("{z}");
12168                 }
12169             }
12170         }
12171     }
12172
12173   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12174      are all 0s in inverted form.  */
12175   if (need_vex && vex.register_specifier != 0)
12176     {
12177       (*info->fprintf_func) (info->stream, "(bad)");
12178       return end_codep - priv.the_buffer;
12179     }
12180
12181   /* Check if the REX prefix is used.  */
12182   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12183     all_prefixes[last_rex_prefix] = 0;
12184
12185   /* Check if the SEG prefix is used.  */
12186   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12187                    | PREFIX_FS | PREFIX_GS)) != 0
12188       && (used_prefixes & active_seg_prefix) != 0)
12189     all_prefixes[last_seg_prefix] = 0;
12190
12191   /* Check if the ADDR prefix is used.  */
12192   if ((prefixes & PREFIX_ADDR) != 0
12193       && (used_prefixes & PREFIX_ADDR) != 0)
12194     all_prefixes[last_addr_prefix] = 0;
12195
12196   /* Check if the DATA prefix is used.  */
12197   if ((prefixes & PREFIX_DATA) != 0
12198       && (used_prefixes & PREFIX_DATA) != 0)
12199     all_prefixes[last_data_prefix] = 0;
12200
12201   /* Print the extra prefixes.  */
12202   prefix_length = 0;
12203   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12204     if (all_prefixes[i])
12205       {
12206         const char *name;
12207         name = prefix_name (all_prefixes[i], orig_sizeflag);
12208         if (name == NULL)
12209           abort ();
12210         prefix_length += strlen (name) + 1;
12211         (*info->fprintf_func) (info->stream, "%s ", name);
12212       }
12213
12214   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12215      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12216      used by putop and MMX/SSE operand and may be overriden by the
12217      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12218      separately.  */
12219   if (dp->prefix_requirement == PREFIX_OPCODE
12220       && dp != &bad_opcode
12221       && (((prefixes
12222             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12223            && (used_prefixes
12224                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12225           || ((((prefixes
12226                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12227                 == PREFIX_DATA)
12228                && (used_prefixes & PREFIX_DATA) == 0))))
12229     {
12230       (*info->fprintf_func) (info->stream, "(bad)");
12231       return end_codep - priv.the_buffer;
12232     }
12233
12234   /* Check maximum code length.  */
12235   if ((codep - start_codep) > MAX_CODE_LENGTH)
12236     {
12237       (*info->fprintf_func) (info->stream, "(bad)");
12238       return MAX_CODE_LENGTH;
12239     }
12240
12241   obufp = mnemonicendp;
12242   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12243     oappend (" ");
12244   oappend (" ");
12245   (*info->fprintf_func) (info->stream, "%s", obuf);
12246
12247   /* The enter and bound instructions are printed with operands in the same
12248      order as the intel book; everything else is printed in reverse order.  */
12249   if (intel_syntax || two_source_ops)
12250     {
12251       bfd_vma riprel;
12252
12253       for (i = 0; i < MAX_OPERANDS; ++i)
12254         op_txt[i] = op_out[i];
12255
12256       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12257           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12258         {
12259           op_txt[2] = op_out[3];
12260           op_txt[3] = op_out[2];
12261         }
12262
12263       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12264         {
12265           op_ad = op_index[i];
12266           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12267           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12268           riprel = op_riprel[i];
12269           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12270           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12271         }
12272     }
12273   else
12274     {
12275       for (i = 0; i < MAX_OPERANDS; ++i)
12276         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12277     }
12278
12279   needcomma = 0;
12280   for (i = 0; i < MAX_OPERANDS; ++i)
12281     if (*op_txt[i])
12282       {
12283         if (needcomma)
12284           (*info->fprintf_func) (info->stream, ",");
12285         if (op_index[i] != -1 && !op_riprel[i])
12286           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12287         else
12288           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12289         needcomma = 1;
12290       }
12291
12292   for (i = 0; i < MAX_OPERANDS; i++)
12293     if (op_index[i] != -1 && op_riprel[i])
12294       {
12295         (*info->fprintf_func) (info->stream, "        # ");
12296         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12297                                                 + op_address[op_index[i]]), info);
12298         break;
12299       }
12300   return codep - priv.the_buffer;
12301 }
12302
12303 static const char *float_mem[] = {
12304   /* d8 */
12305   "fadd{s|}",
12306   "fmul{s|}",
12307   "fcom{s|}",
12308   "fcomp{s|}",
12309   "fsub{s|}",
12310   "fsubr{s|}",
12311   "fdiv{s|}",
12312   "fdivr{s|}",
12313   /* d9 */
12314   "fld{s|}",
12315   "(bad)",
12316   "fst{s|}",
12317   "fstp{s|}",
12318   "fldenvIC",
12319   "fldcw",
12320   "fNstenvIC",
12321   "fNstcw",
12322   /* da */
12323   "fiadd{l|}",
12324   "fimul{l|}",
12325   "ficom{l|}",
12326   "ficomp{l|}",
12327   "fisub{l|}",
12328   "fisubr{l|}",
12329   "fidiv{l|}",
12330   "fidivr{l|}",
12331   /* db */
12332   "fild{l|}",
12333   "fisttp{l|}",
12334   "fist{l|}",
12335   "fistp{l|}",
12336   "(bad)",
12337   "fld{t||t|}",
12338   "(bad)",
12339   "fstp{t||t|}",
12340   /* dc */
12341   "fadd{l|}",
12342   "fmul{l|}",
12343   "fcom{l|}",
12344   "fcomp{l|}",
12345   "fsub{l|}",
12346   "fsubr{l|}",
12347   "fdiv{l|}",
12348   "fdivr{l|}",
12349   /* dd */
12350   "fld{l|}",
12351   "fisttp{ll|}",
12352   "fst{l||}",
12353   "fstp{l|}",
12354   "frstorIC",
12355   "(bad)",
12356   "fNsaveIC",
12357   "fNstsw",
12358   /* de */
12359   "fiadd{s|}",
12360   "fimul{s|}",
12361   "ficom{s|}",
12362   "ficomp{s|}",
12363   "fisub{s|}",
12364   "fisubr{s|}",
12365   "fidiv{s|}",
12366   "fidivr{s|}",
12367   /* df */
12368   "fild{s|}",
12369   "fisttp{s|}",
12370   "fist{s|}",
12371   "fistp{s|}",
12372   "fbld",
12373   "fild{ll|}",
12374   "fbstp",
12375   "fistp{ll|}",
12376 };
12377
12378 static const unsigned char float_mem_mode[] = {
12379   /* d8 */
12380   d_mode,
12381   d_mode,
12382   d_mode,
12383   d_mode,
12384   d_mode,
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   /* d9 */
12389   d_mode,
12390   0,
12391   d_mode,
12392   d_mode,
12393   0,
12394   w_mode,
12395   0,
12396   w_mode,
12397   /* da */
12398   d_mode,
12399   d_mode,
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   d_mode,
12404   d_mode,
12405   d_mode,
12406   /* db */
12407   d_mode,
12408   d_mode,
12409   d_mode,
12410   d_mode,
12411   0,
12412   t_mode,
12413   0,
12414   t_mode,
12415   /* dc */
12416   q_mode,
12417   q_mode,
12418   q_mode,
12419   q_mode,
12420   q_mode,
12421   q_mode,
12422   q_mode,
12423   q_mode,
12424   /* dd */
12425   q_mode,
12426   q_mode,
12427   q_mode,
12428   q_mode,
12429   0,
12430   0,
12431   0,
12432   w_mode,
12433   /* de */
12434   w_mode,
12435   w_mode,
12436   w_mode,
12437   w_mode,
12438   w_mode,
12439   w_mode,
12440   w_mode,
12441   w_mode,
12442   /* df */
12443   w_mode,
12444   w_mode,
12445   w_mode,
12446   w_mode,
12447   t_mode,
12448   q_mode,
12449   t_mode,
12450   q_mode
12451 };
12452
12453 #define ST { OP_ST, 0 }
12454 #define STi { OP_STi, 0 }
12455
12456 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12457 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12458 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12459 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12460 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12461 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12462 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12463 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12464 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12465
12466 static const struct dis386 float_reg[][8] = {
12467   /* d8 */
12468   {
12469     { "fadd",   { ST, STi }, 0 },
12470     { "fmul",   { ST, STi }, 0 },
12471     { "fcom",   { STi }, 0 },
12472     { "fcomp",  { STi }, 0 },
12473     { "fsub",   { ST, STi }, 0 },
12474     { "fsubr",  { ST, STi }, 0 },
12475     { "fdiv",   { ST, STi }, 0 },
12476     { "fdivr",  { ST, STi }, 0 },
12477   },
12478   /* d9 */
12479   {
12480     { "fld",    { STi }, 0 },
12481     { "fxch",   { STi }, 0 },
12482     { FGRPd9_2 },
12483     { Bad_Opcode },
12484     { FGRPd9_4 },
12485     { FGRPd9_5 },
12486     { FGRPd9_6 },
12487     { FGRPd9_7 },
12488   },
12489   /* da */
12490   {
12491     { "fcmovb", { ST, STi }, 0 },
12492     { "fcmove", { ST, STi }, 0 },
12493     { "fcmovbe",{ ST, STi }, 0 },
12494     { "fcmovu", { ST, STi }, 0 },
12495     { Bad_Opcode },
12496     { FGRPda_5 },
12497     { Bad_Opcode },
12498     { Bad_Opcode },
12499   },
12500   /* db */
12501   {
12502     { "fcmovnb",{ ST, STi }, 0 },
12503     { "fcmovne",{ ST, STi }, 0 },
12504     { "fcmovnbe",{ ST, STi }, 0 },
12505     { "fcmovnu",{ ST, STi }, 0 },
12506     { FGRPdb_4 },
12507     { "fucomi", { ST, STi }, 0 },
12508     { "fcomi",  { ST, STi }, 0 },
12509     { Bad_Opcode },
12510   },
12511   /* dc */
12512   {
12513     { "fadd",   { STi, ST }, 0 },
12514     { "fmul",   { STi, ST }, 0 },
12515     { Bad_Opcode },
12516     { Bad_Opcode },
12517     { "fsub{!M|r}",     { STi, ST }, 0 },
12518     { "fsub{M|}",       { STi, ST }, 0 },
12519     { "fdiv{!M|r}",     { STi, ST }, 0 },
12520     { "fdiv{M|}",       { STi, ST }, 0 },
12521   },
12522   /* dd */
12523   {
12524     { "ffree",  { STi }, 0 },
12525     { Bad_Opcode },
12526     { "fst",    { STi }, 0 },
12527     { "fstp",   { STi }, 0 },
12528     { "fucom",  { STi }, 0 },
12529     { "fucomp", { STi }, 0 },
12530     { Bad_Opcode },
12531     { Bad_Opcode },
12532   },
12533   /* de */
12534   {
12535     { "faddp",  { STi, ST }, 0 },
12536     { "fmulp",  { STi, ST }, 0 },
12537     { Bad_Opcode },
12538     { FGRPde_3 },
12539     { "fsub{!M|r}p",    { STi, ST }, 0 },
12540     { "fsub{M|}p",      { STi, ST }, 0 },
12541     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12542     { "fdiv{M|}p",      { STi, ST }, 0 },
12543   },
12544   /* df */
12545   {
12546     { "ffreep", { STi }, 0 },
12547     { Bad_Opcode },
12548     { Bad_Opcode },
12549     { Bad_Opcode },
12550     { FGRPdf_4 },
12551     { "fucomip", { ST, STi }, 0 },
12552     { "fcomip", { ST, STi }, 0 },
12553     { Bad_Opcode },
12554   },
12555 };
12556
12557 static char *fgrps[][8] = {
12558   /* Bad opcode 0 */
12559   {
12560     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12561   },
12562
12563   /* d9_2  1 */
12564   {
12565     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12566   },
12567
12568   /* d9_4  2 */
12569   {
12570     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12571   },
12572
12573   /* d9_5  3 */
12574   {
12575     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12576   },
12577
12578   /* d9_6  4 */
12579   {
12580     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12581   },
12582
12583   /* d9_7  5 */
12584   {
12585     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12586   },
12587
12588   /* da_5  6 */
12589   {
12590     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12591   },
12592
12593   /* db_4  7 */
12594   {
12595     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12596     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12597   },
12598
12599   /* de_3  8 */
12600   {
12601     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12602   },
12603
12604   /* df_4  9 */
12605   {
12606     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12607   },
12608 };
12609
12610 static void
12611 swap_operand (void)
12612 {
12613   mnemonicendp[0] = '.';
12614   mnemonicendp[1] = 's';
12615   mnemonicendp += 2;
12616 }
12617
12618 static void
12619 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12620                int sizeflag ATTRIBUTE_UNUSED)
12621 {
12622   /* Skip mod/rm byte.  */
12623   MODRM_CHECK;
12624   codep++;
12625 }
12626
12627 static void
12628 dofloat (int sizeflag)
12629 {
12630   const struct dis386 *dp;
12631   unsigned char floatop;
12632
12633   floatop = codep[-1];
12634
12635   if (modrm.mod != 3)
12636     {
12637       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12638
12639       putop (float_mem[fp_indx], sizeflag);
12640       obufp = op_out[0];
12641       op_ad = 2;
12642       OP_E (float_mem_mode[fp_indx], sizeflag);
12643       return;
12644     }
12645   /* Skip mod/rm byte.  */
12646   MODRM_CHECK;
12647   codep++;
12648
12649   dp = &float_reg[floatop - 0xd8][modrm.reg];
12650   if (dp->name == NULL)
12651     {
12652       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12653
12654       /* Instruction fnstsw is only one with strange arg.  */
12655       if (floatop == 0xdf && codep[-1] == 0xe0)
12656         strcpy (op_out[0], names16[0]);
12657     }
12658   else
12659     {
12660       putop (dp->name, sizeflag);
12661
12662       obufp = op_out[0];
12663       op_ad = 2;
12664       if (dp->op[0].rtn)
12665         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12666
12667       obufp = op_out[1];
12668       op_ad = 1;
12669       if (dp->op[1].rtn)
12670         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12671     }
12672 }
12673
12674 /* Like oappend (below), but S is a string starting with '%'.
12675    In Intel syntax, the '%' is elided.  */
12676 static void
12677 oappend_maybe_intel (const char *s)
12678 {
12679   oappend (s + intel_syntax);
12680 }
12681
12682 static void
12683 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12684 {
12685   oappend_maybe_intel ("%st");
12686 }
12687
12688 static void
12689 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12690 {
12691   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12692   oappend_maybe_intel (scratchbuf);
12693 }
12694
12695 /* Capital letters in template are macros.  */
12696 static int
12697 putop (const char *in_template, int sizeflag)
12698 {
12699   const char *p;
12700   int alt = 0;
12701   int cond = 1;
12702   unsigned int l = 0, len = 1;
12703   char last[4];
12704
12705 #define SAVE_LAST(c)                    \
12706   if (l < len && l < sizeof (last))     \
12707     last[l++] = c;                      \
12708   else                                  \
12709     abort ();
12710
12711   for (p = in_template; *p; p++)
12712     {
12713       switch (*p)
12714         {
12715         default:
12716           *obufp++ = *p;
12717           break;
12718         case '%':
12719           len++;
12720           break;
12721         case '!':
12722           cond = 0;
12723           break;
12724         case '{':
12725           if (intel_syntax)
12726             {
12727               while (*++p != '|')
12728                 if (*p == '}' || *p == '\0')
12729                   abort ();
12730             }
12731           /* Fall through.  */
12732         case 'I':
12733           alt = 1;
12734           continue;
12735         case '|':
12736           while (*++p != '}')
12737             {
12738               if (*p == '\0')
12739                 abort ();
12740             }
12741           break;
12742         case '}':
12743           break;
12744         case 'A':
12745           if (intel_syntax)
12746             break;
12747           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12748             *obufp++ = 'b';
12749           break;
12750         case 'B':
12751           if (l == 0 && len == 1)
12752             {
12753 case_B:
12754               if (intel_syntax)
12755                 break;
12756               if (sizeflag & SUFFIX_ALWAYS)
12757                 *obufp++ = 'b';
12758             }
12759           else
12760             {
12761               if (l != 1
12762                   || len != 2
12763                   || last[0] != 'L')
12764                 {
12765                   SAVE_LAST (*p);
12766                   break;
12767                 }
12768
12769               if (address_mode == mode_64bit
12770                   && !(prefixes & PREFIX_ADDR))
12771                 {
12772                   *obufp++ = 'a';
12773                   *obufp++ = 'b';
12774                   *obufp++ = 's';
12775                 }
12776
12777               goto case_B;
12778             }
12779           break;
12780         case 'C':
12781           if (intel_syntax && !alt)
12782             break;
12783           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12784             {
12785               if (sizeflag & DFLAG)
12786                 *obufp++ = intel_syntax ? 'd' : 'l';
12787               else
12788                 *obufp++ = intel_syntax ? 'w' : 's';
12789               used_prefixes |= (prefixes & PREFIX_DATA);
12790             }
12791           break;
12792         case 'D':
12793           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12794             break;
12795           USED_REX (REX_W);
12796           if (modrm.mod == 3)
12797             {
12798               if (rex & REX_W)
12799                 *obufp++ = 'q';
12800               else
12801                 {
12802                   if (sizeflag & DFLAG)
12803                     *obufp++ = intel_syntax ? 'd' : 'l';
12804                   else
12805                     *obufp++ = 'w';
12806                   used_prefixes |= (prefixes & PREFIX_DATA);
12807                 }
12808             }
12809           else
12810             *obufp++ = 'w';
12811           break;
12812         case 'E':               /* For jcxz/jecxz */
12813           if (address_mode == mode_64bit)
12814             {
12815               if (sizeflag & AFLAG)
12816                 *obufp++ = 'r';
12817               else
12818                 *obufp++ = 'e';
12819             }
12820           else
12821             if (sizeflag & AFLAG)
12822               *obufp++ = 'e';
12823           used_prefixes |= (prefixes & PREFIX_ADDR);
12824           break;
12825         case 'F':
12826           if (intel_syntax)
12827             break;
12828           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12829             {
12830               if (sizeflag & AFLAG)
12831                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12832               else
12833                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12834               used_prefixes |= (prefixes & PREFIX_ADDR);
12835             }
12836           break;
12837         case 'G':
12838           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12839             break;
12840           if ((rex & REX_W) || (sizeflag & DFLAG))
12841             *obufp++ = 'l';
12842           else
12843             *obufp++ = 'w';
12844           if (!(rex & REX_W))
12845             used_prefixes |= (prefixes & PREFIX_DATA);
12846           break;
12847         case 'H':
12848           if (intel_syntax)
12849             break;
12850           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12851               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12852             {
12853               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12854               *obufp++ = ',';
12855               *obufp++ = 'p';
12856               if (prefixes & PREFIX_DS)
12857                 *obufp++ = 't';
12858               else
12859                 *obufp++ = 'n';
12860             }
12861           break;
12862         case 'J':
12863           if (intel_syntax)
12864             break;
12865           *obufp++ = 'l';
12866           break;
12867         case 'K':
12868           USED_REX (REX_W);
12869           if (rex & REX_W)
12870             *obufp++ = 'q';
12871           else
12872             *obufp++ = 'd';
12873           break;
12874         case 'Z':
12875           if (l != 0 || len != 1)
12876             {
12877               if (l != 1 || len != 2 || last[0] != 'X')
12878                 {
12879                   SAVE_LAST (*p);
12880                   break;
12881                 }
12882               if (!need_vex || !vex.evex)
12883                 abort ();
12884               if (intel_syntax
12885                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12886                 break;
12887               switch (vex.length)
12888                 {
12889                 case 128:
12890                   *obufp++ = 'x';
12891                   break;
12892                 case 256:
12893                   *obufp++ = 'y';
12894                   break;
12895                 case 512:
12896                   *obufp++ = 'z';
12897                   break;
12898                 default:
12899                   abort ();
12900                 }
12901               break;
12902             }
12903           if (intel_syntax)
12904             break;
12905           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12906             {
12907               *obufp++ = 'q';
12908               break;
12909             }
12910           /* Fall through.  */
12911           goto case_L;
12912         case 'L':
12913           if (l != 0 || len != 1)
12914             {
12915               SAVE_LAST (*p);
12916               break;
12917             }
12918 case_L:
12919           if (intel_syntax)
12920             break;
12921           if (sizeflag & SUFFIX_ALWAYS)
12922             *obufp++ = 'l';
12923           break;
12924         case 'M':
12925           if (intel_mnemonic != cond)
12926             *obufp++ = 'r';
12927           break;
12928         case 'N':
12929           if ((prefixes & PREFIX_FWAIT) == 0)
12930             *obufp++ = 'n';
12931           else
12932             used_prefixes |= PREFIX_FWAIT;
12933           break;
12934         case 'O':
12935           USED_REX (REX_W);
12936           if (rex & REX_W)
12937             *obufp++ = 'o';
12938           else if (intel_syntax && (sizeflag & DFLAG))
12939             *obufp++ = 'q';
12940           else
12941             *obufp++ = 'd';
12942           if (!(rex & REX_W))
12943             used_prefixes |= (prefixes & PREFIX_DATA);
12944           break;
12945         case '&':
12946           if (!intel_syntax
12947               && address_mode == mode_64bit
12948               && isa64 == intel64)
12949             {
12950               *obufp++ = 'q';
12951               break;
12952             }
12953           /* Fall through.  */
12954         case 'T':
12955           if (!intel_syntax
12956               && address_mode == mode_64bit
12957               && ((sizeflag & DFLAG) || (rex & REX_W)))
12958             {
12959               *obufp++ = 'q';
12960               break;
12961             }
12962           /* Fall through.  */
12963           goto case_P;
12964         case 'P':
12965           if (l == 0 && len == 1)
12966             {
12967 case_P:
12968               if (intel_syntax)
12969                 {
12970                   if ((rex & REX_W) == 0
12971                       && (prefixes & PREFIX_DATA))
12972                     {
12973                       if ((sizeflag & DFLAG) == 0)
12974                         *obufp++ = 'w';
12975                       used_prefixes |= (prefixes & PREFIX_DATA);
12976                     }
12977                   break;
12978                 }
12979               if ((prefixes & PREFIX_DATA)
12980                   || (rex & REX_W)
12981                   || (sizeflag & SUFFIX_ALWAYS))
12982                 {
12983                   USED_REX (REX_W);
12984                   if (rex & REX_W)
12985                     *obufp++ = 'q';
12986                   else
12987                     {
12988                       if (sizeflag & DFLAG)
12989                         *obufp++ = 'l';
12990                       else
12991                         *obufp++ = 'w';
12992                       used_prefixes |= (prefixes & PREFIX_DATA);
12993                     }
12994                 }
12995             }
12996           else
12997             {
12998               if (l != 1 || len != 2 || last[0] != 'L')
12999                 {
13000                   SAVE_LAST (*p);
13001                   break;
13002                 }
13003
13004               if ((prefixes & PREFIX_DATA)
13005                   || (rex & REX_W)
13006                   || (sizeflag & SUFFIX_ALWAYS))
13007                 {
13008                   USED_REX (REX_W);
13009                   if (rex & REX_W)
13010                     *obufp++ = 'q';
13011                   else
13012                     {
13013                       if (sizeflag & DFLAG)
13014                         *obufp++ = intel_syntax ? 'd' : 'l';
13015                       else
13016                         *obufp++ = 'w';
13017                       used_prefixes |= (prefixes & PREFIX_DATA);
13018                     }
13019                 }
13020             }
13021           break;
13022         case 'U':
13023           if (intel_syntax)
13024             break;
13025           if (address_mode == mode_64bit
13026               && ((sizeflag & DFLAG) || (rex & REX_W)))
13027             {
13028               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13029                 *obufp++ = 'q';
13030               break;
13031             }
13032           /* Fall through.  */
13033           goto case_Q;
13034         case 'Q':
13035           if (l == 0 && len == 1)
13036             {
13037 case_Q:
13038               if (intel_syntax && !alt)
13039                 break;
13040               USED_REX (REX_W);
13041               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13042                 {
13043                   if (rex & REX_W)
13044                     *obufp++ = 'q';
13045                   else
13046                     {
13047                       if (sizeflag & DFLAG)
13048                         *obufp++ = intel_syntax ? 'd' : 'l';
13049                       else
13050                         *obufp++ = 'w';
13051                       used_prefixes |= (prefixes & PREFIX_DATA);
13052                     }
13053                 }
13054             }
13055           else
13056             {
13057               if (l != 1 || len != 2 || last[0] != 'L')
13058                 {
13059                   SAVE_LAST (*p);
13060                   break;
13061                 }
13062               if (intel_syntax
13063                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13064                 break;
13065               if ((rex & REX_W))
13066                 {
13067                   USED_REX (REX_W);
13068                   *obufp++ = 'q';
13069                 }
13070               else
13071                 *obufp++ = 'l';
13072             }
13073           break;
13074         case 'R':
13075           USED_REX (REX_W);
13076           if (rex & REX_W)
13077             *obufp++ = 'q';
13078           else if (sizeflag & DFLAG)
13079             {
13080               if (intel_syntax)
13081                   *obufp++ = 'd';
13082               else
13083                   *obufp++ = 'l';
13084             }
13085           else
13086             *obufp++ = 'w';
13087           if (intel_syntax && !p[1]
13088               && ((rex & REX_W) || (sizeflag & DFLAG)))
13089             *obufp++ = 'e';
13090           if (!(rex & REX_W))
13091             used_prefixes |= (prefixes & PREFIX_DATA);
13092           break;
13093         case 'V':
13094           if (l == 0 && len == 1)
13095             {
13096               if (intel_syntax)
13097                 break;
13098               if (address_mode == mode_64bit
13099                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13100                 {
13101                   if (sizeflag & SUFFIX_ALWAYS)
13102                     *obufp++ = 'q';
13103                   break;
13104                 }
13105             }
13106           else
13107             {
13108               if (l != 1
13109                   || len != 2
13110                   || last[0] != 'L')
13111                 {
13112                   SAVE_LAST (*p);
13113                   break;
13114                 }
13115
13116               if (rex & REX_W)
13117                 {
13118                   *obufp++ = 'a';
13119                   *obufp++ = 'b';
13120                   *obufp++ = 's';
13121                 }
13122             }
13123           /* Fall through.  */
13124           goto case_S;
13125         case 'S':
13126           if (l == 0 && len == 1)
13127             {
13128 case_S:
13129               if (intel_syntax)
13130                 break;
13131               if (sizeflag & SUFFIX_ALWAYS)
13132                 {
13133                   if (rex & REX_W)
13134                     *obufp++ = 'q';
13135                   else
13136                     {
13137                       if (sizeflag & DFLAG)
13138                         *obufp++ = 'l';
13139                       else
13140                         *obufp++ = 'w';
13141                       used_prefixes |= (prefixes & PREFIX_DATA);
13142                     }
13143                 }
13144             }
13145           else
13146             {
13147               if (l != 1
13148                   || len != 2
13149                   || last[0] != 'L')
13150                 {
13151                   SAVE_LAST (*p);
13152                   break;
13153                 }
13154
13155               if (address_mode == mode_64bit
13156                   && !(prefixes & PREFIX_ADDR))
13157                 {
13158                   *obufp++ = 'a';
13159                   *obufp++ = 'b';
13160                   *obufp++ = 's';
13161                 }
13162
13163               goto case_S;
13164             }
13165           break;
13166         case 'X':
13167           if (l != 0 || len != 1)
13168             {
13169               SAVE_LAST (*p);
13170               break;
13171             }
13172           if (need_vex && vex.prefix)
13173             {
13174               if (vex.prefix == DATA_PREFIX_OPCODE)
13175                 *obufp++ = 'd';
13176               else
13177                 *obufp++ = 's';
13178             }
13179           else
13180             {
13181               if (prefixes & PREFIX_DATA)
13182                 *obufp++ = 'd';
13183               else
13184                 *obufp++ = 's';
13185               used_prefixes |= (prefixes & PREFIX_DATA);
13186             }
13187           break;
13188         case 'Y':
13189           if (l == 0 && len == 1)
13190             abort ();
13191           else
13192             {
13193               if (l != 1 || len != 2 || last[0] != 'X')
13194                 {
13195                   SAVE_LAST (*p);
13196                   break;
13197                 }
13198               if (!need_vex)
13199                 abort ();
13200               if (intel_syntax
13201                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13202                 break;
13203               switch (vex.length)
13204                 {
13205                 case 128:
13206                   *obufp++ = 'x';
13207                   break;
13208                 case 256:
13209                   *obufp++ = 'y';
13210                   break;
13211                 case 512:
13212                   if (!vex.evex)
13213                 default:
13214                     abort ();
13215                 }
13216             }
13217           break;
13218         case 'W':
13219           if (l == 0 && len == 1)
13220             {
13221               /* operand size flag for cwtl, cbtw */
13222               USED_REX (REX_W);
13223               if (rex & REX_W)
13224                 {
13225                   if (intel_syntax)
13226                     *obufp++ = 'd';
13227                   else
13228                     *obufp++ = 'l';
13229                 }
13230               else if (sizeflag & DFLAG)
13231                 *obufp++ = 'w';
13232               else
13233                 *obufp++ = 'b';
13234               if (!(rex & REX_W))
13235                 used_prefixes |= (prefixes & PREFIX_DATA);
13236             }
13237           else
13238             {
13239               if (l != 1
13240                   || len != 2
13241                   || (last[0] != 'X'
13242                       && last[0] != 'L'))
13243                 {
13244                   SAVE_LAST (*p);
13245                   break;
13246                 }
13247               if (!need_vex)
13248                 abort ();
13249               if (last[0] == 'X')
13250                 *obufp++ = vex.w ? 'd': 's';
13251               else
13252                 *obufp++ = vex.w ? 'q': 'd';
13253             }
13254           break;
13255         case '^':
13256           if (intel_syntax)
13257             break;
13258           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13259             {
13260               if (sizeflag & DFLAG)
13261                 *obufp++ = 'l';
13262               else
13263                 *obufp++ = 'w';
13264               used_prefixes |= (prefixes & PREFIX_DATA);
13265             }
13266           break;
13267         case '@':
13268           if (intel_syntax)
13269             break;
13270           if (address_mode == mode_64bit
13271               && (isa64 == intel64
13272                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13273               *obufp++ = 'q';
13274           else if ((prefixes & PREFIX_DATA))
13275             {
13276               if (!(sizeflag & DFLAG))
13277                 *obufp++ = 'w';
13278               used_prefixes |= (prefixes & PREFIX_DATA);
13279             }
13280           break;
13281         }
13282       alt = 0;
13283     }
13284   *obufp = 0;
13285   mnemonicendp = obufp;
13286   return 0;
13287 }
13288
13289 static void
13290 oappend (const char *s)
13291 {
13292   obufp = stpcpy (obufp, s);
13293 }
13294
13295 static void
13296 append_seg (void)
13297 {
13298   /* Only print the active segment register.  */
13299   if (!active_seg_prefix)
13300     return;
13301
13302   used_prefixes |= active_seg_prefix;
13303   switch (active_seg_prefix)
13304     {
13305     case PREFIX_CS:
13306       oappend_maybe_intel ("%cs:");
13307       break;
13308     case PREFIX_DS:
13309       oappend_maybe_intel ("%ds:");
13310       break;
13311     case PREFIX_SS:
13312       oappend_maybe_intel ("%ss:");
13313       break;
13314     case PREFIX_ES:
13315       oappend_maybe_intel ("%es:");
13316       break;
13317     case PREFIX_FS:
13318       oappend_maybe_intel ("%fs:");
13319       break;
13320     case PREFIX_GS:
13321       oappend_maybe_intel ("%gs:");
13322       break;
13323     default:
13324       break;
13325     }
13326 }
13327
13328 static void
13329 OP_indirE (int bytemode, int sizeflag)
13330 {
13331   if (!intel_syntax)
13332     oappend ("*");
13333   OP_E (bytemode, sizeflag);
13334 }
13335
13336 static void
13337 print_operand_value (char *buf, int hex, bfd_vma disp)
13338 {
13339   if (address_mode == mode_64bit)
13340     {
13341       if (hex)
13342         {
13343           char tmp[30];
13344           int i;
13345           buf[0] = '0';
13346           buf[1] = 'x';
13347           sprintf_vma (tmp, disp);
13348           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13349           strcpy (buf + 2, tmp + i);
13350         }
13351       else
13352         {
13353           bfd_signed_vma v = disp;
13354           char tmp[30];
13355           int i;
13356           if (v < 0)
13357             {
13358               *(buf++) = '-';
13359               v = -disp;
13360               /* Check for possible overflow on 0x8000000000000000.  */
13361               if (v < 0)
13362                 {
13363                   strcpy (buf, "9223372036854775808");
13364                   return;
13365                 }
13366             }
13367           if (!v)
13368             {
13369               strcpy (buf, "0");
13370               return;
13371             }
13372
13373           i = 0;
13374           tmp[29] = 0;
13375           while (v)
13376             {
13377               tmp[28 - i] = (v % 10) + '0';
13378               v /= 10;
13379               i++;
13380             }
13381           strcpy (buf, tmp + 29 - i);
13382         }
13383     }
13384   else
13385     {
13386       if (hex)
13387         sprintf (buf, "0x%x", (unsigned int) disp);
13388       else
13389         sprintf (buf, "%d", (int) disp);
13390     }
13391 }
13392
13393 /* Put DISP in BUF as signed hex number.  */
13394
13395 static void
13396 print_displacement (char *buf, bfd_vma disp)
13397 {
13398   bfd_signed_vma val = disp;
13399   char tmp[30];
13400   int i, j = 0;
13401
13402   if (val < 0)
13403     {
13404       buf[j++] = '-';
13405       val = -disp;
13406
13407       /* Check for possible overflow.  */
13408       if (val < 0)
13409         {
13410           switch (address_mode)
13411             {
13412             case mode_64bit:
13413               strcpy (buf + j, "0x8000000000000000");
13414               break;
13415             case mode_32bit:
13416               strcpy (buf + j, "0x80000000");
13417               break;
13418             case mode_16bit:
13419               strcpy (buf + j, "0x8000");
13420               break;
13421             }
13422           return;
13423         }
13424     }
13425
13426   buf[j++] = '0';
13427   buf[j++] = 'x';
13428
13429   sprintf_vma (tmp, (bfd_vma) val);
13430   for (i = 0; tmp[i] == '0'; i++)
13431     continue;
13432   if (tmp[i] == '\0')
13433     i--;
13434   strcpy (buf + j, tmp + i);
13435 }
13436
13437 static void
13438 intel_operand_size (int bytemode, int sizeflag)
13439 {
13440   if (vex.evex
13441       && vex.b
13442       && (bytemode == x_mode
13443           || bytemode == evex_half_bcst_xmmq_mode))
13444     {
13445       if (vex.w)
13446         oappend ("QWORD PTR ");
13447       else
13448         oappend ("DWORD PTR ");
13449       return;
13450     }
13451   switch (bytemode)
13452     {
13453     case b_mode:
13454     case b_swap_mode:
13455     case dqb_mode:
13456     case db_mode:
13457       oappend ("BYTE PTR ");
13458       break;
13459     case w_mode:
13460     case dw_mode:
13461     case dqw_mode:
13462       oappend ("WORD PTR ");
13463       break;
13464     case indir_v_mode:
13465       if (address_mode == mode_64bit && isa64 == intel64)
13466         {
13467           oappend ("QWORD PTR ");
13468           break;
13469         }
13470       /* Fall through.  */
13471     case stack_v_mode:
13472       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13473         {
13474           oappend ("QWORD PTR ");
13475           break;
13476         }
13477       /* Fall through.  */
13478     case v_mode:
13479     case v_swap_mode:
13480     case dq_mode:
13481       USED_REX (REX_W);
13482       if (rex & REX_W)
13483         oappend ("QWORD PTR ");
13484       else
13485         {
13486           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13487             oappend ("DWORD PTR ");
13488           else
13489             oappend ("WORD PTR ");
13490           used_prefixes |= (prefixes & PREFIX_DATA);
13491         }
13492       break;
13493     case z_mode:
13494       if ((rex & REX_W) || (sizeflag & DFLAG))
13495         *obufp++ = 'D';
13496       oappend ("WORD PTR ");
13497       if (!(rex & REX_W))
13498         used_prefixes |= (prefixes & PREFIX_DATA);
13499       break;
13500     case a_mode:
13501       if (sizeflag & DFLAG)
13502         oappend ("QWORD PTR ");
13503       else
13504         oappend ("DWORD PTR ");
13505       used_prefixes |= (prefixes & PREFIX_DATA);
13506       break;
13507     case d_mode:
13508     case d_scalar_mode:
13509     case d_scalar_swap_mode:
13510     case d_swap_mode:
13511     case dqd_mode:
13512       oappend ("DWORD PTR ");
13513       break;
13514     case q_mode:
13515     case q_scalar_mode:
13516     case q_scalar_swap_mode:
13517     case q_swap_mode:
13518       oappend ("QWORD PTR ");
13519       break;
13520     case m_mode:
13521       if (address_mode == mode_64bit)
13522         oappend ("QWORD PTR ");
13523       else
13524         oappend ("DWORD PTR ");
13525       break;
13526     case f_mode:
13527       if (sizeflag & DFLAG)
13528         oappend ("FWORD PTR ");
13529       else
13530         oappend ("DWORD PTR ");
13531       used_prefixes |= (prefixes & PREFIX_DATA);
13532       break;
13533     case t_mode:
13534       oappend ("TBYTE PTR ");
13535       break;
13536     case x_mode:
13537     case x_swap_mode:
13538     case evex_x_gscat_mode:
13539     case evex_x_nobcst_mode:
13540     case b_scalar_mode:
13541     case w_scalar_mode:
13542       if (need_vex)
13543         {
13544           switch (vex.length)
13545             {
13546             case 128:
13547               oappend ("XMMWORD PTR ");
13548               break;
13549             case 256:
13550               oappend ("YMMWORD PTR ");
13551               break;
13552             case 512:
13553               oappend ("ZMMWORD PTR ");
13554               break;
13555             default:
13556               abort ();
13557             }
13558         }
13559       else
13560         oappend ("XMMWORD PTR ");
13561       break;
13562     case xmm_mode:
13563       oappend ("XMMWORD PTR ");
13564       break;
13565     case ymm_mode:
13566       oappend ("YMMWORD PTR ");
13567       break;
13568     case xmmq_mode:
13569     case evex_half_bcst_xmmq_mode:
13570       if (!need_vex)
13571         abort ();
13572
13573       switch (vex.length)
13574         {
13575         case 128:
13576           oappend ("QWORD PTR ");
13577           break;
13578         case 256:
13579           oappend ("XMMWORD PTR ");
13580           break;
13581         case 512:
13582           oappend ("YMMWORD PTR ");
13583           break;
13584         default:
13585           abort ();
13586         }
13587       break;
13588     case xmm_mb_mode:
13589       if (!need_vex)
13590         abort ();
13591
13592       switch (vex.length)
13593         {
13594         case 128:
13595         case 256:
13596         case 512:
13597           oappend ("BYTE PTR ");
13598           break;
13599         default:
13600           abort ();
13601         }
13602       break;
13603     case xmm_mw_mode:
13604       if (!need_vex)
13605         abort ();
13606
13607       switch (vex.length)
13608         {
13609         case 128:
13610         case 256:
13611         case 512:
13612           oappend ("WORD PTR ");
13613           break;
13614         default:
13615           abort ();
13616         }
13617       break;
13618     case xmm_md_mode:
13619       if (!need_vex)
13620         abort ();
13621
13622       switch (vex.length)
13623         {
13624         case 128:
13625         case 256:
13626         case 512:
13627           oappend ("DWORD PTR ");
13628           break;
13629         default:
13630           abort ();
13631         }
13632       break;
13633     case xmm_mq_mode:
13634       if (!need_vex)
13635         abort ();
13636
13637       switch (vex.length)
13638         {
13639         case 128:
13640         case 256:
13641         case 512:
13642           oappend ("QWORD PTR ");
13643           break;
13644         default:
13645           abort ();
13646         }
13647       break;
13648     case xmmdw_mode:
13649       if (!need_vex)
13650         abort ();
13651
13652       switch (vex.length)
13653         {
13654         case 128:
13655           oappend ("WORD PTR ");
13656           break;
13657         case 256:
13658           oappend ("DWORD PTR ");
13659           break;
13660         case 512:
13661           oappend ("QWORD PTR ");
13662           break;
13663         default:
13664           abort ();
13665         }
13666       break;
13667     case xmmqd_mode:
13668       if (!need_vex)
13669         abort ();
13670
13671       switch (vex.length)
13672         {
13673         case 128:
13674           oappend ("DWORD PTR ");
13675           break;
13676         case 256:
13677           oappend ("QWORD PTR ");
13678           break;
13679         case 512:
13680           oappend ("XMMWORD PTR ");
13681           break;
13682         default:
13683           abort ();
13684         }
13685       break;
13686     case ymmq_mode:
13687       if (!need_vex)
13688         abort ();
13689
13690       switch (vex.length)
13691         {
13692         case 128:
13693           oappend ("QWORD PTR ");
13694           break;
13695         case 256:
13696           oappend ("YMMWORD PTR ");
13697           break;
13698         case 512:
13699           oappend ("ZMMWORD PTR ");
13700           break;
13701         default:
13702           abort ();
13703         }
13704       break;
13705     case ymmxmm_mode:
13706       if (!need_vex)
13707         abort ();
13708
13709       switch (vex.length)
13710         {
13711         case 128:
13712         case 256:
13713           oappend ("XMMWORD PTR ");
13714           break;
13715         default:
13716           abort ();
13717         }
13718       break;
13719     case o_mode:
13720       oappend ("OWORD PTR ");
13721       break;
13722     case xmm_mdq_mode:
13723     case vex_w_dq_mode:
13724     case vex_scalar_w_dq_mode:
13725       if (!need_vex)
13726         abort ();
13727
13728       if (vex.w)
13729         oappend ("QWORD PTR ");
13730       else
13731         oappend ("DWORD PTR ");
13732       break;
13733     case vex_vsib_d_w_dq_mode:
13734     case vex_vsib_q_w_dq_mode:
13735       if (!need_vex)
13736         abort ();
13737
13738       if (!vex.evex)
13739         {
13740           if (vex.w)
13741             oappend ("QWORD PTR ");
13742           else
13743             oappend ("DWORD PTR ");
13744         }
13745       else
13746         {
13747           switch (vex.length)
13748             {
13749             case 128:
13750               oappend ("XMMWORD PTR ");
13751               break;
13752             case 256:
13753               oappend ("YMMWORD PTR ");
13754               break;
13755             case 512:
13756               oappend ("ZMMWORD PTR ");
13757               break;
13758             default:
13759               abort ();
13760             }
13761         }
13762       break;
13763     case vex_vsib_q_w_d_mode:
13764     case vex_vsib_d_w_d_mode:
13765       if (!need_vex || !vex.evex)
13766         abort ();
13767
13768       switch (vex.length)
13769         {
13770         case 128:
13771           oappend ("QWORD PTR ");
13772           break;
13773         case 256:
13774           oappend ("XMMWORD PTR ");
13775           break;
13776         case 512:
13777           oappend ("YMMWORD PTR ");
13778           break;
13779         default:
13780           abort ();
13781         }
13782
13783       break;
13784     case mask_bd_mode:
13785       if (!need_vex || vex.length != 128)
13786         abort ();
13787       if (vex.w)
13788         oappend ("DWORD PTR ");
13789       else
13790         oappend ("BYTE PTR ");
13791       break;
13792     case mask_mode:
13793       if (!need_vex)
13794         abort ();
13795       if (vex.w)
13796         oappend ("QWORD PTR ");
13797       else
13798         oappend ("WORD PTR ");
13799       break;
13800     case v_bnd_mode:
13801     case v_bndmk_mode:
13802     default:
13803       break;
13804     }
13805 }
13806
13807 static void
13808 OP_E_register (int bytemode, int sizeflag)
13809 {
13810   int reg = modrm.rm;
13811   const char **names;
13812
13813   USED_REX (REX_B);
13814   if ((rex & REX_B))
13815     reg += 8;
13816
13817   if ((sizeflag & SUFFIX_ALWAYS)
13818       && (bytemode == b_swap_mode
13819           || bytemode == bnd_swap_mode
13820           || bytemode == v_swap_mode))
13821     swap_operand ();
13822
13823   switch (bytemode)
13824     {
13825     case b_mode:
13826     case b_swap_mode:
13827       USED_REX (0);
13828       if (rex)
13829         names = names8rex;
13830       else
13831         names = names8;
13832       break;
13833     case w_mode:
13834       names = names16;
13835       break;
13836     case d_mode:
13837     case dw_mode:
13838     case db_mode:
13839       names = names32;
13840       break;
13841     case q_mode:
13842       names = names64;
13843       break;
13844     case m_mode:
13845     case v_bnd_mode:
13846       names = address_mode == mode_64bit ? names64 : names32;
13847       break;
13848     case bnd_mode:
13849     case bnd_swap_mode:
13850       if (reg > 0x3)
13851         {
13852           oappend ("(bad)");
13853           return;
13854         }
13855       names = names_bnd;
13856       break;
13857     case indir_v_mode:
13858       if (address_mode == mode_64bit && isa64 == intel64)
13859         {
13860           names = names64;
13861           break;
13862         }
13863       /* Fall through.  */
13864     case stack_v_mode:
13865       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13866         {
13867           names = names64;
13868           break;
13869         }
13870       bytemode = v_mode;
13871       /* Fall through.  */
13872     case v_mode:
13873     case v_swap_mode:
13874     case dq_mode:
13875     case dqb_mode:
13876     case dqd_mode:
13877     case dqw_mode:
13878       USED_REX (REX_W);
13879       if (rex & REX_W)
13880         names = names64;
13881       else
13882         {
13883           if ((sizeflag & DFLAG)
13884               || (bytemode != v_mode
13885                   && bytemode != v_swap_mode))
13886             names = names32;
13887           else
13888             names = names16;
13889           used_prefixes |= (prefixes & PREFIX_DATA);
13890         }
13891       break;
13892     case va_mode:
13893       names = (address_mode == mode_64bit
13894                ? names64 : names32);
13895       if (!(prefixes & PREFIX_ADDR))
13896         names = (address_mode == mode_16bit
13897                      ? names16 : names);
13898       else
13899         {
13900           /* Remove "addr16/addr32".  */
13901           all_prefixes[last_addr_prefix] = 0;
13902           names = (address_mode != mode_32bit
13903                        ? names32 : names16);
13904           used_prefixes |= PREFIX_ADDR;
13905         }
13906       break;
13907     case mask_bd_mode:
13908     case mask_mode:
13909       if (reg > 0x7)
13910         {
13911           oappend ("(bad)");
13912           return;
13913         }
13914       names = names_mask;
13915       break;
13916     case 0:
13917       return;
13918     default:
13919       oappend (INTERNAL_DISASSEMBLER_ERROR);
13920       return;
13921     }
13922   oappend (names[reg]);
13923 }
13924
13925 static void
13926 OP_E_memory (int bytemode, int sizeflag)
13927 {
13928   bfd_vma disp = 0;
13929   int add = (rex & REX_B) ? 8 : 0;
13930   int riprel = 0;
13931   int shift;
13932
13933   if (vex.evex)
13934     {
13935       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13936       if (vex.b
13937           && bytemode != x_mode
13938           && bytemode != xmmq_mode
13939           && bytemode != evex_half_bcst_xmmq_mode)
13940         {
13941           BadOp ();
13942           return;
13943         }
13944       switch (bytemode)
13945         {
13946         case dqw_mode:
13947         case dw_mode:
13948           shift = 1;
13949           break;
13950         case dqb_mode:
13951         case db_mode:
13952           shift = 0;
13953           break;
13954         case dq_mode:
13955           if (address_mode != mode_64bit)
13956             {
13957               shift = 2;
13958               break;
13959             }
13960             /* fall through */
13961         case vex_vsib_d_w_dq_mode:
13962         case vex_vsib_d_w_d_mode:
13963         case vex_vsib_q_w_dq_mode:
13964         case vex_vsib_q_w_d_mode:
13965         case evex_x_gscat_mode:
13966         case xmm_mdq_mode:
13967           shift = vex.w ? 3 : 2;
13968           break;
13969         case x_mode:
13970         case evex_half_bcst_xmmq_mode:
13971         case xmmq_mode:
13972           if (vex.b)
13973             {
13974               shift = vex.w ? 3 : 2;
13975               break;
13976             }
13977           /* Fall through.  */
13978         case xmmqd_mode:
13979         case xmmdw_mode:
13980         case ymmq_mode:
13981         case evex_x_nobcst_mode:
13982         case x_swap_mode:
13983           switch (vex.length)
13984             {
13985             case 128:
13986               shift = 4;
13987               break;
13988             case 256:
13989               shift = 5;
13990               break;
13991             case 512:
13992               shift = 6;
13993               break;
13994             default:
13995               abort ();
13996             }
13997           break;
13998         case ymm_mode:
13999           shift = 5;
14000           break;
14001         case xmm_mode:
14002           shift = 4;
14003           break;
14004         case xmm_mq_mode:
14005         case q_mode:
14006         case q_scalar_mode:
14007         case q_swap_mode:
14008         case q_scalar_swap_mode:
14009           shift = 3;
14010           break;
14011         case dqd_mode:
14012         case xmm_md_mode:
14013         case d_mode:
14014         case d_scalar_mode:
14015         case d_swap_mode:
14016         case d_scalar_swap_mode:
14017           shift = 2;
14018           break;
14019         case w_scalar_mode:
14020         case xmm_mw_mode:
14021           shift = 1;
14022           break;
14023         case b_scalar_mode:
14024         case xmm_mb_mode:
14025           shift = 0;
14026           break;
14027         default:
14028           abort ();
14029         }
14030       /* Make necessary corrections to shift for modes that need it.
14031          For these modes we currently have shift 4, 5 or 6 depending on
14032          vex.length (it corresponds to xmmword, ymmword or zmmword
14033          operand).  We might want to make it 3, 4 or 5 (e.g. for
14034          xmmq_mode).  In case of broadcast enabled the corrections
14035          aren't needed, as element size is always 32 or 64 bits.  */
14036       if (!vex.b
14037           && (bytemode == xmmq_mode
14038               || bytemode == evex_half_bcst_xmmq_mode))
14039         shift -= 1;
14040       else if (bytemode == xmmqd_mode)
14041         shift -= 2;
14042       else if (bytemode == xmmdw_mode)
14043         shift -= 3;
14044       else if (bytemode == ymmq_mode && vex.length == 128)
14045         shift -= 1;
14046     }
14047   else
14048     shift = 0;
14049
14050   USED_REX (REX_B);
14051   if (intel_syntax)
14052     intel_operand_size (bytemode, sizeflag);
14053   append_seg ();
14054
14055   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14056     {
14057       /* 32/64 bit address mode */
14058       int havedisp;
14059       int havesib;
14060       int havebase;
14061       int haveindex;
14062       int needindex;
14063       int needaddr32;
14064       int base, rbase;
14065       int vindex = 0;
14066       int scale = 0;
14067       int addr32flag = !((sizeflag & AFLAG)
14068                          || bytemode == v_bnd_mode
14069                          || bytemode == v_bndmk_mode
14070                          || bytemode == bnd_mode
14071                          || bytemode == bnd_swap_mode);
14072       const char **indexes64 = names64;
14073       const char **indexes32 = names32;
14074
14075       havesib = 0;
14076       havebase = 1;
14077       haveindex = 0;
14078       base = modrm.rm;
14079
14080       if (base == 4)
14081         {
14082           havesib = 1;
14083           vindex = sib.index;
14084           USED_REX (REX_X);
14085           if (rex & REX_X)
14086             vindex += 8;
14087           switch (bytemode)
14088             {
14089             case vex_vsib_d_w_dq_mode:
14090             case vex_vsib_d_w_d_mode:
14091             case vex_vsib_q_w_dq_mode:
14092             case vex_vsib_q_w_d_mode:
14093               if (!need_vex)
14094                 abort ();
14095               if (vex.evex)
14096                 {
14097                   if (!vex.v)
14098                     vindex += 16;
14099                 }
14100
14101               haveindex = 1;
14102               switch (vex.length)
14103                 {
14104                 case 128:
14105                   indexes64 = indexes32 = names_xmm;
14106                   break;
14107                 case 256:
14108                   if (!vex.w
14109                       || bytemode == vex_vsib_q_w_dq_mode
14110                       || bytemode == vex_vsib_q_w_d_mode)
14111                     indexes64 = indexes32 = names_ymm;
14112                   else
14113                     indexes64 = indexes32 = names_xmm;
14114                   break;
14115                 case 512:
14116                   if (!vex.w
14117                       || bytemode == vex_vsib_q_w_dq_mode
14118                       || bytemode == vex_vsib_q_w_d_mode)
14119                     indexes64 = indexes32 = names_zmm;
14120                   else
14121                     indexes64 = indexes32 = names_ymm;
14122                   break;
14123                 default:
14124                   abort ();
14125                 }
14126               break;
14127             default:
14128               haveindex = vindex != 4;
14129               break;
14130             }
14131           scale = sib.scale;
14132           base = sib.base;
14133           codep++;
14134         }
14135       rbase = base + add;
14136
14137       switch (modrm.mod)
14138         {
14139         case 0:
14140           if (base == 5)
14141             {
14142               havebase = 0;
14143               if (address_mode == mode_64bit && !havesib)
14144                 riprel = 1;
14145               disp = get32s ();
14146               if (riprel && bytemode == v_bndmk_mode)
14147                 {
14148                   oappend ("(bad)");
14149                   return;
14150                 }
14151             }
14152           break;
14153         case 1:
14154           FETCH_DATA (the_info, codep + 1);
14155           disp = *codep++;
14156           if ((disp & 0x80) != 0)
14157             disp -= 0x100;
14158           if (vex.evex && shift > 0)
14159             disp <<= shift;
14160           break;
14161         case 2:
14162           disp = get32s ();
14163           break;
14164         }
14165
14166       needindex = 0;
14167       needaddr32 = 0;
14168       if (havesib
14169           && !havebase
14170           && !haveindex
14171           && address_mode != mode_16bit)
14172         {
14173           if (address_mode == mode_64bit)
14174             {
14175               /* Display eiz instead of addr32.  */
14176               needindex = addr32flag;
14177               needaddr32 = 1;
14178             }
14179           else
14180             {
14181               /* In 32-bit mode, we need index register to tell [offset]
14182                  from [eiz*1 + offset].  */
14183               needindex = 1;
14184             }
14185         }
14186
14187       havedisp = (havebase
14188                   || needindex
14189                   || (havesib && (haveindex || scale != 0)));
14190
14191       if (!intel_syntax)
14192         if (modrm.mod != 0 || base == 5)
14193           {
14194             if (havedisp || riprel)
14195               print_displacement (scratchbuf, disp);
14196             else
14197               print_operand_value (scratchbuf, 1, disp);
14198             oappend (scratchbuf);
14199             if (riprel)
14200               {
14201                 set_op (disp, 1);
14202                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14203               }
14204           }
14205
14206       if ((havebase || haveindex || needaddr32 || riprel)
14207           && (bytemode != v_bnd_mode)
14208           && (bytemode != v_bndmk_mode)
14209           && (bytemode != bnd_mode)
14210           && (bytemode != bnd_swap_mode))
14211         used_prefixes |= PREFIX_ADDR;
14212
14213       if (havedisp || (intel_syntax && riprel))
14214         {
14215           *obufp++ = open_char;
14216           if (intel_syntax && riprel)
14217             {
14218               set_op (disp, 1);
14219               oappend (!addr32flag ? "rip" : "eip");
14220             }
14221           *obufp = '\0';
14222           if (havebase)
14223             oappend (address_mode == mode_64bit && !addr32flag
14224                      ? names64[rbase] : names32[rbase]);
14225           if (havesib)
14226             {
14227               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14228                  print index to tell base + index from base.  */
14229               if (scale != 0
14230                   || needindex
14231                   || haveindex
14232                   || (havebase && base != ESP_REG_NUM))
14233                 {
14234                   if (!intel_syntax || havebase)
14235                     {
14236                       *obufp++ = separator_char;
14237                       *obufp = '\0';
14238                     }
14239                   if (haveindex)
14240                     oappend (address_mode == mode_64bit && !addr32flag
14241                              ? indexes64[vindex] : indexes32[vindex]);
14242                   else
14243                     oappend (address_mode == mode_64bit && !addr32flag
14244                              ? index64 : index32);
14245
14246                   *obufp++ = scale_char;
14247                   *obufp = '\0';
14248                   sprintf (scratchbuf, "%d", 1 << scale);
14249                   oappend (scratchbuf);
14250                 }
14251             }
14252           if (intel_syntax
14253               && (disp || modrm.mod != 0 || base == 5))
14254             {
14255               if (!havedisp || (bfd_signed_vma) disp >= 0)
14256                 {
14257                   *obufp++ = '+';
14258                   *obufp = '\0';
14259                 }
14260               else if (modrm.mod != 1 && disp != -disp)
14261                 {
14262                   *obufp++ = '-';
14263                   *obufp = '\0';
14264                   disp = - (bfd_signed_vma) disp;
14265                 }
14266
14267               if (havedisp)
14268                 print_displacement (scratchbuf, disp);
14269               else
14270                 print_operand_value (scratchbuf, 1, disp);
14271               oappend (scratchbuf);
14272             }
14273
14274           *obufp++ = close_char;
14275           *obufp = '\0';
14276         }
14277       else if (intel_syntax)
14278         {
14279           if (modrm.mod != 0 || base == 5)
14280             {
14281               if (!active_seg_prefix)
14282                 {
14283                   oappend (names_seg[ds_reg - es_reg]);
14284                   oappend (":");
14285                 }
14286               print_operand_value (scratchbuf, 1, disp);
14287               oappend (scratchbuf);
14288             }
14289         }
14290     }
14291   else
14292     {
14293       /* 16 bit address mode */
14294       used_prefixes |= prefixes & PREFIX_ADDR;
14295       switch (modrm.mod)
14296         {
14297         case 0:
14298           if (modrm.rm == 6)
14299             {
14300               disp = get16 ();
14301               if ((disp & 0x8000) != 0)
14302                 disp -= 0x10000;
14303             }
14304           break;
14305         case 1:
14306           FETCH_DATA (the_info, codep + 1);
14307           disp = *codep++;
14308           if ((disp & 0x80) != 0)
14309             disp -= 0x100;
14310           if (vex.evex && shift > 0)
14311             disp <<= shift;
14312           break;
14313         case 2:
14314           disp = get16 ();
14315           if ((disp & 0x8000) != 0)
14316             disp -= 0x10000;
14317           break;
14318         }
14319
14320       if (!intel_syntax)
14321         if (modrm.mod != 0 || modrm.rm == 6)
14322           {
14323             print_displacement (scratchbuf, disp);
14324             oappend (scratchbuf);
14325           }
14326
14327       if (modrm.mod != 0 || modrm.rm != 6)
14328         {
14329           *obufp++ = open_char;
14330           *obufp = '\0';
14331           oappend (index16[modrm.rm]);
14332           if (intel_syntax
14333               && (disp || modrm.mod != 0 || modrm.rm == 6))
14334             {
14335               if ((bfd_signed_vma) disp >= 0)
14336                 {
14337                   *obufp++ = '+';
14338                   *obufp = '\0';
14339                 }
14340               else if (modrm.mod != 1)
14341                 {
14342                   *obufp++ = '-';
14343                   *obufp = '\0';
14344                   disp = - (bfd_signed_vma) disp;
14345                 }
14346
14347               print_displacement (scratchbuf, disp);
14348               oappend (scratchbuf);
14349             }
14350
14351           *obufp++ = close_char;
14352           *obufp = '\0';
14353         }
14354       else if (intel_syntax)
14355         {
14356           if (!active_seg_prefix)
14357             {
14358               oappend (names_seg[ds_reg - es_reg]);
14359               oappend (":");
14360             }
14361           print_operand_value (scratchbuf, 1, disp & 0xffff);
14362           oappend (scratchbuf);
14363         }
14364     }
14365   if (vex.evex && vex.b
14366       && (bytemode == x_mode
14367           || bytemode == xmmq_mode
14368           || bytemode == evex_half_bcst_xmmq_mode))
14369     {
14370       if (vex.w
14371           || bytemode == xmmq_mode
14372           || bytemode == evex_half_bcst_xmmq_mode)
14373         {
14374           switch (vex.length)
14375             {
14376             case 128:
14377               oappend ("{1to2}");
14378               break;
14379             case 256:
14380               oappend ("{1to4}");
14381               break;
14382             case 512:
14383               oappend ("{1to8}");
14384               break;
14385             default:
14386               abort ();
14387             }
14388         }
14389       else
14390         {
14391           switch (vex.length)
14392             {
14393             case 128:
14394               oappend ("{1to4}");
14395               break;
14396             case 256:
14397               oappend ("{1to8}");
14398               break;
14399             case 512:
14400               oappend ("{1to16}");
14401               break;
14402             default:
14403               abort ();
14404             }
14405         }
14406     }
14407 }
14408
14409 static void
14410 OP_E (int bytemode, int sizeflag)
14411 {
14412   /* Skip mod/rm byte.  */
14413   MODRM_CHECK;
14414   codep++;
14415
14416   if (modrm.mod == 3)
14417     OP_E_register (bytemode, sizeflag);
14418   else
14419     OP_E_memory (bytemode, sizeflag);
14420 }
14421
14422 static void
14423 OP_G (int bytemode, int sizeflag)
14424 {
14425   int add = 0;
14426   const char **names;
14427   USED_REX (REX_R);
14428   if (rex & REX_R)
14429     add += 8;
14430   switch (bytemode)
14431     {
14432     case b_mode:
14433       USED_REX (0);
14434       if (rex)
14435         oappend (names8rex[modrm.reg + add]);
14436       else
14437         oappend (names8[modrm.reg + add]);
14438       break;
14439     case w_mode:
14440       oappend (names16[modrm.reg + add]);
14441       break;
14442     case d_mode:
14443     case db_mode:
14444     case dw_mode:
14445       oappend (names32[modrm.reg + add]);
14446       break;
14447     case q_mode:
14448       oappend (names64[modrm.reg + add]);
14449       break;
14450     case bnd_mode:
14451       if (modrm.reg > 0x3)
14452         {
14453           oappend ("(bad)");
14454           return;
14455         }
14456       oappend (names_bnd[modrm.reg]);
14457       break;
14458     case v_mode:
14459     case dq_mode:
14460     case dqb_mode:
14461     case dqd_mode:
14462     case dqw_mode:
14463       USED_REX (REX_W);
14464       if (rex & REX_W)
14465         oappend (names64[modrm.reg + add]);
14466       else
14467         {
14468           if ((sizeflag & DFLAG) || bytemode != v_mode)
14469             oappend (names32[modrm.reg + add]);
14470           else
14471             oappend (names16[modrm.reg + add]);
14472           used_prefixes |= (prefixes & PREFIX_DATA);
14473         }
14474       break;
14475     case va_mode:
14476       names = (address_mode == mode_64bit
14477                ? names64 : names32);
14478       if (!(prefixes & PREFIX_ADDR))
14479         {
14480           if (address_mode == mode_16bit)
14481             names = names16;
14482         }
14483       else
14484         {
14485           /* Remove "addr16/addr32".  */
14486           all_prefixes[last_addr_prefix] = 0;
14487           names = (address_mode != mode_32bit
14488                        ? names32 : names16);
14489           used_prefixes |= PREFIX_ADDR;
14490         }
14491       oappend (names[modrm.reg + add]);
14492       break;
14493     case m_mode:
14494       if (address_mode == mode_64bit)
14495         oappend (names64[modrm.reg + add]);
14496       else
14497         oappend (names32[modrm.reg + add]);
14498       break;
14499     case mask_bd_mode:
14500     case mask_mode:
14501       if ((modrm.reg + add) > 0x7)
14502         {
14503           oappend ("(bad)");
14504           return;
14505         }
14506       oappend (names_mask[modrm.reg + add]);
14507       break;
14508     default:
14509       oappend (INTERNAL_DISASSEMBLER_ERROR);
14510       break;
14511     }
14512 }
14513
14514 static bfd_vma
14515 get64 (void)
14516 {
14517   bfd_vma x;
14518 #ifdef BFD64
14519   unsigned int a;
14520   unsigned int b;
14521
14522   FETCH_DATA (the_info, codep + 8);
14523   a = *codep++ & 0xff;
14524   a |= (*codep++ & 0xff) << 8;
14525   a |= (*codep++ & 0xff) << 16;
14526   a |= (*codep++ & 0xffu) << 24;
14527   b = *codep++ & 0xff;
14528   b |= (*codep++ & 0xff) << 8;
14529   b |= (*codep++ & 0xff) << 16;
14530   b |= (*codep++ & 0xffu) << 24;
14531   x = a + ((bfd_vma) b << 32);
14532 #else
14533   abort ();
14534   x = 0;
14535 #endif
14536   return x;
14537 }
14538
14539 static bfd_signed_vma
14540 get32 (void)
14541 {
14542   bfd_signed_vma x = 0;
14543
14544   FETCH_DATA (the_info, codep + 4);
14545   x = *codep++ & (bfd_signed_vma) 0xff;
14546   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14547   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14548   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14549   return x;
14550 }
14551
14552 static bfd_signed_vma
14553 get32s (void)
14554 {
14555   bfd_signed_vma x = 0;
14556
14557   FETCH_DATA (the_info, codep + 4);
14558   x = *codep++ & (bfd_signed_vma) 0xff;
14559   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14560   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14561   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14562
14563   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14564
14565   return x;
14566 }
14567
14568 static int
14569 get16 (void)
14570 {
14571   int x = 0;
14572
14573   FETCH_DATA (the_info, codep + 2);
14574   x = *codep++ & 0xff;
14575   x |= (*codep++ & 0xff) << 8;
14576   return x;
14577 }
14578
14579 static void
14580 set_op (bfd_vma op, int riprel)
14581 {
14582   op_index[op_ad] = op_ad;
14583   if (address_mode == mode_64bit)
14584     {
14585       op_address[op_ad] = op;
14586       op_riprel[op_ad] = riprel;
14587     }
14588   else
14589     {
14590       /* Mask to get a 32-bit address.  */
14591       op_address[op_ad] = op & 0xffffffff;
14592       op_riprel[op_ad] = riprel & 0xffffffff;
14593     }
14594 }
14595
14596 static void
14597 OP_REG (int code, int sizeflag)
14598 {
14599   const char *s;
14600   int add;
14601
14602   switch (code)
14603     {
14604     case es_reg: case ss_reg: case cs_reg:
14605     case ds_reg: case fs_reg: case gs_reg:
14606       oappend (names_seg[code - es_reg]);
14607       return;
14608     }
14609
14610   USED_REX (REX_B);
14611   if (rex & REX_B)
14612     add = 8;
14613   else
14614     add = 0;
14615
14616   switch (code)
14617     {
14618     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14619     case sp_reg: case bp_reg: case si_reg: case di_reg:
14620       s = names16[code - ax_reg + add];
14621       break;
14622     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14623     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14624       USED_REX (0);
14625       if (rex)
14626         s = names8rex[code - al_reg + add];
14627       else
14628         s = names8[code - al_reg];
14629       break;
14630     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14631     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14632       if (address_mode == mode_64bit
14633           && ((sizeflag & DFLAG) || (rex & REX_W)))
14634         {
14635           s = names64[code - rAX_reg + add];
14636           break;
14637         }
14638       code += eAX_reg - rAX_reg;
14639       /* Fall through.  */
14640     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14641     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14642       USED_REX (REX_W);
14643       if (rex & REX_W)
14644         s = names64[code - eAX_reg + add];
14645       else
14646         {
14647           if (sizeflag & DFLAG)
14648             s = names32[code - eAX_reg + add];
14649           else
14650             s = names16[code - eAX_reg + add];
14651           used_prefixes |= (prefixes & PREFIX_DATA);
14652         }
14653       break;
14654     default:
14655       s = INTERNAL_DISASSEMBLER_ERROR;
14656       break;
14657     }
14658   oappend (s);
14659 }
14660
14661 static void
14662 OP_IMREG (int code, int sizeflag)
14663 {
14664   const char *s;
14665
14666   switch (code)
14667     {
14668     case indir_dx_reg:
14669       if (intel_syntax)
14670         s = "dx";
14671       else
14672         s = "(%dx)";
14673       break;
14674     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14675     case sp_reg: case bp_reg: case si_reg: case di_reg:
14676       s = names16[code - ax_reg];
14677       break;
14678     case es_reg: case ss_reg: case cs_reg:
14679     case ds_reg: case fs_reg: case gs_reg:
14680       s = names_seg[code - es_reg];
14681       break;
14682     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14683     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14684       USED_REX (0);
14685       if (rex)
14686         s = names8rex[code - al_reg];
14687       else
14688         s = names8[code - al_reg];
14689       break;
14690     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14691     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14692       USED_REX (REX_W);
14693       if (rex & REX_W)
14694         s = names64[code - eAX_reg];
14695       else
14696         {
14697           if (sizeflag & DFLAG)
14698             s = names32[code - eAX_reg];
14699           else
14700             s = names16[code - eAX_reg];
14701           used_prefixes |= (prefixes & PREFIX_DATA);
14702         }
14703       break;
14704     case z_mode_ax_reg:
14705       if ((rex & REX_W) || (sizeflag & DFLAG))
14706         s = *names32;
14707       else
14708         s = *names16;
14709       if (!(rex & REX_W))
14710         used_prefixes |= (prefixes & PREFIX_DATA);
14711       break;
14712     default:
14713       s = INTERNAL_DISASSEMBLER_ERROR;
14714       break;
14715     }
14716   oappend (s);
14717 }
14718
14719 static void
14720 OP_I (int bytemode, int sizeflag)
14721 {
14722   bfd_signed_vma op;
14723   bfd_signed_vma mask = -1;
14724
14725   switch (bytemode)
14726     {
14727     case b_mode:
14728       FETCH_DATA (the_info, codep + 1);
14729       op = *codep++;
14730       mask = 0xff;
14731       break;
14732     case q_mode:
14733       if (address_mode == mode_64bit)
14734         {
14735           op = get32s ();
14736           break;
14737         }
14738       /* Fall through.  */
14739     case v_mode:
14740       USED_REX (REX_W);
14741       if (rex & REX_W)
14742         op = get32s ();
14743       else
14744         {
14745           if (sizeflag & DFLAG)
14746             {
14747               op = get32 ();
14748               mask = 0xffffffff;
14749             }
14750           else
14751             {
14752               op = get16 ();
14753               mask = 0xfffff;
14754             }
14755           used_prefixes |= (prefixes & PREFIX_DATA);
14756         }
14757       break;
14758     case w_mode:
14759       mask = 0xfffff;
14760       op = get16 ();
14761       break;
14762     case const_1_mode:
14763       if (intel_syntax)
14764         oappend ("1");
14765       return;
14766     default:
14767       oappend (INTERNAL_DISASSEMBLER_ERROR);
14768       return;
14769     }
14770
14771   op &= mask;
14772   scratchbuf[0] = '$';
14773   print_operand_value (scratchbuf + 1, 1, op);
14774   oappend_maybe_intel (scratchbuf);
14775   scratchbuf[0] = '\0';
14776 }
14777
14778 static void
14779 OP_I64 (int bytemode, int sizeflag)
14780 {
14781   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14782     {
14783       OP_I (bytemode, sizeflag);
14784       return;
14785     }
14786
14787   USED_REX (REX_W);
14788
14789   scratchbuf[0] = '$';
14790   print_operand_value (scratchbuf + 1, 1, get64 ());
14791   oappend_maybe_intel (scratchbuf);
14792   scratchbuf[0] = '\0';
14793 }
14794
14795 static void
14796 OP_sI (int bytemode, int sizeflag)
14797 {
14798   bfd_signed_vma op;
14799
14800   switch (bytemode)
14801     {
14802     case b_mode:
14803     case b_T_mode:
14804       FETCH_DATA (the_info, codep + 1);
14805       op = *codep++;
14806       if ((op & 0x80) != 0)
14807         op -= 0x100;
14808       if (bytemode == b_T_mode)
14809         {
14810           if (address_mode != mode_64bit
14811               || !((sizeflag & DFLAG) || (rex & REX_W)))
14812             {
14813               /* The operand-size prefix is overridden by a REX prefix.  */
14814               if ((sizeflag & DFLAG) || (rex & REX_W))
14815                 op &= 0xffffffff;
14816               else
14817                 op &= 0xffff;
14818           }
14819         }
14820       else
14821         {
14822           if (!(rex & REX_W))
14823             {
14824               if (sizeflag & DFLAG)
14825                 op &= 0xffffffff;
14826               else
14827                 op &= 0xffff;
14828             }
14829         }
14830       break;
14831     case v_mode:
14832       /* The operand-size prefix is overridden by a REX prefix.  */
14833       if ((sizeflag & DFLAG) || (rex & REX_W))
14834         op = get32s ();
14835       else
14836         op = get16 ();
14837       break;
14838     default:
14839       oappend (INTERNAL_DISASSEMBLER_ERROR);
14840       return;
14841     }
14842
14843   scratchbuf[0] = '$';
14844   print_operand_value (scratchbuf + 1, 1, op);
14845   oappend_maybe_intel (scratchbuf);
14846 }
14847
14848 static void
14849 OP_J (int bytemode, int sizeflag)
14850 {
14851   bfd_vma disp;
14852   bfd_vma mask = -1;
14853   bfd_vma segment = 0;
14854
14855   switch (bytemode)
14856     {
14857     case b_mode:
14858       FETCH_DATA (the_info, codep + 1);
14859       disp = *codep++;
14860       if ((disp & 0x80) != 0)
14861         disp -= 0x100;
14862       break;
14863     case v_mode:
14864       if (isa64 == amd64)
14865         USED_REX (REX_W);
14866       if ((sizeflag & DFLAG)
14867           || (address_mode == mode_64bit
14868               && (isa64 != amd64 || (rex & REX_W))))
14869         disp = get32s ();
14870       else
14871         {
14872           disp = get16 ();
14873           if ((disp & 0x8000) != 0)
14874             disp -= 0x10000;
14875           /* In 16bit mode, address is wrapped around at 64k within
14876              the same segment.  Otherwise, a data16 prefix on a jump
14877              instruction means that the pc is masked to 16 bits after
14878              the displacement is added!  */
14879           mask = 0xffff;
14880           if ((prefixes & PREFIX_DATA) == 0)
14881             segment = ((start_pc + (codep - start_codep))
14882                        & ~((bfd_vma) 0xffff));
14883         }
14884       if (address_mode != mode_64bit
14885           || (isa64 == amd64 && !(rex & REX_W)))
14886         used_prefixes |= (prefixes & PREFIX_DATA);
14887       break;
14888     default:
14889       oappend (INTERNAL_DISASSEMBLER_ERROR);
14890       return;
14891     }
14892   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14893   set_op (disp, 0);
14894   print_operand_value (scratchbuf, 1, disp);
14895   oappend (scratchbuf);
14896 }
14897
14898 static void
14899 OP_SEG (int bytemode, int sizeflag)
14900 {
14901   if (bytemode == w_mode)
14902     oappend (names_seg[modrm.reg]);
14903   else
14904     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14905 }
14906
14907 static void
14908 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14909 {
14910   int seg, offset;
14911
14912   if (sizeflag & DFLAG)
14913     {
14914       offset = get32 ();
14915       seg = get16 ();
14916     }
14917   else
14918     {
14919       offset = get16 ();
14920       seg = get16 ();
14921     }
14922   used_prefixes |= (prefixes & PREFIX_DATA);
14923   if (intel_syntax)
14924     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14925   else
14926     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14927   oappend (scratchbuf);
14928 }
14929
14930 static void
14931 OP_OFF (int bytemode, int sizeflag)
14932 {
14933   bfd_vma off;
14934
14935   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14936     intel_operand_size (bytemode, sizeflag);
14937   append_seg ();
14938
14939   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14940     off = get32 ();
14941   else
14942     off = get16 ();
14943
14944   if (intel_syntax)
14945     {
14946       if (!active_seg_prefix)
14947         {
14948           oappend (names_seg[ds_reg - es_reg]);
14949           oappend (":");
14950         }
14951     }
14952   print_operand_value (scratchbuf, 1, off);
14953   oappend (scratchbuf);
14954 }
14955
14956 static void
14957 OP_OFF64 (int bytemode, int sizeflag)
14958 {
14959   bfd_vma off;
14960
14961   if (address_mode != mode_64bit
14962       || (prefixes & PREFIX_ADDR))
14963     {
14964       OP_OFF (bytemode, sizeflag);
14965       return;
14966     }
14967
14968   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14969     intel_operand_size (bytemode, sizeflag);
14970   append_seg ();
14971
14972   off = get64 ();
14973
14974   if (intel_syntax)
14975     {
14976       if (!active_seg_prefix)
14977         {
14978           oappend (names_seg[ds_reg - es_reg]);
14979           oappend (":");
14980         }
14981     }
14982   print_operand_value (scratchbuf, 1, off);
14983   oappend (scratchbuf);
14984 }
14985
14986 static void
14987 ptr_reg (int code, int sizeflag)
14988 {
14989   const char *s;
14990
14991   *obufp++ = open_char;
14992   used_prefixes |= (prefixes & PREFIX_ADDR);
14993   if (address_mode == mode_64bit)
14994     {
14995       if (!(sizeflag & AFLAG))
14996         s = names32[code - eAX_reg];
14997       else
14998         s = names64[code - eAX_reg];
14999     }
15000   else if (sizeflag & AFLAG)
15001     s = names32[code - eAX_reg];
15002   else
15003     s = names16[code - eAX_reg];
15004   oappend (s);
15005   *obufp++ = close_char;
15006   *obufp = 0;
15007 }
15008
15009 static void
15010 OP_ESreg (int code, int sizeflag)
15011 {
15012   if (intel_syntax)
15013     {
15014       switch (codep[-1])
15015         {
15016         case 0x6d:      /* insw/insl */
15017           intel_operand_size (z_mode, sizeflag);
15018           break;
15019         case 0xa5:      /* movsw/movsl/movsq */
15020         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15021         case 0xab:      /* stosw/stosl */
15022         case 0xaf:      /* scasw/scasl */
15023           intel_operand_size (v_mode, sizeflag);
15024           break;
15025         default:
15026           intel_operand_size (b_mode, sizeflag);
15027         }
15028     }
15029   oappend_maybe_intel ("%es:");
15030   ptr_reg (code, sizeflag);
15031 }
15032
15033 static void
15034 OP_DSreg (int code, int sizeflag)
15035 {
15036   if (intel_syntax)
15037     {
15038       switch (codep[-1])
15039         {
15040         case 0x6f:      /* outsw/outsl */
15041           intel_operand_size (z_mode, sizeflag);
15042           break;
15043         case 0xa5:      /* movsw/movsl/movsq */
15044         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15045         case 0xad:      /* lodsw/lodsl/lodsq */
15046           intel_operand_size (v_mode, sizeflag);
15047           break;
15048         default:
15049           intel_operand_size (b_mode, sizeflag);
15050         }
15051     }
15052   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15053      default segment register DS is printed.  */
15054   if (!active_seg_prefix)
15055     active_seg_prefix = PREFIX_DS;
15056   append_seg ();
15057   ptr_reg (code, sizeflag);
15058 }
15059
15060 static void
15061 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15062 {
15063   int add;
15064   if (rex & REX_R)
15065     {
15066       USED_REX (REX_R);
15067       add = 8;
15068     }
15069   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15070     {
15071       all_prefixes[last_lock_prefix] = 0;
15072       used_prefixes |= PREFIX_LOCK;
15073       add = 8;
15074     }
15075   else
15076     add = 0;
15077   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15078   oappend_maybe_intel (scratchbuf);
15079 }
15080
15081 static void
15082 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15083 {
15084   int add;
15085   USED_REX (REX_R);
15086   if (rex & REX_R)
15087     add = 8;
15088   else
15089     add = 0;
15090   if (intel_syntax)
15091     sprintf (scratchbuf, "db%d", modrm.reg + add);
15092   else
15093     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15094   oappend (scratchbuf);
15095 }
15096
15097 static void
15098 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15099 {
15100   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15101   oappend_maybe_intel (scratchbuf);
15102 }
15103
15104 static void
15105 OP_R (int bytemode, int sizeflag)
15106 {
15107   /* Skip mod/rm byte.  */
15108   MODRM_CHECK;
15109   codep++;
15110   OP_E_register (bytemode, sizeflag);
15111 }
15112
15113 static void
15114 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15115 {
15116   int reg = modrm.reg;
15117   const char **names;
15118
15119   used_prefixes |= (prefixes & PREFIX_DATA);
15120   if (prefixes & PREFIX_DATA)
15121     {
15122       names = names_xmm;
15123       USED_REX (REX_R);
15124       if (rex & REX_R)
15125         reg += 8;
15126     }
15127   else
15128     names = names_mm;
15129   oappend (names[reg]);
15130 }
15131
15132 static void
15133 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15134 {
15135   int reg = modrm.reg;
15136   const char **names;
15137
15138   USED_REX (REX_R);
15139   if (rex & REX_R)
15140     reg += 8;
15141   if (vex.evex)
15142     {
15143       if (!vex.r)
15144         reg += 16;
15145     }
15146
15147   if (need_vex
15148       && bytemode != xmm_mode
15149       && bytemode != xmmq_mode
15150       && bytemode != evex_half_bcst_xmmq_mode
15151       && bytemode != ymm_mode
15152       && bytemode != scalar_mode)
15153     {
15154       switch (vex.length)
15155         {
15156         case 128:
15157           names = names_xmm;
15158           break;
15159         case 256:
15160           if (vex.w
15161               || (bytemode != vex_vsib_q_w_dq_mode
15162                   && bytemode != vex_vsib_q_w_d_mode))
15163             names = names_ymm;
15164           else
15165             names = names_xmm;
15166           break;
15167         case 512:
15168           names = names_zmm;
15169           break;
15170         default:
15171           abort ();
15172         }
15173     }
15174   else if (bytemode == xmmq_mode
15175            || bytemode == evex_half_bcst_xmmq_mode)
15176     {
15177       switch (vex.length)
15178         {
15179         case 128:
15180         case 256:
15181           names = names_xmm;
15182           break;
15183         case 512:
15184           names = names_ymm;
15185           break;
15186         default:
15187           abort ();
15188         }
15189     }
15190   else if (bytemode == ymm_mode)
15191     names = names_ymm;
15192   else
15193     names = names_xmm;
15194   oappend (names[reg]);
15195 }
15196
15197 static void
15198 OP_EM (int bytemode, int sizeflag)
15199 {
15200   int reg;
15201   const char **names;
15202
15203   if (modrm.mod != 3)
15204     {
15205       if (intel_syntax
15206           && (bytemode == v_mode || bytemode == v_swap_mode))
15207         {
15208           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15209           used_prefixes |= (prefixes & PREFIX_DATA);
15210         }
15211       OP_E (bytemode, sizeflag);
15212       return;
15213     }
15214
15215   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15216     swap_operand ();
15217
15218   /* Skip mod/rm byte.  */
15219   MODRM_CHECK;
15220   codep++;
15221   used_prefixes |= (prefixes & PREFIX_DATA);
15222   reg = modrm.rm;
15223   if (prefixes & PREFIX_DATA)
15224     {
15225       names = names_xmm;
15226       USED_REX (REX_B);
15227       if (rex & REX_B)
15228         reg += 8;
15229     }
15230   else
15231     names = names_mm;
15232   oappend (names[reg]);
15233 }
15234
15235 /* cvt* are the only instructions in sse2 which have
15236    both SSE and MMX operands and also have 0x66 prefix
15237    in their opcode. 0x66 was originally used to differentiate
15238    between SSE and MMX instruction(operands). So we have to handle the
15239    cvt* separately using OP_EMC and OP_MXC */
15240 static void
15241 OP_EMC (int bytemode, int sizeflag)
15242 {
15243   if (modrm.mod != 3)
15244     {
15245       if (intel_syntax && bytemode == v_mode)
15246         {
15247           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15248           used_prefixes |= (prefixes & PREFIX_DATA);
15249         }
15250       OP_E (bytemode, sizeflag);
15251       return;
15252     }
15253
15254   /* Skip mod/rm byte.  */
15255   MODRM_CHECK;
15256   codep++;
15257   used_prefixes |= (prefixes & PREFIX_DATA);
15258   oappend (names_mm[modrm.rm]);
15259 }
15260
15261 static void
15262 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15263 {
15264   used_prefixes |= (prefixes & PREFIX_DATA);
15265   oappend (names_mm[modrm.reg]);
15266 }
15267
15268 static void
15269 OP_EX (int bytemode, int sizeflag)
15270 {
15271   int reg;
15272   const char **names;
15273
15274   /* Skip mod/rm byte.  */
15275   MODRM_CHECK;
15276   codep++;
15277
15278   if (modrm.mod != 3)
15279     {
15280       OP_E_memory (bytemode, sizeflag);
15281       return;
15282     }
15283
15284   reg = modrm.rm;
15285   USED_REX (REX_B);
15286   if (rex & REX_B)
15287     reg += 8;
15288   if (vex.evex)
15289     {
15290       USED_REX (REX_X);
15291       if ((rex & REX_X))
15292         reg += 16;
15293     }
15294
15295   if ((sizeflag & SUFFIX_ALWAYS)
15296       && (bytemode == x_swap_mode
15297           || bytemode == d_swap_mode
15298           || bytemode == d_scalar_swap_mode
15299           || bytemode == q_swap_mode
15300           || bytemode == q_scalar_swap_mode))
15301     swap_operand ();
15302
15303   if (need_vex
15304       && bytemode != xmm_mode
15305       && bytemode != xmmdw_mode
15306       && bytemode != xmmqd_mode
15307       && bytemode != xmm_mb_mode
15308       && bytemode != xmm_mw_mode
15309       && bytemode != xmm_md_mode
15310       && bytemode != xmm_mq_mode
15311       && bytemode != xmm_mdq_mode
15312       && bytemode != xmmq_mode
15313       && bytemode != evex_half_bcst_xmmq_mode
15314       && bytemode != ymm_mode
15315       && bytemode != d_scalar_mode
15316       && bytemode != d_scalar_swap_mode
15317       && bytemode != q_scalar_mode
15318       && bytemode != q_scalar_swap_mode
15319       && bytemode != vex_scalar_w_dq_mode)
15320     {
15321       switch (vex.length)
15322         {
15323         case 128:
15324           names = names_xmm;
15325           break;
15326         case 256:
15327           names = names_ymm;
15328           break;
15329         case 512:
15330           names = names_zmm;
15331           break;
15332         default:
15333           abort ();
15334         }
15335     }
15336   else if (bytemode == xmmq_mode
15337            || bytemode == evex_half_bcst_xmmq_mode)
15338     {
15339       switch (vex.length)
15340         {
15341         case 128:
15342         case 256:
15343           names = names_xmm;
15344           break;
15345         case 512:
15346           names = names_ymm;
15347           break;
15348         default:
15349           abort ();
15350         }
15351     }
15352   else if (bytemode == ymm_mode)
15353     names = names_ymm;
15354   else
15355     names = names_xmm;
15356   oappend (names[reg]);
15357 }
15358
15359 static void
15360 OP_MS (int bytemode, int sizeflag)
15361 {
15362   if (modrm.mod == 3)
15363     OP_EM (bytemode, sizeflag);
15364   else
15365     BadOp ();
15366 }
15367
15368 static void
15369 OP_XS (int bytemode, int sizeflag)
15370 {
15371   if (modrm.mod == 3)
15372     OP_EX (bytemode, sizeflag);
15373   else
15374     BadOp ();
15375 }
15376
15377 static void
15378 OP_M (int bytemode, int sizeflag)
15379 {
15380   if (modrm.mod == 3)
15381     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15382     BadOp ();
15383   else
15384     OP_E (bytemode, sizeflag);
15385 }
15386
15387 static void
15388 OP_0f07 (int bytemode, int sizeflag)
15389 {
15390   if (modrm.mod != 3 || modrm.rm != 0)
15391     BadOp ();
15392   else
15393     OP_E (bytemode, sizeflag);
15394 }
15395
15396 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15397    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15398
15399 static void
15400 NOP_Fixup1 (int bytemode, int sizeflag)
15401 {
15402   if ((prefixes & PREFIX_DATA) != 0
15403       || (rex != 0
15404           && rex != 0x48
15405           && address_mode == mode_64bit))
15406     OP_REG (bytemode, sizeflag);
15407   else
15408     strcpy (obuf, "nop");
15409 }
15410
15411 static void
15412 NOP_Fixup2 (int bytemode, int sizeflag)
15413 {
15414   if ((prefixes & PREFIX_DATA) != 0
15415       || (rex != 0
15416           && rex != 0x48
15417           && address_mode == mode_64bit))
15418     OP_IMREG (bytemode, sizeflag);
15419 }
15420
15421 static const char *const Suffix3DNow[] = {
15422 /* 00 */        NULL,           NULL,           NULL,           NULL,
15423 /* 04 */        NULL,           NULL,           NULL,           NULL,
15424 /* 08 */        NULL,           NULL,           NULL,           NULL,
15425 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15426 /* 10 */        NULL,           NULL,           NULL,           NULL,
15427 /* 14 */        NULL,           NULL,           NULL,           NULL,
15428 /* 18 */        NULL,           NULL,           NULL,           NULL,
15429 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15430 /* 20 */        NULL,           NULL,           NULL,           NULL,
15431 /* 24 */        NULL,           NULL,           NULL,           NULL,
15432 /* 28 */        NULL,           NULL,           NULL,           NULL,
15433 /* 2C */        NULL,           NULL,           NULL,           NULL,
15434 /* 30 */        NULL,           NULL,           NULL,           NULL,
15435 /* 34 */        NULL,           NULL,           NULL,           NULL,
15436 /* 38 */        NULL,           NULL,           NULL,           NULL,
15437 /* 3C */        NULL,           NULL,           NULL,           NULL,
15438 /* 40 */        NULL,           NULL,           NULL,           NULL,
15439 /* 44 */        NULL,           NULL,           NULL,           NULL,
15440 /* 48 */        NULL,           NULL,           NULL,           NULL,
15441 /* 4C */        NULL,           NULL,           NULL,           NULL,
15442 /* 50 */        NULL,           NULL,           NULL,           NULL,
15443 /* 54 */        NULL,           NULL,           NULL,           NULL,
15444 /* 58 */        NULL,           NULL,           NULL,           NULL,
15445 /* 5C */        NULL,           NULL,           NULL,           NULL,
15446 /* 60 */        NULL,           NULL,           NULL,           NULL,
15447 /* 64 */        NULL,           NULL,           NULL,           NULL,
15448 /* 68 */        NULL,           NULL,           NULL,           NULL,
15449 /* 6C */        NULL,           NULL,           NULL,           NULL,
15450 /* 70 */        NULL,           NULL,           NULL,           NULL,
15451 /* 74 */        NULL,           NULL,           NULL,           NULL,
15452 /* 78 */        NULL,           NULL,           NULL,           NULL,
15453 /* 7C */        NULL,           NULL,           NULL,           NULL,
15454 /* 80 */        NULL,           NULL,           NULL,           NULL,
15455 /* 84 */        NULL,           NULL,           NULL,           NULL,
15456 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15457 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15458 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15459 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15460 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15461 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15462 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15463 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15464 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15465 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15466 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15467 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15468 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15469 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15470 /* C0 */        NULL,           NULL,           NULL,           NULL,
15471 /* C4 */        NULL,           NULL,           NULL,           NULL,
15472 /* C8 */        NULL,           NULL,           NULL,           NULL,
15473 /* CC */        NULL,           NULL,           NULL,           NULL,
15474 /* D0 */        NULL,           NULL,           NULL,           NULL,
15475 /* D4 */        NULL,           NULL,           NULL,           NULL,
15476 /* D8 */        NULL,           NULL,           NULL,           NULL,
15477 /* DC */        NULL,           NULL,           NULL,           NULL,
15478 /* E0 */        NULL,           NULL,           NULL,           NULL,
15479 /* E4 */        NULL,           NULL,           NULL,           NULL,
15480 /* E8 */        NULL,           NULL,           NULL,           NULL,
15481 /* EC */        NULL,           NULL,           NULL,           NULL,
15482 /* F0 */        NULL,           NULL,           NULL,           NULL,
15483 /* F4 */        NULL,           NULL,           NULL,           NULL,
15484 /* F8 */        NULL,           NULL,           NULL,           NULL,
15485 /* FC */        NULL,           NULL,           NULL,           NULL,
15486 };
15487
15488 static void
15489 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15490 {
15491   const char *mnemonic;
15492
15493   FETCH_DATA (the_info, codep + 1);
15494   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15495      place where an 8-bit immediate would normally go.  ie. the last
15496      byte of the instruction.  */
15497   obufp = mnemonicendp;
15498   mnemonic = Suffix3DNow[*codep++ & 0xff];
15499   if (mnemonic)
15500     oappend (mnemonic);
15501   else
15502     {
15503       /* Since a variable sized modrm/sib chunk is between the start
15504          of the opcode (0x0f0f) and the opcode suffix, we need to do
15505          all the modrm processing first, and don't know until now that
15506          we have a bad opcode.  This necessitates some cleaning up.  */
15507       op_out[0][0] = '\0';
15508       op_out[1][0] = '\0';
15509       BadOp ();
15510     }
15511   mnemonicendp = obufp;
15512 }
15513
15514 static struct op simd_cmp_op[] =
15515 {
15516   { STRING_COMMA_LEN ("eq") },
15517   { STRING_COMMA_LEN ("lt") },
15518   { STRING_COMMA_LEN ("le") },
15519   { STRING_COMMA_LEN ("unord") },
15520   { STRING_COMMA_LEN ("neq") },
15521   { STRING_COMMA_LEN ("nlt") },
15522   { STRING_COMMA_LEN ("nle") },
15523   { STRING_COMMA_LEN ("ord") }
15524 };
15525
15526 static void
15527 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15528 {
15529   unsigned int cmp_type;
15530
15531   FETCH_DATA (the_info, codep + 1);
15532   cmp_type = *codep++ & 0xff;
15533   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15534     {
15535       char suffix [3];
15536       char *p = mnemonicendp - 2;
15537       suffix[0] = p[0];
15538       suffix[1] = p[1];
15539       suffix[2] = '\0';
15540       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15541       mnemonicendp += simd_cmp_op[cmp_type].len;
15542     }
15543   else
15544     {
15545       /* We have a reserved extension byte.  Output it directly.  */
15546       scratchbuf[0] = '$';
15547       print_operand_value (scratchbuf + 1, 1, cmp_type);
15548       oappend_maybe_intel (scratchbuf);
15549       scratchbuf[0] = '\0';
15550     }
15551 }
15552
15553 static void
15554 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15555           int sizeflag ATTRIBUTE_UNUSED)
15556 {
15557   /* mwaitx %eax,%ecx,%ebx */
15558   if (!intel_syntax)
15559     {
15560       const char **names = (address_mode == mode_64bit
15561                             ? names64 : names32);
15562       strcpy (op_out[0], names[0]);
15563       strcpy (op_out[1], names[1]);
15564       strcpy (op_out[2], names[3]);
15565       two_source_ops = 1;
15566     }
15567   /* Skip mod/rm byte.  */
15568   MODRM_CHECK;
15569   codep++;
15570 }
15571
15572 static void
15573 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15574           int sizeflag ATTRIBUTE_UNUSED)
15575 {
15576   /* mwait %eax,%ecx  */
15577   if (!intel_syntax)
15578     {
15579       const char **names = (address_mode == mode_64bit
15580                             ? names64 : names32);
15581       strcpy (op_out[0], names[0]);
15582       strcpy (op_out[1], names[1]);
15583       two_source_ops = 1;
15584     }
15585   /* Skip mod/rm byte.  */
15586   MODRM_CHECK;
15587   codep++;
15588 }
15589
15590 static void
15591 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15592             int sizeflag ATTRIBUTE_UNUSED)
15593 {
15594   /* monitor %eax,%ecx,%edx"  */
15595   if (!intel_syntax)
15596     {
15597       const char **op1_names;
15598       const char **names = (address_mode == mode_64bit
15599                             ? names64 : names32);
15600
15601       if (!(prefixes & PREFIX_ADDR))
15602         op1_names = (address_mode == mode_16bit
15603                      ? names16 : names);
15604       else
15605         {
15606           /* Remove "addr16/addr32".  */
15607           all_prefixes[last_addr_prefix] = 0;
15608           op1_names = (address_mode != mode_32bit
15609                        ? names32 : names16);
15610           used_prefixes |= PREFIX_ADDR;
15611         }
15612       strcpy (op_out[0], op1_names[0]);
15613       strcpy (op_out[1], names[1]);
15614       strcpy (op_out[2], names[2]);
15615       two_source_ops = 1;
15616     }
15617   /* Skip mod/rm byte.  */
15618   MODRM_CHECK;
15619   codep++;
15620 }
15621
15622 static void
15623 BadOp (void)
15624 {
15625   /* Throw away prefixes and 1st. opcode byte.  */
15626   codep = insn_codep + 1;
15627   oappend ("(bad)");
15628 }
15629
15630 static void
15631 REP_Fixup (int bytemode, int sizeflag)
15632 {
15633   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15634      lods and stos.  */
15635   if (prefixes & PREFIX_REPZ)
15636     all_prefixes[last_repz_prefix] = REP_PREFIX;
15637
15638   switch (bytemode)
15639     {
15640     case al_reg:
15641     case eAX_reg:
15642     case indir_dx_reg:
15643       OP_IMREG (bytemode, sizeflag);
15644       break;
15645     case eDI_reg:
15646       OP_ESreg (bytemode, sizeflag);
15647       break;
15648     case eSI_reg:
15649       OP_DSreg (bytemode, sizeflag);
15650       break;
15651     default:
15652       abort ();
15653       break;
15654     }
15655 }
15656
15657 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15658    "bnd".  */
15659
15660 static void
15661 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15662 {
15663   if (prefixes & PREFIX_REPNZ)
15664     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15665 }
15666
15667 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15668    "notrack".  */
15669
15670 static void
15671 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15672                int sizeflag ATTRIBUTE_UNUSED)
15673 {
15674   if (active_seg_prefix == PREFIX_DS
15675       && (address_mode != mode_64bit || last_data_prefix < 0))
15676     {
15677       /* NOTRACK prefix is only valid on indirect branch instructions.
15678          NB: DATA prefix is unsupported for Intel64.  */
15679       active_seg_prefix = 0;
15680       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15681     }
15682 }
15683
15684 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15685    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15686  */
15687
15688 static void
15689 HLE_Fixup1 (int bytemode, int sizeflag)
15690 {
15691   if (modrm.mod != 3
15692       && (prefixes & PREFIX_LOCK) != 0)
15693     {
15694       if (prefixes & PREFIX_REPZ)
15695         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15696       if (prefixes & PREFIX_REPNZ)
15697         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15698     }
15699
15700   OP_E (bytemode, sizeflag);
15701 }
15702
15703 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15704    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15705  */
15706
15707 static void
15708 HLE_Fixup2 (int bytemode, int sizeflag)
15709 {
15710   if (modrm.mod != 3)
15711     {
15712       if (prefixes & PREFIX_REPZ)
15713         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15714       if (prefixes & PREFIX_REPNZ)
15715         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15716     }
15717
15718   OP_E (bytemode, sizeflag);
15719 }
15720
15721 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15722    "xrelease" for memory operand.  No check for LOCK prefix.   */
15723
15724 static void
15725 HLE_Fixup3 (int bytemode, int sizeflag)
15726 {
15727   if (modrm.mod != 3
15728       && last_repz_prefix > last_repnz_prefix
15729       && (prefixes & PREFIX_REPZ) != 0)
15730     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15731
15732   OP_E (bytemode, sizeflag);
15733 }
15734
15735 static void
15736 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15737 {
15738   USED_REX (REX_W);
15739   if (rex & REX_W)
15740     {
15741       /* Change cmpxchg8b to cmpxchg16b.  */
15742       char *p = mnemonicendp - 2;
15743       mnemonicendp = stpcpy (p, "16b");
15744       bytemode = o_mode;
15745     }
15746   else if ((prefixes & PREFIX_LOCK) != 0)
15747     {
15748       if (prefixes & PREFIX_REPZ)
15749         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15750       if (prefixes & PREFIX_REPNZ)
15751         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15752     }
15753
15754   OP_M (bytemode, sizeflag);
15755 }
15756
15757 static void
15758 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15759 {
15760   const char **names;
15761
15762   if (need_vex)
15763     {
15764       switch (vex.length)
15765         {
15766         case 128:
15767           names = names_xmm;
15768           break;
15769         case 256:
15770           names = names_ymm;
15771           break;
15772         default:
15773           abort ();
15774         }
15775     }
15776   else
15777     names = names_xmm;
15778   oappend (names[reg]);
15779 }
15780
15781 static void
15782 CRC32_Fixup (int bytemode, int sizeflag)
15783 {
15784   /* Add proper suffix to "crc32".  */
15785   char *p = mnemonicendp;
15786
15787   switch (bytemode)
15788     {
15789     case b_mode:
15790       if (intel_syntax)
15791         goto skip;
15792
15793       *p++ = 'b';
15794       break;
15795     case v_mode:
15796       if (intel_syntax)
15797         goto skip;
15798
15799       USED_REX (REX_W);
15800       if (rex & REX_W)
15801         *p++ = 'q';
15802       else
15803         {
15804           if (sizeflag & DFLAG)
15805             *p++ = 'l';
15806           else
15807             *p++ = 'w';
15808           used_prefixes |= (prefixes & PREFIX_DATA);
15809         }
15810       break;
15811     default:
15812       oappend (INTERNAL_DISASSEMBLER_ERROR);
15813       break;
15814     }
15815   mnemonicendp = p;
15816   *p = '\0';
15817
15818 skip:
15819   if (modrm.mod == 3)
15820     {
15821       int add;
15822
15823       /* Skip mod/rm byte.  */
15824       MODRM_CHECK;
15825       codep++;
15826
15827       USED_REX (REX_B);
15828       add = (rex & REX_B) ? 8 : 0;
15829       if (bytemode == b_mode)
15830         {
15831           USED_REX (0);
15832           if (rex)
15833             oappend (names8rex[modrm.rm + add]);
15834           else
15835             oappend (names8[modrm.rm + add]);
15836         }
15837       else
15838         {
15839           USED_REX (REX_W);
15840           if (rex & REX_W)
15841             oappend (names64[modrm.rm + add]);
15842           else if ((prefixes & PREFIX_DATA))
15843             oappend (names16[modrm.rm + add]);
15844           else
15845             oappend (names32[modrm.rm + add]);
15846         }
15847     }
15848   else
15849     OP_E (bytemode, sizeflag);
15850 }
15851
15852 static void
15853 FXSAVE_Fixup (int bytemode, int sizeflag)
15854 {
15855   /* Add proper suffix to "fxsave" and "fxrstor".  */
15856   USED_REX (REX_W);
15857   if (rex & REX_W)
15858     {
15859       char *p = mnemonicendp;
15860       *p++ = '6';
15861       *p++ = '4';
15862       *p = '\0';
15863       mnemonicendp = p;
15864     }
15865   OP_M (bytemode, sizeflag);
15866 }
15867
15868 static void
15869 PCMPESTR_Fixup (int bytemode, int sizeflag)
15870 {
15871   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15872   if (!intel_syntax)
15873     {
15874       char *p = mnemonicendp;
15875
15876       USED_REX (REX_W);
15877       if (rex & REX_W)
15878         *p++ = 'q';
15879       else if (sizeflag & SUFFIX_ALWAYS)
15880         *p++ = 'l';
15881
15882       *p = '\0';
15883       mnemonicendp = p;
15884     }
15885
15886   OP_EX (bytemode, sizeflag);
15887 }
15888
15889 /* Display the destination register operand for instructions with
15890    VEX. */
15891
15892 static void
15893 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15894 {
15895   int reg;
15896   const char **names;
15897
15898   if (!need_vex)
15899     abort ();
15900
15901   if (!need_vex_reg)
15902     return;
15903
15904   reg = vex.register_specifier;
15905   vex.register_specifier = 0;
15906   if (address_mode != mode_64bit)
15907     reg &= 7;
15908   else if (vex.evex && !vex.v)
15909     reg += 16;
15910
15911   if (bytemode == vex_scalar_mode)
15912     {
15913       oappend (names_xmm[reg]);
15914       return;
15915     }
15916
15917   switch (vex.length)
15918     {
15919     case 128:
15920       switch (bytemode)
15921         {
15922         case vex_mode:
15923         case vex128_mode:
15924         case vex_vsib_q_w_dq_mode:
15925         case vex_vsib_q_w_d_mode:
15926           names = names_xmm;
15927           break;
15928         case dq_mode:
15929           if (rex & REX_W)
15930             names = names64;
15931           else
15932             names = names32;
15933           break;
15934         case mask_bd_mode:
15935         case mask_mode:
15936           if (reg > 0x7)
15937             {
15938               oappend ("(bad)");
15939               return;
15940             }
15941           names = names_mask;
15942           break;
15943         default:
15944           abort ();
15945           return;
15946         }
15947       break;
15948     case 256:
15949       switch (bytemode)
15950         {
15951         case vex_mode:
15952         case vex256_mode:
15953           names = names_ymm;
15954           break;
15955         case vex_vsib_q_w_dq_mode:
15956         case vex_vsib_q_w_d_mode:
15957           names = vex.w ? names_ymm : names_xmm;
15958           break;
15959         case mask_bd_mode:
15960         case mask_mode:
15961           if (reg > 0x7)
15962             {
15963               oappend ("(bad)");
15964               return;
15965             }
15966           names = names_mask;
15967           break;
15968         default:
15969           /* See PR binutils/20893 for a reproducer.  */
15970           oappend ("(bad)");
15971           return;
15972         }
15973       break;
15974     case 512:
15975       names = names_zmm;
15976       break;
15977     default:
15978       abort ();
15979       break;
15980     }
15981   oappend (names[reg]);
15982 }
15983
15984 /* Get the VEX immediate byte without moving codep.  */
15985
15986 static unsigned char
15987 get_vex_imm8 (int sizeflag, int opnum)
15988 {
15989   int bytes_before_imm = 0;
15990
15991   if (modrm.mod != 3)
15992     {
15993       /* There are SIB/displacement bytes.  */
15994       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15995         {
15996           /* 32/64 bit address mode */
15997           int base = modrm.rm;
15998
15999           /* Check SIB byte.  */
16000           if (base == 4)
16001             {
16002               FETCH_DATA (the_info, codep + 1);
16003               base = *codep & 7;
16004               /* When decoding the third source, don't increase
16005                  bytes_before_imm as this has already been incremented
16006                  by one in OP_E_memory while decoding the second
16007                  source operand.  */
16008               if (opnum == 0)
16009                 bytes_before_imm++;
16010             }
16011
16012           /* Don't increase bytes_before_imm when decoding the third source,
16013              it has already been incremented by OP_E_memory while decoding
16014              the second source operand.  */
16015           if (opnum == 0)
16016             {
16017               switch (modrm.mod)
16018                 {
16019                   case 0:
16020                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16021                        SIB == 5, there is a 4 byte displacement.  */
16022                     if (base != 5)
16023                       /* No displacement. */
16024                       break;
16025                     /* Fall through.  */
16026                   case 2:
16027                     /* 4 byte displacement.  */
16028                     bytes_before_imm += 4;
16029                     break;
16030                   case 1:
16031                     /* 1 byte displacement.  */
16032                     bytes_before_imm++;
16033                     break;
16034                 }
16035             }
16036         }
16037       else
16038         {
16039           /* 16 bit address mode */
16040           /* Don't increase bytes_before_imm when decoding the third source,
16041              it has already been incremented by OP_E_memory while decoding
16042              the second source operand.  */
16043           if (opnum == 0)
16044             {
16045               switch (modrm.mod)
16046                 {
16047                 case 0:
16048                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16049                   if (modrm.rm != 6)
16050                     /* No displacement. */
16051                     break;
16052                   /* Fall through.  */
16053                 case 2:
16054                   /* 2 byte displacement.  */
16055                   bytes_before_imm += 2;
16056                   break;
16057                 case 1:
16058                   /* 1 byte displacement: when decoding the third source,
16059                      don't increase bytes_before_imm as this has already
16060                      been incremented by one in OP_E_memory while decoding
16061                      the second source operand.  */
16062                   if (opnum == 0)
16063                     bytes_before_imm++;
16064
16065                   break;
16066                 }
16067             }
16068         }
16069     }
16070
16071   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16072   return codep [bytes_before_imm];
16073 }
16074
16075 static void
16076 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16077 {
16078   const char **names;
16079
16080   if (reg == -1 && modrm.mod != 3)
16081     {
16082       OP_E_memory (bytemode, sizeflag);
16083       return;
16084     }
16085   else
16086     {
16087       if (reg == -1)
16088         {
16089           reg = modrm.rm;
16090           USED_REX (REX_B);
16091           if (rex & REX_B)
16092             reg += 8;
16093         }
16094       if (address_mode != mode_64bit)
16095         reg &= 7;
16096     }
16097
16098   switch (vex.length)
16099     {
16100     case 128:
16101       names = names_xmm;
16102       break;
16103     case 256:
16104       names = names_ymm;
16105       break;
16106     default:
16107       abort ();
16108     }
16109   oappend (names[reg]);
16110 }
16111
16112 static void
16113 OP_EX_VexImmW (int bytemode, int sizeflag)
16114 {
16115   int reg = -1;
16116   static unsigned char vex_imm8;
16117
16118   if (vex_w_done == 0)
16119     {
16120       vex_w_done = 1;
16121
16122       /* Skip mod/rm byte.  */
16123       MODRM_CHECK;
16124       codep++;
16125
16126       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16127
16128       if (vex.w)
16129           reg = vex_imm8 >> 4;
16130
16131       OP_EX_VexReg (bytemode, sizeflag, reg);
16132     }
16133   else if (vex_w_done == 1)
16134     {
16135       vex_w_done = 2;
16136
16137       if (!vex.w)
16138           reg = vex_imm8 >> 4;
16139
16140       OP_EX_VexReg (bytemode, sizeflag, reg);
16141     }
16142   else
16143     {
16144       /* Output the imm8 directly.  */
16145       scratchbuf[0] = '$';
16146       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16147       oappend_maybe_intel (scratchbuf);
16148       scratchbuf[0] = '\0';
16149       codep++;
16150     }
16151 }
16152
16153 static void
16154 OP_Vex_2src (int bytemode, int sizeflag)
16155 {
16156   if (modrm.mod == 3)
16157     {
16158       int reg = modrm.rm;
16159       USED_REX (REX_B);
16160       if (rex & REX_B)
16161         reg += 8;
16162       oappend (names_xmm[reg]);
16163     }
16164   else
16165     {
16166       if (intel_syntax
16167           && (bytemode == v_mode || bytemode == v_swap_mode))
16168         {
16169           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16170           used_prefixes |= (prefixes & PREFIX_DATA);
16171         }
16172       OP_E (bytemode, sizeflag);
16173     }
16174 }
16175
16176 static void
16177 OP_Vex_2src_1 (int bytemode, int sizeflag)
16178 {
16179   if (modrm.mod == 3)
16180     {
16181       /* Skip mod/rm byte.   */
16182       MODRM_CHECK;
16183       codep++;
16184     }
16185
16186   if (vex.w)
16187     {
16188       unsigned int reg = vex.register_specifier;
16189       vex.register_specifier = 0;
16190
16191       if (address_mode != mode_64bit)
16192         reg &= 7;
16193       oappend (names_xmm[reg]);
16194     }
16195   else
16196     OP_Vex_2src (bytemode, sizeflag);
16197 }
16198
16199 static void
16200 OP_Vex_2src_2 (int bytemode, int sizeflag)
16201 {
16202   if (vex.w)
16203     OP_Vex_2src (bytemode, sizeflag);
16204   else
16205     {
16206       unsigned int reg = vex.register_specifier;
16207       vex.register_specifier = 0;
16208
16209       if (address_mode != mode_64bit)
16210         reg &= 7;
16211       oappend (names_xmm[reg]);
16212     }
16213 }
16214
16215 static void
16216 OP_EX_VexW (int bytemode, int sizeflag)
16217 {
16218   int reg = -1;
16219
16220   if (!vex_w_done)
16221     {
16222       /* Skip mod/rm byte.  */
16223       MODRM_CHECK;
16224       codep++;
16225
16226       if (vex.w)
16227         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16228     }
16229   else
16230     {
16231       if (!vex.w)
16232         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16233     }
16234
16235   OP_EX_VexReg (bytemode, sizeflag, reg);
16236
16237   if (vex_w_done)
16238     codep++;
16239   vex_w_done = 1;
16240 }
16241
16242 static void
16243 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16244 {
16245   int reg;
16246   const char **names;
16247
16248   FETCH_DATA (the_info, codep + 1);
16249   reg = *codep++;
16250
16251   if (bytemode != x_mode)
16252     abort ();
16253
16254   reg >>= 4;
16255   if (address_mode != mode_64bit)
16256     reg &= 7;
16257
16258   switch (vex.length)
16259     {
16260     case 128:
16261       names = names_xmm;
16262       break;
16263     case 256:
16264       names = names_ymm;
16265       break;
16266     default:
16267       abort ();
16268     }
16269   oappend (names[reg]);
16270 }
16271
16272 static void
16273 OP_XMM_VexW (int bytemode, int sizeflag)
16274 {
16275   /* Turn off the REX.W bit since it is used for swapping operands
16276      now.  */
16277   rex &= ~REX_W;
16278   OP_XMM (bytemode, sizeflag);
16279 }
16280
16281 static void
16282 OP_EX_Vex (int bytemode, int sizeflag)
16283 {
16284   if (modrm.mod != 3)
16285     need_vex_reg = 0;
16286   OP_EX (bytemode, sizeflag);
16287 }
16288
16289 static void
16290 OP_XMM_Vex (int bytemode, int sizeflag)
16291 {
16292   if (modrm.mod != 3)
16293     need_vex_reg = 0;
16294   OP_XMM (bytemode, sizeflag);
16295 }
16296
16297 static struct op vex_cmp_op[] =
16298 {
16299   { STRING_COMMA_LEN ("eq") },
16300   { STRING_COMMA_LEN ("lt") },
16301   { STRING_COMMA_LEN ("le") },
16302   { STRING_COMMA_LEN ("unord") },
16303   { STRING_COMMA_LEN ("neq") },
16304   { STRING_COMMA_LEN ("nlt") },
16305   { STRING_COMMA_LEN ("nle") },
16306   { STRING_COMMA_LEN ("ord") },
16307   { STRING_COMMA_LEN ("eq_uq") },
16308   { STRING_COMMA_LEN ("nge") },
16309   { STRING_COMMA_LEN ("ngt") },
16310   { STRING_COMMA_LEN ("false") },
16311   { STRING_COMMA_LEN ("neq_oq") },
16312   { STRING_COMMA_LEN ("ge") },
16313   { STRING_COMMA_LEN ("gt") },
16314   { STRING_COMMA_LEN ("true") },
16315   { STRING_COMMA_LEN ("eq_os") },
16316   { STRING_COMMA_LEN ("lt_oq") },
16317   { STRING_COMMA_LEN ("le_oq") },
16318   { STRING_COMMA_LEN ("unord_s") },
16319   { STRING_COMMA_LEN ("neq_us") },
16320   { STRING_COMMA_LEN ("nlt_uq") },
16321   { STRING_COMMA_LEN ("nle_uq") },
16322   { STRING_COMMA_LEN ("ord_s") },
16323   { STRING_COMMA_LEN ("eq_us") },
16324   { STRING_COMMA_LEN ("nge_uq") },
16325   { STRING_COMMA_LEN ("ngt_uq") },
16326   { STRING_COMMA_LEN ("false_os") },
16327   { STRING_COMMA_LEN ("neq_os") },
16328   { STRING_COMMA_LEN ("ge_oq") },
16329   { STRING_COMMA_LEN ("gt_oq") },
16330   { STRING_COMMA_LEN ("true_us") },
16331 };
16332
16333 static void
16334 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16335 {
16336   unsigned int cmp_type;
16337
16338   FETCH_DATA (the_info, codep + 1);
16339   cmp_type = *codep++ & 0xff;
16340   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16341     {
16342       char suffix [3];
16343       char *p = mnemonicendp - 2;
16344       suffix[0] = p[0];
16345       suffix[1] = p[1];
16346       suffix[2] = '\0';
16347       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16348       mnemonicendp += vex_cmp_op[cmp_type].len;
16349     }
16350   else
16351     {
16352       /* We have a reserved extension byte.  Output it directly.  */
16353       scratchbuf[0] = '$';
16354       print_operand_value (scratchbuf + 1, 1, cmp_type);
16355       oappend_maybe_intel (scratchbuf);
16356       scratchbuf[0] = '\0';
16357     }
16358 }
16359
16360 static void
16361 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16362              int sizeflag ATTRIBUTE_UNUSED)
16363 {
16364   unsigned int cmp_type;
16365
16366   if (!vex.evex)
16367     abort ();
16368
16369   FETCH_DATA (the_info, codep + 1);
16370   cmp_type = *codep++ & 0xff;
16371   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16372      If it's the case, print suffix, otherwise - print the immediate.  */
16373   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16374       && cmp_type != 3
16375       && cmp_type != 7)
16376     {
16377       char suffix [3];
16378       char *p = mnemonicendp - 2;
16379
16380       /* vpcmp* can have both one- and two-lettered suffix.  */
16381       if (p[0] == 'p')
16382         {
16383           p++;
16384           suffix[0] = p[0];
16385           suffix[1] = '\0';
16386         }
16387       else
16388         {
16389           suffix[0] = p[0];
16390           suffix[1] = p[1];
16391           suffix[2] = '\0';
16392         }
16393
16394       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16395       mnemonicendp += simd_cmp_op[cmp_type].len;
16396     }
16397   else
16398     {
16399       /* We have a reserved extension byte.  Output it directly.  */
16400       scratchbuf[0] = '$';
16401       print_operand_value (scratchbuf + 1, 1, cmp_type);
16402       oappend_maybe_intel (scratchbuf);
16403       scratchbuf[0] = '\0';
16404     }
16405 }
16406
16407 static const struct op xop_cmp_op[] =
16408 {
16409   { STRING_COMMA_LEN ("lt") },
16410   { STRING_COMMA_LEN ("le") },
16411   { STRING_COMMA_LEN ("gt") },
16412   { STRING_COMMA_LEN ("ge") },
16413   { STRING_COMMA_LEN ("eq") },
16414   { STRING_COMMA_LEN ("neq") },
16415   { STRING_COMMA_LEN ("false") },
16416   { STRING_COMMA_LEN ("true") }
16417 };
16418
16419 static void
16420 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16421              int sizeflag ATTRIBUTE_UNUSED)
16422 {
16423   unsigned int cmp_type;
16424
16425   FETCH_DATA (the_info, codep + 1);
16426   cmp_type = *codep++ & 0xff;
16427   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16428     {
16429       char suffix[3];
16430       char *p = mnemonicendp - 2;
16431
16432       /* vpcom* can have both one- and two-lettered suffix.  */
16433       if (p[0] == 'm')
16434         {
16435           p++;
16436           suffix[0] = p[0];
16437           suffix[1] = '\0';
16438         }
16439       else
16440         {
16441           suffix[0] = p[0];
16442           suffix[1] = p[1];
16443           suffix[2] = '\0';
16444         }
16445
16446       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16447       mnemonicendp += xop_cmp_op[cmp_type].len;
16448     }
16449   else
16450     {
16451       /* We have a reserved extension byte.  Output it directly.  */
16452       scratchbuf[0] = '$';
16453       print_operand_value (scratchbuf + 1, 1, cmp_type);
16454       oappend_maybe_intel (scratchbuf);
16455       scratchbuf[0] = '\0';
16456     }
16457 }
16458
16459 static const struct op pclmul_op[] =
16460 {
16461   { STRING_COMMA_LEN ("lql") },
16462   { STRING_COMMA_LEN ("hql") },
16463   { STRING_COMMA_LEN ("lqh") },
16464   { STRING_COMMA_LEN ("hqh") }
16465 };
16466
16467 static void
16468 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16469               int sizeflag ATTRIBUTE_UNUSED)
16470 {
16471   unsigned int pclmul_type;
16472
16473   FETCH_DATA (the_info, codep + 1);
16474   pclmul_type = *codep++ & 0xff;
16475   switch (pclmul_type)
16476     {
16477     case 0x10:
16478       pclmul_type = 2;
16479       break;
16480     case 0x11:
16481       pclmul_type = 3;
16482       break;
16483     default:
16484       break;
16485     }
16486   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16487     {
16488       char suffix [4];
16489       char *p = mnemonicendp - 3;
16490       suffix[0] = p[0];
16491       suffix[1] = p[1];
16492       suffix[2] = p[2];
16493       suffix[3] = '\0';
16494       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16495       mnemonicendp += pclmul_op[pclmul_type].len;
16496     }
16497   else
16498     {
16499       /* We have a reserved extension byte.  Output it directly.  */
16500       scratchbuf[0] = '$';
16501       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16502       oappend_maybe_intel (scratchbuf);
16503       scratchbuf[0] = '\0';
16504     }
16505 }
16506
16507 static void
16508 MOVBE_Fixup (int bytemode, int sizeflag)
16509 {
16510   /* Add proper suffix to "movbe".  */
16511   char *p = mnemonicendp;
16512
16513   switch (bytemode)
16514     {
16515     case v_mode:
16516       if (intel_syntax)
16517         goto skip;
16518
16519       USED_REX (REX_W);
16520       if (sizeflag & SUFFIX_ALWAYS)
16521         {
16522           if (rex & REX_W)
16523             *p++ = 'q';
16524           else
16525             {
16526               if (sizeflag & DFLAG)
16527                 *p++ = 'l';
16528               else
16529                 *p++ = 'w';
16530               used_prefixes |= (prefixes & PREFIX_DATA);
16531             }
16532         }
16533       break;
16534     default:
16535       oappend (INTERNAL_DISASSEMBLER_ERROR);
16536       break;
16537     }
16538   mnemonicendp = p;
16539   *p = '\0';
16540
16541 skip:
16542   OP_M (bytemode, sizeflag);
16543 }
16544
16545 static void
16546 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16547 {
16548   int reg;
16549   const char **names;
16550
16551   /* Skip mod/rm byte.  */
16552   MODRM_CHECK;
16553   codep++;
16554
16555   if (rex & REX_W)
16556     names = names64;
16557   else
16558     names = names32;
16559
16560   reg = modrm.rm;
16561   USED_REX (REX_B);
16562   if (rex & REX_B)
16563     reg += 8;
16564
16565   oappend (names[reg]);
16566 }
16567
16568 static void
16569 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16570 {
16571   const char **names;
16572   unsigned int reg = vex.register_specifier;
16573   vex.register_specifier = 0;
16574
16575   if (rex & REX_W)
16576     names = names64;
16577   else
16578     names = names32;
16579
16580   if (address_mode != mode_64bit)
16581     reg &= 7;
16582   oappend (names[reg]);
16583 }
16584
16585 static void
16586 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16587 {
16588   if (!vex.evex
16589       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16590     abort ();
16591
16592   USED_REX (REX_R);
16593   if ((rex & REX_R) != 0 || !vex.r)
16594     {
16595       BadOp ();
16596       return;
16597     }
16598
16599   oappend (names_mask [modrm.reg]);
16600 }
16601
16602 static void
16603 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16604 {
16605   if (!vex.evex
16606       || (bytemode != evex_rounding_mode
16607           && bytemode != evex_rounding_64_mode
16608           && bytemode != evex_sae_mode))
16609     abort ();
16610   if (modrm.mod == 3 && vex.b)
16611     switch (bytemode)
16612       {
16613       case evex_rounding_64_mode:
16614         if (address_mode != mode_64bit)
16615           {
16616             oappend ("(bad)");
16617             break;
16618           }
16619         /* Fall through.  */
16620       case evex_rounding_mode:
16621         oappend (names_rounding[vex.ll]);
16622         break;
16623       case evex_sae_mode:
16624         oappend ("{sae}");
16625         break;
16626       default:
16627         break;
16628       }
16629 }