opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define EbndS { OP_E, bnd_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Eva { OP_E, va_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mv_bnd { OP_M, v_bndmk_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gva { OP_G, va_mode }
 284 #define Gw { OP_G, w_mode }
 285 #define Rd { OP_R, d_mode }
 286 #define Rdq { OP_R, dq_mode }
 287 #define Rm { OP_R, m_mode }
 288 #define Ib { OP_I, b_mode }
 289 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 291 #define Iv { OP_I, v_mode }
 292 #define sIv { OP_sI, v_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Id { OP_I, d_mode }
 295 #define Iw { OP_I, w_mode }
 296 #define I1 { OP_I, const_1_mode }
 297 #define Jb { OP_J, b_mode }
 298 #define Jv { OP_J, v_mode }
 299 #define Jdqw { OP_J, dqw_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define SEP { SEP_Fixup, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 433 #define XMVexW { OP_XMM_VexW, 0 }
 434 #define XMVexI4 { OP_REG_VexI4, x_mode }
 435 #define PCLMUL { PCLMUL_Fixup, 0 }
 436 #define VCMP { VCMP_Fixup, 0 }
 437 #define VPCMP { VPCMP_Fixup, 0 }
 438 #define VPCOM { VPCOM_Fixup, 0 }
 439
 440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 441 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475 #define NOTRACK { NOTRACK_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* operand size depends on address prefix */
 498   va_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   movsxd_mode,
 554   v_bnd_mode,
 555   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 556   v_bndmk_mode,
 557   /* operand size depends on REX prefixes.  */
 558   dq_mode,
 559   /* registers like dq_mode, memory like w_mode, displacements like
 560      v_mode without considering Intel64 ISA.  */
 561   dqw_mode,
 562   /* bounds operand */
 563   bnd_mode,
 564   /* bounds operand with operand swapped */
 565   bnd_swap_mode,
 566   /* 4- or 6-byte pointer operand */
 567   f_mode,
 568   const_1_mode,
 569   /* v_mode for indirect branch opcodes.  */
 570   indir_v_mode,
 571   /* v_mode for stack-related opcodes.  */
 572   stack_v_mode,
 573   /* non-quad operand size depends on prefixes */
 574   z_mode,
 575   /* 16-byte operand */
 576   o_mode,
 577   /* registers like dq_mode, memory like b_mode.  */
 578   dqb_mode,
 579   /* registers like d_mode, memory like b_mode.  */
 580   db_mode,
 581   /* registers like d_mode, memory like w_mode.  */
 582   dw_mode,
 583   /* registers like dq_mode, memory like d_mode.  */
 584   dqd_mode,
 585   /* normal vex mode */
 586   vex_mode,
 587   /* 128bit vex mode */
 588   vex128_mode,
 589   /* 256bit vex mode */
 590   vex256_mode,
 591
 592   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Static rounding, 64-bit mode only.  */
 623   evex_rounding_64_mode,
 624   /* Supress all exceptions.  */
 625   evex_sae_mode,
 626
 627   /* Mask register operand.  */
 628   mask_mode,
 629   /* Mask register operand.  */
 630   mask_bd_mode,
 631
 632   es_reg,
 633   cs_reg,
 634   ss_reg,
 635   ds_reg,
 636   fs_reg,
 637   gs_reg,
 638
 639   eAX_reg,
 640   eCX_reg,
 641   eDX_reg,
 642   eBX_reg,
 643   eSP_reg,
 644   eBP_reg,
 645   eSI_reg,
 646   eDI_reg,
 647
 648   al_reg,
 649   cl_reg,
 650   dl_reg,
 651   bl_reg,
 652   ah_reg,
 653   ch_reg,
 654   dh_reg,
 655   bh_reg,
 656
 657   ax_reg,
 658   cx_reg,
 659   dx_reg,
 660   bx_reg,
 661   sp_reg,
 662   bp_reg,
 663   si_reg,
 664   di_reg,
 665
 666   rAX_reg,
 667   rCX_reg,
 668   rDX_reg,
 669   rBX_reg,
 670   rSP_reg,
 671   rBP_reg,
 672   rSI_reg,
 673   rDI_reg,
 674
 675   z_mode_ax_reg,
 676   indir_dx_reg
 677 };
 678
 679 enum
 680 {
 681   FLOATCODE = 1,
 682   USE_REG_TABLE,
 683   USE_MOD_TABLE,
 684   USE_RM_TABLE,
 685   USE_PREFIX_TABLE,
 686   USE_X86_64_TABLE,
 687   USE_3BYTE_TABLE,
 688   USE_XOP_8F_TABLE,
 689   USE_VEX_C4_TABLE,
 690   USE_VEX_C5_TABLE,
 691   USE_VEX_LEN_TABLE,
 692   USE_VEX_W_TABLE,
 693   USE_EVEX_TABLE,
 694   USE_EVEX_LEN_TABLE
 695 };
 696
 697 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 698
 699 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 700 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 701 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 702 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 703 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 704 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 705 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 706 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 707 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 708 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 709 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 710 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 711 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 712 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 713 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 714 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 715
 716 enum
 717 {
 718   REG_80 = 0,
 719   REG_81,
 720   REG_83,
 721   REG_8F,
 722   REG_C0,
 723   REG_C1,
 724   REG_C6,
 725   REG_C7,
 726   REG_D0,
 727   REG_D1,
 728   REG_D2,
 729   REG_D3,
 730   REG_F6,
 731   REG_F7,
 732   REG_FE,
 733   REG_FF,
 734   REG_0F00,
 735   REG_0F01,
 736   REG_0F0D,
 737   REG_0F18,
 738   REG_0F1C_P_0_MOD_0,
 739   REG_0F1E_P_1_MOD_3,
 740   REG_0F71,
 741   REG_0F72,
 742   REG_0F73,
 743   REG_0FA6,
 744   REG_0FA7,
 745   REG_0FAE,
 746   REG_0FBA,
 747   REG_0FC7,
 748   REG_VEX_0F71,
 749   REG_VEX_0F72,
 750   REG_VEX_0F73,
 751   REG_VEX_0FAE,
 752   REG_VEX_0F38F3,
 753   REG_XOP_LWPCB,
 754   REG_XOP_LWP,
 755   REG_XOP_TBM_01,
 756   REG_XOP_TBM_02,
 757
 758   REG_EVEX_0F71,
 759   REG_EVEX_0F72,
 760   REG_EVEX_0F73,
 761   REG_EVEX_0F38C6,
 762   REG_EVEX_0F38C7
 763 };
 764
 765 enum
 766 {
 767   MOD_8D = 0,
 768   MOD_C6_REG_7,
 769   MOD_C7_REG_7,
 770   MOD_FF_REG_3,
 771   MOD_FF_REG_5,
 772   MOD_0F01_REG_0,
 773   MOD_0F01_REG_1,
 774   MOD_0F01_REG_2,
 775   MOD_0F01_REG_3,
 776   MOD_0F01_REG_5,
 777   MOD_0F01_REG_7,
 778   MOD_0F12_PREFIX_0,
 779   MOD_0F12_PREFIX_2,
 780   MOD_0F13,
 781   MOD_0F16_PREFIX_0,
 782   MOD_0F16_PREFIX_2,
 783   MOD_0F17,
 784   MOD_0F18_REG_0,
 785   MOD_0F18_REG_1,
 786   MOD_0F18_REG_2,
 787   MOD_0F18_REG_3,
 788   MOD_0F18_REG_4,
 789   MOD_0F18_REG_5,
 790   MOD_0F18_REG_6,
 791   MOD_0F18_REG_7,
 792   MOD_0F1A_PREFIX_0,
 793   MOD_0F1B_PREFIX_0,
 794   MOD_0F1B_PREFIX_1,
 795   MOD_0F1C_PREFIX_0,
 796   MOD_0F1E_PREFIX_1,
 797   MOD_0F24,
 798   MOD_0F26,
 799   MOD_0F2B_PREFIX_0,
 800   MOD_0F2B_PREFIX_1,
 801   MOD_0F2B_PREFIX_2,
 802   MOD_0F2B_PREFIX_3,
 803   MOD_0F50,
 804   MOD_0F71_REG_2,
 805   MOD_0F71_REG_4,
 806   MOD_0F71_REG_6,
 807   MOD_0F72_REG_2,
 808   MOD_0F72_REG_4,
 809   MOD_0F72_REG_6,
 810   MOD_0F73_REG_2,
 811   MOD_0F73_REG_3,
 812   MOD_0F73_REG_6,
 813   MOD_0F73_REG_7,
 814   MOD_0FAE_REG_0,
 815   MOD_0FAE_REG_1,
 816   MOD_0FAE_REG_2,
 817   MOD_0FAE_REG_3,
 818   MOD_0FAE_REG_4,
 819   MOD_0FAE_REG_5,
 820   MOD_0FAE_REG_6,
 821   MOD_0FAE_REG_7,
 822   MOD_0FB2,
 823   MOD_0FB4,
 824   MOD_0FB5,
 825   MOD_0FC3,
 826   MOD_0FC7_REG_3,
 827   MOD_0FC7_REG_4,
 828   MOD_0FC7_REG_5,
 829   MOD_0FC7_REG_6,
 830   MOD_0FC7_REG_7,
 831   MOD_0FD7,
 832   MOD_0FE7_PREFIX_2,
 833   MOD_0FF0_PREFIX_3,
 834   MOD_0F382A_PREFIX_2,
 835   MOD_0F38F5_PREFIX_2,
 836   MOD_0F38F6_PREFIX_0,
 837   MOD_0F38F8_PREFIX_1,
 838   MOD_0F38F8_PREFIX_2,
 839   MOD_0F38F8_PREFIX_3,
 840   MOD_0F38F9_PREFIX_0,
 841   MOD_62_32BIT,
 842   MOD_C4_32BIT,
 843   MOD_C5_32BIT,
 844   MOD_VEX_0F12_PREFIX_0,
 845   MOD_VEX_0F12_PREFIX_2,
 846   MOD_VEX_0F13,
 847   MOD_VEX_0F16_PREFIX_0,
 848   MOD_VEX_0F16_PREFIX_2,
 849   MOD_VEX_0F17,
 850   MOD_VEX_0F2B,
 851   MOD_VEX_W_0_0F41_P_0_LEN_1,
 852   MOD_VEX_W_1_0F41_P_0_LEN_1,
 853   MOD_VEX_W_0_0F41_P_2_LEN_1,
 854   MOD_VEX_W_1_0F41_P_2_LEN_1,
 855   MOD_VEX_W_0_0F42_P_0_LEN_1,
 856   MOD_VEX_W_1_0F42_P_0_LEN_1,
 857   MOD_VEX_W_0_0F42_P_2_LEN_1,
 858   MOD_VEX_W_1_0F42_P_2_LEN_1,
 859   MOD_VEX_W_0_0F44_P_0_LEN_1,
 860   MOD_VEX_W_1_0F44_P_0_LEN_1,
 861   MOD_VEX_W_0_0F44_P_2_LEN_1,
 862   MOD_VEX_W_1_0F44_P_2_LEN_1,
 863   MOD_VEX_W_0_0F45_P_0_LEN_1,
 864   MOD_VEX_W_1_0F45_P_0_LEN_1,
 865   MOD_VEX_W_0_0F45_P_2_LEN_1,
 866   MOD_VEX_W_1_0F45_P_2_LEN_1,
 867   MOD_VEX_W_0_0F46_P_0_LEN_1,
 868   MOD_VEX_W_1_0F46_P_0_LEN_1,
 869   MOD_VEX_W_0_0F46_P_2_LEN_1,
 870   MOD_VEX_W_1_0F46_P_2_LEN_1,
 871   MOD_VEX_W_0_0F47_P_0_LEN_1,
 872   MOD_VEX_W_1_0F47_P_0_LEN_1,
 873   MOD_VEX_W_0_0F47_P_2_LEN_1,
 874   MOD_VEX_W_1_0F47_P_2_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 878   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 880   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 882   MOD_VEX_0F50,
 883   MOD_VEX_0F71_REG_2,
 884   MOD_VEX_0F71_REG_4,
 885   MOD_VEX_0F71_REG_6,
 886   MOD_VEX_0F72_REG_2,
 887   MOD_VEX_0F72_REG_4,
 888   MOD_VEX_0F72_REG_6,
 889   MOD_VEX_0F73_REG_2,
 890   MOD_VEX_0F73_REG_3,
 891   MOD_VEX_0F73_REG_6,
 892   MOD_VEX_0F73_REG_7,
 893   MOD_VEX_W_0_0F91_P_0_LEN_0,
 894   MOD_VEX_W_1_0F91_P_0_LEN_0,
 895   MOD_VEX_W_0_0F91_P_2_LEN_0,
 896   MOD_VEX_W_1_0F91_P_2_LEN_0,
 897   MOD_VEX_W_0_0F92_P_0_LEN_0,
 898   MOD_VEX_W_0_0F92_P_2_LEN_0,
 899   MOD_VEX_0F92_P_3_LEN_0,
 900   MOD_VEX_W_0_0F93_P_0_LEN_0,
 901   MOD_VEX_W_0_0F93_P_2_LEN_0,
 902   MOD_VEX_0F93_P_3_LEN_0,
 903   MOD_VEX_W_0_0F98_P_0_LEN_0,
 904   MOD_VEX_W_1_0F98_P_0_LEN_0,
 905   MOD_VEX_W_0_0F98_P_2_LEN_0,
 906   MOD_VEX_W_1_0F98_P_2_LEN_0,
 907   MOD_VEX_W_0_0F99_P_0_LEN_0,
 908   MOD_VEX_W_1_0F99_P_0_LEN_0,
 909   MOD_VEX_W_0_0F99_P_2_LEN_0,
 910   MOD_VEX_W_1_0F99_P_2_LEN_0,
 911   MOD_VEX_0FAE_REG_2,
 912   MOD_VEX_0FAE_REG_3,
 913   MOD_VEX_0FD7_PREFIX_2,
 914   MOD_VEX_0FE7_PREFIX_2,
 915   MOD_VEX_0FF0_PREFIX_3,
 916   MOD_VEX_0F381A_PREFIX_2,
 917   MOD_VEX_0F382A_PREFIX_2,
 918   MOD_VEX_0F382C_PREFIX_2,
 919   MOD_VEX_0F382D_PREFIX_2,
 920   MOD_VEX_0F382E_PREFIX_2,
 921   MOD_VEX_0F382F_PREFIX_2,
 922   MOD_VEX_0F385A_PREFIX_2,
 923   MOD_VEX_0F388C_PREFIX_2,
 924   MOD_VEX_0F388E_PREFIX_2,
 925   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 931   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 933
 934   MOD_EVEX_0F12_PREFIX_0,
 935   MOD_EVEX_0F12_PREFIX_2,
 936   MOD_EVEX_0F13,
 937   MOD_EVEX_0F16_PREFIX_0,
 938   MOD_EVEX_0F16_PREFIX_2,
 939   MOD_EVEX_0F17,
 940   MOD_EVEX_0F2B,
 941   MOD_EVEX_0F38C6_REG_1,
 942   MOD_EVEX_0F38C6_REG_2,
 943   MOD_EVEX_0F38C6_REG_5,
 944   MOD_EVEX_0F38C6_REG_6,
 945   MOD_EVEX_0F38C7_REG_1,
 946   MOD_EVEX_0F38C7_REG_2,
 947   MOD_EVEX_0F38C7_REG_5,
 948   MOD_EVEX_0F38C7_REG_6
 949 };
 950
 951 enum
 952 {
 953   RM_C6_REG_7 = 0,
 954   RM_C7_REG_7,
 955   RM_0F01_REG_0,
 956   RM_0F01_REG_1,
 957   RM_0F01_REG_2,
 958   RM_0F01_REG_3,
 959   RM_0F01_REG_5_MOD_3,
 960   RM_0F01_REG_7_MOD_3,
 961   RM_0F1E_P_1_MOD_3_REG_7,
 962   RM_0FAE_REG_6_MOD_3_P_0,
 963   RM_0FAE_REG_7_MOD_3,
 964 };
 965
 966 enum
 967 {
 968   PREFIX_90 = 0,
 969   PREFIX_0F01_REG_3_RM_1,
 970   PREFIX_0F01_REG_5_MOD_0,
 971   PREFIX_0F01_REG_5_MOD_3_RM_0,
 972   PREFIX_0F01_REG_5_MOD_3_RM_1,
 973   PREFIX_0F01_REG_5_MOD_3_RM_2,
 974   PREFIX_0F01_REG_7_MOD_3_RM_2,
 975   PREFIX_0F01_REG_7_MOD_3_RM_3,
 976   PREFIX_0F09,
 977   PREFIX_0F10,
 978   PREFIX_0F11,
 979   PREFIX_0F12,
 980   PREFIX_0F16,
 981   PREFIX_0F1A,
 982   PREFIX_0F1B,
 983   PREFIX_0F1C,
 984   PREFIX_0F1E,
 985   PREFIX_0F2A,
 986   PREFIX_0F2B,
 987   PREFIX_0F2C,
 988   PREFIX_0F2D,
 989   PREFIX_0F2E,
 990   PREFIX_0F2F,
 991   PREFIX_0F51,
 992   PREFIX_0F52,
 993   PREFIX_0F53,
 994   PREFIX_0F58,
 995   PREFIX_0F59,
 996   PREFIX_0F5A,
 997   PREFIX_0F5B,
 998   PREFIX_0F5C,
 999   PREFIX_0F5D,
1000   PREFIX_0F5E,
1001   PREFIX_0F5F,
1002   PREFIX_0F60,
1003   PREFIX_0F61,
1004   PREFIX_0F62,
1005   PREFIX_0F6C,
1006   PREFIX_0F6D,
1007   PREFIX_0F6F,
1008   PREFIX_0F70,
1009   PREFIX_0F73_REG_3,
1010   PREFIX_0F73_REG_7,
1011   PREFIX_0F78,
1012   PREFIX_0F79,
1013   PREFIX_0F7C,
1014   PREFIX_0F7D,
1015   PREFIX_0F7E,
1016   PREFIX_0F7F,
1017   PREFIX_0FAE_REG_0_MOD_3,
1018   PREFIX_0FAE_REG_1_MOD_3,
1019   PREFIX_0FAE_REG_2_MOD_3,
1020   PREFIX_0FAE_REG_3_MOD_3,
1021   PREFIX_0FAE_REG_4_MOD_0,
1022   PREFIX_0FAE_REG_4_MOD_3,
1023   PREFIX_0FAE_REG_5_MOD_0,
1024   PREFIX_0FAE_REG_5_MOD_3,
1025   PREFIX_0FAE_REG_6_MOD_0,
1026   PREFIX_0FAE_REG_6_MOD_3,
1027   PREFIX_0FAE_REG_7_MOD_0,
1028   PREFIX_0FB8,
1029   PREFIX_0FBC,
1030   PREFIX_0FBD,
1031   PREFIX_0FC2,
1032   PREFIX_0FC3_MOD_0,
1033   PREFIX_0FC7_REG_6_MOD_0,
1034   PREFIX_0FC7_REG_6_MOD_3,
1035   PREFIX_0FC7_REG_7_MOD_3,
1036   PREFIX_0FD0,
1037   PREFIX_0FD6,
1038   PREFIX_0FE6,
1039   PREFIX_0FE7,
1040   PREFIX_0FF0,
1041   PREFIX_0FF7,
1042   PREFIX_0F3810,
1043   PREFIX_0F3814,
1044   PREFIX_0F3815,
1045   PREFIX_0F3817,
1046   PREFIX_0F3820,
1047   PREFIX_0F3821,
1048   PREFIX_0F3822,
1049   PREFIX_0F3823,
1050   PREFIX_0F3824,
1051   PREFIX_0F3825,
1052   PREFIX_0F3828,
1053   PREFIX_0F3829,
1054   PREFIX_0F382A,
1055   PREFIX_0F382B,
1056   PREFIX_0F3830,
1057   PREFIX_0F3831,
1058   PREFIX_0F3832,
1059   PREFIX_0F3833,
1060   PREFIX_0F3834,
1061   PREFIX_0F3835,
1062   PREFIX_0F3837,
1063   PREFIX_0F3838,
1064   PREFIX_0F3839,
1065   PREFIX_0F383A,
1066   PREFIX_0F383B,
1067   PREFIX_0F383C,
1068   PREFIX_0F383D,
1069   PREFIX_0F383E,
1070   PREFIX_0F383F,
1071   PREFIX_0F3840,
1072   PREFIX_0F3841,
1073   PREFIX_0F3880,
1074   PREFIX_0F3881,
1075   PREFIX_0F3882,
1076   PREFIX_0F38C8,
1077   PREFIX_0F38C9,
1078   PREFIX_0F38CA,
1079   PREFIX_0F38CB,
1080   PREFIX_0F38CC,
1081   PREFIX_0F38CD,
1082   PREFIX_0F38CF,
1083   PREFIX_0F38DB,
1084   PREFIX_0F38DC,
1085   PREFIX_0F38DD,
1086   PREFIX_0F38DE,
1087   PREFIX_0F38DF,
1088   PREFIX_0F38F0,
1089   PREFIX_0F38F1,
1090   PREFIX_0F38F5,
1091   PREFIX_0F38F6,
1092   PREFIX_0F38F8,
1093   PREFIX_0F38F9,
1094   PREFIX_0F3A08,
1095   PREFIX_0F3A09,
1096   PREFIX_0F3A0A,
1097   PREFIX_0F3A0B,
1098   PREFIX_0F3A0C,
1099   PREFIX_0F3A0D,
1100   PREFIX_0F3A0E,
1101   PREFIX_0F3A14,
1102   PREFIX_0F3A15,
1103   PREFIX_0F3A16,
1104   PREFIX_0F3A17,
1105   PREFIX_0F3A20,
1106   PREFIX_0F3A21,
1107   PREFIX_0F3A22,
1108   PREFIX_0F3A40,
1109   PREFIX_0F3A41,
1110   PREFIX_0F3A42,
1111   PREFIX_0F3A44,
1112   PREFIX_0F3A60,
1113   PREFIX_0F3A61,
1114   PREFIX_0F3A62,
1115   PREFIX_0F3A63,
1116   PREFIX_0F3ACC,
1117   PREFIX_0F3ACE,
1118   PREFIX_0F3ACF,
1119   PREFIX_0F3ADF,
1120   PREFIX_VEX_0F10,
1121   PREFIX_VEX_0F11,
1122   PREFIX_VEX_0F12,
1123   PREFIX_VEX_0F16,
1124   PREFIX_VEX_0F2A,
1125   PREFIX_VEX_0F2C,
1126   PREFIX_VEX_0F2D,
1127   PREFIX_VEX_0F2E,
1128   PREFIX_VEX_0F2F,
1129   PREFIX_VEX_0F41,
1130   PREFIX_VEX_0F42,
1131   PREFIX_VEX_0F44,
1132   PREFIX_VEX_0F45,
1133   PREFIX_VEX_0F46,
1134   PREFIX_VEX_0F47,
1135   PREFIX_VEX_0F4A,
1136   PREFIX_VEX_0F4B,
1137   PREFIX_VEX_0F51,
1138   PREFIX_VEX_0F52,
1139   PREFIX_VEX_0F53,
1140   PREFIX_VEX_0F58,
1141   PREFIX_VEX_0F59,
1142   PREFIX_VEX_0F5A,
1143   PREFIX_VEX_0F5B,
1144   PREFIX_VEX_0F5C,
1145   PREFIX_VEX_0F5D,
1146   PREFIX_VEX_0F5E,
1147   PREFIX_VEX_0F5F,
1148   PREFIX_VEX_0F60,
1149   PREFIX_VEX_0F61,
1150   PREFIX_VEX_0F62,
1151   PREFIX_VEX_0F63,
1152   PREFIX_VEX_0F64,
1153   PREFIX_VEX_0F65,
1154   PREFIX_VEX_0F66,
1155   PREFIX_VEX_0F67,
1156   PREFIX_VEX_0F68,
1157   PREFIX_VEX_0F69,
1158   PREFIX_VEX_0F6A,
1159   PREFIX_VEX_0F6B,
1160   PREFIX_VEX_0F6C,
1161   PREFIX_VEX_0F6D,
1162   PREFIX_VEX_0F6E,
1163   PREFIX_VEX_0F6F,
1164   PREFIX_VEX_0F70,
1165   PREFIX_VEX_0F71_REG_2,
1166   PREFIX_VEX_0F71_REG_4,
1167   PREFIX_VEX_0F71_REG_6,
1168   PREFIX_VEX_0F72_REG_2,
1169   PREFIX_VEX_0F72_REG_4,
1170   PREFIX_VEX_0F72_REG_6,
1171   PREFIX_VEX_0F73_REG_2,
1172   PREFIX_VEX_0F73_REG_3,
1173   PREFIX_VEX_0F73_REG_6,
1174   PREFIX_VEX_0F73_REG_7,
1175   PREFIX_VEX_0F74,
1176   PREFIX_VEX_0F75,
1177   PREFIX_VEX_0F76,
1178   PREFIX_VEX_0F77,
1179   PREFIX_VEX_0F7C,
1180   PREFIX_VEX_0F7D,
1181   PREFIX_VEX_0F7E,
1182   PREFIX_VEX_0F7F,
1183   PREFIX_VEX_0F90,
1184   PREFIX_VEX_0F91,
1185   PREFIX_VEX_0F92,
1186   PREFIX_VEX_0F93,
1187   PREFIX_VEX_0F98,
1188   PREFIX_VEX_0F99,
1189   PREFIX_VEX_0FC2,
1190   PREFIX_VEX_0FC4,
1191   PREFIX_VEX_0FC5,
1192   PREFIX_VEX_0FD0,
1193   PREFIX_VEX_0FD1,
1194   PREFIX_VEX_0FD2,
1195   PREFIX_VEX_0FD3,
1196   PREFIX_VEX_0FD4,
1197   PREFIX_VEX_0FD5,
1198   PREFIX_VEX_0FD6,
1199   PREFIX_VEX_0FD7,
1200   PREFIX_VEX_0FD8,
1201   PREFIX_VEX_0FD9,
1202   PREFIX_VEX_0FDA,
1203   PREFIX_VEX_0FDB,
1204   PREFIX_VEX_0FDC,
1205   PREFIX_VEX_0FDD,
1206   PREFIX_VEX_0FDE,
1207   PREFIX_VEX_0FDF,
1208   PREFIX_VEX_0FE0,
1209   PREFIX_VEX_0FE1,
1210   PREFIX_VEX_0FE2,
1211   PREFIX_VEX_0FE3,
1212   PREFIX_VEX_0FE4,
1213   PREFIX_VEX_0FE5,
1214   PREFIX_VEX_0FE6,
1215   PREFIX_VEX_0FE7,
1216   PREFIX_VEX_0FE8,
1217   PREFIX_VEX_0FE9,
1218   PREFIX_VEX_0FEA,
1219   PREFIX_VEX_0FEB,
1220   PREFIX_VEX_0FEC,
1221   PREFIX_VEX_0FED,
1222   PREFIX_VEX_0FEE,
1223   PREFIX_VEX_0FEF,
1224   PREFIX_VEX_0FF0,
1225   PREFIX_VEX_0FF1,
1226   PREFIX_VEX_0FF2,
1227   PREFIX_VEX_0FF3,
1228   PREFIX_VEX_0FF4,
1229   PREFIX_VEX_0FF5,
1230   PREFIX_VEX_0FF6,
1231   PREFIX_VEX_0FF7,
1232   PREFIX_VEX_0FF8,
1233   PREFIX_VEX_0FF9,
1234   PREFIX_VEX_0FFA,
1235   PREFIX_VEX_0FFB,
1236   PREFIX_VEX_0FFC,
1237   PREFIX_VEX_0FFD,
1238   PREFIX_VEX_0FFE,
1239   PREFIX_VEX_0F3800,
1240   PREFIX_VEX_0F3801,
1241   PREFIX_VEX_0F3802,
1242   PREFIX_VEX_0F3803,
1243   PREFIX_VEX_0F3804,
1244   PREFIX_VEX_0F3805,
1245   PREFIX_VEX_0F3806,
1246   PREFIX_VEX_0F3807,
1247   PREFIX_VEX_0F3808,
1248   PREFIX_VEX_0F3809,
1249   PREFIX_VEX_0F380A,
1250   PREFIX_VEX_0F380B,
1251   PREFIX_VEX_0F380C,
1252   PREFIX_VEX_0F380D,
1253   PREFIX_VEX_0F380E,
1254   PREFIX_VEX_0F380F,
1255   PREFIX_VEX_0F3813,
1256   PREFIX_VEX_0F3816,
1257   PREFIX_VEX_0F3817,
1258   PREFIX_VEX_0F3818,
1259   PREFIX_VEX_0F3819,
1260   PREFIX_VEX_0F381A,
1261   PREFIX_VEX_0F381C,
1262   PREFIX_VEX_0F381D,
1263   PREFIX_VEX_0F381E,
1264   PREFIX_VEX_0F3820,
1265   PREFIX_VEX_0F3821,
1266   PREFIX_VEX_0F3822,
1267   PREFIX_VEX_0F3823,
1268   PREFIX_VEX_0F3824,
1269   PREFIX_VEX_0F3825,
1270   PREFIX_VEX_0F3828,
1271   PREFIX_VEX_0F3829,
1272   PREFIX_VEX_0F382A,
1273   PREFIX_VEX_0F382B,
1274   PREFIX_VEX_0F382C,
1275   PREFIX_VEX_0F382D,
1276   PREFIX_VEX_0F382E,
1277   PREFIX_VEX_0F382F,
1278   PREFIX_VEX_0F3830,
1279   PREFIX_VEX_0F3831,
1280   PREFIX_VEX_0F3832,
1281   PREFIX_VEX_0F3833,
1282   PREFIX_VEX_0F3834,
1283   PREFIX_VEX_0F3835,
1284   PREFIX_VEX_0F3836,
1285   PREFIX_VEX_0F3837,
1286   PREFIX_VEX_0F3838,
1287   PREFIX_VEX_0F3839,
1288   PREFIX_VEX_0F383A,
1289   PREFIX_VEX_0F383B,
1290   PREFIX_VEX_0F383C,
1291   PREFIX_VEX_0F383D,
1292   PREFIX_VEX_0F383E,
1293   PREFIX_VEX_0F383F,
1294   PREFIX_VEX_0F3840,
1295   PREFIX_VEX_0F3841,
1296   PREFIX_VEX_0F3845,
1297   PREFIX_VEX_0F3846,
1298   PREFIX_VEX_0F3847,
1299   PREFIX_VEX_0F3858,
1300   PREFIX_VEX_0F3859,
1301   PREFIX_VEX_0F385A,
1302   PREFIX_VEX_0F3878,
1303   PREFIX_VEX_0F3879,
1304   PREFIX_VEX_0F388C,
1305   PREFIX_VEX_0F388E,
1306   PREFIX_VEX_0F3890,
1307   PREFIX_VEX_0F3891,
1308   PREFIX_VEX_0F3892,
1309   PREFIX_VEX_0F3893,
1310   PREFIX_VEX_0F3896,
1311   PREFIX_VEX_0F3897,
1312   PREFIX_VEX_0F3898,
1313   PREFIX_VEX_0F3899,
1314   PREFIX_VEX_0F389A,
1315   PREFIX_VEX_0F389B,
1316   PREFIX_VEX_0F389C,
1317   PREFIX_VEX_0F389D,
1318   PREFIX_VEX_0F389E,
1319   PREFIX_VEX_0F389F,
1320   PREFIX_VEX_0F38A6,
1321   PREFIX_VEX_0F38A7,
1322   PREFIX_VEX_0F38A8,
1323   PREFIX_VEX_0F38A9,
1324   PREFIX_VEX_0F38AA,
1325   PREFIX_VEX_0F38AB,
1326   PREFIX_VEX_0F38AC,
1327   PREFIX_VEX_0F38AD,
1328   PREFIX_VEX_0F38AE,
1329   PREFIX_VEX_0F38AF,
1330   PREFIX_VEX_0F38B6,
1331   PREFIX_VEX_0F38B7,
1332   PREFIX_VEX_0F38B8,
1333   PREFIX_VEX_0F38B9,
1334   PREFIX_VEX_0F38BA,
1335   PREFIX_VEX_0F38BB,
1336   PREFIX_VEX_0F38BC,
1337   PREFIX_VEX_0F38BD,
1338   PREFIX_VEX_0F38BE,
1339   PREFIX_VEX_0F38BF,
1340   PREFIX_VEX_0F38CF,
1341   PREFIX_VEX_0F38DB,
1342   PREFIX_VEX_0F38DC,
1343   PREFIX_VEX_0F38DD,
1344   PREFIX_VEX_0F38DE,
1345   PREFIX_VEX_0F38DF,
1346   PREFIX_VEX_0F38F2,
1347   PREFIX_VEX_0F38F3_REG_1,
1348   PREFIX_VEX_0F38F3_REG_2,
1349   PREFIX_VEX_0F38F3_REG_3,
1350   PREFIX_VEX_0F38F5,
1351   PREFIX_VEX_0F38F6,
1352   PREFIX_VEX_0F38F7,
1353   PREFIX_VEX_0F3A00,
1354   PREFIX_VEX_0F3A01,
1355   PREFIX_VEX_0F3A02,
1356   PREFIX_VEX_0F3A04,
1357   PREFIX_VEX_0F3A05,
1358   PREFIX_VEX_0F3A06,
1359   PREFIX_VEX_0F3A08,
1360   PREFIX_VEX_0F3A09,
1361   PREFIX_VEX_0F3A0A,
1362   PREFIX_VEX_0F3A0B,
1363   PREFIX_VEX_0F3A0C,
1364   PREFIX_VEX_0F3A0D,
1365   PREFIX_VEX_0F3A0E,
1366   PREFIX_VEX_0F3A0F,
1367   PREFIX_VEX_0F3A14,
1368   PREFIX_VEX_0F3A15,
1369   PREFIX_VEX_0F3A16,
1370   PREFIX_VEX_0F3A17,
1371   PREFIX_VEX_0F3A18,
1372   PREFIX_VEX_0F3A19,
1373   PREFIX_VEX_0F3A1D,
1374   PREFIX_VEX_0F3A20,
1375   PREFIX_VEX_0F3A21,
1376   PREFIX_VEX_0F3A22,
1377   PREFIX_VEX_0F3A30,
1378   PREFIX_VEX_0F3A31,
1379   PREFIX_VEX_0F3A32,
1380   PREFIX_VEX_0F3A33,
1381   PREFIX_VEX_0F3A38,
1382   PREFIX_VEX_0F3A39,
1383   PREFIX_VEX_0F3A40,
1384   PREFIX_VEX_0F3A41,
1385   PREFIX_VEX_0F3A42,
1386   PREFIX_VEX_0F3A44,
1387   PREFIX_VEX_0F3A46,
1388   PREFIX_VEX_0F3A48,
1389   PREFIX_VEX_0F3A49,
1390   PREFIX_VEX_0F3A4A,
1391   PREFIX_VEX_0F3A4B,
1392   PREFIX_VEX_0F3A4C,
1393   PREFIX_VEX_0F3A5C,
1394   PREFIX_VEX_0F3A5D,
1395   PREFIX_VEX_0F3A5E,
1396   PREFIX_VEX_0F3A5F,
1397   PREFIX_VEX_0F3A60,
1398   PREFIX_VEX_0F3A61,
1399   PREFIX_VEX_0F3A62,
1400   PREFIX_VEX_0F3A63,
1401   PREFIX_VEX_0F3A68,
1402   PREFIX_VEX_0F3A69,
1403   PREFIX_VEX_0F3A6A,
1404   PREFIX_VEX_0F3A6B,
1405   PREFIX_VEX_0F3A6C,
1406   PREFIX_VEX_0F3A6D,
1407   PREFIX_VEX_0F3A6E,
1408   PREFIX_VEX_0F3A6F,
1409   PREFIX_VEX_0F3A78,
1410   PREFIX_VEX_0F3A79,
1411   PREFIX_VEX_0F3A7A,
1412   PREFIX_VEX_0F3A7B,
1413   PREFIX_VEX_0F3A7C,
1414   PREFIX_VEX_0F3A7D,
1415   PREFIX_VEX_0F3A7E,
1416   PREFIX_VEX_0F3A7F,
1417   PREFIX_VEX_0F3ACE,
1418   PREFIX_VEX_0F3ACF,
1419   PREFIX_VEX_0F3ADF,
1420   PREFIX_VEX_0F3AF0,
1421
1422   PREFIX_EVEX_0F10,
1423   PREFIX_EVEX_0F11,
1424   PREFIX_EVEX_0F12,
1425   PREFIX_EVEX_0F16,
1426   PREFIX_EVEX_0F2A,
1427   PREFIX_EVEX_0F2C,
1428   PREFIX_EVEX_0F2D,
1429   PREFIX_EVEX_0F2E,
1430   PREFIX_EVEX_0F2F,
1431   PREFIX_EVEX_0F51,
1432   PREFIX_EVEX_0F58,
1433   PREFIX_EVEX_0F59,
1434   PREFIX_EVEX_0F5A,
1435   PREFIX_EVEX_0F5B,
1436   PREFIX_EVEX_0F5C,
1437   PREFIX_EVEX_0F5D,
1438   PREFIX_EVEX_0F5E,
1439   PREFIX_EVEX_0F5F,
1440   PREFIX_EVEX_0F60,
1441   PREFIX_EVEX_0F61,
1442   PREFIX_EVEX_0F62,
1443   PREFIX_EVEX_0F63,
1444   PREFIX_EVEX_0F64,
1445   PREFIX_EVEX_0F65,
1446   PREFIX_EVEX_0F66,
1447   PREFIX_EVEX_0F67,
1448   PREFIX_EVEX_0F68,
1449   PREFIX_EVEX_0F69,
1450   PREFIX_EVEX_0F6A,
1451   PREFIX_EVEX_0F6B,
1452   PREFIX_EVEX_0F6C,
1453   PREFIX_EVEX_0F6D,
1454   PREFIX_EVEX_0F6E,
1455   PREFIX_EVEX_0F6F,
1456   PREFIX_EVEX_0F70,
1457   PREFIX_EVEX_0F71_REG_2,
1458   PREFIX_EVEX_0F71_REG_4,
1459   PREFIX_EVEX_0F71_REG_6,
1460   PREFIX_EVEX_0F72_REG_0,
1461   PREFIX_EVEX_0F72_REG_1,
1462   PREFIX_EVEX_0F72_REG_2,
1463   PREFIX_EVEX_0F72_REG_4,
1464   PREFIX_EVEX_0F72_REG_6,
1465   PREFIX_EVEX_0F73_REG_2,
1466   PREFIX_EVEX_0F73_REG_3,
1467   PREFIX_EVEX_0F73_REG_6,
1468   PREFIX_EVEX_0F73_REG_7,
1469   PREFIX_EVEX_0F74,
1470   PREFIX_EVEX_0F75,
1471   PREFIX_EVEX_0F76,
1472   PREFIX_EVEX_0F78,
1473   PREFIX_EVEX_0F79,
1474   PREFIX_EVEX_0F7A,
1475   PREFIX_EVEX_0F7B,
1476   PREFIX_EVEX_0F7E,
1477   PREFIX_EVEX_0F7F,
1478   PREFIX_EVEX_0FC2,
1479   PREFIX_EVEX_0FC4,
1480   PREFIX_EVEX_0FC5,
1481   PREFIX_EVEX_0FD1,
1482   PREFIX_EVEX_0FD2,
1483   PREFIX_EVEX_0FD3,
1484   PREFIX_EVEX_0FD4,
1485   PREFIX_EVEX_0FD5,
1486   PREFIX_EVEX_0FD6,
1487   PREFIX_EVEX_0FD8,
1488   PREFIX_EVEX_0FD9,
1489   PREFIX_EVEX_0FDA,
1490   PREFIX_EVEX_0FDB,
1491   PREFIX_EVEX_0FDC,
1492   PREFIX_EVEX_0FDD,
1493   PREFIX_EVEX_0FDE,
1494   PREFIX_EVEX_0FDF,
1495   PREFIX_EVEX_0FE0,
1496   PREFIX_EVEX_0FE1,
1497   PREFIX_EVEX_0FE2,
1498   PREFIX_EVEX_0FE3,
1499   PREFIX_EVEX_0FE4,
1500   PREFIX_EVEX_0FE5,
1501   PREFIX_EVEX_0FE6,
1502   PREFIX_EVEX_0FE7,
1503   PREFIX_EVEX_0FE8,
1504   PREFIX_EVEX_0FE9,
1505   PREFIX_EVEX_0FEA,
1506   PREFIX_EVEX_0FEB,
1507   PREFIX_EVEX_0FEC,
1508   PREFIX_EVEX_0FED,
1509   PREFIX_EVEX_0FEE,
1510   PREFIX_EVEX_0FEF,
1511   PREFIX_EVEX_0FF1,
1512   PREFIX_EVEX_0FF2,
1513   PREFIX_EVEX_0FF3,
1514   PREFIX_EVEX_0FF4,
1515   PREFIX_EVEX_0FF5,
1516   PREFIX_EVEX_0FF6,
1517   PREFIX_EVEX_0FF8,
1518   PREFIX_EVEX_0FF9,
1519   PREFIX_EVEX_0FFA,
1520   PREFIX_EVEX_0FFB,
1521   PREFIX_EVEX_0FFC,
1522   PREFIX_EVEX_0FFD,
1523   PREFIX_EVEX_0FFE,
1524   PREFIX_EVEX_0F3800,
1525   PREFIX_EVEX_0F3804,
1526   PREFIX_EVEX_0F380B,
1527   PREFIX_EVEX_0F380C,
1528   PREFIX_EVEX_0F380D,
1529   PREFIX_EVEX_0F3810,
1530   PREFIX_EVEX_0F3811,
1531   PREFIX_EVEX_0F3812,
1532   PREFIX_EVEX_0F3813,
1533   PREFIX_EVEX_0F3814,
1534   PREFIX_EVEX_0F3815,
1535   PREFIX_EVEX_0F3816,
1536   PREFIX_EVEX_0F3818,
1537   PREFIX_EVEX_0F3819,
1538   PREFIX_EVEX_0F381A,
1539   PREFIX_EVEX_0F381B,
1540   PREFIX_EVEX_0F381C,
1541   PREFIX_EVEX_0F381D,
1542   PREFIX_EVEX_0F381E,
1543   PREFIX_EVEX_0F381F,
1544   PREFIX_EVEX_0F3820,
1545   PREFIX_EVEX_0F3821,
1546   PREFIX_EVEX_0F3822,
1547   PREFIX_EVEX_0F3823,
1548   PREFIX_EVEX_0F3824,
1549   PREFIX_EVEX_0F3825,
1550   PREFIX_EVEX_0F3826,
1551   PREFIX_EVEX_0F3827,
1552   PREFIX_EVEX_0F3828,
1553   PREFIX_EVEX_0F3829,
1554   PREFIX_EVEX_0F382A,
1555   PREFIX_EVEX_0F382B,
1556   PREFIX_EVEX_0F382C,
1557   PREFIX_EVEX_0F382D,
1558   PREFIX_EVEX_0F3830,
1559   PREFIX_EVEX_0F3831,
1560   PREFIX_EVEX_0F3832,
1561   PREFIX_EVEX_0F3833,
1562   PREFIX_EVEX_0F3834,
1563   PREFIX_EVEX_0F3835,
1564   PREFIX_EVEX_0F3836,
1565   PREFIX_EVEX_0F3837,
1566   PREFIX_EVEX_0F3838,
1567   PREFIX_EVEX_0F3839,
1568   PREFIX_EVEX_0F383A,
1569   PREFIX_EVEX_0F383B,
1570   PREFIX_EVEX_0F383C,
1571   PREFIX_EVEX_0F383D,
1572   PREFIX_EVEX_0F383E,
1573   PREFIX_EVEX_0F383F,
1574   PREFIX_EVEX_0F3840,
1575   PREFIX_EVEX_0F3842,
1576   PREFIX_EVEX_0F3843,
1577   PREFIX_EVEX_0F3844,
1578   PREFIX_EVEX_0F3845,
1579   PREFIX_EVEX_0F3846,
1580   PREFIX_EVEX_0F3847,
1581   PREFIX_EVEX_0F384C,
1582   PREFIX_EVEX_0F384D,
1583   PREFIX_EVEX_0F384E,
1584   PREFIX_EVEX_0F384F,
1585   PREFIX_EVEX_0F3850,
1586   PREFIX_EVEX_0F3851,
1587   PREFIX_EVEX_0F3852,
1588   PREFIX_EVEX_0F3853,
1589   PREFIX_EVEX_0F3854,
1590   PREFIX_EVEX_0F3855,
1591   PREFIX_EVEX_0F3858,
1592   PREFIX_EVEX_0F3859,
1593   PREFIX_EVEX_0F385A,
1594   PREFIX_EVEX_0F385B,
1595   PREFIX_EVEX_0F3862,
1596   PREFIX_EVEX_0F3863,
1597   PREFIX_EVEX_0F3864,
1598   PREFIX_EVEX_0F3865,
1599   PREFIX_EVEX_0F3866,
1600   PREFIX_EVEX_0F3868,
1601   PREFIX_EVEX_0F3870,
1602   PREFIX_EVEX_0F3871,
1603   PREFIX_EVEX_0F3872,
1604   PREFIX_EVEX_0F3873,
1605   PREFIX_EVEX_0F3875,
1606   PREFIX_EVEX_0F3876,
1607   PREFIX_EVEX_0F3877,
1608   PREFIX_EVEX_0F3878,
1609   PREFIX_EVEX_0F3879,
1610   PREFIX_EVEX_0F387A,
1611   PREFIX_EVEX_0F387B,
1612   PREFIX_EVEX_0F387C,
1613   PREFIX_EVEX_0F387D,
1614   PREFIX_EVEX_0F387E,
1615   PREFIX_EVEX_0F387F,
1616   PREFIX_EVEX_0F3883,
1617   PREFIX_EVEX_0F3888,
1618   PREFIX_EVEX_0F3889,
1619   PREFIX_EVEX_0F388A,
1620   PREFIX_EVEX_0F388B,
1621   PREFIX_EVEX_0F388D,
1622   PREFIX_EVEX_0F388F,
1623   PREFIX_EVEX_0F3890,
1624   PREFIX_EVEX_0F3891,
1625   PREFIX_EVEX_0F3892,
1626   PREFIX_EVEX_0F3893,
1627   PREFIX_EVEX_0F3896,
1628   PREFIX_EVEX_0F3897,
1629   PREFIX_EVEX_0F3898,
1630   PREFIX_EVEX_0F3899,
1631   PREFIX_EVEX_0F389A,
1632   PREFIX_EVEX_0F389B,
1633   PREFIX_EVEX_0F389C,
1634   PREFIX_EVEX_0F389D,
1635   PREFIX_EVEX_0F389E,
1636   PREFIX_EVEX_0F389F,
1637   PREFIX_EVEX_0F38A0,
1638   PREFIX_EVEX_0F38A1,
1639   PREFIX_EVEX_0F38A2,
1640   PREFIX_EVEX_0F38A3,
1641   PREFIX_EVEX_0F38A6,
1642   PREFIX_EVEX_0F38A7,
1643   PREFIX_EVEX_0F38A8,
1644   PREFIX_EVEX_0F38A9,
1645   PREFIX_EVEX_0F38AA,
1646   PREFIX_EVEX_0F38AB,
1647   PREFIX_EVEX_0F38AC,
1648   PREFIX_EVEX_0F38AD,
1649   PREFIX_EVEX_0F38AE,
1650   PREFIX_EVEX_0F38AF,
1651   PREFIX_EVEX_0F38B4,
1652   PREFIX_EVEX_0F38B5,
1653   PREFIX_EVEX_0F38B6,
1654   PREFIX_EVEX_0F38B7,
1655   PREFIX_EVEX_0F38B8,
1656   PREFIX_EVEX_0F38B9,
1657   PREFIX_EVEX_0F38BA,
1658   PREFIX_EVEX_0F38BB,
1659   PREFIX_EVEX_0F38BC,
1660   PREFIX_EVEX_0F38BD,
1661   PREFIX_EVEX_0F38BE,
1662   PREFIX_EVEX_0F38BF,
1663   PREFIX_EVEX_0F38C4,
1664   PREFIX_EVEX_0F38C6_REG_1,
1665   PREFIX_EVEX_0F38C6_REG_2,
1666   PREFIX_EVEX_0F38C6_REG_5,
1667   PREFIX_EVEX_0F38C6_REG_6,
1668   PREFIX_EVEX_0F38C7_REG_1,
1669   PREFIX_EVEX_0F38C7_REG_2,
1670   PREFIX_EVEX_0F38C7_REG_5,
1671   PREFIX_EVEX_0F38C7_REG_6,
1672   PREFIX_EVEX_0F38C8,
1673   PREFIX_EVEX_0F38CA,
1674   PREFIX_EVEX_0F38CB,
1675   PREFIX_EVEX_0F38CC,
1676   PREFIX_EVEX_0F38CD,
1677   PREFIX_EVEX_0F38CF,
1678   PREFIX_EVEX_0F38DC,
1679   PREFIX_EVEX_0F38DD,
1680   PREFIX_EVEX_0F38DE,
1681   PREFIX_EVEX_0F38DF,
1682
1683   PREFIX_EVEX_0F3A00,
1684   PREFIX_EVEX_0F3A01,
1685   PREFIX_EVEX_0F3A03,
1686   PREFIX_EVEX_0F3A04,
1687   PREFIX_EVEX_0F3A05,
1688   PREFIX_EVEX_0F3A08,
1689   PREFIX_EVEX_0F3A09,
1690   PREFIX_EVEX_0F3A0A,
1691   PREFIX_EVEX_0F3A0B,
1692   PREFIX_EVEX_0F3A0F,
1693   PREFIX_EVEX_0F3A14,
1694   PREFIX_EVEX_0F3A15,
1695   PREFIX_EVEX_0F3A16,
1696   PREFIX_EVEX_0F3A17,
1697   PREFIX_EVEX_0F3A18,
1698   PREFIX_EVEX_0F3A19,
1699   PREFIX_EVEX_0F3A1A,
1700   PREFIX_EVEX_0F3A1B,
1701   PREFIX_EVEX_0F3A1D,
1702   PREFIX_EVEX_0F3A1E,
1703   PREFIX_EVEX_0F3A1F,
1704   PREFIX_EVEX_0F3A20,
1705   PREFIX_EVEX_0F3A21,
1706   PREFIX_EVEX_0F3A22,
1707   PREFIX_EVEX_0F3A23,
1708   PREFIX_EVEX_0F3A25,
1709   PREFIX_EVEX_0F3A26,
1710   PREFIX_EVEX_0F3A27,
1711   PREFIX_EVEX_0F3A38,
1712   PREFIX_EVEX_0F3A39,
1713   PREFIX_EVEX_0F3A3A,
1714   PREFIX_EVEX_0F3A3B,
1715   PREFIX_EVEX_0F3A3E,
1716   PREFIX_EVEX_0F3A3F,
1717   PREFIX_EVEX_0F3A42,
1718   PREFIX_EVEX_0F3A43,
1719   PREFIX_EVEX_0F3A44,
1720   PREFIX_EVEX_0F3A50,
1721   PREFIX_EVEX_0F3A51,
1722   PREFIX_EVEX_0F3A54,
1723   PREFIX_EVEX_0F3A55,
1724   PREFIX_EVEX_0F3A56,
1725   PREFIX_EVEX_0F3A57,
1726   PREFIX_EVEX_0F3A66,
1727   PREFIX_EVEX_0F3A67,
1728   PREFIX_EVEX_0F3A70,
1729   PREFIX_EVEX_0F3A71,
1730   PREFIX_EVEX_0F3A72,
1731   PREFIX_EVEX_0F3A73,
1732   PREFIX_EVEX_0F3ACE,
1733   PREFIX_EVEX_0F3ACF
1734 };
1735
1736 enum
1737 {
1738   X86_64_06 = 0,
1739   X86_64_07,
1740   X86_64_0E,
1741   X86_64_16,
1742   X86_64_17,
1743   X86_64_1E,
1744   X86_64_1F,
1745   X86_64_27,
1746   X86_64_2F,
1747   X86_64_37,
1748   X86_64_3F,
1749   X86_64_60,
1750   X86_64_61,
1751   X86_64_62,
1752   X86_64_63,
1753   X86_64_6D,
1754   X86_64_6F,
1755   X86_64_82,
1756   X86_64_9A,
1757   X86_64_C2,
1758   X86_64_C3,
1759   X86_64_C4,
1760   X86_64_C5,
1761   X86_64_CE,
1762   X86_64_D4,
1763   X86_64_D5,
1764   X86_64_E8,
1765   X86_64_E9,
1766   X86_64_EA,
1767   X86_64_0F01_REG_0,
1768   X86_64_0F01_REG_1,
1769   X86_64_0F01_REG_2,
1770   X86_64_0F01_REG_3
1771 };
1772
1773 enum
1774 {
1775   THREE_BYTE_0F38 = 0,
1776   THREE_BYTE_0F3A
1777 };
1778
1779 enum
1780 {
1781   XOP_08 = 0,
1782   XOP_09,
1783   XOP_0A
1784 };
1785
1786 enum
1787 {
1788   VEX_0F = 0,
1789   VEX_0F38,
1790   VEX_0F3A
1791 };
1792
1793 enum
1794 {
1795   EVEX_0F = 0,
1796   EVEX_0F38,
1797   EVEX_0F3A
1798 };
1799
1800 enum
1801 {
1802   VEX_LEN_0F12_P_0_M_0 = 0,
1803   VEX_LEN_0F12_P_0_M_1,
1804 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1805   VEX_LEN_0F13_M_0,
1806   VEX_LEN_0F16_P_0_M_0,
1807   VEX_LEN_0F16_P_0_M_1,
1808 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1809   VEX_LEN_0F17_M_0,
1810   VEX_LEN_0F41_P_0,
1811   VEX_LEN_0F41_P_2,
1812   VEX_LEN_0F42_P_0,
1813   VEX_LEN_0F42_P_2,
1814   VEX_LEN_0F44_P_0,
1815   VEX_LEN_0F44_P_2,
1816   VEX_LEN_0F45_P_0,
1817   VEX_LEN_0F45_P_2,
1818   VEX_LEN_0F46_P_0,
1819   VEX_LEN_0F46_P_2,
1820   VEX_LEN_0F47_P_0,
1821   VEX_LEN_0F47_P_2,
1822   VEX_LEN_0F4A_P_0,
1823   VEX_LEN_0F4A_P_2,
1824   VEX_LEN_0F4B_P_0,
1825   VEX_LEN_0F4B_P_2,
1826   VEX_LEN_0F6E_P_2,
1827   VEX_LEN_0F77_P_0,
1828   VEX_LEN_0F7E_P_1,
1829   VEX_LEN_0F7E_P_2,
1830   VEX_LEN_0F90_P_0,
1831   VEX_LEN_0F90_P_2,
1832   VEX_LEN_0F91_P_0,
1833   VEX_LEN_0F91_P_2,
1834   VEX_LEN_0F92_P_0,
1835   VEX_LEN_0F92_P_2,
1836   VEX_LEN_0F92_P_3,
1837   VEX_LEN_0F93_P_0,
1838   VEX_LEN_0F93_P_2,
1839   VEX_LEN_0F93_P_3,
1840   VEX_LEN_0F98_P_0,
1841   VEX_LEN_0F98_P_2,
1842   VEX_LEN_0F99_P_0,
1843   VEX_LEN_0F99_P_2,
1844   VEX_LEN_0FAE_R_2_M_0,
1845   VEX_LEN_0FAE_R_3_M_0,
1846   VEX_LEN_0FC4_P_2,
1847   VEX_LEN_0FC5_P_2,
1848   VEX_LEN_0FD6_P_2,
1849   VEX_LEN_0FF7_P_2,
1850   VEX_LEN_0F3816_P_2,
1851   VEX_LEN_0F3819_P_2,
1852   VEX_LEN_0F381A_P_2_M_0,
1853   VEX_LEN_0F3836_P_2,
1854   VEX_LEN_0F3841_P_2,
1855   VEX_LEN_0F385A_P_2_M_0,
1856   VEX_LEN_0F38DB_P_2,
1857   VEX_LEN_0F38F2_P_0,
1858   VEX_LEN_0F38F3_R_1_P_0,
1859   VEX_LEN_0F38F3_R_2_P_0,
1860   VEX_LEN_0F38F3_R_3_P_0,
1861   VEX_LEN_0F38F5_P_0,
1862   VEX_LEN_0F38F5_P_1,
1863   VEX_LEN_0F38F5_P_3,
1864   VEX_LEN_0F38F6_P_3,
1865   VEX_LEN_0F38F7_P_0,
1866   VEX_LEN_0F38F7_P_1,
1867   VEX_LEN_0F38F7_P_2,
1868   VEX_LEN_0F38F7_P_3,
1869   VEX_LEN_0F3A00_P_2,
1870   VEX_LEN_0F3A01_P_2,
1871   VEX_LEN_0F3A06_P_2,
1872   VEX_LEN_0F3A14_P_2,
1873   VEX_LEN_0F3A15_P_2,
1874   VEX_LEN_0F3A16_P_2,
1875   VEX_LEN_0F3A17_P_2,
1876   VEX_LEN_0F3A18_P_2,
1877   VEX_LEN_0F3A19_P_2,
1878   VEX_LEN_0F3A20_P_2,
1879   VEX_LEN_0F3A21_P_2,
1880   VEX_LEN_0F3A22_P_2,
1881   VEX_LEN_0F3A30_P_2,
1882   VEX_LEN_0F3A31_P_2,
1883   VEX_LEN_0F3A32_P_2,
1884   VEX_LEN_0F3A33_P_2,
1885   VEX_LEN_0F3A38_P_2,
1886   VEX_LEN_0F3A39_P_2,
1887   VEX_LEN_0F3A41_P_2,
1888   VEX_LEN_0F3A46_P_2,
1889   VEX_LEN_0F3A60_P_2,
1890   VEX_LEN_0F3A61_P_2,
1891   VEX_LEN_0F3A62_P_2,
1892   VEX_LEN_0F3A63_P_2,
1893   VEX_LEN_0F3A6A_P_2,
1894   VEX_LEN_0F3A6B_P_2,
1895   VEX_LEN_0F3A6E_P_2,
1896   VEX_LEN_0F3A6F_P_2,
1897   VEX_LEN_0F3A7A_P_2,
1898   VEX_LEN_0F3A7B_P_2,
1899   VEX_LEN_0F3A7E_P_2,
1900   VEX_LEN_0F3A7F_P_2,
1901   VEX_LEN_0F3ADF_P_2,
1902   VEX_LEN_0F3AF0_P_3,
1903   VEX_LEN_0FXOP_08_CC,
1904   VEX_LEN_0FXOP_08_CD,
1905   VEX_LEN_0FXOP_08_CE,
1906   VEX_LEN_0FXOP_08_CF,
1907   VEX_LEN_0FXOP_08_EC,
1908   VEX_LEN_0FXOP_08_ED,
1909   VEX_LEN_0FXOP_08_EE,
1910   VEX_LEN_0FXOP_08_EF,
1911   VEX_LEN_0FXOP_09_80,
1912   VEX_LEN_0FXOP_09_81
1913 };
1914
1915 enum
1916 {
1917   EVEX_LEN_0F6E_P_2 = 0,
1918   EVEX_LEN_0F7E_P_1,
1919   EVEX_LEN_0F7E_P_2,
1920   EVEX_LEN_0FD6_P_2,
1921   EVEX_LEN_0F3819_P_2_W_0,
1922   EVEX_LEN_0F3819_P_2_W_1,
1923   EVEX_LEN_0F381A_P_2_W_0,
1924   EVEX_LEN_0F381A_P_2_W_1,
1925   EVEX_LEN_0F381B_P_2_W_0,
1926   EVEX_LEN_0F381B_P_2_W_1,
1927   EVEX_LEN_0F385A_P_2_W_0,
1928   EVEX_LEN_0F385A_P_2_W_1,
1929   EVEX_LEN_0F385B_P_2_W_0,
1930   EVEX_LEN_0F385B_P_2_W_1,
1931   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1932   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1933   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1934   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1935   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1936   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1937   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1938   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1939   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1943   EVEX_LEN_0F3A18_P_2_W_0,
1944   EVEX_LEN_0F3A18_P_2_W_1,
1945   EVEX_LEN_0F3A19_P_2_W_0,
1946   EVEX_LEN_0F3A19_P_2_W_1,
1947   EVEX_LEN_0F3A1A_P_2_W_0,
1948   EVEX_LEN_0F3A1A_P_2_W_1,
1949   EVEX_LEN_0F3A1B_P_2_W_0,
1950   EVEX_LEN_0F3A1B_P_2_W_1,
1951   EVEX_LEN_0F3A23_P_2_W_0,
1952   EVEX_LEN_0F3A23_P_2_W_1,
1953   EVEX_LEN_0F3A38_P_2_W_0,
1954   EVEX_LEN_0F3A38_P_2_W_1,
1955   EVEX_LEN_0F3A39_P_2_W_0,
1956   EVEX_LEN_0F3A39_P_2_W_1,
1957   EVEX_LEN_0F3A3A_P_2_W_0,
1958   EVEX_LEN_0F3A3A_P_2_W_1,
1959   EVEX_LEN_0F3A3B_P_2_W_0,
1960   EVEX_LEN_0F3A3B_P_2_W_1,
1961   EVEX_LEN_0F3A43_P_2_W_0,
1962   EVEX_LEN_0F3A43_P_2_W_1
1963 };
1964
1965 enum
1966 {
1967   VEX_W_0F41_P_0_LEN_1 = 0,
1968   VEX_W_0F41_P_2_LEN_1,
1969   VEX_W_0F42_P_0_LEN_1,
1970   VEX_W_0F42_P_2_LEN_1,
1971   VEX_W_0F44_P_0_LEN_0,
1972   VEX_W_0F44_P_2_LEN_0,
1973   VEX_W_0F45_P_0_LEN_1,
1974   VEX_W_0F45_P_2_LEN_1,
1975   VEX_W_0F46_P_0_LEN_1,
1976   VEX_W_0F46_P_2_LEN_1,
1977   VEX_W_0F47_P_0_LEN_1,
1978   VEX_W_0F47_P_2_LEN_1,
1979   VEX_W_0F4A_P_0_LEN_1,
1980   VEX_W_0F4A_P_2_LEN_1,
1981   VEX_W_0F4B_P_0_LEN_1,
1982   VEX_W_0F4B_P_2_LEN_1,
1983   VEX_W_0F90_P_0_LEN_0,
1984   VEX_W_0F90_P_2_LEN_0,
1985   VEX_W_0F91_P_0_LEN_0,
1986   VEX_W_0F91_P_2_LEN_0,
1987   VEX_W_0F92_P_0_LEN_0,
1988   VEX_W_0F92_P_2_LEN_0,
1989   VEX_W_0F93_P_0_LEN_0,
1990   VEX_W_0F93_P_2_LEN_0,
1991   VEX_W_0F98_P_0_LEN_0,
1992   VEX_W_0F98_P_2_LEN_0,
1993   VEX_W_0F99_P_0_LEN_0,
1994   VEX_W_0F99_P_2_LEN_0,
1995   VEX_W_0F380C_P_2,
1996   VEX_W_0F380D_P_2,
1997   VEX_W_0F380E_P_2,
1998   VEX_W_0F380F_P_2,
1999   VEX_W_0F3816_P_2,
2000   VEX_W_0F3818_P_2,
2001   VEX_W_0F3819_P_2,
2002   VEX_W_0F381A_P_2_M_0,
2003   VEX_W_0F382C_P_2_M_0,
2004   VEX_W_0F382D_P_2_M_0,
2005   VEX_W_0F382E_P_2_M_0,
2006   VEX_W_0F382F_P_2_M_0,
2007   VEX_W_0F3836_P_2,
2008   VEX_W_0F3846_P_2,
2009   VEX_W_0F3858_P_2,
2010   VEX_W_0F3859_P_2,
2011   VEX_W_0F385A_P_2_M_0,
2012   VEX_W_0F3878_P_2,
2013   VEX_W_0F3879_P_2,
2014   VEX_W_0F38CF_P_2,
2015   VEX_W_0F3A00_P_2,
2016   VEX_W_0F3A01_P_2,
2017   VEX_W_0F3A02_P_2,
2018   VEX_W_0F3A04_P_2,
2019   VEX_W_0F3A05_P_2,
2020   VEX_W_0F3A06_P_2,
2021   VEX_W_0F3A18_P_2,
2022   VEX_W_0F3A19_P_2,
2023   VEX_W_0F3A30_P_2_LEN_0,
2024   VEX_W_0F3A31_P_2_LEN_0,
2025   VEX_W_0F3A32_P_2_LEN_0,
2026   VEX_W_0F3A33_P_2_LEN_0,
2027   VEX_W_0F3A38_P_2,
2028   VEX_W_0F3A39_P_2,
2029   VEX_W_0F3A46_P_2,
2030   VEX_W_0F3A48_P_2,
2031   VEX_W_0F3A49_P_2,
2032   VEX_W_0F3A4A_P_2,
2033   VEX_W_0F3A4B_P_2,
2034   VEX_W_0F3A4C_P_2,
2035   VEX_W_0F3ACE_P_2,
2036   VEX_W_0F3ACF_P_2,
2037
2038   EVEX_W_0F10_P_1,
2039   EVEX_W_0F10_P_3,
2040   EVEX_W_0F11_P_1,
2041   EVEX_W_0F11_P_3,
2042   EVEX_W_0F12_P_0_M_1,
2043   EVEX_W_0F12_P_1,
2044   EVEX_W_0F12_P_3,
2045   EVEX_W_0F16_P_0_M_1,
2046   EVEX_W_0F16_P_1,
2047   EVEX_W_0F2A_P_3,
2048   EVEX_W_0F51_P_1,
2049   EVEX_W_0F51_P_3,
2050   EVEX_W_0F58_P_1,
2051   EVEX_W_0F58_P_3,
2052   EVEX_W_0F59_P_1,
2053   EVEX_W_0F59_P_3,
2054   EVEX_W_0F5A_P_0,
2055   EVEX_W_0F5A_P_1,
2056   EVEX_W_0F5A_P_2,
2057   EVEX_W_0F5A_P_3,
2058   EVEX_W_0F5B_P_0,
2059   EVEX_W_0F5B_P_1,
2060   EVEX_W_0F5B_P_2,
2061   EVEX_W_0F5C_P_1,
2062   EVEX_W_0F5C_P_3,
2063   EVEX_W_0F5D_P_1,
2064   EVEX_W_0F5D_P_3,
2065   EVEX_W_0F5E_P_1,
2066   EVEX_W_0F5E_P_3,
2067   EVEX_W_0F5F_P_1,
2068   EVEX_W_0F5F_P_3,
2069   EVEX_W_0F62_P_2,
2070   EVEX_W_0F66_P_2,
2071   EVEX_W_0F6A_P_2,
2072   EVEX_W_0F6B_P_2,
2073   EVEX_W_0F6C_P_2,
2074   EVEX_W_0F6D_P_2,
2075   EVEX_W_0F6F_P_1,
2076   EVEX_W_0F6F_P_2,
2077   EVEX_W_0F6F_P_3,
2078   EVEX_W_0F70_P_2,
2079   EVEX_W_0F72_R_2_P_2,
2080   EVEX_W_0F72_R_6_P_2,
2081   EVEX_W_0F73_R_2_P_2,
2082   EVEX_W_0F73_R_6_P_2,
2083   EVEX_W_0F76_P_2,
2084   EVEX_W_0F78_P_0,
2085   EVEX_W_0F78_P_2,
2086   EVEX_W_0F79_P_0,
2087   EVEX_W_0F79_P_2,
2088   EVEX_W_0F7A_P_1,
2089   EVEX_W_0F7A_P_2,
2090   EVEX_W_0F7A_P_3,
2091   EVEX_W_0F7B_P_2,
2092   EVEX_W_0F7B_P_3,
2093   EVEX_W_0F7E_P_1,
2094   EVEX_W_0F7F_P_1,
2095   EVEX_W_0F7F_P_2,
2096   EVEX_W_0F7F_P_3,
2097   EVEX_W_0FC2_P_1,
2098   EVEX_W_0FC2_P_3,
2099   EVEX_W_0FD2_P_2,
2100   EVEX_W_0FD3_P_2,
2101   EVEX_W_0FD4_P_2,
2102   EVEX_W_0FD6_P_2,
2103   EVEX_W_0FE6_P_1,
2104   EVEX_W_0FE6_P_2,
2105   EVEX_W_0FE6_P_3,
2106   EVEX_W_0FE7_P_2,
2107   EVEX_W_0FF2_P_2,
2108   EVEX_W_0FF3_P_2,
2109   EVEX_W_0FF4_P_2,
2110   EVEX_W_0FFA_P_2,
2111   EVEX_W_0FFB_P_2,
2112   EVEX_W_0FFE_P_2,
2113   EVEX_W_0F380C_P_2,
2114   EVEX_W_0F380D_P_2,
2115   EVEX_W_0F3810_P_1,
2116   EVEX_W_0F3810_P_2,
2117   EVEX_W_0F3811_P_1,
2118   EVEX_W_0F3811_P_2,
2119   EVEX_W_0F3812_P_1,
2120   EVEX_W_0F3812_P_2,
2121   EVEX_W_0F3813_P_1,
2122   EVEX_W_0F3813_P_2,
2123   EVEX_W_0F3814_P_1,
2124   EVEX_W_0F3815_P_1,
2125   EVEX_W_0F3818_P_2,
2126   EVEX_W_0F3819_P_2,
2127   EVEX_W_0F381A_P_2,
2128   EVEX_W_0F381B_P_2,
2129   EVEX_W_0F381E_P_2,
2130   EVEX_W_0F381F_P_2,
2131   EVEX_W_0F3820_P_1,
2132   EVEX_W_0F3821_P_1,
2133   EVEX_W_0F3822_P_1,
2134   EVEX_W_0F3823_P_1,
2135   EVEX_W_0F3824_P_1,
2136   EVEX_W_0F3825_P_1,
2137   EVEX_W_0F3825_P_2,
2138   EVEX_W_0F3826_P_1,
2139   EVEX_W_0F3826_P_2,
2140   EVEX_W_0F3828_P_1,
2141   EVEX_W_0F3828_P_2,
2142   EVEX_W_0F3829_P_1,
2143   EVEX_W_0F3829_P_2,
2144   EVEX_W_0F382A_P_1,
2145   EVEX_W_0F382A_P_2,
2146   EVEX_W_0F382B_P_2,
2147   EVEX_W_0F3830_P_1,
2148   EVEX_W_0F3831_P_1,
2149   EVEX_W_0F3832_P_1,
2150   EVEX_W_0F3833_P_1,
2151   EVEX_W_0F3834_P_1,
2152   EVEX_W_0F3835_P_1,
2153   EVEX_W_0F3835_P_2,
2154   EVEX_W_0F3837_P_2,
2155   EVEX_W_0F3838_P_1,
2156   EVEX_W_0F3839_P_1,
2157   EVEX_W_0F383A_P_1,
2158   EVEX_W_0F3840_P_2,
2159   EVEX_W_0F3852_P_1,
2160   EVEX_W_0F3854_P_2,
2161   EVEX_W_0F3855_P_2,
2162   EVEX_W_0F3858_P_2,
2163   EVEX_W_0F3859_P_2,
2164   EVEX_W_0F385A_P_2,
2165   EVEX_W_0F385B_P_2,
2166   EVEX_W_0F3862_P_2,
2167   EVEX_W_0F3863_P_2,
2168   EVEX_W_0F3866_P_2,
2169   EVEX_W_0F3868_P_3,
2170   EVEX_W_0F3870_P_2,
2171   EVEX_W_0F3871_P_2,
2172   EVEX_W_0F3872_P_1,
2173   EVEX_W_0F3872_P_2,
2174   EVEX_W_0F3872_P_3,
2175   EVEX_W_0F3873_P_2,
2176   EVEX_W_0F3875_P_2,
2177   EVEX_W_0F3878_P_2,
2178   EVEX_W_0F3879_P_2,
2179   EVEX_W_0F387A_P_2,
2180   EVEX_W_0F387B_P_2,
2181   EVEX_W_0F387D_P_2,
2182   EVEX_W_0F3883_P_2,
2183   EVEX_W_0F388D_P_2,
2184   EVEX_W_0F3891_P_2,
2185   EVEX_W_0F3893_P_2,
2186   EVEX_W_0F38A1_P_2,
2187   EVEX_W_0F38A3_P_2,
2188   EVEX_W_0F38C7_R_1_P_2,
2189   EVEX_W_0F38C7_R_2_P_2,
2190   EVEX_W_0F38C7_R_5_P_2,
2191   EVEX_W_0F38C7_R_6_P_2,
2192
2193   EVEX_W_0F3A00_P_2,
2194   EVEX_W_0F3A01_P_2,
2195   EVEX_W_0F3A04_P_2,
2196   EVEX_W_0F3A05_P_2,
2197   EVEX_W_0F3A08_P_2,
2198   EVEX_W_0F3A09_P_2,
2199   EVEX_W_0F3A0A_P_2,
2200   EVEX_W_0F3A0B_P_2,
2201   EVEX_W_0F3A18_P_2,
2202   EVEX_W_0F3A19_P_2,
2203   EVEX_W_0F3A1A_P_2,
2204   EVEX_W_0F3A1B_P_2,
2205   EVEX_W_0F3A1D_P_2,
2206   EVEX_W_0F3A21_P_2,
2207   EVEX_W_0F3A23_P_2,
2208   EVEX_W_0F3A38_P_2,
2209   EVEX_W_0F3A39_P_2,
2210   EVEX_W_0F3A3A_P_2,
2211   EVEX_W_0F3A3B_P_2,
2212   EVEX_W_0F3A3E_P_2,
2213   EVEX_W_0F3A3F_P_2,
2214   EVEX_W_0F3A42_P_2,
2215   EVEX_W_0F3A43_P_2,
2216   EVEX_W_0F3A50_P_2,
2217   EVEX_W_0F3A51_P_2,
2218   EVEX_W_0F3A56_P_2,
2219   EVEX_W_0F3A57_P_2,
2220   EVEX_W_0F3A66_P_2,
2221   EVEX_W_0F3A67_P_2,
2222   EVEX_W_0F3A70_P_2,
2223   EVEX_W_0F3A71_P_2,
2224   EVEX_W_0F3A72_P_2,
2225   EVEX_W_0F3A73_P_2,
2226   EVEX_W_0F3ACE_P_2,
2227   EVEX_W_0F3ACF_P_2
2228 };
2229
2230 typedef void (*op_rtn) (int bytemode, int sizeflag);
2231
2232 struct dis386 {
2233   const char *name;
2234   struct
2235     {
2236       op_rtn rtn;
2237       int bytemode;
2238     } op[MAX_OPERANDS];
2239   unsigned int prefix_requirement;
2240 };
2241
2242 /* Upper case letters in the instruction names here are macros.
2243    'A' => print 'b' if no register operands or suffix_always is true
2244    'B' => print 'b' if suffix_always is true
2245    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2246           size prefix
2247    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2248           suffix_always is true
2249    'E' => print 'e' if 32-bit form of jcxz
2250    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2251    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2252    'H' => print ",pt" or ",pn" branch hint
2253    'I' => honor following macro letter even in Intel mode (implemented only
2254           for some of the macro letters)
2255    'J' unused.
2256    'K' => print 'd' or 'q' if rex prefix is present.
2257    'L' => print 'l' if suffix_always is true
2258    'M' => print 'r' if intel_mnemonic is false.
2259    'N' => print 'n' if instruction has no wait "prefix"
2260    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2261    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2262           or suffix_always is true.  print 'q' if rex prefix is present.
2263    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2264           is true
2265    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2266    'S' => print 'w', 'l' or 'q' if suffix_always is true
2267    'T' => print 'q' in 64bit mode if instruction has no operand size
2268           prefix and behave as 'P' otherwise
2269    'U' => print 'q' in 64bit mode if instruction has no operand size
2270           prefix and behave as 'Q' otherwise
2271    'V' => print 'q' in 64bit mode if instruction has no operand size
2272           prefix and behave as 'S' otherwise
2273    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2274    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2275    'Y' unused.
2276    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2277    '!' => change condition from true to false or from false to true.
2278    '%' => add 1 upper case letter to the macro.
2279    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2280           prefix or suffix_always is true (lcall/ljmp).
2281    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2282           on operand size prefix.
2283    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2284           has no operand size prefix for AMD64 ISA, behave as 'P'
2285           otherwise
2286
2287    2 upper case letter macros:
2288    "XY" => print 'x' or 'y' if suffix_always is true or no register
2289            operands and no broadcast.
2290    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2291            register operands and no broadcast.
2292    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2293    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2294            operand or no operand at all in 64bit mode, or if suffix_always
2295            is true.
2296    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2297    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2298    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2299    "LW" => print 'd', 'q' depending on the VEX.W bit
2300    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2301            an operand size prefix, or suffix_always is true.  print
2302            'q' if rex prefix is present.
2303
2304    Many of the above letters print nothing in Intel mode.  See "putop"
2305    for the details.
2306
2307    Braces '{' and '}', and vertical bars '|', indicate alternative
2308    mnemonic strings for AT&T and Intel.  */
2309
2310 static const struct dis386 dis386[] = {
2311   /* 00 */
2312   { "addB",             { Ebh1, Gb }, 0 },
2313   { "addS",             { Evh1, Gv }, 0 },
2314   { "addB",             { Gb, EbS }, 0 },
2315   { "addS",             { Gv, EvS }, 0 },
2316   { "addB",             { AL, Ib }, 0 },
2317   { "addS",             { eAX, Iv }, 0 },
2318   { X86_64_TABLE (X86_64_06) },
2319   { X86_64_TABLE (X86_64_07) },
2320   /* 08 */
2321   { "orB",              { Ebh1, Gb }, 0 },
2322   { "orS",              { Evh1, Gv }, 0 },
2323   { "orB",              { Gb, EbS }, 0 },
2324   { "orS",              { Gv, EvS }, 0 },
2325   { "orB",              { AL, Ib }, 0 },
2326   { "orS",              { eAX, Iv }, 0 },
2327   { X86_64_TABLE (X86_64_0E) },
2328   { Bad_Opcode },       /* 0x0f extended opcode escape */
2329   /* 10 */
2330   { "adcB",             { Ebh1, Gb }, 0 },
2331   { "adcS",             { Evh1, Gv }, 0 },
2332   { "adcB",             { Gb, EbS }, 0 },
2333   { "adcS",             { Gv, EvS }, 0 },
2334   { "adcB",             { AL, Ib }, 0 },
2335   { "adcS",             { eAX, Iv }, 0 },
2336   { X86_64_TABLE (X86_64_16) },
2337   { X86_64_TABLE (X86_64_17) },
2338   /* 18 */
2339   { "sbbB",             { Ebh1, Gb }, 0 },
2340   { "sbbS",             { Evh1, Gv }, 0 },
2341   { "sbbB",             { Gb, EbS }, 0 },
2342   { "sbbS",             { Gv, EvS }, 0 },
2343   { "sbbB",             { AL, Ib }, 0 },
2344   { "sbbS",             { eAX, Iv }, 0 },
2345   { X86_64_TABLE (X86_64_1E) },
2346   { X86_64_TABLE (X86_64_1F) },
2347   /* 20 */
2348   { "andB",             { Ebh1, Gb }, 0 },
2349   { "andS",             { Evh1, Gv }, 0 },
2350   { "andB",             { Gb, EbS }, 0 },
2351   { "andS",             { Gv, EvS }, 0 },
2352   { "andB",             { AL, Ib }, 0 },
2353   { "andS",             { eAX, Iv }, 0 },
2354   { Bad_Opcode },       /* SEG ES prefix */
2355   { X86_64_TABLE (X86_64_27) },
2356   /* 28 */
2357   { "subB",             { Ebh1, Gb }, 0 },
2358   { "subS",             { Evh1, Gv }, 0 },
2359   { "subB",             { Gb, EbS }, 0 },
2360   { "subS",             { Gv, EvS }, 0 },
2361   { "subB",             { AL, Ib }, 0 },
2362   { "subS",             { eAX, Iv }, 0 },
2363   { Bad_Opcode },       /* SEG CS prefix */
2364   { X86_64_TABLE (X86_64_2F) },
2365   /* 30 */
2366   { "xorB",             { Ebh1, Gb }, 0 },
2367   { "xorS",             { Evh1, Gv }, 0 },
2368   { "xorB",             { Gb, EbS }, 0 },
2369   { "xorS",             { Gv, EvS }, 0 },
2370   { "xorB",             { AL, Ib }, 0 },
2371   { "xorS",             { eAX, Iv }, 0 },
2372   { Bad_Opcode },       /* SEG SS prefix */
2373   { X86_64_TABLE (X86_64_37) },
2374   /* 38 */
2375   { "cmpB",             { Eb, Gb }, 0 },
2376   { "cmpS",             { Ev, Gv }, 0 },
2377   { "cmpB",             { Gb, EbS }, 0 },
2378   { "cmpS",             { Gv, EvS }, 0 },
2379   { "cmpB",             { AL, Ib }, 0 },
2380   { "cmpS",             { eAX, Iv }, 0 },
2381   { Bad_Opcode },       /* SEG DS prefix */
2382   { X86_64_TABLE (X86_64_3F) },
2383   /* 40 */
2384   { "inc{S|}",          { RMeAX }, 0 },
2385   { "inc{S|}",          { RMeCX }, 0 },
2386   { "inc{S|}",          { RMeDX }, 0 },
2387   { "inc{S|}",          { RMeBX }, 0 },
2388   { "inc{S|}",          { RMeSP }, 0 },
2389   { "inc{S|}",          { RMeBP }, 0 },
2390   { "inc{S|}",          { RMeSI }, 0 },
2391   { "inc{S|}",          { RMeDI }, 0 },
2392   /* 48 */
2393   { "dec{S|}",          { RMeAX }, 0 },
2394   { "dec{S|}",          { RMeCX }, 0 },
2395   { "dec{S|}",          { RMeDX }, 0 },
2396   { "dec{S|}",          { RMeBX }, 0 },
2397   { "dec{S|}",          { RMeSP }, 0 },
2398   { "dec{S|}",          { RMeBP }, 0 },
2399   { "dec{S|}",          { RMeSI }, 0 },
2400   { "dec{S|}",          { RMeDI }, 0 },
2401   /* 50 */
2402   { "pushV",            { RMrAX }, 0 },
2403   { "pushV",            { RMrCX }, 0 },
2404   { "pushV",            { RMrDX }, 0 },
2405   { "pushV",            { RMrBX }, 0 },
2406   { "pushV",            { RMrSP }, 0 },
2407   { "pushV",            { RMrBP }, 0 },
2408   { "pushV",            { RMrSI }, 0 },
2409   { "pushV",            { RMrDI }, 0 },
2410   /* 58 */
2411   { "popV",             { RMrAX }, 0 },
2412   { "popV",             { RMrCX }, 0 },
2413   { "popV",             { RMrDX }, 0 },
2414   { "popV",             { RMrBX }, 0 },
2415   { "popV",             { RMrSP }, 0 },
2416   { "popV",             { RMrBP }, 0 },
2417   { "popV",             { RMrSI }, 0 },
2418   { "popV",             { RMrDI }, 0 },
2419   /* 60 */
2420   { X86_64_TABLE (X86_64_60) },
2421   { X86_64_TABLE (X86_64_61) },
2422   { X86_64_TABLE (X86_64_62) },
2423   { X86_64_TABLE (X86_64_63) },
2424   { Bad_Opcode },       /* seg fs */
2425   { Bad_Opcode },       /* seg gs */
2426   { Bad_Opcode },       /* op size prefix */
2427   { Bad_Opcode },       /* adr size prefix */
2428   /* 68 */
2429   { "pushT",            { sIv }, 0 },
2430   { "imulS",            { Gv, Ev, Iv }, 0 },
2431   { "pushT",            { sIbT }, 0 },
2432   { "imulS",            { Gv, Ev, sIb }, 0 },
2433   { "ins{b|}",          { Ybr, indirDX }, 0 },
2434   { X86_64_TABLE (X86_64_6D) },
2435   { "outs{b|}",         { indirDXr, Xb }, 0 },
2436   { X86_64_TABLE (X86_64_6F) },
2437   /* 70 */
2438   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2439   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2440   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2441   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2442   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2443   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2444   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2446   /* 78 */
2447   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2448   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2449   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2450   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2451   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2452   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2453   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2454   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2455   /* 80 */
2456   { REG_TABLE (REG_80) },
2457   { REG_TABLE (REG_81) },
2458   { X86_64_TABLE (X86_64_82) },
2459   { REG_TABLE (REG_83) },
2460   { "testB",            { Eb, Gb }, 0 },
2461   { "testS",            { Ev, Gv }, 0 },
2462   { "xchgB",            { Ebh2, Gb }, 0 },
2463   { "xchgS",            { Evh2, Gv }, 0 },
2464   /* 88 */
2465   { "movB",             { Ebh3, Gb }, 0 },
2466   { "movS",             { Evh3, Gv }, 0 },
2467   { "movB",             { Gb, EbS }, 0 },
2468   { "movS",             { Gv, EvS }, 0 },
2469   { "movD",             { Sv, Sw }, 0 },
2470   { MOD_TABLE (MOD_8D) },
2471   { "movD",             { Sw, Sv }, 0 },
2472   { REG_TABLE (REG_8F) },
2473   /* 90 */
2474   { PREFIX_TABLE (PREFIX_90) },
2475   { "xchgS",            { RMeCX, eAX }, 0 },
2476   { "xchgS",            { RMeDX, eAX }, 0 },
2477   { "xchgS",            { RMeBX, eAX }, 0 },
2478   { "xchgS",            { RMeSP, eAX }, 0 },
2479   { "xchgS",            { RMeBP, eAX }, 0 },
2480   { "xchgS",            { RMeSI, eAX }, 0 },
2481   { "xchgS",            { RMeDI, eAX }, 0 },
2482   /* 98 */
2483   { "cW{t|}R",          { XX }, 0 },
2484   { "cR{t|}O",          { XX }, 0 },
2485   { X86_64_TABLE (X86_64_9A) },
2486   { Bad_Opcode },       /* fwait */
2487   { "pushfT",           { XX }, 0 },
2488   { "popfT",            { XX }, 0 },
2489   { "sahf",             { XX }, 0 },
2490   { "lahf",             { XX }, 0 },
2491   /* a0 */
2492   { "mov%LB",           { AL, Ob }, 0 },
2493   { "mov%LS",           { eAX, Ov }, 0 },
2494   { "mov%LB",           { Ob, AL }, 0 },
2495   { "mov%LS",           { Ov, eAX }, 0 },
2496   { "movs{b|}",         { Ybr, Xb }, 0 },
2497   { "movs{R|}",         { Yvr, Xv }, 0 },
2498   { "cmps{b|}",         { Xb, Yb }, 0 },
2499   { "cmps{R|}",         { Xv, Yv }, 0 },
2500   /* a8 */
2501   { "testB",            { AL, Ib }, 0 },
2502   { "testS",            { eAX, Iv }, 0 },
2503   { "stosB",            { Ybr, AL }, 0 },
2504   { "stosS",            { Yvr, eAX }, 0 },
2505   { "lodsB",            { ALr, Xb }, 0 },
2506   { "lodsS",            { eAXr, Xv }, 0 },
2507   { "scasB",            { AL, Yb }, 0 },
2508   { "scasS",            { eAX, Yv }, 0 },
2509   /* b0 */
2510   { "movB",             { RMAL, Ib }, 0 },
2511   { "movB",             { RMCL, Ib }, 0 },
2512   { "movB",             { RMDL, Ib }, 0 },
2513   { "movB",             { RMBL, Ib }, 0 },
2514   { "movB",             { RMAH, Ib }, 0 },
2515   { "movB",             { RMCH, Ib }, 0 },
2516   { "movB",             { RMDH, Ib }, 0 },
2517   { "movB",             { RMBH, Ib }, 0 },
2518   /* b8 */
2519   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2520   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2521   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2522   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2523   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2524   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2525   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2526   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2527   /* c0 */
2528   { REG_TABLE (REG_C0) },
2529   { REG_TABLE (REG_C1) },
2530   { X86_64_TABLE (X86_64_C2) },
2531   { X86_64_TABLE (X86_64_C3) },
2532   { X86_64_TABLE (X86_64_C4) },
2533   { X86_64_TABLE (X86_64_C5) },
2534   { REG_TABLE (REG_C6) },
2535   { REG_TABLE (REG_C7) },
2536   /* c8 */
2537   { "enterT",           { Iw, Ib }, 0 },
2538   { "leaveT",           { XX }, 0 },
2539   { "{l|}ret{|f}P",     { Iw }, 0 },
2540   { "{l|}ret{|f}P",     { XX }, 0 },
2541   { "int3",             { XX }, 0 },
2542   { "int",              { Ib }, 0 },
2543   { X86_64_TABLE (X86_64_CE) },
2544   { "iret%LP",          { XX }, 0 },
2545   /* d0 */
2546   { REG_TABLE (REG_D0) },
2547   { REG_TABLE (REG_D1) },
2548   { REG_TABLE (REG_D2) },
2549   { REG_TABLE (REG_D3) },
2550   { X86_64_TABLE (X86_64_D4) },
2551   { X86_64_TABLE (X86_64_D5) },
2552   { Bad_Opcode },
2553   { "xlat",             { DSBX }, 0 },
2554   /* d8 */
2555   { FLOAT },
2556   { FLOAT },
2557   { FLOAT },
2558   { FLOAT },
2559   { FLOAT },
2560   { FLOAT },
2561   { FLOAT },
2562   { FLOAT },
2563   /* e0 */
2564   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2565   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2566   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2567   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2568   { "inB",              { AL, Ib }, 0 },
2569   { "inG",              { zAX, Ib }, 0 },
2570   { "outB",             { Ib, AL }, 0 },
2571   { "outG",             { Ib, zAX }, 0 },
2572   /* e8 */
2573   { X86_64_TABLE (X86_64_E8) },
2574   { X86_64_TABLE (X86_64_E9) },
2575   { X86_64_TABLE (X86_64_EA) },
2576   { "jmp",              { Jb, BND }, 0 },
2577   { "inB",              { AL, indirDX }, 0 },
2578   { "inG",              { zAX, indirDX }, 0 },
2579   { "outB",             { indirDX, AL }, 0 },
2580   { "outG",             { indirDX, zAX }, 0 },
2581   /* f0 */
2582   { Bad_Opcode },       /* lock prefix */
2583   { "icebp",            { XX }, 0 },
2584   { Bad_Opcode },       /* repne */
2585   { Bad_Opcode },       /* repz */
2586   { "hlt",              { XX }, 0 },
2587   { "cmc",              { XX }, 0 },
2588   { REG_TABLE (REG_F6) },
2589   { REG_TABLE (REG_F7) },
2590   /* f8 */
2591   { "clc",              { XX }, 0 },
2592   { "stc",              { XX }, 0 },
2593   { "cli",              { XX }, 0 },
2594   { "sti",              { XX }, 0 },
2595   { "cld",              { XX }, 0 },
2596   { "std",              { XX }, 0 },
2597   { REG_TABLE (REG_FE) },
2598   { REG_TABLE (REG_FF) },
2599 };
2600
2601 static const struct dis386 dis386_twobyte[] = {
2602   /* 00 */
2603   { REG_TABLE (REG_0F00 ) },
2604   { REG_TABLE (REG_0F01 ) },
2605   { "larS",             { Gv, Ew }, 0 },
2606   { "lslS",             { Gv, Ew }, 0 },
2607   { Bad_Opcode },
2608   { "syscall",          { XX }, 0 },
2609   { "clts",             { XX }, 0 },
2610   { "sysret%LQ",                { XX }, 0 },
2611   /* 08 */
2612   { "invd",             { XX }, 0 },
2613   { PREFIX_TABLE (PREFIX_0F09) },
2614   { Bad_Opcode },
2615   { "ud2",              { XX }, 0 },
2616   { Bad_Opcode },
2617   { REG_TABLE (REG_0F0D) },
2618   { "femms",            { XX }, 0 },
2619   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2620   /* 10 */
2621   { PREFIX_TABLE (PREFIX_0F10) },
2622   { PREFIX_TABLE (PREFIX_0F11) },
2623   { PREFIX_TABLE (PREFIX_0F12) },
2624   { MOD_TABLE (MOD_0F13) },
2625   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2626   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2627   { PREFIX_TABLE (PREFIX_0F16) },
2628   { MOD_TABLE (MOD_0F17) },
2629   /* 18 */
2630   { REG_TABLE (REG_0F18) },
2631   { "nopQ",             { Ev }, 0 },
2632   { PREFIX_TABLE (PREFIX_0F1A) },
2633   { PREFIX_TABLE (PREFIX_0F1B) },
2634   { PREFIX_TABLE (PREFIX_0F1C) },
2635   { "nopQ",             { Ev }, 0 },
2636   { PREFIX_TABLE (PREFIX_0F1E) },
2637   { "nopQ",             { Ev }, 0 },
2638   /* 20 */
2639   { "movZ",             { Rm, Cm }, 0 },
2640   { "movZ",             { Rm, Dm }, 0 },
2641   { "movZ",             { Cm, Rm }, 0 },
2642   { "movZ",             { Dm, Rm }, 0 },
2643   { MOD_TABLE (MOD_0F24) },
2644   { Bad_Opcode },
2645   { MOD_TABLE (MOD_0F26) },
2646   { Bad_Opcode },
2647   /* 28 */
2648   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2649   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2650   { PREFIX_TABLE (PREFIX_0F2A) },
2651   { PREFIX_TABLE (PREFIX_0F2B) },
2652   { PREFIX_TABLE (PREFIX_0F2C) },
2653   { PREFIX_TABLE (PREFIX_0F2D) },
2654   { PREFIX_TABLE (PREFIX_0F2E) },
2655   { PREFIX_TABLE (PREFIX_0F2F) },
2656   /* 30 */
2657   { "wrmsr",            { XX }, 0 },
2658   { "rdtsc",            { XX }, 0 },
2659   { "rdmsr",            { XX }, 0 },
2660   { "rdpmc",            { XX }, 0 },
2661   { "sysenter",         { SEP }, 0 },
2662   { "sysexit",          { SEP }, 0 },
2663   { Bad_Opcode },
2664   { "getsec",           { XX }, 0 },
2665   /* 38 */
2666   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2667   { Bad_Opcode },
2668   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2669   { Bad_Opcode },
2670   { Bad_Opcode },
2671   { Bad_Opcode },
2672   { Bad_Opcode },
2673   { Bad_Opcode },
2674   /* 40 */
2675   { "cmovoS",           { Gv, Ev }, 0 },
2676   { "cmovnoS",          { Gv, Ev }, 0 },
2677   { "cmovbS",           { Gv, Ev }, 0 },
2678   { "cmovaeS",          { Gv, Ev }, 0 },
2679   { "cmoveS",           { Gv, Ev }, 0 },
2680   { "cmovneS",          { Gv, Ev }, 0 },
2681   { "cmovbeS",          { Gv, Ev }, 0 },
2682   { "cmovaS",           { Gv, Ev }, 0 },
2683   /* 48 */
2684   { "cmovsS",           { Gv, Ev }, 0 },
2685   { "cmovnsS",          { Gv, Ev }, 0 },
2686   { "cmovpS",           { Gv, Ev }, 0 },
2687   { "cmovnpS",          { Gv, Ev }, 0 },
2688   { "cmovlS",           { Gv, Ev }, 0 },
2689   { "cmovgeS",          { Gv, Ev }, 0 },
2690   { "cmovleS",          { Gv, Ev }, 0 },
2691   { "cmovgS",           { Gv, Ev }, 0 },
2692   /* 50 */
2693   { MOD_TABLE (MOD_0F50) },
2694   { PREFIX_TABLE (PREFIX_0F51) },
2695   { PREFIX_TABLE (PREFIX_0F52) },
2696   { PREFIX_TABLE (PREFIX_0F53) },
2697   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2698   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2699   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2700   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2701   /* 58 */
2702   { PREFIX_TABLE (PREFIX_0F58) },
2703   { PREFIX_TABLE (PREFIX_0F59) },
2704   { PREFIX_TABLE (PREFIX_0F5A) },
2705   { PREFIX_TABLE (PREFIX_0F5B) },
2706   { PREFIX_TABLE (PREFIX_0F5C) },
2707   { PREFIX_TABLE (PREFIX_0F5D) },
2708   { PREFIX_TABLE (PREFIX_0F5E) },
2709   { PREFIX_TABLE (PREFIX_0F5F) },
2710   /* 60 */
2711   { PREFIX_TABLE (PREFIX_0F60) },
2712   { PREFIX_TABLE (PREFIX_0F61) },
2713   { PREFIX_TABLE (PREFIX_0F62) },
2714   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2715   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2716   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2717   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2718   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2719   /* 68 */
2720   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2721   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2722   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2723   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2724   { PREFIX_TABLE (PREFIX_0F6C) },
2725   { PREFIX_TABLE (PREFIX_0F6D) },
2726   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2727   { PREFIX_TABLE (PREFIX_0F6F) },
2728   /* 70 */
2729   { PREFIX_TABLE (PREFIX_0F70) },
2730   { REG_TABLE (REG_0F71) },
2731   { REG_TABLE (REG_0F72) },
2732   { REG_TABLE (REG_0F73) },
2733   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2734   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2735   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2736   { "emms",             { XX }, PREFIX_OPCODE },
2737   /* 78 */
2738   { PREFIX_TABLE (PREFIX_0F78) },
2739   { PREFIX_TABLE (PREFIX_0F79) },
2740   { Bad_Opcode },
2741   { Bad_Opcode },
2742   { PREFIX_TABLE (PREFIX_0F7C) },
2743   { PREFIX_TABLE (PREFIX_0F7D) },
2744   { PREFIX_TABLE (PREFIX_0F7E) },
2745   { PREFIX_TABLE (PREFIX_0F7F) },
2746   /* 80 */
2747   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2748   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2749   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2750   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2751   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2752   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2753   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2755   /* 88 */
2756   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2757   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2758   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2759   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2760   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2761   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2762   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2763   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2764   /* 90 */
2765   { "seto",             { Eb }, 0 },
2766   { "setno",            { Eb }, 0 },
2767   { "setb",             { Eb }, 0 },
2768   { "setae",            { Eb }, 0 },
2769   { "sete",             { Eb }, 0 },
2770   { "setne",            { Eb }, 0 },
2771   { "setbe",            { Eb }, 0 },
2772   { "seta",             { Eb }, 0 },
2773   /* 98 */
2774   { "sets",             { Eb }, 0 },
2775   { "setns",            { Eb }, 0 },
2776   { "setp",             { Eb }, 0 },
2777   { "setnp",            { Eb }, 0 },
2778   { "setl",             { Eb }, 0 },
2779   { "setge",            { Eb }, 0 },
2780   { "setle",            { Eb }, 0 },
2781   { "setg",             { Eb }, 0 },
2782   /* a0 */
2783   { "pushT",            { fs }, 0 },
2784   { "popT",             { fs }, 0 },
2785   { "cpuid",            { XX }, 0 },
2786   { "btS",              { Ev, Gv }, 0 },
2787   { "shldS",            { Ev, Gv, Ib }, 0 },
2788   { "shldS",            { Ev, Gv, CL }, 0 },
2789   { REG_TABLE (REG_0FA6) },
2790   { REG_TABLE (REG_0FA7) },
2791   /* a8 */
2792   { "pushT",            { gs }, 0 },
2793   { "popT",             { gs }, 0 },
2794   { "rsm",              { XX }, 0 },
2795   { "btsS",             { Evh1, Gv }, 0 },
2796   { "shrdS",            { Ev, Gv, Ib }, 0 },
2797   { "shrdS",            { Ev, Gv, CL }, 0 },
2798   { REG_TABLE (REG_0FAE) },
2799   { "imulS",            { Gv, Ev }, 0 },
2800   /* b0 */
2801   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2802   { "cmpxchgS",         { Evh1, Gv }, 0 },
2803   { MOD_TABLE (MOD_0FB2) },
2804   { "btrS",             { Evh1, Gv }, 0 },
2805   { MOD_TABLE (MOD_0FB4) },
2806   { MOD_TABLE (MOD_0FB5) },
2807   { "movz{bR|x}",       { Gv, Eb }, 0 },
2808   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2809   /* b8 */
2810   { PREFIX_TABLE (PREFIX_0FB8) },
2811   { "ud1S",             { Gv, Ev }, 0 },
2812   { REG_TABLE (REG_0FBA) },
2813   { "btcS",             { Evh1, Gv }, 0 },
2814   { PREFIX_TABLE (PREFIX_0FBC) },
2815   { PREFIX_TABLE (PREFIX_0FBD) },
2816   { "movs{bR|x}",       { Gv, Eb }, 0 },
2817   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2818   /* c0 */
2819   { "xaddB",            { Ebh1, Gb }, 0 },
2820   { "xaddS",            { Evh1, Gv }, 0 },
2821   { PREFIX_TABLE (PREFIX_0FC2) },
2822   { MOD_TABLE (MOD_0FC3) },
2823   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2824   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2825   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2826   { REG_TABLE (REG_0FC7) },
2827   /* c8 */
2828   { "bswap",            { RMeAX }, 0 },
2829   { "bswap",            { RMeCX }, 0 },
2830   { "bswap",            { RMeDX }, 0 },
2831   { "bswap",            { RMeBX }, 0 },
2832   { "bswap",            { RMeSP }, 0 },
2833   { "bswap",            { RMeBP }, 0 },
2834   { "bswap",            { RMeSI }, 0 },
2835   { "bswap",            { RMeDI }, 0 },
2836   /* d0 */
2837   { PREFIX_TABLE (PREFIX_0FD0) },
2838   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2839   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2840   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2841   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2842   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2843   { PREFIX_TABLE (PREFIX_0FD6) },
2844   { MOD_TABLE (MOD_0FD7) },
2845   /* d8 */
2846   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2847   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2848   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2849   { "pand",             { MX, EM }, PREFIX_OPCODE },
2850   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2851   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2852   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2853   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2854   /* e0 */
2855   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2856   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2857   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2858   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2859   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2860   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2861   { PREFIX_TABLE (PREFIX_0FE6) },
2862   { PREFIX_TABLE (PREFIX_0FE7) },
2863   /* e8 */
2864   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2865   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2866   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2867   { "por",              { MX, EM }, PREFIX_OPCODE },
2868   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2869   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2870   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2871   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2872   /* f0 */
2873   { PREFIX_TABLE (PREFIX_0FF0) },
2874   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2875   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2876   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2877   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2878   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2879   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2880   { PREFIX_TABLE (PREFIX_0FF7) },
2881   /* f8 */
2882   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2883   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2884   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2885   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2886   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2887   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2888   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2889   { "ud0S",             { Gv, Ev }, 0 },
2890 };
2891
2892 static const unsigned char onebyte_has_modrm[256] = {
2893   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2894   /*       -------------------------------        */
2895   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2896   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2897   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2898   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2899   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2900   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2901   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2902   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2903   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2904   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2905   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2906   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2907   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2908   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2909   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2910   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2911   /*       -------------------------------        */
2912   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2913 };
2914
2915 static const unsigned char twobyte_has_modrm[256] = {
2916   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2917   /*       -------------------------------        */
2918   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2919   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2920   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2921   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2922   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2923   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2924   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2925   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2926   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2927   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2928   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2929   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2930   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2931   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2932   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2933   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2934   /*       -------------------------------        */
2935   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2936 };
2937
2938 static char obuf[100];
2939 static char *obufp;
2940 static char *mnemonicendp;
2941 static char scratchbuf[100];
2942 static unsigned char *start_codep;
2943 static unsigned char *insn_codep;
2944 static unsigned char *codep;
2945 static unsigned char *end_codep;
2946 static int last_lock_prefix;
2947 static int last_repz_prefix;
2948 static int last_repnz_prefix;
2949 static int last_data_prefix;
2950 static int last_addr_prefix;
2951 static int last_rex_prefix;
2952 static int last_seg_prefix;
2953 static int fwait_prefix;
2954 /* The active segment register prefix.  */
2955 static int active_seg_prefix;
2956 #define MAX_CODE_LENGTH 15
2957 /* We can up to 14 prefixes since the maximum instruction length is
2958    15bytes.  */
2959 static int all_prefixes[MAX_CODE_LENGTH - 1];
2960 static disassemble_info *the_info;
2961 static struct
2962   {
2963     int mod;
2964     int reg;
2965     int rm;
2966   }
2967 modrm;
2968 static unsigned char need_modrm;
2969 static struct
2970   {
2971     int scale;
2972     int index;
2973     int base;
2974   }
2975 sib;
2976 static struct
2977   {
2978     int register_specifier;
2979     int length;
2980     int prefix;
2981     int w;
2982     int evex;
2983     int r;
2984     int v;
2985     int mask_register_specifier;
2986     int zeroing;
2987     int ll;
2988     int b;
2989   }
2990 vex;
2991 static unsigned char need_vex;
2992 static unsigned char need_vex_reg;
2993 static unsigned char vex_w_done;
2994
2995 struct op
2996   {
2997     const char *name;
2998     unsigned int len;
2999   };
3000
3001 /* If we are accessing mod/rm/reg without need_modrm set, then the
3002    values are stale.  Hitting this abort likely indicates that you
3003    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3004 #define MODRM_CHECK  if (!need_modrm) abort ()
3005
3006 static const char **names64;
3007 static const char **names32;
3008 static const char **names16;
3009 static const char **names8;
3010 static const char **names8rex;
3011 static const char **names_seg;
3012 static const char *index64;
3013 static const char *index32;
3014 static const char **index16;
3015 static const char **names_bnd;
3016
3017 static const char *intel_names64[] = {
3018   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3019   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3020 };
3021 static const char *intel_names32[] = {
3022   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3023   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3024 };
3025 static const char *intel_names16[] = {
3026   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3027   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3028 };
3029 static const char *intel_names8[] = {
3030   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3031 };
3032 static const char *intel_names8rex[] = {
3033   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3034   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3035 };
3036 static const char *intel_names_seg[] = {
3037   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3038 };
3039 static const char *intel_index64 = "riz";
3040 static const char *intel_index32 = "eiz";
3041 static const char *intel_index16[] = {
3042   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3043 };
3044
3045 static const char *att_names64[] = {
3046   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3047   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3048 };
3049 static const char *att_names32[] = {
3050   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3051   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3052 };
3053 static const char *att_names16[] = {
3054   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3055   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3056 };
3057 static const char *att_names8[] = {
3058   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3059 };
3060 static const char *att_names8rex[] = {
3061   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3062   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3063 };
3064 static const char *att_names_seg[] = {
3065   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3066 };
3067 static const char *att_index64 = "%riz";
3068 static const char *att_index32 = "%eiz";
3069 static const char *att_index16[] = {
3070   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3071 };
3072
3073 static const char **names_mm;
3074 static const char *intel_names_mm[] = {
3075   "mm0", "mm1", "mm2", "mm3",
3076   "mm4", "mm5", "mm6", "mm7"
3077 };
3078 static const char *att_names_mm[] = {
3079   "%mm0", "%mm1", "%mm2", "%mm3",
3080   "%mm4", "%mm5", "%mm6", "%mm7"
3081 };
3082
3083 static const char *intel_names_bnd[] = {
3084   "bnd0", "bnd1", "bnd2", "bnd3"
3085 };
3086
3087 static const char *att_names_bnd[] = {
3088   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3089 };
3090
3091 static const char **names_xmm;
3092 static const char *intel_names_xmm[] = {
3093   "xmm0", "xmm1", "xmm2", "xmm3",
3094   "xmm4", "xmm5", "xmm6", "xmm7",
3095   "xmm8", "xmm9", "xmm10", "xmm11",
3096   "xmm12", "xmm13", "xmm14", "xmm15",
3097   "xmm16", "xmm17", "xmm18", "xmm19",
3098   "xmm20", "xmm21", "xmm22", "xmm23",
3099   "xmm24", "xmm25", "xmm26", "xmm27",
3100   "xmm28", "xmm29", "xmm30", "xmm31"
3101 };
3102 static const char *att_names_xmm[] = {
3103   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3104   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3105   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3106   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3107   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3108   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3109   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3110   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3111 };
3112
3113 static const char **names_ymm;
3114 static const char *intel_names_ymm[] = {
3115   "ymm0", "ymm1", "ymm2", "ymm3",
3116   "ymm4", "ymm5", "ymm6", "ymm7",
3117   "ymm8", "ymm9", "ymm10", "ymm11",
3118   "ymm12", "ymm13", "ymm14", "ymm15",
3119   "ymm16", "ymm17", "ymm18", "ymm19",
3120   "ymm20", "ymm21", "ymm22", "ymm23",
3121   "ymm24", "ymm25", "ymm26", "ymm27",
3122   "ymm28", "ymm29", "ymm30", "ymm31"
3123 };
3124 static const char *att_names_ymm[] = {
3125   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3126   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3127   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3128   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3129   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3130   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3131   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3132   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3133 };
3134
3135 static const char **names_zmm;
3136 static const char *intel_names_zmm[] = {
3137   "zmm0", "zmm1", "zmm2", "zmm3",
3138   "zmm4", "zmm5", "zmm6", "zmm7",
3139   "zmm8", "zmm9", "zmm10", "zmm11",
3140   "zmm12", "zmm13", "zmm14", "zmm15",
3141   "zmm16", "zmm17", "zmm18", "zmm19",
3142   "zmm20", "zmm21", "zmm22", "zmm23",
3143   "zmm24", "zmm25", "zmm26", "zmm27",
3144   "zmm28", "zmm29", "zmm30", "zmm31"
3145 };
3146 static const char *att_names_zmm[] = {
3147   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3148   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3149   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3150   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3151   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3152   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3153   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3154   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3155 };
3156
3157 static const char **names_mask;
3158 static const char *intel_names_mask[] = {
3159   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3160 };
3161 static const char *att_names_mask[] = {
3162   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3163 };
3164
3165 static const char *names_rounding[] =
3166 {
3167   "{rn-sae}",
3168   "{rd-sae}",
3169   "{ru-sae}",
3170   "{rz-sae}"
3171 };
3172
3173 static const struct dis386 reg_table[][8] = {
3174   /* REG_80 */
3175   {
3176     { "addA",   { Ebh1, Ib }, 0 },
3177     { "orA",    { Ebh1, Ib }, 0 },
3178     { "adcA",   { Ebh1, Ib }, 0 },
3179     { "sbbA",   { Ebh1, Ib }, 0 },
3180     { "andA",   { Ebh1, Ib }, 0 },
3181     { "subA",   { Ebh1, Ib }, 0 },
3182     { "xorA",   { Ebh1, Ib }, 0 },
3183     { "cmpA",   { Eb, Ib }, 0 },
3184   },
3185   /* REG_81 */
3186   {
3187     { "addQ",   { Evh1, Iv }, 0 },
3188     { "orQ",    { Evh1, Iv }, 0 },
3189     { "adcQ",   { Evh1, Iv }, 0 },
3190     { "sbbQ",   { Evh1, Iv }, 0 },
3191     { "andQ",   { Evh1, Iv }, 0 },
3192     { "subQ",   { Evh1, Iv }, 0 },
3193     { "xorQ",   { Evh1, Iv }, 0 },
3194     { "cmpQ",   { Ev, Iv }, 0 },
3195   },
3196   /* REG_83 */
3197   {
3198     { "addQ",   { Evh1, sIb }, 0 },
3199     { "orQ",    { Evh1, sIb }, 0 },
3200     { "adcQ",   { Evh1, sIb }, 0 },
3201     { "sbbQ",   { Evh1, sIb }, 0 },
3202     { "andQ",   { Evh1, sIb }, 0 },
3203     { "subQ",   { Evh1, sIb }, 0 },
3204     { "xorQ",   { Evh1, sIb }, 0 },
3205     { "cmpQ",   { Ev, sIb }, 0 },
3206   },
3207   /* REG_8F */
3208   {
3209     { "popU",   { stackEv }, 0 },
3210     { XOP_8F_TABLE (XOP_09) },
3211     { Bad_Opcode },
3212     { Bad_Opcode },
3213     { Bad_Opcode },
3214     { XOP_8F_TABLE (XOP_09) },
3215   },
3216   /* REG_C0 */
3217   {
3218     { "rolA",   { Eb, Ib }, 0 },
3219     { "rorA",   { Eb, Ib }, 0 },
3220     { "rclA",   { Eb, Ib }, 0 },
3221     { "rcrA",   { Eb, Ib }, 0 },
3222     { "shlA",   { Eb, Ib }, 0 },
3223     { "shrA",   { Eb, Ib }, 0 },
3224     { "shlA",   { Eb, Ib }, 0 },
3225     { "sarA",   { Eb, Ib }, 0 },
3226   },
3227   /* REG_C1 */
3228   {
3229     { "rolQ",   { Ev, Ib }, 0 },
3230     { "rorQ",   { Ev, Ib }, 0 },
3231     { "rclQ",   { Ev, Ib }, 0 },
3232     { "rcrQ",   { Ev, Ib }, 0 },
3233     { "shlQ",   { Ev, Ib }, 0 },
3234     { "shrQ",   { Ev, Ib }, 0 },
3235     { "shlQ",   { Ev, Ib }, 0 },
3236     { "sarQ",   { Ev, Ib }, 0 },
3237   },
3238   /* REG_C6 */
3239   {
3240     { "movA",   { Ebh3, Ib }, 0 },
3241     { Bad_Opcode },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { MOD_TABLE (MOD_C6_REG_7) },
3248   },
3249   /* REG_C7 */
3250   {
3251     { "movQ",   { Evh3, Iv }, 0 },
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { MOD_TABLE (MOD_C7_REG_7) },
3259   },
3260   /* REG_D0 */
3261   {
3262     { "rolA",   { Eb, I1 }, 0 },
3263     { "rorA",   { Eb, I1 }, 0 },
3264     { "rclA",   { Eb, I1 }, 0 },
3265     { "rcrA",   { Eb, I1 }, 0 },
3266     { "shlA",   { Eb, I1 }, 0 },
3267     { "shrA",   { Eb, I1 }, 0 },
3268     { "shlA",   { Eb, I1 }, 0 },
3269     { "sarA",   { Eb, I1 }, 0 },
3270   },
3271   /* REG_D1 */
3272   {
3273     { "rolQ",   { Ev, I1 }, 0 },
3274     { "rorQ",   { Ev, I1 }, 0 },
3275     { "rclQ",   { Ev, I1 }, 0 },
3276     { "rcrQ",   { Ev, I1 }, 0 },
3277     { "shlQ",   { Ev, I1 }, 0 },
3278     { "shrQ",   { Ev, I1 }, 0 },
3279     { "shlQ",   { Ev, I1 }, 0 },
3280     { "sarQ",   { Ev, I1 }, 0 },
3281   },
3282   /* REG_D2 */
3283   {
3284     { "rolA",   { Eb, CL }, 0 },
3285     { "rorA",   { Eb, CL }, 0 },
3286     { "rclA",   { Eb, CL }, 0 },
3287     { "rcrA",   { Eb, CL }, 0 },
3288     { "shlA",   { Eb, CL }, 0 },
3289     { "shrA",   { Eb, CL }, 0 },
3290     { "shlA",   { Eb, CL }, 0 },
3291     { "sarA",   { Eb, CL }, 0 },
3292   },
3293   /* REG_D3 */
3294   {
3295     { "rolQ",   { Ev, CL }, 0 },
3296     { "rorQ",   { Ev, CL }, 0 },
3297     { "rclQ",   { Ev, CL }, 0 },
3298     { "rcrQ",   { Ev, CL }, 0 },
3299     { "shlQ",   { Ev, CL }, 0 },
3300     { "shrQ",   { Ev, CL }, 0 },
3301     { "shlQ",   { Ev, CL }, 0 },
3302     { "sarQ",   { Ev, CL }, 0 },
3303   },
3304   /* REG_F6 */
3305   {
3306     { "testA",  { Eb, Ib }, 0 },
3307     { "testA",  { Eb, Ib }, 0 },
3308     { "notA",   { Ebh1 }, 0 },
3309     { "negA",   { Ebh1 }, 0 },
3310     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3311     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3312     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3313     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3314   },
3315   /* REG_F7 */
3316   {
3317     { "testQ",  { Ev, Iv }, 0 },
3318     { "testQ",  { Ev, Iv }, 0 },
3319     { "notQ",   { Evh1 }, 0 },
3320     { "negQ",   { Evh1 }, 0 },
3321     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3322     { "imulQ",  { Ev }, 0 },
3323     { "divQ",   { Ev }, 0 },
3324     { "idivQ",  { Ev }, 0 },
3325   },
3326   /* REG_FE */
3327   {
3328     { "incA",   { Ebh1 }, 0 },
3329     { "decA",   { Ebh1 }, 0 },
3330   },
3331   /* REG_FF */
3332   {
3333     { "incQ",   { Evh1 }, 0 },
3334     { "decQ",   { Evh1 }, 0 },
3335     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3336     { MOD_TABLE (MOD_FF_REG_3) },
3337     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3338     { MOD_TABLE (MOD_FF_REG_5) },
3339     { "pushU",  { stackEv }, 0 },
3340     { Bad_Opcode },
3341   },
3342   /* REG_0F00 */
3343   {
3344     { "sldtD",  { Sv }, 0 },
3345     { "strD",   { Sv }, 0 },
3346     { "lldt",   { Ew }, 0 },
3347     { "ltr",    { Ew }, 0 },
3348     { "verr",   { Ew }, 0 },
3349     { "verw",   { Ew }, 0 },
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352   },
3353   /* REG_0F01 */
3354   {
3355     { MOD_TABLE (MOD_0F01_REG_0) },
3356     { MOD_TABLE (MOD_0F01_REG_1) },
3357     { MOD_TABLE (MOD_0F01_REG_2) },
3358     { MOD_TABLE (MOD_0F01_REG_3) },
3359     { "smswD",  { Sv }, 0 },
3360     { MOD_TABLE (MOD_0F01_REG_5) },
3361     { "lmsw",   { Ew }, 0 },
3362     { MOD_TABLE (MOD_0F01_REG_7) },
3363   },
3364   /* REG_0F0D */
3365   {
3366     { "prefetch",       { Mb }, 0 },
3367     { "prefetchw",      { Mb }, 0 },
3368     { "prefetchwt1",    { Mb }, 0 },
3369     { "prefetch",       { Mb }, 0 },
3370     { "prefetch",       { Mb }, 0 },
3371     { "prefetch",       { Mb }, 0 },
3372     { "prefetch",       { Mb }, 0 },
3373     { "prefetch",       { Mb }, 0 },
3374   },
3375   /* REG_0F18 */
3376   {
3377     { MOD_TABLE (MOD_0F18_REG_0) },
3378     { MOD_TABLE (MOD_0F18_REG_1) },
3379     { MOD_TABLE (MOD_0F18_REG_2) },
3380     { MOD_TABLE (MOD_0F18_REG_3) },
3381     { MOD_TABLE (MOD_0F18_REG_4) },
3382     { MOD_TABLE (MOD_0F18_REG_5) },
3383     { MOD_TABLE (MOD_0F18_REG_6) },
3384     { MOD_TABLE (MOD_0F18_REG_7) },
3385   },
3386   /* REG_0F1C_P_0_MOD_0 */
3387   {
3388     { "cldemote",       { Mb }, 0 },
3389     { "nopQ",           { Ev }, 0 },
3390     { "nopQ",           { Ev }, 0 },
3391     { "nopQ",           { Ev }, 0 },
3392     { "nopQ",           { Ev }, 0 },
3393     { "nopQ",           { Ev }, 0 },
3394     { "nopQ",           { Ev }, 0 },
3395     { "nopQ",           { Ev }, 0 },
3396   },
3397   /* REG_0F1E_P_1_MOD_3 */
3398   {
3399     { "nopQ",           { Ev }, 0 },
3400     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3401     { "nopQ",           { Ev }, 0 },
3402     { "nopQ",           { Ev }, 0 },
3403     { "nopQ",           { Ev }, 0 },
3404     { "nopQ",           { Ev }, 0 },
3405     { "nopQ",           { Ev }, 0 },
3406     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3407   },
3408   /* REG_0F71 */
3409   {
3410     { Bad_Opcode },
3411     { Bad_Opcode },
3412     { MOD_TABLE (MOD_0F71_REG_2) },
3413     { Bad_Opcode },
3414     { MOD_TABLE (MOD_0F71_REG_4) },
3415     { Bad_Opcode },
3416     { MOD_TABLE (MOD_0F71_REG_6) },
3417   },
3418   /* REG_0F72 */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { MOD_TABLE (MOD_0F72_REG_2) },
3423     { Bad_Opcode },
3424     { MOD_TABLE (MOD_0F72_REG_4) },
3425     { Bad_Opcode },
3426     { MOD_TABLE (MOD_0F72_REG_6) },
3427   },
3428   /* REG_0F73 */
3429   {
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { MOD_TABLE (MOD_0F73_REG_2) },
3433     { MOD_TABLE (MOD_0F73_REG_3) },
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { MOD_TABLE (MOD_0F73_REG_6) },
3437     { MOD_TABLE (MOD_0F73_REG_7) },
3438   },
3439   /* REG_0FA6 */
3440   {
3441     { "montmul",        { { OP_0f07, 0 } }, 0 },
3442     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3443     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3444   },
3445   /* REG_0FA7 */
3446   {
3447     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3448     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3449     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3450     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3451     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3452     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3453   },
3454   /* REG_0FAE */
3455   {
3456     { MOD_TABLE (MOD_0FAE_REG_0) },
3457     { MOD_TABLE (MOD_0FAE_REG_1) },
3458     { MOD_TABLE (MOD_0FAE_REG_2) },
3459     { MOD_TABLE (MOD_0FAE_REG_3) },
3460     { MOD_TABLE (MOD_0FAE_REG_4) },
3461     { MOD_TABLE (MOD_0FAE_REG_5) },
3462     { MOD_TABLE (MOD_0FAE_REG_6) },
3463     { MOD_TABLE (MOD_0FAE_REG_7) },
3464   },
3465   /* REG_0FBA */
3466   {
3467     { Bad_Opcode },
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { "btQ",    { Ev, Ib }, 0 },
3472     { "btsQ",   { Evh1, Ib }, 0 },
3473     { "btrQ",   { Evh1, Ib }, 0 },
3474     { "btcQ",   { Evh1, Ib }, 0 },
3475   },
3476   /* REG_0FC7 */
3477   {
3478     { Bad_Opcode },
3479     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0FC7_REG_3) },
3482     { MOD_TABLE (MOD_0FC7_REG_4) },
3483     { MOD_TABLE (MOD_0FC7_REG_5) },
3484     { MOD_TABLE (MOD_0FC7_REG_6) },
3485     { MOD_TABLE (MOD_0FC7_REG_7) },
3486   },
3487   /* REG_VEX_0F71 */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3492     { Bad_Opcode },
3493     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3494     { Bad_Opcode },
3495     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3496   },
3497   /* REG_VEX_0F72 */
3498   {
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3502     { Bad_Opcode },
3503     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3504     { Bad_Opcode },
3505     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3506   },
3507   /* REG_VEX_0F73 */
3508   {
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3512     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3516     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3517   },
3518   /* REG_VEX_0FAE */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3523     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3524   },
3525   /* REG_VEX_0F38F3 */
3526   {
3527     { Bad_Opcode },
3528     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3529     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3530     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3531   },
3532   /* REG_XOP_LWPCB */
3533   {
3534     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3535     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3536   },
3537   /* REG_XOP_LWP */
3538   {
3539     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3540     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3541   },
3542   /* REG_XOP_TBM_01 */
3543   {
3544     { Bad_Opcode },
3545     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3546     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3547     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3548     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3549     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3550     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3551     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3552   },
3553   /* REG_XOP_TBM_02 */
3554   {
3555     { Bad_Opcode },
3556     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3557     { Bad_Opcode },
3558     { Bad_Opcode },
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3562   },
3563
3564 #include "i386-dis-evex-reg.h"
3565 };
3566
3567 static const struct dis386 prefix_table[][4] = {
3568   /* PREFIX_90 */
3569   {
3570     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3571     { "pause", { XX }, 0 },
3572     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3573     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3574   },
3575
3576   /* PREFIX_0F01_REG_3_RM_1 */
3577   {
3578     { "vmmcall",        { Skip_MODRM }, 0 },
3579     { "vmgexit",        { Skip_MODRM }, 0 },
3580     { Bad_Opcode },
3581     { "vmgexit",        { Skip_MODRM }, 0 },
3582   },
3583
3584   /* PREFIX_0F01_REG_5_MOD_0 */
3585   {
3586     { Bad_Opcode },
3587     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3588   },
3589
3590   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3591   {
3592     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3593     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3594     { Bad_Opcode },
3595     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3596   },
3597
3598   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3599   {
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3604   },
3605
3606   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3607   {
3608     { Bad_Opcode },
3609     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3610   },
3611
3612   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3613   {
3614     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3615     { "mcommit",        { Skip_MODRM }, 0 },
3616   },
3617
3618   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3619   {
3620     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3621   },
3622
3623   /* PREFIX_0F09 */
3624   {
3625     { "wbinvd",   { XX }, 0 },
3626     { "wbnoinvd", { XX }, 0 },
3627   },
3628
3629   /* PREFIX_0F10 */
3630   {
3631     { "movups", { XM, EXx }, PREFIX_OPCODE },
3632     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3633     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3634     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3635   },
3636
3637   /* PREFIX_0F11 */
3638   {
3639     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3640     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3641     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3642     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3643   },
3644
3645   /* PREFIX_0F12 */
3646   {
3647     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3648     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3649     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3650     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_0F16 */
3654   {
3655     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3656     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3657     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3658   },
3659
3660   /* PREFIX_0F1A */
3661   {
3662     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3663     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3664     { "bndmov", { Gbnd, Ebnd }, 0 },
3665     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3666   },
3667
3668   /* PREFIX_0F1B */
3669   {
3670     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3671     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3672     { "bndmov", { EbndS, Gbnd }, 0 },
3673     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3674   },
3675
3676   /* PREFIX_0F1C */
3677   {
3678     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3679     { "nopQ",   { Ev }, PREFIX_OPCODE },
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681     { "nopQ",   { Ev }, PREFIX_OPCODE },
3682   },
3683
3684   /* PREFIX_0F1E */
3685   {
3686     { "nopQ",   { Ev }, PREFIX_OPCODE },
3687     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3688     { "nopQ",   { Ev }, PREFIX_OPCODE },
3689     { "nopQ",   { Ev }, PREFIX_OPCODE },
3690   },
3691
3692   /* PREFIX_0F2A */
3693   {
3694     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3695     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3696     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3697     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3698   },
3699
3700   /* PREFIX_0F2B */
3701   {
3702     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3703     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3704     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3705     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3706   },
3707
3708   /* PREFIX_0F2C */
3709   {
3710     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3711     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3712     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3713     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3714   },
3715
3716   /* PREFIX_0F2D */
3717   {
3718     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3719     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3720     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3721     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F2E */
3725   {
3726     { "ucomiss",{ XM, EXd }, 0 },
3727     { Bad_Opcode },
3728     { "ucomisd",{ XM, EXq }, 0 },
3729   },
3730
3731   /* PREFIX_0F2F */
3732   {
3733     { "comiss", { XM, EXd }, 0 },
3734     { Bad_Opcode },
3735     { "comisd", { XM, EXq }, 0 },
3736   },
3737
3738   /* PREFIX_0F51 */
3739   {
3740     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3741     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3742     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3743     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3744   },
3745
3746   /* PREFIX_0F52 */
3747   {
3748     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3749     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F53 */
3753   {
3754     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3755     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3756   },
3757
3758   /* PREFIX_0F58 */
3759   {
3760     { "addps", { XM, EXx }, PREFIX_OPCODE },
3761     { "addss", { XM, EXd }, PREFIX_OPCODE },
3762     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3763     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3764   },
3765
3766   /* PREFIX_0F59 */
3767   {
3768     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3769     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3770     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3771     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3772   },
3773
3774   /* PREFIX_0F5A */
3775   {
3776     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3777     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3778     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3779     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F5B */
3783   {
3784     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3785     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3786     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F5C */
3790   {
3791     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3793     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3794     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F5D */
3798   {
3799     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3800     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3801     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3802     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F5E */
3806   {
3807     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3808     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3809     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3810     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F5F */
3814   {
3815     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3816     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3817     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3818     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3819   },
3820
3821   /* PREFIX_0F60 */
3822   {
3823     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3824     { Bad_Opcode },
3825     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F61 */
3829   {
3830     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3831     { Bad_Opcode },
3832     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F62 */
3836   {
3837     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3838     { Bad_Opcode },
3839     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F6C */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F6D */
3850   {
3851     { Bad_Opcode },
3852     { Bad_Opcode },
3853     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F6F */
3857   {
3858     { "movq",   { MX, EM }, PREFIX_OPCODE },
3859     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3860     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F70 */
3864   {
3865     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3866     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3867     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3868     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F73_REG_3 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "psrldq", { XS, Ib }, 0 },
3876   },
3877
3878   /* PREFIX_0F73_REG_7 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "pslldq", { XS, Ib }, 0 },
3883   },
3884
3885   /* PREFIX_0F78 */
3886   {
3887     {"vmread",  { Em, Gm }, 0 },
3888     { Bad_Opcode },
3889     {"extrq",   { XS, Ib, Ib }, 0 },
3890     {"insertq", { XM, XS, Ib, Ib }, 0 },
3891   },
3892
3893   /* PREFIX_0F79 */
3894   {
3895     {"vmwrite", { Gm, Em }, 0 },
3896     { Bad_Opcode },
3897     {"extrq",   { XM, XS }, 0 },
3898     {"insertq", { XM, XS }, 0 },
3899   },
3900
3901   /* PREFIX_0F7C */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3906     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3907   },
3908
3909   /* PREFIX_0F7D */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3914     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3915   },
3916
3917   /* PREFIX_0F7E */
3918   {
3919     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3920     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3921     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F7F */
3925   {
3926     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3927     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3928     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3929   },
3930
3931   /* PREFIX_0FAE_REG_0_MOD_3 */
3932   {
3933     { Bad_Opcode },
3934     { "rdfsbase", { Ev }, 0 },
3935   },
3936
3937   /* PREFIX_0FAE_REG_1_MOD_3 */
3938   {
3939     { Bad_Opcode },
3940     { "rdgsbase", { Ev }, 0 },
3941   },
3942
3943   /* PREFIX_0FAE_REG_2_MOD_3 */
3944   {
3945     { Bad_Opcode },
3946     { "wrfsbase", { Ev }, 0 },
3947   },
3948
3949   /* PREFIX_0FAE_REG_3_MOD_3 */
3950   {
3951     { Bad_Opcode },
3952     { "wrgsbase", { Ev }, 0 },
3953   },
3954
3955   /* PREFIX_0FAE_REG_4_MOD_0 */
3956   {
3957     { "xsave",  { FXSAVE }, 0 },
3958     { "ptwrite%LQ", { Edq }, 0 },
3959   },
3960
3961   /* PREFIX_0FAE_REG_4_MOD_3 */
3962   {
3963     { Bad_Opcode },
3964     { "ptwrite%LQ", { Edq }, 0 },
3965   },
3966
3967   /* PREFIX_0FAE_REG_5_MOD_0 */
3968   {
3969     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0FAE_REG_5_MOD_3 */
3973   {
3974     { "lfence",         { Skip_MODRM }, 0 },
3975     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_0FAE_REG_6_MOD_0 */
3979   {
3980     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3981     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3982     { "clwb",   { Mb }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_0FAE_REG_6_MOD_3 */
3986   {
3987     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3988     { "umonitor",       { Eva }, PREFIX_OPCODE },
3989     { "tpause", { Edq }, PREFIX_OPCODE },
3990     { "umwait", { Edq }, PREFIX_OPCODE },
3991   },
3992
3993   /* PREFIX_0FAE_REG_7_MOD_0 */
3994   {
3995     { "clflush",        { Mb }, 0 },
3996     { Bad_Opcode },
3997     { "clflushopt",     { Mb }, 0 },
3998   },
3999
4000   /* PREFIX_0FB8 */
4001   {
4002     { Bad_Opcode },
4003     { "popcntS", { Gv, Ev }, 0 },
4004   },
4005
4006   /* PREFIX_0FBC */
4007   {
4008     { "bsfS",   { Gv, Ev }, 0 },
4009     { "tzcntS", { Gv, Ev }, 0 },
4010     { "bsfS",   { Gv, Ev }, 0 },
4011   },
4012
4013   /* PREFIX_0FBD */
4014   {
4015     { "bsrS",   { Gv, Ev }, 0 },
4016     { "lzcntS", { Gv, Ev }, 0 },
4017     { "bsrS",   { Gv, Ev }, 0 },
4018   },
4019
4020   /* PREFIX_0FC2 */
4021   {
4022     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4023     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4024     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4025     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0FC3_MOD_0 */
4029   {
4030     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0FC7_REG_6_MOD_0 */
4034   {
4035     { "vmptrld",{ Mq }, 0 },
4036     { "vmxon",  { Mq }, 0 },
4037     { "vmclear",{ Mq }, 0 },
4038   },
4039
4040   /* PREFIX_0FC7_REG_6_MOD_3 */
4041   {
4042     { "rdrand", { Ev }, 0 },
4043     { Bad_Opcode },
4044     { "rdrand", { Ev }, 0 }
4045   },
4046
4047   /* PREFIX_0FC7_REG_7_MOD_3 */
4048   {
4049     { "rdseed", { Ev }, 0 },
4050     { "rdpid",  { Em }, 0 },
4051     { "rdseed", { Ev }, 0 },
4052   },
4053
4054   /* PREFIX_0FD0 */
4055   {
4056     { Bad_Opcode },
4057     { Bad_Opcode },
4058     { "addsubpd", { XM, EXx }, 0 },
4059     { "addsubps", { XM, EXx }, 0 },
4060   },
4061
4062   /* PREFIX_0FD6 */
4063   {
4064     { Bad_Opcode },
4065     { "movq2dq",{ XM, MS }, 0 },
4066     { "movq",   { EXqS, XM }, 0 },
4067     { "movdq2q",{ MX, XS }, 0 },
4068   },
4069
4070   /* PREFIX_0FE6 */
4071   {
4072     { Bad_Opcode },
4073     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4074     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4075     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0FE7 */
4079   {
4080     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4081     { Bad_Opcode },
4082     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4083   },
4084
4085   /* PREFIX_0FF0 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4091   },
4092
4093   /* PREFIX_0FF7 */
4094   {
4095     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4096     { Bad_Opcode },
4097     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4098   },
4099
4100   /* PREFIX_0F3810 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4105   },
4106
4107   /* PREFIX_0F3814 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0F3815 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F3817 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4126   },
4127
4128   /* PREFIX_0F3820 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3821 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3822 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3823 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3824 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3825 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3828 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3829 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F382A */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4189   },
4190
4191   /* PREFIX_0F382B */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3830 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3831 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3832 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3833 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3834 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3835 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3837 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3838 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3839 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F383A */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F383B */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F383C */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F383D */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F383E */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383F */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3840 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3841 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3880 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3881 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3882 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F38C8 */
4339   {
4340     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F38C9 */
4344   {
4345     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F38CA */
4349   {
4350     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F38CB */
4354   {
4355     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38CC */
4359   {
4360     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38CD */
4364   {
4365     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38CF */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38DB */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38DC */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38DD */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38DE */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38DF */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38F0 */
4411   {
4412     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4413     { Bad_Opcode },
4414     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4415     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38F1 */
4419   {
4420     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4421     { Bad_Opcode },
4422     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4423     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38F5 */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4431   },
4432
4433   /* PREFIX_0F38F6 */
4434   {
4435     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4436     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4437     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4438     { Bad_Opcode },
4439   },
4440
4441   /* PREFIX_0F38F8 */
4442   {
4443     { Bad_Opcode },
4444     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4445     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4446     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4447   },
4448
4449   /* PREFIX_0F38F9 */
4450   {
4451     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4452   },
4453
4454   /* PREFIX_0F3A08 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3A09 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3A0A */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A0B */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0C */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A0D */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A0E */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A14 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A15 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A16 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A17 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A20 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A21 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A22 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A40 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A41 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A42 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A44 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A60 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A61 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A62 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A63 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3ACC */
4609   {
4610     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3ACE */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3ACF */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3ADF */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_VEX_0F10 */
4635   {
4636     { "vmovups",        { XM, EXx }, 0 },
4637     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4638     { "vmovupd",        { XM, EXx }, 0 },
4639     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4640   },
4641
4642   /* PREFIX_VEX_0F11 */
4643   {
4644     { "vmovups",        { EXxS, XM }, 0 },
4645     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4646     { "vmovupd",        { EXxS, XM }, 0 },
4647     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4648   },
4649
4650   /* PREFIX_VEX_0F12 */
4651   {
4652     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4653     { "vmovsldup",      { XM, EXx }, 0 },
4654     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4655     { "vmovddup",       { XM, EXymmq }, 0 },
4656   },
4657
4658   /* PREFIX_VEX_0F16 */
4659   {
4660     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4661     { "vmovshdup",      { XM, EXx }, 0 },
4662     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4663   },
4664
4665   /* PREFIX_VEX_0F2A */
4666   {
4667     { Bad_Opcode },
4668     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4669     { Bad_Opcode },
4670     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4671   },
4672
4673   /* PREFIX_VEX_0F2C */
4674   {
4675     { Bad_Opcode },
4676     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4677     { Bad_Opcode },
4678     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4679   },
4680
4681   /* PREFIX_VEX_0F2D */
4682   {
4683     { Bad_Opcode },
4684     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4685     { Bad_Opcode },
4686     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4687   },
4688
4689   /* PREFIX_VEX_0F2E */
4690   {
4691     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4692     { Bad_Opcode },
4693     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4694   },
4695
4696   /* PREFIX_VEX_0F2F */
4697   {
4698     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4699     { Bad_Opcode },
4700     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4701   },
4702
4703   /* PREFIX_VEX_0F41 */
4704   {
4705     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F42 */
4711   {
4712     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F44 */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F45 */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F46 */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F47 */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F4A */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F4B */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F51 */
4760   {
4761     { "vsqrtps",        { XM, EXx }, 0 },
4762     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4763     { "vsqrtpd",        { XM, EXx }, 0 },
4764     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4765   },
4766
4767   /* PREFIX_VEX_0F52 */
4768   {
4769     { "vrsqrtps",       { XM, EXx }, 0 },
4770     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4771   },
4772
4773   /* PREFIX_VEX_0F53 */
4774   {
4775     { "vrcpps",         { XM, EXx }, 0 },
4776     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4777   },
4778
4779   /* PREFIX_VEX_0F58 */
4780   {
4781     { "vaddps",         { XM, Vex, EXx }, 0 },
4782     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4783     { "vaddpd",         { XM, Vex, EXx }, 0 },
4784     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4785   },
4786
4787   /* PREFIX_VEX_0F59 */
4788   {
4789     { "vmulps",         { XM, Vex, EXx }, 0 },
4790     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4791     { "vmulpd",         { XM, Vex, EXx }, 0 },
4792     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4793   },
4794
4795   /* PREFIX_VEX_0F5A */
4796   {
4797     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4798     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4799     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4800     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F5B */
4804   {
4805     { "vcvtdq2ps",      { XM, EXx }, 0 },
4806     { "vcvttps2dq",     { XM, EXx }, 0 },
4807     { "vcvtps2dq",      { XM, EXx }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F5C */
4811   {
4812     { "vsubps",         { XM, Vex, EXx }, 0 },
4813     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814     { "vsubpd",         { XM, Vex, EXx }, 0 },
4815     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F5D */
4819   {
4820     { "vminps",         { XM, Vex, EXx }, 0 },
4821     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4822     { "vminpd",         { XM, Vex, EXx }, 0 },
4823     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4824   },
4825
4826   /* PREFIX_VEX_0F5E */
4827   {
4828     { "vdivps",         { XM, Vex, EXx }, 0 },
4829     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4830     { "vdivpd",         { XM, Vex, EXx }, 0 },
4831     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4832   },
4833
4834   /* PREFIX_VEX_0F5F */
4835   {
4836     { "vmaxps",         { XM, Vex, EXx }, 0 },
4837     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4838     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4839     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F60 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F61 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F62 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F63 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F64 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F65 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F66 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F67 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F68 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F69 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F6A */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F6B */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F6C */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F6D */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F6E */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F6F */
4948   {
4949     { Bad_Opcode },
4950     { "vmovdqu",        { XM, EXx }, 0 },
4951     { "vmovdqa",        { XM, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F70 */
4955   {
4956     { Bad_Opcode },
4957     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4958     { "vpshufd",        { XM, EXx, Ib }, 0 },
4959     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F71_REG_2 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F71_REG_4 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpsraw",         { Vex, XS, Ib }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F71_REG_6 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vpsllw",         { Vex, XS, Ib }, 0 },
4981   },
4982
4983   /* PREFIX_VEX_0F72_REG_2 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { "vpsrld",         { Vex, XS, Ib }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F72_REG_4 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { "vpsrad",         { Vex, XS, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F72_REG_6 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpslld",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F73_REG_2 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F73_REG_3 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F73_REG_6 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsllq",         { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F73_REG_7 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpslldq",        { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F74 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F75 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F76 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F77 */
5054   {
5055     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5056   },
5057
5058   /* PREFIX_VEX_0F7C */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5063     { "vhaddps",        { XM, Vex, EXx }, 0 },
5064   },
5065
5066   /* PREFIX_VEX_0F7D */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5071     { "vhsubps",        { XM, Vex, EXx }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0F7E */
5075   {
5076     { Bad_Opcode },
5077     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5078     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F7F */
5082   {
5083     { Bad_Opcode },
5084     { "vmovdqu",        { EXxS, XM }, 0 },
5085     { "vmovdqa",        { EXxS, XM }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0F90 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F91 */
5096   {
5097     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F92 */
5103   {
5104     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5107     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5108   },
5109
5110   /* PREFIX_VEX_0F93 */
5111   {
5112     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5115     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5116   },
5117
5118   /* PREFIX_VEX_0F98 */
5119   {
5120     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F99 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0FC2 */
5133   {
5134     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5135     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5136     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5137     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5138   },
5139
5140   /* PREFIX_VEX_0FC4 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0FC5 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0FD0 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5159     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5160   },
5161
5162   /* PREFIX_VEX_0FD1 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5167   },
5168
5169   /* PREFIX_VEX_0FD2 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FD3 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5181   },
5182
5183   /* PREFIX_VEX_0FD4 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpaddq",         { XM, Vex, EXx }, 0 },
5188   },
5189
5190   /* PREFIX_VEX_0FD5 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { "vpmullw",        { XM, Vex, EXx }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FD6 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FD7 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FD8 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FD9 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FDA */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpminub",        { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FDB */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpand",          { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FDC */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FDD */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FDE */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FDF */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpandn",         { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FE0 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpavgb",         { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FE1 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FE2 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FE3 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpavgw",         { XM, Vex, EXx }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FE4 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE5 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FE6 */
5310   {
5311     { Bad_Opcode },
5312     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5313     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5314     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FE7 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FE8 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FE9 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FEA */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpminsw",        { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FEB */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpor",           { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FEC */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FED */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FEE */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FEF */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpxor",          { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FF0 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5386   },
5387
5388   /* PREFIX_VEX_0FF1 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FF2 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FF3 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FF4 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF5 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5421   },
5422
5423   /* PREFIX_VEX_0FF6 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5428   },
5429
5430   /* PREFIX_VEX_0FF7 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0FF8 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { "vpsubb",         { XM, Vex, EXx }, 0 },
5442   },
5443
5444   /* PREFIX_VEX_0FF9 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpsubw",         { XM, Vex, EXx }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FFA */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpsubd",         { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FFB */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsubq",         { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FFC */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { "vpaddb",         { XM, Vex, EXx }, 0 },
5470   },
5471
5472   /* PREFIX_VEX_0FFD */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpaddw",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FFE */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpaddd",         { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0F3800 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vpshufb",        { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0F3801 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vphaddw",        { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0F3802 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vphaddd",        { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0F3803 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0F3804 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3805 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vphsubw",        { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3806 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vphsubd",        { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3807 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3808 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vpsignb",        { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3809 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vpsignw",        { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F380A */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vpsignd",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F380B */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F380C */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F380D */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F380E */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F380F */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3813 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5603   },
5604
5605   /* PREFIX_VEX_0F3816 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3817 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { "vptest",         { XM, EXx }, 0 },
5617   },
5618
5619   /* PREFIX_VEX_0F3818 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3819 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F381A */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F381C */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { "vpabsb",         { XM, EXx }, 0 },
5645   },
5646
5647   /* PREFIX_VEX_0F381D */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vpabsw",         { XM, EXx }, 0 },
5652   },
5653
5654   /* PREFIX_VEX_0F381E */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vpabsd",         { XM, EXx }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F3820 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5666   },
5667
5668   /* PREFIX_VEX_0F3821 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5673   },
5674
5675   /* PREFIX_VEX_0F3822 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F3823 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F3824 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3825 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3828 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F3829 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F382A */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F382B */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5729   },
5730
5731   /* PREFIX_VEX_0F382C */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F382D */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F382E */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F382F */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3830 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5764   },
5765
5766   /* PREFIX_VEX_0F3831 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5771   },
5772
5773   /* PREFIX_VEX_0F3832 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5778   },
5779
5780   /* PREFIX_VEX_0F3833 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5785   },
5786
5787   /* PREFIX_VEX_0F3834 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5792   },
5793
5794   /* PREFIX_VEX_0F3835 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3836 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F3837 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5813   },
5814
5815   /* PREFIX_VEX_0F3838 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpminsb",        { XM, Vex, EXx }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F3839 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpminsd",        { XM, Vex, EXx }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F383A */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpminuw",        { XM, Vex, EXx }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F383B */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpminud",        { XM, Vex, EXx }, 0 },
5841   },
5842
5843   /* PREFIX_VEX_0F383C */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F383D */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F383E */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F383F */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F3840 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpmulld",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F3841 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F3845 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5890   },
5891
5892   /* PREFIX_VEX_0F3846 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F3847 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5904   },
5905
5906   /* PREFIX_VEX_0F3858 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F3859 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F385A */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3878 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3879 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F388C */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F388E */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3890 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3891 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3892 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F3893 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F3896 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F3897 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F3898 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F3899 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F389A */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F389B */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F389C */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F389D */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F389E */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F389F */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F38A6 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6058     { Bad_Opcode },
6059   },
6060
6061   /* PREFIX_VEX_0F38A7 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F38A8 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38A9 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F38AA */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38AB */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38AC */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38AD */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38AE */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38AF */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38B6 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38B7 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38B8 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38B9 */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38BA */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38BB */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38BC */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38BD */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38BE */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38BF */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38CF */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F38DB */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F38DC */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vaesenc",        { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38DD */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38DE */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vaesdec",        { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38DF */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38F2 */
6237   {
6238     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6239   },
6240
6241   /* PREFIX_VEX_0F38F3_REG_1 */
6242   {
6243     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6244   },
6245
6246   /* PREFIX_VEX_0F38F3_REG_2 */
6247   {
6248     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6249   },
6250
6251   /* PREFIX_VEX_0F38F3_REG_3 */
6252   {
6253     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6254   },
6255
6256   /* PREFIX_VEX_0F38F5 */
6257   {
6258     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6259     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6260     { Bad_Opcode },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6262   },
6263
6264   /* PREFIX_VEX_0F38F6 */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6270   },
6271
6272   /* PREFIX_VEX_0F38F7 */
6273   {
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A00 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A01 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A02 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A04 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A05 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A06 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A08 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { "vroundps",       { XM, EXx, Ib }, 0 },
6327   },
6328
6329   /* PREFIX_VEX_0F3A09 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { "vroundpd",       { XM, EXx, Ib }, 0 },
6334   },
6335
6336   /* PREFIX_VEX_0F3A0A */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6341   },
6342
6343   /* PREFIX_VEX_0F3A0B */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6348   },
6349
6350   /* PREFIX_VEX_0F3A0C */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6355   },
6356
6357   /* PREFIX_VEX_0F3A0D */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6362   },
6363
6364   /* PREFIX_VEX_0F3A0E */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6369   },
6370
6371   /* PREFIX_VEX_0F3A0F */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6376   },
6377
6378   /* PREFIX_VEX_0F3A14 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A15 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A16 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A17 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A18 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A19 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A1D */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6425   },
6426
6427   /* PREFIX_VEX_0F3A20 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A21 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A22 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A30 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A31 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A32 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A33 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A38 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A39 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A40 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6495   },
6496
6497   /* PREFIX_VEX_0F3A41 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A42 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6509   },
6510
6511   /* PREFIX_VEX_0F3A44 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6516   },
6517
6518   /* PREFIX_VEX_0F3A46 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A48 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A49 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A4A */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A4B */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A4C */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A5C */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6565   },
6566
6567   /* PREFIX_VEX_0F3A5D */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6572   },
6573
6574   /* PREFIX_VEX_0F3A5E */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6579   },
6580
6581   /* PREFIX_VEX_0F3A5F */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6586   },
6587
6588   /* PREFIX_VEX_0F3A60 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6593     { Bad_Opcode },
6594   },
6595
6596   /* PREFIX_VEX_0F3A61 */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A62 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A63 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3A68 */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A69 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6629   },
6630
6631   /* PREFIX_VEX_0F3A6A */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A6B */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A6C */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6650   },
6651
6652   /* PREFIX_VEX_0F3A6D */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A6E */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A6F */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A78 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A79 */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A7A */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A7B */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A7C */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6706     { Bad_Opcode },
6707   },
6708
6709   /* PREFIX_VEX_0F3A7D */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6714   },
6715
6716   /* PREFIX_VEX_0F3A7E */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7F */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3ACE */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3ACF */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6742   },
6743
6744   /* PREFIX_VEX_0F3ADF */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6749   },
6750
6751   /* PREFIX_VEX_0F3AF0 */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6757   },
6758
6759 #include "i386-dis-evex-prefix.h"
6760 };
6761
6762 static const struct dis386 x86_64_table[][2] = {
6763   /* X86_64_06 */
6764   {
6765     { "pushP", { es }, 0 },
6766   },
6767
6768   /* X86_64_07 */
6769   {
6770     { "popP", { es }, 0 },
6771   },
6772
6773   /* X86_64_0E */
6774   {
6775     { "pushP", { cs }, 0 },
6776   },
6777
6778   /* X86_64_16 */
6779   {
6780     { "pushP", { ss }, 0 },
6781   },
6782
6783   /* X86_64_17 */
6784   {
6785     { "popP", { ss }, 0 },
6786   },
6787
6788   /* X86_64_1E */
6789   {
6790     { "pushP", { ds }, 0 },
6791   },
6792
6793   /* X86_64_1F */
6794   {
6795     { "popP", { ds }, 0 },
6796   },
6797
6798   /* X86_64_27 */
6799   {
6800     { "daa", { XX }, 0 },
6801   },
6802
6803   /* X86_64_2F */
6804   {
6805     { "das", { XX }, 0 },
6806   },
6807
6808   /* X86_64_37 */
6809   {
6810     { "aaa", { XX }, 0 },
6811   },
6812
6813   /* X86_64_3F */
6814   {
6815     { "aas", { XX }, 0 },
6816   },
6817
6818   /* X86_64_60 */
6819   {
6820     { "pushaP", { XX }, 0 },
6821   },
6822
6823   /* X86_64_61 */
6824   {
6825     { "popaP", { XX }, 0 },
6826   },
6827
6828   /* X86_64_62 */
6829   {
6830     { MOD_TABLE (MOD_62_32BIT) },
6831     { EVEX_TABLE (EVEX_0F) },
6832   },
6833
6834   /* X86_64_63 */
6835   {
6836     { "arpl", { Ew, Gw }, 0 },
6837     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6838   },
6839
6840   /* X86_64_6D */
6841   {
6842     { "ins{R|}", { Yzr, indirDX }, 0 },
6843     { "ins{G|}", { Yzr, indirDX }, 0 },
6844   },
6845
6846   /* X86_64_6F */
6847   {
6848     { "outs{R|}", { indirDXr, Xz }, 0 },
6849     { "outs{G|}", { indirDXr, Xz }, 0 },
6850   },
6851
6852   /* X86_64_82 */
6853   {
6854     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6855     { REG_TABLE (REG_80) },
6856   },
6857
6858   /* X86_64_9A */
6859   {
6860     { "{l|}call{T|}", { Ap }, 0 },
6861   },
6862
6863   /* X86_64_C2 */
6864   {
6865     { "retP",           { Iw, BND }, 0 },
6866     { "ret@",           { Iw, BND }, 0 },
6867   },
6868
6869   /* X86_64_C3 */
6870   {
6871     { "retP",           { BND }, 0 },
6872     { "ret@",           { BND }, 0 },
6873   },
6874
6875   /* X86_64_C4 */
6876   {
6877     { MOD_TABLE (MOD_C4_32BIT) },
6878     { VEX_C4_TABLE (VEX_0F) },
6879   },
6880
6881   /* X86_64_C5 */
6882   {
6883     { MOD_TABLE (MOD_C5_32BIT) },
6884     { VEX_C5_TABLE (VEX_0F) },
6885   },
6886
6887   /* X86_64_CE */
6888   {
6889     { "into", { XX }, 0 },
6890   },
6891
6892   /* X86_64_D4 */
6893   {
6894     { "aam", { Ib }, 0 },
6895   },
6896
6897   /* X86_64_D5 */
6898   {
6899     { "aad", { Ib }, 0 },
6900   },
6901
6902   /* X86_64_E8 */
6903   {
6904     { "callP",          { Jv, BND }, 0 },
6905     { "call@",          { Jv, BND }, 0 }
6906   },
6907
6908   /* X86_64_E9 */
6909   {
6910     { "jmpP",           { Jv, BND }, 0 },
6911     { "jmp@",           { Jv, BND }, 0 }
6912   },
6913
6914   /* X86_64_EA */
6915   {
6916     { "{l|}jmp{T|}", { Ap }, 0 },
6917   },
6918
6919   /* X86_64_0F01_REG_0 */
6920   {
6921     { "sgdt{Q|IQ}", { M }, 0 },
6922     { "sgdt", { M }, 0 },
6923   },
6924
6925   /* X86_64_0F01_REG_1 */
6926   {
6927     { "sidt{Q|IQ}", { M }, 0 },
6928     { "sidt", { M }, 0 },
6929   },
6930
6931   /* X86_64_0F01_REG_2 */
6932   {
6933     { "lgdt{Q|Q}", { M }, 0 },
6934     { "lgdt", { M }, 0 },
6935   },
6936
6937   /* X86_64_0F01_REG_3 */
6938   {
6939     { "lidt{Q|Q}", { M }, 0 },
6940     { "lidt", { M }, 0 },
6941   },
6942 };
6943
6944 static const struct dis386 three_byte_table[][256] = {
6945
6946   /* THREE_BYTE_0F38 */
6947   {
6948     /* 00 */
6949     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6950     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6951     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6952     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6953     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6954     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6955     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6956     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6957     /* 08 */
6958     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6959     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6960     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6961     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     /* 10 */
6967     { PREFIX_TABLE (PREFIX_0F3810) },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { PREFIX_TABLE (PREFIX_0F3814) },
6972     { PREFIX_TABLE (PREFIX_0F3815) },
6973     { Bad_Opcode },
6974     { PREFIX_TABLE (PREFIX_0F3817) },
6975     /* 18 */
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6981     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6982     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6983     { Bad_Opcode },
6984     /* 20 */
6985     { PREFIX_TABLE (PREFIX_0F3820) },
6986     { PREFIX_TABLE (PREFIX_0F3821) },
6987     { PREFIX_TABLE (PREFIX_0F3822) },
6988     { PREFIX_TABLE (PREFIX_0F3823) },
6989     { PREFIX_TABLE (PREFIX_0F3824) },
6990     { PREFIX_TABLE (PREFIX_0F3825) },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 28 */
6994     { PREFIX_TABLE (PREFIX_0F3828) },
6995     { PREFIX_TABLE (PREFIX_0F3829) },
6996     { PREFIX_TABLE (PREFIX_0F382A) },
6997     { PREFIX_TABLE (PREFIX_0F382B) },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     /* 30 */
7003     { PREFIX_TABLE (PREFIX_0F3830) },
7004     { PREFIX_TABLE (PREFIX_0F3831) },
7005     { PREFIX_TABLE (PREFIX_0F3832) },
7006     { PREFIX_TABLE (PREFIX_0F3833) },
7007     { PREFIX_TABLE (PREFIX_0F3834) },
7008     { PREFIX_TABLE (PREFIX_0F3835) },
7009     { Bad_Opcode },
7010     { PREFIX_TABLE (PREFIX_0F3837) },
7011     /* 38 */
7012     { PREFIX_TABLE (PREFIX_0F3838) },
7013     { PREFIX_TABLE (PREFIX_0F3839) },
7014     { PREFIX_TABLE (PREFIX_0F383A) },
7015     { PREFIX_TABLE (PREFIX_0F383B) },
7016     { PREFIX_TABLE (PREFIX_0F383C) },
7017     { PREFIX_TABLE (PREFIX_0F383D) },
7018     { PREFIX_TABLE (PREFIX_0F383E) },
7019     { PREFIX_TABLE (PREFIX_0F383F) },
7020     /* 40 */
7021     { PREFIX_TABLE (PREFIX_0F3840) },
7022     { PREFIX_TABLE (PREFIX_0F3841) },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 48 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 50 */
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 58 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 60 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 68 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 70 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 78 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 80 */
7093     { PREFIX_TABLE (PREFIX_0F3880) },
7094     { PREFIX_TABLE (PREFIX_0F3881) },
7095     { PREFIX_TABLE (PREFIX_0F3882) },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 88 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 90 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 98 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* a0 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* a8 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* b0 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* b8 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* c0 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* c8 */
7174     { PREFIX_TABLE (PREFIX_0F38C8) },
7175     { PREFIX_TABLE (PREFIX_0F38C9) },
7176     { PREFIX_TABLE (PREFIX_0F38CA) },
7177     { PREFIX_TABLE (PREFIX_0F38CB) },
7178     { PREFIX_TABLE (PREFIX_0F38CC) },
7179     { PREFIX_TABLE (PREFIX_0F38CD) },
7180     { Bad_Opcode },
7181     { PREFIX_TABLE (PREFIX_0F38CF) },
7182     /* d0 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* d8 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { PREFIX_TABLE (PREFIX_0F38DB) },
7196     { PREFIX_TABLE (PREFIX_0F38DC) },
7197     { PREFIX_TABLE (PREFIX_0F38DD) },
7198     { PREFIX_TABLE (PREFIX_0F38DE) },
7199     { PREFIX_TABLE (PREFIX_0F38DF) },
7200     /* e0 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* e8 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* f0 */
7219     { PREFIX_TABLE (PREFIX_0F38F0) },
7220     { PREFIX_TABLE (PREFIX_0F38F1) },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { PREFIX_TABLE (PREFIX_0F38F5) },
7225     { PREFIX_TABLE (PREFIX_0F38F6) },
7226     { Bad_Opcode },
7227     /* f8 */
7228     { PREFIX_TABLE (PREFIX_0F38F8) },
7229     { PREFIX_TABLE (PREFIX_0F38F9) },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236   },
7237   /* THREE_BYTE_0F3A */
7238   {
7239     /* 00 */
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     /* 08 */
7249     { PREFIX_TABLE (PREFIX_0F3A08) },
7250     { PREFIX_TABLE (PREFIX_0F3A09) },
7251     { PREFIX_TABLE (PREFIX_0F3A0A) },
7252     { PREFIX_TABLE (PREFIX_0F3A0B) },
7253     { PREFIX_TABLE (PREFIX_0F3A0C) },
7254     { PREFIX_TABLE (PREFIX_0F3A0D) },
7255     { PREFIX_TABLE (PREFIX_0F3A0E) },
7256     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7257     /* 10 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { PREFIX_TABLE (PREFIX_0F3A14) },
7263     { PREFIX_TABLE (PREFIX_0F3A15) },
7264     { PREFIX_TABLE (PREFIX_0F3A16) },
7265     { PREFIX_TABLE (PREFIX_0F3A17) },
7266     /* 18 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 20 */
7276     { PREFIX_TABLE (PREFIX_0F3A20) },
7277     { PREFIX_TABLE (PREFIX_0F3A21) },
7278     { PREFIX_TABLE (PREFIX_0F3A22) },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 28 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 30 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 38 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 40 */
7312     { PREFIX_TABLE (PREFIX_0F3A40) },
7313     { PREFIX_TABLE (PREFIX_0F3A41) },
7314     { PREFIX_TABLE (PREFIX_0F3A42) },
7315     { Bad_Opcode },
7316     { PREFIX_TABLE (PREFIX_0F3A44) },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 48 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 50 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 58 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 60 */
7348     { PREFIX_TABLE (PREFIX_0F3A60) },
7349     { PREFIX_TABLE (PREFIX_0F3A61) },
7350     { PREFIX_TABLE (PREFIX_0F3A62) },
7351     { PREFIX_TABLE (PREFIX_0F3A63) },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 68 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 70 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 78 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 80 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 88 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 90 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 98 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* a0 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* a8 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* b0 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* b8 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* c0 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* c8 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { PREFIX_TABLE (PREFIX_0F3ACC) },
7470     { Bad_Opcode },
7471     { PREFIX_TABLE (PREFIX_0F3ACE) },
7472     { PREFIX_TABLE (PREFIX_0F3ACF) },
7473     /* d0 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* d8 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { PREFIX_TABLE (PREFIX_0F3ADF) },
7491     /* e0 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* e8 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* f0 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* f8 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527   },
7528 };
7529
7530 static const struct dis386 xop_table[][256] = {
7531   /* XOP_08 */
7532   {
7533     /* 00 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 08 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* 10 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 18 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 20 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 28 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 30 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 38 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 40 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 48 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 50 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 58 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 60 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 68 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 70 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 78 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 80 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7684     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7685     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686     /* 88 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7694     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     /* 90 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7702     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7703     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     /* 98 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     /* a0 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721     { Bad_Opcode },
7722     /* a8 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* b0 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { Bad_Opcode },
7740     /* b8 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* c0 */
7750     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7751     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7752     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7753     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* c8 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7764     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7765     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7766     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7767     /* d0 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* d8 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* e0 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* e8 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7800     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7801     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7802     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7803     /* f0 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* f8 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821   },
7822   /* XOP_09 */
7823   {
7824     /* 00 */
7825     { Bad_Opcode },
7826     { REG_TABLE (REG_XOP_TBM_01) },
7827     { REG_TABLE (REG_XOP_TBM_02) },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     /* 08 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* 10 */
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { REG_TABLE (REG_XOP_LWPCB) },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* 18 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 20 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 28 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 30 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 38 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 40 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 48 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 50 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 58 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 60 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 68 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 70 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 78 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 80 */
7969     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7970     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7971     { "vfrczss",        { XM, EXd }, 0 },
7972     { "vfrczsd",        { XM, EXq }, 0 },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 88 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 90 */
7987     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     /* 98 */
7996     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7997     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7998     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* a0 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* a8 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* b0 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* b8 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* c0 */
8041     { Bad_Opcode },
8042     { "vphaddbw",       { XM, EXxmm }, 0 },
8043     { "vphaddbd",       { XM, EXxmm }, 0 },
8044     { "vphaddbq",       { XM, EXxmm }, 0 },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { "vphaddwd",       { XM, EXxmm }, 0 },
8048     { "vphaddwq",       { XM, EXxmm }, 0 },
8049     /* c8 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { "vphadddq",       { XM, EXxmm }, 0 },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* d0 */
8059     { Bad_Opcode },
8060     { "vphaddubw",      { XM, EXxmm }, 0 },
8061     { "vphaddubd",      { XM, EXxmm }, 0 },
8062     { "vphaddubq",      { XM, EXxmm }, 0 },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { "vphadduwd",      { XM, EXxmm }, 0 },
8066     { "vphadduwq",      { XM, EXxmm }, 0 },
8067     /* d8 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { "vphaddudq",      { XM, EXxmm }, 0 },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* e0 */
8077     { Bad_Opcode },
8078     { "vphsubbw",       { XM, EXxmm }, 0 },
8079     { "vphsubwd",       { XM, EXxmm }, 0 },
8080     { "vphsubdq",       { XM, EXxmm }, 0 },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* e8 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* f0 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* f8 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112   },
8113   /* XOP_0A */
8114   {
8115     /* 00 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* 08 */
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* 10 */
8134     { "bextrS", { Gdq, Edq, Id }, 0 },
8135     { Bad_Opcode },
8136     { REG_TABLE (REG_XOP_LWP) },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     /* 18 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 20 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 28 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 30 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 38 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 40 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 48 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 50 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 58 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 60 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 68 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 70 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 78 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 80 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 88 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 90 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 98 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* a0 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* a8 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* b0 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* b8 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* c0 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* c8 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* d0 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* d8 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* e0 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* e8 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* f0 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* f8 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403   },
8404 };
8405
8406 static const struct dis386 vex_table[][256] = {
8407   /* VEX_0F */
8408   {
8409     /* 00 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* 08 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* 10 */
8428     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8431     { MOD_TABLE (MOD_VEX_0F13) },
8432     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8433     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8434     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8435     { MOD_TABLE (MOD_VEX_0F17) },
8436     /* 18 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 20 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 28 */
8455     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8456     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8457     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8458     { MOD_TABLE (MOD_VEX_0F2B) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8463     /* 30 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 38 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 40 */
8482     { Bad_Opcode },
8483     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8485     { Bad_Opcode },
8486     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8490     /* 48 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 50 */
8500     { MOD_TABLE (MOD_VEX_0F50) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8504     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8505     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8506     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8507     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8508     /* 58 */
8509     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8517     /* 60 */
8518     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8526     /* 68 */
8527     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8535     /* 70 */
8536     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8537     { REG_TABLE (REG_VEX_0F71) },
8538     { REG_TABLE (REG_VEX_0F72) },
8539     { REG_TABLE (REG_VEX_0F73) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8544     /* 78 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8553     /* 80 */
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     /* 88 */
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     /* 90 */
8572     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     /* 98 */
8581     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* a0 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* a8 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { REG_TABLE (REG_VEX_0FAE) },
8606     { Bad_Opcode },
8607     /* b0 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* b8 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* c0 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8629     { Bad_Opcode },
8630     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8631     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8632     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8633     { Bad_Opcode },
8634     /* c8 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* d0 */
8644     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8652     /* d8 */
8653     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8661     /* e0 */
8662     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8670     /* e8 */
8671     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8679     /* f0 */
8680     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8688     /* f8 */
8689     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8696     { Bad_Opcode },
8697   },
8698   /* VEX_0F38 */
8699   {
8700     /* 00 */
8701     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8709     /* 08 */
8710     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8718     /* 10 */
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8727     /* 18 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8731     { Bad_Opcode },
8732     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8735     { Bad_Opcode },
8736     /* 20 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     /* 28 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8754     /* 30 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8763     /* 38 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8772     /* 40 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8781     /* 48 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 50 */
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 58 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     /* 60 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 68 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 70 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 78 */
8836     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 80 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 88 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8859     { Bad_Opcode },
8860     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8861     { Bad_Opcode },
8862     /* 90 */
8863     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8871     /* 98 */
8872     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8880     /* a0 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8889     /* a8 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8898     /* b0 */
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8907     /* b8 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8916     /* c0 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     /* c8 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8934     /* d0 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* d8 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8952     /* e0 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* e8 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* f0 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8974     { REG_TABLE (REG_VEX_0F38F3) },
8975     { Bad_Opcode },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8979     /* f8 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988   },
8989   /* VEX_0F3A */
8990   {
8991     /* 00 */
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8995     { Bad_Opcode },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8999     { Bad_Opcode },
9000     /* 08 */
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9009     /* 10 */
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9018     /* 18 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* 20 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     /* 28 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     /* 30 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 38 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 40 */
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9067     { Bad_Opcode },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9069     { Bad_Opcode },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9071     { Bad_Opcode },
9072     /* 48 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 50 */
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 58 */
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9099     /* 60 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 68 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9117     /* 70 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     /* 78 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9135     /* 80 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* 88 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 90 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* 98 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* a0 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* a8 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* b0 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* b8 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* c0 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* c8 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9224     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9225     /* d0 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* d8 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9243     /* e0 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* e8 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* f0 */
9262     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     /* f8 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279   },
9280 };
9281
9282 #include "i386-dis-evex.h"
9283
9284 static const struct dis386 vex_len_table[][2] = {
9285   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9286   {
9287     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9288   },
9289
9290   /* VEX_LEN_0F12_P_0_M_1 */
9291   {
9292     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9293   },
9294
9295   /* VEX_LEN_0F13_M_0 */
9296   {
9297     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9298   },
9299
9300   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9301   {
9302     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9303   },
9304
9305   /* VEX_LEN_0F16_P_0_M_1 */
9306   {
9307     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9308   },
9309
9310   /* VEX_LEN_0F17_M_0 */
9311   {
9312     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9313   },
9314
9315   /* VEX_LEN_0F41_P_0 */
9316   {
9317     { Bad_Opcode },
9318     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9319   },
9320   /* VEX_LEN_0F41_P_2 */
9321   {
9322     { Bad_Opcode },
9323     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9324   },
9325   /* VEX_LEN_0F42_P_0 */
9326   {
9327     { Bad_Opcode },
9328     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9329   },
9330   /* VEX_LEN_0F42_P_2 */
9331   {
9332     { Bad_Opcode },
9333     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9334   },
9335   /* VEX_LEN_0F44_P_0 */
9336   {
9337     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9338   },
9339   /* VEX_LEN_0F44_P_2 */
9340   {
9341     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9342   },
9343   /* VEX_LEN_0F45_P_0 */
9344   {
9345     { Bad_Opcode },
9346     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9347   },
9348   /* VEX_LEN_0F45_P_2 */
9349   {
9350     { Bad_Opcode },
9351     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9352   },
9353   /* VEX_LEN_0F46_P_0 */
9354   {
9355     { Bad_Opcode },
9356     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9357   },
9358   /* VEX_LEN_0F46_P_2 */
9359   {
9360     { Bad_Opcode },
9361     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9362   },
9363   /* VEX_LEN_0F47_P_0 */
9364   {
9365     { Bad_Opcode },
9366     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9367   },
9368   /* VEX_LEN_0F47_P_2 */
9369   {
9370     { Bad_Opcode },
9371     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9372   },
9373   /* VEX_LEN_0F4A_P_0 */
9374   {
9375     { Bad_Opcode },
9376     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9377   },
9378   /* VEX_LEN_0F4A_P_2 */
9379   {
9380     { Bad_Opcode },
9381     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9382   },
9383   /* VEX_LEN_0F4B_P_0 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9387   },
9388   /* VEX_LEN_0F4B_P_2 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9392   },
9393
9394   /* VEX_LEN_0F6E_P_2 */
9395   {
9396     { "vmovK",          { XMScalar, Edq }, 0 },
9397   },
9398
9399   /* VEX_LEN_0F77_P_1 */
9400   {
9401     { "vzeroupper",     { XX }, 0 },
9402     { "vzeroall",       { XX }, 0 },
9403   },
9404
9405   /* VEX_LEN_0F7E_P_1 */
9406   {
9407     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9408   },
9409
9410   /* VEX_LEN_0F7E_P_2 */
9411   {
9412     { "vmovK",          { Edq, XMScalar }, 0 },
9413   },
9414
9415   /* VEX_LEN_0F90_P_0 */
9416   {
9417     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9418   },
9419
9420   /* VEX_LEN_0F90_P_2 */
9421   {
9422     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9423   },
9424
9425   /* VEX_LEN_0F91_P_0 */
9426   {
9427     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9428   },
9429
9430   /* VEX_LEN_0F91_P_2 */
9431   {
9432     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9433   },
9434
9435   /* VEX_LEN_0F92_P_0 */
9436   {
9437     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9438   },
9439
9440   /* VEX_LEN_0F92_P_2 */
9441   {
9442     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9443   },
9444
9445   /* VEX_LEN_0F92_P_3 */
9446   {
9447     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9448   },
9449
9450   /* VEX_LEN_0F93_P_0 */
9451   {
9452     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9453   },
9454
9455   /* VEX_LEN_0F93_P_2 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9458   },
9459
9460   /* VEX_LEN_0F93_P_3 */
9461   {
9462     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9463   },
9464
9465   /* VEX_LEN_0F98_P_0 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9468   },
9469
9470   /* VEX_LEN_0F98_P_2 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F99_P_0 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F99_P_2 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0FAE_R_2_M_0 */
9486   {
9487     { "vldmxcsr",       { Md }, 0 },
9488   },
9489
9490   /* VEX_LEN_0FAE_R_3_M_0 */
9491   {
9492     { "vstmxcsr",       { Md }, 0 },
9493   },
9494
9495   /* VEX_LEN_0FC4_P_2 */
9496   {
9497     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9498   },
9499
9500   /* VEX_LEN_0FC5_P_2 */
9501   {
9502     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9503   },
9504
9505   /* VEX_LEN_0FD6_P_2 */
9506   {
9507     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9508   },
9509
9510   /* VEX_LEN_0FF7_P_2 */
9511   {
9512     { "vmaskmovdqu",    { XM, XS }, 0 },
9513   },
9514
9515   /* VEX_LEN_0F3816_P_2 */
9516   {
9517     { Bad_Opcode },
9518     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9519   },
9520
9521   /* VEX_LEN_0F3819_P_2 */
9522   {
9523     { Bad_Opcode },
9524     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9525   },
9526
9527   /* VEX_LEN_0F381A_P_2_M_0 */
9528   {
9529     { Bad_Opcode },
9530     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9531   },
9532
9533   /* VEX_LEN_0F3836_P_2 */
9534   {
9535     { Bad_Opcode },
9536     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9537   },
9538
9539   /* VEX_LEN_0F3841_P_2 */
9540   {
9541     { "vphminposuw",    { XM, EXx }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F385A_P_2_M_0 */
9545   {
9546     { Bad_Opcode },
9547     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9548   },
9549
9550   /* VEX_LEN_0F38DB_P_2 */
9551   {
9552     { "vaesimc",        { XM, EXx }, 0 },
9553   },
9554
9555   /* VEX_LEN_0F38F2_P_0 */
9556   {
9557     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9558   },
9559
9560   /* VEX_LEN_0F38F3_R_1_P_0 */
9561   {
9562     { "blsrS",          { VexGdq, Edq }, 0 },
9563   },
9564
9565   /* VEX_LEN_0F38F3_R_2_P_0 */
9566   {
9567     { "blsmskS",        { VexGdq, Edq }, 0 },
9568   },
9569
9570   /* VEX_LEN_0F38F3_R_3_P_0 */
9571   {
9572     { "blsiS",          { VexGdq, Edq }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F38F5_P_0 */
9576   {
9577     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9578   },
9579
9580   /* VEX_LEN_0F38F5_P_1 */
9581   {
9582     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9583   },
9584
9585   /* VEX_LEN_0F38F5_P_3 */
9586   {
9587     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F38F6_P_3 */
9591   {
9592     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F38F7_P_0 */
9596   {
9597     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F38F7_P_1 */
9601   {
9602     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F38F7_P_2 */
9606   {
9607     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F7_P_3 */
9611   {
9612     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F3A00_P_2 */
9616   {
9617     { Bad_Opcode },
9618     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9619   },
9620
9621   /* VEX_LEN_0F3A01_P_2 */
9622   {
9623     { Bad_Opcode },
9624     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9625   },
9626
9627   /* VEX_LEN_0F3A06_P_2 */
9628   {
9629     { Bad_Opcode },
9630     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9631   },
9632
9633   /* VEX_LEN_0F3A14_P_2 */
9634   {
9635     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F3A15_P_2 */
9639   {
9640     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F3A16_P_2  */
9644   {
9645     { "vpextrK",        { Edq, XM, Ib }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F3A17_P_2 */
9649   {
9650     { "vextractps",     { Edqd, XM, Ib }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F3A18_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9657   },
9658
9659   /* VEX_LEN_0F3A19_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9663   },
9664
9665   /* VEX_LEN_0F3A20_P_2 */
9666   {
9667     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F3A21_P_2 */
9671   {
9672     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F3A22_P_2 */
9676   {
9677     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F3A30_P_2 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9683   },
9684
9685   /* VEX_LEN_0F3A31_P_2 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9688   },
9689
9690   /* VEX_LEN_0F3A32_P_2 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9693   },
9694
9695   /* VEX_LEN_0F3A33_P_2 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9698   },
9699
9700   /* VEX_LEN_0F3A38_P_2 */
9701   {
9702     { Bad_Opcode },
9703     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9704   },
9705
9706   /* VEX_LEN_0F3A39_P_2 */
9707   {
9708     { Bad_Opcode },
9709     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9710   },
9711
9712   /* VEX_LEN_0F3A41_P_2 */
9713   {
9714     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9715   },
9716
9717   /* VEX_LEN_0F3A46_P_2 */
9718   {
9719     { Bad_Opcode },
9720     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9721   },
9722
9723   /* VEX_LEN_0F3A60_P_2 */
9724   {
9725     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9726   },
9727
9728   /* VEX_LEN_0F3A61_P_2 */
9729   {
9730     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9731   },
9732
9733   /* VEX_LEN_0F3A62_P_2 */
9734   {
9735     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9736   },
9737
9738   /* VEX_LEN_0F3A63_P_2 */
9739   {
9740     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9741   },
9742
9743   /* VEX_LEN_0F3A6A_P_2 */
9744   {
9745     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9746   },
9747
9748   /* VEX_LEN_0F3A6B_P_2 */
9749   {
9750     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9751   },
9752
9753   /* VEX_LEN_0F3A6E_P_2 */
9754   {
9755     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9756   },
9757
9758   /* VEX_LEN_0F3A6F_P_2 */
9759   {
9760     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9761   },
9762
9763   /* VEX_LEN_0F3A7A_P_2 */
9764   {
9765     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9766   },
9767
9768   /* VEX_LEN_0F3A7B_P_2 */
9769   {
9770     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9771   },
9772
9773   /* VEX_LEN_0F3A7E_P_2 */
9774   {
9775     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F3A7F_P_2 */
9779   {
9780     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3ADF_P_2 */
9784   {
9785     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3AF0_P_3 */
9789   {
9790     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9791   },
9792
9793   /* VEX_LEN_0FXOP_08_CC */
9794   {
9795      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9796   },
9797
9798   /* VEX_LEN_0FXOP_08_CD */
9799   {
9800      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9801   },
9802
9803   /* VEX_LEN_0FXOP_08_CE */
9804   {
9805      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9806   },
9807
9808   /* VEX_LEN_0FXOP_08_CF */
9809   {
9810      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9811   },
9812
9813   /* VEX_LEN_0FXOP_08_EC */
9814   {
9815      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9816   },
9817
9818   /* VEX_LEN_0FXOP_08_ED */
9819   {
9820      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9821   },
9822
9823   /* VEX_LEN_0FXOP_08_EE */
9824   {
9825      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9826   },
9827
9828   /* VEX_LEN_0FXOP_08_EF */
9829   {
9830      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9831   },
9832
9833   /* VEX_LEN_0FXOP_09_80 */
9834   {
9835     { "vfrczps",        { XM, EXxmm }, 0 },
9836     { "vfrczps",        { XM, EXymmq }, 0 },
9837   },
9838
9839   /* VEX_LEN_0FXOP_09_81 */
9840   {
9841     { "vfrczpd",        { XM, EXxmm }, 0 },
9842     { "vfrczpd",        { XM, EXymmq }, 0 },
9843   },
9844 };
9845
9846 #include "i386-dis-evex-len.h"
9847
9848 static const struct dis386 vex_w_table[][2] = {
9849   {
9850     /* VEX_W_0F41_P_0_LEN_1 */
9851     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9852     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9853   },
9854   {
9855     /* VEX_W_0F41_P_2_LEN_1 */
9856     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9857     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9858   },
9859   {
9860     /* VEX_W_0F42_P_0_LEN_1 */
9861     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9862     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9863   },
9864   {
9865     /* VEX_W_0F42_P_2_LEN_1 */
9866     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9867     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9868   },
9869   {
9870     /* VEX_W_0F44_P_0_LEN_0 */
9871     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9872     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9873   },
9874   {
9875     /* VEX_W_0F44_P_2_LEN_0 */
9876     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9877     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9878   },
9879   {
9880     /* VEX_W_0F45_P_0_LEN_1 */
9881     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9882     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9883   },
9884   {
9885     /* VEX_W_0F45_P_2_LEN_1 */
9886     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9887     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9888   },
9889   {
9890     /* VEX_W_0F46_P_0_LEN_1 */
9891     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9892     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9893   },
9894   {
9895     /* VEX_W_0F46_P_2_LEN_1 */
9896     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9897     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9898   },
9899   {
9900     /* VEX_W_0F47_P_0_LEN_1 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F47_P_2_LEN_1 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F4A_P_0_LEN_1 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F4A_P_2_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F4B_P_0_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F4B_P_2_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9927   },
9928   {
9929     /* VEX_W_0F90_P_0_LEN_0 */
9930     { "kmovw",          { MaskG, MaskE }, 0 },
9931     { "kmovq",          { MaskG, MaskE }, 0 },
9932   },
9933   {
9934     /* VEX_W_0F90_P_2_LEN_0 */
9935     { "kmovb",          { MaskG, MaskBDE }, 0 },
9936     { "kmovd",          { MaskG, MaskBDE }, 0 },
9937   },
9938   {
9939     /* VEX_W_0F91_P_0_LEN_0 */
9940     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9941     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9942   },
9943   {
9944     /* VEX_W_0F91_P_2_LEN_0 */
9945     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9946     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9947   },
9948   {
9949     /* VEX_W_0F92_P_0_LEN_0 */
9950     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9951   },
9952   {
9953     /* VEX_W_0F92_P_2_LEN_0 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9955   },
9956   {
9957     /* VEX_W_0F93_P_0_LEN_0 */
9958     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9959   },
9960   {
9961     /* VEX_W_0F93_P_2_LEN_0 */
9962     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9963   },
9964   {
9965     /* VEX_W_0F98_P_0_LEN_0 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9968   },
9969   {
9970     /* VEX_W_0F98_P_2_LEN_0 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9972     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9973   },
9974   {
9975     /* VEX_W_0F99_P_0_LEN_0 */
9976     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9977     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9978   },
9979   {
9980     /* VEX_W_0F99_P_2_LEN_0 */
9981     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9982     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9983   },
9984   {
9985     /* VEX_W_0F380C_P_2  */
9986     { "vpermilps",      { XM, Vex, EXx }, 0 },
9987   },
9988   {
9989     /* VEX_W_0F380D_P_2  */
9990     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9991   },
9992   {
9993     /* VEX_W_0F380E_P_2  */
9994     { "vtestps",        { XM, EXx }, 0 },
9995   },
9996   {
9997     /* VEX_W_0F380F_P_2  */
9998     { "vtestpd",        { XM, EXx }, 0 },
9999   },
10000   {
10001     /* VEX_W_0F3816_P_2  */
10002     { "vpermps",        { XM, Vex, EXx }, 0 },
10003   },
10004   {
10005     /* VEX_W_0F3818_P_2 */
10006     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10007   },
10008   {
10009     /* VEX_W_0F3819_P_2 */
10010     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10011   },
10012   {
10013     /* VEX_W_0F381A_P_2_M_0 */
10014     { "vbroadcastf128", { XM, Mxmm }, 0 },
10015   },
10016   {
10017     /* VEX_W_0F382C_P_2_M_0 */
10018     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10019   },
10020   {
10021     /* VEX_W_0F382D_P_2_M_0 */
10022     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10023   },
10024   {
10025     /* VEX_W_0F382E_P_2_M_0 */
10026     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10027   },
10028   {
10029     /* VEX_W_0F382F_P_2_M_0 */
10030     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10031   },
10032   {
10033     /* VEX_W_0F3836_P_2  */
10034     { "vpermd",         { XM, Vex, EXx }, 0 },
10035   },
10036   {
10037     /* VEX_W_0F3846_P_2 */
10038     { "vpsravd",        { XM, Vex, EXx }, 0 },
10039   },
10040   {
10041     /* VEX_W_0F3858_P_2 */
10042     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F3859_P_2 */
10046     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F385A_P_2_M_0 */
10050     { "vbroadcasti128", { XM, Mxmm }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F3878_P_2 */
10054     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3879_P_2 */
10058     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F38CF_P_2 */
10062     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F3A00_P_2 */
10066     { Bad_Opcode },
10067     { "vpermq",         { XM, EXx, Ib }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F3A01_P_2 */
10071     { Bad_Opcode },
10072     { "vpermpd",        { XM, EXx, Ib }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3A02_P_2 */
10076     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3A04_P_2 */
10080     { "vpermilps",      { XM, EXx, Ib }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3A05_P_2 */
10084     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3A06_P_2 */
10088     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F3A18_P_2 */
10092     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F3A19_P_2 */
10096     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F3A30_P_2_LEN_0 */
10100     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10101     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10102   },
10103   {
10104     /* VEX_W_0F3A31_P_2_LEN_0 */
10105     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10106     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10107   },
10108   {
10109     /* VEX_W_0F3A32_P_2_LEN_0 */
10110     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10111     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10112   },
10113   {
10114     /* VEX_W_0F3A33_P_2_LEN_0 */
10115     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10116     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10117   },
10118   {
10119     /* VEX_W_0F3A38_P_2 */
10120     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3A39_P_2 */
10124     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F3A46_P_2 */
10128     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A48_P_2 */
10132     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10133     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F3A49_P_2 */
10137     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10138     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A4A_P_2 */
10142     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10143   },
10144   {
10145     /* VEX_W_0F3A4B_P_2 */
10146     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10147   },
10148   {
10149     /* VEX_W_0F3A4C_P_2 */
10150     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F3ACE_P_2 */
10154     { Bad_Opcode },
10155     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F3ACF_P_2 */
10159     { Bad_Opcode },
10160     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10161   },
10162
10163 #include "i386-dis-evex-w.h"
10164 };
10165
10166 static const struct dis386 mod_table[][2] = {
10167   {
10168     /* MOD_8D */
10169     { "leaS",           { Gv, M }, 0 },
10170   },
10171   {
10172     /* MOD_C6_REG_7 */
10173     { Bad_Opcode },
10174     { RM_TABLE (RM_C6_REG_7) },
10175   },
10176   {
10177     /* MOD_C7_REG_7 */
10178     { Bad_Opcode },
10179     { RM_TABLE (RM_C7_REG_7) },
10180   },
10181   {
10182     /* MOD_FF_REG_3 */
10183     { "{l|}call^", { indirEp }, 0 },
10184   },
10185   {
10186     /* MOD_FF_REG_5 */
10187     { "{l|}jmp^", { indirEp }, 0 },
10188   },
10189   {
10190     /* MOD_0F01_REG_0 */
10191     { X86_64_TABLE (X86_64_0F01_REG_0) },
10192     { RM_TABLE (RM_0F01_REG_0) },
10193   },
10194   {
10195     /* MOD_0F01_REG_1 */
10196     { X86_64_TABLE (X86_64_0F01_REG_1) },
10197     { RM_TABLE (RM_0F01_REG_1) },
10198   },
10199   {
10200     /* MOD_0F01_REG_2 */
10201     { X86_64_TABLE (X86_64_0F01_REG_2) },
10202     { RM_TABLE (RM_0F01_REG_2) },
10203   },
10204   {
10205     /* MOD_0F01_REG_3 */
10206     { X86_64_TABLE (X86_64_0F01_REG_3) },
10207     { RM_TABLE (RM_0F01_REG_3) },
10208   },
10209   {
10210     /* MOD_0F01_REG_5 */
10211     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10212     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10213   },
10214   {
10215     /* MOD_0F01_REG_7 */
10216     { "invlpg",         { Mb }, 0 },
10217     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10218   },
10219   {
10220     /* MOD_0F12_PREFIX_0 */
10221     { "movlpX",         { XM, EXq }, 0 },
10222     { "movhlps",        { XM, EXq }, 0 },
10223   },
10224   {
10225     /* MOD_0F12_PREFIX_2 */
10226     { "movlpX", { XM, EXq }, 0 },
10227   },
10228   {
10229     /* MOD_0F13 */
10230     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10231   },
10232   {
10233     /* MOD_0F16_PREFIX_0 */
10234     { "movhpX",         { XM, EXq }, 0 },
10235     { "movlhps",        { XM, EXq }, 0 },
10236   },
10237   {
10238     /* MOD_0F16_PREFIX_2 */
10239     { "movhpX", { XM, EXq }, 0 },
10240   },
10241   {
10242     /* MOD_0F17 */
10243     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10244   },
10245   {
10246     /* MOD_0F18_REG_0 */
10247     { "prefetchnta",    { Mb }, 0 },
10248   },
10249   {
10250     /* MOD_0F18_REG_1 */
10251     { "prefetcht0",     { Mb }, 0 },
10252   },
10253   {
10254     /* MOD_0F18_REG_2 */
10255     { "prefetcht1",     { Mb }, 0 },
10256   },
10257   {
10258     /* MOD_0F18_REG_3 */
10259     { "prefetcht2",     { Mb }, 0 },
10260   },
10261   {
10262     /* MOD_0F18_REG_4 */
10263     { "nop/reserved",   { Mb }, 0 },
10264   },
10265   {
10266     /* MOD_0F18_REG_5 */
10267     { "nop/reserved",   { Mb }, 0 },
10268   },
10269   {
10270     /* MOD_0F18_REG_6 */
10271     { "nop/reserved",   { Mb }, 0 },
10272   },
10273   {
10274     /* MOD_0F18_REG_7 */
10275     { "nop/reserved",   { Mb }, 0 },
10276   },
10277   {
10278     /* MOD_0F1A_PREFIX_0 */
10279     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10280     { "nopQ",           { Ev }, 0 },
10281   },
10282   {
10283     /* MOD_0F1B_PREFIX_0 */
10284     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10285     { "nopQ",           { Ev }, 0 },
10286   },
10287   {
10288     /* MOD_0F1B_PREFIX_1 */
10289     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10290     { "nopQ",           { Ev }, 0 },
10291   },
10292   {
10293     /* MOD_0F1C_PREFIX_0 */
10294     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10295     { "nopQ",           { Ev }, 0 },
10296   },
10297   {
10298     /* MOD_0F1E_PREFIX_1 */
10299     { "nopQ",           { Ev }, 0 },
10300     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10301   },
10302   {
10303     /* MOD_0F24 */
10304     { Bad_Opcode },
10305     { "movL",           { Rd, Td }, 0 },
10306   },
10307   {
10308     /* MOD_0F26 */
10309     { Bad_Opcode },
10310     { "movL",           { Td, Rd }, 0 },
10311   },
10312   {
10313     /* MOD_0F2B_PREFIX_0 */
10314     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10315   },
10316   {
10317     /* MOD_0F2B_PREFIX_1 */
10318     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10319   },
10320   {
10321     /* MOD_0F2B_PREFIX_2 */
10322     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10323   },
10324   {
10325     /* MOD_0F2B_PREFIX_3 */
10326     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10327   },
10328   {
10329     /* MOD_0F50 */
10330     { Bad_Opcode },
10331     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10332   },
10333   {
10334     /* MOD_0F71_REG_2 */
10335     { Bad_Opcode },
10336     { "psrlw",          { MS, Ib }, 0 },
10337   },
10338   {
10339     /* MOD_0F71_REG_4 */
10340     { Bad_Opcode },
10341     { "psraw",          { MS, Ib }, 0 },
10342   },
10343   {
10344     /* MOD_0F71_REG_6 */
10345     { Bad_Opcode },
10346     { "psllw",          { MS, Ib }, 0 },
10347   },
10348   {
10349     /* MOD_0F72_REG_2 */
10350     { Bad_Opcode },
10351     { "psrld",          { MS, Ib }, 0 },
10352   },
10353   {
10354     /* MOD_0F72_REG_4 */
10355     { Bad_Opcode },
10356     { "psrad",          { MS, Ib }, 0 },
10357   },
10358   {
10359     /* MOD_0F72_REG_6 */
10360     { Bad_Opcode },
10361     { "pslld",          { MS, Ib }, 0 },
10362   },
10363   {
10364     /* MOD_0F73_REG_2 */
10365     { Bad_Opcode },
10366     { "psrlq",          { MS, Ib }, 0 },
10367   },
10368   {
10369     /* MOD_0F73_REG_3 */
10370     { Bad_Opcode },
10371     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10372   },
10373   {
10374     /* MOD_0F73_REG_6 */
10375     { Bad_Opcode },
10376     { "psllq",          { MS, Ib }, 0 },
10377   },
10378   {
10379     /* MOD_0F73_REG_7 */
10380     { Bad_Opcode },
10381     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10382   },
10383   {
10384     /* MOD_0FAE_REG_0 */
10385     { "fxsave",         { FXSAVE }, 0 },
10386     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10387   },
10388   {
10389     /* MOD_0FAE_REG_1 */
10390     { "fxrstor",        { FXSAVE }, 0 },
10391     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10392   },
10393   {
10394     /* MOD_0FAE_REG_2 */
10395     { "ldmxcsr",        { Md }, 0 },
10396     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10397   },
10398   {
10399     /* MOD_0FAE_REG_3 */
10400     { "stmxcsr",        { Md }, 0 },
10401     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10402   },
10403   {
10404     /* MOD_0FAE_REG_4 */
10405     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10406     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10407   },
10408   {
10409     /* MOD_0FAE_REG_5 */
10410     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10411     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10412   },
10413   {
10414     /* MOD_0FAE_REG_6 */
10415     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10416     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10417   },
10418   {
10419     /* MOD_0FAE_REG_7 */
10420     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10421     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10422   },
10423   {
10424     /* MOD_0FB2 */
10425     { "lssS",           { Gv, Mp }, 0 },
10426   },
10427   {
10428     /* MOD_0FB4 */
10429     { "lfsS",           { Gv, Mp }, 0 },
10430   },
10431   {
10432     /* MOD_0FB5 */
10433     { "lgsS",           { Gv, Mp }, 0 },
10434   },
10435   {
10436     /* MOD_0FC3 */
10437     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10438   },
10439   {
10440     /* MOD_0FC7_REG_3 */
10441     { "xrstors",        { FXSAVE }, 0 },
10442   },
10443   {
10444     /* MOD_0FC7_REG_4 */
10445     { "xsavec",         { FXSAVE }, 0 },
10446   },
10447   {
10448     /* MOD_0FC7_REG_5 */
10449     { "xsaves",         { FXSAVE }, 0 },
10450   },
10451   {
10452     /* MOD_0FC7_REG_6 */
10453     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10454     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10455   },
10456   {
10457     /* MOD_0FC7_REG_7 */
10458     { "vmptrst",        { Mq }, 0 },
10459     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10460   },
10461   {
10462     /* MOD_0FD7 */
10463     { Bad_Opcode },
10464     { "pmovmskb",       { Gdq, MS }, 0 },
10465   },
10466   {
10467     /* MOD_0FE7_PREFIX_2 */
10468     { "movntdq",        { Mx, XM }, 0 },
10469   },
10470   {
10471     /* MOD_0FF0_PREFIX_3 */
10472     { "lddqu",          { XM, M }, 0 },
10473   },
10474   {
10475     /* MOD_0F382A_PREFIX_2 */
10476     { "movntdqa",       { XM, Mx }, 0 },
10477   },
10478   {
10479     /* MOD_0F38F5_PREFIX_2 */
10480     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10481   },
10482   {
10483     /* MOD_0F38F6_PREFIX_0 */
10484     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10485   },
10486   {
10487     /* MOD_0F38F8_PREFIX_1 */
10488     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10489   },
10490   {
10491     /* MOD_0F38F8_PREFIX_2 */
10492     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10493   },
10494   {
10495     /* MOD_0F38F8_PREFIX_3 */
10496     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10497   },
10498   {
10499     /* MOD_0F38F9_PREFIX_0 */
10500     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10501   },
10502   {
10503     /* MOD_62_32BIT */
10504     { "bound{S|}",      { Gv, Ma }, 0 },
10505     { EVEX_TABLE (EVEX_0F) },
10506   },
10507   {
10508     /* MOD_C4_32BIT */
10509     { "lesS",           { Gv, Mp }, 0 },
10510     { VEX_C4_TABLE (VEX_0F) },
10511   },
10512   {
10513     /* MOD_C5_32BIT */
10514     { "ldsS",           { Gv, Mp }, 0 },
10515     { VEX_C5_TABLE (VEX_0F) },
10516   },
10517   {
10518     /* MOD_VEX_0F12_PREFIX_0 */
10519     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10520     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10521   },
10522   {
10523     /* MOD_VEX_0F12_PREFIX_2 */
10524     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10525   },
10526   {
10527     /* MOD_VEX_0F13 */
10528     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10529   },
10530   {
10531     /* MOD_VEX_0F16_PREFIX_0 */
10532     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10533     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10534   },
10535   {
10536     /* MOD_VEX_0F16_PREFIX_2 */
10537     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10538   },
10539   {
10540     /* MOD_VEX_0F17 */
10541     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10542   },
10543   {
10544     /* MOD_VEX_0F2B */
10545     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10546   },
10547   {
10548     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10549     { Bad_Opcode },
10550     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10551   },
10552   {
10553     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10554     { Bad_Opcode },
10555     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10556   },
10557   {
10558     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10559     { Bad_Opcode },
10560     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10561   },
10562   {
10563     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10564     { Bad_Opcode },
10565     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10566   },
10567   {
10568     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10569     { Bad_Opcode },
10570     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10571   },
10572   {
10573     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10574     { Bad_Opcode },
10575     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10576   },
10577   {
10578     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10579     { Bad_Opcode },
10580     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10581   },
10582   {
10583     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10584     { Bad_Opcode },
10585     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10586   },
10587   {
10588     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10589     { Bad_Opcode },
10590     { "knotw",          { MaskG, MaskR }, 0 },
10591   },
10592   {
10593     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10594     { Bad_Opcode },
10595     { "knotq",          { MaskG, MaskR }, 0 },
10596   },
10597   {
10598     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10599     { Bad_Opcode },
10600     { "knotb",          { MaskG, MaskR }, 0 },
10601   },
10602   {
10603     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10604     { Bad_Opcode },
10605     { "knotd",          { MaskG, MaskR }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10609     { Bad_Opcode },
10610     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10611   },
10612   {
10613     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10614     { Bad_Opcode },
10615     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10616   },
10617   {
10618     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10619     { Bad_Opcode },
10620     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10621   },
10622   {
10623     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10624     { Bad_Opcode },
10625     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10626   },
10627  {
10628     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10629     { Bad_Opcode },
10630     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10631   },
10632   {
10633     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10634     { Bad_Opcode },
10635     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10639     { Bad_Opcode },
10640     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10644     { Bad_Opcode },
10645     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10649     { Bad_Opcode },
10650     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10654     { Bad_Opcode },
10655     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10656   },
10657   {
10658     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10659     { Bad_Opcode },
10660     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10664     { Bad_Opcode },
10665     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10669     { Bad_Opcode },
10670     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10674     { Bad_Opcode },
10675     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10676   },
10677   {
10678     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10679     { Bad_Opcode },
10680     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10684     { Bad_Opcode },
10685     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10689     { Bad_Opcode },
10690     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10694     { Bad_Opcode },
10695     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10699     { Bad_Opcode },
10700     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_0F50 */
10704     { Bad_Opcode },
10705     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10706   },
10707   {
10708     /* MOD_VEX_0F71_REG_2 */
10709     { Bad_Opcode },
10710     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10711   },
10712   {
10713     /* MOD_VEX_0F71_REG_4 */
10714     { Bad_Opcode },
10715     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10716   },
10717   {
10718     /* MOD_VEX_0F71_REG_6 */
10719     { Bad_Opcode },
10720     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10721   },
10722   {
10723     /* MOD_VEX_0F72_REG_2 */
10724     { Bad_Opcode },
10725     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10726   },
10727   {
10728     /* MOD_VEX_0F72_REG_4 */
10729     { Bad_Opcode },
10730     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10731   },
10732   {
10733     /* MOD_VEX_0F72_REG_6 */
10734     { Bad_Opcode },
10735     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10736   },
10737   {
10738     /* MOD_VEX_0F73_REG_2 */
10739     { Bad_Opcode },
10740     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10741   },
10742   {
10743     /* MOD_VEX_0F73_REG_3 */
10744     { Bad_Opcode },
10745     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10746   },
10747   {
10748     /* MOD_VEX_0F73_REG_6 */
10749     { Bad_Opcode },
10750     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10751   },
10752   {
10753     /* MOD_VEX_0F73_REG_7 */
10754     { Bad_Opcode },
10755     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10756   },
10757   {
10758     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10759     { "kmovw",          { Ew, MaskG }, 0 },
10760     { Bad_Opcode },
10761   },
10762   {
10763     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10764     { "kmovq",          { Eq, MaskG }, 0 },
10765     { Bad_Opcode },
10766   },
10767   {
10768     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10769     { "kmovb",          { Eb, MaskG }, 0 },
10770     { Bad_Opcode },
10771   },
10772   {
10773     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10774     { "kmovd",          { Ed, MaskG }, 0 },
10775     { Bad_Opcode },
10776   },
10777   {
10778     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10779     { Bad_Opcode },
10780     { "kmovw",          { MaskG, Rdq }, 0 },
10781   },
10782   {
10783     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10784     { Bad_Opcode },
10785     { "kmovb",          { MaskG, Rdq }, 0 },
10786   },
10787   {
10788     /* MOD_VEX_0F92_P_3_LEN_0 */
10789     { Bad_Opcode },
10790     { "kmovK",          { MaskG, Rdq }, 0 },
10791   },
10792   {
10793     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10794     { Bad_Opcode },
10795     { "kmovw",          { Gdq, MaskR }, 0 },
10796   },
10797   {
10798     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10799     { Bad_Opcode },
10800     { "kmovb",          { Gdq, MaskR }, 0 },
10801   },
10802   {
10803     /* MOD_VEX_0F93_P_3_LEN_0 */
10804     { Bad_Opcode },
10805     { "kmovK",          { Gdq, MaskR }, 0 },
10806   },
10807   {
10808     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10809     { Bad_Opcode },
10810     { "kortestw", { MaskG, MaskR }, 0 },
10811   },
10812   {
10813     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10814     { Bad_Opcode },
10815     { "kortestq", { MaskG, MaskR }, 0 },
10816   },
10817   {
10818     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10819     { Bad_Opcode },
10820     { "kortestb", { MaskG, MaskR }, 0 },
10821   },
10822   {
10823     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10824     { Bad_Opcode },
10825     { "kortestd", { MaskG, MaskR }, 0 },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10829     { Bad_Opcode },
10830     { "ktestw", { MaskG, MaskR }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10834     { Bad_Opcode },
10835     { "ktestq", { MaskG, MaskR }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10839     { Bad_Opcode },
10840     { "ktestb", { MaskG, MaskR }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10844     { Bad_Opcode },
10845     { "ktestd", { MaskG, MaskR }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_0FAE_REG_2 */
10849     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10850   },
10851   {
10852     /* MOD_VEX_0FAE_REG_3 */
10853     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10854   },
10855   {
10856     /* MOD_VEX_0FD7_PREFIX_2 */
10857     { Bad_Opcode },
10858     { "vpmovmskb",      { Gdq, XS }, 0 },
10859   },
10860   {
10861     /* MOD_VEX_0FE7_PREFIX_2 */
10862     { "vmovntdq",       { Mx, XM }, 0 },
10863   },
10864   {
10865     /* MOD_VEX_0FF0_PREFIX_3 */
10866     { "vlddqu",         { XM, M }, 0 },
10867   },
10868   {
10869     /* MOD_VEX_0F381A_PREFIX_2 */
10870     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10871   },
10872   {
10873     /* MOD_VEX_0F382A_PREFIX_2 */
10874     { "vmovntdqa",      { XM, Mx }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_0F382C_PREFIX_2 */
10878     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10879   },
10880   {
10881     /* MOD_VEX_0F382D_PREFIX_2 */
10882     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10883   },
10884   {
10885     /* MOD_VEX_0F382E_PREFIX_2 */
10886     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10887   },
10888   {
10889     /* MOD_VEX_0F382F_PREFIX_2 */
10890     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10891   },
10892   {
10893     /* MOD_VEX_0F385A_PREFIX_2 */
10894     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10895   },
10896   {
10897     /* MOD_VEX_0F388C_PREFIX_2 */
10898     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10899   },
10900   {
10901     /* MOD_VEX_0F388E_PREFIX_2 */
10902     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10903   },
10904   {
10905     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10906     { Bad_Opcode },
10907     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10908   },
10909   {
10910     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10911     { Bad_Opcode },
10912     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10916     { Bad_Opcode },
10917     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10921     { Bad_Opcode },
10922     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10923   },
10924   {
10925     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10926     { Bad_Opcode },
10927     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10928   },
10929   {
10930     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10931     { Bad_Opcode },
10932     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10933   },
10934   {
10935     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10936     { Bad_Opcode },
10937     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10938   },
10939   {
10940     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10941     { Bad_Opcode },
10942     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10943   },
10944
10945 #include "i386-dis-evex-mod.h"
10946 };
10947
10948 static const struct dis386 rm_table[][8] = {
10949   {
10950     /* RM_C6_REG_7 */
10951     { "xabort",         { Skip_MODRM, Ib }, 0 },
10952   },
10953   {
10954     /* RM_C7_REG_7 */
10955     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10956   },
10957   {
10958     /* RM_0F01_REG_0 */
10959     { "enclv",          { Skip_MODRM }, 0 },
10960     { "vmcall",         { Skip_MODRM }, 0 },
10961     { "vmlaunch",       { Skip_MODRM }, 0 },
10962     { "vmresume",       { Skip_MODRM }, 0 },
10963     { "vmxoff",         { Skip_MODRM }, 0 },
10964     { "pconfig",        { Skip_MODRM }, 0 },
10965   },
10966   {
10967     /* RM_0F01_REG_1 */
10968     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10969     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10970     { "clac",           { Skip_MODRM }, 0 },
10971     { "stac",           { Skip_MODRM }, 0 },
10972     { Bad_Opcode },
10973     { Bad_Opcode },
10974     { Bad_Opcode },
10975     { "encls",          { Skip_MODRM }, 0 },
10976   },
10977   {
10978     /* RM_0F01_REG_2 */
10979     { "xgetbv",         { Skip_MODRM }, 0 },
10980     { "xsetbv",         { Skip_MODRM }, 0 },
10981     { Bad_Opcode },
10982     { Bad_Opcode },
10983     { "vmfunc",         { Skip_MODRM }, 0 },
10984     { "xend",           { Skip_MODRM }, 0 },
10985     { "xtest",          { Skip_MODRM }, 0 },
10986     { "enclu",          { Skip_MODRM }, 0 },
10987   },
10988   {
10989     /* RM_0F01_REG_3 */
10990     { "vmrun",          { Skip_MODRM }, 0 },
10991     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10992     { "vmload",         { Skip_MODRM }, 0 },
10993     { "vmsave",         { Skip_MODRM }, 0 },
10994     { "stgi",           { Skip_MODRM }, 0 },
10995     { "clgi",           { Skip_MODRM }, 0 },
10996     { "skinit",         { Skip_MODRM }, 0 },
10997     { "invlpga",        { Skip_MODRM }, 0 },
10998   },
10999   {
11000     /* RM_0F01_REG_5_MOD_3 */
11001     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11002     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11003     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11004     { Bad_Opcode },
11005     { Bad_Opcode },
11006     { Bad_Opcode },
11007     { "rdpkru",         { Skip_MODRM }, 0 },
11008     { "wrpkru",         { Skip_MODRM }, 0 },
11009   },
11010   {
11011     /* RM_0F01_REG_7_MOD_3 */
11012     { "swapgs",         { Skip_MODRM }, 0  },
11013     { "rdtscp",         { Skip_MODRM }, 0  },
11014     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11015     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11016     { "clzero",         { Skip_MODRM }, 0  },
11017     { "rdpru",          { Skip_MODRM }, 0  },
11018   },
11019   {
11020     /* RM_0F1E_P_1_MOD_3_REG_7 */
11021     { "nopQ",           { Ev }, 0 },
11022     { "nopQ",           { Ev }, 0 },
11023     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11024     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11025     { "nopQ",           { Ev }, 0 },
11026     { "nopQ",           { Ev }, 0 },
11027     { "nopQ",           { Ev }, 0 },
11028     { "nopQ",           { Ev }, 0 },
11029   },
11030   {
11031     /* RM_0FAE_REG_6_MOD_3 */
11032     { "mfence",         { Skip_MODRM }, 0 },
11033   },
11034   {
11035     /* RM_0FAE_REG_7_MOD_3 */
11036     { "sfence",         { Skip_MODRM }, 0 },
11037
11038   },
11039 };
11040
11041 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11042
11043 /* We use the high bit to indicate different name for the same
11044    prefix.  */
11045 #define REP_PREFIX      (0xf3 | 0x100)
11046 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11047 #define XRELEASE_PREFIX (0xf3 | 0x400)
11048 #define BND_PREFIX      (0xf2 | 0x400)
11049 #define NOTRACK_PREFIX  (0x3e | 0x100)
11050
11051 /* Remember if the current op is a jump instruction.  */
11052 static bfd_boolean op_is_jump = FALSE;
11053
11054 static int
11055 ckprefix (void)
11056 {
11057   int newrex, i, length;
11058   rex = 0;
11059   prefixes = 0;
11060   used_prefixes = 0;
11061   rex_used = 0;
11062   last_lock_prefix = -1;
11063   last_repz_prefix = -1;
11064   last_repnz_prefix = -1;
11065   last_data_prefix = -1;
11066   last_addr_prefix = -1;
11067   last_rex_prefix = -1;
11068   last_seg_prefix = -1;
11069   fwait_prefix = -1;
11070   active_seg_prefix = 0;
11071   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11072     all_prefixes[i] = 0;
11073   i = 0;
11074   length = 0;
11075   /* The maximum instruction length is 15bytes.  */
11076   while (length < MAX_CODE_LENGTH - 1)
11077     {
11078       FETCH_DATA (the_info, codep + 1);
11079       newrex = 0;
11080       switch (*codep)
11081         {
11082         /* REX prefixes family.  */
11083         case 0x40:
11084         case 0x41:
11085         case 0x42:
11086         case 0x43:
11087         case 0x44:
11088         case 0x45:
11089         case 0x46:
11090         case 0x47:
11091         case 0x48:
11092         case 0x49:
11093         case 0x4a:
11094         case 0x4b:
11095         case 0x4c:
11096         case 0x4d:
11097         case 0x4e:
11098         case 0x4f:
11099           if (address_mode == mode_64bit)
11100             newrex = *codep;
11101           else
11102             return 1;
11103           last_rex_prefix = i;
11104           break;
11105         case 0xf3:
11106           prefixes |= PREFIX_REPZ;
11107           last_repz_prefix = i;
11108           break;
11109         case 0xf2:
11110           prefixes |= PREFIX_REPNZ;
11111           last_repnz_prefix = i;
11112           break;
11113         case 0xf0:
11114           prefixes |= PREFIX_LOCK;
11115           last_lock_prefix = i;
11116           break;
11117         case 0x2e:
11118           prefixes |= PREFIX_CS;
11119           last_seg_prefix = i;
11120           active_seg_prefix = PREFIX_CS;
11121           break;
11122         case 0x36:
11123           prefixes |= PREFIX_SS;
11124           last_seg_prefix = i;
11125           active_seg_prefix = PREFIX_SS;
11126           break;
11127         case 0x3e:
11128           prefixes |= PREFIX_DS;
11129           last_seg_prefix = i;
11130           active_seg_prefix = PREFIX_DS;
11131           break;
11132         case 0x26:
11133           prefixes |= PREFIX_ES;
11134           last_seg_prefix = i;
11135           active_seg_prefix = PREFIX_ES;
11136           break;
11137         case 0x64:
11138           prefixes |= PREFIX_FS;
11139           last_seg_prefix = i;
11140           active_seg_prefix = PREFIX_FS;
11141           break;
11142         case 0x65:
11143           prefixes |= PREFIX_GS;
11144           last_seg_prefix = i;
11145           active_seg_prefix = PREFIX_GS;
11146           break;
11147         case 0x66:
11148           prefixes |= PREFIX_DATA;
11149           last_data_prefix = i;
11150           break;
11151         case 0x67:
11152           prefixes |= PREFIX_ADDR;
11153           last_addr_prefix = i;
11154           break;
11155         case FWAIT_OPCODE:
11156           /* fwait is really an instruction.  If there are prefixes
11157              before the fwait, they belong to the fwait, *not* to the
11158              following instruction.  */
11159           fwait_prefix = i;
11160           if (prefixes || rex)
11161             {
11162               prefixes |= PREFIX_FWAIT;
11163               codep++;
11164               /* This ensures that the previous REX prefixes are noticed
11165                  as unused prefixes, as in the return case below.  */
11166               rex_used = rex;
11167               return 1;
11168             }
11169           prefixes = PREFIX_FWAIT;
11170           break;
11171         default:
11172           return 1;
11173         }
11174       /* Rex is ignored when followed by another prefix.  */
11175       if (rex)
11176         {
11177           rex_used = rex;
11178           return 1;
11179         }
11180       if (*codep != FWAIT_OPCODE)
11181         all_prefixes[i++] = *codep;
11182       rex = newrex;
11183       codep++;
11184       length++;
11185     }
11186   return 0;
11187 }
11188
11189 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11190    prefix byte.  */
11191
11192 static const char *
11193 prefix_name (int pref, int sizeflag)
11194 {
11195   static const char *rexes [16] =
11196     {
11197       "rex",            /* 0x40 */
11198       "rex.B",          /* 0x41 */
11199       "rex.X",          /* 0x42 */
11200       "rex.XB",         /* 0x43 */
11201       "rex.R",          /* 0x44 */
11202       "rex.RB",         /* 0x45 */
11203       "rex.RX",         /* 0x46 */
11204       "rex.RXB",        /* 0x47 */
11205       "rex.W",          /* 0x48 */
11206       "rex.WB",         /* 0x49 */
11207       "rex.WX",         /* 0x4a */
11208       "rex.WXB",        /* 0x4b */
11209       "rex.WR",         /* 0x4c */
11210       "rex.WRB",        /* 0x4d */
11211       "rex.WRX",        /* 0x4e */
11212       "rex.WRXB",       /* 0x4f */
11213     };
11214
11215   switch (pref)
11216     {
11217     /* REX prefixes family.  */
11218     case 0x40:
11219     case 0x41:
11220     case 0x42:
11221     case 0x43:
11222     case 0x44:
11223     case 0x45:
11224     case 0x46:
11225     case 0x47:
11226     case 0x48:
11227     case 0x49:
11228     case 0x4a:
11229     case 0x4b:
11230     case 0x4c:
11231     case 0x4d:
11232     case 0x4e:
11233     case 0x4f:
11234       return rexes [pref - 0x40];
11235     case 0xf3:
11236       return "repz";
11237     case 0xf2:
11238       return "repnz";
11239     case 0xf0:
11240       return "lock";
11241     case 0x2e:
11242       return "cs";
11243     case 0x36:
11244       return "ss";
11245     case 0x3e:
11246       return "ds";
11247     case 0x26:
11248       return "es";
11249     case 0x64:
11250       return "fs";
11251     case 0x65:
11252       return "gs";
11253     case 0x66:
11254       return (sizeflag & DFLAG) ? "data16" : "data32";
11255     case 0x67:
11256       if (address_mode == mode_64bit)
11257         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11258       else
11259         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11260     case FWAIT_OPCODE:
11261       return "fwait";
11262     case REP_PREFIX:
11263       return "rep";
11264     case XACQUIRE_PREFIX:
11265       return "xacquire";
11266     case XRELEASE_PREFIX:
11267       return "xrelease";
11268     case BND_PREFIX:
11269       return "bnd";
11270     case NOTRACK_PREFIX:
11271       return "notrack";
11272     default:
11273       return NULL;
11274     }
11275 }
11276
11277 static char op_out[MAX_OPERANDS][100];
11278 static int op_ad, op_index[MAX_OPERANDS];
11279 static int two_source_ops;
11280 static bfd_vma op_address[MAX_OPERANDS];
11281 static bfd_vma op_riprel[MAX_OPERANDS];
11282 static bfd_vma start_pc;
11283
11284 /*
11285  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11286  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11287  *   section of the "Virtual 8086 Mode" chapter.)
11288  * 'pc' should be the address of this instruction, it will
11289  *   be used to print the target address if this is a relative jump or call
11290  * The function returns the length of this instruction in bytes.
11291  */
11292
11293 static char intel_syntax;
11294 static char intel_mnemonic = !SYSV386_COMPAT;
11295 static char open_char;
11296 static char close_char;
11297 static char separator_char;
11298 static char scale_char;
11299
11300 enum x86_64_isa
11301 {
11302   amd64 = 1,
11303   intel64
11304 };
11305
11306 static enum x86_64_isa isa64;
11307
11308 /* Here for backwards compatibility.  When gdb stops using
11309    print_insn_i386_att and print_insn_i386_intel these functions can
11310    disappear, and print_insn_i386 be merged into print_insn.  */
11311 int
11312 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11313 {
11314   intel_syntax = 0;
11315
11316   return print_insn (pc, info);
11317 }
11318
11319 int
11320 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11321 {
11322   intel_syntax = 1;
11323
11324   return print_insn (pc, info);
11325 }
11326
11327 int
11328 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11329 {
11330   intel_syntax = -1;
11331
11332   return print_insn (pc, info);
11333 }
11334
11335 void
11336 print_i386_disassembler_options (FILE *stream)
11337 {
11338   fprintf (stream, _("\n\
11339 The following i386/x86-64 specific disassembler options are supported for use\n\
11340 with the -M switch (multiple options should be separated by commas):\n"));
11341
11342   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11343   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11344   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11345   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11346   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11347   fprintf (stream, _("  att-mnemonic\n"
11348                      "              Display instruction in AT&T mnemonic\n"));
11349   fprintf (stream, _("  intel-mnemonic\n"
11350                      "              Display instruction in Intel mnemonic\n"));
11351   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11352   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11353   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11354   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11355   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11356   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11357   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11358   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11359 }
11360
11361 /* Bad opcode.  */
11362 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11363
11364 /* Get a pointer to struct dis386 with a valid name.  */
11365
11366 static const struct dis386 *
11367 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11368 {
11369   int vindex, vex_table_index;
11370
11371   if (dp->name != NULL)
11372     return dp;
11373
11374   switch (dp->op[0].bytemode)
11375     {
11376     case USE_REG_TABLE:
11377       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11378       break;
11379
11380     case USE_MOD_TABLE:
11381       vindex = modrm.mod == 0x3 ? 1 : 0;
11382       dp = &mod_table[dp->op[1].bytemode][vindex];
11383       break;
11384
11385     case USE_RM_TABLE:
11386       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11387       break;
11388
11389     case USE_PREFIX_TABLE:
11390       if (need_vex)
11391         {
11392           /* The prefix in VEX is implicit.  */
11393           switch (vex.prefix)
11394             {
11395             case 0:
11396               vindex = 0;
11397               break;
11398             case REPE_PREFIX_OPCODE:
11399               vindex = 1;
11400               break;
11401             case DATA_PREFIX_OPCODE:
11402               vindex = 2;
11403               break;
11404             case REPNE_PREFIX_OPCODE:
11405               vindex = 3;
11406               break;
11407             default:
11408               abort ();
11409               break;
11410             }
11411         }
11412       else
11413         {
11414           int last_prefix = -1;
11415           int prefix = 0;
11416           vindex = 0;
11417           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11418              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11419              last one wins.  */
11420           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11421             {
11422               if (last_repz_prefix > last_repnz_prefix)
11423                 {
11424                   vindex = 1;
11425                   prefix = PREFIX_REPZ;
11426                   last_prefix = last_repz_prefix;
11427                 }
11428               else
11429                 {
11430                   vindex = 3;
11431                   prefix = PREFIX_REPNZ;
11432                   last_prefix = last_repnz_prefix;
11433                 }
11434
11435               /* Check if prefix should be ignored.  */
11436               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11437                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11438                    & prefix) != 0)
11439                 vindex = 0;
11440             }
11441
11442           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11443             {
11444               vindex = 2;
11445               prefix = PREFIX_DATA;
11446               last_prefix = last_data_prefix;
11447             }
11448
11449           if (vindex != 0)
11450             {
11451               used_prefixes |= prefix;
11452               all_prefixes[last_prefix] = 0;
11453             }
11454         }
11455       dp = &prefix_table[dp->op[1].bytemode][vindex];
11456       break;
11457
11458     case USE_X86_64_TABLE:
11459       vindex = address_mode == mode_64bit ? 1 : 0;
11460       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11461       break;
11462
11463     case USE_3BYTE_TABLE:
11464       FETCH_DATA (info, codep + 2);
11465       vindex = *codep++;
11466       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11467       end_codep = codep;
11468       modrm.mod = (*codep >> 6) & 3;
11469       modrm.reg = (*codep >> 3) & 7;
11470       modrm.rm = *codep & 7;
11471       break;
11472
11473     case USE_VEX_LEN_TABLE:
11474       if (!need_vex)
11475         abort ();
11476
11477       switch (vex.length)
11478         {
11479         case 128:
11480           vindex = 0;
11481           break;
11482         case 256:
11483           vindex = 1;
11484           break;
11485         default:
11486           abort ();
11487           break;
11488         }
11489
11490       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11491       break;
11492
11493     case USE_EVEX_LEN_TABLE:
11494       if (!vex.evex)
11495         abort ();
11496
11497       switch (vex.length)
11498         {
11499         case 128:
11500           vindex = 0;
11501           break;
11502         case 256:
11503           vindex = 1;
11504           break;
11505         case 512:
11506           vindex = 2;
11507           break;
11508         default:
11509           abort ();
11510           break;
11511         }
11512
11513       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11514       break;
11515
11516     case USE_XOP_8F_TABLE:
11517       FETCH_DATA (info, codep + 3);
11518       rex = ~(*codep >> 5) & 0x7;
11519
11520       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11521       switch ((*codep & 0x1f))
11522         {
11523         default:
11524           dp = &bad_opcode;
11525           return dp;
11526         case 0x8:
11527           vex_table_index = XOP_08;
11528           break;
11529         case 0x9:
11530           vex_table_index = XOP_09;
11531           break;
11532         case 0xa:
11533           vex_table_index = XOP_0A;
11534           break;
11535         }
11536       codep++;
11537       vex.w = *codep & 0x80;
11538       if (vex.w && address_mode == mode_64bit)
11539         rex |= REX_W;
11540
11541       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11542       if (address_mode != mode_64bit)
11543         {
11544           /* In 16/32-bit mode REX_B is silently ignored.  */
11545           rex &= ~REX_B;
11546         }
11547
11548       vex.length = (*codep & 0x4) ? 256 : 128;
11549       switch ((*codep & 0x3))
11550         {
11551         case 0:
11552           break;
11553         case 1:
11554           vex.prefix = DATA_PREFIX_OPCODE;
11555           break;
11556         case 2:
11557           vex.prefix = REPE_PREFIX_OPCODE;
11558           break;
11559         case 3:
11560           vex.prefix = REPNE_PREFIX_OPCODE;
11561           break;
11562         }
11563       need_vex = 1;
11564       need_vex_reg = 1;
11565       codep++;
11566       vindex = *codep++;
11567       dp = &xop_table[vex_table_index][vindex];
11568
11569       end_codep = codep;
11570       FETCH_DATA (info, codep + 1);
11571       modrm.mod = (*codep >> 6) & 3;
11572       modrm.reg = (*codep >> 3) & 7;
11573       modrm.rm = *codep & 7;
11574       break;
11575
11576     case USE_VEX_C4_TABLE:
11577       /* VEX prefix.  */
11578       FETCH_DATA (info, codep + 3);
11579       rex = ~(*codep >> 5) & 0x7;
11580       switch ((*codep & 0x1f))
11581         {
11582         default:
11583           dp = &bad_opcode;
11584           return dp;
11585         case 0x1:
11586           vex_table_index = VEX_0F;
11587           break;
11588         case 0x2:
11589           vex_table_index = VEX_0F38;
11590           break;
11591         case 0x3:
11592           vex_table_index = VEX_0F3A;
11593           break;
11594         }
11595       codep++;
11596       vex.w = *codep & 0x80;
11597       if (address_mode == mode_64bit)
11598         {
11599           if (vex.w)
11600             rex |= REX_W;
11601         }
11602       else
11603         {
11604           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11605              is ignored, other REX bits are 0 and the highest bit in
11606              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11607           rex = 0;
11608         }
11609       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11610       vex.length = (*codep & 0x4) ? 256 : 128;
11611       switch ((*codep & 0x3))
11612         {
11613         case 0:
11614           break;
11615         case 1:
11616           vex.prefix = DATA_PREFIX_OPCODE;
11617           break;
11618         case 2:
11619           vex.prefix = REPE_PREFIX_OPCODE;
11620           break;
11621         case 3:
11622           vex.prefix = REPNE_PREFIX_OPCODE;
11623           break;
11624         }
11625       need_vex = 1;
11626       need_vex_reg = 1;
11627       codep++;
11628       vindex = *codep++;
11629       dp = &vex_table[vex_table_index][vindex];
11630       end_codep = codep;
11631       /* There is no MODRM byte for VEX0F 77.  */
11632       if (vex_table_index != VEX_0F || vindex != 0x77)
11633         {
11634           FETCH_DATA (info, codep + 1);
11635           modrm.mod = (*codep >> 6) & 3;
11636           modrm.reg = (*codep >> 3) & 7;
11637           modrm.rm = *codep & 7;
11638         }
11639       break;
11640
11641     case USE_VEX_C5_TABLE:
11642       /* VEX prefix.  */
11643       FETCH_DATA (info, codep + 2);
11644       rex = (*codep & 0x80) ? 0 : REX_R;
11645
11646       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11647          VEX.vvvv is 1.  */
11648       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11649       vex.length = (*codep & 0x4) ? 256 : 128;
11650       switch ((*codep & 0x3))
11651         {
11652         case 0:
11653           break;
11654         case 1:
11655           vex.prefix = DATA_PREFIX_OPCODE;
11656           break;
11657         case 2:
11658           vex.prefix = REPE_PREFIX_OPCODE;
11659           break;
11660         case 3:
11661           vex.prefix = REPNE_PREFIX_OPCODE;
11662           break;
11663         }
11664       need_vex = 1;
11665       need_vex_reg = 1;
11666       codep++;
11667       vindex = *codep++;
11668       dp = &vex_table[dp->op[1].bytemode][vindex];
11669       end_codep = codep;
11670       /* There is no MODRM byte for VEX 77.  */
11671       if (vindex != 0x77)
11672         {
11673           FETCH_DATA (info, codep + 1);
11674           modrm.mod = (*codep >> 6) & 3;
11675           modrm.reg = (*codep >> 3) & 7;
11676           modrm.rm = *codep & 7;
11677         }
11678       break;
11679
11680     case USE_VEX_W_TABLE:
11681       if (!need_vex)
11682         abort ();
11683
11684       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11685       break;
11686
11687     case USE_EVEX_TABLE:
11688       two_source_ops = 0;
11689       /* EVEX prefix.  */
11690       vex.evex = 1;
11691       FETCH_DATA (info, codep + 4);
11692       /* The first byte after 0x62.  */
11693       rex = ~(*codep >> 5) & 0x7;
11694       vex.r = *codep & 0x10;
11695       switch ((*codep & 0xf))
11696         {
11697         default:
11698           return &bad_opcode;
11699         case 0x1:
11700           vex_table_index = EVEX_0F;
11701           break;
11702         case 0x2:
11703           vex_table_index = EVEX_0F38;
11704           break;
11705         case 0x3:
11706           vex_table_index = EVEX_0F3A;
11707           break;
11708         }
11709
11710       /* The second byte after 0x62.  */
11711       codep++;
11712       vex.w = *codep & 0x80;
11713       if (vex.w && address_mode == mode_64bit)
11714         rex |= REX_W;
11715
11716       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11717
11718       /* The U bit.  */
11719       if (!(*codep & 0x4))
11720         return &bad_opcode;
11721
11722       switch ((*codep & 0x3))
11723         {
11724         case 0:
11725           break;
11726         case 1:
11727           vex.prefix = DATA_PREFIX_OPCODE;
11728           break;
11729         case 2:
11730           vex.prefix = REPE_PREFIX_OPCODE;
11731           break;
11732         case 3:
11733           vex.prefix = REPNE_PREFIX_OPCODE;
11734           break;
11735         }
11736
11737       /* The third byte after 0x62.  */
11738       codep++;
11739
11740       /* Remember the static rounding bits.  */
11741       vex.ll = (*codep >> 5) & 3;
11742       vex.b = (*codep & 0x10) != 0;
11743
11744       vex.v = *codep & 0x8;
11745       vex.mask_register_specifier = *codep & 0x7;
11746       vex.zeroing = *codep & 0x80;
11747
11748       if (address_mode != mode_64bit)
11749         {
11750           /* In 16/32-bit mode silently ignore following bits.  */
11751           rex &= ~REX_B;
11752           vex.r = 1;
11753           vex.v = 1;
11754         }
11755
11756       need_vex = 1;
11757       need_vex_reg = 1;
11758       codep++;
11759       vindex = *codep++;
11760       dp = &evex_table[vex_table_index][vindex];
11761       end_codep = codep;
11762       FETCH_DATA (info, codep + 1);
11763       modrm.mod = (*codep >> 6) & 3;
11764       modrm.reg = (*codep >> 3) & 7;
11765       modrm.rm = *codep & 7;
11766
11767       /* Set vector length.  */
11768       if (modrm.mod == 3 && vex.b)
11769         vex.length = 512;
11770       else
11771         {
11772           switch (vex.ll)
11773             {
11774             case 0x0:
11775               vex.length = 128;
11776               break;
11777             case 0x1:
11778               vex.length = 256;
11779               break;
11780             case 0x2:
11781               vex.length = 512;
11782               break;
11783             default:
11784               return &bad_opcode;
11785             }
11786         }
11787       break;
11788
11789     case 0:
11790       dp = &bad_opcode;
11791       break;
11792
11793     default:
11794       abort ();
11795     }
11796
11797   if (dp->name != NULL)
11798     return dp;
11799   else
11800     return get_valid_dis386 (dp, info);
11801 }
11802
11803 static void
11804 get_sib (disassemble_info *info, int sizeflag)
11805 {
11806   /* If modrm.mod == 3, operand must be register.  */
11807   if (need_modrm
11808       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11809       && modrm.mod != 3
11810       && modrm.rm == 4)
11811     {
11812       FETCH_DATA (info, codep + 2);
11813       sib.index = (codep [1] >> 3) & 7;
11814       sib.scale = (codep [1] >> 6) & 3;
11815       sib.base = codep [1] & 7;
11816     }
11817 }
11818
11819 static int
11820 print_insn (bfd_vma pc, disassemble_info *info)
11821 {
11822   const struct dis386 *dp;
11823   int i;
11824   char *op_txt[MAX_OPERANDS];
11825   int needcomma;
11826   int sizeflag, orig_sizeflag;
11827   const char *p;
11828   struct dis_private priv;
11829   int prefix_length;
11830
11831   priv.orig_sizeflag = AFLAG | DFLAG;
11832   if ((info->mach & bfd_mach_i386_i386) != 0)
11833     address_mode = mode_32bit;
11834   else if (info->mach == bfd_mach_i386_i8086)
11835     {
11836       address_mode = mode_16bit;
11837       priv.orig_sizeflag = 0;
11838     }
11839   else
11840     address_mode = mode_64bit;
11841
11842   if (intel_syntax == (char) -1)
11843     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11844
11845   for (p = info->disassembler_options; p != NULL; )
11846     {
11847       if (CONST_STRNEQ (p, "amd64"))
11848         isa64 = amd64;
11849       else if (CONST_STRNEQ (p, "intel64"))
11850         isa64 = intel64;
11851       else if (CONST_STRNEQ (p, "x86-64"))
11852         {
11853           address_mode = mode_64bit;
11854           priv.orig_sizeflag = AFLAG | DFLAG;
11855         }
11856       else if (CONST_STRNEQ (p, "i386"))
11857         {
11858           address_mode = mode_32bit;
11859           priv.orig_sizeflag = AFLAG | DFLAG;
11860         }
11861       else if (CONST_STRNEQ (p, "i8086"))
11862         {
11863           address_mode = mode_16bit;
11864           priv.orig_sizeflag = 0;
11865         }
11866       else if (CONST_STRNEQ (p, "intel"))
11867         {
11868           intel_syntax = 1;
11869           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11870             intel_mnemonic = 1;
11871         }
11872       else if (CONST_STRNEQ (p, "att"))
11873         {
11874           intel_syntax = 0;
11875           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11876             intel_mnemonic = 0;
11877         }
11878       else if (CONST_STRNEQ (p, "addr"))
11879         {
11880           if (address_mode == mode_64bit)
11881             {
11882               if (p[4] == '3' && p[5] == '2')
11883                 priv.orig_sizeflag &= ~AFLAG;
11884               else if (p[4] == '6' && p[5] == '4')
11885                 priv.orig_sizeflag |= AFLAG;
11886             }
11887           else
11888             {
11889               if (p[4] == '1' && p[5] == '6')
11890                 priv.orig_sizeflag &= ~AFLAG;
11891               else if (p[4] == '3' && p[5] == '2')
11892                 priv.orig_sizeflag |= AFLAG;
11893             }
11894         }
11895       else if (CONST_STRNEQ (p, "data"))
11896         {
11897           if (p[4] == '1' && p[5] == '6')
11898             priv.orig_sizeflag &= ~DFLAG;
11899           else if (p[4] == '3' && p[5] == '2')
11900             priv.orig_sizeflag |= DFLAG;
11901         }
11902       else if (CONST_STRNEQ (p, "suffix"))
11903         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11904
11905       p = strchr (p, ',');
11906       if (p != NULL)
11907         p++;
11908     }
11909
11910   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11911     {
11912       (*info->fprintf_func) (info->stream,
11913                              _("64-bit address is disabled"));
11914       return -1;
11915     }
11916
11917   if (intel_syntax)
11918     {
11919       names64 = intel_names64;
11920       names32 = intel_names32;
11921       names16 = intel_names16;
11922       names8 = intel_names8;
11923       names8rex = intel_names8rex;
11924       names_seg = intel_names_seg;
11925       names_mm = intel_names_mm;
11926       names_bnd = intel_names_bnd;
11927       names_xmm = intel_names_xmm;
11928       names_ymm = intel_names_ymm;
11929       names_zmm = intel_names_zmm;
11930       index64 = intel_index64;
11931       index32 = intel_index32;
11932       names_mask = intel_names_mask;
11933       index16 = intel_index16;
11934       open_char = '[';
11935       close_char = ']';
11936       separator_char = '+';
11937       scale_char = '*';
11938     }
11939   else
11940     {
11941       names64 = att_names64;
11942       names32 = att_names32;
11943       names16 = att_names16;
11944       names8 = att_names8;
11945       names8rex = att_names8rex;
11946       names_seg = att_names_seg;
11947       names_mm = att_names_mm;
11948       names_bnd = att_names_bnd;
11949       names_xmm = att_names_xmm;
11950       names_ymm = att_names_ymm;
11951       names_zmm = att_names_zmm;
11952       index64 = att_index64;
11953       index32 = att_index32;
11954       names_mask = att_names_mask;
11955       index16 = att_index16;
11956       open_char = '(';
11957       close_char =  ')';
11958       separator_char = ',';
11959       scale_char = ',';
11960     }
11961
11962   /* The output looks better if we put 7 bytes on a line, since that
11963      puts most long word instructions on a single line.  Use 8 bytes
11964      for Intel L1OM.  */
11965   if ((info->mach & bfd_mach_l1om) != 0)
11966     info->bytes_per_line = 8;
11967   else
11968     info->bytes_per_line = 7;
11969
11970   info->private_data = &priv;
11971   priv.max_fetched = priv.the_buffer;
11972   priv.insn_start = pc;
11973
11974   obuf[0] = 0;
11975   for (i = 0; i < MAX_OPERANDS; ++i)
11976     {
11977       op_out[i][0] = 0;
11978       op_index[i] = -1;
11979     }
11980
11981   the_info = info;
11982   start_pc = pc;
11983   start_codep = priv.the_buffer;
11984   codep = priv.the_buffer;
11985
11986   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11987     {
11988       const char *name;
11989
11990       /* Getting here means we tried for data but didn't get it.  That
11991          means we have an incomplete instruction of some sort.  Just
11992          print the first byte as a prefix or a .byte pseudo-op.  */
11993       if (codep > priv.the_buffer)
11994         {
11995           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11996           if (name != NULL)
11997             (*info->fprintf_func) (info->stream, "%s", name);
11998           else
11999             {
12000               /* Just print the first byte as a .byte instruction.  */
12001               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12002                                      (unsigned int) priv.the_buffer[0]);
12003             }
12004
12005           return 1;
12006         }
12007
12008       return -1;
12009     }
12010
12011   obufp = obuf;
12012   sizeflag = priv.orig_sizeflag;
12013
12014   if (!ckprefix () || rex_used)
12015     {
12016       /* Too many prefixes or unused REX prefixes.  */
12017       for (i = 0;
12018            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12019            i++)
12020         (*info->fprintf_func) (info->stream, "%s%s",
12021                                i == 0 ? "" : " ",
12022                                prefix_name (all_prefixes[i], sizeflag));
12023       return i;
12024     }
12025
12026   insn_codep = codep;
12027
12028   FETCH_DATA (info, codep + 1);
12029   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12030
12031   if (((prefixes & PREFIX_FWAIT)
12032        && ((*codep < 0xd8) || (*codep > 0xdf))))
12033     {
12034       /* Handle prefixes before fwait.  */
12035       for (i = 0; i < fwait_prefix && all_prefixes[i];
12036            i++)
12037         (*info->fprintf_func) (info->stream, "%s ",
12038                                prefix_name (all_prefixes[i], sizeflag));
12039       (*info->fprintf_func) (info->stream, "fwait");
12040       return i + 1;
12041     }
12042
12043   if (*codep == 0x0f)
12044     {
12045       unsigned char threebyte;
12046
12047       codep++;
12048       FETCH_DATA (info, codep + 1);
12049       threebyte = *codep;
12050       dp = &dis386_twobyte[threebyte];
12051       need_modrm = twobyte_has_modrm[*codep];
12052       codep++;
12053     }
12054   else
12055     {
12056       dp = &dis386[*codep];
12057       need_modrm = onebyte_has_modrm[*codep];
12058       codep++;
12059     }
12060
12061   /* Save sizeflag for printing the extra prefixes later before updating
12062      it for mnemonic and operand processing.  The prefix names depend
12063      only on the address mode.  */
12064   orig_sizeflag = sizeflag;
12065   if (prefixes & PREFIX_ADDR)
12066     sizeflag ^= AFLAG;
12067   if ((prefixes & PREFIX_DATA))
12068     sizeflag ^= DFLAG;
12069
12070   end_codep = codep;
12071   if (need_modrm)
12072     {
12073       FETCH_DATA (info, codep + 1);
12074       modrm.mod = (*codep >> 6) & 3;
12075       modrm.reg = (*codep >> 3) & 7;
12076       modrm.rm = *codep & 7;
12077     }
12078
12079   need_vex = 0;
12080   need_vex_reg = 0;
12081   vex_w_done = 0;
12082   memset (&vex, 0, sizeof (vex));
12083
12084   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12085     {
12086       get_sib (info, sizeflag);
12087       dofloat (sizeflag);
12088     }
12089   else
12090     {
12091       dp = get_valid_dis386 (dp, info);
12092       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12093         {
12094           get_sib (info, sizeflag);
12095           for (i = 0; i < MAX_OPERANDS; ++i)
12096             {
12097               obufp = op_out[i];
12098               op_ad = MAX_OPERANDS - 1 - i;
12099               if (dp->op[i].rtn)
12100                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12101               /* For EVEX instruction after the last operand masking
12102                  should be printed.  */
12103               if (i == 0 && vex.evex)
12104                 {
12105                   /* Don't print {%k0}.  */
12106                   if (vex.mask_register_specifier)
12107                     {
12108                       oappend ("{");
12109                       oappend (names_mask[vex.mask_register_specifier]);
12110                       oappend ("}");
12111                     }
12112                   if (vex.zeroing)
12113                     oappend ("{z}");
12114                 }
12115             }
12116         }
12117     }
12118
12119   /* Clear instruction information.  */
12120   if (the_info)
12121     {
12122       the_info->insn_info_valid = 0;
12123       the_info->branch_delay_insns = 0;
12124       the_info->data_size = 0;
12125       the_info->insn_type = dis_noninsn;
12126       the_info->target = 0;
12127       the_info->target2 = 0;
12128     }
12129
12130   /* Reset jump operation indicator.  */
12131   op_is_jump = FALSE;
12132
12133   {
12134     int jump_detection = 0;
12135
12136     /* Extract flags.  */
12137     for (i = 0; i < MAX_OPERANDS; ++i)
12138       {
12139         if ((dp->op[i].rtn == OP_J)
12140             || (dp->op[i].rtn == OP_indirE))
12141           jump_detection |= 1;
12142         else if ((dp->op[i].rtn == BND_Fixup)
12143                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12144           jump_detection |= 2;
12145         else if ((dp->op[i].bytemode == cond_jump_mode)
12146                  || (dp->op[i].bytemode == loop_jcxz_mode))
12147           jump_detection |= 4;
12148       }
12149
12150     /* Determine if this is a jump or branch.  */
12151     if ((jump_detection & 0x3) == 0x3)
12152       {
12153         op_is_jump = TRUE;
12154         if (jump_detection & 0x4)
12155           the_info->insn_type = dis_condbranch;
12156         else
12157           the_info->insn_type =
12158             (dp->name && !strncmp(dp->name, "call", 4))
12159             ? dis_jsr : dis_branch;
12160       }
12161   }
12162
12163   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12164      are all 0s in inverted form.  */
12165   if (need_vex && vex.register_specifier != 0)
12166     {
12167       (*info->fprintf_func) (info->stream, "(bad)");
12168       return end_codep - priv.the_buffer;
12169     }
12170
12171   /* Check if the REX prefix is used.  */
12172   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12173     all_prefixes[last_rex_prefix] = 0;
12174
12175   /* Check if the SEG prefix is used.  */
12176   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12177                    | PREFIX_FS | PREFIX_GS)) != 0
12178       && (used_prefixes & active_seg_prefix) != 0)
12179     all_prefixes[last_seg_prefix] = 0;
12180
12181   /* Check if the ADDR prefix is used.  */
12182   if ((prefixes & PREFIX_ADDR) != 0
12183       && (used_prefixes & PREFIX_ADDR) != 0)
12184     all_prefixes[last_addr_prefix] = 0;
12185
12186   /* Check if the DATA prefix is used.  */
12187   if ((prefixes & PREFIX_DATA) != 0
12188       && (used_prefixes & PREFIX_DATA) != 0
12189       && !need_vex)
12190     all_prefixes[last_data_prefix] = 0;
12191
12192   /* Print the extra prefixes.  */
12193   prefix_length = 0;
12194   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12195     if (all_prefixes[i])
12196       {
12197         const char *name;
12198         name = prefix_name (all_prefixes[i], orig_sizeflag);
12199         if (name == NULL)
12200           abort ();
12201         prefix_length += strlen (name) + 1;
12202         (*info->fprintf_func) (info->stream, "%s ", name);
12203       }
12204
12205   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12206      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12207      used by putop and MMX/SSE operand and may be overriden by the
12208      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12209      separately.  */
12210   if (dp->prefix_requirement == PREFIX_OPCODE
12211       && (((need_vex
12212             ? vex.prefix == REPE_PREFIX_OPCODE
12213               || vex.prefix == REPNE_PREFIX_OPCODE
12214             : (prefixes
12215                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12216            && (used_prefixes
12217                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12218           || (((need_vex
12219                 ? vex.prefix == DATA_PREFIX_OPCODE
12220                 : ((prefixes
12221                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12222                    == PREFIX_DATA))
12223                && (used_prefixes & PREFIX_DATA) == 0))
12224           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12225     {
12226       (*info->fprintf_func) (info->stream, "(bad)");
12227       return end_codep - priv.the_buffer;
12228     }
12229
12230   /* Check maximum code length.  */
12231   if ((codep - start_codep) > MAX_CODE_LENGTH)
12232     {
12233       (*info->fprintf_func) (info->stream, "(bad)");
12234       return MAX_CODE_LENGTH;
12235     }
12236
12237   obufp = mnemonicendp;
12238   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12239     oappend (" ");
12240   oappend (" ");
12241   (*info->fprintf_func) (info->stream, "%s", obuf);
12242
12243   /* The enter and bound instructions are printed with operands in the same
12244      order as the intel book; everything else is printed in reverse order.  */
12245   if (intel_syntax || two_source_ops)
12246     {
12247       bfd_vma riprel;
12248
12249       for (i = 0; i < MAX_OPERANDS; ++i)
12250         op_txt[i] = op_out[i];
12251
12252       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12253           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12254         {
12255           op_txt[2] = op_out[3];
12256           op_txt[3] = op_out[2];
12257         }
12258
12259       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12260         {
12261           op_ad = op_index[i];
12262           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12263           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12264           riprel = op_riprel[i];
12265           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12266           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12267         }
12268     }
12269   else
12270     {
12271       for (i = 0; i < MAX_OPERANDS; ++i)
12272         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12273     }
12274
12275   needcomma = 0;
12276   for (i = 0; i < MAX_OPERANDS; ++i)
12277     if (*op_txt[i])
12278       {
12279         if (needcomma)
12280           (*info->fprintf_func) (info->stream, ",");
12281         if (op_index[i] != -1 && !op_riprel[i])
12282           {
12283             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12284
12285             if (the_info && op_is_jump)
12286               {
12287                 the_info->insn_info_valid = 1;
12288                 the_info->branch_delay_insns = 0;
12289                 the_info->data_size = 0;
12290                 the_info->target = target;
12291                 the_info->target2 = 0;
12292               }
12293             (*info->print_address_func) (target, info);
12294           }
12295         else
12296           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12297         needcomma = 1;
12298       }
12299
12300   for (i = 0; i < MAX_OPERANDS; i++)
12301     if (op_index[i] != -1 && op_riprel[i])
12302       {
12303         (*info->fprintf_func) (info->stream, "        # ");
12304         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12305                                                 + op_address[op_index[i]]), info);
12306         break;
12307       }
12308   return codep - priv.the_buffer;
12309 }
12310
12311 static const char *float_mem[] = {
12312   /* d8 */
12313   "fadd{s|}",
12314   "fmul{s|}",
12315   "fcom{s|}",
12316   "fcomp{s|}",
12317   "fsub{s|}",
12318   "fsubr{s|}",
12319   "fdiv{s|}",
12320   "fdivr{s|}",
12321   /* d9 */
12322   "fld{s|}",
12323   "(bad)",
12324   "fst{s|}",
12325   "fstp{s|}",
12326   "fldenvIC",
12327   "fldcw",
12328   "fNstenvIC",
12329   "fNstcw",
12330   /* da */
12331   "fiadd{l|}",
12332   "fimul{l|}",
12333   "ficom{l|}",
12334   "ficomp{l|}",
12335   "fisub{l|}",
12336   "fisubr{l|}",
12337   "fidiv{l|}",
12338   "fidivr{l|}",
12339   /* db */
12340   "fild{l|}",
12341   "fisttp{l|}",
12342   "fist{l|}",
12343   "fistp{l|}",
12344   "(bad)",
12345   "fld{t|}",
12346   "(bad)",
12347   "fstp{t|}",
12348   /* dc */
12349   "fadd{l|}",
12350   "fmul{l|}",
12351   "fcom{l|}",
12352   "fcomp{l|}",
12353   "fsub{l|}",
12354   "fsubr{l|}",
12355   "fdiv{l|}",
12356   "fdivr{l|}",
12357   /* dd */
12358   "fld{l|}",
12359   "fisttp{ll|}",
12360   "fst{l||}",
12361   "fstp{l|}",
12362   "frstorIC",
12363   "(bad)",
12364   "fNsaveIC",
12365   "fNstsw",
12366   /* de */
12367   "fiadd{s|}",
12368   "fimul{s|}",
12369   "ficom{s|}",
12370   "ficomp{s|}",
12371   "fisub{s|}",
12372   "fisubr{s|}",
12373   "fidiv{s|}",
12374   "fidivr{s|}",
12375   /* df */
12376   "fild{s|}",
12377   "fisttp{s|}",
12378   "fist{s|}",
12379   "fistp{s|}",
12380   "fbld",
12381   "fild{ll|}",
12382   "fbstp",
12383   "fistp{ll|}",
12384 };
12385
12386 static const unsigned char float_mem_mode[] = {
12387   /* d8 */
12388   d_mode,
12389   d_mode,
12390   d_mode,
12391   d_mode,
12392   d_mode,
12393   d_mode,
12394   d_mode,
12395   d_mode,
12396   /* d9 */
12397   d_mode,
12398   0,
12399   d_mode,
12400   d_mode,
12401   0,
12402   w_mode,
12403   0,
12404   w_mode,
12405   /* da */
12406   d_mode,
12407   d_mode,
12408   d_mode,
12409   d_mode,
12410   d_mode,
12411   d_mode,
12412   d_mode,
12413   d_mode,
12414   /* db */
12415   d_mode,
12416   d_mode,
12417   d_mode,
12418   d_mode,
12419   0,
12420   t_mode,
12421   0,
12422   t_mode,
12423   /* dc */
12424   q_mode,
12425   q_mode,
12426   q_mode,
12427   q_mode,
12428   q_mode,
12429   q_mode,
12430   q_mode,
12431   q_mode,
12432   /* dd */
12433   q_mode,
12434   q_mode,
12435   q_mode,
12436   q_mode,
12437   0,
12438   0,
12439   0,
12440   w_mode,
12441   /* de */
12442   w_mode,
12443   w_mode,
12444   w_mode,
12445   w_mode,
12446   w_mode,
12447   w_mode,
12448   w_mode,
12449   w_mode,
12450   /* df */
12451   w_mode,
12452   w_mode,
12453   w_mode,
12454   w_mode,
12455   t_mode,
12456   q_mode,
12457   t_mode,
12458   q_mode
12459 };
12460
12461 #define ST { OP_ST, 0 }
12462 #define STi { OP_STi, 0 }
12463
12464 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12465 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12466 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12467 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12468 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12469 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12470 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12471 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12472 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12473
12474 static const struct dis386 float_reg[][8] = {
12475   /* d8 */
12476   {
12477     { "fadd",   { ST, STi }, 0 },
12478     { "fmul",   { ST, STi }, 0 },
12479     { "fcom",   { STi }, 0 },
12480     { "fcomp",  { STi }, 0 },
12481     { "fsub",   { ST, STi }, 0 },
12482     { "fsubr",  { ST, STi }, 0 },
12483     { "fdiv",   { ST, STi }, 0 },
12484     { "fdivr",  { ST, STi }, 0 },
12485   },
12486   /* d9 */
12487   {
12488     { "fld",    { STi }, 0 },
12489     { "fxch",   { STi }, 0 },
12490     { FGRPd9_2 },
12491     { Bad_Opcode },
12492     { FGRPd9_4 },
12493     { FGRPd9_5 },
12494     { FGRPd9_6 },
12495     { FGRPd9_7 },
12496   },
12497   /* da */
12498   {
12499     { "fcmovb", { ST, STi }, 0 },
12500     { "fcmove", { ST, STi }, 0 },
12501     { "fcmovbe",{ ST, STi }, 0 },
12502     { "fcmovu", { ST, STi }, 0 },
12503     { Bad_Opcode },
12504     { FGRPda_5 },
12505     { Bad_Opcode },
12506     { Bad_Opcode },
12507   },
12508   /* db */
12509   {
12510     { "fcmovnb",{ ST, STi }, 0 },
12511     { "fcmovne",{ ST, STi }, 0 },
12512     { "fcmovnbe",{ ST, STi }, 0 },
12513     { "fcmovnu",{ ST, STi }, 0 },
12514     { FGRPdb_4 },
12515     { "fucomi", { ST, STi }, 0 },
12516     { "fcomi",  { ST, STi }, 0 },
12517     { Bad_Opcode },
12518   },
12519   /* dc */
12520   {
12521     { "fadd",   { STi, ST }, 0 },
12522     { "fmul",   { STi, ST }, 0 },
12523     { Bad_Opcode },
12524     { Bad_Opcode },
12525     { "fsub{!M|r}",     { STi, ST }, 0 },
12526     { "fsub{M|}",       { STi, ST }, 0 },
12527     { "fdiv{!M|r}",     { STi, ST }, 0 },
12528     { "fdiv{M|}",       { STi, ST }, 0 },
12529   },
12530   /* dd */
12531   {
12532     { "ffree",  { STi }, 0 },
12533     { Bad_Opcode },
12534     { "fst",    { STi }, 0 },
12535     { "fstp",   { STi }, 0 },
12536     { "fucom",  { STi }, 0 },
12537     { "fucomp", { STi }, 0 },
12538     { Bad_Opcode },
12539     { Bad_Opcode },
12540   },
12541   /* de */
12542   {
12543     { "faddp",  { STi, ST }, 0 },
12544     { "fmulp",  { STi, ST }, 0 },
12545     { Bad_Opcode },
12546     { FGRPde_3 },
12547     { "fsub{!M|r}p",    { STi, ST }, 0 },
12548     { "fsub{M|}p",      { STi, ST }, 0 },
12549     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12550     { "fdiv{M|}p",      { STi, ST }, 0 },
12551   },
12552   /* df */
12553   {
12554     { "ffreep", { STi }, 0 },
12555     { Bad_Opcode },
12556     { Bad_Opcode },
12557     { Bad_Opcode },
12558     { FGRPdf_4 },
12559     { "fucomip", { ST, STi }, 0 },
12560     { "fcomip", { ST, STi }, 0 },
12561     { Bad_Opcode },
12562   },
12563 };
12564
12565 static char *fgrps[][8] = {
12566   /* Bad opcode 0 */
12567   {
12568     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12569   },
12570
12571   /* d9_2  1 */
12572   {
12573     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12574   },
12575
12576   /* d9_4  2 */
12577   {
12578     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12579   },
12580
12581   /* d9_5  3 */
12582   {
12583     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12584   },
12585
12586   /* d9_6  4 */
12587   {
12588     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12589   },
12590
12591   /* d9_7  5 */
12592   {
12593     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12594   },
12595
12596   /* da_5  6 */
12597   {
12598     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12599   },
12600
12601   /* db_4  7 */
12602   {
12603     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12604     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12605   },
12606
12607   /* de_3  8 */
12608   {
12609     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12610   },
12611
12612   /* df_4  9 */
12613   {
12614     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12615   },
12616 };
12617
12618 static void
12619 swap_operand (void)
12620 {
12621   mnemonicendp[0] = '.';
12622   mnemonicendp[1] = 's';
12623   mnemonicendp += 2;
12624 }
12625
12626 static void
12627 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12628                int sizeflag ATTRIBUTE_UNUSED)
12629 {
12630   /* Skip mod/rm byte.  */
12631   MODRM_CHECK;
12632   codep++;
12633 }
12634
12635 static void
12636 dofloat (int sizeflag)
12637 {
12638   const struct dis386 *dp;
12639   unsigned char floatop;
12640
12641   floatop = codep[-1];
12642
12643   if (modrm.mod != 3)
12644     {
12645       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12646
12647       putop (float_mem[fp_indx], sizeflag);
12648       obufp = op_out[0];
12649       op_ad = 2;
12650       OP_E (float_mem_mode[fp_indx], sizeflag);
12651       return;
12652     }
12653   /* Skip mod/rm byte.  */
12654   MODRM_CHECK;
12655   codep++;
12656
12657   dp = &float_reg[floatop - 0xd8][modrm.reg];
12658   if (dp->name == NULL)
12659     {
12660       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12661
12662       /* Instruction fnstsw is only one with strange arg.  */
12663       if (floatop == 0xdf && codep[-1] == 0xe0)
12664         strcpy (op_out[0], names16[0]);
12665     }
12666   else
12667     {
12668       putop (dp->name, sizeflag);
12669
12670       obufp = op_out[0];
12671       op_ad = 2;
12672       if (dp->op[0].rtn)
12673         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12674
12675       obufp = op_out[1];
12676       op_ad = 1;
12677       if (dp->op[1].rtn)
12678         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12679     }
12680 }
12681
12682 /* Like oappend (below), but S is a string starting with '%'.
12683    In Intel syntax, the '%' is elided.  */
12684 static void
12685 oappend_maybe_intel (const char *s)
12686 {
12687   oappend (s + intel_syntax);
12688 }
12689
12690 static void
12691 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12692 {
12693   oappend_maybe_intel ("%st");
12694 }
12695
12696 static void
12697 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12698 {
12699   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12700   oappend_maybe_intel (scratchbuf);
12701 }
12702
12703 /* Capital letters in template are macros.  */
12704 static int
12705 putop (const char *in_template, int sizeflag)
12706 {
12707   const char *p;
12708   int alt = 0;
12709   int cond = 1;
12710   unsigned int l = 0, len = 1;
12711   char last[4];
12712
12713 #define SAVE_LAST(c)                    \
12714   if (l < len && l < sizeof (last))     \
12715     last[l++] = c;                      \
12716   else                                  \
12717     abort ();
12718
12719   for (p = in_template; *p; p++)
12720     {
12721       switch (*p)
12722         {
12723         default:
12724           *obufp++ = *p;
12725           break;
12726         case '%':
12727           len++;
12728           break;
12729         case '!':
12730           cond = 0;
12731           break;
12732         case '{':
12733           if (intel_syntax)
12734             {
12735               while (*++p != '|')
12736                 if (*p == '}' || *p == '\0')
12737                   abort ();
12738             }
12739           /* Fall through.  */
12740         case 'I':
12741           alt = 1;
12742           continue;
12743         case '|':
12744           while (*++p != '}')
12745             {
12746               if (*p == '\0')
12747                 abort ();
12748             }
12749           break;
12750         case '}':
12751           break;
12752         case 'A':
12753           if (intel_syntax)
12754             break;
12755           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12756             *obufp++ = 'b';
12757           break;
12758         case 'B':
12759           if (l == 0 && len == 1)
12760             {
12761             case_B:
12762               if (intel_syntax)
12763                 break;
12764               if (sizeflag & SUFFIX_ALWAYS)
12765                 *obufp++ = 'b';
12766             }
12767           else
12768             {
12769               if (l != 1
12770                   || len != 2
12771                   || last[0] != 'L')
12772                 {
12773                   SAVE_LAST (*p);
12774                   break;
12775                 }
12776
12777               if (address_mode == mode_64bit
12778                   && !(prefixes & PREFIX_ADDR))
12779                 {
12780                   *obufp++ = 'a';
12781                   *obufp++ = 'b';
12782                   *obufp++ = 's';
12783                 }
12784
12785               goto case_B;
12786             }
12787           break;
12788         case 'C':
12789           if (intel_syntax && !alt)
12790             break;
12791           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12792             {
12793               if (sizeflag & DFLAG)
12794                 *obufp++ = intel_syntax ? 'd' : 'l';
12795               else
12796                 *obufp++ = intel_syntax ? 'w' : 's';
12797               used_prefixes |= (prefixes & PREFIX_DATA);
12798             }
12799           break;
12800         case 'D':
12801           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12802             break;
12803           USED_REX (REX_W);
12804           if (modrm.mod == 3)
12805             {
12806               if (rex & REX_W)
12807                 *obufp++ = 'q';
12808               else
12809                 {
12810                   if (sizeflag & DFLAG)
12811                     *obufp++ = intel_syntax ? 'd' : 'l';
12812                   else
12813                     *obufp++ = 'w';
12814                   used_prefixes |= (prefixes & PREFIX_DATA);
12815                 }
12816             }
12817           else
12818             *obufp++ = 'w';
12819           break;
12820         case 'E':               /* For jcxz/jecxz */
12821           if (address_mode == mode_64bit)
12822             {
12823               if (sizeflag & AFLAG)
12824                 *obufp++ = 'r';
12825               else
12826                 *obufp++ = 'e';
12827             }
12828           else
12829             if (sizeflag & AFLAG)
12830               *obufp++ = 'e';
12831           used_prefixes |= (prefixes & PREFIX_ADDR);
12832           break;
12833         case 'F':
12834           if (intel_syntax)
12835             break;
12836           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12837             {
12838               if (sizeflag & AFLAG)
12839                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12840               else
12841                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12842               used_prefixes |= (prefixes & PREFIX_ADDR);
12843             }
12844           break;
12845         case 'G':
12846           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12847             break;
12848           if ((rex & REX_W) || (sizeflag & DFLAG))
12849             *obufp++ = 'l';
12850           else
12851             *obufp++ = 'w';
12852           if (!(rex & REX_W))
12853             used_prefixes |= (prefixes & PREFIX_DATA);
12854           break;
12855         case 'H':
12856           if (intel_syntax)
12857             break;
12858           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12859               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12860             {
12861               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12862               *obufp++ = ',';
12863               *obufp++ = 'p';
12864               if (prefixes & PREFIX_DS)
12865                 *obufp++ = 't';
12866               else
12867                 *obufp++ = 'n';
12868             }
12869           break;
12870         case 'K':
12871           USED_REX (REX_W);
12872           if (rex & REX_W)
12873             *obufp++ = 'q';
12874           else
12875             *obufp++ = 'd';
12876           break;
12877         case 'Z':
12878           if (l != 0 || len != 1)
12879             {
12880               if (l != 1 || len != 2 || last[0] != 'X')
12881                 {
12882                   SAVE_LAST (*p);
12883                   break;
12884                 }
12885               if (!need_vex || !vex.evex)
12886                 abort ();
12887               if (intel_syntax
12888                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12889                 break;
12890               switch (vex.length)
12891                 {
12892                 case 128:
12893                   *obufp++ = 'x';
12894                   break;
12895                 case 256:
12896                   *obufp++ = 'y';
12897                   break;
12898                 case 512:
12899                   *obufp++ = 'z';
12900                   break;
12901                 default:
12902                   abort ();
12903                 }
12904               break;
12905             }
12906           if (intel_syntax)
12907             break;
12908           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12909             {
12910               *obufp++ = 'q';
12911               break;
12912             }
12913           /* Fall through.  */
12914           goto case_L;
12915         case 'L':
12916           if (l != 0 || len != 1)
12917             {
12918               SAVE_LAST (*p);
12919               break;
12920             }
12921         case_L:
12922           if (intel_syntax)
12923             break;
12924           if (sizeflag & SUFFIX_ALWAYS)
12925             *obufp++ = 'l';
12926           break;
12927         case 'M':
12928           if (intel_mnemonic != cond)
12929             *obufp++ = 'r';
12930           break;
12931         case 'N':
12932           if ((prefixes & PREFIX_FWAIT) == 0)
12933             *obufp++ = 'n';
12934           else
12935             used_prefixes |= PREFIX_FWAIT;
12936           break;
12937         case 'O':
12938           USED_REX (REX_W);
12939           if (rex & REX_W)
12940             *obufp++ = 'o';
12941           else if (intel_syntax && (sizeflag & DFLAG))
12942             *obufp++ = 'q';
12943           else
12944             *obufp++ = 'd';
12945           if (!(rex & REX_W))
12946             used_prefixes |= (prefixes & PREFIX_DATA);
12947           break;
12948         case '&':
12949           if (!intel_syntax
12950               && address_mode == mode_64bit
12951               && isa64 == intel64)
12952             {
12953               *obufp++ = 'q';
12954               break;
12955             }
12956           /* Fall through.  */
12957         case 'T':
12958           if (!intel_syntax
12959               && address_mode == mode_64bit
12960               && ((sizeflag & DFLAG) || (rex & REX_W)))
12961             {
12962               *obufp++ = 'q';
12963               break;
12964             }
12965           /* Fall through.  */
12966           goto case_P;
12967         case 'P':
12968           if (l == 0 && len == 1)
12969             {
12970             case_P:
12971               if (intel_syntax)
12972                 {
12973                   if ((rex & REX_W) == 0
12974                       && (prefixes & PREFIX_DATA))
12975                     {
12976                       if ((sizeflag & DFLAG) == 0)
12977                         *obufp++ = 'w';
12978                       used_prefixes |= (prefixes & PREFIX_DATA);
12979                     }
12980                   break;
12981                 }
12982               if ((prefixes & PREFIX_DATA)
12983                   || (rex & REX_W)
12984                   || (sizeflag & SUFFIX_ALWAYS))
12985                 {
12986                   USED_REX (REX_W);
12987                   if (rex & REX_W)
12988                     *obufp++ = 'q';
12989                   else
12990                     {
12991                       if (sizeflag & DFLAG)
12992                         *obufp++ = 'l';
12993                       else
12994                         *obufp++ = 'w';
12995                       used_prefixes |= (prefixes & PREFIX_DATA);
12996                     }
12997                 }
12998             }
12999           else
13000             {
13001               if (l != 1 || len != 2 || last[0] != 'L')
13002                 {
13003                   SAVE_LAST (*p);
13004                   break;
13005                 }
13006
13007               if ((prefixes & PREFIX_DATA)
13008                   || (rex & REX_W)
13009                   || (sizeflag & SUFFIX_ALWAYS))
13010                 {
13011                   USED_REX (REX_W);
13012                   if (rex & REX_W)
13013                     *obufp++ = 'q';
13014                   else
13015                     {
13016                       if (sizeflag & DFLAG)
13017                         *obufp++ = intel_syntax ? 'd' : 'l';
13018                       else
13019                         *obufp++ = 'w';
13020                       used_prefixes |= (prefixes & PREFIX_DATA);
13021                     }
13022                 }
13023             }
13024           break;
13025         case 'U':
13026           if (intel_syntax)
13027             break;
13028           if (address_mode == mode_64bit
13029               && ((sizeflag & DFLAG) || (rex & REX_W)))
13030             {
13031               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13032                 *obufp++ = 'q';
13033               break;
13034             }
13035           /* Fall through.  */
13036           goto case_Q;
13037         case 'Q':
13038           if (l == 0 && len == 1)
13039             {
13040             case_Q:
13041               if (intel_syntax && !alt)
13042                 break;
13043               USED_REX (REX_W);
13044               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13045                 {
13046                   if (rex & REX_W)
13047                     *obufp++ = 'q';
13048                   else
13049                     {
13050                       if (sizeflag & DFLAG)
13051                         *obufp++ = intel_syntax ? 'd' : 'l';
13052                       else
13053                         *obufp++ = 'w';
13054                       used_prefixes |= (prefixes & PREFIX_DATA);
13055                     }
13056                 }
13057             }
13058           else
13059             {
13060               if (l != 1 || len != 2 || last[0] != 'L')
13061                 {
13062                   SAVE_LAST (*p);
13063                   break;
13064                 }
13065               if ((intel_syntax && need_modrm)
13066                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13067                 break;
13068               if ((rex & REX_W))
13069                 {
13070                   USED_REX (REX_W);
13071                   *obufp++ = 'q';
13072                 }
13073               else if((address_mode == mode_64bit && need_modrm)
13074                       || (sizeflag & SUFFIX_ALWAYS))
13075                 *obufp++ = intel_syntax? 'd' : 'l';
13076             }
13077           break;
13078         case 'R':
13079           USED_REX (REX_W);
13080           if (rex & REX_W)
13081             *obufp++ = 'q';
13082           else if (sizeflag & DFLAG)
13083             {
13084               if (intel_syntax)
13085                   *obufp++ = 'd';
13086               else
13087                   *obufp++ = 'l';
13088             }
13089           else
13090             *obufp++ = 'w';
13091           if (intel_syntax && !p[1]
13092               && ((rex & REX_W) || (sizeflag & DFLAG)))
13093             *obufp++ = 'e';
13094           if (!(rex & REX_W))
13095             used_prefixes |= (prefixes & PREFIX_DATA);
13096           break;
13097         case 'V':
13098           if (l == 0 && len == 1)
13099             {
13100               if (intel_syntax)
13101                 break;
13102               if (address_mode == mode_64bit
13103                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13104                 {
13105                   if (sizeflag & SUFFIX_ALWAYS)
13106                     *obufp++ = 'q';
13107                   break;
13108                 }
13109             }
13110           else
13111             {
13112               if (l != 1
13113                   || len != 2
13114                   || last[0] != 'L')
13115                 {
13116                   SAVE_LAST (*p);
13117                   break;
13118                 }
13119
13120               if (rex & REX_W)
13121                 {
13122                   *obufp++ = 'a';
13123                   *obufp++ = 'b';
13124                   *obufp++ = 's';
13125                 }
13126             }
13127           /* Fall through.  */
13128           goto case_S;
13129         case 'S':
13130           if (l == 0 && len == 1)
13131             {
13132             case_S:
13133               if (intel_syntax)
13134                 break;
13135               if (sizeflag & SUFFIX_ALWAYS)
13136                 {
13137                   if (rex & REX_W)
13138                     *obufp++ = 'q';
13139                   else
13140                     {
13141                       if (sizeflag & DFLAG)
13142                         *obufp++ = 'l';
13143                       else
13144                         *obufp++ = 'w';
13145                       used_prefixes |= (prefixes & PREFIX_DATA);
13146                     }
13147                 }
13148             }
13149           else
13150             {
13151               if (l != 1
13152                   || len != 2
13153                   || last[0] != 'L')
13154                 {
13155                   SAVE_LAST (*p);
13156                   break;
13157                 }
13158
13159               if (address_mode == mode_64bit
13160                   && !(prefixes & PREFIX_ADDR))
13161                 {
13162                   *obufp++ = 'a';
13163                   *obufp++ = 'b';
13164                   *obufp++ = 's';
13165                 }
13166
13167               goto case_S;
13168             }
13169           break;
13170         case 'X':
13171           if (l != 0 || len != 1)
13172             {
13173               SAVE_LAST (*p);
13174               break;
13175             }
13176           if (need_vex
13177               ? vex.prefix == DATA_PREFIX_OPCODE
13178               : prefixes & PREFIX_DATA)
13179             {
13180               *obufp++ = 'd';
13181               used_prefixes |= PREFIX_DATA;
13182             }
13183           else
13184             *obufp++ = 's';
13185           break;
13186         case 'Y':
13187           if (l == 0 && len == 1)
13188             abort ();
13189           else
13190             {
13191               if (l != 1 || len != 2 || last[0] != 'X')
13192                 {
13193                   SAVE_LAST (*p);
13194                   break;
13195                 }
13196               if (!need_vex)
13197                 abort ();
13198               if (intel_syntax
13199                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13200                 break;
13201               switch (vex.length)
13202                 {
13203                 case 128:
13204                   *obufp++ = 'x';
13205                   break;
13206                 case 256:
13207                   *obufp++ = 'y';
13208                   break;
13209                 case 512:
13210                   if (!vex.evex)
13211                 default:
13212                     abort ();
13213                 }
13214             }
13215           break;
13216         case 'W':
13217           if (l == 0 && len == 1)
13218             {
13219               /* operand size flag for cwtl, cbtw */
13220               USED_REX (REX_W);
13221               if (rex & REX_W)
13222                 {
13223                   if (intel_syntax)
13224                     *obufp++ = 'd';
13225                   else
13226                     *obufp++ = 'l';
13227                 }
13228               else if (sizeflag & DFLAG)
13229                 *obufp++ = 'w';
13230               else
13231                 *obufp++ = 'b';
13232               if (!(rex & REX_W))
13233                 used_prefixes |= (prefixes & PREFIX_DATA);
13234             }
13235           else
13236             {
13237               if (l != 1
13238                   || len != 2
13239                   || (last[0] != 'X'
13240                       && last[0] != 'L'))
13241                 {
13242                   SAVE_LAST (*p);
13243                   break;
13244                 }
13245               if (!need_vex)
13246                 abort ();
13247               if (last[0] == 'X')
13248                 *obufp++ = vex.w ? 'd': 's';
13249               else
13250                 *obufp++ = vex.w ? 'q': 'd';
13251             }
13252           break;
13253         case '^':
13254           if (intel_syntax)
13255             break;
13256           if (isa64 == intel64 && (rex & REX_W))
13257             {
13258               USED_REX (REX_W);
13259               *obufp++ = 'q';
13260               break;
13261             }
13262           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13263             {
13264               if (sizeflag & DFLAG)
13265                 *obufp++ = 'l';
13266               else
13267                 *obufp++ = 'w';
13268               used_prefixes |= (prefixes & PREFIX_DATA);
13269             }
13270           break;
13271         case '@':
13272           if (intel_syntax)
13273             break;
13274           if (address_mode == mode_64bit
13275               && (isa64 == intel64
13276                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13277               *obufp++ = 'q';
13278           else if ((prefixes & PREFIX_DATA))
13279             {
13280               if (!(sizeflag & DFLAG))
13281                 *obufp++ = 'w';
13282               used_prefixes |= (prefixes & PREFIX_DATA);
13283             }
13284           break;
13285         }
13286       alt = 0;
13287     }
13288   *obufp = 0;
13289   mnemonicendp = obufp;
13290   return 0;
13291 }
13292
13293 static void
13294 oappend (const char *s)
13295 {
13296   obufp = stpcpy (obufp, s);
13297 }
13298
13299 static void
13300 append_seg (void)
13301 {
13302   /* Only print the active segment register.  */
13303   if (!active_seg_prefix)
13304     return;
13305
13306   used_prefixes |= active_seg_prefix;
13307   switch (active_seg_prefix)
13308     {
13309     case PREFIX_CS:
13310       oappend_maybe_intel ("%cs:");
13311       break;
13312     case PREFIX_DS:
13313       oappend_maybe_intel ("%ds:");
13314       break;
13315     case PREFIX_SS:
13316       oappend_maybe_intel ("%ss:");
13317       break;
13318     case PREFIX_ES:
13319       oappend_maybe_intel ("%es:");
13320       break;
13321     case PREFIX_FS:
13322       oappend_maybe_intel ("%fs:");
13323       break;
13324     case PREFIX_GS:
13325       oappend_maybe_intel ("%gs:");
13326       break;
13327     default:
13328       break;
13329     }
13330 }
13331
13332 static void
13333 OP_indirE (int bytemode, int sizeflag)
13334 {
13335   if (!intel_syntax)
13336     oappend ("*");
13337   OP_E (bytemode, sizeflag);
13338 }
13339
13340 static void
13341 print_operand_value (char *buf, int hex, bfd_vma disp)
13342 {
13343   if (address_mode == mode_64bit)
13344     {
13345       if (hex)
13346         {
13347           char tmp[30];
13348           int i;
13349           buf[0] = '0';
13350           buf[1] = 'x';
13351           sprintf_vma (tmp, disp);
13352           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13353           strcpy (buf + 2, tmp + i);
13354         }
13355       else
13356         {
13357           bfd_signed_vma v = disp;
13358           char tmp[30];
13359           int i;
13360           if (v < 0)
13361             {
13362               *(buf++) = '-';
13363               v = -disp;
13364               /* Check for possible overflow on 0x8000000000000000.  */
13365               if (v < 0)
13366                 {
13367                   strcpy (buf, "9223372036854775808");
13368                   return;
13369                 }
13370             }
13371           if (!v)
13372             {
13373               strcpy (buf, "0");
13374               return;
13375             }
13376
13377           i = 0;
13378           tmp[29] = 0;
13379           while (v)
13380             {
13381               tmp[28 - i] = (v % 10) + '0';
13382               v /= 10;
13383               i++;
13384             }
13385           strcpy (buf, tmp + 29 - i);
13386         }
13387     }
13388   else
13389     {
13390       if (hex)
13391         sprintf (buf, "0x%x", (unsigned int) disp);
13392       else
13393         sprintf (buf, "%d", (int) disp);
13394     }
13395 }
13396
13397 /* Put DISP in BUF as signed hex number.  */
13398
13399 static void
13400 print_displacement (char *buf, bfd_vma disp)
13401 {
13402   bfd_signed_vma val = disp;
13403   char tmp[30];
13404   int i, j = 0;
13405
13406   if (val < 0)
13407     {
13408       buf[j++] = '-';
13409       val = -disp;
13410
13411       /* Check for possible overflow.  */
13412       if (val < 0)
13413         {
13414           switch (address_mode)
13415             {
13416             case mode_64bit:
13417               strcpy (buf + j, "0x8000000000000000");
13418               break;
13419             case mode_32bit:
13420               strcpy (buf + j, "0x80000000");
13421               break;
13422             case mode_16bit:
13423               strcpy (buf + j, "0x8000");
13424               break;
13425             }
13426           return;
13427         }
13428     }
13429
13430   buf[j++] = '0';
13431   buf[j++] = 'x';
13432
13433   sprintf_vma (tmp, (bfd_vma) val);
13434   for (i = 0; tmp[i] == '0'; i++)
13435     continue;
13436   if (tmp[i] == '\0')
13437     i--;
13438   strcpy (buf + j, tmp + i);
13439 }
13440
13441 static void
13442 intel_operand_size (int bytemode, int sizeflag)
13443 {
13444   if (vex.evex
13445       && vex.b
13446       && (bytemode == x_mode
13447           || bytemode == evex_half_bcst_xmmq_mode))
13448     {
13449       if (vex.w)
13450         oappend ("QWORD PTR ");
13451       else
13452         oappend ("DWORD PTR ");
13453       return;
13454     }
13455   switch (bytemode)
13456     {
13457     case b_mode:
13458     case b_swap_mode:
13459     case dqb_mode:
13460     case db_mode:
13461       oappend ("BYTE PTR ");
13462       break;
13463     case w_mode:
13464     case dw_mode:
13465     case dqw_mode:
13466       oappend ("WORD PTR ");
13467       break;
13468     case indir_v_mode:
13469       if (address_mode == mode_64bit && isa64 == intel64)
13470         {
13471           oappend ("QWORD PTR ");
13472           break;
13473         }
13474       /* Fall through.  */
13475     case stack_v_mode:
13476       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13477         {
13478           oappend ("QWORD PTR ");
13479           break;
13480         }
13481       /* Fall through.  */
13482     case v_mode:
13483     case v_swap_mode:
13484     case dq_mode:
13485       USED_REX (REX_W);
13486       if (rex & REX_W)
13487         oappend ("QWORD PTR ");
13488       else
13489         {
13490           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13491             oappend ("DWORD PTR ");
13492           else
13493             oappend ("WORD PTR ");
13494           used_prefixes |= (prefixes & PREFIX_DATA);
13495         }
13496       break;
13497     case z_mode:
13498       if ((rex & REX_W) || (sizeflag & DFLAG))
13499         *obufp++ = 'D';
13500       oappend ("WORD PTR ");
13501       if (!(rex & REX_W))
13502         used_prefixes |= (prefixes & PREFIX_DATA);
13503       break;
13504     case a_mode:
13505       if (sizeflag & DFLAG)
13506         oappend ("QWORD PTR ");
13507       else
13508         oappend ("DWORD PTR ");
13509       used_prefixes |= (prefixes & PREFIX_DATA);
13510       break;
13511     case movsxd_mode:
13512       if (!(sizeflag & DFLAG) && isa64 == intel64)
13513         oappend ("WORD PTR ");
13514       else
13515         oappend ("DWORD PTR ");
13516       used_prefixes |= (prefixes & PREFIX_DATA);
13517       break;
13518     case d_mode:
13519     case d_scalar_mode:
13520     case d_scalar_swap_mode:
13521     case d_swap_mode:
13522     case dqd_mode:
13523       oappend ("DWORD PTR ");
13524       break;
13525     case q_mode:
13526     case q_scalar_mode:
13527     case q_scalar_swap_mode:
13528     case q_swap_mode:
13529       oappend ("QWORD PTR ");
13530       break;
13531     case m_mode:
13532       if (address_mode == mode_64bit)
13533         oappend ("QWORD PTR ");
13534       else
13535         oappend ("DWORD PTR ");
13536       break;
13537     case f_mode:
13538       if (sizeflag & DFLAG)
13539         oappend ("FWORD PTR ");
13540       else
13541         oappend ("DWORD PTR ");
13542       used_prefixes |= (prefixes & PREFIX_DATA);
13543       break;
13544     case t_mode:
13545       oappend ("TBYTE PTR ");
13546       break;
13547     case x_mode:
13548     case x_swap_mode:
13549     case evex_x_gscat_mode:
13550     case evex_x_nobcst_mode:
13551     case b_scalar_mode:
13552     case w_scalar_mode:
13553       if (need_vex)
13554         {
13555           switch (vex.length)
13556             {
13557             case 128:
13558               oappend ("XMMWORD PTR ");
13559               break;
13560             case 256:
13561               oappend ("YMMWORD PTR ");
13562               break;
13563             case 512:
13564               oappend ("ZMMWORD PTR ");
13565               break;
13566             default:
13567               abort ();
13568             }
13569         }
13570       else
13571         oappend ("XMMWORD PTR ");
13572       break;
13573     case xmm_mode:
13574       oappend ("XMMWORD PTR ");
13575       break;
13576     case ymm_mode:
13577       oappend ("YMMWORD PTR ");
13578       break;
13579     case xmmq_mode:
13580     case evex_half_bcst_xmmq_mode:
13581       if (!need_vex)
13582         abort ();
13583
13584       switch (vex.length)
13585         {
13586         case 128:
13587           oappend ("QWORD PTR ");
13588           break;
13589         case 256:
13590           oappend ("XMMWORD PTR ");
13591           break;
13592         case 512:
13593           oappend ("YMMWORD PTR ");
13594           break;
13595         default:
13596           abort ();
13597         }
13598       break;
13599     case xmm_mb_mode:
13600       if (!need_vex)
13601         abort ();
13602
13603       switch (vex.length)
13604         {
13605         case 128:
13606         case 256:
13607         case 512:
13608           oappend ("BYTE PTR ");
13609           break;
13610         default:
13611           abort ();
13612         }
13613       break;
13614     case xmm_mw_mode:
13615       if (!need_vex)
13616         abort ();
13617
13618       switch (vex.length)
13619         {
13620         case 128:
13621         case 256:
13622         case 512:
13623           oappend ("WORD PTR ");
13624           break;
13625         default:
13626           abort ();
13627         }
13628       break;
13629     case xmm_md_mode:
13630       if (!need_vex)
13631         abort ();
13632
13633       switch (vex.length)
13634         {
13635         case 128:
13636         case 256:
13637         case 512:
13638           oappend ("DWORD PTR ");
13639           break;
13640         default:
13641           abort ();
13642         }
13643       break;
13644     case xmm_mq_mode:
13645       if (!need_vex)
13646         abort ();
13647
13648       switch (vex.length)
13649         {
13650         case 128:
13651         case 256:
13652         case 512:
13653           oappend ("QWORD PTR ");
13654           break;
13655         default:
13656           abort ();
13657         }
13658       break;
13659     case xmmdw_mode:
13660       if (!need_vex)
13661         abort ();
13662
13663       switch (vex.length)
13664         {
13665         case 128:
13666           oappend ("WORD PTR ");
13667           break;
13668         case 256:
13669           oappend ("DWORD PTR ");
13670           break;
13671         case 512:
13672           oappend ("QWORD PTR ");
13673           break;
13674         default:
13675           abort ();
13676         }
13677       break;
13678     case xmmqd_mode:
13679       if (!need_vex)
13680         abort ();
13681
13682       switch (vex.length)
13683         {
13684         case 128:
13685           oappend ("DWORD PTR ");
13686           break;
13687         case 256:
13688           oappend ("QWORD PTR ");
13689           break;
13690         case 512:
13691           oappend ("XMMWORD PTR ");
13692           break;
13693         default:
13694           abort ();
13695         }
13696       break;
13697     case ymmq_mode:
13698       if (!need_vex)
13699         abort ();
13700
13701       switch (vex.length)
13702         {
13703         case 128:
13704           oappend ("QWORD PTR ");
13705           break;
13706         case 256:
13707           oappend ("YMMWORD PTR ");
13708           break;
13709         case 512:
13710           oappend ("ZMMWORD PTR ");
13711           break;
13712         default:
13713           abort ();
13714         }
13715       break;
13716     case ymmxmm_mode:
13717       if (!need_vex)
13718         abort ();
13719
13720       switch (vex.length)
13721         {
13722         case 128:
13723         case 256:
13724           oappend ("XMMWORD PTR ");
13725           break;
13726         default:
13727           abort ();
13728         }
13729       break;
13730     case o_mode:
13731       oappend ("OWORD PTR ");
13732       break;
13733     case vex_scalar_w_dq_mode:
13734       if (!need_vex)
13735         abort ();
13736
13737       if (vex.w)
13738         oappend ("QWORD PTR ");
13739       else
13740         oappend ("DWORD PTR ");
13741       break;
13742     case vex_vsib_d_w_dq_mode:
13743     case vex_vsib_q_w_dq_mode:
13744       if (!need_vex)
13745         abort ();
13746
13747       if (!vex.evex)
13748         {
13749           if (vex.w)
13750             oappend ("QWORD PTR ");
13751           else
13752             oappend ("DWORD PTR ");
13753         }
13754       else
13755         {
13756           switch (vex.length)
13757             {
13758             case 128:
13759               oappend ("XMMWORD PTR ");
13760               break;
13761             case 256:
13762               oappend ("YMMWORD PTR ");
13763               break;
13764             case 512:
13765               oappend ("ZMMWORD PTR ");
13766               break;
13767             default:
13768               abort ();
13769             }
13770         }
13771       break;
13772     case vex_vsib_q_w_d_mode:
13773     case vex_vsib_d_w_d_mode:
13774       if (!need_vex || !vex.evex)
13775         abort ();
13776
13777       switch (vex.length)
13778         {
13779         case 128:
13780           oappend ("QWORD PTR ");
13781           break;
13782         case 256:
13783           oappend ("XMMWORD PTR ");
13784           break;
13785         case 512:
13786           oappend ("YMMWORD PTR ");
13787           break;
13788         default:
13789           abort ();
13790         }
13791
13792       break;
13793     case mask_bd_mode:
13794       if (!need_vex || vex.length != 128)
13795         abort ();
13796       if (vex.w)
13797         oappend ("DWORD PTR ");
13798       else
13799         oappend ("BYTE PTR ");
13800       break;
13801     case mask_mode:
13802       if (!need_vex)
13803         abort ();
13804       if (vex.w)
13805         oappend ("QWORD PTR ");
13806       else
13807         oappend ("WORD PTR ");
13808       break;
13809     case v_bnd_mode:
13810     case v_bndmk_mode:
13811     default:
13812       break;
13813     }
13814 }
13815
13816 static void
13817 OP_E_register (int bytemode, int sizeflag)
13818 {
13819   int reg = modrm.rm;
13820   const char **names;
13821
13822   USED_REX (REX_B);
13823   if ((rex & REX_B))
13824     reg += 8;
13825
13826   if ((sizeflag & SUFFIX_ALWAYS)
13827       && (bytemode == b_swap_mode
13828           || bytemode == bnd_swap_mode
13829           || bytemode == v_swap_mode))
13830     swap_operand ();
13831
13832   switch (bytemode)
13833     {
13834     case b_mode:
13835     case b_swap_mode:
13836       USED_REX (0);
13837       if (rex)
13838         names = names8rex;
13839       else
13840         names = names8;
13841       break;
13842     case w_mode:
13843       names = names16;
13844       break;
13845     case d_mode:
13846     case dw_mode:
13847     case db_mode:
13848       names = names32;
13849       break;
13850     case q_mode:
13851       names = names64;
13852       break;
13853     case m_mode:
13854     case v_bnd_mode:
13855       names = address_mode == mode_64bit ? names64 : names32;
13856       break;
13857     case bnd_mode:
13858     case bnd_swap_mode:
13859       if (reg > 0x3)
13860         {
13861           oappend ("(bad)");
13862           return;
13863         }
13864       names = names_bnd;
13865       break;
13866     case indir_v_mode:
13867       if (address_mode == mode_64bit && isa64 == intel64)
13868         {
13869           names = names64;
13870           break;
13871         }
13872       /* Fall through.  */
13873     case stack_v_mode:
13874       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13875         {
13876           names = names64;
13877           break;
13878         }
13879       bytemode = v_mode;
13880       /* Fall through.  */
13881     case v_mode:
13882     case v_swap_mode:
13883     case dq_mode:
13884     case dqb_mode:
13885     case dqd_mode:
13886     case dqw_mode:
13887       USED_REX (REX_W);
13888       if (rex & REX_W)
13889         names = names64;
13890       else
13891         {
13892           if ((sizeflag & DFLAG)
13893               || (bytemode != v_mode
13894                   && bytemode != v_swap_mode))
13895             names = names32;
13896           else
13897             names = names16;
13898           used_prefixes |= (prefixes & PREFIX_DATA);
13899         }
13900       break;
13901     case movsxd_mode:
13902       if (!(sizeflag & DFLAG) && isa64 == intel64)
13903         names = names16;
13904       else
13905         names = names32;
13906       used_prefixes |= (prefixes & PREFIX_DATA);
13907       break;
13908     case va_mode:
13909       names = (address_mode == mode_64bit
13910                ? names64 : names32);
13911       if (!(prefixes & PREFIX_ADDR))
13912         names = (address_mode == mode_16bit
13913                      ? names16 : names);
13914       else
13915         {
13916           /* Remove "addr16/addr32".  */
13917           all_prefixes[last_addr_prefix] = 0;
13918           names = (address_mode != mode_32bit
13919                        ? names32 : names16);
13920           used_prefixes |= PREFIX_ADDR;
13921         }
13922       break;
13923     case mask_bd_mode:
13924     case mask_mode:
13925       if (reg > 0x7)
13926         {
13927           oappend ("(bad)");
13928           return;
13929         }
13930       names = names_mask;
13931       break;
13932     case 0:
13933       return;
13934     default:
13935       oappend (INTERNAL_DISASSEMBLER_ERROR);
13936       return;
13937     }
13938   oappend (names[reg]);
13939 }
13940
13941 static void
13942 OP_E_memory (int bytemode, int sizeflag)
13943 {
13944   bfd_vma disp = 0;
13945   int add = (rex & REX_B) ? 8 : 0;
13946   int riprel = 0;
13947   int shift;
13948
13949   if (vex.evex)
13950     {
13951       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13952       if (vex.b
13953           && bytemode != x_mode
13954           && bytemode != xmmq_mode
13955           && bytemode != evex_half_bcst_xmmq_mode)
13956         {
13957           BadOp ();
13958           return;
13959         }
13960       switch (bytemode)
13961         {
13962         case dqw_mode:
13963         case dw_mode:
13964           shift = 1;
13965           break;
13966         case dqb_mode:
13967         case db_mode:
13968           shift = 0;
13969           break;
13970         case dq_mode:
13971           if (address_mode != mode_64bit)
13972             {
13973               shift = 2;
13974               break;
13975             }
13976             /* fall through */
13977         case vex_scalar_w_dq_mode:
13978         case vex_vsib_d_w_dq_mode:
13979         case vex_vsib_d_w_d_mode:
13980         case vex_vsib_q_w_dq_mode:
13981         case vex_vsib_q_w_d_mode:
13982         case evex_x_gscat_mode:
13983           shift = vex.w ? 3 : 2;
13984           break;
13985         case x_mode:
13986         case evex_half_bcst_xmmq_mode:
13987         case xmmq_mode:
13988           if (vex.b)
13989             {
13990               shift = vex.w ? 3 : 2;
13991               break;
13992             }
13993           /* Fall through.  */
13994         case xmmqd_mode:
13995         case xmmdw_mode:
13996         case ymmq_mode:
13997         case evex_x_nobcst_mode:
13998         case x_swap_mode:
13999           switch (vex.length)
14000             {
14001             case 128:
14002               shift = 4;
14003               break;
14004             case 256:
14005               shift = 5;
14006               break;
14007             case 512:
14008               shift = 6;
14009               break;
14010             default:
14011               abort ();
14012             }
14013           break;
14014         case ymm_mode:
14015           shift = 5;
14016           break;
14017         case xmm_mode:
14018           shift = 4;
14019           break;
14020         case xmm_mq_mode:
14021         case q_mode:
14022         case q_scalar_mode:
14023         case q_swap_mode:
14024         case q_scalar_swap_mode:
14025           shift = 3;
14026           break;
14027         case dqd_mode:
14028         case xmm_md_mode:
14029         case d_mode:
14030         case d_scalar_mode:
14031         case d_swap_mode:
14032         case d_scalar_swap_mode:
14033           shift = 2;
14034           break;
14035         case w_scalar_mode:
14036         case xmm_mw_mode:
14037           shift = 1;
14038           break;
14039         case b_scalar_mode:
14040         case xmm_mb_mode:
14041           shift = 0;
14042           break;
14043         default:
14044           abort ();
14045         }
14046       /* Make necessary corrections to shift for modes that need it.
14047          For these modes we currently have shift 4, 5 or 6 depending on
14048          vex.length (it corresponds to xmmword, ymmword or zmmword
14049          operand).  We might want to make it 3, 4 or 5 (e.g. for
14050          xmmq_mode).  In case of broadcast enabled the corrections
14051          aren't needed, as element size is always 32 or 64 bits.  */
14052       if (!vex.b
14053           && (bytemode == xmmq_mode
14054               || bytemode == evex_half_bcst_xmmq_mode))
14055         shift -= 1;
14056       else if (bytemode == xmmqd_mode)
14057         shift -= 2;
14058       else if (bytemode == xmmdw_mode)
14059         shift -= 3;
14060       else if (bytemode == ymmq_mode && vex.length == 128)
14061         shift -= 1;
14062     }
14063   else
14064     shift = 0;
14065
14066   USED_REX (REX_B);
14067   if (intel_syntax)
14068     intel_operand_size (bytemode, sizeflag);
14069   append_seg ();
14070
14071   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14072     {
14073       /* 32/64 bit address mode */
14074       int havedisp;
14075       int havesib;
14076       int havebase;
14077       int haveindex;
14078       int needindex;
14079       int needaddr32;
14080       int base, rbase;
14081       int vindex = 0;
14082       int scale = 0;
14083       int addr32flag = !((sizeflag & AFLAG)
14084                          || bytemode == v_bnd_mode
14085                          || bytemode == v_bndmk_mode
14086                          || bytemode == bnd_mode
14087                          || bytemode == bnd_swap_mode);
14088       const char **indexes64 = names64;
14089       const char **indexes32 = names32;
14090
14091       havesib = 0;
14092       havebase = 1;
14093       haveindex = 0;
14094       base = modrm.rm;
14095
14096       if (base == 4)
14097         {
14098           havesib = 1;
14099           vindex = sib.index;
14100           USED_REX (REX_X);
14101           if (rex & REX_X)
14102             vindex += 8;
14103           switch (bytemode)
14104             {
14105             case vex_vsib_d_w_dq_mode:
14106             case vex_vsib_d_w_d_mode:
14107             case vex_vsib_q_w_dq_mode:
14108             case vex_vsib_q_w_d_mode:
14109               if (!need_vex)
14110                 abort ();
14111               if (vex.evex)
14112                 {
14113                   if (!vex.v)
14114                     vindex += 16;
14115                 }
14116
14117               haveindex = 1;
14118               switch (vex.length)
14119                 {
14120                 case 128:
14121                   indexes64 = indexes32 = names_xmm;
14122                   break;
14123                 case 256:
14124                   if (!vex.w
14125                       || bytemode == vex_vsib_q_w_dq_mode
14126                       || bytemode == vex_vsib_q_w_d_mode)
14127                     indexes64 = indexes32 = names_ymm;
14128                   else
14129                     indexes64 = indexes32 = names_xmm;
14130                   break;
14131                 case 512:
14132                   if (!vex.w
14133                       || bytemode == vex_vsib_q_w_dq_mode
14134                       || bytemode == vex_vsib_q_w_d_mode)
14135                     indexes64 = indexes32 = names_zmm;
14136                   else
14137                     indexes64 = indexes32 = names_ymm;
14138                   break;
14139                 default:
14140                   abort ();
14141                 }
14142               break;
14143             default:
14144               haveindex = vindex != 4;
14145               break;
14146             }
14147           scale = sib.scale;
14148           base = sib.base;
14149           codep++;
14150         }
14151       rbase = base + add;
14152
14153       switch (modrm.mod)
14154         {
14155         case 0:
14156           if (base == 5)
14157             {
14158               havebase = 0;
14159               if (address_mode == mode_64bit && !havesib)
14160                 riprel = 1;
14161               disp = get32s ();
14162               if (riprel && bytemode == v_bndmk_mode)
14163                 {
14164                   oappend ("(bad)");
14165                   return;
14166                 }
14167             }
14168           break;
14169         case 1:
14170           FETCH_DATA (the_info, codep + 1);
14171           disp = *codep++;
14172           if ((disp & 0x80) != 0)
14173             disp -= 0x100;
14174           if (vex.evex && shift > 0)
14175             disp <<= shift;
14176           break;
14177         case 2:
14178           disp = get32s ();
14179           break;
14180         }
14181
14182       needindex = 0;
14183       needaddr32 = 0;
14184       if (havesib
14185           && !havebase
14186           && !haveindex
14187           && address_mode != mode_16bit)
14188         {
14189           if (address_mode == mode_64bit)
14190             {
14191               /* Display eiz instead of addr32.  */
14192               needindex = addr32flag;
14193               needaddr32 = 1;
14194             }
14195           else
14196             {
14197               /* In 32-bit mode, we need index register to tell [offset]
14198                  from [eiz*1 + offset].  */
14199               needindex = 1;
14200             }
14201         }
14202
14203       havedisp = (havebase
14204                   || needindex
14205                   || (havesib && (haveindex || scale != 0)));
14206
14207       if (!intel_syntax)
14208         if (modrm.mod != 0 || base == 5)
14209           {
14210             if (havedisp || riprel)
14211               print_displacement (scratchbuf, disp);
14212             else
14213               print_operand_value (scratchbuf, 1, disp);
14214             oappend (scratchbuf);
14215             if (riprel)
14216               {
14217                 set_op (disp, 1);
14218                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14219               }
14220           }
14221
14222       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14223           && (address_mode != mode_64bit
14224               || ((bytemode != v_bnd_mode)
14225                   && (bytemode != v_bndmk_mode)
14226                   && (bytemode != bnd_mode)
14227                   && (bytemode != bnd_swap_mode))))
14228         used_prefixes |= PREFIX_ADDR;
14229
14230       if (havedisp || (intel_syntax && riprel))
14231         {
14232           *obufp++ = open_char;
14233           if (intel_syntax && riprel)
14234             {
14235               set_op (disp, 1);
14236               oappend (!addr32flag ? "rip" : "eip");
14237             }
14238           *obufp = '\0';
14239           if (havebase)
14240             oappend (address_mode == mode_64bit && !addr32flag
14241                      ? names64[rbase] : names32[rbase]);
14242           if (havesib)
14243             {
14244               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14245                  print index to tell base + index from base.  */
14246               if (scale != 0
14247                   || needindex
14248                   || haveindex
14249                   || (havebase && base != ESP_REG_NUM))
14250                 {
14251                   if (!intel_syntax || havebase)
14252                     {
14253                       *obufp++ = separator_char;
14254                       *obufp = '\0';
14255                     }
14256                   if (haveindex)
14257                     oappend (address_mode == mode_64bit && !addr32flag
14258                              ? indexes64[vindex] : indexes32[vindex]);
14259                   else
14260                     oappend (address_mode == mode_64bit && !addr32flag
14261                              ? index64 : index32);
14262
14263                   *obufp++ = scale_char;
14264                   *obufp = '\0';
14265                   sprintf (scratchbuf, "%d", 1 << scale);
14266                   oappend (scratchbuf);
14267                 }
14268             }
14269           if (intel_syntax
14270               && (disp || modrm.mod != 0 || base == 5))
14271             {
14272               if (!havedisp || (bfd_signed_vma) disp >= 0)
14273                 {
14274                   *obufp++ = '+';
14275                   *obufp = '\0';
14276                 }
14277               else if (modrm.mod != 1 && disp != -disp)
14278                 {
14279                   *obufp++ = '-';
14280                   *obufp = '\0';
14281                   disp = - (bfd_signed_vma) disp;
14282                 }
14283
14284               if (havedisp)
14285                 print_displacement (scratchbuf, disp);
14286               else
14287                 print_operand_value (scratchbuf, 1, disp);
14288               oappend (scratchbuf);
14289             }
14290
14291           *obufp++ = close_char;
14292           *obufp = '\0';
14293         }
14294       else if (intel_syntax)
14295         {
14296           if (modrm.mod != 0 || base == 5)
14297             {
14298               if (!active_seg_prefix)
14299                 {
14300                   oappend (names_seg[ds_reg - es_reg]);
14301                   oappend (":");
14302                 }
14303               print_operand_value (scratchbuf, 1, disp);
14304               oappend (scratchbuf);
14305             }
14306         }
14307     }
14308   else if (bytemode == v_bnd_mode
14309            || bytemode == v_bndmk_mode
14310            || bytemode == bnd_mode
14311            || bytemode == bnd_swap_mode)
14312     {
14313       oappend ("(bad)");
14314       return;
14315     }
14316   else
14317     {
14318       /* 16 bit address mode */
14319       used_prefixes |= prefixes & PREFIX_ADDR;
14320       switch (modrm.mod)
14321         {
14322         case 0:
14323           if (modrm.rm == 6)
14324             {
14325               disp = get16 ();
14326               if ((disp & 0x8000) != 0)
14327                 disp -= 0x10000;
14328             }
14329           break;
14330         case 1:
14331           FETCH_DATA (the_info, codep + 1);
14332           disp = *codep++;
14333           if ((disp & 0x80) != 0)
14334             disp -= 0x100;
14335           if (vex.evex && shift > 0)
14336             disp <<= shift;
14337           break;
14338         case 2:
14339           disp = get16 ();
14340           if ((disp & 0x8000) != 0)
14341             disp -= 0x10000;
14342           break;
14343         }
14344
14345       if (!intel_syntax)
14346         if (modrm.mod != 0 || modrm.rm == 6)
14347           {
14348             print_displacement (scratchbuf, disp);
14349             oappend (scratchbuf);
14350           }
14351
14352       if (modrm.mod != 0 || modrm.rm != 6)
14353         {
14354           *obufp++ = open_char;
14355           *obufp = '\0';
14356           oappend (index16[modrm.rm]);
14357           if (intel_syntax
14358               && (disp || modrm.mod != 0 || modrm.rm == 6))
14359             {
14360               if ((bfd_signed_vma) disp >= 0)
14361                 {
14362                   *obufp++ = '+';
14363                   *obufp = '\0';
14364                 }
14365               else if (modrm.mod != 1)
14366                 {
14367                   *obufp++ = '-';
14368                   *obufp = '\0';
14369                   disp = - (bfd_signed_vma) disp;
14370                 }
14371
14372               print_displacement (scratchbuf, disp);
14373               oappend (scratchbuf);
14374             }
14375
14376           *obufp++ = close_char;
14377           *obufp = '\0';
14378         }
14379       else if (intel_syntax)
14380         {
14381           if (!active_seg_prefix)
14382             {
14383               oappend (names_seg[ds_reg - es_reg]);
14384               oappend (":");
14385             }
14386           print_operand_value (scratchbuf, 1, disp & 0xffff);
14387           oappend (scratchbuf);
14388         }
14389     }
14390   if (vex.evex && vex.b
14391       && (bytemode == x_mode
14392           || bytemode == xmmq_mode
14393           || bytemode == evex_half_bcst_xmmq_mode))
14394     {
14395       if (vex.w
14396           || bytemode == xmmq_mode
14397           || bytemode == evex_half_bcst_xmmq_mode)
14398         {
14399           switch (vex.length)
14400             {
14401             case 128:
14402               oappend ("{1to2}");
14403               break;
14404             case 256:
14405               oappend ("{1to4}");
14406               break;
14407             case 512:
14408               oappend ("{1to8}");
14409               break;
14410             default:
14411               abort ();
14412             }
14413         }
14414       else
14415         {
14416           switch (vex.length)
14417             {
14418             case 128:
14419               oappend ("{1to4}");
14420               break;
14421             case 256:
14422               oappend ("{1to8}");
14423               break;
14424             case 512:
14425               oappend ("{1to16}");
14426               break;
14427             default:
14428               abort ();
14429             }
14430         }
14431     }
14432 }
14433
14434 static void
14435 OP_E (int bytemode, int sizeflag)
14436 {
14437   /* Skip mod/rm byte.  */
14438   MODRM_CHECK;
14439   codep++;
14440
14441   if (modrm.mod == 3)
14442     OP_E_register (bytemode, sizeflag);
14443   else
14444     OP_E_memory (bytemode, sizeflag);
14445 }
14446
14447 static void
14448 OP_G (int bytemode, int sizeflag)
14449 {
14450   int add = 0;
14451   const char **names;
14452   USED_REX (REX_R);
14453   if (rex & REX_R)
14454     add += 8;
14455   switch (bytemode)
14456     {
14457     case b_mode:
14458       USED_REX (0);
14459       if (rex)
14460         oappend (names8rex[modrm.reg + add]);
14461       else
14462         oappend (names8[modrm.reg + add]);
14463       break;
14464     case w_mode:
14465       oappend (names16[modrm.reg + add]);
14466       break;
14467     case d_mode:
14468     case db_mode:
14469     case dw_mode:
14470       oappend (names32[modrm.reg + add]);
14471       break;
14472     case q_mode:
14473       oappend (names64[modrm.reg + add]);
14474       break;
14475     case bnd_mode:
14476       if (modrm.reg > 0x3)
14477         {
14478           oappend ("(bad)");
14479           return;
14480         }
14481       oappend (names_bnd[modrm.reg]);
14482       break;
14483     case v_mode:
14484     case dq_mode:
14485     case dqb_mode:
14486     case dqd_mode:
14487     case dqw_mode:
14488     case movsxd_mode:
14489       USED_REX (REX_W);
14490       if (rex & REX_W)
14491         oappend (names64[modrm.reg + add]);
14492       else
14493         {
14494           if ((sizeflag & DFLAG)
14495               || (bytemode != v_mode && bytemode != movsxd_mode))
14496             oappend (names32[modrm.reg + add]);
14497           else
14498             oappend (names16[modrm.reg + add]);
14499           used_prefixes |= (prefixes & PREFIX_DATA);
14500         }
14501       break;
14502     case va_mode:
14503       names = (address_mode == mode_64bit
14504                ? names64 : names32);
14505       if (!(prefixes & PREFIX_ADDR))
14506         {
14507           if (address_mode == mode_16bit)
14508             names = names16;
14509         }
14510       else
14511         {
14512           /* Remove "addr16/addr32".  */
14513           all_prefixes[last_addr_prefix] = 0;
14514           names = (address_mode != mode_32bit
14515                        ? names32 : names16);
14516           used_prefixes |= PREFIX_ADDR;
14517         }
14518       oappend (names[modrm.reg + add]);
14519       break;
14520     case m_mode:
14521       if (address_mode == mode_64bit)
14522         oappend (names64[modrm.reg + add]);
14523       else
14524         oappend (names32[modrm.reg + add]);
14525       break;
14526     case mask_bd_mode:
14527     case mask_mode:
14528       if ((modrm.reg + add) > 0x7)
14529         {
14530           oappend ("(bad)");
14531           return;
14532         }
14533       oappend (names_mask[modrm.reg + add]);
14534       break;
14535     default:
14536       oappend (INTERNAL_DISASSEMBLER_ERROR);
14537       break;
14538     }
14539 }
14540
14541 static bfd_vma
14542 get64 (void)
14543 {
14544   bfd_vma x;
14545 #ifdef BFD64
14546   unsigned int a;
14547   unsigned int b;
14548
14549   FETCH_DATA (the_info, codep + 8);
14550   a = *codep++ & 0xff;
14551   a |= (*codep++ & 0xff) << 8;
14552   a |= (*codep++ & 0xff) << 16;
14553   a |= (*codep++ & 0xffu) << 24;
14554   b = *codep++ & 0xff;
14555   b |= (*codep++ & 0xff) << 8;
14556   b |= (*codep++ & 0xff) << 16;
14557   b |= (*codep++ & 0xffu) << 24;
14558   x = a + ((bfd_vma) b << 32);
14559 #else
14560   abort ();
14561   x = 0;
14562 #endif
14563   return x;
14564 }
14565
14566 static bfd_signed_vma
14567 get32 (void)
14568 {
14569   bfd_signed_vma x = 0;
14570
14571   FETCH_DATA (the_info, codep + 4);
14572   x = *codep++ & (bfd_signed_vma) 0xff;
14573   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14574   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14575   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14576   return x;
14577 }
14578
14579 static bfd_signed_vma
14580 get32s (void)
14581 {
14582   bfd_signed_vma x = 0;
14583
14584   FETCH_DATA (the_info, codep + 4);
14585   x = *codep++ & (bfd_signed_vma) 0xff;
14586   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14587   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14588   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14589
14590   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14591
14592   return x;
14593 }
14594
14595 static int
14596 get16 (void)
14597 {
14598   int x = 0;
14599
14600   FETCH_DATA (the_info, codep + 2);
14601   x = *codep++ & 0xff;
14602   x |= (*codep++ & 0xff) << 8;
14603   return x;
14604 }
14605
14606 static void
14607 set_op (bfd_vma op, int riprel)
14608 {
14609   op_index[op_ad] = op_ad;
14610   if (address_mode == mode_64bit)
14611     {
14612       op_address[op_ad] = op;
14613       op_riprel[op_ad] = riprel;
14614     }
14615   else
14616     {
14617       /* Mask to get a 32-bit address.  */
14618       op_address[op_ad] = op & 0xffffffff;
14619       op_riprel[op_ad] = riprel & 0xffffffff;
14620     }
14621 }
14622
14623 static void
14624 OP_REG (int code, int sizeflag)
14625 {
14626   const char *s;
14627   int add;
14628
14629   switch (code)
14630     {
14631     case es_reg: case ss_reg: case cs_reg:
14632     case ds_reg: case fs_reg: case gs_reg:
14633       oappend (names_seg[code - es_reg]);
14634       return;
14635     }
14636
14637   USED_REX (REX_B);
14638   if (rex & REX_B)
14639     add = 8;
14640   else
14641     add = 0;
14642
14643   switch (code)
14644     {
14645     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14646     case sp_reg: case bp_reg: case si_reg: case di_reg:
14647       s = names16[code - ax_reg + add];
14648       break;
14649     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14650     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14651       USED_REX (0);
14652       if (rex)
14653         s = names8rex[code - al_reg + add];
14654       else
14655         s = names8[code - al_reg];
14656       break;
14657     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14658     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14659       if (address_mode == mode_64bit
14660           && ((sizeflag & DFLAG) || (rex & REX_W)))
14661         {
14662           s = names64[code - rAX_reg + add];
14663           break;
14664         }
14665       code += eAX_reg - rAX_reg;
14666       /* Fall through.  */
14667     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14668     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14669       USED_REX (REX_W);
14670       if (rex & REX_W)
14671         s = names64[code - eAX_reg + add];
14672       else
14673         {
14674           if (sizeflag & DFLAG)
14675             s = names32[code - eAX_reg + add];
14676           else
14677             s = names16[code - eAX_reg + add];
14678           used_prefixes |= (prefixes & PREFIX_DATA);
14679         }
14680       break;
14681     default:
14682       s = INTERNAL_DISASSEMBLER_ERROR;
14683       break;
14684     }
14685   oappend (s);
14686 }
14687
14688 static void
14689 OP_IMREG (int code, int sizeflag)
14690 {
14691   const char *s;
14692
14693   switch (code)
14694     {
14695     case indir_dx_reg:
14696       if (intel_syntax)
14697         s = "dx";
14698       else
14699         s = "(%dx)";
14700       break;
14701     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14702     case sp_reg: case bp_reg: case si_reg: case di_reg:
14703       s = names16[code - ax_reg];
14704       break;
14705     case es_reg: case ss_reg: case cs_reg:
14706     case ds_reg: case fs_reg: case gs_reg:
14707       s = names_seg[code - es_reg];
14708       break;
14709     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14710     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14711       USED_REX (0);
14712       if (rex)
14713         s = names8rex[code - al_reg];
14714       else
14715         s = names8[code - al_reg];
14716       break;
14717     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14718     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14719       USED_REX (REX_W);
14720       if (rex & REX_W)
14721         s = names64[code - eAX_reg];
14722       else
14723         {
14724           if (sizeflag & DFLAG)
14725             s = names32[code - eAX_reg];
14726           else
14727             s = names16[code - eAX_reg];
14728           used_prefixes |= (prefixes & PREFIX_DATA);
14729         }
14730       break;
14731     case z_mode_ax_reg:
14732       if ((rex & REX_W) || (sizeflag & DFLAG))
14733         s = *names32;
14734       else
14735         s = *names16;
14736       if (!(rex & REX_W))
14737         used_prefixes |= (prefixes & PREFIX_DATA);
14738       break;
14739     default:
14740       s = INTERNAL_DISASSEMBLER_ERROR;
14741       break;
14742     }
14743   oappend (s);
14744 }
14745
14746 static void
14747 OP_I (int bytemode, int sizeflag)
14748 {
14749   bfd_signed_vma op;
14750   bfd_signed_vma mask = -1;
14751
14752   switch (bytemode)
14753     {
14754     case b_mode:
14755       FETCH_DATA (the_info, codep + 1);
14756       op = *codep++;
14757       mask = 0xff;
14758       break;
14759     case v_mode:
14760       USED_REX (REX_W);
14761       if (rex & REX_W)
14762         op = get32s ();
14763       else
14764         {
14765           if (sizeflag & DFLAG)
14766             {
14767               op = get32 ();
14768               mask = 0xffffffff;
14769             }
14770           else
14771             {
14772               op = get16 ();
14773               mask = 0xfffff;
14774             }
14775           used_prefixes |= (prefixes & PREFIX_DATA);
14776         }
14777       break;
14778     case d_mode:
14779       mask = 0xffffffff;
14780       op = get32 ();
14781       break;
14782     case w_mode:
14783       mask = 0xfffff;
14784       op = get16 ();
14785       break;
14786     case const_1_mode:
14787       if (intel_syntax)
14788         oappend ("1");
14789       return;
14790     default:
14791       oappend (INTERNAL_DISASSEMBLER_ERROR);
14792       return;
14793     }
14794
14795   op &= mask;
14796   scratchbuf[0] = '$';
14797   print_operand_value (scratchbuf + 1, 1, op);
14798   oappend_maybe_intel (scratchbuf);
14799   scratchbuf[0] = '\0';
14800 }
14801
14802 static void
14803 OP_I64 (int bytemode, int sizeflag)
14804 {
14805   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14806     {
14807       OP_I (bytemode, sizeflag);
14808       return;
14809     }
14810
14811   USED_REX (REX_W);
14812
14813   scratchbuf[0] = '$';
14814   print_operand_value (scratchbuf + 1, 1, get64 ());
14815   oappend_maybe_intel (scratchbuf);
14816   scratchbuf[0] = '\0';
14817 }
14818
14819 static void
14820 OP_sI (int bytemode, int sizeflag)
14821 {
14822   bfd_signed_vma op;
14823
14824   switch (bytemode)
14825     {
14826     case b_mode:
14827     case b_T_mode:
14828       FETCH_DATA (the_info, codep + 1);
14829       op = *codep++;
14830       if ((op & 0x80) != 0)
14831         op -= 0x100;
14832       if (bytemode == b_T_mode)
14833         {
14834           if (address_mode != mode_64bit
14835               || !((sizeflag & DFLAG) || (rex & REX_W)))
14836             {
14837               /* The operand-size prefix is overridden by a REX prefix.  */
14838               if ((sizeflag & DFLAG) || (rex & REX_W))
14839                 op &= 0xffffffff;
14840               else
14841                 op &= 0xffff;
14842           }
14843         }
14844       else
14845         {
14846           if (!(rex & REX_W))
14847             {
14848               if (sizeflag & DFLAG)
14849                 op &= 0xffffffff;
14850               else
14851                 op &= 0xffff;
14852             }
14853         }
14854       break;
14855     case v_mode:
14856       /* The operand-size prefix is overridden by a REX prefix.  */
14857       if ((sizeflag & DFLAG) || (rex & REX_W))
14858         op = get32s ();
14859       else
14860         op = get16 ();
14861       break;
14862     default:
14863       oappend (INTERNAL_DISASSEMBLER_ERROR);
14864       return;
14865     }
14866
14867   scratchbuf[0] = '$';
14868   print_operand_value (scratchbuf + 1, 1, op);
14869   oappend_maybe_intel (scratchbuf);
14870 }
14871
14872 static void
14873 OP_J (int bytemode, int sizeflag)
14874 {
14875   bfd_vma disp;
14876   bfd_vma mask = -1;
14877   bfd_vma segment = 0;
14878
14879   switch (bytemode)
14880     {
14881     case b_mode:
14882       FETCH_DATA (the_info, codep + 1);
14883       disp = *codep++;
14884       if ((disp & 0x80) != 0)
14885         disp -= 0x100;
14886       break;
14887     case v_mode:
14888       if (isa64 != intel64)
14889     case dqw_mode:
14890         USED_REX (REX_W);
14891       if ((sizeflag & DFLAG)
14892           || (address_mode == mode_64bit
14893               && ((isa64 == intel64 && bytemode != dqw_mode)
14894                   || (rex & REX_W))))
14895         disp = get32s ();
14896       else
14897         {
14898           disp = get16 ();
14899           if ((disp & 0x8000) != 0)
14900             disp -= 0x10000;
14901           /* In 16bit mode, address is wrapped around at 64k within
14902              the same segment.  Otherwise, a data16 prefix on a jump
14903              instruction means that the pc is masked to 16 bits after
14904              the displacement is added!  */
14905           mask = 0xffff;
14906           if ((prefixes & PREFIX_DATA) == 0)
14907             segment = ((start_pc + (codep - start_codep))
14908                        & ~((bfd_vma) 0xffff));
14909         }
14910       if (address_mode != mode_64bit
14911           || (isa64 != intel64 && !(rex & REX_W)))
14912         used_prefixes |= (prefixes & PREFIX_DATA);
14913       break;
14914     default:
14915       oappend (INTERNAL_DISASSEMBLER_ERROR);
14916       return;
14917     }
14918   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14919   set_op (disp, 0);
14920   print_operand_value (scratchbuf, 1, disp);
14921   oappend (scratchbuf);
14922 }
14923
14924 static void
14925 OP_SEG (int bytemode, int sizeflag)
14926 {
14927   if (bytemode == w_mode)
14928     oappend (names_seg[modrm.reg]);
14929   else
14930     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14931 }
14932
14933 static void
14934 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14935 {
14936   int seg, offset;
14937
14938   if (sizeflag & DFLAG)
14939     {
14940       offset = get32 ();
14941       seg = get16 ();
14942     }
14943   else
14944     {
14945       offset = get16 ();
14946       seg = get16 ();
14947     }
14948   used_prefixes |= (prefixes & PREFIX_DATA);
14949   if (intel_syntax)
14950     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14951   else
14952     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14953   oappend (scratchbuf);
14954 }
14955
14956 static void
14957 OP_OFF (int bytemode, int sizeflag)
14958 {
14959   bfd_vma off;
14960
14961   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14962     intel_operand_size (bytemode, sizeflag);
14963   append_seg ();
14964
14965   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14966     off = get32 ();
14967   else
14968     off = get16 ();
14969
14970   if (intel_syntax)
14971     {
14972       if (!active_seg_prefix)
14973         {
14974           oappend (names_seg[ds_reg - es_reg]);
14975           oappend (":");
14976         }
14977     }
14978   print_operand_value (scratchbuf, 1, off);
14979   oappend (scratchbuf);
14980 }
14981
14982 static void
14983 OP_OFF64 (int bytemode, int sizeflag)
14984 {
14985   bfd_vma off;
14986
14987   if (address_mode != mode_64bit
14988       || (prefixes & PREFIX_ADDR))
14989     {
14990       OP_OFF (bytemode, sizeflag);
14991       return;
14992     }
14993
14994   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14995     intel_operand_size (bytemode, sizeflag);
14996   append_seg ();
14997
14998   off = get64 ();
14999
15000   if (intel_syntax)
15001     {
15002       if (!active_seg_prefix)
15003         {
15004           oappend (names_seg[ds_reg - es_reg]);
15005           oappend (":");
15006         }
15007     }
15008   print_operand_value (scratchbuf, 1, off);
15009   oappend (scratchbuf);
15010 }
15011
15012 static void
15013 ptr_reg (int code, int sizeflag)
15014 {
15015   const char *s;
15016
15017   *obufp++ = open_char;
15018   used_prefixes |= (prefixes & PREFIX_ADDR);
15019   if (address_mode == mode_64bit)
15020     {
15021       if (!(sizeflag & AFLAG))
15022         s = names32[code - eAX_reg];
15023       else
15024         s = names64[code - eAX_reg];
15025     }
15026   else if (sizeflag & AFLAG)
15027     s = names32[code - eAX_reg];
15028   else
15029     s = names16[code - eAX_reg];
15030   oappend (s);
15031   *obufp++ = close_char;
15032   *obufp = 0;
15033 }
15034
15035 static void
15036 OP_ESreg (int code, int sizeflag)
15037 {
15038   if (intel_syntax)
15039     {
15040       switch (codep[-1])
15041         {
15042         case 0x6d:      /* insw/insl */
15043           intel_operand_size (z_mode, sizeflag);
15044           break;
15045         case 0xa5:      /* movsw/movsl/movsq */
15046         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15047         case 0xab:      /* stosw/stosl */
15048         case 0xaf:      /* scasw/scasl */
15049           intel_operand_size (v_mode, sizeflag);
15050           break;
15051         default:
15052           intel_operand_size (b_mode, sizeflag);
15053         }
15054     }
15055   oappend_maybe_intel ("%es:");
15056   ptr_reg (code, sizeflag);
15057 }
15058
15059 static void
15060 OP_DSreg (int code, int sizeflag)
15061 {
15062   if (intel_syntax)
15063     {
15064       switch (codep[-1])
15065         {
15066         case 0x6f:      /* outsw/outsl */
15067           intel_operand_size (z_mode, sizeflag);
15068           break;
15069         case 0xa5:      /* movsw/movsl/movsq */
15070         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15071         case 0xad:      /* lodsw/lodsl/lodsq */
15072           intel_operand_size (v_mode, sizeflag);
15073           break;
15074         default:
15075           intel_operand_size (b_mode, sizeflag);
15076         }
15077     }
15078   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15079      default segment register DS is printed.  */
15080   if (!active_seg_prefix)
15081     active_seg_prefix = PREFIX_DS;
15082   append_seg ();
15083   ptr_reg (code, sizeflag);
15084 }
15085
15086 static void
15087 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15088 {
15089   int add;
15090   if (rex & REX_R)
15091     {
15092       USED_REX (REX_R);
15093       add = 8;
15094     }
15095   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15096     {
15097       all_prefixes[last_lock_prefix] = 0;
15098       used_prefixes |= PREFIX_LOCK;
15099       add = 8;
15100     }
15101   else
15102     add = 0;
15103   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15104   oappend_maybe_intel (scratchbuf);
15105 }
15106
15107 static void
15108 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15109 {
15110   int add;
15111   USED_REX (REX_R);
15112   if (rex & REX_R)
15113     add = 8;
15114   else
15115     add = 0;
15116   if (intel_syntax)
15117     sprintf (scratchbuf, "db%d", modrm.reg + add);
15118   else
15119     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15120   oappend (scratchbuf);
15121 }
15122
15123 static void
15124 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15125 {
15126   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15127   oappend_maybe_intel (scratchbuf);
15128 }
15129
15130 static void
15131 OP_R (int bytemode, int sizeflag)
15132 {
15133   /* Skip mod/rm byte.  */
15134   MODRM_CHECK;
15135   codep++;
15136   OP_E_register (bytemode, sizeflag);
15137 }
15138
15139 static void
15140 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15141 {
15142   int reg = modrm.reg;
15143   const char **names;
15144
15145   used_prefixes |= (prefixes & PREFIX_DATA);
15146   if (prefixes & PREFIX_DATA)
15147     {
15148       names = names_xmm;
15149       USED_REX (REX_R);
15150       if (rex & REX_R)
15151         reg += 8;
15152     }
15153   else
15154     names = names_mm;
15155   oappend (names[reg]);
15156 }
15157
15158 static void
15159 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15160 {
15161   int reg = modrm.reg;
15162   const char **names;
15163
15164   USED_REX (REX_R);
15165   if (rex & REX_R)
15166     reg += 8;
15167   if (vex.evex)
15168     {
15169       if (!vex.r)
15170         reg += 16;
15171     }
15172
15173   if (need_vex
15174       && bytemode != xmm_mode
15175       && bytemode != xmmq_mode
15176       && bytemode != evex_half_bcst_xmmq_mode
15177       && bytemode != ymm_mode
15178       && bytemode != scalar_mode)
15179     {
15180       switch (vex.length)
15181         {
15182         case 128:
15183           names = names_xmm;
15184           break;
15185         case 256:
15186           if (vex.w
15187               || (bytemode != vex_vsib_q_w_dq_mode
15188                   && bytemode != vex_vsib_q_w_d_mode))
15189             names = names_ymm;
15190           else
15191             names = names_xmm;
15192           break;
15193         case 512:
15194           names = names_zmm;
15195           break;
15196         default:
15197           abort ();
15198         }
15199     }
15200   else if (bytemode == xmmq_mode
15201            || bytemode == evex_half_bcst_xmmq_mode)
15202     {
15203       switch (vex.length)
15204         {
15205         case 128:
15206         case 256:
15207           names = names_xmm;
15208           break;
15209         case 512:
15210           names = names_ymm;
15211           break;
15212         default:
15213           abort ();
15214         }
15215     }
15216   else if (bytemode == ymm_mode)
15217     names = names_ymm;
15218   else
15219     names = names_xmm;
15220   oappend (names[reg]);
15221 }
15222
15223 static void
15224 OP_EM (int bytemode, int sizeflag)
15225 {
15226   int reg;
15227   const char **names;
15228
15229   if (modrm.mod != 3)
15230     {
15231       if (intel_syntax
15232           && (bytemode == v_mode || bytemode == v_swap_mode))
15233         {
15234           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15235           used_prefixes |= (prefixes & PREFIX_DATA);
15236         }
15237       OP_E (bytemode, sizeflag);
15238       return;
15239     }
15240
15241   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15242     swap_operand ();
15243
15244   /* Skip mod/rm byte.  */
15245   MODRM_CHECK;
15246   codep++;
15247   used_prefixes |= (prefixes & PREFIX_DATA);
15248   reg = modrm.rm;
15249   if (prefixes & PREFIX_DATA)
15250     {
15251       names = names_xmm;
15252       USED_REX (REX_B);
15253       if (rex & REX_B)
15254         reg += 8;
15255     }
15256   else
15257     names = names_mm;
15258   oappend (names[reg]);
15259 }
15260
15261 /* cvt* are the only instructions in sse2 which have
15262    both SSE and MMX operands and also have 0x66 prefix
15263    in their opcode. 0x66 was originally used to differentiate
15264    between SSE and MMX instruction(operands). So we have to handle the
15265    cvt* separately using OP_EMC and OP_MXC */
15266 static void
15267 OP_EMC (int bytemode, int sizeflag)
15268 {
15269   if (modrm.mod != 3)
15270     {
15271       if (intel_syntax && bytemode == v_mode)
15272         {
15273           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15274           used_prefixes |= (prefixes & PREFIX_DATA);
15275         }
15276       OP_E (bytemode, sizeflag);
15277       return;
15278     }
15279
15280   /* Skip mod/rm byte.  */
15281   MODRM_CHECK;
15282   codep++;
15283   used_prefixes |= (prefixes & PREFIX_DATA);
15284   oappend (names_mm[modrm.rm]);
15285 }
15286
15287 static void
15288 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15289 {
15290   used_prefixes |= (prefixes & PREFIX_DATA);
15291   oappend (names_mm[modrm.reg]);
15292 }
15293
15294 static void
15295 OP_EX (int bytemode, int sizeflag)
15296 {
15297   int reg;
15298   const char **names;
15299
15300   /* Skip mod/rm byte.  */
15301   MODRM_CHECK;
15302   codep++;
15303
15304   if (modrm.mod != 3)
15305     {
15306       OP_E_memory (bytemode, sizeflag);
15307       return;
15308     }
15309
15310   reg = modrm.rm;
15311   USED_REX (REX_B);
15312   if (rex & REX_B)
15313     reg += 8;
15314   if (vex.evex)
15315     {
15316       USED_REX (REX_X);
15317       if ((rex & REX_X))
15318         reg += 16;
15319     }
15320
15321   if ((sizeflag & SUFFIX_ALWAYS)
15322       && (bytemode == x_swap_mode
15323           || bytemode == d_swap_mode
15324           || bytemode == d_scalar_swap_mode
15325           || bytemode == q_swap_mode
15326           || bytemode == q_scalar_swap_mode))
15327     swap_operand ();
15328
15329   if (need_vex
15330       && bytemode != xmm_mode
15331       && bytemode != xmmdw_mode
15332       && bytemode != xmmqd_mode
15333       && bytemode != xmm_mb_mode
15334       && bytemode != xmm_mw_mode
15335       && bytemode != xmm_md_mode
15336       && bytemode != xmm_mq_mode
15337       && bytemode != xmmq_mode
15338       && bytemode != evex_half_bcst_xmmq_mode
15339       && bytemode != ymm_mode
15340       && bytemode != d_scalar_mode
15341       && bytemode != d_scalar_swap_mode
15342       && bytemode != q_scalar_mode
15343       && bytemode != q_scalar_swap_mode
15344       && bytemode != vex_scalar_w_dq_mode)
15345     {
15346       switch (vex.length)
15347         {
15348         case 128:
15349           names = names_xmm;
15350           break;
15351         case 256:
15352           names = names_ymm;
15353           break;
15354         case 512:
15355           names = names_zmm;
15356           break;
15357         default:
15358           abort ();
15359         }
15360     }
15361   else if (bytemode == xmmq_mode
15362            || bytemode == evex_half_bcst_xmmq_mode)
15363     {
15364       switch (vex.length)
15365         {
15366         case 128:
15367         case 256:
15368           names = names_xmm;
15369           break;
15370         case 512:
15371           names = names_ymm;
15372           break;
15373         default:
15374           abort ();
15375         }
15376     }
15377   else if (bytemode == ymm_mode)
15378     names = names_ymm;
15379   else
15380     names = names_xmm;
15381   oappend (names[reg]);
15382 }
15383
15384 static void
15385 OP_MS (int bytemode, int sizeflag)
15386 {
15387   if (modrm.mod == 3)
15388     OP_EM (bytemode, sizeflag);
15389   else
15390     BadOp ();
15391 }
15392
15393 static void
15394 OP_XS (int bytemode, int sizeflag)
15395 {
15396   if (modrm.mod == 3)
15397     OP_EX (bytemode, sizeflag);
15398   else
15399     BadOp ();
15400 }
15401
15402 static void
15403 OP_M (int bytemode, int sizeflag)
15404 {
15405   if (modrm.mod == 3)
15406     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15407     BadOp ();
15408   else
15409     OP_E (bytemode, sizeflag);
15410 }
15411
15412 static void
15413 OP_0f07 (int bytemode, int sizeflag)
15414 {
15415   if (modrm.mod != 3 || modrm.rm != 0)
15416     BadOp ();
15417   else
15418     OP_E (bytemode, sizeflag);
15419 }
15420
15421 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15422    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15423
15424 static void
15425 NOP_Fixup1 (int bytemode, int sizeflag)
15426 {
15427   if ((prefixes & PREFIX_DATA) != 0
15428       || (rex != 0
15429           && rex != 0x48
15430           && address_mode == mode_64bit))
15431     OP_REG (bytemode, sizeflag);
15432   else
15433     strcpy (obuf, "nop");
15434 }
15435
15436 static void
15437 NOP_Fixup2 (int bytemode, int sizeflag)
15438 {
15439   if ((prefixes & PREFIX_DATA) != 0
15440       || (rex != 0
15441           && rex != 0x48
15442           && address_mode == mode_64bit))
15443     OP_IMREG (bytemode, sizeflag);
15444 }
15445
15446 static const char *const Suffix3DNow[] = {
15447 /* 00 */        NULL,           NULL,           NULL,           NULL,
15448 /* 04 */        NULL,           NULL,           NULL,           NULL,
15449 /* 08 */        NULL,           NULL,           NULL,           NULL,
15450 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15451 /* 10 */        NULL,           NULL,           NULL,           NULL,
15452 /* 14 */        NULL,           NULL,           NULL,           NULL,
15453 /* 18 */        NULL,           NULL,           NULL,           NULL,
15454 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15455 /* 20 */        NULL,           NULL,           NULL,           NULL,
15456 /* 24 */        NULL,           NULL,           NULL,           NULL,
15457 /* 28 */        NULL,           NULL,           NULL,           NULL,
15458 /* 2C */        NULL,           NULL,           NULL,           NULL,
15459 /* 30 */        NULL,           NULL,           NULL,           NULL,
15460 /* 34 */        NULL,           NULL,           NULL,           NULL,
15461 /* 38 */        NULL,           NULL,           NULL,           NULL,
15462 /* 3C */        NULL,           NULL,           NULL,           NULL,
15463 /* 40 */        NULL,           NULL,           NULL,           NULL,
15464 /* 44 */        NULL,           NULL,           NULL,           NULL,
15465 /* 48 */        NULL,           NULL,           NULL,           NULL,
15466 /* 4C */        NULL,           NULL,           NULL,           NULL,
15467 /* 50 */        NULL,           NULL,           NULL,           NULL,
15468 /* 54 */        NULL,           NULL,           NULL,           NULL,
15469 /* 58 */        NULL,           NULL,           NULL,           NULL,
15470 /* 5C */        NULL,           NULL,           NULL,           NULL,
15471 /* 60 */        NULL,           NULL,           NULL,           NULL,
15472 /* 64 */        NULL,           NULL,           NULL,           NULL,
15473 /* 68 */        NULL,           NULL,           NULL,           NULL,
15474 /* 6C */        NULL,           NULL,           NULL,           NULL,
15475 /* 70 */        NULL,           NULL,           NULL,           NULL,
15476 /* 74 */        NULL,           NULL,           NULL,           NULL,
15477 /* 78 */        NULL,           NULL,           NULL,           NULL,
15478 /* 7C */        NULL,           NULL,           NULL,           NULL,
15479 /* 80 */        NULL,           NULL,           NULL,           NULL,
15480 /* 84 */        NULL,           NULL,           NULL,           NULL,
15481 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15482 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15483 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15484 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15485 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15486 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15487 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15488 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15489 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15490 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15491 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15492 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15493 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15494 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15495 /* C0 */        NULL,           NULL,           NULL,           NULL,
15496 /* C4 */        NULL,           NULL,           NULL,           NULL,
15497 /* C8 */        NULL,           NULL,           NULL,           NULL,
15498 /* CC */        NULL,           NULL,           NULL,           NULL,
15499 /* D0 */        NULL,           NULL,           NULL,           NULL,
15500 /* D4 */        NULL,           NULL,           NULL,           NULL,
15501 /* D8 */        NULL,           NULL,           NULL,           NULL,
15502 /* DC */        NULL,           NULL,           NULL,           NULL,
15503 /* E0 */        NULL,           NULL,           NULL,           NULL,
15504 /* E4 */        NULL,           NULL,           NULL,           NULL,
15505 /* E8 */        NULL,           NULL,           NULL,           NULL,
15506 /* EC */        NULL,           NULL,           NULL,           NULL,
15507 /* F0 */        NULL,           NULL,           NULL,           NULL,
15508 /* F4 */        NULL,           NULL,           NULL,           NULL,
15509 /* F8 */        NULL,           NULL,           NULL,           NULL,
15510 /* FC */        NULL,           NULL,           NULL,           NULL,
15511 };
15512
15513 static void
15514 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15515 {
15516   const char *mnemonic;
15517
15518   FETCH_DATA (the_info, codep + 1);
15519   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15520      place where an 8-bit immediate would normally go.  ie. the last
15521      byte of the instruction.  */
15522   obufp = mnemonicendp;
15523   mnemonic = Suffix3DNow[*codep++ & 0xff];
15524   if (mnemonic)
15525     oappend (mnemonic);
15526   else
15527     {
15528       /* Since a variable sized modrm/sib chunk is between the start
15529          of the opcode (0x0f0f) and the opcode suffix, we need to do
15530          all the modrm processing first, and don't know until now that
15531          we have a bad opcode.  This necessitates some cleaning up.  */
15532       op_out[0][0] = '\0';
15533       op_out[1][0] = '\0';
15534       BadOp ();
15535     }
15536   mnemonicendp = obufp;
15537 }
15538
15539 static struct op simd_cmp_op[] =
15540 {
15541   { STRING_COMMA_LEN ("eq") },
15542   { STRING_COMMA_LEN ("lt") },
15543   { STRING_COMMA_LEN ("le") },
15544   { STRING_COMMA_LEN ("unord") },
15545   { STRING_COMMA_LEN ("neq") },
15546   { STRING_COMMA_LEN ("nlt") },
15547   { STRING_COMMA_LEN ("nle") },
15548   { STRING_COMMA_LEN ("ord") }
15549 };
15550
15551 static void
15552 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15553 {
15554   unsigned int cmp_type;
15555
15556   FETCH_DATA (the_info, codep + 1);
15557   cmp_type = *codep++ & 0xff;
15558   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15559     {
15560       char suffix [3];
15561       char *p = mnemonicendp - 2;
15562       suffix[0] = p[0];
15563       suffix[1] = p[1];
15564       suffix[2] = '\0';
15565       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15566       mnemonicendp += simd_cmp_op[cmp_type].len;
15567     }
15568   else
15569     {
15570       /* We have a reserved extension byte.  Output it directly.  */
15571       scratchbuf[0] = '$';
15572       print_operand_value (scratchbuf + 1, 1, cmp_type);
15573       oappend_maybe_intel (scratchbuf);
15574       scratchbuf[0] = '\0';
15575     }
15576 }
15577
15578 static void
15579 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15580 {
15581   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15582   if (!intel_syntax)
15583     {
15584       strcpy (op_out[0], names32[0]);
15585       strcpy (op_out[1], names32[1]);
15586       if (bytemode == eBX_reg)
15587         strcpy (op_out[2], names32[3]);
15588       two_source_ops = 1;
15589     }
15590   /* Skip mod/rm byte.  */
15591   MODRM_CHECK;
15592   codep++;
15593 }
15594
15595 static void
15596 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15597             int sizeflag ATTRIBUTE_UNUSED)
15598 {
15599   /* monitor %{e,r,}ax,%ecx,%edx"  */
15600   if (!intel_syntax)
15601     {
15602       const char **names = (address_mode == mode_64bit
15603                             ? names64 : names32);
15604
15605       if (prefixes & PREFIX_ADDR)
15606         {
15607           /* Remove "addr16/addr32".  */
15608           all_prefixes[last_addr_prefix] = 0;
15609           names = (address_mode != mode_32bit
15610                    ? names32 : names16);
15611           used_prefixes |= PREFIX_ADDR;
15612         }
15613       else if (address_mode == mode_16bit)
15614         names = names16;
15615       strcpy (op_out[0], names[0]);
15616       strcpy (op_out[1], names32[1]);
15617       strcpy (op_out[2], names32[2]);
15618       two_source_ops = 1;
15619     }
15620   /* Skip mod/rm byte.  */
15621   MODRM_CHECK;
15622   codep++;
15623 }
15624
15625 static void
15626 BadOp (void)
15627 {
15628   /* Throw away prefixes and 1st. opcode byte.  */
15629   codep = insn_codep + 1;
15630   oappend ("(bad)");
15631 }
15632
15633 static void
15634 REP_Fixup (int bytemode, int sizeflag)
15635 {
15636   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15637      lods and stos.  */
15638   if (prefixes & PREFIX_REPZ)
15639     all_prefixes[last_repz_prefix] = REP_PREFIX;
15640
15641   switch (bytemode)
15642     {
15643     case al_reg:
15644     case eAX_reg:
15645     case indir_dx_reg:
15646       OP_IMREG (bytemode, sizeflag);
15647       break;
15648     case eDI_reg:
15649       OP_ESreg (bytemode, sizeflag);
15650       break;
15651     case eSI_reg:
15652       OP_DSreg (bytemode, sizeflag);
15653       break;
15654     default:
15655       abort ();
15656       break;
15657     }
15658 }
15659
15660 static void
15661 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15662 {
15663   if ( isa64 != amd64 )
15664     return;
15665
15666   obufp = obuf;
15667   BadOp ();
15668   mnemonicendp = obufp;
15669   ++codep;
15670 }
15671
15672 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15673    "bnd".  */
15674
15675 static void
15676 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15677 {
15678   if (prefixes & PREFIX_REPNZ)
15679     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15680 }
15681
15682 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15683    "notrack".  */
15684
15685 static void
15686 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15687                int sizeflag ATTRIBUTE_UNUSED)
15688 {
15689   if (active_seg_prefix == PREFIX_DS
15690       && (address_mode != mode_64bit || last_data_prefix < 0))
15691     {
15692       /* NOTRACK prefix is only valid on indirect branch instructions.
15693          NB: DATA prefix is unsupported for Intel64.  */
15694       active_seg_prefix = 0;
15695       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15696     }
15697 }
15698
15699 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15700    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15701  */
15702
15703 static void
15704 HLE_Fixup1 (int bytemode, int sizeflag)
15705 {
15706   if (modrm.mod != 3
15707       && (prefixes & PREFIX_LOCK) != 0)
15708     {
15709       if (prefixes & PREFIX_REPZ)
15710         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15711       if (prefixes & PREFIX_REPNZ)
15712         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15713     }
15714
15715   OP_E (bytemode, sizeflag);
15716 }
15717
15718 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15719    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15720  */
15721
15722 static void
15723 HLE_Fixup2 (int bytemode, int sizeflag)
15724 {
15725   if (modrm.mod != 3)
15726     {
15727       if (prefixes & PREFIX_REPZ)
15728         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15729       if (prefixes & PREFIX_REPNZ)
15730         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15731     }
15732
15733   OP_E (bytemode, sizeflag);
15734 }
15735
15736 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15737    "xrelease" for memory operand.  No check for LOCK prefix.   */
15738
15739 static void
15740 HLE_Fixup3 (int bytemode, int sizeflag)
15741 {
15742   if (modrm.mod != 3
15743       && last_repz_prefix > last_repnz_prefix
15744       && (prefixes & PREFIX_REPZ) != 0)
15745     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15746
15747   OP_E (bytemode, sizeflag);
15748 }
15749
15750 static void
15751 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15752 {
15753   USED_REX (REX_W);
15754   if (rex & REX_W)
15755     {
15756       /* Change cmpxchg8b to cmpxchg16b.  */
15757       char *p = mnemonicendp - 2;
15758       mnemonicendp = stpcpy (p, "16b");
15759       bytemode = o_mode;
15760     }
15761   else if ((prefixes & PREFIX_LOCK) != 0)
15762     {
15763       if (prefixes & PREFIX_REPZ)
15764         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15765       if (prefixes & PREFIX_REPNZ)
15766         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15767     }
15768
15769   OP_M (bytemode, sizeflag);
15770 }
15771
15772 static void
15773 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15774 {
15775   const char **names;
15776
15777   if (need_vex)
15778     {
15779       switch (vex.length)
15780         {
15781         case 128:
15782           names = names_xmm;
15783           break;
15784         case 256:
15785           names = names_ymm;
15786           break;
15787         default:
15788           abort ();
15789         }
15790     }
15791   else
15792     names = names_xmm;
15793   oappend (names[reg]);
15794 }
15795
15796 static void
15797 CRC32_Fixup (int bytemode, int sizeflag)
15798 {
15799   /* Add proper suffix to "crc32".  */
15800   char *p = mnemonicendp;
15801
15802   switch (bytemode)
15803     {
15804     case b_mode:
15805       if (intel_syntax)
15806         goto skip;
15807
15808       *p++ = 'b';
15809       break;
15810     case v_mode:
15811       if (intel_syntax)
15812         goto skip;
15813
15814       USED_REX (REX_W);
15815       if (rex & REX_W)
15816         *p++ = 'q';
15817       else
15818         {
15819           if (sizeflag & DFLAG)
15820             *p++ = 'l';
15821           else
15822             *p++ = 'w';
15823           used_prefixes |= (prefixes & PREFIX_DATA);
15824         }
15825       break;
15826     default:
15827       oappend (INTERNAL_DISASSEMBLER_ERROR);
15828       break;
15829     }
15830   mnemonicendp = p;
15831   *p = '\0';
15832
15833  skip:
15834   if (modrm.mod == 3)
15835     {
15836       int add;
15837
15838       /* Skip mod/rm byte.  */
15839       MODRM_CHECK;
15840       codep++;
15841
15842       USED_REX (REX_B);
15843       add = (rex & REX_B) ? 8 : 0;
15844       if (bytemode == b_mode)
15845         {
15846           USED_REX (0);
15847           if (rex)
15848             oappend (names8rex[modrm.rm + add]);
15849           else
15850             oappend (names8[modrm.rm + add]);
15851         }
15852       else
15853         {
15854           USED_REX (REX_W);
15855           if (rex & REX_W)
15856             oappend (names64[modrm.rm + add]);
15857           else if ((prefixes & PREFIX_DATA))
15858             oappend (names16[modrm.rm + add]);
15859           else
15860             oappend (names32[modrm.rm + add]);
15861         }
15862     }
15863   else
15864     OP_E (bytemode, sizeflag);
15865 }
15866
15867 static void
15868 FXSAVE_Fixup (int bytemode, int sizeflag)
15869 {
15870   /* Add proper suffix to "fxsave" and "fxrstor".  */
15871   USED_REX (REX_W);
15872   if (rex & REX_W)
15873     {
15874       char *p = mnemonicendp;
15875       *p++ = '6';
15876       *p++ = '4';
15877       *p = '\0';
15878       mnemonicendp = p;
15879     }
15880   OP_M (bytemode, sizeflag);
15881 }
15882
15883 static void
15884 PCMPESTR_Fixup (int bytemode, int sizeflag)
15885 {
15886   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15887   if (!intel_syntax)
15888     {
15889       char *p = mnemonicendp;
15890
15891       USED_REX (REX_W);
15892       if (rex & REX_W)
15893         *p++ = 'q';
15894       else if (sizeflag & SUFFIX_ALWAYS)
15895         *p++ = 'l';
15896
15897       *p = '\0';
15898       mnemonicendp = p;
15899     }
15900
15901   OP_EX (bytemode, sizeflag);
15902 }
15903
15904 /* Display the destination register operand for instructions with
15905    VEX. */
15906
15907 static void
15908 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15909 {
15910   int reg;
15911   const char **names;
15912
15913   if (!need_vex)
15914     abort ();
15915
15916   if (!need_vex_reg)
15917     return;
15918
15919   reg = vex.register_specifier;
15920   vex.register_specifier = 0;
15921   if (address_mode != mode_64bit)
15922     reg &= 7;
15923   else if (vex.evex && !vex.v)
15924     reg += 16;
15925
15926   if (bytemode == vex_scalar_mode)
15927     {
15928       oappend (names_xmm[reg]);
15929       return;
15930     }
15931
15932   switch (vex.length)
15933     {
15934     case 128:
15935       switch (bytemode)
15936         {
15937         case vex_mode:
15938         case vex128_mode:
15939         case vex_vsib_q_w_dq_mode:
15940         case vex_vsib_q_w_d_mode:
15941           names = names_xmm;
15942           break;
15943         case dq_mode:
15944           if (rex & REX_W)
15945             names = names64;
15946           else
15947             names = names32;
15948           break;
15949         case mask_bd_mode:
15950         case mask_mode:
15951           if (reg > 0x7)
15952             {
15953               oappend ("(bad)");
15954               return;
15955             }
15956           names = names_mask;
15957           break;
15958         default:
15959           abort ();
15960           return;
15961         }
15962       break;
15963     case 256:
15964       switch (bytemode)
15965         {
15966         case vex_mode:
15967         case vex256_mode:
15968           names = names_ymm;
15969           break;
15970         case vex_vsib_q_w_dq_mode:
15971         case vex_vsib_q_w_d_mode:
15972           names = vex.w ? names_ymm : names_xmm;
15973           break;
15974         case mask_bd_mode:
15975         case mask_mode:
15976           if (reg > 0x7)
15977             {
15978               oappend ("(bad)");
15979               return;
15980             }
15981           names = names_mask;
15982           break;
15983         default:
15984           /* See PR binutils/20893 for a reproducer.  */
15985           oappend ("(bad)");
15986           return;
15987         }
15988       break;
15989     case 512:
15990       names = names_zmm;
15991       break;
15992     default:
15993       abort ();
15994       break;
15995     }
15996   oappend (names[reg]);
15997 }
15998
15999 /* Get the VEX immediate byte without moving codep.  */
16000
16001 static unsigned char
16002 get_vex_imm8 (int sizeflag, int opnum)
16003 {
16004   int bytes_before_imm = 0;
16005
16006   if (modrm.mod != 3)
16007     {
16008       /* There are SIB/displacement bytes.  */
16009       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16010         {
16011           /* 32/64 bit address mode */
16012           int base = modrm.rm;
16013
16014           /* Check SIB byte.  */
16015           if (base == 4)
16016             {
16017               FETCH_DATA (the_info, codep + 1);
16018               base = *codep & 7;
16019               /* When decoding the third source, don't increase
16020                  bytes_before_imm as this has already been incremented
16021                  by one in OP_E_memory while decoding the second
16022                  source operand.  */
16023               if (opnum == 0)
16024                 bytes_before_imm++;
16025             }
16026
16027           /* Don't increase bytes_before_imm when decoding the third source,
16028              it has already been incremented by OP_E_memory while decoding
16029              the second source operand.  */
16030           if (opnum == 0)
16031             {
16032               switch (modrm.mod)
16033                 {
16034                   case 0:
16035                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16036                        SIB == 5, there is a 4 byte displacement.  */
16037                     if (base != 5)
16038                       /* No displacement. */
16039                       break;
16040                     /* Fall through.  */
16041                   case 2:
16042                     /* 4 byte displacement.  */
16043                     bytes_before_imm += 4;
16044                     break;
16045                   case 1:
16046                     /* 1 byte displacement.  */
16047                     bytes_before_imm++;
16048                     break;
16049                 }
16050             }
16051         }
16052       else
16053         {
16054           /* 16 bit address mode */
16055           /* Don't increase bytes_before_imm when decoding the third source,
16056              it has already been incremented by OP_E_memory while decoding
16057              the second source operand.  */
16058           if (opnum == 0)
16059             {
16060               switch (modrm.mod)
16061                 {
16062                 case 0:
16063                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16064                   if (modrm.rm != 6)
16065                     /* No displacement. */
16066                     break;
16067                   /* Fall through.  */
16068                 case 2:
16069                   /* 2 byte displacement.  */
16070                   bytes_before_imm += 2;
16071                   break;
16072                 case 1:
16073                   /* 1 byte displacement: when decoding the third source,
16074                      don't increase bytes_before_imm as this has already
16075                      been incremented by one in OP_E_memory while decoding
16076                      the second source operand.  */
16077                   if (opnum == 0)
16078                     bytes_before_imm++;
16079
16080                   break;
16081                 }
16082             }
16083         }
16084     }
16085
16086   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16087   return codep [bytes_before_imm];
16088 }
16089
16090 static void
16091 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16092 {
16093   const char **names;
16094
16095   if (reg == -1 && modrm.mod != 3)
16096     {
16097       OP_E_memory (bytemode, sizeflag);
16098       return;
16099     }
16100   else
16101     {
16102       if (reg == -1)
16103         {
16104           reg = modrm.rm;
16105           USED_REX (REX_B);
16106           if (rex & REX_B)
16107             reg += 8;
16108         }
16109       if (address_mode != mode_64bit)
16110         reg &= 7;
16111     }
16112
16113   switch (vex.length)
16114     {
16115     case 128:
16116       names = names_xmm;
16117       break;
16118     case 256:
16119       names = names_ymm;
16120       break;
16121     default:
16122       abort ();
16123     }
16124   oappend (names[reg]);
16125 }
16126
16127 static void
16128 OP_EX_VexImmW (int bytemode, int sizeflag)
16129 {
16130   int reg = -1;
16131   static unsigned char vex_imm8;
16132
16133   if (vex_w_done == 0)
16134     {
16135       vex_w_done = 1;
16136
16137       /* Skip mod/rm byte.  */
16138       MODRM_CHECK;
16139       codep++;
16140
16141       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16142
16143       if (vex.w)
16144           reg = vex_imm8 >> 4;
16145
16146       OP_EX_VexReg (bytemode, sizeflag, reg);
16147     }
16148   else if (vex_w_done == 1)
16149     {
16150       vex_w_done = 2;
16151
16152       if (!vex.w)
16153           reg = vex_imm8 >> 4;
16154
16155       OP_EX_VexReg (bytemode, sizeflag, reg);
16156     }
16157   else
16158     {
16159       /* Output the imm8 directly.  */
16160       scratchbuf[0] = '$';
16161       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16162       oappend_maybe_intel (scratchbuf);
16163       scratchbuf[0] = '\0';
16164       codep++;
16165     }
16166 }
16167
16168 static void
16169 OP_Vex_2src (int bytemode, int sizeflag)
16170 {
16171   if (modrm.mod == 3)
16172     {
16173       int reg = modrm.rm;
16174       USED_REX (REX_B);
16175       if (rex & REX_B)
16176         reg += 8;
16177       oappend (names_xmm[reg]);
16178     }
16179   else
16180     {
16181       if (intel_syntax
16182           && (bytemode == v_mode || bytemode == v_swap_mode))
16183         {
16184           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16185           used_prefixes |= (prefixes & PREFIX_DATA);
16186         }
16187       OP_E (bytemode, sizeflag);
16188     }
16189 }
16190
16191 static void
16192 OP_Vex_2src_1 (int bytemode, int sizeflag)
16193 {
16194   if (modrm.mod == 3)
16195     {
16196       /* Skip mod/rm byte.   */
16197       MODRM_CHECK;
16198       codep++;
16199     }
16200
16201   if (vex.w)
16202     {
16203       unsigned int reg = vex.register_specifier;
16204       vex.register_specifier = 0;
16205
16206       if (address_mode != mode_64bit)
16207         reg &= 7;
16208       oappend (names_xmm[reg]);
16209     }
16210   else
16211     OP_Vex_2src (bytemode, sizeflag);
16212 }
16213
16214 static void
16215 OP_Vex_2src_2 (int bytemode, int sizeflag)
16216 {
16217   if (vex.w)
16218     OP_Vex_2src (bytemode, sizeflag);
16219   else
16220     {
16221       unsigned int reg = vex.register_specifier;
16222       vex.register_specifier = 0;
16223
16224       if (address_mode != mode_64bit)
16225         reg &= 7;
16226       oappend (names_xmm[reg]);
16227     }
16228 }
16229
16230 static void
16231 OP_EX_VexW (int bytemode, int sizeflag)
16232 {
16233   int reg = -1;
16234
16235   if (!vex_w_done)
16236     {
16237       /* Skip mod/rm byte.  */
16238       MODRM_CHECK;
16239       codep++;
16240
16241       if (vex.w)
16242         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16243     }
16244   else
16245     {
16246       if (!vex.w)
16247         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16248     }
16249
16250   OP_EX_VexReg (bytemode, sizeflag, reg);
16251
16252   if (vex_w_done)
16253     codep++;
16254   vex_w_done = 1;
16255 }
16256
16257 static void
16258 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16259 {
16260   int reg;
16261   const char **names;
16262
16263   FETCH_DATA (the_info, codep + 1);
16264   reg = *codep++;
16265
16266   if (bytemode != x_mode)
16267     abort ();
16268
16269   reg >>= 4;
16270   if (address_mode != mode_64bit)
16271     reg &= 7;
16272
16273   switch (vex.length)
16274     {
16275     case 128:
16276       names = names_xmm;
16277       break;
16278     case 256:
16279       names = names_ymm;
16280       break;
16281     default:
16282       abort ();
16283     }
16284   oappend (names[reg]);
16285 }
16286
16287 static void
16288 OP_XMM_VexW (int bytemode, int sizeflag)
16289 {
16290   /* Turn off the REX.W bit since it is used for swapping operands
16291      now.  */
16292   rex &= ~REX_W;
16293   OP_XMM (bytemode, sizeflag);
16294 }
16295
16296 static void
16297 OP_EX_Vex (int bytemode, int sizeflag)
16298 {
16299   if (modrm.mod != 3)
16300     need_vex_reg = 0;
16301   OP_EX (bytemode, sizeflag);
16302 }
16303
16304 static void
16305 OP_XMM_Vex (int bytemode, int sizeflag)
16306 {
16307   if (modrm.mod != 3)
16308     need_vex_reg = 0;
16309   OP_XMM (bytemode, sizeflag);
16310 }
16311
16312 static struct op vex_cmp_op[] =
16313 {
16314   { STRING_COMMA_LEN ("eq") },
16315   { STRING_COMMA_LEN ("lt") },
16316   { STRING_COMMA_LEN ("le") },
16317   { STRING_COMMA_LEN ("unord") },
16318   { STRING_COMMA_LEN ("neq") },
16319   { STRING_COMMA_LEN ("nlt") },
16320   { STRING_COMMA_LEN ("nle") },
16321   { STRING_COMMA_LEN ("ord") },
16322   { STRING_COMMA_LEN ("eq_uq") },
16323   { STRING_COMMA_LEN ("nge") },
16324   { STRING_COMMA_LEN ("ngt") },
16325   { STRING_COMMA_LEN ("false") },
16326   { STRING_COMMA_LEN ("neq_oq") },
16327   { STRING_COMMA_LEN ("ge") },
16328   { STRING_COMMA_LEN ("gt") },
16329   { STRING_COMMA_LEN ("true") },
16330   { STRING_COMMA_LEN ("eq_os") },
16331   { STRING_COMMA_LEN ("lt_oq") },
16332   { STRING_COMMA_LEN ("le_oq") },
16333   { STRING_COMMA_LEN ("unord_s") },
16334   { STRING_COMMA_LEN ("neq_us") },
16335   { STRING_COMMA_LEN ("nlt_uq") },
16336   { STRING_COMMA_LEN ("nle_uq") },
16337   { STRING_COMMA_LEN ("ord_s") },
16338   { STRING_COMMA_LEN ("eq_us") },
16339   { STRING_COMMA_LEN ("nge_uq") },
16340   { STRING_COMMA_LEN ("ngt_uq") },
16341   { STRING_COMMA_LEN ("false_os") },
16342   { STRING_COMMA_LEN ("neq_os") },
16343   { STRING_COMMA_LEN ("ge_oq") },
16344   { STRING_COMMA_LEN ("gt_oq") },
16345   { STRING_COMMA_LEN ("true_us") },
16346 };
16347
16348 static void
16349 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16350 {
16351   unsigned int cmp_type;
16352
16353   FETCH_DATA (the_info, codep + 1);
16354   cmp_type = *codep++ & 0xff;
16355   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16356     {
16357       char suffix [3];
16358       char *p = mnemonicendp - 2;
16359       suffix[0] = p[0];
16360       suffix[1] = p[1];
16361       suffix[2] = '\0';
16362       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16363       mnemonicendp += vex_cmp_op[cmp_type].len;
16364     }
16365   else
16366     {
16367       /* We have a reserved extension byte.  Output it directly.  */
16368       scratchbuf[0] = '$';
16369       print_operand_value (scratchbuf + 1, 1, cmp_type);
16370       oappend_maybe_intel (scratchbuf);
16371       scratchbuf[0] = '\0';
16372     }
16373 }
16374
16375 static void
16376 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16377              int sizeflag ATTRIBUTE_UNUSED)
16378 {
16379   unsigned int cmp_type;
16380
16381   if (!vex.evex)
16382     abort ();
16383
16384   FETCH_DATA (the_info, codep + 1);
16385   cmp_type = *codep++ & 0xff;
16386   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16387      If it's the case, print suffix, otherwise - print the immediate.  */
16388   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16389       && cmp_type != 3
16390       && cmp_type != 7)
16391     {
16392       char suffix [3];
16393       char *p = mnemonicendp - 2;
16394
16395       /* vpcmp* can have both one- and two-lettered suffix.  */
16396       if (p[0] == 'p')
16397         {
16398           p++;
16399           suffix[0] = p[0];
16400           suffix[1] = '\0';
16401         }
16402       else
16403         {
16404           suffix[0] = p[0];
16405           suffix[1] = p[1];
16406           suffix[2] = '\0';
16407         }
16408
16409       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16410       mnemonicendp += simd_cmp_op[cmp_type].len;
16411     }
16412   else
16413     {
16414       /* We have a reserved extension byte.  Output it directly.  */
16415       scratchbuf[0] = '$';
16416       print_operand_value (scratchbuf + 1, 1, cmp_type);
16417       oappend_maybe_intel (scratchbuf);
16418       scratchbuf[0] = '\0';
16419     }
16420 }
16421
16422 static const struct op xop_cmp_op[] =
16423 {
16424   { STRING_COMMA_LEN ("lt") },
16425   { STRING_COMMA_LEN ("le") },
16426   { STRING_COMMA_LEN ("gt") },
16427   { STRING_COMMA_LEN ("ge") },
16428   { STRING_COMMA_LEN ("eq") },
16429   { STRING_COMMA_LEN ("neq") },
16430   { STRING_COMMA_LEN ("false") },
16431   { STRING_COMMA_LEN ("true") }
16432 };
16433
16434 static void
16435 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16436              int sizeflag ATTRIBUTE_UNUSED)
16437 {
16438   unsigned int cmp_type;
16439
16440   FETCH_DATA (the_info, codep + 1);
16441   cmp_type = *codep++ & 0xff;
16442   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16443     {
16444       char suffix[3];
16445       char *p = mnemonicendp - 2;
16446
16447       /* vpcom* can have both one- and two-lettered suffix.  */
16448       if (p[0] == 'm')
16449         {
16450           p++;
16451           suffix[0] = p[0];
16452           suffix[1] = '\0';
16453         }
16454       else
16455         {
16456           suffix[0] = p[0];
16457           suffix[1] = p[1];
16458           suffix[2] = '\0';
16459         }
16460
16461       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16462       mnemonicendp += xop_cmp_op[cmp_type].len;
16463     }
16464   else
16465     {
16466       /* We have a reserved extension byte.  Output it directly.  */
16467       scratchbuf[0] = '$';
16468       print_operand_value (scratchbuf + 1, 1, cmp_type);
16469       oappend_maybe_intel (scratchbuf);
16470       scratchbuf[0] = '\0';
16471     }
16472 }
16473
16474 static const struct op pclmul_op[] =
16475 {
16476   { STRING_COMMA_LEN ("lql") },
16477   { STRING_COMMA_LEN ("hql") },
16478   { STRING_COMMA_LEN ("lqh") },
16479   { STRING_COMMA_LEN ("hqh") }
16480 };
16481
16482 static void
16483 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16484               int sizeflag ATTRIBUTE_UNUSED)
16485 {
16486   unsigned int pclmul_type;
16487
16488   FETCH_DATA (the_info, codep + 1);
16489   pclmul_type = *codep++ & 0xff;
16490   switch (pclmul_type)
16491     {
16492     case 0x10:
16493       pclmul_type = 2;
16494       break;
16495     case 0x11:
16496       pclmul_type = 3;
16497       break;
16498     default:
16499       break;
16500     }
16501   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16502     {
16503       char suffix [4];
16504       char *p = mnemonicendp - 3;
16505       suffix[0] = p[0];
16506       suffix[1] = p[1];
16507       suffix[2] = p[2];
16508       suffix[3] = '\0';
16509       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16510       mnemonicendp += pclmul_op[pclmul_type].len;
16511     }
16512   else
16513     {
16514       /* We have a reserved extension byte.  Output it directly.  */
16515       scratchbuf[0] = '$';
16516       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16517       oappend_maybe_intel (scratchbuf);
16518       scratchbuf[0] = '\0';
16519     }
16520 }
16521
16522 static void
16523 MOVBE_Fixup (int bytemode, int sizeflag)
16524 {
16525   /* Add proper suffix to "movbe".  */
16526   char *p = mnemonicendp;
16527
16528   switch (bytemode)
16529     {
16530     case v_mode:
16531       if (intel_syntax)
16532         goto skip;
16533
16534       USED_REX (REX_W);
16535       if (sizeflag & SUFFIX_ALWAYS)
16536         {
16537           if (rex & REX_W)
16538             *p++ = 'q';
16539           else
16540             {
16541               if (sizeflag & DFLAG)
16542                 *p++ = 'l';
16543               else
16544                 *p++ = 'w';
16545               used_prefixes |= (prefixes & PREFIX_DATA);
16546             }
16547         }
16548       break;
16549     default:
16550       oappend (INTERNAL_DISASSEMBLER_ERROR);
16551       break;
16552     }
16553   mnemonicendp = p;
16554   *p = '\0';
16555
16556  skip:
16557   OP_M (bytemode, sizeflag);
16558 }
16559
16560 static void
16561 MOVSXD_Fixup (int bytemode, int sizeflag)
16562 {
16563   /* Add proper suffix to "movsxd".  */
16564   char *p = mnemonicendp;
16565
16566   switch (bytemode)
16567     {
16568     case movsxd_mode:
16569       if (intel_syntax)
16570         {
16571           *p++ = 'x';
16572           *p++ = 'd';
16573           goto skip;
16574         }
16575
16576       USED_REX (REX_W);
16577       if (rex & REX_W)
16578         {
16579           *p++ = 'l';
16580           *p++ = 'q';
16581         }
16582       else
16583         {
16584           *p++ = 'x';
16585           *p++ = 'd';
16586         }
16587       break;
16588     default:
16589       oappend (INTERNAL_DISASSEMBLER_ERROR);
16590       break;
16591     }
16592
16593  skip:
16594   mnemonicendp = p;
16595   *p = '\0';
16596   OP_E (bytemode, sizeflag);
16597 }
16598
16599 static void
16600 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16601 {
16602   int reg;
16603   const char **names;
16604
16605   /* Skip mod/rm byte.  */
16606   MODRM_CHECK;
16607   codep++;
16608
16609   if (rex & REX_W)
16610     names = names64;
16611   else
16612     names = names32;
16613
16614   reg = modrm.rm;
16615   USED_REX (REX_B);
16616   if (rex & REX_B)
16617     reg += 8;
16618
16619   oappend (names[reg]);
16620 }
16621
16622 static void
16623 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16624 {
16625   const char **names;
16626   unsigned int reg = vex.register_specifier;
16627   vex.register_specifier = 0;
16628
16629   if (rex & REX_W)
16630     names = names64;
16631   else
16632     names = names32;
16633
16634   if (address_mode != mode_64bit)
16635     reg &= 7;
16636   oappend (names[reg]);
16637 }
16638
16639 static void
16640 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16641 {
16642   if (!vex.evex
16643       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16644     abort ();
16645
16646   USED_REX (REX_R);
16647   if ((rex & REX_R) != 0 || !vex.r)
16648     {
16649       BadOp ();
16650       return;
16651     }
16652
16653   oappend (names_mask [modrm.reg]);
16654 }
16655
16656 static void
16657 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16658 {
16659   if (!vex.evex
16660       || (bytemode != evex_rounding_mode
16661           && bytemode != evex_rounding_64_mode
16662           && bytemode != evex_sae_mode))
16663     abort ();
16664   if (modrm.mod == 3 && vex.b)
16665     switch (bytemode)
16666       {
16667       case evex_rounding_64_mode:
16668         if (address_mode != mode_64bit)
16669           {
16670             oappend ("(bad)");
16671             break;
16672           }
16673         /* Fall through.  */
16674       case evex_rounding_mode:
16675         oappend (names_rounding[vex.ll]);
16676         break;
16677       case evex_sae_mode:
16678         oappend ("{sae}");
16679         break;
16680       default:
16681         break;
16682       }
16683 }