opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_XMM_Vex (int, int);
  93 static void OP_Rounding (int, int);
  94 static void OP_REG_VexI4 (int, int);
  95 static void OP_VexI4 (int, int);
  96 static void PCLMUL_Fixup (int, int);
  97 static void VCMP_Fixup (int, int);
  98 static void VPCMP_Fixup (int, int);
  99 static void VPCOM_Fixup (int, int);
 100 static void OP_0f07 (int, int);
 101 static void OP_Monitor (int, int);
 102 static void OP_Mwait (int, int);
 103 static void NOP_Fixup1 (int, int);
 104 static void NOP_Fixup2 (int, int);
 105 static void OP_3DNowSuffix (int, int);
 106 static void CMP_Fixup (int, int);
 107 static void BadOp (void);
 108 static void REP_Fixup (int, int);
 109 static void SEP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void PCMPESTR_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126 static void MOVSXD_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_IGNORED_SHIFT    16
 226 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 231
 232 /* Opcode prefixes.  */
 233 #define PREFIX_OPCODE           (PREFIX_REPZ \
 234                                  | PREFIX_REPNZ \
 235                                  | PREFIX_DATA)
 236
 237 /* Prefixes ignored.  */
 238 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 239                                  | PREFIX_IGNORED_REPNZ \
 240                                  | PREFIX_IGNORED_DATA)
 241
 242 #define XX { NULL, 0 }
 243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 244
 245 #define Eb { OP_E, b_mode }
 246 #define Ebnd { OP_E, bnd_mode }
 247 #define EbS { OP_E, b_swap_mode }
 248 #define EbndS { OP_E, bnd_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Eva { OP_E, va_mode }
 251 #define Ev_bnd { OP_E, v_bnd_mode }
 252 #define EvS { OP_E, v_swap_mode }
 253 #define Ed { OP_E, d_mode }
 254 #define Edq { OP_E, dq_mode }
 255 #define Edqw { OP_E, dqw_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mv_bnd { OP_M, v_bndmk_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gva { OP_G, va_mode }
 283 #define Gw { OP_G, w_mode }
 284 #define Rd { OP_R, d_mode }
 285 #define Rdq { OP_R, dq_mode }
 286 #define Rm { OP_R, m_mode }
 287 #define Ib { OP_I, b_mode }
 288 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 290 #define Iv { OP_I, v_mode }
 291 #define sIv { OP_sI, v_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Id { OP_I, d_mode }
 294 #define Iw { OP_I, w_mode }
 295 #define I1 { OP_I, const_1_mode }
 296 #define Jb { OP_J, b_mode }
 297 #define Jv { OP_J, v_mode }
 298 #define Jdqw { OP_J, dqw_mode }
 299 #define Cm { OP_C, m_mode }
 300 #define Dm { OP_D, m_mode }
 301 #define Td { OP_T, d_mode }
 302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 303
 304 #define RMeAX { OP_REG, eAX_reg }
 305 #define RMeBX { OP_REG, eBX_reg }
 306 #define RMeCX { OP_REG, eCX_reg }
 307 #define RMeDX { OP_REG, eDX_reg }
 308 #define RMeSP { OP_REG, eSP_reg }
 309 #define RMeBP { OP_REG, eBP_reg }
 310 #define RMeSI { OP_REG, eSI_reg }
 311 #define RMeDI { OP_REG, eDI_reg }
 312 #define RMrAX { OP_REG, rAX_reg }
 313 #define RMrBX { OP_REG, rBX_reg }
 314 #define RMrCX { OP_REG, rCX_reg }
 315 #define RMrDX { OP_REG, rDX_reg }
 316 #define RMrSP { OP_REG, rSP_reg }
 317 #define RMrBP { OP_REG, rBP_reg }
 318 #define RMrSI { OP_REG, rSI_reg }
 319 #define RMrDI { OP_REG, rDI_reg }
 320 #define RMAL { OP_REG, al_reg }
 321 #define RMCL { OP_REG, cl_reg }
 322 #define RMDL { OP_REG, dl_reg }
 323 #define RMBL { OP_REG, bl_reg }
 324 #define RMAH { OP_REG, ah_reg }
 325 #define RMCH { OP_REG, ch_reg }
 326 #define RMDH { OP_REG, dh_reg }
 327 #define RMBH { OP_REG, bh_reg }
 328 #define RMAX { OP_REG, ax_reg }
 329 #define RMDX { OP_REG, dx_reg }
 330
 331 #define eAX { OP_IMREG, eAX_reg }
 332 #define eBX { OP_IMREG, eBX_reg }
 333 #define eCX { OP_IMREG, eCX_reg }
 334 #define eDX { OP_IMREG, eDX_reg }
 335 #define eSP { OP_IMREG, eSP_reg }
 336 #define eBP { OP_IMREG, eBP_reg }
 337 #define eSI { OP_IMREG, eSI_reg }
 338 #define eDI { OP_IMREG, eDI_reg }
 339 #define AL { OP_IMREG, al_reg }
 340 #define CL { OP_IMREG, cl_reg }
 341 #define DL { OP_IMREG, dl_reg }
 342 #define BL { OP_IMREG, bl_reg }
 343 #define AH { OP_IMREG, ah_reg }
 344 #define CH { OP_IMREG, ch_reg }
 345 #define DH { OP_IMREG, dh_reg }
 346 #define BH { OP_IMREG, bh_reg }
 347 #define AX { OP_IMREG, ax_reg }
 348 #define DX { OP_IMREG, dx_reg }
 349 #define zAX { OP_IMREG, z_mode_ax_reg }
 350 #define indirDX { OP_IMREG, indir_dx_reg }
 351
 352 #define Sw { OP_SEG, w_mode }
 353 #define Sv { OP_SEG, v_mode }
 354 #define Ap { OP_DIR, 0 }
 355 #define Ob { OP_OFF64, b_mode }
 356 #define Ov { OP_OFF64, v_mode }
 357 #define Xb { OP_DSreg, eSI_reg }
 358 #define Xv { OP_DSreg, eSI_reg }
 359 #define Xz { OP_DSreg, eSI_reg }
 360 #define Yb { OP_ESreg, eDI_reg }
 361 #define Yv { OP_ESreg, eDI_reg }
 362 #define DSBX { OP_DSreg, eBX_reg }
 363
 364 #define es { OP_REG, es_reg }
 365 #define ss { OP_REG, ss_reg }
 366 #define cs { OP_REG, cs_reg }
 367 #define ds { OP_REG, ds_reg }
 368 #define fs { OP_REG, fs_reg }
 369 #define gs { OP_REG, gs_reg }
 370
 371 #define MX { OP_MMX, 0 }
 372 #define XM { OP_XMM, 0 }
 373 #define XMScalar { OP_XMM, scalar_mode }
 374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 375 #define XMM { OP_XMM, xmm_mode }
 376 #define XMxmmq { OP_XMM, xmmq_mode }
 377 #define EM { OP_EM, v_mode }
 378 #define EMS { OP_EM, v_swap_mode }
 379 #define EMd { OP_EM, d_mode }
 380 #define EMx { OP_EM, x_mode }
 381 #define EXbScalar { OP_EX, b_scalar_mode }
 382 #define EXw { OP_EX, w_mode }
 383 #define EXwScalar { OP_EX, w_scalar_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdS { OP_EX, d_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqS { OP_EX, q_swap_mode }
 388 #define EXx { OP_EX, x_mode }
 389 #define EXxS { OP_EX, x_swap_mode }
 390 #define EXxmm { OP_EX, xmm_mode }
 391 #define EXymm { OP_EX, ymm_mode }
 392 #define EXxmmq { OP_EX, xmmq_mode }
 393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 396 #define EXxmm_md { OP_EX, xmm_md_mode }
 397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define SEP { SEP_Fixup, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 423 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 424 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 425 #define XMVexI4 { OP_REG_VexI4, x_mode }
 426 #define VexI4 { OP_VexI4, 0 }
 427 #define PCLMUL { PCLMUL_Fixup, 0 }
 428 #define VCMP { VCMP_Fixup, 0 }
 429 #define VPCMP { VPCMP_Fixup, 0 }
 430 #define VPCOM { VPCOM_Fixup, 0 }
 431
 432 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 433 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 434 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 435
 436 #define XMask { OP_Mask, mask_mode }
 437 #define MaskG { OP_G, mask_mode }
 438 #define MaskE { OP_E, mask_mode }
 439 #define MaskBDE { OP_E, mask_bd_mode }
 440 #define MaskR { OP_R, mask_mode }
 441 #define MaskVex { OP_VEX, mask_mode }
 442
 443 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 444 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 445 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 446 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 447
 448 /* Used handle "rep" prefix for string instructions.  */
 449 #define Xbr { REP_Fixup, eSI_reg }
 450 #define Xvr { REP_Fixup, eSI_reg }
 451 #define Ybr { REP_Fixup, eDI_reg }
 452 #define Yvr { REP_Fixup, eDI_reg }
 453 #define Yzr { REP_Fixup, eDI_reg }
 454 #define indirDXr { REP_Fixup, indir_dx_reg }
 455 #define ALr { REP_Fixup, al_reg }
 456 #define eAXr { REP_Fixup, eAX_reg }
 457
 458 /* Used handle HLE prefix for lockable instructions.  */
 459 #define Ebh1 { HLE_Fixup1, b_mode }
 460 #define Evh1 { HLE_Fixup1, v_mode }
 461 #define Ebh2 { HLE_Fixup2, b_mode }
 462 #define Evh2 { HLE_Fixup2, v_mode }
 463 #define Ebh3 { HLE_Fixup3, b_mode }
 464 #define Evh3 { HLE_Fixup3, v_mode }
 465
 466 #define BND { BND_Fixup, 0 }
 467 #define NOTRACK { NOTRACK_Fixup, 0 }
 468
 469 #define cond_jump_flag { NULL, cond_jump_mode }
 470 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 471
 472 /* bits in sizeflag */
 473 #define SUFFIX_ALWAYS 4
 474 #define AFLAG 2
 475 #define DFLAG 1
 476
 477 enum
 478 {
 479   /* byte operand */
 480   b_mode = 1,
 481   /* byte operand with operand swapped */
 482   b_swap_mode,
 483   /* byte operand, sign extend like 'T' suffix */
 484   b_T_mode,
 485   /* operand size depends on prefixes */
 486   v_mode,
 487   /* operand size depends on prefixes with operand swapped */
 488   v_swap_mode,
 489   /* operand size depends on address prefix */
 490   va_mode,
 491   /* word operand */
 492   w_mode,
 493   /* double word operand  */
 494   d_mode,
 495   /* double word operand with operand swapped */
 496   d_swap_mode,
 497   /* quad word operand */
 498   q_mode,
 499   /* quad word operand with operand swapped */
 500   q_swap_mode,
 501   /* ten-byte operand */
 502   t_mode,
 503   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 504      broadcast enabled.  */
 505   x_mode,
 506   /* Similar to x_mode, but with different EVEX mem shifts.  */
 507   evex_x_gscat_mode,
 508   /* Similar to x_mode, but with disabled broadcast.  */
 509   evex_x_nobcst_mode,
 510   /* Similar to x_mode, but with operands swapped and disabled broadcast
 511      in EVEX.  */
 512   x_swap_mode,
 513   /* 16-byte XMM operand */
 514   xmm_mode,
 515   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 516      memory operand (depending on vector length).  Broadcast isn't
 517      allowed.  */
 518   xmmq_mode,
 519   /* Same as xmmq_mode, but broadcast is allowed.  */
 520   evex_half_bcst_xmmq_mode,
 521   /* XMM register or byte memory operand */
 522   xmm_mb_mode,
 523   /* XMM register or word memory operand */
 524   xmm_mw_mode,
 525   /* XMM register or double word memory operand */
 526   xmm_md_mode,
 527   /* XMM register or quad word memory operand */
 528   xmm_mq_mode,
 529   /* 16-byte XMM, word, double word or quad word operand.  */
 530   xmmdw_mode,
 531   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 532   xmmqd_mode,
 533   /* 32-byte YMM operand */
 534   ymm_mode,
 535   /* quad word, ymmword or zmmword memory operand.  */
 536   ymmq_mode,
 537   /* 32-byte YMM or 16-byte word operand */
 538   ymmxmm_mode,
 539   /* d_mode in 32bit, q_mode in 64bit mode.  */
 540   m_mode,
 541   /* pair of v_mode operands */
 542   a_mode,
 543   cond_jump_mode,
 544   loop_jcxz_mode,
 545   movsxd_mode,
 546   v_bnd_mode,
 547   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 548   v_bndmk_mode,
 549   /* operand size depends on REX prefixes.  */
 550   dq_mode,
 551   /* registers like dq_mode, memory like w_mode, displacements like
 552      v_mode without considering Intel64 ISA.  */
 553   dqw_mode,
 554   /* bounds operand */
 555   bnd_mode,
 556   /* bounds operand with operand swapped */
 557   bnd_swap_mode,
 558   /* 4- or 6-byte pointer operand */
 559   f_mode,
 560   const_1_mode,
 561   /* v_mode for indirect branch opcodes.  */
 562   indir_v_mode,
 563   /* v_mode for stack-related opcodes.  */
 564   stack_v_mode,
 565   /* non-quad operand size depends on prefixes */
 566   z_mode,
 567   /* 16-byte operand */
 568   o_mode,
 569   /* registers like dq_mode, memory like b_mode.  */
 570   dqb_mode,
 571   /* registers like d_mode, memory like b_mode.  */
 572   db_mode,
 573   /* registers like d_mode, memory like w_mode.  */
 574   dw_mode,
 575   /* registers like dq_mode, memory like d_mode.  */
 576   dqd_mode,
 577   /* normal vex mode */
 578   vex_mode,
 579   /* 128bit vex mode */
 580   vex128_mode,
 581   /* 256bit vex mode */
 582   vex256_mode,
 583
 584   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 585   vex_vsib_d_w_dq_mode,
 586   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 587   vex_vsib_d_w_d_mode,
 588   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 589   vex_vsib_q_w_dq_mode,
 590   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 591   vex_vsib_q_w_d_mode,
 592
 593   /* scalar, ignore vector length.  */
 594   scalar_mode,
 595   /* like b_mode, ignore vector length.  */
 596   b_scalar_mode,
 597   /* like w_mode, ignore vector length.  */
 598   w_scalar_mode,
 599   /* like d_swap_mode, ignore vector length.  */
 600   d_scalar_swap_mode,
 601   /* like q_swap_mode, ignore vector length.  */
 602   q_scalar_swap_mode,
 603   /* like vex_mode, ignore vector length.  */
 604   vex_scalar_mode,
 605   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 606   vex_scalar_w_dq_mode,
 607
 608   /* Static rounding.  */
 609   evex_rounding_mode,
 610   /* Static rounding, 64-bit mode only.  */
 611   evex_rounding_64_mode,
 612   /* Supress all exceptions.  */
 613   evex_sae_mode,
 614
 615   /* Mask register operand.  */
 616   mask_mode,
 617   /* Mask register operand.  */
 618   mask_bd_mode,
 619
 620   es_reg,
 621   cs_reg,
 622   ss_reg,
 623   ds_reg,
 624   fs_reg,
 625   gs_reg,
 626
 627   eAX_reg,
 628   eCX_reg,
 629   eDX_reg,
 630   eBX_reg,
 631   eSP_reg,
 632   eBP_reg,
 633   eSI_reg,
 634   eDI_reg,
 635
 636   al_reg,
 637   cl_reg,
 638   dl_reg,
 639   bl_reg,
 640   ah_reg,
 641   ch_reg,
 642   dh_reg,
 643   bh_reg,
 644
 645   ax_reg,
 646   cx_reg,
 647   dx_reg,
 648   bx_reg,
 649   sp_reg,
 650   bp_reg,
 651   si_reg,
 652   di_reg,
 653
 654   rAX_reg,
 655   rCX_reg,
 656   rDX_reg,
 657   rBX_reg,
 658   rSP_reg,
 659   rBP_reg,
 660   rSI_reg,
 661   rDI_reg,
 662
 663   z_mode_ax_reg,
 664   indir_dx_reg
 665 };
 666
 667 enum
 668 {
 669   FLOATCODE = 1,
 670   USE_REG_TABLE,
 671   USE_MOD_TABLE,
 672   USE_RM_TABLE,
 673   USE_PREFIX_TABLE,
 674   USE_X86_64_TABLE,
 675   USE_3BYTE_TABLE,
 676   USE_XOP_8F_TABLE,
 677   USE_VEX_C4_TABLE,
 678   USE_VEX_C5_TABLE,
 679   USE_VEX_LEN_TABLE,
 680   USE_VEX_W_TABLE,
 681   USE_EVEX_TABLE,
 682   USE_EVEX_LEN_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 703
 704 enum
 705 {
 706   REG_80 = 0,
 707   REG_81,
 708   REG_83,
 709   REG_8F,
 710   REG_C0,
 711   REG_C1,
 712   REG_C6,
 713   REG_C7,
 714   REG_D0,
 715   REG_D1,
 716   REG_D2,
 717   REG_D3,
 718   REG_F6,
 719   REG_F7,
 720   REG_FE,
 721   REG_FF,
 722   REG_0F00,
 723   REG_0F01,
 724   REG_0F0D,
 725   REG_0F18,
 726   REG_0F1C_P_0_MOD_0,
 727   REG_0F1E_P_1_MOD_3,
 728   REG_0F71,
 729   REG_0F72,
 730   REG_0F73,
 731   REG_0FA6,
 732   REG_0FA7,
 733   REG_0FAE,
 734   REG_0FBA,
 735   REG_0FC7,
 736   REG_VEX_0F71,
 737   REG_VEX_0F72,
 738   REG_VEX_0F73,
 739   REG_VEX_0FAE,
 740   REG_VEX_0F38F3,
 741   REG_XOP_LWPCB,
 742   REG_XOP_LWP,
 743   REG_XOP_TBM_01,
 744   REG_XOP_TBM_02,
 745
 746   REG_EVEX_0F71,
 747   REG_EVEX_0F72,
 748   REG_EVEX_0F73,
 749   REG_EVEX_0F38C6,
 750   REG_EVEX_0F38C7
 751 };
 752
 753 enum
 754 {
 755   MOD_8D = 0,
 756   MOD_C6_REG_7,
 757   MOD_C7_REG_7,
 758   MOD_FF_REG_3,
 759   MOD_FF_REG_5,
 760   MOD_0F01_REG_0,
 761   MOD_0F01_REG_1,
 762   MOD_0F01_REG_2,
 763   MOD_0F01_REG_3,
 764   MOD_0F01_REG_5,
 765   MOD_0F01_REG_7,
 766   MOD_0F12_PREFIX_0,
 767   MOD_0F12_PREFIX_2,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F16_PREFIX_2,
 771   MOD_0F17,
 772   MOD_0F18_REG_0,
 773   MOD_0F18_REG_1,
 774   MOD_0F18_REG_2,
 775   MOD_0F18_REG_3,
 776   MOD_0F18_REG_4,
 777   MOD_0F18_REG_5,
 778   MOD_0F18_REG_6,
 779   MOD_0F18_REG_7,
 780   MOD_0F1A_PREFIX_0,
 781   MOD_0F1B_PREFIX_0,
 782   MOD_0F1B_PREFIX_1,
 783   MOD_0F1C_PREFIX_0,
 784   MOD_0F1E_PREFIX_1,
 785   MOD_0F24,
 786   MOD_0F26,
 787   MOD_0F2B_PREFIX_0,
 788   MOD_0F2B_PREFIX_1,
 789   MOD_0F2B_PREFIX_2,
 790   MOD_0F2B_PREFIX_3,
 791   MOD_0F50,
 792   MOD_0F71_REG_2,
 793   MOD_0F71_REG_4,
 794   MOD_0F71_REG_6,
 795   MOD_0F72_REG_2,
 796   MOD_0F72_REG_4,
 797   MOD_0F72_REG_6,
 798   MOD_0F73_REG_2,
 799   MOD_0F73_REG_3,
 800   MOD_0F73_REG_6,
 801   MOD_0F73_REG_7,
 802   MOD_0FAE_REG_0,
 803   MOD_0FAE_REG_1,
 804   MOD_0FAE_REG_2,
 805   MOD_0FAE_REG_3,
 806   MOD_0FAE_REG_4,
 807   MOD_0FAE_REG_5,
 808   MOD_0FAE_REG_6,
 809   MOD_0FAE_REG_7,
 810   MOD_0FB2,
 811   MOD_0FB4,
 812   MOD_0FB5,
 813   MOD_0FC3,
 814   MOD_0FC7_REG_3,
 815   MOD_0FC7_REG_4,
 816   MOD_0FC7_REG_5,
 817   MOD_0FC7_REG_6,
 818   MOD_0FC7_REG_7,
 819   MOD_0FD7,
 820   MOD_0FE7_PREFIX_2,
 821   MOD_0FF0_PREFIX_3,
 822   MOD_0F382A_PREFIX_2,
 823   MOD_0F38F5_PREFIX_2,
 824   MOD_0F38F6_PREFIX_0,
 825   MOD_0F38F8_PREFIX_1,
 826   MOD_0F38F8_PREFIX_2,
 827   MOD_0F38F8_PREFIX_3,
 828   MOD_0F38F9_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F12_PREFIX_2,
 834   MOD_VEX_0F13,
 835   MOD_VEX_0F16_PREFIX_0,
 836   MOD_VEX_0F16_PREFIX_2,
 837   MOD_VEX_0F17,
 838   MOD_VEX_0F2B,
 839   MOD_VEX_W_0_0F41_P_0_LEN_1,
 840   MOD_VEX_W_1_0F41_P_0_LEN_1,
 841   MOD_VEX_W_0_0F41_P_2_LEN_1,
 842   MOD_VEX_W_1_0F41_P_2_LEN_1,
 843   MOD_VEX_W_0_0F42_P_0_LEN_1,
 844   MOD_VEX_W_1_0F42_P_0_LEN_1,
 845   MOD_VEX_W_0_0F42_P_2_LEN_1,
 846   MOD_VEX_W_1_0F42_P_2_LEN_1,
 847   MOD_VEX_W_0_0F44_P_0_LEN_1,
 848   MOD_VEX_W_1_0F44_P_0_LEN_1,
 849   MOD_VEX_W_0_0F44_P_2_LEN_1,
 850   MOD_VEX_W_1_0F44_P_2_LEN_1,
 851   MOD_VEX_W_0_0F45_P_0_LEN_1,
 852   MOD_VEX_W_1_0F45_P_0_LEN_1,
 853   MOD_VEX_W_0_0F45_P_2_LEN_1,
 854   MOD_VEX_W_1_0F45_P_2_LEN_1,
 855   MOD_VEX_W_0_0F46_P_0_LEN_1,
 856   MOD_VEX_W_1_0F46_P_0_LEN_1,
 857   MOD_VEX_W_0_0F46_P_2_LEN_1,
 858   MOD_VEX_W_1_0F46_P_2_LEN_1,
 859   MOD_VEX_W_0_0F47_P_0_LEN_1,
 860   MOD_VEX_W_1_0F47_P_0_LEN_1,
 861   MOD_VEX_W_0_0F47_P_2_LEN_1,
 862   MOD_VEX_W_1_0F47_P_2_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 865   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 866   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 868   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 869   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 870   MOD_VEX_0F50,
 871   MOD_VEX_0F71_REG_2,
 872   MOD_VEX_0F71_REG_4,
 873   MOD_VEX_0F71_REG_6,
 874   MOD_VEX_0F72_REG_2,
 875   MOD_VEX_0F72_REG_4,
 876   MOD_VEX_0F72_REG_6,
 877   MOD_VEX_0F73_REG_2,
 878   MOD_VEX_0F73_REG_3,
 879   MOD_VEX_0F73_REG_6,
 880   MOD_VEX_0F73_REG_7,
 881   MOD_VEX_W_0_0F91_P_0_LEN_0,
 882   MOD_VEX_W_1_0F91_P_0_LEN_0,
 883   MOD_VEX_W_0_0F91_P_2_LEN_0,
 884   MOD_VEX_W_1_0F91_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_0_LEN_0,
 886   MOD_VEX_W_0_0F92_P_2_LEN_0,
 887   MOD_VEX_0F92_P_3_LEN_0,
 888   MOD_VEX_W_0_0F93_P_0_LEN_0,
 889   MOD_VEX_W_0_0F93_P_2_LEN_0,
 890   MOD_VEX_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F12_PREFIX_0,
 923   MOD_EVEX_0F12_PREFIX_2,
 924   MOD_EVEX_0F13,
 925   MOD_EVEX_0F16_PREFIX_0,
 926   MOD_EVEX_0F16_PREFIX_2,
 927   MOD_EVEX_0F17,
 928   MOD_EVEX_0F2B,
 929   MOD_EVEX_0F381A_P_2_W_0,
 930   MOD_EVEX_0F381A_P_2_W_1,
 931   MOD_EVEX_0F381B_P_2_W_0,
 932   MOD_EVEX_0F381B_P_2_W_1,
 933   MOD_EVEX_0F385A_P_2_W_0,
 934   MOD_EVEX_0F385A_P_2_W_1,
 935   MOD_EVEX_0F385B_P_2_W_0,
 936   MOD_EVEX_0F385B_P_2_W_1,
 937   MOD_EVEX_0F38C6_REG_1,
 938   MOD_EVEX_0F38C6_REG_2,
 939   MOD_EVEX_0F38C6_REG_5,
 940   MOD_EVEX_0F38C6_REG_6,
 941   MOD_EVEX_0F38C7_REG_1,
 942   MOD_EVEX_0F38C7_REG_2,
 943   MOD_EVEX_0F38C7_REG_5,
 944   MOD_EVEX_0F38C7_REG_6
 945 };
 946
 947 enum
 948 {
 949   RM_C6_REG_7 = 0,
 950   RM_C7_REG_7,
 951   RM_0F01_REG_0,
 952   RM_0F01_REG_1,
 953   RM_0F01_REG_2,
 954   RM_0F01_REG_3,
 955   RM_0F01_REG_5_MOD_3,
 956   RM_0F01_REG_7_MOD_3,
 957   RM_0F1E_P_1_MOD_3_REG_7,
 958   RM_0FAE_REG_6_MOD_3_P_0,
 959   RM_0FAE_REG_7_MOD_3,
 960 };
 961
 962 enum
 963 {
 964   PREFIX_90 = 0,
 965   PREFIX_0F01_REG_3_RM_1,
 966   PREFIX_0F01_REG_5_MOD_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_0,
 968   PREFIX_0F01_REG_5_MOD_3_RM_1,
 969   PREFIX_0F01_REG_5_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_2,
 971   PREFIX_0F01_REG_7_MOD_3_RM_3,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6C,
1002   PREFIX_0F6D,
1003   PREFIX_0F6F,
1004   PREFIX_0F70,
1005   PREFIX_0F73_REG_3,
1006   PREFIX_0F73_REG_7,
1007   PREFIX_0F78,
1008   PREFIX_0F79,
1009   PREFIX_0F7C,
1010   PREFIX_0F7D,
1011   PREFIX_0F7E,
1012   PREFIX_0F7F,
1013   PREFIX_0FAE_REG_0_MOD_3,
1014   PREFIX_0FAE_REG_1_MOD_3,
1015   PREFIX_0FAE_REG_2_MOD_3,
1016   PREFIX_0FAE_REG_3_MOD_3,
1017   PREFIX_0FAE_REG_4_MOD_0,
1018   PREFIX_0FAE_REG_4_MOD_3,
1019   PREFIX_0FAE_REG_5_MOD_0,
1020   PREFIX_0FAE_REG_5_MOD_3,
1021   PREFIX_0FAE_REG_6_MOD_0,
1022   PREFIX_0FAE_REG_6_MOD_3,
1023   PREFIX_0FAE_REG_7_MOD_0,
1024   PREFIX_0FB8,
1025   PREFIX_0FBC,
1026   PREFIX_0FBD,
1027   PREFIX_0FC2,
1028   PREFIX_0FC3_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_0,
1030   PREFIX_0FC7_REG_6_MOD_3,
1031   PREFIX_0FC7_REG_7_MOD_3,
1032   PREFIX_0FD0,
1033   PREFIX_0FD6,
1034   PREFIX_0FE6,
1035   PREFIX_0FE7,
1036   PREFIX_0FF0,
1037   PREFIX_0FF7,
1038   PREFIX_0F3810,
1039   PREFIX_0F3814,
1040   PREFIX_0F3815,
1041   PREFIX_0F3817,
1042   PREFIX_0F3820,
1043   PREFIX_0F3821,
1044   PREFIX_0F3822,
1045   PREFIX_0F3823,
1046   PREFIX_0F3824,
1047   PREFIX_0F3825,
1048   PREFIX_0F3828,
1049   PREFIX_0F3829,
1050   PREFIX_0F382A,
1051   PREFIX_0F382B,
1052   PREFIX_0F3830,
1053   PREFIX_0F3831,
1054   PREFIX_0F3832,
1055   PREFIX_0F3833,
1056   PREFIX_0F3834,
1057   PREFIX_0F3835,
1058   PREFIX_0F3837,
1059   PREFIX_0F3838,
1060   PREFIX_0F3839,
1061   PREFIX_0F383A,
1062   PREFIX_0F383B,
1063   PREFIX_0F383C,
1064   PREFIX_0F383D,
1065   PREFIX_0F383E,
1066   PREFIX_0F383F,
1067   PREFIX_0F3840,
1068   PREFIX_0F3841,
1069   PREFIX_0F3880,
1070   PREFIX_0F3881,
1071   PREFIX_0F3882,
1072   PREFIX_0F38C8,
1073   PREFIX_0F38C9,
1074   PREFIX_0F38CA,
1075   PREFIX_0F38CB,
1076   PREFIX_0F38CC,
1077   PREFIX_0F38CD,
1078   PREFIX_0F38CF,
1079   PREFIX_0F38DB,
1080   PREFIX_0F38DC,
1081   PREFIX_0F38DD,
1082   PREFIX_0F38DE,
1083   PREFIX_0F38DF,
1084   PREFIX_0F38F0,
1085   PREFIX_0F38F1,
1086   PREFIX_0F38F5,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8,
1089   PREFIX_0F38F9,
1090   PREFIX_0F3A08,
1091   PREFIX_0F3A09,
1092   PREFIX_0F3A0A,
1093   PREFIX_0F3A0B,
1094   PREFIX_0F3A0C,
1095   PREFIX_0F3A0D,
1096   PREFIX_0F3A0E,
1097   PREFIX_0F3A14,
1098   PREFIX_0F3A15,
1099   PREFIX_0F3A16,
1100   PREFIX_0F3A17,
1101   PREFIX_0F3A20,
1102   PREFIX_0F3A21,
1103   PREFIX_0F3A22,
1104   PREFIX_0F3A40,
1105   PREFIX_0F3A41,
1106   PREFIX_0F3A42,
1107   PREFIX_0F3A44,
1108   PREFIX_0F3A60,
1109   PREFIX_0F3A61,
1110   PREFIX_0F3A62,
1111   PREFIX_0F3A63,
1112   PREFIX_0F3ACC,
1113   PREFIX_0F3ACE,
1114   PREFIX_0F3ACF,
1115   PREFIX_0F3ADF,
1116   PREFIX_VEX_0F10,
1117   PREFIX_VEX_0F11,
1118   PREFIX_VEX_0F12,
1119   PREFIX_VEX_0F16,
1120   PREFIX_VEX_0F2A,
1121   PREFIX_VEX_0F2C,
1122   PREFIX_VEX_0F2D,
1123   PREFIX_VEX_0F2E,
1124   PREFIX_VEX_0F2F,
1125   PREFIX_VEX_0F41,
1126   PREFIX_VEX_0F42,
1127   PREFIX_VEX_0F44,
1128   PREFIX_VEX_0F45,
1129   PREFIX_VEX_0F46,
1130   PREFIX_VEX_0F47,
1131   PREFIX_VEX_0F4A,
1132   PREFIX_VEX_0F4B,
1133   PREFIX_VEX_0F51,
1134   PREFIX_VEX_0F52,
1135   PREFIX_VEX_0F53,
1136   PREFIX_VEX_0F58,
1137   PREFIX_VEX_0F59,
1138   PREFIX_VEX_0F5A,
1139   PREFIX_VEX_0F5B,
1140   PREFIX_VEX_0F5C,
1141   PREFIX_VEX_0F5D,
1142   PREFIX_VEX_0F5E,
1143   PREFIX_VEX_0F5F,
1144   PREFIX_VEX_0F60,
1145   PREFIX_VEX_0F61,
1146   PREFIX_VEX_0F62,
1147   PREFIX_VEX_0F63,
1148   PREFIX_VEX_0F64,
1149   PREFIX_VEX_0F65,
1150   PREFIX_VEX_0F66,
1151   PREFIX_VEX_0F67,
1152   PREFIX_VEX_0F68,
1153   PREFIX_VEX_0F69,
1154   PREFIX_VEX_0F6A,
1155   PREFIX_VEX_0F6B,
1156   PREFIX_VEX_0F6C,
1157   PREFIX_VEX_0F6D,
1158   PREFIX_VEX_0F6E,
1159   PREFIX_VEX_0F6F,
1160   PREFIX_VEX_0F70,
1161   PREFIX_VEX_0F71_REG_2,
1162   PREFIX_VEX_0F71_REG_4,
1163   PREFIX_VEX_0F71_REG_6,
1164   PREFIX_VEX_0F72_REG_2,
1165   PREFIX_VEX_0F72_REG_4,
1166   PREFIX_VEX_0F72_REG_6,
1167   PREFIX_VEX_0F73_REG_2,
1168   PREFIX_VEX_0F73_REG_3,
1169   PREFIX_VEX_0F73_REG_6,
1170   PREFIX_VEX_0F73_REG_7,
1171   PREFIX_VEX_0F74,
1172   PREFIX_VEX_0F75,
1173   PREFIX_VEX_0F76,
1174   PREFIX_VEX_0F77,
1175   PREFIX_VEX_0F7C,
1176   PREFIX_VEX_0F7D,
1177   PREFIX_VEX_0F7E,
1178   PREFIX_VEX_0F7F,
1179   PREFIX_VEX_0F90,
1180   PREFIX_VEX_0F91,
1181   PREFIX_VEX_0F92,
1182   PREFIX_VEX_0F93,
1183   PREFIX_VEX_0F98,
1184   PREFIX_VEX_0F99,
1185   PREFIX_VEX_0FC2,
1186   PREFIX_VEX_0FC4,
1187   PREFIX_VEX_0FC5,
1188   PREFIX_VEX_0FD0,
1189   PREFIX_VEX_0FD1,
1190   PREFIX_VEX_0FD2,
1191   PREFIX_VEX_0FD3,
1192   PREFIX_VEX_0FD4,
1193   PREFIX_VEX_0FD5,
1194   PREFIX_VEX_0FD6,
1195   PREFIX_VEX_0FD7,
1196   PREFIX_VEX_0FD8,
1197   PREFIX_VEX_0FD9,
1198   PREFIX_VEX_0FDA,
1199   PREFIX_VEX_0FDB,
1200   PREFIX_VEX_0FDC,
1201   PREFIX_VEX_0FDD,
1202   PREFIX_VEX_0FDE,
1203   PREFIX_VEX_0FDF,
1204   PREFIX_VEX_0FE0,
1205   PREFIX_VEX_0FE1,
1206   PREFIX_VEX_0FE2,
1207   PREFIX_VEX_0FE3,
1208   PREFIX_VEX_0FE4,
1209   PREFIX_VEX_0FE5,
1210   PREFIX_VEX_0FE6,
1211   PREFIX_VEX_0FE7,
1212   PREFIX_VEX_0FE8,
1213   PREFIX_VEX_0FE9,
1214   PREFIX_VEX_0FEA,
1215   PREFIX_VEX_0FEB,
1216   PREFIX_VEX_0FEC,
1217   PREFIX_VEX_0FED,
1218   PREFIX_VEX_0FEE,
1219   PREFIX_VEX_0FEF,
1220   PREFIX_VEX_0FF0,
1221   PREFIX_VEX_0FF1,
1222   PREFIX_VEX_0FF2,
1223   PREFIX_VEX_0FF3,
1224   PREFIX_VEX_0FF4,
1225   PREFIX_VEX_0FF5,
1226   PREFIX_VEX_0FF6,
1227   PREFIX_VEX_0FF7,
1228   PREFIX_VEX_0FF8,
1229   PREFIX_VEX_0FF9,
1230   PREFIX_VEX_0FFA,
1231   PREFIX_VEX_0FFB,
1232   PREFIX_VEX_0FFC,
1233   PREFIX_VEX_0FFD,
1234   PREFIX_VEX_0FFE,
1235   PREFIX_VEX_0F3800,
1236   PREFIX_VEX_0F3801,
1237   PREFIX_VEX_0F3802,
1238   PREFIX_VEX_0F3803,
1239   PREFIX_VEX_0F3804,
1240   PREFIX_VEX_0F3805,
1241   PREFIX_VEX_0F3806,
1242   PREFIX_VEX_0F3807,
1243   PREFIX_VEX_0F3808,
1244   PREFIX_VEX_0F3809,
1245   PREFIX_VEX_0F380A,
1246   PREFIX_VEX_0F380B,
1247   PREFIX_VEX_0F380C,
1248   PREFIX_VEX_0F380D,
1249   PREFIX_VEX_0F380E,
1250   PREFIX_VEX_0F380F,
1251   PREFIX_VEX_0F3813,
1252   PREFIX_VEX_0F3816,
1253   PREFIX_VEX_0F3817,
1254   PREFIX_VEX_0F3818,
1255   PREFIX_VEX_0F3819,
1256   PREFIX_VEX_0F381A,
1257   PREFIX_VEX_0F381C,
1258   PREFIX_VEX_0F381D,
1259   PREFIX_VEX_0F381E,
1260   PREFIX_VEX_0F3820,
1261   PREFIX_VEX_0F3821,
1262   PREFIX_VEX_0F3822,
1263   PREFIX_VEX_0F3823,
1264   PREFIX_VEX_0F3824,
1265   PREFIX_VEX_0F3825,
1266   PREFIX_VEX_0F3828,
1267   PREFIX_VEX_0F3829,
1268   PREFIX_VEX_0F382A,
1269   PREFIX_VEX_0F382B,
1270   PREFIX_VEX_0F382C,
1271   PREFIX_VEX_0F382D,
1272   PREFIX_VEX_0F382E,
1273   PREFIX_VEX_0F382F,
1274   PREFIX_VEX_0F3830,
1275   PREFIX_VEX_0F3831,
1276   PREFIX_VEX_0F3832,
1277   PREFIX_VEX_0F3833,
1278   PREFIX_VEX_0F3834,
1279   PREFIX_VEX_0F3835,
1280   PREFIX_VEX_0F3836,
1281   PREFIX_VEX_0F3837,
1282   PREFIX_VEX_0F3838,
1283   PREFIX_VEX_0F3839,
1284   PREFIX_VEX_0F383A,
1285   PREFIX_VEX_0F383B,
1286   PREFIX_VEX_0F383C,
1287   PREFIX_VEX_0F383D,
1288   PREFIX_VEX_0F383E,
1289   PREFIX_VEX_0F383F,
1290   PREFIX_VEX_0F3840,
1291   PREFIX_VEX_0F3841,
1292   PREFIX_VEX_0F3845,
1293   PREFIX_VEX_0F3846,
1294   PREFIX_VEX_0F3847,
1295   PREFIX_VEX_0F3858,
1296   PREFIX_VEX_0F3859,
1297   PREFIX_VEX_0F385A,
1298   PREFIX_VEX_0F3878,
1299   PREFIX_VEX_0F3879,
1300   PREFIX_VEX_0F388C,
1301   PREFIX_VEX_0F388E,
1302   PREFIX_VEX_0F3890,
1303   PREFIX_VEX_0F3891,
1304   PREFIX_VEX_0F3892,
1305   PREFIX_VEX_0F3893,
1306   PREFIX_VEX_0F3896,
1307   PREFIX_VEX_0F3897,
1308   PREFIX_VEX_0F3898,
1309   PREFIX_VEX_0F3899,
1310   PREFIX_VEX_0F389A,
1311   PREFIX_VEX_0F389B,
1312   PREFIX_VEX_0F389C,
1313   PREFIX_VEX_0F389D,
1314   PREFIX_VEX_0F389E,
1315   PREFIX_VEX_0F389F,
1316   PREFIX_VEX_0F38A6,
1317   PREFIX_VEX_0F38A7,
1318   PREFIX_VEX_0F38A8,
1319   PREFIX_VEX_0F38A9,
1320   PREFIX_VEX_0F38AA,
1321   PREFIX_VEX_0F38AB,
1322   PREFIX_VEX_0F38AC,
1323   PREFIX_VEX_0F38AD,
1324   PREFIX_VEX_0F38AE,
1325   PREFIX_VEX_0F38AF,
1326   PREFIX_VEX_0F38B6,
1327   PREFIX_VEX_0F38B7,
1328   PREFIX_VEX_0F38B8,
1329   PREFIX_VEX_0F38B9,
1330   PREFIX_VEX_0F38BA,
1331   PREFIX_VEX_0F38BB,
1332   PREFIX_VEX_0F38BC,
1333   PREFIX_VEX_0F38BD,
1334   PREFIX_VEX_0F38BE,
1335   PREFIX_VEX_0F38BF,
1336   PREFIX_VEX_0F38CF,
1337   PREFIX_VEX_0F38DB,
1338   PREFIX_VEX_0F38DC,
1339   PREFIX_VEX_0F38DD,
1340   PREFIX_VEX_0F38DE,
1341   PREFIX_VEX_0F38DF,
1342   PREFIX_VEX_0F38F2,
1343   PREFIX_VEX_0F38F3_REG_1,
1344   PREFIX_VEX_0F38F3_REG_2,
1345   PREFIX_VEX_0F38F3_REG_3,
1346   PREFIX_VEX_0F38F5,
1347   PREFIX_VEX_0F38F6,
1348   PREFIX_VEX_0F38F7,
1349   PREFIX_VEX_0F3A00,
1350   PREFIX_VEX_0F3A01,
1351   PREFIX_VEX_0F3A02,
1352   PREFIX_VEX_0F3A04,
1353   PREFIX_VEX_0F3A05,
1354   PREFIX_VEX_0F3A06,
1355   PREFIX_VEX_0F3A08,
1356   PREFIX_VEX_0F3A09,
1357   PREFIX_VEX_0F3A0A,
1358   PREFIX_VEX_0F3A0B,
1359   PREFIX_VEX_0F3A0C,
1360   PREFIX_VEX_0F3A0D,
1361   PREFIX_VEX_0F3A0E,
1362   PREFIX_VEX_0F3A0F,
1363   PREFIX_VEX_0F3A14,
1364   PREFIX_VEX_0F3A15,
1365   PREFIX_VEX_0F3A16,
1366   PREFIX_VEX_0F3A17,
1367   PREFIX_VEX_0F3A18,
1368   PREFIX_VEX_0F3A19,
1369   PREFIX_VEX_0F3A1D,
1370   PREFIX_VEX_0F3A20,
1371   PREFIX_VEX_0F3A21,
1372   PREFIX_VEX_0F3A22,
1373   PREFIX_VEX_0F3A30,
1374   PREFIX_VEX_0F3A31,
1375   PREFIX_VEX_0F3A32,
1376   PREFIX_VEX_0F3A33,
1377   PREFIX_VEX_0F3A38,
1378   PREFIX_VEX_0F3A39,
1379   PREFIX_VEX_0F3A40,
1380   PREFIX_VEX_0F3A41,
1381   PREFIX_VEX_0F3A42,
1382   PREFIX_VEX_0F3A44,
1383   PREFIX_VEX_0F3A46,
1384   PREFIX_VEX_0F3A48,
1385   PREFIX_VEX_0F3A49,
1386   PREFIX_VEX_0F3A4A,
1387   PREFIX_VEX_0F3A4B,
1388   PREFIX_VEX_0F3A4C,
1389   PREFIX_VEX_0F3A5C,
1390   PREFIX_VEX_0F3A5D,
1391   PREFIX_VEX_0F3A5E,
1392   PREFIX_VEX_0F3A5F,
1393   PREFIX_VEX_0F3A60,
1394   PREFIX_VEX_0F3A61,
1395   PREFIX_VEX_0F3A62,
1396   PREFIX_VEX_0F3A63,
1397   PREFIX_VEX_0F3A68,
1398   PREFIX_VEX_0F3A69,
1399   PREFIX_VEX_0F3A6A,
1400   PREFIX_VEX_0F3A6B,
1401   PREFIX_VEX_0F3A6C,
1402   PREFIX_VEX_0F3A6D,
1403   PREFIX_VEX_0F3A6E,
1404   PREFIX_VEX_0F3A6F,
1405   PREFIX_VEX_0F3A78,
1406   PREFIX_VEX_0F3A79,
1407   PREFIX_VEX_0F3A7A,
1408   PREFIX_VEX_0F3A7B,
1409   PREFIX_VEX_0F3A7C,
1410   PREFIX_VEX_0F3A7D,
1411   PREFIX_VEX_0F3A7E,
1412   PREFIX_VEX_0F3A7F,
1413   PREFIX_VEX_0F3ACE,
1414   PREFIX_VEX_0F3ACF,
1415   PREFIX_VEX_0F3ADF,
1416   PREFIX_VEX_0F3AF0,
1417
1418   PREFIX_EVEX_0F10,
1419   PREFIX_EVEX_0F11,
1420   PREFIX_EVEX_0F12,
1421   PREFIX_EVEX_0F16,
1422   PREFIX_EVEX_0F2A,
1423   PREFIX_EVEX_0F2C,
1424   PREFIX_EVEX_0F2D,
1425   PREFIX_EVEX_0F2E,
1426   PREFIX_EVEX_0F2F,
1427   PREFIX_EVEX_0F51,
1428   PREFIX_EVEX_0F58,
1429   PREFIX_EVEX_0F59,
1430   PREFIX_EVEX_0F5A,
1431   PREFIX_EVEX_0F5B,
1432   PREFIX_EVEX_0F5C,
1433   PREFIX_EVEX_0F5D,
1434   PREFIX_EVEX_0F5E,
1435   PREFIX_EVEX_0F5F,
1436   PREFIX_EVEX_0F64,
1437   PREFIX_EVEX_0F65,
1438   PREFIX_EVEX_0F66,
1439   PREFIX_EVEX_0F6E,
1440   PREFIX_EVEX_0F6F,
1441   PREFIX_EVEX_0F70,
1442   PREFIX_EVEX_0F71_REG_2,
1443   PREFIX_EVEX_0F71_REG_4,
1444   PREFIX_EVEX_0F71_REG_6,
1445   PREFIX_EVEX_0F72_REG_0,
1446   PREFIX_EVEX_0F72_REG_1,
1447   PREFIX_EVEX_0F72_REG_2,
1448   PREFIX_EVEX_0F72_REG_4,
1449   PREFIX_EVEX_0F72_REG_6,
1450   PREFIX_EVEX_0F73_REG_2,
1451   PREFIX_EVEX_0F73_REG_3,
1452   PREFIX_EVEX_0F73_REG_6,
1453   PREFIX_EVEX_0F73_REG_7,
1454   PREFIX_EVEX_0F74,
1455   PREFIX_EVEX_0F75,
1456   PREFIX_EVEX_0F76,
1457   PREFIX_EVEX_0F78,
1458   PREFIX_EVEX_0F79,
1459   PREFIX_EVEX_0F7A,
1460   PREFIX_EVEX_0F7B,
1461   PREFIX_EVEX_0F7E,
1462   PREFIX_EVEX_0F7F,
1463   PREFIX_EVEX_0FC2,
1464   PREFIX_EVEX_0FC4,
1465   PREFIX_EVEX_0FC5,
1466   PREFIX_EVEX_0FD6,
1467   PREFIX_EVEX_0FDB,
1468   PREFIX_EVEX_0FDF,
1469   PREFIX_EVEX_0FE2,
1470   PREFIX_EVEX_0FE6,
1471   PREFIX_EVEX_0FE7,
1472   PREFIX_EVEX_0FEB,
1473   PREFIX_EVEX_0FEF,
1474   PREFIX_EVEX_0F380D,
1475   PREFIX_EVEX_0F3810,
1476   PREFIX_EVEX_0F3811,
1477   PREFIX_EVEX_0F3812,
1478   PREFIX_EVEX_0F3813,
1479   PREFIX_EVEX_0F3814,
1480   PREFIX_EVEX_0F3815,
1481   PREFIX_EVEX_0F3816,
1482   PREFIX_EVEX_0F3819,
1483   PREFIX_EVEX_0F381A,
1484   PREFIX_EVEX_0F381B,
1485   PREFIX_EVEX_0F381E,
1486   PREFIX_EVEX_0F381F,
1487   PREFIX_EVEX_0F3820,
1488   PREFIX_EVEX_0F3821,
1489   PREFIX_EVEX_0F3822,
1490   PREFIX_EVEX_0F3823,
1491   PREFIX_EVEX_0F3824,
1492   PREFIX_EVEX_0F3825,
1493   PREFIX_EVEX_0F3826,
1494   PREFIX_EVEX_0F3827,
1495   PREFIX_EVEX_0F3828,
1496   PREFIX_EVEX_0F3829,
1497   PREFIX_EVEX_0F382A,
1498   PREFIX_EVEX_0F382C,
1499   PREFIX_EVEX_0F382D,
1500   PREFIX_EVEX_0F3830,
1501   PREFIX_EVEX_0F3831,
1502   PREFIX_EVEX_0F3832,
1503   PREFIX_EVEX_0F3833,
1504   PREFIX_EVEX_0F3834,
1505   PREFIX_EVEX_0F3835,
1506   PREFIX_EVEX_0F3836,
1507   PREFIX_EVEX_0F3837,
1508   PREFIX_EVEX_0F3838,
1509   PREFIX_EVEX_0F3839,
1510   PREFIX_EVEX_0F383A,
1511   PREFIX_EVEX_0F383B,
1512   PREFIX_EVEX_0F383D,
1513   PREFIX_EVEX_0F383F,
1514   PREFIX_EVEX_0F3840,
1515   PREFIX_EVEX_0F3842,
1516   PREFIX_EVEX_0F3843,
1517   PREFIX_EVEX_0F3844,
1518   PREFIX_EVEX_0F3845,
1519   PREFIX_EVEX_0F3846,
1520   PREFIX_EVEX_0F3847,
1521   PREFIX_EVEX_0F384C,
1522   PREFIX_EVEX_0F384D,
1523   PREFIX_EVEX_0F384E,
1524   PREFIX_EVEX_0F384F,
1525   PREFIX_EVEX_0F3850,
1526   PREFIX_EVEX_0F3851,
1527   PREFIX_EVEX_0F3852,
1528   PREFIX_EVEX_0F3853,
1529   PREFIX_EVEX_0F3854,
1530   PREFIX_EVEX_0F3855,
1531   PREFIX_EVEX_0F3859,
1532   PREFIX_EVEX_0F385A,
1533   PREFIX_EVEX_0F385B,
1534   PREFIX_EVEX_0F3862,
1535   PREFIX_EVEX_0F3863,
1536   PREFIX_EVEX_0F3864,
1537   PREFIX_EVEX_0F3865,
1538   PREFIX_EVEX_0F3866,
1539   PREFIX_EVEX_0F3868,
1540   PREFIX_EVEX_0F3870,
1541   PREFIX_EVEX_0F3871,
1542   PREFIX_EVEX_0F3872,
1543   PREFIX_EVEX_0F3873,
1544   PREFIX_EVEX_0F3875,
1545   PREFIX_EVEX_0F3876,
1546   PREFIX_EVEX_0F3877,
1547   PREFIX_EVEX_0F387A,
1548   PREFIX_EVEX_0F387B,
1549   PREFIX_EVEX_0F387C,
1550   PREFIX_EVEX_0F387D,
1551   PREFIX_EVEX_0F387E,
1552   PREFIX_EVEX_0F387F,
1553   PREFIX_EVEX_0F3883,
1554   PREFIX_EVEX_0F3888,
1555   PREFIX_EVEX_0F3889,
1556   PREFIX_EVEX_0F388A,
1557   PREFIX_EVEX_0F388B,
1558   PREFIX_EVEX_0F388D,
1559   PREFIX_EVEX_0F388F,
1560   PREFIX_EVEX_0F3890,
1561   PREFIX_EVEX_0F3891,
1562   PREFIX_EVEX_0F3892,
1563   PREFIX_EVEX_0F3893,
1564   PREFIX_EVEX_0F389A,
1565   PREFIX_EVEX_0F389B,
1566   PREFIX_EVEX_0F38A0,
1567   PREFIX_EVEX_0F38A1,
1568   PREFIX_EVEX_0F38A2,
1569   PREFIX_EVEX_0F38A3,
1570   PREFIX_EVEX_0F38AA,
1571   PREFIX_EVEX_0F38AB,
1572   PREFIX_EVEX_0F38B4,
1573   PREFIX_EVEX_0F38B5,
1574   PREFIX_EVEX_0F38C4,
1575   PREFIX_EVEX_0F38C6_REG_1,
1576   PREFIX_EVEX_0F38C6_REG_2,
1577   PREFIX_EVEX_0F38C6_REG_5,
1578   PREFIX_EVEX_0F38C6_REG_6,
1579   PREFIX_EVEX_0F38C7_REG_1,
1580   PREFIX_EVEX_0F38C7_REG_2,
1581   PREFIX_EVEX_0F38C7_REG_5,
1582   PREFIX_EVEX_0F38C7_REG_6,
1583   PREFIX_EVEX_0F38C8,
1584   PREFIX_EVEX_0F38CA,
1585   PREFIX_EVEX_0F38CB,
1586   PREFIX_EVEX_0F38CC,
1587   PREFIX_EVEX_0F38CD,
1588
1589   PREFIX_EVEX_0F3A00,
1590   PREFIX_EVEX_0F3A01,
1591   PREFIX_EVEX_0F3A03,
1592   PREFIX_EVEX_0F3A05,
1593   PREFIX_EVEX_0F3A08,
1594   PREFIX_EVEX_0F3A09,
1595   PREFIX_EVEX_0F3A0A,
1596   PREFIX_EVEX_0F3A0B,
1597   PREFIX_EVEX_0F3A14,
1598   PREFIX_EVEX_0F3A15,
1599   PREFIX_EVEX_0F3A16,
1600   PREFIX_EVEX_0F3A17,
1601   PREFIX_EVEX_0F3A18,
1602   PREFIX_EVEX_0F3A19,
1603   PREFIX_EVEX_0F3A1A,
1604   PREFIX_EVEX_0F3A1B,
1605   PREFIX_EVEX_0F3A1E,
1606   PREFIX_EVEX_0F3A1F,
1607   PREFIX_EVEX_0F3A20,
1608   PREFIX_EVEX_0F3A21,
1609   PREFIX_EVEX_0F3A22,
1610   PREFIX_EVEX_0F3A23,
1611   PREFIX_EVEX_0F3A25,
1612   PREFIX_EVEX_0F3A26,
1613   PREFIX_EVEX_0F3A27,
1614   PREFIX_EVEX_0F3A38,
1615   PREFIX_EVEX_0F3A39,
1616   PREFIX_EVEX_0F3A3A,
1617   PREFIX_EVEX_0F3A3B,
1618   PREFIX_EVEX_0F3A3E,
1619   PREFIX_EVEX_0F3A3F,
1620   PREFIX_EVEX_0F3A42,
1621   PREFIX_EVEX_0F3A43,
1622   PREFIX_EVEX_0F3A50,
1623   PREFIX_EVEX_0F3A51,
1624   PREFIX_EVEX_0F3A54,
1625   PREFIX_EVEX_0F3A55,
1626   PREFIX_EVEX_0F3A56,
1627   PREFIX_EVEX_0F3A57,
1628   PREFIX_EVEX_0F3A66,
1629   PREFIX_EVEX_0F3A67,
1630   PREFIX_EVEX_0F3A70,
1631   PREFIX_EVEX_0F3A71,
1632   PREFIX_EVEX_0F3A72,
1633   PREFIX_EVEX_0F3A73,
1634 };
1635
1636 enum
1637 {
1638   X86_64_06 = 0,
1639   X86_64_07,
1640   X86_64_0E,
1641   X86_64_16,
1642   X86_64_17,
1643   X86_64_1E,
1644   X86_64_1F,
1645   X86_64_27,
1646   X86_64_2F,
1647   X86_64_37,
1648   X86_64_3F,
1649   X86_64_60,
1650   X86_64_61,
1651   X86_64_62,
1652   X86_64_63,
1653   X86_64_6D,
1654   X86_64_6F,
1655   X86_64_82,
1656   X86_64_9A,
1657   X86_64_C2,
1658   X86_64_C3,
1659   X86_64_C4,
1660   X86_64_C5,
1661   X86_64_CE,
1662   X86_64_D4,
1663   X86_64_D5,
1664   X86_64_E8,
1665   X86_64_E9,
1666   X86_64_EA,
1667   X86_64_0F01_REG_0,
1668   X86_64_0F01_REG_1,
1669   X86_64_0F01_REG_2,
1670   X86_64_0F01_REG_3
1671 };
1672
1673 enum
1674 {
1675   THREE_BYTE_0F38 = 0,
1676   THREE_BYTE_0F3A
1677 };
1678
1679 enum
1680 {
1681   XOP_08 = 0,
1682   XOP_09,
1683   XOP_0A
1684 };
1685
1686 enum
1687 {
1688   VEX_0F = 0,
1689   VEX_0F38,
1690   VEX_0F3A
1691 };
1692
1693 enum
1694 {
1695   EVEX_0F = 0,
1696   EVEX_0F38,
1697   EVEX_0F3A
1698 };
1699
1700 enum
1701 {
1702   VEX_LEN_0F12_P_0_M_0 = 0,
1703   VEX_LEN_0F12_P_0_M_1,
1704 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1705   VEX_LEN_0F13_M_0,
1706   VEX_LEN_0F16_P_0_M_0,
1707   VEX_LEN_0F16_P_0_M_1,
1708 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1709   VEX_LEN_0F17_M_0,
1710   VEX_LEN_0F41_P_0,
1711   VEX_LEN_0F41_P_2,
1712   VEX_LEN_0F42_P_0,
1713   VEX_LEN_0F42_P_2,
1714   VEX_LEN_0F44_P_0,
1715   VEX_LEN_0F44_P_2,
1716   VEX_LEN_0F45_P_0,
1717   VEX_LEN_0F45_P_2,
1718   VEX_LEN_0F46_P_0,
1719   VEX_LEN_0F46_P_2,
1720   VEX_LEN_0F47_P_0,
1721   VEX_LEN_0F47_P_2,
1722   VEX_LEN_0F4A_P_0,
1723   VEX_LEN_0F4A_P_2,
1724   VEX_LEN_0F4B_P_0,
1725   VEX_LEN_0F4B_P_2,
1726   VEX_LEN_0F6E_P_2,
1727   VEX_LEN_0F77_P_0,
1728   VEX_LEN_0F7E_P_1,
1729   VEX_LEN_0F7E_P_2,
1730   VEX_LEN_0F90_P_0,
1731   VEX_LEN_0F90_P_2,
1732   VEX_LEN_0F91_P_0,
1733   VEX_LEN_0F91_P_2,
1734   VEX_LEN_0F92_P_0,
1735   VEX_LEN_0F92_P_2,
1736   VEX_LEN_0F92_P_3,
1737   VEX_LEN_0F93_P_0,
1738   VEX_LEN_0F93_P_2,
1739   VEX_LEN_0F93_P_3,
1740   VEX_LEN_0F98_P_0,
1741   VEX_LEN_0F98_P_2,
1742   VEX_LEN_0F99_P_0,
1743   VEX_LEN_0F99_P_2,
1744   VEX_LEN_0FAE_R_2_M_0,
1745   VEX_LEN_0FAE_R_3_M_0,
1746   VEX_LEN_0FC4_P_2,
1747   VEX_LEN_0FC5_P_2,
1748   VEX_LEN_0FD6_P_2,
1749   VEX_LEN_0FF7_P_2,
1750   VEX_LEN_0F3816_P_2,
1751   VEX_LEN_0F3819_P_2,
1752   VEX_LEN_0F381A_P_2_M_0,
1753   VEX_LEN_0F3836_P_2,
1754   VEX_LEN_0F3841_P_2,
1755   VEX_LEN_0F385A_P_2_M_0,
1756   VEX_LEN_0F38DB_P_2,
1757   VEX_LEN_0F38F2_P_0,
1758   VEX_LEN_0F38F3_R_1_P_0,
1759   VEX_LEN_0F38F3_R_2_P_0,
1760   VEX_LEN_0F38F3_R_3_P_0,
1761   VEX_LEN_0F38F5_P_0,
1762   VEX_LEN_0F38F5_P_1,
1763   VEX_LEN_0F38F5_P_3,
1764   VEX_LEN_0F38F6_P_3,
1765   VEX_LEN_0F38F7_P_0,
1766   VEX_LEN_0F38F7_P_1,
1767   VEX_LEN_0F38F7_P_2,
1768   VEX_LEN_0F38F7_P_3,
1769   VEX_LEN_0F3A00_P_2,
1770   VEX_LEN_0F3A01_P_2,
1771   VEX_LEN_0F3A06_P_2,
1772   VEX_LEN_0F3A14_P_2,
1773   VEX_LEN_0F3A15_P_2,
1774   VEX_LEN_0F3A16_P_2,
1775   VEX_LEN_0F3A17_P_2,
1776   VEX_LEN_0F3A18_P_2,
1777   VEX_LEN_0F3A19_P_2,
1778   VEX_LEN_0F3A20_P_2,
1779   VEX_LEN_0F3A21_P_2,
1780   VEX_LEN_0F3A22_P_2,
1781   VEX_LEN_0F3A30_P_2,
1782   VEX_LEN_0F3A31_P_2,
1783   VEX_LEN_0F3A32_P_2,
1784   VEX_LEN_0F3A33_P_2,
1785   VEX_LEN_0F3A38_P_2,
1786   VEX_LEN_0F3A39_P_2,
1787   VEX_LEN_0F3A41_P_2,
1788   VEX_LEN_0F3A46_P_2,
1789   VEX_LEN_0F3A60_P_2,
1790   VEX_LEN_0F3A61_P_2,
1791   VEX_LEN_0F3A62_P_2,
1792   VEX_LEN_0F3A63_P_2,
1793   VEX_LEN_0F3A6A_P_2,
1794   VEX_LEN_0F3A6B_P_2,
1795   VEX_LEN_0F3A6E_P_2,
1796   VEX_LEN_0F3A6F_P_2,
1797   VEX_LEN_0F3A7A_P_2,
1798   VEX_LEN_0F3A7B_P_2,
1799   VEX_LEN_0F3A7E_P_2,
1800   VEX_LEN_0F3A7F_P_2,
1801   VEX_LEN_0F3ADF_P_2,
1802   VEX_LEN_0F3AF0_P_3,
1803   VEX_LEN_0FXOP_08_CC,
1804   VEX_LEN_0FXOP_08_CD,
1805   VEX_LEN_0FXOP_08_CE,
1806   VEX_LEN_0FXOP_08_CF,
1807   VEX_LEN_0FXOP_08_EC,
1808   VEX_LEN_0FXOP_08_ED,
1809   VEX_LEN_0FXOP_08_EE,
1810   VEX_LEN_0FXOP_08_EF,
1811   VEX_LEN_0FXOP_09_82_W_0,
1812   VEX_LEN_0FXOP_09_83_W_0,
1813 };
1814
1815 enum
1816 {
1817   EVEX_LEN_0F6E_P_2 = 0,
1818   EVEX_LEN_0F7E_P_1,
1819   EVEX_LEN_0F7E_P_2,
1820   EVEX_LEN_0FC4_P_2,
1821   EVEX_LEN_0FC5_P_2,
1822   EVEX_LEN_0FD6_P_2,
1823   EVEX_LEN_0F3816_P_2,
1824   EVEX_LEN_0F3819_P_2_W_0,
1825   EVEX_LEN_0F3819_P_2_W_1,
1826   EVEX_LEN_0F381A_P_2_W_0_M_0,
1827   EVEX_LEN_0F381A_P_2_W_1_M_0,
1828   EVEX_LEN_0F381B_P_2_W_0_M_0,
1829   EVEX_LEN_0F381B_P_2_W_1_M_0,
1830   EVEX_LEN_0F3836_P_2,
1831   EVEX_LEN_0F385A_P_2_W_0_M_0,
1832   EVEX_LEN_0F385A_P_2_W_1_M_0,
1833   EVEX_LEN_0F385B_P_2_W_0_M_0,
1834   EVEX_LEN_0F385B_P_2_W_1_M_0,
1835   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1836   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1837   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1838   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1839   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1840   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1841   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1842   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1843   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1844   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1845   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1846   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1847   EVEX_LEN_0F3A00_P_2_W_1,
1848   EVEX_LEN_0F3A01_P_2_W_1,
1849   EVEX_LEN_0F3A14_P_2,
1850   EVEX_LEN_0F3A15_P_2,
1851   EVEX_LEN_0F3A16_P_2,
1852   EVEX_LEN_0F3A17_P_2,
1853   EVEX_LEN_0F3A18_P_2_W_0,
1854   EVEX_LEN_0F3A18_P_2_W_1,
1855   EVEX_LEN_0F3A19_P_2_W_0,
1856   EVEX_LEN_0F3A19_P_2_W_1,
1857   EVEX_LEN_0F3A1A_P_2_W_0,
1858   EVEX_LEN_0F3A1A_P_2_W_1,
1859   EVEX_LEN_0F3A1B_P_2_W_0,
1860   EVEX_LEN_0F3A1B_P_2_W_1,
1861   EVEX_LEN_0F3A20_P_2,
1862   EVEX_LEN_0F3A21_P_2_W_0,
1863   EVEX_LEN_0F3A22_P_2,
1864   EVEX_LEN_0F3A23_P_2_W_0,
1865   EVEX_LEN_0F3A23_P_2_W_1,
1866   EVEX_LEN_0F3A38_P_2_W_0,
1867   EVEX_LEN_0F3A38_P_2_W_1,
1868   EVEX_LEN_0F3A39_P_2_W_0,
1869   EVEX_LEN_0F3A39_P_2_W_1,
1870   EVEX_LEN_0F3A3A_P_2_W_0,
1871   EVEX_LEN_0F3A3A_P_2_W_1,
1872   EVEX_LEN_0F3A3B_P_2_W_0,
1873   EVEX_LEN_0F3A3B_P_2_W_1,
1874   EVEX_LEN_0F3A43_P_2_W_0,
1875   EVEX_LEN_0F3A43_P_2_W_1
1876 };
1877
1878 enum
1879 {
1880   VEX_W_0F41_P_0_LEN_1 = 0,
1881   VEX_W_0F41_P_2_LEN_1,
1882   VEX_W_0F42_P_0_LEN_1,
1883   VEX_W_0F42_P_2_LEN_1,
1884   VEX_W_0F44_P_0_LEN_0,
1885   VEX_W_0F44_P_2_LEN_0,
1886   VEX_W_0F45_P_0_LEN_1,
1887   VEX_W_0F45_P_2_LEN_1,
1888   VEX_W_0F46_P_0_LEN_1,
1889   VEX_W_0F46_P_2_LEN_1,
1890   VEX_W_0F47_P_0_LEN_1,
1891   VEX_W_0F47_P_2_LEN_1,
1892   VEX_W_0F4A_P_0_LEN_1,
1893   VEX_W_0F4A_P_2_LEN_1,
1894   VEX_W_0F4B_P_0_LEN_1,
1895   VEX_W_0F4B_P_2_LEN_1,
1896   VEX_W_0F90_P_0_LEN_0,
1897   VEX_W_0F90_P_2_LEN_0,
1898   VEX_W_0F91_P_0_LEN_0,
1899   VEX_W_0F91_P_2_LEN_0,
1900   VEX_W_0F92_P_0_LEN_0,
1901   VEX_W_0F92_P_2_LEN_0,
1902   VEX_W_0F93_P_0_LEN_0,
1903   VEX_W_0F93_P_2_LEN_0,
1904   VEX_W_0F98_P_0_LEN_0,
1905   VEX_W_0F98_P_2_LEN_0,
1906   VEX_W_0F99_P_0_LEN_0,
1907   VEX_W_0F99_P_2_LEN_0,
1908   VEX_W_0F380C_P_2,
1909   VEX_W_0F380D_P_2,
1910   VEX_W_0F380E_P_2,
1911   VEX_W_0F380F_P_2,
1912   VEX_W_0F3813_P_2,
1913   VEX_W_0F3816_P_2,
1914   VEX_W_0F3818_P_2,
1915   VEX_W_0F3819_P_2,
1916   VEX_W_0F381A_P_2_M_0,
1917   VEX_W_0F382C_P_2_M_0,
1918   VEX_W_0F382D_P_2_M_0,
1919   VEX_W_0F382E_P_2_M_0,
1920   VEX_W_0F382F_P_2_M_0,
1921   VEX_W_0F3836_P_2,
1922   VEX_W_0F3846_P_2,
1923   VEX_W_0F3858_P_2,
1924   VEX_W_0F3859_P_2,
1925   VEX_W_0F385A_P_2_M_0,
1926   VEX_W_0F3878_P_2,
1927   VEX_W_0F3879_P_2,
1928   VEX_W_0F38CF_P_2,
1929   VEX_W_0F3A00_P_2,
1930   VEX_W_0F3A01_P_2,
1931   VEX_W_0F3A02_P_2,
1932   VEX_W_0F3A04_P_2,
1933   VEX_W_0F3A05_P_2,
1934   VEX_W_0F3A06_P_2,
1935   VEX_W_0F3A18_P_2,
1936   VEX_W_0F3A19_P_2,
1937   VEX_W_0F3A1D_P_2,
1938   VEX_W_0F3A30_P_2_LEN_0,
1939   VEX_W_0F3A31_P_2_LEN_0,
1940   VEX_W_0F3A32_P_2_LEN_0,
1941   VEX_W_0F3A33_P_2_LEN_0,
1942   VEX_W_0F3A38_P_2,
1943   VEX_W_0F3A39_P_2,
1944   VEX_W_0F3A46_P_2,
1945   VEX_W_0F3A4A_P_2,
1946   VEX_W_0F3A4B_P_2,
1947   VEX_W_0F3A4C_P_2,
1948   VEX_W_0F3ACE_P_2,
1949   VEX_W_0F3ACF_P_2,
1950
1951   VEX_W_0FXOP_09_80,
1952   VEX_W_0FXOP_09_81,
1953   VEX_W_0FXOP_09_82,
1954   VEX_W_0FXOP_09_83,
1955
1956   EVEX_W_0F10_P_1,
1957   EVEX_W_0F10_P_3,
1958   EVEX_W_0F11_P_1,
1959   EVEX_W_0F11_P_3,
1960   EVEX_W_0F12_P_0_M_1,
1961   EVEX_W_0F12_P_1,
1962   EVEX_W_0F12_P_3,
1963   EVEX_W_0F16_P_0_M_1,
1964   EVEX_W_0F16_P_1,
1965   EVEX_W_0F2A_P_3,
1966   EVEX_W_0F51_P_1,
1967   EVEX_W_0F51_P_3,
1968   EVEX_W_0F58_P_1,
1969   EVEX_W_0F58_P_3,
1970   EVEX_W_0F59_P_1,
1971   EVEX_W_0F59_P_3,
1972   EVEX_W_0F5A_P_0,
1973   EVEX_W_0F5A_P_1,
1974   EVEX_W_0F5A_P_2,
1975   EVEX_W_0F5A_P_3,
1976   EVEX_W_0F5B_P_0,
1977   EVEX_W_0F5B_P_1,
1978   EVEX_W_0F5B_P_2,
1979   EVEX_W_0F5C_P_1,
1980   EVEX_W_0F5C_P_3,
1981   EVEX_W_0F5D_P_1,
1982   EVEX_W_0F5D_P_3,
1983   EVEX_W_0F5E_P_1,
1984   EVEX_W_0F5E_P_3,
1985   EVEX_W_0F5F_P_1,
1986   EVEX_W_0F5F_P_3,
1987   EVEX_W_0F62,
1988   EVEX_W_0F66_P_2,
1989   EVEX_W_0F6A,
1990   EVEX_W_0F6B,
1991   EVEX_W_0F6C,
1992   EVEX_W_0F6D,
1993   EVEX_W_0F6F_P_1,
1994   EVEX_W_0F6F_P_2,
1995   EVEX_W_0F6F_P_3,
1996   EVEX_W_0F70_P_2,
1997   EVEX_W_0F72_R_2_P_2,
1998   EVEX_W_0F72_R_6_P_2,
1999   EVEX_W_0F73_R_2_P_2,
2000   EVEX_W_0F73_R_6_P_2,
2001   EVEX_W_0F76_P_2,
2002   EVEX_W_0F78_P_0,
2003   EVEX_W_0F78_P_2,
2004   EVEX_W_0F79_P_0,
2005   EVEX_W_0F79_P_2,
2006   EVEX_W_0F7A_P_1,
2007   EVEX_W_0F7A_P_2,
2008   EVEX_W_0F7A_P_3,
2009   EVEX_W_0F7B_P_2,
2010   EVEX_W_0F7B_P_3,
2011   EVEX_W_0F7E_P_1,
2012   EVEX_W_0F7F_P_1,
2013   EVEX_W_0F7F_P_2,
2014   EVEX_W_0F7F_P_3,
2015   EVEX_W_0FC2_P_1,
2016   EVEX_W_0FC2_P_3,
2017   EVEX_W_0FD2,
2018   EVEX_W_0FD3,
2019   EVEX_W_0FD4,
2020   EVEX_W_0FD6_P_2,
2021   EVEX_W_0FE6_P_1,
2022   EVEX_W_0FE6_P_2,
2023   EVEX_W_0FE6_P_3,
2024   EVEX_W_0FE7_P_2,
2025   EVEX_W_0FF2,
2026   EVEX_W_0FF3,
2027   EVEX_W_0FF4,
2028   EVEX_W_0FFA,
2029   EVEX_W_0FFB,
2030   EVEX_W_0FFE,
2031   EVEX_W_0F380D_P_2,
2032   EVEX_W_0F3810_P_1,
2033   EVEX_W_0F3810_P_2,
2034   EVEX_W_0F3811_P_1,
2035   EVEX_W_0F3811_P_2,
2036   EVEX_W_0F3812_P_1,
2037   EVEX_W_0F3812_P_2,
2038   EVEX_W_0F3813_P_1,
2039   EVEX_W_0F3813_P_2,
2040   EVEX_W_0F3814_P_1,
2041   EVEX_W_0F3815_P_1,
2042   EVEX_W_0F3819_P_2,
2043   EVEX_W_0F381A_P_2,
2044   EVEX_W_0F381B_P_2,
2045   EVEX_W_0F381E_P_2,
2046   EVEX_W_0F381F_P_2,
2047   EVEX_W_0F3820_P_1,
2048   EVEX_W_0F3821_P_1,
2049   EVEX_W_0F3822_P_1,
2050   EVEX_W_0F3823_P_1,
2051   EVEX_W_0F3824_P_1,
2052   EVEX_W_0F3825_P_1,
2053   EVEX_W_0F3825_P_2,
2054   EVEX_W_0F3828_P_2,
2055   EVEX_W_0F3829_P_2,
2056   EVEX_W_0F382A_P_1,
2057   EVEX_W_0F382A_P_2,
2058   EVEX_W_0F382B,
2059   EVEX_W_0F3830_P_1,
2060   EVEX_W_0F3831_P_1,
2061   EVEX_W_0F3832_P_1,
2062   EVEX_W_0F3833_P_1,
2063   EVEX_W_0F3834_P_1,
2064   EVEX_W_0F3835_P_1,
2065   EVEX_W_0F3835_P_2,
2066   EVEX_W_0F3837_P_2,
2067   EVEX_W_0F383A_P_1,
2068   EVEX_W_0F3852_P_1,
2069   EVEX_W_0F3859_P_2,
2070   EVEX_W_0F385A_P_2,
2071   EVEX_W_0F385B_P_2,
2072   EVEX_W_0F3862_P_2,
2073   EVEX_W_0F3863_P_2,
2074   EVEX_W_0F3870_P_2,
2075   EVEX_W_0F3872_P_1,
2076   EVEX_W_0F3872_P_2,
2077   EVEX_W_0F3872_P_3,
2078   EVEX_W_0F387A_P_2,
2079   EVEX_W_0F387B_P_2,
2080   EVEX_W_0F3883_P_2,
2081   EVEX_W_0F3891_P_2,
2082   EVEX_W_0F3893_P_2,
2083   EVEX_W_0F38A1_P_2,
2084   EVEX_W_0F38A3_P_2,
2085   EVEX_W_0F38C7_R_1_P_2,
2086   EVEX_W_0F38C7_R_2_P_2,
2087   EVEX_W_0F38C7_R_5_P_2,
2088   EVEX_W_0F38C7_R_6_P_2,
2089
2090   EVEX_W_0F3A00_P_2,
2091   EVEX_W_0F3A01_P_2,
2092   EVEX_W_0F3A05_P_2,
2093   EVEX_W_0F3A08_P_2,
2094   EVEX_W_0F3A09_P_2,
2095   EVEX_W_0F3A0A_P_2,
2096   EVEX_W_0F3A0B_P_2,
2097   EVEX_W_0F3A18_P_2,
2098   EVEX_W_0F3A19_P_2,
2099   EVEX_W_0F3A1A_P_2,
2100   EVEX_W_0F3A1B_P_2,
2101   EVEX_W_0F3A21_P_2,
2102   EVEX_W_0F3A23_P_2,
2103   EVEX_W_0F3A38_P_2,
2104   EVEX_W_0F3A39_P_2,
2105   EVEX_W_0F3A3A_P_2,
2106   EVEX_W_0F3A3B_P_2,
2107   EVEX_W_0F3A42_P_2,
2108   EVEX_W_0F3A43_P_2,
2109   EVEX_W_0F3A70_P_2,
2110   EVEX_W_0F3A72_P_2,
2111 };
2112
2113 typedef void (*op_rtn) (int bytemode, int sizeflag);
2114
2115 struct dis386 {
2116   const char *name;
2117   struct
2118     {
2119       op_rtn rtn;
2120       int bytemode;
2121     } op[MAX_OPERANDS];
2122   unsigned int prefix_requirement;
2123 };
2124
2125 /* Upper case letters in the instruction names here are macros.
2126    'A' => print 'b' if no register operands or suffix_always is true
2127    'B' => print 'b' if suffix_always is true
2128    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2129           size prefix
2130    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2131           suffix_always is true
2132    'E' => print 'e' if 32-bit form of jcxz
2133    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2134    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2135    'H' => print ",pt" or ",pn" branch hint
2136    'I' unused.
2137    'J' unused.
2138    'K' => print 'd' or 'q' if rex prefix is present.
2139    'L' => print 'l' if suffix_always is true
2140    'M' => print 'r' if intel_mnemonic is false.
2141    'N' => print 'n' if instruction has no wait "prefix"
2142    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2143    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2144           or suffix_always is true.  print 'q' if rex prefix is present.
2145    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2146           is true
2147    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2148    'S' => print 'w', 'l' or 'q' if suffix_always is true
2149    'T' => print 'q' in 64bit mode if instruction has no operand size
2150           prefix and behave as 'P' otherwise
2151    'U' => print 'q' in 64bit mode if instruction has no operand size
2152           prefix and behave as 'Q' otherwise
2153    'V' => print 'q' in 64bit mode if instruction has no operand size
2154           prefix and behave as 'S' otherwise
2155    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2156    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2157    'Y' unused.
2158    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2159    '!' => change condition from true to false or from false to true.
2160    '%' => add 1 upper case letter to the macro.
2161    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2162           prefix or suffix_always is true (lcall/ljmp).
2163    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2164           on operand size prefix.
2165    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2166           has no operand size prefix for AMD64 ISA, behave as 'P'
2167           otherwise
2168
2169    2 upper case letter macros:
2170    "XY" => print 'x' or 'y' if suffix_always is true or no register
2171            operands and no broadcast.
2172    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2173            register operands and no broadcast.
2174    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2175    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2176            operand or no operand at all in 64bit mode, or if suffix_always
2177            is true.
2178    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2179    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2180    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2181    "LW" => print 'd', 'q' depending on the VEX.W bit
2182    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2183    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2184            an operand size prefix, or suffix_always is true.  print
2185            'q' if rex prefix is present.
2186
2187    Many of the above letters print nothing in Intel mode.  See "putop"
2188    for the details.
2189
2190    Braces '{' and '}', and vertical bars '|', indicate alternative
2191    mnemonic strings for AT&T and Intel.  */
2192
2193 static const struct dis386 dis386[] = {
2194   /* 00 */
2195   { "addB",             { Ebh1, Gb }, 0 },
2196   { "addS",             { Evh1, Gv }, 0 },
2197   { "addB",             { Gb, EbS }, 0 },
2198   { "addS",             { Gv, EvS }, 0 },
2199   { "addB",             { AL, Ib }, 0 },
2200   { "addS",             { eAX, Iv }, 0 },
2201   { X86_64_TABLE (X86_64_06) },
2202   { X86_64_TABLE (X86_64_07) },
2203   /* 08 */
2204   { "orB",              { Ebh1, Gb }, 0 },
2205   { "orS",              { Evh1, Gv }, 0 },
2206   { "orB",              { Gb, EbS }, 0 },
2207   { "orS",              { Gv, EvS }, 0 },
2208   { "orB",              { AL, Ib }, 0 },
2209   { "orS",              { eAX, Iv }, 0 },
2210   { X86_64_TABLE (X86_64_0E) },
2211   { Bad_Opcode },       /* 0x0f extended opcode escape */
2212   /* 10 */
2213   { "adcB",             { Ebh1, Gb }, 0 },
2214   { "adcS",             { Evh1, Gv }, 0 },
2215   { "adcB",             { Gb, EbS }, 0 },
2216   { "adcS",             { Gv, EvS }, 0 },
2217   { "adcB",             { AL, Ib }, 0 },
2218   { "adcS",             { eAX, Iv }, 0 },
2219   { X86_64_TABLE (X86_64_16) },
2220   { X86_64_TABLE (X86_64_17) },
2221   /* 18 */
2222   { "sbbB",             { Ebh1, Gb }, 0 },
2223   { "sbbS",             { Evh1, Gv }, 0 },
2224   { "sbbB",             { Gb, EbS }, 0 },
2225   { "sbbS",             { Gv, EvS }, 0 },
2226   { "sbbB",             { AL, Ib }, 0 },
2227   { "sbbS",             { eAX, Iv }, 0 },
2228   { X86_64_TABLE (X86_64_1E) },
2229   { X86_64_TABLE (X86_64_1F) },
2230   /* 20 */
2231   { "andB",             { Ebh1, Gb }, 0 },
2232   { "andS",             { Evh1, Gv }, 0 },
2233   { "andB",             { Gb, EbS }, 0 },
2234   { "andS",             { Gv, EvS }, 0 },
2235   { "andB",             { AL, Ib }, 0 },
2236   { "andS",             { eAX, Iv }, 0 },
2237   { Bad_Opcode },       /* SEG ES prefix */
2238   { X86_64_TABLE (X86_64_27) },
2239   /* 28 */
2240   { "subB",             { Ebh1, Gb }, 0 },
2241   { "subS",             { Evh1, Gv }, 0 },
2242   { "subB",             { Gb, EbS }, 0 },
2243   { "subS",             { Gv, EvS }, 0 },
2244   { "subB",             { AL, Ib }, 0 },
2245   { "subS",             { eAX, Iv }, 0 },
2246   { Bad_Opcode },       /* SEG CS prefix */
2247   { X86_64_TABLE (X86_64_2F) },
2248   /* 30 */
2249   { "xorB",             { Ebh1, Gb }, 0 },
2250   { "xorS",             { Evh1, Gv }, 0 },
2251   { "xorB",             { Gb, EbS }, 0 },
2252   { "xorS",             { Gv, EvS }, 0 },
2253   { "xorB",             { AL, Ib }, 0 },
2254   { "xorS",             { eAX, Iv }, 0 },
2255   { Bad_Opcode },       /* SEG SS prefix */
2256   { X86_64_TABLE (X86_64_37) },
2257   /* 38 */
2258   { "cmpB",             { Eb, Gb }, 0 },
2259   { "cmpS",             { Ev, Gv }, 0 },
2260   { "cmpB",             { Gb, EbS }, 0 },
2261   { "cmpS",             { Gv, EvS }, 0 },
2262   { "cmpB",             { AL, Ib }, 0 },
2263   { "cmpS",             { eAX, Iv }, 0 },
2264   { Bad_Opcode },       /* SEG DS prefix */
2265   { X86_64_TABLE (X86_64_3F) },
2266   /* 40 */
2267   { "inc{S|}",          { RMeAX }, 0 },
2268   { "inc{S|}",          { RMeCX }, 0 },
2269   { "inc{S|}",          { RMeDX }, 0 },
2270   { "inc{S|}",          { RMeBX }, 0 },
2271   { "inc{S|}",          { RMeSP }, 0 },
2272   { "inc{S|}",          { RMeBP }, 0 },
2273   { "inc{S|}",          { RMeSI }, 0 },
2274   { "inc{S|}",          { RMeDI }, 0 },
2275   /* 48 */
2276   { "dec{S|}",          { RMeAX }, 0 },
2277   { "dec{S|}",          { RMeCX }, 0 },
2278   { "dec{S|}",          { RMeDX }, 0 },
2279   { "dec{S|}",          { RMeBX }, 0 },
2280   { "dec{S|}",          { RMeSP }, 0 },
2281   { "dec{S|}",          { RMeBP }, 0 },
2282   { "dec{S|}",          { RMeSI }, 0 },
2283   { "dec{S|}",          { RMeDI }, 0 },
2284   /* 50 */
2285   { "pushV",            { RMrAX }, 0 },
2286   { "pushV",            { RMrCX }, 0 },
2287   { "pushV",            { RMrDX }, 0 },
2288   { "pushV",            { RMrBX }, 0 },
2289   { "pushV",            { RMrSP }, 0 },
2290   { "pushV",            { RMrBP }, 0 },
2291   { "pushV",            { RMrSI }, 0 },
2292   { "pushV",            { RMrDI }, 0 },
2293   /* 58 */
2294   { "popV",             { RMrAX }, 0 },
2295   { "popV",             { RMrCX }, 0 },
2296   { "popV",             { RMrDX }, 0 },
2297   { "popV",             { RMrBX }, 0 },
2298   { "popV",             { RMrSP }, 0 },
2299   { "popV",             { RMrBP }, 0 },
2300   { "popV",             { RMrSI }, 0 },
2301   { "popV",             { RMrDI }, 0 },
2302   /* 60 */
2303   { X86_64_TABLE (X86_64_60) },
2304   { X86_64_TABLE (X86_64_61) },
2305   { X86_64_TABLE (X86_64_62) },
2306   { X86_64_TABLE (X86_64_63) },
2307   { Bad_Opcode },       /* seg fs */
2308   { Bad_Opcode },       /* seg gs */
2309   { Bad_Opcode },       /* op size prefix */
2310   { Bad_Opcode },       /* adr size prefix */
2311   /* 68 */
2312   { "pushT",            { sIv }, 0 },
2313   { "imulS",            { Gv, Ev, Iv }, 0 },
2314   { "pushT",            { sIbT }, 0 },
2315   { "imulS",            { Gv, Ev, sIb }, 0 },
2316   { "ins{b|}",          { Ybr, indirDX }, 0 },
2317   { X86_64_TABLE (X86_64_6D) },
2318   { "outs{b|}",         { indirDXr, Xb }, 0 },
2319   { X86_64_TABLE (X86_64_6F) },
2320   /* 70 */
2321   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2322   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2323   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2324   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2325   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2326   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2327   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2328   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2329   /* 78 */
2330   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2331   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2332   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2333   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2334   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2335   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2336   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2337   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2338   /* 80 */
2339   { REG_TABLE (REG_80) },
2340   { REG_TABLE (REG_81) },
2341   { X86_64_TABLE (X86_64_82) },
2342   { REG_TABLE (REG_83) },
2343   { "testB",            { Eb, Gb }, 0 },
2344   { "testS",            { Ev, Gv }, 0 },
2345   { "xchgB",            { Ebh2, Gb }, 0 },
2346   { "xchgS",            { Evh2, Gv }, 0 },
2347   /* 88 */
2348   { "movB",             { Ebh3, Gb }, 0 },
2349   { "movS",             { Evh3, Gv }, 0 },
2350   { "movB",             { Gb, EbS }, 0 },
2351   { "movS",             { Gv, EvS }, 0 },
2352   { "movD",             { Sv, Sw }, 0 },
2353   { MOD_TABLE (MOD_8D) },
2354   { "movD",             { Sw, Sv }, 0 },
2355   { REG_TABLE (REG_8F) },
2356   /* 90 */
2357   { PREFIX_TABLE (PREFIX_90) },
2358   { "xchgS",            { RMeCX, eAX }, 0 },
2359   { "xchgS",            { RMeDX, eAX }, 0 },
2360   { "xchgS",            { RMeBX, eAX }, 0 },
2361   { "xchgS",            { RMeSP, eAX }, 0 },
2362   { "xchgS",            { RMeBP, eAX }, 0 },
2363   { "xchgS",            { RMeSI, eAX }, 0 },
2364   { "xchgS",            { RMeDI, eAX }, 0 },
2365   /* 98 */
2366   { "cW{t|}R",          { XX }, 0 },
2367   { "cR{t|}O",          { XX }, 0 },
2368   { X86_64_TABLE (X86_64_9A) },
2369   { Bad_Opcode },       /* fwait */
2370   { "pushfT",           { XX }, 0 },
2371   { "popfT",            { XX }, 0 },
2372   { "sahf",             { XX }, 0 },
2373   { "lahf",             { XX }, 0 },
2374   /* a0 */
2375   { "mov%LB",           { AL, Ob }, 0 },
2376   { "mov%LS",           { eAX, Ov }, 0 },
2377   { "mov%LB",           { Ob, AL }, 0 },
2378   { "mov%LS",           { Ov, eAX }, 0 },
2379   { "movs{b|}",         { Ybr, Xb }, 0 },
2380   { "movs{R|}",         { Yvr, Xv }, 0 },
2381   { "cmps{b|}",         { Xb, Yb }, 0 },
2382   { "cmps{R|}",         { Xv, Yv }, 0 },
2383   /* a8 */
2384   { "testB",            { AL, Ib }, 0 },
2385   { "testS",            { eAX, Iv }, 0 },
2386   { "stosB",            { Ybr, AL }, 0 },
2387   { "stosS",            { Yvr, eAX }, 0 },
2388   { "lodsB",            { ALr, Xb }, 0 },
2389   { "lodsS",            { eAXr, Xv }, 0 },
2390   { "scasB",            { AL, Yb }, 0 },
2391   { "scasS",            { eAX, Yv }, 0 },
2392   /* b0 */
2393   { "movB",             { RMAL, Ib }, 0 },
2394   { "movB",             { RMCL, Ib }, 0 },
2395   { "movB",             { RMDL, Ib }, 0 },
2396   { "movB",             { RMBL, Ib }, 0 },
2397   { "movB",             { RMAH, Ib }, 0 },
2398   { "movB",             { RMCH, Ib }, 0 },
2399   { "movB",             { RMDH, Ib }, 0 },
2400   { "movB",             { RMBH, Ib }, 0 },
2401   /* b8 */
2402   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2403   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2404   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2405   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2406   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2407   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2408   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2409   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2410   /* c0 */
2411   { REG_TABLE (REG_C0) },
2412   { REG_TABLE (REG_C1) },
2413   { X86_64_TABLE (X86_64_C2) },
2414   { X86_64_TABLE (X86_64_C3) },
2415   { X86_64_TABLE (X86_64_C4) },
2416   { X86_64_TABLE (X86_64_C5) },
2417   { REG_TABLE (REG_C6) },
2418   { REG_TABLE (REG_C7) },
2419   /* c8 */
2420   { "enterT",           { Iw, Ib }, 0 },
2421   { "leaveT",           { XX }, 0 },
2422   { "{l|}ret{|f}P",     { Iw }, 0 },
2423   { "{l|}ret{|f}P",     { XX }, 0 },
2424   { "int3",             { XX }, 0 },
2425   { "int",              { Ib }, 0 },
2426   { X86_64_TABLE (X86_64_CE) },
2427   { "iret%LP",          { XX }, 0 },
2428   /* d0 */
2429   { REG_TABLE (REG_D0) },
2430   { REG_TABLE (REG_D1) },
2431   { REG_TABLE (REG_D2) },
2432   { REG_TABLE (REG_D3) },
2433   { X86_64_TABLE (X86_64_D4) },
2434   { X86_64_TABLE (X86_64_D5) },
2435   { Bad_Opcode },
2436   { "xlat",             { DSBX }, 0 },
2437   /* d8 */
2438   { FLOAT },
2439   { FLOAT },
2440   { FLOAT },
2441   { FLOAT },
2442   { FLOAT },
2443   { FLOAT },
2444   { FLOAT },
2445   { FLOAT },
2446   /* e0 */
2447   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2448   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2449   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2450   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2451   { "inB",              { AL, Ib }, 0 },
2452   { "inG",              { zAX, Ib }, 0 },
2453   { "outB",             { Ib, AL }, 0 },
2454   { "outG",             { Ib, zAX }, 0 },
2455   /* e8 */
2456   { X86_64_TABLE (X86_64_E8) },
2457   { X86_64_TABLE (X86_64_E9) },
2458   { X86_64_TABLE (X86_64_EA) },
2459   { "jmp",              { Jb, BND }, 0 },
2460   { "inB",              { AL, indirDX }, 0 },
2461   { "inG",              { zAX, indirDX }, 0 },
2462   { "outB",             { indirDX, AL }, 0 },
2463   { "outG",             { indirDX, zAX }, 0 },
2464   /* f0 */
2465   { Bad_Opcode },       /* lock prefix */
2466   { "icebp",            { XX }, 0 },
2467   { Bad_Opcode },       /* repne */
2468   { Bad_Opcode },       /* repz */
2469   { "hlt",              { XX }, 0 },
2470   { "cmc",              { XX }, 0 },
2471   { REG_TABLE (REG_F6) },
2472   { REG_TABLE (REG_F7) },
2473   /* f8 */
2474   { "clc",              { XX }, 0 },
2475   { "stc",              { XX }, 0 },
2476   { "cli",              { XX }, 0 },
2477   { "sti",              { XX }, 0 },
2478   { "cld",              { XX }, 0 },
2479   { "std",              { XX }, 0 },
2480   { REG_TABLE (REG_FE) },
2481   { REG_TABLE (REG_FF) },
2482 };
2483
2484 static const struct dis386 dis386_twobyte[] = {
2485   /* 00 */
2486   { REG_TABLE (REG_0F00 ) },
2487   { REG_TABLE (REG_0F01 ) },
2488   { "larS",             { Gv, Ew }, 0 },
2489   { "lslS",             { Gv, Ew }, 0 },
2490   { Bad_Opcode },
2491   { "syscall",          { XX }, 0 },
2492   { "clts",             { XX }, 0 },
2493   { "sysret%LQ",                { XX }, 0 },
2494   /* 08 */
2495   { "invd",             { XX }, 0 },
2496   { PREFIX_TABLE (PREFIX_0F09) },
2497   { Bad_Opcode },
2498   { "ud2",              { XX }, 0 },
2499   { Bad_Opcode },
2500   { REG_TABLE (REG_0F0D) },
2501   { "femms",            { XX }, 0 },
2502   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2503   /* 10 */
2504   { PREFIX_TABLE (PREFIX_0F10) },
2505   { PREFIX_TABLE (PREFIX_0F11) },
2506   { PREFIX_TABLE (PREFIX_0F12) },
2507   { MOD_TABLE (MOD_0F13) },
2508   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2509   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2510   { PREFIX_TABLE (PREFIX_0F16) },
2511   { MOD_TABLE (MOD_0F17) },
2512   /* 18 */
2513   { REG_TABLE (REG_0F18) },
2514   { "nopQ",             { Ev }, 0 },
2515   { PREFIX_TABLE (PREFIX_0F1A) },
2516   { PREFIX_TABLE (PREFIX_0F1B) },
2517   { PREFIX_TABLE (PREFIX_0F1C) },
2518   { "nopQ",             { Ev }, 0 },
2519   { PREFIX_TABLE (PREFIX_0F1E) },
2520   { "nopQ",             { Ev }, 0 },
2521   /* 20 */
2522   { "movZ",             { Rm, Cm }, 0 },
2523   { "movZ",             { Rm, Dm }, 0 },
2524   { "movZ",             { Cm, Rm }, 0 },
2525   { "movZ",             { Dm, Rm }, 0 },
2526   { MOD_TABLE (MOD_0F24) },
2527   { Bad_Opcode },
2528   { MOD_TABLE (MOD_0F26) },
2529   { Bad_Opcode },
2530   /* 28 */
2531   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2532   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2533   { PREFIX_TABLE (PREFIX_0F2A) },
2534   { PREFIX_TABLE (PREFIX_0F2B) },
2535   { PREFIX_TABLE (PREFIX_0F2C) },
2536   { PREFIX_TABLE (PREFIX_0F2D) },
2537   { PREFIX_TABLE (PREFIX_0F2E) },
2538   { PREFIX_TABLE (PREFIX_0F2F) },
2539   /* 30 */
2540   { "wrmsr",            { XX }, 0 },
2541   { "rdtsc",            { XX }, 0 },
2542   { "rdmsr",            { XX }, 0 },
2543   { "rdpmc",            { XX }, 0 },
2544   { "sysenter",         { SEP }, 0 },
2545   { "sysexit",          { SEP }, 0 },
2546   { Bad_Opcode },
2547   { "getsec",           { XX }, 0 },
2548   /* 38 */
2549   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2550   { Bad_Opcode },
2551   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2552   { Bad_Opcode },
2553   { Bad_Opcode },
2554   { Bad_Opcode },
2555   { Bad_Opcode },
2556   { Bad_Opcode },
2557   /* 40 */
2558   { "cmovoS",           { Gv, Ev }, 0 },
2559   { "cmovnoS",          { Gv, Ev }, 0 },
2560   { "cmovbS",           { Gv, Ev }, 0 },
2561   { "cmovaeS",          { Gv, Ev }, 0 },
2562   { "cmoveS",           { Gv, Ev }, 0 },
2563   { "cmovneS",          { Gv, Ev }, 0 },
2564   { "cmovbeS",          { Gv, Ev }, 0 },
2565   { "cmovaS",           { Gv, Ev }, 0 },
2566   /* 48 */
2567   { "cmovsS",           { Gv, Ev }, 0 },
2568   { "cmovnsS",          { Gv, Ev }, 0 },
2569   { "cmovpS",           { Gv, Ev }, 0 },
2570   { "cmovnpS",          { Gv, Ev }, 0 },
2571   { "cmovlS",           { Gv, Ev }, 0 },
2572   { "cmovgeS",          { Gv, Ev }, 0 },
2573   { "cmovleS",          { Gv, Ev }, 0 },
2574   { "cmovgS",           { Gv, Ev }, 0 },
2575   /* 50 */
2576   { MOD_TABLE (MOD_0F50) },
2577   { PREFIX_TABLE (PREFIX_0F51) },
2578   { PREFIX_TABLE (PREFIX_0F52) },
2579   { PREFIX_TABLE (PREFIX_0F53) },
2580   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2581   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2582   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2583   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2584   /* 58 */
2585   { PREFIX_TABLE (PREFIX_0F58) },
2586   { PREFIX_TABLE (PREFIX_0F59) },
2587   { PREFIX_TABLE (PREFIX_0F5A) },
2588   { PREFIX_TABLE (PREFIX_0F5B) },
2589   { PREFIX_TABLE (PREFIX_0F5C) },
2590   { PREFIX_TABLE (PREFIX_0F5D) },
2591   { PREFIX_TABLE (PREFIX_0F5E) },
2592   { PREFIX_TABLE (PREFIX_0F5F) },
2593   /* 60 */
2594   { PREFIX_TABLE (PREFIX_0F60) },
2595   { PREFIX_TABLE (PREFIX_0F61) },
2596   { PREFIX_TABLE (PREFIX_0F62) },
2597   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2598   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2599   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2600   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2601   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2602   /* 68 */
2603   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2604   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2605   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2606   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2607   { PREFIX_TABLE (PREFIX_0F6C) },
2608   { PREFIX_TABLE (PREFIX_0F6D) },
2609   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2610   { PREFIX_TABLE (PREFIX_0F6F) },
2611   /* 70 */
2612   { PREFIX_TABLE (PREFIX_0F70) },
2613   { REG_TABLE (REG_0F71) },
2614   { REG_TABLE (REG_0F72) },
2615   { REG_TABLE (REG_0F73) },
2616   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2617   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2618   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2619   { "emms",             { XX }, PREFIX_OPCODE },
2620   /* 78 */
2621   { PREFIX_TABLE (PREFIX_0F78) },
2622   { PREFIX_TABLE (PREFIX_0F79) },
2623   { Bad_Opcode },
2624   { Bad_Opcode },
2625   { PREFIX_TABLE (PREFIX_0F7C) },
2626   { PREFIX_TABLE (PREFIX_0F7D) },
2627   { PREFIX_TABLE (PREFIX_0F7E) },
2628   { PREFIX_TABLE (PREFIX_0F7F) },
2629   /* 80 */
2630   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2631   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2632   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2633   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2634   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2635   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2636   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2637   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2638   /* 88 */
2639   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2640   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2641   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2642   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2643   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2644   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2645   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2646   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2647   /* 90 */
2648   { "seto",             { Eb }, 0 },
2649   { "setno",            { Eb }, 0 },
2650   { "setb",             { Eb }, 0 },
2651   { "setae",            { Eb }, 0 },
2652   { "sete",             { Eb }, 0 },
2653   { "setne",            { Eb }, 0 },
2654   { "setbe",            { Eb }, 0 },
2655   { "seta",             { Eb }, 0 },
2656   /* 98 */
2657   { "sets",             { Eb }, 0 },
2658   { "setns",            { Eb }, 0 },
2659   { "setp",             { Eb }, 0 },
2660   { "setnp",            { Eb }, 0 },
2661   { "setl",             { Eb }, 0 },
2662   { "setge",            { Eb }, 0 },
2663   { "setle",            { Eb }, 0 },
2664   { "setg",             { Eb }, 0 },
2665   /* a0 */
2666   { "pushT",            { fs }, 0 },
2667   { "popT",             { fs }, 0 },
2668   { "cpuid",            { XX }, 0 },
2669   { "btS",              { Ev, Gv }, 0 },
2670   { "shldS",            { Ev, Gv, Ib }, 0 },
2671   { "shldS",            { Ev, Gv, CL }, 0 },
2672   { REG_TABLE (REG_0FA6) },
2673   { REG_TABLE (REG_0FA7) },
2674   /* a8 */
2675   { "pushT",            { gs }, 0 },
2676   { "popT",             { gs }, 0 },
2677   { "rsm",              { XX }, 0 },
2678   { "btsS",             { Evh1, Gv }, 0 },
2679   { "shrdS",            { Ev, Gv, Ib }, 0 },
2680   { "shrdS",            { Ev, Gv, CL }, 0 },
2681   { REG_TABLE (REG_0FAE) },
2682   { "imulS",            { Gv, Ev }, 0 },
2683   /* b0 */
2684   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2685   { "cmpxchgS",         { Evh1, Gv }, 0 },
2686   { MOD_TABLE (MOD_0FB2) },
2687   { "btrS",             { Evh1, Gv }, 0 },
2688   { MOD_TABLE (MOD_0FB4) },
2689   { MOD_TABLE (MOD_0FB5) },
2690   { "movz{bR|x}",       { Gv, Eb }, 0 },
2691   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2692   /* b8 */
2693   { PREFIX_TABLE (PREFIX_0FB8) },
2694   { "ud1S",             { Gv, Ev }, 0 },
2695   { REG_TABLE (REG_0FBA) },
2696   { "btcS",             { Evh1, Gv }, 0 },
2697   { PREFIX_TABLE (PREFIX_0FBC) },
2698   { PREFIX_TABLE (PREFIX_0FBD) },
2699   { "movs{bR|x}",       { Gv, Eb }, 0 },
2700   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2701   /* c0 */
2702   { "xaddB",            { Ebh1, Gb }, 0 },
2703   { "xaddS",            { Evh1, Gv }, 0 },
2704   { PREFIX_TABLE (PREFIX_0FC2) },
2705   { MOD_TABLE (MOD_0FC3) },
2706   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2707   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2708   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2709   { REG_TABLE (REG_0FC7) },
2710   /* c8 */
2711   { "bswap",            { RMeAX }, 0 },
2712   { "bswap",            { RMeCX }, 0 },
2713   { "bswap",            { RMeDX }, 0 },
2714   { "bswap",            { RMeBX }, 0 },
2715   { "bswap",            { RMeSP }, 0 },
2716   { "bswap",            { RMeBP }, 0 },
2717   { "bswap",            { RMeSI }, 0 },
2718   { "bswap",            { RMeDI }, 0 },
2719   /* d0 */
2720   { PREFIX_TABLE (PREFIX_0FD0) },
2721   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2722   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2723   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2724   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2725   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2726   { PREFIX_TABLE (PREFIX_0FD6) },
2727   { MOD_TABLE (MOD_0FD7) },
2728   /* d8 */
2729   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2730   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2731   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2732   { "pand",             { MX, EM }, PREFIX_OPCODE },
2733   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2734   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2735   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2736   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2737   /* e0 */
2738   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2739   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2740   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2741   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2742   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2743   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2744   { PREFIX_TABLE (PREFIX_0FE6) },
2745   { PREFIX_TABLE (PREFIX_0FE7) },
2746   /* e8 */
2747   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2748   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2749   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2750   { "por",              { MX, EM }, PREFIX_OPCODE },
2751   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2752   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2753   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2754   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2755   /* f0 */
2756   { PREFIX_TABLE (PREFIX_0FF0) },
2757   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2758   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2759   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2760   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2761   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2762   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2763   { PREFIX_TABLE (PREFIX_0FF7) },
2764   /* f8 */
2765   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2766   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2767   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2768   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2769   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2770   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2771   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2772   { "ud0S",             { Gv, Ev }, 0 },
2773 };
2774
2775 static const unsigned char onebyte_has_modrm[256] = {
2776   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2777   /*       -------------------------------        */
2778   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2779   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2780   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2781   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2782   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2783   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2784   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2785   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2786   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2787   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2788   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2789   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2790   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2791   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2792   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2793   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2794   /*       -------------------------------        */
2795   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2796 };
2797
2798 static const unsigned char twobyte_has_modrm[256] = {
2799   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2800   /*       -------------------------------        */
2801   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2802   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2803   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2804   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2805   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2806   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2807   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2808   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2809   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2810   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2811   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2812   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2813   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2814   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2815   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2816   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2817   /*       -------------------------------        */
2818   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2819 };
2820
2821 static char obuf[100];
2822 static char *obufp;
2823 static char *mnemonicendp;
2824 static char scratchbuf[100];
2825 static unsigned char *start_codep;
2826 static unsigned char *insn_codep;
2827 static unsigned char *codep;
2828 static unsigned char *end_codep;
2829 static int last_lock_prefix;
2830 static int last_repz_prefix;
2831 static int last_repnz_prefix;
2832 static int last_data_prefix;
2833 static int last_addr_prefix;
2834 static int last_rex_prefix;
2835 static int last_seg_prefix;
2836 static int fwait_prefix;
2837 /* The active segment register prefix.  */
2838 static int active_seg_prefix;
2839 #define MAX_CODE_LENGTH 15
2840 /* We can up to 14 prefixes since the maximum instruction length is
2841    15bytes.  */
2842 static int all_prefixes[MAX_CODE_LENGTH - 1];
2843 static disassemble_info *the_info;
2844 static struct
2845   {
2846     int mod;
2847     int reg;
2848     int rm;
2849   }
2850 modrm;
2851 static unsigned char need_modrm;
2852 static struct
2853   {
2854     int scale;
2855     int index;
2856     int base;
2857   }
2858 sib;
2859 static struct
2860   {
2861     int register_specifier;
2862     int length;
2863     int prefix;
2864     int w;
2865     int evex;
2866     int r;
2867     int v;
2868     int mask_register_specifier;
2869     int zeroing;
2870     int ll;
2871     int b;
2872   }
2873 vex;
2874 static unsigned char need_vex;
2875 static unsigned char need_vex_reg;
2876
2877 struct op
2878   {
2879     const char *name;
2880     unsigned int len;
2881   };
2882
2883 /* If we are accessing mod/rm/reg without need_modrm set, then the
2884    values are stale.  Hitting this abort likely indicates that you
2885    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2886 #define MODRM_CHECK  if (!need_modrm) abort ()
2887
2888 static const char **names64;
2889 static const char **names32;
2890 static const char **names16;
2891 static const char **names8;
2892 static const char **names8rex;
2893 static const char **names_seg;
2894 static const char *index64;
2895 static const char *index32;
2896 static const char **index16;
2897 static const char **names_bnd;
2898
2899 static const char *intel_names64[] = {
2900   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2901   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2902 };
2903 static const char *intel_names32[] = {
2904   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2905   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2906 };
2907 static const char *intel_names16[] = {
2908   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2909   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2910 };
2911 static const char *intel_names8[] = {
2912   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2913 };
2914 static const char *intel_names8rex[] = {
2915   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2916   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2917 };
2918 static const char *intel_names_seg[] = {
2919   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2920 };
2921 static const char *intel_index64 = "riz";
2922 static const char *intel_index32 = "eiz";
2923 static const char *intel_index16[] = {
2924   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2925 };
2926
2927 static const char *att_names64[] = {
2928   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2929   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2930 };
2931 static const char *att_names32[] = {
2932   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2933   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2934 };
2935 static const char *att_names16[] = {
2936   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2937   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2938 };
2939 static const char *att_names8[] = {
2940   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2941 };
2942 static const char *att_names8rex[] = {
2943   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2944   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2945 };
2946 static const char *att_names_seg[] = {
2947   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2948 };
2949 static const char *att_index64 = "%riz";
2950 static const char *att_index32 = "%eiz";
2951 static const char *att_index16[] = {
2952   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2953 };
2954
2955 static const char **names_mm;
2956 static const char *intel_names_mm[] = {
2957   "mm0", "mm1", "mm2", "mm3",
2958   "mm4", "mm5", "mm6", "mm7"
2959 };
2960 static const char *att_names_mm[] = {
2961   "%mm0", "%mm1", "%mm2", "%mm3",
2962   "%mm4", "%mm5", "%mm6", "%mm7"
2963 };
2964
2965 static const char *intel_names_bnd[] = {
2966   "bnd0", "bnd1", "bnd2", "bnd3"
2967 };
2968
2969 static const char *att_names_bnd[] = {
2970   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2971 };
2972
2973 static const char **names_xmm;
2974 static const char *intel_names_xmm[] = {
2975   "xmm0", "xmm1", "xmm2", "xmm3",
2976   "xmm4", "xmm5", "xmm6", "xmm7",
2977   "xmm8", "xmm9", "xmm10", "xmm11",
2978   "xmm12", "xmm13", "xmm14", "xmm15",
2979   "xmm16", "xmm17", "xmm18", "xmm19",
2980   "xmm20", "xmm21", "xmm22", "xmm23",
2981   "xmm24", "xmm25", "xmm26", "xmm27",
2982   "xmm28", "xmm29", "xmm30", "xmm31"
2983 };
2984 static const char *att_names_xmm[] = {
2985   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2986   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2987   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2988   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2989   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2990   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2991   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2992   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2993 };
2994
2995 static const char **names_ymm;
2996 static const char *intel_names_ymm[] = {
2997   "ymm0", "ymm1", "ymm2", "ymm3",
2998   "ymm4", "ymm5", "ymm6", "ymm7",
2999   "ymm8", "ymm9", "ymm10", "ymm11",
3000   "ymm12", "ymm13", "ymm14", "ymm15",
3001   "ymm16", "ymm17", "ymm18", "ymm19",
3002   "ymm20", "ymm21", "ymm22", "ymm23",
3003   "ymm24", "ymm25", "ymm26", "ymm27",
3004   "ymm28", "ymm29", "ymm30", "ymm31"
3005 };
3006 static const char *att_names_ymm[] = {
3007   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3008   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3009   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3010   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3011   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3012   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3013   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3014   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3015 };
3016
3017 static const char **names_zmm;
3018 static const char *intel_names_zmm[] = {
3019   "zmm0", "zmm1", "zmm2", "zmm3",
3020   "zmm4", "zmm5", "zmm6", "zmm7",
3021   "zmm8", "zmm9", "zmm10", "zmm11",
3022   "zmm12", "zmm13", "zmm14", "zmm15",
3023   "zmm16", "zmm17", "zmm18", "zmm19",
3024   "zmm20", "zmm21", "zmm22", "zmm23",
3025   "zmm24", "zmm25", "zmm26", "zmm27",
3026   "zmm28", "zmm29", "zmm30", "zmm31"
3027 };
3028 static const char *att_names_zmm[] = {
3029   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3030   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3031   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3032   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3033   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3034   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3035   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3036   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3037 };
3038
3039 static const char **names_mask;
3040 static const char *intel_names_mask[] = {
3041   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3042 };
3043 static const char *att_names_mask[] = {
3044   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3045 };
3046
3047 static const char *names_rounding[] =
3048 {
3049   "{rn-sae}",
3050   "{rd-sae}",
3051   "{ru-sae}",
3052   "{rz-sae}"
3053 };
3054
3055 static const struct dis386 reg_table[][8] = {
3056   /* REG_80 */
3057   {
3058     { "addA",   { Ebh1, Ib }, 0 },
3059     { "orA",    { Ebh1, Ib }, 0 },
3060     { "adcA",   { Ebh1, Ib }, 0 },
3061     { "sbbA",   { Ebh1, Ib }, 0 },
3062     { "andA",   { Ebh1, Ib }, 0 },
3063     { "subA",   { Ebh1, Ib }, 0 },
3064     { "xorA",   { Ebh1, Ib }, 0 },
3065     { "cmpA",   { Eb, Ib }, 0 },
3066   },
3067   /* REG_81 */
3068   {
3069     { "addQ",   { Evh1, Iv }, 0 },
3070     { "orQ",    { Evh1, Iv }, 0 },
3071     { "adcQ",   { Evh1, Iv }, 0 },
3072     { "sbbQ",   { Evh1, Iv }, 0 },
3073     { "andQ",   { Evh1, Iv }, 0 },
3074     { "subQ",   { Evh1, Iv }, 0 },
3075     { "xorQ",   { Evh1, Iv }, 0 },
3076     { "cmpQ",   { Ev, Iv }, 0 },
3077   },
3078   /* REG_83 */
3079   {
3080     { "addQ",   { Evh1, sIb }, 0 },
3081     { "orQ",    { Evh1, sIb }, 0 },
3082     { "adcQ",   { Evh1, sIb }, 0 },
3083     { "sbbQ",   { Evh1, sIb }, 0 },
3084     { "andQ",   { Evh1, sIb }, 0 },
3085     { "subQ",   { Evh1, sIb }, 0 },
3086     { "xorQ",   { Evh1, sIb }, 0 },
3087     { "cmpQ",   { Ev, sIb }, 0 },
3088   },
3089   /* REG_8F */
3090   {
3091     { "popU",   { stackEv }, 0 },
3092     { XOP_8F_TABLE (XOP_09) },
3093     { Bad_Opcode },
3094     { Bad_Opcode },
3095     { Bad_Opcode },
3096     { XOP_8F_TABLE (XOP_09) },
3097   },
3098   /* REG_C0 */
3099   {
3100     { "rolA",   { Eb, Ib }, 0 },
3101     { "rorA",   { Eb, Ib }, 0 },
3102     { "rclA",   { Eb, Ib }, 0 },
3103     { "rcrA",   { Eb, Ib }, 0 },
3104     { "shlA",   { Eb, Ib }, 0 },
3105     { "shrA",   { Eb, Ib }, 0 },
3106     { "shlA",   { Eb, Ib }, 0 },
3107     { "sarA",   { Eb, Ib }, 0 },
3108   },
3109   /* REG_C1 */
3110   {
3111     { "rolQ",   { Ev, Ib }, 0 },
3112     { "rorQ",   { Ev, Ib }, 0 },
3113     { "rclQ",   { Ev, Ib }, 0 },
3114     { "rcrQ",   { Ev, Ib }, 0 },
3115     { "shlQ",   { Ev, Ib }, 0 },
3116     { "shrQ",   { Ev, Ib }, 0 },
3117     { "shlQ",   { Ev, Ib }, 0 },
3118     { "sarQ",   { Ev, Ib }, 0 },
3119   },
3120   /* REG_C6 */
3121   {
3122     { "movA",   { Ebh3, Ib }, 0 },
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { Bad_Opcode },
3126     { Bad_Opcode },
3127     { Bad_Opcode },
3128     { Bad_Opcode },
3129     { MOD_TABLE (MOD_C6_REG_7) },
3130   },
3131   /* REG_C7 */
3132   {
3133     { "movQ",   { Evh3, Iv }, 0 },
3134     { Bad_Opcode },
3135     { Bad_Opcode },
3136     { Bad_Opcode },
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { Bad_Opcode },
3140     { MOD_TABLE (MOD_C7_REG_7) },
3141   },
3142   /* REG_D0 */
3143   {
3144     { "rolA",   { Eb, I1 }, 0 },
3145     { "rorA",   { Eb, I1 }, 0 },
3146     { "rclA",   { Eb, I1 }, 0 },
3147     { "rcrA",   { Eb, I1 }, 0 },
3148     { "shlA",   { Eb, I1 }, 0 },
3149     { "shrA",   { Eb, I1 }, 0 },
3150     { "shlA",   { Eb, I1 }, 0 },
3151     { "sarA",   { Eb, I1 }, 0 },
3152   },
3153   /* REG_D1 */
3154   {
3155     { "rolQ",   { Ev, I1 }, 0 },
3156     { "rorQ",   { Ev, I1 }, 0 },
3157     { "rclQ",   { Ev, I1 }, 0 },
3158     { "rcrQ",   { Ev, I1 }, 0 },
3159     { "shlQ",   { Ev, I1 }, 0 },
3160     { "shrQ",   { Ev, I1 }, 0 },
3161     { "shlQ",   { Ev, I1 }, 0 },
3162     { "sarQ",   { Ev, I1 }, 0 },
3163   },
3164   /* REG_D2 */
3165   {
3166     { "rolA",   { Eb, CL }, 0 },
3167     { "rorA",   { Eb, CL }, 0 },
3168     { "rclA",   { Eb, CL }, 0 },
3169     { "rcrA",   { Eb, CL }, 0 },
3170     { "shlA",   { Eb, CL }, 0 },
3171     { "shrA",   { Eb, CL }, 0 },
3172     { "shlA",   { Eb, CL }, 0 },
3173     { "sarA",   { Eb, CL }, 0 },
3174   },
3175   /* REG_D3 */
3176   {
3177     { "rolQ",   { Ev, CL }, 0 },
3178     { "rorQ",   { Ev, CL }, 0 },
3179     { "rclQ",   { Ev, CL }, 0 },
3180     { "rcrQ",   { Ev, CL }, 0 },
3181     { "shlQ",   { Ev, CL }, 0 },
3182     { "shrQ",   { Ev, CL }, 0 },
3183     { "shlQ",   { Ev, CL }, 0 },
3184     { "sarQ",   { Ev, CL }, 0 },
3185   },
3186   /* REG_F6 */
3187   {
3188     { "testA",  { Eb, Ib }, 0 },
3189     { "testA",  { Eb, Ib }, 0 },
3190     { "notA",   { Ebh1 }, 0 },
3191     { "negA",   { Ebh1 }, 0 },
3192     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3193     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3194     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3195     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3196   },
3197   /* REG_F7 */
3198   {
3199     { "testQ",  { Ev, Iv }, 0 },
3200     { "testQ",  { Ev, Iv }, 0 },
3201     { "notQ",   { Evh1 }, 0 },
3202     { "negQ",   { Evh1 }, 0 },
3203     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3204     { "imulQ",  { Ev }, 0 },
3205     { "divQ",   { Ev }, 0 },
3206     { "idivQ",  { Ev }, 0 },
3207   },
3208   /* REG_FE */
3209   {
3210     { "incA",   { Ebh1 }, 0 },
3211     { "decA",   { Ebh1 }, 0 },
3212   },
3213   /* REG_FF */
3214   {
3215     { "incQ",   { Evh1 }, 0 },
3216     { "decQ",   { Evh1 }, 0 },
3217     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3218     { MOD_TABLE (MOD_FF_REG_3) },
3219     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3220     { MOD_TABLE (MOD_FF_REG_5) },
3221     { "pushU",  { stackEv }, 0 },
3222     { Bad_Opcode },
3223   },
3224   /* REG_0F00 */
3225   {
3226     { "sldtD",  { Sv }, 0 },
3227     { "strD",   { Sv }, 0 },
3228     { "lldt",   { Ew }, 0 },
3229     { "ltr",    { Ew }, 0 },
3230     { "verr",   { Ew }, 0 },
3231     { "verw",   { Ew }, 0 },
3232     { Bad_Opcode },
3233     { Bad_Opcode },
3234   },
3235   /* REG_0F01 */
3236   {
3237     { MOD_TABLE (MOD_0F01_REG_0) },
3238     { MOD_TABLE (MOD_0F01_REG_1) },
3239     { MOD_TABLE (MOD_0F01_REG_2) },
3240     { MOD_TABLE (MOD_0F01_REG_3) },
3241     { "smswD",  { Sv }, 0 },
3242     { MOD_TABLE (MOD_0F01_REG_5) },
3243     { "lmsw",   { Ew }, 0 },
3244     { MOD_TABLE (MOD_0F01_REG_7) },
3245   },
3246   /* REG_0F0D */
3247   {
3248     { "prefetch",       { Mb }, 0 },
3249     { "prefetchw",      { Mb }, 0 },
3250     { "prefetchwt1",    { Mb }, 0 },
3251     { "prefetch",       { Mb }, 0 },
3252     { "prefetch",       { Mb }, 0 },
3253     { "prefetch",       { Mb }, 0 },
3254     { "prefetch",       { Mb }, 0 },
3255     { "prefetch",       { Mb }, 0 },
3256   },
3257   /* REG_0F18 */
3258   {
3259     { MOD_TABLE (MOD_0F18_REG_0) },
3260     { MOD_TABLE (MOD_0F18_REG_1) },
3261     { MOD_TABLE (MOD_0F18_REG_2) },
3262     { MOD_TABLE (MOD_0F18_REG_3) },
3263     { MOD_TABLE (MOD_0F18_REG_4) },
3264     { MOD_TABLE (MOD_0F18_REG_5) },
3265     { MOD_TABLE (MOD_0F18_REG_6) },
3266     { MOD_TABLE (MOD_0F18_REG_7) },
3267   },
3268   /* REG_0F1C_P_0_MOD_0 */
3269   {
3270     { "cldemote",       { Mb }, 0 },
3271     { "nopQ",           { Ev }, 0 },
3272     { "nopQ",           { Ev }, 0 },
3273     { "nopQ",           { Ev }, 0 },
3274     { "nopQ",           { Ev }, 0 },
3275     { "nopQ",           { Ev }, 0 },
3276     { "nopQ",           { Ev }, 0 },
3277     { "nopQ",           { Ev }, 0 },
3278   },
3279   /* REG_0F1E_P_1_MOD_3 */
3280   {
3281     { "nopQ",           { Ev }, 0 },
3282     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3283     { "nopQ",           { Ev }, 0 },
3284     { "nopQ",           { Ev }, 0 },
3285     { "nopQ",           { Ev }, 0 },
3286     { "nopQ",           { Ev }, 0 },
3287     { "nopQ",           { Ev }, 0 },
3288     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3289   },
3290   /* REG_0F71 */
3291   {
3292     { Bad_Opcode },
3293     { Bad_Opcode },
3294     { MOD_TABLE (MOD_0F71_REG_2) },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F71_REG_4) },
3297     { Bad_Opcode },
3298     { MOD_TABLE (MOD_0F71_REG_6) },
3299   },
3300   /* REG_0F72 */
3301   {
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { MOD_TABLE (MOD_0F72_REG_2) },
3305     { Bad_Opcode },
3306     { MOD_TABLE (MOD_0F72_REG_4) },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_0F72_REG_6) },
3309   },
3310   /* REG_0F73 */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { MOD_TABLE (MOD_0F73_REG_2) },
3315     { MOD_TABLE (MOD_0F73_REG_3) },
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { MOD_TABLE (MOD_0F73_REG_6) },
3319     { MOD_TABLE (MOD_0F73_REG_7) },
3320   },
3321   /* REG_0FA6 */
3322   {
3323     { "montmul",        { { OP_0f07, 0 } }, 0 },
3324     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3325     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3326   },
3327   /* REG_0FA7 */
3328   {
3329     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3330     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3331     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3332     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3333     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3334     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3335   },
3336   /* REG_0FAE */
3337   {
3338     { MOD_TABLE (MOD_0FAE_REG_0) },
3339     { MOD_TABLE (MOD_0FAE_REG_1) },
3340     { MOD_TABLE (MOD_0FAE_REG_2) },
3341     { MOD_TABLE (MOD_0FAE_REG_3) },
3342     { MOD_TABLE (MOD_0FAE_REG_4) },
3343     { MOD_TABLE (MOD_0FAE_REG_5) },
3344     { MOD_TABLE (MOD_0FAE_REG_6) },
3345     { MOD_TABLE (MOD_0FAE_REG_7) },
3346   },
3347   /* REG_0FBA */
3348   {
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353     { "btQ",    { Ev, Ib }, 0 },
3354     { "btsQ",   { Evh1, Ib }, 0 },
3355     { "btrQ",   { Evh1, Ib }, 0 },
3356     { "btcQ",   { Evh1, Ib }, 0 },
3357   },
3358   /* REG_0FC7 */
3359   {
3360     { Bad_Opcode },
3361     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3362     { Bad_Opcode },
3363     { MOD_TABLE (MOD_0FC7_REG_3) },
3364     { MOD_TABLE (MOD_0FC7_REG_4) },
3365     { MOD_TABLE (MOD_0FC7_REG_5) },
3366     { MOD_TABLE (MOD_0FC7_REG_6) },
3367     { MOD_TABLE (MOD_0FC7_REG_7) },
3368   },
3369   /* REG_VEX_0F71 */
3370   {
3371     { Bad_Opcode },
3372     { Bad_Opcode },
3373     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3374     { Bad_Opcode },
3375     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3378   },
3379   /* REG_VEX_0F72 */
3380   {
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3386     { Bad_Opcode },
3387     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3388   },
3389   /* REG_VEX_0F73 */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3394     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3395     { Bad_Opcode },
3396     { Bad_Opcode },
3397     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3398     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3399   },
3400   /* REG_VEX_0FAE */
3401   {
3402     { Bad_Opcode },
3403     { Bad_Opcode },
3404     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3405     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3406   },
3407   /* REG_VEX_0F38F3 */
3408   {
3409     { Bad_Opcode },
3410     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3411     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3412     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3413   },
3414   /* REG_XOP_LWPCB */
3415   {
3416     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3417     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3418   },
3419   /* REG_XOP_LWP */
3420   {
3421     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3422     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3423   },
3424   /* REG_XOP_TBM_01 */
3425   {
3426     { Bad_Opcode },
3427     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3428     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3429     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3430     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3431     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3432     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3433     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3434   },
3435   /* REG_XOP_TBM_02 */
3436   {
3437     { Bad_Opcode },
3438     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3444   },
3445
3446 #include "i386-dis-evex-reg.h"
3447 };
3448
3449 static const struct dis386 prefix_table[][4] = {
3450   /* PREFIX_90 */
3451   {
3452     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3453     { "pause", { XX }, 0 },
3454     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3455     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3456   },
3457
3458   /* PREFIX_0F01_REG_3_RM_1 */
3459   {
3460     { "vmmcall",        { Skip_MODRM }, 0 },
3461     { "vmgexit",        { Skip_MODRM }, 0 },
3462     { Bad_Opcode },
3463     { "vmgexit",        { Skip_MODRM }, 0 },
3464   },
3465
3466   /* PREFIX_0F01_REG_5_MOD_0 */
3467   {
3468     { Bad_Opcode },
3469     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3470   },
3471
3472   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3473   {
3474     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3475     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3476     { Bad_Opcode },
3477     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3478   },
3479
3480   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3486   },
3487
3488   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3489   {
3490     { Bad_Opcode },
3491     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3492   },
3493
3494   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3495   {
3496     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3497     { "mcommit",        { Skip_MODRM }, 0 },
3498   },
3499
3500   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3501   {
3502     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3503   },
3504
3505   /* PREFIX_0F09 */
3506   {
3507     { "wbinvd",   { XX }, 0 },
3508     { "wbnoinvd", { XX }, 0 },
3509   },
3510
3511   /* PREFIX_0F10 */
3512   {
3513     { "movups", { XM, EXx }, PREFIX_OPCODE },
3514     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3515     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3516     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3517   },
3518
3519   /* PREFIX_0F11 */
3520   {
3521     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3522     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3523     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3524     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3525   },
3526
3527   /* PREFIX_0F12 */
3528   {
3529     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3530     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3531     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3532     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3533   },
3534
3535   /* PREFIX_0F16 */
3536   {
3537     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3538     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3539     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3540   },
3541
3542   /* PREFIX_0F1A */
3543   {
3544     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3545     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3546     { "bndmov", { Gbnd, Ebnd }, 0 },
3547     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3548   },
3549
3550   /* PREFIX_0F1B */
3551   {
3552     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3553     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3554     { "bndmov", { EbndS, Gbnd }, 0 },
3555     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3556   },
3557
3558   /* PREFIX_0F1C */
3559   {
3560     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3561     { "nopQ",   { Ev }, PREFIX_OPCODE },
3562     { "nopQ",   { Ev }, PREFIX_OPCODE },
3563     { "nopQ",   { Ev }, PREFIX_OPCODE },
3564   },
3565
3566   /* PREFIX_0F1E */
3567   {
3568     { "nopQ",   { Ev }, PREFIX_OPCODE },
3569     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3570     { "nopQ",   { Ev }, PREFIX_OPCODE },
3571     { "nopQ",   { Ev }, PREFIX_OPCODE },
3572   },
3573
3574   /* PREFIX_0F2A */
3575   {
3576     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3577     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3578     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3579     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3580   },
3581
3582   /* PREFIX_0F2B */
3583   {
3584     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3585     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3586     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3587     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3588   },
3589
3590   /* PREFIX_0F2C */
3591   {
3592     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3593     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3594     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3595     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3596   },
3597
3598   /* PREFIX_0F2D */
3599   {
3600     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3601     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3602     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3603     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3604   },
3605
3606   /* PREFIX_0F2E */
3607   {
3608     { "ucomiss",{ XM, EXd }, 0 },
3609     { Bad_Opcode },
3610     { "ucomisd",{ XM, EXq }, 0 },
3611   },
3612
3613   /* PREFIX_0F2F */
3614   {
3615     { "comiss", { XM, EXd }, 0 },
3616     { Bad_Opcode },
3617     { "comisd", { XM, EXq }, 0 },
3618   },
3619
3620   /* PREFIX_0F51 */
3621   {
3622     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3623     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3624     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3625     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3626   },
3627
3628   /* PREFIX_0F52 */
3629   {
3630     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3631     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3632   },
3633
3634   /* PREFIX_0F53 */
3635   {
3636     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3637     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3638   },
3639
3640   /* PREFIX_0F58 */
3641   {
3642     { "addps", { XM, EXx }, PREFIX_OPCODE },
3643     { "addss", { XM, EXd }, PREFIX_OPCODE },
3644     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3645     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F59 */
3649   {
3650     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3651     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3652     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3653     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3654   },
3655
3656   /* PREFIX_0F5A */
3657   {
3658     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3659     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3660     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3661     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3662   },
3663
3664   /* PREFIX_0F5B */
3665   {
3666     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3667     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3668     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3669   },
3670
3671   /* PREFIX_0F5C */
3672   {
3673     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3674     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3675     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3676     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3677   },
3678
3679   /* PREFIX_0F5D */
3680   {
3681     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3682     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3683     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3684     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3685   },
3686
3687   /* PREFIX_0F5E */
3688   {
3689     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3690     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3691     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3692     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3693   },
3694
3695   /* PREFIX_0F5F */
3696   {
3697     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3698     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3699     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3700     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3701   },
3702
3703   /* PREFIX_0F60 */
3704   {
3705     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3706     { Bad_Opcode },
3707     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3708   },
3709
3710   /* PREFIX_0F61 */
3711   {
3712     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3713     { Bad_Opcode },
3714     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F62 */
3718   {
3719     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3720     { Bad_Opcode },
3721     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F6C */
3725   {
3726     { Bad_Opcode },
3727     { Bad_Opcode },
3728     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F6D */
3732   {
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3736   },
3737
3738   /* PREFIX_0F6F */
3739   {
3740     { "movq",   { MX, EM }, PREFIX_OPCODE },
3741     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3742     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_0F70 */
3746   {
3747     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3748     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3749     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3750     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F73_REG_3 */
3754   {
3755     { Bad_Opcode },
3756     { Bad_Opcode },
3757     { "psrldq", { XS, Ib }, 0 },
3758   },
3759
3760   /* PREFIX_0F73_REG_7 */
3761   {
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { "pslldq", { XS, Ib }, 0 },
3765   },
3766
3767   /* PREFIX_0F78 */
3768   {
3769     {"vmread",  { Em, Gm }, 0 },
3770     { Bad_Opcode },
3771     {"extrq",   { XS, Ib, Ib }, 0 },
3772     {"insertq", { XM, XS, Ib, Ib }, 0 },
3773   },
3774
3775   /* PREFIX_0F79 */
3776   {
3777     {"vmwrite", { Gm, Em }, 0 },
3778     { Bad_Opcode },
3779     {"extrq",   { XM, XS }, 0 },
3780     {"insertq", { XM, XS }, 0 },
3781   },
3782
3783   /* PREFIX_0F7C */
3784   {
3785     { Bad_Opcode },
3786     { Bad_Opcode },
3787     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3788     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F7D */
3792   {
3793     { Bad_Opcode },
3794     { Bad_Opcode },
3795     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3796     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_0F7E */
3800   {
3801     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3802     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3803     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F7F */
3807   {
3808     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3809     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3810     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0FAE_REG_0_MOD_3 */
3814   {
3815     { Bad_Opcode },
3816     { "rdfsbase", { Ev }, 0 },
3817   },
3818
3819   /* PREFIX_0FAE_REG_1_MOD_3 */
3820   {
3821     { Bad_Opcode },
3822     { "rdgsbase", { Ev }, 0 },
3823   },
3824
3825   /* PREFIX_0FAE_REG_2_MOD_3 */
3826   {
3827     { Bad_Opcode },
3828     { "wrfsbase", { Ev }, 0 },
3829   },
3830
3831   /* PREFIX_0FAE_REG_3_MOD_3 */
3832   {
3833     { Bad_Opcode },
3834     { "wrgsbase", { Ev }, 0 },
3835   },
3836
3837   /* PREFIX_0FAE_REG_4_MOD_0 */
3838   {
3839     { "xsave",  { FXSAVE }, 0 },
3840     { "ptwrite%LQ", { Edq }, 0 },
3841   },
3842
3843   /* PREFIX_0FAE_REG_4_MOD_3 */
3844   {
3845     { Bad_Opcode },
3846     { "ptwrite%LQ", { Edq }, 0 },
3847   },
3848
3849   /* PREFIX_0FAE_REG_5_MOD_0 */
3850   {
3851     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3852   },
3853
3854   /* PREFIX_0FAE_REG_5_MOD_3 */
3855   {
3856     { "lfence",         { Skip_MODRM }, 0 },
3857     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3858   },
3859
3860   /* PREFIX_0FAE_REG_6_MOD_0 */
3861   {
3862     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3863     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3864     { "clwb",   { Mb }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0FAE_REG_6_MOD_3 */
3868   {
3869     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3870     { "umonitor",       { Eva }, PREFIX_OPCODE },
3871     { "tpause", { Edq }, PREFIX_OPCODE },
3872     { "umwait", { Edq }, PREFIX_OPCODE },
3873   },
3874
3875   /* PREFIX_0FAE_REG_7_MOD_0 */
3876   {
3877     { "clflush",        { Mb }, 0 },
3878     { Bad_Opcode },
3879     { "clflushopt",     { Mb }, 0 },
3880   },
3881
3882   /* PREFIX_0FB8 */
3883   {
3884     { Bad_Opcode },
3885     { "popcntS", { Gv, Ev }, 0 },
3886   },
3887
3888   /* PREFIX_0FBC */
3889   {
3890     { "bsfS",   { Gv, Ev }, 0 },
3891     { "tzcntS", { Gv, Ev }, 0 },
3892     { "bsfS",   { Gv, Ev }, 0 },
3893   },
3894
3895   /* PREFIX_0FBD */
3896   {
3897     { "bsrS",   { Gv, Ev }, 0 },
3898     { "lzcntS", { Gv, Ev }, 0 },
3899     { "bsrS",   { Gv, Ev }, 0 },
3900   },
3901
3902   /* PREFIX_0FC2 */
3903   {
3904     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3905     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3906     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3907     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0FC3_MOD_0 */
3911   {
3912     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3913   },
3914
3915   /* PREFIX_0FC7_REG_6_MOD_0 */
3916   {
3917     { "vmptrld",{ Mq }, 0 },
3918     { "vmxon",  { Mq }, 0 },
3919     { "vmclear",{ Mq }, 0 },
3920   },
3921
3922   /* PREFIX_0FC7_REG_6_MOD_3 */
3923   {
3924     { "rdrand", { Ev }, 0 },
3925     { Bad_Opcode },
3926     { "rdrand", { Ev }, 0 }
3927   },
3928
3929   /* PREFIX_0FC7_REG_7_MOD_3 */
3930   {
3931     { "rdseed", { Ev }, 0 },
3932     { "rdpid",  { Em }, 0 },
3933     { "rdseed", { Ev }, 0 },
3934   },
3935
3936   /* PREFIX_0FD0 */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { "addsubpd", { XM, EXx }, 0 },
3941     { "addsubps", { XM, EXx }, 0 },
3942   },
3943
3944   /* PREFIX_0FD6 */
3945   {
3946     { Bad_Opcode },
3947     { "movq2dq",{ XM, MS }, 0 },
3948     { "movq",   { EXqS, XM }, 0 },
3949     { "movdq2q",{ MX, XS }, 0 },
3950   },
3951
3952   /* PREFIX_0FE6 */
3953   {
3954     { Bad_Opcode },
3955     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3956     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3957     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0FE7 */
3961   {
3962     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3963     { Bad_Opcode },
3964     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3965   },
3966
3967   /* PREFIX_0FF0 */
3968   {
3969     { Bad_Opcode },
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3973   },
3974
3975   /* PREFIX_0FF7 */
3976   {
3977     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3978     { Bad_Opcode },
3979     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3980   },
3981
3982   /* PREFIX_0F3810 */
3983   {
3984     { Bad_Opcode },
3985     { Bad_Opcode },
3986     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3987   },
3988
3989   /* PREFIX_0F3814 */
3990   {
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3994   },
3995
3996   /* PREFIX_0F3815 */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4001   },
4002
4003   /* PREFIX_0F3817 */
4004   {
4005     { Bad_Opcode },
4006     { Bad_Opcode },
4007     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_0F3820 */
4011   {
4012     { Bad_Opcode },
4013     { Bad_Opcode },
4014     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4015   },
4016
4017   /* PREFIX_0F3821 */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F3822 */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4029   },
4030
4031   /* PREFIX_0F3823 */
4032   {
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F3824 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4043   },
4044
4045   /* PREFIX_0F3825 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4050   },
4051
4052   /* PREFIX_0F3828 */
4053   {
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4057   },
4058
4059   /* PREFIX_0F3829 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4064   },
4065
4066   /* PREFIX_0F382A */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4071   },
4072
4073   /* PREFIX_0F382B */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4078   },
4079
4080   /* PREFIX_0F3830 */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4085   },
4086
4087   /* PREFIX_0F3831 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4092   },
4093
4094   /* PREFIX_0F3832 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F3833 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4106   },
4107
4108   /* PREFIX_0F3834 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3835 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3837 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3838 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3839 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F383A */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F383B */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F383C */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F383D */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F383E */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F383F */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3840 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3841 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3880 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3881 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3882 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F38C8 */
4221   {
4222     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F38C9 */
4226   {
4227     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4228   },
4229
4230   /* PREFIX_0F38CA */
4231   {
4232     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F38CB */
4236   {
4237     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F38CC */
4241   {
4242     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F38CD */
4246   {
4247     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F38CF */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F38DB */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F38DC */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F38DD */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F38DE */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F38DF */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F38F0 */
4293   {
4294     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4295     { Bad_Opcode },
4296     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4297     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F38F1 */
4301   {
4302     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4303     { Bad_Opcode },
4304     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4305     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F38F5 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4313   },
4314
4315   /* PREFIX_0F38F6 */
4316   {
4317     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4318     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4319     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4320     { Bad_Opcode },
4321   },
4322
4323   /* PREFIX_0F38F8 */
4324   {
4325     { Bad_Opcode },
4326     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4327     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4328     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4329   },
4330
4331   /* PREFIX_0F38F9 */
4332   {
4333     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4334   },
4335
4336   /* PREFIX_0F3A08 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3A09 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3A0A */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3A0B */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3A0C */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3A0D */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F3A0E */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F3A14 */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F3A15 */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3A16 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3A17 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3A20 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3A21 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3A22 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F3A40 */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F3A41 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3A42 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3A44 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A60 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A61 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A62 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A63 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3ACC */
4491   {
4492     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3ACE */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3ACF */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3ADF */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_VEX_0F10 */
4517   {
4518     { "vmovups",        { XM, EXx }, 0 },
4519     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4520     { "vmovupd",        { XM, EXx }, 0 },
4521     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4522   },
4523
4524   /* PREFIX_VEX_0F11 */
4525   {
4526     { "vmovups",        { EXxS, XM }, 0 },
4527     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4528     { "vmovupd",        { EXxS, XM }, 0 },
4529     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4530   },
4531
4532   /* PREFIX_VEX_0F12 */
4533   {
4534     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4535     { "vmovsldup",      { XM, EXx }, 0 },
4536     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4537     { "vmovddup",       { XM, EXymmq }, 0 },
4538   },
4539
4540   /* PREFIX_VEX_0F16 */
4541   {
4542     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4543     { "vmovshdup",      { XM, EXx }, 0 },
4544     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4545   },
4546
4547   /* PREFIX_VEX_0F2A */
4548   {
4549     { Bad_Opcode },
4550     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4551     { Bad_Opcode },
4552     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4553   },
4554
4555   /* PREFIX_VEX_0F2C */
4556   {
4557     { Bad_Opcode },
4558     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4559     { Bad_Opcode },
4560     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4561   },
4562
4563   /* PREFIX_VEX_0F2D */
4564   {
4565     { Bad_Opcode },
4566     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4567     { Bad_Opcode },
4568     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4569   },
4570
4571   /* PREFIX_VEX_0F2E */
4572   {
4573     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4574     { Bad_Opcode },
4575     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4576   },
4577
4578   /* PREFIX_VEX_0F2F */
4579   {
4580     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4581     { Bad_Opcode },
4582     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4583   },
4584
4585   /* PREFIX_VEX_0F41 */
4586   {
4587     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4588     { Bad_Opcode },
4589     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4590   },
4591
4592   /* PREFIX_VEX_0F42 */
4593   {
4594     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4595     { Bad_Opcode },
4596     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4597   },
4598
4599   /* PREFIX_VEX_0F44 */
4600   {
4601     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4602     { Bad_Opcode },
4603     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4604   },
4605
4606   /* PREFIX_VEX_0F45 */
4607   {
4608     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4609     { Bad_Opcode },
4610     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4611   },
4612
4613   /* PREFIX_VEX_0F46 */
4614   {
4615     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4616     { Bad_Opcode },
4617     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4618   },
4619
4620   /* PREFIX_VEX_0F47 */
4621   {
4622     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4623     { Bad_Opcode },
4624     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4625   },
4626
4627   /* PREFIX_VEX_0F4A */
4628   {
4629     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4632   },
4633
4634   /* PREFIX_VEX_0F4B */
4635   {
4636     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F51 */
4642   {
4643     { "vsqrtps",        { XM, EXx }, 0 },
4644     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4645     { "vsqrtpd",        { XM, EXx }, 0 },
4646     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4647   },
4648
4649   /* PREFIX_VEX_0F52 */
4650   {
4651     { "vrsqrtps",       { XM, EXx }, 0 },
4652     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4653   },
4654
4655   /* PREFIX_VEX_0F53 */
4656   {
4657     { "vrcpps",         { XM, EXx }, 0 },
4658     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4659   },
4660
4661   /* PREFIX_VEX_0F58 */
4662   {
4663     { "vaddps",         { XM, Vex, EXx }, 0 },
4664     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4665     { "vaddpd",         { XM, Vex, EXx }, 0 },
4666     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4667   },
4668
4669   /* PREFIX_VEX_0F59 */
4670   {
4671     { "vmulps",         { XM, Vex, EXx }, 0 },
4672     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4673     { "vmulpd",         { XM, Vex, EXx }, 0 },
4674     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4675   },
4676
4677   /* PREFIX_VEX_0F5A */
4678   {
4679     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4680     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4681     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4682     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4683   },
4684
4685   /* PREFIX_VEX_0F5B */
4686   {
4687     { "vcvtdq2ps",      { XM, EXx }, 0 },
4688     { "vcvttps2dq",     { XM, EXx }, 0 },
4689     { "vcvtps2dq",      { XM, EXx }, 0 },
4690   },
4691
4692   /* PREFIX_VEX_0F5C */
4693   {
4694     { "vsubps",         { XM, Vex, EXx }, 0 },
4695     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4696     { "vsubpd",         { XM, Vex, EXx }, 0 },
4697     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4698   },
4699
4700   /* PREFIX_VEX_0F5D */
4701   {
4702     { "vminps",         { XM, Vex, EXx }, 0 },
4703     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4704     { "vminpd",         { XM, Vex, EXx }, 0 },
4705     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F5E */
4709   {
4710     { "vdivps",         { XM, Vex, EXx }, 0 },
4711     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4712     { "vdivpd",         { XM, Vex, EXx }, 0 },
4713     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4714   },
4715
4716   /* PREFIX_VEX_0F5F */
4717   {
4718     { "vmaxps",         { XM, Vex, EXx }, 0 },
4719     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4720     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4721     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4722   },
4723
4724   /* PREFIX_VEX_0F60 */
4725   {
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4729   },
4730
4731   /* PREFIX_VEX_0F61 */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4736   },
4737
4738   /* PREFIX_VEX_0F62 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4743   },
4744
4745   /* PREFIX_VEX_0F63 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4750   },
4751
4752   /* PREFIX_VEX_0F64 */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4757   },
4758
4759   /* PREFIX_VEX_0F65 */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F66 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4771   },
4772
4773   /* PREFIX_VEX_0F67 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F68 */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4785   },
4786
4787   /* PREFIX_VEX_0F69 */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F6A */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4799   },
4800
4801   /* PREFIX_VEX_0F6B */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F6C */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F6D */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F6E */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4827   },
4828
4829   /* PREFIX_VEX_0F6F */
4830   {
4831     { Bad_Opcode },
4832     { "vmovdqu",        { XM, EXx }, 0 },
4833     { "vmovdqa",        { XM, EXx }, 0 },
4834   },
4835
4836   /* PREFIX_VEX_0F70 */
4837   {
4838     { Bad_Opcode },
4839     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4840     { "vpshufd",        { XM, EXx, Ib }, 0 },
4841     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4842   },
4843
4844   /* PREFIX_VEX_0F71_REG_2 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4849   },
4850
4851   /* PREFIX_VEX_0F71_REG_4 */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { "vpsraw",         { Vex, XS, Ib }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F71_REG_6 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "vpsllw",         { Vex, XS, Ib }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F72_REG_2 */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vpsrld",         { Vex, XS, Ib }, 0 },
4870   },
4871
4872   /* PREFIX_VEX_0F72_REG_4 */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vpsrad",         { Vex, XS, Ib }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F72_REG_6 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpslld",         { Vex, XS, Ib }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F73_REG_2 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F73_REG_3 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F73_REG_6 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpsllq",         { Vex, XS, Ib }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F73_REG_7 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpslldq",        { Vex, XS, Ib }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F74 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F75 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F76 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F77 */
4936   {
4937     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4938   },
4939
4940   /* PREFIX_VEX_0F7C */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4945     { "vhaddps",        { XM, Vex, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F7D */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4953     { "vhsubps",        { XM, Vex, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F7E */
4957   {
4958     { Bad_Opcode },
4959     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4960     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_0F7F */
4964   {
4965     { Bad_Opcode },
4966     { "vmovdqu",        { EXxS, XM }, 0 },
4967     { "vmovdqa",        { EXxS, XM }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F90 */
4971   {
4972     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4973     { Bad_Opcode },
4974     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F91 */
4978   {
4979     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4980     { Bad_Opcode },
4981     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F92 */
4985   {
4986     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4987     { Bad_Opcode },
4988     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4989     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4990   },
4991
4992   /* PREFIX_VEX_0F93 */
4993   {
4994     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4995     { Bad_Opcode },
4996     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4997     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4998   },
4999
5000   /* PREFIX_VEX_0F98 */
5001   {
5002     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F99 */
5008   {
5009     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5010     { Bad_Opcode },
5011     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0FC2 */
5015   {
5016     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5017     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5018     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5019     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5020   },
5021
5022   /* PREFIX_VEX_0FC4 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0FC5 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0FD0 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5041     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0FD1 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5049   },
5050
5051   /* PREFIX_VEX_0FD2 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0FD3 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0FD4 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vpaddq",         { XM, Vex, EXx }, 0 },
5070   },
5071
5072   /* PREFIX_VEX_0FD5 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { "vpmullw",        { XM, Vex, EXx }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0FD6 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0FD7 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5091   },
5092
5093   /* PREFIX_VEX_0FD8 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5098   },
5099
5100   /* PREFIX_VEX_0FD9 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5105   },
5106
5107   /* PREFIX_VEX_0FDA */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { "vpminub",        { XM, Vex, EXx }, 0 },
5112   },
5113
5114   /* PREFIX_VEX_0FDB */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { "vpand",          { XM, Vex, EXx }, 0 },
5119   },
5120
5121   /* PREFIX_VEX_0FDC */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5126   },
5127
5128   /* PREFIX_VEX_0FDD */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5133   },
5134
5135   /* PREFIX_VEX_0FDE */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5140   },
5141
5142   /* PREFIX_VEX_0FDF */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { "vpandn",         { XM, Vex, EXx }, 0 },
5147   },
5148
5149   /* PREFIX_VEX_0FE0 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { "vpavgb",         { XM, Vex, EXx }, 0 },
5154   },
5155
5156   /* PREFIX_VEX_0FE1 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FE2 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FE3 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpavgw",         { XM, Vex, EXx }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FE4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FE5 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FE6 */
5192   {
5193     { Bad_Opcode },
5194     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5195     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5196     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FE7 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5204   },
5205
5206   /* PREFIX_VEX_0FE8 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FE9 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FEA */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpminsw",        { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FEB */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpor",           { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FEC */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5239   },
5240
5241   /* PREFIX_VEX_0FED */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5246   },
5247
5248   /* PREFIX_VEX_0FEE */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FEF */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpxor",          { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FF0 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5268   },
5269
5270   /* PREFIX_VEX_0FF1 */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5275   },
5276
5277   /* PREFIX_VEX_0FF2 */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5282   },
5283
5284   /* PREFIX_VEX_0FF3 */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5289   },
5290
5291   /* PREFIX_VEX_0FF4 */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5296   },
5297
5298   /* PREFIX_VEX_0FF5 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5303   },
5304
5305   /* PREFIX_VEX_0FF6 */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5310   },
5311
5312   /* PREFIX_VEX_0FF7 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5317   },
5318
5319   /* PREFIX_VEX_0FF8 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { "vpsubb",         { XM, Vex, EXx }, 0 },
5324   },
5325
5326   /* PREFIX_VEX_0FF9 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { "vpsubw",         { XM, Vex, EXx }, 0 },
5331   },
5332
5333   /* PREFIX_VEX_0FFA */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { "vpsubd",         { XM, Vex, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FFB */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { "vpsubq",         { XM, Vex, EXx }, 0 },
5345   },
5346
5347   /* PREFIX_VEX_0FFC */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { "vpaddb",         { XM, Vex, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FFD */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { "vpaddw",         { XM, Vex, EXx }, 0 },
5359   },
5360
5361   /* PREFIX_VEX_0FFE */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpaddd",         { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0F3800 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpshufb",        { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0F3801 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vphaddw",        { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0F3802 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vphaddd",        { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0F3803 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0F3804 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0F3805 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vphsubw",        { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0F3806 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vphsubd",        { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0F3807 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0F3808 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsignb",        { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0F3809 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpsignw",        { XM, Vex, EXx }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0F380A */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsignd",        { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0F380B */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0F380C */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0F380D */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0F380E */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0F380F */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0F3813 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0F3816 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0F3817 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vptest",         { XM, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3818 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0F3819 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0F381A */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5520   },
5521
5522   /* PREFIX_VEX_0F381C */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vpabsb",         { XM, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F381D */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vpabsw",         { XM, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F381E */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vpabsd",         { XM, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3820 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3821 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3822 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3823 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F3824 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F3825 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F3828 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5590   },
5591
5592   /* PREFIX_VEX_0F3829 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F382A */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F382B */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5611   },
5612
5613   /* PREFIX_VEX_0F382C */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F382D */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F382E */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F382F */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3830 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F3831 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F3832 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3833 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3834 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3835 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3836 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5688   },
5689
5690   /* PREFIX_VEX_0F3837 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3838 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpminsb",        { XM, Vex, EXx }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3839 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpminsd",        { XM, Vex, EXx }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F383A */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpminuw",        { XM, Vex, EXx }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F383B */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpminud",        { XM, Vex, EXx }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F383C */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F383D */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5737   },
5738
5739   /* PREFIX_VEX_0F383E */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F383F */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F3840 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vpmulld",        { XM, Vex, EXx }, 0 },
5758   },
5759
5760   /* PREFIX_VEX_0F3841 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F3845 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3846 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F3847 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3858 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3859 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F385A */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3878 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F3879 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F388C */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5828   },
5829
5830   /* PREFIX_VEX_0F388E */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5835   },
5836
5837   /* PREFIX_VEX_0F3890 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F3891 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F3892 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3893 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F3896 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F3897 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F3898 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F3899 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F389A */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F389B */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F389C */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5912   },
5913
5914   /* PREFIX_VEX_0F389D */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5919   },
5920
5921   /* PREFIX_VEX_0F389E */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5926   },
5927
5928   /* PREFIX_VEX_0F389F */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5933   },
5934
5935   /* PREFIX_VEX_0F38A6 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5940     { Bad_Opcode },
5941   },
5942
5943   /* PREFIX_VEX_0F38A7 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5948   },
5949
5950   /* PREFIX_VEX_0F38A8 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5955   },
5956
5957   /* PREFIX_VEX_0F38A9 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F38AA */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5969   },
5970
5971   /* PREFIX_VEX_0F38AB */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5976   },
5977
5978   /* PREFIX_VEX_0F38AC */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5983   },
5984
5985   /* PREFIX_VEX_0F38AD */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F38AE */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F38AF */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F38B6 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F38B7 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F38B8 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F38B9 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F38BA */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F38BB */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F38BC */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F38BD */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F38BE */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F38BF */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38CF */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6081   },
6082
6083   /* PREFIX_VEX_0F38DB */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6088   },
6089
6090   /* PREFIX_VEX_0F38DC */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vaesenc",        { XM, Vex, EXx }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38DD */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38DE */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vaesdec",        { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38DF */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38F2 */
6119   {
6120     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6121   },
6122
6123   /* PREFIX_VEX_0F38F3_REG_1 */
6124   {
6125     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6126   },
6127
6128   /* PREFIX_VEX_0F38F3_REG_2 */
6129   {
6130     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6131   },
6132
6133   /* PREFIX_VEX_0F38F3_REG_3 */
6134   {
6135     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6136   },
6137
6138   /* PREFIX_VEX_0F38F5 */
6139   {
6140     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6141     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6142     { Bad_Opcode },
6143     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6144   },
6145
6146   /* PREFIX_VEX_0F38F6 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6152   },
6153
6154   /* PREFIX_VEX_0F38F7 */
6155   {
6156     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6157     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6158     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6159     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6160   },
6161
6162   /* PREFIX_VEX_0F3A00 */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6167   },
6168
6169   /* PREFIX_VEX_0F3A01 */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6174   },
6175
6176   /* PREFIX_VEX_0F3A02 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6181   },
6182
6183   /* PREFIX_VEX_0F3A04 */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6188   },
6189
6190   /* PREFIX_VEX_0F3A05 */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6195   },
6196
6197   /* PREFIX_VEX_0F3A06 */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6202   },
6203
6204   /* PREFIX_VEX_0F3A08 */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { "vroundps",       { XM, EXx, Ib }, 0 },
6209   },
6210
6211   /* PREFIX_VEX_0F3A09 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vroundpd",       { XM, EXx, Ib }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F3A0A */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F3A0B */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F3A0C */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F3A0D */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6244   },
6245
6246   /* PREFIX_VEX_0F3A0E */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F3A0F */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F3A14 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6265   },
6266
6267   /* PREFIX_VEX_0F3A15 */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6272   },
6273
6274   /* PREFIX_VEX_0F3A16 */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A17 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A18 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A19 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A1D */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A20 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A21 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A22 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A30 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A31 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A32 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A33 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A38 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A39 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F3A40 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A41 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A42 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A44 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A46 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A48 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A49 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F3A4A */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A4B */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A4C */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A5C */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6447   },
6448
6449   /* PREFIX_VEX_0F3A5D */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6454   },
6455
6456   /* PREFIX_VEX_0F3A5E */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6461   },
6462
6463   /* PREFIX_VEX_0F3A5F */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6468   },
6469
6470   /* PREFIX_VEX_0F3A60 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6475     { Bad_Opcode },
6476   },
6477
6478   /* PREFIX_VEX_0F3A61 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A62 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A63 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A68 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6504   },
6505
6506   /* PREFIX_VEX_0F3A69 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6511   },
6512
6513   /* PREFIX_VEX_0F3A6A */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A6B */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A6C */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6532   },
6533
6534   /* PREFIX_VEX_0F3A6D */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6539   },
6540
6541   /* PREFIX_VEX_0F3A6E */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A6F */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A78 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6560   },
6561
6562   /* PREFIX_VEX_0F3A79 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6567   },
6568
6569   /* PREFIX_VEX_0F3A7A */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A7B */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A7C */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6588     { Bad_Opcode },
6589   },
6590
6591   /* PREFIX_VEX_0F3A7D */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6596   },
6597
6598   /* PREFIX_VEX_0F3A7E */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A7F */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3ACE */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3ACF */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3ADF */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3AF0 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6639   },
6640
6641 #include "i386-dis-evex-prefix.h"
6642 };
6643
6644 static const struct dis386 x86_64_table[][2] = {
6645   /* X86_64_06 */
6646   {
6647     { "pushP", { es }, 0 },
6648   },
6649
6650   /* X86_64_07 */
6651   {
6652     { "popP", { es }, 0 },
6653   },
6654
6655   /* X86_64_0E */
6656   {
6657     { "pushP", { cs }, 0 },
6658   },
6659
6660   /* X86_64_16 */
6661   {
6662     { "pushP", { ss }, 0 },
6663   },
6664
6665   /* X86_64_17 */
6666   {
6667     { "popP", { ss }, 0 },
6668   },
6669
6670   /* X86_64_1E */
6671   {
6672     { "pushP", { ds }, 0 },
6673   },
6674
6675   /* X86_64_1F */
6676   {
6677     { "popP", { ds }, 0 },
6678   },
6679
6680   /* X86_64_27 */
6681   {
6682     { "daa", { XX }, 0 },
6683   },
6684
6685   /* X86_64_2F */
6686   {
6687     { "das", { XX }, 0 },
6688   },
6689
6690   /* X86_64_37 */
6691   {
6692     { "aaa", { XX }, 0 },
6693   },
6694
6695   /* X86_64_3F */
6696   {
6697     { "aas", { XX }, 0 },
6698   },
6699
6700   /* X86_64_60 */
6701   {
6702     { "pushaP", { XX }, 0 },
6703   },
6704
6705   /* X86_64_61 */
6706   {
6707     { "popaP", { XX }, 0 },
6708   },
6709
6710   /* X86_64_62 */
6711   {
6712     { MOD_TABLE (MOD_62_32BIT) },
6713     { EVEX_TABLE (EVEX_0F) },
6714   },
6715
6716   /* X86_64_63 */
6717   {
6718     { "arpl", { Ew, Gw }, 0 },
6719     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6720   },
6721
6722   /* X86_64_6D */
6723   {
6724     { "ins{R|}", { Yzr, indirDX }, 0 },
6725     { "ins{G|}", { Yzr, indirDX }, 0 },
6726   },
6727
6728   /* X86_64_6F */
6729   {
6730     { "outs{R|}", { indirDXr, Xz }, 0 },
6731     { "outs{G|}", { indirDXr, Xz }, 0 },
6732   },
6733
6734   /* X86_64_82 */
6735   {
6736     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6737     { REG_TABLE (REG_80) },
6738   },
6739
6740   /* X86_64_9A */
6741   {
6742     { "{l|}call{T|}", { Ap }, 0 },
6743   },
6744
6745   /* X86_64_C2 */
6746   {
6747     { "retP",           { Iw, BND }, 0 },
6748     { "ret@",           { Iw, BND }, 0 },
6749   },
6750
6751   /* X86_64_C3 */
6752   {
6753     { "retP",           { BND }, 0 },
6754     { "ret@",           { BND }, 0 },
6755   },
6756
6757   /* X86_64_C4 */
6758   {
6759     { MOD_TABLE (MOD_C4_32BIT) },
6760     { VEX_C4_TABLE (VEX_0F) },
6761   },
6762
6763   /* X86_64_C5 */
6764   {
6765     { MOD_TABLE (MOD_C5_32BIT) },
6766     { VEX_C5_TABLE (VEX_0F) },
6767   },
6768
6769   /* X86_64_CE */
6770   {
6771     { "into", { XX }, 0 },
6772   },
6773
6774   /* X86_64_D4 */
6775   {
6776     { "aam", { Ib }, 0 },
6777   },
6778
6779   /* X86_64_D5 */
6780   {
6781     { "aad", { Ib }, 0 },
6782   },
6783
6784   /* X86_64_E8 */
6785   {
6786     { "callP",          { Jv, BND }, 0 },
6787     { "call@",          { Jv, BND }, 0 }
6788   },
6789
6790   /* X86_64_E9 */
6791   {
6792     { "jmpP",           { Jv, BND }, 0 },
6793     { "jmp@",           { Jv, BND }, 0 }
6794   },
6795
6796   /* X86_64_EA */
6797   {
6798     { "{l|}jmp{T|}", { Ap }, 0 },
6799   },
6800
6801   /* X86_64_0F01_REG_0 */
6802   {
6803     { "sgdt{Q|Q}", { M }, 0 },
6804     { "sgdt", { M }, 0 },
6805   },
6806
6807   /* X86_64_0F01_REG_1 */
6808   {
6809     { "sidt{Q|Q}", { M }, 0 },
6810     { "sidt", { M }, 0 },
6811   },
6812
6813   /* X86_64_0F01_REG_2 */
6814   {
6815     { "lgdt{Q|Q}", { M }, 0 },
6816     { "lgdt", { M }, 0 },
6817   },
6818
6819   /* X86_64_0F01_REG_3 */
6820   {
6821     { "lidt{Q|Q}", { M }, 0 },
6822     { "lidt", { M }, 0 },
6823   },
6824 };
6825
6826 static const struct dis386 three_byte_table[][256] = {
6827
6828   /* THREE_BYTE_0F38 */
6829   {
6830     /* 00 */
6831     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6832     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6833     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6834     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6835     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6836     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6837     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6838     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6839     /* 08 */
6840     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6841     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6842     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6843     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     /* 10 */
6849     { PREFIX_TABLE (PREFIX_0F3810) },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { PREFIX_TABLE (PREFIX_0F3814) },
6854     { PREFIX_TABLE (PREFIX_0F3815) },
6855     { Bad_Opcode },
6856     { PREFIX_TABLE (PREFIX_0F3817) },
6857     /* 18 */
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6863     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6864     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6865     { Bad_Opcode },
6866     /* 20 */
6867     { PREFIX_TABLE (PREFIX_0F3820) },
6868     { PREFIX_TABLE (PREFIX_0F3821) },
6869     { PREFIX_TABLE (PREFIX_0F3822) },
6870     { PREFIX_TABLE (PREFIX_0F3823) },
6871     { PREFIX_TABLE (PREFIX_0F3824) },
6872     { PREFIX_TABLE (PREFIX_0F3825) },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     /* 28 */
6876     { PREFIX_TABLE (PREFIX_0F3828) },
6877     { PREFIX_TABLE (PREFIX_0F3829) },
6878     { PREFIX_TABLE (PREFIX_0F382A) },
6879     { PREFIX_TABLE (PREFIX_0F382B) },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     /* 30 */
6885     { PREFIX_TABLE (PREFIX_0F3830) },
6886     { PREFIX_TABLE (PREFIX_0F3831) },
6887     { PREFIX_TABLE (PREFIX_0F3832) },
6888     { PREFIX_TABLE (PREFIX_0F3833) },
6889     { PREFIX_TABLE (PREFIX_0F3834) },
6890     { PREFIX_TABLE (PREFIX_0F3835) },
6891     { Bad_Opcode },
6892     { PREFIX_TABLE (PREFIX_0F3837) },
6893     /* 38 */
6894     { PREFIX_TABLE (PREFIX_0F3838) },
6895     { PREFIX_TABLE (PREFIX_0F3839) },
6896     { PREFIX_TABLE (PREFIX_0F383A) },
6897     { PREFIX_TABLE (PREFIX_0F383B) },
6898     { PREFIX_TABLE (PREFIX_0F383C) },
6899     { PREFIX_TABLE (PREFIX_0F383D) },
6900     { PREFIX_TABLE (PREFIX_0F383E) },
6901     { PREFIX_TABLE (PREFIX_0F383F) },
6902     /* 40 */
6903     { PREFIX_TABLE (PREFIX_0F3840) },
6904     { PREFIX_TABLE (PREFIX_0F3841) },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     /* 48 */
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* 50 */
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* 58 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     /* 60 */
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 68 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 70 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 78 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 80 */
6975     { PREFIX_TABLE (PREFIX_0F3880) },
6976     { PREFIX_TABLE (PREFIX_0F3881) },
6977     { PREFIX_TABLE (PREFIX_0F3882) },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 88 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 90 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 98 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* a0 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* a8 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* b0 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* b8 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* c0 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* c8 */
7056     { PREFIX_TABLE (PREFIX_0F38C8) },
7057     { PREFIX_TABLE (PREFIX_0F38C9) },
7058     { PREFIX_TABLE (PREFIX_0F38CA) },
7059     { PREFIX_TABLE (PREFIX_0F38CB) },
7060     { PREFIX_TABLE (PREFIX_0F38CC) },
7061     { PREFIX_TABLE (PREFIX_0F38CD) },
7062     { Bad_Opcode },
7063     { PREFIX_TABLE (PREFIX_0F38CF) },
7064     /* d0 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* d8 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { PREFIX_TABLE (PREFIX_0F38DB) },
7078     { PREFIX_TABLE (PREFIX_0F38DC) },
7079     { PREFIX_TABLE (PREFIX_0F38DD) },
7080     { PREFIX_TABLE (PREFIX_0F38DE) },
7081     { PREFIX_TABLE (PREFIX_0F38DF) },
7082     /* e0 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* e8 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* f0 */
7101     { PREFIX_TABLE (PREFIX_0F38F0) },
7102     { PREFIX_TABLE (PREFIX_0F38F1) },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { PREFIX_TABLE (PREFIX_0F38F5) },
7107     { PREFIX_TABLE (PREFIX_0F38F6) },
7108     { Bad_Opcode },
7109     /* f8 */
7110     { PREFIX_TABLE (PREFIX_0F38F8) },
7111     { PREFIX_TABLE (PREFIX_0F38F9) },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118   },
7119   /* THREE_BYTE_0F3A */
7120   {
7121     /* 00 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* 08 */
7131     { PREFIX_TABLE (PREFIX_0F3A08) },
7132     { PREFIX_TABLE (PREFIX_0F3A09) },
7133     { PREFIX_TABLE (PREFIX_0F3A0A) },
7134     { PREFIX_TABLE (PREFIX_0F3A0B) },
7135     { PREFIX_TABLE (PREFIX_0F3A0C) },
7136     { PREFIX_TABLE (PREFIX_0F3A0D) },
7137     { PREFIX_TABLE (PREFIX_0F3A0E) },
7138     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7139     /* 10 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { PREFIX_TABLE (PREFIX_0F3A14) },
7145     { PREFIX_TABLE (PREFIX_0F3A15) },
7146     { PREFIX_TABLE (PREFIX_0F3A16) },
7147     { PREFIX_TABLE (PREFIX_0F3A17) },
7148     /* 18 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* 20 */
7158     { PREFIX_TABLE (PREFIX_0F3A20) },
7159     { PREFIX_TABLE (PREFIX_0F3A21) },
7160     { PREFIX_TABLE (PREFIX_0F3A22) },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 28 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 30 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 38 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 40 */
7194     { PREFIX_TABLE (PREFIX_0F3A40) },
7195     { PREFIX_TABLE (PREFIX_0F3A41) },
7196     { PREFIX_TABLE (PREFIX_0F3A42) },
7197     { Bad_Opcode },
7198     { PREFIX_TABLE (PREFIX_0F3A44) },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 48 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 50 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 58 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 60 */
7230     { PREFIX_TABLE (PREFIX_0F3A60) },
7231     { PREFIX_TABLE (PREFIX_0F3A61) },
7232     { PREFIX_TABLE (PREFIX_0F3A62) },
7233     { PREFIX_TABLE (PREFIX_0F3A63) },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 68 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 70 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 78 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 80 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 88 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 90 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 98 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* a0 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* a8 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* b0 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* b8 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* c0 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* c8 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { PREFIX_TABLE (PREFIX_0F3ACC) },
7352     { Bad_Opcode },
7353     { PREFIX_TABLE (PREFIX_0F3ACE) },
7354     { PREFIX_TABLE (PREFIX_0F3ACF) },
7355     /* d0 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* d8 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { PREFIX_TABLE (PREFIX_0F3ADF) },
7373     /* e0 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* e8 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* f0 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* f8 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409   },
7410 };
7411
7412 static const struct dis386 xop_table[][256] = {
7413   /* XOP_08 */
7414   {
7415     /* 00 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 08 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 10 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 18 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 20 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 28 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 30 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 38 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 40 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 48 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 50 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 58 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 60 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 68 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 70 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 78 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 80 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7566     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7567     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7568     /* 88 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7576     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7577     /* 90 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7584     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7585     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7586     /* 98 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7594     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7595     /* a0 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7599     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7603     { Bad_Opcode },
7604     /* a8 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* b0 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7621     { Bad_Opcode },
7622     /* b8 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* c0 */
7632     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7633     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7634     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7635     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* c8 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7646     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7647     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7648     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7649     /* d0 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* d8 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* e0 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* e8 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7683     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7684     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7685     /* f0 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* f8 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703   },
7704   /* XOP_09 */
7705   {
7706     /* 00 */
7707     { Bad_Opcode },
7708     { REG_TABLE (REG_XOP_TBM_01) },
7709     { REG_TABLE (REG_XOP_TBM_02) },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* 08 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 10 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { REG_TABLE (REG_XOP_LWPCB) },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 18 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 20 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 28 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 30 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 38 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 40 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 48 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 50 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 58 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 60 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 68 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 70 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 78 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 80 */
7851     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7852     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7853     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7854     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 88 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 90 */
7869     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7870     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7871     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7872     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7873     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7874     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7875     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7876     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7877     /* 98 */
7878     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7879     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7880     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7881     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* a0 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* a8 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* b0 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* b8 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* c0 */
7923     { Bad_Opcode },
7924     { "vphaddbw",       { XM, EXxmm }, 0 },
7925     { "vphaddbd",       { XM, EXxmm }, 0 },
7926     { "vphaddbq",       { XM, EXxmm }, 0 },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { "vphaddwd",       { XM, EXxmm }, 0 },
7930     { "vphaddwq",       { XM, EXxmm }, 0 },
7931     /* c8 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vphadddq",       { XM, EXxmm }, 0 },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* d0 */
7941     { Bad_Opcode },
7942     { "vphaddubw",      { XM, EXxmm }, 0 },
7943     { "vphaddubd",      { XM, EXxmm }, 0 },
7944     { "vphaddubq",      { XM, EXxmm }, 0 },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { "vphadduwd",      { XM, EXxmm }, 0 },
7948     { "vphadduwq",      { XM, EXxmm }, 0 },
7949     /* d8 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { "vphaddudq",      { XM, EXxmm }, 0 },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* e0 */
7959     { Bad_Opcode },
7960     { "vphsubbw",       { XM, EXxmm }, 0 },
7961     { "vphsubwd",       { XM, EXxmm }, 0 },
7962     { "vphsubdq",       { XM, EXxmm }, 0 },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* e8 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* f0 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* f8 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994   },
7995   /* XOP_0A */
7996   {
7997     /* 00 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* 08 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 10 */
8016     { "bextrS", { Gdq, Edq, Id }, 0 },
8017     { Bad_Opcode },
8018     { REG_TABLE (REG_XOP_LWP) },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 18 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 20 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 28 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 30 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 38 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 40 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 48 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 50 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 58 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 60 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 68 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 70 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 78 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 80 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 88 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 90 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 98 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* a0 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* a8 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* b0 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* b8 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* c0 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* c8 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* d0 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* d8 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* e0 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* e8 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* f0 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* f8 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285   },
8286 };
8287
8288 static const struct dis386 vex_table[][256] = {
8289   /* VEX_0F */
8290   {
8291     /* 00 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 08 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 10 */
8310     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8311     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8312     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8313     { MOD_TABLE (MOD_VEX_0F13) },
8314     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8315     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8316     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8317     { MOD_TABLE (MOD_VEX_0F17) },
8318     /* 18 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 20 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 28 */
8337     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8338     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8339     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8340     { MOD_TABLE (MOD_VEX_0F2B) },
8341     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8342     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8343     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8344     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8345     /* 30 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 38 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 40 */
8364     { Bad_Opcode },
8365     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8366     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8367     { Bad_Opcode },
8368     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8369     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8370     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8371     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8372     /* 48 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8376     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* 50 */
8382     { MOD_TABLE (MOD_VEX_0F50) },
8383     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8384     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8386     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8387     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8388     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8389     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8390     /* 58 */
8391     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8395     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8396     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8399     /* 60 */
8400     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8405     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8408     /* 68 */
8409     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8417     /* 70 */
8418     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8419     { REG_TABLE (REG_VEX_0F71) },
8420     { REG_TABLE (REG_VEX_0F72) },
8421     { REG_TABLE (REG_VEX_0F73) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8426     /* 78 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8435     /* 80 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 88 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 90 */
8454     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* 98 */
8463     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* a0 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* a8 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { REG_TABLE (REG_VEX_0FAE) },
8488     { Bad_Opcode },
8489     /* b0 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* b8 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* c0 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8511     { Bad_Opcode },
8512     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8513     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8514     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8515     { Bad_Opcode },
8516     /* c8 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* d0 */
8526     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8527     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8528     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8529     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8530     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8531     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8532     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8533     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8534     /* d8 */
8535     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8536     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8537     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8538     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8539     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8540     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8541     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8542     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8543     /* e0 */
8544     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8552     /* e8 */
8553     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8561     /* f0 */
8562     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8570     /* f8 */
8571     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8578     { Bad_Opcode },
8579   },
8580   /* VEX_0F38 */
8581   {
8582     /* 00 */
8583     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8591     /* 08 */
8592     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8600     /* 10 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8609     /* 18 */
8610     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8613     { Bad_Opcode },
8614     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8617     { Bad_Opcode },
8618     /* 20 */
8619     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* 28 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8636     /* 30 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8645     /* 38 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8654     /* 40 */
8655     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8663     /* 48 */
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     /* 50 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 58 */
8682     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 60 */
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 68 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 70 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 78 */
8718     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 80 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* 88 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8741     { Bad_Opcode },
8742     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8743     { Bad_Opcode },
8744     /* 90 */
8745     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8753     /* 98 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8762     /* a0 */
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8771     /* a8 */
8772     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8780     /* b0 */
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8789     /* b8 */
8790     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8798     /* c0 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     /* c8 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8816     /* d0 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* d8 */
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8834     /* e0 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* e8 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     /* f0 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8856     { REG_TABLE (REG_VEX_0F38F3) },
8857     { Bad_Opcode },
8858     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8861     /* f8 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870   },
8871   /* VEX_0F3A */
8872   {
8873     /* 00 */
8874     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8877     { Bad_Opcode },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8881     { Bad_Opcode },
8882     /* 08 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8891     /* 10 */
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8900     /* 18 */
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     /* 20 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     /* 28 */
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 30 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* 38 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* 40 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8949     { Bad_Opcode },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8951     { Bad_Opcode },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8953     { Bad_Opcode },
8954     /* 48 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* 50 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 58 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8981     /* 60 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* 68 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8999     /* 70 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     /* 78 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9017     /* 80 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 88 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 90 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 98 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* a0 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* a8 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* b0 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* b8 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* c0 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* c8 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9106     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9107     /* d0 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* d8 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9125     /* e0 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* e8 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* f0 */
9144     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* f8 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161   },
9162 };
9163
9164 #include "i386-dis-evex.h"
9165
9166 static const struct dis386 vex_len_table[][2] = {
9167   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9168   {
9169     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9170   },
9171
9172   /* VEX_LEN_0F12_P_0_M_1 */
9173   {
9174     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9175   },
9176
9177   /* VEX_LEN_0F13_M_0 */
9178   {
9179     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9180   },
9181
9182   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9183   {
9184     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9185   },
9186
9187   /* VEX_LEN_0F16_P_0_M_1 */
9188   {
9189     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9190   },
9191
9192   /* VEX_LEN_0F17_M_0 */
9193   {
9194     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9195   },
9196
9197   /* VEX_LEN_0F41_P_0 */
9198   {
9199     { Bad_Opcode },
9200     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9201   },
9202   /* VEX_LEN_0F41_P_2 */
9203   {
9204     { Bad_Opcode },
9205     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9206   },
9207   /* VEX_LEN_0F42_P_0 */
9208   {
9209     { Bad_Opcode },
9210     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9211   },
9212   /* VEX_LEN_0F42_P_2 */
9213   {
9214     { Bad_Opcode },
9215     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9216   },
9217   /* VEX_LEN_0F44_P_0 */
9218   {
9219     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9220   },
9221   /* VEX_LEN_0F44_P_2 */
9222   {
9223     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9224   },
9225   /* VEX_LEN_0F45_P_0 */
9226   {
9227     { Bad_Opcode },
9228     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9229   },
9230   /* VEX_LEN_0F45_P_2 */
9231   {
9232     { Bad_Opcode },
9233     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9234   },
9235   /* VEX_LEN_0F46_P_0 */
9236   {
9237     { Bad_Opcode },
9238     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9239   },
9240   /* VEX_LEN_0F46_P_2 */
9241   {
9242     { Bad_Opcode },
9243     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9244   },
9245   /* VEX_LEN_0F47_P_0 */
9246   {
9247     { Bad_Opcode },
9248     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9249   },
9250   /* VEX_LEN_0F47_P_2 */
9251   {
9252     { Bad_Opcode },
9253     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9254   },
9255   /* VEX_LEN_0F4A_P_0 */
9256   {
9257     { Bad_Opcode },
9258     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9259   },
9260   /* VEX_LEN_0F4A_P_2 */
9261   {
9262     { Bad_Opcode },
9263     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9264   },
9265   /* VEX_LEN_0F4B_P_0 */
9266   {
9267     { Bad_Opcode },
9268     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9269   },
9270   /* VEX_LEN_0F4B_P_2 */
9271   {
9272     { Bad_Opcode },
9273     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9274   },
9275
9276   /* VEX_LEN_0F6E_P_2 */
9277   {
9278     { "vmovK",          { XMScalar, Edq }, 0 },
9279   },
9280
9281   /* VEX_LEN_0F77_P_1 */
9282   {
9283     { "vzeroupper",     { XX }, 0 },
9284     { "vzeroall",       { XX }, 0 },
9285   },
9286
9287   /* VEX_LEN_0F7E_P_1 */
9288   {
9289     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9290   },
9291
9292   /* VEX_LEN_0F7E_P_2 */
9293   {
9294     { "vmovK",          { Edq, XMScalar }, 0 },
9295   },
9296
9297   /* VEX_LEN_0F90_P_0 */
9298   {
9299     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9300   },
9301
9302   /* VEX_LEN_0F90_P_2 */
9303   {
9304     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9305   },
9306
9307   /* VEX_LEN_0F91_P_0 */
9308   {
9309     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9310   },
9311
9312   /* VEX_LEN_0F91_P_2 */
9313   {
9314     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9315   },
9316
9317   /* VEX_LEN_0F92_P_0 */
9318   {
9319     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9320   },
9321
9322   /* VEX_LEN_0F92_P_2 */
9323   {
9324     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9325   },
9326
9327   /* VEX_LEN_0F92_P_3 */
9328   {
9329     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9330   },
9331
9332   /* VEX_LEN_0F93_P_0 */
9333   {
9334     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9335   },
9336
9337   /* VEX_LEN_0F93_P_2 */
9338   {
9339     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9340   },
9341
9342   /* VEX_LEN_0F93_P_3 */
9343   {
9344     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9345   },
9346
9347   /* VEX_LEN_0F98_P_0 */
9348   {
9349     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9350   },
9351
9352   /* VEX_LEN_0F98_P_2 */
9353   {
9354     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9355   },
9356
9357   /* VEX_LEN_0F99_P_0 */
9358   {
9359     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9360   },
9361
9362   /* VEX_LEN_0F99_P_2 */
9363   {
9364     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9365   },
9366
9367   /* VEX_LEN_0FAE_R_2_M_0 */
9368   {
9369     { "vldmxcsr",       { Md }, 0 },
9370   },
9371
9372   /* VEX_LEN_0FAE_R_3_M_0 */
9373   {
9374     { "vstmxcsr",       { Md }, 0 },
9375   },
9376
9377   /* VEX_LEN_0FC4_P_2 */
9378   {
9379     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9380   },
9381
9382   /* VEX_LEN_0FC5_P_2 */
9383   {
9384     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9385   },
9386
9387   /* VEX_LEN_0FD6_P_2 */
9388   {
9389     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9390   },
9391
9392   /* VEX_LEN_0FF7_P_2 */
9393   {
9394     { "vmaskmovdqu",    { XM, XS }, 0 },
9395   },
9396
9397   /* VEX_LEN_0F3816_P_2 */
9398   {
9399     { Bad_Opcode },
9400     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9401   },
9402
9403   /* VEX_LEN_0F3819_P_2 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9407   },
9408
9409   /* VEX_LEN_0F381A_P_2_M_0 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9413   },
9414
9415   /* VEX_LEN_0F3836_P_2 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9419   },
9420
9421   /* VEX_LEN_0F3841_P_2 */
9422   {
9423     { "vphminposuw",    { XM, EXx }, 0 },
9424   },
9425
9426   /* VEX_LEN_0F385A_P_2_M_0 */
9427   {
9428     { Bad_Opcode },
9429     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9430   },
9431
9432   /* VEX_LEN_0F38DB_P_2 */
9433   {
9434     { "vaesimc",        { XM, EXx }, 0 },
9435   },
9436
9437   /* VEX_LEN_0F38F2_P_0 */
9438   {
9439     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9440   },
9441
9442   /* VEX_LEN_0F38F3_R_1_P_0 */
9443   {
9444     { "blsrS",          { VexGdq, Edq }, 0 },
9445   },
9446
9447   /* VEX_LEN_0F38F3_R_2_P_0 */
9448   {
9449     { "blsmskS",        { VexGdq, Edq }, 0 },
9450   },
9451
9452   /* VEX_LEN_0F38F3_R_3_P_0 */
9453   {
9454     { "blsiS",          { VexGdq, Edq }, 0 },
9455   },
9456
9457   /* VEX_LEN_0F38F5_P_0 */
9458   {
9459     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9460   },
9461
9462   /* VEX_LEN_0F38F5_P_1 */
9463   {
9464     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9465   },
9466
9467   /* VEX_LEN_0F38F5_P_3 */
9468   {
9469     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9470   },
9471
9472   /* VEX_LEN_0F38F6_P_3 */
9473   {
9474     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9475   },
9476
9477   /* VEX_LEN_0F38F7_P_0 */
9478   {
9479     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9480   },
9481
9482   /* VEX_LEN_0F38F7_P_1 */
9483   {
9484     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9485   },
9486
9487   /* VEX_LEN_0F38F7_P_2 */
9488   {
9489     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9490   },
9491
9492   /* VEX_LEN_0F38F7_P_3 */
9493   {
9494     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9495   },
9496
9497   /* VEX_LEN_0F3A00_P_2 */
9498   {
9499     { Bad_Opcode },
9500     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9501   },
9502
9503   /* VEX_LEN_0F3A01_P_2 */
9504   {
9505     { Bad_Opcode },
9506     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9507   },
9508
9509   /* VEX_LEN_0F3A06_P_2 */
9510   {
9511     { Bad_Opcode },
9512     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9513   },
9514
9515   /* VEX_LEN_0F3A14_P_2 */
9516   {
9517     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9518   },
9519
9520   /* VEX_LEN_0F3A15_P_2 */
9521   {
9522     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9523   },
9524
9525   /* VEX_LEN_0F3A16_P_2  */
9526   {
9527     { "vpextrK",        { Edq, XM, Ib }, 0 },
9528   },
9529
9530   /* VEX_LEN_0F3A17_P_2 */
9531   {
9532     { "vextractps",     { Edqd, XM, Ib }, 0 },
9533   },
9534
9535   /* VEX_LEN_0F3A18_P_2 */
9536   {
9537     { Bad_Opcode },
9538     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9539   },
9540
9541   /* VEX_LEN_0F3A19_P_2 */
9542   {
9543     { Bad_Opcode },
9544     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9545   },
9546
9547   /* VEX_LEN_0F3A20_P_2 */
9548   {
9549     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9550   },
9551
9552   /* VEX_LEN_0F3A21_P_2 */
9553   {
9554     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F3A22_P_2 */
9558   {
9559     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9560   },
9561
9562   /* VEX_LEN_0F3A30_P_2 */
9563   {
9564     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9565   },
9566
9567   /* VEX_LEN_0F3A31_P_2 */
9568   {
9569     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9570   },
9571
9572   /* VEX_LEN_0F3A32_P_2 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9575   },
9576
9577   /* VEX_LEN_0F3A33_P_2 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9580   },
9581
9582   /* VEX_LEN_0F3A38_P_2 */
9583   {
9584     { Bad_Opcode },
9585     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9586   },
9587
9588   /* VEX_LEN_0F3A39_P_2 */
9589   {
9590     { Bad_Opcode },
9591     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9592   },
9593
9594   /* VEX_LEN_0F3A41_P_2 */
9595   {
9596     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F3A46_P_2 */
9600   {
9601     { Bad_Opcode },
9602     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9603   },
9604
9605   /* VEX_LEN_0F3A60_P_2 */
9606   {
9607     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F3A61_P_2 */
9611   {
9612     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F3A62_P_2 */
9616   {
9617     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F3A63_P_2 */
9621   {
9622     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F3A6A_P_2 */
9626   {
9627     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F3A6B_P_2 */
9631   {
9632     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F3A6E_P_2 */
9636   {
9637     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F3A6F_P_2 */
9641   {
9642     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F3A7A_P_2 */
9646   {
9647     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F3A7B_P_2 */
9651   {
9652     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F3A7E_P_2 */
9656   {
9657     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F3A7F_P_2 */
9661   {
9662     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F3ADF_P_2 */
9666   {
9667     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F3AF0_P_3 */
9671   {
9672     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9673   },
9674
9675   /* VEX_LEN_0FXOP_08_CC */
9676   {
9677      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9678   },
9679
9680   /* VEX_LEN_0FXOP_08_CD */
9681   {
9682      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9683   },
9684
9685   /* VEX_LEN_0FXOP_08_CE */
9686   {
9687      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9688   },
9689
9690   /* VEX_LEN_0FXOP_08_CF */
9691   {
9692      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9693   },
9694
9695   /* VEX_LEN_0FXOP_08_EC */
9696   {
9697      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9698   },
9699
9700   /* VEX_LEN_0FXOP_08_ED */
9701   {
9702      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9703   },
9704
9705   /* VEX_LEN_0FXOP_08_EE */
9706   {
9707      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9708   },
9709
9710   /* VEX_LEN_0FXOP_08_EF */
9711   {
9712      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9713   },
9714
9715   /* VEX_LEN_0FXOP_09_82_W_0 */
9716   {
9717     { "vfrczss",        { XM, EXd }, 0 },
9718   },
9719
9720   /* VEX_LEN_0FXOP_09_83_W_0 */
9721   {
9722     { "vfrczsd",        { XM, EXq }, 0 },
9723   },
9724 };
9725
9726 #include "i386-dis-evex-len.h"
9727
9728 static const struct dis386 vex_w_table[][2] = {
9729   {
9730     /* VEX_W_0F41_P_0_LEN_1 */
9731     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9732     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9733   },
9734   {
9735     /* VEX_W_0F41_P_2_LEN_1 */
9736     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9737     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9738   },
9739   {
9740     /* VEX_W_0F42_P_0_LEN_1 */
9741     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9742     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9743   },
9744   {
9745     /* VEX_W_0F42_P_2_LEN_1 */
9746     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9747     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9748   },
9749   {
9750     /* VEX_W_0F44_P_0_LEN_0 */
9751     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9752     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9753   },
9754   {
9755     /* VEX_W_0F44_P_2_LEN_0 */
9756     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9757     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9758   },
9759   {
9760     /* VEX_W_0F45_P_0_LEN_1 */
9761     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9762     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9763   },
9764   {
9765     /* VEX_W_0F45_P_2_LEN_1 */
9766     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9767     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9768   },
9769   {
9770     /* VEX_W_0F46_P_0_LEN_1 */
9771     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9772     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9773   },
9774   {
9775     /* VEX_W_0F46_P_2_LEN_1 */
9776     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9777     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9778   },
9779   {
9780     /* VEX_W_0F47_P_0_LEN_1 */
9781     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9782     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9783   },
9784   {
9785     /* VEX_W_0F47_P_2_LEN_1 */
9786     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9787     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9788   },
9789   {
9790     /* VEX_W_0F4A_P_0_LEN_1 */
9791     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9792     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9793   },
9794   {
9795     /* VEX_W_0F4A_P_2_LEN_1 */
9796     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9797     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9798   },
9799   {
9800     /* VEX_W_0F4B_P_0_LEN_1 */
9801     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9802     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9803   },
9804   {
9805     /* VEX_W_0F4B_P_2_LEN_1 */
9806     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9807   },
9808   {
9809     /* VEX_W_0F90_P_0_LEN_0 */
9810     { "kmovw",          { MaskG, MaskE }, 0 },
9811     { "kmovq",          { MaskG, MaskE }, 0 },
9812   },
9813   {
9814     /* VEX_W_0F90_P_2_LEN_0 */
9815     { "kmovb",          { MaskG, MaskBDE }, 0 },
9816     { "kmovd",          { MaskG, MaskBDE }, 0 },
9817   },
9818   {
9819     /* VEX_W_0F91_P_0_LEN_0 */
9820     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9821     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9822   },
9823   {
9824     /* VEX_W_0F91_P_2_LEN_0 */
9825     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9826     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9827   },
9828   {
9829     /* VEX_W_0F92_P_0_LEN_0 */
9830     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9831   },
9832   {
9833     /* VEX_W_0F92_P_2_LEN_0 */
9834     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9835   },
9836   {
9837     /* VEX_W_0F93_P_0_LEN_0 */
9838     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9839   },
9840   {
9841     /* VEX_W_0F93_P_2_LEN_0 */
9842     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9843   },
9844   {
9845     /* VEX_W_0F98_P_0_LEN_0 */
9846     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9847     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9848   },
9849   {
9850     /* VEX_W_0F98_P_2_LEN_0 */
9851     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9852     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9853   },
9854   {
9855     /* VEX_W_0F99_P_0_LEN_0 */
9856     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9857     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9858   },
9859   {
9860     /* VEX_W_0F99_P_2_LEN_0 */
9861     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9862     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9863   },
9864   {
9865     /* VEX_W_0F380C_P_2  */
9866     { "vpermilps",      { XM, Vex, EXx }, 0 },
9867   },
9868   {
9869     /* VEX_W_0F380D_P_2  */
9870     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9871   },
9872   {
9873     /* VEX_W_0F380E_P_2  */
9874     { "vtestps",        { XM, EXx }, 0 },
9875   },
9876   {
9877     /* VEX_W_0F380F_P_2  */
9878     { "vtestpd",        { XM, EXx }, 0 },
9879   },
9880   {
9881     /* VEX_W_0F3813_P_2 */
9882     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9883   },
9884   {
9885     /* VEX_W_0F3816_P_2  */
9886     { "vpermps",        { XM, Vex, EXx }, 0 },
9887   },
9888   {
9889     /* VEX_W_0F3818_P_2 */
9890     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9891   },
9892   {
9893     /* VEX_W_0F3819_P_2 */
9894     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9895   },
9896   {
9897     /* VEX_W_0F381A_P_2_M_0 */
9898     { "vbroadcastf128", { XM, Mxmm }, 0 },
9899   },
9900   {
9901     /* VEX_W_0F382C_P_2_M_0 */
9902     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9903   },
9904   {
9905     /* VEX_W_0F382D_P_2_M_0 */
9906     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9907   },
9908   {
9909     /* VEX_W_0F382E_P_2_M_0 */
9910     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9911   },
9912   {
9913     /* VEX_W_0F382F_P_2_M_0 */
9914     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9915   },
9916   {
9917     /* VEX_W_0F3836_P_2  */
9918     { "vpermd",         { XM, Vex, EXx }, 0 },
9919   },
9920   {
9921     /* VEX_W_0F3846_P_2 */
9922     { "vpsravd",        { XM, Vex, EXx }, 0 },
9923   },
9924   {
9925     /* VEX_W_0F3858_P_2 */
9926     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9927   },
9928   {
9929     /* VEX_W_0F3859_P_2 */
9930     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9931   },
9932   {
9933     /* VEX_W_0F385A_P_2_M_0 */
9934     { "vbroadcasti128", { XM, Mxmm }, 0 },
9935   },
9936   {
9937     /* VEX_W_0F3878_P_2 */
9938     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9939   },
9940   {
9941     /* VEX_W_0F3879_P_2 */
9942     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9943   },
9944   {
9945     /* VEX_W_0F38CF_P_2 */
9946     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9947   },
9948   {
9949     /* VEX_W_0F3A00_P_2 */
9950     { Bad_Opcode },
9951     { "vpermq",         { XM, EXx, Ib }, 0 },
9952   },
9953   {
9954     /* VEX_W_0F3A01_P_2 */
9955     { Bad_Opcode },
9956     { "vpermpd",        { XM, EXx, Ib }, 0 },
9957   },
9958   {
9959     /* VEX_W_0F3A02_P_2 */
9960     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9961   },
9962   {
9963     /* VEX_W_0F3A04_P_2 */
9964     { "vpermilps",      { XM, EXx, Ib }, 0 },
9965   },
9966   {
9967     /* VEX_W_0F3A05_P_2 */
9968     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F3A06_P_2 */
9972     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9973   },
9974   {
9975     /* VEX_W_0F3A18_P_2 */
9976     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9977   },
9978   {
9979     /* VEX_W_0F3A19_P_2 */
9980     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
9981   },
9982   {
9983     /* VEX_W_0F3A1D_P_2 */
9984     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F3A30_P_2_LEN_0 */
9988     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
9989     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
9990   },
9991   {
9992     /* VEX_W_0F3A31_P_2_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
9994     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F3A32_P_2_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
9999     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10000   },
10001   {
10002     /* VEX_W_0F3A33_P_2_LEN_0 */
10003     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10004     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F3A38_P_2 */
10008     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10009   },
10010   {
10011     /* VEX_W_0F3A39_P_2 */
10012     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10013   },
10014   {
10015     /* VEX_W_0F3A46_P_2 */
10016     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10017   },
10018   {
10019     /* VEX_W_0F3A4A_P_2 */
10020     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10021   },
10022   {
10023     /* VEX_W_0F3A4B_P_2 */
10024     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10025   },
10026   {
10027     /* VEX_W_0F3A4C_P_2 */
10028     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10029   },
10030   {
10031     /* VEX_W_0F3ACE_P_2 */
10032     { Bad_Opcode },
10033     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10034   },
10035   {
10036     /* VEX_W_0F3ACF_P_2 */
10037     { Bad_Opcode },
10038     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10039   },
10040   /* VEX_W_0FXOP_09_80 */
10041   {
10042     { "vfrczps",        { XM, EXx }, 0 },
10043   },
10044   /* VEX_W_0FXOP_09_81 */
10045   {
10046     { "vfrczpd",        { XM, EXx }, 0 },
10047   },
10048   /* VEX_W_0FXOP_09_82 */
10049   {
10050     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10051   },
10052   /* VEX_W_0FXOP_09_83 */
10053   {
10054     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10055   },
10056
10057 #include "i386-dis-evex-w.h"
10058 };
10059
10060 static const struct dis386 mod_table[][2] = {
10061   {
10062     /* MOD_8D */
10063     { "leaS",           { Gv, M }, 0 },
10064   },
10065   {
10066     /* MOD_C6_REG_7 */
10067     { Bad_Opcode },
10068     { RM_TABLE (RM_C6_REG_7) },
10069   },
10070   {
10071     /* MOD_C7_REG_7 */
10072     { Bad_Opcode },
10073     { RM_TABLE (RM_C7_REG_7) },
10074   },
10075   {
10076     /* MOD_FF_REG_3 */
10077     { "{l|}call^", { indirEp }, 0 },
10078   },
10079   {
10080     /* MOD_FF_REG_5 */
10081     { "{l|}jmp^", { indirEp }, 0 },
10082   },
10083   {
10084     /* MOD_0F01_REG_0 */
10085     { X86_64_TABLE (X86_64_0F01_REG_0) },
10086     { RM_TABLE (RM_0F01_REG_0) },
10087   },
10088   {
10089     /* MOD_0F01_REG_1 */
10090     { X86_64_TABLE (X86_64_0F01_REG_1) },
10091     { RM_TABLE (RM_0F01_REG_1) },
10092   },
10093   {
10094     /* MOD_0F01_REG_2 */
10095     { X86_64_TABLE (X86_64_0F01_REG_2) },
10096     { RM_TABLE (RM_0F01_REG_2) },
10097   },
10098   {
10099     /* MOD_0F01_REG_3 */
10100     { X86_64_TABLE (X86_64_0F01_REG_3) },
10101     { RM_TABLE (RM_0F01_REG_3) },
10102   },
10103   {
10104     /* MOD_0F01_REG_5 */
10105     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10106     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10107   },
10108   {
10109     /* MOD_0F01_REG_7 */
10110     { "invlpg",         { Mb }, 0 },
10111     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10112   },
10113   {
10114     /* MOD_0F12_PREFIX_0 */
10115     { "movlpX",         { XM, EXq }, 0 },
10116     { "movhlps",        { XM, EXq }, 0 },
10117   },
10118   {
10119     /* MOD_0F12_PREFIX_2 */
10120     { "movlpX", { XM, EXq }, 0 },
10121   },
10122   {
10123     /* MOD_0F13 */
10124     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10125   },
10126   {
10127     /* MOD_0F16_PREFIX_0 */
10128     { "movhpX",         { XM, EXq }, 0 },
10129     { "movlhps",        { XM, EXq }, 0 },
10130   },
10131   {
10132     /* MOD_0F16_PREFIX_2 */
10133     { "movhpX", { XM, EXq }, 0 },
10134   },
10135   {
10136     /* MOD_0F17 */
10137     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10138   },
10139   {
10140     /* MOD_0F18_REG_0 */
10141     { "prefetchnta",    { Mb }, 0 },
10142   },
10143   {
10144     /* MOD_0F18_REG_1 */
10145     { "prefetcht0",     { Mb }, 0 },
10146   },
10147   {
10148     /* MOD_0F18_REG_2 */
10149     { "prefetcht1",     { Mb }, 0 },
10150   },
10151   {
10152     /* MOD_0F18_REG_3 */
10153     { "prefetcht2",     { Mb }, 0 },
10154   },
10155   {
10156     /* MOD_0F18_REG_4 */
10157     { "nop/reserved",   { Mb }, 0 },
10158   },
10159   {
10160     /* MOD_0F18_REG_5 */
10161     { "nop/reserved",   { Mb }, 0 },
10162   },
10163   {
10164     /* MOD_0F18_REG_6 */
10165     { "nop/reserved",   { Mb }, 0 },
10166   },
10167   {
10168     /* MOD_0F18_REG_7 */
10169     { "nop/reserved",   { Mb }, 0 },
10170   },
10171   {
10172     /* MOD_0F1A_PREFIX_0 */
10173     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10174     { "nopQ",           { Ev }, 0 },
10175   },
10176   {
10177     /* MOD_0F1B_PREFIX_0 */
10178     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10179     { "nopQ",           { Ev }, 0 },
10180   },
10181   {
10182     /* MOD_0F1B_PREFIX_1 */
10183     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10184     { "nopQ",           { Ev }, 0 },
10185   },
10186   {
10187     /* MOD_0F1C_PREFIX_0 */
10188     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10189     { "nopQ",           { Ev }, 0 },
10190   },
10191   {
10192     /* MOD_0F1E_PREFIX_1 */
10193     { "nopQ",           { Ev }, 0 },
10194     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10195   },
10196   {
10197     /* MOD_0F24 */
10198     { Bad_Opcode },
10199     { "movL",           { Rd, Td }, 0 },
10200   },
10201   {
10202     /* MOD_0F26 */
10203     { Bad_Opcode },
10204     { "movL",           { Td, Rd }, 0 },
10205   },
10206   {
10207     /* MOD_0F2B_PREFIX_0 */
10208     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10209   },
10210   {
10211     /* MOD_0F2B_PREFIX_1 */
10212     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10213   },
10214   {
10215     /* MOD_0F2B_PREFIX_2 */
10216     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10217   },
10218   {
10219     /* MOD_0F2B_PREFIX_3 */
10220     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10221   },
10222   {
10223     /* MOD_0F50 */
10224     { Bad_Opcode },
10225     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10226   },
10227   {
10228     /* MOD_0F71_REG_2 */
10229     { Bad_Opcode },
10230     { "psrlw",          { MS, Ib }, 0 },
10231   },
10232   {
10233     /* MOD_0F71_REG_4 */
10234     { Bad_Opcode },
10235     { "psraw",          { MS, Ib }, 0 },
10236   },
10237   {
10238     /* MOD_0F71_REG_6 */
10239     { Bad_Opcode },
10240     { "psllw",          { MS, Ib }, 0 },
10241   },
10242   {
10243     /* MOD_0F72_REG_2 */
10244     { Bad_Opcode },
10245     { "psrld",          { MS, Ib }, 0 },
10246   },
10247   {
10248     /* MOD_0F72_REG_4 */
10249     { Bad_Opcode },
10250     { "psrad",          { MS, Ib }, 0 },
10251   },
10252   {
10253     /* MOD_0F72_REG_6 */
10254     { Bad_Opcode },
10255     { "pslld",          { MS, Ib }, 0 },
10256   },
10257   {
10258     /* MOD_0F73_REG_2 */
10259     { Bad_Opcode },
10260     { "psrlq",          { MS, Ib }, 0 },
10261   },
10262   {
10263     /* MOD_0F73_REG_3 */
10264     { Bad_Opcode },
10265     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10266   },
10267   {
10268     /* MOD_0F73_REG_6 */
10269     { Bad_Opcode },
10270     { "psllq",          { MS, Ib }, 0 },
10271   },
10272   {
10273     /* MOD_0F73_REG_7 */
10274     { Bad_Opcode },
10275     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10276   },
10277   {
10278     /* MOD_0FAE_REG_0 */
10279     { "fxsave",         { FXSAVE }, 0 },
10280     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10281   },
10282   {
10283     /* MOD_0FAE_REG_1 */
10284     { "fxrstor",        { FXSAVE }, 0 },
10285     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10286   },
10287   {
10288     /* MOD_0FAE_REG_2 */
10289     { "ldmxcsr",        { Md }, 0 },
10290     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10291   },
10292   {
10293     /* MOD_0FAE_REG_3 */
10294     { "stmxcsr",        { Md }, 0 },
10295     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10296   },
10297   {
10298     /* MOD_0FAE_REG_4 */
10299     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10300     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10301   },
10302   {
10303     /* MOD_0FAE_REG_5 */
10304     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10305     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10306   },
10307   {
10308     /* MOD_0FAE_REG_6 */
10309     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10310     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10311   },
10312   {
10313     /* MOD_0FAE_REG_7 */
10314     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10315     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10316   },
10317   {
10318     /* MOD_0FB2 */
10319     { "lssS",           { Gv, Mp }, 0 },
10320   },
10321   {
10322     /* MOD_0FB4 */
10323     { "lfsS",           { Gv, Mp }, 0 },
10324   },
10325   {
10326     /* MOD_0FB5 */
10327     { "lgsS",           { Gv, Mp }, 0 },
10328   },
10329   {
10330     /* MOD_0FC3 */
10331     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10332   },
10333   {
10334     /* MOD_0FC7_REG_3 */
10335     { "xrstors",        { FXSAVE }, 0 },
10336   },
10337   {
10338     /* MOD_0FC7_REG_4 */
10339     { "xsavec",         { FXSAVE }, 0 },
10340   },
10341   {
10342     /* MOD_0FC7_REG_5 */
10343     { "xsaves",         { FXSAVE }, 0 },
10344   },
10345   {
10346     /* MOD_0FC7_REG_6 */
10347     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10348     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10349   },
10350   {
10351     /* MOD_0FC7_REG_7 */
10352     { "vmptrst",        { Mq }, 0 },
10353     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10354   },
10355   {
10356     /* MOD_0FD7 */
10357     { Bad_Opcode },
10358     { "pmovmskb",       { Gdq, MS }, 0 },
10359   },
10360   {
10361     /* MOD_0FE7_PREFIX_2 */
10362     { "movntdq",        { Mx, XM }, 0 },
10363   },
10364   {
10365     /* MOD_0FF0_PREFIX_3 */
10366     { "lddqu",          { XM, M }, 0 },
10367   },
10368   {
10369     /* MOD_0F382A_PREFIX_2 */
10370     { "movntdqa",       { XM, Mx }, 0 },
10371   },
10372   {
10373     /* MOD_0F38F5_PREFIX_2 */
10374     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10375   },
10376   {
10377     /* MOD_0F38F6_PREFIX_0 */
10378     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10379   },
10380   {
10381     /* MOD_0F38F8_PREFIX_1 */
10382     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10383   },
10384   {
10385     /* MOD_0F38F8_PREFIX_2 */
10386     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10387   },
10388   {
10389     /* MOD_0F38F8_PREFIX_3 */
10390     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10391   },
10392   {
10393     /* MOD_0F38F9_PREFIX_0 */
10394     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10395   },
10396   {
10397     /* MOD_62_32BIT */
10398     { "bound{S|}",      { Gv, Ma }, 0 },
10399     { EVEX_TABLE (EVEX_0F) },
10400   },
10401   {
10402     /* MOD_C4_32BIT */
10403     { "lesS",           { Gv, Mp }, 0 },
10404     { VEX_C4_TABLE (VEX_0F) },
10405   },
10406   {
10407     /* MOD_C5_32BIT */
10408     { "ldsS",           { Gv, Mp }, 0 },
10409     { VEX_C5_TABLE (VEX_0F) },
10410   },
10411   {
10412     /* MOD_VEX_0F12_PREFIX_0 */
10413     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10414     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10415   },
10416   {
10417     /* MOD_VEX_0F12_PREFIX_2 */
10418     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10419   },
10420   {
10421     /* MOD_VEX_0F13 */
10422     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10423   },
10424   {
10425     /* MOD_VEX_0F16_PREFIX_0 */
10426     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10427     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10428   },
10429   {
10430     /* MOD_VEX_0F16_PREFIX_2 */
10431     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10432   },
10433   {
10434     /* MOD_VEX_0F17 */
10435     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10436   },
10437   {
10438     /* MOD_VEX_0F2B */
10439     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10440   },
10441   {
10442     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10443     { Bad_Opcode },
10444     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10445   },
10446   {
10447     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10448     { Bad_Opcode },
10449     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10450   },
10451   {
10452     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10453     { Bad_Opcode },
10454     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10455   },
10456   {
10457     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10458     { Bad_Opcode },
10459     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10460   },
10461   {
10462     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10463     { Bad_Opcode },
10464     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10465   },
10466   {
10467     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10468     { Bad_Opcode },
10469     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10470   },
10471   {
10472     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10473     { Bad_Opcode },
10474     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10475   },
10476   {
10477     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10478     { Bad_Opcode },
10479     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10480   },
10481   {
10482     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10483     { Bad_Opcode },
10484     { "knotw",          { MaskG, MaskR }, 0 },
10485   },
10486   {
10487     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10488     { Bad_Opcode },
10489     { "knotq",          { MaskG, MaskR }, 0 },
10490   },
10491   {
10492     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10493     { Bad_Opcode },
10494     { "knotb",          { MaskG, MaskR }, 0 },
10495   },
10496   {
10497     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10498     { Bad_Opcode },
10499     { "knotd",          { MaskG, MaskR }, 0 },
10500   },
10501   {
10502     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10503     { Bad_Opcode },
10504     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10505   },
10506   {
10507     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10508     { Bad_Opcode },
10509     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10510   },
10511   {
10512     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10513     { Bad_Opcode },
10514     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10515   },
10516   {
10517     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10518     { Bad_Opcode },
10519     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10520   },
10521  {
10522     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10523     { Bad_Opcode },
10524     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10525   },
10526   {
10527     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10528     { Bad_Opcode },
10529     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10530   },
10531   {
10532     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10533     { Bad_Opcode },
10534     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10535   },
10536   {
10537     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10538     { Bad_Opcode },
10539     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10540   },
10541   {
10542     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10543     { Bad_Opcode },
10544     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10545   },
10546   {
10547     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10548     { Bad_Opcode },
10549     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10550   },
10551   {
10552     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10553     { Bad_Opcode },
10554     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10555   },
10556   {
10557     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10558     { Bad_Opcode },
10559     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10560   },
10561   {
10562     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10563     { Bad_Opcode },
10564     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10573     { Bad_Opcode },
10574     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10583     { Bad_Opcode },
10584     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10593     { Bad_Opcode },
10594     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_0F50 */
10598     { Bad_Opcode },
10599     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10600   },
10601   {
10602     /* MOD_VEX_0F71_REG_2 */
10603     { Bad_Opcode },
10604     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10605   },
10606   {
10607     /* MOD_VEX_0F71_REG_4 */
10608     { Bad_Opcode },
10609     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10610   },
10611   {
10612     /* MOD_VEX_0F71_REG_6 */
10613     { Bad_Opcode },
10614     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10615   },
10616   {
10617     /* MOD_VEX_0F72_REG_2 */
10618     { Bad_Opcode },
10619     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10620   },
10621   {
10622     /* MOD_VEX_0F72_REG_4 */
10623     { Bad_Opcode },
10624     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10625   },
10626   {
10627     /* MOD_VEX_0F72_REG_6 */
10628     { Bad_Opcode },
10629     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10630   },
10631   {
10632     /* MOD_VEX_0F73_REG_2 */
10633     { Bad_Opcode },
10634     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10635   },
10636   {
10637     /* MOD_VEX_0F73_REG_3 */
10638     { Bad_Opcode },
10639     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10640   },
10641   {
10642     /* MOD_VEX_0F73_REG_6 */
10643     { Bad_Opcode },
10644     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10645   },
10646   {
10647     /* MOD_VEX_0F73_REG_7 */
10648     { Bad_Opcode },
10649     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10653     { "kmovw",          { Ew, MaskG }, 0 },
10654     { Bad_Opcode },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10658     { "kmovq",          { Eq, MaskG }, 0 },
10659     { Bad_Opcode },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10663     { "kmovb",          { Eb, MaskG }, 0 },
10664     { Bad_Opcode },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10668     { "kmovd",          { Ed, MaskG }, 0 },
10669     { Bad_Opcode },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10673     { Bad_Opcode },
10674     { "kmovw",          { MaskG, Rdq }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10678     { Bad_Opcode },
10679     { "kmovb",          { MaskG, Rdq }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_0F92_P_3_LEN_0 */
10683     { Bad_Opcode },
10684     { "kmovK",          { MaskG, Rdq }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10688     { Bad_Opcode },
10689     { "kmovw",          { Gdq, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10693     { Bad_Opcode },
10694     { "kmovb",          { Gdq, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_0F93_P_3_LEN_0 */
10698     { Bad_Opcode },
10699     { "kmovK",          { Gdq, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10703     { Bad_Opcode },
10704     { "kortestw", { MaskG, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10708     { Bad_Opcode },
10709     { "kortestq", { MaskG, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10713     { Bad_Opcode },
10714     { "kortestb", { MaskG, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10718     { Bad_Opcode },
10719     { "kortestd", { MaskG, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10723     { Bad_Opcode },
10724     { "ktestw", { MaskG, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10728     { Bad_Opcode },
10729     { "ktestq", { MaskG, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10733     { Bad_Opcode },
10734     { "ktestb", { MaskG, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10738     { Bad_Opcode },
10739     { "ktestd", { MaskG, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_0FAE_REG_2 */
10743     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10744   },
10745   {
10746     /* MOD_VEX_0FAE_REG_3 */
10747     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10748   },
10749   {
10750     /* MOD_VEX_0FD7_PREFIX_2 */
10751     { Bad_Opcode },
10752     { "vpmovmskb",      { Gdq, XS }, 0 },
10753   },
10754   {
10755     /* MOD_VEX_0FE7_PREFIX_2 */
10756     { "vmovntdq",       { Mx, XM }, 0 },
10757   },
10758   {
10759     /* MOD_VEX_0FF0_PREFIX_3 */
10760     { "vlddqu",         { XM, M }, 0 },
10761   },
10762   {
10763     /* MOD_VEX_0F381A_PREFIX_2 */
10764     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10765   },
10766   {
10767     /* MOD_VEX_0F382A_PREFIX_2 */
10768     { "vmovntdqa",      { XM, Mx }, 0 },
10769   },
10770   {
10771     /* MOD_VEX_0F382C_PREFIX_2 */
10772     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10773   },
10774   {
10775     /* MOD_VEX_0F382D_PREFIX_2 */
10776     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10777   },
10778   {
10779     /* MOD_VEX_0F382E_PREFIX_2 */
10780     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10781   },
10782   {
10783     /* MOD_VEX_0F382F_PREFIX_2 */
10784     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10785   },
10786   {
10787     /* MOD_VEX_0F385A_PREFIX_2 */
10788     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10789   },
10790   {
10791     /* MOD_VEX_0F388C_PREFIX_2 */
10792     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10793   },
10794   {
10795     /* MOD_VEX_0F388E_PREFIX_2 */
10796     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10797   },
10798   {
10799     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10800     { Bad_Opcode },
10801     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10802   },
10803   {
10804     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10805     { Bad_Opcode },
10806     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10807   },
10808   {
10809     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10810     { Bad_Opcode },
10811     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10815     { Bad_Opcode },
10816     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10817   },
10818   {
10819     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10820     { Bad_Opcode },
10821     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10825     { Bad_Opcode },
10826     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10830     { Bad_Opcode },
10831     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10835     { Bad_Opcode },
10836     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10837   },
10838
10839 #include "i386-dis-evex-mod.h"
10840 };
10841
10842 static const struct dis386 rm_table[][8] = {
10843   {
10844     /* RM_C6_REG_7 */
10845     { "xabort",         { Skip_MODRM, Ib }, 0 },
10846   },
10847   {
10848     /* RM_C7_REG_7 */
10849     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10850   },
10851   {
10852     /* RM_0F01_REG_0 */
10853     { "enclv",          { Skip_MODRM }, 0 },
10854     { "vmcall",         { Skip_MODRM }, 0 },
10855     { "vmlaunch",       { Skip_MODRM }, 0 },
10856     { "vmresume",       { Skip_MODRM }, 0 },
10857     { "vmxoff",         { Skip_MODRM }, 0 },
10858     { "pconfig",        { Skip_MODRM }, 0 },
10859   },
10860   {
10861     /* RM_0F01_REG_1 */
10862     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10863     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10864     { "clac",           { Skip_MODRM }, 0 },
10865     { "stac",           { Skip_MODRM }, 0 },
10866     { Bad_Opcode },
10867     { Bad_Opcode },
10868     { Bad_Opcode },
10869     { "encls",          { Skip_MODRM }, 0 },
10870   },
10871   {
10872     /* RM_0F01_REG_2 */
10873     { "xgetbv",         { Skip_MODRM }, 0 },
10874     { "xsetbv",         { Skip_MODRM }, 0 },
10875     { Bad_Opcode },
10876     { Bad_Opcode },
10877     { "vmfunc",         { Skip_MODRM }, 0 },
10878     { "xend",           { Skip_MODRM }, 0 },
10879     { "xtest",          { Skip_MODRM }, 0 },
10880     { "enclu",          { Skip_MODRM }, 0 },
10881   },
10882   {
10883     /* RM_0F01_REG_3 */
10884     { "vmrun",          { Skip_MODRM }, 0 },
10885     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10886     { "vmload",         { Skip_MODRM }, 0 },
10887     { "vmsave",         { Skip_MODRM }, 0 },
10888     { "stgi",           { Skip_MODRM }, 0 },
10889     { "clgi",           { Skip_MODRM }, 0 },
10890     { "skinit",         { Skip_MODRM }, 0 },
10891     { "invlpga",        { Skip_MODRM }, 0 },
10892   },
10893   {
10894     /* RM_0F01_REG_5_MOD_3 */
10895     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10896     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10897     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10898     { Bad_Opcode },
10899     { Bad_Opcode },
10900     { Bad_Opcode },
10901     { "rdpkru",         { Skip_MODRM }, 0 },
10902     { "wrpkru",         { Skip_MODRM }, 0 },
10903   },
10904   {
10905     /* RM_0F01_REG_7_MOD_3 */
10906     { "swapgs",         { Skip_MODRM }, 0  },
10907     { "rdtscp",         { Skip_MODRM }, 0  },
10908     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10909     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10910     { "clzero",         { Skip_MODRM }, 0  },
10911     { "rdpru",          { Skip_MODRM }, 0  },
10912   },
10913   {
10914     /* RM_0F1E_P_1_MOD_3_REG_7 */
10915     { "nopQ",           { Ev }, 0 },
10916     { "nopQ",           { Ev }, 0 },
10917     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10918     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10919     { "nopQ",           { Ev }, 0 },
10920     { "nopQ",           { Ev }, 0 },
10921     { "nopQ",           { Ev }, 0 },
10922     { "nopQ",           { Ev }, 0 },
10923   },
10924   {
10925     /* RM_0FAE_REG_6_MOD_3 */
10926     { "mfence",         { Skip_MODRM }, 0 },
10927   },
10928   {
10929     /* RM_0FAE_REG_7_MOD_3 */
10930     { "sfence",         { Skip_MODRM }, 0 },
10931
10932   },
10933 };
10934
10935 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10936
10937 /* We use the high bit to indicate different name for the same
10938    prefix.  */
10939 #define REP_PREFIX      (0xf3 | 0x100)
10940 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10941 #define XRELEASE_PREFIX (0xf3 | 0x400)
10942 #define BND_PREFIX      (0xf2 | 0x400)
10943 #define NOTRACK_PREFIX  (0x3e | 0x100)
10944
10945 /* Remember if the current op is a jump instruction.  */
10946 static bfd_boolean op_is_jump = FALSE;
10947
10948 static int
10949 ckprefix (void)
10950 {
10951   int newrex, i, length;
10952   rex = 0;
10953   prefixes = 0;
10954   used_prefixes = 0;
10955   rex_used = 0;
10956   last_lock_prefix = -1;
10957   last_repz_prefix = -1;
10958   last_repnz_prefix = -1;
10959   last_data_prefix = -1;
10960   last_addr_prefix = -1;
10961   last_rex_prefix = -1;
10962   last_seg_prefix = -1;
10963   fwait_prefix = -1;
10964   active_seg_prefix = 0;
10965   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10966     all_prefixes[i] = 0;
10967   i = 0;
10968   length = 0;
10969   /* The maximum instruction length is 15bytes.  */
10970   while (length < MAX_CODE_LENGTH - 1)
10971     {
10972       FETCH_DATA (the_info, codep + 1);
10973       newrex = 0;
10974       switch (*codep)
10975         {
10976         /* REX prefixes family.  */
10977         case 0x40:
10978         case 0x41:
10979         case 0x42:
10980         case 0x43:
10981         case 0x44:
10982         case 0x45:
10983         case 0x46:
10984         case 0x47:
10985         case 0x48:
10986         case 0x49:
10987         case 0x4a:
10988         case 0x4b:
10989         case 0x4c:
10990         case 0x4d:
10991         case 0x4e:
10992         case 0x4f:
10993           if (address_mode == mode_64bit)
10994             newrex = *codep;
10995           else
10996             return 1;
10997           last_rex_prefix = i;
10998           break;
10999         case 0xf3:
11000           prefixes |= PREFIX_REPZ;
11001           last_repz_prefix = i;
11002           break;
11003         case 0xf2:
11004           prefixes |= PREFIX_REPNZ;
11005           last_repnz_prefix = i;
11006           break;
11007         case 0xf0:
11008           prefixes |= PREFIX_LOCK;
11009           last_lock_prefix = i;
11010           break;
11011         case 0x2e:
11012           prefixes |= PREFIX_CS;
11013           last_seg_prefix = i;
11014           active_seg_prefix = PREFIX_CS;
11015           break;
11016         case 0x36:
11017           prefixes |= PREFIX_SS;
11018           last_seg_prefix = i;
11019           active_seg_prefix = PREFIX_SS;
11020           break;
11021         case 0x3e:
11022           prefixes |= PREFIX_DS;
11023           last_seg_prefix = i;
11024           active_seg_prefix = PREFIX_DS;
11025           break;
11026         case 0x26:
11027           prefixes |= PREFIX_ES;
11028           last_seg_prefix = i;
11029           active_seg_prefix = PREFIX_ES;
11030           break;
11031         case 0x64:
11032           prefixes |= PREFIX_FS;
11033           last_seg_prefix = i;
11034           active_seg_prefix = PREFIX_FS;
11035           break;
11036         case 0x65:
11037           prefixes |= PREFIX_GS;
11038           last_seg_prefix = i;
11039           active_seg_prefix = PREFIX_GS;
11040           break;
11041         case 0x66:
11042           prefixes |= PREFIX_DATA;
11043           last_data_prefix = i;
11044           break;
11045         case 0x67:
11046           prefixes |= PREFIX_ADDR;
11047           last_addr_prefix = i;
11048           break;
11049         case FWAIT_OPCODE:
11050           /* fwait is really an instruction.  If there are prefixes
11051              before the fwait, they belong to the fwait, *not* to the
11052              following instruction.  */
11053           fwait_prefix = i;
11054           if (prefixes || rex)
11055             {
11056               prefixes |= PREFIX_FWAIT;
11057               codep++;
11058               /* This ensures that the previous REX prefixes are noticed
11059                  as unused prefixes, as in the return case below.  */
11060               rex_used = rex;
11061               return 1;
11062             }
11063           prefixes = PREFIX_FWAIT;
11064           break;
11065         default:
11066           return 1;
11067         }
11068       /* Rex is ignored when followed by another prefix.  */
11069       if (rex)
11070         {
11071           rex_used = rex;
11072           return 1;
11073         }
11074       if (*codep != FWAIT_OPCODE)
11075         all_prefixes[i++] = *codep;
11076       rex = newrex;
11077       codep++;
11078       length++;
11079     }
11080   return 0;
11081 }
11082
11083 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11084    prefix byte.  */
11085
11086 static const char *
11087 prefix_name (int pref, int sizeflag)
11088 {
11089   static const char *rexes [16] =
11090     {
11091       "rex",            /* 0x40 */
11092       "rex.B",          /* 0x41 */
11093       "rex.X",          /* 0x42 */
11094       "rex.XB",         /* 0x43 */
11095       "rex.R",          /* 0x44 */
11096       "rex.RB",         /* 0x45 */
11097       "rex.RX",         /* 0x46 */
11098       "rex.RXB",        /* 0x47 */
11099       "rex.W",          /* 0x48 */
11100       "rex.WB",         /* 0x49 */
11101       "rex.WX",         /* 0x4a */
11102       "rex.WXB",        /* 0x4b */
11103       "rex.WR",         /* 0x4c */
11104       "rex.WRB",        /* 0x4d */
11105       "rex.WRX",        /* 0x4e */
11106       "rex.WRXB",       /* 0x4f */
11107     };
11108
11109   switch (pref)
11110     {
11111     /* REX prefixes family.  */
11112     case 0x40:
11113     case 0x41:
11114     case 0x42:
11115     case 0x43:
11116     case 0x44:
11117     case 0x45:
11118     case 0x46:
11119     case 0x47:
11120     case 0x48:
11121     case 0x49:
11122     case 0x4a:
11123     case 0x4b:
11124     case 0x4c:
11125     case 0x4d:
11126     case 0x4e:
11127     case 0x4f:
11128       return rexes [pref - 0x40];
11129     case 0xf3:
11130       return "repz";
11131     case 0xf2:
11132       return "repnz";
11133     case 0xf0:
11134       return "lock";
11135     case 0x2e:
11136       return "cs";
11137     case 0x36:
11138       return "ss";
11139     case 0x3e:
11140       return "ds";
11141     case 0x26:
11142       return "es";
11143     case 0x64:
11144       return "fs";
11145     case 0x65:
11146       return "gs";
11147     case 0x66:
11148       return (sizeflag & DFLAG) ? "data16" : "data32";
11149     case 0x67:
11150       if (address_mode == mode_64bit)
11151         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11152       else
11153         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11154     case FWAIT_OPCODE:
11155       return "fwait";
11156     case REP_PREFIX:
11157       return "rep";
11158     case XACQUIRE_PREFIX:
11159       return "xacquire";
11160     case XRELEASE_PREFIX:
11161       return "xrelease";
11162     case BND_PREFIX:
11163       return "bnd";
11164     case NOTRACK_PREFIX:
11165       return "notrack";
11166     default:
11167       return NULL;
11168     }
11169 }
11170
11171 static char op_out[MAX_OPERANDS][100];
11172 static int op_ad, op_index[MAX_OPERANDS];
11173 static int two_source_ops;
11174 static bfd_vma op_address[MAX_OPERANDS];
11175 static bfd_vma op_riprel[MAX_OPERANDS];
11176 static bfd_vma start_pc;
11177
11178 /*
11179  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11180  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11181  *   section of the "Virtual 8086 Mode" chapter.)
11182  * 'pc' should be the address of this instruction, it will
11183  *   be used to print the target address if this is a relative jump or call
11184  * The function returns the length of this instruction in bytes.
11185  */
11186
11187 static char intel_syntax;
11188 static char intel_mnemonic = !SYSV386_COMPAT;
11189 static char open_char;
11190 static char close_char;
11191 static char separator_char;
11192 static char scale_char;
11193
11194 enum x86_64_isa
11195 {
11196   amd64 = 1,
11197   intel64
11198 };
11199
11200 static enum x86_64_isa isa64;
11201
11202 /* Here for backwards compatibility.  When gdb stops using
11203    print_insn_i386_att and print_insn_i386_intel these functions can
11204    disappear, and print_insn_i386 be merged into print_insn.  */
11205 int
11206 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11207 {
11208   intel_syntax = 0;
11209
11210   return print_insn (pc, info);
11211 }
11212
11213 int
11214 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11215 {
11216   intel_syntax = 1;
11217
11218   return print_insn (pc, info);
11219 }
11220
11221 int
11222 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11223 {
11224   intel_syntax = -1;
11225
11226   return print_insn (pc, info);
11227 }
11228
11229 void
11230 print_i386_disassembler_options (FILE *stream)
11231 {
11232   fprintf (stream, _("\n\
11233 The following i386/x86-64 specific disassembler options are supported for use\n\
11234 with the -M switch (multiple options should be separated by commas):\n"));
11235
11236   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11237   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11238   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11239   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11240   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11241   fprintf (stream, _("  att-mnemonic\n"
11242                      "              Display instruction in AT&T mnemonic\n"));
11243   fprintf (stream, _("  intel-mnemonic\n"
11244                      "              Display instruction in Intel mnemonic\n"));
11245   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11246   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11247   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11248   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11249   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11250   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11251   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11252   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11253 }
11254
11255 /* Bad opcode.  */
11256 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11257
11258 /* Get a pointer to struct dis386 with a valid name.  */
11259
11260 static const struct dis386 *
11261 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11262 {
11263   int vindex, vex_table_index;
11264
11265   if (dp->name != NULL)
11266     return dp;
11267
11268   switch (dp->op[0].bytemode)
11269     {
11270     case USE_REG_TABLE:
11271       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11272       break;
11273
11274     case USE_MOD_TABLE:
11275       vindex = modrm.mod == 0x3 ? 1 : 0;
11276       dp = &mod_table[dp->op[1].bytemode][vindex];
11277       break;
11278
11279     case USE_RM_TABLE:
11280       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11281       break;
11282
11283     case USE_PREFIX_TABLE:
11284       if (need_vex)
11285         {
11286           /* The prefix in VEX is implicit.  */
11287           switch (vex.prefix)
11288             {
11289             case 0:
11290               vindex = 0;
11291               break;
11292             case REPE_PREFIX_OPCODE:
11293               vindex = 1;
11294               break;
11295             case DATA_PREFIX_OPCODE:
11296               vindex = 2;
11297               break;
11298             case REPNE_PREFIX_OPCODE:
11299               vindex = 3;
11300               break;
11301             default:
11302               abort ();
11303               break;
11304             }
11305         }
11306       else
11307         {
11308           int last_prefix = -1;
11309           int prefix = 0;
11310           vindex = 0;
11311           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11312              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11313              last one wins.  */
11314           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11315             {
11316               if (last_repz_prefix > last_repnz_prefix)
11317                 {
11318                   vindex = 1;
11319                   prefix = PREFIX_REPZ;
11320                   last_prefix = last_repz_prefix;
11321                 }
11322               else
11323                 {
11324                   vindex = 3;
11325                   prefix = PREFIX_REPNZ;
11326                   last_prefix = last_repnz_prefix;
11327                 }
11328
11329               /* Check if prefix should be ignored.  */
11330               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11331                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11332                    & prefix) != 0)
11333                 vindex = 0;
11334             }
11335
11336           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11337             {
11338               vindex = 2;
11339               prefix = PREFIX_DATA;
11340               last_prefix = last_data_prefix;
11341             }
11342
11343           if (vindex != 0)
11344             {
11345               used_prefixes |= prefix;
11346               all_prefixes[last_prefix] = 0;
11347             }
11348         }
11349       dp = &prefix_table[dp->op[1].bytemode][vindex];
11350       break;
11351
11352     case USE_X86_64_TABLE:
11353       vindex = address_mode == mode_64bit ? 1 : 0;
11354       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11355       break;
11356
11357     case USE_3BYTE_TABLE:
11358       FETCH_DATA (info, codep + 2);
11359       vindex = *codep++;
11360       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11361       end_codep = codep;
11362       modrm.mod = (*codep >> 6) & 3;
11363       modrm.reg = (*codep >> 3) & 7;
11364       modrm.rm = *codep & 7;
11365       break;
11366
11367     case USE_VEX_LEN_TABLE:
11368       if (!need_vex)
11369         abort ();
11370
11371       switch (vex.length)
11372         {
11373         case 128:
11374           vindex = 0;
11375           break;
11376         case 256:
11377           vindex = 1;
11378           break;
11379         default:
11380           abort ();
11381           break;
11382         }
11383
11384       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11385       break;
11386
11387     case USE_EVEX_LEN_TABLE:
11388       if (!vex.evex)
11389         abort ();
11390
11391       switch (vex.length)
11392         {
11393         case 128:
11394           vindex = 0;
11395           break;
11396         case 256:
11397           vindex = 1;
11398           break;
11399         case 512:
11400           vindex = 2;
11401           break;
11402         default:
11403           abort ();
11404           break;
11405         }
11406
11407       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11408       break;
11409
11410     case USE_XOP_8F_TABLE:
11411       FETCH_DATA (info, codep + 3);
11412       rex = ~(*codep >> 5) & 0x7;
11413
11414       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11415       switch ((*codep & 0x1f))
11416         {
11417         default:
11418           dp = &bad_opcode;
11419           return dp;
11420         case 0x8:
11421           vex_table_index = XOP_08;
11422           break;
11423         case 0x9:
11424           vex_table_index = XOP_09;
11425           break;
11426         case 0xa:
11427           vex_table_index = XOP_0A;
11428           break;
11429         }
11430       codep++;
11431       vex.w = *codep & 0x80;
11432       if (vex.w && address_mode == mode_64bit)
11433         rex |= REX_W;
11434
11435       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11436       if (address_mode != mode_64bit)
11437         {
11438           /* In 16/32-bit mode REX_B is silently ignored.  */
11439           rex &= ~REX_B;
11440         }
11441
11442       vex.length = (*codep & 0x4) ? 256 : 128;
11443       switch ((*codep & 0x3))
11444         {
11445         case 0:
11446           break;
11447         case 1:
11448           vex.prefix = DATA_PREFIX_OPCODE;
11449           break;
11450         case 2:
11451           vex.prefix = REPE_PREFIX_OPCODE;
11452           break;
11453         case 3:
11454           vex.prefix = REPNE_PREFIX_OPCODE;
11455           break;
11456         }
11457       need_vex = 1;
11458       need_vex_reg = 1;
11459       codep++;
11460       vindex = *codep++;
11461       dp = &xop_table[vex_table_index][vindex];
11462
11463       end_codep = codep;
11464       FETCH_DATA (info, codep + 1);
11465       modrm.mod = (*codep >> 6) & 3;
11466       modrm.reg = (*codep >> 3) & 7;
11467       modrm.rm = *codep & 7;
11468
11469       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11470          having to decode the bits for every otherwise valid encoding.  */
11471       if (vex.prefix)
11472         return &bad_opcode;
11473       break;
11474
11475     case USE_VEX_C4_TABLE:
11476       /* VEX prefix.  */
11477       FETCH_DATA (info, codep + 3);
11478       rex = ~(*codep >> 5) & 0x7;
11479       switch ((*codep & 0x1f))
11480         {
11481         default:
11482           dp = &bad_opcode;
11483           return dp;
11484         case 0x1:
11485           vex_table_index = VEX_0F;
11486           break;
11487         case 0x2:
11488           vex_table_index = VEX_0F38;
11489           break;
11490         case 0x3:
11491           vex_table_index = VEX_0F3A;
11492           break;
11493         }
11494       codep++;
11495       vex.w = *codep & 0x80;
11496       if (address_mode == mode_64bit)
11497         {
11498           if (vex.w)
11499             rex |= REX_W;
11500         }
11501       else
11502         {
11503           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11504              is ignored, other REX bits are 0 and the highest bit in
11505              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11506           rex = 0;
11507         }
11508       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11509       vex.length = (*codep & 0x4) ? 256 : 128;
11510       switch ((*codep & 0x3))
11511         {
11512         case 0:
11513           break;
11514         case 1:
11515           vex.prefix = DATA_PREFIX_OPCODE;
11516           break;
11517         case 2:
11518           vex.prefix = REPE_PREFIX_OPCODE;
11519           break;
11520         case 3:
11521           vex.prefix = REPNE_PREFIX_OPCODE;
11522           break;
11523         }
11524       need_vex = 1;
11525       need_vex_reg = 1;
11526       codep++;
11527       vindex = *codep++;
11528       dp = &vex_table[vex_table_index][vindex];
11529       end_codep = codep;
11530       /* There is no MODRM byte for VEX0F 77.  */
11531       if (vex_table_index != VEX_0F || vindex != 0x77)
11532         {
11533           FETCH_DATA (info, codep + 1);
11534           modrm.mod = (*codep >> 6) & 3;
11535           modrm.reg = (*codep >> 3) & 7;
11536           modrm.rm = *codep & 7;
11537         }
11538       break;
11539
11540     case USE_VEX_C5_TABLE:
11541       /* VEX prefix.  */
11542       FETCH_DATA (info, codep + 2);
11543       rex = (*codep & 0x80) ? 0 : REX_R;
11544
11545       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11546          VEX.vvvv is 1.  */
11547       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11548       vex.length = (*codep & 0x4) ? 256 : 128;
11549       switch ((*codep & 0x3))
11550         {
11551         case 0:
11552           break;
11553         case 1:
11554           vex.prefix = DATA_PREFIX_OPCODE;
11555           break;
11556         case 2:
11557           vex.prefix = REPE_PREFIX_OPCODE;
11558           break;
11559         case 3:
11560           vex.prefix = REPNE_PREFIX_OPCODE;
11561           break;
11562         }
11563       need_vex = 1;
11564       need_vex_reg = 1;
11565       codep++;
11566       vindex = *codep++;
11567       dp = &vex_table[dp->op[1].bytemode][vindex];
11568       end_codep = codep;
11569       /* There is no MODRM byte for VEX 77.  */
11570       if (vindex != 0x77)
11571         {
11572           FETCH_DATA (info, codep + 1);
11573           modrm.mod = (*codep >> 6) & 3;
11574           modrm.reg = (*codep >> 3) & 7;
11575           modrm.rm = *codep & 7;
11576         }
11577       break;
11578
11579     case USE_VEX_W_TABLE:
11580       if (!need_vex)
11581         abort ();
11582
11583       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11584       break;
11585
11586     case USE_EVEX_TABLE:
11587       two_source_ops = 0;
11588       /* EVEX prefix.  */
11589       vex.evex = 1;
11590       FETCH_DATA (info, codep + 4);
11591       /* The first byte after 0x62.  */
11592       rex = ~(*codep >> 5) & 0x7;
11593       vex.r = *codep & 0x10;
11594       switch ((*codep & 0xf))
11595         {
11596         default:
11597           return &bad_opcode;
11598         case 0x1:
11599           vex_table_index = EVEX_0F;
11600           break;
11601         case 0x2:
11602           vex_table_index = EVEX_0F38;
11603           break;
11604         case 0x3:
11605           vex_table_index = EVEX_0F3A;
11606           break;
11607         }
11608
11609       /* The second byte after 0x62.  */
11610       codep++;
11611       vex.w = *codep & 0x80;
11612       if (vex.w && address_mode == mode_64bit)
11613         rex |= REX_W;
11614
11615       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11616
11617       /* The U bit.  */
11618       if (!(*codep & 0x4))
11619         return &bad_opcode;
11620
11621       switch ((*codep & 0x3))
11622         {
11623         case 0:
11624           break;
11625         case 1:
11626           vex.prefix = DATA_PREFIX_OPCODE;
11627           break;
11628         case 2:
11629           vex.prefix = REPE_PREFIX_OPCODE;
11630           break;
11631         case 3:
11632           vex.prefix = REPNE_PREFIX_OPCODE;
11633           break;
11634         }
11635
11636       /* The third byte after 0x62.  */
11637       codep++;
11638
11639       /* Remember the static rounding bits.  */
11640       vex.ll = (*codep >> 5) & 3;
11641       vex.b = (*codep & 0x10) != 0;
11642
11643       vex.v = *codep & 0x8;
11644       vex.mask_register_specifier = *codep & 0x7;
11645       vex.zeroing = *codep & 0x80;
11646
11647       if (address_mode != mode_64bit)
11648         {
11649           /* In 16/32-bit mode silently ignore following bits.  */
11650           rex &= ~REX_B;
11651           vex.r = 1;
11652           vex.v = 1;
11653         }
11654
11655       need_vex = 1;
11656       need_vex_reg = 1;
11657       codep++;
11658       vindex = *codep++;
11659       dp = &evex_table[vex_table_index][vindex];
11660       end_codep = codep;
11661       FETCH_DATA (info, codep + 1);
11662       modrm.mod = (*codep >> 6) & 3;
11663       modrm.reg = (*codep >> 3) & 7;
11664       modrm.rm = *codep & 7;
11665
11666       /* Set vector length.  */
11667       if (modrm.mod == 3 && vex.b)
11668         vex.length = 512;
11669       else
11670         {
11671           switch (vex.ll)
11672             {
11673             case 0x0:
11674               vex.length = 128;
11675               break;
11676             case 0x1:
11677               vex.length = 256;
11678               break;
11679             case 0x2:
11680               vex.length = 512;
11681               break;
11682             default:
11683               return &bad_opcode;
11684             }
11685         }
11686       break;
11687
11688     case 0:
11689       dp = &bad_opcode;
11690       break;
11691
11692     default:
11693       abort ();
11694     }
11695
11696   if (dp->name != NULL)
11697     return dp;
11698   else
11699     return get_valid_dis386 (dp, info);
11700 }
11701
11702 static void
11703 get_sib (disassemble_info *info, int sizeflag)
11704 {
11705   /* If modrm.mod == 3, operand must be register.  */
11706   if (need_modrm
11707       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11708       && modrm.mod != 3
11709       && modrm.rm == 4)
11710     {
11711       FETCH_DATA (info, codep + 2);
11712       sib.index = (codep [1] >> 3) & 7;
11713       sib.scale = (codep [1] >> 6) & 3;
11714       sib.base = codep [1] & 7;
11715     }
11716 }
11717
11718 static int
11719 print_insn (bfd_vma pc, disassemble_info *info)
11720 {
11721   const struct dis386 *dp;
11722   int i;
11723   char *op_txt[MAX_OPERANDS];
11724   int needcomma;
11725   int sizeflag, orig_sizeflag;
11726   const char *p;
11727   struct dis_private priv;
11728   int prefix_length;
11729
11730   priv.orig_sizeflag = AFLAG | DFLAG;
11731   if ((info->mach & bfd_mach_i386_i386) != 0)
11732     address_mode = mode_32bit;
11733   else if (info->mach == bfd_mach_i386_i8086)
11734     {
11735       address_mode = mode_16bit;
11736       priv.orig_sizeflag = 0;
11737     }
11738   else
11739     address_mode = mode_64bit;
11740
11741   if (intel_syntax == (char) -1)
11742     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11743
11744   for (p = info->disassembler_options; p != NULL; )
11745     {
11746       if (CONST_STRNEQ (p, "amd64"))
11747         isa64 = amd64;
11748       else if (CONST_STRNEQ (p, "intel64"))
11749         isa64 = intel64;
11750       else if (CONST_STRNEQ (p, "x86-64"))
11751         {
11752           address_mode = mode_64bit;
11753           priv.orig_sizeflag |= AFLAG | DFLAG;
11754         }
11755       else if (CONST_STRNEQ (p, "i386"))
11756         {
11757           address_mode = mode_32bit;
11758           priv.orig_sizeflag |= AFLAG | DFLAG;
11759         }
11760       else if (CONST_STRNEQ (p, "i8086"))
11761         {
11762           address_mode = mode_16bit;
11763           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11764         }
11765       else if (CONST_STRNEQ (p, "intel"))
11766         {
11767           intel_syntax = 1;
11768           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11769             intel_mnemonic = 1;
11770         }
11771       else if (CONST_STRNEQ (p, "att"))
11772         {
11773           intel_syntax = 0;
11774           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11775             intel_mnemonic = 0;
11776         }
11777       else if (CONST_STRNEQ (p, "addr"))
11778         {
11779           if (address_mode == mode_64bit)
11780             {
11781               if (p[4] == '3' && p[5] == '2')
11782                 priv.orig_sizeflag &= ~AFLAG;
11783               else if (p[4] == '6' && p[5] == '4')
11784                 priv.orig_sizeflag |= AFLAG;
11785             }
11786           else
11787             {
11788               if (p[4] == '1' && p[5] == '6')
11789                 priv.orig_sizeflag &= ~AFLAG;
11790               else if (p[4] == '3' && p[5] == '2')
11791                 priv.orig_sizeflag |= AFLAG;
11792             }
11793         }
11794       else if (CONST_STRNEQ (p, "data"))
11795         {
11796           if (p[4] == '1' && p[5] == '6')
11797             priv.orig_sizeflag &= ~DFLAG;
11798           else if (p[4] == '3' && p[5] == '2')
11799             priv.orig_sizeflag |= DFLAG;
11800         }
11801       else if (CONST_STRNEQ (p, "suffix"))
11802         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11803
11804       p = strchr (p, ',');
11805       if (p != NULL)
11806         p++;
11807     }
11808
11809   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11810     {
11811       (*info->fprintf_func) (info->stream,
11812                              _("64-bit address is disabled"));
11813       return -1;
11814     }
11815
11816   if (intel_syntax)
11817     {
11818       names64 = intel_names64;
11819       names32 = intel_names32;
11820       names16 = intel_names16;
11821       names8 = intel_names8;
11822       names8rex = intel_names8rex;
11823       names_seg = intel_names_seg;
11824       names_mm = intel_names_mm;
11825       names_bnd = intel_names_bnd;
11826       names_xmm = intel_names_xmm;
11827       names_ymm = intel_names_ymm;
11828       names_zmm = intel_names_zmm;
11829       index64 = intel_index64;
11830       index32 = intel_index32;
11831       names_mask = intel_names_mask;
11832       index16 = intel_index16;
11833       open_char = '[';
11834       close_char = ']';
11835       separator_char = '+';
11836       scale_char = '*';
11837     }
11838   else
11839     {
11840       names64 = att_names64;
11841       names32 = att_names32;
11842       names16 = att_names16;
11843       names8 = att_names8;
11844       names8rex = att_names8rex;
11845       names_seg = att_names_seg;
11846       names_mm = att_names_mm;
11847       names_bnd = att_names_bnd;
11848       names_xmm = att_names_xmm;
11849       names_ymm = att_names_ymm;
11850       names_zmm = att_names_zmm;
11851       index64 = att_index64;
11852       index32 = att_index32;
11853       names_mask = att_names_mask;
11854       index16 = att_index16;
11855       open_char = '(';
11856       close_char =  ')';
11857       separator_char = ',';
11858       scale_char = ',';
11859     }
11860
11861   /* The output looks better if we put 7 bytes on a line, since that
11862      puts most long word instructions on a single line.  Use 8 bytes
11863      for Intel L1OM.  */
11864   if ((info->mach & bfd_mach_l1om) != 0)
11865     info->bytes_per_line = 8;
11866   else
11867     info->bytes_per_line = 7;
11868
11869   info->private_data = &priv;
11870   priv.max_fetched = priv.the_buffer;
11871   priv.insn_start = pc;
11872
11873   obuf[0] = 0;
11874   for (i = 0; i < MAX_OPERANDS; ++i)
11875     {
11876       op_out[i][0] = 0;
11877       op_index[i] = -1;
11878     }
11879
11880   the_info = info;
11881   start_pc = pc;
11882   start_codep = priv.the_buffer;
11883   codep = priv.the_buffer;
11884
11885   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11886     {
11887       const char *name;
11888
11889       /* Getting here means we tried for data but didn't get it.  That
11890          means we have an incomplete instruction of some sort.  Just
11891          print the first byte as a prefix or a .byte pseudo-op.  */
11892       if (codep > priv.the_buffer)
11893         {
11894           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11895           if (name != NULL)
11896             (*info->fprintf_func) (info->stream, "%s", name);
11897           else
11898             {
11899               /* Just print the first byte as a .byte instruction.  */
11900               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11901                                      (unsigned int) priv.the_buffer[0]);
11902             }
11903
11904           return 1;
11905         }
11906
11907       return -1;
11908     }
11909
11910   obufp = obuf;
11911   sizeflag = priv.orig_sizeflag;
11912
11913   if (!ckprefix () || rex_used)
11914     {
11915       /* Too many prefixes or unused REX prefixes.  */
11916       for (i = 0;
11917            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11918            i++)
11919         (*info->fprintf_func) (info->stream, "%s%s",
11920                                i == 0 ? "" : " ",
11921                                prefix_name (all_prefixes[i], sizeflag));
11922       return i;
11923     }
11924
11925   insn_codep = codep;
11926
11927   FETCH_DATA (info, codep + 1);
11928   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11929
11930   if (((prefixes & PREFIX_FWAIT)
11931        && ((*codep < 0xd8) || (*codep > 0xdf))))
11932     {
11933       /* Handle prefixes before fwait.  */
11934       for (i = 0; i < fwait_prefix && all_prefixes[i];
11935            i++)
11936         (*info->fprintf_func) (info->stream, "%s ",
11937                                prefix_name (all_prefixes[i], sizeflag));
11938       (*info->fprintf_func) (info->stream, "fwait");
11939       return i + 1;
11940     }
11941
11942   if (*codep == 0x0f)
11943     {
11944       unsigned char threebyte;
11945
11946       codep++;
11947       FETCH_DATA (info, codep + 1);
11948       threebyte = *codep;
11949       dp = &dis386_twobyte[threebyte];
11950       need_modrm = twobyte_has_modrm[*codep];
11951       codep++;
11952     }
11953   else
11954     {
11955       dp = &dis386[*codep];
11956       need_modrm = onebyte_has_modrm[*codep];
11957       codep++;
11958     }
11959
11960   /* Save sizeflag for printing the extra prefixes later before updating
11961      it for mnemonic and operand processing.  The prefix names depend
11962      only on the address mode.  */
11963   orig_sizeflag = sizeflag;
11964   if (prefixes & PREFIX_ADDR)
11965     sizeflag ^= AFLAG;
11966   if ((prefixes & PREFIX_DATA))
11967     sizeflag ^= DFLAG;
11968
11969   end_codep = codep;
11970   if (need_modrm)
11971     {
11972       FETCH_DATA (info, codep + 1);
11973       modrm.mod = (*codep >> 6) & 3;
11974       modrm.reg = (*codep >> 3) & 7;
11975       modrm.rm = *codep & 7;
11976     }
11977
11978   need_vex = 0;
11979   need_vex_reg = 0;
11980   memset (&vex, 0, sizeof (vex));
11981
11982   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11983     {
11984       get_sib (info, sizeflag);
11985       dofloat (sizeflag);
11986     }
11987   else
11988     {
11989       dp = get_valid_dis386 (dp, info);
11990       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11991         {
11992           get_sib (info, sizeflag);
11993           for (i = 0; i < MAX_OPERANDS; ++i)
11994             {
11995               obufp = op_out[i];
11996               op_ad = MAX_OPERANDS - 1 - i;
11997               if (dp->op[i].rtn)
11998                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11999               /* For EVEX instruction after the last operand masking
12000                  should be printed.  */
12001               if (i == 0 && vex.evex)
12002                 {
12003                   /* Don't print {%k0}.  */
12004                   if (vex.mask_register_specifier)
12005                     {
12006                       oappend ("{");
12007                       oappend (names_mask[vex.mask_register_specifier]);
12008                       oappend ("}");
12009                     }
12010                   if (vex.zeroing)
12011                     oappend ("{z}");
12012                 }
12013             }
12014         }
12015     }
12016
12017   /* Clear instruction information.  */
12018   if (the_info)
12019     {
12020       the_info->insn_info_valid = 0;
12021       the_info->branch_delay_insns = 0;
12022       the_info->data_size = 0;
12023       the_info->insn_type = dis_noninsn;
12024       the_info->target = 0;
12025       the_info->target2 = 0;
12026     }
12027
12028   /* Reset jump operation indicator.  */
12029   op_is_jump = FALSE;
12030
12031   {
12032     int jump_detection = 0;
12033
12034     /* Extract flags.  */
12035     for (i = 0; i < MAX_OPERANDS; ++i)
12036       {
12037         if ((dp->op[i].rtn == OP_J)
12038             || (dp->op[i].rtn == OP_indirE))
12039           jump_detection |= 1;
12040         else if ((dp->op[i].rtn == BND_Fixup)
12041                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12042           jump_detection |= 2;
12043         else if ((dp->op[i].bytemode == cond_jump_mode)
12044                  || (dp->op[i].bytemode == loop_jcxz_mode))
12045           jump_detection |= 4;
12046       }
12047
12048     /* Determine if this is a jump or branch.  */
12049     if ((jump_detection & 0x3) == 0x3)
12050       {
12051         op_is_jump = TRUE;
12052         if (jump_detection & 0x4)
12053           the_info->insn_type = dis_condbranch;
12054         else
12055           the_info->insn_type =
12056             (dp->name && !strncmp(dp->name, "call", 4))
12057             ? dis_jsr : dis_branch;
12058       }
12059   }
12060
12061   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12062      are all 0s in inverted form.  */
12063   if (need_vex && vex.register_specifier != 0)
12064     {
12065       (*info->fprintf_func) (info->stream, "(bad)");
12066       return end_codep - priv.the_buffer;
12067     }
12068
12069   /* Check if the REX prefix is used.  */
12070   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12071     all_prefixes[last_rex_prefix] = 0;
12072
12073   /* Check if the SEG prefix is used.  */
12074   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12075                    | PREFIX_FS | PREFIX_GS)) != 0
12076       && (used_prefixes & active_seg_prefix) != 0)
12077     all_prefixes[last_seg_prefix] = 0;
12078
12079   /* Check if the ADDR prefix is used.  */
12080   if ((prefixes & PREFIX_ADDR) != 0
12081       && (used_prefixes & PREFIX_ADDR) != 0)
12082     all_prefixes[last_addr_prefix] = 0;
12083
12084   /* Check if the DATA prefix is used.  */
12085   if ((prefixes & PREFIX_DATA) != 0
12086       && (used_prefixes & PREFIX_DATA) != 0
12087       && !need_vex)
12088     all_prefixes[last_data_prefix] = 0;
12089
12090   /* Print the extra prefixes.  */
12091   prefix_length = 0;
12092   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12093     if (all_prefixes[i])
12094       {
12095         const char *name;
12096         name = prefix_name (all_prefixes[i], orig_sizeflag);
12097         if (name == NULL)
12098           abort ();
12099         prefix_length += strlen (name) + 1;
12100         (*info->fprintf_func) (info->stream, "%s ", name);
12101       }
12102
12103   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12104      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12105      used by putop and MMX/SSE operand and may be overriden by the
12106      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12107      separately.  */
12108   if (dp->prefix_requirement == PREFIX_OPCODE
12109       && (((need_vex
12110             ? vex.prefix == REPE_PREFIX_OPCODE
12111               || vex.prefix == REPNE_PREFIX_OPCODE
12112             : (prefixes
12113                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12114            && (used_prefixes
12115                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12116           || (((need_vex
12117                 ? vex.prefix == DATA_PREFIX_OPCODE
12118                 : ((prefixes
12119                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12120                    == PREFIX_DATA))
12121                && (used_prefixes & PREFIX_DATA) == 0))
12122           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12123     {
12124       (*info->fprintf_func) (info->stream, "(bad)");
12125       return end_codep - priv.the_buffer;
12126     }
12127
12128   /* Check maximum code length.  */
12129   if ((codep - start_codep) > MAX_CODE_LENGTH)
12130     {
12131       (*info->fprintf_func) (info->stream, "(bad)");
12132       return MAX_CODE_LENGTH;
12133     }
12134
12135   obufp = mnemonicendp;
12136   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12137     oappend (" ");
12138   oappend (" ");
12139   (*info->fprintf_func) (info->stream, "%s", obuf);
12140
12141   /* The enter and bound instructions are printed with operands in the same
12142      order as the intel book; everything else is printed in reverse order.  */
12143   if (intel_syntax || two_source_ops)
12144     {
12145       bfd_vma riprel;
12146
12147       for (i = 0; i < MAX_OPERANDS; ++i)
12148         op_txt[i] = op_out[i];
12149
12150       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12151           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12152         {
12153           op_txt[2] = op_out[3];
12154           op_txt[3] = op_out[2];
12155         }
12156
12157       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12158         {
12159           op_ad = op_index[i];
12160           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12161           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12162           riprel = op_riprel[i];
12163           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12164           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12165         }
12166     }
12167   else
12168     {
12169       for (i = 0; i < MAX_OPERANDS; ++i)
12170         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12171     }
12172
12173   needcomma = 0;
12174   for (i = 0; i < MAX_OPERANDS; ++i)
12175     if (*op_txt[i])
12176       {
12177         if (needcomma)
12178           (*info->fprintf_func) (info->stream, ",");
12179         if (op_index[i] != -1 && !op_riprel[i])
12180           {
12181             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12182
12183             if (the_info && op_is_jump)
12184               {
12185                 the_info->insn_info_valid = 1;
12186                 the_info->branch_delay_insns = 0;
12187                 the_info->data_size = 0;
12188                 the_info->target = target;
12189                 the_info->target2 = 0;
12190               }
12191             (*info->print_address_func) (target, info);
12192           }
12193         else
12194           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12195         needcomma = 1;
12196       }
12197
12198   for (i = 0; i < MAX_OPERANDS; i++)
12199     if (op_index[i] != -1 && op_riprel[i])
12200       {
12201         (*info->fprintf_func) (info->stream, "        # ");
12202         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12203                                                 + op_address[op_index[i]]), info);
12204         break;
12205       }
12206   return codep - priv.the_buffer;
12207 }
12208
12209 static const char *float_mem[] = {
12210   /* d8 */
12211   "fadd{s|}",
12212   "fmul{s|}",
12213   "fcom{s|}",
12214   "fcomp{s|}",
12215   "fsub{s|}",
12216   "fsubr{s|}",
12217   "fdiv{s|}",
12218   "fdivr{s|}",
12219   /* d9 */
12220   "fld{s|}",
12221   "(bad)",
12222   "fst{s|}",
12223   "fstp{s|}",
12224   "fldenv{C|C}",
12225   "fldcw",
12226   "fNstenv{C|C}",
12227   "fNstcw",
12228   /* da */
12229   "fiadd{l|}",
12230   "fimul{l|}",
12231   "ficom{l|}",
12232   "ficomp{l|}",
12233   "fisub{l|}",
12234   "fisubr{l|}",
12235   "fidiv{l|}",
12236   "fidivr{l|}",
12237   /* db */
12238   "fild{l|}",
12239   "fisttp{l|}",
12240   "fist{l|}",
12241   "fistp{l|}",
12242   "(bad)",
12243   "fld{t|}",
12244   "(bad)",
12245   "fstp{t|}",
12246   /* dc */
12247   "fadd{l|}",
12248   "fmul{l|}",
12249   "fcom{l|}",
12250   "fcomp{l|}",
12251   "fsub{l|}",
12252   "fsubr{l|}",
12253   "fdiv{l|}",
12254   "fdivr{l|}",
12255   /* dd */
12256   "fld{l|}",
12257   "fisttp{ll|}",
12258   "fst{l||}",
12259   "fstp{l|}",
12260   "frstor{C|C}",
12261   "(bad)",
12262   "fNsave{C|C}",
12263   "fNstsw",
12264   /* de */
12265   "fiadd{s|}",
12266   "fimul{s|}",
12267   "ficom{s|}",
12268   "ficomp{s|}",
12269   "fisub{s|}",
12270   "fisubr{s|}",
12271   "fidiv{s|}",
12272   "fidivr{s|}",
12273   /* df */
12274   "fild{s|}",
12275   "fisttp{s|}",
12276   "fist{s|}",
12277   "fistp{s|}",
12278   "fbld",
12279   "fild{ll|}",
12280   "fbstp",
12281   "fistp{ll|}",
12282 };
12283
12284 static const unsigned char float_mem_mode[] = {
12285   /* d8 */
12286   d_mode,
12287   d_mode,
12288   d_mode,
12289   d_mode,
12290   d_mode,
12291   d_mode,
12292   d_mode,
12293   d_mode,
12294   /* d9 */
12295   d_mode,
12296   0,
12297   d_mode,
12298   d_mode,
12299   0,
12300   w_mode,
12301   0,
12302   w_mode,
12303   /* da */
12304   d_mode,
12305   d_mode,
12306   d_mode,
12307   d_mode,
12308   d_mode,
12309   d_mode,
12310   d_mode,
12311   d_mode,
12312   /* db */
12313   d_mode,
12314   d_mode,
12315   d_mode,
12316   d_mode,
12317   0,
12318   t_mode,
12319   0,
12320   t_mode,
12321   /* dc */
12322   q_mode,
12323   q_mode,
12324   q_mode,
12325   q_mode,
12326   q_mode,
12327   q_mode,
12328   q_mode,
12329   q_mode,
12330   /* dd */
12331   q_mode,
12332   q_mode,
12333   q_mode,
12334   q_mode,
12335   0,
12336   0,
12337   0,
12338   w_mode,
12339   /* de */
12340   w_mode,
12341   w_mode,
12342   w_mode,
12343   w_mode,
12344   w_mode,
12345   w_mode,
12346   w_mode,
12347   w_mode,
12348   /* df */
12349   w_mode,
12350   w_mode,
12351   w_mode,
12352   w_mode,
12353   t_mode,
12354   q_mode,
12355   t_mode,
12356   q_mode
12357 };
12358
12359 #define ST { OP_ST, 0 }
12360 #define STi { OP_STi, 0 }
12361
12362 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12363 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12364 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12365 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12366 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12367 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12368 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12369 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12370 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12371
12372 static const struct dis386 float_reg[][8] = {
12373   /* d8 */
12374   {
12375     { "fadd",   { ST, STi }, 0 },
12376     { "fmul",   { ST, STi }, 0 },
12377     { "fcom",   { STi }, 0 },
12378     { "fcomp",  { STi }, 0 },
12379     { "fsub",   { ST, STi }, 0 },
12380     { "fsubr",  { ST, STi }, 0 },
12381     { "fdiv",   { ST, STi }, 0 },
12382     { "fdivr",  { ST, STi }, 0 },
12383   },
12384   /* d9 */
12385   {
12386     { "fld",    { STi }, 0 },
12387     { "fxch",   { STi }, 0 },
12388     { FGRPd9_2 },
12389     { Bad_Opcode },
12390     { FGRPd9_4 },
12391     { FGRPd9_5 },
12392     { FGRPd9_6 },
12393     { FGRPd9_7 },
12394   },
12395   /* da */
12396   {
12397     { "fcmovb", { ST, STi }, 0 },
12398     { "fcmove", { ST, STi }, 0 },
12399     { "fcmovbe",{ ST, STi }, 0 },
12400     { "fcmovu", { ST, STi }, 0 },
12401     { Bad_Opcode },
12402     { FGRPda_5 },
12403     { Bad_Opcode },
12404     { Bad_Opcode },
12405   },
12406   /* db */
12407   {
12408     { "fcmovnb",{ ST, STi }, 0 },
12409     { "fcmovne",{ ST, STi }, 0 },
12410     { "fcmovnbe",{ ST, STi }, 0 },
12411     { "fcmovnu",{ ST, STi }, 0 },
12412     { FGRPdb_4 },
12413     { "fucomi", { ST, STi }, 0 },
12414     { "fcomi",  { ST, STi }, 0 },
12415     { Bad_Opcode },
12416   },
12417   /* dc */
12418   {
12419     { "fadd",   { STi, ST }, 0 },
12420     { "fmul",   { STi, ST }, 0 },
12421     { Bad_Opcode },
12422     { Bad_Opcode },
12423     { "fsub{!M|r}",     { STi, ST }, 0 },
12424     { "fsub{M|}",       { STi, ST }, 0 },
12425     { "fdiv{!M|r}",     { STi, ST }, 0 },
12426     { "fdiv{M|}",       { STi, ST }, 0 },
12427   },
12428   /* dd */
12429   {
12430     { "ffree",  { STi }, 0 },
12431     { Bad_Opcode },
12432     { "fst",    { STi }, 0 },
12433     { "fstp",   { STi }, 0 },
12434     { "fucom",  { STi }, 0 },
12435     { "fucomp", { STi }, 0 },
12436     { Bad_Opcode },
12437     { Bad_Opcode },
12438   },
12439   /* de */
12440   {
12441     { "faddp",  { STi, ST }, 0 },
12442     { "fmulp",  { STi, ST }, 0 },
12443     { Bad_Opcode },
12444     { FGRPde_3 },
12445     { "fsub{!M|r}p",    { STi, ST }, 0 },
12446     { "fsub{M|}p",      { STi, ST }, 0 },
12447     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12448     { "fdiv{M|}p",      { STi, ST }, 0 },
12449   },
12450   /* df */
12451   {
12452     { "ffreep", { STi }, 0 },
12453     { Bad_Opcode },
12454     { Bad_Opcode },
12455     { Bad_Opcode },
12456     { FGRPdf_4 },
12457     { "fucomip", { ST, STi }, 0 },
12458     { "fcomip", { ST, STi }, 0 },
12459     { Bad_Opcode },
12460   },
12461 };
12462
12463 static char *fgrps[][8] = {
12464   /* Bad opcode 0 */
12465   {
12466     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12467   },
12468
12469   /* d9_2  1 */
12470   {
12471     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12472   },
12473
12474   /* d9_4  2 */
12475   {
12476     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12477   },
12478
12479   /* d9_5  3 */
12480   {
12481     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12482   },
12483
12484   /* d9_6  4 */
12485   {
12486     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12487   },
12488
12489   /* d9_7  5 */
12490   {
12491     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12492   },
12493
12494   /* da_5  6 */
12495   {
12496     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12497   },
12498
12499   /* db_4  7 */
12500   {
12501     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12502     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12503   },
12504
12505   /* de_3  8 */
12506   {
12507     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12508   },
12509
12510   /* df_4  9 */
12511   {
12512     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12513   },
12514 };
12515
12516 static void
12517 swap_operand (void)
12518 {
12519   mnemonicendp[0] = '.';
12520   mnemonicendp[1] = 's';
12521   mnemonicendp += 2;
12522 }
12523
12524 static void
12525 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12526                int sizeflag ATTRIBUTE_UNUSED)
12527 {
12528   /* Skip mod/rm byte.  */
12529   MODRM_CHECK;
12530   codep++;
12531 }
12532
12533 static void
12534 dofloat (int sizeflag)
12535 {
12536   const struct dis386 *dp;
12537   unsigned char floatop;
12538
12539   floatop = codep[-1];
12540
12541   if (modrm.mod != 3)
12542     {
12543       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12544
12545       putop (float_mem[fp_indx], sizeflag);
12546       obufp = op_out[0];
12547       op_ad = 2;
12548       OP_E (float_mem_mode[fp_indx], sizeflag);
12549       return;
12550     }
12551   /* Skip mod/rm byte.  */
12552   MODRM_CHECK;
12553   codep++;
12554
12555   dp = &float_reg[floatop - 0xd8][modrm.reg];
12556   if (dp->name == NULL)
12557     {
12558       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12559
12560       /* Instruction fnstsw is only one with strange arg.  */
12561       if (floatop == 0xdf && codep[-1] == 0xe0)
12562         strcpy (op_out[0], names16[0]);
12563     }
12564   else
12565     {
12566       putop (dp->name, sizeflag);
12567
12568       obufp = op_out[0];
12569       op_ad = 2;
12570       if (dp->op[0].rtn)
12571         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12572
12573       obufp = op_out[1];
12574       op_ad = 1;
12575       if (dp->op[1].rtn)
12576         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12577     }
12578 }
12579
12580 /* Like oappend (below), but S is a string starting with '%'.
12581    In Intel syntax, the '%' is elided.  */
12582 static void
12583 oappend_maybe_intel (const char *s)
12584 {
12585   oappend (s + intel_syntax);
12586 }
12587
12588 static void
12589 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12590 {
12591   oappend_maybe_intel ("%st");
12592 }
12593
12594 static void
12595 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12596 {
12597   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12598   oappend_maybe_intel (scratchbuf);
12599 }
12600
12601 /* Capital letters in template are macros.  */
12602 static int
12603 putop (const char *in_template, int sizeflag)
12604 {
12605   const char *p;
12606   int alt = 0;
12607   int cond = 1;
12608   unsigned int l = 0, len = 0;
12609   char last[4];
12610
12611   for (p = in_template; *p; p++)
12612     {
12613       if (len > l)
12614         {
12615           if (l >= sizeof (last) || !ISUPPER (*p))
12616             abort ();
12617           last[l++] = *p;
12618           continue;
12619         }
12620       switch (*p)
12621         {
12622         default:
12623           *obufp++ = *p;
12624           break;
12625         case '%':
12626           len++;
12627           break;
12628         case '!':
12629           cond = 0;
12630           break;
12631         case '{':
12632           if (intel_syntax)
12633             {
12634               while (*++p != '|')
12635                 if (*p == '}' || *p == '\0')
12636                   abort ();
12637               alt = 1;
12638             }
12639           break;
12640         case '|':
12641           while (*++p != '}')
12642             {
12643               if (*p == '\0')
12644                 abort ();
12645             }
12646           break;
12647         case '}':
12648           alt = 0;
12649           break;
12650         case 'A':
12651           if (intel_syntax)
12652             break;
12653           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12654             *obufp++ = 'b';
12655           break;
12656         case 'B':
12657           if (l == 0)
12658             {
12659             case_B:
12660               if (intel_syntax)
12661                 break;
12662               if (sizeflag & SUFFIX_ALWAYS)
12663                 *obufp++ = 'b';
12664             }
12665           else if (l == 1 && last[0] == 'L')
12666             {
12667               if (address_mode == mode_64bit
12668                   && !(prefixes & PREFIX_ADDR))
12669                 {
12670                   *obufp++ = 'a';
12671                   *obufp++ = 'b';
12672                   *obufp++ = 's';
12673                 }
12674
12675               goto case_B;
12676             }
12677           else
12678             abort ();
12679           break;
12680         case 'C':
12681           if (intel_syntax && !alt)
12682             break;
12683           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12684             {
12685               if (sizeflag & DFLAG)
12686                 *obufp++ = intel_syntax ? 'd' : 'l';
12687               else
12688                 *obufp++ = intel_syntax ? 'w' : 's';
12689               used_prefixes |= (prefixes & PREFIX_DATA);
12690             }
12691           break;
12692         case 'D':
12693           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12694             break;
12695           USED_REX (REX_W);
12696           if (modrm.mod == 3)
12697             {
12698               if (rex & REX_W)
12699                 *obufp++ = 'q';
12700               else
12701                 {
12702                   if (sizeflag & DFLAG)
12703                     *obufp++ = intel_syntax ? 'd' : 'l';
12704                   else
12705                     *obufp++ = 'w';
12706                   used_prefixes |= (prefixes & PREFIX_DATA);
12707                 }
12708             }
12709           else
12710             *obufp++ = 'w';
12711           break;
12712         case 'E':               /* For jcxz/jecxz */
12713           if (address_mode == mode_64bit)
12714             {
12715               if (sizeflag & AFLAG)
12716                 *obufp++ = 'r';
12717               else
12718                 *obufp++ = 'e';
12719             }
12720           else
12721             if (sizeflag & AFLAG)
12722               *obufp++ = 'e';
12723           used_prefixes |= (prefixes & PREFIX_ADDR);
12724           break;
12725         case 'F':
12726           if (intel_syntax)
12727             break;
12728           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12729             {
12730               if (sizeflag & AFLAG)
12731                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12732               else
12733                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12734               used_prefixes |= (prefixes & PREFIX_ADDR);
12735             }
12736           break;
12737         case 'G':
12738           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12739             break;
12740           if ((rex & REX_W) || (sizeflag & DFLAG))
12741             *obufp++ = 'l';
12742           else
12743             *obufp++ = 'w';
12744           if (!(rex & REX_W))
12745             used_prefixes |= (prefixes & PREFIX_DATA);
12746           break;
12747         case 'H':
12748           if (intel_syntax)
12749             break;
12750           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12751               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12752             {
12753               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12754               *obufp++ = ',';
12755               *obufp++ = 'p';
12756               if (prefixes & PREFIX_DS)
12757                 *obufp++ = 't';
12758               else
12759                 *obufp++ = 'n';
12760             }
12761           break;
12762         case 'K':
12763           USED_REX (REX_W);
12764           if (rex & REX_W)
12765             *obufp++ = 'q';
12766           else
12767             *obufp++ = 'd';
12768           break;
12769         case 'Z':
12770           if (l != 0)
12771             {
12772               if (l != 1 || last[0] != 'X')
12773                 abort ();
12774               if (!need_vex || !vex.evex)
12775                 abort ();
12776               if (intel_syntax
12777                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12778                 break;
12779               switch (vex.length)
12780                 {
12781                 case 128:
12782                   *obufp++ = 'x';
12783                   break;
12784                 case 256:
12785                   *obufp++ = 'y';
12786                   break;
12787                 case 512:
12788                   *obufp++ = 'z';
12789                   break;
12790                 default:
12791                   abort ();
12792                 }
12793               break;
12794             }
12795           if (intel_syntax)
12796             break;
12797           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12798             {
12799               *obufp++ = 'q';
12800               break;
12801             }
12802           /* Fall through.  */
12803           goto case_L;
12804         case 'L':
12805           if (l != 0)
12806             abort ();
12807         case_L:
12808           if (intel_syntax)
12809             break;
12810           if (sizeflag & SUFFIX_ALWAYS)
12811             *obufp++ = 'l';
12812           break;
12813         case 'M':
12814           if (intel_mnemonic != cond)
12815             *obufp++ = 'r';
12816           break;
12817         case 'N':
12818           if ((prefixes & PREFIX_FWAIT) == 0)
12819             *obufp++ = 'n';
12820           else
12821             used_prefixes |= PREFIX_FWAIT;
12822           break;
12823         case 'O':
12824           USED_REX (REX_W);
12825           if (rex & REX_W)
12826             *obufp++ = 'o';
12827           else if (intel_syntax && (sizeflag & DFLAG))
12828             *obufp++ = 'q';
12829           else
12830             *obufp++ = 'd';
12831           if (!(rex & REX_W))
12832             used_prefixes |= (prefixes & PREFIX_DATA);
12833           break;
12834         case '&':
12835           if (!intel_syntax
12836               && address_mode == mode_64bit
12837               && isa64 == intel64)
12838             {
12839               *obufp++ = 'q';
12840               break;
12841             }
12842           /* Fall through.  */
12843         case 'T':
12844           if (!intel_syntax
12845               && address_mode == mode_64bit
12846               && ((sizeflag & DFLAG) || (rex & REX_W)))
12847             {
12848               *obufp++ = 'q';
12849               break;
12850             }
12851           /* Fall through.  */
12852           goto case_P;
12853         case 'P':
12854           if (l == 0)
12855             {
12856             case_P:
12857               if (intel_syntax)
12858                 {
12859                   if ((rex & REX_W) == 0
12860                       && (prefixes & PREFIX_DATA))
12861                     {
12862                       if ((sizeflag & DFLAG) == 0)
12863                         *obufp++ = 'w';
12864                       used_prefixes |= (prefixes & PREFIX_DATA);
12865                     }
12866                   break;
12867                 }
12868               if ((prefixes & PREFIX_DATA)
12869                   || (rex & REX_W)
12870                   || (sizeflag & SUFFIX_ALWAYS))
12871                 {
12872                   USED_REX (REX_W);
12873                   if (rex & REX_W)
12874                     *obufp++ = 'q';
12875                   else
12876                     {
12877                       if (sizeflag & DFLAG)
12878                         *obufp++ = 'l';
12879                       else
12880                         *obufp++ = 'w';
12881                       used_prefixes |= (prefixes & PREFIX_DATA);
12882                     }
12883                 }
12884             }
12885           else if (l == 1 && last[0] == 'L')
12886             {
12887               if ((prefixes & PREFIX_DATA)
12888                   || (rex & REX_W)
12889                   || (sizeflag & SUFFIX_ALWAYS))
12890                 {
12891                   USED_REX (REX_W);
12892                   if (rex & REX_W)
12893                     *obufp++ = 'q';
12894                   else
12895                     {
12896                       if (sizeflag & DFLAG)
12897                         *obufp++ = intel_syntax ? 'd' : 'l';
12898                       else
12899                         *obufp++ = 'w';
12900                       used_prefixes |= (prefixes & PREFIX_DATA);
12901                     }
12902                 }
12903             }
12904           else
12905             abort ();
12906           break;
12907         case 'U':
12908           if (intel_syntax)
12909             break;
12910           if (address_mode == mode_64bit
12911               && ((sizeflag & DFLAG) || (rex & REX_W)))
12912             {
12913               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12914                 *obufp++ = 'q';
12915               break;
12916             }
12917           /* Fall through.  */
12918           goto case_Q;
12919         case 'Q':
12920           if (l == 0)
12921             {
12922             case_Q:
12923               if (intel_syntax && !alt)
12924                 break;
12925               USED_REX (REX_W);
12926               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12927                 {
12928                   if (rex & REX_W)
12929                     *obufp++ = 'q';
12930                   else
12931                     {
12932                       if (sizeflag & DFLAG)
12933                         *obufp++ = intel_syntax ? 'd' : 'l';
12934                       else
12935                         *obufp++ = 'w';
12936                       used_prefixes |= (prefixes & PREFIX_DATA);
12937                     }
12938                 }
12939             }
12940           else if (l == 1 && last[0] == 'L')
12941             {
12942               if ((intel_syntax && need_modrm)
12943                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12944                 break;
12945               if ((rex & REX_W))
12946                 {
12947                   USED_REX (REX_W);
12948                   *obufp++ = 'q';
12949                 }
12950               else if((address_mode == mode_64bit && need_modrm)
12951                       || (sizeflag & SUFFIX_ALWAYS))
12952                 *obufp++ = intel_syntax? 'd' : 'l';
12953             }
12954           else
12955             abort ();
12956           break;
12957         case 'R':
12958           USED_REX (REX_W);
12959           if (rex & REX_W)
12960             *obufp++ = 'q';
12961           else if (sizeflag & DFLAG)
12962             {
12963               if (intel_syntax)
12964                   *obufp++ = 'd';
12965               else
12966                   *obufp++ = 'l';
12967             }
12968           else
12969             *obufp++ = 'w';
12970           if (intel_syntax && !p[1]
12971               && ((rex & REX_W) || (sizeflag & DFLAG)))
12972             *obufp++ = 'e';
12973           if (!(rex & REX_W))
12974             used_prefixes |= (prefixes & PREFIX_DATA);
12975           break;
12976         case 'V':
12977           if (l == 0)
12978             {
12979               if (intel_syntax)
12980                 break;
12981               if (address_mode == mode_64bit
12982                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12983                 {
12984                   if (sizeflag & SUFFIX_ALWAYS)
12985                     *obufp++ = 'q';
12986                   break;
12987                 }
12988             }
12989           else if (l == 1 && last[0] == 'L')
12990             {
12991               if (rex & REX_W)
12992                 {
12993                   *obufp++ = 'a';
12994                   *obufp++ = 'b';
12995                   *obufp++ = 's';
12996                 }
12997             }
12998           else
12999             abort ();
13000           /* Fall through.  */
13001           goto case_S;
13002         case 'S':
13003           if (l == 0)
13004             {
13005             case_S:
13006               if (intel_syntax)
13007                 break;
13008               if (sizeflag & SUFFIX_ALWAYS)
13009                 {
13010                   if (rex & REX_W)
13011                     *obufp++ = 'q';
13012                   else
13013                     {
13014                       if (sizeflag & DFLAG)
13015                         *obufp++ = 'l';
13016                       else
13017                         *obufp++ = 'w';
13018                       used_prefixes |= (prefixes & PREFIX_DATA);
13019                     }
13020                 }
13021             }
13022           else if (l == 1 && last[0] == 'L')
13023             {
13024               if (address_mode == mode_64bit
13025                   && !(prefixes & PREFIX_ADDR))
13026                 {
13027                   *obufp++ = 'a';
13028                   *obufp++ = 'b';
13029                   *obufp++ = 's';
13030                 }
13031
13032               goto case_S;
13033             }
13034           else
13035             abort ();
13036           break;
13037         case 'X':
13038           if (l != 0)
13039             abort ();
13040           if (need_vex
13041               ? vex.prefix == DATA_PREFIX_OPCODE
13042               : prefixes & PREFIX_DATA)
13043             {
13044               *obufp++ = 'd';
13045               used_prefixes |= PREFIX_DATA;
13046             }
13047           else
13048             *obufp++ = 's';
13049           break;
13050         case 'Y':
13051           if (l == 1 && last[0] == 'X')
13052             {
13053               if (!need_vex)
13054                 abort ();
13055               if (intel_syntax
13056                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13057                 break;
13058               switch (vex.length)
13059                 {
13060                 case 128:
13061                   *obufp++ = 'x';
13062                   break;
13063                 case 256:
13064                   *obufp++ = 'y';
13065                   break;
13066                 case 512:
13067                   if (!vex.evex)
13068                 default:
13069                     abort ();
13070                 }
13071             }
13072           else
13073             abort ();
13074           break;
13075         case 'W':
13076           if (l == 0)
13077             {
13078               /* operand size flag for cwtl, cbtw */
13079               USED_REX (REX_W);
13080               if (rex & REX_W)
13081                 {
13082                   if (intel_syntax)
13083                     *obufp++ = 'd';
13084                   else
13085                     *obufp++ = 'l';
13086                 }
13087               else if (sizeflag & DFLAG)
13088                 *obufp++ = 'w';
13089               else
13090                 *obufp++ = 'b';
13091               if (!(rex & REX_W))
13092                 used_prefixes |= (prefixes & PREFIX_DATA);
13093             }
13094           else if (l == 1)
13095             {
13096               if (!need_vex)
13097                 abort ();
13098               if (last[0] == 'X')
13099                 *obufp++ = vex.w ? 'd': 's';
13100               else if (last[0] == 'L')
13101                 *obufp++ = vex.w ? 'q': 'd';
13102               else if (last[0] == 'B')
13103                 *obufp++ = vex.w ? 'w': 'b';
13104               else
13105                 abort ();
13106             }
13107           else
13108             abort ();
13109           break;
13110         case '^':
13111           if (intel_syntax)
13112             break;
13113           if (isa64 == intel64 && (rex & REX_W))
13114             {
13115               USED_REX (REX_W);
13116               *obufp++ = 'q';
13117               break;
13118             }
13119           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13120             {
13121               if (sizeflag & DFLAG)
13122                 *obufp++ = 'l';
13123               else
13124                 *obufp++ = 'w';
13125               used_prefixes |= (prefixes & PREFIX_DATA);
13126             }
13127           break;
13128         case '@':
13129           if (intel_syntax)
13130             break;
13131           if (address_mode == mode_64bit
13132               && (isa64 == intel64
13133                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13134               *obufp++ = 'q';
13135           else if ((prefixes & PREFIX_DATA))
13136             {
13137               if (!(sizeflag & DFLAG))
13138                 *obufp++ = 'w';
13139               used_prefixes |= (prefixes & PREFIX_DATA);
13140             }
13141           break;
13142         }
13143
13144       if (len == l)
13145         len = l = 0;
13146     }
13147   *obufp = 0;
13148   mnemonicendp = obufp;
13149   return 0;
13150 }
13151
13152 static void
13153 oappend (const char *s)
13154 {
13155   obufp = stpcpy (obufp, s);
13156 }
13157
13158 static void
13159 append_seg (void)
13160 {
13161   /* Only print the active segment register.  */
13162   if (!active_seg_prefix)
13163     return;
13164
13165   used_prefixes |= active_seg_prefix;
13166   switch (active_seg_prefix)
13167     {
13168     case PREFIX_CS:
13169       oappend_maybe_intel ("%cs:");
13170       break;
13171     case PREFIX_DS:
13172       oappend_maybe_intel ("%ds:");
13173       break;
13174     case PREFIX_SS:
13175       oappend_maybe_intel ("%ss:");
13176       break;
13177     case PREFIX_ES:
13178       oappend_maybe_intel ("%es:");
13179       break;
13180     case PREFIX_FS:
13181       oappend_maybe_intel ("%fs:");
13182       break;
13183     case PREFIX_GS:
13184       oappend_maybe_intel ("%gs:");
13185       break;
13186     default:
13187       break;
13188     }
13189 }
13190
13191 static void
13192 OP_indirE (int bytemode, int sizeflag)
13193 {
13194   if (!intel_syntax)
13195     oappend ("*");
13196   OP_E (bytemode, sizeflag);
13197 }
13198
13199 static void
13200 print_operand_value (char *buf, int hex, bfd_vma disp)
13201 {
13202   if (address_mode == mode_64bit)
13203     {
13204       if (hex)
13205         {
13206           char tmp[30];
13207           int i;
13208           buf[0] = '0';
13209           buf[1] = 'x';
13210           sprintf_vma (tmp, disp);
13211           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13212           strcpy (buf + 2, tmp + i);
13213         }
13214       else
13215         {
13216           bfd_signed_vma v = disp;
13217           char tmp[30];
13218           int i;
13219           if (v < 0)
13220             {
13221               *(buf++) = '-';
13222               v = -disp;
13223               /* Check for possible overflow on 0x8000000000000000.  */
13224               if (v < 0)
13225                 {
13226                   strcpy (buf, "9223372036854775808");
13227                   return;
13228                 }
13229             }
13230           if (!v)
13231             {
13232               strcpy (buf, "0");
13233               return;
13234             }
13235
13236           i = 0;
13237           tmp[29] = 0;
13238           while (v)
13239             {
13240               tmp[28 - i] = (v % 10) + '0';
13241               v /= 10;
13242               i++;
13243             }
13244           strcpy (buf, tmp + 29 - i);
13245         }
13246     }
13247   else
13248     {
13249       if (hex)
13250         sprintf (buf, "0x%x", (unsigned int) disp);
13251       else
13252         sprintf (buf, "%d", (int) disp);
13253     }
13254 }
13255
13256 /* Put DISP in BUF as signed hex number.  */
13257
13258 static void
13259 print_displacement (char *buf, bfd_vma disp)
13260 {
13261   bfd_signed_vma val = disp;
13262   char tmp[30];
13263   int i, j = 0;
13264
13265   if (val < 0)
13266     {
13267       buf[j++] = '-';
13268       val = -disp;
13269
13270       /* Check for possible overflow.  */
13271       if (val < 0)
13272         {
13273           switch (address_mode)
13274             {
13275             case mode_64bit:
13276               strcpy (buf + j, "0x8000000000000000");
13277               break;
13278             case mode_32bit:
13279               strcpy (buf + j, "0x80000000");
13280               break;
13281             case mode_16bit:
13282               strcpy (buf + j, "0x8000");
13283               break;
13284             }
13285           return;
13286         }
13287     }
13288
13289   buf[j++] = '0';
13290   buf[j++] = 'x';
13291
13292   sprintf_vma (tmp, (bfd_vma) val);
13293   for (i = 0; tmp[i] == '0'; i++)
13294     continue;
13295   if (tmp[i] == '\0')
13296     i--;
13297   strcpy (buf + j, tmp + i);
13298 }
13299
13300 static void
13301 intel_operand_size (int bytemode, int sizeflag)
13302 {
13303   if (vex.evex
13304       && vex.b
13305       && (bytemode == x_mode
13306           || bytemode == evex_half_bcst_xmmq_mode))
13307     {
13308       if (vex.w)
13309         oappend ("QWORD PTR ");
13310       else
13311         oappend ("DWORD PTR ");
13312       return;
13313     }
13314   switch (bytemode)
13315     {
13316     case b_mode:
13317     case b_swap_mode:
13318     case dqb_mode:
13319     case db_mode:
13320       oappend ("BYTE PTR ");
13321       break;
13322     case w_mode:
13323     case dw_mode:
13324     case dqw_mode:
13325       oappend ("WORD PTR ");
13326       break;
13327     case indir_v_mode:
13328       if (address_mode == mode_64bit && isa64 == intel64)
13329         {
13330           oappend ("QWORD PTR ");
13331           break;
13332         }
13333       /* Fall through.  */
13334     case stack_v_mode:
13335       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13336         {
13337           oappend ("QWORD PTR ");
13338           break;
13339         }
13340       /* Fall through.  */
13341     case v_mode:
13342     case v_swap_mode:
13343     case dq_mode:
13344       USED_REX (REX_W);
13345       if (rex & REX_W)
13346         oappend ("QWORD PTR ");
13347       else
13348         {
13349           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13350             oappend ("DWORD PTR ");
13351           else
13352             oappend ("WORD PTR ");
13353           used_prefixes |= (prefixes & PREFIX_DATA);
13354         }
13355       break;
13356     case z_mode:
13357       if ((rex & REX_W) || (sizeflag & DFLAG))
13358         *obufp++ = 'D';
13359       oappend ("WORD PTR ");
13360       if (!(rex & REX_W))
13361         used_prefixes |= (prefixes & PREFIX_DATA);
13362       break;
13363     case a_mode:
13364       if (sizeflag & DFLAG)
13365         oappend ("QWORD PTR ");
13366       else
13367         oappend ("DWORD PTR ");
13368       used_prefixes |= (prefixes & PREFIX_DATA);
13369       break;
13370     case movsxd_mode:
13371       if (!(sizeflag & DFLAG) && isa64 == intel64)
13372         oappend ("WORD PTR ");
13373       else
13374         oappend ("DWORD PTR ");
13375       used_prefixes |= (prefixes & PREFIX_DATA);
13376       break;
13377     case d_mode:
13378     case d_scalar_swap_mode:
13379     case d_swap_mode:
13380     case dqd_mode:
13381       oappend ("DWORD PTR ");
13382       break;
13383     case q_mode:
13384     case q_scalar_swap_mode:
13385     case q_swap_mode:
13386       oappend ("QWORD PTR ");
13387       break;
13388     case m_mode:
13389       if (address_mode == mode_64bit)
13390         oappend ("QWORD PTR ");
13391       else
13392         oappend ("DWORD PTR ");
13393       break;
13394     case f_mode:
13395       if (sizeflag & DFLAG)
13396         oappend ("FWORD PTR ");
13397       else
13398         oappend ("DWORD PTR ");
13399       used_prefixes |= (prefixes & PREFIX_DATA);
13400       break;
13401     case t_mode:
13402       oappend ("TBYTE PTR ");
13403       break;
13404     case x_mode:
13405     case x_swap_mode:
13406     case evex_x_gscat_mode:
13407     case evex_x_nobcst_mode:
13408     case b_scalar_mode:
13409     case w_scalar_mode:
13410       if (need_vex)
13411         {
13412           switch (vex.length)
13413             {
13414             case 128:
13415               oappend ("XMMWORD PTR ");
13416               break;
13417             case 256:
13418               oappend ("YMMWORD PTR ");
13419               break;
13420             case 512:
13421               oappend ("ZMMWORD PTR ");
13422               break;
13423             default:
13424               abort ();
13425             }
13426         }
13427       else
13428         oappend ("XMMWORD PTR ");
13429       break;
13430     case xmm_mode:
13431       oappend ("XMMWORD PTR ");
13432       break;
13433     case ymm_mode:
13434       oappend ("YMMWORD PTR ");
13435       break;
13436     case xmmq_mode:
13437     case evex_half_bcst_xmmq_mode:
13438       if (!need_vex)
13439         abort ();
13440
13441       switch (vex.length)
13442         {
13443         case 128:
13444           oappend ("QWORD PTR ");
13445           break;
13446         case 256:
13447           oappend ("XMMWORD PTR ");
13448           break;
13449         case 512:
13450           oappend ("YMMWORD PTR ");
13451           break;
13452         default:
13453           abort ();
13454         }
13455       break;
13456     case xmm_mb_mode:
13457       if (!need_vex)
13458         abort ();
13459
13460       switch (vex.length)
13461         {
13462         case 128:
13463         case 256:
13464         case 512:
13465           oappend ("BYTE PTR ");
13466           break;
13467         default:
13468           abort ();
13469         }
13470       break;
13471     case xmm_mw_mode:
13472       if (!need_vex)
13473         abort ();
13474
13475       switch (vex.length)
13476         {
13477         case 128:
13478         case 256:
13479         case 512:
13480           oappend ("WORD PTR ");
13481           break;
13482         default:
13483           abort ();
13484         }
13485       break;
13486     case xmm_md_mode:
13487       if (!need_vex)
13488         abort ();
13489
13490       switch (vex.length)
13491         {
13492         case 128:
13493         case 256:
13494         case 512:
13495           oappend ("DWORD PTR ");
13496           break;
13497         default:
13498           abort ();
13499         }
13500       break;
13501     case xmm_mq_mode:
13502       if (!need_vex)
13503         abort ();
13504
13505       switch (vex.length)
13506         {
13507         case 128:
13508         case 256:
13509         case 512:
13510           oappend ("QWORD PTR ");
13511           break;
13512         default:
13513           abort ();
13514         }
13515       break;
13516     case xmmdw_mode:
13517       if (!need_vex)
13518         abort ();
13519
13520       switch (vex.length)
13521         {
13522         case 128:
13523           oappend ("WORD PTR ");
13524           break;
13525         case 256:
13526           oappend ("DWORD PTR ");
13527           break;
13528         case 512:
13529           oappend ("QWORD PTR ");
13530           break;
13531         default:
13532           abort ();
13533         }
13534       break;
13535     case xmmqd_mode:
13536       if (!need_vex)
13537         abort ();
13538
13539       switch (vex.length)
13540         {
13541         case 128:
13542           oappend ("DWORD PTR ");
13543           break;
13544         case 256:
13545           oappend ("QWORD PTR ");
13546           break;
13547         case 512:
13548           oappend ("XMMWORD PTR ");
13549           break;
13550         default:
13551           abort ();
13552         }
13553       break;
13554     case ymmq_mode:
13555       if (!need_vex)
13556         abort ();
13557
13558       switch (vex.length)
13559         {
13560         case 128:
13561           oappend ("QWORD PTR ");
13562           break;
13563         case 256:
13564           oappend ("YMMWORD PTR ");
13565           break;
13566         case 512:
13567           oappend ("ZMMWORD PTR ");
13568           break;
13569         default:
13570           abort ();
13571         }
13572       break;
13573     case ymmxmm_mode:
13574       if (!need_vex)
13575         abort ();
13576
13577       switch (vex.length)
13578         {
13579         case 128:
13580         case 256:
13581           oappend ("XMMWORD PTR ");
13582           break;
13583         default:
13584           abort ();
13585         }
13586       break;
13587     case o_mode:
13588       oappend ("OWORD PTR ");
13589       break;
13590     case vex_scalar_w_dq_mode:
13591       if (!need_vex)
13592         abort ();
13593
13594       if (vex.w)
13595         oappend ("QWORD PTR ");
13596       else
13597         oappend ("DWORD PTR ");
13598       break;
13599     case vex_vsib_d_w_dq_mode:
13600     case vex_vsib_q_w_dq_mode:
13601       if (!need_vex)
13602         abort ();
13603
13604       if (!vex.evex)
13605         {
13606           if (vex.w)
13607             oappend ("QWORD PTR ");
13608           else
13609             oappend ("DWORD PTR ");
13610         }
13611       else
13612         {
13613           switch (vex.length)
13614             {
13615             case 128:
13616               oappend ("XMMWORD PTR ");
13617               break;
13618             case 256:
13619               oappend ("YMMWORD PTR ");
13620               break;
13621             case 512:
13622               oappend ("ZMMWORD PTR ");
13623               break;
13624             default:
13625               abort ();
13626             }
13627         }
13628       break;
13629     case vex_vsib_q_w_d_mode:
13630     case vex_vsib_d_w_d_mode:
13631       if (!need_vex || !vex.evex)
13632         abort ();
13633
13634       switch (vex.length)
13635         {
13636         case 128:
13637           oappend ("QWORD PTR ");
13638           break;
13639         case 256:
13640           oappend ("XMMWORD PTR ");
13641           break;
13642         case 512:
13643           oappend ("YMMWORD PTR ");
13644           break;
13645         default:
13646           abort ();
13647         }
13648
13649       break;
13650     case mask_bd_mode:
13651       if (!need_vex || vex.length != 128)
13652         abort ();
13653       if (vex.w)
13654         oappend ("DWORD PTR ");
13655       else
13656         oappend ("BYTE PTR ");
13657       break;
13658     case mask_mode:
13659       if (!need_vex)
13660         abort ();
13661       if (vex.w)
13662         oappend ("QWORD PTR ");
13663       else
13664         oappend ("WORD PTR ");
13665       break;
13666     case v_bnd_mode:
13667     case v_bndmk_mode:
13668     default:
13669       break;
13670     }
13671 }
13672
13673 static void
13674 OP_E_register (int bytemode, int sizeflag)
13675 {
13676   int reg = modrm.rm;
13677   const char **names;
13678
13679   USED_REX (REX_B);
13680   if ((rex & REX_B))
13681     reg += 8;
13682
13683   if ((sizeflag & SUFFIX_ALWAYS)
13684       && (bytemode == b_swap_mode
13685           || bytemode == bnd_swap_mode
13686           || bytemode == v_swap_mode))
13687     swap_operand ();
13688
13689   switch (bytemode)
13690     {
13691     case b_mode:
13692     case b_swap_mode:
13693       USED_REX (0);
13694       if (rex)
13695         names = names8rex;
13696       else
13697         names = names8;
13698       break;
13699     case w_mode:
13700       names = names16;
13701       break;
13702     case d_mode:
13703     case dw_mode:
13704     case db_mode:
13705       names = names32;
13706       break;
13707     case q_mode:
13708       names = names64;
13709       break;
13710     case m_mode:
13711     case v_bnd_mode:
13712       names = address_mode == mode_64bit ? names64 : names32;
13713       break;
13714     case bnd_mode:
13715     case bnd_swap_mode:
13716       if (reg > 0x3)
13717         {
13718           oappend ("(bad)");
13719           return;
13720         }
13721       names = names_bnd;
13722       break;
13723     case indir_v_mode:
13724       if (address_mode == mode_64bit && isa64 == intel64)
13725         {
13726           names = names64;
13727           break;
13728         }
13729       /* Fall through.  */
13730     case stack_v_mode:
13731       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13732         {
13733           names = names64;
13734           break;
13735         }
13736       bytemode = v_mode;
13737       /* Fall through.  */
13738     case v_mode:
13739     case v_swap_mode:
13740     case dq_mode:
13741     case dqb_mode:
13742     case dqd_mode:
13743     case dqw_mode:
13744       USED_REX (REX_W);
13745       if (rex & REX_W)
13746         names = names64;
13747       else
13748         {
13749           if ((sizeflag & DFLAG)
13750               || (bytemode != v_mode
13751                   && bytemode != v_swap_mode))
13752             names = names32;
13753           else
13754             names = names16;
13755           used_prefixes |= (prefixes & PREFIX_DATA);
13756         }
13757       break;
13758     case movsxd_mode:
13759       if (!(sizeflag & DFLAG) && isa64 == intel64)
13760         names = names16;
13761       else
13762         names = names32;
13763       used_prefixes |= (prefixes & PREFIX_DATA);
13764       break;
13765     case va_mode:
13766       names = (address_mode == mode_64bit
13767                ? names64 : names32);
13768       if (!(prefixes & PREFIX_ADDR))
13769         names = (address_mode == mode_16bit
13770                      ? names16 : names);
13771       else
13772         {
13773           /* Remove "addr16/addr32".  */
13774           all_prefixes[last_addr_prefix] = 0;
13775           names = (address_mode != mode_32bit
13776                        ? names32 : names16);
13777           used_prefixes |= PREFIX_ADDR;
13778         }
13779       break;
13780     case mask_bd_mode:
13781     case mask_mode:
13782       if (reg > 0x7)
13783         {
13784           oappend ("(bad)");
13785           return;
13786         }
13787       names = names_mask;
13788       break;
13789     case 0:
13790       return;
13791     default:
13792       oappend (INTERNAL_DISASSEMBLER_ERROR);
13793       return;
13794     }
13795   oappend (names[reg]);
13796 }
13797
13798 static void
13799 OP_E_memory (int bytemode, int sizeflag)
13800 {
13801   bfd_vma disp = 0;
13802   int add = (rex & REX_B) ? 8 : 0;
13803   int riprel = 0;
13804   int shift;
13805
13806   if (vex.evex)
13807     {
13808       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13809       if (vex.b
13810           && bytemode != x_mode
13811           && bytemode != xmmq_mode
13812           && bytemode != evex_half_bcst_xmmq_mode)
13813         {
13814           BadOp ();
13815           return;
13816         }
13817       switch (bytemode)
13818         {
13819         case dqw_mode:
13820         case dw_mode:
13821           shift = 1;
13822           break;
13823         case dqb_mode:
13824         case db_mode:
13825           shift = 0;
13826           break;
13827         case dq_mode:
13828           if (address_mode != mode_64bit)
13829             {
13830               shift = 2;
13831               break;
13832             }
13833             /* fall through */
13834         case vex_scalar_w_dq_mode:
13835         case vex_vsib_d_w_dq_mode:
13836         case vex_vsib_d_w_d_mode:
13837         case vex_vsib_q_w_dq_mode:
13838         case vex_vsib_q_w_d_mode:
13839         case evex_x_gscat_mode:
13840           shift = vex.w ? 3 : 2;
13841           break;
13842         case x_mode:
13843         case evex_half_bcst_xmmq_mode:
13844         case xmmq_mode:
13845           if (vex.b)
13846             {
13847               shift = vex.w ? 3 : 2;
13848               break;
13849             }
13850           /* Fall through.  */
13851         case xmmqd_mode:
13852         case xmmdw_mode:
13853         case ymmq_mode:
13854         case evex_x_nobcst_mode:
13855         case x_swap_mode:
13856           switch (vex.length)
13857             {
13858             case 128:
13859               shift = 4;
13860               break;
13861             case 256:
13862               shift = 5;
13863               break;
13864             case 512:
13865               shift = 6;
13866               break;
13867             default:
13868               abort ();
13869             }
13870           break;
13871         case ymm_mode:
13872           shift = 5;
13873           break;
13874         case xmm_mode:
13875           shift = 4;
13876           break;
13877         case xmm_mq_mode:
13878         case q_mode:
13879         case q_swap_mode:
13880         case q_scalar_swap_mode:
13881           shift = 3;
13882           break;
13883         case dqd_mode:
13884         case xmm_md_mode:
13885         case d_mode:
13886         case d_swap_mode:
13887         case d_scalar_swap_mode:
13888           shift = 2;
13889           break;
13890         case w_scalar_mode:
13891         case xmm_mw_mode:
13892           shift = 1;
13893           break;
13894         case b_scalar_mode:
13895         case xmm_mb_mode:
13896           shift = 0;
13897           break;
13898         default:
13899           abort ();
13900         }
13901       /* Make necessary corrections to shift for modes that need it.
13902          For these modes we currently have shift 4, 5 or 6 depending on
13903          vex.length (it corresponds to xmmword, ymmword or zmmword
13904          operand).  We might want to make it 3, 4 or 5 (e.g. for
13905          xmmq_mode).  In case of broadcast enabled the corrections
13906          aren't needed, as element size is always 32 or 64 bits.  */
13907       if (!vex.b
13908           && (bytemode == xmmq_mode
13909               || bytemode == evex_half_bcst_xmmq_mode))
13910         shift -= 1;
13911       else if (bytemode == xmmqd_mode)
13912         shift -= 2;
13913       else if (bytemode == xmmdw_mode)
13914         shift -= 3;
13915       else if (bytemode == ymmq_mode && vex.length == 128)
13916         shift -= 1;
13917     }
13918   else
13919     shift = 0;
13920
13921   USED_REX (REX_B);
13922   if (intel_syntax)
13923     intel_operand_size (bytemode, sizeflag);
13924   append_seg ();
13925
13926   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13927     {
13928       /* 32/64 bit address mode */
13929       int havedisp;
13930       int havesib;
13931       int havebase;
13932       int haveindex;
13933       int needindex;
13934       int needaddr32;
13935       int base, rbase;
13936       int vindex = 0;
13937       int scale = 0;
13938       int addr32flag = !((sizeflag & AFLAG)
13939                          || bytemode == v_bnd_mode
13940                          || bytemode == v_bndmk_mode
13941                          || bytemode == bnd_mode
13942                          || bytemode == bnd_swap_mode);
13943       const char **indexes64 = names64;
13944       const char **indexes32 = names32;
13945
13946       havesib = 0;
13947       havebase = 1;
13948       haveindex = 0;
13949       base = modrm.rm;
13950
13951       if (base == 4)
13952         {
13953           havesib = 1;
13954           vindex = sib.index;
13955           USED_REX (REX_X);
13956           if (rex & REX_X)
13957             vindex += 8;
13958           switch (bytemode)
13959             {
13960             case vex_vsib_d_w_dq_mode:
13961             case vex_vsib_d_w_d_mode:
13962             case vex_vsib_q_w_dq_mode:
13963             case vex_vsib_q_w_d_mode:
13964               if (!need_vex)
13965                 abort ();
13966               if (vex.evex)
13967                 {
13968                   if (!vex.v)
13969                     vindex += 16;
13970                 }
13971
13972               haveindex = 1;
13973               switch (vex.length)
13974                 {
13975                 case 128:
13976                   indexes64 = indexes32 = names_xmm;
13977                   break;
13978                 case 256:
13979                   if (!vex.w
13980                       || bytemode == vex_vsib_q_w_dq_mode
13981                       || bytemode == vex_vsib_q_w_d_mode)
13982                     indexes64 = indexes32 = names_ymm;
13983                   else
13984                     indexes64 = indexes32 = names_xmm;
13985                   break;
13986                 case 512:
13987                   if (!vex.w
13988                       || bytemode == vex_vsib_q_w_dq_mode
13989                       || bytemode == vex_vsib_q_w_d_mode)
13990                     indexes64 = indexes32 = names_zmm;
13991                   else
13992                     indexes64 = indexes32 = names_ymm;
13993                   break;
13994                 default:
13995                   abort ();
13996                 }
13997               break;
13998             default:
13999               haveindex = vindex != 4;
14000               break;
14001             }
14002           scale = sib.scale;
14003           base = sib.base;
14004           codep++;
14005         }
14006       rbase = base + add;
14007
14008       switch (modrm.mod)
14009         {
14010         case 0:
14011           if (base == 5)
14012             {
14013               havebase = 0;
14014               if (address_mode == mode_64bit && !havesib)
14015                 riprel = 1;
14016               disp = get32s ();
14017               if (riprel && bytemode == v_bndmk_mode)
14018                 {
14019                   oappend ("(bad)");
14020                   return;
14021                 }
14022             }
14023           break;
14024         case 1:
14025           FETCH_DATA (the_info, codep + 1);
14026           disp = *codep++;
14027           if ((disp & 0x80) != 0)
14028             disp -= 0x100;
14029           if (vex.evex && shift > 0)
14030             disp <<= shift;
14031           break;
14032         case 2:
14033           disp = get32s ();
14034           break;
14035         }
14036
14037       needindex = 0;
14038       needaddr32 = 0;
14039       if (havesib
14040           && !havebase
14041           && !haveindex
14042           && address_mode != mode_16bit)
14043         {
14044           if (address_mode == mode_64bit)
14045             {
14046               /* Display eiz instead of addr32.  */
14047               needindex = addr32flag;
14048               needaddr32 = 1;
14049             }
14050           else
14051             {
14052               /* In 32-bit mode, we need index register to tell [offset]
14053                  from [eiz*1 + offset].  */
14054               needindex = 1;
14055             }
14056         }
14057
14058       havedisp = (havebase
14059                   || needindex
14060                   || (havesib && (haveindex || scale != 0)));
14061
14062       if (!intel_syntax)
14063         if (modrm.mod != 0 || base == 5)
14064           {
14065             if (havedisp || riprel)
14066               print_displacement (scratchbuf, disp);
14067             else
14068               print_operand_value (scratchbuf, 1, disp);
14069             oappend (scratchbuf);
14070             if (riprel)
14071               {
14072                 set_op (disp, 1);
14073                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14074               }
14075           }
14076
14077       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14078           && (address_mode != mode_64bit
14079               || ((bytemode != v_bnd_mode)
14080                   && (bytemode != v_bndmk_mode)
14081                   && (bytemode != bnd_mode)
14082                   && (bytemode != bnd_swap_mode))))
14083         used_prefixes |= PREFIX_ADDR;
14084
14085       if (havedisp || (intel_syntax && riprel))
14086         {
14087           *obufp++ = open_char;
14088           if (intel_syntax && riprel)
14089             {
14090               set_op (disp, 1);
14091               oappend (!addr32flag ? "rip" : "eip");
14092             }
14093           *obufp = '\0';
14094           if (havebase)
14095             oappend (address_mode == mode_64bit && !addr32flag
14096                      ? names64[rbase] : names32[rbase]);
14097           if (havesib)
14098             {
14099               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14100                  print index to tell base + index from base.  */
14101               if (scale != 0
14102                   || needindex
14103                   || haveindex
14104                   || (havebase && base != ESP_REG_NUM))
14105                 {
14106                   if (!intel_syntax || havebase)
14107                     {
14108                       *obufp++ = separator_char;
14109                       *obufp = '\0';
14110                     }
14111                   if (haveindex)
14112                     oappend (address_mode == mode_64bit && !addr32flag
14113                              ? indexes64[vindex] : indexes32[vindex]);
14114                   else
14115                     oappend (address_mode == mode_64bit && !addr32flag
14116                              ? index64 : index32);
14117
14118                   *obufp++ = scale_char;
14119                   *obufp = '\0';
14120                   sprintf (scratchbuf, "%d", 1 << scale);
14121                   oappend (scratchbuf);
14122                 }
14123             }
14124           if (intel_syntax
14125               && (disp || modrm.mod != 0 || base == 5))
14126             {
14127               if (!havedisp || (bfd_signed_vma) disp >= 0)
14128                 {
14129                   *obufp++ = '+';
14130                   *obufp = '\0';
14131                 }
14132               else if (modrm.mod != 1 && disp != -disp)
14133                 {
14134                   *obufp++ = '-';
14135                   *obufp = '\0';
14136                   disp = - (bfd_signed_vma) disp;
14137                 }
14138
14139               if (havedisp)
14140                 print_displacement (scratchbuf, disp);
14141               else
14142                 print_operand_value (scratchbuf, 1, disp);
14143               oappend (scratchbuf);
14144             }
14145
14146           *obufp++ = close_char;
14147           *obufp = '\0';
14148         }
14149       else if (intel_syntax)
14150         {
14151           if (modrm.mod != 0 || base == 5)
14152             {
14153               if (!active_seg_prefix)
14154                 {
14155                   oappend (names_seg[ds_reg - es_reg]);
14156                   oappend (":");
14157                 }
14158               print_operand_value (scratchbuf, 1, disp);
14159               oappend (scratchbuf);
14160             }
14161         }
14162     }
14163   else if (bytemode == v_bnd_mode
14164            || bytemode == v_bndmk_mode
14165            || bytemode == bnd_mode
14166            || bytemode == bnd_swap_mode)
14167     {
14168       oappend ("(bad)");
14169       return;
14170     }
14171   else
14172     {
14173       /* 16 bit address mode */
14174       used_prefixes |= prefixes & PREFIX_ADDR;
14175       switch (modrm.mod)
14176         {
14177         case 0:
14178           if (modrm.rm == 6)
14179             {
14180               disp = get16 ();
14181               if ((disp & 0x8000) != 0)
14182                 disp -= 0x10000;
14183             }
14184           break;
14185         case 1:
14186           FETCH_DATA (the_info, codep + 1);
14187           disp = *codep++;
14188           if ((disp & 0x80) != 0)
14189             disp -= 0x100;
14190           if (vex.evex && shift > 0)
14191             disp <<= shift;
14192           break;
14193         case 2:
14194           disp = get16 ();
14195           if ((disp & 0x8000) != 0)
14196             disp -= 0x10000;
14197           break;
14198         }
14199
14200       if (!intel_syntax)
14201         if (modrm.mod != 0 || modrm.rm == 6)
14202           {
14203             print_displacement (scratchbuf, disp);
14204             oappend (scratchbuf);
14205           }
14206
14207       if (modrm.mod != 0 || modrm.rm != 6)
14208         {
14209           *obufp++ = open_char;
14210           *obufp = '\0';
14211           oappend (index16[modrm.rm]);
14212           if (intel_syntax
14213               && (disp || modrm.mod != 0 || modrm.rm == 6))
14214             {
14215               if ((bfd_signed_vma) disp >= 0)
14216                 {
14217                   *obufp++ = '+';
14218                   *obufp = '\0';
14219                 }
14220               else if (modrm.mod != 1)
14221                 {
14222                   *obufp++ = '-';
14223                   *obufp = '\0';
14224                   disp = - (bfd_signed_vma) disp;
14225                 }
14226
14227               print_displacement (scratchbuf, disp);
14228               oappend (scratchbuf);
14229             }
14230
14231           *obufp++ = close_char;
14232           *obufp = '\0';
14233         }
14234       else if (intel_syntax)
14235         {
14236           if (!active_seg_prefix)
14237             {
14238               oappend (names_seg[ds_reg - es_reg]);
14239               oappend (":");
14240             }
14241           print_operand_value (scratchbuf, 1, disp & 0xffff);
14242           oappend (scratchbuf);
14243         }
14244     }
14245   if (vex.evex && vex.b
14246       && (bytemode == x_mode
14247           || bytemode == xmmq_mode
14248           || bytemode == evex_half_bcst_xmmq_mode))
14249     {
14250       if (vex.w
14251           || bytemode == xmmq_mode
14252           || bytemode == evex_half_bcst_xmmq_mode)
14253         {
14254           switch (vex.length)
14255             {
14256             case 128:
14257               oappend ("{1to2}");
14258               break;
14259             case 256:
14260               oappend ("{1to4}");
14261               break;
14262             case 512:
14263               oappend ("{1to8}");
14264               break;
14265             default:
14266               abort ();
14267             }
14268         }
14269       else
14270         {
14271           switch (vex.length)
14272             {
14273             case 128:
14274               oappend ("{1to4}");
14275               break;
14276             case 256:
14277               oappend ("{1to8}");
14278               break;
14279             case 512:
14280               oappend ("{1to16}");
14281               break;
14282             default:
14283               abort ();
14284             }
14285         }
14286     }
14287 }
14288
14289 static void
14290 OP_E (int bytemode, int sizeflag)
14291 {
14292   /* Skip mod/rm byte.  */
14293   MODRM_CHECK;
14294   codep++;
14295
14296   if (modrm.mod == 3)
14297     OP_E_register (bytemode, sizeflag);
14298   else
14299     OP_E_memory (bytemode, sizeflag);
14300 }
14301
14302 static void
14303 OP_G (int bytemode, int sizeflag)
14304 {
14305   int add = 0;
14306   const char **names;
14307   USED_REX (REX_R);
14308   if (rex & REX_R)
14309     add += 8;
14310   switch (bytemode)
14311     {
14312     case b_mode:
14313       USED_REX (0);
14314       if (rex)
14315         oappend (names8rex[modrm.reg + add]);
14316       else
14317         oappend (names8[modrm.reg + add]);
14318       break;
14319     case w_mode:
14320       oappend (names16[modrm.reg + add]);
14321       break;
14322     case d_mode:
14323     case db_mode:
14324     case dw_mode:
14325       oappend (names32[modrm.reg + add]);
14326       break;
14327     case q_mode:
14328       oappend (names64[modrm.reg + add]);
14329       break;
14330     case bnd_mode:
14331       if (modrm.reg > 0x3)
14332         {
14333           oappend ("(bad)");
14334           return;
14335         }
14336       oappend (names_bnd[modrm.reg]);
14337       break;
14338     case v_mode:
14339     case dq_mode:
14340     case dqb_mode:
14341     case dqd_mode:
14342     case dqw_mode:
14343     case movsxd_mode:
14344       USED_REX (REX_W);
14345       if (rex & REX_W)
14346         oappend (names64[modrm.reg + add]);
14347       else
14348         {
14349           if ((sizeflag & DFLAG)
14350               || (bytemode != v_mode && bytemode != movsxd_mode))
14351             oappend (names32[modrm.reg + add]);
14352           else
14353             oappend (names16[modrm.reg + add]);
14354           used_prefixes |= (prefixes & PREFIX_DATA);
14355         }
14356       break;
14357     case va_mode:
14358       names = (address_mode == mode_64bit
14359                ? names64 : names32);
14360       if (!(prefixes & PREFIX_ADDR))
14361         {
14362           if (address_mode == mode_16bit)
14363             names = names16;
14364         }
14365       else
14366         {
14367           /* Remove "addr16/addr32".  */
14368           all_prefixes[last_addr_prefix] = 0;
14369           names = (address_mode != mode_32bit
14370                        ? names32 : names16);
14371           used_prefixes |= PREFIX_ADDR;
14372         }
14373       oappend (names[modrm.reg + add]);
14374       break;
14375     case m_mode:
14376       if (address_mode == mode_64bit)
14377         oappend (names64[modrm.reg + add]);
14378       else
14379         oappend (names32[modrm.reg + add]);
14380       break;
14381     case mask_bd_mode:
14382     case mask_mode:
14383       if ((modrm.reg + add) > 0x7)
14384         {
14385           oappend ("(bad)");
14386           return;
14387         }
14388       oappend (names_mask[modrm.reg + add]);
14389       break;
14390     default:
14391       oappend (INTERNAL_DISASSEMBLER_ERROR);
14392       break;
14393     }
14394 }
14395
14396 static bfd_vma
14397 get64 (void)
14398 {
14399   bfd_vma x;
14400 #ifdef BFD64
14401   unsigned int a;
14402   unsigned int b;
14403
14404   FETCH_DATA (the_info, codep + 8);
14405   a = *codep++ & 0xff;
14406   a |= (*codep++ & 0xff) << 8;
14407   a |= (*codep++ & 0xff) << 16;
14408   a |= (*codep++ & 0xffu) << 24;
14409   b = *codep++ & 0xff;
14410   b |= (*codep++ & 0xff) << 8;
14411   b |= (*codep++ & 0xff) << 16;
14412   b |= (*codep++ & 0xffu) << 24;
14413   x = a + ((bfd_vma) b << 32);
14414 #else
14415   abort ();
14416   x = 0;
14417 #endif
14418   return x;
14419 }
14420
14421 static bfd_signed_vma
14422 get32 (void)
14423 {
14424   bfd_signed_vma x = 0;
14425
14426   FETCH_DATA (the_info, codep + 4);
14427   x = *codep++ & (bfd_signed_vma) 0xff;
14428   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14429   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14430   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14431   return x;
14432 }
14433
14434 static bfd_signed_vma
14435 get32s (void)
14436 {
14437   bfd_signed_vma x = 0;
14438
14439   FETCH_DATA (the_info, codep + 4);
14440   x = *codep++ & (bfd_signed_vma) 0xff;
14441   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14442   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14443   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14444
14445   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14446
14447   return x;
14448 }
14449
14450 static int
14451 get16 (void)
14452 {
14453   int x = 0;
14454
14455   FETCH_DATA (the_info, codep + 2);
14456   x = *codep++ & 0xff;
14457   x |= (*codep++ & 0xff) << 8;
14458   return x;
14459 }
14460
14461 static void
14462 set_op (bfd_vma op, int riprel)
14463 {
14464   op_index[op_ad] = op_ad;
14465   if (address_mode == mode_64bit)
14466     {
14467       op_address[op_ad] = op;
14468       op_riprel[op_ad] = riprel;
14469     }
14470   else
14471     {
14472       /* Mask to get a 32-bit address.  */
14473       op_address[op_ad] = op & 0xffffffff;
14474       op_riprel[op_ad] = riprel & 0xffffffff;
14475     }
14476 }
14477
14478 static void
14479 OP_REG (int code, int sizeflag)
14480 {
14481   const char *s;
14482   int add;
14483
14484   switch (code)
14485     {
14486     case es_reg: case ss_reg: case cs_reg:
14487     case ds_reg: case fs_reg: case gs_reg:
14488       oappend (names_seg[code - es_reg]);
14489       return;
14490     }
14491
14492   USED_REX (REX_B);
14493   if (rex & REX_B)
14494     add = 8;
14495   else
14496     add = 0;
14497
14498   switch (code)
14499     {
14500     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14501     case sp_reg: case bp_reg: case si_reg: case di_reg:
14502       s = names16[code - ax_reg + add];
14503       break;
14504     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14505     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14506       USED_REX (0);
14507       if (rex)
14508         s = names8rex[code - al_reg + add];
14509       else
14510         s = names8[code - al_reg];
14511       break;
14512     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14513     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14514       if (address_mode == mode_64bit
14515           && ((sizeflag & DFLAG) || (rex & REX_W)))
14516         {
14517           s = names64[code - rAX_reg + add];
14518           break;
14519         }
14520       code += eAX_reg - rAX_reg;
14521       /* Fall through.  */
14522     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14523     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14524       USED_REX (REX_W);
14525       if (rex & REX_W)
14526         s = names64[code - eAX_reg + add];
14527       else
14528         {
14529           if (sizeflag & DFLAG)
14530             s = names32[code - eAX_reg + add];
14531           else
14532             s = names16[code - eAX_reg + add];
14533           used_prefixes |= (prefixes & PREFIX_DATA);
14534         }
14535       break;
14536     default:
14537       s = INTERNAL_DISASSEMBLER_ERROR;
14538       break;
14539     }
14540   oappend (s);
14541 }
14542
14543 static void
14544 OP_IMREG (int code, int sizeflag)
14545 {
14546   const char *s;
14547
14548   switch (code)
14549     {
14550     case indir_dx_reg:
14551       if (intel_syntax)
14552         s = "dx";
14553       else
14554         s = "(%dx)";
14555       break;
14556     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14557     case sp_reg: case bp_reg: case si_reg: case di_reg:
14558       s = names16[code - ax_reg];
14559       break;
14560     case es_reg: case ss_reg: case cs_reg:
14561     case ds_reg: case fs_reg: case gs_reg:
14562       s = names_seg[code - es_reg];
14563       break;
14564     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14565     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14566       USED_REX (0);
14567       if (rex)
14568         s = names8rex[code - al_reg];
14569       else
14570         s = names8[code - al_reg];
14571       break;
14572     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14573     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14574       USED_REX (REX_W);
14575       if (rex & REX_W)
14576         s = names64[code - eAX_reg];
14577       else
14578         {
14579           if (sizeflag & DFLAG)
14580             s = names32[code - eAX_reg];
14581           else
14582             s = names16[code - eAX_reg];
14583           used_prefixes |= (prefixes & PREFIX_DATA);
14584         }
14585       break;
14586     case z_mode_ax_reg:
14587       if ((rex & REX_W) || (sizeflag & DFLAG))
14588         s = *names32;
14589       else
14590         s = *names16;
14591       if (!(rex & REX_W))
14592         used_prefixes |= (prefixes & PREFIX_DATA);
14593       break;
14594     default:
14595       s = INTERNAL_DISASSEMBLER_ERROR;
14596       break;
14597     }
14598   oappend (s);
14599 }
14600
14601 static void
14602 OP_I (int bytemode, int sizeflag)
14603 {
14604   bfd_signed_vma op;
14605   bfd_signed_vma mask = -1;
14606
14607   switch (bytemode)
14608     {
14609     case b_mode:
14610       FETCH_DATA (the_info, codep + 1);
14611       op = *codep++;
14612       mask = 0xff;
14613       break;
14614     case v_mode:
14615       USED_REX (REX_W);
14616       if (rex & REX_W)
14617         op = get32s ();
14618       else
14619         {
14620           if (sizeflag & DFLAG)
14621             {
14622               op = get32 ();
14623               mask = 0xffffffff;
14624             }
14625           else
14626             {
14627               op = get16 ();
14628               mask = 0xfffff;
14629             }
14630           used_prefixes |= (prefixes & PREFIX_DATA);
14631         }
14632       break;
14633     case d_mode:
14634       mask = 0xffffffff;
14635       op = get32 ();
14636       break;
14637     case w_mode:
14638       mask = 0xfffff;
14639       op = get16 ();
14640       break;
14641     case const_1_mode:
14642       if (intel_syntax)
14643         oappend ("1");
14644       return;
14645     default:
14646       oappend (INTERNAL_DISASSEMBLER_ERROR);
14647       return;
14648     }
14649
14650   op &= mask;
14651   scratchbuf[0] = '$';
14652   print_operand_value (scratchbuf + 1, 1, op);
14653   oappend_maybe_intel (scratchbuf);
14654   scratchbuf[0] = '\0';
14655 }
14656
14657 static void
14658 OP_I64 (int bytemode, int sizeflag)
14659 {
14660   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14661     {
14662       OP_I (bytemode, sizeflag);
14663       return;
14664     }
14665
14666   USED_REX (REX_W);
14667
14668   scratchbuf[0] = '$';
14669   print_operand_value (scratchbuf + 1, 1, get64 ());
14670   oappend_maybe_intel (scratchbuf);
14671   scratchbuf[0] = '\0';
14672 }
14673
14674 static void
14675 OP_sI (int bytemode, int sizeflag)
14676 {
14677   bfd_signed_vma op;
14678
14679   switch (bytemode)
14680     {
14681     case b_mode:
14682     case b_T_mode:
14683       FETCH_DATA (the_info, codep + 1);
14684       op = *codep++;
14685       if ((op & 0x80) != 0)
14686         op -= 0x100;
14687       if (bytemode == b_T_mode)
14688         {
14689           if (address_mode != mode_64bit
14690               || !((sizeflag & DFLAG) || (rex & REX_W)))
14691             {
14692               /* The operand-size prefix is overridden by a REX prefix.  */
14693               if ((sizeflag & DFLAG) || (rex & REX_W))
14694                 op &= 0xffffffff;
14695               else
14696                 op &= 0xffff;
14697           }
14698         }
14699       else
14700         {
14701           if (!(rex & REX_W))
14702             {
14703               if (sizeflag & DFLAG)
14704                 op &= 0xffffffff;
14705               else
14706                 op &= 0xffff;
14707             }
14708         }
14709       break;
14710     case v_mode:
14711       /* The operand-size prefix is overridden by a REX prefix.  */
14712       if ((sizeflag & DFLAG) || (rex & REX_W))
14713         op = get32s ();
14714       else
14715         op = get16 ();
14716       break;
14717     default:
14718       oappend (INTERNAL_DISASSEMBLER_ERROR);
14719       return;
14720     }
14721
14722   scratchbuf[0] = '$';
14723   print_operand_value (scratchbuf + 1, 1, op);
14724   oappend_maybe_intel (scratchbuf);
14725 }
14726
14727 static void
14728 OP_J (int bytemode, int sizeflag)
14729 {
14730   bfd_vma disp;
14731   bfd_vma mask = -1;
14732   bfd_vma segment = 0;
14733
14734   switch (bytemode)
14735     {
14736     case b_mode:
14737       FETCH_DATA (the_info, codep + 1);
14738       disp = *codep++;
14739       if ((disp & 0x80) != 0)
14740         disp -= 0x100;
14741       break;
14742     case v_mode:
14743       if (isa64 != intel64)
14744     case dqw_mode:
14745         USED_REX (REX_W);
14746       if ((sizeflag & DFLAG)
14747           || (address_mode == mode_64bit
14748               && ((isa64 == intel64 && bytemode != dqw_mode)
14749                   || (rex & REX_W))))
14750         disp = get32s ();
14751       else
14752         {
14753           disp = get16 ();
14754           if ((disp & 0x8000) != 0)
14755             disp -= 0x10000;
14756           /* In 16bit mode, address is wrapped around at 64k within
14757              the same segment.  Otherwise, a data16 prefix on a jump
14758              instruction means that the pc is masked to 16 bits after
14759              the displacement is added!  */
14760           mask = 0xffff;
14761           if ((prefixes & PREFIX_DATA) == 0)
14762             segment = ((start_pc + (codep - start_codep))
14763                        & ~((bfd_vma) 0xffff));
14764         }
14765       if (address_mode != mode_64bit
14766           || (isa64 != intel64 && !(rex & REX_W)))
14767         used_prefixes |= (prefixes & PREFIX_DATA);
14768       break;
14769     default:
14770       oappend (INTERNAL_DISASSEMBLER_ERROR);
14771       return;
14772     }
14773   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14774   set_op (disp, 0);
14775   print_operand_value (scratchbuf, 1, disp);
14776   oappend (scratchbuf);
14777 }
14778
14779 static void
14780 OP_SEG (int bytemode, int sizeflag)
14781 {
14782   if (bytemode == w_mode)
14783     oappend (names_seg[modrm.reg]);
14784   else
14785     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14786 }
14787
14788 static void
14789 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14790 {
14791   int seg, offset;
14792
14793   if (sizeflag & DFLAG)
14794     {
14795       offset = get32 ();
14796       seg = get16 ();
14797     }
14798   else
14799     {
14800       offset = get16 ();
14801       seg = get16 ();
14802     }
14803   used_prefixes |= (prefixes & PREFIX_DATA);
14804   if (intel_syntax)
14805     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14806   else
14807     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14808   oappend (scratchbuf);
14809 }
14810
14811 static void
14812 OP_OFF (int bytemode, int sizeflag)
14813 {
14814   bfd_vma off;
14815
14816   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14817     intel_operand_size (bytemode, sizeflag);
14818   append_seg ();
14819
14820   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14821     off = get32 ();
14822   else
14823     off = get16 ();
14824
14825   if (intel_syntax)
14826     {
14827       if (!active_seg_prefix)
14828         {
14829           oappend (names_seg[ds_reg - es_reg]);
14830           oappend (":");
14831         }
14832     }
14833   print_operand_value (scratchbuf, 1, off);
14834   oappend (scratchbuf);
14835 }
14836
14837 static void
14838 OP_OFF64 (int bytemode, int sizeflag)
14839 {
14840   bfd_vma off;
14841
14842   if (address_mode != mode_64bit
14843       || (prefixes & PREFIX_ADDR))
14844     {
14845       OP_OFF (bytemode, sizeflag);
14846       return;
14847     }
14848
14849   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14850     intel_operand_size (bytemode, sizeflag);
14851   append_seg ();
14852
14853   off = get64 ();
14854
14855   if (intel_syntax)
14856     {
14857       if (!active_seg_prefix)
14858         {
14859           oappend (names_seg[ds_reg - es_reg]);
14860           oappend (":");
14861         }
14862     }
14863   print_operand_value (scratchbuf, 1, off);
14864   oappend (scratchbuf);
14865 }
14866
14867 static void
14868 ptr_reg (int code, int sizeflag)
14869 {
14870   const char *s;
14871
14872   *obufp++ = open_char;
14873   used_prefixes |= (prefixes & PREFIX_ADDR);
14874   if (address_mode == mode_64bit)
14875     {
14876       if (!(sizeflag & AFLAG))
14877         s = names32[code - eAX_reg];
14878       else
14879         s = names64[code - eAX_reg];
14880     }
14881   else if (sizeflag & AFLAG)
14882     s = names32[code - eAX_reg];
14883   else
14884     s = names16[code - eAX_reg];
14885   oappend (s);
14886   *obufp++ = close_char;
14887   *obufp = 0;
14888 }
14889
14890 static void
14891 OP_ESreg (int code, int sizeflag)
14892 {
14893   if (intel_syntax)
14894     {
14895       switch (codep[-1])
14896         {
14897         case 0x6d:      /* insw/insl */
14898           intel_operand_size (z_mode, sizeflag);
14899           break;
14900         case 0xa5:      /* movsw/movsl/movsq */
14901         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14902         case 0xab:      /* stosw/stosl */
14903         case 0xaf:      /* scasw/scasl */
14904           intel_operand_size (v_mode, sizeflag);
14905           break;
14906         default:
14907           intel_operand_size (b_mode, sizeflag);
14908         }
14909     }
14910   oappend_maybe_intel ("%es:");
14911   ptr_reg (code, sizeflag);
14912 }
14913
14914 static void
14915 OP_DSreg (int code, int sizeflag)
14916 {
14917   if (intel_syntax)
14918     {
14919       switch (codep[-1])
14920         {
14921         case 0x6f:      /* outsw/outsl */
14922           intel_operand_size (z_mode, sizeflag);
14923           break;
14924         case 0xa5:      /* movsw/movsl/movsq */
14925         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14926         case 0xad:      /* lodsw/lodsl/lodsq */
14927           intel_operand_size (v_mode, sizeflag);
14928           break;
14929         default:
14930           intel_operand_size (b_mode, sizeflag);
14931         }
14932     }
14933   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14934      default segment register DS is printed.  */
14935   if (!active_seg_prefix)
14936     active_seg_prefix = PREFIX_DS;
14937   append_seg ();
14938   ptr_reg (code, sizeflag);
14939 }
14940
14941 static void
14942 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14943 {
14944   int add;
14945   if (rex & REX_R)
14946     {
14947       USED_REX (REX_R);
14948       add = 8;
14949     }
14950   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14951     {
14952       all_prefixes[last_lock_prefix] = 0;
14953       used_prefixes |= PREFIX_LOCK;
14954       add = 8;
14955     }
14956   else
14957     add = 0;
14958   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14959   oappend_maybe_intel (scratchbuf);
14960 }
14961
14962 static void
14963 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14964 {
14965   int add;
14966   USED_REX (REX_R);
14967   if (rex & REX_R)
14968     add = 8;
14969   else
14970     add = 0;
14971   if (intel_syntax)
14972     sprintf (scratchbuf, "db%d", modrm.reg + add);
14973   else
14974     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14975   oappend (scratchbuf);
14976 }
14977
14978 static void
14979 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14980 {
14981   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14982   oappend_maybe_intel (scratchbuf);
14983 }
14984
14985 static void
14986 OP_R (int bytemode, int sizeflag)
14987 {
14988   /* Skip mod/rm byte.  */
14989   MODRM_CHECK;
14990   codep++;
14991   OP_E_register (bytemode, sizeflag);
14992 }
14993
14994 static void
14995 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14996 {
14997   int reg = modrm.reg;
14998   const char **names;
14999
15000   used_prefixes |= (prefixes & PREFIX_DATA);
15001   if (prefixes & PREFIX_DATA)
15002     {
15003       names = names_xmm;
15004       USED_REX (REX_R);
15005       if (rex & REX_R)
15006         reg += 8;
15007     }
15008   else
15009     names = names_mm;
15010   oappend (names[reg]);
15011 }
15012
15013 static void
15014 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15015 {
15016   int reg = modrm.reg;
15017   const char **names;
15018
15019   USED_REX (REX_R);
15020   if (rex & REX_R)
15021     reg += 8;
15022   if (vex.evex)
15023     {
15024       if (!vex.r)
15025         reg += 16;
15026     }
15027
15028   if (need_vex
15029       && bytemode != xmm_mode
15030       && bytemode != xmmq_mode
15031       && bytemode != evex_half_bcst_xmmq_mode
15032       && bytemode != ymm_mode
15033       && bytemode != scalar_mode)
15034     {
15035       switch (vex.length)
15036         {
15037         case 128:
15038           names = names_xmm;
15039           break;
15040         case 256:
15041           if (vex.w
15042               || (bytemode != vex_vsib_q_w_dq_mode
15043                   && bytemode != vex_vsib_q_w_d_mode))
15044             names = names_ymm;
15045           else
15046             names = names_xmm;
15047           break;
15048         case 512:
15049           names = names_zmm;
15050           break;
15051         default:
15052           abort ();
15053         }
15054     }
15055   else if (bytemode == xmmq_mode
15056            || bytemode == evex_half_bcst_xmmq_mode)
15057     {
15058       switch (vex.length)
15059         {
15060         case 128:
15061         case 256:
15062           names = names_xmm;
15063           break;
15064         case 512:
15065           names = names_ymm;
15066           break;
15067         default:
15068           abort ();
15069         }
15070     }
15071   else if (bytemode == ymm_mode)
15072     names = names_ymm;
15073   else
15074     names = names_xmm;
15075   oappend (names[reg]);
15076 }
15077
15078 static void
15079 OP_EM (int bytemode, int sizeflag)
15080 {
15081   int reg;
15082   const char **names;
15083
15084   if (modrm.mod != 3)
15085     {
15086       if (intel_syntax
15087           && (bytemode == v_mode || bytemode == v_swap_mode))
15088         {
15089           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15090           used_prefixes |= (prefixes & PREFIX_DATA);
15091         }
15092       OP_E (bytemode, sizeflag);
15093       return;
15094     }
15095
15096   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15097     swap_operand ();
15098
15099   /* Skip mod/rm byte.  */
15100   MODRM_CHECK;
15101   codep++;
15102   used_prefixes |= (prefixes & PREFIX_DATA);
15103   reg = modrm.rm;
15104   if (prefixes & PREFIX_DATA)
15105     {
15106       names = names_xmm;
15107       USED_REX (REX_B);
15108       if (rex & REX_B)
15109         reg += 8;
15110     }
15111   else
15112     names = names_mm;
15113   oappend (names[reg]);
15114 }
15115
15116 /* cvt* are the only instructions in sse2 which have
15117    both SSE and MMX operands and also have 0x66 prefix
15118    in their opcode. 0x66 was originally used to differentiate
15119    between SSE and MMX instruction(operands). So we have to handle the
15120    cvt* separately using OP_EMC and OP_MXC */
15121 static void
15122 OP_EMC (int bytemode, int sizeflag)
15123 {
15124   if (modrm.mod != 3)
15125     {
15126       if (intel_syntax && bytemode == v_mode)
15127         {
15128           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15129           used_prefixes |= (prefixes & PREFIX_DATA);
15130         }
15131       OP_E (bytemode, sizeflag);
15132       return;
15133     }
15134
15135   /* Skip mod/rm byte.  */
15136   MODRM_CHECK;
15137   codep++;
15138   used_prefixes |= (prefixes & PREFIX_DATA);
15139   oappend (names_mm[modrm.rm]);
15140 }
15141
15142 static void
15143 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15144 {
15145   used_prefixes |= (prefixes & PREFIX_DATA);
15146   oappend (names_mm[modrm.reg]);
15147 }
15148
15149 static void
15150 OP_EX (int bytemode, int sizeflag)
15151 {
15152   int reg;
15153   const char **names;
15154
15155   /* Skip mod/rm byte.  */
15156   MODRM_CHECK;
15157   codep++;
15158
15159   if (modrm.mod != 3)
15160     {
15161       OP_E_memory (bytemode, sizeflag);
15162       return;
15163     }
15164
15165   reg = modrm.rm;
15166   USED_REX (REX_B);
15167   if (rex & REX_B)
15168     reg += 8;
15169   if (vex.evex)
15170     {
15171       USED_REX (REX_X);
15172       if ((rex & REX_X))
15173         reg += 16;
15174     }
15175
15176   if ((sizeflag & SUFFIX_ALWAYS)
15177       && (bytemode == x_swap_mode
15178           || bytemode == d_swap_mode
15179           || bytemode == d_scalar_swap_mode
15180           || bytemode == q_swap_mode
15181           || bytemode == q_scalar_swap_mode))
15182     swap_operand ();
15183
15184   if (need_vex
15185       && bytemode != xmm_mode
15186       && bytemode != xmmdw_mode
15187       && bytemode != xmmqd_mode
15188       && bytemode != xmm_mb_mode
15189       && bytemode != xmm_mw_mode
15190       && bytemode != xmm_md_mode
15191       && bytemode != xmm_mq_mode
15192       && bytemode != xmmq_mode
15193       && bytemode != evex_half_bcst_xmmq_mode
15194       && bytemode != ymm_mode
15195       && bytemode != d_scalar_swap_mode
15196       && bytemode != q_scalar_swap_mode
15197       && bytemode != vex_scalar_w_dq_mode)
15198     {
15199       switch (vex.length)
15200         {
15201         case 128:
15202           names = names_xmm;
15203           break;
15204         case 256:
15205           names = names_ymm;
15206           break;
15207         case 512:
15208           names = names_zmm;
15209           break;
15210         default:
15211           abort ();
15212         }
15213     }
15214   else if (bytemode == xmmq_mode
15215            || bytemode == evex_half_bcst_xmmq_mode)
15216     {
15217       switch (vex.length)
15218         {
15219         case 128:
15220         case 256:
15221           names = names_xmm;
15222           break;
15223         case 512:
15224           names = names_ymm;
15225           break;
15226         default:
15227           abort ();
15228         }
15229     }
15230   else if (bytemode == ymm_mode)
15231     names = names_ymm;
15232   else
15233     names = names_xmm;
15234   oappend (names[reg]);
15235 }
15236
15237 static void
15238 OP_MS (int bytemode, int sizeflag)
15239 {
15240   if (modrm.mod == 3)
15241     OP_EM (bytemode, sizeflag);
15242   else
15243     BadOp ();
15244 }
15245
15246 static void
15247 OP_XS (int bytemode, int sizeflag)
15248 {
15249   if (modrm.mod == 3)
15250     OP_EX (bytemode, sizeflag);
15251   else
15252     BadOp ();
15253 }
15254
15255 static void
15256 OP_M (int bytemode, int sizeflag)
15257 {
15258   if (modrm.mod == 3)
15259     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15260     BadOp ();
15261   else
15262     OP_E (bytemode, sizeflag);
15263 }
15264
15265 static void
15266 OP_0f07 (int bytemode, int sizeflag)
15267 {
15268   if (modrm.mod != 3 || modrm.rm != 0)
15269     BadOp ();
15270   else
15271     OP_E (bytemode, sizeflag);
15272 }
15273
15274 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15275    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15276
15277 static void
15278 NOP_Fixup1 (int bytemode, int sizeflag)
15279 {
15280   if ((prefixes & PREFIX_DATA) != 0
15281       || (rex != 0
15282           && rex != 0x48
15283           && address_mode == mode_64bit))
15284     OP_REG (bytemode, sizeflag);
15285   else
15286     strcpy (obuf, "nop");
15287 }
15288
15289 static void
15290 NOP_Fixup2 (int bytemode, int sizeflag)
15291 {
15292   if ((prefixes & PREFIX_DATA) != 0
15293       || (rex != 0
15294           && rex != 0x48
15295           && address_mode == mode_64bit))
15296     OP_IMREG (bytemode, sizeflag);
15297 }
15298
15299 static const char *const Suffix3DNow[] = {
15300 /* 00 */        NULL,           NULL,           NULL,           NULL,
15301 /* 04 */        NULL,           NULL,           NULL,           NULL,
15302 /* 08 */        NULL,           NULL,           NULL,           NULL,
15303 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15304 /* 10 */        NULL,           NULL,           NULL,           NULL,
15305 /* 14 */        NULL,           NULL,           NULL,           NULL,
15306 /* 18 */        NULL,           NULL,           NULL,           NULL,
15307 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15308 /* 20 */        NULL,           NULL,           NULL,           NULL,
15309 /* 24 */        NULL,           NULL,           NULL,           NULL,
15310 /* 28 */        NULL,           NULL,           NULL,           NULL,
15311 /* 2C */        NULL,           NULL,           NULL,           NULL,
15312 /* 30 */        NULL,           NULL,           NULL,           NULL,
15313 /* 34 */        NULL,           NULL,           NULL,           NULL,
15314 /* 38 */        NULL,           NULL,           NULL,           NULL,
15315 /* 3C */        NULL,           NULL,           NULL,           NULL,
15316 /* 40 */        NULL,           NULL,           NULL,           NULL,
15317 /* 44 */        NULL,           NULL,           NULL,           NULL,
15318 /* 48 */        NULL,           NULL,           NULL,           NULL,
15319 /* 4C */        NULL,           NULL,           NULL,           NULL,
15320 /* 50 */        NULL,           NULL,           NULL,           NULL,
15321 /* 54 */        NULL,           NULL,           NULL,           NULL,
15322 /* 58 */        NULL,           NULL,           NULL,           NULL,
15323 /* 5C */        NULL,           NULL,           NULL,           NULL,
15324 /* 60 */        NULL,           NULL,           NULL,           NULL,
15325 /* 64 */        NULL,           NULL,           NULL,           NULL,
15326 /* 68 */        NULL,           NULL,           NULL,           NULL,
15327 /* 6C */        NULL,           NULL,           NULL,           NULL,
15328 /* 70 */        NULL,           NULL,           NULL,           NULL,
15329 /* 74 */        NULL,           NULL,           NULL,           NULL,
15330 /* 78 */        NULL,           NULL,           NULL,           NULL,
15331 /* 7C */        NULL,           NULL,           NULL,           NULL,
15332 /* 80 */        NULL,           NULL,           NULL,           NULL,
15333 /* 84 */        NULL,           NULL,           NULL,           NULL,
15334 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15335 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15336 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15337 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15338 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15339 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15340 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15341 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15342 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15343 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15344 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15345 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15346 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15347 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15348 /* C0 */        NULL,           NULL,           NULL,           NULL,
15349 /* C4 */        NULL,           NULL,           NULL,           NULL,
15350 /* C8 */        NULL,           NULL,           NULL,           NULL,
15351 /* CC */        NULL,           NULL,           NULL,           NULL,
15352 /* D0 */        NULL,           NULL,           NULL,           NULL,
15353 /* D4 */        NULL,           NULL,           NULL,           NULL,
15354 /* D8 */        NULL,           NULL,           NULL,           NULL,
15355 /* DC */        NULL,           NULL,           NULL,           NULL,
15356 /* E0 */        NULL,           NULL,           NULL,           NULL,
15357 /* E4 */        NULL,           NULL,           NULL,           NULL,
15358 /* E8 */        NULL,           NULL,           NULL,           NULL,
15359 /* EC */        NULL,           NULL,           NULL,           NULL,
15360 /* F0 */        NULL,           NULL,           NULL,           NULL,
15361 /* F4 */        NULL,           NULL,           NULL,           NULL,
15362 /* F8 */        NULL,           NULL,           NULL,           NULL,
15363 /* FC */        NULL,           NULL,           NULL,           NULL,
15364 };
15365
15366 static void
15367 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15368 {
15369   const char *mnemonic;
15370
15371   FETCH_DATA (the_info, codep + 1);
15372   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15373      place where an 8-bit immediate would normally go.  ie. the last
15374      byte of the instruction.  */
15375   obufp = mnemonicendp;
15376   mnemonic = Suffix3DNow[*codep++ & 0xff];
15377   if (mnemonic)
15378     oappend (mnemonic);
15379   else
15380     {
15381       /* Since a variable sized modrm/sib chunk is between the start
15382          of the opcode (0x0f0f) and the opcode suffix, we need to do
15383          all the modrm processing first, and don't know until now that
15384          we have a bad opcode.  This necessitates some cleaning up.  */
15385       op_out[0][0] = '\0';
15386       op_out[1][0] = '\0';
15387       BadOp ();
15388     }
15389   mnemonicendp = obufp;
15390 }
15391
15392 static struct op simd_cmp_op[] =
15393 {
15394   { STRING_COMMA_LEN ("eq") },
15395   { STRING_COMMA_LEN ("lt") },
15396   { STRING_COMMA_LEN ("le") },
15397   { STRING_COMMA_LEN ("unord") },
15398   { STRING_COMMA_LEN ("neq") },
15399   { STRING_COMMA_LEN ("nlt") },
15400   { STRING_COMMA_LEN ("nle") },
15401   { STRING_COMMA_LEN ("ord") }
15402 };
15403
15404 static void
15405 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15406 {
15407   unsigned int cmp_type;
15408
15409   FETCH_DATA (the_info, codep + 1);
15410   cmp_type = *codep++ & 0xff;
15411   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15412     {
15413       char suffix [3];
15414       char *p = mnemonicendp - 2;
15415       suffix[0] = p[0];
15416       suffix[1] = p[1];
15417       suffix[2] = '\0';
15418       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15419       mnemonicendp += simd_cmp_op[cmp_type].len;
15420     }
15421   else
15422     {
15423       /* We have a reserved extension byte.  Output it directly.  */
15424       scratchbuf[0] = '$';
15425       print_operand_value (scratchbuf + 1, 1, cmp_type);
15426       oappend_maybe_intel (scratchbuf);
15427       scratchbuf[0] = '\0';
15428     }
15429 }
15430
15431 static void
15432 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15433 {
15434   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15435   if (!intel_syntax)
15436     {
15437       strcpy (op_out[0], names32[0]);
15438       strcpy (op_out[1], names32[1]);
15439       if (bytemode == eBX_reg)
15440         strcpy (op_out[2], names32[3]);
15441       two_source_ops = 1;
15442     }
15443   /* Skip mod/rm byte.  */
15444   MODRM_CHECK;
15445   codep++;
15446 }
15447
15448 static void
15449 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15450             int sizeflag ATTRIBUTE_UNUSED)
15451 {
15452   /* monitor %{e,r,}ax,%ecx,%edx"  */
15453   if (!intel_syntax)
15454     {
15455       const char **names = (address_mode == mode_64bit
15456                             ? names64 : names32);
15457
15458       if (prefixes & PREFIX_ADDR)
15459         {
15460           /* Remove "addr16/addr32".  */
15461           all_prefixes[last_addr_prefix] = 0;
15462           names = (address_mode != mode_32bit
15463                    ? names32 : names16);
15464           used_prefixes |= PREFIX_ADDR;
15465         }
15466       else if (address_mode == mode_16bit)
15467         names = names16;
15468       strcpy (op_out[0], names[0]);
15469       strcpy (op_out[1], names32[1]);
15470       strcpy (op_out[2], names32[2]);
15471       two_source_ops = 1;
15472     }
15473   /* Skip mod/rm byte.  */
15474   MODRM_CHECK;
15475   codep++;
15476 }
15477
15478 static void
15479 BadOp (void)
15480 {
15481   /* Throw away prefixes and 1st. opcode byte.  */
15482   codep = insn_codep + 1;
15483   oappend ("(bad)");
15484 }
15485
15486 static void
15487 REP_Fixup (int bytemode, int sizeflag)
15488 {
15489   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15490      lods and stos.  */
15491   if (prefixes & PREFIX_REPZ)
15492     all_prefixes[last_repz_prefix] = REP_PREFIX;
15493
15494   switch (bytemode)
15495     {
15496     case al_reg:
15497     case eAX_reg:
15498     case indir_dx_reg:
15499       OP_IMREG (bytemode, sizeflag);
15500       break;
15501     case eDI_reg:
15502       OP_ESreg (bytemode, sizeflag);
15503       break;
15504     case eSI_reg:
15505       OP_DSreg (bytemode, sizeflag);
15506       break;
15507     default:
15508       abort ();
15509       break;
15510     }
15511 }
15512
15513 static void
15514 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15515 {
15516   if ( isa64 != amd64 )
15517     return;
15518
15519   obufp = obuf;
15520   BadOp ();
15521   mnemonicendp = obufp;
15522   ++codep;
15523 }
15524
15525 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15526    "bnd".  */
15527
15528 static void
15529 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15530 {
15531   if (prefixes & PREFIX_REPNZ)
15532     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15533 }
15534
15535 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15536    "notrack".  */
15537
15538 static void
15539 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15540                int sizeflag ATTRIBUTE_UNUSED)
15541 {
15542   if (active_seg_prefix == PREFIX_DS
15543       && (address_mode != mode_64bit || last_data_prefix < 0))
15544     {
15545       /* NOTRACK prefix is only valid on indirect branch instructions.
15546          NB: DATA prefix is unsupported for Intel64.  */
15547       active_seg_prefix = 0;
15548       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15549     }
15550 }
15551
15552 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15553    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15554  */
15555
15556 static void
15557 HLE_Fixup1 (int bytemode, int sizeflag)
15558 {
15559   if (modrm.mod != 3
15560       && (prefixes & PREFIX_LOCK) != 0)
15561     {
15562       if (prefixes & PREFIX_REPZ)
15563         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15564       if (prefixes & PREFIX_REPNZ)
15565         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15566     }
15567
15568   OP_E (bytemode, sizeflag);
15569 }
15570
15571 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15572    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15573  */
15574
15575 static void
15576 HLE_Fixup2 (int bytemode, int sizeflag)
15577 {
15578   if (modrm.mod != 3)
15579     {
15580       if (prefixes & PREFIX_REPZ)
15581         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15582       if (prefixes & PREFIX_REPNZ)
15583         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15584     }
15585
15586   OP_E (bytemode, sizeflag);
15587 }
15588
15589 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15590    "xrelease" for memory operand.  No check for LOCK prefix.   */
15591
15592 static void
15593 HLE_Fixup3 (int bytemode, int sizeflag)
15594 {
15595   if (modrm.mod != 3
15596       && last_repz_prefix > last_repnz_prefix
15597       && (prefixes & PREFIX_REPZ) != 0)
15598     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15599
15600   OP_E (bytemode, sizeflag);
15601 }
15602
15603 static void
15604 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15605 {
15606   USED_REX (REX_W);
15607   if (rex & REX_W)
15608     {
15609       /* Change cmpxchg8b to cmpxchg16b.  */
15610       char *p = mnemonicendp - 2;
15611       mnemonicendp = stpcpy (p, "16b");
15612       bytemode = o_mode;
15613     }
15614   else if ((prefixes & PREFIX_LOCK) != 0)
15615     {
15616       if (prefixes & PREFIX_REPZ)
15617         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15618       if (prefixes & PREFIX_REPNZ)
15619         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15620     }
15621
15622   OP_M (bytemode, sizeflag);
15623 }
15624
15625 static void
15626 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15627 {
15628   const char **names;
15629
15630   if (need_vex)
15631     {
15632       switch (vex.length)
15633         {
15634         case 128:
15635           names = names_xmm;
15636           break;
15637         case 256:
15638           names = names_ymm;
15639           break;
15640         default:
15641           abort ();
15642         }
15643     }
15644   else
15645     names = names_xmm;
15646   oappend (names[reg]);
15647 }
15648
15649 static void
15650 CRC32_Fixup (int bytemode, int sizeflag)
15651 {
15652   /* Add proper suffix to "crc32".  */
15653   char *p = mnemonicendp;
15654
15655   switch (bytemode)
15656     {
15657     case b_mode:
15658       if (intel_syntax)
15659         goto skip;
15660
15661       *p++ = 'b';
15662       break;
15663     case v_mode:
15664       if (intel_syntax)
15665         goto skip;
15666
15667       USED_REX (REX_W);
15668       if (rex & REX_W)
15669         *p++ = 'q';
15670       else
15671         {
15672           if (sizeflag & DFLAG)
15673             *p++ = 'l';
15674           else
15675             *p++ = 'w';
15676           used_prefixes |= (prefixes & PREFIX_DATA);
15677         }
15678       break;
15679     default:
15680       oappend (INTERNAL_DISASSEMBLER_ERROR);
15681       break;
15682     }
15683   mnemonicendp = p;
15684   *p = '\0';
15685
15686  skip:
15687   if (modrm.mod == 3)
15688     {
15689       int add;
15690
15691       /* Skip mod/rm byte.  */
15692       MODRM_CHECK;
15693       codep++;
15694
15695       USED_REX (REX_B);
15696       add = (rex & REX_B) ? 8 : 0;
15697       if (bytemode == b_mode)
15698         {
15699           USED_REX (0);
15700           if (rex)
15701             oappend (names8rex[modrm.rm + add]);
15702           else
15703             oappend (names8[modrm.rm + add]);
15704         }
15705       else
15706         {
15707           USED_REX (REX_W);
15708           if (rex & REX_W)
15709             oappend (names64[modrm.rm + add]);
15710           else if ((prefixes & PREFIX_DATA))
15711             oappend (names16[modrm.rm + add]);
15712           else
15713             oappend (names32[modrm.rm + add]);
15714         }
15715     }
15716   else
15717     OP_E (bytemode, sizeflag);
15718 }
15719
15720 static void
15721 FXSAVE_Fixup (int bytemode, int sizeflag)
15722 {
15723   /* Add proper suffix to "fxsave" and "fxrstor".  */
15724   USED_REX (REX_W);
15725   if (rex & REX_W)
15726     {
15727       char *p = mnemonicendp;
15728       *p++ = '6';
15729       *p++ = '4';
15730       *p = '\0';
15731       mnemonicendp = p;
15732     }
15733   OP_M (bytemode, sizeflag);
15734 }
15735
15736 static void
15737 PCMPESTR_Fixup (int bytemode, int sizeflag)
15738 {
15739   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15740   if (!intel_syntax)
15741     {
15742       char *p = mnemonicendp;
15743
15744       USED_REX (REX_W);
15745       if (rex & REX_W)
15746         *p++ = 'q';
15747       else if (sizeflag & SUFFIX_ALWAYS)
15748         *p++ = 'l';
15749
15750       *p = '\0';
15751       mnemonicendp = p;
15752     }
15753
15754   OP_EX (bytemode, sizeflag);
15755 }
15756
15757 /* Display the destination register operand for instructions with
15758    VEX. */
15759
15760 static void
15761 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15762 {
15763   int reg;
15764   const char **names;
15765
15766   if (!need_vex)
15767     abort ();
15768
15769   if (!need_vex_reg)
15770     return;
15771
15772   reg = vex.register_specifier;
15773   vex.register_specifier = 0;
15774   if (address_mode != mode_64bit)
15775     reg &= 7;
15776   else if (vex.evex && !vex.v)
15777     reg += 16;
15778
15779   if (bytemode == vex_scalar_mode)
15780     {
15781       oappend (names_xmm[reg]);
15782       return;
15783     }
15784
15785   switch (vex.length)
15786     {
15787     case 128:
15788       switch (bytemode)
15789         {
15790         case vex_mode:
15791         case vex128_mode:
15792         case vex_vsib_q_w_dq_mode:
15793         case vex_vsib_q_w_d_mode:
15794           names = names_xmm;
15795           break;
15796         case dq_mode:
15797           if (rex & REX_W)
15798             names = names64;
15799           else
15800             names = names32;
15801           break;
15802         case mask_bd_mode:
15803         case mask_mode:
15804           if (reg > 0x7)
15805             {
15806               oappend ("(bad)");
15807               return;
15808             }
15809           names = names_mask;
15810           break;
15811         default:
15812           abort ();
15813           return;
15814         }
15815       break;
15816     case 256:
15817       switch (bytemode)
15818         {
15819         case vex_mode:
15820         case vex256_mode:
15821           names = names_ymm;
15822           break;
15823         case vex_vsib_q_w_dq_mode:
15824         case vex_vsib_q_w_d_mode:
15825           names = vex.w ? names_ymm : names_xmm;
15826           break;
15827         case mask_bd_mode:
15828         case mask_mode:
15829           if (reg > 0x7)
15830             {
15831               oappend ("(bad)");
15832               return;
15833             }
15834           names = names_mask;
15835           break;
15836         default:
15837           /* See PR binutils/20893 for a reproducer.  */
15838           oappend ("(bad)");
15839           return;
15840         }
15841       break;
15842     case 512:
15843       names = names_zmm;
15844       break;
15845     default:
15846       abort ();
15847       break;
15848     }
15849   oappend (names[reg]);
15850 }
15851
15852 static void
15853 OP_Vex_2src (int bytemode, int sizeflag)
15854 {
15855   if (modrm.mod == 3)
15856     {
15857       int reg = modrm.rm;
15858       USED_REX (REX_B);
15859       if (rex & REX_B)
15860         reg += 8;
15861       oappend (names_xmm[reg]);
15862     }
15863   else
15864     {
15865       if (intel_syntax
15866           && (bytemode == v_mode || bytemode == v_swap_mode))
15867         {
15868           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15869           used_prefixes |= (prefixes & PREFIX_DATA);
15870         }
15871       OP_E (bytemode, sizeflag);
15872     }
15873 }
15874
15875 static void
15876 OP_Vex_2src_1 (int bytemode, int sizeflag)
15877 {
15878   if (modrm.mod == 3)
15879     {
15880       /* Skip mod/rm byte.   */
15881       MODRM_CHECK;
15882       codep++;
15883     }
15884
15885   if (vex.w)
15886     {
15887       unsigned int reg = vex.register_specifier;
15888       vex.register_specifier = 0;
15889
15890       if (address_mode != mode_64bit)
15891         reg &= 7;
15892       oappend (names_xmm[reg]);
15893     }
15894   else
15895     OP_Vex_2src (bytemode, sizeflag);
15896 }
15897
15898 static void
15899 OP_Vex_2src_2 (int bytemode, int sizeflag)
15900 {
15901   if (vex.w)
15902     OP_Vex_2src (bytemode, sizeflag);
15903   else
15904     {
15905       unsigned int reg = vex.register_specifier;
15906       vex.register_specifier = 0;
15907
15908       if (address_mode != mode_64bit)
15909         reg &= 7;
15910       oappend (names_xmm[reg]);
15911     }
15912 }
15913
15914 static void
15915 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15916 {
15917   int reg;
15918   const char **names;
15919
15920   FETCH_DATA (the_info, codep + 1);
15921   reg = *codep++;
15922
15923   if (bytemode != x_mode)
15924     abort ();
15925
15926   reg >>= 4;
15927   if (address_mode != mode_64bit)
15928     reg &= 7;
15929
15930   switch (vex.length)
15931     {
15932     case 128:
15933       names = names_xmm;
15934       break;
15935     case 256:
15936       names = names_ymm;
15937       break;
15938     default:
15939       abort ();
15940     }
15941   oappend (names[reg]);
15942
15943   if (vex.w)
15944     {
15945       /* Swap 3rd and 4th operands.  */
15946       strcpy (scratchbuf, op_out[3]);
15947       strcpy (op_out[3], op_out[2]);
15948       strcpy (op_out[2], scratchbuf);
15949     }
15950 }
15951
15952 static void
15953 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
15954           int sizeflag ATTRIBUTE_UNUSED)
15955 {
15956   scratchbuf[0] = '$';
15957   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
15958   oappend_maybe_intel (scratchbuf);
15959 }
15960
15961 static void
15962 OP_EX_Vex (int bytemode, int sizeflag)
15963 {
15964   if (modrm.mod != 3)
15965     need_vex_reg = 0;
15966   OP_EX (bytemode, sizeflag);
15967 }
15968
15969 static void
15970 OP_XMM_Vex (int bytemode, int sizeflag)
15971 {
15972   if (modrm.mod != 3)
15973     need_vex_reg = 0;
15974   OP_XMM (bytemode, sizeflag);
15975 }
15976
15977 static struct op vex_cmp_op[] =
15978 {
15979   { STRING_COMMA_LEN ("eq") },
15980   { STRING_COMMA_LEN ("lt") },
15981   { STRING_COMMA_LEN ("le") },
15982   { STRING_COMMA_LEN ("unord") },
15983   { STRING_COMMA_LEN ("neq") },
15984   { STRING_COMMA_LEN ("nlt") },
15985   { STRING_COMMA_LEN ("nle") },
15986   { STRING_COMMA_LEN ("ord") },
15987   { STRING_COMMA_LEN ("eq_uq") },
15988   { STRING_COMMA_LEN ("nge") },
15989   { STRING_COMMA_LEN ("ngt") },
15990   { STRING_COMMA_LEN ("false") },
15991   { STRING_COMMA_LEN ("neq_oq") },
15992   { STRING_COMMA_LEN ("ge") },
15993   { STRING_COMMA_LEN ("gt") },
15994   { STRING_COMMA_LEN ("true") },
15995   { STRING_COMMA_LEN ("eq_os") },
15996   { STRING_COMMA_LEN ("lt_oq") },
15997   { STRING_COMMA_LEN ("le_oq") },
15998   { STRING_COMMA_LEN ("unord_s") },
15999   { STRING_COMMA_LEN ("neq_us") },
16000   { STRING_COMMA_LEN ("nlt_uq") },
16001   { STRING_COMMA_LEN ("nle_uq") },
16002   { STRING_COMMA_LEN ("ord_s") },
16003   { STRING_COMMA_LEN ("eq_us") },
16004   { STRING_COMMA_LEN ("nge_uq") },
16005   { STRING_COMMA_LEN ("ngt_uq") },
16006   { STRING_COMMA_LEN ("false_os") },
16007   { STRING_COMMA_LEN ("neq_os") },
16008   { STRING_COMMA_LEN ("ge_oq") },
16009   { STRING_COMMA_LEN ("gt_oq") },
16010   { STRING_COMMA_LEN ("true_us") },
16011 };
16012
16013 static void
16014 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16015 {
16016   unsigned int cmp_type;
16017
16018   FETCH_DATA (the_info, codep + 1);
16019   cmp_type = *codep++ & 0xff;
16020   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16021     {
16022       char suffix [3];
16023       char *p = mnemonicendp - 2;
16024       suffix[0] = p[0];
16025       suffix[1] = p[1];
16026       suffix[2] = '\0';
16027       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16028       mnemonicendp += vex_cmp_op[cmp_type].len;
16029     }
16030   else
16031     {
16032       /* We have a reserved extension byte.  Output it directly.  */
16033       scratchbuf[0] = '$';
16034       print_operand_value (scratchbuf + 1, 1, cmp_type);
16035       oappend_maybe_intel (scratchbuf);
16036       scratchbuf[0] = '\0';
16037     }
16038 }
16039
16040 static void
16041 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16042              int sizeflag ATTRIBUTE_UNUSED)
16043 {
16044   unsigned int cmp_type;
16045
16046   if (!vex.evex)
16047     abort ();
16048
16049   FETCH_DATA (the_info, codep + 1);
16050   cmp_type = *codep++ & 0xff;
16051   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16052      If it's the case, print suffix, otherwise - print the immediate.  */
16053   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16054       && cmp_type != 3
16055       && cmp_type != 7)
16056     {
16057       char suffix [3];
16058       char *p = mnemonicendp - 2;
16059
16060       /* vpcmp* can have both one- and two-lettered suffix.  */
16061       if (p[0] == 'p')
16062         {
16063           p++;
16064           suffix[0] = p[0];
16065           suffix[1] = '\0';
16066         }
16067       else
16068         {
16069           suffix[0] = p[0];
16070           suffix[1] = p[1];
16071           suffix[2] = '\0';
16072         }
16073
16074       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16075       mnemonicendp += simd_cmp_op[cmp_type].len;
16076     }
16077   else
16078     {
16079       /* We have a reserved extension byte.  Output it directly.  */
16080       scratchbuf[0] = '$';
16081       print_operand_value (scratchbuf + 1, 1, cmp_type);
16082       oappend_maybe_intel (scratchbuf);
16083       scratchbuf[0] = '\0';
16084     }
16085 }
16086
16087 static const struct op xop_cmp_op[] =
16088 {
16089   { STRING_COMMA_LEN ("lt") },
16090   { STRING_COMMA_LEN ("le") },
16091   { STRING_COMMA_LEN ("gt") },
16092   { STRING_COMMA_LEN ("ge") },
16093   { STRING_COMMA_LEN ("eq") },
16094   { STRING_COMMA_LEN ("neq") },
16095   { STRING_COMMA_LEN ("false") },
16096   { STRING_COMMA_LEN ("true") }
16097 };
16098
16099 static void
16100 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16101              int sizeflag ATTRIBUTE_UNUSED)
16102 {
16103   unsigned int cmp_type;
16104
16105   FETCH_DATA (the_info, codep + 1);
16106   cmp_type = *codep++ & 0xff;
16107   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16108     {
16109       char suffix[3];
16110       char *p = mnemonicendp - 2;
16111
16112       /* vpcom* can have both one- and two-lettered suffix.  */
16113       if (p[0] == 'm')
16114         {
16115           p++;
16116           suffix[0] = p[0];
16117           suffix[1] = '\0';
16118         }
16119       else
16120         {
16121           suffix[0] = p[0];
16122           suffix[1] = p[1];
16123           suffix[2] = '\0';
16124         }
16125
16126       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16127       mnemonicendp += xop_cmp_op[cmp_type].len;
16128     }
16129   else
16130     {
16131       /* We have a reserved extension byte.  Output it directly.  */
16132       scratchbuf[0] = '$';
16133       print_operand_value (scratchbuf + 1, 1, cmp_type);
16134       oappend_maybe_intel (scratchbuf);
16135       scratchbuf[0] = '\0';
16136     }
16137 }
16138
16139 static const struct op pclmul_op[] =
16140 {
16141   { STRING_COMMA_LEN ("lql") },
16142   { STRING_COMMA_LEN ("hql") },
16143   { STRING_COMMA_LEN ("lqh") },
16144   { STRING_COMMA_LEN ("hqh") }
16145 };
16146
16147 static void
16148 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16149               int sizeflag ATTRIBUTE_UNUSED)
16150 {
16151   unsigned int pclmul_type;
16152
16153   FETCH_DATA (the_info, codep + 1);
16154   pclmul_type = *codep++ & 0xff;
16155   switch (pclmul_type)
16156     {
16157     case 0x10:
16158       pclmul_type = 2;
16159       break;
16160     case 0x11:
16161       pclmul_type = 3;
16162       break;
16163     default:
16164       break;
16165     }
16166   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16167     {
16168       char suffix [4];
16169       char *p = mnemonicendp - 3;
16170       suffix[0] = p[0];
16171       suffix[1] = p[1];
16172       suffix[2] = p[2];
16173       suffix[3] = '\0';
16174       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16175       mnemonicendp += pclmul_op[pclmul_type].len;
16176     }
16177   else
16178     {
16179       /* We have a reserved extension byte.  Output it directly.  */
16180       scratchbuf[0] = '$';
16181       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16182       oappend_maybe_intel (scratchbuf);
16183       scratchbuf[0] = '\0';
16184     }
16185 }
16186
16187 static void
16188 MOVBE_Fixup (int bytemode, int sizeflag)
16189 {
16190   /* Add proper suffix to "movbe".  */
16191   char *p = mnemonicendp;
16192
16193   switch (bytemode)
16194     {
16195     case v_mode:
16196       if (intel_syntax)
16197         goto skip;
16198
16199       USED_REX (REX_W);
16200       if (sizeflag & SUFFIX_ALWAYS)
16201         {
16202           if (rex & REX_W)
16203             *p++ = 'q';
16204           else
16205             {
16206               if (sizeflag & DFLAG)
16207                 *p++ = 'l';
16208               else
16209                 *p++ = 'w';
16210               used_prefixes |= (prefixes & PREFIX_DATA);
16211             }
16212         }
16213       break;
16214     default:
16215       oappend (INTERNAL_DISASSEMBLER_ERROR);
16216       break;
16217     }
16218   mnemonicendp = p;
16219   *p = '\0';
16220
16221  skip:
16222   OP_M (bytemode, sizeflag);
16223 }
16224
16225 static void
16226 MOVSXD_Fixup (int bytemode, int sizeflag)
16227 {
16228   /* Add proper suffix to "movsxd".  */
16229   char *p = mnemonicendp;
16230
16231   switch (bytemode)
16232     {
16233     case movsxd_mode:
16234       if (intel_syntax)
16235         {
16236           *p++ = 'x';
16237           *p++ = 'd';
16238           goto skip;
16239         }
16240
16241       USED_REX (REX_W);
16242       if (rex & REX_W)
16243         {
16244           *p++ = 'l';
16245           *p++ = 'q';
16246         }
16247       else
16248         {
16249           *p++ = 'x';
16250           *p++ = 'd';
16251         }
16252       break;
16253     default:
16254       oappend (INTERNAL_DISASSEMBLER_ERROR);
16255       break;
16256     }
16257
16258  skip:
16259   mnemonicendp = p;
16260   *p = '\0';
16261   OP_E (bytemode, sizeflag);
16262 }
16263
16264 static void
16265 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16266 {
16267   int reg;
16268   const char **names;
16269
16270   /* Skip mod/rm byte.  */
16271   MODRM_CHECK;
16272   codep++;
16273
16274   if (rex & REX_W)
16275     names = names64;
16276   else
16277     names = names32;
16278
16279   reg = modrm.rm;
16280   USED_REX (REX_B);
16281   if (rex & REX_B)
16282     reg += 8;
16283
16284   oappend (names[reg]);
16285 }
16286
16287 static void
16288 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16289 {
16290   const char **names;
16291   unsigned int reg = vex.register_specifier;
16292   vex.register_specifier = 0;
16293
16294   if (rex & REX_W)
16295     names = names64;
16296   else
16297     names = names32;
16298
16299   if (address_mode != mode_64bit)
16300     reg &= 7;
16301   oappend (names[reg]);
16302 }
16303
16304 static void
16305 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16306 {
16307   if (!vex.evex
16308       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16309     abort ();
16310
16311   USED_REX (REX_R);
16312   if ((rex & REX_R) != 0 || !vex.r)
16313     {
16314       BadOp ();
16315       return;
16316     }
16317
16318   oappend (names_mask [modrm.reg]);
16319 }
16320
16321 static void
16322 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16323 {
16324   if (modrm.mod == 3 && vex.b)
16325     switch (bytemode)
16326       {
16327       case evex_rounding_64_mode:
16328         if (address_mode != mode_64bit)
16329           {
16330             oappend ("(bad)");
16331             break;
16332           }
16333         /* Fall through.  */
16334       case evex_rounding_mode:
16335         oappend (names_rounding[vex.ll]);
16336         break;
16337       case evex_sae_mode:
16338         oappend ("{sae}");
16339         break;
16340       default:
16341         abort ();
16342         break;
16343       }
16344 }