1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_Rounding (int, int);
98 static void OP_REG_VexI4 (int, int);
99 static void PCLMUL_Fixup (int, int);
100 static void VEXI4_Fixup (int, int);
101 static void VZERO_Fixup (int, int);
102 static void VCMP_Fixup (int, int);
103 static void VPCMP_Fixup (int, int);
104 static void OP_0f07 (int, int);
105 static void OP_Monitor (int, int);
106 static void OP_Mwait (int, int);
107 static void NOP_Fixup1 (int, int);
108 static void NOP_Fixup2 (int, int);
109 static void OP_3DNowSuffix (int, int);
110 static void CMP_Fixup (int, int);
111 static void BadOp (void);
112 static void REP_Fixup (int, int);
113 static void BND_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 longjmp (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 #define XX { NULL, 0 }
227 #define Bad_Opcode NULL, { { NULL, 0 } }
229 #define Eb { OP_E, b_mode }
230 #define Ebnd { OP_E, bnd_mode }
231 #define EbS { OP_E, b_swap_mode }
232 #define Ev { OP_E, v_mode }
233 #define Ev_bnd { OP_E, v_bnd_mode }
234 #define EvS { OP_E, v_swap_mode }
235 #define Ed { OP_E, d_mode }
236 #define Edq { OP_E, dq_mode }
237 #define Edqw { OP_E, dqw_mode }
238 #define Edqb { OP_E, dqb_mode }
239 #define Edqd { OP_E, dqd_mode }
240 #define Eq { OP_E, q_mode }
241 #define indirEv { OP_indirE, stack_v_mode }
242 #define indirEp { OP_indirE, f_mode }
243 #define stackEv { OP_E, stack_v_mode }
244 #define Em { OP_E, m_mode }
245 #define Ew { OP_E, w_mode }
246 #define M { OP_M, 0 } /* lea, lgdt, etc. */
247 #define Ma { OP_M, a_mode }
248 #define Mb { OP_M, b_mode }
249 #define Md { OP_M, d_mode }
250 #define Mo { OP_M, o_mode }
251 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
252 #define Mq { OP_M, q_mode }
253 #define Mx { OP_M, x_mode }
254 #define Mxmm { OP_M, xmm_mode }
255 #define Gb { OP_G, b_mode }
256 #define Gbnd { OP_G, bnd_mode }
257 #define Gv { OP_G, v_mode }
258 #define Gd { OP_G, d_mode }
259 #define Gdq { OP_G, dq_mode }
260 #define Gm { OP_G, m_mode }
261 #define Gw { OP_G, w_mode }
262 #define Rd { OP_R, d_mode }
263 #define Rdq { OP_R, dq_mode }
264 #define Rm { OP_R, m_mode }
265 #define Ib { OP_I, b_mode }
266 #define sIb { OP_sI, b_mode } /* sign extened byte */
267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
268 #define Iv { OP_I, v_mode }
269 #define sIv { OP_sI, v_mode }
270 #define Iq { OP_I, q_mode }
271 #define Iv64 { OP_I64, v_mode }
272 #define Iw { OP_I, w_mode }
273 #define I1 { OP_I, const_1_mode }
274 #define Jb { OP_J, b_mode }
275 #define Jv { OP_J, v_mode }
276 #define Cm { OP_C, m_mode }
277 #define Dm { OP_D, m_mode }
278 #define Td { OP_T, d_mode }
279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
281 #define RMeAX { OP_REG, eAX_reg }
282 #define RMeBX { OP_REG, eBX_reg }
283 #define RMeCX { OP_REG, eCX_reg }
284 #define RMeDX { OP_REG, eDX_reg }
285 #define RMeSP { OP_REG, eSP_reg }
286 #define RMeBP { OP_REG, eBP_reg }
287 #define RMeSI { OP_REG, eSI_reg }
288 #define RMeDI { OP_REG, eDI_reg }
289 #define RMrAX { OP_REG, rAX_reg }
290 #define RMrBX { OP_REG, rBX_reg }
291 #define RMrCX { OP_REG, rCX_reg }
292 #define RMrDX { OP_REG, rDX_reg }
293 #define RMrSP { OP_REG, rSP_reg }
294 #define RMrBP { OP_REG, rBP_reg }
295 #define RMrSI { OP_REG, rSI_reg }
296 #define RMrDI { OP_REG, rDI_reg }
297 #define RMAL { OP_REG, al_reg }
298 #define RMCL { OP_REG, cl_reg }
299 #define RMDL { OP_REG, dl_reg }
300 #define RMBL { OP_REG, bl_reg }
301 #define RMAH { OP_REG, ah_reg }
302 #define RMCH { OP_REG, ch_reg }
303 #define RMDH { OP_REG, dh_reg }
304 #define RMBH { OP_REG, bh_reg }
305 #define RMAX { OP_REG, ax_reg }
306 #define RMDX { OP_REG, dx_reg }
308 #define eAX { OP_IMREG, eAX_reg }
309 #define eBX { OP_IMREG, eBX_reg }
310 #define eCX { OP_IMREG, eCX_reg }
311 #define eDX { OP_IMREG, eDX_reg }
312 #define eSP { OP_IMREG, eSP_reg }
313 #define eBP { OP_IMREG, eBP_reg }
314 #define eSI { OP_IMREG, eSI_reg }
315 #define eDI { OP_IMREG, eDI_reg }
316 #define AL { OP_IMREG, al_reg }
317 #define CL { OP_IMREG, cl_reg }
318 #define DL { OP_IMREG, dl_reg }
319 #define BL { OP_IMREG, bl_reg }
320 #define AH { OP_IMREG, ah_reg }
321 #define CH { OP_IMREG, ch_reg }
322 #define DH { OP_IMREG, dh_reg }
323 #define BH { OP_IMREG, bh_reg }
324 #define AX { OP_IMREG, ax_reg }
325 #define DX { OP_IMREG, dx_reg }
326 #define zAX { OP_IMREG, z_mode_ax_reg }
327 #define indirDX { OP_IMREG, indir_dx_reg }
329 #define Sw { OP_SEG, w_mode }
330 #define Sv { OP_SEG, v_mode }
331 #define Ap { OP_DIR, 0 }
332 #define Ob { OP_OFF64, b_mode }
333 #define Ov { OP_OFF64, v_mode }
334 #define Xb { OP_DSreg, eSI_reg }
335 #define Xv { OP_DSreg, eSI_reg }
336 #define Xz { OP_DSreg, eSI_reg }
337 #define Yb { OP_ESreg, eDI_reg }
338 #define Yv { OP_ESreg, eDI_reg }
339 #define DSBX { OP_DSreg, eBX_reg }
341 #define es { OP_REG, es_reg }
342 #define ss { OP_REG, ss_reg }
343 #define cs { OP_REG, cs_reg }
344 #define ds { OP_REG, ds_reg }
345 #define fs { OP_REG, fs_reg }
346 #define gs { OP_REG, gs_reg }
348 #define MX { OP_MMX, 0 }
349 #define XM { OP_XMM, 0 }
350 #define XMScalar { OP_XMM, scalar_mode }
351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
352 #define XMM { OP_XMM, xmm_mode }
353 #define XMxmmq { OP_XMM, xmmq_mode }
354 #define EM { OP_EM, v_mode }
355 #define EMS { OP_EM, v_swap_mode }
356 #define EMd { OP_EM, d_mode }
357 #define EMx { OP_EM, x_mode }
358 #define EXw { OP_EX, w_mode }
359 #define EXd { OP_EX, d_mode }
360 #define EXdScalar { OP_EX, d_scalar_mode }
361 #define EXdS { OP_EX, d_swap_mode }
362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
363 #define EXq { OP_EX, q_mode }
364 #define EXqScalar { OP_EX, q_scalar_mode }
365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
366 #define EXqS { OP_EX, q_swap_mode }
367 #define EXx { OP_EX, x_mode }
368 #define EXxS { OP_EX, x_swap_mode }
369 #define EXxmm { OP_EX, xmm_mode }
370 #define EXymm { OP_EX, ymm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
378 #define EXxmmdw { OP_EX, xmmdw_mode }
379 #define EXxmmqd { OP_EX, xmmqd_mode }
380 #define EXymmq { OP_EX, ymmq_mode }
381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
385 #define MS { OP_MS, v_mode }
386 #define XS { OP_XS, v_mode }
387 #define EMCq { OP_EMC, q_mode }
388 #define MXC { OP_MXC, 0 }
389 #define OPSUF { OP_3DNowSuffix, 0 }
390 #define CMP { CMP_Fixup, 0 }
391 #define XMM0 { XMM_Fixup, 0 }
392 #define FXSAVE { FXSAVE_Fixup, 0 }
393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
396 #define Vex { OP_VEX, vex_mode }
397 #define VexScalar { OP_VEX, vex_scalar_mode }
398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
399 #define Vex128 { OP_VEX, vex128_mode }
400 #define Vex256 { OP_VEX, vex256_mode }
401 #define VexGdq { OP_VEX, dq_mode }
402 #define VexI4 { VEXI4_Fixup, 0}
403 #define EXdVex { OP_EX_Vex, d_mode }
404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
406 #define EXqVex { OP_EX_Vex, q_mode }
407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
409 #define EXVexW { OP_EX_VexW, x_mode }
410 #define EXdVexW { OP_EX_VexW, d_mode }
411 #define EXqVexW { OP_EX_VexW, q_mode }
412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
413 #define XMVex { OP_XMM_Vex, 0 }
414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
415 #define XMVexW { OP_XMM_VexW, 0 }
416 #define XMVexI4 { OP_REG_VexI4, x_mode }
417 #define PCLMUL { PCLMUL_Fixup, 0 }
418 #define VZERO { VZERO_Fixup, 0 }
419 #define VCMP { VCMP_Fixup, 0 }
420 #define VPCMP { VPCMP_Fixup, 0 }
422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
425 #define XMask { OP_Mask, mask_mode }
426 #define MaskG { OP_G, mask_mode }
427 #define MaskE { OP_E, mask_mode }
428 #define MaskR { OP_R, mask_mode }
429 #define MaskVex { OP_VEX, mask_mode }
431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode
,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode
,
561 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
562 vex_vsib_q_w_dq_mode
,
564 /* scalar, ignore vector length. */
566 /* like d_mode, ignore vector length. */
568 /* like d_swap_mode, ignore vector length. */
570 /* like q_mode, ignore vector length. */
572 /* like q_swap_mode, ignore vector length. */
574 /* like vex_mode, ignore vector length. */
576 /* like vex_w_dq_mode, ignore vector length. */
577 vex_scalar_w_dq_mode
,
579 /* Static rounding. */
581 /* Supress all exceptions. */
584 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
654 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
655 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
656 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
657 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
658 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
659 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
660 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
661 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
662 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
663 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
664 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
665 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
784 MOD_VEX_0F12_PREFIX_0
,
786 MOD_VEX_0F16_PREFIX_0
,
802 MOD_VEX_0FD7_PREFIX_2
,
803 MOD_VEX_0FE7_PREFIX_2
,
804 MOD_VEX_0FF0_PREFIX_3
,
805 MOD_VEX_0F381A_PREFIX_2
,
806 MOD_VEX_0F382A_PREFIX_2
,
807 MOD_VEX_0F382C_PREFIX_2
,
808 MOD_VEX_0F382D_PREFIX_2
,
809 MOD_VEX_0F382E_PREFIX_2
,
810 MOD_VEX_0F382F_PREFIX_2
,
811 MOD_VEX_0F385A_PREFIX_2
,
812 MOD_VEX_0F388C_PREFIX_2
,
813 MOD_VEX_0F388E_PREFIX_2
,
815 MOD_EVEX_0F10_PREFIX_1
,
816 MOD_EVEX_0F10_PREFIX_3
,
817 MOD_EVEX_0F11_PREFIX_1
,
818 MOD_EVEX_0F11_PREFIX_3
,
819 MOD_EVEX_0F12_PREFIX_0
,
820 MOD_EVEX_0F16_PREFIX_0
,
821 MOD_EVEX_0F38C6_REG_1
,
822 MOD_EVEX_0F38C6_REG_2
,
823 MOD_EVEX_0F38C6_REG_5
,
824 MOD_EVEX_0F38C6_REG_6
,
825 MOD_EVEX_0F38C7_REG_1
,
826 MOD_EVEX_0F38C7_REG_2
,
827 MOD_EVEX_0F38C7_REG_5
,
828 MOD_EVEX_0F38C7_REG_6
1019 PREFIX_VEX_0F71_REG_2
,
1020 PREFIX_VEX_0F71_REG_4
,
1021 PREFIX_VEX_0F71_REG_6
,
1022 PREFIX_VEX_0F72_REG_2
,
1023 PREFIX_VEX_0F72_REG_4
,
1024 PREFIX_VEX_0F72_REG_6
,
1025 PREFIX_VEX_0F73_REG_2
,
1026 PREFIX_VEX_0F73_REG_3
,
1027 PREFIX_VEX_0F73_REG_6
,
1028 PREFIX_VEX_0F73_REG_7
,
1199 PREFIX_VEX_0F38F3_REG_1
,
1200 PREFIX_VEX_0F38F3_REG_2
,
1201 PREFIX_VEX_0F38F3_REG_3
,
1303 PREFIX_EVEX_0F72_REG_0
,
1304 PREFIX_EVEX_0F72_REG_1
,
1305 PREFIX_EVEX_0F72_REG_2
,
1306 PREFIX_EVEX_0F72_REG_4
,
1307 PREFIX_EVEX_0F72_REG_6
,
1308 PREFIX_EVEX_0F73_REG_2
,
1309 PREFIX_EVEX_0F73_REG_6
,
1438 PREFIX_EVEX_0F38C6_REG_1
,
1439 PREFIX_EVEX_0F38C6_REG_2
,
1440 PREFIX_EVEX_0F38C6_REG_5
,
1441 PREFIX_EVEX_0F38C6_REG_6
,
1442 PREFIX_EVEX_0F38C7_REG_1
,
1443 PREFIX_EVEX_0F38C7_REG_2
,
1444 PREFIX_EVEX_0F38C7_REG_5
,
1445 PREFIX_EVEX_0F38C7_REG_6
,
1517 THREE_BYTE_0F38
= 0,
1545 VEX_LEN_0F10_P_1
= 0,
1549 VEX_LEN_0F12_P_0_M_0
,
1550 VEX_LEN_0F12_P_0_M_1
,
1553 VEX_LEN_0F16_P_0_M_0
,
1554 VEX_LEN_0F16_P_0_M_1
,
1600 VEX_LEN_0FAE_R_2_M_0
,
1601 VEX_LEN_0FAE_R_3_M_0
,
1610 VEX_LEN_0F381A_P_2_M_0
,
1613 VEX_LEN_0F385A_P_2_M_0
,
1620 VEX_LEN_0F38F3_R_1_P_0
,
1621 VEX_LEN_0F38F3_R_2_P_0
,
1622 VEX_LEN_0F38F3_R_3_P_0
,
1666 VEX_LEN_0FXOP_08_CC
,
1667 VEX_LEN_0FXOP_08_CD
,
1668 VEX_LEN_0FXOP_08_CE
,
1669 VEX_LEN_0FXOP_08_CF
,
1670 VEX_LEN_0FXOP_08_EC
,
1671 VEX_LEN_0FXOP_08_ED
,
1672 VEX_LEN_0FXOP_08_EE
,
1673 VEX_LEN_0FXOP_08_EF
,
1674 VEX_LEN_0FXOP_09_80
,
1708 VEX_W_0F41_P_0_LEN_1
,
1709 VEX_W_0F42_P_0_LEN_1
,
1710 VEX_W_0F44_P_0_LEN_0
,
1711 VEX_W_0F45_P_0_LEN_1
,
1712 VEX_W_0F46_P_0_LEN_1
,
1713 VEX_W_0F47_P_0_LEN_1
,
1714 VEX_W_0F4B_P_2_LEN_1
,
1794 VEX_W_0F90_P_0_LEN_0
,
1795 VEX_W_0F91_P_0_LEN_0
,
1796 VEX_W_0F92_P_0_LEN_0
,
1797 VEX_W_0F93_P_0_LEN_0
,
1798 VEX_W_0F98_P_0_LEN_0
,
1877 VEX_W_0F381A_P_2_M_0
,
1889 VEX_W_0F382A_P_2_M_0
,
1891 VEX_W_0F382C_P_2_M_0
,
1892 VEX_W_0F382D_P_2_M_0
,
1893 VEX_W_0F382E_P_2_M_0
,
1894 VEX_W_0F382F_P_2_M_0
,
1916 VEX_W_0F385A_P_2_M_0
,
1944 VEX_W_0F3A30_P_2_LEN_0
,
1945 VEX_W_0F3A32_P_2_LEN_0
,
1965 EVEX_W_0F10_P_1_M_0
,
1966 EVEX_W_0F10_P_1_M_1
,
1968 EVEX_W_0F10_P_3_M_0
,
1969 EVEX_W_0F10_P_3_M_1
,
1971 EVEX_W_0F11_P_1_M_0
,
1972 EVEX_W_0F11_P_1_M_1
,
1974 EVEX_W_0F11_P_3_M_0
,
1975 EVEX_W_0F11_P_3_M_1
,
1976 EVEX_W_0F12_P_0_M_0
,
1977 EVEX_W_0F12_P_0_M_1
,
1987 EVEX_W_0F16_P_0_M_0
,
1988 EVEX_W_0F16_P_0_M_1
,
2049 EVEX_W_0F72_R_2_P_2
,
2050 EVEX_W_0F72_R_6_P_2
,
2051 EVEX_W_0F73_R_2_P_2
,
2052 EVEX_W_0F73_R_6_P_2
,
2125 EVEX_W_0F38C7_R_1_P_2
,
2126 EVEX_W_0F38C7_R_2_P_2
,
2127 EVEX_W_0F38C7_R_5_P_2
,
2128 EVEX_W_0F38C7_R_6_P_2
,
2152 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2163 /* Upper case letters in the instruction names here are macros.
2164 'A' => print 'b' if no register operands or suffix_always is true
2165 'B' => print 'b' if suffix_always is true
2166 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2168 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2169 suffix_always is true
2170 'E' => print 'e' if 32-bit form of jcxz
2171 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2172 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2173 'H' => print ",pt" or ",pn" branch hint
2174 'I' => honor following macro letter even in Intel mode (implemented only
2175 for some of the macro letters)
2177 'K' => print 'd' or 'q' if rex prefix is present.
2178 'L' => print 'l' if suffix_always is true
2179 'M' => print 'r' if intel_mnemonic is false.
2180 'N' => print 'n' if instruction has no wait "prefix"
2181 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2182 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2183 or suffix_always is true. print 'q' if rex prefix is present.
2184 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2186 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2187 'S' => print 'w', 'l' or 'q' if suffix_always is true
2188 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2189 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2190 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2191 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2192 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2193 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2194 suffix_always is true.
2195 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2196 '!' => change condition from true to false or from false to true.
2197 '%' => add 1 upper case letter to the macro.
2199 2 upper case letter macros:
2200 "XY" => print 'x' or 'y' if no register operands or suffix_always
2202 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2203 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2204 or suffix_always is true
2205 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2206 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2207 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2208 "LW" => print 'd', 'q' depending on the VEX.W bit
2210 Many of the above letters print nothing in Intel mode. See "putop"
2213 Braces '{' and '}', and vertical bars '|', indicate alternative
2214 mnemonic strings for AT&T and Intel. */
2216 static const struct dis386 dis386
[] = {
2218 { "addB", { Ebh1
, Gb
} },
2219 { "addS", { Evh1
, Gv
} },
2220 { "addB", { Gb
, EbS
} },
2221 { "addS", { Gv
, EvS
} },
2222 { "addB", { AL
, Ib
} },
2223 { "addS", { eAX
, Iv
} },
2224 { X86_64_TABLE (X86_64_06
) },
2225 { X86_64_TABLE (X86_64_07
) },
2227 { "orB", { Ebh1
, Gb
} },
2228 { "orS", { Evh1
, Gv
} },
2229 { "orB", { Gb
, EbS
} },
2230 { "orS", { Gv
, EvS
} },
2231 { "orB", { AL
, Ib
} },
2232 { "orS", { eAX
, Iv
} },
2233 { X86_64_TABLE (X86_64_0D
) },
2234 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2236 { "adcB", { Ebh1
, Gb
} },
2237 { "adcS", { Evh1
, Gv
} },
2238 { "adcB", { Gb
, EbS
} },
2239 { "adcS", { Gv
, EvS
} },
2240 { "adcB", { AL
, Ib
} },
2241 { "adcS", { eAX
, Iv
} },
2242 { X86_64_TABLE (X86_64_16
) },
2243 { X86_64_TABLE (X86_64_17
) },
2245 { "sbbB", { Ebh1
, Gb
} },
2246 { "sbbS", { Evh1
, Gv
} },
2247 { "sbbB", { Gb
, EbS
} },
2248 { "sbbS", { Gv
, EvS
} },
2249 { "sbbB", { AL
, Ib
} },
2250 { "sbbS", { eAX
, Iv
} },
2251 { X86_64_TABLE (X86_64_1E
) },
2252 { X86_64_TABLE (X86_64_1F
) },
2254 { "andB", { Ebh1
, Gb
} },
2255 { "andS", { Evh1
, Gv
} },
2256 { "andB", { Gb
, EbS
} },
2257 { "andS", { Gv
, EvS
} },
2258 { "andB", { AL
, Ib
} },
2259 { "andS", { eAX
, Iv
} },
2260 { Bad_Opcode
}, /* SEG ES prefix */
2261 { X86_64_TABLE (X86_64_27
) },
2263 { "subB", { Ebh1
, Gb
} },
2264 { "subS", { Evh1
, Gv
} },
2265 { "subB", { Gb
, EbS
} },
2266 { "subS", { Gv
, EvS
} },
2267 { "subB", { AL
, Ib
} },
2268 { "subS", { eAX
, Iv
} },
2269 { Bad_Opcode
}, /* SEG CS prefix */
2270 { X86_64_TABLE (X86_64_2F
) },
2272 { "xorB", { Ebh1
, Gb
} },
2273 { "xorS", { Evh1
, Gv
} },
2274 { "xorB", { Gb
, EbS
} },
2275 { "xorS", { Gv
, EvS
} },
2276 { "xorB", { AL
, Ib
} },
2277 { "xorS", { eAX
, Iv
} },
2278 { Bad_Opcode
}, /* SEG SS prefix */
2279 { X86_64_TABLE (X86_64_37
) },
2281 { "cmpB", { Eb
, Gb
} },
2282 { "cmpS", { Ev
, Gv
} },
2283 { "cmpB", { Gb
, EbS
} },
2284 { "cmpS", { Gv
, EvS
} },
2285 { "cmpB", { AL
, Ib
} },
2286 { "cmpS", { eAX
, Iv
} },
2287 { Bad_Opcode
}, /* SEG DS prefix */
2288 { X86_64_TABLE (X86_64_3F
) },
2290 { "inc{S|}", { RMeAX
} },
2291 { "inc{S|}", { RMeCX
} },
2292 { "inc{S|}", { RMeDX
} },
2293 { "inc{S|}", { RMeBX
} },
2294 { "inc{S|}", { RMeSP
} },
2295 { "inc{S|}", { RMeBP
} },
2296 { "inc{S|}", { RMeSI
} },
2297 { "inc{S|}", { RMeDI
} },
2299 { "dec{S|}", { RMeAX
} },
2300 { "dec{S|}", { RMeCX
} },
2301 { "dec{S|}", { RMeDX
} },
2302 { "dec{S|}", { RMeBX
} },
2303 { "dec{S|}", { RMeSP
} },
2304 { "dec{S|}", { RMeBP
} },
2305 { "dec{S|}", { RMeSI
} },
2306 { "dec{S|}", { RMeDI
} },
2308 { "pushV", { RMrAX
} },
2309 { "pushV", { RMrCX
} },
2310 { "pushV", { RMrDX
} },
2311 { "pushV", { RMrBX
} },
2312 { "pushV", { RMrSP
} },
2313 { "pushV", { RMrBP
} },
2314 { "pushV", { RMrSI
} },
2315 { "pushV", { RMrDI
} },
2317 { "popV", { RMrAX
} },
2318 { "popV", { RMrCX
} },
2319 { "popV", { RMrDX
} },
2320 { "popV", { RMrBX
} },
2321 { "popV", { RMrSP
} },
2322 { "popV", { RMrBP
} },
2323 { "popV", { RMrSI
} },
2324 { "popV", { RMrDI
} },
2326 { X86_64_TABLE (X86_64_60
) },
2327 { X86_64_TABLE (X86_64_61
) },
2328 { X86_64_TABLE (X86_64_62
) },
2329 { X86_64_TABLE (X86_64_63
) },
2330 { Bad_Opcode
}, /* seg fs */
2331 { Bad_Opcode
}, /* seg gs */
2332 { Bad_Opcode
}, /* op size prefix */
2333 { Bad_Opcode
}, /* adr size prefix */
2335 { "pushT", { sIv
} },
2336 { "imulS", { Gv
, Ev
, Iv
} },
2337 { "pushT", { sIbT
} },
2338 { "imulS", { Gv
, Ev
, sIb
} },
2339 { "ins{b|}", { Ybr
, indirDX
} },
2340 { X86_64_TABLE (X86_64_6D
) },
2341 { "outs{b|}", { indirDXr
, Xb
} },
2342 { X86_64_TABLE (X86_64_6F
) },
2344 { "joH", { Jb
, BND
, cond_jump_flag
} },
2345 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2346 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2347 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2348 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2349 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2350 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2351 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2353 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2354 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2355 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2356 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2357 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2358 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2359 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2360 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2362 { REG_TABLE (REG_80
) },
2363 { REG_TABLE (REG_81
) },
2365 { REG_TABLE (REG_82
) },
2366 { "testB", { Eb
, Gb
} },
2367 { "testS", { Ev
, Gv
} },
2368 { "xchgB", { Ebh2
, Gb
} },
2369 { "xchgS", { Evh2
, Gv
} },
2371 { "movB", { Ebh3
, Gb
} },
2372 { "movS", { Evh3
, Gv
} },
2373 { "movB", { Gb
, EbS
} },
2374 { "movS", { Gv
, EvS
} },
2375 { "movD", { Sv
, Sw
} },
2376 { MOD_TABLE (MOD_8D
) },
2377 { "movD", { Sw
, Sv
} },
2378 { REG_TABLE (REG_8F
) },
2380 { PREFIX_TABLE (PREFIX_90
) },
2381 { "xchgS", { RMeCX
, eAX
} },
2382 { "xchgS", { RMeDX
, eAX
} },
2383 { "xchgS", { RMeBX
, eAX
} },
2384 { "xchgS", { RMeSP
, eAX
} },
2385 { "xchgS", { RMeBP
, eAX
} },
2386 { "xchgS", { RMeSI
, eAX
} },
2387 { "xchgS", { RMeDI
, eAX
} },
2389 { "cW{t|}R", { XX
} },
2390 { "cR{t|}O", { XX
} },
2391 { X86_64_TABLE (X86_64_9A
) },
2392 { Bad_Opcode
}, /* fwait */
2393 { "pushfT", { XX
} },
2394 { "popfT", { XX
} },
2398 { "mov%LB", { AL
, Ob
} },
2399 { "mov%LS", { eAX
, Ov
} },
2400 { "mov%LB", { Ob
, AL
} },
2401 { "mov%LS", { Ov
, eAX
} },
2402 { "movs{b|}", { Ybr
, Xb
} },
2403 { "movs{R|}", { Yvr
, Xv
} },
2404 { "cmps{b|}", { Xb
, Yb
} },
2405 { "cmps{R|}", { Xv
, Yv
} },
2407 { "testB", { AL
, Ib
} },
2408 { "testS", { eAX
, Iv
} },
2409 { "stosB", { Ybr
, AL
} },
2410 { "stosS", { Yvr
, eAX
} },
2411 { "lodsB", { ALr
, Xb
} },
2412 { "lodsS", { eAXr
, Xv
} },
2413 { "scasB", { AL
, Yb
} },
2414 { "scasS", { eAX
, Yv
} },
2416 { "movB", { RMAL
, Ib
} },
2417 { "movB", { RMCL
, Ib
} },
2418 { "movB", { RMDL
, Ib
} },
2419 { "movB", { RMBL
, Ib
} },
2420 { "movB", { RMAH
, Ib
} },
2421 { "movB", { RMCH
, Ib
} },
2422 { "movB", { RMDH
, Ib
} },
2423 { "movB", { RMBH
, Ib
} },
2425 { "mov%LV", { RMeAX
, Iv64
} },
2426 { "mov%LV", { RMeCX
, Iv64
} },
2427 { "mov%LV", { RMeDX
, Iv64
} },
2428 { "mov%LV", { RMeBX
, Iv64
} },
2429 { "mov%LV", { RMeSP
, Iv64
} },
2430 { "mov%LV", { RMeBP
, Iv64
} },
2431 { "mov%LV", { RMeSI
, Iv64
} },
2432 { "mov%LV", { RMeDI
, Iv64
} },
2434 { REG_TABLE (REG_C0
) },
2435 { REG_TABLE (REG_C1
) },
2436 { "retT", { Iw
, BND
} },
2437 { "retT", { BND
} },
2438 { X86_64_TABLE (X86_64_C4
) },
2439 { X86_64_TABLE (X86_64_C5
) },
2440 { REG_TABLE (REG_C6
) },
2441 { REG_TABLE (REG_C7
) },
2443 { "enterT", { Iw
, Ib
} },
2444 { "leaveT", { XX
} },
2445 { "Jret{|f}P", { Iw
} },
2446 { "Jret{|f}P", { XX
} },
2449 { X86_64_TABLE (X86_64_CE
) },
2450 { "iretP", { XX
} },
2452 { REG_TABLE (REG_D0
) },
2453 { REG_TABLE (REG_D1
) },
2454 { REG_TABLE (REG_D2
) },
2455 { REG_TABLE (REG_D3
) },
2456 { X86_64_TABLE (X86_64_D4
) },
2457 { X86_64_TABLE (X86_64_D5
) },
2459 { "xlat", { DSBX
} },
2470 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2471 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2472 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2473 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2474 { "inB", { AL
, Ib
} },
2475 { "inG", { zAX
, Ib
} },
2476 { "outB", { Ib
, AL
} },
2477 { "outG", { Ib
, zAX
} },
2479 { "callT", { Jv
, BND
} },
2480 { "jmpT", { Jv
, BND
} },
2481 { X86_64_TABLE (X86_64_EA
) },
2482 { "jmp", { Jb
, BND
} },
2483 { "inB", { AL
, indirDX
} },
2484 { "inG", { zAX
, indirDX
} },
2485 { "outB", { indirDX
, AL
} },
2486 { "outG", { indirDX
, zAX
} },
2488 { Bad_Opcode
}, /* lock prefix */
2489 { "icebp", { XX
} },
2490 { Bad_Opcode
}, /* repne */
2491 { Bad_Opcode
}, /* repz */
2494 { REG_TABLE (REG_F6
) },
2495 { REG_TABLE (REG_F7
) },
2503 { REG_TABLE (REG_FE
) },
2504 { REG_TABLE (REG_FF
) },
2507 static const struct dis386 dis386_twobyte
[] = {
2509 { REG_TABLE (REG_0F00
) },
2510 { REG_TABLE (REG_0F01
) },
2511 { "larS", { Gv
, Ew
} },
2512 { "lslS", { Gv
, Ew
} },
2514 { "syscall", { XX
} },
2516 { "sysretP", { XX
} },
2519 { "wbinvd", { XX
} },
2523 { REG_TABLE (REG_0F0D
) },
2524 { "femms", { XX
} },
2525 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2527 { PREFIX_TABLE (PREFIX_0F10
) },
2528 { PREFIX_TABLE (PREFIX_0F11
) },
2529 { PREFIX_TABLE (PREFIX_0F12
) },
2530 { MOD_TABLE (MOD_0F13
) },
2531 { "unpcklpX", { XM
, EXx
} },
2532 { "unpckhpX", { XM
, EXx
} },
2533 { PREFIX_TABLE (PREFIX_0F16
) },
2534 { MOD_TABLE (MOD_0F17
) },
2536 { REG_TABLE (REG_0F18
) },
2538 { PREFIX_TABLE (PREFIX_0F1A
) },
2539 { PREFIX_TABLE (PREFIX_0F1B
) },
2545 { MOD_TABLE (MOD_0F20
) },
2546 { MOD_TABLE (MOD_0F21
) },
2547 { MOD_TABLE (MOD_0F22
) },
2548 { MOD_TABLE (MOD_0F23
) },
2549 { MOD_TABLE (MOD_0F24
) },
2551 { MOD_TABLE (MOD_0F26
) },
2554 { "movapX", { XM
, EXx
} },
2555 { "movapX", { EXxS
, XM
} },
2556 { PREFIX_TABLE (PREFIX_0F2A
) },
2557 { PREFIX_TABLE (PREFIX_0F2B
) },
2558 { PREFIX_TABLE (PREFIX_0F2C
) },
2559 { PREFIX_TABLE (PREFIX_0F2D
) },
2560 { PREFIX_TABLE (PREFIX_0F2E
) },
2561 { PREFIX_TABLE (PREFIX_0F2F
) },
2563 { "wrmsr", { XX
} },
2564 { "rdtsc", { XX
} },
2565 { "rdmsr", { XX
} },
2566 { "rdpmc", { XX
} },
2567 { "sysenter", { XX
} },
2568 { "sysexit", { XX
} },
2570 { "getsec", { XX
} },
2572 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2574 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2581 { "cmovoS", { Gv
, Ev
} },
2582 { "cmovnoS", { Gv
, Ev
} },
2583 { "cmovbS", { Gv
, Ev
} },
2584 { "cmovaeS", { Gv
, Ev
} },
2585 { "cmoveS", { Gv
, Ev
} },
2586 { "cmovneS", { Gv
, Ev
} },
2587 { "cmovbeS", { Gv
, Ev
} },
2588 { "cmovaS", { Gv
, Ev
} },
2590 { "cmovsS", { Gv
, Ev
} },
2591 { "cmovnsS", { Gv
, Ev
} },
2592 { "cmovpS", { Gv
, Ev
} },
2593 { "cmovnpS", { Gv
, Ev
} },
2594 { "cmovlS", { Gv
, Ev
} },
2595 { "cmovgeS", { Gv
, Ev
} },
2596 { "cmovleS", { Gv
, Ev
} },
2597 { "cmovgS", { Gv
, Ev
} },
2599 { MOD_TABLE (MOD_0F51
) },
2600 { PREFIX_TABLE (PREFIX_0F51
) },
2601 { PREFIX_TABLE (PREFIX_0F52
) },
2602 { PREFIX_TABLE (PREFIX_0F53
) },
2603 { "andpX", { XM
, EXx
} },
2604 { "andnpX", { XM
, EXx
} },
2605 { "orpX", { XM
, EXx
} },
2606 { "xorpX", { XM
, EXx
} },
2608 { PREFIX_TABLE (PREFIX_0F58
) },
2609 { PREFIX_TABLE (PREFIX_0F59
) },
2610 { PREFIX_TABLE (PREFIX_0F5A
) },
2611 { PREFIX_TABLE (PREFIX_0F5B
) },
2612 { PREFIX_TABLE (PREFIX_0F5C
) },
2613 { PREFIX_TABLE (PREFIX_0F5D
) },
2614 { PREFIX_TABLE (PREFIX_0F5E
) },
2615 { PREFIX_TABLE (PREFIX_0F5F
) },
2617 { PREFIX_TABLE (PREFIX_0F60
) },
2618 { PREFIX_TABLE (PREFIX_0F61
) },
2619 { PREFIX_TABLE (PREFIX_0F62
) },
2620 { "packsswb", { MX
, EM
} },
2621 { "pcmpgtb", { MX
, EM
} },
2622 { "pcmpgtw", { MX
, EM
} },
2623 { "pcmpgtd", { MX
, EM
} },
2624 { "packuswb", { MX
, EM
} },
2626 { "punpckhbw", { MX
, EM
} },
2627 { "punpckhwd", { MX
, EM
} },
2628 { "punpckhdq", { MX
, EM
} },
2629 { "packssdw", { MX
, EM
} },
2630 { PREFIX_TABLE (PREFIX_0F6C
) },
2631 { PREFIX_TABLE (PREFIX_0F6D
) },
2632 { "movK", { MX
, Edq
} },
2633 { PREFIX_TABLE (PREFIX_0F6F
) },
2635 { PREFIX_TABLE (PREFIX_0F70
) },
2636 { REG_TABLE (REG_0F71
) },
2637 { REG_TABLE (REG_0F72
) },
2638 { REG_TABLE (REG_0F73
) },
2639 { "pcmpeqb", { MX
, EM
} },
2640 { "pcmpeqw", { MX
, EM
} },
2641 { "pcmpeqd", { MX
, EM
} },
2644 { PREFIX_TABLE (PREFIX_0F78
) },
2645 { PREFIX_TABLE (PREFIX_0F79
) },
2646 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2648 { PREFIX_TABLE (PREFIX_0F7C
) },
2649 { PREFIX_TABLE (PREFIX_0F7D
) },
2650 { PREFIX_TABLE (PREFIX_0F7E
) },
2651 { PREFIX_TABLE (PREFIX_0F7F
) },
2653 { "joH", { Jv
, BND
, cond_jump_flag
} },
2654 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2655 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2656 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2657 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2658 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2659 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2660 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2662 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2663 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2664 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2665 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2666 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2667 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2668 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2669 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2672 { "setno", { Eb
} },
2674 { "setae", { Eb
} },
2676 { "setne", { Eb
} },
2677 { "setbe", { Eb
} },
2681 { "setns", { Eb
} },
2683 { "setnp", { Eb
} },
2685 { "setge", { Eb
} },
2686 { "setle", { Eb
} },
2689 { "pushT", { fs
} },
2691 { "cpuid", { XX
} },
2692 { "btS", { Ev
, Gv
} },
2693 { "shldS", { Ev
, Gv
, Ib
} },
2694 { "shldS", { Ev
, Gv
, CL
} },
2695 { REG_TABLE (REG_0FA6
) },
2696 { REG_TABLE (REG_0FA7
) },
2698 { "pushT", { gs
} },
2701 { "btsS", { Evh1
, Gv
} },
2702 { "shrdS", { Ev
, Gv
, Ib
} },
2703 { "shrdS", { Ev
, Gv
, CL
} },
2704 { REG_TABLE (REG_0FAE
) },
2705 { "imulS", { Gv
, Ev
} },
2707 { "cmpxchgB", { Ebh1
, Gb
} },
2708 { "cmpxchgS", { Evh1
, Gv
} },
2709 { MOD_TABLE (MOD_0FB2
) },
2710 { "btrS", { Evh1
, Gv
} },
2711 { MOD_TABLE (MOD_0FB4
) },
2712 { MOD_TABLE (MOD_0FB5
) },
2713 { "movz{bR|x}", { Gv
, Eb
} },
2714 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2716 { PREFIX_TABLE (PREFIX_0FB8
) },
2718 { REG_TABLE (REG_0FBA
) },
2719 { "btcS", { Evh1
, Gv
} },
2720 { PREFIX_TABLE (PREFIX_0FBC
) },
2721 { PREFIX_TABLE (PREFIX_0FBD
) },
2722 { "movs{bR|x}", { Gv
, Eb
} },
2723 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2725 { "xaddB", { Ebh1
, Gb
} },
2726 { "xaddS", { Evh1
, Gv
} },
2727 { PREFIX_TABLE (PREFIX_0FC2
) },
2728 { PREFIX_TABLE (PREFIX_0FC3
) },
2729 { "pinsrw", { MX
, Edqw
, Ib
} },
2730 { "pextrw", { Gdq
, MS
, Ib
} },
2731 { "shufpX", { XM
, EXx
, Ib
} },
2732 { REG_TABLE (REG_0FC7
) },
2734 { "bswap", { RMeAX
} },
2735 { "bswap", { RMeCX
} },
2736 { "bswap", { RMeDX
} },
2737 { "bswap", { RMeBX
} },
2738 { "bswap", { RMeSP
} },
2739 { "bswap", { RMeBP
} },
2740 { "bswap", { RMeSI
} },
2741 { "bswap", { RMeDI
} },
2743 { PREFIX_TABLE (PREFIX_0FD0
) },
2744 { "psrlw", { MX
, EM
} },
2745 { "psrld", { MX
, EM
} },
2746 { "psrlq", { MX
, EM
} },
2747 { "paddq", { MX
, EM
} },
2748 { "pmullw", { MX
, EM
} },
2749 { PREFIX_TABLE (PREFIX_0FD6
) },
2750 { MOD_TABLE (MOD_0FD7
) },
2752 { "psubusb", { MX
, EM
} },
2753 { "psubusw", { MX
, EM
} },
2754 { "pminub", { MX
, EM
} },
2755 { "pand", { MX
, EM
} },
2756 { "paddusb", { MX
, EM
} },
2757 { "paddusw", { MX
, EM
} },
2758 { "pmaxub", { MX
, EM
} },
2759 { "pandn", { MX
, EM
} },
2761 { "pavgb", { MX
, EM
} },
2762 { "psraw", { MX
, EM
} },
2763 { "psrad", { MX
, EM
} },
2764 { "pavgw", { MX
, EM
} },
2765 { "pmulhuw", { MX
, EM
} },
2766 { "pmulhw", { MX
, EM
} },
2767 { PREFIX_TABLE (PREFIX_0FE6
) },
2768 { PREFIX_TABLE (PREFIX_0FE7
) },
2770 { "psubsb", { MX
, EM
} },
2771 { "psubsw", { MX
, EM
} },
2772 { "pminsw", { MX
, EM
} },
2773 { "por", { MX
, EM
} },
2774 { "paddsb", { MX
, EM
} },
2775 { "paddsw", { MX
, EM
} },
2776 { "pmaxsw", { MX
, EM
} },
2777 { "pxor", { MX
, EM
} },
2779 { PREFIX_TABLE (PREFIX_0FF0
) },
2780 { "psllw", { MX
, EM
} },
2781 { "pslld", { MX
, EM
} },
2782 { "psllq", { MX
, EM
} },
2783 { "pmuludq", { MX
, EM
} },
2784 { "pmaddwd", { MX
, EM
} },
2785 { "psadbw", { MX
, EM
} },
2786 { PREFIX_TABLE (PREFIX_0FF7
) },
2788 { "psubb", { MX
, EM
} },
2789 { "psubw", { MX
, EM
} },
2790 { "psubd", { MX
, EM
} },
2791 { "psubq", { MX
, EM
} },
2792 { "paddb", { MX
, EM
} },
2793 { "paddw", { MX
, EM
} },
2794 { "paddd", { MX
, EM
} },
2798 static const unsigned char onebyte_has_modrm
[256] = {
2799 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2800 /* ------------------------------- */
2801 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2802 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2803 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2804 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2805 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2806 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2807 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2808 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2809 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2810 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2811 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2812 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2813 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2814 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2815 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2816 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2817 /* ------------------------------- */
2818 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2821 static const unsigned char twobyte_has_modrm
[256] = {
2822 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2823 /* ------------------------------- */
2824 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2825 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2826 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2827 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2828 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2829 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2830 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2831 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2832 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2833 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2834 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2835 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2836 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2837 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2838 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2839 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2840 /* ------------------------------- */
2841 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2844 static char obuf
[100];
2846 static char *mnemonicendp
;
2847 static char scratchbuf
[100];
2848 static unsigned char *start_codep
;
2849 static unsigned char *insn_codep
;
2850 static unsigned char *codep
;
2851 static int last_lock_prefix
;
2852 static int last_repz_prefix
;
2853 static int last_repnz_prefix
;
2854 static int last_data_prefix
;
2855 static int last_addr_prefix
;
2856 static int last_rex_prefix
;
2857 static int last_seg_prefix
;
2858 #define MAX_CODE_LENGTH 15
2859 /* We can up to 14 prefixes since the maximum instruction length is
2861 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2862 static disassemble_info
*the_info
;
2870 static unsigned char need_modrm
;
2880 int register_specifier
;
2887 int mask_register_specifier
;
2893 static unsigned char need_vex
;
2894 static unsigned char need_vex_reg
;
2895 static unsigned char vex_w_done
;
2903 /* If we are accessing mod/rm/reg without need_modrm set, then the
2904 values are stale. Hitting this abort likely indicates that you
2905 need to update onebyte_has_modrm or twobyte_has_modrm. */
2906 #define MODRM_CHECK if (!need_modrm) abort ()
2908 static const char **names64
;
2909 static const char **names32
;
2910 static const char **names16
;
2911 static const char **names8
;
2912 static const char **names8rex
;
2913 static const char **names_seg
;
2914 static const char *index64
;
2915 static const char *index32
;
2916 static const char **index16
;
2917 static const char **names_bnd
;
2919 static const char *intel_names64
[] = {
2920 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2921 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2923 static const char *intel_names32
[] = {
2924 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2925 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2927 static const char *intel_names16
[] = {
2928 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2929 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2931 static const char *intel_names8
[] = {
2932 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2934 static const char *intel_names8rex
[] = {
2935 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2936 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2938 static const char *intel_names_seg
[] = {
2939 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2941 static const char *intel_index64
= "riz";
2942 static const char *intel_index32
= "eiz";
2943 static const char *intel_index16
[] = {
2944 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2947 static const char *att_names64
[] = {
2948 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2949 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2951 static const char *att_names32
[] = {
2952 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2953 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2955 static const char *att_names16
[] = {
2956 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2957 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2959 static const char *att_names8
[] = {
2960 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2962 static const char *att_names8rex
[] = {
2963 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2964 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2966 static const char *att_names_seg
[] = {
2967 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2969 static const char *att_index64
= "%riz";
2970 static const char *att_index32
= "%eiz";
2971 static const char *att_index16
[] = {
2972 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2975 static const char **names_mm
;
2976 static const char *intel_names_mm
[] = {
2977 "mm0", "mm1", "mm2", "mm3",
2978 "mm4", "mm5", "mm6", "mm7"
2980 static const char *att_names_mm
[] = {
2981 "%mm0", "%mm1", "%mm2", "%mm3",
2982 "%mm4", "%mm5", "%mm6", "%mm7"
2985 static const char *intel_names_bnd
[] = {
2986 "bnd0", "bnd1", "bnd2", "bnd3"
2989 static const char *att_names_bnd
[] = {
2990 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2993 static const char **names_xmm
;
2994 static const char *intel_names_xmm
[] = {
2995 "xmm0", "xmm1", "xmm2", "xmm3",
2996 "xmm4", "xmm5", "xmm6", "xmm7",
2997 "xmm8", "xmm9", "xmm10", "xmm11",
2998 "xmm12", "xmm13", "xmm14", "xmm15",
2999 "xmm16", "xmm17", "xmm18", "xmm19",
3000 "xmm20", "xmm21", "xmm22", "xmm23",
3001 "xmm24", "xmm25", "xmm26", "xmm27",
3002 "xmm28", "xmm29", "xmm30", "xmm31"
3004 static const char *att_names_xmm
[] = {
3005 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3006 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3007 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3008 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3009 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3010 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3011 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3012 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3015 static const char **names_ymm
;
3016 static const char *intel_names_ymm
[] = {
3017 "ymm0", "ymm1", "ymm2", "ymm3",
3018 "ymm4", "ymm5", "ymm6", "ymm7",
3019 "ymm8", "ymm9", "ymm10", "ymm11",
3020 "ymm12", "ymm13", "ymm14", "ymm15",
3021 "ymm16", "ymm17", "ymm18", "ymm19",
3022 "ymm20", "ymm21", "ymm22", "ymm23",
3023 "ymm24", "ymm25", "ymm26", "ymm27",
3024 "ymm28", "ymm29", "ymm30", "ymm31"
3026 static const char *att_names_ymm
[] = {
3027 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3028 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3029 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3030 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3031 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3032 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3033 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3034 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3037 static const char **names_zmm
;
3038 static const char *intel_names_zmm
[] = {
3039 "zmm0", "zmm1", "zmm2", "zmm3",
3040 "zmm4", "zmm5", "zmm6", "zmm7",
3041 "zmm8", "zmm9", "zmm10", "zmm11",
3042 "zmm12", "zmm13", "zmm14", "zmm15",
3043 "zmm16", "zmm17", "zmm18", "zmm19",
3044 "zmm20", "zmm21", "zmm22", "zmm23",
3045 "zmm24", "zmm25", "zmm26", "zmm27",
3046 "zmm28", "zmm29", "zmm30", "zmm31"
3048 static const char *att_names_zmm
[] = {
3049 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3050 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3051 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3052 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3053 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3054 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3055 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3056 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3059 static const char **names_mask
;
3060 static const char *intel_names_mask
[] = {
3061 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3063 static const char *att_names_mask
[] = {
3064 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3067 static const char *names_rounding
[] =
3075 static const struct dis386 reg_table
[][8] = {
3078 { "addA", { Ebh1
, Ib
} },
3079 { "orA", { Ebh1
, Ib
} },
3080 { "adcA", { Ebh1
, Ib
} },
3081 { "sbbA", { Ebh1
, Ib
} },
3082 { "andA", { Ebh1
, Ib
} },
3083 { "subA", { Ebh1
, Ib
} },
3084 { "xorA", { Ebh1
, Ib
} },
3085 { "cmpA", { Eb
, Ib
} },
3089 { "addQ", { Evh1
, Iv
} },
3090 { "orQ", { Evh1
, Iv
} },
3091 { "adcQ", { Evh1
, Iv
} },
3092 { "sbbQ", { Evh1
, Iv
} },
3093 { "andQ", { Evh1
, Iv
} },
3094 { "subQ", { Evh1
, Iv
} },
3095 { "xorQ", { Evh1
, Iv
} },
3096 { "cmpQ", { Ev
, Iv
} },
3100 { "addQ", { Evh1
, sIb
} },
3101 { "orQ", { Evh1
, sIb
} },
3102 { "adcQ", { Evh1
, sIb
} },
3103 { "sbbQ", { Evh1
, sIb
} },
3104 { "andQ", { Evh1
, sIb
} },
3105 { "subQ", { Evh1
, sIb
} },
3106 { "xorQ", { Evh1
, sIb
} },
3107 { "cmpQ", { Ev
, sIb
} },
3111 { "popU", { stackEv
} },
3112 { XOP_8F_TABLE (XOP_09
) },
3116 { XOP_8F_TABLE (XOP_09
) },
3120 { "rolA", { Eb
, Ib
} },
3121 { "rorA", { Eb
, Ib
} },
3122 { "rclA", { Eb
, Ib
} },
3123 { "rcrA", { Eb
, Ib
} },
3124 { "shlA", { Eb
, Ib
} },
3125 { "shrA", { Eb
, Ib
} },
3127 { "sarA", { Eb
, Ib
} },
3131 { "rolQ", { Ev
, Ib
} },
3132 { "rorQ", { Ev
, Ib
} },
3133 { "rclQ", { Ev
, Ib
} },
3134 { "rcrQ", { Ev
, Ib
} },
3135 { "shlQ", { Ev
, Ib
} },
3136 { "shrQ", { Ev
, Ib
} },
3138 { "sarQ", { Ev
, Ib
} },
3142 { "movA", { Ebh3
, Ib
} },
3149 { MOD_TABLE (MOD_C6_REG_7
) },
3153 { "movQ", { Evh3
, Iv
} },
3160 { MOD_TABLE (MOD_C7_REG_7
) },
3164 { "rolA", { Eb
, I1
} },
3165 { "rorA", { Eb
, I1
} },
3166 { "rclA", { Eb
, I1
} },
3167 { "rcrA", { Eb
, I1
} },
3168 { "shlA", { Eb
, I1
} },
3169 { "shrA", { Eb
, I1
} },
3171 { "sarA", { Eb
, I1
} },
3175 { "rolQ", { Ev
, I1
} },
3176 { "rorQ", { Ev
, I1
} },
3177 { "rclQ", { Ev
, I1
} },
3178 { "rcrQ", { Ev
, I1
} },
3179 { "shlQ", { Ev
, I1
} },
3180 { "shrQ", { Ev
, I1
} },
3182 { "sarQ", { Ev
, I1
} },
3186 { "rolA", { Eb
, CL
} },
3187 { "rorA", { Eb
, CL
} },
3188 { "rclA", { Eb
, CL
} },
3189 { "rcrA", { Eb
, CL
} },
3190 { "shlA", { Eb
, CL
} },
3191 { "shrA", { Eb
, CL
} },
3193 { "sarA", { Eb
, CL
} },
3197 { "rolQ", { Ev
, CL
} },
3198 { "rorQ", { Ev
, CL
} },
3199 { "rclQ", { Ev
, CL
} },
3200 { "rcrQ", { Ev
, CL
} },
3201 { "shlQ", { Ev
, CL
} },
3202 { "shrQ", { Ev
, CL
} },
3204 { "sarQ", { Ev
, CL
} },
3208 { "testA", { Eb
, Ib
} },
3210 { "notA", { Ebh1
} },
3211 { "negA", { Ebh1
} },
3212 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3213 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3214 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3215 { "idivA", { Eb
} }, /* and idiv for consistency. */
3219 { "testQ", { Ev
, Iv
} },
3221 { "notQ", { Evh1
} },
3222 { "negQ", { Evh1
} },
3223 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3224 { "imulQ", { Ev
} },
3226 { "idivQ", { Ev
} },
3230 { "incA", { Ebh1
} },
3231 { "decA", { Ebh1
} },
3235 { "incQ", { Evh1
} },
3236 { "decQ", { Evh1
} },
3237 { "call{T|}", { indirEv
, BND
} },
3238 { MOD_TABLE (MOD_FF_REG_3
) },
3239 { "jmp{T|}", { indirEv
, BND
} },
3240 { MOD_TABLE (MOD_FF_REG_5
) },
3241 { "pushU", { stackEv
} },
3246 { "sldtD", { Sv
} },
3257 { MOD_TABLE (MOD_0F01_REG_0
) },
3258 { MOD_TABLE (MOD_0F01_REG_1
) },
3259 { MOD_TABLE (MOD_0F01_REG_2
) },
3260 { MOD_TABLE (MOD_0F01_REG_3
) },
3261 { "smswD", { Sv
} },
3264 { MOD_TABLE (MOD_0F01_REG_7
) },
3268 { "prefetch", { Mb
} },
3269 { "prefetchw", { Mb
} },
3270 { "prefetchwt1", { Mb
} },
3271 { "prefetch", { Mb
} },
3272 { "prefetch", { Mb
} },
3273 { "prefetch", { Mb
} },
3274 { "prefetch", { Mb
} },
3275 { "prefetch", { Mb
} },
3279 { MOD_TABLE (MOD_0F18_REG_0
) },
3280 { MOD_TABLE (MOD_0F18_REG_1
) },
3281 { MOD_TABLE (MOD_0F18_REG_2
) },
3282 { MOD_TABLE (MOD_0F18_REG_3
) },
3283 { MOD_TABLE (MOD_0F18_REG_4
) },
3284 { MOD_TABLE (MOD_0F18_REG_5
) },
3285 { MOD_TABLE (MOD_0F18_REG_6
) },
3286 { MOD_TABLE (MOD_0F18_REG_7
) },
3292 { MOD_TABLE (MOD_0F71_REG_2
) },
3294 { MOD_TABLE (MOD_0F71_REG_4
) },
3296 { MOD_TABLE (MOD_0F71_REG_6
) },
3302 { MOD_TABLE (MOD_0F72_REG_2
) },
3304 { MOD_TABLE (MOD_0F72_REG_4
) },
3306 { MOD_TABLE (MOD_0F72_REG_6
) },
3312 { MOD_TABLE (MOD_0F73_REG_2
) },
3313 { MOD_TABLE (MOD_0F73_REG_3
) },
3316 { MOD_TABLE (MOD_0F73_REG_6
) },
3317 { MOD_TABLE (MOD_0F73_REG_7
) },
3321 { "montmul", { { OP_0f07
, 0 } } },
3322 { "xsha1", { { OP_0f07
, 0 } } },
3323 { "xsha256", { { OP_0f07
, 0 } } },
3327 { "xstore-rng", { { OP_0f07
, 0 } } },
3328 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3329 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3330 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3331 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3332 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3336 { MOD_TABLE (MOD_0FAE_REG_0
) },
3337 { MOD_TABLE (MOD_0FAE_REG_1
) },
3338 { MOD_TABLE (MOD_0FAE_REG_2
) },
3339 { MOD_TABLE (MOD_0FAE_REG_3
) },
3340 { MOD_TABLE (MOD_0FAE_REG_4
) },
3341 { MOD_TABLE (MOD_0FAE_REG_5
) },
3342 { MOD_TABLE (MOD_0FAE_REG_6
) },
3343 { MOD_TABLE (MOD_0FAE_REG_7
) },
3351 { "btQ", { Ev
, Ib
} },
3352 { "btsQ", { Evh1
, Ib
} },
3353 { "btrQ", { Evh1
, Ib
} },
3354 { "btcQ", { Evh1
, Ib
} },
3359 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3361 { MOD_TABLE (MOD_0FC7_REG_3
) },
3362 { MOD_TABLE (MOD_0FC7_REG_4
) },
3363 { MOD_TABLE (MOD_0FC7_REG_5
) },
3364 { MOD_TABLE (MOD_0FC7_REG_6
) },
3365 { MOD_TABLE (MOD_0FC7_REG_7
) },
3371 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3373 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3375 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3381 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3383 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3385 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3391 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3392 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3395 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3396 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3402 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3403 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3405 /* REG_VEX_0F38F3 */
3408 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3409 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3410 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3414 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3415 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3419 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3420 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3422 /* REG_XOP_TBM_01 */
3425 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3426 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3427 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3428 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3429 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3430 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3431 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3433 /* REG_XOP_TBM_02 */
3436 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3441 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3443 #define NEED_REG_TABLE
3444 #include "i386-dis-evex.h"
3445 #undef NEED_REG_TABLE
3448 static const struct dis386 prefix_table
[][4] = {
3451 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3452 { "pause", { XX
} },
3453 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3458 { "movups", { XM
, EXx
} },
3459 { "movss", { XM
, EXd
} },
3460 { "movupd", { XM
, EXx
} },
3461 { "movsd", { XM
, EXq
} },
3466 { "movups", { EXxS
, XM
} },
3467 { "movss", { EXdS
, XM
} },
3468 { "movupd", { EXxS
, XM
} },
3469 { "movsd", { EXqS
, XM
} },
3474 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3475 { "movsldup", { XM
, EXx
} },
3476 { "movlpd", { XM
, EXq
} },
3477 { "movddup", { XM
, EXq
} },
3482 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3483 { "movshdup", { XM
, EXx
} },
3484 { "movhpd", { XM
, EXq
} },
3489 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3490 { "bndcl", { Gbnd
, Ev_bnd
} },
3491 { "bndmov", { Gbnd
, Ebnd
} },
3492 { "bndcu", { Gbnd
, Ev_bnd
} },
3497 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3498 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3499 { "bndmov", { Ebnd
, Gbnd
} },
3500 { "bndcn", { Gbnd
, Ev_bnd
} },
3505 { "cvtpi2ps", { XM
, EMCq
} },
3506 { "cvtsi2ss%LQ", { XM
, Ev
} },
3507 { "cvtpi2pd", { XM
, EMCq
} },
3508 { "cvtsi2sd%LQ", { XM
, Ev
} },
3513 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3514 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3515 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3516 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3521 { "cvttps2pi", { MXC
, EXq
} },
3522 { "cvttss2siY", { Gv
, EXd
} },
3523 { "cvttpd2pi", { MXC
, EXx
} },
3524 { "cvttsd2siY", { Gv
, EXq
} },
3529 { "cvtps2pi", { MXC
, EXq
} },
3530 { "cvtss2siY", { Gv
, EXd
} },
3531 { "cvtpd2pi", { MXC
, EXx
} },
3532 { "cvtsd2siY", { Gv
, EXq
} },
3537 { "ucomiss",{ XM
, EXd
} },
3539 { "ucomisd",{ XM
, EXq
} },
3544 { "comiss", { XM
, EXd
} },
3546 { "comisd", { XM
, EXq
} },
3551 { "sqrtps", { XM
, EXx
} },
3552 { "sqrtss", { XM
, EXd
} },
3553 { "sqrtpd", { XM
, EXx
} },
3554 { "sqrtsd", { XM
, EXq
} },
3559 { "rsqrtps",{ XM
, EXx
} },
3560 { "rsqrtss",{ XM
, EXd
} },
3565 { "rcpps", { XM
, EXx
} },
3566 { "rcpss", { XM
, EXd
} },
3571 { "addps", { XM
, EXx
} },
3572 { "addss", { XM
, EXd
} },
3573 { "addpd", { XM
, EXx
} },
3574 { "addsd", { XM
, EXq
} },
3579 { "mulps", { XM
, EXx
} },
3580 { "mulss", { XM
, EXd
} },
3581 { "mulpd", { XM
, EXx
} },
3582 { "mulsd", { XM
, EXq
} },
3587 { "cvtps2pd", { XM
, EXq
} },
3588 { "cvtss2sd", { XM
, EXd
} },
3589 { "cvtpd2ps", { XM
, EXx
} },
3590 { "cvtsd2ss", { XM
, EXq
} },
3595 { "cvtdq2ps", { XM
, EXx
} },
3596 { "cvttps2dq", { XM
, EXx
} },
3597 { "cvtps2dq", { XM
, EXx
} },
3602 { "subps", { XM
, EXx
} },
3603 { "subss", { XM
, EXd
} },
3604 { "subpd", { XM
, EXx
} },
3605 { "subsd", { XM
, EXq
} },
3610 { "minps", { XM
, EXx
} },
3611 { "minss", { XM
, EXd
} },
3612 { "minpd", { XM
, EXx
} },
3613 { "minsd", { XM
, EXq
} },
3618 { "divps", { XM
, EXx
} },
3619 { "divss", { XM
, EXd
} },
3620 { "divpd", { XM
, EXx
} },
3621 { "divsd", { XM
, EXq
} },
3626 { "maxps", { XM
, EXx
} },
3627 { "maxss", { XM
, EXd
} },
3628 { "maxpd", { XM
, EXx
} },
3629 { "maxsd", { XM
, EXq
} },
3634 { "punpcklbw",{ MX
, EMd
} },
3636 { "punpcklbw",{ MX
, EMx
} },
3641 { "punpcklwd",{ MX
, EMd
} },
3643 { "punpcklwd",{ MX
, EMx
} },
3648 { "punpckldq",{ MX
, EMd
} },
3650 { "punpckldq",{ MX
, EMx
} },
3657 { "punpcklqdq", { XM
, EXx
} },
3664 { "punpckhqdq", { XM
, EXx
} },
3669 { "movq", { MX
, EM
} },
3670 { "movdqu", { XM
, EXx
} },
3671 { "movdqa", { XM
, EXx
} },
3676 { "pshufw", { MX
, EM
, Ib
} },
3677 { "pshufhw",{ XM
, EXx
, Ib
} },
3678 { "pshufd", { XM
, EXx
, Ib
} },
3679 { "pshuflw",{ XM
, EXx
, Ib
} },
3682 /* PREFIX_0F73_REG_3 */
3686 { "psrldq", { XS
, Ib
} },
3689 /* PREFIX_0F73_REG_7 */
3693 { "pslldq", { XS
, Ib
} },
3698 {"vmread", { Em
, Gm
} },
3700 {"extrq", { XS
, Ib
, Ib
} },
3701 {"insertq", { XM
, XS
, Ib
, Ib
} },
3706 {"vmwrite", { Gm
, Em
} },
3708 {"extrq", { XM
, XS
} },
3709 {"insertq", { XM
, XS
} },
3716 { "haddpd", { XM
, EXx
} },
3717 { "haddps", { XM
, EXx
} },
3724 { "hsubpd", { XM
, EXx
} },
3725 { "hsubps", { XM
, EXx
} },
3730 { "movK", { Edq
, MX
} },
3731 { "movq", { XM
, EXq
} },
3732 { "movK", { Edq
, XM
} },
3737 { "movq", { EMS
, MX
} },
3738 { "movdqu", { EXxS
, XM
} },
3739 { "movdqa", { EXxS
, XM
} },
3742 /* PREFIX_0FAE_REG_0 */
3745 { "rdfsbase", { Ev
} },
3748 /* PREFIX_0FAE_REG_1 */
3751 { "rdgsbase", { Ev
} },
3754 /* PREFIX_0FAE_REG_2 */
3757 { "wrfsbase", { Ev
} },
3760 /* PREFIX_0FAE_REG_3 */
3763 { "wrgsbase", { Ev
} },
3766 /* PREFIX_0FAE_REG_7 */
3768 { "clflush", { Mb
} },
3770 { "clflushopt", { Mb
} },
3776 { "popcntS", { Gv
, Ev
} },
3781 { "bsfS", { Gv
, Ev
} },
3782 { "tzcntS", { Gv
, Ev
} },
3783 { "bsfS", { Gv
, Ev
} },
3788 { "bsrS", { Gv
, Ev
} },
3789 { "lzcntS", { Gv
, Ev
} },
3790 { "bsrS", { Gv
, Ev
} },
3795 { "cmpps", { XM
, EXx
, CMP
} },
3796 { "cmpss", { XM
, EXd
, CMP
} },
3797 { "cmppd", { XM
, EXx
, CMP
} },
3798 { "cmpsd", { XM
, EXq
, CMP
} },
3803 { "movntiS", { Ma
, Gv
} },
3806 /* PREFIX_0FC7_REG_6 */
3808 { "vmptrld",{ Mq
} },
3809 { "vmxon", { Mq
} },
3810 { "vmclear",{ Mq
} },
3817 { "addsubpd", { XM
, EXx
} },
3818 { "addsubps", { XM
, EXx
} },
3824 { "movq2dq",{ XM
, MS
} },
3825 { "movq", { EXqS
, XM
} },
3826 { "movdq2q",{ MX
, XS
} },
3832 { "cvtdq2pd", { XM
, EXq
} },
3833 { "cvttpd2dq", { XM
, EXx
} },
3834 { "cvtpd2dq", { XM
, EXx
} },
3839 { "movntq", { Mq
, MX
} },
3841 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3849 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3854 { "maskmovq", { MX
, MS
} },
3856 { "maskmovdqu", { XM
, XS
} },
3863 { "pblendvb", { XM
, EXx
, XMM0
} },
3870 { "blendvps", { XM
, EXx
, XMM0
} },
3877 { "blendvpd", { XM
, EXx
, XMM0
} },
3884 { "ptest", { XM
, EXx
} },
3891 { "pmovsxbw", { XM
, EXq
} },
3898 { "pmovsxbd", { XM
, EXd
} },
3905 { "pmovsxbq", { XM
, EXw
} },
3912 { "pmovsxwd", { XM
, EXq
} },
3919 { "pmovsxwq", { XM
, EXd
} },
3926 { "pmovsxdq", { XM
, EXq
} },
3933 { "pmuldq", { XM
, EXx
} },
3940 { "pcmpeqq", { XM
, EXx
} },
3947 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3954 { "packusdw", { XM
, EXx
} },
3961 { "pmovzxbw", { XM
, EXq
} },
3968 { "pmovzxbd", { XM
, EXd
} },
3975 { "pmovzxbq", { XM
, EXw
} },
3982 { "pmovzxwd", { XM
, EXq
} },
3989 { "pmovzxwq", { XM
, EXd
} },
3996 { "pmovzxdq", { XM
, EXq
} },
4003 { "pcmpgtq", { XM
, EXx
} },
4010 { "pminsb", { XM
, EXx
} },
4017 { "pminsd", { XM
, EXx
} },
4024 { "pminuw", { XM
, EXx
} },
4031 { "pminud", { XM
, EXx
} },
4038 { "pmaxsb", { XM
, EXx
} },
4045 { "pmaxsd", { XM
, EXx
} },
4052 { "pmaxuw", { XM
, EXx
} },
4059 { "pmaxud", { XM
, EXx
} },
4066 { "pmulld", { XM
, EXx
} },
4073 { "phminposuw", { XM
, EXx
} },
4080 { "invept", { Gm
, Mo
} },
4087 { "invvpid", { Gm
, Mo
} },
4094 { "invpcid", { Gm
, M
} },
4099 { "sha1nexte", { XM
, EXxmm
} },
4104 { "sha1msg1", { XM
, EXxmm
} },
4109 { "sha1msg2", { XM
, EXxmm
} },
4114 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4119 { "sha256msg1", { XM
, EXxmm
} },
4124 { "sha256msg2", { XM
, EXxmm
} },
4131 { "aesimc", { XM
, EXx
} },
4138 { "aesenc", { XM
, EXx
} },
4145 { "aesenclast", { XM
, EXx
} },
4152 { "aesdec", { XM
, EXx
} },
4159 { "aesdeclast", { XM
, EXx
} },
4164 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4166 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4167 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4172 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4174 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4175 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4181 { "adoxS", { Gdq
, Edq
} },
4182 { "adcxS", { Gdq
, Edq
} },
4190 { "roundps", { XM
, EXx
, Ib
} },
4197 { "roundpd", { XM
, EXx
, Ib
} },
4204 { "roundss", { XM
, EXd
, Ib
} },
4211 { "roundsd", { XM
, EXq
, Ib
} },
4218 { "blendps", { XM
, EXx
, Ib
} },
4225 { "blendpd", { XM
, EXx
, Ib
} },
4232 { "pblendw", { XM
, EXx
, Ib
} },
4239 { "pextrb", { Edqb
, XM
, Ib
} },
4246 { "pextrw", { Edqw
, XM
, Ib
} },
4253 { "pextrK", { Edq
, XM
, Ib
} },
4260 { "extractps", { Edqd
, XM
, Ib
} },
4267 { "pinsrb", { XM
, Edqb
, Ib
} },
4274 { "insertps", { XM
, EXd
, Ib
} },
4281 { "pinsrK", { XM
, Edq
, Ib
} },
4288 { "dpps", { XM
, EXx
, Ib
} },
4295 { "dppd", { XM
, EXx
, Ib
} },
4302 { "mpsadbw", { XM
, EXx
, Ib
} },
4309 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4316 { "pcmpestrm", { XM
, EXx
, Ib
} },
4323 { "pcmpestri", { XM
, EXx
, Ib
} },
4330 { "pcmpistrm", { XM
, EXx
, Ib
} },
4337 { "pcmpistri", { XM
, EXx
, Ib
} },
4342 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4349 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4352 /* PREFIX_VEX_0F10 */
4354 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4355 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4356 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4357 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4360 /* PREFIX_VEX_0F11 */
4362 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4363 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4364 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4365 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4368 /* PREFIX_VEX_0F12 */
4370 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4371 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4372 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4373 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4376 /* PREFIX_VEX_0F16 */
4378 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4379 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4380 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4383 /* PREFIX_VEX_0F2A */
4386 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4388 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4391 /* PREFIX_VEX_0F2C */
4394 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4396 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4399 /* PREFIX_VEX_0F2D */
4402 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4404 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4407 /* PREFIX_VEX_0F2E */
4409 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4411 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4414 /* PREFIX_VEX_0F2F */
4416 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4418 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4421 /* PREFIX_VEX_0F41 */
4423 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4426 /* PREFIX_VEX_0F42 */
4428 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4431 /* PREFIX_VEX_0F44 */
4433 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4436 /* PREFIX_VEX_0F45 */
4438 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4441 /* PREFIX_VEX_0F46 */
4443 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4446 /* PREFIX_VEX_0F47 */
4448 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4451 /* PREFIX_VEX_0F4B */
4455 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4458 /* PREFIX_VEX_0F51 */
4460 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4461 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4462 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4463 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4466 /* PREFIX_VEX_0F52 */
4468 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4469 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4472 /* PREFIX_VEX_0F53 */
4474 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4475 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4478 /* PREFIX_VEX_0F58 */
4480 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4481 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4482 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4483 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4486 /* PREFIX_VEX_0F59 */
4488 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4489 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4490 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4491 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4494 /* PREFIX_VEX_0F5A */
4496 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4497 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4498 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4499 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4502 /* PREFIX_VEX_0F5B */
4504 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4505 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4506 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4509 /* PREFIX_VEX_0F5C */
4511 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4512 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4513 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4514 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4517 /* PREFIX_VEX_0F5D */
4519 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4520 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4521 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4522 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4525 /* PREFIX_VEX_0F5E */
4527 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4528 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4529 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4530 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4533 /* PREFIX_VEX_0F5F */
4535 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4536 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4537 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4538 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4541 /* PREFIX_VEX_0F60 */
4545 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4548 /* PREFIX_VEX_0F61 */
4552 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4555 /* PREFIX_VEX_0F62 */
4559 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4562 /* PREFIX_VEX_0F63 */
4566 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4569 /* PREFIX_VEX_0F64 */
4573 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4576 /* PREFIX_VEX_0F65 */
4580 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4583 /* PREFIX_VEX_0F66 */
4587 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4590 /* PREFIX_VEX_0F67 */
4594 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4597 /* PREFIX_VEX_0F68 */
4601 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4604 /* PREFIX_VEX_0F69 */
4608 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4611 /* PREFIX_VEX_0F6A */
4615 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4618 /* PREFIX_VEX_0F6B */
4622 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4625 /* PREFIX_VEX_0F6C */
4629 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4632 /* PREFIX_VEX_0F6D */
4636 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4639 /* PREFIX_VEX_0F6E */
4643 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4646 /* PREFIX_VEX_0F6F */
4649 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4650 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4653 /* PREFIX_VEX_0F70 */
4656 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4657 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4658 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4661 /* PREFIX_VEX_0F71_REG_2 */
4665 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4668 /* PREFIX_VEX_0F71_REG_4 */
4672 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4675 /* PREFIX_VEX_0F71_REG_6 */
4679 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4682 /* PREFIX_VEX_0F72_REG_2 */
4686 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4689 /* PREFIX_VEX_0F72_REG_4 */
4693 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4696 /* PREFIX_VEX_0F72_REG_6 */
4700 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4703 /* PREFIX_VEX_0F73_REG_2 */
4707 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4710 /* PREFIX_VEX_0F73_REG_3 */
4714 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4717 /* PREFIX_VEX_0F73_REG_6 */
4721 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4724 /* PREFIX_VEX_0F73_REG_7 */
4728 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4731 /* PREFIX_VEX_0F74 */
4735 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4738 /* PREFIX_VEX_0F75 */
4742 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4745 /* PREFIX_VEX_0F76 */
4749 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4752 /* PREFIX_VEX_0F77 */
4754 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4757 /* PREFIX_VEX_0F7C */
4761 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
4762 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
4765 /* PREFIX_VEX_0F7D */
4769 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
4770 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
4773 /* PREFIX_VEX_0F7E */
4776 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4780 /* PREFIX_VEX_0F7F */
4783 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
4784 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
4787 /* PREFIX_VEX_0F90 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4792 /* PREFIX_VEX_0F91 */
4794 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4797 /* PREFIX_VEX_0F92 */
4799 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4802 /* PREFIX_VEX_0F93 */
4804 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
4807 /* PREFIX_VEX_0F98 */
4809 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
4812 /* PREFIX_VEX_0FC2 */
4814 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
4815 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
4816 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
4817 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
4820 /* PREFIX_VEX_0FC4 */
4824 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4827 /* PREFIX_VEX_0FC5 */
4831 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4834 /* PREFIX_VEX_0FD0 */
4838 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4839 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4842 /* PREFIX_VEX_0FD1 */
4846 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
4849 /* PREFIX_VEX_0FD2 */
4853 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
4856 /* PREFIX_VEX_0FD3 */
4860 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
4863 /* PREFIX_VEX_0FD4 */
4867 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
4870 /* PREFIX_VEX_0FD5 */
4874 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
4877 /* PREFIX_VEX_0FD6 */
4881 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4884 /* PREFIX_VEX_0FD7 */
4888 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4891 /* PREFIX_VEX_0FD8 */
4895 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
4898 /* PREFIX_VEX_0FD9 */
4902 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
4905 /* PREFIX_VEX_0FDA */
4909 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
4912 /* PREFIX_VEX_0FDB */
4916 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
4919 /* PREFIX_VEX_0FDC */
4923 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
4926 /* PREFIX_VEX_0FDD */
4930 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
4933 /* PREFIX_VEX_0FDE */
4937 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
4940 /* PREFIX_VEX_0FDF */
4944 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
4947 /* PREFIX_VEX_0FE0 */
4951 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
4954 /* PREFIX_VEX_0FE1 */
4958 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
4961 /* PREFIX_VEX_0FE2 */
4965 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
4968 /* PREFIX_VEX_0FE3 */
4972 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
4975 /* PREFIX_VEX_0FE4 */
4979 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
4982 /* PREFIX_VEX_0FE5 */
4986 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
4989 /* PREFIX_VEX_0FE6 */
4992 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4993 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4994 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
4997 /* PREFIX_VEX_0FE7 */
5001 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5004 /* PREFIX_VEX_0FE8 */
5008 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5011 /* PREFIX_VEX_0FE9 */
5015 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5018 /* PREFIX_VEX_0FEA */
5022 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5025 /* PREFIX_VEX_0FEB */
5029 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5032 /* PREFIX_VEX_0FEC */
5036 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5039 /* PREFIX_VEX_0FED */
5043 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5046 /* PREFIX_VEX_0FEE */
5050 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5053 /* PREFIX_VEX_0FEF */
5057 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5060 /* PREFIX_VEX_0FF0 */
5065 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5068 /* PREFIX_VEX_0FF1 */
5072 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5075 /* PREFIX_VEX_0FF2 */
5079 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5082 /* PREFIX_VEX_0FF3 */
5086 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5089 /* PREFIX_VEX_0FF4 */
5093 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5096 /* PREFIX_VEX_0FF5 */
5100 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5103 /* PREFIX_VEX_0FF6 */
5107 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5110 /* PREFIX_VEX_0FF7 */
5114 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5117 /* PREFIX_VEX_0FF8 */
5121 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5124 /* PREFIX_VEX_0FF9 */
5128 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5131 /* PREFIX_VEX_0FFA */
5135 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5138 /* PREFIX_VEX_0FFB */
5142 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5145 /* PREFIX_VEX_0FFC */
5149 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5152 /* PREFIX_VEX_0FFD */
5156 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5159 /* PREFIX_VEX_0FFE */
5163 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5166 /* PREFIX_VEX_0F3800 */
5170 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5173 /* PREFIX_VEX_0F3801 */
5177 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5180 /* PREFIX_VEX_0F3802 */
5184 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5187 /* PREFIX_VEX_0F3803 */
5191 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5194 /* PREFIX_VEX_0F3804 */
5198 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5201 /* PREFIX_VEX_0F3805 */
5205 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5208 /* PREFIX_VEX_0F3806 */
5212 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5215 /* PREFIX_VEX_0F3807 */
5219 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5222 /* PREFIX_VEX_0F3808 */
5226 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5229 /* PREFIX_VEX_0F3809 */
5233 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5236 /* PREFIX_VEX_0F380A */
5240 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5243 /* PREFIX_VEX_0F380B */
5247 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5250 /* PREFIX_VEX_0F380C */
5254 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5257 /* PREFIX_VEX_0F380D */
5261 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5264 /* PREFIX_VEX_0F380E */
5268 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5271 /* PREFIX_VEX_0F380F */
5275 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5278 /* PREFIX_VEX_0F3813 */
5282 { "vcvtph2ps", { XM
, EXxmmq
} },
5285 /* PREFIX_VEX_0F3816 */
5289 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5292 /* PREFIX_VEX_0F3817 */
5296 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5299 /* PREFIX_VEX_0F3818 */
5303 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5306 /* PREFIX_VEX_0F3819 */
5310 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5313 /* PREFIX_VEX_0F381A */
5317 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5320 /* PREFIX_VEX_0F381C */
5324 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5327 /* PREFIX_VEX_0F381D */
5331 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5334 /* PREFIX_VEX_0F381E */
5338 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5341 /* PREFIX_VEX_0F3820 */
5345 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5348 /* PREFIX_VEX_0F3821 */
5352 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5355 /* PREFIX_VEX_0F3822 */
5359 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5362 /* PREFIX_VEX_0F3823 */
5366 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5369 /* PREFIX_VEX_0F3824 */
5373 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5376 /* PREFIX_VEX_0F3825 */
5380 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5383 /* PREFIX_VEX_0F3828 */
5387 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5390 /* PREFIX_VEX_0F3829 */
5394 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5397 /* PREFIX_VEX_0F382A */
5401 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5404 /* PREFIX_VEX_0F382B */
5408 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5411 /* PREFIX_VEX_0F382C */
5415 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5418 /* PREFIX_VEX_0F382D */
5422 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5425 /* PREFIX_VEX_0F382E */
5429 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5432 /* PREFIX_VEX_0F382F */
5436 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5439 /* PREFIX_VEX_0F3830 */
5443 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5446 /* PREFIX_VEX_0F3831 */
5450 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5453 /* PREFIX_VEX_0F3832 */
5457 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5460 /* PREFIX_VEX_0F3833 */
5464 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5467 /* PREFIX_VEX_0F3834 */
5471 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5474 /* PREFIX_VEX_0F3835 */
5478 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5481 /* PREFIX_VEX_0F3836 */
5485 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5488 /* PREFIX_VEX_0F3837 */
5492 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5495 /* PREFIX_VEX_0F3838 */
5499 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5502 /* PREFIX_VEX_0F3839 */
5506 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5509 /* PREFIX_VEX_0F383A */
5513 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5516 /* PREFIX_VEX_0F383B */
5520 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5523 /* PREFIX_VEX_0F383C */
5527 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5530 /* PREFIX_VEX_0F383D */
5534 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5537 /* PREFIX_VEX_0F383E */
5541 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5544 /* PREFIX_VEX_0F383F */
5548 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5551 /* PREFIX_VEX_0F3840 */
5555 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5558 /* PREFIX_VEX_0F3841 */
5562 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5565 /* PREFIX_VEX_0F3845 */
5569 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5572 /* PREFIX_VEX_0F3846 */
5576 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5579 /* PREFIX_VEX_0F3847 */
5583 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5586 /* PREFIX_VEX_0F3858 */
5590 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5593 /* PREFIX_VEX_0F3859 */
5597 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5600 /* PREFIX_VEX_0F385A */
5604 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5607 /* PREFIX_VEX_0F3878 */
5611 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5614 /* PREFIX_VEX_0F3879 */
5618 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5621 /* PREFIX_VEX_0F388C */
5625 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5628 /* PREFIX_VEX_0F388E */
5632 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5635 /* PREFIX_VEX_0F3890 */
5639 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5642 /* PREFIX_VEX_0F3891 */
5646 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5649 /* PREFIX_VEX_0F3892 */
5653 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5656 /* PREFIX_VEX_0F3893 */
5660 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5663 /* PREFIX_VEX_0F3896 */
5667 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5670 /* PREFIX_VEX_0F3897 */
5674 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5677 /* PREFIX_VEX_0F3898 */
5681 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5684 /* PREFIX_VEX_0F3899 */
5688 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5691 /* PREFIX_VEX_0F389A */
5695 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5698 /* PREFIX_VEX_0F389B */
5702 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5705 /* PREFIX_VEX_0F389C */
5709 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5712 /* PREFIX_VEX_0F389D */
5716 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5719 /* PREFIX_VEX_0F389E */
5723 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
5726 /* PREFIX_VEX_0F389F */
5730 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5733 /* PREFIX_VEX_0F38A6 */
5737 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
5741 /* PREFIX_VEX_0F38A7 */
5745 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
5748 /* PREFIX_VEX_0F38A8 */
5752 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
5755 /* PREFIX_VEX_0F38A9 */
5759 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5762 /* PREFIX_VEX_0F38AA */
5766 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
5769 /* PREFIX_VEX_0F38AB */
5773 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5776 /* PREFIX_VEX_0F38AC */
5780 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
5783 /* PREFIX_VEX_0F38AD */
5787 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5790 /* PREFIX_VEX_0F38AE */
5794 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
5797 /* PREFIX_VEX_0F38AF */
5801 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5804 /* PREFIX_VEX_0F38B6 */
5808 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
5811 /* PREFIX_VEX_0F38B7 */
5815 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
5818 /* PREFIX_VEX_0F38B8 */
5822 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
5825 /* PREFIX_VEX_0F38B9 */
5829 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5832 /* PREFIX_VEX_0F38BA */
5836 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
5839 /* PREFIX_VEX_0F38BB */
5843 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5846 /* PREFIX_VEX_0F38BC */
5850 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
5853 /* PREFIX_VEX_0F38BD */
5857 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5860 /* PREFIX_VEX_0F38BE */
5864 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
5867 /* PREFIX_VEX_0F38BF */
5871 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5874 /* PREFIX_VEX_0F38DB */
5878 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
5881 /* PREFIX_VEX_0F38DC */
5885 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
5888 /* PREFIX_VEX_0F38DD */
5892 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
5895 /* PREFIX_VEX_0F38DE */
5899 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
5902 /* PREFIX_VEX_0F38DF */
5906 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
5909 /* PREFIX_VEX_0F38F2 */
5911 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
5914 /* PREFIX_VEX_0F38F3_REG_1 */
5916 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
5919 /* PREFIX_VEX_0F38F3_REG_2 */
5921 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
5924 /* PREFIX_VEX_0F38F3_REG_3 */
5926 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
5929 /* PREFIX_VEX_0F38F5 */
5931 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
5932 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
5934 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
5937 /* PREFIX_VEX_0F38F6 */
5942 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
5945 /* PREFIX_VEX_0F38F7 */
5947 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
5948 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
5949 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
5950 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
5953 /* PREFIX_VEX_0F3A00 */
5957 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
5960 /* PREFIX_VEX_0F3A01 */
5964 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
5967 /* PREFIX_VEX_0F3A02 */
5971 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
5974 /* PREFIX_VEX_0F3A04 */
5978 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
5981 /* PREFIX_VEX_0F3A05 */
5985 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
5988 /* PREFIX_VEX_0F3A06 */
5992 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
5995 /* PREFIX_VEX_0F3A08 */
5999 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6002 /* PREFIX_VEX_0F3A09 */
6006 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6009 /* PREFIX_VEX_0F3A0A */
6013 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6016 /* PREFIX_VEX_0F3A0B */
6020 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6023 /* PREFIX_VEX_0F3A0C */
6027 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6030 /* PREFIX_VEX_0F3A0D */
6034 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6037 /* PREFIX_VEX_0F3A0E */
6041 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6044 /* PREFIX_VEX_0F3A0F */
6048 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6051 /* PREFIX_VEX_0F3A14 */
6055 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6058 /* PREFIX_VEX_0F3A15 */
6062 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6065 /* PREFIX_VEX_0F3A16 */
6069 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6072 /* PREFIX_VEX_0F3A17 */
6076 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6079 /* PREFIX_VEX_0F3A18 */
6083 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6086 /* PREFIX_VEX_0F3A19 */
6090 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6093 /* PREFIX_VEX_0F3A1D */
6097 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6100 /* PREFIX_VEX_0F3A20 */
6104 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6107 /* PREFIX_VEX_0F3A21 */
6111 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6114 /* PREFIX_VEX_0F3A22 */
6118 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6121 /* PREFIX_VEX_0F3A30 */
6125 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6128 /* PREFIX_VEX_0F3A32 */
6132 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6135 /* PREFIX_VEX_0F3A38 */
6139 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6142 /* PREFIX_VEX_0F3A39 */
6146 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6149 /* PREFIX_VEX_0F3A40 */
6153 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6156 /* PREFIX_VEX_0F3A41 */
6160 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6163 /* PREFIX_VEX_0F3A42 */
6167 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6170 /* PREFIX_VEX_0F3A44 */
6174 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6177 /* PREFIX_VEX_0F3A46 */
6181 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6184 /* PREFIX_VEX_0F3A48 */
6188 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6191 /* PREFIX_VEX_0F3A49 */
6195 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6198 /* PREFIX_VEX_0F3A4A */
6202 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6205 /* PREFIX_VEX_0F3A4B */
6209 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6212 /* PREFIX_VEX_0F3A4C */
6216 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6219 /* PREFIX_VEX_0F3A5C */
6223 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6226 /* PREFIX_VEX_0F3A5D */
6230 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6233 /* PREFIX_VEX_0F3A5E */
6237 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6240 /* PREFIX_VEX_0F3A5F */
6244 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6247 /* PREFIX_VEX_0F3A60 */
6251 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6255 /* PREFIX_VEX_0F3A61 */
6259 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6262 /* PREFIX_VEX_0F3A62 */
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6269 /* PREFIX_VEX_0F3A63 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6276 /* PREFIX_VEX_0F3A68 */
6280 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6283 /* PREFIX_VEX_0F3A69 */
6287 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6290 /* PREFIX_VEX_0F3A6A */
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6297 /* PREFIX_VEX_0F3A6B */
6301 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6304 /* PREFIX_VEX_0F3A6C */
6308 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6311 /* PREFIX_VEX_0F3A6D */
6315 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6318 /* PREFIX_VEX_0F3A6E */
6322 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6325 /* PREFIX_VEX_0F3A6F */
6329 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6332 /* PREFIX_VEX_0F3A78 */
6336 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6339 /* PREFIX_VEX_0F3A79 */
6343 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6346 /* PREFIX_VEX_0F3A7A */
6350 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6353 /* PREFIX_VEX_0F3A7B */
6357 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6360 /* PREFIX_VEX_0F3A7C */
6364 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6368 /* PREFIX_VEX_0F3A7D */
6372 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6375 /* PREFIX_VEX_0F3A7E */
6379 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6382 /* PREFIX_VEX_0F3A7F */
6386 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6389 /* PREFIX_VEX_0F3ADF */
6393 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6396 /* PREFIX_VEX_0F3AF0 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6404 #define NEED_PREFIX_TABLE
6405 #include "i386-dis-evex.h"
6406 #undef NEED_PREFIX_TABLE
6409 static const struct dis386 x86_64_table
[][2] = {
6412 { "pushP", { es
} },
6422 { "pushP", { cs
} },
6427 { "pushP", { ss
} },
6437 { "pushP", { ds
} },
6467 { "pushaP", { XX
} },
6472 { "popaP", { XX
} },
6477 { MOD_TABLE (MOD_62_32BIT
) },
6478 { EVEX_TABLE (EVEX_0F
) },
6483 { "arpl", { Ew
, Gw
} },
6484 { "movs{lq|xd}", { Gv
, Ed
} },
6489 { "ins{R|}", { Yzr
, indirDX
} },
6490 { "ins{G|}", { Yzr
, indirDX
} },
6495 { "outs{R|}", { indirDXr
, Xz
} },
6496 { "outs{G|}", { indirDXr
, Xz
} },
6501 { "Jcall{T|}", { Ap
} },
6506 { MOD_TABLE (MOD_C4_32BIT
) },
6507 { VEX_C4_TABLE (VEX_0F
) },
6512 { MOD_TABLE (MOD_C5_32BIT
) },
6513 { VEX_C5_TABLE (VEX_0F
) },
6533 { "Jjmp{T|}", { Ap
} },
6536 /* X86_64_0F01_REG_0 */
6538 { "sgdt{Q|IQ}", { M
} },
6542 /* X86_64_0F01_REG_1 */
6544 { "sidt{Q|IQ}", { M
} },
6548 /* X86_64_0F01_REG_2 */
6550 { "lgdt{Q|Q}", { M
} },
6554 /* X86_64_0F01_REG_3 */
6556 { "lidt{Q|Q}", { M
} },
6561 static const struct dis386 three_byte_table
[][256] = {
6563 /* THREE_BYTE_0F38 */
6566 { "pshufb", { MX
, EM
} },
6567 { "phaddw", { MX
, EM
} },
6568 { "phaddd", { MX
, EM
} },
6569 { "phaddsw", { MX
, EM
} },
6570 { "pmaddubsw", { MX
, EM
} },
6571 { "phsubw", { MX
, EM
} },
6572 { "phsubd", { MX
, EM
} },
6573 { "phsubsw", { MX
, EM
} },
6575 { "psignb", { MX
, EM
} },
6576 { "psignw", { MX
, EM
} },
6577 { "psignd", { MX
, EM
} },
6578 { "pmulhrsw", { MX
, EM
} },
6584 { PREFIX_TABLE (PREFIX_0F3810
) },
6588 { PREFIX_TABLE (PREFIX_0F3814
) },
6589 { PREFIX_TABLE (PREFIX_0F3815
) },
6591 { PREFIX_TABLE (PREFIX_0F3817
) },
6597 { "pabsb", { MX
, EM
} },
6598 { "pabsw", { MX
, EM
} },
6599 { "pabsd", { MX
, EM
} },
6602 { PREFIX_TABLE (PREFIX_0F3820
) },
6603 { PREFIX_TABLE (PREFIX_0F3821
) },
6604 { PREFIX_TABLE (PREFIX_0F3822
) },
6605 { PREFIX_TABLE (PREFIX_0F3823
) },
6606 { PREFIX_TABLE (PREFIX_0F3824
) },
6607 { PREFIX_TABLE (PREFIX_0F3825
) },
6611 { PREFIX_TABLE (PREFIX_0F3828
) },
6612 { PREFIX_TABLE (PREFIX_0F3829
) },
6613 { PREFIX_TABLE (PREFIX_0F382A
) },
6614 { PREFIX_TABLE (PREFIX_0F382B
) },
6620 { PREFIX_TABLE (PREFIX_0F3830
) },
6621 { PREFIX_TABLE (PREFIX_0F3831
) },
6622 { PREFIX_TABLE (PREFIX_0F3832
) },
6623 { PREFIX_TABLE (PREFIX_0F3833
) },
6624 { PREFIX_TABLE (PREFIX_0F3834
) },
6625 { PREFIX_TABLE (PREFIX_0F3835
) },
6627 { PREFIX_TABLE (PREFIX_0F3837
) },
6629 { PREFIX_TABLE (PREFIX_0F3838
) },
6630 { PREFIX_TABLE (PREFIX_0F3839
) },
6631 { PREFIX_TABLE (PREFIX_0F383A
) },
6632 { PREFIX_TABLE (PREFIX_0F383B
) },
6633 { PREFIX_TABLE (PREFIX_0F383C
) },
6634 { PREFIX_TABLE (PREFIX_0F383D
) },
6635 { PREFIX_TABLE (PREFIX_0F383E
) },
6636 { PREFIX_TABLE (PREFIX_0F383F
) },
6638 { PREFIX_TABLE (PREFIX_0F3840
) },
6639 { PREFIX_TABLE (PREFIX_0F3841
) },
6710 { PREFIX_TABLE (PREFIX_0F3880
) },
6711 { PREFIX_TABLE (PREFIX_0F3881
) },
6712 { PREFIX_TABLE (PREFIX_0F3882
) },
6791 { PREFIX_TABLE (PREFIX_0F38C8
) },
6792 { PREFIX_TABLE (PREFIX_0F38C9
) },
6793 { PREFIX_TABLE (PREFIX_0F38CA
) },
6794 { PREFIX_TABLE (PREFIX_0F38CB
) },
6795 { PREFIX_TABLE (PREFIX_0F38CC
) },
6796 { PREFIX_TABLE (PREFIX_0F38CD
) },
6812 { PREFIX_TABLE (PREFIX_0F38DB
) },
6813 { PREFIX_TABLE (PREFIX_0F38DC
) },
6814 { PREFIX_TABLE (PREFIX_0F38DD
) },
6815 { PREFIX_TABLE (PREFIX_0F38DE
) },
6816 { PREFIX_TABLE (PREFIX_0F38DF
) },
6836 { PREFIX_TABLE (PREFIX_0F38F0
) },
6837 { PREFIX_TABLE (PREFIX_0F38F1
) },
6842 { PREFIX_TABLE (PREFIX_0F38F6
) },
6854 /* THREE_BYTE_0F3A */
6866 { PREFIX_TABLE (PREFIX_0F3A08
) },
6867 { PREFIX_TABLE (PREFIX_0F3A09
) },
6868 { PREFIX_TABLE (PREFIX_0F3A0A
) },
6869 { PREFIX_TABLE (PREFIX_0F3A0B
) },
6870 { PREFIX_TABLE (PREFIX_0F3A0C
) },
6871 { PREFIX_TABLE (PREFIX_0F3A0D
) },
6872 { PREFIX_TABLE (PREFIX_0F3A0E
) },
6873 { "palignr", { MX
, EM
, Ib
} },
6879 { PREFIX_TABLE (PREFIX_0F3A14
) },
6880 { PREFIX_TABLE (PREFIX_0F3A15
) },
6881 { PREFIX_TABLE (PREFIX_0F3A16
) },
6882 { PREFIX_TABLE (PREFIX_0F3A17
) },
6893 { PREFIX_TABLE (PREFIX_0F3A20
) },
6894 { PREFIX_TABLE (PREFIX_0F3A21
) },
6895 { PREFIX_TABLE (PREFIX_0F3A22
) },
6929 { PREFIX_TABLE (PREFIX_0F3A40
) },
6930 { PREFIX_TABLE (PREFIX_0F3A41
) },
6931 { PREFIX_TABLE (PREFIX_0F3A42
) },
6933 { PREFIX_TABLE (PREFIX_0F3A44
) },
6965 { PREFIX_TABLE (PREFIX_0F3A60
) },
6966 { PREFIX_TABLE (PREFIX_0F3A61
) },
6967 { PREFIX_TABLE (PREFIX_0F3A62
) },
6968 { PREFIX_TABLE (PREFIX_0F3A63
) },
7086 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7107 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7146 /* THREE_BYTE_0F7A */
7185 { "ptest", { XX
} },
7222 { "phaddbw", { XM
, EXq
} },
7223 { "phaddbd", { XM
, EXq
} },
7224 { "phaddbq", { XM
, EXq
} },
7227 { "phaddwd", { XM
, EXq
} },
7228 { "phaddwq", { XM
, EXq
} },
7233 { "phadddq", { XM
, EXq
} },
7240 { "phaddubw", { XM
, EXq
} },
7241 { "phaddubd", { XM
, EXq
} },
7242 { "phaddubq", { XM
, EXq
} },
7245 { "phadduwd", { XM
, EXq
} },
7246 { "phadduwq", { XM
, EXq
} },
7251 { "phaddudq", { XM
, EXq
} },
7258 { "phsubbw", { XM
, EXq
} },
7259 { "phsubbd", { XM
, EXq
} },
7260 { "phsubbq", { XM
, EXq
} },
7439 static const struct dis386 xop_table
[][256] = {
7592 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7593 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7594 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7602 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7603 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7610 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7611 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7612 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7620 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7621 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7625 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7626 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7629 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7647 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7659 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7660 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7661 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7662 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7672 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7673 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7674 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7675 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7708 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7709 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7710 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7711 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7735 { REG_TABLE (REG_XOP_TBM_01
) },
7736 { REG_TABLE (REG_XOP_TBM_02
) },
7754 { REG_TABLE (REG_XOP_LWPCB
) },
7878 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7879 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7880 { "vfrczss", { XM
, EXd
} },
7881 { "vfrczsd", { XM
, EXq
} },
7896 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7897 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7898 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
7899 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7900 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7901 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7902 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
7903 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7905 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
7906 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7907 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
7908 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7951 { "vphaddbw", { XM
, EXxmm
} },
7952 { "vphaddbd", { XM
, EXxmm
} },
7953 { "vphaddbq", { XM
, EXxmm
} },
7956 { "vphaddwd", { XM
, EXxmm
} },
7957 { "vphaddwq", { XM
, EXxmm
} },
7962 { "vphadddq", { XM
, EXxmm
} },
7969 { "vphaddubw", { XM
, EXxmm
} },
7970 { "vphaddubd", { XM
, EXxmm
} },
7971 { "vphaddubq", { XM
, EXxmm
} },
7974 { "vphadduwd", { XM
, EXxmm
} },
7975 { "vphadduwq", { XM
, EXxmm
} },
7980 { "vphaddudq", { XM
, EXxmm
} },
7987 { "vphsubbw", { XM
, EXxmm
} },
7988 { "vphsubwd", { XM
, EXxmm
} },
7989 { "vphsubdq", { XM
, EXxmm
} },
8043 { "bextr", { Gv
, Ev
, Iq
} },
8045 { REG_TABLE (REG_XOP_LWP
) },
8315 static const struct dis386 vex_table
[][256] = {
8337 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8338 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8339 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8340 { MOD_TABLE (MOD_VEX_0F13
) },
8341 { VEX_W_TABLE (VEX_W_0F14
) },
8342 { VEX_W_TABLE (VEX_W_0F15
) },
8343 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8344 { MOD_TABLE (MOD_VEX_0F17
) },
8364 { VEX_W_TABLE (VEX_W_0F28
) },
8365 { VEX_W_TABLE (VEX_W_0F29
) },
8366 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8367 { MOD_TABLE (MOD_VEX_0F2B
) },
8368 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8369 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8370 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8371 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8392 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8393 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8395 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8396 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8403 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8409 { MOD_TABLE (MOD_VEX_0F50
) },
8410 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8411 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8412 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8413 { "vandpX", { XM
, Vex
, EXx
} },
8414 { "vandnpX", { XM
, Vex
, EXx
} },
8415 { "vorpX", { XM
, Vex
, EXx
} },
8416 { "vxorpX", { XM
, Vex
, EXx
} },
8418 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8420 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8422 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8433 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8440 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8442 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8446 { REG_TABLE (REG_VEX_0F71
) },
8447 { REG_TABLE (REG_VEX_0F72
) },
8448 { REG_TABLE (REG_VEX_0F73
) },
8449 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8450 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8451 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8460 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8461 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8514 { REG_TABLE (REG_VEX_0FAE
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8541 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8553 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8883 { REG_TABLE (REG_VEX_0F38F3
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9191 #define NEED_OPCODE_TABLE
9192 #include "i386-dis-evex.h"
9193 #undef NEED_OPCODE_TABLE
9194 static const struct dis386 vex_len_table
[][2] = {
9195 /* VEX_LEN_0F10_P_1 */
9197 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9198 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9201 /* VEX_LEN_0F10_P_3 */
9203 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9204 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9207 /* VEX_LEN_0F11_P_1 */
9209 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9210 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9213 /* VEX_LEN_0F11_P_3 */
9215 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9216 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9219 /* VEX_LEN_0F12_P_0_M_0 */
9221 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9224 /* VEX_LEN_0F12_P_0_M_1 */
9226 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9229 /* VEX_LEN_0F12_P_2 */
9231 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9234 /* VEX_LEN_0F13_M_0 */
9236 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9239 /* VEX_LEN_0F16_P_0_M_0 */
9241 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9244 /* VEX_LEN_0F16_P_0_M_1 */
9246 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9249 /* VEX_LEN_0F16_P_2 */
9251 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9254 /* VEX_LEN_0F17_M_0 */
9256 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9259 /* VEX_LEN_0F2A_P_1 */
9261 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9262 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9265 /* VEX_LEN_0F2A_P_3 */
9267 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9268 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9271 /* VEX_LEN_0F2C_P_1 */
9273 { "vcvttss2siY", { Gv
, EXdScalar
} },
9274 { "vcvttss2siY", { Gv
, EXdScalar
} },
9277 /* VEX_LEN_0F2C_P_3 */
9279 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9280 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9283 /* VEX_LEN_0F2D_P_1 */
9285 { "vcvtss2siY", { Gv
, EXdScalar
} },
9286 { "vcvtss2siY", { Gv
, EXdScalar
} },
9289 /* VEX_LEN_0F2D_P_3 */
9291 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9292 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9295 /* VEX_LEN_0F2E_P_0 */
9297 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9298 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9301 /* VEX_LEN_0F2E_P_2 */
9303 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9304 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9307 /* VEX_LEN_0F2F_P_0 */
9309 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9310 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9313 /* VEX_LEN_0F2F_P_2 */
9315 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9316 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9319 /* VEX_LEN_0F41_P_0 */
9322 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9324 /* VEX_LEN_0F42_P_0 */
9327 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9329 /* VEX_LEN_0F44_P_0 */
9331 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9333 /* VEX_LEN_0F45_P_0 */
9336 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9338 /* VEX_LEN_0F46_P_0 */
9341 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9343 /* VEX_LEN_0F47_P_0 */
9346 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9348 /* VEX_LEN_0F4B_P_2 */
9351 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9354 /* VEX_LEN_0F51_P_1 */
9356 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9357 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9360 /* VEX_LEN_0F51_P_3 */
9362 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9363 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9366 /* VEX_LEN_0F52_P_1 */
9368 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9369 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9372 /* VEX_LEN_0F53_P_1 */
9374 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9375 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9378 /* VEX_LEN_0F58_P_1 */
9380 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9381 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9384 /* VEX_LEN_0F58_P_3 */
9386 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9387 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9390 /* VEX_LEN_0F59_P_1 */
9392 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9393 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9396 /* VEX_LEN_0F59_P_3 */
9398 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9399 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9402 /* VEX_LEN_0F5A_P_1 */
9404 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9405 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9408 /* VEX_LEN_0F5A_P_3 */
9410 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9411 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9414 /* VEX_LEN_0F5C_P_1 */
9416 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9417 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9420 /* VEX_LEN_0F5C_P_3 */
9422 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9423 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9426 /* VEX_LEN_0F5D_P_1 */
9428 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9429 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9432 /* VEX_LEN_0F5D_P_3 */
9434 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9435 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9438 /* VEX_LEN_0F5E_P_1 */
9440 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9441 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9444 /* VEX_LEN_0F5E_P_3 */
9446 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9447 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9450 /* VEX_LEN_0F5F_P_1 */
9452 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9453 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9456 /* VEX_LEN_0F5F_P_3 */
9458 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9459 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9462 /* VEX_LEN_0F6E_P_2 */
9464 { "vmovK", { XMScalar
, Edq
} },
9465 { "vmovK", { XMScalar
, Edq
} },
9468 /* VEX_LEN_0F7E_P_1 */
9470 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9471 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9474 /* VEX_LEN_0F7E_P_2 */
9476 { "vmovK", { Edq
, XMScalar
} },
9477 { "vmovK", { Edq
, XMScalar
} },
9480 /* VEX_LEN_0F90_P_0 */
9482 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9485 /* VEX_LEN_0F91_P_0 */
9487 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9490 /* VEX_LEN_0F92_P_0 */
9492 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9495 /* VEX_LEN_0F93_P_0 */
9497 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9500 /* VEX_LEN_0F98_P_0 */
9502 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9505 /* VEX_LEN_0FAE_R_2_M_0 */
9507 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9510 /* VEX_LEN_0FAE_R_3_M_0 */
9512 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9515 /* VEX_LEN_0FC2_P_1 */
9517 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9518 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9521 /* VEX_LEN_0FC2_P_3 */
9523 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9524 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9527 /* VEX_LEN_0FC4_P_2 */
9529 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9532 /* VEX_LEN_0FC5_P_2 */
9534 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9537 /* VEX_LEN_0FD6_P_2 */
9539 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9540 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9543 /* VEX_LEN_0FF7_P_2 */
9545 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9548 /* VEX_LEN_0F3816_P_2 */
9551 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9554 /* VEX_LEN_0F3819_P_2 */
9557 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9560 /* VEX_LEN_0F381A_P_2_M_0 */
9563 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9566 /* VEX_LEN_0F3836_P_2 */
9569 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9572 /* VEX_LEN_0F3841_P_2 */
9574 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9577 /* VEX_LEN_0F385A_P_2_M_0 */
9580 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9583 /* VEX_LEN_0F38DB_P_2 */
9585 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9588 /* VEX_LEN_0F38DC_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9593 /* VEX_LEN_0F38DD_P_2 */
9595 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9598 /* VEX_LEN_0F38DE_P_2 */
9600 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9603 /* VEX_LEN_0F38DF_P_2 */
9605 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9608 /* VEX_LEN_0F38F2_P_0 */
9610 { "andnS", { Gdq
, VexGdq
, Edq
} },
9613 /* VEX_LEN_0F38F3_R_1_P_0 */
9615 { "blsrS", { VexGdq
, Edq
} },
9618 /* VEX_LEN_0F38F3_R_2_P_0 */
9620 { "blsmskS", { VexGdq
, Edq
} },
9623 /* VEX_LEN_0F38F3_R_3_P_0 */
9625 { "blsiS", { VexGdq
, Edq
} },
9628 /* VEX_LEN_0F38F5_P_0 */
9630 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
9633 /* VEX_LEN_0F38F5_P_1 */
9635 { "pextS", { Gdq
, VexGdq
, Edq
} },
9638 /* VEX_LEN_0F38F5_P_3 */
9640 { "pdepS", { Gdq
, VexGdq
, Edq
} },
9643 /* VEX_LEN_0F38F6_P_3 */
9645 { "mulxS", { Gdq
, VexGdq
, Edq
} },
9648 /* VEX_LEN_0F38F7_P_0 */
9650 { "bextrS", { Gdq
, Edq
, VexGdq
} },
9653 /* VEX_LEN_0F38F7_P_1 */
9655 { "sarxS", { Gdq
, Edq
, VexGdq
} },
9658 /* VEX_LEN_0F38F7_P_2 */
9660 { "shlxS", { Gdq
, Edq
, VexGdq
} },
9663 /* VEX_LEN_0F38F7_P_3 */
9665 { "shrxS", { Gdq
, Edq
, VexGdq
} },
9668 /* VEX_LEN_0F3A00_P_2 */
9671 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9674 /* VEX_LEN_0F3A01_P_2 */
9677 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9680 /* VEX_LEN_0F3A06_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9686 /* VEX_LEN_0F3A0A_P_2 */
9688 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9689 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9692 /* VEX_LEN_0F3A0B_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9695 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9698 /* VEX_LEN_0F3A14_P_2 */
9700 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9703 /* VEX_LEN_0F3A15_P_2 */
9705 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9708 /* VEX_LEN_0F3A16_P_2 */
9710 { "vpextrK", { Edq
, XM
, Ib
} },
9713 /* VEX_LEN_0F3A17_P_2 */
9715 { "vextractps", { Edqd
, XM
, Ib
} },
9718 /* VEX_LEN_0F3A18_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9724 /* VEX_LEN_0F3A19_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9730 /* VEX_LEN_0F3A20_P_2 */
9732 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9735 /* VEX_LEN_0F3A21_P_2 */
9737 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9740 /* VEX_LEN_0F3A22_P_2 */
9742 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9745 /* VEX_LEN_0F3A30_P_2 */
9747 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9750 /* VEX_LEN_0F3A32_P_2 */
9752 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9755 /* VEX_LEN_0F3A38_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9761 /* VEX_LEN_0F3A39_P_2 */
9764 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9767 /* VEX_LEN_0F3A41_P_2 */
9769 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9772 /* VEX_LEN_0F3A44_P_2 */
9774 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9777 /* VEX_LEN_0F3A46_P_2 */
9780 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9783 /* VEX_LEN_0F3A60_P_2 */
9785 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9788 /* VEX_LEN_0F3A61_P_2 */
9790 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9793 /* VEX_LEN_0F3A62_P_2 */
9795 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9798 /* VEX_LEN_0F3A63_P_2 */
9800 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9803 /* VEX_LEN_0F3A6A_P_2 */
9805 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9808 /* VEX_LEN_0F3A6B_P_2 */
9810 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9813 /* VEX_LEN_0F3A6E_P_2 */
9815 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9818 /* VEX_LEN_0F3A6F_P_2 */
9820 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9823 /* VEX_LEN_0F3A7A_P_2 */
9825 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9828 /* VEX_LEN_0F3A7B_P_2 */
9830 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9833 /* VEX_LEN_0F3A7E_P_2 */
9835 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9838 /* VEX_LEN_0F3A7F_P_2 */
9840 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9843 /* VEX_LEN_0F3ADF_P_2 */
9845 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9848 /* VEX_LEN_0F3AF0_P_3 */
9850 { "rorxS", { Gdq
, Edq
, Ib
} },
9853 /* VEX_LEN_0FXOP_08_CC */
9855 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
9858 /* VEX_LEN_0FXOP_08_CD */
9860 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
9863 /* VEX_LEN_0FXOP_08_CE */
9865 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
9868 /* VEX_LEN_0FXOP_08_CF */
9870 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
9873 /* VEX_LEN_0FXOP_08_EC */
9875 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
9878 /* VEX_LEN_0FXOP_08_ED */
9880 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
9883 /* VEX_LEN_0FXOP_08_EE */
9885 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
9888 /* VEX_LEN_0FXOP_08_EF */
9890 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
9893 /* VEX_LEN_0FXOP_09_80 */
9895 { "vfrczps", { XM
, EXxmm
} },
9896 { "vfrczps", { XM
, EXymmq
} },
9899 /* VEX_LEN_0FXOP_09_81 */
9901 { "vfrczpd", { XM
, EXxmm
} },
9902 { "vfrczpd", { XM
, EXymmq
} },
9906 static const struct dis386 vex_w_table
[][2] = {
9908 /* VEX_W_0F10_P_0 */
9909 { "vmovups", { XM
, EXx
} },
9912 /* VEX_W_0F10_P_1 */
9913 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9916 /* VEX_W_0F10_P_2 */
9917 { "vmovupd", { XM
, EXx
} },
9920 /* VEX_W_0F10_P_3 */
9921 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9924 /* VEX_W_0F11_P_0 */
9925 { "vmovups", { EXxS
, XM
} },
9928 /* VEX_W_0F11_P_1 */
9929 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9932 /* VEX_W_0F11_P_2 */
9933 { "vmovupd", { EXxS
, XM
} },
9936 /* VEX_W_0F11_P_3 */
9937 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9940 /* VEX_W_0F12_P_0_M_0 */
9941 { "vmovlps", { XM
, Vex128
, EXq
} },
9944 /* VEX_W_0F12_P_0_M_1 */
9945 { "vmovhlps", { XM
, Vex128
, EXq
} },
9948 /* VEX_W_0F12_P_1 */
9949 { "vmovsldup", { XM
, EXx
} },
9952 /* VEX_W_0F12_P_2 */
9953 { "vmovlpd", { XM
, Vex128
, EXq
} },
9956 /* VEX_W_0F12_P_3 */
9957 { "vmovddup", { XM
, EXymmq
} },
9960 /* VEX_W_0F13_M_0 */
9961 { "vmovlpX", { EXq
, XM
} },
9965 { "vunpcklpX", { XM
, Vex
, EXx
} },
9969 { "vunpckhpX", { XM
, Vex
, EXx
} },
9972 /* VEX_W_0F16_P_0_M_0 */
9973 { "vmovhps", { XM
, Vex128
, EXq
} },
9976 /* VEX_W_0F16_P_0_M_1 */
9977 { "vmovlhps", { XM
, Vex128
, EXq
} },
9980 /* VEX_W_0F16_P_1 */
9981 { "vmovshdup", { XM
, EXx
} },
9984 /* VEX_W_0F16_P_2 */
9985 { "vmovhpd", { XM
, Vex128
, EXq
} },
9988 /* VEX_W_0F17_M_0 */
9989 { "vmovhpX", { EXq
, XM
} },
9993 { "vmovapX", { XM
, EXx
} },
9997 { "vmovapX", { EXxS
, XM
} },
10000 /* VEX_W_0F2B_M_0 */
10001 { "vmovntpX", { Mx
, XM
} },
10004 /* VEX_W_0F2E_P_0 */
10005 { "vucomiss", { XMScalar
, EXdScalar
} },
10008 /* VEX_W_0F2E_P_2 */
10009 { "vucomisd", { XMScalar
, EXqScalar
} },
10012 /* VEX_W_0F2F_P_0 */
10013 { "vcomiss", { XMScalar
, EXdScalar
} },
10016 /* VEX_W_0F2F_P_2 */
10017 { "vcomisd", { XMScalar
, EXqScalar
} },
10020 /* VEX_W_0F41_P_0_LEN_1 */
10021 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10024 /* VEX_W_0F42_P_0_LEN_1 */
10025 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10028 /* VEX_W_0F44_P_0_LEN_0 */
10029 { "knotw", { MaskG
, MaskR
} },
10032 /* VEX_W_0F45_P_0_LEN_1 */
10033 { "korw", { MaskG
, MaskVex
, MaskR
} },
10036 /* VEX_W_0F46_P_0_LEN_1 */
10037 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10040 /* VEX_W_0F47_P_0_LEN_1 */
10041 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10044 /* VEX_W_0F4B_P_2_LEN_1 */
10045 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10048 /* VEX_W_0F50_M_0 */
10049 { "vmovmskpX", { Gdq
, XS
} },
10052 /* VEX_W_0F51_P_0 */
10053 { "vsqrtps", { XM
, EXx
} },
10056 /* VEX_W_0F51_P_1 */
10057 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10060 /* VEX_W_0F51_P_2 */
10061 { "vsqrtpd", { XM
, EXx
} },
10064 /* VEX_W_0F51_P_3 */
10065 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10068 /* VEX_W_0F52_P_0 */
10069 { "vrsqrtps", { XM
, EXx
} },
10072 /* VEX_W_0F52_P_1 */
10073 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10076 /* VEX_W_0F53_P_0 */
10077 { "vrcpps", { XM
, EXx
} },
10080 /* VEX_W_0F53_P_1 */
10081 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10084 /* VEX_W_0F58_P_0 */
10085 { "vaddps", { XM
, Vex
, EXx
} },
10088 /* VEX_W_0F58_P_1 */
10089 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10092 /* VEX_W_0F58_P_2 */
10093 { "vaddpd", { XM
, Vex
, EXx
} },
10096 /* VEX_W_0F58_P_3 */
10097 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10100 /* VEX_W_0F59_P_0 */
10101 { "vmulps", { XM
, Vex
, EXx
} },
10104 /* VEX_W_0F59_P_1 */
10105 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10108 /* VEX_W_0F59_P_2 */
10109 { "vmulpd", { XM
, Vex
, EXx
} },
10112 /* VEX_W_0F59_P_3 */
10113 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10116 /* VEX_W_0F5A_P_0 */
10117 { "vcvtps2pd", { XM
, EXxmmq
} },
10120 /* VEX_W_0F5A_P_1 */
10121 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10124 /* VEX_W_0F5A_P_3 */
10125 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10128 /* VEX_W_0F5B_P_0 */
10129 { "vcvtdq2ps", { XM
, EXx
} },
10132 /* VEX_W_0F5B_P_1 */
10133 { "vcvttps2dq", { XM
, EXx
} },
10136 /* VEX_W_0F5B_P_2 */
10137 { "vcvtps2dq", { XM
, EXx
} },
10140 /* VEX_W_0F5C_P_0 */
10141 { "vsubps", { XM
, Vex
, EXx
} },
10144 /* VEX_W_0F5C_P_1 */
10145 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10148 /* VEX_W_0F5C_P_2 */
10149 { "vsubpd", { XM
, Vex
, EXx
} },
10152 /* VEX_W_0F5C_P_3 */
10153 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10156 /* VEX_W_0F5D_P_0 */
10157 { "vminps", { XM
, Vex
, EXx
} },
10160 /* VEX_W_0F5D_P_1 */
10161 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10164 /* VEX_W_0F5D_P_2 */
10165 { "vminpd", { XM
, Vex
, EXx
} },
10168 /* VEX_W_0F5D_P_3 */
10169 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10172 /* VEX_W_0F5E_P_0 */
10173 { "vdivps", { XM
, Vex
, EXx
} },
10176 /* VEX_W_0F5E_P_1 */
10177 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10180 /* VEX_W_0F5E_P_2 */
10181 { "vdivpd", { XM
, Vex
, EXx
} },
10184 /* VEX_W_0F5E_P_3 */
10185 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10188 /* VEX_W_0F5F_P_0 */
10189 { "vmaxps", { XM
, Vex
, EXx
} },
10192 /* VEX_W_0F5F_P_1 */
10193 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10196 /* VEX_W_0F5F_P_2 */
10197 { "vmaxpd", { XM
, Vex
, EXx
} },
10200 /* VEX_W_0F5F_P_3 */
10201 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10204 /* VEX_W_0F60_P_2 */
10205 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10208 /* VEX_W_0F61_P_2 */
10209 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10212 /* VEX_W_0F62_P_2 */
10213 { "vpunpckldq", { XM
, Vex
, EXx
} },
10216 /* VEX_W_0F63_P_2 */
10217 { "vpacksswb", { XM
, Vex
, EXx
} },
10220 /* VEX_W_0F64_P_2 */
10221 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10224 /* VEX_W_0F65_P_2 */
10225 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10228 /* VEX_W_0F66_P_2 */
10229 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10232 /* VEX_W_0F67_P_2 */
10233 { "vpackuswb", { XM
, Vex
, EXx
} },
10236 /* VEX_W_0F68_P_2 */
10237 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10240 /* VEX_W_0F69_P_2 */
10241 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10244 /* VEX_W_0F6A_P_2 */
10245 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10248 /* VEX_W_0F6B_P_2 */
10249 { "vpackssdw", { XM
, Vex
, EXx
} },
10252 /* VEX_W_0F6C_P_2 */
10253 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10256 /* VEX_W_0F6D_P_2 */
10257 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10260 /* VEX_W_0F6F_P_1 */
10261 { "vmovdqu", { XM
, EXx
} },
10264 /* VEX_W_0F6F_P_2 */
10265 { "vmovdqa", { XM
, EXx
} },
10268 /* VEX_W_0F70_P_1 */
10269 { "vpshufhw", { XM
, EXx
, Ib
} },
10272 /* VEX_W_0F70_P_2 */
10273 { "vpshufd", { XM
, EXx
, Ib
} },
10276 /* VEX_W_0F70_P_3 */
10277 { "vpshuflw", { XM
, EXx
, Ib
} },
10280 /* VEX_W_0F71_R_2_P_2 */
10281 { "vpsrlw", { Vex
, XS
, Ib
} },
10284 /* VEX_W_0F71_R_4_P_2 */
10285 { "vpsraw", { Vex
, XS
, Ib
} },
10288 /* VEX_W_0F71_R_6_P_2 */
10289 { "vpsllw", { Vex
, XS
, Ib
} },
10292 /* VEX_W_0F72_R_2_P_2 */
10293 { "vpsrld", { Vex
, XS
, Ib
} },
10296 /* VEX_W_0F72_R_4_P_2 */
10297 { "vpsrad", { Vex
, XS
, Ib
} },
10300 /* VEX_W_0F72_R_6_P_2 */
10301 { "vpslld", { Vex
, XS
, Ib
} },
10304 /* VEX_W_0F73_R_2_P_2 */
10305 { "vpsrlq", { Vex
, XS
, Ib
} },
10308 /* VEX_W_0F73_R_3_P_2 */
10309 { "vpsrldq", { Vex
, XS
, Ib
} },
10312 /* VEX_W_0F73_R_6_P_2 */
10313 { "vpsllq", { Vex
, XS
, Ib
} },
10316 /* VEX_W_0F73_R_7_P_2 */
10317 { "vpslldq", { Vex
, XS
, Ib
} },
10320 /* VEX_W_0F74_P_2 */
10321 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10324 /* VEX_W_0F75_P_2 */
10325 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10328 /* VEX_W_0F76_P_2 */
10329 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10332 /* VEX_W_0F77_P_0 */
10336 /* VEX_W_0F7C_P_2 */
10337 { "vhaddpd", { XM
, Vex
, EXx
} },
10340 /* VEX_W_0F7C_P_3 */
10341 { "vhaddps", { XM
, Vex
, EXx
} },
10344 /* VEX_W_0F7D_P_2 */
10345 { "vhsubpd", { XM
, Vex
, EXx
} },
10348 /* VEX_W_0F7D_P_3 */
10349 { "vhsubps", { XM
, Vex
, EXx
} },
10352 /* VEX_W_0F7E_P_1 */
10353 { "vmovq", { XMScalar
, EXqScalar
} },
10356 /* VEX_W_0F7F_P_1 */
10357 { "vmovdqu", { EXxS
, XM
} },
10360 /* VEX_W_0F7F_P_2 */
10361 { "vmovdqa", { EXxS
, XM
} },
10364 /* VEX_W_0F90_P_0_LEN_0 */
10365 { "kmovw", { MaskG
, MaskE
} },
10368 /* VEX_W_0F91_P_0_LEN_0 */
10369 { "kmovw", { Ew
, MaskG
} },
10372 /* VEX_W_0F92_P_0_LEN_0 */
10373 { "kmovw", { MaskG
, Rdq
} },
10376 /* VEX_W_0F93_P_0_LEN_0 */
10377 { "kmovw", { Gdq
, MaskR
} },
10380 /* VEX_W_0F98_P_0_LEN_0 */
10381 { "kortestw", { MaskG
, MaskR
} },
10384 /* VEX_W_0FAE_R_2_M_0 */
10385 { "vldmxcsr", { Md
} },
10388 /* VEX_W_0FAE_R_3_M_0 */
10389 { "vstmxcsr", { Md
} },
10392 /* VEX_W_0FC2_P_0 */
10393 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10396 /* VEX_W_0FC2_P_1 */
10397 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10400 /* VEX_W_0FC2_P_2 */
10401 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10404 /* VEX_W_0FC2_P_3 */
10405 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10408 /* VEX_W_0FC4_P_2 */
10409 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10412 /* VEX_W_0FC5_P_2 */
10413 { "vpextrw", { Gdq
, XS
, Ib
} },
10416 /* VEX_W_0FD0_P_2 */
10417 { "vaddsubpd", { XM
, Vex
, EXx
} },
10420 /* VEX_W_0FD0_P_3 */
10421 { "vaddsubps", { XM
, Vex
, EXx
} },
10424 /* VEX_W_0FD1_P_2 */
10425 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10428 /* VEX_W_0FD2_P_2 */
10429 { "vpsrld", { XM
, Vex
, EXxmm
} },
10432 /* VEX_W_0FD3_P_2 */
10433 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10436 /* VEX_W_0FD4_P_2 */
10437 { "vpaddq", { XM
, Vex
, EXx
} },
10440 /* VEX_W_0FD5_P_2 */
10441 { "vpmullw", { XM
, Vex
, EXx
} },
10444 /* VEX_W_0FD6_P_2 */
10445 { "vmovq", { EXqScalarS
, XMScalar
} },
10448 /* VEX_W_0FD7_P_2_M_1 */
10449 { "vpmovmskb", { Gdq
, XS
} },
10452 /* VEX_W_0FD8_P_2 */
10453 { "vpsubusb", { XM
, Vex
, EXx
} },
10456 /* VEX_W_0FD9_P_2 */
10457 { "vpsubusw", { XM
, Vex
, EXx
} },
10460 /* VEX_W_0FDA_P_2 */
10461 { "vpminub", { XM
, Vex
, EXx
} },
10464 /* VEX_W_0FDB_P_2 */
10465 { "vpand", { XM
, Vex
, EXx
} },
10468 /* VEX_W_0FDC_P_2 */
10469 { "vpaddusb", { XM
, Vex
, EXx
} },
10472 /* VEX_W_0FDD_P_2 */
10473 { "vpaddusw", { XM
, Vex
, EXx
} },
10476 /* VEX_W_0FDE_P_2 */
10477 { "vpmaxub", { XM
, Vex
, EXx
} },
10480 /* VEX_W_0FDF_P_2 */
10481 { "vpandn", { XM
, Vex
, EXx
} },
10484 /* VEX_W_0FE0_P_2 */
10485 { "vpavgb", { XM
, Vex
, EXx
} },
10488 /* VEX_W_0FE1_P_2 */
10489 { "vpsraw", { XM
, Vex
, EXxmm
} },
10492 /* VEX_W_0FE2_P_2 */
10493 { "vpsrad", { XM
, Vex
, EXxmm
} },
10496 /* VEX_W_0FE3_P_2 */
10497 { "vpavgw", { XM
, Vex
, EXx
} },
10500 /* VEX_W_0FE4_P_2 */
10501 { "vpmulhuw", { XM
, Vex
, EXx
} },
10504 /* VEX_W_0FE5_P_2 */
10505 { "vpmulhw", { XM
, Vex
, EXx
} },
10508 /* VEX_W_0FE6_P_1 */
10509 { "vcvtdq2pd", { XM
, EXxmmq
} },
10512 /* VEX_W_0FE6_P_2 */
10513 { "vcvttpd2dq%XY", { XMM
, EXx
} },
10516 /* VEX_W_0FE6_P_3 */
10517 { "vcvtpd2dq%XY", { XMM
, EXx
} },
10520 /* VEX_W_0FE7_P_2_M_0 */
10521 { "vmovntdq", { Mx
, XM
} },
10524 /* VEX_W_0FE8_P_2 */
10525 { "vpsubsb", { XM
, Vex
, EXx
} },
10528 /* VEX_W_0FE9_P_2 */
10529 { "vpsubsw", { XM
, Vex
, EXx
} },
10532 /* VEX_W_0FEA_P_2 */
10533 { "vpminsw", { XM
, Vex
, EXx
} },
10536 /* VEX_W_0FEB_P_2 */
10537 { "vpor", { XM
, Vex
, EXx
} },
10540 /* VEX_W_0FEC_P_2 */
10541 { "vpaddsb", { XM
, Vex
, EXx
} },
10544 /* VEX_W_0FED_P_2 */
10545 { "vpaddsw", { XM
, Vex
, EXx
} },
10548 /* VEX_W_0FEE_P_2 */
10549 { "vpmaxsw", { XM
, Vex
, EXx
} },
10552 /* VEX_W_0FEF_P_2 */
10553 { "vpxor", { XM
, Vex
, EXx
} },
10556 /* VEX_W_0FF0_P_3_M_0 */
10557 { "vlddqu", { XM
, M
} },
10560 /* VEX_W_0FF1_P_2 */
10561 { "vpsllw", { XM
, Vex
, EXxmm
} },
10564 /* VEX_W_0FF2_P_2 */
10565 { "vpslld", { XM
, Vex
, EXxmm
} },
10568 /* VEX_W_0FF3_P_2 */
10569 { "vpsllq", { XM
, Vex
, EXxmm
} },
10572 /* VEX_W_0FF4_P_2 */
10573 { "vpmuludq", { XM
, Vex
, EXx
} },
10576 /* VEX_W_0FF5_P_2 */
10577 { "vpmaddwd", { XM
, Vex
, EXx
} },
10580 /* VEX_W_0FF6_P_2 */
10581 { "vpsadbw", { XM
, Vex
, EXx
} },
10584 /* VEX_W_0FF7_P_2 */
10585 { "vmaskmovdqu", { XM
, XS
} },
10588 /* VEX_W_0FF8_P_2 */
10589 { "vpsubb", { XM
, Vex
, EXx
} },
10592 /* VEX_W_0FF9_P_2 */
10593 { "vpsubw", { XM
, Vex
, EXx
} },
10596 /* VEX_W_0FFA_P_2 */
10597 { "vpsubd", { XM
, Vex
, EXx
} },
10600 /* VEX_W_0FFB_P_2 */
10601 { "vpsubq", { XM
, Vex
, EXx
} },
10604 /* VEX_W_0FFC_P_2 */
10605 { "vpaddb", { XM
, Vex
, EXx
} },
10608 /* VEX_W_0FFD_P_2 */
10609 { "vpaddw", { XM
, Vex
, EXx
} },
10612 /* VEX_W_0FFE_P_2 */
10613 { "vpaddd", { XM
, Vex
, EXx
} },
10616 /* VEX_W_0F3800_P_2 */
10617 { "vpshufb", { XM
, Vex
, EXx
} },
10620 /* VEX_W_0F3801_P_2 */
10621 { "vphaddw", { XM
, Vex
, EXx
} },
10624 /* VEX_W_0F3802_P_2 */
10625 { "vphaddd", { XM
, Vex
, EXx
} },
10628 /* VEX_W_0F3803_P_2 */
10629 { "vphaddsw", { XM
, Vex
, EXx
} },
10632 /* VEX_W_0F3804_P_2 */
10633 { "vpmaddubsw", { XM
, Vex
, EXx
} },
10636 /* VEX_W_0F3805_P_2 */
10637 { "vphsubw", { XM
, Vex
, EXx
} },
10640 /* VEX_W_0F3806_P_2 */
10641 { "vphsubd", { XM
, Vex
, EXx
} },
10644 /* VEX_W_0F3807_P_2 */
10645 { "vphsubsw", { XM
, Vex
, EXx
} },
10648 /* VEX_W_0F3808_P_2 */
10649 { "vpsignb", { XM
, Vex
, EXx
} },
10652 /* VEX_W_0F3809_P_2 */
10653 { "vpsignw", { XM
, Vex
, EXx
} },
10656 /* VEX_W_0F380A_P_2 */
10657 { "vpsignd", { XM
, Vex
, EXx
} },
10660 /* VEX_W_0F380B_P_2 */
10661 { "vpmulhrsw", { XM
, Vex
, EXx
} },
10664 /* VEX_W_0F380C_P_2 */
10665 { "vpermilps", { XM
, Vex
, EXx
} },
10668 /* VEX_W_0F380D_P_2 */
10669 { "vpermilpd", { XM
, Vex
, EXx
} },
10672 /* VEX_W_0F380E_P_2 */
10673 { "vtestps", { XM
, EXx
} },
10676 /* VEX_W_0F380F_P_2 */
10677 { "vtestpd", { XM
, EXx
} },
10680 /* VEX_W_0F3816_P_2 */
10681 { "vpermps", { XM
, Vex
, EXx
} },
10684 /* VEX_W_0F3817_P_2 */
10685 { "vptest", { XM
, EXx
} },
10688 /* VEX_W_0F3818_P_2 */
10689 { "vbroadcastss", { XM
, EXxmm_md
} },
10692 /* VEX_W_0F3819_P_2 */
10693 { "vbroadcastsd", { XM
, EXxmm_mq
} },
10696 /* VEX_W_0F381A_P_2_M_0 */
10697 { "vbroadcastf128", { XM
, Mxmm
} },
10700 /* VEX_W_0F381C_P_2 */
10701 { "vpabsb", { XM
, EXx
} },
10704 /* VEX_W_0F381D_P_2 */
10705 { "vpabsw", { XM
, EXx
} },
10708 /* VEX_W_0F381E_P_2 */
10709 { "vpabsd", { XM
, EXx
} },
10712 /* VEX_W_0F3820_P_2 */
10713 { "vpmovsxbw", { XM
, EXxmmq
} },
10716 /* VEX_W_0F3821_P_2 */
10717 { "vpmovsxbd", { XM
, EXxmmqd
} },
10720 /* VEX_W_0F3822_P_2 */
10721 { "vpmovsxbq", { XM
, EXxmmdw
} },
10724 /* VEX_W_0F3823_P_2 */
10725 { "vpmovsxwd", { XM
, EXxmmq
} },
10728 /* VEX_W_0F3824_P_2 */
10729 { "vpmovsxwq", { XM
, EXxmmqd
} },
10732 /* VEX_W_0F3825_P_2 */
10733 { "vpmovsxdq", { XM
, EXxmmq
} },
10736 /* VEX_W_0F3828_P_2 */
10737 { "vpmuldq", { XM
, Vex
, EXx
} },
10740 /* VEX_W_0F3829_P_2 */
10741 { "vpcmpeqq", { XM
, Vex
, EXx
} },
10744 /* VEX_W_0F382A_P_2_M_0 */
10745 { "vmovntdqa", { XM
, Mx
} },
10748 /* VEX_W_0F382B_P_2 */
10749 { "vpackusdw", { XM
, Vex
, EXx
} },
10752 /* VEX_W_0F382C_P_2_M_0 */
10753 { "vmaskmovps", { XM
, Vex
, Mx
} },
10756 /* VEX_W_0F382D_P_2_M_0 */
10757 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10760 /* VEX_W_0F382E_P_2_M_0 */
10761 { "vmaskmovps", { Mx
, Vex
, XM
} },
10764 /* VEX_W_0F382F_P_2_M_0 */
10765 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10768 /* VEX_W_0F3830_P_2 */
10769 { "vpmovzxbw", { XM
, EXxmmq
} },
10772 /* VEX_W_0F3831_P_2 */
10773 { "vpmovzxbd", { XM
, EXxmmqd
} },
10776 /* VEX_W_0F3832_P_2 */
10777 { "vpmovzxbq", { XM
, EXxmmdw
} },
10780 /* VEX_W_0F3833_P_2 */
10781 { "vpmovzxwd", { XM
, EXxmmq
} },
10784 /* VEX_W_0F3834_P_2 */
10785 { "vpmovzxwq", { XM
, EXxmmqd
} },
10788 /* VEX_W_0F3835_P_2 */
10789 { "vpmovzxdq", { XM
, EXxmmq
} },
10792 /* VEX_W_0F3836_P_2 */
10793 { "vpermd", { XM
, Vex
, EXx
} },
10796 /* VEX_W_0F3837_P_2 */
10797 { "vpcmpgtq", { XM
, Vex
, EXx
} },
10800 /* VEX_W_0F3838_P_2 */
10801 { "vpminsb", { XM
, Vex
, EXx
} },
10804 /* VEX_W_0F3839_P_2 */
10805 { "vpminsd", { XM
, Vex
, EXx
} },
10808 /* VEX_W_0F383A_P_2 */
10809 { "vpminuw", { XM
, Vex
, EXx
} },
10812 /* VEX_W_0F383B_P_2 */
10813 { "vpminud", { XM
, Vex
, EXx
} },
10816 /* VEX_W_0F383C_P_2 */
10817 { "vpmaxsb", { XM
, Vex
, EXx
} },
10820 /* VEX_W_0F383D_P_2 */
10821 { "vpmaxsd", { XM
, Vex
, EXx
} },
10824 /* VEX_W_0F383E_P_2 */
10825 { "vpmaxuw", { XM
, Vex
, EXx
} },
10828 /* VEX_W_0F383F_P_2 */
10829 { "vpmaxud", { XM
, Vex
, EXx
} },
10832 /* VEX_W_0F3840_P_2 */
10833 { "vpmulld", { XM
, Vex
, EXx
} },
10836 /* VEX_W_0F3841_P_2 */
10837 { "vphminposuw", { XM
, EXx
} },
10840 /* VEX_W_0F3846_P_2 */
10841 { "vpsravd", { XM
, Vex
, EXx
} },
10844 /* VEX_W_0F3858_P_2 */
10845 { "vpbroadcastd", { XM
, EXxmm_md
} },
10848 /* VEX_W_0F3859_P_2 */
10849 { "vpbroadcastq", { XM
, EXxmm_mq
} },
10852 /* VEX_W_0F385A_P_2_M_0 */
10853 { "vbroadcasti128", { XM
, Mxmm
} },
10856 /* VEX_W_0F3878_P_2 */
10857 { "vpbroadcastb", { XM
, EXxmm_mb
} },
10860 /* VEX_W_0F3879_P_2 */
10861 { "vpbroadcastw", { XM
, EXxmm_mw
} },
10864 /* VEX_W_0F38DB_P_2 */
10865 { "vaesimc", { XM
, EXx
} },
10868 /* VEX_W_0F38DC_P_2 */
10869 { "vaesenc", { XM
, Vex128
, EXx
} },
10872 /* VEX_W_0F38DD_P_2 */
10873 { "vaesenclast", { XM
, Vex128
, EXx
} },
10876 /* VEX_W_0F38DE_P_2 */
10877 { "vaesdec", { XM
, Vex128
, EXx
} },
10880 /* VEX_W_0F38DF_P_2 */
10881 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10884 /* VEX_W_0F3A00_P_2 */
10886 { "vpermq", { XM
, EXx
, Ib
} },
10889 /* VEX_W_0F3A01_P_2 */
10891 { "vpermpd", { XM
, EXx
, Ib
} },
10894 /* VEX_W_0F3A02_P_2 */
10895 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
10898 /* VEX_W_0F3A04_P_2 */
10899 { "vpermilps", { XM
, EXx
, Ib
} },
10902 /* VEX_W_0F3A05_P_2 */
10903 { "vpermilpd", { XM
, EXx
, Ib
} },
10906 /* VEX_W_0F3A06_P_2 */
10907 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10910 /* VEX_W_0F3A08_P_2 */
10911 { "vroundps", { XM
, EXx
, Ib
} },
10914 /* VEX_W_0F3A09_P_2 */
10915 { "vroundpd", { XM
, EXx
, Ib
} },
10918 /* VEX_W_0F3A0A_P_2 */
10919 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10922 /* VEX_W_0F3A0B_P_2 */
10923 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10926 /* VEX_W_0F3A0C_P_2 */
10927 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10930 /* VEX_W_0F3A0D_P_2 */
10931 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10934 /* VEX_W_0F3A0E_P_2 */
10935 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
10938 /* VEX_W_0F3A0F_P_2 */
10939 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
10942 /* VEX_W_0F3A14_P_2 */
10943 { "vpextrb", { Edqb
, XM
, Ib
} },
10946 /* VEX_W_0F3A15_P_2 */
10947 { "vpextrw", { Edqw
, XM
, Ib
} },
10950 /* VEX_W_0F3A18_P_2 */
10951 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10954 /* VEX_W_0F3A19_P_2 */
10955 { "vextractf128", { EXxmm
, XM
, Ib
} },
10958 /* VEX_W_0F3A20_P_2 */
10959 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10962 /* VEX_W_0F3A21_P_2 */
10963 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10966 /* VEX_W_0F3A30_P_2 */
10968 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
10971 /* VEX_W_0F3A32_P_2 */
10973 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
10976 /* VEX_W_0F3A38_P_2 */
10977 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
10980 /* VEX_W_0F3A39_P_2 */
10981 { "vextracti128", { EXxmm
, XM
, Ib
} },
10984 /* VEX_W_0F3A40_P_2 */
10985 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10988 /* VEX_W_0F3A41_P_2 */
10989 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10992 /* VEX_W_0F3A42_P_2 */
10993 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
10996 /* VEX_W_0F3A44_P_2 */
10997 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11000 /* VEX_W_0F3A46_P_2 */
11001 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11004 /* VEX_W_0F3A48_P_2 */
11005 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11006 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11009 /* VEX_W_0F3A49_P_2 */
11010 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11011 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11014 /* VEX_W_0F3A4A_P_2 */
11015 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11018 /* VEX_W_0F3A4B_P_2 */
11019 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11022 /* VEX_W_0F3A4C_P_2 */
11023 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11026 /* VEX_W_0F3A60_P_2 */
11027 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11030 /* VEX_W_0F3A61_P_2 */
11031 { "vpcmpestri", { XM
, EXx
, Ib
} },
11034 /* VEX_W_0F3A62_P_2 */
11035 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11038 /* VEX_W_0F3A63_P_2 */
11039 { "vpcmpistri", { XM
, EXx
, Ib
} },
11042 /* VEX_W_0F3ADF_P_2 */
11043 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11045 #define NEED_VEX_W_TABLE
11046 #include "i386-dis-evex.h"
11047 #undef NEED_VEX_W_TABLE
11050 static const struct dis386 mod_table
[][2] = {
11053 { "leaS", { Gv
, M
} },
11058 { RM_TABLE (RM_C6_REG_7
) },
11063 { RM_TABLE (RM_C7_REG_7
) },
11067 { "Jcall{T|}", { indirEp
} },
11071 { "Jjmp{T|}", { indirEp
} },
11074 /* MOD_0F01_REG_0 */
11075 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11076 { RM_TABLE (RM_0F01_REG_0
) },
11079 /* MOD_0F01_REG_1 */
11080 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11081 { RM_TABLE (RM_0F01_REG_1
) },
11084 /* MOD_0F01_REG_2 */
11085 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11086 { RM_TABLE (RM_0F01_REG_2
) },
11089 /* MOD_0F01_REG_3 */
11090 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11091 { RM_TABLE (RM_0F01_REG_3
) },
11094 /* MOD_0F01_REG_7 */
11095 { "invlpg", { Mb
} },
11096 { RM_TABLE (RM_0F01_REG_7
) },
11099 /* MOD_0F12_PREFIX_0 */
11100 { "movlps", { XM
, EXq
} },
11101 { "movhlps", { XM
, EXq
} },
11105 { "movlpX", { EXq
, XM
} },
11108 /* MOD_0F16_PREFIX_0 */
11109 { "movhps", { XM
, EXq
} },
11110 { "movlhps", { XM
, EXq
} },
11114 { "movhpX", { EXq
, XM
} },
11117 /* MOD_0F18_REG_0 */
11118 { "prefetchnta", { Mb
} },
11121 /* MOD_0F18_REG_1 */
11122 { "prefetcht0", { Mb
} },
11125 /* MOD_0F18_REG_2 */
11126 { "prefetcht1", { Mb
} },
11129 /* MOD_0F18_REG_3 */
11130 { "prefetcht2", { Mb
} },
11133 /* MOD_0F18_REG_4 */
11134 { "nop/reserved", { Mb
} },
11137 /* MOD_0F18_REG_5 */
11138 { "nop/reserved", { Mb
} },
11141 /* MOD_0F18_REG_6 */
11142 { "nop/reserved", { Mb
} },
11145 /* MOD_0F18_REG_7 */
11146 { "nop/reserved", { Mb
} },
11149 /* MOD_0F1A_PREFIX_0 */
11150 { "bndldx", { Gbnd
, Ev_bnd
} },
11151 { "nopQ", { Ev
} },
11154 /* MOD_0F1B_PREFIX_0 */
11155 { "bndstx", { Ev_bnd
, Gbnd
} },
11156 { "nopQ", { Ev
} },
11159 /* MOD_0F1B_PREFIX_1 */
11160 { "bndmk", { Gbnd
, Ev_bnd
} },
11161 { "nopQ", { Ev
} },
11166 { "movZ", { Rm
, Cm
} },
11171 { "movZ", { Rm
, Dm
} },
11176 { "movZ", { Cm
, Rm
} },
11181 { "movZ", { Dm
, Rm
} },
11186 { "movL", { Rd
, Td
} },
11191 { "movL", { Td
, Rd
} },
11194 /* MOD_0F2B_PREFIX_0 */
11195 {"movntps", { Mx
, XM
} },
11198 /* MOD_0F2B_PREFIX_1 */
11199 {"movntss", { Md
, XM
} },
11202 /* MOD_0F2B_PREFIX_2 */
11203 {"movntpd", { Mx
, XM
} },
11206 /* MOD_0F2B_PREFIX_3 */
11207 {"movntsd", { Mq
, XM
} },
11212 { "movmskpX", { Gdq
, XS
} },
11215 /* MOD_0F71_REG_2 */
11217 { "psrlw", { MS
, Ib
} },
11220 /* MOD_0F71_REG_4 */
11222 { "psraw", { MS
, Ib
} },
11225 /* MOD_0F71_REG_6 */
11227 { "psllw", { MS
, Ib
} },
11230 /* MOD_0F72_REG_2 */
11232 { "psrld", { MS
, Ib
} },
11235 /* MOD_0F72_REG_4 */
11237 { "psrad", { MS
, Ib
} },
11240 /* MOD_0F72_REG_6 */
11242 { "pslld", { MS
, Ib
} },
11245 /* MOD_0F73_REG_2 */
11247 { "psrlq", { MS
, Ib
} },
11250 /* MOD_0F73_REG_3 */
11252 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11255 /* MOD_0F73_REG_6 */
11257 { "psllq", { MS
, Ib
} },
11260 /* MOD_0F73_REG_7 */
11262 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11265 /* MOD_0FAE_REG_0 */
11266 { "fxsave", { FXSAVE
} },
11267 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11270 /* MOD_0FAE_REG_1 */
11271 { "fxrstor", { FXSAVE
} },
11272 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11275 /* MOD_0FAE_REG_2 */
11276 { "ldmxcsr", { Md
} },
11277 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11280 /* MOD_0FAE_REG_3 */
11281 { "stmxcsr", { Md
} },
11282 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11285 /* MOD_0FAE_REG_4 */
11286 { "xsave", { FXSAVE
} },
11289 /* MOD_0FAE_REG_5 */
11290 { "xrstor", { FXSAVE
} },
11291 { RM_TABLE (RM_0FAE_REG_5
) },
11294 /* MOD_0FAE_REG_6 */
11295 { "xsaveopt", { FXSAVE
} },
11296 { RM_TABLE (RM_0FAE_REG_6
) },
11299 /* MOD_0FAE_REG_7 */
11300 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11301 { RM_TABLE (RM_0FAE_REG_7
) },
11305 { "lssS", { Gv
, Mp
} },
11309 { "lfsS", { Gv
, Mp
} },
11313 { "lgsS", { Gv
, Mp
} },
11316 /* MOD_0FC7_REG_3 */
11317 { "xrstors", { FXSAVE
} },
11320 /* MOD_0FC7_REG_4 */
11321 { "xsavec", { FXSAVE
} },
11324 /* MOD_0FC7_REG_5 */
11325 { "xsaves", { FXSAVE
} },
11328 /* MOD_0FC7_REG_6 */
11329 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11330 { "rdrand", { Ev
} },
11333 /* MOD_0FC7_REG_7 */
11334 { "vmptrst", { Mq
} },
11335 { "rdseed", { Ev
} },
11340 { "pmovmskb", { Gdq
, MS
} },
11343 /* MOD_0FE7_PREFIX_2 */
11344 { "movntdq", { Mx
, XM
} },
11347 /* MOD_0FF0_PREFIX_3 */
11348 { "lddqu", { XM
, M
} },
11351 /* MOD_0F382A_PREFIX_2 */
11352 { "movntdqa", { XM
, Mx
} },
11356 { "bound{S|}", { Gv
, Ma
} },
11357 { EVEX_TABLE (EVEX_0F
) },
11361 { "lesS", { Gv
, Mp
} },
11362 { VEX_C4_TABLE (VEX_0F
) },
11366 { "ldsS", { Gv
, Mp
} },
11367 { VEX_C5_TABLE (VEX_0F
) },
11370 /* MOD_VEX_0F12_PREFIX_0 */
11371 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11372 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11376 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11379 /* MOD_VEX_0F16_PREFIX_0 */
11380 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11381 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11385 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11389 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11394 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11397 /* MOD_VEX_0F71_REG_2 */
11399 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11402 /* MOD_VEX_0F71_REG_4 */
11404 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11407 /* MOD_VEX_0F71_REG_6 */
11409 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11412 /* MOD_VEX_0F72_REG_2 */
11414 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11417 /* MOD_VEX_0F72_REG_4 */
11419 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11422 /* MOD_VEX_0F72_REG_6 */
11424 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11427 /* MOD_VEX_0F73_REG_2 */
11429 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11432 /* MOD_VEX_0F73_REG_3 */
11434 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11437 /* MOD_VEX_0F73_REG_6 */
11439 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11442 /* MOD_VEX_0F73_REG_7 */
11444 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11447 /* MOD_VEX_0FAE_REG_2 */
11448 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11451 /* MOD_VEX_0FAE_REG_3 */
11452 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11455 /* MOD_VEX_0FD7_PREFIX_2 */
11457 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11460 /* MOD_VEX_0FE7_PREFIX_2 */
11461 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11464 /* MOD_VEX_0FF0_PREFIX_3 */
11465 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11468 /* MOD_VEX_0F381A_PREFIX_2 */
11469 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11472 /* MOD_VEX_0F382A_PREFIX_2 */
11473 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11476 /* MOD_VEX_0F382C_PREFIX_2 */
11477 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11480 /* MOD_VEX_0F382D_PREFIX_2 */
11481 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11484 /* MOD_VEX_0F382E_PREFIX_2 */
11485 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11488 /* MOD_VEX_0F382F_PREFIX_2 */
11489 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11492 /* MOD_VEX_0F385A_PREFIX_2 */
11493 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11496 /* MOD_VEX_0F388C_PREFIX_2 */
11497 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11500 /* MOD_VEX_0F388E_PREFIX_2 */
11501 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11503 #define NEED_MOD_TABLE
11504 #include "i386-dis-evex.h"
11505 #undef NEED_MOD_TABLE
11508 static const struct dis386 rm_table
[][8] = {
11511 { "xabort", { Skip_MODRM
, Ib
} },
11515 { "xbeginT", { Skip_MODRM
, Jv
} },
11518 /* RM_0F01_REG_0 */
11520 { "vmcall", { Skip_MODRM
} },
11521 { "vmlaunch", { Skip_MODRM
} },
11522 { "vmresume", { Skip_MODRM
} },
11523 { "vmxoff", { Skip_MODRM
} },
11526 /* RM_0F01_REG_1 */
11527 { "monitor", { { OP_Monitor
, 0 } } },
11528 { "mwait", { { OP_Mwait
, 0 } } },
11529 { "clac", { Skip_MODRM
} },
11530 { "stac", { Skip_MODRM
} },
11533 /* RM_0F01_REG_2 */
11534 { "xgetbv", { Skip_MODRM
} },
11535 { "xsetbv", { Skip_MODRM
} },
11538 { "vmfunc", { Skip_MODRM
} },
11539 { "xend", { Skip_MODRM
} },
11540 { "xtest", { Skip_MODRM
} },
11544 /* RM_0F01_REG_3 */
11545 { "vmrun", { Skip_MODRM
} },
11546 { "vmmcall", { Skip_MODRM
} },
11547 { "vmload", { Skip_MODRM
} },
11548 { "vmsave", { Skip_MODRM
} },
11549 { "stgi", { Skip_MODRM
} },
11550 { "clgi", { Skip_MODRM
} },
11551 { "skinit", { Skip_MODRM
} },
11552 { "invlpga", { Skip_MODRM
} },
11555 /* RM_0F01_REG_7 */
11556 { "swapgs", { Skip_MODRM
} },
11557 { "rdtscp", { Skip_MODRM
} },
11560 /* RM_0FAE_REG_5 */
11561 { "lfence", { Skip_MODRM
} },
11564 /* RM_0FAE_REG_6 */
11565 { "mfence", { Skip_MODRM
} },
11568 /* RM_0FAE_REG_7 */
11569 { "sfence", { Skip_MODRM
} },
11573 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11575 /* We use the high bit to indicate different name for the same
11577 #define ADDR16_PREFIX (0x67 | 0x100)
11578 #define ADDR32_PREFIX (0x67 | 0x200)
11579 #define DATA16_PREFIX (0x66 | 0x100)
11580 #define DATA32_PREFIX (0x66 | 0x200)
11581 #define REP_PREFIX (0xf3 | 0x100)
11582 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11583 #define XRELEASE_PREFIX (0xf3 | 0x400)
11584 #define BND_PREFIX (0xf2 | 0x400)
11589 int newrex
, i
, length
;
11595 last_lock_prefix
= -1;
11596 last_repz_prefix
= -1;
11597 last_repnz_prefix
= -1;
11598 last_data_prefix
= -1;
11599 last_addr_prefix
= -1;
11600 last_rex_prefix
= -1;
11601 last_seg_prefix
= -1;
11602 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11603 all_prefixes
[i
] = 0;
11606 /* The maximum instruction length is 15bytes. */
11607 while (length
< MAX_CODE_LENGTH
- 1)
11609 FETCH_DATA (the_info
, codep
+ 1);
11613 /* REX prefixes family. */
11630 if (address_mode
== mode_64bit
)
11634 last_rex_prefix
= i
;
11637 prefixes
|= PREFIX_REPZ
;
11638 last_repz_prefix
= i
;
11641 prefixes
|= PREFIX_REPNZ
;
11642 last_repnz_prefix
= i
;
11645 prefixes
|= PREFIX_LOCK
;
11646 last_lock_prefix
= i
;
11649 prefixes
|= PREFIX_CS
;
11650 last_seg_prefix
= i
;
11653 prefixes
|= PREFIX_SS
;
11654 last_seg_prefix
= i
;
11657 prefixes
|= PREFIX_DS
;
11658 last_seg_prefix
= i
;
11661 prefixes
|= PREFIX_ES
;
11662 last_seg_prefix
= i
;
11665 prefixes
|= PREFIX_FS
;
11666 last_seg_prefix
= i
;
11669 prefixes
|= PREFIX_GS
;
11670 last_seg_prefix
= i
;
11673 prefixes
|= PREFIX_DATA
;
11674 last_data_prefix
= i
;
11677 prefixes
|= PREFIX_ADDR
;
11678 last_addr_prefix
= i
;
11681 /* fwait is really an instruction. If there are prefixes
11682 before the fwait, they belong to the fwait, *not* to the
11683 following instruction. */
11684 if (prefixes
|| rex
)
11686 prefixes
|= PREFIX_FWAIT
;
11688 /* This ensures that the previous REX prefixes are noticed
11689 as unused prefixes, as in the return case below. */
11693 prefixes
= PREFIX_FWAIT
;
11698 /* Rex is ignored when followed by another prefix. */
11704 if (*codep
!= FWAIT_OPCODE
)
11705 all_prefixes
[i
++] = *codep
;
11714 seg_prefix (int pref
)
11735 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11738 static const char *
11739 prefix_name (int pref
, int sizeflag
)
11741 static const char *rexes
[16] =
11744 "rex.B", /* 0x41 */
11745 "rex.X", /* 0x42 */
11746 "rex.XB", /* 0x43 */
11747 "rex.R", /* 0x44 */
11748 "rex.RB", /* 0x45 */
11749 "rex.RX", /* 0x46 */
11750 "rex.RXB", /* 0x47 */
11751 "rex.W", /* 0x48 */
11752 "rex.WB", /* 0x49 */
11753 "rex.WX", /* 0x4a */
11754 "rex.WXB", /* 0x4b */
11755 "rex.WR", /* 0x4c */
11756 "rex.WRB", /* 0x4d */
11757 "rex.WRX", /* 0x4e */
11758 "rex.WRXB", /* 0x4f */
11763 /* REX prefixes family. */
11780 return rexes
[pref
- 0x40];
11800 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11802 if (address_mode
== mode_64bit
)
11803 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11805 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11808 case ADDR16_PREFIX
:
11810 case ADDR32_PREFIX
:
11812 case DATA16_PREFIX
:
11814 case DATA32_PREFIX
:
11818 case XACQUIRE_PREFIX
:
11820 case XRELEASE_PREFIX
:
11829 static char op_out
[MAX_OPERANDS
][100];
11830 static int op_ad
, op_index
[MAX_OPERANDS
];
11831 static int two_source_ops
;
11832 static bfd_vma op_address
[MAX_OPERANDS
];
11833 static bfd_vma op_riprel
[MAX_OPERANDS
];
11834 static bfd_vma start_pc
;
11837 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11838 * (see topic "Redundant prefixes" in the "Differences from 8086"
11839 * section of the "Virtual 8086 Mode" chapter.)
11840 * 'pc' should be the address of this instruction, it will
11841 * be used to print the target address if this is a relative jump or call
11842 * The function returns the length of this instruction in bytes.
11845 static char intel_syntax
;
11846 static char intel_mnemonic
= !SYSV386_COMPAT
;
11847 static char open_char
;
11848 static char close_char
;
11849 static char separator_char
;
11850 static char scale_char
;
11852 /* Here for backwards compatibility. When gdb stops using
11853 print_insn_i386_att and print_insn_i386_intel these functions can
11854 disappear, and print_insn_i386 be merged into print_insn. */
11856 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11860 return print_insn (pc
, info
);
11864 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11868 return print_insn (pc
, info
);
11872 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11876 return print_insn (pc
, info
);
11880 print_i386_disassembler_options (FILE *stream
)
11882 fprintf (stream
, _("\n\
11883 The following i386/x86-64 specific disassembler options are supported for use\n\
11884 with the -M switch (multiple options should be separated by commas):\n"));
11886 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11887 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11888 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11889 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11890 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11891 fprintf (stream
, _(" att-mnemonic\n"
11892 " Display instruction in AT&T mnemonic\n"));
11893 fprintf (stream
, _(" intel-mnemonic\n"
11894 " Display instruction in Intel mnemonic\n"));
11895 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11896 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11897 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11898 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11899 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11900 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11904 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
11906 /* Get a pointer to struct dis386 with a valid name. */
11908 static const struct dis386
*
11909 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11911 int vindex
, vex_table_index
;
11913 if (dp
->name
!= NULL
)
11916 switch (dp
->op
[0].bytemode
)
11918 case USE_REG_TABLE
:
11919 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11922 case USE_MOD_TABLE
:
11923 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11924 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11928 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11931 case USE_PREFIX_TABLE
:
11934 /* The prefix in VEX is implicit. */
11935 switch (vex
.prefix
)
11940 case REPE_PREFIX_OPCODE
:
11943 case DATA_PREFIX_OPCODE
:
11946 case REPNE_PREFIX_OPCODE
:
11957 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11958 if (prefixes
& PREFIX_REPZ
)
11961 all_prefixes
[last_repz_prefix
] = 0;
11965 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11967 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11968 if (prefixes
& PREFIX_REPNZ
)
11971 all_prefixes
[last_repnz_prefix
] = 0;
11975 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11976 if (prefixes
& PREFIX_DATA
)
11979 all_prefixes
[last_data_prefix
] = 0;
11984 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11987 case USE_X86_64_TABLE
:
11988 vindex
= address_mode
== mode_64bit
? 1 : 0;
11989 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11992 case USE_3BYTE_TABLE
:
11993 FETCH_DATA (info
, codep
+ 2);
11995 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11996 modrm
.mod
= (*codep
>> 6) & 3;
11997 modrm
.reg
= (*codep
>> 3) & 7;
11998 modrm
.rm
= *codep
& 7;
12001 case USE_VEX_LEN_TABLE
:
12005 switch (vex
.length
)
12018 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12021 case USE_XOP_8F_TABLE
:
12022 FETCH_DATA (info
, codep
+ 3);
12023 /* All bits in the REX prefix are ignored. */
12025 rex
= ~(*codep
>> 5) & 0x7;
12027 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12028 switch ((*codep
& 0x1f))
12034 vex_table_index
= XOP_08
;
12037 vex_table_index
= XOP_09
;
12040 vex_table_index
= XOP_0A
;
12044 vex
.w
= *codep
& 0x80;
12045 if (vex
.w
&& address_mode
== mode_64bit
)
12048 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12049 if (address_mode
!= mode_64bit
12050 && vex
.register_specifier
> 0x7)
12056 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12057 switch ((*codep
& 0x3))
12063 vex
.prefix
= DATA_PREFIX_OPCODE
;
12066 vex
.prefix
= REPE_PREFIX_OPCODE
;
12069 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12076 dp
= &xop_table
[vex_table_index
][vindex
];
12078 FETCH_DATA (info
, codep
+ 1);
12079 modrm
.mod
= (*codep
>> 6) & 3;
12080 modrm
.reg
= (*codep
>> 3) & 7;
12081 modrm
.rm
= *codep
& 7;
12084 case USE_VEX_C4_TABLE
:
12086 FETCH_DATA (info
, codep
+ 3);
12087 /* All bits in the REX prefix are ignored. */
12089 rex
= ~(*codep
>> 5) & 0x7;
12090 switch ((*codep
& 0x1f))
12096 vex_table_index
= VEX_0F
;
12099 vex_table_index
= VEX_0F38
;
12102 vex_table_index
= VEX_0F3A
;
12106 vex
.w
= *codep
& 0x80;
12107 if (vex
.w
&& address_mode
== mode_64bit
)
12110 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12111 if (address_mode
!= mode_64bit
12112 && vex
.register_specifier
> 0x7)
12118 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12119 switch ((*codep
& 0x3))
12125 vex
.prefix
= DATA_PREFIX_OPCODE
;
12128 vex
.prefix
= REPE_PREFIX_OPCODE
;
12131 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12138 dp
= &vex_table
[vex_table_index
][vindex
];
12139 /* There is no MODRM byte for VEX [82|77]. */
12140 if (vindex
!= 0x77 && vindex
!= 0x82)
12142 FETCH_DATA (info
, codep
+ 1);
12143 modrm
.mod
= (*codep
>> 6) & 3;
12144 modrm
.reg
= (*codep
>> 3) & 7;
12145 modrm
.rm
= *codep
& 7;
12149 case USE_VEX_C5_TABLE
:
12151 FETCH_DATA (info
, codep
+ 2);
12152 /* All bits in the REX prefix are ignored. */
12154 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12156 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12157 if (address_mode
!= mode_64bit
12158 && vex
.register_specifier
> 0x7)
12166 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12167 switch ((*codep
& 0x3))
12173 vex
.prefix
= DATA_PREFIX_OPCODE
;
12176 vex
.prefix
= REPE_PREFIX_OPCODE
;
12179 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12186 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12187 /* There is no MODRM byte for VEX [82|77]. */
12188 if (vindex
!= 0x77 && vindex
!= 0x82)
12190 FETCH_DATA (info
, codep
+ 1);
12191 modrm
.mod
= (*codep
>> 6) & 3;
12192 modrm
.reg
= (*codep
>> 3) & 7;
12193 modrm
.rm
= *codep
& 7;
12197 case USE_VEX_W_TABLE
:
12201 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12204 case USE_EVEX_TABLE
:
12205 two_source_ops
= 0;
12208 FETCH_DATA (info
, codep
+ 4);
12209 /* All bits in the REX prefix are ignored. */
12211 /* The first byte after 0x62. */
12212 rex
= ~(*codep
>> 5) & 0x7;
12213 vex
.r
= *codep
& 0x10;
12214 switch ((*codep
& 0xf))
12217 return &bad_opcode
;
12219 vex_table_index
= EVEX_0F
;
12222 vex_table_index
= EVEX_0F38
;
12225 vex_table_index
= EVEX_0F3A
;
12229 /* The second byte after 0x62. */
12231 vex
.w
= *codep
& 0x80;
12232 if (vex
.w
&& address_mode
== mode_64bit
)
12235 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12236 if (address_mode
!= mode_64bit
)
12238 /* In 16/32-bit mode silently ignore following bits. */
12242 vex
.register_specifier
&= 0x7;
12246 if (!(*codep
& 0x4))
12247 return &bad_opcode
;
12249 switch ((*codep
& 0x3))
12255 vex
.prefix
= DATA_PREFIX_OPCODE
;
12258 vex
.prefix
= REPE_PREFIX_OPCODE
;
12261 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12265 /* The third byte after 0x62. */
12268 /* Remember the static rounding bits. */
12269 vex
.ll
= (*codep
>> 5) & 3;
12270 vex
.b
= (*codep
& 0x10) != 0;
12272 vex
.v
= *codep
& 0x8;
12273 vex
.mask_register_specifier
= *codep
& 0x7;
12274 vex
.zeroing
= *codep
& 0x80;
12280 dp
= &evex_table
[vex_table_index
][vindex
];
12281 FETCH_DATA (info
, codep
+ 1);
12282 modrm
.mod
= (*codep
>> 6) & 3;
12283 modrm
.reg
= (*codep
>> 3) & 7;
12284 modrm
.rm
= *codep
& 7;
12286 /* Set vector length. */
12287 if (modrm
.mod
== 3 && vex
.b
)
12303 return &bad_opcode
;
12316 if (dp
->name
!= NULL
)
12319 return get_valid_dis386 (dp
, info
);
12323 get_sib (disassemble_info
*info
, int sizeflag
)
12325 /* If modrm.mod == 3, operand must be register. */
12327 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12331 FETCH_DATA (info
, codep
+ 2);
12332 sib
.index
= (codep
[1] >> 3) & 7;
12333 sib
.scale
= (codep
[1] >> 6) & 3;
12334 sib
.base
= codep
[1] & 7;
12339 print_insn (bfd_vma pc
, disassemble_info
*info
)
12341 const struct dis386
*dp
;
12343 char *op_txt
[MAX_OPERANDS
];
12347 struct dis_private priv
;
12349 int default_prefixes
;
12351 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12352 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12353 address_mode
= mode_32bit
;
12354 else if (info
->mach
== bfd_mach_i386_i8086
)
12356 address_mode
= mode_16bit
;
12357 priv
.orig_sizeflag
= 0;
12360 address_mode
= mode_64bit
;
12362 if (intel_syntax
== (char) -1)
12363 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12365 for (p
= info
->disassembler_options
; p
!= NULL
; )
12367 if (CONST_STRNEQ (p
, "x86-64"))
12369 address_mode
= mode_64bit
;
12370 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12372 else if (CONST_STRNEQ (p
, "i386"))
12374 address_mode
= mode_32bit
;
12375 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12377 else if (CONST_STRNEQ (p
, "i8086"))
12379 address_mode
= mode_16bit
;
12380 priv
.orig_sizeflag
= 0;
12382 else if (CONST_STRNEQ (p
, "intel"))
12385 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12386 intel_mnemonic
= 1;
12388 else if (CONST_STRNEQ (p
, "att"))
12391 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12392 intel_mnemonic
= 0;
12394 else if (CONST_STRNEQ (p
, "addr"))
12396 if (address_mode
== mode_64bit
)
12398 if (p
[4] == '3' && p
[5] == '2')
12399 priv
.orig_sizeflag
&= ~AFLAG
;
12400 else if (p
[4] == '6' && p
[5] == '4')
12401 priv
.orig_sizeflag
|= AFLAG
;
12405 if (p
[4] == '1' && p
[5] == '6')
12406 priv
.orig_sizeflag
&= ~AFLAG
;
12407 else if (p
[4] == '3' && p
[5] == '2')
12408 priv
.orig_sizeflag
|= AFLAG
;
12411 else if (CONST_STRNEQ (p
, "data"))
12413 if (p
[4] == '1' && p
[5] == '6')
12414 priv
.orig_sizeflag
&= ~DFLAG
;
12415 else if (p
[4] == '3' && p
[5] == '2')
12416 priv
.orig_sizeflag
|= DFLAG
;
12418 else if (CONST_STRNEQ (p
, "suffix"))
12419 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12421 p
= strchr (p
, ',');
12428 names64
= intel_names64
;
12429 names32
= intel_names32
;
12430 names16
= intel_names16
;
12431 names8
= intel_names8
;
12432 names8rex
= intel_names8rex
;
12433 names_seg
= intel_names_seg
;
12434 names_mm
= intel_names_mm
;
12435 names_bnd
= intel_names_bnd
;
12436 names_xmm
= intel_names_xmm
;
12437 names_ymm
= intel_names_ymm
;
12438 names_zmm
= intel_names_zmm
;
12439 index64
= intel_index64
;
12440 index32
= intel_index32
;
12441 names_mask
= intel_names_mask
;
12442 index16
= intel_index16
;
12445 separator_char
= '+';
12450 names64
= att_names64
;
12451 names32
= att_names32
;
12452 names16
= att_names16
;
12453 names8
= att_names8
;
12454 names8rex
= att_names8rex
;
12455 names_seg
= att_names_seg
;
12456 names_mm
= att_names_mm
;
12457 names_bnd
= att_names_bnd
;
12458 names_xmm
= att_names_xmm
;
12459 names_ymm
= att_names_ymm
;
12460 names_zmm
= att_names_zmm
;
12461 index64
= att_index64
;
12462 index32
= att_index32
;
12463 names_mask
= att_names_mask
;
12464 index16
= att_index16
;
12467 separator_char
= ',';
12471 /* The output looks better if we put 7 bytes on a line, since that
12472 puts most long word instructions on a single line. Use 8 bytes
12474 if ((info
->mach
& bfd_mach_l1om
) != 0)
12475 info
->bytes_per_line
= 8;
12477 info
->bytes_per_line
= 7;
12479 info
->private_data
= &priv
;
12480 priv
.max_fetched
= priv
.the_buffer
;
12481 priv
.insn_start
= pc
;
12484 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12492 start_codep
= priv
.the_buffer
;
12493 codep
= priv
.the_buffer
;
12495 if (setjmp (priv
.bailout
) != 0)
12499 /* Getting here means we tried for data but didn't get it. That
12500 means we have an incomplete instruction of some sort. Just
12501 print the first byte as a prefix or a .byte pseudo-op. */
12502 if (codep
> priv
.the_buffer
)
12504 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12506 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12509 /* Just print the first byte as a .byte instruction. */
12510 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12511 (unsigned int) priv
.the_buffer
[0]);
12521 sizeflag
= priv
.orig_sizeflag
;
12523 if (!ckprefix () || rex_used
)
12525 /* Too many prefixes or unused REX prefixes. */
12527 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12529 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12531 prefix_name (all_prefixes
[i
], sizeflag
));
12535 insn_codep
= codep
;
12537 FETCH_DATA (info
, codep
+ 1);
12538 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12540 if (((prefixes
& PREFIX_FWAIT
)
12541 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12543 (*info
->fprintf_func
) (info
->stream
, "fwait");
12547 if (*codep
== 0x0f)
12549 unsigned char threebyte
;
12550 FETCH_DATA (info
, codep
+ 2);
12551 threebyte
= *++codep
;
12552 dp
= &dis386_twobyte
[threebyte
];
12553 need_modrm
= twobyte_has_modrm
[*codep
];
12558 dp
= &dis386
[*codep
];
12559 need_modrm
= onebyte_has_modrm
[*codep
];
12563 if ((prefixes
& PREFIX_REPZ
))
12564 used_prefixes
|= PREFIX_REPZ
;
12565 if ((prefixes
& PREFIX_REPNZ
))
12566 used_prefixes
|= PREFIX_REPNZ
;
12567 if ((prefixes
& PREFIX_LOCK
))
12568 used_prefixes
|= PREFIX_LOCK
;
12570 default_prefixes
= 0;
12571 if (prefixes
& PREFIX_ADDR
)
12574 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
12576 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12577 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
12579 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
12580 default_prefixes
|= PREFIX_ADDR
;
12584 if ((prefixes
& PREFIX_DATA
))
12587 if (dp
->op
[2].bytemode
== cond_jump_mode
12588 && dp
->op
[0].bytemode
== v_mode
12591 if (sizeflag
& DFLAG
)
12592 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
12594 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
12595 default_prefixes
|= PREFIX_DATA
;
12597 else if (rex
& REX_W
)
12599 /* REX_W will override PREFIX_DATA. */
12600 default_prefixes
|= PREFIX_DATA
;
12606 FETCH_DATA (info
, codep
+ 1);
12607 modrm
.mod
= (*codep
>> 6) & 3;
12608 modrm
.reg
= (*codep
>> 3) & 7;
12609 modrm
.rm
= *codep
& 7;
12617 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12619 get_sib (info
, sizeflag
);
12620 dofloat (sizeflag
);
12624 dp
= get_valid_dis386 (dp
, info
);
12625 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12627 get_sib (info
, sizeflag
);
12628 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12631 op_ad
= MAX_OPERANDS
- 1 - i
;
12633 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12634 /* For EVEX instruction after the last operand masking
12635 should be printed. */
12636 if (i
== 0 && vex
.evex
)
12638 /* Don't print {%k0}. */
12639 if (vex
.mask_register_specifier
)
12642 oappend (names_mask
[vex
.mask_register_specifier
]);
12652 /* See if any prefixes were not used. If so, print the first one
12653 separately. If we don't do this, we'll wind up printing an
12654 instruction stream which does not precisely correspond to the
12655 bytes we are disassembling. */
12656 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
12658 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12659 if (all_prefixes
[i
])
12662 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
12664 name
= INTERNAL_DISASSEMBLER_ERROR
;
12665 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12670 /* Check if the REX prefix is used. */
12671 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12672 all_prefixes
[last_rex_prefix
] = 0;
12674 /* Check if the SEG prefix is used. */
12675 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12676 | PREFIX_FS
| PREFIX_GS
)) != 0
12678 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
12679 all_prefixes
[last_seg_prefix
] = 0;
12681 /* Check if the ADDR prefix is used. */
12682 if ((prefixes
& PREFIX_ADDR
) != 0
12683 && (used_prefixes
& PREFIX_ADDR
) != 0)
12684 all_prefixes
[last_addr_prefix
] = 0;
12686 /* Check if the DATA prefix is used. */
12687 if ((prefixes
& PREFIX_DATA
) != 0
12688 && (used_prefixes
& PREFIX_DATA
) != 0)
12689 all_prefixes
[last_data_prefix
] = 0;
12692 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12693 if (all_prefixes
[i
])
12696 name
= prefix_name (all_prefixes
[i
], sizeflag
);
12699 prefix_length
+= strlen (name
) + 1;
12700 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12703 /* Check maximum code length. */
12704 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12706 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12707 return MAX_CODE_LENGTH
;
12710 obufp
= mnemonicendp
;
12711 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12714 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12716 /* The enter and bound instructions are printed with operands in the same
12717 order as the intel book; everything else is printed in reverse order. */
12718 if (intel_syntax
|| two_source_ops
)
12722 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12723 op_txt
[i
] = op_out
[i
];
12725 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12727 op_ad
= op_index
[i
];
12728 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12729 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12730 riprel
= op_riprel
[i
];
12731 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12732 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12737 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12738 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12742 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12746 (*info
->fprintf_func
) (info
->stream
, ",");
12747 if (op_index
[i
] != -1 && !op_riprel
[i
])
12748 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12750 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12754 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12755 if (op_index
[i
] != -1 && op_riprel
[i
])
12757 (*info
->fprintf_func
) (info
->stream
, " # ");
12758 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
12759 + op_address
[op_index
[i
]]), info
);
12762 return codep
- priv
.the_buffer
;
12765 static const char *float_mem
[] = {
12840 static const unsigned char float_mem_mode
[] = {
12915 #define ST { OP_ST, 0 }
12916 #define STi { OP_STi, 0 }
12918 #define FGRPd9_2 NULL, { { NULL, 0 } }
12919 #define FGRPd9_4 NULL, { { NULL, 1 } }
12920 #define FGRPd9_5 NULL, { { NULL, 2 } }
12921 #define FGRPd9_6 NULL, { { NULL, 3 } }
12922 #define FGRPd9_7 NULL, { { NULL, 4 } }
12923 #define FGRPda_5 NULL, { { NULL, 5 } }
12924 #define FGRPdb_4 NULL, { { NULL, 6 } }
12925 #define FGRPde_3 NULL, { { NULL, 7 } }
12926 #define FGRPdf_4 NULL, { { NULL, 8 } }
12928 static const struct dis386 float_reg
[][8] = {
12931 { "fadd", { ST
, STi
} },
12932 { "fmul", { ST
, STi
} },
12933 { "fcom", { STi
} },
12934 { "fcomp", { STi
} },
12935 { "fsub", { ST
, STi
} },
12936 { "fsubr", { ST
, STi
} },
12937 { "fdiv", { ST
, STi
} },
12938 { "fdivr", { ST
, STi
} },
12942 { "fld", { STi
} },
12943 { "fxch", { STi
} },
12953 { "fcmovb", { ST
, STi
} },
12954 { "fcmove", { ST
, STi
} },
12955 { "fcmovbe",{ ST
, STi
} },
12956 { "fcmovu", { ST
, STi
} },
12964 { "fcmovnb",{ ST
, STi
} },
12965 { "fcmovne",{ ST
, STi
} },
12966 { "fcmovnbe",{ ST
, STi
} },
12967 { "fcmovnu",{ ST
, STi
} },
12969 { "fucomi", { ST
, STi
} },
12970 { "fcomi", { ST
, STi
} },
12975 { "fadd", { STi
, ST
} },
12976 { "fmul", { STi
, ST
} },
12979 { "fsub!M", { STi
, ST
} },
12980 { "fsubM", { STi
, ST
} },
12981 { "fdiv!M", { STi
, ST
} },
12982 { "fdivM", { STi
, ST
} },
12986 { "ffree", { STi
} },
12988 { "fst", { STi
} },
12989 { "fstp", { STi
} },
12990 { "fucom", { STi
} },
12991 { "fucomp", { STi
} },
12997 { "faddp", { STi
, ST
} },
12998 { "fmulp", { STi
, ST
} },
13001 { "fsub!Mp", { STi
, ST
} },
13002 { "fsubMp", { STi
, ST
} },
13003 { "fdiv!Mp", { STi
, ST
} },
13004 { "fdivMp", { STi
, ST
} },
13008 { "ffreep", { STi
} },
13013 { "fucomip", { ST
, STi
} },
13014 { "fcomip", { ST
, STi
} },
13019 static char *fgrps
[][8] = {
13022 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13027 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13032 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13037 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13042 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13047 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13052 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13053 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13058 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13063 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13068 swap_operand (void)
13070 mnemonicendp
[0] = '.';
13071 mnemonicendp
[1] = 's';
13076 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13077 int sizeflag ATTRIBUTE_UNUSED
)
13079 /* Skip mod/rm byte. */
13085 dofloat (int sizeflag
)
13087 const struct dis386
*dp
;
13088 unsigned char floatop
;
13090 floatop
= codep
[-1];
13092 if (modrm
.mod
!= 3)
13094 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13096 putop (float_mem
[fp_indx
], sizeflag
);
13099 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13102 /* Skip mod/rm byte. */
13106 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13107 if (dp
->name
== NULL
)
13109 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13111 /* Instruction fnstsw is only one with strange arg. */
13112 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13113 strcpy (op_out
[0], names16
[0]);
13117 putop (dp
->name
, sizeflag
);
13122 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13127 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13131 /* Like oappend (below), but S is a string starting with '%'.
13132 In Intel syntax, the '%' is elided. */
13134 oappend_maybe_intel (const char *s
)
13136 oappend (s
+ intel_syntax
);
13140 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13142 oappend_maybe_intel ("%st");
13146 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13148 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13149 oappend_maybe_intel (scratchbuf
);
13152 /* Capital letters in template are macros. */
13154 putop (const char *in_template
, int sizeflag
)
13159 unsigned int l
= 0, len
= 1;
13162 #define SAVE_LAST(c) \
13163 if (l < len && l < sizeof (last)) \
13168 for (p
= in_template
; *p
; p
++)
13185 while (*++p
!= '|')
13186 if (*p
== '}' || *p
== '\0')
13189 /* Fall through. */
13194 while (*++p
!= '}')
13205 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13209 if (l
== 0 && len
== 1)
13214 if (sizeflag
& SUFFIX_ALWAYS
)
13227 if (address_mode
== mode_64bit
13228 && !(prefixes
& PREFIX_ADDR
))
13239 if (intel_syntax
&& !alt
)
13241 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13243 if (sizeflag
& DFLAG
)
13244 *obufp
++ = intel_syntax
? 'd' : 'l';
13246 *obufp
++ = intel_syntax
? 'w' : 's';
13247 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13251 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13254 if (modrm
.mod
== 3)
13260 if (sizeflag
& DFLAG
)
13261 *obufp
++ = intel_syntax
? 'd' : 'l';
13264 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13270 case 'E': /* For jcxz/jecxz */
13271 if (address_mode
== mode_64bit
)
13273 if (sizeflag
& AFLAG
)
13279 if (sizeflag
& AFLAG
)
13281 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13286 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13288 if (sizeflag
& AFLAG
)
13289 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13291 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13292 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13296 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13298 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13302 if (!(rex
& REX_W
))
13303 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13308 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13309 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13311 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13314 if (prefixes
& PREFIX_DS
)
13335 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13340 /* Fall through. */
13343 if (l
!= 0 || len
!= 1)
13351 if (sizeflag
& SUFFIX_ALWAYS
)
13355 if (intel_mnemonic
!= cond
)
13359 if ((prefixes
& PREFIX_FWAIT
) == 0)
13362 used_prefixes
|= PREFIX_FWAIT
;
13368 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13372 if (!(rex
& REX_W
))
13373 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13377 && address_mode
== mode_64bit
13378 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13383 /* Fall through. */
13387 if ((rex
& REX_W
) == 0
13388 && (prefixes
& PREFIX_DATA
))
13390 if ((sizeflag
& DFLAG
) == 0)
13392 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13396 if ((prefixes
& PREFIX_DATA
)
13398 || (sizeflag
& SUFFIX_ALWAYS
))
13405 if (sizeflag
& DFLAG
)
13409 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13416 if (address_mode
== mode_64bit
13417 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13419 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13423 /* Fall through. */
13426 if (l
== 0 && len
== 1)
13429 if (intel_syntax
&& !alt
)
13432 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13438 if (sizeflag
& DFLAG
)
13439 *obufp
++ = intel_syntax
? 'd' : 'l';
13442 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13448 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13454 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13469 else if (sizeflag
& DFLAG
)
13478 if (intel_syntax
&& !p
[1]
13479 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13481 if (!(rex
& REX_W
))
13482 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13485 if (l
== 0 && len
== 1)
13489 if (address_mode
== mode_64bit
13490 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13492 if (sizeflag
& SUFFIX_ALWAYS
)
13514 /* Fall through. */
13517 if (l
== 0 && len
== 1)
13522 if (sizeflag
& SUFFIX_ALWAYS
)
13528 if (sizeflag
& DFLAG
)
13532 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13546 if (address_mode
== mode_64bit
13547 && !(prefixes
& PREFIX_ADDR
))
13558 if (l
!= 0 || len
!= 1)
13563 if (need_vex
&& vex
.prefix
)
13565 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13572 if (prefixes
& PREFIX_DATA
)
13576 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13580 if (l
== 0 && len
== 1)
13582 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13593 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13601 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13603 switch (vex
.length
)
13617 if (l
== 0 && len
== 1)
13619 /* operand size flag for cwtl, cbtw */
13628 else if (sizeflag
& DFLAG
)
13632 if (!(rex
& REX_W
))
13633 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13640 && last
[0] != 'L'))
13647 if (last
[0] == 'X')
13648 *obufp
++ = vex
.w
? 'd': 's';
13650 *obufp
++ = vex
.w
? 'q': 'd';
13657 mnemonicendp
= obufp
;
13662 oappend (const char *s
)
13664 obufp
= stpcpy (obufp
, s
);
13670 if (prefixes
& PREFIX_CS
)
13672 used_prefixes
|= PREFIX_CS
;
13673 oappend_maybe_intel ("%cs:");
13675 if (prefixes
& PREFIX_DS
)
13677 used_prefixes
|= PREFIX_DS
;
13678 oappend_maybe_intel ("%ds:");
13680 if (prefixes
& PREFIX_SS
)
13682 used_prefixes
|= PREFIX_SS
;
13683 oappend_maybe_intel ("%ss:");
13685 if (prefixes
& PREFIX_ES
)
13687 used_prefixes
|= PREFIX_ES
;
13688 oappend_maybe_intel ("%es:");
13690 if (prefixes
& PREFIX_FS
)
13692 used_prefixes
|= PREFIX_FS
;
13693 oappend_maybe_intel ("%fs:");
13695 if (prefixes
& PREFIX_GS
)
13697 used_prefixes
|= PREFIX_GS
;
13698 oappend_maybe_intel ("%gs:");
13703 OP_indirE (int bytemode
, int sizeflag
)
13707 OP_E (bytemode
, sizeflag
);
13711 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13713 if (address_mode
== mode_64bit
)
13721 sprintf_vma (tmp
, disp
);
13722 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13723 strcpy (buf
+ 2, tmp
+ i
);
13727 bfd_signed_vma v
= disp
;
13734 /* Check for possible overflow on 0x8000000000000000. */
13737 strcpy (buf
, "9223372036854775808");
13751 tmp
[28 - i
] = (v
% 10) + '0';
13755 strcpy (buf
, tmp
+ 29 - i
);
13761 sprintf (buf
, "0x%x", (unsigned int) disp
);
13763 sprintf (buf
, "%d", (int) disp
);
13767 /* Put DISP in BUF as signed hex number. */
13770 print_displacement (char *buf
, bfd_vma disp
)
13772 bfd_signed_vma val
= disp
;
13781 /* Check for possible overflow. */
13784 switch (address_mode
)
13787 strcpy (buf
+ j
, "0x8000000000000000");
13790 strcpy (buf
+ j
, "0x80000000");
13793 strcpy (buf
+ j
, "0x8000");
13803 sprintf_vma (tmp
, (bfd_vma
) val
);
13804 for (i
= 0; tmp
[i
] == '0'; i
++)
13806 if (tmp
[i
] == '\0')
13808 strcpy (buf
+ j
, tmp
+ i
);
13812 intel_operand_size (int bytemode
, int sizeflag
)
13816 && (bytemode
== x_mode
13817 || bytemode
== evex_half_bcst_xmmq_mode
))
13820 oappend ("QWORD PTR ");
13822 oappend ("DWORD PTR ");
13830 oappend ("BYTE PTR ");
13834 oappend ("WORD PTR ");
13837 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13839 oappend ("QWORD PTR ");
13848 oappend ("QWORD PTR ");
13851 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13852 oappend ("DWORD PTR ");
13854 oappend ("WORD PTR ");
13855 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13859 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13861 oappend ("WORD PTR ");
13862 if (!(rex
& REX_W
))
13863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13866 if (sizeflag
& DFLAG
)
13867 oappend ("QWORD PTR ");
13869 oappend ("DWORD PTR ");
13870 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13873 case d_scalar_mode
:
13874 case d_scalar_swap_mode
:
13877 oappend ("DWORD PTR ");
13880 case q_scalar_mode
:
13881 case q_scalar_swap_mode
:
13883 oappend ("QWORD PTR ");
13886 if (address_mode
== mode_64bit
)
13887 oappend ("QWORD PTR ");
13889 oappend ("DWORD PTR ");
13892 if (sizeflag
& DFLAG
)
13893 oappend ("FWORD PTR ");
13895 oappend ("DWORD PTR ");
13896 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13899 oappend ("TBYTE PTR ");
13903 case evex_x_gscat_mode
:
13904 case evex_x_nobcst_mode
:
13907 switch (vex
.length
)
13910 oappend ("XMMWORD PTR ");
13913 oappend ("YMMWORD PTR ");
13916 oappend ("ZMMWORD PTR ");
13923 oappend ("XMMWORD PTR ");
13926 oappend ("XMMWORD PTR ");
13929 oappend ("YMMWORD PTR ");
13932 case evex_half_bcst_xmmq_mode
:
13936 switch (vex
.length
)
13939 oappend ("QWORD PTR ");
13942 oappend ("XMMWORD PTR ");
13945 oappend ("YMMWORD PTR ");
13955 switch (vex
.length
)
13960 oappend ("BYTE PTR ");
13970 switch (vex
.length
)
13975 oappend ("WORD PTR ");
13985 switch (vex
.length
)
13990 oappend ("DWORD PTR ");
14000 switch (vex
.length
)
14005 oappend ("QWORD PTR ");
14015 switch (vex
.length
)
14018 oappend ("WORD PTR ");
14021 oappend ("DWORD PTR ");
14024 oappend ("QWORD PTR ");
14034 switch (vex
.length
)
14037 oappend ("DWORD PTR ");
14040 oappend ("QWORD PTR ");
14043 oappend ("XMMWORD PTR ");
14053 switch (vex
.length
)
14056 oappend ("QWORD PTR ");
14059 oappend ("YMMWORD PTR ");
14062 oappend ("ZMMWORD PTR ");
14072 switch (vex
.length
)
14076 oappend ("XMMWORD PTR ");
14083 oappend ("OWORD PTR ");
14086 case vex_w_dq_mode
:
14087 case vex_scalar_w_dq_mode
:
14092 oappend ("QWORD PTR ");
14094 oappend ("DWORD PTR ");
14096 case vex_vsib_d_w_dq_mode
:
14097 case vex_vsib_q_w_dq_mode
:
14104 oappend ("QWORD PTR ");
14106 oappend ("DWORD PTR ");
14110 if (vex
.length
!= 512)
14112 oappend ("ZMMWORD PTR ");
14118 /* Currently the only instructions, which allows either mask or
14119 memory operand, are AVX512's KMOVW instructions. They need
14120 Word-sized operand. */
14121 if (vex
.w
|| vex
.length
!= 128)
14123 oappend ("WORD PTR ");
14132 OP_E_register (int bytemode
, int sizeflag
)
14134 int reg
= modrm
.rm
;
14135 const char **names
;
14141 if ((sizeflag
& SUFFIX_ALWAYS
)
14142 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
14166 names
= address_mode
== mode_64bit
? names64
: names32
;
14172 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14190 if ((sizeflag
& DFLAG
)
14191 || (bytemode
!= v_mode
14192 && bytemode
!= v_swap_mode
))
14196 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14200 names
= names_mask
;
14205 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14208 oappend (names
[reg
]);
14212 OP_E_memory (int bytemode
, int sizeflag
)
14215 int add
= (rex
& REX_B
) ? 8 : 0;
14221 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14223 && bytemode
!= x_mode
14224 && bytemode
!= evex_half_bcst_xmmq_mode
)
14231 case vex_vsib_d_w_dq_mode
:
14232 case vex_vsib_q_w_dq_mode
:
14233 case evex_x_gscat_mode
:
14235 shift
= vex
.w
? 3 : 2;
14238 case evex_half_bcst_xmmq_mode
:
14241 shift
= vex
.w
? 3 : 2;
14244 /* Fall through if vex.b == 0. */
14249 case evex_x_nobcst_mode
:
14251 switch (vex
.length
)
14274 case q_scalar_mode
:
14276 case q_scalar_swap_mode
:
14282 case d_scalar_mode
:
14284 case d_scalar_swap_mode
:
14296 /* Make necessary corrections to shift for modes that need it.
14297 For these modes we currently have shift 4, 5 or 6 depending on
14298 vex.length (it corresponds to xmmword, ymmword or zmmword
14299 operand). We might want to make it 3, 4 or 5 (e.g. for
14300 xmmq_mode). In case of broadcast enabled the corrections
14301 aren't needed, as element size is always 32 or 64 bits. */
14302 if (bytemode
== xmmq_mode
14303 || (bytemode
== evex_half_bcst_xmmq_mode
14306 else if (bytemode
== xmmqd_mode
)
14308 else if (bytemode
== xmmdw_mode
)
14316 intel_operand_size (bytemode
, sizeflag
);
14319 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14321 /* 32/64 bit address mode */
14330 int addr32flag
= !((sizeflag
& AFLAG
)
14331 || bytemode
== v_bnd_mode
14332 || bytemode
== bnd_mode
);
14333 const char **indexes64
= names64
;
14334 const char **indexes32
= names32
;
14344 vindex
= sib
.index
;
14350 case vex_vsib_d_w_dq_mode
:
14351 case vex_vsib_q_w_dq_mode
:
14361 switch (vex
.length
)
14364 indexes64
= indexes32
= names_xmm
;
14367 if (!vex
.w
|| bytemode
== vex_vsib_q_w_dq_mode
)
14368 indexes64
= indexes32
= names_ymm
;
14370 indexes64
= indexes32
= names_xmm
;
14373 if (!vex
.w
|| bytemode
== vex_vsib_q_w_dq_mode
)
14374 indexes64
= indexes32
= names_zmm
;
14376 indexes64
= indexes32
= names_ymm
;
14383 haveindex
= vindex
!= 4;
14390 rbase
= base
+ add
;
14398 if (address_mode
== mode_64bit
&& !havesib
)
14404 FETCH_DATA (the_info
, codep
+ 1);
14406 if ((disp
& 0x80) != 0)
14408 if (vex
.evex
&& shift
> 0)
14416 /* In 32bit mode, we need index register to tell [offset] from
14417 [eiz*1 + offset]. */
14418 needindex
= (havesib
14421 && address_mode
== mode_32bit
);
14422 havedisp
= (havebase
14424 || (havesib
&& (haveindex
|| scale
!= 0)));
14427 if (modrm
.mod
!= 0 || base
== 5)
14429 if (havedisp
|| riprel
)
14430 print_displacement (scratchbuf
, disp
);
14432 print_operand_value (scratchbuf
, 1, disp
);
14433 oappend (scratchbuf
);
14437 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14441 if ((havebase
|| haveindex
|| riprel
)
14442 && (bytemode
!= v_bnd_mode
)
14443 && (bytemode
!= bnd_mode
))
14444 used_prefixes
|= PREFIX_ADDR
;
14446 if (havedisp
|| (intel_syntax
&& riprel
))
14448 *obufp
++ = open_char
;
14449 if (intel_syntax
&& riprel
)
14452 oappend (sizeflag
& AFLAG
? "rip" : "eip");
14456 oappend (address_mode
== mode_64bit
&& !addr32flag
14457 ? names64
[rbase
] : names32
[rbase
]);
14460 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14461 print index to tell base + index from base. */
14465 || (havebase
&& base
!= ESP_REG_NUM
))
14467 if (!intel_syntax
|| havebase
)
14469 *obufp
++ = separator_char
;
14473 oappend (address_mode
== mode_64bit
&& !addr32flag
14474 ? indexes64
[vindex
] : indexes32
[vindex
]);
14476 oappend (address_mode
== mode_64bit
&& !addr32flag
14477 ? index64
: index32
);
14479 *obufp
++ = scale_char
;
14481 sprintf (scratchbuf
, "%d", 1 << scale
);
14482 oappend (scratchbuf
);
14486 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14488 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14493 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14497 disp
= - (bfd_signed_vma
) disp
;
14501 print_displacement (scratchbuf
, disp
);
14503 print_operand_value (scratchbuf
, 1, disp
);
14504 oappend (scratchbuf
);
14507 *obufp
++ = close_char
;
14510 else if (intel_syntax
)
14512 if (modrm
.mod
!= 0 || base
== 5)
14514 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
14515 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
14519 oappend (names_seg
[ds_reg
- es_reg
]);
14522 print_operand_value (scratchbuf
, 1, disp
);
14523 oappend (scratchbuf
);
14529 /* 16 bit address mode */
14530 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14537 if ((disp
& 0x8000) != 0)
14542 FETCH_DATA (the_info
, codep
+ 1);
14544 if ((disp
& 0x80) != 0)
14549 if ((disp
& 0x8000) != 0)
14555 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14557 print_displacement (scratchbuf
, disp
);
14558 oappend (scratchbuf
);
14561 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14563 *obufp
++ = open_char
;
14565 oappend (index16
[modrm
.rm
]);
14567 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14569 if ((bfd_signed_vma
) disp
>= 0)
14574 else if (modrm
.mod
!= 1)
14578 disp
= - (bfd_signed_vma
) disp
;
14581 print_displacement (scratchbuf
, disp
);
14582 oappend (scratchbuf
);
14585 *obufp
++ = close_char
;
14588 else if (intel_syntax
)
14590 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
14591 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
14595 oappend (names_seg
[ds_reg
- es_reg
]);
14598 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14599 oappend (scratchbuf
);
14602 if (vex
.evex
&& vex
.b
14603 && (bytemode
== x_mode
14604 || bytemode
== evex_half_bcst_xmmq_mode
))
14606 if (vex
.w
|| bytemode
== evex_half_bcst_xmmq_mode
)
14607 oappend ("{1to8}");
14609 oappend ("{1to16}");
14614 OP_E (int bytemode
, int sizeflag
)
14616 /* Skip mod/rm byte. */
14620 if (modrm
.mod
== 3)
14621 OP_E_register (bytemode
, sizeflag
);
14623 OP_E_memory (bytemode
, sizeflag
);
14627 OP_G (int bytemode
, int sizeflag
)
14638 oappend (names8rex
[modrm
.reg
+ add
]);
14640 oappend (names8
[modrm
.reg
+ add
]);
14643 oappend (names16
[modrm
.reg
+ add
]);
14646 oappend (names32
[modrm
.reg
+ add
]);
14649 oappend (names64
[modrm
.reg
+ add
]);
14652 oappend (names_bnd
[modrm
.reg
]);
14661 oappend (names64
[modrm
.reg
+ add
]);
14664 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14665 oappend (names32
[modrm
.reg
+ add
]);
14667 oappend (names16
[modrm
.reg
+ add
]);
14668 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14672 if (address_mode
== mode_64bit
)
14673 oappend (names64
[modrm
.reg
+ add
]);
14675 oappend (names32
[modrm
.reg
+ add
]);
14678 oappend (names_mask
[modrm
.reg
+ add
]);
14681 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14694 FETCH_DATA (the_info
, codep
+ 8);
14695 a
= *codep
++ & 0xff;
14696 a
|= (*codep
++ & 0xff) << 8;
14697 a
|= (*codep
++ & 0xff) << 16;
14698 a
|= (*codep
++ & 0xff) << 24;
14699 b
= *codep
++ & 0xff;
14700 b
|= (*codep
++ & 0xff) << 8;
14701 b
|= (*codep
++ & 0xff) << 16;
14702 b
|= (*codep
++ & 0xff) << 24;
14703 x
= a
+ ((bfd_vma
) b
<< 32);
14711 static bfd_signed_vma
14714 bfd_signed_vma x
= 0;
14716 FETCH_DATA (the_info
, codep
+ 4);
14717 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14718 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14719 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14720 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14724 static bfd_signed_vma
14727 bfd_signed_vma x
= 0;
14729 FETCH_DATA (the_info
, codep
+ 4);
14730 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14731 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14732 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14733 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14735 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14745 FETCH_DATA (the_info
, codep
+ 2);
14746 x
= *codep
++ & 0xff;
14747 x
|= (*codep
++ & 0xff) << 8;
14752 set_op (bfd_vma op
, int riprel
)
14754 op_index
[op_ad
] = op_ad
;
14755 if (address_mode
== mode_64bit
)
14757 op_address
[op_ad
] = op
;
14758 op_riprel
[op_ad
] = riprel
;
14762 /* Mask to get a 32-bit address. */
14763 op_address
[op_ad
] = op
& 0xffffffff;
14764 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14769 OP_REG (int code
, int sizeflag
)
14776 case es_reg
: case ss_reg
: case cs_reg
:
14777 case ds_reg
: case fs_reg
: case gs_reg
:
14778 oappend (names_seg
[code
- es_reg
]);
14790 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14791 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14792 s
= names16
[code
- ax_reg
+ add
];
14794 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14795 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14798 s
= names8rex
[code
- al_reg
+ add
];
14800 s
= names8
[code
- al_reg
];
14802 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14803 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14804 if (address_mode
== mode_64bit
14805 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14807 s
= names64
[code
- rAX_reg
+ add
];
14810 code
+= eAX_reg
- rAX_reg
;
14811 /* Fall through. */
14812 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14813 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14816 s
= names64
[code
- eAX_reg
+ add
];
14819 if (sizeflag
& DFLAG
)
14820 s
= names32
[code
- eAX_reg
+ add
];
14822 s
= names16
[code
- eAX_reg
+ add
];
14823 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14827 s
= INTERNAL_DISASSEMBLER_ERROR
;
14834 OP_IMREG (int code
, int sizeflag
)
14846 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14847 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14848 s
= names16
[code
- ax_reg
];
14850 case es_reg
: case ss_reg
: case cs_reg
:
14851 case ds_reg
: case fs_reg
: case gs_reg
:
14852 s
= names_seg
[code
- es_reg
];
14854 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14855 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14858 s
= names8rex
[code
- al_reg
];
14860 s
= names8
[code
- al_reg
];
14862 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14863 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14866 s
= names64
[code
- eAX_reg
];
14869 if (sizeflag
& DFLAG
)
14870 s
= names32
[code
- eAX_reg
];
14872 s
= names16
[code
- eAX_reg
];
14873 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14876 case z_mode_ax_reg
:
14877 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14881 if (!(rex
& REX_W
))
14882 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14885 s
= INTERNAL_DISASSEMBLER_ERROR
;
14892 OP_I (int bytemode
, int sizeflag
)
14895 bfd_signed_vma mask
= -1;
14900 FETCH_DATA (the_info
, codep
+ 1);
14905 if (address_mode
== mode_64bit
)
14910 /* Fall through. */
14917 if (sizeflag
& DFLAG
)
14927 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14939 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14944 scratchbuf
[0] = '$';
14945 print_operand_value (scratchbuf
+ 1, 1, op
);
14946 oappend_maybe_intel (scratchbuf
);
14947 scratchbuf
[0] = '\0';
14951 OP_I64 (int bytemode
, int sizeflag
)
14954 bfd_signed_vma mask
= -1;
14956 if (address_mode
!= mode_64bit
)
14958 OP_I (bytemode
, sizeflag
);
14965 FETCH_DATA (the_info
, codep
+ 1);
14975 if (sizeflag
& DFLAG
)
14985 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14993 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14998 scratchbuf
[0] = '$';
14999 print_operand_value (scratchbuf
+ 1, 1, op
);
15000 oappend_maybe_intel (scratchbuf
);
15001 scratchbuf
[0] = '\0';
15005 OP_sI (int bytemode
, int sizeflag
)
15013 FETCH_DATA (the_info
, codep
+ 1);
15015 if ((op
& 0x80) != 0)
15017 if (bytemode
== b_T_mode
)
15019 if (address_mode
!= mode_64bit
15020 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15022 /* The operand-size prefix is overridden by a REX prefix. */
15023 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15031 if (!(rex
& REX_W
))
15033 if (sizeflag
& DFLAG
)
15041 /* The operand-size prefix is overridden by a REX prefix. */
15042 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15048 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15052 scratchbuf
[0] = '$';
15053 print_operand_value (scratchbuf
+ 1, 1, op
);
15054 oappend_maybe_intel (scratchbuf
);
15058 OP_J (int bytemode
, int sizeflag
)
15062 bfd_vma segment
= 0;
15067 FETCH_DATA (the_info
, codep
+ 1);
15069 if ((disp
& 0x80) != 0)
15074 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15079 if ((disp
& 0x8000) != 0)
15081 /* In 16bit mode, address is wrapped around at 64k within
15082 the same segment. Otherwise, a data16 prefix on a jump
15083 instruction means that the pc is masked to 16 bits after
15084 the displacement is added! */
15086 if ((prefixes
& PREFIX_DATA
) == 0)
15087 segment
= ((start_pc
+ codep
- start_codep
)
15088 & ~((bfd_vma
) 0xffff));
15090 if (!(rex
& REX_W
))
15091 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15094 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15097 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15099 print_operand_value (scratchbuf
, 1, disp
);
15100 oappend (scratchbuf
);
15104 OP_SEG (int bytemode
, int sizeflag
)
15106 if (bytemode
== w_mode
)
15107 oappend (names_seg
[modrm
.reg
]);
15109 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15113 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15117 if (sizeflag
& DFLAG
)
15127 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15129 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15131 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15132 oappend (scratchbuf
);
15136 OP_OFF (int bytemode
, int sizeflag
)
15140 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15141 intel_operand_size (bytemode
, sizeflag
);
15144 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15151 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
15152 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
15154 oappend (names_seg
[ds_reg
- es_reg
]);
15158 print_operand_value (scratchbuf
, 1, off
);
15159 oappend (scratchbuf
);
15163 OP_OFF64 (int bytemode
, int sizeflag
)
15167 if (address_mode
!= mode_64bit
15168 || (prefixes
& PREFIX_ADDR
))
15170 OP_OFF (bytemode
, sizeflag
);
15174 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15175 intel_operand_size (bytemode
, sizeflag
);
15182 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
15183 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
15185 oappend (names_seg
[ds_reg
- es_reg
]);
15189 print_operand_value (scratchbuf
, 1, off
);
15190 oappend (scratchbuf
);
15194 ptr_reg (int code
, int sizeflag
)
15198 *obufp
++ = open_char
;
15199 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15200 if (address_mode
== mode_64bit
)
15202 if (!(sizeflag
& AFLAG
))
15203 s
= names32
[code
- eAX_reg
];
15205 s
= names64
[code
- eAX_reg
];
15207 else if (sizeflag
& AFLAG
)
15208 s
= names32
[code
- eAX_reg
];
15210 s
= names16
[code
- eAX_reg
];
15212 *obufp
++ = close_char
;
15217 OP_ESreg (int code
, int sizeflag
)
15223 case 0x6d: /* insw/insl */
15224 intel_operand_size (z_mode
, sizeflag
);
15226 case 0xa5: /* movsw/movsl/movsq */
15227 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15228 case 0xab: /* stosw/stosl */
15229 case 0xaf: /* scasw/scasl */
15230 intel_operand_size (v_mode
, sizeflag
);
15233 intel_operand_size (b_mode
, sizeflag
);
15236 oappend_maybe_intel ("%es:");
15237 ptr_reg (code
, sizeflag
);
15241 OP_DSreg (int code
, int sizeflag
)
15247 case 0x6f: /* outsw/outsl */
15248 intel_operand_size (z_mode
, sizeflag
);
15250 case 0xa5: /* movsw/movsl/movsq */
15251 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15252 case 0xad: /* lodsw/lodsl/lodsq */
15253 intel_operand_size (v_mode
, sizeflag
);
15256 intel_operand_size (b_mode
, sizeflag
);
15265 | PREFIX_GS
)) == 0)
15266 prefixes
|= PREFIX_DS
;
15268 ptr_reg (code
, sizeflag
);
15272 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15280 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15282 all_prefixes
[last_lock_prefix
] = 0;
15283 used_prefixes
|= PREFIX_LOCK
;
15288 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15289 oappend_maybe_intel (scratchbuf
);
15293 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15302 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15304 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15305 oappend (scratchbuf
);
15309 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15311 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15312 oappend_maybe_intel (scratchbuf
);
15316 OP_R (int bytemode
, int sizeflag
)
15318 if (modrm
.mod
== 3)
15319 OP_E (bytemode
, sizeflag
);
15325 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15327 int reg
= modrm
.reg
;
15328 const char **names
;
15330 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15331 if (prefixes
& PREFIX_DATA
)
15340 oappend (names
[reg
]);
15344 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15346 int reg
= modrm
.reg
;
15347 const char **names
;
15359 && bytemode
!= xmm_mode
15360 && bytemode
!= xmmq_mode
15361 && bytemode
!= evex_half_bcst_xmmq_mode
15362 && bytemode
!= ymm_mode
15363 && bytemode
!= scalar_mode
)
15365 switch (vex
.length
)
15371 if (vex
.w
|| bytemode
!= vex_vsib_q_w_dq_mode
)
15383 else if (bytemode
== xmmq_mode
15384 || bytemode
== evex_half_bcst_xmmq_mode
)
15386 switch (vex
.length
)
15399 else if (bytemode
== ymm_mode
)
15403 oappend (names
[reg
]);
15407 OP_EM (int bytemode
, int sizeflag
)
15410 const char **names
;
15412 if (modrm
.mod
!= 3)
15415 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15417 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15420 OP_E (bytemode
, sizeflag
);
15424 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15427 /* Skip mod/rm byte. */
15430 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15432 if (prefixes
& PREFIX_DATA
)
15441 oappend (names
[reg
]);
15444 /* cvt* are the only instructions in sse2 which have
15445 both SSE and MMX operands and also have 0x66 prefix
15446 in their opcode. 0x66 was originally used to differentiate
15447 between SSE and MMX instruction(operands). So we have to handle the
15448 cvt* separately using OP_EMC and OP_MXC */
15450 OP_EMC (int bytemode
, int sizeflag
)
15452 if (modrm
.mod
!= 3)
15454 if (intel_syntax
&& bytemode
== v_mode
)
15456 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15457 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15459 OP_E (bytemode
, sizeflag
);
15463 /* Skip mod/rm byte. */
15466 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15467 oappend (names_mm
[modrm
.rm
]);
15471 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15473 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15474 oappend (names_mm
[modrm
.reg
]);
15478 OP_EX (int bytemode
, int sizeflag
)
15481 const char **names
;
15483 /* Skip mod/rm byte. */
15487 if (modrm
.mod
!= 3)
15489 OP_E_memory (bytemode
, sizeflag
);
15504 if ((sizeflag
& SUFFIX_ALWAYS
)
15505 && (bytemode
== x_swap_mode
15506 || bytemode
== d_swap_mode
15507 || bytemode
== d_scalar_swap_mode
15508 || bytemode
== q_swap_mode
15509 || bytemode
== q_scalar_swap_mode
))
15513 && bytemode
!= xmm_mode
15514 && bytemode
!= xmmdw_mode
15515 && bytemode
!= xmmqd_mode
15516 && bytemode
!= xmm_mb_mode
15517 && bytemode
!= xmm_mw_mode
15518 && bytemode
!= xmm_md_mode
15519 && bytemode
!= xmm_mq_mode
15520 && bytemode
!= xmm_mdq_mode
15521 && bytemode
!= xmmq_mode
15522 && bytemode
!= evex_half_bcst_xmmq_mode
15523 && bytemode
!= ymm_mode
15524 && bytemode
!= d_scalar_mode
15525 && bytemode
!= d_scalar_swap_mode
15526 && bytemode
!= q_scalar_mode
15527 && bytemode
!= q_scalar_swap_mode
15528 && bytemode
!= vex_scalar_w_dq_mode
)
15530 switch (vex
.length
)
15545 else if (bytemode
== xmmq_mode
15546 || bytemode
== evex_half_bcst_xmmq_mode
)
15548 switch (vex
.length
)
15561 else if (bytemode
== ymm_mode
)
15565 oappend (names
[reg
]);
15569 OP_MS (int bytemode
, int sizeflag
)
15571 if (modrm
.mod
== 3)
15572 OP_EM (bytemode
, sizeflag
);
15578 OP_XS (int bytemode
, int sizeflag
)
15580 if (modrm
.mod
== 3)
15581 OP_EX (bytemode
, sizeflag
);
15587 OP_M (int bytemode
, int sizeflag
)
15589 if (modrm
.mod
== 3)
15590 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15593 OP_E (bytemode
, sizeflag
);
15597 OP_0f07 (int bytemode
, int sizeflag
)
15599 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15602 OP_E (bytemode
, sizeflag
);
15605 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15606 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15609 NOP_Fixup1 (int bytemode
, int sizeflag
)
15611 if ((prefixes
& PREFIX_DATA
) != 0
15614 && address_mode
== mode_64bit
))
15615 OP_REG (bytemode
, sizeflag
);
15617 strcpy (obuf
, "nop");
15621 NOP_Fixup2 (int bytemode
, int sizeflag
)
15623 if ((prefixes
& PREFIX_DATA
) != 0
15626 && address_mode
== mode_64bit
))
15627 OP_IMREG (bytemode
, sizeflag
);
15630 static const char *const Suffix3DNow
[] = {
15631 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15632 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15633 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15634 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15635 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15636 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15637 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15638 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15639 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15640 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15641 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15642 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15643 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15644 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15645 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15646 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15647 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15648 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15649 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15650 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15651 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15652 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15653 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15654 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15655 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15656 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15657 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15658 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15659 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15660 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15661 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15662 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15663 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15664 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15665 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15666 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15667 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15668 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15669 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15670 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15671 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15672 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15673 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15674 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15675 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15676 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15677 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15678 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15679 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15680 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15681 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15682 /* CC */ NULL
, NULL
, NULL
, NULL
,
15683 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15684 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15685 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15686 /* DC */ NULL
, NULL
, NULL
, NULL
,
15687 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15688 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15689 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15690 /* EC */ NULL
, NULL
, NULL
, NULL
,
15691 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15692 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15693 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15694 /* FC */ NULL
, NULL
, NULL
, NULL
,
15698 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15700 const char *mnemonic
;
15702 FETCH_DATA (the_info
, codep
+ 1);
15703 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15704 place where an 8-bit immediate would normally go. ie. the last
15705 byte of the instruction. */
15706 obufp
= mnemonicendp
;
15707 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15709 oappend (mnemonic
);
15712 /* Since a variable sized modrm/sib chunk is between the start
15713 of the opcode (0x0f0f) and the opcode suffix, we need to do
15714 all the modrm processing first, and don't know until now that
15715 we have a bad opcode. This necessitates some cleaning up. */
15716 op_out
[0][0] = '\0';
15717 op_out
[1][0] = '\0';
15720 mnemonicendp
= obufp
;
15723 static struct op simd_cmp_op
[] =
15725 { STRING_COMMA_LEN ("eq") },
15726 { STRING_COMMA_LEN ("lt") },
15727 { STRING_COMMA_LEN ("le") },
15728 { STRING_COMMA_LEN ("unord") },
15729 { STRING_COMMA_LEN ("neq") },
15730 { STRING_COMMA_LEN ("nlt") },
15731 { STRING_COMMA_LEN ("nle") },
15732 { STRING_COMMA_LEN ("ord") }
15736 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15738 unsigned int cmp_type
;
15740 FETCH_DATA (the_info
, codep
+ 1);
15741 cmp_type
= *codep
++ & 0xff;
15742 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15745 char *p
= mnemonicendp
- 2;
15749 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15750 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15754 /* We have a reserved extension byte. Output it directly. */
15755 scratchbuf
[0] = '$';
15756 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15757 oappend_maybe_intel (scratchbuf
);
15758 scratchbuf
[0] = '\0';
15763 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15764 int sizeflag ATTRIBUTE_UNUSED
)
15766 /* mwait %eax,%ecx */
15769 const char **names
= (address_mode
== mode_64bit
15770 ? names64
: names32
);
15771 strcpy (op_out
[0], names
[0]);
15772 strcpy (op_out
[1], names
[1]);
15773 two_source_ops
= 1;
15775 /* Skip mod/rm byte. */
15781 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15782 int sizeflag ATTRIBUTE_UNUSED
)
15784 /* monitor %eax,%ecx,%edx" */
15787 const char **op1_names
;
15788 const char **names
= (address_mode
== mode_64bit
15789 ? names64
: names32
);
15791 if (!(prefixes
& PREFIX_ADDR
))
15792 op1_names
= (address_mode
== mode_16bit
15793 ? names16
: names
);
15796 /* Remove "addr16/addr32". */
15797 all_prefixes
[last_addr_prefix
] = 0;
15798 op1_names
= (address_mode
!= mode_32bit
15799 ? names32
: names16
);
15800 used_prefixes
|= PREFIX_ADDR
;
15802 strcpy (op_out
[0], op1_names
[0]);
15803 strcpy (op_out
[1], names
[1]);
15804 strcpy (op_out
[2], names
[2]);
15805 two_source_ops
= 1;
15807 /* Skip mod/rm byte. */
15815 /* Throw away prefixes and 1st. opcode byte. */
15816 codep
= insn_codep
+ 1;
15821 REP_Fixup (int bytemode
, int sizeflag
)
15823 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15825 if (prefixes
& PREFIX_REPZ
)
15826 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15833 OP_IMREG (bytemode
, sizeflag
);
15836 OP_ESreg (bytemode
, sizeflag
);
15839 OP_DSreg (bytemode
, sizeflag
);
15847 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15851 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15853 if (prefixes
& PREFIX_REPNZ
)
15854 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15857 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15858 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15862 HLE_Fixup1 (int bytemode
, int sizeflag
)
15865 && (prefixes
& PREFIX_LOCK
) != 0)
15867 if (prefixes
& PREFIX_REPZ
)
15868 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15869 if (prefixes
& PREFIX_REPNZ
)
15870 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15873 OP_E (bytemode
, sizeflag
);
15876 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15877 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15881 HLE_Fixup2 (int bytemode
, int sizeflag
)
15883 if (modrm
.mod
!= 3)
15885 if (prefixes
& PREFIX_REPZ
)
15886 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15887 if (prefixes
& PREFIX_REPNZ
)
15888 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15891 OP_E (bytemode
, sizeflag
);
15894 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15895 "xrelease" for memory operand. No check for LOCK prefix. */
15898 HLE_Fixup3 (int bytemode
, int sizeflag
)
15901 && last_repz_prefix
> last_repnz_prefix
15902 && (prefixes
& PREFIX_REPZ
) != 0)
15903 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15905 OP_E (bytemode
, sizeflag
);
15909 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15914 /* Change cmpxchg8b to cmpxchg16b. */
15915 char *p
= mnemonicendp
- 2;
15916 mnemonicendp
= stpcpy (p
, "16b");
15919 else if ((prefixes
& PREFIX_LOCK
) != 0)
15921 if (prefixes
& PREFIX_REPZ
)
15922 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15923 if (prefixes
& PREFIX_REPNZ
)
15924 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15927 OP_M (bytemode
, sizeflag
);
15931 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15933 const char **names
;
15937 switch (vex
.length
)
15951 oappend (names
[reg
]);
15955 CRC32_Fixup (int bytemode
, int sizeflag
)
15957 /* Add proper suffix to "crc32". */
15958 char *p
= mnemonicendp
;
15977 if (sizeflag
& DFLAG
)
15981 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15985 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15992 if (modrm
.mod
== 3)
15996 /* Skip mod/rm byte. */
16001 add
= (rex
& REX_B
) ? 8 : 0;
16002 if (bytemode
== b_mode
)
16006 oappend (names8rex
[modrm
.rm
+ add
]);
16008 oappend (names8
[modrm
.rm
+ add
]);
16014 oappend (names64
[modrm
.rm
+ add
]);
16015 else if ((prefixes
& PREFIX_DATA
))
16016 oappend (names16
[modrm
.rm
+ add
]);
16018 oappend (names32
[modrm
.rm
+ add
]);
16022 OP_E (bytemode
, sizeflag
);
16026 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16028 /* Add proper suffix to "fxsave" and "fxrstor". */
16032 char *p
= mnemonicendp
;
16038 OP_M (bytemode
, sizeflag
);
16041 /* Display the destination register operand for instructions with
16045 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16048 const char **names
;
16056 reg
= vex
.register_specifier
;
16063 if (bytemode
== vex_scalar_mode
)
16065 oappend (names_xmm
[reg
]);
16069 switch (vex
.length
)
16076 case vex_vsib_q_w_dq_mode
:
16086 names
= names_mask
;
16100 case vex_vsib_q_w_dq_mode
:
16101 names
= vex
.w
? names_ymm
: names_xmm
;
16104 names
= names_mask
;
16118 oappend (names
[reg
]);
16121 /* Get the VEX immediate byte without moving codep. */
16123 static unsigned char
16124 get_vex_imm8 (int sizeflag
, int opnum
)
16126 int bytes_before_imm
= 0;
16128 if (modrm
.mod
!= 3)
16130 /* There are SIB/displacement bytes. */
16131 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16133 /* 32/64 bit address mode */
16134 int base
= modrm
.rm
;
16136 /* Check SIB byte. */
16139 FETCH_DATA (the_info
, codep
+ 1);
16141 /* When decoding the third source, don't increase
16142 bytes_before_imm as this has already been incremented
16143 by one in OP_E_memory while decoding the second
16146 bytes_before_imm
++;
16149 /* Don't increase bytes_before_imm when decoding the third source,
16150 it has already been incremented by OP_E_memory while decoding
16151 the second source operand. */
16157 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16158 SIB == 5, there is a 4 byte displacement. */
16160 /* No displacement. */
16163 /* 4 byte displacement. */
16164 bytes_before_imm
+= 4;
16167 /* 1 byte displacement. */
16168 bytes_before_imm
++;
16175 /* 16 bit address mode */
16176 /* Don't increase bytes_before_imm when decoding the third source,
16177 it has already been incremented by OP_E_memory while decoding
16178 the second source operand. */
16184 /* When modrm.rm == 6, there is a 2 byte displacement. */
16186 /* No displacement. */
16189 /* 2 byte displacement. */
16190 bytes_before_imm
+= 2;
16193 /* 1 byte displacement: when decoding the third source,
16194 don't increase bytes_before_imm as this has already
16195 been incremented by one in OP_E_memory while decoding
16196 the second source operand. */
16198 bytes_before_imm
++;
16206 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16207 return codep
[bytes_before_imm
];
16211 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16213 const char **names
;
16215 if (reg
== -1 && modrm
.mod
!= 3)
16217 OP_E_memory (bytemode
, sizeflag
);
16229 else if (reg
> 7 && address_mode
!= mode_64bit
)
16233 switch (vex
.length
)
16244 oappend (names
[reg
]);
16248 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16251 static unsigned char vex_imm8
;
16253 if (vex_w_done
== 0)
16257 /* Skip mod/rm byte. */
16261 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16264 reg
= vex_imm8
>> 4;
16266 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16268 else if (vex_w_done
== 1)
16273 reg
= vex_imm8
>> 4;
16275 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16279 /* Output the imm8 directly. */
16280 scratchbuf
[0] = '$';
16281 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16282 oappend_maybe_intel (scratchbuf
);
16283 scratchbuf
[0] = '\0';
16289 OP_Vex_2src (int bytemode
, int sizeflag
)
16291 if (modrm
.mod
== 3)
16293 int reg
= modrm
.rm
;
16297 oappend (names_xmm
[reg
]);
16302 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16304 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16305 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16307 OP_E (bytemode
, sizeflag
);
16312 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16314 if (modrm
.mod
== 3)
16316 /* Skip mod/rm byte. */
16322 oappend (names_xmm
[vex
.register_specifier
]);
16324 OP_Vex_2src (bytemode
, sizeflag
);
16328 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16331 OP_Vex_2src (bytemode
, sizeflag
);
16333 oappend (names_xmm
[vex
.register_specifier
]);
16337 OP_EX_VexW (int bytemode
, int sizeflag
)
16345 /* Skip mod/rm byte. */
16350 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16355 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16358 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16362 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16363 int sizeflag ATTRIBUTE_UNUSED
)
16365 /* Skip the immediate byte and check for invalid bits. */
16366 FETCH_DATA (the_info
, codep
+ 1);
16367 if (*codep
++ & 0xf)
16372 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16375 const char **names
;
16377 FETCH_DATA (the_info
, codep
+ 1);
16380 if (bytemode
!= x_mode
)
16387 if (reg
> 7 && address_mode
!= mode_64bit
)
16390 switch (vex
.length
)
16401 oappend (names
[reg
]);
16405 OP_XMM_VexW (int bytemode
, int sizeflag
)
16407 /* Turn off the REX.W bit since it is used for swapping operands
16410 OP_XMM (bytemode
, sizeflag
);
16414 OP_EX_Vex (int bytemode
, int sizeflag
)
16416 if (modrm
.mod
!= 3)
16418 if (vex
.register_specifier
!= 0)
16422 OP_EX (bytemode
, sizeflag
);
16426 OP_XMM_Vex (int bytemode
, int sizeflag
)
16428 if (modrm
.mod
!= 3)
16430 if (vex
.register_specifier
!= 0)
16434 OP_XMM (bytemode
, sizeflag
);
16438 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16440 switch (vex
.length
)
16443 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
16446 mnemonicendp
= stpcpy (obuf
, "vzeroall");
16453 static struct op vex_cmp_op
[] =
16455 { STRING_COMMA_LEN ("eq") },
16456 { STRING_COMMA_LEN ("lt") },
16457 { STRING_COMMA_LEN ("le") },
16458 { STRING_COMMA_LEN ("unord") },
16459 { STRING_COMMA_LEN ("neq") },
16460 { STRING_COMMA_LEN ("nlt") },
16461 { STRING_COMMA_LEN ("nle") },
16462 { STRING_COMMA_LEN ("ord") },
16463 { STRING_COMMA_LEN ("eq_uq") },
16464 { STRING_COMMA_LEN ("nge") },
16465 { STRING_COMMA_LEN ("ngt") },
16466 { STRING_COMMA_LEN ("false") },
16467 { STRING_COMMA_LEN ("neq_oq") },
16468 { STRING_COMMA_LEN ("ge") },
16469 { STRING_COMMA_LEN ("gt") },
16470 { STRING_COMMA_LEN ("true") },
16471 { STRING_COMMA_LEN ("eq_os") },
16472 { STRING_COMMA_LEN ("lt_oq") },
16473 { STRING_COMMA_LEN ("le_oq") },
16474 { STRING_COMMA_LEN ("unord_s") },
16475 { STRING_COMMA_LEN ("neq_us") },
16476 { STRING_COMMA_LEN ("nlt_uq") },
16477 { STRING_COMMA_LEN ("nle_uq") },
16478 { STRING_COMMA_LEN ("ord_s") },
16479 { STRING_COMMA_LEN ("eq_us") },
16480 { STRING_COMMA_LEN ("nge_uq") },
16481 { STRING_COMMA_LEN ("ngt_uq") },
16482 { STRING_COMMA_LEN ("false_os") },
16483 { STRING_COMMA_LEN ("neq_os") },
16484 { STRING_COMMA_LEN ("ge_oq") },
16485 { STRING_COMMA_LEN ("gt_oq") },
16486 { STRING_COMMA_LEN ("true_us") },
16490 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16492 unsigned int cmp_type
;
16494 FETCH_DATA (the_info
, codep
+ 1);
16495 cmp_type
= *codep
++ & 0xff;
16496 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16499 char *p
= mnemonicendp
- 2;
16503 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16504 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16508 /* We have a reserved extension byte. Output it directly. */
16509 scratchbuf
[0] = '$';
16510 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16511 oappend_maybe_intel (scratchbuf
);
16512 scratchbuf
[0] = '\0';
16517 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16518 int sizeflag ATTRIBUTE_UNUSED
)
16520 unsigned int cmp_type
;
16525 FETCH_DATA (the_info
, codep
+ 1);
16526 cmp_type
= *codep
++ & 0xff;
16527 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16528 If it's the case, print suffix, otherwise - print the immediate. */
16529 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16534 char *p
= mnemonicendp
- 2;
16536 /* vpcmp* can have both one- and two-lettered suffix. */
16550 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16551 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16555 /* We have a reserved extension byte. Output it directly. */
16556 scratchbuf
[0] = '$';
16557 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16558 oappend_maybe_intel (scratchbuf
);
16559 scratchbuf
[0] = '\0';
16563 static const struct op pclmul_op
[] =
16565 { STRING_COMMA_LEN ("lql") },
16566 { STRING_COMMA_LEN ("hql") },
16567 { STRING_COMMA_LEN ("lqh") },
16568 { STRING_COMMA_LEN ("hqh") }
16572 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16573 int sizeflag ATTRIBUTE_UNUSED
)
16575 unsigned int pclmul_type
;
16577 FETCH_DATA (the_info
, codep
+ 1);
16578 pclmul_type
= *codep
++ & 0xff;
16579 switch (pclmul_type
)
16590 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16593 char *p
= mnemonicendp
- 3;
16598 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16599 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16603 /* We have a reserved extension byte. Output it directly. */
16604 scratchbuf
[0] = '$';
16605 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16606 oappend_maybe_intel (scratchbuf
);
16607 scratchbuf
[0] = '\0';
16612 MOVBE_Fixup (int bytemode
, int sizeflag
)
16614 /* Add proper suffix to "movbe". */
16615 char *p
= mnemonicendp
;
16624 if (sizeflag
& SUFFIX_ALWAYS
)
16630 if (sizeflag
& DFLAG
)
16634 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16639 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16646 OP_M (bytemode
, sizeflag
);
16650 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16653 const char **names
;
16655 /* Skip mod/rm byte. */
16669 oappend (names
[reg
]);
16673 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16675 const char **names
;
16682 oappend (names
[vex
.register_specifier
]);
16686 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16689 || bytemode
!= mask_mode
)
16693 if ((rex
& REX_R
) != 0 || !vex
.r
)
16699 oappend (names_mask
[modrm
.reg
]);
16703 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16706 || (bytemode
!= evex_rounding_mode
16707 && bytemode
!= evex_sae_mode
))
16709 if (modrm
.mod
== 3 && vex
.b
)
16712 case evex_rounding_mode
:
16713 oappend (names_rounding
[vex
.ll
]);
16715 case evex_sae_mode
: