1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
134 OPCODES_SIGJMP_BUF bailout
;
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 /* Possible values for prefix requirement. */
225 #define PREFIX_MANDATORY_REPZ PREFIX_REPZ
226 #define PREFIX_MANDATORY_REPNZ PREFIX_REPNZ
227 #define PREFIX_MANDATORY_DATA PREFIX_DATA
228 #define PREFIX_MANDATORY_ADDR PREFIX_ADDR
229 #define PREFIX_MANDATORY_LOCK PREFIX_LOCK
230 #define PREFIX_UD_SHIFT 16
231 #define PREFIX_UD_REPZ (PREFIX_MANDATORY_REPZ << PREFIX_UD_SHIFT)
232 #define PREFIX_UD_REPNZ (PREFIX_MANDATORY_REPNZ << PREFIX_UD_SHIFT)
233 #define PREFIX_UD_DATA (PREFIX_MANDATORY_DATA << PREFIX_UD_SHIFT)
234 #define PREFIX_UD_ADDR (PREFIX_MANDATORY_ADDR << PREFIX_UD_SHIFT)
235 #define PREFIX_UD_LOCK (PREFIX_MANDATORY_LOCK << PREFIX_UD_SHIFT)
237 #define PREFIX_MANDATORY (PREFIX_MANDATORY_REPZ \
238 | PREFIX_MANDATORY_REPNZ \
239 | PREFIX_MANDATORY_DATA)
241 #define XX { NULL, 0 }
242 #define Bad_Opcode NULL, { { NULL, 0 } }, PREFIX_MANDATORY
244 #define Eb { OP_E, b_mode }
245 #define Ebnd { OP_E, bnd_mode }
246 #define EbS { OP_E, b_swap_mode }
247 #define Ev { OP_E, v_mode }
248 #define Ev_bnd { OP_E, v_bnd_mode }
249 #define EvS { OP_E, v_swap_mode }
250 #define Ed { OP_E, d_mode }
251 #define Edq { OP_E, dq_mode }
252 #define Edqw { OP_E, dqw_mode }
253 #define EdqwS { OP_E, dqw_swap_mode }
254 #define Edqb { OP_E, dqb_mode }
255 #define Edb { OP_E, db_mode }
256 #define Edw { OP_E, dw_mode }
257 #define Edqd { OP_E, dqd_mode }
258 #define Eq { OP_E, q_mode }
259 #define indirEv { OP_indirE, stack_v_mode }
260 #define indirEp { OP_indirE, f_mode }
261 #define stackEv { OP_E, stack_v_mode }
262 #define Em { OP_E, m_mode }
263 #define Ew { OP_E, w_mode }
264 #define M { OP_M, 0 } /* lea, lgdt, etc. */
265 #define Ma { OP_M, a_mode }
266 #define Mb { OP_M, b_mode }
267 #define Md { OP_M, d_mode }
268 #define Mo { OP_M, o_mode }
269 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
270 #define Mq { OP_M, q_mode }
271 #define Mx { OP_M, x_mode }
272 #define Mxmm { OP_M, xmm_mode }
273 #define Gb { OP_G, b_mode }
274 #define Gbnd { OP_G, bnd_mode }
275 #define Gv { OP_G, v_mode }
276 #define Gd { OP_G, d_mode }
277 #define Gdq { OP_G, dq_mode }
278 #define Gm { OP_G, m_mode }
279 #define Gw { OP_G, w_mode }
280 #define Rd { OP_R, d_mode }
281 #define Rdq { OP_R, dq_mode }
282 #define Rm { OP_R, m_mode }
283 #define Ib { OP_I, b_mode }
284 #define sIb { OP_sI, b_mode } /* sign extened byte */
285 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
286 #define Iv { OP_I, v_mode }
287 #define sIv { OP_sI, v_mode }
288 #define Iq { OP_I, q_mode }
289 #define Iv64 { OP_I64, v_mode }
290 #define Iw { OP_I, w_mode }
291 #define I1 { OP_I, const_1_mode }
292 #define Jb { OP_J, b_mode }
293 #define Jv { OP_J, v_mode }
294 #define Cm { OP_C, m_mode }
295 #define Dm { OP_D, m_mode }
296 #define Td { OP_T, d_mode }
297 #define Skip_MODRM { OP_Skip_MODRM, 0 }
299 #define RMeAX { OP_REG, eAX_reg }
300 #define RMeBX { OP_REG, eBX_reg }
301 #define RMeCX { OP_REG, eCX_reg }
302 #define RMeDX { OP_REG, eDX_reg }
303 #define RMeSP { OP_REG, eSP_reg }
304 #define RMeBP { OP_REG, eBP_reg }
305 #define RMeSI { OP_REG, eSI_reg }
306 #define RMeDI { OP_REG, eDI_reg }
307 #define RMrAX { OP_REG, rAX_reg }
308 #define RMrBX { OP_REG, rBX_reg }
309 #define RMrCX { OP_REG, rCX_reg }
310 #define RMrDX { OP_REG, rDX_reg }
311 #define RMrSP { OP_REG, rSP_reg }
312 #define RMrBP { OP_REG, rBP_reg }
313 #define RMrSI { OP_REG, rSI_reg }
314 #define RMrDI { OP_REG, rDI_reg }
315 #define RMAL { OP_REG, al_reg }
316 #define RMCL { OP_REG, cl_reg }
317 #define RMDL { OP_REG, dl_reg }
318 #define RMBL { OP_REG, bl_reg }
319 #define RMAH { OP_REG, ah_reg }
320 #define RMCH { OP_REG, ch_reg }
321 #define RMDH { OP_REG, dh_reg }
322 #define RMBH { OP_REG, bh_reg }
323 #define RMAX { OP_REG, ax_reg }
324 #define RMDX { OP_REG, dx_reg }
326 #define eAX { OP_IMREG, eAX_reg }
327 #define eBX { OP_IMREG, eBX_reg }
328 #define eCX { OP_IMREG, eCX_reg }
329 #define eDX { OP_IMREG, eDX_reg }
330 #define eSP { OP_IMREG, eSP_reg }
331 #define eBP { OP_IMREG, eBP_reg }
332 #define eSI { OP_IMREG, eSI_reg }
333 #define eDI { OP_IMREG, eDI_reg }
334 #define AL { OP_IMREG, al_reg }
335 #define CL { OP_IMREG, cl_reg }
336 #define DL { OP_IMREG, dl_reg }
337 #define BL { OP_IMREG, bl_reg }
338 #define AH { OP_IMREG, ah_reg }
339 #define CH { OP_IMREG, ch_reg }
340 #define DH { OP_IMREG, dh_reg }
341 #define BH { OP_IMREG, bh_reg }
342 #define AX { OP_IMREG, ax_reg }
343 #define DX { OP_IMREG, dx_reg }
344 #define zAX { OP_IMREG, z_mode_ax_reg }
345 #define indirDX { OP_IMREG, indir_dx_reg }
347 #define Sw { OP_SEG, w_mode }
348 #define Sv { OP_SEG, v_mode }
349 #define Ap { OP_DIR, 0 }
350 #define Ob { OP_OFF64, b_mode }
351 #define Ov { OP_OFF64, v_mode }
352 #define Xb { OP_DSreg, eSI_reg }
353 #define Xv { OP_DSreg, eSI_reg }
354 #define Xz { OP_DSreg, eSI_reg }
355 #define Yb { OP_ESreg, eDI_reg }
356 #define Yv { OP_ESreg, eDI_reg }
357 #define DSBX { OP_DSreg, eBX_reg }
359 #define es { OP_REG, es_reg }
360 #define ss { OP_REG, ss_reg }
361 #define cs { OP_REG, cs_reg }
362 #define ds { OP_REG, ds_reg }
363 #define fs { OP_REG, fs_reg }
364 #define gs { OP_REG, gs_reg }
366 #define MX { OP_MMX, 0 }
367 #define XM { OP_XMM, 0 }
368 #define XMScalar { OP_XMM, scalar_mode }
369 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
370 #define XMM { OP_XMM, xmm_mode }
371 #define XMxmmq { OP_XMM, xmmq_mode }
372 #define EM { OP_EM, v_mode }
373 #define EMS { OP_EM, v_swap_mode }
374 #define EMd { OP_EM, d_mode }
375 #define EMx { OP_EM, x_mode }
376 #define EXw { OP_EX, w_mode }
377 #define EXd { OP_EX, d_mode }
378 #define EXdScalar { OP_EX, d_scalar_mode }
379 #define EXdS { OP_EX, d_swap_mode }
380 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
381 #define EXq { OP_EX, q_mode }
382 #define EXqScalar { OP_EX, q_scalar_mode }
383 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
384 #define EXqS { OP_EX, q_swap_mode }
385 #define EXx { OP_EX, x_mode }
386 #define EXxS { OP_EX, x_swap_mode }
387 #define EXxmm { OP_EX, xmm_mode }
388 #define EXymm { OP_EX, ymm_mode }
389 #define EXxmmq { OP_EX, xmmq_mode }
390 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
391 #define EXxmm_mb { OP_EX, xmm_mb_mode }
392 #define EXxmm_mw { OP_EX, xmm_mw_mode }
393 #define EXxmm_md { OP_EX, xmm_md_mode }
394 #define EXxmm_mq { OP_EX, xmm_mq_mode }
395 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
396 #define EXxmmdw { OP_EX, xmmdw_mode }
397 #define EXxmmqd { OP_EX, xmmqd_mode }
398 #define EXymmq { OP_EX, ymmq_mode }
399 #define EXVexWdq { OP_EX, vex_w_dq_mode }
400 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
401 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
402 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
403 #define MS { OP_MS, v_mode }
404 #define XS { OP_XS, v_mode }
405 #define EMCq { OP_EMC, q_mode }
406 #define MXC { OP_MXC, 0 }
407 #define OPSUF { OP_3DNowSuffix, 0 }
408 #define CMP { CMP_Fixup, 0 }
409 #define XMM0 { XMM_Fixup, 0 }
410 #define FXSAVE { FXSAVE_Fixup, 0 }
411 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
412 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
414 #define Vex { OP_VEX, vex_mode }
415 #define VexScalar { OP_VEX, vex_scalar_mode }
416 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
417 #define Vex128 { OP_VEX, vex128_mode }
418 #define Vex256 { OP_VEX, vex256_mode }
419 #define VexGdq { OP_VEX, dq_mode }
420 #define VexI4 { VEXI4_Fixup, 0}
421 #define EXdVex { OP_EX_Vex, d_mode }
422 #define EXdVexS { OP_EX_Vex, d_swap_mode }
423 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
424 #define EXqVex { OP_EX_Vex, q_mode }
425 #define EXqVexS { OP_EX_Vex, q_swap_mode }
426 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
427 #define EXVexW { OP_EX_VexW, x_mode }
428 #define EXdVexW { OP_EX_VexW, d_mode }
429 #define EXqVexW { OP_EX_VexW, q_mode }
430 #define EXVexImmW { OP_EX_VexImmW, x_mode }
431 #define XMVex { OP_XMM_Vex, 0 }
432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
433 #define XMVexW { OP_XMM_VexW, 0 }
434 #define XMVexI4 { OP_REG_VexI4, x_mode }
435 #define PCLMUL { PCLMUL_Fixup, 0 }
436 #define VZERO { VZERO_Fixup, 0 }
437 #define VCMP { VCMP_Fixup, 0 }
438 #define VPCMP { VPCMP_Fixup, 0 }
440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
441 #define EXxEVexS { OP_Rounding, evex_sae_mode }
443 #define XMask { OP_Mask, mask_mode }
444 #define MaskG { OP_G, mask_mode }
445 #define MaskE { OP_E, mask_mode }
446 #define MaskBDE { OP_E, mask_bd_mode }
447 #define MaskR { OP_R, mask_mode }
448 #define MaskVex { OP_VEX, mask_mode }
450 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
451 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
452 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
453 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
455 /* Used handle "rep" prefix for string instructions. */
456 #define Xbr { REP_Fixup, eSI_reg }
457 #define Xvr { REP_Fixup, eSI_reg }
458 #define Ybr { REP_Fixup, eDI_reg }
459 #define Yvr { REP_Fixup, eDI_reg }
460 #define Yzr { REP_Fixup, eDI_reg }
461 #define indirDXr { REP_Fixup, indir_dx_reg }
462 #define ALr { REP_Fixup, al_reg }
463 #define eAXr { REP_Fixup, eAX_reg }
465 /* Used handle HLE prefix for lockable instructions. */
466 #define Ebh1 { HLE_Fixup1, b_mode }
467 #define Evh1 { HLE_Fixup1, v_mode }
468 #define Ebh2 { HLE_Fixup2, b_mode }
469 #define Evh2 { HLE_Fixup2, v_mode }
470 #define Ebh3 { HLE_Fixup3, b_mode }
471 #define Evh3 { HLE_Fixup3, v_mode }
473 #define BND { BND_Fixup, 0 }
475 #define cond_jump_flag { NULL, cond_jump_mode }
476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
478 /* bits in sizeflag */
479 #define SUFFIX_ALWAYS 4
487 /* byte operand with operand swapped */
489 /* byte operand, sign extend like 'T' suffix */
491 /* operand size depends on prefixes */
493 /* operand size depends on prefixes with operand swapped */
497 /* double word operand */
499 /* double word operand with operand swapped */
501 /* quad word operand */
503 /* quad word operand with operand swapped */
505 /* ten-byte operand */
507 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
508 broadcast enabled. */
510 /* Similar to x_mode, but with different EVEX mem shifts. */
512 /* Similar to x_mode, but with disabled broadcast. */
514 /* Similar to x_mode, but with operands swapped and disabled broadcast
517 /* 16-byte XMM operand */
519 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
520 memory operand (depending on vector length). Broadcast isn't
523 /* Same as xmmq_mode, but broadcast is allowed. */
524 evex_half_bcst_xmmq_mode
,
525 /* XMM register or byte memory operand */
527 /* XMM register or word memory operand */
529 /* XMM register or double word memory operand */
531 /* XMM register or quad word memory operand */
533 /* XMM register or double/quad word memory operand, depending on
536 /* 16-byte XMM, word, double word or quad word operand. */
538 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
540 /* 32-byte YMM operand */
542 /* quad word, ymmword or zmmword memory operand. */
544 /* 32-byte YMM or 16-byte word operand */
546 /* d_mode in 32bit, q_mode in 64bit mode. */
548 /* pair of v_mode operands */
553 /* operand size depends on REX prefixes. */
555 /* registers like dq_mode, memory like w_mode. */
559 /* 4- or 6-byte pointer operand */
562 /* v_mode for stack-related opcodes. */
564 /* non-quad operand size depends on prefixes */
566 /* 16-byte operand */
568 /* registers like dq_mode, memory like b_mode. */
570 /* registers like d_mode, memory like b_mode. */
572 /* registers like d_mode, memory like w_mode. */
574 /* registers like dq_mode, memory like d_mode. */
576 /* normal vex mode */
578 /* 128bit vex mode */
580 /* 256bit vex mode */
582 /* operand size depends on the VEX.W bit. */
585 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
586 vex_vsib_d_w_dq_mode
,
587 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
589 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
590 vex_vsib_q_w_dq_mode
,
591 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
594 /* scalar, ignore vector length. */
596 /* like d_mode, ignore vector length. */
598 /* like d_swap_mode, ignore vector length. */
600 /* like q_mode, ignore vector length. */
602 /* like q_swap_mode, ignore vector length. */
604 /* like vex_mode, ignore vector length. */
606 /* like vex_w_dq_mode, ignore vector length. */
607 vex_scalar_w_dq_mode
,
609 /* Static rounding. */
611 /* Supress all exceptions. */
614 /* Mask register operand. */
616 /* Mask register operand. */
683 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
685 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
686 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
687 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
688 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
689 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
690 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
691 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
692 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
693 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
694 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
695 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
696 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
697 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
698 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
699 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
815 MOD_VEX_0F12_PREFIX_0
,
817 MOD_VEX_0F16_PREFIX_0
,
833 MOD_VEX_0FD7_PREFIX_2
,
834 MOD_VEX_0FE7_PREFIX_2
,
835 MOD_VEX_0FF0_PREFIX_3
,
836 MOD_VEX_0F381A_PREFIX_2
,
837 MOD_VEX_0F382A_PREFIX_2
,
838 MOD_VEX_0F382C_PREFIX_2
,
839 MOD_VEX_0F382D_PREFIX_2
,
840 MOD_VEX_0F382E_PREFIX_2
,
841 MOD_VEX_0F382F_PREFIX_2
,
842 MOD_VEX_0F385A_PREFIX_2
,
843 MOD_VEX_0F388C_PREFIX_2
,
844 MOD_VEX_0F388E_PREFIX_2
,
846 MOD_EVEX_0F10_PREFIX_1
,
847 MOD_EVEX_0F10_PREFIX_3
,
848 MOD_EVEX_0F11_PREFIX_1
,
849 MOD_EVEX_0F11_PREFIX_3
,
850 MOD_EVEX_0F12_PREFIX_0
,
851 MOD_EVEX_0F16_PREFIX_0
,
852 MOD_EVEX_0F38C6_REG_1
,
853 MOD_EVEX_0F38C6_REG_2
,
854 MOD_EVEX_0F38C6_REG_5
,
855 MOD_EVEX_0F38C6_REG_6
,
856 MOD_EVEX_0F38C7_REG_1
,
857 MOD_EVEX_0F38C7_REG_2
,
858 MOD_EVEX_0F38C7_REG_5
,
859 MOD_EVEX_0F38C7_REG_6
923 PREFIX_RM_0_0FAE_REG_7
,
1053 PREFIX_VEX_0F71_REG_2
,
1054 PREFIX_VEX_0F71_REG_4
,
1055 PREFIX_VEX_0F71_REG_6
,
1056 PREFIX_VEX_0F72_REG_2
,
1057 PREFIX_VEX_0F72_REG_4
,
1058 PREFIX_VEX_0F72_REG_6
,
1059 PREFIX_VEX_0F73_REG_2
,
1060 PREFIX_VEX_0F73_REG_3
,
1061 PREFIX_VEX_0F73_REG_6
,
1062 PREFIX_VEX_0F73_REG_7
,
1234 PREFIX_VEX_0F38F3_REG_1
,
1235 PREFIX_VEX_0F38F3_REG_2
,
1236 PREFIX_VEX_0F38F3_REG_3
,
1353 PREFIX_EVEX_0F71_REG_2
,
1354 PREFIX_EVEX_0F71_REG_4
,
1355 PREFIX_EVEX_0F71_REG_6
,
1356 PREFIX_EVEX_0F72_REG_0
,
1357 PREFIX_EVEX_0F72_REG_1
,
1358 PREFIX_EVEX_0F72_REG_2
,
1359 PREFIX_EVEX_0F72_REG_4
,
1360 PREFIX_EVEX_0F72_REG_6
,
1361 PREFIX_EVEX_0F73_REG_2
,
1362 PREFIX_EVEX_0F73_REG_3
,
1363 PREFIX_EVEX_0F73_REG_6
,
1364 PREFIX_EVEX_0F73_REG_7
,
1547 PREFIX_EVEX_0F38C6_REG_1
,
1548 PREFIX_EVEX_0F38C6_REG_2
,
1549 PREFIX_EVEX_0F38C6_REG_5
,
1550 PREFIX_EVEX_0F38C6_REG_6
,
1551 PREFIX_EVEX_0F38C7_REG_1
,
1552 PREFIX_EVEX_0F38C7_REG_2
,
1553 PREFIX_EVEX_0F38C7_REG_5
,
1554 PREFIX_EVEX_0F38C7_REG_6
,
1641 THREE_BYTE_0F38
= 0,
1669 VEX_LEN_0F10_P_1
= 0,
1673 VEX_LEN_0F12_P_0_M_0
,
1674 VEX_LEN_0F12_P_0_M_1
,
1677 VEX_LEN_0F16_P_0_M_0
,
1678 VEX_LEN_0F16_P_0_M_1
,
1742 VEX_LEN_0FAE_R_2_M_0
,
1743 VEX_LEN_0FAE_R_3_M_0
,
1752 VEX_LEN_0F381A_P_2_M_0
,
1755 VEX_LEN_0F385A_P_2_M_0
,
1762 VEX_LEN_0F38F3_R_1_P_0
,
1763 VEX_LEN_0F38F3_R_2_P_0
,
1764 VEX_LEN_0F38F3_R_3_P_0
,
1810 VEX_LEN_0FXOP_08_CC
,
1811 VEX_LEN_0FXOP_08_CD
,
1812 VEX_LEN_0FXOP_08_CE
,
1813 VEX_LEN_0FXOP_08_CF
,
1814 VEX_LEN_0FXOP_08_EC
,
1815 VEX_LEN_0FXOP_08_ED
,
1816 VEX_LEN_0FXOP_08_EE
,
1817 VEX_LEN_0FXOP_08_EF
,
1818 VEX_LEN_0FXOP_09_80
,
1852 VEX_W_0F41_P_0_LEN_1
,
1853 VEX_W_0F41_P_2_LEN_1
,
1854 VEX_W_0F42_P_0_LEN_1
,
1855 VEX_W_0F42_P_2_LEN_1
,
1856 VEX_W_0F44_P_0_LEN_0
,
1857 VEX_W_0F44_P_2_LEN_0
,
1858 VEX_W_0F45_P_0_LEN_1
,
1859 VEX_W_0F45_P_2_LEN_1
,
1860 VEX_W_0F46_P_0_LEN_1
,
1861 VEX_W_0F46_P_2_LEN_1
,
1862 VEX_W_0F47_P_0_LEN_1
,
1863 VEX_W_0F47_P_2_LEN_1
,
1864 VEX_W_0F4A_P_0_LEN_1
,
1865 VEX_W_0F4A_P_2_LEN_1
,
1866 VEX_W_0F4B_P_0_LEN_1
,
1867 VEX_W_0F4B_P_2_LEN_1
,
1947 VEX_W_0F90_P_0_LEN_0
,
1948 VEX_W_0F90_P_2_LEN_0
,
1949 VEX_W_0F91_P_0_LEN_0
,
1950 VEX_W_0F91_P_2_LEN_0
,
1951 VEX_W_0F92_P_0_LEN_0
,
1952 VEX_W_0F92_P_2_LEN_0
,
1953 VEX_W_0F92_P_3_LEN_0
,
1954 VEX_W_0F93_P_0_LEN_0
,
1955 VEX_W_0F93_P_2_LEN_0
,
1956 VEX_W_0F93_P_3_LEN_0
,
1957 VEX_W_0F98_P_0_LEN_0
,
1958 VEX_W_0F98_P_2_LEN_0
,
1959 VEX_W_0F99_P_0_LEN_0
,
1960 VEX_W_0F99_P_2_LEN_0
,
2039 VEX_W_0F381A_P_2_M_0
,
2051 VEX_W_0F382A_P_2_M_0
,
2053 VEX_W_0F382C_P_2_M_0
,
2054 VEX_W_0F382D_P_2_M_0
,
2055 VEX_W_0F382E_P_2_M_0
,
2056 VEX_W_0F382F_P_2_M_0
,
2078 VEX_W_0F385A_P_2_M_0
,
2106 VEX_W_0F3A30_P_2_LEN_0
,
2107 VEX_W_0F3A31_P_2_LEN_0
,
2108 VEX_W_0F3A32_P_2_LEN_0
,
2109 VEX_W_0F3A33_P_2_LEN_0
,
2129 EVEX_W_0F10_P_1_M_0
,
2130 EVEX_W_0F10_P_1_M_1
,
2132 EVEX_W_0F10_P_3_M_0
,
2133 EVEX_W_0F10_P_3_M_1
,
2135 EVEX_W_0F11_P_1_M_0
,
2136 EVEX_W_0F11_P_1_M_1
,
2138 EVEX_W_0F11_P_3_M_0
,
2139 EVEX_W_0F11_P_3_M_1
,
2140 EVEX_W_0F12_P_0_M_0
,
2141 EVEX_W_0F12_P_0_M_1
,
2151 EVEX_W_0F16_P_0_M_0
,
2152 EVEX_W_0F16_P_0_M_1
,
2223 EVEX_W_0F72_R_2_P_2
,
2224 EVEX_W_0F72_R_6_P_2
,
2225 EVEX_W_0F73_R_2_P_2
,
2226 EVEX_W_0F73_R_6_P_2
,
2326 EVEX_W_0F38C7_R_1_P_2
,
2327 EVEX_W_0F38C7_R_2_P_2
,
2328 EVEX_W_0F38C7_R_5_P_2
,
2329 EVEX_W_0F38C7_R_6_P_2
,
2364 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2373 unsigned int prefix_requirement
;
2376 /* Upper case letters in the instruction names here are macros.
2377 'A' => print 'b' if no register operands or suffix_always is true
2378 'B' => print 'b' if suffix_always is true
2379 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2381 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2382 suffix_always is true
2383 'E' => print 'e' if 32-bit form of jcxz
2384 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2385 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2386 'H' => print ",pt" or ",pn" branch hint
2387 'I' => honor following macro letter even in Intel mode (implemented only
2388 for some of the macro letters)
2390 'K' => print 'd' or 'q' if rex prefix is present.
2391 'L' => print 'l' if suffix_always is true
2392 'M' => print 'r' if intel_mnemonic is false.
2393 'N' => print 'n' if instruction has no wait "prefix"
2394 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2395 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2396 or suffix_always is true. print 'q' if rex prefix is present.
2397 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2399 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2400 'S' => print 'w', 'l' or 'q' if suffix_always is true
2401 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2402 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2403 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2404 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2405 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2406 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2407 suffix_always is true.
2408 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2409 '!' => change condition from true to false or from false to true.
2410 '%' => add 1 upper case letter to the macro.
2412 2 upper case letter macros:
2413 "XY" => print 'x' or 'y' if no register operands or suffix_always
2415 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2416 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2417 or suffix_always is true
2418 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2419 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2420 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2421 "LW" => print 'd', 'q' depending on the VEX.W bit
2422 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2423 an operand size prefix, or suffix_always is true. print
2424 'q' if rex prefix is present.
2426 Many of the above letters print nothing in Intel mode. See "putop"
2429 Braces '{' and '}', and vertical bars '|', indicate alternative
2430 mnemonic strings for AT&T and Intel. */
2432 static const struct dis386 dis386
[] = {
2434 { "addB", { Ebh1
, Gb
}, 0 },
2435 { "addS", { Evh1
, Gv
}, 0 },
2436 { "addB", { Gb
, EbS
}, 0 },
2437 { "addS", { Gv
, EvS
}, 0 },
2438 { "addB", { AL
, Ib
}, 0 },
2439 { "addS", { eAX
, Iv
}, 0 },
2440 { X86_64_TABLE (X86_64_06
) },
2441 { X86_64_TABLE (X86_64_07
) },
2443 { "orB", { Ebh1
, Gb
}, 0 },
2444 { "orS", { Evh1
, Gv
}, 0 },
2445 { "orB", { Gb
, EbS
}, 0 },
2446 { "orS", { Gv
, EvS
}, 0 },
2447 { "orB", { AL
, Ib
}, 0 },
2448 { "orS", { eAX
, Iv
}, 0 },
2449 { X86_64_TABLE (X86_64_0D
) },
2450 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2452 { "adcB", { Ebh1
, Gb
}, 0 },
2453 { "adcS", { Evh1
, Gv
}, 0 },
2454 { "adcB", { Gb
, EbS
}, 0 },
2455 { "adcS", { Gv
, EvS
}, 0 },
2456 { "adcB", { AL
, Ib
}, 0 },
2457 { "adcS", { eAX
, Iv
}, 0 },
2458 { X86_64_TABLE (X86_64_16
) },
2459 { X86_64_TABLE (X86_64_17
) },
2461 { "sbbB", { Ebh1
, Gb
}, 0 },
2462 { "sbbS", { Evh1
, Gv
}, 0 },
2463 { "sbbB", { Gb
, EbS
}, 0 },
2464 { "sbbS", { Gv
, EvS
}, 0 },
2465 { "sbbB", { AL
, Ib
}, 0 },
2466 { "sbbS", { eAX
, Iv
}, 0 },
2467 { X86_64_TABLE (X86_64_1E
) },
2468 { X86_64_TABLE (X86_64_1F
) },
2470 { "andB", { Ebh1
, Gb
}, 0 },
2471 { "andS", { Evh1
, Gv
}, 0 },
2472 { "andB", { Gb
, EbS
}, 0 },
2473 { "andS", { Gv
, EvS
}, 0 },
2474 { "andB", { AL
, Ib
}, 0 },
2475 { "andS", { eAX
, Iv
}, 0 },
2476 { Bad_Opcode
}, /* SEG ES prefix */
2477 { X86_64_TABLE (X86_64_27
) },
2479 { "subB", { Ebh1
, Gb
}, 0 },
2480 { "subS", { Evh1
, Gv
}, 0 },
2481 { "subB", { Gb
, EbS
}, 0 },
2482 { "subS", { Gv
, EvS
}, 0 },
2483 { "subB", { AL
, Ib
}, 0 },
2484 { "subS", { eAX
, Iv
}, 0 },
2485 { Bad_Opcode
}, /* SEG CS prefix */
2486 { X86_64_TABLE (X86_64_2F
) },
2488 { "xorB", { Ebh1
, Gb
}, 0 },
2489 { "xorS", { Evh1
, Gv
}, 0 },
2490 { "xorB", { Gb
, EbS
}, 0 },
2491 { "xorS", { Gv
, EvS
}, 0 },
2492 { "xorB", { AL
, Ib
}, 0 },
2493 { "xorS", { eAX
, Iv
}, 0 },
2494 { Bad_Opcode
}, /* SEG SS prefix */
2495 { X86_64_TABLE (X86_64_37
) },
2497 { "cmpB", { Eb
, Gb
}, 0 },
2498 { "cmpS", { Ev
, Gv
}, 0 },
2499 { "cmpB", { Gb
, EbS
}, 0 },
2500 { "cmpS", { Gv
, EvS
}, 0 },
2501 { "cmpB", { AL
, Ib
}, 0 },
2502 { "cmpS", { eAX
, Iv
}, 0 },
2503 { Bad_Opcode
}, /* SEG DS prefix */
2504 { X86_64_TABLE (X86_64_3F
) },
2506 { "inc{S|}", { RMeAX
}, 0 },
2507 { "inc{S|}", { RMeCX
}, 0 },
2508 { "inc{S|}", { RMeDX
}, 0 },
2509 { "inc{S|}", { RMeBX
}, 0 },
2510 { "inc{S|}", { RMeSP
}, 0 },
2511 { "inc{S|}", { RMeBP
}, 0 },
2512 { "inc{S|}", { RMeSI
}, 0 },
2513 { "inc{S|}", { RMeDI
}, 0 },
2515 { "dec{S|}", { RMeAX
}, 0 },
2516 { "dec{S|}", { RMeCX
}, 0 },
2517 { "dec{S|}", { RMeDX
}, 0 },
2518 { "dec{S|}", { RMeBX
}, 0 },
2519 { "dec{S|}", { RMeSP
}, 0 },
2520 { "dec{S|}", { RMeBP
}, 0 },
2521 { "dec{S|}", { RMeSI
}, 0 },
2522 { "dec{S|}", { RMeDI
}, 0 },
2524 { "pushV", { RMrAX
}, 0 },
2525 { "pushV", { RMrCX
}, 0 },
2526 { "pushV", { RMrDX
}, 0 },
2527 { "pushV", { RMrBX
}, 0 },
2528 { "pushV", { RMrSP
}, 0 },
2529 { "pushV", { RMrBP
}, 0 },
2530 { "pushV", { RMrSI
}, 0 },
2531 { "pushV", { RMrDI
}, 0 },
2533 { "popV", { RMrAX
}, 0 },
2534 { "popV", { RMrCX
}, 0 },
2535 { "popV", { RMrDX
}, 0 },
2536 { "popV", { RMrBX
}, 0 },
2537 { "popV", { RMrSP
}, 0 },
2538 { "popV", { RMrBP
}, 0 },
2539 { "popV", { RMrSI
}, 0 },
2540 { "popV", { RMrDI
}, 0 },
2542 { X86_64_TABLE (X86_64_60
) },
2543 { X86_64_TABLE (X86_64_61
) },
2544 { X86_64_TABLE (X86_64_62
) },
2545 { X86_64_TABLE (X86_64_63
) },
2546 { Bad_Opcode
}, /* seg fs */
2547 { Bad_Opcode
}, /* seg gs */
2548 { Bad_Opcode
}, /* op size prefix */
2549 { Bad_Opcode
}, /* adr size prefix */
2551 { "pushT", { sIv
}, 0 },
2552 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2553 { "pushT", { sIbT
}, 0 },
2554 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2555 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2556 { X86_64_TABLE (X86_64_6D
) },
2557 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2558 { X86_64_TABLE (X86_64_6F
) },
2560 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2561 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2562 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2563 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2564 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2565 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2566 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2567 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2569 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2570 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2571 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2572 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2573 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2574 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2575 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2576 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2578 { REG_TABLE (REG_80
) },
2579 { REG_TABLE (REG_81
) },
2581 { REG_TABLE (REG_82
) },
2582 { "testB", { Eb
, Gb
}, 0 },
2583 { "testS", { Ev
, Gv
}, 0 },
2584 { "xchgB", { Ebh2
, Gb
}, 0 },
2585 { "xchgS", { Evh2
, Gv
}, 0 },
2587 { "movB", { Ebh3
, Gb
}, 0 },
2588 { "movS", { Evh3
, Gv
}, 0 },
2589 { "movB", { Gb
, EbS
}, 0 },
2590 { "movS", { Gv
, EvS
}, 0 },
2591 { "movD", { Sv
, Sw
}, 0 },
2592 { MOD_TABLE (MOD_8D
) },
2593 { "movD", { Sw
, Sv
}, 0 },
2594 { REG_TABLE (REG_8F
) },
2596 { PREFIX_TABLE (PREFIX_90
) },
2597 { "xchgS", { RMeCX
, eAX
}, 0 },
2598 { "xchgS", { RMeDX
, eAX
}, 0 },
2599 { "xchgS", { RMeBX
, eAX
}, 0 },
2600 { "xchgS", { RMeSP
, eAX
}, 0 },
2601 { "xchgS", { RMeBP
, eAX
}, 0 },
2602 { "xchgS", { RMeSI
, eAX
}, 0 },
2603 { "xchgS", { RMeDI
, eAX
}, 0 },
2605 { "cW{t|}R", { XX
}, 0 },
2606 { "cR{t|}O", { XX
}, 0 },
2607 { X86_64_TABLE (X86_64_9A
) },
2608 { Bad_Opcode
}, /* fwait */
2609 { "pushfT", { XX
}, 0 },
2610 { "popfT", { XX
}, 0 },
2611 { "sahf", { XX
}, 0 },
2612 { "lahf", { XX
}, 0 },
2614 { "mov%LB", { AL
, Ob
}, 0 },
2615 { "mov%LS", { eAX
, Ov
}, 0 },
2616 { "mov%LB", { Ob
, AL
}, 0 },
2617 { "mov%LS", { Ov
, eAX
}, 0 },
2618 { "movs{b|}", { Ybr
, Xb
}, 0 },
2619 { "movs{R|}", { Yvr
, Xv
}, 0 },
2620 { "cmps{b|}", { Xb
, Yb
}, 0 },
2621 { "cmps{R|}", { Xv
, Yv
}, 0 },
2623 { "testB", { AL
, Ib
}, 0 },
2624 { "testS", { eAX
, Iv
}, 0 },
2625 { "stosB", { Ybr
, AL
}, 0 },
2626 { "stosS", { Yvr
, eAX
}, 0 },
2627 { "lodsB", { ALr
, Xb
}, 0 },
2628 { "lodsS", { eAXr
, Xv
}, 0 },
2629 { "scasB", { AL
, Yb
}, 0 },
2630 { "scasS", { eAX
, Yv
}, 0 },
2632 { "movB", { RMAL
, Ib
}, 0 },
2633 { "movB", { RMCL
, Ib
}, 0 },
2634 { "movB", { RMDL
, Ib
}, 0 },
2635 { "movB", { RMBL
, Ib
}, 0 },
2636 { "movB", { RMAH
, Ib
}, 0 },
2637 { "movB", { RMCH
, Ib
}, 0 },
2638 { "movB", { RMDH
, Ib
}, 0 },
2639 { "movB", { RMBH
, Ib
}, 0 },
2641 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2642 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2643 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2644 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2645 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2646 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2647 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2648 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2650 { REG_TABLE (REG_C0
) },
2651 { REG_TABLE (REG_C1
) },
2652 { "retT", { Iw
, BND
}, 0 },
2653 { "retT", { BND
}, 0 },
2654 { X86_64_TABLE (X86_64_C4
) },
2655 { X86_64_TABLE (X86_64_C5
) },
2656 { REG_TABLE (REG_C6
) },
2657 { REG_TABLE (REG_C7
) },
2659 { "enterT", { Iw
, Ib
}, 0 },
2660 { "leaveT", { XX
}, 0 },
2661 { "Jret{|f}P", { Iw
}, 0 },
2662 { "Jret{|f}P", { XX
}, 0 },
2663 { "int3", { XX
}, 0 },
2664 { "int", { Ib
}, 0 },
2665 { X86_64_TABLE (X86_64_CE
) },
2666 { "iret%LP", { XX
}, 0 },
2668 { REG_TABLE (REG_D0
) },
2669 { REG_TABLE (REG_D1
) },
2670 { REG_TABLE (REG_D2
) },
2671 { REG_TABLE (REG_D3
) },
2672 { X86_64_TABLE (X86_64_D4
) },
2673 { X86_64_TABLE (X86_64_D5
) },
2675 { "xlat", { DSBX
}, 0 },
2686 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2687 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2688 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2689 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2690 { "inB", { AL
, Ib
}, 0 },
2691 { "inG", { zAX
, Ib
}, 0 },
2692 { "outB", { Ib
, AL
}, 0 },
2693 { "outG", { Ib
, zAX
}, 0 },
2695 { "callT", { Jv
, BND
}, 0 },
2696 { "jmpT", { Jv
, BND
}, 0 },
2697 { X86_64_TABLE (X86_64_EA
) },
2698 { "jmp", { Jb
, BND
}, 0 },
2699 { "inB", { AL
, indirDX
}, 0 },
2700 { "inG", { zAX
, indirDX
}, 0 },
2701 { "outB", { indirDX
, AL
}, 0 },
2702 { "outG", { indirDX
, zAX
}, 0 },
2704 { Bad_Opcode
}, /* lock prefix */
2705 { "icebp", { XX
}, 0 },
2706 { Bad_Opcode
}, /* repne */
2707 { Bad_Opcode
}, /* repz */
2708 { "hlt", { XX
}, 0 },
2709 { "cmc", { XX
}, 0 },
2710 { REG_TABLE (REG_F6
) },
2711 { REG_TABLE (REG_F7
) },
2713 { "clc", { XX
}, 0 },
2714 { "stc", { XX
}, 0 },
2715 { "cli", { XX
}, 0 },
2716 { "sti", { XX
}, 0 },
2717 { "cld", { XX
}, 0 },
2718 { "std", { XX
}, 0 },
2719 { REG_TABLE (REG_FE
) },
2720 { REG_TABLE (REG_FF
) },
2723 static const struct dis386 dis386_twobyte
[] = {
2725 { REG_TABLE (REG_0F00
) },
2726 { REG_TABLE (REG_0F01
) },
2727 { "larS", { Gv
, Ew
}, 0 },
2728 { "lslS", { Gv
, Ew
}, 0 },
2730 { "syscall", { XX
}, 0 },
2731 { "clts", { XX
}, 0 },
2732 { "sysret%LP", { XX
}, 0 },
2734 { "invd", { XX
}, 0 },
2735 { "wbinvd", { XX
}, 0 },
2737 { "ud2", { XX
}, 0 },
2739 { REG_TABLE (REG_0F0D
) },
2740 { "femms", { XX
}, 0 },
2741 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2743 { PREFIX_TABLE (PREFIX_0F10
) },
2744 { PREFIX_TABLE (PREFIX_0F11
) },
2745 { PREFIX_TABLE (PREFIX_0F12
) },
2746 { MOD_TABLE (MOD_0F13
) },
2747 { "unpcklpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2748 { "unpckhpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2749 { PREFIX_TABLE (PREFIX_0F16
) },
2750 { MOD_TABLE (MOD_0F17
) },
2752 { REG_TABLE (REG_0F18
) },
2753 { "nopQ", { Ev
}, 0 },
2754 { PREFIX_TABLE (PREFIX_0F1A
) },
2755 { PREFIX_TABLE (PREFIX_0F1B
) },
2756 { "nopQ", { Ev
}, 0 },
2757 { "nopQ", { Ev
}, 0 },
2758 { "nopQ", { Ev
}, 0 },
2759 { "nopQ", { Ev
}, 0 },
2761 { "movZ", { Rm
, Cm
}, 0 },
2762 { "movZ", { Rm
, Dm
}, 0 },
2763 { "movZ", { Cm
, Rm
}, 0 },
2764 { "movZ", { Dm
, Rm
}, 0 },
2765 { MOD_TABLE (MOD_0F24
) },
2767 { MOD_TABLE (MOD_0F26
) },
2770 { "movapX", { XM
, EXx
}, PREFIX_MANDATORY
},
2771 { "movapX", { EXxS
, XM
}, PREFIX_MANDATORY
},
2772 { PREFIX_TABLE (PREFIX_0F2A
) },
2773 { PREFIX_TABLE (PREFIX_0F2B
) },
2774 { PREFIX_TABLE (PREFIX_0F2C
) },
2775 { PREFIX_TABLE (PREFIX_0F2D
) },
2776 { PREFIX_TABLE (PREFIX_0F2E
) },
2777 { PREFIX_TABLE (PREFIX_0F2F
) },
2779 { "wrmsr", { XX
}, 0 },
2780 { "rdtsc", { XX
}, 0 },
2781 { "rdmsr", { XX
}, 0 },
2782 { "rdpmc", { XX
}, 0 },
2783 { "sysenter", { XX
}, 0 },
2784 { "sysexit", { XX
}, 0 },
2786 { "getsec", { XX
}, 0 },
2788 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_MANDATORY
) },
2790 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_MANDATORY
) },
2797 { "cmovoS", { Gv
, Ev
}, 0 },
2798 { "cmovnoS", { Gv
, Ev
}, 0 },
2799 { "cmovbS", { Gv
, Ev
}, 0 },
2800 { "cmovaeS", { Gv
, Ev
}, 0 },
2801 { "cmoveS", { Gv
, Ev
}, 0 },
2802 { "cmovneS", { Gv
, Ev
}, 0 },
2803 { "cmovbeS", { Gv
, Ev
}, 0 },
2804 { "cmovaS", { Gv
, Ev
}, 0 },
2806 { "cmovsS", { Gv
, Ev
}, 0 },
2807 { "cmovnsS", { Gv
, Ev
}, 0 },
2808 { "cmovpS", { Gv
, Ev
}, 0 },
2809 { "cmovnpS", { Gv
, Ev
}, 0 },
2810 { "cmovlS", { Gv
, Ev
}, 0 },
2811 { "cmovgeS", { Gv
, Ev
}, 0 },
2812 { "cmovleS", { Gv
, Ev
}, 0 },
2813 { "cmovgS", { Gv
, Ev
}, 0 },
2815 { MOD_TABLE (MOD_0F51
) },
2816 { PREFIX_TABLE (PREFIX_0F51
) },
2817 { PREFIX_TABLE (PREFIX_0F52
) },
2818 { PREFIX_TABLE (PREFIX_0F53
) },
2819 { "andpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2820 { "andnpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2821 { "orpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2822 { "xorpX", { XM
, EXx
}, PREFIX_MANDATORY
},
2824 { PREFIX_TABLE (PREFIX_0F58
) },
2825 { PREFIX_TABLE (PREFIX_0F59
) },
2826 { PREFIX_TABLE (PREFIX_0F5A
) },
2827 { PREFIX_TABLE (PREFIX_0F5B
) },
2828 { PREFIX_TABLE (PREFIX_0F5C
) },
2829 { PREFIX_TABLE (PREFIX_0F5D
) },
2830 { PREFIX_TABLE (PREFIX_0F5E
) },
2831 { PREFIX_TABLE (PREFIX_0F5F
) },
2833 { PREFIX_TABLE (PREFIX_0F60
) },
2834 { PREFIX_TABLE (PREFIX_0F61
) },
2835 { PREFIX_TABLE (PREFIX_0F62
) },
2836 { "packsswb", { MX
, EM
}, PREFIX_MANDATORY
},
2837 { "pcmpgtb", { MX
, EM
}, PREFIX_MANDATORY
},
2838 { "pcmpgtw", { MX
, EM
}, PREFIX_MANDATORY
},
2839 { "pcmpgtd", { MX
, EM
}, PREFIX_MANDATORY
},
2840 { "packuswb", { MX
, EM
}, PREFIX_MANDATORY
},
2842 { "punpckhbw", { MX
, EM
}, PREFIX_MANDATORY
},
2843 { "punpckhwd", { MX
, EM
}, PREFIX_MANDATORY
},
2844 { "punpckhdq", { MX
, EM
}, PREFIX_MANDATORY
},
2845 { "packssdw", { MX
, EM
}, PREFIX_MANDATORY
},
2846 { PREFIX_TABLE (PREFIX_0F6C
) },
2847 { PREFIX_TABLE (PREFIX_0F6D
) },
2848 { "movK", { MX
, Edq
}, PREFIX_MANDATORY
},
2849 { PREFIX_TABLE (PREFIX_0F6F
) },
2851 { PREFIX_TABLE (PREFIX_0F70
) },
2852 { REG_TABLE (REG_0F71
) },
2853 { REG_TABLE (REG_0F72
) },
2854 { REG_TABLE (REG_0F73
) },
2855 { "pcmpeqb", { MX
, EM
}, PREFIX_MANDATORY
},
2856 { "pcmpeqw", { MX
, EM
}, PREFIX_MANDATORY
},
2857 { "pcmpeqd", { MX
, EM
}, PREFIX_MANDATORY
},
2858 { "emms", { XX
}, PREFIX_MANDATORY
},
2860 { PREFIX_TABLE (PREFIX_0F78
) },
2861 { PREFIX_TABLE (PREFIX_0F79
) },
2862 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2864 { PREFIX_TABLE (PREFIX_0F7C
) },
2865 { PREFIX_TABLE (PREFIX_0F7D
) },
2866 { PREFIX_TABLE (PREFIX_0F7E
) },
2867 { PREFIX_TABLE (PREFIX_0F7F
) },
2869 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2870 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2871 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2872 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2873 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2874 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2875 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2876 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2878 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2879 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2880 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2881 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2882 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2883 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2884 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2885 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2887 { "seto", { Eb
}, 0 },
2888 { "setno", { Eb
}, 0 },
2889 { "setb", { Eb
}, 0 },
2890 { "setae", { Eb
}, 0 },
2891 { "sete", { Eb
}, 0 },
2892 { "setne", { Eb
}, 0 },
2893 { "setbe", { Eb
}, 0 },
2894 { "seta", { Eb
}, 0 },
2896 { "sets", { Eb
}, 0 },
2897 { "setns", { Eb
}, 0 },
2898 { "setp", { Eb
}, 0 },
2899 { "setnp", { Eb
}, 0 },
2900 { "setl", { Eb
}, 0 },
2901 { "setge", { Eb
}, 0 },
2902 { "setle", { Eb
}, 0 },
2903 { "setg", { Eb
}, 0 },
2905 { "pushT", { fs
}, 0 },
2906 { "popT", { fs
}, 0 },
2907 { "cpuid", { XX
}, 0 },
2908 { "btS", { Ev
, Gv
}, 0 },
2909 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2910 { "shldS", { Ev
, Gv
, CL
}, 0 },
2911 { REG_TABLE (REG_0FA6
) },
2912 { REG_TABLE (REG_0FA7
) },
2914 { "pushT", { gs
}, 0 },
2915 { "popT", { gs
}, 0 },
2916 { "rsm", { XX
}, 0 },
2917 { "btsS", { Evh1
, Gv
}, 0 },
2918 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2919 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2920 { REG_TABLE (REG_0FAE
) },
2921 { "imulS", { Gv
, Ev
}, 0 },
2923 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2924 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2925 { MOD_TABLE (MOD_0FB2
) },
2926 { "btrS", { Evh1
, Gv
}, 0 },
2927 { MOD_TABLE (MOD_0FB4
) },
2928 { MOD_TABLE (MOD_0FB5
) },
2929 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2930 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2932 { PREFIX_TABLE (PREFIX_0FB8
) },
2933 { "ud1", { XX
}, 0 },
2934 { REG_TABLE (REG_0FBA
) },
2935 { "btcS", { Evh1
, Gv
}, 0 },
2936 { PREFIX_TABLE (PREFIX_0FBC
) },
2937 { PREFIX_TABLE (PREFIX_0FBD
) },
2938 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2939 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2941 { "xaddB", { Ebh1
, Gb
}, 0 },
2942 { "xaddS", { Evh1
, Gv
}, 0 },
2943 { PREFIX_TABLE (PREFIX_0FC2
) },
2944 { PREFIX_TABLE (PREFIX_0FC3
) },
2945 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_MANDATORY
},
2946 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_MANDATORY
},
2947 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
2948 { REG_TABLE (REG_0FC7
) },
2950 { "bswap", { RMeAX
}, 0 },
2951 { "bswap", { RMeCX
}, 0 },
2952 { "bswap", { RMeDX
}, 0 },
2953 { "bswap", { RMeBX
}, 0 },
2954 { "bswap", { RMeSP
}, 0 },
2955 { "bswap", { RMeBP
}, 0 },
2956 { "bswap", { RMeSI
}, 0 },
2957 { "bswap", { RMeDI
}, 0 },
2959 { PREFIX_TABLE (PREFIX_0FD0
) },
2960 { "psrlw", { MX
, EM
}, PREFIX_MANDATORY
},
2961 { "psrld", { MX
, EM
}, PREFIX_MANDATORY
},
2962 { "psrlq", { MX
, EM
}, PREFIX_MANDATORY
},
2963 { "paddq", { MX
, EM
}, PREFIX_MANDATORY
},
2964 { "pmullw", { MX
, EM
}, PREFIX_MANDATORY
},
2965 { PREFIX_TABLE (PREFIX_0FD6
) },
2966 { MOD_TABLE (MOD_0FD7
) },
2968 { "psubusb", { MX
, EM
}, PREFIX_MANDATORY
},
2969 { "psubusw", { MX
, EM
}, PREFIX_MANDATORY
},
2970 { "pminub", { MX
, EM
}, PREFIX_MANDATORY
},
2971 { "pand", { MX
, EM
}, PREFIX_MANDATORY
},
2972 { "paddusb", { MX
, EM
}, PREFIX_MANDATORY
},
2973 { "paddusw", { MX
, EM
}, PREFIX_MANDATORY
},
2974 { "pmaxub", { MX
, EM
}, PREFIX_MANDATORY
},
2975 { "pandn", { MX
, EM
}, PREFIX_MANDATORY
},
2977 { "pavgb", { MX
, EM
}, PREFIX_MANDATORY
},
2978 { "psraw", { MX
, EM
}, PREFIX_MANDATORY
},
2979 { "psrad", { MX
, EM
}, PREFIX_MANDATORY
},
2980 { "pavgw", { MX
, EM
}, PREFIX_MANDATORY
},
2981 { "pmulhuw", { MX
, EM
}, PREFIX_MANDATORY
},
2982 { "pmulhw", { MX
, EM
}, PREFIX_MANDATORY
},
2983 { PREFIX_TABLE (PREFIX_0FE6
) },
2984 { PREFIX_TABLE (PREFIX_0FE7
) },
2986 { "psubsb", { MX
, EM
}, PREFIX_MANDATORY
},
2987 { "psubsw", { MX
, EM
}, PREFIX_MANDATORY
},
2988 { "pminsw", { MX
, EM
}, PREFIX_MANDATORY
},
2989 { "por", { MX
, EM
}, PREFIX_MANDATORY
},
2990 { "paddsb", { MX
, EM
}, PREFIX_MANDATORY
},
2991 { "paddsw", { MX
, EM
}, PREFIX_MANDATORY
},
2992 { "pmaxsw", { MX
, EM
}, PREFIX_MANDATORY
},
2993 { "pxor", { MX
, EM
}, PREFIX_MANDATORY
},
2995 { PREFIX_TABLE (PREFIX_0FF0
) },
2996 { "psllw", { MX
, EM
}, PREFIX_MANDATORY
},
2997 { "pslld", { MX
, EM
}, PREFIX_MANDATORY
},
2998 { "psllq", { MX
, EM
}, PREFIX_MANDATORY
},
2999 { "pmuludq", { MX
, EM
}, PREFIX_MANDATORY
},
3000 { "pmaddwd", { MX
, EM
}, PREFIX_MANDATORY
},
3001 { "psadbw", { MX
, EM
}, PREFIX_MANDATORY
},
3002 { PREFIX_TABLE (PREFIX_0FF7
) },
3004 { "psubb", { MX
, EM
}, PREFIX_MANDATORY
},
3005 { "psubw", { MX
, EM
}, PREFIX_MANDATORY
},
3006 { "psubd", { MX
, EM
}, PREFIX_MANDATORY
},
3007 { "psubq", { MX
, EM
}, PREFIX_MANDATORY
},
3008 { "paddb", { MX
, EM
}, PREFIX_MANDATORY
},
3009 { "paddw", { MX
, EM
}, PREFIX_MANDATORY
},
3010 { "paddd", { MX
, EM
}, PREFIX_MANDATORY
},
3014 static const unsigned char onebyte_has_modrm
[256] = {
3015 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3016 /* ------------------------------- */
3017 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3018 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3019 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3020 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3021 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3022 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3023 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3024 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3025 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3026 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3027 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3028 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3029 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3030 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3031 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3032 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3033 /* ------------------------------- */
3034 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3037 static const unsigned char twobyte_has_modrm
[256] = {
3038 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3039 /* ------------------------------- */
3040 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3041 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3042 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3043 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3044 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3045 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3046 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3047 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3048 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3049 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3050 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3051 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3052 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3053 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3054 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3055 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3056 /* ------------------------------- */
3057 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3060 static char obuf
[100];
3062 static char *mnemonicendp
;
3063 static char scratchbuf
[100];
3064 static unsigned char *start_codep
;
3065 static unsigned char *insn_codep
;
3066 static unsigned char *codep
;
3067 static unsigned char *end_codep
;
3068 static int last_lock_prefix
;
3069 static int last_repz_prefix
;
3070 static int last_repnz_prefix
;
3071 static int last_data_prefix
;
3072 static int last_addr_prefix
;
3073 static int last_rex_prefix
;
3074 static int last_seg_prefix
;
3075 static int fwait_prefix
;
3076 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3077 static int mandatory_prefix
;
3078 /* The active segment register prefix. */
3079 static int active_seg_prefix
;
3080 #define MAX_CODE_LENGTH 15
3081 /* We can up to 14 prefixes since the maximum instruction length is
3083 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3084 static disassemble_info
*the_info
;
3092 static unsigned char need_modrm
;
3102 int register_specifier
;
3109 int mask_register_specifier
;
3115 static unsigned char need_vex
;
3116 static unsigned char need_vex_reg
;
3117 static unsigned char vex_w_done
;
3125 /* If we are accessing mod/rm/reg without need_modrm set, then the
3126 values are stale. Hitting this abort likely indicates that you
3127 need to update onebyte_has_modrm or twobyte_has_modrm. */
3128 #define MODRM_CHECK if (!need_modrm) abort ()
3130 static const char **names64
;
3131 static const char **names32
;
3132 static const char **names16
;
3133 static const char **names8
;
3134 static const char **names8rex
;
3135 static const char **names_seg
;
3136 static const char *index64
;
3137 static const char *index32
;
3138 static const char **index16
;
3139 static const char **names_bnd
;
3141 static const char *intel_names64
[] = {
3142 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3145 static const char *intel_names32
[] = {
3146 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3147 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3149 static const char *intel_names16
[] = {
3150 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3151 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3153 static const char *intel_names8
[] = {
3154 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3156 static const char *intel_names8rex
[] = {
3157 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3158 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3160 static const char *intel_names_seg
[] = {
3161 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3163 static const char *intel_index64
= "riz";
3164 static const char *intel_index32
= "eiz";
3165 static const char *intel_index16
[] = {
3166 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3169 static const char *att_names64
[] = {
3170 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3171 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3173 static const char *att_names32
[] = {
3174 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3175 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3177 static const char *att_names16
[] = {
3178 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3179 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3181 static const char *att_names8
[] = {
3182 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3184 static const char *att_names8rex
[] = {
3185 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3186 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3188 static const char *att_names_seg
[] = {
3189 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3191 static const char *att_index64
= "%riz";
3192 static const char *att_index32
= "%eiz";
3193 static const char *att_index16
[] = {
3194 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3197 static const char **names_mm
;
3198 static const char *intel_names_mm
[] = {
3199 "mm0", "mm1", "mm2", "mm3",
3200 "mm4", "mm5", "mm6", "mm7"
3202 static const char *att_names_mm
[] = {
3203 "%mm0", "%mm1", "%mm2", "%mm3",
3204 "%mm4", "%mm5", "%mm6", "%mm7"
3207 static const char *intel_names_bnd
[] = {
3208 "bnd0", "bnd1", "bnd2", "bnd3"
3211 static const char *att_names_bnd
[] = {
3212 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3215 static const char **names_xmm
;
3216 static const char *intel_names_xmm
[] = {
3217 "xmm0", "xmm1", "xmm2", "xmm3",
3218 "xmm4", "xmm5", "xmm6", "xmm7",
3219 "xmm8", "xmm9", "xmm10", "xmm11",
3220 "xmm12", "xmm13", "xmm14", "xmm15",
3221 "xmm16", "xmm17", "xmm18", "xmm19",
3222 "xmm20", "xmm21", "xmm22", "xmm23",
3223 "xmm24", "xmm25", "xmm26", "xmm27",
3224 "xmm28", "xmm29", "xmm30", "xmm31"
3226 static const char *att_names_xmm
[] = {
3227 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3228 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3229 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3230 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3231 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3232 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3233 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3234 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3237 static const char **names_ymm
;
3238 static const char *intel_names_ymm
[] = {
3239 "ymm0", "ymm1", "ymm2", "ymm3",
3240 "ymm4", "ymm5", "ymm6", "ymm7",
3241 "ymm8", "ymm9", "ymm10", "ymm11",
3242 "ymm12", "ymm13", "ymm14", "ymm15",
3243 "ymm16", "ymm17", "ymm18", "ymm19",
3244 "ymm20", "ymm21", "ymm22", "ymm23",
3245 "ymm24", "ymm25", "ymm26", "ymm27",
3246 "ymm28", "ymm29", "ymm30", "ymm31"
3248 static const char *att_names_ymm
[] = {
3249 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3250 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3251 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3252 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3253 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3254 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3255 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3256 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3259 static const char **names_zmm
;
3260 static const char *intel_names_zmm
[] = {
3261 "zmm0", "zmm1", "zmm2", "zmm3",
3262 "zmm4", "zmm5", "zmm6", "zmm7",
3263 "zmm8", "zmm9", "zmm10", "zmm11",
3264 "zmm12", "zmm13", "zmm14", "zmm15",
3265 "zmm16", "zmm17", "zmm18", "zmm19",
3266 "zmm20", "zmm21", "zmm22", "zmm23",
3267 "zmm24", "zmm25", "zmm26", "zmm27",
3268 "zmm28", "zmm29", "zmm30", "zmm31"
3270 static const char *att_names_zmm
[] = {
3271 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3272 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3273 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3274 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3275 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3276 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3277 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3278 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3281 static const char **names_mask
;
3282 static const char *intel_names_mask
[] = {
3283 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3285 static const char *att_names_mask
[] = {
3286 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3289 static const char *names_rounding
[] =
3297 static const struct dis386 reg_table
[][8] = {
3300 { "addA", { Ebh1
, Ib
}, 0 },
3301 { "orA", { Ebh1
, Ib
}, 0 },
3302 { "adcA", { Ebh1
, Ib
}, 0 },
3303 { "sbbA", { Ebh1
, Ib
}, 0 },
3304 { "andA", { Ebh1
, Ib
}, 0 },
3305 { "subA", { Ebh1
, Ib
}, 0 },
3306 { "xorA", { Ebh1
, Ib
}, 0 },
3307 { "cmpA", { Eb
, Ib
}, 0 },
3311 { "addQ", { Evh1
, Iv
}, 0 },
3312 { "orQ", { Evh1
, Iv
}, 0 },
3313 { "adcQ", { Evh1
, Iv
}, 0 },
3314 { "sbbQ", { Evh1
, Iv
}, 0 },
3315 { "andQ", { Evh1
, Iv
}, 0 },
3316 { "subQ", { Evh1
, Iv
}, 0 },
3317 { "xorQ", { Evh1
, Iv
}, 0 },
3318 { "cmpQ", { Ev
, Iv
}, 0 },
3322 { "addQ", { Evh1
, sIb
}, 0 },
3323 { "orQ", { Evh1
, sIb
}, 0 },
3324 { "adcQ", { Evh1
, sIb
}, 0 },
3325 { "sbbQ", { Evh1
, sIb
}, 0 },
3326 { "andQ", { Evh1
, sIb
}, 0 },
3327 { "subQ", { Evh1
, sIb
}, 0 },
3328 { "xorQ", { Evh1
, sIb
}, 0 },
3329 { "cmpQ", { Ev
, sIb
}, 0 },
3333 { "popU", { stackEv
}, 0 },
3334 { XOP_8F_TABLE (XOP_09
) },
3338 { XOP_8F_TABLE (XOP_09
) },
3342 { "rolA", { Eb
, Ib
}, 0 },
3343 { "rorA", { Eb
, Ib
}, 0 },
3344 { "rclA", { Eb
, Ib
}, 0 },
3345 { "rcrA", { Eb
, Ib
}, 0 },
3346 { "shlA", { Eb
, Ib
}, 0 },
3347 { "shrA", { Eb
, Ib
}, 0 },
3349 { "sarA", { Eb
, Ib
}, 0 },
3353 { "rolQ", { Ev
, Ib
}, 0 },
3354 { "rorQ", { Ev
, Ib
}, 0 },
3355 { "rclQ", { Ev
, Ib
}, 0 },
3356 { "rcrQ", { Ev
, Ib
}, 0 },
3357 { "shlQ", { Ev
, Ib
}, 0 },
3358 { "shrQ", { Ev
, Ib
}, 0 },
3360 { "sarQ", { Ev
, Ib
}, 0 },
3364 { "movA", { Ebh3
, Ib
}, 0 },
3371 { MOD_TABLE (MOD_C6_REG_7
) },
3375 { "movQ", { Evh3
, Iv
}, 0 },
3382 { MOD_TABLE (MOD_C7_REG_7
) },
3386 { "rolA", { Eb
, I1
}, 0 },
3387 { "rorA", { Eb
, I1
}, 0 },
3388 { "rclA", { Eb
, I1
}, 0 },
3389 { "rcrA", { Eb
, I1
}, 0 },
3390 { "shlA", { Eb
, I1
}, 0 },
3391 { "shrA", { Eb
, I1
}, 0 },
3393 { "sarA", { Eb
, I1
}, 0 },
3397 { "rolQ", { Ev
, I1
}, 0 },
3398 { "rorQ", { Ev
, I1
}, 0 },
3399 { "rclQ", { Ev
, I1
}, 0 },
3400 { "rcrQ", { Ev
, I1
}, 0 },
3401 { "shlQ", { Ev
, I1
}, 0 },
3402 { "shrQ", { Ev
, I1
}, 0 },
3404 { "sarQ", { Ev
, I1
}, 0 },
3408 { "rolA", { Eb
, CL
}, 0 },
3409 { "rorA", { Eb
, CL
}, 0 },
3410 { "rclA", { Eb
, CL
}, 0 },
3411 { "rcrA", { Eb
, CL
}, 0 },
3412 { "shlA", { Eb
, CL
}, 0 },
3413 { "shrA", { Eb
, CL
}, 0 },
3415 { "sarA", { Eb
, CL
}, 0 },
3419 { "rolQ", { Ev
, CL
}, 0 },
3420 { "rorQ", { Ev
, CL
}, 0 },
3421 { "rclQ", { Ev
, CL
}, 0 },
3422 { "rcrQ", { Ev
, CL
}, 0 },
3423 { "shlQ", { Ev
, CL
}, 0 },
3424 { "shrQ", { Ev
, CL
}, 0 },
3426 { "sarQ", { Ev
, CL
}, 0 },
3430 { "testA", { Eb
, Ib
}, 0 },
3432 { "notA", { Ebh1
}, 0 },
3433 { "negA", { Ebh1
}, 0 },
3434 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3435 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3436 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3437 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3441 { "testQ", { Ev
, Iv
}, 0 },
3443 { "notQ", { Evh1
}, 0 },
3444 { "negQ", { Evh1
}, 0 },
3445 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3446 { "imulQ", { Ev
}, 0 },
3447 { "divQ", { Ev
}, 0 },
3448 { "idivQ", { Ev
}, 0 },
3452 { "incA", { Ebh1
}, 0 },
3453 { "decA", { Ebh1
}, 0 },
3457 { "incQ", { Evh1
}, 0 },
3458 { "decQ", { Evh1
}, 0 },
3459 { "call{T|}", { indirEv
, BND
}, 0 },
3460 { MOD_TABLE (MOD_FF_REG_3
) },
3461 { "jmp{T|}", { indirEv
, BND
}, 0 },
3462 { MOD_TABLE (MOD_FF_REG_5
) },
3463 { "pushU", { stackEv
}, 0 },
3468 { "sldtD", { Sv
}, 0 },
3469 { "strD", { Sv
}, 0 },
3470 { "lldt", { Ew
}, 0 },
3471 { "ltr", { Ew
}, 0 },
3472 { "verr", { Ew
}, 0 },
3473 { "verw", { Ew
}, 0 },
3479 { MOD_TABLE (MOD_0F01_REG_0
) },
3480 { MOD_TABLE (MOD_0F01_REG_1
) },
3481 { MOD_TABLE (MOD_0F01_REG_2
) },
3482 { MOD_TABLE (MOD_0F01_REG_3
) },
3483 { "smswD", { Sv
}, 0 },
3485 { "lmsw", { Ew
}, 0 },
3486 { MOD_TABLE (MOD_0F01_REG_7
) },
3490 { "prefetch", { Mb
}, 0 },
3491 { "prefetchw", { Mb
}, 0 },
3492 { "prefetchwt1", { Mb
}, 0 },
3493 { "prefetch", { Mb
}, 0 },
3494 { "prefetch", { Mb
}, 0 },
3495 { "prefetch", { Mb
}, 0 },
3496 { "prefetch", { Mb
}, 0 },
3497 { "prefetch", { Mb
}, 0 },
3501 { MOD_TABLE (MOD_0F18_REG_0
) },
3502 { MOD_TABLE (MOD_0F18_REG_1
) },
3503 { MOD_TABLE (MOD_0F18_REG_2
) },
3504 { MOD_TABLE (MOD_0F18_REG_3
) },
3505 { MOD_TABLE (MOD_0F18_REG_4
) },
3506 { MOD_TABLE (MOD_0F18_REG_5
) },
3507 { MOD_TABLE (MOD_0F18_REG_6
) },
3508 { MOD_TABLE (MOD_0F18_REG_7
) },
3514 { MOD_TABLE (MOD_0F71_REG_2
) },
3516 { MOD_TABLE (MOD_0F71_REG_4
) },
3518 { MOD_TABLE (MOD_0F71_REG_6
) },
3524 { MOD_TABLE (MOD_0F72_REG_2
) },
3526 { MOD_TABLE (MOD_0F72_REG_4
) },
3528 { MOD_TABLE (MOD_0F72_REG_6
) },
3534 { MOD_TABLE (MOD_0F73_REG_2
) },
3535 { MOD_TABLE (MOD_0F73_REG_3
) },
3538 { MOD_TABLE (MOD_0F73_REG_6
) },
3539 { MOD_TABLE (MOD_0F73_REG_7
) },
3543 { "montmul", { { OP_0f07
, 0 } }, 0 },
3544 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3545 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3549 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3550 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3551 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3552 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3553 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3554 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3558 { MOD_TABLE (MOD_0FAE_REG_0
) },
3559 { MOD_TABLE (MOD_0FAE_REG_1
) },
3560 { MOD_TABLE (MOD_0FAE_REG_2
) },
3561 { MOD_TABLE (MOD_0FAE_REG_3
) },
3562 { MOD_TABLE (MOD_0FAE_REG_4
) },
3563 { MOD_TABLE (MOD_0FAE_REG_5
) },
3564 { MOD_TABLE (MOD_0FAE_REG_6
) },
3565 { MOD_TABLE (MOD_0FAE_REG_7
) },
3573 { "btQ", { Ev
, Ib
}, 0 },
3574 { "btsQ", { Evh1
, Ib
}, 0 },
3575 { "btrQ", { Evh1
, Ib
}, 0 },
3576 { "btcQ", { Evh1
, Ib
}, 0 },
3581 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3583 { MOD_TABLE (MOD_0FC7_REG_3
) },
3584 { MOD_TABLE (MOD_0FC7_REG_4
) },
3585 { MOD_TABLE (MOD_0FC7_REG_5
) },
3586 { MOD_TABLE (MOD_0FC7_REG_6
) },
3587 { MOD_TABLE (MOD_0FC7_REG_7
) },
3593 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3595 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3597 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3603 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3605 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3607 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3613 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3614 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3617 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3618 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3624 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3625 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3627 /* REG_VEX_0F38F3 */
3630 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3631 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3632 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3636 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3637 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3641 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3642 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3644 /* REG_XOP_TBM_01 */
3647 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3648 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3649 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3650 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3651 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3652 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3653 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3655 /* REG_XOP_TBM_02 */
3658 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3663 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3665 #define NEED_REG_TABLE
3666 #include "i386-dis-evex.h"
3667 #undef NEED_REG_TABLE
3670 static const struct dis386 prefix_table
[][4] = {
3673 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3674 { "pause", { XX
}, 0 },
3675 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3680 { "movups", { XM
, EXx
}, PREFIX_MANDATORY
},
3681 { "movss", { XM
, EXd
}, PREFIX_MANDATORY
},
3682 { "movupd", { XM
, EXx
}, PREFIX_MANDATORY
},
3683 { "movsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3688 { "movups", { EXxS
, XM
}, PREFIX_MANDATORY
},
3689 { "movss", { EXdS
, XM
}, PREFIX_MANDATORY
},
3690 { "movupd", { EXxS
, XM
}, PREFIX_MANDATORY
},
3691 { "movsd", { EXqS
, XM
}, PREFIX_MANDATORY
},
3696 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3697 { "movsldup", { XM
, EXx
}, PREFIX_MANDATORY
},
3698 { "movlpd", { XM
, EXq
}, PREFIX_MANDATORY
},
3699 { "movddup", { XM
, EXq
}, PREFIX_MANDATORY
},
3704 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3705 { "movshdup", { XM
, EXx
}, PREFIX_MANDATORY
},
3706 { "movhpd", { XM
, EXq
}, PREFIX_MANDATORY
},
3711 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3712 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3713 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3714 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3719 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3720 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3721 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3722 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3727 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_MANDATORY
},
3728 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_MANDATORY
},
3729 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_MANDATORY
},
3730 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3735 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3743 { "cvttps2pi", { MXC
, EXq
}, PREFIX_MANDATORY
},
3744 { "cvttss2siY", { Gv
, EXd
}, PREFIX_MANDATORY
},
3745 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_MANDATORY
},
3746 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_MANDATORY
},
3751 { "cvtps2pi", { MXC
, EXq
}, PREFIX_MANDATORY
},
3752 { "cvtss2siY", { Gv
, EXd
}, PREFIX_MANDATORY
},
3753 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_MANDATORY
},
3754 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_MANDATORY
},
3759 { "ucomiss",{ XM
, EXd
}, 0 },
3761 { "ucomisd",{ XM
, EXq
}, 0 },
3766 { "comiss", { XM
, EXd
}, 0 },
3768 { "comisd", { XM
, EXq
}, 0 },
3773 { "sqrtps", { XM
, EXx
}, PREFIX_MANDATORY
},
3774 { "sqrtss", { XM
, EXd
}, PREFIX_MANDATORY
},
3775 { "sqrtpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3776 { "sqrtsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3781 { "rsqrtps",{ XM
, EXx
}, PREFIX_MANDATORY
},
3782 { "rsqrtss",{ XM
, EXd
}, PREFIX_MANDATORY
},
3787 { "rcpps", { XM
, EXx
}, PREFIX_MANDATORY
},
3788 { "rcpss", { XM
, EXd
}, PREFIX_MANDATORY
},
3793 { "addps", { XM
, EXx
}, PREFIX_MANDATORY
},
3794 { "addss", { XM
, EXd
}, PREFIX_MANDATORY
},
3795 { "addpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3796 { "addsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3801 { "mulps", { XM
, EXx
}, PREFIX_MANDATORY
},
3802 { "mulss", { XM
, EXd
}, PREFIX_MANDATORY
},
3803 { "mulpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3804 { "mulsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3809 { "cvtps2pd", { XM
, EXq
}, PREFIX_MANDATORY
},
3810 { "cvtss2sd", { XM
, EXd
}, PREFIX_MANDATORY
},
3811 { "cvtpd2ps", { XM
, EXx
}, PREFIX_MANDATORY
},
3812 { "cvtsd2ss", { XM
, EXq
}, PREFIX_MANDATORY
},
3817 { "cvtdq2ps", { XM
, EXx
}, PREFIX_MANDATORY
},
3818 { "cvttps2dq", { XM
, EXx
}, PREFIX_MANDATORY
},
3819 { "cvtps2dq", { XM
, EXx
}, PREFIX_MANDATORY
},
3824 { "subps", { XM
, EXx
}, PREFIX_MANDATORY
},
3825 { "subss", { XM
, EXd
}, PREFIX_MANDATORY
},
3826 { "subpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3827 { "subsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3832 { "minps", { XM
, EXx
}, PREFIX_MANDATORY
},
3833 { "minss", { XM
, EXd
}, PREFIX_MANDATORY
},
3834 { "minpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3835 { "minsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3840 { "divps", { XM
, EXx
}, PREFIX_MANDATORY
},
3841 { "divss", { XM
, EXd
}, PREFIX_MANDATORY
},
3842 { "divpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3843 { "divsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3848 { "maxps", { XM
, EXx
}, PREFIX_MANDATORY
},
3849 { "maxss", { XM
, EXd
}, PREFIX_MANDATORY
},
3850 { "maxpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3851 { "maxsd", { XM
, EXq
}, PREFIX_MANDATORY
},
3856 { "punpcklbw",{ MX
, EMd
}, PREFIX_MANDATORY
},
3858 { "punpcklbw",{ MX
, EMx
}, PREFIX_MANDATORY
},
3863 { "punpcklwd",{ MX
, EMd
}, PREFIX_MANDATORY
},
3865 { "punpcklwd",{ MX
, EMx
}, PREFIX_MANDATORY
},
3870 { "punpckldq",{ MX
, EMd
}, PREFIX_MANDATORY
},
3872 { "punpckldq",{ MX
, EMx
}, PREFIX_MANDATORY
},
3879 { "punpcklqdq", { XM
, EXx
}, PREFIX_MANDATORY
},
3886 { "punpckhqdq", { XM
, EXx
}, PREFIX_MANDATORY
},
3891 { "movq", { MX
, EM
}, PREFIX_MANDATORY
},
3892 { "movdqu", { XM
, EXx
}, PREFIX_MANDATORY
},
3893 { "movdqa", { XM
, EXx
}, PREFIX_MANDATORY
},
3898 { "pshufw", { MX
, EM
, Ib
}, PREFIX_MANDATORY
},
3899 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
3900 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
3901 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
3904 /* PREFIX_0F73_REG_3 */
3908 { "psrldq", { XS
, Ib
}, 0 },
3911 /* PREFIX_0F73_REG_7 */
3915 { "pslldq", { XS
, Ib
}, 0 },
3920 {"vmread", { Em
, Gm
}, 0 },
3922 {"extrq", { XS
, Ib
, Ib
}, 0 },
3923 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3928 {"vmwrite", { Gm
, Em
}, 0 },
3930 {"extrq", { XM
, XS
}, 0 },
3931 {"insertq", { XM
, XS
}, 0 },
3938 { "haddpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3939 { "haddps", { XM
, EXx
}, PREFIX_MANDATORY
},
3946 { "hsubpd", { XM
, EXx
}, PREFIX_MANDATORY
},
3947 { "hsubps", { XM
, EXx
}, PREFIX_MANDATORY
},
3952 { "movK", { Edq
, MX
}, PREFIX_MANDATORY
},
3953 { "movq", { XM
, EXq
}, PREFIX_MANDATORY
},
3954 { "movK", { Edq
, XM
}, PREFIX_MANDATORY
},
3959 { "movq", { EMS
, MX
}, PREFIX_MANDATORY
},
3960 { "movdqu", { EXxS
, XM
}, PREFIX_MANDATORY
},
3961 { "movdqa", { EXxS
, XM
}, PREFIX_MANDATORY
},
3964 /* PREFIX_0FAE_REG_0 */
3967 { "rdfsbase", { Ev
}, 0 },
3970 /* PREFIX_0FAE_REG_1 */
3973 { "rdgsbase", { Ev
}, 0 },
3976 /* PREFIX_0FAE_REG_2 */
3979 { "wrfsbase", { Ev
}, 0 },
3982 /* PREFIX_0FAE_REG_3 */
3985 { "wrgsbase", { Ev
}, 0 },
3988 /* PREFIX_0FAE_REG_6 */
3990 { "xsaveopt", { FXSAVE
}, 0 },
3992 { "clwb", { Mb
}, 0 },
3995 /* PREFIX_0FAE_REG_7 */
3997 { "clflush", { Mb
}, 0 },
3999 { "clflushopt", { Mb
}, 0 },
4002 /* PREFIX_RM_0_0FAE_REG_7 */
4004 { "sfence", { Skip_MODRM
}, 0 },
4006 { "pcommit", { Skip_MODRM
}, 0 },
4012 { "popcntS", { Gv
, Ev
}, 0 },
4017 { "bsfS", { Gv
, Ev
}, 0 },
4018 { "tzcntS", { Gv
, Ev
}, 0 },
4019 { "bsfS", { Gv
, Ev
}, 0 },
4024 { "bsrS", { Gv
, Ev
}, 0 },
4025 { "lzcntS", { Gv
, Ev
}, 0 },
4026 { "bsrS", { Gv
, Ev
}, 0 },
4031 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_MANDATORY
},
4032 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_MANDATORY
},
4033 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_MANDATORY
},
4034 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_MANDATORY
},
4039 { "movntiS", { Ma
, Gv
}, PREFIX_MANDATORY
},
4042 /* PREFIX_0FC7_REG_6 */
4044 { "vmptrld",{ Mq
}, 0 },
4045 { "vmxon", { Mq
}, 0 },
4046 { "vmclear",{ Mq
}, 0 },
4053 { "addsubpd", { XM
, EXx
}, 0 },
4054 { "addsubps", { XM
, EXx
}, 0 },
4060 { "movq2dq",{ XM
, MS
}, 0 },
4061 { "movq", { EXqS
, XM
}, 0 },
4062 { "movdq2q",{ MX
, XS
}, 0 },
4068 { "cvtdq2pd", { XM
, EXq
}, PREFIX_MANDATORY
},
4069 { "cvttpd2dq", { XM
, EXx
}, PREFIX_MANDATORY
},
4070 { "cvtpd2dq", { XM
, EXx
}, PREFIX_MANDATORY
},
4075 { "movntq", { Mq
, MX
}, PREFIX_MANDATORY
},
4077 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4085 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4090 { "maskmovq", { MX
, MS
}, PREFIX_MANDATORY
},
4092 { "maskmovdqu", { XM
, XS
}, PREFIX_MANDATORY
},
4099 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_MANDATORY
},
4106 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_MANDATORY
},
4113 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_MANDATORY
},
4120 { "ptest", { XM
, EXx
}, PREFIX_MANDATORY
},
4127 { "pmovsxbw", { XM
, EXq
}, PREFIX_MANDATORY
},
4134 { "pmovsxbd", { XM
, EXd
}, PREFIX_MANDATORY
},
4141 { "pmovsxbq", { XM
, EXw
}, PREFIX_MANDATORY
},
4148 { "pmovsxwd", { XM
, EXq
}, PREFIX_MANDATORY
},
4155 { "pmovsxwq", { XM
, EXd
}, PREFIX_MANDATORY
},
4162 { "pmovsxdq", { XM
, EXq
}, PREFIX_MANDATORY
},
4169 { "pmuldq", { XM
, EXx
}, PREFIX_MANDATORY
},
4176 { "pcmpeqq", { XM
, EXx
}, PREFIX_MANDATORY
},
4183 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4190 { "packusdw", { XM
, EXx
}, PREFIX_MANDATORY
},
4197 { "pmovzxbw", { XM
, EXq
}, PREFIX_MANDATORY
},
4204 { "pmovzxbd", { XM
, EXd
}, PREFIX_MANDATORY
},
4211 { "pmovzxbq", { XM
, EXw
}, PREFIX_MANDATORY
},
4218 { "pmovzxwd", { XM
, EXq
}, PREFIX_MANDATORY
},
4225 { "pmovzxwq", { XM
, EXd
}, PREFIX_MANDATORY
},
4232 { "pmovzxdq", { XM
, EXq
}, PREFIX_MANDATORY
},
4239 { "pcmpgtq", { XM
, EXx
}, PREFIX_MANDATORY
},
4246 { "pminsb", { XM
, EXx
}, PREFIX_MANDATORY
},
4253 { "pminsd", { XM
, EXx
}, PREFIX_MANDATORY
},
4260 { "pminuw", { XM
, EXx
}, PREFIX_MANDATORY
},
4267 { "pminud", { XM
, EXx
}, PREFIX_MANDATORY
},
4274 { "pmaxsb", { XM
, EXx
}, PREFIX_MANDATORY
},
4281 { "pmaxsd", { XM
, EXx
}, PREFIX_MANDATORY
},
4288 { "pmaxuw", { XM
, EXx
}, PREFIX_MANDATORY
},
4295 { "pmaxud", { XM
, EXx
}, PREFIX_MANDATORY
},
4302 { "pmulld", { XM
, EXx
}, PREFIX_MANDATORY
},
4309 { "phminposuw", { XM
, EXx
}, PREFIX_MANDATORY
},
4316 { "invept", { Gm
, Mo
}, PREFIX_MANDATORY
},
4323 { "invvpid", { Gm
, Mo
}, PREFIX_MANDATORY
},
4330 { "invpcid", { Gm
, M
}, PREFIX_MANDATORY
},
4335 { "sha1nexte", { XM
, EXxmm
}, PREFIX_MANDATORY
},
4340 { "sha1msg1", { XM
, EXxmm
}, PREFIX_MANDATORY
},
4345 { "sha1msg2", { XM
, EXxmm
}, PREFIX_MANDATORY
},
4350 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_MANDATORY
},
4355 { "sha256msg1", { XM
, EXxmm
}, PREFIX_MANDATORY
},
4360 { "sha256msg2", { XM
, EXxmm
}, PREFIX_MANDATORY
},
4367 { "aesimc", { XM
, EXx
}, PREFIX_MANDATORY
},
4374 { "aesenc", { XM
, EXx
}, PREFIX_MANDATORY
},
4381 { "aesenclast", { XM
, EXx
}, PREFIX_MANDATORY
},
4388 { "aesdec", { XM
, EXx
}, PREFIX_MANDATORY
},
4395 { "aesdeclast", { XM
, EXx
}, PREFIX_MANDATORY
},
4400 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_MANDATORY
},
4402 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_MANDATORY
},
4403 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_MANDATORY
},
4408 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_MANDATORY
},
4410 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_MANDATORY
},
4411 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_MANDATORY
},
4417 { "adoxS", { Gdq
, Edq
}, PREFIX_MANDATORY
},
4418 { "adcxS", { Gdq
, Edq
}, PREFIX_MANDATORY
},
4426 { "roundps", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4433 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4440 { "roundss", { XM
, EXd
, Ib
}, PREFIX_MANDATORY
},
4447 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_MANDATORY
},
4454 { "blendps", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4461 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4468 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4475 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_MANDATORY
},
4482 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_MANDATORY
},
4489 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_MANDATORY
},
4496 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_MANDATORY
},
4503 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_MANDATORY
},
4510 { "insertps", { XM
, EXd
, Ib
}, PREFIX_MANDATORY
},
4517 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_MANDATORY
},
4524 { "dpps", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4531 { "dppd", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4538 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4545 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_MANDATORY
},
4552 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4559 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4566 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4573 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4578 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_MANDATORY
},
4585 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_MANDATORY
},
4588 /* PREFIX_VEX_0F10 */
4590 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4591 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4592 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4593 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4596 /* PREFIX_VEX_0F11 */
4598 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4599 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4600 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4601 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4604 /* PREFIX_VEX_0F12 */
4606 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4607 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4608 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4609 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4612 /* PREFIX_VEX_0F16 */
4614 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4615 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4616 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4619 /* PREFIX_VEX_0F2A */
4622 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4627 /* PREFIX_VEX_0F2C */
4630 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4632 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4635 /* PREFIX_VEX_0F2D */
4638 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4640 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4643 /* PREFIX_VEX_0F2E */
4645 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4647 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4650 /* PREFIX_VEX_0F2F */
4652 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4654 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4657 /* PREFIX_VEX_0F41 */
4659 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4661 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4664 /* PREFIX_VEX_0F42 */
4666 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4668 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4671 /* PREFIX_VEX_0F44 */
4673 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4675 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4678 /* PREFIX_VEX_0F45 */
4680 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4682 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4685 /* PREFIX_VEX_0F46 */
4687 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4689 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4692 /* PREFIX_VEX_0F47 */
4694 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4696 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4699 /* PREFIX_VEX_0F4A */
4701 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4703 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4706 /* PREFIX_VEX_0F4B */
4708 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4710 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4713 /* PREFIX_VEX_0F51 */
4715 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4716 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4717 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4718 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4721 /* PREFIX_VEX_0F52 */
4723 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4724 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4727 /* PREFIX_VEX_0F53 */
4729 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4730 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4733 /* PREFIX_VEX_0F58 */
4735 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4736 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4737 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4738 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4741 /* PREFIX_VEX_0F59 */
4743 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4745 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4749 /* PREFIX_VEX_0F5A */
4751 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4753 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4754 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4757 /* PREFIX_VEX_0F5B */
4759 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4760 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4761 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4764 /* PREFIX_VEX_0F5C */
4766 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4768 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4772 /* PREFIX_VEX_0F5D */
4774 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4775 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4776 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4780 /* PREFIX_VEX_0F5E */
4782 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4784 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4788 /* PREFIX_VEX_0F5F */
4790 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4792 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4796 /* PREFIX_VEX_0F60 */
4800 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4803 /* PREFIX_VEX_0F61 */
4807 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4810 /* PREFIX_VEX_0F62 */
4814 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4817 /* PREFIX_VEX_0F63 */
4821 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4824 /* PREFIX_VEX_0F64 */
4828 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4831 /* PREFIX_VEX_0F65 */
4835 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4838 /* PREFIX_VEX_0F66 */
4842 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4845 /* PREFIX_VEX_0F67 */
4849 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4852 /* PREFIX_VEX_0F68 */
4856 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4859 /* PREFIX_VEX_0F69 */
4863 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4866 /* PREFIX_VEX_0F6A */
4870 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4873 /* PREFIX_VEX_0F6B */
4877 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4880 /* PREFIX_VEX_0F6C */
4884 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4887 /* PREFIX_VEX_0F6D */
4891 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4894 /* PREFIX_VEX_0F6E */
4898 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4901 /* PREFIX_VEX_0F6F */
4904 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4905 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4908 /* PREFIX_VEX_0F70 */
4911 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4912 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4913 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4916 /* PREFIX_VEX_0F71_REG_2 */
4920 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4923 /* PREFIX_VEX_0F71_REG_4 */
4927 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4930 /* PREFIX_VEX_0F71_REG_6 */
4934 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4937 /* PREFIX_VEX_0F72_REG_2 */
4941 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4944 /* PREFIX_VEX_0F72_REG_4 */
4948 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4951 /* PREFIX_VEX_0F72_REG_6 */
4955 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4958 /* PREFIX_VEX_0F73_REG_2 */
4962 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4965 /* PREFIX_VEX_0F73_REG_3 */
4969 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4972 /* PREFIX_VEX_0F73_REG_6 */
4976 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4979 /* PREFIX_VEX_0F73_REG_7 */
4983 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4986 /* PREFIX_VEX_0F74 */
4990 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4993 /* PREFIX_VEX_0F75 */
4997 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5000 /* PREFIX_VEX_0F76 */
5004 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5007 /* PREFIX_VEX_0F77 */
5009 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5012 /* PREFIX_VEX_0F7C */
5016 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5017 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5020 /* PREFIX_VEX_0F7D */
5024 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5025 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5028 /* PREFIX_VEX_0F7E */
5031 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5032 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5035 /* PREFIX_VEX_0F7F */
5038 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5039 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5042 /* PREFIX_VEX_0F90 */
5044 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5046 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5049 /* PREFIX_VEX_0F91 */
5051 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5053 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5056 /* PREFIX_VEX_0F92 */
5058 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5060 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5061 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5064 /* PREFIX_VEX_0F93 */
5066 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5072 /* PREFIX_VEX_0F98 */
5074 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5076 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5079 /* PREFIX_VEX_0F99 */
5081 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5086 /* PREFIX_VEX_0FC2 */
5088 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5089 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5090 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5091 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5094 /* PREFIX_VEX_0FC4 */
5098 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5101 /* PREFIX_VEX_0FC5 */
5105 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5108 /* PREFIX_VEX_0FD0 */
5112 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5113 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5116 /* PREFIX_VEX_0FD1 */
5120 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5123 /* PREFIX_VEX_0FD2 */
5127 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5130 /* PREFIX_VEX_0FD3 */
5134 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5137 /* PREFIX_VEX_0FD4 */
5141 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5144 /* PREFIX_VEX_0FD5 */
5148 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5151 /* PREFIX_VEX_0FD6 */
5155 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5158 /* PREFIX_VEX_0FD7 */
5162 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5165 /* PREFIX_VEX_0FD8 */
5169 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5172 /* PREFIX_VEX_0FD9 */
5176 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5179 /* PREFIX_VEX_0FDA */
5183 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5186 /* PREFIX_VEX_0FDB */
5190 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5193 /* PREFIX_VEX_0FDC */
5197 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5200 /* PREFIX_VEX_0FDD */
5204 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5207 /* PREFIX_VEX_0FDE */
5211 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5214 /* PREFIX_VEX_0FDF */
5218 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5221 /* PREFIX_VEX_0FE0 */
5225 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5228 /* PREFIX_VEX_0FE1 */
5232 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5235 /* PREFIX_VEX_0FE2 */
5239 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5242 /* PREFIX_VEX_0FE3 */
5246 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5249 /* PREFIX_VEX_0FE4 */
5253 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5256 /* PREFIX_VEX_0FE5 */
5260 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5263 /* PREFIX_VEX_0FE6 */
5266 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5267 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5268 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5271 /* PREFIX_VEX_0FE7 */
5275 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5278 /* PREFIX_VEX_0FE8 */
5282 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5285 /* PREFIX_VEX_0FE9 */
5289 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5292 /* PREFIX_VEX_0FEA */
5296 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5299 /* PREFIX_VEX_0FEB */
5303 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5306 /* PREFIX_VEX_0FEC */
5310 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5313 /* PREFIX_VEX_0FED */
5317 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5320 /* PREFIX_VEX_0FEE */
5324 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5327 /* PREFIX_VEX_0FEF */
5331 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5334 /* PREFIX_VEX_0FF0 */
5339 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5342 /* PREFIX_VEX_0FF1 */
5346 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5349 /* PREFIX_VEX_0FF2 */
5353 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5356 /* PREFIX_VEX_0FF3 */
5360 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5363 /* PREFIX_VEX_0FF4 */
5367 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5370 /* PREFIX_VEX_0FF5 */
5374 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5377 /* PREFIX_VEX_0FF6 */
5381 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5384 /* PREFIX_VEX_0FF7 */
5388 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5391 /* PREFIX_VEX_0FF8 */
5395 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5398 /* PREFIX_VEX_0FF9 */
5402 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5405 /* PREFIX_VEX_0FFA */
5409 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5412 /* PREFIX_VEX_0FFB */
5416 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5419 /* PREFIX_VEX_0FFC */
5423 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5426 /* PREFIX_VEX_0FFD */
5430 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5433 /* PREFIX_VEX_0FFE */
5437 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5440 /* PREFIX_VEX_0F3800 */
5444 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5447 /* PREFIX_VEX_0F3801 */
5451 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5454 /* PREFIX_VEX_0F3802 */
5458 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5461 /* PREFIX_VEX_0F3803 */
5465 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5468 /* PREFIX_VEX_0F3804 */
5472 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5475 /* PREFIX_VEX_0F3805 */
5479 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5482 /* PREFIX_VEX_0F3806 */
5486 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5489 /* PREFIX_VEX_0F3807 */
5493 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5496 /* PREFIX_VEX_0F3808 */
5500 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5503 /* PREFIX_VEX_0F3809 */
5507 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5510 /* PREFIX_VEX_0F380A */
5514 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5517 /* PREFIX_VEX_0F380B */
5521 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5524 /* PREFIX_VEX_0F380C */
5528 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5531 /* PREFIX_VEX_0F380D */
5535 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5538 /* PREFIX_VEX_0F380E */
5542 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5545 /* PREFIX_VEX_0F380F */
5549 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5552 /* PREFIX_VEX_0F3813 */
5556 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5559 /* PREFIX_VEX_0F3816 */
5563 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5566 /* PREFIX_VEX_0F3817 */
5570 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5573 /* PREFIX_VEX_0F3818 */
5577 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5580 /* PREFIX_VEX_0F3819 */
5584 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5587 /* PREFIX_VEX_0F381A */
5591 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5594 /* PREFIX_VEX_0F381C */
5598 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5601 /* PREFIX_VEX_0F381D */
5605 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5608 /* PREFIX_VEX_0F381E */
5612 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5615 /* PREFIX_VEX_0F3820 */
5619 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5622 /* PREFIX_VEX_0F3821 */
5626 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5629 /* PREFIX_VEX_0F3822 */
5633 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5636 /* PREFIX_VEX_0F3823 */
5640 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5643 /* PREFIX_VEX_0F3824 */
5647 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5650 /* PREFIX_VEX_0F3825 */
5654 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5657 /* PREFIX_VEX_0F3828 */
5661 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5664 /* PREFIX_VEX_0F3829 */
5668 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5671 /* PREFIX_VEX_0F382A */
5675 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5678 /* PREFIX_VEX_0F382B */
5682 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5685 /* PREFIX_VEX_0F382C */
5689 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5692 /* PREFIX_VEX_0F382D */
5696 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5699 /* PREFIX_VEX_0F382E */
5703 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5706 /* PREFIX_VEX_0F382F */
5710 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5713 /* PREFIX_VEX_0F3830 */
5717 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5720 /* PREFIX_VEX_0F3831 */
5724 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5727 /* PREFIX_VEX_0F3832 */
5731 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5734 /* PREFIX_VEX_0F3833 */
5738 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5741 /* PREFIX_VEX_0F3834 */
5745 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5748 /* PREFIX_VEX_0F3835 */
5752 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5755 /* PREFIX_VEX_0F3836 */
5759 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5762 /* PREFIX_VEX_0F3837 */
5766 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5769 /* PREFIX_VEX_0F3838 */
5773 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5776 /* PREFIX_VEX_0F3839 */
5780 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5783 /* PREFIX_VEX_0F383A */
5787 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5790 /* PREFIX_VEX_0F383B */
5794 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5797 /* PREFIX_VEX_0F383C */
5801 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5804 /* PREFIX_VEX_0F383D */
5808 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5811 /* PREFIX_VEX_0F383E */
5815 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5818 /* PREFIX_VEX_0F383F */
5822 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5825 /* PREFIX_VEX_0F3840 */
5829 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5832 /* PREFIX_VEX_0F3841 */
5836 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5839 /* PREFIX_VEX_0F3845 */
5843 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5846 /* PREFIX_VEX_0F3846 */
5850 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5853 /* PREFIX_VEX_0F3847 */
5857 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5860 /* PREFIX_VEX_0F3858 */
5864 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5867 /* PREFIX_VEX_0F3859 */
5871 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5874 /* PREFIX_VEX_0F385A */
5878 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5881 /* PREFIX_VEX_0F3878 */
5885 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5888 /* PREFIX_VEX_0F3879 */
5892 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5895 /* PREFIX_VEX_0F388C */
5899 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5902 /* PREFIX_VEX_0F388E */
5906 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5909 /* PREFIX_VEX_0F3890 */
5913 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5916 /* PREFIX_VEX_0F3891 */
5920 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5923 /* PREFIX_VEX_0F3892 */
5927 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5930 /* PREFIX_VEX_0F3893 */
5934 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5937 /* PREFIX_VEX_0F3896 */
5941 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5944 /* PREFIX_VEX_0F3897 */
5948 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5951 /* PREFIX_VEX_0F3898 */
5955 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5958 /* PREFIX_VEX_0F3899 */
5962 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5965 /* PREFIX_VEX_0F389A */
5969 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5972 /* PREFIX_VEX_0F389B */
5976 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5979 /* PREFIX_VEX_0F389C */
5983 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5986 /* PREFIX_VEX_0F389D */
5990 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5993 /* PREFIX_VEX_0F389E */
5997 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6000 /* PREFIX_VEX_0F389F */
6004 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6007 /* PREFIX_VEX_0F38A6 */
6011 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6015 /* PREFIX_VEX_0F38A7 */
6019 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6022 /* PREFIX_VEX_0F38A8 */
6026 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6029 /* PREFIX_VEX_0F38A9 */
6033 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6036 /* PREFIX_VEX_0F38AA */
6040 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6043 /* PREFIX_VEX_0F38AB */
6047 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6050 /* PREFIX_VEX_0F38AC */
6054 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6057 /* PREFIX_VEX_0F38AD */
6061 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6064 /* PREFIX_VEX_0F38AE */
6068 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6071 /* PREFIX_VEX_0F38AF */
6075 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6078 /* PREFIX_VEX_0F38B6 */
6082 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6085 /* PREFIX_VEX_0F38B7 */
6089 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6092 /* PREFIX_VEX_0F38B8 */
6096 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6099 /* PREFIX_VEX_0F38B9 */
6103 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6106 /* PREFIX_VEX_0F38BA */
6110 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6113 /* PREFIX_VEX_0F38BB */
6117 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6120 /* PREFIX_VEX_0F38BC */
6124 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6127 /* PREFIX_VEX_0F38BD */
6131 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6134 /* PREFIX_VEX_0F38BE */
6138 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6141 /* PREFIX_VEX_0F38BF */
6145 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6148 /* PREFIX_VEX_0F38DB */
6152 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6155 /* PREFIX_VEX_0F38DC */
6159 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6162 /* PREFIX_VEX_0F38DD */
6166 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6169 /* PREFIX_VEX_0F38DE */
6173 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6176 /* PREFIX_VEX_0F38DF */
6180 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6183 /* PREFIX_VEX_0F38F2 */
6185 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6188 /* PREFIX_VEX_0F38F3_REG_1 */
6190 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6193 /* PREFIX_VEX_0F38F3_REG_2 */
6195 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6198 /* PREFIX_VEX_0F38F3_REG_3 */
6200 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6203 /* PREFIX_VEX_0F38F5 */
6205 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6206 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6208 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6211 /* PREFIX_VEX_0F38F6 */
6216 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6219 /* PREFIX_VEX_0F38F7 */
6221 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6222 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6223 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6227 /* PREFIX_VEX_0F3A00 */
6231 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6234 /* PREFIX_VEX_0F3A01 */
6238 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6241 /* PREFIX_VEX_0F3A02 */
6245 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6248 /* PREFIX_VEX_0F3A04 */
6252 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6255 /* PREFIX_VEX_0F3A05 */
6259 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6262 /* PREFIX_VEX_0F3A06 */
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6269 /* PREFIX_VEX_0F3A08 */
6273 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6276 /* PREFIX_VEX_0F3A09 */
6280 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6283 /* PREFIX_VEX_0F3A0A */
6287 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6290 /* PREFIX_VEX_0F3A0B */
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6297 /* PREFIX_VEX_0F3A0C */
6301 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6304 /* PREFIX_VEX_0F3A0D */
6308 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6311 /* PREFIX_VEX_0F3A0E */
6315 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6318 /* PREFIX_VEX_0F3A0F */
6322 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6325 /* PREFIX_VEX_0F3A14 */
6329 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6332 /* PREFIX_VEX_0F3A15 */
6336 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6339 /* PREFIX_VEX_0F3A16 */
6343 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6346 /* PREFIX_VEX_0F3A17 */
6350 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6353 /* PREFIX_VEX_0F3A18 */
6357 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6360 /* PREFIX_VEX_0F3A19 */
6364 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6367 /* PREFIX_VEX_0F3A1D */
6371 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6374 /* PREFIX_VEX_0F3A20 */
6378 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6381 /* PREFIX_VEX_0F3A21 */
6385 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6388 /* PREFIX_VEX_0F3A22 */
6392 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6395 /* PREFIX_VEX_0F3A30 */
6399 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6402 /* PREFIX_VEX_0F3A31 */
6406 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6409 /* PREFIX_VEX_0F3A32 */
6413 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6416 /* PREFIX_VEX_0F3A33 */
6420 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6423 /* PREFIX_VEX_0F3A38 */
6427 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6430 /* PREFIX_VEX_0F3A39 */
6434 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6437 /* PREFIX_VEX_0F3A40 */
6441 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6444 /* PREFIX_VEX_0F3A41 */
6448 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6451 /* PREFIX_VEX_0F3A42 */
6455 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6458 /* PREFIX_VEX_0F3A44 */
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6465 /* PREFIX_VEX_0F3A46 */
6469 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6472 /* PREFIX_VEX_0F3A48 */
6476 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6479 /* PREFIX_VEX_0F3A49 */
6483 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6486 /* PREFIX_VEX_0F3A4A */
6490 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6493 /* PREFIX_VEX_0F3A4B */
6497 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6500 /* PREFIX_VEX_0F3A4C */
6504 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6507 /* PREFIX_VEX_0F3A5C */
6511 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6514 /* PREFIX_VEX_0F3A5D */
6518 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6521 /* PREFIX_VEX_0F3A5E */
6525 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6528 /* PREFIX_VEX_0F3A5F */
6532 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6535 /* PREFIX_VEX_0F3A60 */
6539 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6543 /* PREFIX_VEX_0F3A61 */
6547 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6550 /* PREFIX_VEX_0F3A62 */
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6557 /* PREFIX_VEX_0F3A63 */
6561 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6564 /* PREFIX_VEX_0F3A68 */
6568 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6571 /* PREFIX_VEX_0F3A69 */
6575 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6578 /* PREFIX_VEX_0F3A6A */
6582 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6585 /* PREFIX_VEX_0F3A6B */
6589 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6592 /* PREFIX_VEX_0F3A6C */
6596 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6599 /* PREFIX_VEX_0F3A6D */
6603 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6606 /* PREFIX_VEX_0F3A6E */
6610 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6613 /* PREFIX_VEX_0F3A6F */
6617 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6620 /* PREFIX_VEX_0F3A78 */
6624 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6627 /* PREFIX_VEX_0F3A79 */
6631 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6634 /* PREFIX_VEX_0F3A7A */
6638 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6641 /* PREFIX_VEX_0F3A7B */
6645 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6648 /* PREFIX_VEX_0F3A7C */
6652 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6656 /* PREFIX_VEX_0F3A7D */
6660 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6663 /* PREFIX_VEX_0F3A7E */
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6670 /* PREFIX_VEX_0F3A7F */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6677 /* PREFIX_VEX_0F3ADF */
6681 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6684 /* PREFIX_VEX_0F3AF0 */
6689 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6692 #define NEED_PREFIX_TABLE
6693 #include "i386-dis-evex.h"
6694 #undef NEED_PREFIX_TABLE
6697 static const struct dis386 x86_64_table
[][2] = {
6700 { "pushP", { es
}, 0 },
6705 { "popP", { es
}, 0 },
6710 { "pushP", { cs
}, 0 },
6715 { "pushP", { ss
}, 0 },
6720 { "popP", { ss
}, 0 },
6725 { "pushP", { ds
}, 0 },
6730 { "popP", { ds
}, 0 },
6735 { "daa", { XX
}, 0 },
6740 { "das", { XX
}, 0 },
6745 { "aaa", { XX
}, 0 },
6750 { "aas", { XX
}, 0 },
6755 { "pushaP", { XX
}, 0 },
6760 { "popaP", { XX
}, 0 },
6765 { MOD_TABLE (MOD_62_32BIT
) },
6766 { EVEX_TABLE (EVEX_0F
) },
6771 { "arpl", { Ew
, Gw
}, 0 },
6772 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6777 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6778 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6783 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6784 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6789 { "Jcall{T|}", { Ap
}, 0 },
6794 { MOD_TABLE (MOD_C4_32BIT
) },
6795 { VEX_C4_TABLE (VEX_0F
) },
6800 { MOD_TABLE (MOD_C5_32BIT
) },
6801 { VEX_C5_TABLE (VEX_0F
) },
6806 { "into", { XX
}, 0 },
6811 { "aam", { Ib
}, 0 },
6816 { "aad", { Ib
}, 0 },
6821 { "Jjmp{T|}", { Ap
}, 0 },
6824 /* X86_64_0F01_REG_0 */
6826 { "sgdt{Q|IQ}", { M
}, 0 },
6827 { "sgdt", { M
}, 0 },
6830 /* X86_64_0F01_REG_1 */
6832 { "sidt{Q|IQ}", { M
}, 0 },
6833 { "sidt", { M
}, 0 },
6836 /* X86_64_0F01_REG_2 */
6838 { "lgdt{Q|Q}", { M
}, 0 },
6839 { "lgdt", { M
}, 0 },
6842 /* X86_64_0F01_REG_3 */
6844 { "lidt{Q|Q}", { M
}, 0 },
6845 { "lidt", { M
}, 0 },
6849 static const struct dis386 three_byte_table
[][256] = {
6851 /* THREE_BYTE_0F38 */
6854 { "pshufb", { MX
, EM
}, PREFIX_MANDATORY
},
6855 { "phaddw", { MX
, EM
}, PREFIX_MANDATORY
},
6856 { "phaddd", { MX
, EM
}, PREFIX_MANDATORY
},
6857 { "phaddsw", { MX
, EM
}, PREFIX_MANDATORY
},
6858 { "pmaddubsw", { MX
, EM
}, PREFIX_MANDATORY
},
6859 { "phsubw", { MX
, EM
}, PREFIX_MANDATORY
},
6860 { "phsubd", { MX
, EM
}, PREFIX_MANDATORY
},
6861 { "phsubsw", { MX
, EM
}, PREFIX_MANDATORY
},
6863 { "psignb", { MX
, EM
}, PREFIX_MANDATORY
},
6864 { "psignw", { MX
, EM
}, PREFIX_MANDATORY
},
6865 { "psignd", { MX
, EM
}, PREFIX_MANDATORY
},
6866 { "pmulhrsw", { MX
, EM
}, PREFIX_MANDATORY
},
6872 { PREFIX_TABLE (PREFIX_0F3810
) },
6876 { PREFIX_TABLE (PREFIX_0F3814
) },
6877 { PREFIX_TABLE (PREFIX_0F3815
) },
6879 { PREFIX_TABLE (PREFIX_0F3817
) },
6885 { "pabsb", { MX
, EM
}, PREFIX_MANDATORY
},
6886 { "pabsw", { MX
, EM
}, PREFIX_MANDATORY
},
6887 { "pabsd", { MX
, EM
}, PREFIX_MANDATORY
},
6890 { PREFIX_TABLE (PREFIX_0F3820
) },
6891 { PREFIX_TABLE (PREFIX_0F3821
) },
6892 { PREFIX_TABLE (PREFIX_0F3822
) },
6893 { PREFIX_TABLE (PREFIX_0F3823
) },
6894 { PREFIX_TABLE (PREFIX_0F3824
) },
6895 { PREFIX_TABLE (PREFIX_0F3825
) },
6899 { PREFIX_TABLE (PREFIX_0F3828
) },
6900 { PREFIX_TABLE (PREFIX_0F3829
) },
6901 { PREFIX_TABLE (PREFIX_0F382A
) },
6902 { PREFIX_TABLE (PREFIX_0F382B
) },
6908 { PREFIX_TABLE (PREFIX_0F3830
) },
6909 { PREFIX_TABLE (PREFIX_0F3831
) },
6910 { PREFIX_TABLE (PREFIX_0F3832
) },
6911 { PREFIX_TABLE (PREFIX_0F3833
) },
6912 { PREFIX_TABLE (PREFIX_0F3834
) },
6913 { PREFIX_TABLE (PREFIX_0F3835
) },
6915 { PREFIX_TABLE (PREFIX_0F3837
) },
6917 { PREFIX_TABLE (PREFIX_0F3838
) },
6918 { PREFIX_TABLE (PREFIX_0F3839
) },
6919 { PREFIX_TABLE (PREFIX_0F383A
) },
6920 { PREFIX_TABLE (PREFIX_0F383B
) },
6921 { PREFIX_TABLE (PREFIX_0F383C
) },
6922 { PREFIX_TABLE (PREFIX_0F383D
) },
6923 { PREFIX_TABLE (PREFIX_0F383E
) },
6924 { PREFIX_TABLE (PREFIX_0F383F
) },
6926 { PREFIX_TABLE (PREFIX_0F3840
) },
6927 { PREFIX_TABLE (PREFIX_0F3841
) },
6998 { PREFIX_TABLE (PREFIX_0F3880
) },
6999 { PREFIX_TABLE (PREFIX_0F3881
) },
7000 { PREFIX_TABLE (PREFIX_0F3882
) },
7079 { PREFIX_TABLE (PREFIX_0F38C8
) },
7080 { PREFIX_TABLE (PREFIX_0F38C9
) },
7081 { PREFIX_TABLE (PREFIX_0F38CA
) },
7082 { PREFIX_TABLE (PREFIX_0F38CB
) },
7083 { PREFIX_TABLE (PREFIX_0F38CC
) },
7084 { PREFIX_TABLE (PREFIX_0F38CD
) },
7100 { PREFIX_TABLE (PREFIX_0F38DB
) },
7101 { PREFIX_TABLE (PREFIX_0F38DC
) },
7102 { PREFIX_TABLE (PREFIX_0F38DD
) },
7103 { PREFIX_TABLE (PREFIX_0F38DE
) },
7104 { PREFIX_TABLE (PREFIX_0F38DF
) },
7124 { PREFIX_TABLE (PREFIX_0F38F0
) },
7125 { PREFIX_TABLE (PREFIX_0F38F1
) },
7130 { PREFIX_TABLE (PREFIX_0F38F6
) },
7142 /* THREE_BYTE_0F3A */
7154 { PREFIX_TABLE (PREFIX_0F3A08
) },
7155 { PREFIX_TABLE (PREFIX_0F3A09
) },
7156 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7157 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7158 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7159 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7160 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7161 { "palignr", { MX
, EM
, Ib
}, PREFIX_MANDATORY
},
7167 { PREFIX_TABLE (PREFIX_0F3A14
) },
7168 { PREFIX_TABLE (PREFIX_0F3A15
) },
7169 { PREFIX_TABLE (PREFIX_0F3A16
) },
7170 { PREFIX_TABLE (PREFIX_0F3A17
) },
7181 { PREFIX_TABLE (PREFIX_0F3A20
) },
7182 { PREFIX_TABLE (PREFIX_0F3A21
) },
7183 { PREFIX_TABLE (PREFIX_0F3A22
) },
7217 { PREFIX_TABLE (PREFIX_0F3A40
) },
7218 { PREFIX_TABLE (PREFIX_0F3A41
) },
7219 { PREFIX_TABLE (PREFIX_0F3A42
) },
7221 { PREFIX_TABLE (PREFIX_0F3A44
) },
7253 { PREFIX_TABLE (PREFIX_0F3A60
) },
7254 { PREFIX_TABLE (PREFIX_0F3A61
) },
7255 { PREFIX_TABLE (PREFIX_0F3A62
) },
7256 { PREFIX_TABLE (PREFIX_0F3A63
) },
7374 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7395 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7434 /* THREE_BYTE_0F7A */
7473 { "ptest", { XX
}, PREFIX_MANDATORY
},
7510 { "phaddbw", { XM
, EXq
}, PREFIX_MANDATORY
},
7511 { "phaddbd", { XM
, EXq
}, PREFIX_MANDATORY
},
7512 { "phaddbq", { XM
, EXq
}, PREFIX_MANDATORY
},
7515 { "phaddwd", { XM
, EXq
}, PREFIX_MANDATORY
},
7516 { "phaddwq", { XM
, EXq
}, PREFIX_MANDATORY
},
7521 { "phadddq", { XM
, EXq
}, PREFIX_MANDATORY
},
7528 { "phaddubw", { XM
, EXq
}, PREFIX_MANDATORY
},
7529 { "phaddubd", { XM
, EXq
}, PREFIX_MANDATORY
},
7530 { "phaddubq", { XM
, EXq
}, PREFIX_MANDATORY
},
7533 { "phadduwd", { XM
, EXq
}, PREFIX_MANDATORY
},
7534 { "phadduwq", { XM
, EXq
}, PREFIX_MANDATORY
},
7539 { "phaddudq", { XM
, EXq
}, PREFIX_MANDATORY
},
7546 { "phsubbw", { XM
, EXq
}, PREFIX_MANDATORY
},
7547 { "phsubbd", { XM
, EXq
}, PREFIX_MANDATORY
},
7548 { "phsubbq", { XM
, EXq
}, PREFIX_MANDATORY
},
7727 static const struct dis386 xop_table
[][256] = {
7880 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7881 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7882 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7890 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7891 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7898 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7899 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7900 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7908 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7909 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7913 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7914 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7917 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7935 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7947 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7948 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7949 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7950 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7960 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7961 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7963 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8023 { REG_TABLE (REG_XOP_TBM_01
) },
8024 { REG_TABLE (REG_XOP_TBM_02
) },
8042 { REG_TABLE (REG_XOP_LWPCB
) },
8166 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8167 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8168 { "vfrczss", { XM
, EXd
}, 0 },
8169 { "vfrczsd", { XM
, EXq
}, 0 },
8184 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8185 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8186 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8187 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8188 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8189 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8190 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8191 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8193 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8194 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8195 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8196 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8239 { "vphaddbw", { XM
, EXxmm
}, 0 },
8240 { "vphaddbd", { XM
, EXxmm
}, 0 },
8241 { "vphaddbq", { XM
, EXxmm
}, 0 },
8244 { "vphaddwd", { XM
, EXxmm
}, 0 },
8245 { "vphaddwq", { XM
, EXxmm
}, 0 },
8250 { "vphadddq", { XM
, EXxmm
}, 0 },
8257 { "vphaddubw", { XM
, EXxmm
}, 0 },
8258 { "vphaddubd", { XM
, EXxmm
}, 0 },
8259 { "vphaddubq", { XM
, EXxmm
}, 0 },
8262 { "vphadduwd", { XM
, EXxmm
}, 0 },
8263 { "vphadduwq", { XM
, EXxmm
}, 0 },
8268 { "vphaddudq", { XM
, EXxmm
}, 0 },
8275 { "vphsubbw", { XM
, EXxmm
}, 0 },
8276 { "vphsubwd", { XM
, EXxmm
}, 0 },
8277 { "vphsubdq", { XM
, EXxmm
}, 0 },
8331 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8333 { REG_TABLE (REG_XOP_LWP
) },
8603 static const struct dis386 vex_table
[][256] = {
8625 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8628 { MOD_TABLE (MOD_VEX_0F13
) },
8629 { VEX_W_TABLE (VEX_W_0F14
) },
8630 { VEX_W_TABLE (VEX_W_0F15
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8632 { MOD_TABLE (MOD_VEX_0F17
) },
8652 { VEX_W_TABLE (VEX_W_0F28
) },
8653 { VEX_W_TABLE (VEX_W_0F29
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8655 { MOD_TABLE (MOD_VEX_0F2B
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8697 { MOD_TABLE (MOD_VEX_0F50
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8701 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8702 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8703 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8704 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8706 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8734 { REG_TABLE (REG_VEX_0F71
) },
8735 { REG_TABLE (REG_VEX_0F72
) },
8736 { REG_TABLE (REG_VEX_0F73
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8802 { REG_TABLE (REG_VEX_0FAE
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8829 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8841 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9171 { REG_TABLE (REG_VEX_0F38F3
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9263 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9439 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9459 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9479 #define NEED_OPCODE_TABLE
9480 #include "i386-dis-evex.h"
9481 #undef NEED_OPCODE_TABLE
9482 static const struct dis386 vex_len_table
[][2] = {
9483 /* VEX_LEN_0F10_P_1 */
9485 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9486 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9489 /* VEX_LEN_0F10_P_3 */
9491 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9492 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9495 /* VEX_LEN_0F11_P_1 */
9497 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9498 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9501 /* VEX_LEN_0F11_P_3 */
9503 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9504 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9507 /* VEX_LEN_0F12_P_0_M_0 */
9509 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9512 /* VEX_LEN_0F12_P_0_M_1 */
9514 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9517 /* VEX_LEN_0F12_P_2 */
9519 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9522 /* VEX_LEN_0F13_M_0 */
9524 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9527 /* VEX_LEN_0F16_P_0_M_0 */
9529 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9532 /* VEX_LEN_0F16_P_0_M_1 */
9534 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9537 /* VEX_LEN_0F16_P_2 */
9539 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9542 /* VEX_LEN_0F17_M_0 */
9544 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9547 /* VEX_LEN_0F2A_P_1 */
9549 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9550 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9553 /* VEX_LEN_0F2A_P_3 */
9555 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9556 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9559 /* VEX_LEN_0F2C_P_1 */
9561 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9562 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9565 /* VEX_LEN_0F2C_P_3 */
9567 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9568 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9571 /* VEX_LEN_0F2D_P_1 */
9573 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9574 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9577 /* VEX_LEN_0F2D_P_3 */
9579 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9580 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9583 /* VEX_LEN_0F2E_P_0 */
9585 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9586 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9589 /* VEX_LEN_0F2E_P_2 */
9591 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9592 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9595 /* VEX_LEN_0F2F_P_0 */
9597 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9598 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9601 /* VEX_LEN_0F2F_P_2 */
9603 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9604 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9607 /* VEX_LEN_0F41_P_0 */
9610 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9612 /* VEX_LEN_0F41_P_2 */
9615 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9617 /* VEX_LEN_0F42_P_0 */
9620 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9622 /* VEX_LEN_0F42_P_2 */
9625 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9627 /* VEX_LEN_0F44_P_0 */
9629 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9631 /* VEX_LEN_0F44_P_2 */
9633 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9635 /* VEX_LEN_0F45_P_0 */
9638 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9640 /* VEX_LEN_0F45_P_2 */
9643 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9645 /* VEX_LEN_0F46_P_0 */
9648 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9650 /* VEX_LEN_0F46_P_2 */
9653 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9655 /* VEX_LEN_0F47_P_0 */
9658 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9660 /* VEX_LEN_0F47_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9665 /* VEX_LEN_0F4A_P_0 */
9668 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9670 /* VEX_LEN_0F4A_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9675 /* VEX_LEN_0F4B_P_0 */
9678 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9680 /* VEX_LEN_0F4B_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9686 /* VEX_LEN_0F51_P_1 */
9688 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9689 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9692 /* VEX_LEN_0F51_P_3 */
9694 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9695 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9698 /* VEX_LEN_0F52_P_1 */
9700 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9701 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9704 /* VEX_LEN_0F53_P_1 */
9706 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9707 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9710 /* VEX_LEN_0F58_P_1 */
9712 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9713 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9716 /* VEX_LEN_0F58_P_3 */
9718 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9719 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9722 /* VEX_LEN_0F59_P_1 */
9724 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9725 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9728 /* VEX_LEN_0F59_P_3 */
9730 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9731 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9734 /* VEX_LEN_0F5A_P_1 */
9736 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9737 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9740 /* VEX_LEN_0F5A_P_3 */
9742 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9743 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9746 /* VEX_LEN_0F5C_P_1 */
9748 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9749 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9752 /* VEX_LEN_0F5C_P_3 */
9754 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9755 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9758 /* VEX_LEN_0F5D_P_1 */
9760 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9761 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9764 /* VEX_LEN_0F5D_P_3 */
9766 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9767 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9770 /* VEX_LEN_0F5E_P_1 */
9772 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9773 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9776 /* VEX_LEN_0F5E_P_3 */
9778 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9779 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9782 /* VEX_LEN_0F5F_P_1 */
9784 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9785 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9788 /* VEX_LEN_0F5F_P_3 */
9790 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9791 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9794 /* VEX_LEN_0F6E_P_2 */
9796 { "vmovK", { XMScalar
, Edq
}, 0 },
9797 { "vmovK", { XMScalar
, Edq
}, 0 },
9800 /* VEX_LEN_0F7E_P_1 */
9802 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9803 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9806 /* VEX_LEN_0F7E_P_2 */
9808 { "vmovK", { Edq
, XMScalar
}, 0 },
9809 { "vmovK", { Edq
, XMScalar
}, 0 },
9812 /* VEX_LEN_0F90_P_0 */
9814 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9817 /* VEX_LEN_0F90_P_2 */
9819 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9822 /* VEX_LEN_0F91_P_0 */
9824 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9827 /* VEX_LEN_0F91_P_2 */
9829 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9832 /* VEX_LEN_0F92_P_0 */
9834 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9837 /* VEX_LEN_0F92_P_2 */
9839 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9842 /* VEX_LEN_0F92_P_3 */
9844 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9847 /* VEX_LEN_0F93_P_0 */
9849 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9852 /* VEX_LEN_0F93_P_2 */
9854 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9857 /* VEX_LEN_0F93_P_3 */
9859 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9862 /* VEX_LEN_0F98_P_0 */
9864 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9867 /* VEX_LEN_0F98_P_2 */
9869 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9872 /* VEX_LEN_0F99_P_0 */
9874 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9877 /* VEX_LEN_0F99_P_2 */
9879 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9882 /* VEX_LEN_0FAE_R_2_M_0 */
9884 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9887 /* VEX_LEN_0FAE_R_3_M_0 */
9889 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9892 /* VEX_LEN_0FC2_P_1 */
9894 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9895 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9898 /* VEX_LEN_0FC2_P_3 */
9900 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9901 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9904 /* VEX_LEN_0FC4_P_2 */
9906 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9909 /* VEX_LEN_0FC5_P_2 */
9911 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9914 /* VEX_LEN_0FD6_P_2 */
9916 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9917 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9920 /* VEX_LEN_0FF7_P_2 */
9922 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9925 /* VEX_LEN_0F3816_P_2 */
9928 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9931 /* VEX_LEN_0F3819_P_2 */
9934 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9937 /* VEX_LEN_0F381A_P_2_M_0 */
9940 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9943 /* VEX_LEN_0F3836_P_2 */
9946 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9949 /* VEX_LEN_0F3841_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9954 /* VEX_LEN_0F385A_P_2_M_0 */
9957 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9960 /* VEX_LEN_0F38DB_P_2 */
9962 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9965 /* VEX_LEN_0F38DC_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9970 /* VEX_LEN_0F38DD_P_2 */
9972 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9975 /* VEX_LEN_0F38DE_P_2 */
9977 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9980 /* VEX_LEN_0F38DF_P_2 */
9982 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9985 /* VEX_LEN_0F38F2_P_0 */
9987 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9990 /* VEX_LEN_0F38F3_R_1_P_0 */
9992 { "blsrS", { VexGdq
, Edq
}, 0 },
9995 /* VEX_LEN_0F38F3_R_2_P_0 */
9997 { "blsmskS", { VexGdq
, Edq
}, 0 },
10000 /* VEX_LEN_0F38F3_R_3_P_0 */
10002 { "blsiS", { VexGdq
, Edq
}, 0 },
10005 /* VEX_LEN_0F38F5_P_0 */
10007 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10010 /* VEX_LEN_0F38F5_P_1 */
10012 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10015 /* VEX_LEN_0F38F5_P_3 */
10017 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10020 /* VEX_LEN_0F38F6_P_3 */
10022 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10025 /* VEX_LEN_0F38F7_P_0 */
10027 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10030 /* VEX_LEN_0F38F7_P_1 */
10032 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10035 /* VEX_LEN_0F38F7_P_2 */
10037 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10040 /* VEX_LEN_0F38F7_P_3 */
10042 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10045 /* VEX_LEN_0F3A00_P_2 */
10048 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10051 /* VEX_LEN_0F3A01_P_2 */
10054 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10057 /* VEX_LEN_0F3A06_P_2 */
10060 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10063 /* VEX_LEN_0F3A0A_P_2 */
10065 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10066 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10069 /* VEX_LEN_0F3A0B_P_2 */
10071 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10072 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10075 /* VEX_LEN_0F3A14_P_2 */
10077 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10080 /* VEX_LEN_0F3A15_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10085 /* VEX_LEN_0F3A16_P_2 */
10087 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10090 /* VEX_LEN_0F3A17_P_2 */
10092 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10095 /* VEX_LEN_0F3A18_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10101 /* VEX_LEN_0F3A19_P_2 */
10104 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10107 /* VEX_LEN_0F3A20_P_2 */
10109 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10112 /* VEX_LEN_0F3A21_P_2 */
10114 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10117 /* VEX_LEN_0F3A22_P_2 */
10119 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10122 /* VEX_LEN_0F3A30_P_2 */
10124 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10127 /* VEX_LEN_0F3A31_P_2 */
10129 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10132 /* VEX_LEN_0F3A32_P_2 */
10134 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10137 /* VEX_LEN_0F3A33_P_2 */
10139 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10142 /* VEX_LEN_0F3A38_P_2 */
10145 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10148 /* VEX_LEN_0F3A39_P_2 */
10151 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10154 /* VEX_LEN_0F3A41_P_2 */
10156 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10159 /* VEX_LEN_0F3A44_P_2 */
10161 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10164 /* VEX_LEN_0F3A46_P_2 */
10167 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10170 /* VEX_LEN_0F3A60_P_2 */
10172 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10175 /* VEX_LEN_0F3A61_P_2 */
10177 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10180 /* VEX_LEN_0F3A62_P_2 */
10182 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10185 /* VEX_LEN_0F3A63_P_2 */
10187 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10190 /* VEX_LEN_0F3A6A_P_2 */
10192 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10195 /* VEX_LEN_0F3A6B_P_2 */
10197 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10200 /* VEX_LEN_0F3A6E_P_2 */
10202 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10205 /* VEX_LEN_0F3A6F_P_2 */
10207 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10210 /* VEX_LEN_0F3A7A_P_2 */
10212 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10215 /* VEX_LEN_0F3A7B_P_2 */
10217 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10220 /* VEX_LEN_0F3A7E_P_2 */
10222 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10225 /* VEX_LEN_0F3A7F_P_2 */
10227 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10230 /* VEX_LEN_0F3ADF_P_2 */
10232 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10235 /* VEX_LEN_0F3AF0_P_3 */
10237 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10240 /* VEX_LEN_0FXOP_08_CC */
10242 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10245 /* VEX_LEN_0FXOP_08_CD */
10247 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10250 /* VEX_LEN_0FXOP_08_CE */
10252 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10255 /* VEX_LEN_0FXOP_08_CF */
10257 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10260 /* VEX_LEN_0FXOP_08_EC */
10262 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10265 /* VEX_LEN_0FXOP_08_ED */
10267 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10270 /* VEX_LEN_0FXOP_08_EE */
10272 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10275 /* VEX_LEN_0FXOP_08_EF */
10277 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10280 /* VEX_LEN_0FXOP_09_80 */
10282 { "vfrczps", { XM
, EXxmm
}, 0 },
10283 { "vfrczps", { XM
, EXymmq
}, 0 },
10286 /* VEX_LEN_0FXOP_09_81 */
10288 { "vfrczpd", { XM
, EXxmm
}, 0 },
10289 { "vfrczpd", { XM
, EXymmq
}, 0 },
10293 static const struct dis386 vex_w_table
[][2] = {
10295 /* VEX_W_0F10_P_0 */
10296 { "vmovups", { XM
, EXx
}, 0 },
10299 /* VEX_W_0F10_P_1 */
10300 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10303 /* VEX_W_0F10_P_2 */
10304 { "vmovupd", { XM
, EXx
}, 0 },
10307 /* VEX_W_0F10_P_3 */
10308 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10311 /* VEX_W_0F11_P_0 */
10312 { "vmovups", { EXxS
, XM
}, 0 },
10315 /* VEX_W_0F11_P_1 */
10316 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10319 /* VEX_W_0F11_P_2 */
10320 { "vmovupd", { EXxS
, XM
}, 0 },
10323 /* VEX_W_0F11_P_3 */
10324 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10327 /* VEX_W_0F12_P_0_M_0 */
10328 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10331 /* VEX_W_0F12_P_0_M_1 */
10332 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10335 /* VEX_W_0F12_P_1 */
10336 { "vmovsldup", { XM
, EXx
}, 0 },
10339 /* VEX_W_0F12_P_2 */
10340 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10343 /* VEX_W_0F12_P_3 */
10344 { "vmovddup", { XM
, EXymmq
}, 0 },
10347 /* VEX_W_0F13_M_0 */
10348 { "vmovlpX", { EXq
, XM
}, 0 },
10352 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10356 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10359 /* VEX_W_0F16_P_0_M_0 */
10360 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10363 /* VEX_W_0F16_P_0_M_1 */
10364 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10367 /* VEX_W_0F16_P_1 */
10368 { "vmovshdup", { XM
, EXx
}, 0 },
10371 /* VEX_W_0F16_P_2 */
10372 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10375 /* VEX_W_0F17_M_0 */
10376 { "vmovhpX", { EXq
, XM
}, 0 },
10380 { "vmovapX", { XM
, EXx
}, 0 },
10384 { "vmovapX", { EXxS
, XM
}, 0 },
10387 /* VEX_W_0F2B_M_0 */
10388 { "vmovntpX", { Mx
, XM
}, 0 },
10391 /* VEX_W_0F2E_P_0 */
10392 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10395 /* VEX_W_0F2E_P_2 */
10396 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10399 /* VEX_W_0F2F_P_0 */
10400 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10403 /* VEX_W_0F2F_P_2 */
10404 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10407 /* VEX_W_0F41_P_0_LEN_1 */
10408 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10409 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10412 /* VEX_W_0F41_P_2_LEN_1 */
10413 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10414 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10417 /* VEX_W_0F42_P_0_LEN_1 */
10418 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10419 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10422 /* VEX_W_0F42_P_2_LEN_1 */
10423 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10424 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10427 /* VEX_W_0F44_P_0_LEN_0 */
10428 { "knotw", { MaskG
, MaskR
}, 0 },
10429 { "knotq", { MaskG
, MaskR
}, 0 },
10432 /* VEX_W_0F44_P_2_LEN_0 */
10433 { "knotb", { MaskG
, MaskR
}, 0 },
10434 { "knotd", { MaskG
, MaskR
}, 0 },
10437 /* VEX_W_0F45_P_0_LEN_1 */
10438 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10439 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10442 /* VEX_W_0F45_P_2_LEN_1 */
10443 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10444 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10447 /* VEX_W_0F46_P_0_LEN_1 */
10448 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10449 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10452 /* VEX_W_0F46_P_2_LEN_1 */
10453 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10454 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10457 /* VEX_W_0F47_P_0_LEN_1 */
10458 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10459 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10462 /* VEX_W_0F47_P_2_LEN_1 */
10463 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10464 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10467 /* VEX_W_0F4A_P_0_LEN_1 */
10468 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10469 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10472 /* VEX_W_0F4A_P_2_LEN_1 */
10473 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10474 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10477 /* VEX_W_0F4B_P_0_LEN_1 */
10478 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10479 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10482 /* VEX_W_0F4B_P_2_LEN_1 */
10483 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10486 /* VEX_W_0F50_M_0 */
10487 { "vmovmskpX", { Gdq
, XS
}, 0 },
10490 /* VEX_W_0F51_P_0 */
10491 { "vsqrtps", { XM
, EXx
}, 0 },
10494 /* VEX_W_0F51_P_1 */
10495 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10498 /* VEX_W_0F51_P_2 */
10499 { "vsqrtpd", { XM
, EXx
}, 0 },
10502 /* VEX_W_0F51_P_3 */
10503 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10506 /* VEX_W_0F52_P_0 */
10507 { "vrsqrtps", { XM
, EXx
}, 0 },
10510 /* VEX_W_0F52_P_1 */
10511 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10514 /* VEX_W_0F53_P_0 */
10515 { "vrcpps", { XM
, EXx
}, 0 },
10518 /* VEX_W_0F53_P_1 */
10519 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10522 /* VEX_W_0F58_P_0 */
10523 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10526 /* VEX_W_0F58_P_1 */
10527 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10530 /* VEX_W_0F58_P_2 */
10531 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10534 /* VEX_W_0F58_P_3 */
10535 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10538 /* VEX_W_0F59_P_0 */
10539 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10542 /* VEX_W_0F59_P_1 */
10543 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10546 /* VEX_W_0F59_P_2 */
10547 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10550 /* VEX_W_0F59_P_3 */
10551 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10554 /* VEX_W_0F5A_P_0 */
10555 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10558 /* VEX_W_0F5A_P_1 */
10559 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10562 /* VEX_W_0F5A_P_3 */
10563 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10566 /* VEX_W_0F5B_P_0 */
10567 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10570 /* VEX_W_0F5B_P_1 */
10571 { "vcvttps2dq", { XM
, EXx
}, 0 },
10574 /* VEX_W_0F5B_P_2 */
10575 { "vcvtps2dq", { XM
, EXx
}, 0 },
10578 /* VEX_W_0F5C_P_0 */
10579 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10582 /* VEX_W_0F5C_P_1 */
10583 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10586 /* VEX_W_0F5C_P_2 */
10587 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10590 /* VEX_W_0F5C_P_3 */
10591 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10594 /* VEX_W_0F5D_P_0 */
10595 { "vminps", { XM
, Vex
, EXx
}, 0 },
10598 /* VEX_W_0F5D_P_1 */
10599 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10602 /* VEX_W_0F5D_P_2 */
10603 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10606 /* VEX_W_0F5D_P_3 */
10607 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10610 /* VEX_W_0F5E_P_0 */
10611 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10614 /* VEX_W_0F5E_P_1 */
10615 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10618 /* VEX_W_0F5E_P_2 */
10619 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10622 /* VEX_W_0F5E_P_3 */
10623 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10626 /* VEX_W_0F5F_P_0 */
10627 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10630 /* VEX_W_0F5F_P_1 */
10631 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10634 /* VEX_W_0F5F_P_2 */
10635 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10638 /* VEX_W_0F5F_P_3 */
10639 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10642 /* VEX_W_0F60_P_2 */
10643 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10646 /* VEX_W_0F61_P_2 */
10647 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10650 /* VEX_W_0F62_P_2 */
10651 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10654 /* VEX_W_0F63_P_2 */
10655 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10658 /* VEX_W_0F64_P_2 */
10659 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10662 /* VEX_W_0F65_P_2 */
10663 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10666 /* VEX_W_0F66_P_2 */
10667 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10670 /* VEX_W_0F67_P_2 */
10671 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10674 /* VEX_W_0F68_P_2 */
10675 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10678 /* VEX_W_0F69_P_2 */
10679 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10682 /* VEX_W_0F6A_P_2 */
10683 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10686 /* VEX_W_0F6B_P_2 */
10687 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10690 /* VEX_W_0F6C_P_2 */
10691 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10694 /* VEX_W_0F6D_P_2 */
10695 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10698 /* VEX_W_0F6F_P_1 */
10699 { "vmovdqu", { XM
, EXx
}, 0 },
10702 /* VEX_W_0F6F_P_2 */
10703 { "vmovdqa", { XM
, EXx
}, 0 },
10706 /* VEX_W_0F70_P_1 */
10707 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10710 /* VEX_W_0F70_P_2 */
10711 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10714 /* VEX_W_0F70_P_3 */
10715 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10718 /* VEX_W_0F71_R_2_P_2 */
10719 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10722 /* VEX_W_0F71_R_4_P_2 */
10723 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10726 /* VEX_W_0F71_R_6_P_2 */
10727 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10730 /* VEX_W_0F72_R_2_P_2 */
10731 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10734 /* VEX_W_0F72_R_4_P_2 */
10735 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10738 /* VEX_W_0F72_R_6_P_2 */
10739 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10742 /* VEX_W_0F73_R_2_P_2 */
10743 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10746 /* VEX_W_0F73_R_3_P_2 */
10747 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10750 /* VEX_W_0F73_R_6_P_2 */
10751 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10754 /* VEX_W_0F73_R_7_P_2 */
10755 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10758 /* VEX_W_0F74_P_2 */
10759 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10762 /* VEX_W_0F75_P_2 */
10763 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10766 /* VEX_W_0F76_P_2 */
10767 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10770 /* VEX_W_0F77_P_0 */
10771 { "", { VZERO
}, 0 },
10774 /* VEX_W_0F7C_P_2 */
10775 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10778 /* VEX_W_0F7C_P_3 */
10779 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10782 /* VEX_W_0F7D_P_2 */
10783 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10786 /* VEX_W_0F7D_P_3 */
10787 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10790 /* VEX_W_0F7E_P_1 */
10791 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10794 /* VEX_W_0F7F_P_1 */
10795 { "vmovdqu", { EXxS
, XM
}, 0 },
10798 /* VEX_W_0F7F_P_2 */
10799 { "vmovdqa", { EXxS
, XM
}, 0 },
10802 /* VEX_W_0F90_P_0_LEN_0 */
10803 { "kmovw", { MaskG
, MaskE
}, 0 },
10804 { "kmovq", { MaskG
, MaskE
}, 0 },
10807 /* VEX_W_0F90_P_2_LEN_0 */
10808 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10809 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10812 /* VEX_W_0F91_P_0_LEN_0 */
10813 { "kmovw", { Ew
, MaskG
}, 0 },
10814 { "kmovq", { Eq
, MaskG
}, 0 },
10817 /* VEX_W_0F91_P_2_LEN_0 */
10818 { "kmovb", { Eb
, MaskG
}, 0 },
10819 { "kmovd", { Ed
, MaskG
}, 0 },
10822 /* VEX_W_0F92_P_0_LEN_0 */
10823 { "kmovw", { MaskG
, Rdq
}, 0 },
10826 /* VEX_W_0F92_P_2_LEN_0 */
10827 { "kmovb", { MaskG
, Rdq
}, 0 },
10830 /* VEX_W_0F92_P_3_LEN_0 */
10831 { "kmovd", { MaskG
, Rdq
}, 0 },
10832 { "kmovq", { MaskG
, Rdq
}, 0 },
10835 /* VEX_W_0F93_P_0_LEN_0 */
10836 { "kmovw", { Gdq
, MaskR
}, 0 },
10839 /* VEX_W_0F93_P_2_LEN_0 */
10840 { "kmovb", { Gdq
, MaskR
}, 0 },
10843 /* VEX_W_0F93_P_3_LEN_0 */
10844 { "kmovd", { Gdq
, MaskR
}, 0 },
10845 { "kmovq", { Gdq
, MaskR
}, 0 },
10848 /* VEX_W_0F98_P_0_LEN_0 */
10849 { "kortestw", { MaskG
, MaskR
}, 0 },
10850 { "kortestq", { MaskG
, MaskR
}, 0 },
10853 /* VEX_W_0F98_P_2_LEN_0 */
10854 { "kortestb", { MaskG
, MaskR
}, 0 },
10855 { "kortestd", { MaskG
, MaskR
}, 0 },
10858 /* VEX_W_0F99_P_0_LEN_0 */
10859 { "ktestw", { MaskG
, MaskR
}, 0 },
10860 { "ktestq", { MaskG
, MaskR
}, 0 },
10863 /* VEX_W_0F99_P_2_LEN_0 */
10864 { "ktestb", { MaskG
, MaskR
}, 0 },
10865 { "ktestd", { MaskG
, MaskR
}, 0 },
10868 /* VEX_W_0FAE_R_2_M_0 */
10869 { "vldmxcsr", { Md
}, 0 },
10872 /* VEX_W_0FAE_R_3_M_0 */
10873 { "vstmxcsr", { Md
}, 0 },
10876 /* VEX_W_0FC2_P_0 */
10877 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10880 /* VEX_W_0FC2_P_1 */
10881 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10884 /* VEX_W_0FC2_P_2 */
10885 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10888 /* VEX_W_0FC2_P_3 */
10889 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10892 /* VEX_W_0FC4_P_2 */
10893 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10896 /* VEX_W_0FC5_P_2 */
10897 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10900 /* VEX_W_0FD0_P_2 */
10901 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0FD0_P_3 */
10905 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0FD1_P_2 */
10909 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10912 /* VEX_W_0FD2_P_2 */
10913 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10916 /* VEX_W_0FD3_P_2 */
10917 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10920 /* VEX_W_0FD4_P_2 */
10921 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10924 /* VEX_W_0FD5_P_2 */
10925 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10928 /* VEX_W_0FD6_P_2 */
10929 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10932 /* VEX_W_0FD7_P_2_M_1 */
10933 { "vpmovmskb", { Gdq
, XS
}, 0 },
10936 /* VEX_W_0FD8_P_2 */
10937 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10940 /* VEX_W_0FD9_P_2 */
10941 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10944 /* VEX_W_0FDA_P_2 */
10945 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10948 /* VEX_W_0FDB_P_2 */
10949 { "vpand", { XM
, Vex
, EXx
}, 0 },
10952 /* VEX_W_0FDC_P_2 */
10953 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10956 /* VEX_W_0FDD_P_2 */
10957 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10960 /* VEX_W_0FDE_P_2 */
10961 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10964 /* VEX_W_0FDF_P_2 */
10965 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10968 /* VEX_W_0FE0_P_2 */
10969 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10972 /* VEX_W_0FE1_P_2 */
10973 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10976 /* VEX_W_0FE2_P_2 */
10977 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10980 /* VEX_W_0FE3_P_2 */
10981 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0FE4_P_2 */
10985 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10988 /* VEX_W_0FE5_P_2 */
10989 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10992 /* VEX_W_0FE6_P_1 */
10993 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10996 /* VEX_W_0FE6_P_2 */
10997 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11000 /* VEX_W_0FE6_P_3 */
11001 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11004 /* VEX_W_0FE7_P_2_M_0 */
11005 { "vmovntdq", { Mx
, XM
}, 0 },
11008 /* VEX_W_0FE8_P_2 */
11009 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11012 /* VEX_W_0FE9_P_2 */
11013 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11016 /* VEX_W_0FEA_P_2 */
11017 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11020 /* VEX_W_0FEB_P_2 */
11021 { "vpor", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0FEC_P_2 */
11025 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0FED_P_2 */
11029 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11032 /* VEX_W_0FEE_P_2 */
11033 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11036 /* VEX_W_0FEF_P_2 */
11037 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11040 /* VEX_W_0FF0_P_3_M_0 */
11041 { "vlddqu", { XM
, M
}, 0 },
11044 /* VEX_W_0FF1_P_2 */
11045 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11048 /* VEX_W_0FF2_P_2 */
11049 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11052 /* VEX_W_0FF3_P_2 */
11053 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11056 /* VEX_W_0FF4_P_2 */
11057 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0FF5_P_2 */
11061 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0FF6_P_2 */
11065 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11068 /* VEX_W_0FF7_P_2 */
11069 { "vmaskmovdqu", { XM
, XS
}, 0 },
11072 /* VEX_W_0FF8_P_2 */
11073 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11076 /* VEX_W_0FF9_P_2 */
11077 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11080 /* VEX_W_0FFA_P_2 */
11081 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11084 /* VEX_W_0FFB_P_2 */
11085 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11088 /* VEX_W_0FFC_P_2 */
11089 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11092 /* VEX_W_0FFD_P_2 */
11093 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11096 /* VEX_W_0FFE_P_2 */
11097 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11100 /* VEX_W_0F3800_P_2 */
11101 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11104 /* VEX_W_0F3801_P_2 */
11105 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11108 /* VEX_W_0F3802_P_2 */
11109 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11112 /* VEX_W_0F3803_P_2 */
11113 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0F3804_P_2 */
11117 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0F3805_P_2 */
11121 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11124 /* VEX_W_0F3806_P_2 */
11125 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0F3807_P_2 */
11129 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11132 /* VEX_W_0F3808_P_2 */
11133 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11136 /* VEX_W_0F3809_P_2 */
11137 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11140 /* VEX_W_0F380A_P_2 */
11141 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11144 /* VEX_W_0F380B_P_2 */
11145 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11148 /* VEX_W_0F380C_P_2 */
11149 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11152 /* VEX_W_0F380D_P_2 */
11153 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11156 /* VEX_W_0F380E_P_2 */
11157 { "vtestps", { XM
, EXx
}, 0 },
11160 /* VEX_W_0F380F_P_2 */
11161 { "vtestpd", { XM
, EXx
}, 0 },
11164 /* VEX_W_0F3816_P_2 */
11165 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11168 /* VEX_W_0F3817_P_2 */
11169 { "vptest", { XM
, EXx
}, 0 },
11172 /* VEX_W_0F3818_P_2 */
11173 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11176 /* VEX_W_0F3819_P_2 */
11177 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11180 /* VEX_W_0F381A_P_2_M_0 */
11181 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11184 /* VEX_W_0F381C_P_2 */
11185 { "vpabsb", { XM
, EXx
}, 0 },
11188 /* VEX_W_0F381D_P_2 */
11189 { "vpabsw", { XM
, EXx
}, 0 },
11192 /* VEX_W_0F381E_P_2 */
11193 { "vpabsd", { XM
, EXx
}, 0 },
11196 /* VEX_W_0F3820_P_2 */
11197 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11200 /* VEX_W_0F3821_P_2 */
11201 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11204 /* VEX_W_0F3822_P_2 */
11205 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11208 /* VEX_W_0F3823_P_2 */
11209 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11212 /* VEX_W_0F3824_P_2 */
11213 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11216 /* VEX_W_0F3825_P_2 */
11217 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11220 /* VEX_W_0F3828_P_2 */
11221 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11224 /* VEX_W_0F3829_P_2 */
11225 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11228 /* VEX_W_0F382A_P_2_M_0 */
11229 { "vmovntdqa", { XM
, Mx
}, 0 },
11232 /* VEX_W_0F382B_P_2 */
11233 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11236 /* VEX_W_0F382C_P_2_M_0 */
11237 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11240 /* VEX_W_0F382D_P_2_M_0 */
11241 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11244 /* VEX_W_0F382E_P_2_M_0 */
11245 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11248 /* VEX_W_0F382F_P_2_M_0 */
11249 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11252 /* VEX_W_0F3830_P_2 */
11253 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11256 /* VEX_W_0F3831_P_2 */
11257 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11260 /* VEX_W_0F3832_P_2 */
11261 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11264 /* VEX_W_0F3833_P_2 */
11265 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11268 /* VEX_W_0F3834_P_2 */
11269 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11272 /* VEX_W_0F3835_P_2 */
11273 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11276 /* VEX_W_0F3836_P_2 */
11277 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11280 /* VEX_W_0F3837_P_2 */
11281 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11284 /* VEX_W_0F3838_P_2 */
11285 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11288 /* VEX_W_0F3839_P_2 */
11289 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11292 /* VEX_W_0F383A_P_2 */
11293 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11296 /* VEX_W_0F383B_P_2 */
11297 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11300 /* VEX_W_0F383C_P_2 */
11301 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11304 /* VEX_W_0F383D_P_2 */
11305 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11308 /* VEX_W_0F383E_P_2 */
11309 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11312 /* VEX_W_0F383F_P_2 */
11313 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11316 /* VEX_W_0F3840_P_2 */
11317 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11320 /* VEX_W_0F3841_P_2 */
11321 { "vphminposuw", { XM
, EXx
}, 0 },
11324 /* VEX_W_0F3846_P_2 */
11325 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11328 /* VEX_W_0F3858_P_2 */
11329 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11332 /* VEX_W_0F3859_P_2 */
11333 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11336 /* VEX_W_0F385A_P_2_M_0 */
11337 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11340 /* VEX_W_0F3878_P_2 */
11341 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11344 /* VEX_W_0F3879_P_2 */
11345 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11348 /* VEX_W_0F38DB_P_2 */
11349 { "vaesimc", { XM
, EXx
}, 0 },
11352 /* VEX_W_0F38DC_P_2 */
11353 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11356 /* VEX_W_0F38DD_P_2 */
11357 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11360 /* VEX_W_0F38DE_P_2 */
11361 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11364 /* VEX_W_0F38DF_P_2 */
11365 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11368 /* VEX_W_0F3A00_P_2 */
11370 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11373 /* VEX_W_0F3A01_P_2 */
11375 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11378 /* VEX_W_0F3A02_P_2 */
11379 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11382 /* VEX_W_0F3A04_P_2 */
11383 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11386 /* VEX_W_0F3A05_P_2 */
11387 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11390 /* VEX_W_0F3A06_P_2 */
11391 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11394 /* VEX_W_0F3A08_P_2 */
11395 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11398 /* VEX_W_0F3A09_P_2 */
11399 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11402 /* VEX_W_0F3A0A_P_2 */
11403 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11406 /* VEX_W_0F3A0B_P_2 */
11407 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11410 /* VEX_W_0F3A0C_P_2 */
11411 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11414 /* VEX_W_0F3A0D_P_2 */
11415 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11418 /* VEX_W_0F3A0E_P_2 */
11419 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11422 /* VEX_W_0F3A0F_P_2 */
11423 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11426 /* VEX_W_0F3A14_P_2 */
11427 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11430 /* VEX_W_0F3A15_P_2 */
11431 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11434 /* VEX_W_0F3A18_P_2 */
11435 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11438 /* VEX_W_0F3A19_P_2 */
11439 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11442 /* VEX_W_0F3A20_P_2 */
11443 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11446 /* VEX_W_0F3A21_P_2 */
11447 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11450 /* VEX_W_0F3A30_P_2_LEN_0 */
11451 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11452 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11455 /* VEX_W_0F3A31_P_2_LEN_0 */
11456 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11457 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11460 /* VEX_W_0F3A32_P_2_LEN_0 */
11461 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11462 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11465 /* VEX_W_0F3A33_P_2_LEN_0 */
11466 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11467 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11470 /* VEX_W_0F3A38_P_2 */
11471 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11474 /* VEX_W_0F3A39_P_2 */
11475 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11478 /* VEX_W_0F3A40_P_2 */
11479 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11482 /* VEX_W_0F3A41_P_2 */
11483 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11486 /* VEX_W_0F3A42_P_2 */
11487 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11490 /* VEX_W_0F3A44_P_2 */
11491 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11494 /* VEX_W_0F3A46_P_2 */
11495 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11498 /* VEX_W_0F3A48_P_2 */
11499 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11500 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11503 /* VEX_W_0F3A49_P_2 */
11504 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11505 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11508 /* VEX_W_0F3A4A_P_2 */
11509 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11512 /* VEX_W_0F3A4B_P_2 */
11513 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11516 /* VEX_W_0F3A4C_P_2 */
11517 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11520 /* VEX_W_0F3A60_P_2 */
11521 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11524 /* VEX_W_0F3A61_P_2 */
11525 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11528 /* VEX_W_0F3A62_P_2 */
11529 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11532 /* VEX_W_0F3A63_P_2 */
11533 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11536 /* VEX_W_0F3ADF_P_2 */
11537 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11539 #define NEED_VEX_W_TABLE
11540 #include "i386-dis-evex.h"
11541 #undef NEED_VEX_W_TABLE
11544 static const struct dis386 mod_table
[][2] = {
11547 { "leaS", { Gv
, M
}, 0 },
11552 { RM_TABLE (RM_C6_REG_7
) },
11557 { RM_TABLE (RM_C7_REG_7
) },
11561 { "Jcall{T|}", { indirEp
}, 0 },
11565 { "Jjmp{T|}", { indirEp
}, 0 },
11568 /* MOD_0F01_REG_0 */
11569 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11570 { RM_TABLE (RM_0F01_REG_0
) },
11573 /* MOD_0F01_REG_1 */
11574 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11575 { RM_TABLE (RM_0F01_REG_1
) },
11578 /* MOD_0F01_REG_2 */
11579 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11580 { RM_TABLE (RM_0F01_REG_2
) },
11583 /* MOD_0F01_REG_3 */
11584 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11585 { RM_TABLE (RM_0F01_REG_3
) },
11588 /* MOD_0F01_REG_7 */
11589 { "invlpg", { Mb
}, 0 },
11590 { RM_TABLE (RM_0F01_REG_7
) },
11593 /* MOD_0F12_PREFIX_0 */
11594 { "movlps", { XM
, EXq
}, PREFIX_MANDATORY
},
11595 { "movhlps", { XM
, EXq
}, PREFIX_MANDATORY
},
11599 { "movlpX", { EXq
, XM
}, PREFIX_MANDATORY
},
11602 /* MOD_0F16_PREFIX_0 */
11603 { "movhps", { XM
, EXq
}, 0 },
11604 { "movlhps", { XM
, EXq
}, 0 },
11608 { "movhpX", { EXq
, XM
}, PREFIX_MANDATORY
},
11611 /* MOD_0F18_REG_0 */
11612 { "prefetchnta", { Mb
}, 0 },
11615 /* MOD_0F18_REG_1 */
11616 { "prefetcht0", { Mb
}, 0 },
11619 /* MOD_0F18_REG_2 */
11620 { "prefetcht1", { Mb
}, 0 },
11623 /* MOD_0F18_REG_3 */
11624 { "prefetcht2", { Mb
}, 0 },
11627 /* MOD_0F18_REG_4 */
11628 { "nop/reserved", { Mb
}, 0 },
11631 /* MOD_0F18_REG_5 */
11632 { "nop/reserved", { Mb
}, 0 },
11635 /* MOD_0F18_REG_6 */
11636 { "nop/reserved", { Mb
}, 0 },
11639 /* MOD_0F18_REG_7 */
11640 { "nop/reserved", { Mb
}, 0 },
11643 /* MOD_0F1A_PREFIX_0 */
11644 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11645 { "nopQ", { Ev
}, 0 },
11648 /* MOD_0F1B_PREFIX_0 */
11649 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11650 { "nopQ", { Ev
}, 0 },
11653 /* MOD_0F1B_PREFIX_1 */
11654 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11655 { "nopQ", { Ev
}, 0 },
11660 { "movL", { Rd
, Td
}, 0 },
11665 { "movL", { Td
, Rd
}, 0 },
11668 /* MOD_0F2B_PREFIX_0 */
11669 {"movntps", { Mx
, XM
}, PREFIX_MANDATORY
},
11672 /* MOD_0F2B_PREFIX_1 */
11673 {"movntss", { Md
, XM
}, PREFIX_MANDATORY
},
11676 /* MOD_0F2B_PREFIX_2 */
11677 {"movntpd", { Mx
, XM
}, PREFIX_MANDATORY
},
11680 /* MOD_0F2B_PREFIX_3 */
11681 {"movntsd", { Mq
, XM
}, PREFIX_MANDATORY
},
11686 { "movmskpX", { Gdq
, XS
}, PREFIX_MANDATORY
},
11689 /* MOD_0F71_REG_2 */
11691 { "psrlw", { MS
, Ib
}, 0 },
11694 /* MOD_0F71_REG_4 */
11696 { "psraw", { MS
, Ib
}, 0 },
11699 /* MOD_0F71_REG_6 */
11701 { "psllw", { MS
, Ib
}, 0 },
11704 /* MOD_0F72_REG_2 */
11706 { "psrld", { MS
, Ib
}, 0 },
11709 /* MOD_0F72_REG_4 */
11711 { "psrad", { MS
, Ib
}, 0 },
11714 /* MOD_0F72_REG_6 */
11716 { "pslld", { MS
, Ib
}, 0 },
11719 /* MOD_0F73_REG_2 */
11721 { "psrlq", { MS
, Ib
}, 0 },
11724 /* MOD_0F73_REG_3 */
11726 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11729 /* MOD_0F73_REG_6 */
11731 { "psllq", { MS
, Ib
}, 0 },
11734 /* MOD_0F73_REG_7 */
11736 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11739 /* MOD_0FAE_REG_0 */
11740 { "fxsave", { FXSAVE
}, 0 },
11741 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11744 /* MOD_0FAE_REG_1 */
11745 { "fxrstor", { FXSAVE
}, 0 },
11746 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11749 /* MOD_0FAE_REG_2 */
11750 { "ldmxcsr", { Md
}, 0 },
11751 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11754 /* MOD_0FAE_REG_3 */
11755 { "stmxcsr", { Md
}, 0 },
11756 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11759 /* MOD_0FAE_REG_4 */
11760 { "xsave", { FXSAVE
}, 0 },
11763 /* MOD_0FAE_REG_5 */
11764 { "xrstor", { FXSAVE
}, 0 },
11765 { RM_TABLE (RM_0FAE_REG_5
) },
11768 /* MOD_0FAE_REG_6 */
11769 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11770 { RM_TABLE (RM_0FAE_REG_6
) },
11773 /* MOD_0FAE_REG_7 */
11774 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11775 { RM_TABLE (RM_0FAE_REG_7
) },
11779 { "lssS", { Gv
, Mp
}, 0 },
11783 { "lfsS", { Gv
, Mp
}, 0 },
11787 { "lgsS", { Gv
, Mp
}, 0 },
11790 /* MOD_0FC7_REG_3 */
11791 { "xrstors", { FXSAVE
}, 0 },
11794 /* MOD_0FC7_REG_4 */
11795 { "xsavec", { FXSAVE
}, 0 },
11798 /* MOD_0FC7_REG_5 */
11799 { "xsaves", { FXSAVE
}, 0 },
11802 /* MOD_0FC7_REG_6 */
11803 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11804 { "rdrand", { Ev
}, 0 },
11807 /* MOD_0FC7_REG_7 */
11808 { "vmptrst", { Mq
}, 0 },
11809 { "rdseed", { Ev
}, 0 },
11814 { "pmovmskb", { Gdq
, MS
}, 0 },
11817 /* MOD_0FE7_PREFIX_2 */
11818 { "movntdq", { Mx
, XM
}, 0 },
11821 /* MOD_0FF0_PREFIX_3 */
11822 { "lddqu", { XM
, M
}, 0 },
11825 /* MOD_0F382A_PREFIX_2 */
11826 { "movntdqa", { XM
, Mx
}, 0 },
11830 { "bound{S|}", { Gv
, Ma
}, 0 },
11831 { EVEX_TABLE (EVEX_0F
) },
11835 { "lesS", { Gv
, Mp
}, 0 },
11836 { VEX_C4_TABLE (VEX_0F
) },
11840 { "ldsS", { Gv
, Mp
}, 0 },
11841 { VEX_C5_TABLE (VEX_0F
) },
11844 /* MOD_VEX_0F12_PREFIX_0 */
11845 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11846 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11850 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11853 /* MOD_VEX_0F16_PREFIX_0 */
11854 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11855 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11859 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11863 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11868 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11871 /* MOD_VEX_0F71_REG_2 */
11873 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11876 /* MOD_VEX_0F71_REG_4 */
11878 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11881 /* MOD_VEX_0F71_REG_6 */
11883 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11886 /* MOD_VEX_0F72_REG_2 */
11888 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11891 /* MOD_VEX_0F72_REG_4 */
11893 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11896 /* MOD_VEX_0F72_REG_6 */
11898 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11901 /* MOD_VEX_0F73_REG_2 */
11903 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11906 /* MOD_VEX_0F73_REG_3 */
11908 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11911 /* MOD_VEX_0F73_REG_6 */
11913 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11916 /* MOD_VEX_0F73_REG_7 */
11918 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11921 /* MOD_VEX_0FAE_REG_2 */
11922 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11925 /* MOD_VEX_0FAE_REG_3 */
11926 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11929 /* MOD_VEX_0FD7_PREFIX_2 */
11931 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11934 /* MOD_VEX_0FE7_PREFIX_2 */
11935 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11938 /* MOD_VEX_0FF0_PREFIX_3 */
11939 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11942 /* MOD_VEX_0F381A_PREFIX_2 */
11943 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11946 /* MOD_VEX_0F382A_PREFIX_2 */
11947 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11950 /* MOD_VEX_0F382C_PREFIX_2 */
11951 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11954 /* MOD_VEX_0F382D_PREFIX_2 */
11955 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11958 /* MOD_VEX_0F382E_PREFIX_2 */
11959 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11962 /* MOD_VEX_0F382F_PREFIX_2 */
11963 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11966 /* MOD_VEX_0F385A_PREFIX_2 */
11967 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11970 /* MOD_VEX_0F388C_PREFIX_2 */
11971 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
11974 /* MOD_VEX_0F388E_PREFIX_2 */
11975 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
11977 #define NEED_MOD_TABLE
11978 #include "i386-dis-evex.h"
11979 #undef NEED_MOD_TABLE
11982 static const struct dis386 rm_table
[][8] = {
11985 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11989 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
11992 /* RM_0F01_REG_0 */
11994 { "vmcall", { Skip_MODRM
}, 0 },
11995 { "vmlaunch", { Skip_MODRM
}, 0 },
11996 { "vmresume", { Skip_MODRM
}, 0 },
11997 { "vmxoff", { Skip_MODRM
}, 0 },
12000 /* RM_0F01_REG_1 */
12001 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12002 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12003 { "clac", { Skip_MODRM
}, 0 },
12004 { "stac", { Skip_MODRM
}, 0 },
12008 { "encls", { Skip_MODRM
}, 0 },
12011 /* RM_0F01_REG_2 */
12012 { "xgetbv", { Skip_MODRM
}, 0 },
12013 { "xsetbv", { Skip_MODRM
}, 0 },
12016 { "vmfunc", { Skip_MODRM
}, 0 },
12017 { "xend", { Skip_MODRM
}, 0 },
12018 { "xtest", { Skip_MODRM
}, 0 },
12019 { "enclu", { Skip_MODRM
}, 0 },
12022 /* RM_0F01_REG_3 */
12023 { "vmrun", { Skip_MODRM
}, 0 },
12024 { "vmmcall", { Skip_MODRM
}, 0 },
12025 { "vmload", { Skip_MODRM
}, 0 },
12026 { "vmsave", { Skip_MODRM
}, 0 },
12027 { "stgi", { Skip_MODRM
}, 0 },
12028 { "clgi", { Skip_MODRM
}, 0 },
12029 { "skinit", { Skip_MODRM
}, 0 },
12030 { "invlpga", { Skip_MODRM
}, 0 },
12033 /* RM_0F01_REG_7 */
12034 { "swapgs", { Skip_MODRM
}, 0 },
12035 { "rdtscp", { Skip_MODRM
}, 0 },
12038 { "clzero", { Skip_MODRM
}, 0 },
12041 /* RM_0FAE_REG_5 */
12042 { "lfence", { Skip_MODRM
}, 0 },
12045 /* RM_0FAE_REG_6 */
12046 { "mfence", { Skip_MODRM
}, 0 },
12049 /* RM_0FAE_REG_7 */
12050 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12054 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12056 /* We use the high bit to indicate different name for the same
12058 #define REP_PREFIX (0xf3 | 0x100)
12059 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12060 #define XRELEASE_PREFIX (0xf3 | 0x400)
12061 #define BND_PREFIX (0xf2 | 0x400)
12066 int newrex
, i
, length
;
12072 last_lock_prefix
= -1;
12073 last_repz_prefix
= -1;
12074 last_repnz_prefix
= -1;
12075 last_data_prefix
= -1;
12076 last_addr_prefix
= -1;
12077 last_rex_prefix
= -1;
12078 last_seg_prefix
= -1;
12080 active_seg_prefix
= 0;
12081 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12082 all_prefixes
[i
] = 0;
12085 /* The maximum instruction length is 15bytes. */
12086 while (length
< MAX_CODE_LENGTH
- 1)
12088 FETCH_DATA (the_info
, codep
+ 1);
12092 /* REX prefixes family. */
12109 if (address_mode
== mode_64bit
)
12113 last_rex_prefix
= i
;
12116 prefixes
|= PREFIX_REPZ
;
12117 last_repz_prefix
= i
;
12120 prefixes
|= PREFIX_REPNZ
;
12121 last_repnz_prefix
= i
;
12124 prefixes
|= PREFIX_LOCK
;
12125 last_lock_prefix
= i
;
12128 prefixes
|= PREFIX_CS
;
12129 last_seg_prefix
= i
;
12130 active_seg_prefix
= PREFIX_CS
;
12133 prefixes
|= PREFIX_SS
;
12134 last_seg_prefix
= i
;
12135 active_seg_prefix
= PREFIX_SS
;
12138 prefixes
|= PREFIX_DS
;
12139 last_seg_prefix
= i
;
12140 active_seg_prefix
= PREFIX_DS
;
12143 prefixes
|= PREFIX_ES
;
12144 last_seg_prefix
= i
;
12145 active_seg_prefix
= PREFIX_ES
;
12148 prefixes
|= PREFIX_FS
;
12149 last_seg_prefix
= i
;
12150 active_seg_prefix
= PREFIX_FS
;
12153 prefixes
|= PREFIX_GS
;
12154 last_seg_prefix
= i
;
12155 active_seg_prefix
= PREFIX_GS
;
12158 prefixes
|= PREFIX_DATA
;
12159 last_data_prefix
= i
;
12162 prefixes
|= PREFIX_ADDR
;
12163 last_addr_prefix
= i
;
12166 /* fwait is really an instruction. If there are prefixes
12167 before the fwait, they belong to the fwait, *not* to the
12168 following instruction. */
12170 if (prefixes
|| rex
)
12172 prefixes
|= PREFIX_FWAIT
;
12174 /* This ensures that the previous REX prefixes are noticed
12175 as unused prefixes, as in the return case below. */
12179 prefixes
= PREFIX_FWAIT
;
12184 /* Rex is ignored when followed by another prefix. */
12190 if (*codep
!= FWAIT_OPCODE
)
12191 all_prefixes
[i
++] = *codep
;
12199 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12202 static const char *
12203 prefix_name (int pref
, int sizeflag
)
12205 static const char *rexes
[16] =
12208 "rex.B", /* 0x41 */
12209 "rex.X", /* 0x42 */
12210 "rex.XB", /* 0x43 */
12211 "rex.R", /* 0x44 */
12212 "rex.RB", /* 0x45 */
12213 "rex.RX", /* 0x46 */
12214 "rex.RXB", /* 0x47 */
12215 "rex.W", /* 0x48 */
12216 "rex.WB", /* 0x49 */
12217 "rex.WX", /* 0x4a */
12218 "rex.WXB", /* 0x4b */
12219 "rex.WR", /* 0x4c */
12220 "rex.WRB", /* 0x4d */
12221 "rex.WRX", /* 0x4e */
12222 "rex.WRXB", /* 0x4f */
12227 /* REX prefixes family. */
12244 return rexes
[pref
- 0x40];
12264 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12266 if (address_mode
== mode_64bit
)
12267 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12269 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12274 case XACQUIRE_PREFIX
:
12276 case XRELEASE_PREFIX
:
12285 static char op_out
[MAX_OPERANDS
][100];
12286 static int op_ad
, op_index
[MAX_OPERANDS
];
12287 static int two_source_ops
;
12288 static bfd_vma op_address
[MAX_OPERANDS
];
12289 static bfd_vma op_riprel
[MAX_OPERANDS
];
12290 static bfd_vma start_pc
;
12293 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12294 * (see topic "Redundant prefixes" in the "Differences from 8086"
12295 * section of the "Virtual 8086 Mode" chapter.)
12296 * 'pc' should be the address of this instruction, it will
12297 * be used to print the target address if this is a relative jump or call
12298 * The function returns the length of this instruction in bytes.
12301 static char intel_syntax
;
12302 static char intel_mnemonic
= !SYSV386_COMPAT
;
12303 static char open_char
;
12304 static char close_char
;
12305 static char separator_char
;
12306 static char scale_char
;
12308 /* Here for backwards compatibility. When gdb stops using
12309 print_insn_i386_att and print_insn_i386_intel these functions can
12310 disappear, and print_insn_i386 be merged into print_insn. */
12312 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12316 return print_insn (pc
, info
);
12320 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12324 return print_insn (pc
, info
);
12328 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12332 return print_insn (pc
, info
);
12336 print_i386_disassembler_options (FILE *stream
)
12338 fprintf (stream
, _("\n\
12339 The following i386/x86-64 specific disassembler options are supported for use\n\
12340 with the -M switch (multiple options should be separated by commas):\n"));
12342 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12343 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12344 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12345 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12346 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12347 fprintf (stream
, _(" att-mnemonic\n"
12348 " Display instruction in AT&T mnemonic\n"));
12349 fprintf (stream
, _(" intel-mnemonic\n"
12350 " Display instruction in Intel mnemonic\n"));
12351 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12352 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12353 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12354 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12355 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12356 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12360 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12362 /* Get a pointer to struct dis386 with a valid name. */
12364 static const struct dis386
*
12365 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12367 int vindex
, vex_table_index
;
12369 if (dp
->name
!= NULL
)
12372 switch (dp
->op
[0].bytemode
)
12374 case USE_REG_TABLE
:
12375 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12378 case USE_MOD_TABLE
:
12379 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12380 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12384 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12387 case USE_PREFIX_TABLE
:
12390 /* The prefix in VEX is implicit. */
12391 switch (vex
.prefix
)
12396 case REPE_PREFIX_OPCODE
:
12399 case DATA_PREFIX_OPCODE
:
12402 case REPNE_PREFIX_OPCODE
:
12412 int last_prefix
= -1;
12415 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12416 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12418 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12420 if (last_repz_prefix
> last_repnz_prefix
)
12423 prefix
= PREFIX_REPZ
;
12424 last_prefix
= last_repz_prefix
;
12429 prefix
= PREFIX_REPNZ
;
12430 last_prefix
= last_repnz_prefix
;
12433 /* Ignore the invalid index if it isn't mandatory. */
12434 if (!mandatory_prefix
12435 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].name
12437 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].op
[0].bytemode
12442 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12445 prefix
= PREFIX_DATA
;
12446 last_prefix
= last_data_prefix
;
12451 used_prefixes
|= prefix
;
12452 all_prefixes
[last_prefix
] = 0;
12455 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12458 case USE_X86_64_TABLE
:
12459 vindex
= address_mode
== mode_64bit
? 1 : 0;
12460 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12463 case USE_3BYTE_TABLE
:
12464 FETCH_DATA (info
, codep
+ 2);
12466 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12468 modrm
.mod
= (*codep
>> 6) & 3;
12469 modrm
.reg
= (*codep
>> 3) & 7;
12470 modrm
.rm
= *codep
& 7;
12473 case USE_VEX_LEN_TABLE
:
12477 switch (vex
.length
)
12490 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12493 case USE_XOP_8F_TABLE
:
12494 FETCH_DATA (info
, codep
+ 3);
12495 /* All bits in the REX prefix are ignored. */
12497 rex
= ~(*codep
>> 5) & 0x7;
12499 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12500 switch ((*codep
& 0x1f))
12506 vex_table_index
= XOP_08
;
12509 vex_table_index
= XOP_09
;
12512 vex_table_index
= XOP_0A
;
12516 vex
.w
= *codep
& 0x80;
12517 if (vex
.w
&& address_mode
== mode_64bit
)
12520 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12521 if (address_mode
!= mode_64bit
12522 && vex
.register_specifier
> 0x7)
12528 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12529 switch ((*codep
& 0x3))
12535 vex
.prefix
= DATA_PREFIX_OPCODE
;
12538 vex
.prefix
= REPE_PREFIX_OPCODE
;
12541 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12548 dp
= &xop_table
[vex_table_index
][vindex
];
12551 FETCH_DATA (info
, codep
+ 1);
12552 modrm
.mod
= (*codep
>> 6) & 3;
12553 modrm
.reg
= (*codep
>> 3) & 7;
12554 modrm
.rm
= *codep
& 7;
12557 case USE_VEX_C4_TABLE
:
12559 FETCH_DATA (info
, codep
+ 3);
12560 /* All bits in the REX prefix are ignored. */
12562 rex
= ~(*codep
>> 5) & 0x7;
12563 switch ((*codep
& 0x1f))
12569 vex_table_index
= VEX_0F
;
12572 vex_table_index
= VEX_0F38
;
12575 vex_table_index
= VEX_0F3A
;
12579 vex
.w
= *codep
& 0x80;
12580 if (vex
.w
&& address_mode
== mode_64bit
)
12583 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12584 if (address_mode
!= mode_64bit
12585 && vex
.register_specifier
> 0x7)
12591 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12592 switch ((*codep
& 0x3))
12598 vex
.prefix
= DATA_PREFIX_OPCODE
;
12601 vex
.prefix
= REPE_PREFIX_OPCODE
;
12604 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12611 dp
= &vex_table
[vex_table_index
][vindex
];
12613 /* There is no MODRM byte for VEX [82|77]. */
12614 if (vindex
!= 0x77 && vindex
!= 0x82)
12616 FETCH_DATA (info
, codep
+ 1);
12617 modrm
.mod
= (*codep
>> 6) & 3;
12618 modrm
.reg
= (*codep
>> 3) & 7;
12619 modrm
.rm
= *codep
& 7;
12623 case USE_VEX_C5_TABLE
:
12625 FETCH_DATA (info
, codep
+ 2);
12626 /* All bits in the REX prefix are ignored. */
12628 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12630 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12631 if (address_mode
!= mode_64bit
12632 && vex
.register_specifier
> 0x7)
12640 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12641 switch ((*codep
& 0x3))
12647 vex
.prefix
= DATA_PREFIX_OPCODE
;
12650 vex
.prefix
= REPE_PREFIX_OPCODE
;
12653 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12660 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12662 /* There is no MODRM byte for VEX [82|77]. */
12663 if (vindex
!= 0x77 && vindex
!= 0x82)
12665 FETCH_DATA (info
, codep
+ 1);
12666 modrm
.mod
= (*codep
>> 6) & 3;
12667 modrm
.reg
= (*codep
>> 3) & 7;
12668 modrm
.rm
= *codep
& 7;
12672 case USE_VEX_W_TABLE
:
12676 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12679 case USE_EVEX_TABLE
:
12680 two_source_ops
= 0;
12683 FETCH_DATA (info
, codep
+ 4);
12684 /* All bits in the REX prefix are ignored. */
12686 /* The first byte after 0x62. */
12687 rex
= ~(*codep
>> 5) & 0x7;
12688 vex
.r
= *codep
& 0x10;
12689 switch ((*codep
& 0xf))
12692 return &bad_opcode
;
12694 vex_table_index
= EVEX_0F
;
12697 vex_table_index
= EVEX_0F38
;
12700 vex_table_index
= EVEX_0F3A
;
12704 /* The second byte after 0x62. */
12706 vex
.w
= *codep
& 0x80;
12707 if (vex
.w
&& address_mode
== mode_64bit
)
12710 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12711 if (address_mode
!= mode_64bit
)
12713 /* In 16/32-bit mode silently ignore following bits. */
12717 vex
.register_specifier
&= 0x7;
12721 if (!(*codep
& 0x4))
12722 return &bad_opcode
;
12724 switch ((*codep
& 0x3))
12730 vex
.prefix
= DATA_PREFIX_OPCODE
;
12733 vex
.prefix
= REPE_PREFIX_OPCODE
;
12736 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12740 /* The third byte after 0x62. */
12743 /* Remember the static rounding bits. */
12744 vex
.ll
= (*codep
>> 5) & 3;
12745 vex
.b
= (*codep
& 0x10) != 0;
12747 vex
.v
= *codep
& 0x8;
12748 vex
.mask_register_specifier
= *codep
& 0x7;
12749 vex
.zeroing
= *codep
& 0x80;
12755 dp
= &evex_table
[vex_table_index
][vindex
];
12757 FETCH_DATA (info
, codep
+ 1);
12758 modrm
.mod
= (*codep
>> 6) & 3;
12759 modrm
.reg
= (*codep
>> 3) & 7;
12760 modrm
.rm
= *codep
& 7;
12762 /* Set vector length. */
12763 if (modrm
.mod
== 3 && vex
.b
)
12779 return &bad_opcode
;
12792 if (dp
->name
!= NULL
)
12795 return get_valid_dis386 (dp
, info
);
12799 get_sib (disassemble_info
*info
, int sizeflag
)
12801 /* If modrm.mod == 3, operand must be register. */
12803 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12807 FETCH_DATA (info
, codep
+ 2);
12808 sib
.index
= (codep
[1] >> 3) & 7;
12809 sib
.scale
= (codep
[1] >> 6) & 3;
12810 sib
.base
= codep
[1] & 7;
12815 print_insn (bfd_vma pc
, disassemble_info
*info
)
12817 const struct dis386
*dp
;
12819 char *op_txt
[MAX_OPERANDS
];
12821 int sizeflag
, orig_sizeflag
;
12823 struct dis_private priv
;
12826 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12827 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12828 address_mode
= mode_32bit
;
12829 else if (info
->mach
== bfd_mach_i386_i8086
)
12831 address_mode
= mode_16bit
;
12832 priv
.orig_sizeflag
= 0;
12835 address_mode
= mode_64bit
;
12837 if (intel_syntax
== (char) -1)
12838 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12840 for (p
= info
->disassembler_options
; p
!= NULL
; )
12842 if (CONST_STRNEQ (p
, "x86-64"))
12844 address_mode
= mode_64bit
;
12845 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12847 else if (CONST_STRNEQ (p
, "i386"))
12849 address_mode
= mode_32bit
;
12850 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12852 else if (CONST_STRNEQ (p
, "i8086"))
12854 address_mode
= mode_16bit
;
12855 priv
.orig_sizeflag
= 0;
12857 else if (CONST_STRNEQ (p
, "intel"))
12860 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12861 intel_mnemonic
= 1;
12863 else if (CONST_STRNEQ (p
, "att"))
12866 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12867 intel_mnemonic
= 0;
12869 else if (CONST_STRNEQ (p
, "addr"))
12871 if (address_mode
== mode_64bit
)
12873 if (p
[4] == '3' && p
[5] == '2')
12874 priv
.orig_sizeflag
&= ~AFLAG
;
12875 else if (p
[4] == '6' && p
[5] == '4')
12876 priv
.orig_sizeflag
|= AFLAG
;
12880 if (p
[4] == '1' && p
[5] == '6')
12881 priv
.orig_sizeflag
&= ~AFLAG
;
12882 else if (p
[4] == '3' && p
[5] == '2')
12883 priv
.orig_sizeflag
|= AFLAG
;
12886 else if (CONST_STRNEQ (p
, "data"))
12888 if (p
[4] == '1' && p
[5] == '6')
12889 priv
.orig_sizeflag
&= ~DFLAG
;
12890 else if (p
[4] == '3' && p
[5] == '2')
12891 priv
.orig_sizeflag
|= DFLAG
;
12893 else if (CONST_STRNEQ (p
, "suffix"))
12894 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12896 p
= strchr (p
, ',');
12903 names64
= intel_names64
;
12904 names32
= intel_names32
;
12905 names16
= intel_names16
;
12906 names8
= intel_names8
;
12907 names8rex
= intel_names8rex
;
12908 names_seg
= intel_names_seg
;
12909 names_mm
= intel_names_mm
;
12910 names_bnd
= intel_names_bnd
;
12911 names_xmm
= intel_names_xmm
;
12912 names_ymm
= intel_names_ymm
;
12913 names_zmm
= intel_names_zmm
;
12914 index64
= intel_index64
;
12915 index32
= intel_index32
;
12916 names_mask
= intel_names_mask
;
12917 index16
= intel_index16
;
12920 separator_char
= '+';
12925 names64
= att_names64
;
12926 names32
= att_names32
;
12927 names16
= att_names16
;
12928 names8
= att_names8
;
12929 names8rex
= att_names8rex
;
12930 names_seg
= att_names_seg
;
12931 names_mm
= att_names_mm
;
12932 names_bnd
= att_names_bnd
;
12933 names_xmm
= att_names_xmm
;
12934 names_ymm
= att_names_ymm
;
12935 names_zmm
= att_names_zmm
;
12936 index64
= att_index64
;
12937 index32
= att_index32
;
12938 names_mask
= att_names_mask
;
12939 index16
= att_index16
;
12942 separator_char
= ',';
12946 /* The output looks better if we put 7 bytes on a line, since that
12947 puts most long word instructions on a single line. Use 8 bytes
12949 if ((info
->mach
& bfd_mach_l1om
) != 0)
12950 info
->bytes_per_line
= 8;
12952 info
->bytes_per_line
= 7;
12954 info
->private_data
= &priv
;
12955 priv
.max_fetched
= priv
.the_buffer
;
12956 priv
.insn_start
= pc
;
12959 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12967 start_codep
= priv
.the_buffer
;
12968 codep
= priv
.the_buffer
;
12970 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12974 /* Getting here means we tried for data but didn't get it. That
12975 means we have an incomplete instruction of some sort. Just
12976 print the first byte as a prefix or a .byte pseudo-op. */
12977 if (codep
> priv
.the_buffer
)
12979 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12981 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12984 /* Just print the first byte as a .byte instruction. */
12985 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12986 (unsigned int) priv
.the_buffer
[0]);
12996 sizeflag
= priv
.orig_sizeflag
;
12998 if (!ckprefix () || rex_used
)
13000 /* Too many prefixes or unused REX prefixes. */
13002 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13004 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13006 prefix_name (all_prefixes
[i
], sizeflag
));
13010 insn_codep
= codep
;
13012 FETCH_DATA (info
, codep
+ 1);
13013 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13015 if (((prefixes
& PREFIX_FWAIT
)
13016 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13018 /* Handle prefixes before fwait. */
13019 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13021 (*info
->fprintf_func
) (info
->stream
, "%s ",
13022 prefix_name (all_prefixes
[i
], sizeflag
));
13023 (*info
->fprintf_func
) (info
->stream
, "fwait");
13027 if (*codep
== 0x0f)
13029 unsigned char threebyte
;
13030 FETCH_DATA (info
, codep
+ 2);
13031 threebyte
= *++codep
;
13032 dp
= &dis386_twobyte
[threebyte
];
13033 need_modrm
= twobyte_has_modrm
[*codep
];
13034 mandatory_prefix
= dp
->prefix_requirement
;
13039 dp
= &dis386
[*codep
];
13040 need_modrm
= onebyte_has_modrm
[*codep
];
13041 mandatory_prefix
= 0;
13045 /* Save sizeflag for printing the extra prefixes later before updating
13046 it for mnemonic and operand processing. The prefix names depend
13047 only on the address mode. */
13048 orig_sizeflag
= sizeflag
;
13049 if (prefixes
& PREFIX_ADDR
)
13051 if ((prefixes
& PREFIX_DATA
))
13057 FETCH_DATA (info
, codep
+ 1);
13058 modrm
.mod
= (*codep
>> 6) & 3;
13059 modrm
.reg
= (*codep
>> 3) & 7;
13060 modrm
.rm
= *codep
& 7;
13068 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13070 get_sib (info
, sizeflag
);
13071 dofloat (sizeflag
);
13075 dp
= get_valid_dis386 (dp
, info
);
13076 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13078 get_sib (info
, sizeflag
);
13079 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13082 op_ad
= MAX_OPERANDS
- 1 - i
;
13084 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13085 /* For EVEX instruction after the last operand masking
13086 should be printed. */
13087 if (i
== 0 && vex
.evex
)
13089 /* Don't print {%k0}. */
13090 if (vex
.mask_register_specifier
)
13093 oappend (names_mask
[vex
.mask_register_specifier
]);
13103 /* Check if the REX prefix is used. */
13104 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13105 all_prefixes
[last_rex_prefix
] = 0;
13107 /* Check if the SEG prefix is used. */
13108 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13109 | PREFIX_FS
| PREFIX_GS
)) != 0
13110 && (used_prefixes
& active_seg_prefix
) != 0)
13111 all_prefixes
[last_seg_prefix
] = 0;
13113 /* Check if the ADDR prefix is used. */
13114 if ((prefixes
& PREFIX_ADDR
) != 0
13115 && (used_prefixes
& PREFIX_ADDR
) != 0)
13116 all_prefixes
[last_addr_prefix
] = 0;
13118 /* Check if the DATA prefix is used. */
13119 if ((prefixes
& PREFIX_DATA
) != 0
13120 && (used_prefixes
& PREFIX_DATA
) != 0)
13121 all_prefixes
[last_data_prefix
] = 0;
13123 /* Print the extra prefixes. */
13125 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13126 if (all_prefixes
[i
])
13129 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13132 prefix_length
+= strlen (name
) + 1;
13133 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13136 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13137 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13138 used by putop and MMX/SSE operand and may be overriden by the
13139 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13141 /* TODO we should check which prefix is mandatory. */
13142 if (mandatory_prefix
13143 && dp
!= &bad_opcode
13145 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13147 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13149 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13151 && (used_prefixes
& PREFIX_DATA
) == 0))))
13153 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13154 return end_codep
- priv
.the_buffer
;
13157 /* Check maximum code length. */
13158 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13160 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13161 return MAX_CODE_LENGTH
;
13164 obufp
= mnemonicendp
;
13165 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13168 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13170 /* The enter and bound instructions are printed with operands in the same
13171 order as the intel book; everything else is printed in reverse order. */
13172 if (intel_syntax
|| two_source_ops
)
13176 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13177 op_txt
[i
] = op_out
[i
];
13179 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13181 op_ad
= op_index
[i
];
13182 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13183 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13184 riprel
= op_riprel
[i
];
13185 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13186 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13191 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13192 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13196 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13200 (*info
->fprintf_func
) (info
->stream
, ",");
13201 if (op_index
[i
] != -1 && !op_riprel
[i
])
13202 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13204 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13208 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13209 if (op_index
[i
] != -1 && op_riprel
[i
])
13211 (*info
->fprintf_func
) (info
->stream
, " # ");
13212 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13213 + op_address
[op_index
[i
]]), info
);
13216 return codep
- priv
.the_buffer
;
13219 static const char *float_mem
[] = {
13294 static const unsigned char float_mem_mode
[] = {
13369 #define ST { OP_ST, 0 }
13370 #define STi { OP_STi, 0 }
13372 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13373 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13374 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13375 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13376 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13377 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13378 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13379 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13380 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13382 static const struct dis386 float_reg
[][8] = {
13385 { "fadd", { ST
, STi
}, 0 },
13386 { "fmul", { ST
, STi
}, 0 },
13387 { "fcom", { STi
}, 0 },
13388 { "fcomp", { STi
}, 0 },
13389 { "fsub", { ST
, STi
}, 0 },
13390 { "fsubr", { ST
, STi
}, 0 },
13391 { "fdiv", { ST
, STi
}, 0 },
13392 { "fdivr", { ST
, STi
}, 0 },
13396 { "fld", { STi
}, 0 },
13397 { "fxch", { STi
}, 0 },
13407 { "fcmovb", { ST
, STi
}, 0 },
13408 { "fcmove", { ST
, STi
}, 0 },
13409 { "fcmovbe",{ ST
, STi
}, 0 },
13410 { "fcmovu", { ST
, STi
}, 0 },
13418 { "fcmovnb",{ ST
, STi
}, 0 },
13419 { "fcmovne",{ ST
, STi
}, 0 },
13420 { "fcmovnbe",{ ST
, STi
}, 0 },
13421 { "fcmovnu",{ ST
, STi
}, 0 },
13423 { "fucomi", { ST
, STi
}, 0 },
13424 { "fcomi", { ST
, STi
}, 0 },
13429 { "fadd", { STi
, ST
}, 0 },
13430 { "fmul", { STi
, ST
}, 0 },
13433 { "fsub!M", { STi
, ST
}, 0 },
13434 { "fsubM", { STi
, ST
}, 0 },
13435 { "fdiv!M", { STi
, ST
}, 0 },
13436 { "fdivM", { STi
, ST
}, 0 },
13440 { "ffree", { STi
}, 0 },
13442 { "fst", { STi
}, 0 },
13443 { "fstp", { STi
}, 0 },
13444 { "fucom", { STi
}, 0 },
13445 { "fucomp", { STi
}, 0 },
13451 { "faddp", { STi
, ST
}, 0 },
13452 { "fmulp", { STi
, ST
}, 0 },
13455 { "fsub!Mp", { STi
, ST
}, 0 },
13456 { "fsubMp", { STi
, ST
}, 0 },
13457 { "fdiv!Mp", { STi
, ST
}, 0 },
13458 { "fdivMp", { STi
, ST
}, 0 },
13462 { "ffreep", { STi
}, 0 },
13467 { "fucomip", { ST
, STi
}, 0 },
13468 { "fcomip", { ST
, STi
}, 0 },
13473 static char *fgrps
[][8] = {
13476 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13481 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13486 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13491 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13496 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13501 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13506 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13507 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13512 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13517 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13522 swap_operand (void)
13524 mnemonicendp
[0] = '.';
13525 mnemonicendp
[1] = 's';
13530 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13531 int sizeflag ATTRIBUTE_UNUSED
)
13533 /* Skip mod/rm byte. */
13539 dofloat (int sizeflag
)
13541 const struct dis386
*dp
;
13542 unsigned char floatop
;
13544 floatop
= codep
[-1];
13546 if (modrm
.mod
!= 3)
13548 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13550 putop (float_mem
[fp_indx
], sizeflag
);
13553 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13556 /* Skip mod/rm byte. */
13560 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13561 if (dp
->name
== NULL
)
13563 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13565 /* Instruction fnstsw is only one with strange arg. */
13566 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13567 strcpy (op_out
[0], names16
[0]);
13571 putop (dp
->name
, sizeflag
);
13576 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13581 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13585 /* Like oappend (below), but S is a string starting with '%'.
13586 In Intel syntax, the '%' is elided. */
13588 oappend_maybe_intel (const char *s
)
13590 oappend (s
+ intel_syntax
);
13594 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13596 oappend_maybe_intel ("%st");
13600 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13602 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13603 oappend_maybe_intel (scratchbuf
);
13606 /* Capital letters in template are macros. */
13608 putop (const char *in_template
, int sizeflag
)
13613 unsigned int l
= 0, len
= 1;
13616 #define SAVE_LAST(c) \
13617 if (l < len && l < sizeof (last)) \
13622 for (p
= in_template
; *p
; p
++)
13639 while (*++p
!= '|')
13640 if (*p
== '}' || *p
== '\0')
13643 /* Fall through. */
13648 while (*++p
!= '}')
13659 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13663 if (l
== 0 && len
== 1)
13668 if (sizeflag
& SUFFIX_ALWAYS
)
13681 if (address_mode
== mode_64bit
13682 && !(prefixes
& PREFIX_ADDR
))
13693 if (intel_syntax
&& !alt
)
13695 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13697 if (sizeflag
& DFLAG
)
13698 *obufp
++ = intel_syntax
? 'd' : 'l';
13700 *obufp
++ = intel_syntax
? 'w' : 's';
13701 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13705 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13708 if (modrm
.mod
== 3)
13714 if (sizeflag
& DFLAG
)
13715 *obufp
++ = intel_syntax
? 'd' : 'l';
13718 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13724 case 'E': /* For jcxz/jecxz */
13725 if (address_mode
== mode_64bit
)
13727 if (sizeflag
& AFLAG
)
13733 if (sizeflag
& AFLAG
)
13735 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13740 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13742 if (sizeflag
& AFLAG
)
13743 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13745 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13746 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13750 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13752 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13756 if (!(rex
& REX_W
))
13757 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13762 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13763 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13765 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13768 if (prefixes
& PREFIX_DS
)
13789 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13794 /* Fall through. */
13797 if (l
!= 0 || len
!= 1)
13805 if (sizeflag
& SUFFIX_ALWAYS
)
13809 if (intel_mnemonic
!= cond
)
13813 if ((prefixes
& PREFIX_FWAIT
) == 0)
13816 used_prefixes
|= PREFIX_FWAIT
;
13822 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13826 if (!(rex
& REX_W
))
13827 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13831 && address_mode
== mode_64bit
13832 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13837 /* Fall through. */
13840 if (l
== 0 && len
== 1)
13845 if ((rex
& REX_W
) == 0
13846 && (prefixes
& PREFIX_DATA
))
13848 if ((sizeflag
& DFLAG
) == 0)
13850 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13854 if ((prefixes
& PREFIX_DATA
)
13856 || (sizeflag
& SUFFIX_ALWAYS
))
13863 if (sizeflag
& DFLAG
)
13867 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13873 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13879 if ((prefixes
& PREFIX_DATA
)
13881 || (sizeflag
& SUFFIX_ALWAYS
))
13888 if (sizeflag
& DFLAG
)
13889 *obufp
++ = intel_syntax
? 'd' : 'l';
13892 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13900 if (address_mode
== mode_64bit
13901 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13903 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13907 /* Fall through. */
13910 if (l
== 0 && len
== 1)
13913 if (intel_syntax
&& !alt
)
13916 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13922 if (sizeflag
& DFLAG
)
13923 *obufp
++ = intel_syntax
? 'd' : 'l';
13926 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13932 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13938 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13953 else if (sizeflag
& DFLAG
)
13962 if (intel_syntax
&& !p
[1]
13963 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13965 if (!(rex
& REX_W
))
13966 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13969 if (l
== 0 && len
== 1)
13973 if (address_mode
== mode_64bit
13974 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13976 if (sizeflag
& SUFFIX_ALWAYS
)
13998 /* Fall through. */
14001 if (l
== 0 && len
== 1)
14006 if (sizeflag
& SUFFIX_ALWAYS
)
14012 if (sizeflag
& DFLAG
)
14016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14030 if (address_mode
== mode_64bit
14031 && !(prefixes
& PREFIX_ADDR
))
14042 if (l
!= 0 || len
!= 1)
14047 if (need_vex
&& vex
.prefix
)
14049 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14056 if (prefixes
& PREFIX_DATA
)
14060 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14064 if (l
== 0 && len
== 1)
14066 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14077 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14085 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14087 switch (vex
.length
)
14101 if (l
== 0 && len
== 1)
14103 /* operand size flag for cwtl, cbtw */
14112 else if (sizeflag
& DFLAG
)
14116 if (!(rex
& REX_W
))
14117 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14124 && last
[0] != 'L'))
14131 if (last
[0] == 'X')
14132 *obufp
++ = vex
.w
? 'd': 's';
14134 *obufp
++ = vex
.w
? 'q': 'd';
14141 mnemonicendp
= obufp
;
14146 oappend (const char *s
)
14148 obufp
= stpcpy (obufp
, s
);
14154 /* Only print the active segment register. */
14155 if (!active_seg_prefix
)
14158 used_prefixes
|= active_seg_prefix
;
14159 switch (active_seg_prefix
)
14162 oappend_maybe_intel ("%cs:");
14165 oappend_maybe_intel ("%ds:");
14168 oappend_maybe_intel ("%ss:");
14171 oappend_maybe_intel ("%es:");
14174 oappend_maybe_intel ("%fs:");
14177 oappend_maybe_intel ("%gs:");
14185 OP_indirE (int bytemode
, int sizeflag
)
14189 OP_E (bytemode
, sizeflag
);
14193 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14195 if (address_mode
== mode_64bit
)
14203 sprintf_vma (tmp
, disp
);
14204 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14205 strcpy (buf
+ 2, tmp
+ i
);
14209 bfd_signed_vma v
= disp
;
14216 /* Check for possible overflow on 0x8000000000000000. */
14219 strcpy (buf
, "9223372036854775808");
14233 tmp
[28 - i
] = (v
% 10) + '0';
14237 strcpy (buf
, tmp
+ 29 - i
);
14243 sprintf (buf
, "0x%x", (unsigned int) disp
);
14245 sprintf (buf
, "%d", (int) disp
);
14249 /* Put DISP in BUF as signed hex number. */
14252 print_displacement (char *buf
, bfd_vma disp
)
14254 bfd_signed_vma val
= disp
;
14263 /* Check for possible overflow. */
14266 switch (address_mode
)
14269 strcpy (buf
+ j
, "0x8000000000000000");
14272 strcpy (buf
+ j
, "0x80000000");
14275 strcpy (buf
+ j
, "0x8000");
14285 sprintf_vma (tmp
, (bfd_vma
) val
);
14286 for (i
= 0; tmp
[i
] == '0'; i
++)
14288 if (tmp
[i
] == '\0')
14290 strcpy (buf
+ j
, tmp
+ i
);
14294 intel_operand_size (int bytemode
, int sizeflag
)
14298 && (bytemode
== x_mode
14299 || bytemode
== evex_half_bcst_xmmq_mode
))
14302 oappend ("QWORD PTR ");
14304 oappend ("DWORD PTR ");
14313 oappend ("BYTE PTR ");
14318 case dqw_swap_mode
:
14319 oappend ("WORD PTR ");
14322 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14324 oappend ("QWORD PTR ");
14333 oappend ("QWORD PTR ");
14336 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14337 oappend ("DWORD PTR ");
14339 oappend ("WORD PTR ");
14340 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14344 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14346 oappend ("WORD PTR ");
14347 if (!(rex
& REX_W
))
14348 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14351 if (sizeflag
& DFLAG
)
14352 oappend ("QWORD PTR ");
14354 oappend ("DWORD PTR ");
14355 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14358 case d_scalar_mode
:
14359 case d_scalar_swap_mode
:
14362 oappend ("DWORD PTR ");
14365 case q_scalar_mode
:
14366 case q_scalar_swap_mode
:
14368 oappend ("QWORD PTR ");
14371 if (address_mode
== mode_64bit
)
14372 oappend ("QWORD PTR ");
14374 oappend ("DWORD PTR ");
14377 if (sizeflag
& DFLAG
)
14378 oappend ("FWORD PTR ");
14380 oappend ("DWORD PTR ");
14381 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14384 oappend ("TBYTE PTR ");
14388 case evex_x_gscat_mode
:
14389 case evex_x_nobcst_mode
:
14392 switch (vex
.length
)
14395 oappend ("XMMWORD PTR ");
14398 oappend ("YMMWORD PTR ");
14401 oappend ("ZMMWORD PTR ");
14408 oappend ("XMMWORD PTR ");
14411 oappend ("XMMWORD PTR ");
14414 oappend ("YMMWORD PTR ");
14417 case evex_half_bcst_xmmq_mode
:
14421 switch (vex
.length
)
14424 oappend ("QWORD PTR ");
14427 oappend ("XMMWORD PTR ");
14430 oappend ("YMMWORD PTR ");
14440 switch (vex
.length
)
14445 oappend ("BYTE PTR ");
14455 switch (vex
.length
)
14460 oappend ("WORD PTR ");
14470 switch (vex
.length
)
14475 oappend ("DWORD PTR ");
14485 switch (vex
.length
)
14490 oappend ("QWORD PTR ");
14500 switch (vex
.length
)
14503 oappend ("WORD PTR ");
14506 oappend ("DWORD PTR ");
14509 oappend ("QWORD PTR ");
14519 switch (vex
.length
)
14522 oappend ("DWORD PTR ");
14525 oappend ("QWORD PTR ");
14528 oappend ("XMMWORD PTR ");
14538 switch (vex
.length
)
14541 oappend ("QWORD PTR ");
14544 oappend ("YMMWORD PTR ");
14547 oappend ("ZMMWORD PTR ");
14557 switch (vex
.length
)
14561 oappend ("XMMWORD PTR ");
14568 oappend ("OWORD PTR ");
14571 case vex_w_dq_mode
:
14572 case vex_scalar_w_dq_mode
:
14577 oappend ("QWORD PTR ");
14579 oappend ("DWORD PTR ");
14581 case vex_vsib_d_w_dq_mode
:
14582 case vex_vsib_q_w_dq_mode
:
14589 oappend ("QWORD PTR ");
14591 oappend ("DWORD PTR ");
14595 switch (vex
.length
)
14598 oappend ("XMMWORD PTR ");
14601 oappend ("YMMWORD PTR ");
14604 oappend ("ZMMWORD PTR ");
14611 case vex_vsib_q_w_d_mode
:
14612 case vex_vsib_d_w_d_mode
:
14613 if (!need_vex
|| !vex
.evex
)
14616 switch (vex
.length
)
14619 oappend ("QWORD PTR ");
14622 oappend ("XMMWORD PTR ");
14625 oappend ("YMMWORD PTR ");
14633 if (!need_vex
|| vex
.length
!= 128)
14636 oappend ("DWORD PTR ");
14638 oappend ("BYTE PTR ");
14644 oappend ("QWORD PTR ");
14646 oappend ("WORD PTR ");
14655 OP_E_register (int bytemode
, int sizeflag
)
14657 int reg
= modrm
.rm
;
14658 const char **names
;
14664 if ((sizeflag
& SUFFIX_ALWAYS
)
14665 && (bytemode
== b_swap_mode
14666 || bytemode
== v_swap_mode
14667 || bytemode
== dqw_swap_mode
))
14693 names
= address_mode
== mode_64bit
? names64
: names32
;
14699 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14712 case dqw_swap_mode
:
14718 if ((sizeflag
& DFLAG
)
14719 || (bytemode
!= v_mode
14720 && bytemode
!= v_swap_mode
))
14724 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14729 names
= names_mask
;
14734 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14737 oappend (names
[reg
]);
14741 OP_E_memory (int bytemode
, int sizeflag
)
14744 int add
= (rex
& REX_B
) ? 8 : 0;
14750 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14752 && bytemode
!= x_mode
14753 && bytemode
!= xmmq_mode
14754 && bytemode
!= evex_half_bcst_xmmq_mode
)
14763 case dqw_swap_mode
:
14770 case vex_vsib_d_w_dq_mode
:
14771 case vex_vsib_d_w_d_mode
:
14772 case vex_vsib_q_w_dq_mode
:
14773 case vex_vsib_q_w_d_mode
:
14774 case evex_x_gscat_mode
:
14776 shift
= vex
.w
? 3 : 2;
14779 case evex_half_bcst_xmmq_mode
:
14783 shift
= vex
.w
? 3 : 2;
14786 /* Fall through if vex.b == 0. */
14790 case evex_x_nobcst_mode
:
14792 switch (vex
.length
)
14815 case q_scalar_mode
:
14817 case q_scalar_swap_mode
:
14823 case d_scalar_mode
:
14825 case d_scalar_swap_mode
:
14837 /* Make necessary corrections to shift for modes that need it.
14838 For these modes we currently have shift 4, 5 or 6 depending on
14839 vex.length (it corresponds to xmmword, ymmword or zmmword
14840 operand). We might want to make it 3, 4 or 5 (e.g. for
14841 xmmq_mode). In case of broadcast enabled the corrections
14842 aren't needed, as element size is always 32 or 64 bits. */
14844 && (bytemode
== xmmq_mode
14845 || bytemode
== evex_half_bcst_xmmq_mode
))
14847 else if (bytemode
== xmmqd_mode
)
14849 else if (bytemode
== xmmdw_mode
)
14851 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14859 intel_operand_size (bytemode
, sizeflag
);
14862 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14864 /* 32/64 bit address mode */
14873 int addr32flag
= !((sizeflag
& AFLAG
)
14874 || bytemode
== v_bnd_mode
14875 || bytemode
== bnd_mode
);
14876 const char **indexes64
= names64
;
14877 const char **indexes32
= names32
;
14887 vindex
= sib
.index
;
14893 case vex_vsib_d_w_dq_mode
:
14894 case vex_vsib_d_w_d_mode
:
14895 case vex_vsib_q_w_dq_mode
:
14896 case vex_vsib_q_w_d_mode
:
14906 switch (vex
.length
)
14909 indexes64
= indexes32
= names_xmm
;
14913 || bytemode
== vex_vsib_q_w_dq_mode
14914 || bytemode
== vex_vsib_q_w_d_mode
)
14915 indexes64
= indexes32
= names_ymm
;
14917 indexes64
= indexes32
= names_xmm
;
14921 || bytemode
== vex_vsib_q_w_dq_mode
14922 || bytemode
== vex_vsib_q_w_d_mode
)
14923 indexes64
= indexes32
= names_zmm
;
14925 indexes64
= indexes32
= names_ymm
;
14932 haveindex
= vindex
!= 4;
14939 rbase
= base
+ add
;
14947 if (address_mode
== mode_64bit
&& !havesib
)
14953 FETCH_DATA (the_info
, codep
+ 1);
14955 if ((disp
& 0x80) != 0)
14957 if (vex
.evex
&& shift
> 0)
14965 /* In 32bit mode, we need index register to tell [offset] from
14966 [eiz*1 + offset]. */
14967 needindex
= (havesib
14970 && address_mode
== mode_32bit
);
14971 havedisp
= (havebase
14973 || (havesib
&& (haveindex
|| scale
!= 0)));
14976 if (modrm
.mod
!= 0 || base
== 5)
14978 if (havedisp
|| riprel
)
14979 print_displacement (scratchbuf
, disp
);
14981 print_operand_value (scratchbuf
, 1, disp
);
14982 oappend (scratchbuf
);
14986 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14990 if ((havebase
|| haveindex
|| riprel
)
14991 && (bytemode
!= v_bnd_mode
)
14992 && (bytemode
!= bnd_mode
))
14993 used_prefixes
|= PREFIX_ADDR
;
14995 if (havedisp
|| (intel_syntax
&& riprel
))
14997 *obufp
++ = open_char
;
14998 if (intel_syntax
&& riprel
)
15001 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15005 oappend (address_mode
== mode_64bit
&& !addr32flag
15006 ? names64
[rbase
] : names32
[rbase
]);
15009 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15010 print index to tell base + index from base. */
15014 || (havebase
&& base
!= ESP_REG_NUM
))
15016 if (!intel_syntax
|| havebase
)
15018 *obufp
++ = separator_char
;
15022 oappend (address_mode
== mode_64bit
&& !addr32flag
15023 ? indexes64
[vindex
] : indexes32
[vindex
]);
15025 oappend (address_mode
== mode_64bit
&& !addr32flag
15026 ? index64
: index32
);
15028 *obufp
++ = scale_char
;
15030 sprintf (scratchbuf
, "%d", 1 << scale
);
15031 oappend (scratchbuf
);
15035 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15037 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15042 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15046 disp
= - (bfd_signed_vma
) disp
;
15050 print_displacement (scratchbuf
, disp
);
15052 print_operand_value (scratchbuf
, 1, disp
);
15053 oappend (scratchbuf
);
15056 *obufp
++ = close_char
;
15059 else if (intel_syntax
)
15061 if (modrm
.mod
!= 0 || base
== 5)
15063 if (!active_seg_prefix
)
15065 oappend (names_seg
[ds_reg
- es_reg
]);
15068 print_operand_value (scratchbuf
, 1, disp
);
15069 oappend (scratchbuf
);
15075 /* 16 bit address mode */
15076 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15083 if ((disp
& 0x8000) != 0)
15088 FETCH_DATA (the_info
, codep
+ 1);
15090 if ((disp
& 0x80) != 0)
15095 if ((disp
& 0x8000) != 0)
15101 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15103 print_displacement (scratchbuf
, disp
);
15104 oappend (scratchbuf
);
15107 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15109 *obufp
++ = open_char
;
15111 oappend (index16
[modrm
.rm
]);
15113 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15115 if ((bfd_signed_vma
) disp
>= 0)
15120 else if (modrm
.mod
!= 1)
15124 disp
= - (bfd_signed_vma
) disp
;
15127 print_displacement (scratchbuf
, disp
);
15128 oappend (scratchbuf
);
15131 *obufp
++ = close_char
;
15134 else if (intel_syntax
)
15136 if (!active_seg_prefix
)
15138 oappend (names_seg
[ds_reg
- es_reg
]);
15141 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15142 oappend (scratchbuf
);
15145 if (vex
.evex
&& vex
.b
15146 && (bytemode
== x_mode
15147 || bytemode
== xmmq_mode
15148 || bytemode
== evex_half_bcst_xmmq_mode
))
15151 || bytemode
== xmmq_mode
15152 || bytemode
== evex_half_bcst_xmmq_mode
)
15154 switch (vex
.length
)
15157 oappend ("{1to2}");
15160 oappend ("{1to4}");
15163 oappend ("{1to8}");
15171 switch (vex
.length
)
15174 oappend ("{1to4}");
15177 oappend ("{1to8}");
15180 oappend ("{1to16}");
15190 OP_E (int bytemode
, int sizeflag
)
15192 /* Skip mod/rm byte. */
15196 if (modrm
.mod
== 3)
15197 OP_E_register (bytemode
, sizeflag
);
15199 OP_E_memory (bytemode
, sizeflag
);
15203 OP_G (int bytemode
, int sizeflag
)
15214 oappend (names8rex
[modrm
.reg
+ add
]);
15216 oappend (names8
[modrm
.reg
+ add
]);
15219 oappend (names16
[modrm
.reg
+ add
]);
15224 oappend (names32
[modrm
.reg
+ add
]);
15227 oappend (names64
[modrm
.reg
+ add
]);
15230 oappend (names_bnd
[modrm
.reg
]);
15237 case dqw_swap_mode
:
15240 oappend (names64
[modrm
.reg
+ add
]);
15243 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15244 oappend (names32
[modrm
.reg
+ add
]);
15246 oappend (names16
[modrm
.reg
+ add
]);
15247 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15251 if (address_mode
== mode_64bit
)
15252 oappend (names64
[modrm
.reg
+ add
]);
15254 oappend (names32
[modrm
.reg
+ add
]);
15258 oappend (names_mask
[modrm
.reg
+ add
]);
15261 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15274 FETCH_DATA (the_info
, codep
+ 8);
15275 a
= *codep
++ & 0xff;
15276 a
|= (*codep
++ & 0xff) << 8;
15277 a
|= (*codep
++ & 0xff) << 16;
15278 a
|= (*codep
++ & 0xff) << 24;
15279 b
= *codep
++ & 0xff;
15280 b
|= (*codep
++ & 0xff) << 8;
15281 b
|= (*codep
++ & 0xff) << 16;
15282 b
|= (*codep
++ & 0xff) << 24;
15283 x
= a
+ ((bfd_vma
) b
<< 32);
15291 static bfd_signed_vma
15294 bfd_signed_vma x
= 0;
15296 FETCH_DATA (the_info
, codep
+ 4);
15297 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15298 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15299 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15300 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15304 static bfd_signed_vma
15307 bfd_signed_vma x
= 0;
15309 FETCH_DATA (the_info
, codep
+ 4);
15310 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15311 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15312 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15313 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15315 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15325 FETCH_DATA (the_info
, codep
+ 2);
15326 x
= *codep
++ & 0xff;
15327 x
|= (*codep
++ & 0xff) << 8;
15332 set_op (bfd_vma op
, int riprel
)
15334 op_index
[op_ad
] = op_ad
;
15335 if (address_mode
== mode_64bit
)
15337 op_address
[op_ad
] = op
;
15338 op_riprel
[op_ad
] = riprel
;
15342 /* Mask to get a 32-bit address. */
15343 op_address
[op_ad
] = op
& 0xffffffff;
15344 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15349 OP_REG (int code
, int sizeflag
)
15356 case es_reg
: case ss_reg
: case cs_reg
:
15357 case ds_reg
: case fs_reg
: case gs_reg
:
15358 oappend (names_seg
[code
- es_reg
]);
15370 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15371 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15372 s
= names16
[code
- ax_reg
+ add
];
15374 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15375 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15378 s
= names8rex
[code
- al_reg
+ add
];
15380 s
= names8
[code
- al_reg
];
15382 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15383 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15384 if (address_mode
== mode_64bit
15385 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15387 s
= names64
[code
- rAX_reg
+ add
];
15390 code
+= eAX_reg
- rAX_reg
;
15391 /* Fall through. */
15392 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15393 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15396 s
= names64
[code
- eAX_reg
+ add
];
15399 if (sizeflag
& DFLAG
)
15400 s
= names32
[code
- eAX_reg
+ add
];
15402 s
= names16
[code
- eAX_reg
+ add
];
15403 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15407 s
= INTERNAL_DISASSEMBLER_ERROR
;
15414 OP_IMREG (int code
, int sizeflag
)
15426 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15427 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15428 s
= names16
[code
- ax_reg
];
15430 case es_reg
: case ss_reg
: case cs_reg
:
15431 case ds_reg
: case fs_reg
: case gs_reg
:
15432 s
= names_seg
[code
- es_reg
];
15434 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15435 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15438 s
= names8rex
[code
- al_reg
];
15440 s
= names8
[code
- al_reg
];
15442 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15443 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15446 s
= names64
[code
- eAX_reg
];
15449 if (sizeflag
& DFLAG
)
15450 s
= names32
[code
- eAX_reg
];
15452 s
= names16
[code
- eAX_reg
];
15453 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15456 case z_mode_ax_reg
:
15457 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15461 if (!(rex
& REX_W
))
15462 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15465 s
= INTERNAL_DISASSEMBLER_ERROR
;
15472 OP_I (int bytemode
, int sizeflag
)
15475 bfd_signed_vma mask
= -1;
15480 FETCH_DATA (the_info
, codep
+ 1);
15485 if (address_mode
== mode_64bit
)
15490 /* Fall through. */
15497 if (sizeflag
& DFLAG
)
15507 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15519 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15524 scratchbuf
[0] = '$';
15525 print_operand_value (scratchbuf
+ 1, 1, op
);
15526 oappend_maybe_intel (scratchbuf
);
15527 scratchbuf
[0] = '\0';
15531 OP_I64 (int bytemode
, int sizeflag
)
15534 bfd_signed_vma mask
= -1;
15536 if (address_mode
!= mode_64bit
)
15538 OP_I (bytemode
, sizeflag
);
15545 FETCH_DATA (the_info
, codep
+ 1);
15555 if (sizeflag
& DFLAG
)
15565 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15573 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15578 scratchbuf
[0] = '$';
15579 print_operand_value (scratchbuf
+ 1, 1, op
);
15580 oappend_maybe_intel (scratchbuf
);
15581 scratchbuf
[0] = '\0';
15585 OP_sI (int bytemode
, int sizeflag
)
15593 FETCH_DATA (the_info
, codep
+ 1);
15595 if ((op
& 0x80) != 0)
15597 if (bytemode
== b_T_mode
)
15599 if (address_mode
!= mode_64bit
15600 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15602 /* The operand-size prefix is overridden by a REX prefix. */
15603 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15611 if (!(rex
& REX_W
))
15613 if (sizeflag
& DFLAG
)
15621 /* The operand-size prefix is overridden by a REX prefix. */
15622 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15628 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15632 scratchbuf
[0] = '$';
15633 print_operand_value (scratchbuf
+ 1, 1, op
);
15634 oappend_maybe_intel (scratchbuf
);
15638 OP_J (int bytemode
, int sizeflag
)
15642 bfd_vma segment
= 0;
15647 FETCH_DATA (the_info
, codep
+ 1);
15649 if ((disp
& 0x80) != 0)
15654 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15659 if ((disp
& 0x8000) != 0)
15661 /* In 16bit mode, address is wrapped around at 64k within
15662 the same segment. Otherwise, a data16 prefix on a jump
15663 instruction means that the pc is masked to 16 bits after
15664 the displacement is added! */
15666 if ((prefixes
& PREFIX_DATA
) == 0)
15667 segment
= ((start_pc
+ codep
- start_codep
)
15668 & ~((bfd_vma
) 0xffff));
15670 if (!(rex
& REX_W
))
15671 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15674 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15677 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15679 print_operand_value (scratchbuf
, 1, disp
);
15680 oappend (scratchbuf
);
15684 OP_SEG (int bytemode
, int sizeflag
)
15686 if (bytemode
== w_mode
)
15687 oappend (names_seg
[modrm
.reg
]);
15689 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15693 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15697 if (sizeflag
& DFLAG
)
15707 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15709 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15711 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15712 oappend (scratchbuf
);
15716 OP_OFF (int bytemode
, int sizeflag
)
15720 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15721 intel_operand_size (bytemode
, sizeflag
);
15724 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15731 if (!active_seg_prefix
)
15733 oappend (names_seg
[ds_reg
- es_reg
]);
15737 print_operand_value (scratchbuf
, 1, off
);
15738 oappend (scratchbuf
);
15742 OP_OFF64 (int bytemode
, int sizeflag
)
15746 if (address_mode
!= mode_64bit
15747 || (prefixes
& PREFIX_ADDR
))
15749 OP_OFF (bytemode
, sizeflag
);
15753 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15754 intel_operand_size (bytemode
, sizeflag
);
15761 if (!active_seg_prefix
)
15763 oappend (names_seg
[ds_reg
- es_reg
]);
15767 print_operand_value (scratchbuf
, 1, off
);
15768 oappend (scratchbuf
);
15772 ptr_reg (int code
, int sizeflag
)
15776 *obufp
++ = open_char
;
15777 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15778 if (address_mode
== mode_64bit
)
15780 if (!(sizeflag
& AFLAG
))
15781 s
= names32
[code
- eAX_reg
];
15783 s
= names64
[code
- eAX_reg
];
15785 else if (sizeflag
& AFLAG
)
15786 s
= names32
[code
- eAX_reg
];
15788 s
= names16
[code
- eAX_reg
];
15790 *obufp
++ = close_char
;
15795 OP_ESreg (int code
, int sizeflag
)
15801 case 0x6d: /* insw/insl */
15802 intel_operand_size (z_mode
, sizeflag
);
15804 case 0xa5: /* movsw/movsl/movsq */
15805 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15806 case 0xab: /* stosw/stosl */
15807 case 0xaf: /* scasw/scasl */
15808 intel_operand_size (v_mode
, sizeflag
);
15811 intel_operand_size (b_mode
, sizeflag
);
15814 oappend_maybe_intel ("%es:");
15815 ptr_reg (code
, sizeflag
);
15819 OP_DSreg (int code
, int sizeflag
)
15825 case 0x6f: /* outsw/outsl */
15826 intel_operand_size (z_mode
, sizeflag
);
15828 case 0xa5: /* movsw/movsl/movsq */
15829 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15830 case 0xad: /* lodsw/lodsl/lodsq */
15831 intel_operand_size (v_mode
, sizeflag
);
15834 intel_operand_size (b_mode
, sizeflag
);
15837 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15838 default segment register DS is printed. */
15839 if (!active_seg_prefix
)
15840 active_seg_prefix
= PREFIX_DS
;
15842 ptr_reg (code
, sizeflag
);
15846 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15854 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15856 all_prefixes
[last_lock_prefix
] = 0;
15857 used_prefixes
|= PREFIX_LOCK
;
15862 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15863 oappend_maybe_intel (scratchbuf
);
15867 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15876 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15878 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15879 oappend (scratchbuf
);
15883 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15885 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15886 oappend_maybe_intel (scratchbuf
);
15890 OP_R (int bytemode
, int sizeflag
)
15892 /* Skip mod/rm byte. */
15895 OP_E_register (bytemode
, sizeflag
);
15899 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15901 int reg
= modrm
.reg
;
15902 const char **names
;
15904 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15905 if (prefixes
& PREFIX_DATA
)
15914 oappend (names
[reg
]);
15918 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15920 int reg
= modrm
.reg
;
15921 const char **names
;
15933 && bytemode
!= xmm_mode
15934 && bytemode
!= xmmq_mode
15935 && bytemode
!= evex_half_bcst_xmmq_mode
15936 && bytemode
!= ymm_mode
15937 && bytemode
!= scalar_mode
)
15939 switch (vex
.length
)
15946 || (bytemode
!= vex_vsib_q_w_dq_mode
15947 && bytemode
!= vex_vsib_q_w_d_mode
))
15959 else if (bytemode
== xmmq_mode
15960 || bytemode
== evex_half_bcst_xmmq_mode
)
15962 switch (vex
.length
)
15975 else if (bytemode
== ymm_mode
)
15979 oappend (names
[reg
]);
15983 OP_EM (int bytemode
, int sizeflag
)
15986 const char **names
;
15988 if (modrm
.mod
!= 3)
15991 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15993 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15994 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15996 OP_E (bytemode
, sizeflag
);
16000 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16003 /* Skip mod/rm byte. */
16006 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16008 if (prefixes
& PREFIX_DATA
)
16017 oappend (names
[reg
]);
16020 /* cvt* are the only instructions in sse2 which have
16021 both SSE and MMX operands and also have 0x66 prefix
16022 in their opcode. 0x66 was originally used to differentiate
16023 between SSE and MMX instruction(operands). So we have to handle the
16024 cvt* separately using OP_EMC and OP_MXC */
16026 OP_EMC (int bytemode
, int sizeflag
)
16028 if (modrm
.mod
!= 3)
16030 if (intel_syntax
&& bytemode
== v_mode
)
16032 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16033 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16035 OP_E (bytemode
, sizeflag
);
16039 /* Skip mod/rm byte. */
16042 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16043 oappend (names_mm
[modrm
.rm
]);
16047 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16049 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16050 oappend (names_mm
[modrm
.reg
]);
16054 OP_EX (int bytemode
, int sizeflag
)
16057 const char **names
;
16059 /* Skip mod/rm byte. */
16063 if (modrm
.mod
!= 3)
16065 OP_E_memory (bytemode
, sizeflag
);
16080 if ((sizeflag
& SUFFIX_ALWAYS
)
16081 && (bytemode
== x_swap_mode
16082 || bytemode
== d_swap_mode
16083 || bytemode
== dqw_swap_mode
16084 || bytemode
== d_scalar_swap_mode
16085 || bytemode
== q_swap_mode
16086 || bytemode
== q_scalar_swap_mode
))
16090 && bytemode
!= xmm_mode
16091 && bytemode
!= xmmdw_mode
16092 && bytemode
!= xmmqd_mode
16093 && bytemode
!= xmm_mb_mode
16094 && bytemode
!= xmm_mw_mode
16095 && bytemode
!= xmm_md_mode
16096 && bytemode
!= xmm_mq_mode
16097 && bytemode
!= xmm_mdq_mode
16098 && bytemode
!= xmmq_mode
16099 && bytemode
!= evex_half_bcst_xmmq_mode
16100 && bytemode
!= ymm_mode
16101 && bytemode
!= d_scalar_mode
16102 && bytemode
!= d_scalar_swap_mode
16103 && bytemode
!= q_scalar_mode
16104 && bytemode
!= q_scalar_swap_mode
16105 && bytemode
!= vex_scalar_w_dq_mode
)
16107 switch (vex
.length
)
16122 else if (bytemode
== xmmq_mode
16123 || bytemode
== evex_half_bcst_xmmq_mode
)
16125 switch (vex
.length
)
16138 else if (bytemode
== ymm_mode
)
16142 oappend (names
[reg
]);
16146 OP_MS (int bytemode
, int sizeflag
)
16148 if (modrm
.mod
== 3)
16149 OP_EM (bytemode
, sizeflag
);
16155 OP_XS (int bytemode
, int sizeflag
)
16157 if (modrm
.mod
== 3)
16158 OP_EX (bytemode
, sizeflag
);
16164 OP_M (int bytemode
, int sizeflag
)
16166 if (modrm
.mod
== 3)
16167 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16170 OP_E (bytemode
, sizeflag
);
16174 OP_0f07 (int bytemode
, int sizeflag
)
16176 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16179 OP_E (bytemode
, sizeflag
);
16182 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16183 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16186 NOP_Fixup1 (int bytemode
, int sizeflag
)
16188 if ((prefixes
& PREFIX_DATA
) != 0
16191 && address_mode
== mode_64bit
))
16192 OP_REG (bytemode
, sizeflag
);
16194 strcpy (obuf
, "nop");
16198 NOP_Fixup2 (int bytemode
, int sizeflag
)
16200 if ((prefixes
& PREFIX_DATA
) != 0
16203 && address_mode
== mode_64bit
))
16204 OP_IMREG (bytemode
, sizeflag
);
16207 static const char *const Suffix3DNow
[] = {
16208 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16209 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16210 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16211 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16212 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16213 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16214 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16215 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16216 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16217 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16218 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16219 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16220 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16221 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16222 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16223 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16224 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16225 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16226 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16227 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16228 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16229 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16230 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16231 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16232 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16233 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16234 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16235 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16236 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16237 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16238 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16239 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16240 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16241 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16242 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16243 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16244 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16245 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16246 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16247 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16248 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16249 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16250 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16251 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16252 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16253 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16254 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16255 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16256 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16257 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16258 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16259 /* CC */ NULL
, NULL
, NULL
, NULL
,
16260 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16261 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16262 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16263 /* DC */ NULL
, NULL
, NULL
, NULL
,
16264 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16265 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16266 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16267 /* EC */ NULL
, NULL
, NULL
, NULL
,
16268 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16269 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16270 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16271 /* FC */ NULL
, NULL
, NULL
, NULL
,
16275 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16277 const char *mnemonic
;
16279 FETCH_DATA (the_info
, codep
+ 1);
16280 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16281 place where an 8-bit immediate would normally go. ie. the last
16282 byte of the instruction. */
16283 obufp
= mnemonicendp
;
16284 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16286 oappend (mnemonic
);
16289 /* Since a variable sized modrm/sib chunk is between the start
16290 of the opcode (0x0f0f) and the opcode suffix, we need to do
16291 all the modrm processing first, and don't know until now that
16292 we have a bad opcode. This necessitates some cleaning up. */
16293 op_out
[0][0] = '\0';
16294 op_out
[1][0] = '\0';
16297 mnemonicendp
= obufp
;
16300 static struct op simd_cmp_op
[] =
16302 { STRING_COMMA_LEN ("eq") },
16303 { STRING_COMMA_LEN ("lt") },
16304 { STRING_COMMA_LEN ("le") },
16305 { STRING_COMMA_LEN ("unord") },
16306 { STRING_COMMA_LEN ("neq") },
16307 { STRING_COMMA_LEN ("nlt") },
16308 { STRING_COMMA_LEN ("nle") },
16309 { STRING_COMMA_LEN ("ord") }
16313 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16315 unsigned int cmp_type
;
16317 FETCH_DATA (the_info
, codep
+ 1);
16318 cmp_type
= *codep
++ & 0xff;
16319 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16322 char *p
= mnemonicendp
- 2;
16326 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16327 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16331 /* We have a reserved extension byte. Output it directly. */
16332 scratchbuf
[0] = '$';
16333 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16334 oappend_maybe_intel (scratchbuf
);
16335 scratchbuf
[0] = '\0';
16340 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16341 int sizeflag ATTRIBUTE_UNUSED
)
16343 /* mwait %eax,%ecx */
16346 const char **names
= (address_mode
== mode_64bit
16347 ? names64
: names32
);
16348 strcpy (op_out
[0], names
[0]);
16349 strcpy (op_out
[1], names
[1]);
16350 two_source_ops
= 1;
16352 /* Skip mod/rm byte. */
16358 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16359 int sizeflag ATTRIBUTE_UNUSED
)
16361 /* monitor %eax,%ecx,%edx" */
16364 const char **op1_names
;
16365 const char **names
= (address_mode
== mode_64bit
16366 ? names64
: names32
);
16368 if (!(prefixes
& PREFIX_ADDR
))
16369 op1_names
= (address_mode
== mode_16bit
16370 ? names16
: names
);
16373 /* Remove "addr16/addr32". */
16374 all_prefixes
[last_addr_prefix
] = 0;
16375 op1_names
= (address_mode
!= mode_32bit
16376 ? names32
: names16
);
16377 used_prefixes
|= PREFIX_ADDR
;
16379 strcpy (op_out
[0], op1_names
[0]);
16380 strcpy (op_out
[1], names
[1]);
16381 strcpy (op_out
[2], names
[2]);
16382 two_source_ops
= 1;
16384 /* Skip mod/rm byte. */
16392 /* Throw away prefixes and 1st. opcode byte. */
16393 codep
= insn_codep
+ 1;
16398 REP_Fixup (int bytemode
, int sizeflag
)
16400 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16402 if (prefixes
& PREFIX_REPZ
)
16403 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16410 OP_IMREG (bytemode
, sizeflag
);
16413 OP_ESreg (bytemode
, sizeflag
);
16416 OP_DSreg (bytemode
, sizeflag
);
16424 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16428 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16430 if (prefixes
& PREFIX_REPNZ
)
16431 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16434 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16435 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16439 HLE_Fixup1 (int bytemode
, int sizeflag
)
16442 && (prefixes
& PREFIX_LOCK
) != 0)
16444 if (prefixes
& PREFIX_REPZ
)
16445 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16446 if (prefixes
& PREFIX_REPNZ
)
16447 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16450 OP_E (bytemode
, sizeflag
);
16453 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16454 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16458 HLE_Fixup2 (int bytemode
, int sizeflag
)
16460 if (modrm
.mod
!= 3)
16462 if (prefixes
& PREFIX_REPZ
)
16463 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16464 if (prefixes
& PREFIX_REPNZ
)
16465 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16468 OP_E (bytemode
, sizeflag
);
16471 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16472 "xrelease" for memory operand. No check for LOCK prefix. */
16475 HLE_Fixup3 (int bytemode
, int sizeflag
)
16478 && last_repz_prefix
> last_repnz_prefix
16479 && (prefixes
& PREFIX_REPZ
) != 0)
16480 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16482 OP_E (bytemode
, sizeflag
);
16486 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16491 /* Change cmpxchg8b to cmpxchg16b. */
16492 char *p
= mnemonicendp
- 2;
16493 mnemonicendp
= stpcpy (p
, "16b");
16496 else if ((prefixes
& PREFIX_LOCK
) != 0)
16498 if (prefixes
& PREFIX_REPZ
)
16499 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16500 if (prefixes
& PREFIX_REPNZ
)
16501 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16504 OP_M (bytemode
, sizeflag
);
16508 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16510 const char **names
;
16514 switch (vex
.length
)
16528 oappend (names
[reg
]);
16532 CRC32_Fixup (int bytemode
, int sizeflag
)
16534 /* Add proper suffix to "crc32". */
16535 char *p
= mnemonicendp
;
16554 if (sizeflag
& DFLAG
)
16558 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16562 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16569 if (modrm
.mod
== 3)
16573 /* Skip mod/rm byte. */
16578 add
= (rex
& REX_B
) ? 8 : 0;
16579 if (bytemode
== b_mode
)
16583 oappend (names8rex
[modrm
.rm
+ add
]);
16585 oappend (names8
[modrm
.rm
+ add
]);
16591 oappend (names64
[modrm
.rm
+ add
]);
16592 else if ((prefixes
& PREFIX_DATA
))
16593 oappend (names16
[modrm
.rm
+ add
]);
16595 oappend (names32
[modrm
.rm
+ add
]);
16599 OP_E (bytemode
, sizeflag
);
16603 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16605 /* Add proper suffix to "fxsave" and "fxrstor". */
16609 char *p
= mnemonicendp
;
16615 OP_M (bytemode
, sizeflag
);
16618 /* Display the destination register operand for instructions with
16622 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16625 const char **names
;
16633 reg
= vex
.register_specifier
;
16640 if (bytemode
== vex_scalar_mode
)
16642 oappend (names_xmm
[reg
]);
16646 switch (vex
.length
)
16653 case vex_vsib_q_w_dq_mode
:
16654 case vex_vsib_q_w_d_mode
:
16665 names
= names_mask
;
16679 case vex_vsib_q_w_dq_mode
:
16680 case vex_vsib_q_w_d_mode
:
16681 names
= vex
.w
? names_ymm
: names_xmm
;
16685 names
= names_mask
;
16699 oappend (names
[reg
]);
16702 /* Get the VEX immediate byte without moving codep. */
16704 static unsigned char
16705 get_vex_imm8 (int sizeflag
, int opnum
)
16707 int bytes_before_imm
= 0;
16709 if (modrm
.mod
!= 3)
16711 /* There are SIB/displacement bytes. */
16712 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16714 /* 32/64 bit address mode */
16715 int base
= modrm
.rm
;
16717 /* Check SIB byte. */
16720 FETCH_DATA (the_info
, codep
+ 1);
16722 /* When decoding the third source, don't increase
16723 bytes_before_imm as this has already been incremented
16724 by one in OP_E_memory while decoding the second
16727 bytes_before_imm
++;
16730 /* Don't increase bytes_before_imm when decoding the third source,
16731 it has already been incremented by OP_E_memory while decoding
16732 the second source operand. */
16738 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16739 SIB == 5, there is a 4 byte displacement. */
16741 /* No displacement. */
16744 /* 4 byte displacement. */
16745 bytes_before_imm
+= 4;
16748 /* 1 byte displacement. */
16749 bytes_before_imm
++;
16756 /* 16 bit address mode */
16757 /* Don't increase bytes_before_imm when decoding the third source,
16758 it has already been incremented by OP_E_memory while decoding
16759 the second source operand. */
16765 /* When modrm.rm == 6, there is a 2 byte displacement. */
16767 /* No displacement. */
16770 /* 2 byte displacement. */
16771 bytes_before_imm
+= 2;
16774 /* 1 byte displacement: when decoding the third source,
16775 don't increase bytes_before_imm as this has already
16776 been incremented by one in OP_E_memory while decoding
16777 the second source operand. */
16779 bytes_before_imm
++;
16787 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16788 return codep
[bytes_before_imm
];
16792 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16794 const char **names
;
16796 if (reg
== -1 && modrm
.mod
!= 3)
16798 OP_E_memory (bytemode
, sizeflag
);
16810 else if (reg
> 7 && address_mode
!= mode_64bit
)
16814 switch (vex
.length
)
16825 oappend (names
[reg
]);
16829 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16832 static unsigned char vex_imm8
;
16834 if (vex_w_done
== 0)
16838 /* Skip mod/rm byte. */
16842 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16845 reg
= vex_imm8
>> 4;
16847 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16849 else if (vex_w_done
== 1)
16854 reg
= vex_imm8
>> 4;
16856 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16860 /* Output the imm8 directly. */
16861 scratchbuf
[0] = '$';
16862 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16863 oappend_maybe_intel (scratchbuf
);
16864 scratchbuf
[0] = '\0';
16870 OP_Vex_2src (int bytemode
, int sizeflag
)
16872 if (modrm
.mod
== 3)
16874 int reg
= modrm
.rm
;
16878 oappend (names_xmm
[reg
]);
16883 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16885 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16886 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16888 OP_E (bytemode
, sizeflag
);
16893 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16895 if (modrm
.mod
== 3)
16897 /* Skip mod/rm byte. */
16903 oappend (names_xmm
[vex
.register_specifier
]);
16905 OP_Vex_2src (bytemode
, sizeflag
);
16909 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16912 OP_Vex_2src (bytemode
, sizeflag
);
16914 oappend (names_xmm
[vex
.register_specifier
]);
16918 OP_EX_VexW (int bytemode
, int sizeflag
)
16926 /* Skip mod/rm byte. */
16931 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16936 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16939 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16943 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16944 int sizeflag ATTRIBUTE_UNUSED
)
16946 /* Skip the immediate byte and check for invalid bits. */
16947 FETCH_DATA (the_info
, codep
+ 1);
16948 if (*codep
++ & 0xf)
16953 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16956 const char **names
;
16958 FETCH_DATA (the_info
, codep
+ 1);
16961 if (bytemode
!= x_mode
)
16968 if (reg
> 7 && address_mode
!= mode_64bit
)
16971 switch (vex
.length
)
16982 oappend (names
[reg
]);
16986 OP_XMM_VexW (int bytemode
, int sizeflag
)
16988 /* Turn off the REX.W bit since it is used for swapping operands
16991 OP_XMM (bytemode
, sizeflag
);
16995 OP_EX_Vex (int bytemode
, int sizeflag
)
16997 if (modrm
.mod
!= 3)
16999 if (vex
.register_specifier
!= 0)
17003 OP_EX (bytemode
, sizeflag
);
17007 OP_XMM_Vex (int bytemode
, int sizeflag
)
17009 if (modrm
.mod
!= 3)
17011 if (vex
.register_specifier
!= 0)
17015 OP_XMM (bytemode
, sizeflag
);
17019 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17021 switch (vex
.length
)
17024 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17027 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17034 static struct op vex_cmp_op
[] =
17036 { STRING_COMMA_LEN ("eq") },
17037 { STRING_COMMA_LEN ("lt") },
17038 { STRING_COMMA_LEN ("le") },
17039 { STRING_COMMA_LEN ("unord") },
17040 { STRING_COMMA_LEN ("neq") },
17041 { STRING_COMMA_LEN ("nlt") },
17042 { STRING_COMMA_LEN ("nle") },
17043 { STRING_COMMA_LEN ("ord") },
17044 { STRING_COMMA_LEN ("eq_uq") },
17045 { STRING_COMMA_LEN ("nge") },
17046 { STRING_COMMA_LEN ("ngt") },
17047 { STRING_COMMA_LEN ("false") },
17048 { STRING_COMMA_LEN ("neq_oq") },
17049 { STRING_COMMA_LEN ("ge") },
17050 { STRING_COMMA_LEN ("gt") },
17051 { STRING_COMMA_LEN ("true") },
17052 { STRING_COMMA_LEN ("eq_os") },
17053 { STRING_COMMA_LEN ("lt_oq") },
17054 { STRING_COMMA_LEN ("le_oq") },
17055 { STRING_COMMA_LEN ("unord_s") },
17056 { STRING_COMMA_LEN ("neq_us") },
17057 { STRING_COMMA_LEN ("nlt_uq") },
17058 { STRING_COMMA_LEN ("nle_uq") },
17059 { STRING_COMMA_LEN ("ord_s") },
17060 { STRING_COMMA_LEN ("eq_us") },
17061 { STRING_COMMA_LEN ("nge_uq") },
17062 { STRING_COMMA_LEN ("ngt_uq") },
17063 { STRING_COMMA_LEN ("false_os") },
17064 { STRING_COMMA_LEN ("neq_os") },
17065 { STRING_COMMA_LEN ("ge_oq") },
17066 { STRING_COMMA_LEN ("gt_oq") },
17067 { STRING_COMMA_LEN ("true_us") },
17071 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17073 unsigned int cmp_type
;
17075 FETCH_DATA (the_info
, codep
+ 1);
17076 cmp_type
= *codep
++ & 0xff;
17077 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17080 char *p
= mnemonicendp
- 2;
17084 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17085 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17089 /* We have a reserved extension byte. Output it directly. */
17090 scratchbuf
[0] = '$';
17091 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17092 oappend_maybe_intel (scratchbuf
);
17093 scratchbuf
[0] = '\0';
17098 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17099 int sizeflag ATTRIBUTE_UNUSED
)
17101 unsigned int cmp_type
;
17106 FETCH_DATA (the_info
, codep
+ 1);
17107 cmp_type
= *codep
++ & 0xff;
17108 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17109 If it's the case, print suffix, otherwise - print the immediate. */
17110 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17115 char *p
= mnemonicendp
- 2;
17117 /* vpcmp* can have both one- and two-lettered suffix. */
17131 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17132 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17136 /* We have a reserved extension byte. Output it directly. */
17137 scratchbuf
[0] = '$';
17138 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17139 oappend_maybe_intel (scratchbuf
);
17140 scratchbuf
[0] = '\0';
17144 static const struct op pclmul_op
[] =
17146 { STRING_COMMA_LEN ("lql") },
17147 { STRING_COMMA_LEN ("hql") },
17148 { STRING_COMMA_LEN ("lqh") },
17149 { STRING_COMMA_LEN ("hqh") }
17153 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17154 int sizeflag ATTRIBUTE_UNUSED
)
17156 unsigned int pclmul_type
;
17158 FETCH_DATA (the_info
, codep
+ 1);
17159 pclmul_type
= *codep
++ & 0xff;
17160 switch (pclmul_type
)
17171 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17174 char *p
= mnemonicendp
- 3;
17179 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17180 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17184 /* We have a reserved extension byte. Output it directly. */
17185 scratchbuf
[0] = '$';
17186 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17187 oappend_maybe_intel (scratchbuf
);
17188 scratchbuf
[0] = '\0';
17193 MOVBE_Fixup (int bytemode
, int sizeflag
)
17195 /* Add proper suffix to "movbe". */
17196 char *p
= mnemonicendp
;
17205 if (sizeflag
& SUFFIX_ALWAYS
)
17211 if (sizeflag
& DFLAG
)
17215 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17220 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17227 OP_M (bytemode
, sizeflag
);
17231 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17234 const char **names
;
17236 /* Skip mod/rm byte. */
17250 oappend (names
[reg
]);
17254 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17256 const char **names
;
17263 oappend (names
[vex
.register_specifier
]);
17267 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17270 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17274 if ((rex
& REX_R
) != 0 || !vex
.r
)
17280 oappend (names_mask
[modrm
.reg
]);
17284 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17287 || (bytemode
!= evex_rounding_mode
17288 && bytemode
!= evex_sae_mode
))
17290 if (modrm
.mod
== 3 && vex
.b
)
17293 case evex_rounding_mode
:
17294 oappend (names_rounding
[vex
.ll
]);
17296 case evex_sae_mode
: