opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gw { OP_G, w_mode }
 284 #define Rd { OP_R, d_mode }
 285 #define Rdq { OP_R, dq_mode }
 286 #define Rm { OP_R, m_mode }
 287 #define Ib { OP_I, b_mode }
 288 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 290 #define Iv { OP_I, v_mode }
 291 #define sIv { OP_sI, v_mode }
 292 #define Iq { OP_I, q_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Iw { OP_I, w_mode }
 295 #define I1 { OP_I, const_1_mode }
 296 #define Jb { OP_J, b_mode }
 297 #define Jv { OP_J, v_mode }
 298 #define Cm { OP_C, m_mode }
 299 #define Dm { OP_D, m_mode }
 300 #define Td { OP_T, d_mode }
 301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 302
 303 #define RMeAX { OP_REG, eAX_reg }
 304 #define RMeBX { OP_REG, eBX_reg }
 305 #define RMeCX { OP_REG, eCX_reg }
 306 #define RMeDX { OP_REG, eDX_reg }
 307 #define RMeSP { OP_REG, eSP_reg }
 308 #define RMeBP { OP_REG, eBP_reg }
 309 #define RMeSI { OP_REG, eSI_reg }
 310 #define RMeDI { OP_REG, eDI_reg }
 311 #define RMrAX { OP_REG, rAX_reg }
 312 #define RMrBX { OP_REG, rBX_reg }
 313 #define RMrCX { OP_REG, rCX_reg }
 314 #define RMrDX { OP_REG, rDX_reg }
 315 #define RMrSP { OP_REG, rSP_reg }
 316 #define RMrBP { OP_REG, rBP_reg }
 317 #define RMrSI { OP_REG, rSI_reg }
 318 #define RMrDI { OP_REG, rDI_reg }
 319 #define RMAL { OP_REG, al_reg }
 320 #define RMCL { OP_REG, cl_reg }
 321 #define RMDL { OP_REG, dl_reg }
 322 #define RMBL { OP_REG, bl_reg }
 323 #define RMAH { OP_REG, ah_reg }
 324 #define RMCH { OP_REG, ch_reg }
 325 #define RMDH { OP_REG, dh_reg }
 326 #define RMBH { OP_REG, bh_reg }
 327 #define RMAX { OP_REG, ax_reg }
 328 #define RMDX { OP_REG, dx_reg }
 329
 330 #define eAX { OP_IMREG, eAX_reg }
 331 #define eBX { OP_IMREG, eBX_reg }
 332 #define eCX { OP_IMREG, eCX_reg }
 333 #define eDX { OP_IMREG, eDX_reg }
 334 #define eSP { OP_IMREG, eSP_reg }
 335 #define eBP { OP_IMREG, eBP_reg }
 336 #define eSI { OP_IMREG, eSI_reg }
 337 #define eDI { OP_IMREG, eDI_reg }
 338 #define AL { OP_IMREG, al_reg }
 339 #define CL { OP_IMREG, cl_reg }
 340 #define DL { OP_IMREG, dl_reg }
 341 #define BL { OP_IMREG, bl_reg }
 342 #define AH { OP_IMREG, ah_reg }
 343 #define CH { OP_IMREG, ch_reg }
 344 #define DH { OP_IMREG, dh_reg }
 345 #define BH { OP_IMREG, bh_reg }
 346 #define AX { OP_IMREG, ax_reg }
 347 #define DX { OP_IMREG, dx_reg }
 348 #define zAX { OP_IMREG, z_mode_ax_reg }
 349 #define indirDX { OP_IMREG, indir_dx_reg }
 350
 351 #define Sw { OP_SEG, w_mode }
 352 #define Sv { OP_SEG, v_mode }
 353 #define Ap { OP_DIR, 0 }
 354 #define Ob { OP_OFF64, b_mode }
 355 #define Ov { OP_OFF64, v_mode }
 356 #define Xb { OP_DSreg, eSI_reg }
 357 #define Xv { OP_DSreg, eSI_reg }
 358 #define Xz { OP_DSreg, eSI_reg }
 359 #define Yb { OP_ESreg, eDI_reg }
 360 #define Yv { OP_ESreg, eDI_reg }
 361 #define DSBX { OP_DSreg, eBX_reg }
 362
 363 #define es { OP_REG, es_reg }
 364 #define ss { OP_REG, ss_reg }
 365 #define cs { OP_REG, cs_reg }
 366 #define ds { OP_REG, ds_reg }
 367 #define fs { OP_REG, fs_reg }
 368 #define gs { OP_REG, gs_reg }
 369
 370 #define MX { OP_MMX, 0 }
 371 #define XM { OP_XMM, 0 }
 372 #define XMScalar { OP_XMM, scalar_mode }
 373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 374 #define XMM { OP_XMM, xmm_mode }
 375 #define XMxmmq { OP_XMM, xmmq_mode }
 376 #define EM { OP_EM, v_mode }
 377 #define EMS { OP_EM, v_swap_mode }
 378 #define EMd { OP_EM, d_mode }
 379 #define EMx { OP_EM, x_mode }
 380 #define EXbScalar { OP_EX, b_scalar_mode }
 381 #define EXw { OP_EX, w_mode }
 382 #define EXwScalar { OP_EX, w_scalar_mode }
 383 #define EXd { OP_EX, d_mode }
 384 #define EXdScalar { OP_EX, d_scalar_mode }
 385 #define EXdS { OP_EX, d_swap_mode }
 386 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 387 #define EXq { OP_EX, q_mode }
 388 #define EXqScalar { OP_EX, q_scalar_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 409 #define MS { OP_MS, v_mode }
 410 #define XS { OP_XS, v_mode }
 411 #define EMCq { OP_EMC, q_mode }
 412 #define MXC { OP_MXC, 0 }
 413 #define OPSUF { OP_3DNowSuffix, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define EXdVex { OP_EX_Vex, d_mode }
 427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVex { OP_EX_Vex, q_mode }
 430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVex { OP_XMM_Vex, 0 }
 437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 438 #define XMVexW { OP_XMM_VexW, 0 }
 439 #define XMVexI4 { OP_REG_VexI4, x_mode }
 440 #define PCLMUL { PCLMUL_Fixup, 0 }
 441 #define VZERO { VZERO_Fixup, 0 }
 442 #define VCMP { VCMP_Fixup, 0 }
 443 #define VPCMP { VPCMP_Fixup, 0 }
 444 #define VPCOM { VPCOM_Fixup, 0 }
 445
 446 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 447 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 448
 449 #define XMask { OP_Mask, mask_mode }
 450 #define MaskG { OP_G, mask_mode }
 451 #define MaskE { OP_E, mask_mode }
 452 #define MaskBDE { OP_E, mask_bd_mode }
 453 #define MaskR { OP_R, mask_mode }
 454 #define MaskVex { OP_VEX, mask_mode }
 455
 456 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 457 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 458 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 459 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 460
 461 /* Used handle "rep" prefix for string instructions.  */
 462 #define Xbr { REP_Fixup, eSI_reg }
 463 #define Xvr { REP_Fixup, eSI_reg }
 464 #define Ybr { REP_Fixup, eDI_reg }
 465 #define Yvr { REP_Fixup, eDI_reg }
 466 #define Yzr { REP_Fixup, eDI_reg }
 467 #define indirDXr { REP_Fixup, indir_dx_reg }
 468 #define ALr { REP_Fixup, al_reg }
 469 #define eAXr { REP_Fixup, eAX_reg }
 470
 471 /* Used handle HLE prefix for lockable instructions.  */
 472 #define Ebh1 { HLE_Fixup1, b_mode }
 473 #define Evh1 { HLE_Fixup1, v_mode }
 474 #define Ebh2 { HLE_Fixup2, b_mode }
 475 #define Evh2 { HLE_Fixup2, v_mode }
 476 #define Ebh3 { HLE_Fixup3, b_mode }
 477 #define Evh3 { HLE_Fixup3, v_mode }
 478
 479 #define BND { BND_Fixup, 0 }
 480 #define NOTRACK { NOTRACK_Fixup, 0 }
 481
 482 #define cond_jump_flag { NULL, cond_jump_mode }
 483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 484
 485 /* bits in sizeflag */
 486 #define SUFFIX_ALWAYS 4
 487 #define AFLAG 2
 488 #define DFLAG 1
 489
 490 enum
 491 {
 492   /* byte operand */
 493   b_mode = 1,
 494   /* byte operand with operand swapped */
 495   b_swap_mode,
 496   /* byte operand, sign extend like 'T' suffix */
 497   b_T_mode,
 498   /* operand size depends on prefixes */
 499   v_mode,
 500   /* operand size depends on prefixes with operand swapped */
 501   v_swap_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   v_bnd_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593   /* operand size depends on the VEX.W bit.  */
 594   vex_w_dq_mode,
 595
 596   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 597   vex_vsib_d_w_dq_mode,
 598   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 599   vex_vsib_d_w_d_mode,
 600   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 601   vex_vsib_q_w_dq_mode,
 602   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 603   vex_vsib_q_w_d_mode,
 604
 605   /* scalar, ignore vector length.  */
 606   scalar_mode,
 607   /* like b_mode, ignore vector length.  */
 608   b_scalar_mode,
 609   /* like w_mode, ignore vector length.  */
 610   w_scalar_mode,
 611   /* like d_mode, ignore vector length.  */
 612   d_scalar_mode,
 613   /* like d_swap_mode, ignore vector length.  */
 614   d_scalar_swap_mode,
 615   /* like q_mode, ignore vector length.  */
 616   q_scalar_mode,
 617   /* like q_swap_mode, ignore vector length.  */
 618   q_scalar_swap_mode,
 619   /* like vex_mode, ignore vector length.  */
 620   vex_scalar_mode,
 621   /* like vex_w_dq_mode, ignore vector length.  */
 622   vex_scalar_w_dq_mode,
 623
 624   /* Static rounding.  */
 625   evex_rounding_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE
 696 };
 697
 698 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 699
 700 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 701 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 702 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 703 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 704 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 705 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 706 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 707 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 708 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 709 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 710 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 711 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 712 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 713 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 714 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 715
 716 enum
 717 {
 718   REG_80 = 0,
 719   REG_81,
 720   REG_83,
 721   REG_8F,
 722   REG_C0,
 723   REG_C1,
 724   REG_C6,
 725   REG_C7,
 726   REG_D0,
 727   REG_D1,
 728   REG_D2,
 729   REG_D3,
 730   REG_F6,
 731   REG_F7,
 732   REG_FE,
 733   REG_FF,
 734   REG_0F00,
 735   REG_0F01,
 736   REG_0F0D,
 737   REG_0F18,
 738   REG_0F1E_MOD_3,
 739   REG_0F71,
 740   REG_0F72,
 741   REG_0F73,
 742   REG_0FA6,
 743   REG_0FA7,
 744   REG_0FAE,
 745   REG_0FBA,
 746   REG_0FC7,
 747   REG_VEX_0F71,
 748   REG_VEX_0F72,
 749   REG_VEX_0F73,
 750   REG_VEX_0FAE,
 751   REG_VEX_0F38F3,
 752   REG_XOP_LWPCB,
 753   REG_XOP_LWP,
 754   REG_XOP_TBM_01,
 755   REG_XOP_TBM_02,
 756
 757   REG_EVEX_0F71,
 758   REG_EVEX_0F72,
 759   REG_EVEX_0F73,
 760   REG_EVEX_0F38C6,
 761   REG_EVEX_0F38C7
 762 };
 763
 764 enum
 765 {
 766   MOD_8D = 0,
 767   MOD_C6_REG_7,
 768   MOD_C7_REG_7,
 769   MOD_FF_REG_3,
 770   MOD_FF_REG_5,
 771   MOD_0F01_REG_0,
 772   MOD_0F01_REG_1,
 773   MOD_0F01_REG_2,
 774   MOD_0F01_REG_3,
 775   MOD_0F01_REG_5,
 776   MOD_0F01_REG_7,
 777   MOD_0F12_PREFIX_0,
 778   MOD_0F13,
 779   MOD_0F16_PREFIX_0,
 780   MOD_0F17,
 781   MOD_0F18_REG_0,
 782   MOD_0F18_REG_1,
 783   MOD_0F18_REG_2,
 784   MOD_0F18_REG_3,
 785   MOD_0F18_REG_4,
 786   MOD_0F18_REG_5,
 787   MOD_0F18_REG_6,
 788   MOD_0F18_REG_7,
 789   MOD_0F1A_PREFIX_0,
 790   MOD_0F1B_PREFIX_0,
 791   MOD_0F1B_PREFIX_1,
 792   MOD_0F1E_PREFIX_1,
 793   MOD_0F24,
 794   MOD_0F26,
 795   MOD_0F2B_PREFIX_0,
 796   MOD_0F2B_PREFIX_1,
 797   MOD_0F2B_PREFIX_2,
 798   MOD_0F2B_PREFIX_3,
 799   MOD_0F51,
 800   MOD_0F71_REG_2,
 801   MOD_0F71_REG_4,
 802   MOD_0F71_REG_6,
 803   MOD_0F72_REG_2,
 804   MOD_0F72_REG_4,
 805   MOD_0F72_REG_6,
 806   MOD_0F73_REG_2,
 807   MOD_0F73_REG_3,
 808   MOD_0F73_REG_6,
 809   MOD_0F73_REG_7,
 810   MOD_0FAE_REG_0,
 811   MOD_0FAE_REG_1,
 812   MOD_0FAE_REG_2,
 813   MOD_0FAE_REG_3,
 814   MOD_0FAE_REG_4,
 815   MOD_0FAE_REG_5,
 816   MOD_0FAE_REG_6,
 817   MOD_0FAE_REG_7,
 818   MOD_0FB2,
 819   MOD_0FB4,
 820   MOD_0FB5,
 821   MOD_0FC3,
 822   MOD_0FC7_REG_3,
 823   MOD_0FC7_REG_4,
 824   MOD_0FC7_REG_5,
 825   MOD_0FC7_REG_6,
 826   MOD_0FC7_REG_7,
 827   MOD_0FD7,
 828   MOD_0FE7_PREFIX_2,
 829   MOD_0FF0_PREFIX_3,
 830   MOD_0F382A_PREFIX_2,
 831   MOD_0F38F5_PREFIX_2,
 832   MOD_0F38F6_PREFIX_0,
 833   MOD_62_32BIT,
 834   MOD_C4_32BIT,
 835   MOD_C5_32BIT,
 836   MOD_VEX_0F12_PREFIX_0,
 837   MOD_VEX_0F13,
 838   MOD_VEX_0F16_PREFIX_0,
 839   MOD_VEX_0F17,
 840   MOD_VEX_0F2B,
 841   MOD_VEX_W_0_0F41_P_0_LEN_1,
 842   MOD_VEX_W_1_0F41_P_0_LEN_1,
 843   MOD_VEX_W_0_0F41_P_2_LEN_1,
 844   MOD_VEX_W_1_0F41_P_2_LEN_1,
 845   MOD_VEX_W_0_0F42_P_0_LEN_1,
 846   MOD_VEX_W_1_0F42_P_0_LEN_1,
 847   MOD_VEX_W_0_0F42_P_2_LEN_1,
 848   MOD_VEX_W_1_0F42_P_2_LEN_1,
 849   MOD_VEX_W_0_0F44_P_0_LEN_1,
 850   MOD_VEX_W_1_0F44_P_0_LEN_1,
 851   MOD_VEX_W_0_0F44_P_2_LEN_1,
 852   MOD_VEX_W_1_0F44_P_2_LEN_1,
 853   MOD_VEX_W_0_0F45_P_0_LEN_1,
 854   MOD_VEX_W_1_0F45_P_0_LEN_1,
 855   MOD_VEX_W_0_0F45_P_2_LEN_1,
 856   MOD_VEX_W_1_0F45_P_2_LEN_1,
 857   MOD_VEX_W_0_0F46_P_0_LEN_1,
 858   MOD_VEX_W_1_0F46_P_0_LEN_1,
 859   MOD_VEX_W_0_0F46_P_2_LEN_1,
 860   MOD_VEX_W_1_0F46_P_2_LEN_1,
 861   MOD_VEX_W_0_0F47_P_0_LEN_1,
 862   MOD_VEX_W_1_0F47_P_0_LEN_1,
 863   MOD_VEX_W_0_0F47_P_2_LEN_1,
 864   MOD_VEX_W_1_0F47_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 868   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 872   MOD_VEX_0F50,
 873   MOD_VEX_0F71_REG_2,
 874   MOD_VEX_0F71_REG_4,
 875   MOD_VEX_0F71_REG_6,
 876   MOD_VEX_0F72_REG_2,
 877   MOD_VEX_0F72_REG_4,
 878   MOD_VEX_0F72_REG_6,
 879   MOD_VEX_0F73_REG_2,
 880   MOD_VEX_0F73_REG_3,
 881   MOD_VEX_0F73_REG_6,
 882   MOD_VEX_0F73_REG_7,
 883   MOD_VEX_W_0_0F91_P_0_LEN_0,
 884   MOD_VEX_W_1_0F91_P_0_LEN_0,
 885   MOD_VEX_W_0_0F91_P_2_LEN_0,
 886   MOD_VEX_W_1_0F91_P_2_LEN_0,
 887   MOD_VEX_W_0_0F92_P_0_LEN_0,
 888   MOD_VEX_W_0_0F92_P_2_LEN_0,
 889   MOD_VEX_W_0_0F92_P_3_LEN_0,
 890   MOD_VEX_W_1_0F92_P_3_LEN_0,
 891   MOD_VEX_W_0_0F93_P_0_LEN_0,
 892   MOD_VEX_W_0_0F93_P_2_LEN_0,
 893   MOD_VEX_W_0_0F93_P_3_LEN_0,
 894   MOD_VEX_W_1_0F93_P_3_LEN_0,
 895   MOD_VEX_W_0_0F98_P_0_LEN_0,
 896   MOD_VEX_W_1_0F98_P_0_LEN_0,
 897   MOD_VEX_W_0_0F98_P_2_LEN_0,
 898   MOD_VEX_W_1_0F98_P_2_LEN_0,
 899   MOD_VEX_W_0_0F99_P_0_LEN_0,
 900   MOD_VEX_W_1_0F99_P_0_LEN_0,
 901   MOD_VEX_W_0_0F99_P_2_LEN_0,
 902   MOD_VEX_W_1_0F99_P_2_LEN_0,
 903   MOD_VEX_0FAE_REG_2,
 904   MOD_VEX_0FAE_REG_3,
 905   MOD_VEX_0FD7_PREFIX_2,
 906   MOD_VEX_0FE7_PREFIX_2,
 907   MOD_VEX_0FF0_PREFIX_3,
 908   MOD_VEX_0F381A_PREFIX_2,
 909   MOD_VEX_0F382A_PREFIX_2,
 910   MOD_VEX_0F382C_PREFIX_2,
 911   MOD_VEX_0F382D_PREFIX_2,
 912   MOD_VEX_0F382E_PREFIX_2,
 913   MOD_VEX_0F382F_PREFIX_2,
 914   MOD_VEX_0F385A_PREFIX_2,
 915   MOD_VEX_0F388C_PREFIX_2,
 916   MOD_VEX_0F388E_PREFIX_2,
 917   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 925
 926   MOD_EVEX_0F10_PREFIX_1,
 927   MOD_EVEX_0F10_PREFIX_3,
 928   MOD_EVEX_0F11_PREFIX_1,
 929   MOD_EVEX_0F11_PREFIX_3,
 930   MOD_EVEX_0F12_PREFIX_0,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F38C6_REG_1,
 933   MOD_EVEX_0F38C6_REG_2,
 934   MOD_EVEX_0F38C6_REG_5,
 935   MOD_EVEX_0F38C6_REG_6,
 936   MOD_EVEX_0F38C7_REG_1,
 937   MOD_EVEX_0F38C7_REG_2,
 938   MOD_EVEX_0F38C7_REG_5,
 939   MOD_EVEX_0F38C7_REG_6
 940 };
 941
 942 enum
 943 {
 944   RM_C6_REG_7 = 0,
 945   RM_C7_REG_7,
 946   RM_0F01_REG_0,
 947   RM_0F01_REG_1,
 948   RM_0F01_REG_2,
 949   RM_0F01_REG_3,
 950   RM_0F01_REG_5,
 951   RM_0F01_REG_7,
 952   RM_0F1E_MOD_3_REG_7,
 953   RM_0FAE_REG_6,
 954   RM_0FAE_REG_7
 955 };
 956
 957 enum
 958 {
 959   PREFIX_90 = 0,
 960   PREFIX_MOD_0_0F01_REG_5,
 961   PREFIX_MOD_3_0F01_REG_5_RM_0,
 962   PREFIX_MOD_3_0F01_REG_5_RM_2,
 963   PREFIX_0F09,
 964   PREFIX_0F10,
 965   PREFIX_0F11,
 966   PREFIX_0F12,
 967   PREFIX_0F16,
 968   PREFIX_0F1A,
 969   PREFIX_0F1B,
 970   PREFIX_0F1E,
 971   PREFIX_0F2A,
 972   PREFIX_0F2B,
 973   PREFIX_0F2C,
 974   PREFIX_0F2D,
 975   PREFIX_0F2E,
 976   PREFIX_0F2F,
 977   PREFIX_0F51,
 978   PREFIX_0F52,
 979   PREFIX_0F53,
 980   PREFIX_0F58,
 981   PREFIX_0F59,
 982   PREFIX_0F5A,
 983   PREFIX_0F5B,
 984   PREFIX_0F5C,
 985   PREFIX_0F5D,
 986   PREFIX_0F5E,
 987   PREFIX_0F5F,
 988   PREFIX_0F60,
 989   PREFIX_0F61,
 990   PREFIX_0F62,
 991   PREFIX_0F6C,
 992   PREFIX_0F6D,
 993   PREFIX_0F6F,
 994   PREFIX_0F70,
 995   PREFIX_0F73_REG_3,
 996   PREFIX_0F73_REG_7,
 997   PREFIX_0F78,
 998   PREFIX_0F79,
 999   PREFIX_0F7C,
1000   PREFIX_0F7D,
1001   PREFIX_0F7E,
1002   PREFIX_0F7F,
1003   PREFIX_0FAE_REG_0,
1004   PREFIX_0FAE_REG_1,
1005   PREFIX_0FAE_REG_2,
1006   PREFIX_0FAE_REG_3,
1007   PREFIX_MOD_0_0FAE_REG_4,
1008   PREFIX_MOD_3_0FAE_REG_4,
1009   PREFIX_MOD_0_0FAE_REG_5,
1010   PREFIX_MOD_3_0FAE_REG_5,
1011   PREFIX_0FAE_REG_6,
1012   PREFIX_0FAE_REG_7,
1013   PREFIX_0FB8,
1014   PREFIX_0FBC,
1015   PREFIX_0FBD,
1016   PREFIX_0FC2,
1017   PREFIX_MOD_0_0FC3,
1018   PREFIX_MOD_0_0FC7_REG_6,
1019   PREFIX_MOD_3_0FC7_REG_6,
1020   PREFIX_MOD_3_0FC7_REG_7,
1021   PREFIX_0FD0,
1022   PREFIX_0FD6,
1023   PREFIX_0FE6,
1024   PREFIX_0FE7,
1025   PREFIX_0FF0,
1026   PREFIX_0FF7,
1027   PREFIX_0F3810,
1028   PREFIX_0F3814,
1029   PREFIX_0F3815,
1030   PREFIX_0F3817,
1031   PREFIX_0F3820,
1032   PREFIX_0F3821,
1033   PREFIX_0F3822,
1034   PREFIX_0F3823,
1035   PREFIX_0F3824,
1036   PREFIX_0F3825,
1037   PREFIX_0F3828,
1038   PREFIX_0F3829,
1039   PREFIX_0F382A,
1040   PREFIX_0F382B,
1041   PREFIX_0F3830,
1042   PREFIX_0F3831,
1043   PREFIX_0F3832,
1044   PREFIX_0F3833,
1045   PREFIX_0F3834,
1046   PREFIX_0F3835,
1047   PREFIX_0F3837,
1048   PREFIX_0F3838,
1049   PREFIX_0F3839,
1050   PREFIX_0F383A,
1051   PREFIX_0F383B,
1052   PREFIX_0F383C,
1053   PREFIX_0F383D,
1054   PREFIX_0F383E,
1055   PREFIX_0F383F,
1056   PREFIX_0F3840,
1057   PREFIX_0F3841,
1058   PREFIX_0F3880,
1059   PREFIX_0F3881,
1060   PREFIX_0F3882,
1061   PREFIX_0F38C8,
1062   PREFIX_0F38C9,
1063   PREFIX_0F38CA,
1064   PREFIX_0F38CB,
1065   PREFIX_0F38CC,
1066   PREFIX_0F38CD,
1067   PREFIX_0F38CF,
1068   PREFIX_0F38DB,
1069   PREFIX_0F38DC,
1070   PREFIX_0F38DD,
1071   PREFIX_0F38DE,
1072   PREFIX_0F38DF,
1073   PREFIX_0F38F0,
1074   PREFIX_0F38F1,
1075   PREFIX_0F38F5,
1076   PREFIX_0F38F6,
1077   PREFIX_0F3A08,
1078   PREFIX_0F3A09,
1079   PREFIX_0F3A0A,
1080   PREFIX_0F3A0B,
1081   PREFIX_0F3A0C,
1082   PREFIX_0F3A0D,
1083   PREFIX_0F3A0E,
1084   PREFIX_0F3A14,
1085   PREFIX_0F3A15,
1086   PREFIX_0F3A16,
1087   PREFIX_0F3A17,
1088   PREFIX_0F3A20,
1089   PREFIX_0F3A21,
1090   PREFIX_0F3A22,
1091   PREFIX_0F3A40,
1092   PREFIX_0F3A41,
1093   PREFIX_0F3A42,
1094   PREFIX_0F3A44,
1095   PREFIX_0F3A60,
1096   PREFIX_0F3A61,
1097   PREFIX_0F3A62,
1098   PREFIX_0F3A63,
1099   PREFIX_0F3ACC,
1100   PREFIX_0F3ACE,
1101   PREFIX_0F3ACF,
1102   PREFIX_0F3ADF,
1103   PREFIX_VEX_0F10,
1104   PREFIX_VEX_0F11,
1105   PREFIX_VEX_0F12,
1106   PREFIX_VEX_0F16,
1107   PREFIX_VEX_0F2A,
1108   PREFIX_VEX_0F2C,
1109   PREFIX_VEX_0F2D,
1110   PREFIX_VEX_0F2E,
1111   PREFIX_VEX_0F2F,
1112   PREFIX_VEX_0F41,
1113   PREFIX_VEX_0F42,
1114   PREFIX_VEX_0F44,
1115   PREFIX_VEX_0F45,
1116   PREFIX_VEX_0F46,
1117   PREFIX_VEX_0F47,
1118   PREFIX_VEX_0F4A,
1119   PREFIX_VEX_0F4B,
1120   PREFIX_VEX_0F51,
1121   PREFIX_VEX_0F52,
1122   PREFIX_VEX_0F53,
1123   PREFIX_VEX_0F58,
1124   PREFIX_VEX_0F59,
1125   PREFIX_VEX_0F5A,
1126   PREFIX_VEX_0F5B,
1127   PREFIX_VEX_0F5C,
1128   PREFIX_VEX_0F5D,
1129   PREFIX_VEX_0F5E,
1130   PREFIX_VEX_0F5F,
1131   PREFIX_VEX_0F60,
1132   PREFIX_VEX_0F61,
1133   PREFIX_VEX_0F62,
1134   PREFIX_VEX_0F63,
1135   PREFIX_VEX_0F64,
1136   PREFIX_VEX_0F65,
1137   PREFIX_VEX_0F66,
1138   PREFIX_VEX_0F67,
1139   PREFIX_VEX_0F68,
1140   PREFIX_VEX_0F69,
1141   PREFIX_VEX_0F6A,
1142   PREFIX_VEX_0F6B,
1143   PREFIX_VEX_0F6C,
1144   PREFIX_VEX_0F6D,
1145   PREFIX_VEX_0F6E,
1146   PREFIX_VEX_0F6F,
1147   PREFIX_VEX_0F70,
1148   PREFIX_VEX_0F71_REG_2,
1149   PREFIX_VEX_0F71_REG_4,
1150   PREFIX_VEX_0F71_REG_6,
1151   PREFIX_VEX_0F72_REG_2,
1152   PREFIX_VEX_0F72_REG_4,
1153   PREFIX_VEX_0F72_REG_6,
1154   PREFIX_VEX_0F73_REG_2,
1155   PREFIX_VEX_0F73_REG_3,
1156   PREFIX_VEX_0F73_REG_6,
1157   PREFIX_VEX_0F73_REG_7,
1158   PREFIX_VEX_0F74,
1159   PREFIX_VEX_0F75,
1160   PREFIX_VEX_0F76,
1161   PREFIX_VEX_0F77,
1162   PREFIX_VEX_0F7C,
1163   PREFIX_VEX_0F7D,
1164   PREFIX_VEX_0F7E,
1165   PREFIX_VEX_0F7F,
1166   PREFIX_VEX_0F90,
1167   PREFIX_VEX_0F91,
1168   PREFIX_VEX_0F92,
1169   PREFIX_VEX_0F93,
1170   PREFIX_VEX_0F98,
1171   PREFIX_VEX_0F99,
1172   PREFIX_VEX_0FC2,
1173   PREFIX_VEX_0FC4,
1174   PREFIX_VEX_0FC5,
1175   PREFIX_VEX_0FD0,
1176   PREFIX_VEX_0FD1,
1177   PREFIX_VEX_0FD2,
1178   PREFIX_VEX_0FD3,
1179   PREFIX_VEX_0FD4,
1180   PREFIX_VEX_0FD5,
1181   PREFIX_VEX_0FD6,
1182   PREFIX_VEX_0FD7,
1183   PREFIX_VEX_0FD8,
1184   PREFIX_VEX_0FD9,
1185   PREFIX_VEX_0FDA,
1186   PREFIX_VEX_0FDB,
1187   PREFIX_VEX_0FDC,
1188   PREFIX_VEX_0FDD,
1189   PREFIX_VEX_0FDE,
1190   PREFIX_VEX_0FDF,
1191   PREFIX_VEX_0FE0,
1192   PREFIX_VEX_0FE1,
1193   PREFIX_VEX_0FE2,
1194   PREFIX_VEX_0FE3,
1195   PREFIX_VEX_0FE4,
1196   PREFIX_VEX_0FE5,
1197   PREFIX_VEX_0FE6,
1198   PREFIX_VEX_0FE7,
1199   PREFIX_VEX_0FE8,
1200   PREFIX_VEX_0FE9,
1201   PREFIX_VEX_0FEA,
1202   PREFIX_VEX_0FEB,
1203   PREFIX_VEX_0FEC,
1204   PREFIX_VEX_0FED,
1205   PREFIX_VEX_0FEE,
1206   PREFIX_VEX_0FEF,
1207   PREFIX_VEX_0FF0,
1208   PREFIX_VEX_0FF1,
1209   PREFIX_VEX_0FF2,
1210   PREFIX_VEX_0FF3,
1211   PREFIX_VEX_0FF4,
1212   PREFIX_VEX_0FF5,
1213   PREFIX_VEX_0FF6,
1214   PREFIX_VEX_0FF7,
1215   PREFIX_VEX_0FF8,
1216   PREFIX_VEX_0FF9,
1217   PREFIX_VEX_0FFA,
1218   PREFIX_VEX_0FFB,
1219   PREFIX_VEX_0FFC,
1220   PREFIX_VEX_0FFD,
1221   PREFIX_VEX_0FFE,
1222   PREFIX_VEX_0F3800,
1223   PREFIX_VEX_0F3801,
1224   PREFIX_VEX_0F3802,
1225   PREFIX_VEX_0F3803,
1226   PREFIX_VEX_0F3804,
1227   PREFIX_VEX_0F3805,
1228   PREFIX_VEX_0F3806,
1229   PREFIX_VEX_0F3807,
1230   PREFIX_VEX_0F3808,
1231   PREFIX_VEX_0F3809,
1232   PREFIX_VEX_0F380A,
1233   PREFIX_VEX_0F380B,
1234   PREFIX_VEX_0F380C,
1235   PREFIX_VEX_0F380D,
1236   PREFIX_VEX_0F380E,
1237   PREFIX_VEX_0F380F,
1238   PREFIX_VEX_0F3813,
1239   PREFIX_VEX_0F3816,
1240   PREFIX_VEX_0F3817,
1241   PREFIX_VEX_0F3818,
1242   PREFIX_VEX_0F3819,
1243   PREFIX_VEX_0F381A,
1244   PREFIX_VEX_0F381C,
1245   PREFIX_VEX_0F381D,
1246   PREFIX_VEX_0F381E,
1247   PREFIX_VEX_0F3820,
1248   PREFIX_VEX_0F3821,
1249   PREFIX_VEX_0F3822,
1250   PREFIX_VEX_0F3823,
1251   PREFIX_VEX_0F3824,
1252   PREFIX_VEX_0F3825,
1253   PREFIX_VEX_0F3828,
1254   PREFIX_VEX_0F3829,
1255   PREFIX_VEX_0F382A,
1256   PREFIX_VEX_0F382B,
1257   PREFIX_VEX_0F382C,
1258   PREFIX_VEX_0F382D,
1259   PREFIX_VEX_0F382E,
1260   PREFIX_VEX_0F382F,
1261   PREFIX_VEX_0F3830,
1262   PREFIX_VEX_0F3831,
1263   PREFIX_VEX_0F3832,
1264   PREFIX_VEX_0F3833,
1265   PREFIX_VEX_0F3834,
1266   PREFIX_VEX_0F3835,
1267   PREFIX_VEX_0F3836,
1268   PREFIX_VEX_0F3837,
1269   PREFIX_VEX_0F3838,
1270   PREFIX_VEX_0F3839,
1271   PREFIX_VEX_0F383A,
1272   PREFIX_VEX_0F383B,
1273   PREFIX_VEX_0F383C,
1274   PREFIX_VEX_0F383D,
1275   PREFIX_VEX_0F383E,
1276   PREFIX_VEX_0F383F,
1277   PREFIX_VEX_0F3840,
1278   PREFIX_VEX_0F3841,
1279   PREFIX_VEX_0F3845,
1280   PREFIX_VEX_0F3846,
1281   PREFIX_VEX_0F3847,
1282   PREFIX_VEX_0F3858,
1283   PREFIX_VEX_0F3859,
1284   PREFIX_VEX_0F385A,
1285   PREFIX_VEX_0F3878,
1286   PREFIX_VEX_0F3879,
1287   PREFIX_VEX_0F388C,
1288   PREFIX_VEX_0F388E,
1289   PREFIX_VEX_0F3890,
1290   PREFIX_VEX_0F3891,
1291   PREFIX_VEX_0F3892,
1292   PREFIX_VEX_0F3893,
1293   PREFIX_VEX_0F3896,
1294   PREFIX_VEX_0F3897,
1295   PREFIX_VEX_0F3898,
1296   PREFIX_VEX_0F3899,
1297   PREFIX_VEX_0F389A,
1298   PREFIX_VEX_0F389B,
1299   PREFIX_VEX_0F389C,
1300   PREFIX_VEX_0F389D,
1301   PREFIX_VEX_0F389E,
1302   PREFIX_VEX_0F389F,
1303   PREFIX_VEX_0F38A6,
1304   PREFIX_VEX_0F38A7,
1305   PREFIX_VEX_0F38A8,
1306   PREFIX_VEX_0F38A9,
1307   PREFIX_VEX_0F38AA,
1308   PREFIX_VEX_0F38AB,
1309   PREFIX_VEX_0F38AC,
1310   PREFIX_VEX_0F38AD,
1311   PREFIX_VEX_0F38AE,
1312   PREFIX_VEX_0F38AF,
1313   PREFIX_VEX_0F38B6,
1314   PREFIX_VEX_0F38B7,
1315   PREFIX_VEX_0F38B8,
1316   PREFIX_VEX_0F38B9,
1317   PREFIX_VEX_0F38BA,
1318   PREFIX_VEX_0F38BB,
1319   PREFIX_VEX_0F38BC,
1320   PREFIX_VEX_0F38BD,
1321   PREFIX_VEX_0F38BE,
1322   PREFIX_VEX_0F38BF,
1323   PREFIX_VEX_0F38CF,
1324   PREFIX_VEX_0F38DB,
1325   PREFIX_VEX_0F38DC,
1326   PREFIX_VEX_0F38DD,
1327   PREFIX_VEX_0F38DE,
1328   PREFIX_VEX_0F38DF,
1329   PREFIX_VEX_0F38F2,
1330   PREFIX_VEX_0F38F3_REG_1,
1331   PREFIX_VEX_0F38F3_REG_2,
1332   PREFIX_VEX_0F38F3_REG_3,
1333   PREFIX_VEX_0F38F5,
1334   PREFIX_VEX_0F38F6,
1335   PREFIX_VEX_0F38F7,
1336   PREFIX_VEX_0F3A00,
1337   PREFIX_VEX_0F3A01,
1338   PREFIX_VEX_0F3A02,
1339   PREFIX_VEX_0F3A04,
1340   PREFIX_VEX_0F3A05,
1341   PREFIX_VEX_0F3A06,
1342   PREFIX_VEX_0F3A08,
1343   PREFIX_VEX_0F3A09,
1344   PREFIX_VEX_0F3A0A,
1345   PREFIX_VEX_0F3A0B,
1346   PREFIX_VEX_0F3A0C,
1347   PREFIX_VEX_0F3A0D,
1348   PREFIX_VEX_0F3A0E,
1349   PREFIX_VEX_0F3A0F,
1350   PREFIX_VEX_0F3A14,
1351   PREFIX_VEX_0F3A15,
1352   PREFIX_VEX_0F3A16,
1353   PREFIX_VEX_0F3A17,
1354   PREFIX_VEX_0F3A18,
1355   PREFIX_VEX_0F3A19,
1356   PREFIX_VEX_0F3A1D,
1357   PREFIX_VEX_0F3A20,
1358   PREFIX_VEX_0F3A21,
1359   PREFIX_VEX_0F3A22,
1360   PREFIX_VEX_0F3A30,
1361   PREFIX_VEX_0F3A31,
1362   PREFIX_VEX_0F3A32,
1363   PREFIX_VEX_0F3A33,
1364   PREFIX_VEX_0F3A38,
1365   PREFIX_VEX_0F3A39,
1366   PREFIX_VEX_0F3A40,
1367   PREFIX_VEX_0F3A41,
1368   PREFIX_VEX_0F3A42,
1369   PREFIX_VEX_0F3A44,
1370   PREFIX_VEX_0F3A46,
1371   PREFIX_VEX_0F3A48,
1372   PREFIX_VEX_0F3A49,
1373   PREFIX_VEX_0F3A4A,
1374   PREFIX_VEX_0F3A4B,
1375   PREFIX_VEX_0F3A4C,
1376   PREFIX_VEX_0F3A5C,
1377   PREFIX_VEX_0F3A5D,
1378   PREFIX_VEX_0F3A5E,
1379   PREFIX_VEX_0F3A5F,
1380   PREFIX_VEX_0F3A60,
1381   PREFIX_VEX_0F3A61,
1382   PREFIX_VEX_0F3A62,
1383   PREFIX_VEX_0F3A63,
1384   PREFIX_VEX_0F3A68,
1385   PREFIX_VEX_0F3A69,
1386   PREFIX_VEX_0F3A6A,
1387   PREFIX_VEX_0F3A6B,
1388   PREFIX_VEX_0F3A6C,
1389   PREFIX_VEX_0F3A6D,
1390   PREFIX_VEX_0F3A6E,
1391   PREFIX_VEX_0F3A6F,
1392   PREFIX_VEX_0F3A78,
1393   PREFIX_VEX_0F3A79,
1394   PREFIX_VEX_0F3A7A,
1395   PREFIX_VEX_0F3A7B,
1396   PREFIX_VEX_0F3A7C,
1397   PREFIX_VEX_0F3A7D,
1398   PREFIX_VEX_0F3A7E,
1399   PREFIX_VEX_0F3A7F,
1400   PREFIX_VEX_0F3ACE,
1401   PREFIX_VEX_0F3ACF,
1402   PREFIX_VEX_0F3ADF,
1403   PREFIX_VEX_0F3AF0,
1404
1405   PREFIX_EVEX_0F10,
1406   PREFIX_EVEX_0F11,
1407   PREFIX_EVEX_0F12,
1408   PREFIX_EVEX_0F13,
1409   PREFIX_EVEX_0F14,
1410   PREFIX_EVEX_0F15,
1411   PREFIX_EVEX_0F16,
1412   PREFIX_EVEX_0F17,
1413   PREFIX_EVEX_0F28,
1414   PREFIX_EVEX_0F29,
1415   PREFIX_EVEX_0F2A,
1416   PREFIX_EVEX_0F2B,
1417   PREFIX_EVEX_0F2C,
1418   PREFIX_EVEX_0F2D,
1419   PREFIX_EVEX_0F2E,
1420   PREFIX_EVEX_0F2F,
1421   PREFIX_EVEX_0F51,
1422   PREFIX_EVEX_0F54,
1423   PREFIX_EVEX_0F55,
1424   PREFIX_EVEX_0F56,
1425   PREFIX_EVEX_0F57,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F60,
1435   PREFIX_EVEX_0F61,
1436   PREFIX_EVEX_0F62,
1437   PREFIX_EVEX_0F63,
1438   PREFIX_EVEX_0F64,
1439   PREFIX_EVEX_0F65,
1440   PREFIX_EVEX_0F66,
1441   PREFIX_EVEX_0F67,
1442   PREFIX_EVEX_0F68,
1443   PREFIX_EVEX_0F69,
1444   PREFIX_EVEX_0F6A,
1445   PREFIX_EVEX_0F6B,
1446   PREFIX_EVEX_0F6C,
1447   PREFIX_EVEX_0F6D,
1448   PREFIX_EVEX_0F6E,
1449   PREFIX_EVEX_0F6F,
1450   PREFIX_EVEX_0F70,
1451   PREFIX_EVEX_0F71_REG_2,
1452   PREFIX_EVEX_0F71_REG_4,
1453   PREFIX_EVEX_0F71_REG_6,
1454   PREFIX_EVEX_0F72_REG_0,
1455   PREFIX_EVEX_0F72_REG_1,
1456   PREFIX_EVEX_0F72_REG_2,
1457   PREFIX_EVEX_0F72_REG_4,
1458   PREFIX_EVEX_0F72_REG_6,
1459   PREFIX_EVEX_0F73_REG_2,
1460   PREFIX_EVEX_0F73_REG_3,
1461   PREFIX_EVEX_0F73_REG_6,
1462   PREFIX_EVEX_0F73_REG_7,
1463   PREFIX_EVEX_0F74,
1464   PREFIX_EVEX_0F75,
1465   PREFIX_EVEX_0F76,
1466   PREFIX_EVEX_0F78,
1467   PREFIX_EVEX_0F79,
1468   PREFIX_EVEX_0F7A,
1469   PREFIX_EVEX_0F7B,
1470   PREFIX_EVEX_0F7E,
1471   PREFIX_EVEX_0F7F,
1472   PREFIX_EVEX_0FC2,
1473   PREFIX_EVEX_0FC4,
1474   PREFIX_EVEX_0FC5,
1475   PREFIX_EVEX_0FC6,
1476   PREFIX_EVEX_0FD1,
1477   PREFIX_EVEX_0FD2,
1478   PREFIX_EVEX_0FD3,
1479   PREFIX_EVEX_0FD4,
1480   PREFIX_EVEX_0FD5,
1481   PREFIX_EVEX_0FD6,
1482   PREFIX_EVEX_0FD8,
1483   PREFIX_EVEX_0FD9,
1484   PREFIX_EVEX_0FDA,
1485   PREFIX_EVEX_0FDB,
1486   PREFIX_EVEX_0FDC,
1487   PREFIX_EVEX_0FDD,
1488   PREFIX_EVEX_0FDE,
1489   PREFIX_EVEX_0FDF,
1490   PREFIX_EVEX_0FE0,
1491   PREFIX_EVEX_0FE1,
1492   PREFIX_EVEX_0FE2,
1493   PREFIX_EVEX_0FE3,
1494   PREFIX_EVEX_0FE4,
1495   PREFIX_EVEX_0FE5,
1496   PREFIX_EVEX_0FE6,
1497   PREFIX_EVEX_0FE7,
1498   PREFIX_EVEX_0FE8,
1499   PREFIX_EVEX_0FE9,
1500   PREFIX_EVEX_0FEA,
1501   PREFIX_EVEX_0FEB,
1502   PREFIX_EVEX_0FEC,
1503   PREFIX_EVEX_0FED,
1504   PREFIX_EVEX_0FEE,
1505   PREFIX_EVEX_0FEF,
1506   PREFIX_EVEX_0FF1,
1507   PREFIX_EVEX_0FF2,
1508   PREFIX_EVEX_0FF3,
1509   PREFIX_EVEX_0FF4,
1510   PREFIX_EVEX_0FF5,
1511   PREFIX_EVEX_0FF6,
1512   PREFIX_EVEX_0FF8,
1513   PREFIX_EVEX_0FF9,
1514   PREFIX_EVEX_0FFA,
1515   PREFIX_EVEX_0FFB,
1516   PREFIX_EVEX_0FFC,
1517   PREFIX_EVEX_0FFD,
1518   PREFIX_EVEX_0FFE,
1519   PREFIX_EVEX_0F3800,
1520   PREFIX_EVEX_0F3804,
1521   PREFIX_EVEX_0F380B,
1522   PREFIX_EVEX_0F380C,
1523   PREFIX_EVEX_0F380D,
1524   PREFIX_EVEX_0F3810,
1525   PREFIX_EVEX_0F3811,
1526   PREFIX_EVEX_0F3812,
1527   PREFIX_EVEX_0F3813,
1528   PREFIX_EVEX_0F3814,
1529   PREFIX_EVEX_0F3815,
1530   PREFIX_EVEX_0F3816,
1531   PREFIX_EVEX_0F3818,
1532   PREFIX_EVEX_0F3819,
1533   PREFIX_EVEX_0F381A,
1534   PREFIX_EVEX_0F381B,
1535   PREFIX_EVEX_0F381C,
1536   PREFIX_EVEX_0F381D,
1537   PREFIX_EVEX_0F381E,
1538   PREFIX_EVEX_0F381F,
1539   PREFIX_EVEX_0F3820,
1540   PREFIX_EVEX_0F3821,
1541   PREFIX_EVEX_0F3822,
1542   PREFIX_EVEX_0F3823,
1543   PREFIX_EVEX_0F3824,
1544   PREFIX_EVEX_0F3825,
1545   PREFIX_EVEX_0F3826,
1546   PREFIX_EVEX_0F3827,
1547   PREFIX_EVEX_0F3828,
1548   PREFIX_EVEX_0F3829,
1549   PREFIX_EVEX_0F382A,
1550   PREFIX_EVEX_0F382B,
1551   PREFIX_EVEX_0F382C,
1552   PREFIX_EVEX_0F382D,
1553   PREFIX_EVEX_0F3830,
1554   PREFIX_EVEX_0F3831,
1555   PREFIX_EVEX_0F3832,
1556   PREFIX_EVEX_0F3833,
1557   PREFIX_EVEX_0F3834,
1558   PREFIX_EVEX_0F3835,
1559   PREFIX_EVEX_0F3836,
1560   PREFIX_EVEX_0F3837,
1561   PREFIX_EVEX_0F3838,
1562   PREFIX_EVEX_0F3839,
1563   PREFIX_EVEX_0F383A,
1564   PREFIX_EVEX_0F383B,
1565   PREFIX_EVEX_0F383C,
1566   PREFIX_EVEX_0F383D,
1567   PREFIX_EVEX_0F383E,
1568   PREFIX_EVEX_0F383F,
1569   PREFIX_EVEX_0F3840,
1570   PREFIX_EVEX_0F3842,
1571   PREFIX_EVEX_0F3843,
1572   PREFIX_EVEX_0F3844,
1573   PREFIX_EVEX_0F3845,
1574   PREFIX_EVEX_0F3846,
1575   PREFIX_EVEX_0F3847,
1576   PREFIX_EVEX_0F384C,
1577   PREFIX_EVEX_0F384D,
1578   PREFIX_EVEX_0F384E,
1579   PREFIX_EVEX_0F384F,
1580   PREFIX_EVEX_0F3850,
1581   PREFIX_EVEX_0F3851,
1582   PREFIX_EVEX_0F3852,
1583   PREFIX_EVEX_0F3853,
1584   PREFIX_EVEX_0F3854,
1585   PREFIX_EVEX_0F3855,
1586   PREFIX_EVEX_0F3858,
1587   PREFIX_EVEX_0F3859,
1588   PREFIX_EVEX_0F385A,
1589   PREFIX_EVEX_0F385B,
1590   PREFIX_EVEX_0F3862,
1591   PREFIX_EVEX_0F3863,
1592   PREFIX_EVEX_0F3864,
1593   PREFIX_EVEX_0F3865,
1594   PREFIX_EVEX_0F3866,
1595   PREFIX_EVEX_0F3870,
1596   PREFIX_EVEX_0F3871,
1597   PREFIX_EVEX_0F3872,
1598   PREFIX_EVEX_0F3873,
1599   PREFIX_EVEX_0F3875,
1600   PREFIX_EVEX_0F3876,
1601   PREFIX_EVEX_0F3877,
1602   PREFIX_EVEX_0F3878,
1603   PREFIX_EVEX_0F3879,
1604   PREFIX_EVEX_0F387A,
1605   PREFIX_EVEX_0F387B,
1606   PREFIX_EVEX_0F387C,
1607   PREFIX_EVEX_0F387D,
1608   PREFIX_EVEX_0F387E,
1609   PREFIX_EVEX_0F387F,
1610   PREFIX_EVEX_0F3883,
1611   PREFIX_EVEX_0F3888,
1612   PREFIX_EVEX_0F3889,
1613   PREFIX_EVEX_0F388A,
1614   PREFIX_EVEX_0F388B,
1615   PREFIX_EVEX_0F388D,
1616   PREFIX_EVEX_0F388F,
1617   PREFIX_EVEX_0F3890,
1618   PREFIX_EVEX_0F3891,
1619   PREFIX_EVEX_0F3892,
1620   PREFIX_EVEX_0F3893,
1621   PREFIX_EVEX_0F3896,
1622   PREFIX_EVEX_0F3897,
1623   PREFIX_EVEX_0F3898,
1624   PREFIX_EVEX_0F3899,
1625   PREFIX_EVEX_0F389A,
1626   PREFIX_EVEX_0F389B,
1627   PREFIX_EVEX_0F389C,
1628   PREFIX_EVEX_0F389D,
1629   PREFIX_EVEX_0F389E,
1630   PREFIX_EVEX_0F389F,
1631   PREFIX_EVEX_0F38A0,
1632   PREFIX_EVEX_0F38A1,
1633   PREFIX_EVEX_0F38A2,
1634   PREFIX_EVEX_0F38A3,
1635   PREFIX_EVEX_0F38A6,
1636   PREFIX_EVEX_0F38A7,
1637   PREFIX_EVEX_0F38A8,
1638   PREFIX_EVEX_0F38A9,
1639   PREFIX_EVEX_0F38AA,
1640   PREFIX_EVEX_0F38AB,
1641   PREFIX_EVEX_0F38AC,
1642   PREFIX_EVEX_0F38AD,
1643   PREFIX_EVEX_0F38AE,
1644   PREFIX_EVEX_0F38AF,
1645   PREFIX_EVEX_0F38B4,
1646   PREFIX_EVEX_0F38B5,
1647   PREFIX_EVEX_0F38B6,
1648   PREFIX_EVEX_0F38B7,
1649   PREFIX_EVEX_0F38B8,
1650   PREFIX_EVEX_0F38B9,
1651   PREFIX_EVEX_0F38BA,
1652   PREFIX_EVEX_0F38BB,
1653   PREFIX_EVEX_0F38BC,
1654   PREFIX_EVEX_0F38BD,
1655   PREFIX_EVEX_0F38BE,
1656   PREFIX_EVEX_0F38BF,
1657   PREFIX_EVEX_0F38C4,
1658   PREFIX_EVEX_0F38C6_REG_1,
1659   PREFIX_EVEX_0F38C6_REG_2,
1660   PREFIX_EVEX_0F38C6_REG_5,
1661   PREFIX_EVEX_0F38C6_REG_6,
1662   PREFIX_EVEX_0F38C7_REG_1,
1663   PREFIX_EVEX_0F38C7_REG_2,
1664   PREFIX_EVEX_0F38C7_REG_5,
1665   PREFIX_EVEX_0F38C7_REG_6,
1666   PREFIX_EVEX_0F38C8,
1667   PREFIX_EVEX_0F38CA,
1668   PREFIX_EVEX_0F38CB,
1669   PREFIX_EVEX_0F38CC,
1670   PREFIX_EVEX_0F38CD,
1671   PREFIX_EVEX_0F38CF,
1672   PREFIX_EVEX_0F38DC,
1673   PREFIX_EVEX_0F38DD,
1674   PREFIX_EVEX_0F38DE,
1675   PREFIX_EVEX_0F38DF,
1676
1677   PREFIX_EVEX_0F3A00,
1678   PREFIX_EVEX_0F3A01,
1679   PREFIX_EVEX_0F3A03,
1680   PREFIX_EVEX_0F3A04,
1681   PREFIX_EVEX_0F3A05,
1682   PREFIX_EVEX_0F3A08,
1683   PREFIX_EVEX_0F3A09,
1684   PREFIX_EVEX_0F3A0A,
1685   PREFIX_EVEX_0F3A0B,
1686   PREFIX_EVEX_0F3A0F,
1687   PREFIX_EVEX_0F3A14,
1688   PREFIX_EVEX_0F3A15,
1689   PREFIX_EVEX_0F3A16,
1690   PREFIX_EVEX_0F3A17,
1691   PREFIX_EVEX_0F3A18,
1692   PREFIX_EVEX_0F3A19,
1693   PREFIX_EVEX_0F3A1A,
1694   PREFIX_EVEX_0F3A1B,
1695   PREFIX_EVEX_0F3A1D,
1696   PREFIX_EVEX_0F3A1E,
1697   PREFIX_EVEX_0F3A1F,
1698   PREFIX_EVEX_0F3A20,
1699   PREFIX_EVEX_0F3A21,
1700   PREFIX_EVEX_0F3A22,
1701   PREFIX_EVEX_0F3A23,
1702   PREFIX_EVEX_0F3A25,
1703   PREFIX_EVEX_0F3A26,
1704   PREFIX_EVEX_0F3A27,
1705   PREFIX_EVEX_0F3A38,
1706   PREFIX_EVEX_0F3A39,
1707   PREFIX_EVEX_0F3A3A,
1708   PREFIX_EVEX_0F3A3B,
1709   PREFIX_EVEX_0F3A3E,
1710   PREFIX_EVEX_0F3A3F,
1711   PREFIX_EVEX_0F3A42,
1712   PREFIX_EVEX_0F3A43,
1713   PREFIX_EVEX_0F3A44,
1714   PREFIX_EVEX_0F3A50,
1715   PREFIX_EVEX_0F3A51,
1716   PREFIX_EVEX_0F3A54,
1717   PREFIX_EVEX_0F3A55,
1718   PREFIX_EVEX_0F3A56,
1719   PREFIX_EVEX_0F3A57,
1720   PREFIX_EVEX_0F3A66,
1721   PREFIX_EVEX_0F3A67,
1722   PREFIX_EVEX_0F3A70,
1723   PREFIX_EVEX_0F3A71,
1724   PREFIX_EVEX_0F3A72,
1725   PREFIX_EVEX_0F3A73,
1726   PREFIX_EVEX_0F3ACE,
1727   PREFIX_EVEX_0F3ACF
1728 };
1729
1730 enum
1731 {
1732   X86_64_06 = 0,
1733   X86_64_07,
1734   X86_64_0D,
1735   X86_64_16,
1736   X86_64_17,
1737   X86_64_1E,
1738   X86_64_1F,
1739   X86_64_27,
1740   X86_64_2F,
1741   X86_64_37,
1742   X86_64_3F,
1743   X86_64_60,
1744   X86_64_61,
1745   X86_64_62,
1746   X86_64_63,
1747   X86_64_6D,
1748   X86_64_6F,
1749   X86_64_82,
1750   X86_64_9A,
1751   X86_64_C4,
1752   X86_64_C5,
1753   X86_64_CE,
1754   X86_64_D4,
1755   X86_64_D5,
1756   X86_64_E8,
1757   X86_64_E9,
1758   X86_64_EA,
1759   X86_64_0F01_REG_0,
1760   X86_64_0F01_REG_1,
1761   X86_64_0F01_REG_2,
1762   X86_64_0F01_REG_3
1763 };
1764
1765 enum
1766 {
1767   THREE_BYTE_0F38 = 0,
1768   THREE_BYTE_0F3A
1769 };
1770
1771 enum
1772 {
1773   XOP_08 = 0,
1774   XOP_09,
1775   XOP_0A
1776 };
1777
1778 enum
1779 {
1780   VEX_0F = 0,
1781   VEX_0F38,
1782   VEX_0F3A
1783 };
1784
1785 enum
1786 {
1787   EVEX_0F = 0,
1788   EVEX_0F38,
1789   EVEX_0F3A
1790 };
1791
1792 enum
1793 {
1794   VEX_LEN_0F10_P_1 = 0,
1795   VEX_LEN_0F10_P_3,
1796   VEX_LEN_0F11_P_1,
1797   VEX_LEN_0F11_P_3,
1798   VEX_LEN_0F12_P_0_M_0,
1799   VEX_LEN_0F12_P_0_M_1,
1800   VEX_LEN_0F12_P_2,
1801   VEX_LEN_0F13_M_0,
1802   VEX_LEN_0F16_P_0_M_0,
1803   VEX_LEN_0F16_P_0_M_1,
1804   VEX_LEN_0F16_P_2,
1805   VEX_LEN_0F17_M_0,
1806   VEX_LEN_0F2A_P_1,
1807   VEX_LEN_0F2A_P_3,
1808   VEX_LEN_0F2C_P_1,
1809   VEX_LEN_0F2C_P_3,
1810   VEX_LEN_0F2D_P_1,
1811   VEX_LEN_0F2D_P_3,
1812   VEX_LEN_0F2E_P_0,
1813   VEX_LEN_0F2E_P_2,
1814   VEX_LEN_0F2F_P_0,
1815   VEX_LEN_0F2F_P_2,
1816   VEX_LEN_0F41_P_0,
1817   VEX_LEN_0F41_P_2,
1818   VEX_LEN_0F42_P_0,
1819   VEX_LEN_0F42_P_2,
1820   VEX_LEN_0F44_P_0,
1821   VEX_LEN_0F44_P_2,
1822   VEX_LEN_0F45_P_0,
1823   VEX_LEN_0F45_P_2,
1824   VEX_LEN_0F46_P_0,
1825   VEX_LEN_0F46_P_2,
1826   VEX_LEN_0F47_P_0,
1827   VEX_LEN_0F47_P_2,
1828   VEX_LEN_0F4A_P_0,
1829   VEX_LEN_0F4A_P_2,
1830   VEX_LEN_0F4B_P_0,
1831   VEX_LEN_0F4B_P_2,
1832   VEX_LEN_0F51_P_1,
1833   VEX_LEN_0F51_P_3,
1834   VEX_LEN_0F52_P_1,
1835   VEX_LEN_0F53_P_1,
1836   VEX_LEN_0F58_P_1,
1837   VEX_LEN_0F58_P_3,
1838   VEX_LEN_0F59_P_1,
1839   VEX_LEN_0F59_P_3,
1840   VEX_LEN_0F5A_P_1,
1841   VEX_LEN_0F5A_P_3,
1842   VEX_LEN_0F5C_P_1,
1843   VEX_LEN_0F5C_P_3,
1844   VEX_LEN_0F5D_P_1,
1845   VEX_LEN_0F5D_P_3,
1846   VEX_LEN_0F5E_P_1,
1847   VEX_LEN_0F5E_P_3,
1848   VEX_LEN_0F5F_P_1,
1849   VEX_LEN_0F5F_P_3,
1850   VEX_LEN_0F6E_P_2,
1851   VEX_LEN_0F7E_P_1,
1852   VEX_LEN_0F7E_P_2,
1853   VEX_LEN_0F90_P_0,
1854   VEX_LEN_0F90_P_2,
1855   VEX_LEN_0F91_P_0,
1856   VEX_LEN_0F91_P_2,
1857   VEX_LEN_0F92_P_0,
1858   VEX_LEN_0F92_P_2,
1859   VEX_LEN_0F92_P_3,
1860   VEX_LEN_0F93_P_0,
1861   VEX_LEN_0F93_P_2,
1862   VEX_LEN_0F93_P_3,
1863   VEX_LEN_0F98_P_0,
1864   VEX_LEN_0F98_P_2,
1865   VEX_LEN_0F99_P_0,
1866   VEX_LEN_0F99_P_2,
1867   VEX_LEN_0FAE_R_2_M_0,
1868   VEX_LEN_0FAE_R_3_M_0,
1869   VEX_LEN_0FC2_P_1,
1870   VEX_LEN_0FC2_P_3,
1871   VEX_LEN_0FC4_P_2,
1872   VEX_LEN_0FC5_P_2,
1873   VEX_LEN_0FD6_P_2,
1874   VEX_LEN_0FF7_P_2,
1875   VEX_LEN_0F3816_P_2,
1876   VEX_LEN_0F3819_P_2,
1877   VEX_LEN_0F381A_P_2_M_0,
1878   VEX_LEN_0F3836_P_2,
1879   VEX_LEN_0F3841_P_2,
1880   VEX_LEN_0F385A_P_2_M_0,
1881   VEX_LEN_0F38DB_P_2,
1882   VEX_LEN_0F38F2_P_0,
1883   VEX_LEN_0F38F3_R_1_P_0,
1884   VEX_LEN_0F38F3_R_2_P_0,
1885   VEX_LEN_0F38F3_R_3_P_0,
1886   VEX_LEN_0F38F5_P_0,
1887   VEX_LEN_0F38F5_P_1,
1888   VEX_LEN_0F38F5_P_3,
1889   VEX_LEN_0F38F6_P_3,
1890   VEX_LEN_0F38F7_P_0,
1891   VEX_LEN_0F38F7_P_1,
1892   VEX_LEN_0F38F7_P_2,
1893   VEX_LEN_0F38F7_P_3,
1894   VEX_LEN_0F3A00_P_2,
1895   VEX_LEN_0F3A01_P_2,
1896   VEX_LEN_0F3A06_P_2,
1897   VEX_LEN_0F3A0A_P_2,
1898   VEX_LEN_0F3A0B_P_2,
1899   VEX_LEN_0F3A14_P_2,
1900   VEX_LEN_0F3A15_P_2,
1901   VEX_LEN_0F3A16_P_2,
1902   VEX_LEN_0F3A17_P_2,
1903   VEX_LEN_0F3A18_P_2,
1904   VEX_LEN_0F3A19_P_2,
1905   VEX_LEN_0F3A20_P_2,
1906   VEX_LEN_0F3A21_P_2,
1907   VEX_LEN_0F3A22_P_2,
1908   VEX_LEN_0F3A30_P_2,
1909   VEX_LEN_0F3A31_P_2,
1910   VEX_LEN_0F3A32_P_2,
1911   VEX_LEN_0F3A33_P_2,
1912   VEX_LEN_0F3A38_P_2,
1913   VEX_LEN_0F3A39_P_2,
1914   VEX_LEN_0F3A41_P_2,
1915   VEX_LEN_0F3A46_P_2,
1916   VEX_LEN_0F3A60_P_2,
1917   VEX_LEN_0F3A61_P_2,
1918   VEX_LEN_0F3A62_P_2,
1919   VEX_LEN_0F3A63_P_2,
1920   VEX_LEN_0F3A6A_P_2,
1921   VEX_LEN_0F3A6B_P_2,
1922   VEX_LEN_0F3A6E_P_2,
1923   VEX_LEN_0F3A6F_P_2,
1924   VEX_LEN_0F3A7A_P_2,
1925   VEX_LEN_0F3A7B_P_2,
1926   VEX_LEN_0F3A7E_P_2,
1927   VEX_LEN_0F3A7F_P_2,
1928   VEX_LEN_0F3ADF_P_2,
1929   VEX_LEN_0F3AF0_P_3,
1930   VEX_LEN_0FXOP_08_CC,
1931   VEX_LEN_0FXOP_08_CD,
1932   VEX_LEN_0FXOP_08_CE,
1933   VEX_LEN_0FXOP_08_CF,
1934   VEX_LEN_0FXOP_08_EC,
1935   VEX_LEN_0FXOP_08_ED,
1936   VEX_LEN_0FXOP_08_EE,
1937   VEX_LEN_0FXOP_08_EF,
1938   VEX_LEN_0FXOP_09_80,
1939   VEX_LEN_0FXOP_09_81
1940 };
1941
1942 enum
1943 {
1944   VEX_W_0F10_P_0 = 0,
1945   VEX_W_0F10_P_1,
1946   VEX_W_0F10_P_2,
1947   VEX_W_0F10_P_3,
1948   VEX_W_0F11_P_0,
1949   VEX_W_0F11_P_1,
1950   VEX_W_0F11_P_2,
1951   VEX_W_0F11_P_3,
1952   VEX_W_0F12_P_0_M_0,
1953   VEX_W_0F12_P_0_M_1,
1954   VEX_W_0F12_P_1,
1955   VEX_W_0F12_P_2,
1956   VEX_W_0F12_P_3,
1957   VEX_W_0F13_M_0,
1958   VEX_W_0F14,
1959   VEX_W_0F15,
1960   VEX_W_0F16_P_0_M_0,
1961   VEX_W_0F16_P_0_M_1,
1962   VEX_W_0F16_P_1,
1963   VEX_W_0F16_P_2,
1964   VEX_W_0F17_M_0,
1965   VEX_W_0F28,
1966   VEX_W_0F29,
1967   VEX_W_0F2B_M_0,
1968   VEX_W_0F2E_P_0,
1969   VEX_W_0F2E_P_2,
1970   VEX_W_0F2F_P_0,
1971   VEX_W_0F2F_P_2,
1972   VEX_W_0F41_P_0_LEN_1,
1973   VEX_W_0F41_P_2_LEN_1,
1974   VEX_W_0F42_P_0_LEN_1,
1975   VEX_W_0F42_P_2_LEN_1,
1976   VEX_W_0F44_P_0_LEN_0,
1977   VEX_W_0F44_P_2_LEN_0,
1978   VEX_W_0F45_P_0_LEN_1,
1979   VEX_W_0F45_P_2_LEN_1,
1980   VEX_W_0F46_P_0_LEN_1,
1981   VEX_W_0F46_P_2_LEN_1,
1982   VEX_W_0F47_P_0_LEN_1,
1983   VEX_W_0F47_P_2_LEN_1,
1984   VEX_W_0F4A_P_0_LEN_1,
1985   VEX_W_0F4A_P_2_LEN_1,
1986   VEX_W_0F4B_P_0_LEN_1,
1987   VEX_W_0F4B_P_2_LEN_1,
1988   VEX_W_0F50_M_0,
1989   VEX_W_0F51_P_0,
1990   VEX_W_0F51_P_1,
1991   VEX_W_0F51_P_2,
1992   VEX_W_0F51_P_3,
1993   VEX_W_0F52_P_0,
1994   VEX_W_0F52_P_1,
1995   VEX_W_0F53_P_0,
1996   VEX_W_0F53_P_1,
1997   VEX_W_0F58_P_0,
1998   VEX_W_0F58_P_1,
1999   VEX_W_0F58_P_2,
2000   VEX_W_0F58_P_3,
2001   VEX_W_0F59_P_0,
2002   VEX_W_0F59_P_1,
2003   VEX_W_0F59_P_2,
2004   VEX_W_0F59_P_3,
2005   VEX_W_0F5A_P_0,
2006   VEX_W_0F5A_P_1,
2007   VEX_W_0F5A_P_3,
2008   VEX_W_0F5B_P_0,
2009   VEX_W_0F5B_P_1,
2010   VEX_W_0F5B_P_2,
2011   VEX_W_0F5C_P_0,
2012   VEX_W_0F5C_P_1,
2013   VEX_W_0F5C_P_2,
2014   VEX_W_0F5C_P_3,
2015   VEX_W_0F5D_P_0,
2016   VEX_W_0F5D_P_1,
2017   VEX_W_0F5D_P_2,
2018   VEX_W_0F5D_P_3,
2019   VEX_W_0F5E_P_0,
2020   VEX_W_0F5E_P_1,
2021   VEX_W_0F5E_P_2,
2022   VEX_W_0F5E_P_3,
2023   VEX_W_0F5F_P_0,
2024   VEX_W_0F5F_P_1,
2025   VEX_W_0F5F_P_2,
2026   VEX_W_0F5F_P_3,
2027   VEX_W_0F60_P_2,
2028   VEX_W_0F61_P_2,
2029   VEX_W_0F62_P_2,
2030   VEX_W_0F63_P_2,
2031   VEX_W_0F64_P_2,
2032   VEX_W_0F65_P_2,
2033   VEX_W_0F66_P_2,
2034   VEX_W_0F67_P_2,
2035   VEX_W_0F68_P_2,
2036   VEX_W_0F69_P_2,
2037   VEX_W_0F6A_P_2,
2038   VEX_W_0F6B_P_2,
2039   VEX_W_0F6C_P_2,
2040   VEX_W_0F6D_P_2,
2041   VEX_W_0F6F_P_1,
2042   VEX_W_0F6F_P_2,
2043   VEX_W_0F70_P_1,
2044   VEX_W_0F70_P_2,
2045   VEX_W_0F70_P_3,
2046   VEX_W_0F71_R_2_P_2,
2047   VEX_W_0F71_R_4_P_2,
2048   VEX_W_0F71_R_6_P_2,
2049   VEX_W_0F72_R_2_P_2,
2050   VEX_W_0F72_R_4_P_2,
2051   VEX_W_0F72_R_6_P_2,
2052   VEX_W_0F73_R_2_P_2,
2053   VEX_W_0F73_R_3_P_2,
2054   VEX_W_0F73_R_6_P_2,
2055   VEX_W_0F73_R_7_P_2,
2056   VEX_W_0F74_P_2,
2057   VEX_W_0F75_P_2,
2058   VEX_W_0F76_P_2,
2059   VEX_W_0F77_P_0,
2060   VEX_W_0F7C_P_2,
2061   VEX_W_0F7C_P_3,
2062   VEX_W_0F7D_P_2,
2063   VEX_W_0F7D_P_3,
2064   VEX_W_0F7E_P_1,
2065   VEX_W_0F7F_P_1,
2066   VEX_W_0F7F_P_2,
2067   VEX_W_0F90_P_0_LEN_0,
2068   VEX_W_0F90_P_2_LEN_0,
2069   VEX_W_0F91_P_0_LEN_0,
2070   VEX_W_0F91_P_2_LEN_0,
2071   VEX_W_0F92_P_0_LEN_0,
2072   VEX_W_0F92_P_2_LEN_0,
2073   VEX_W_0F92_P_3_LEN_0,
2074   VEX_W_0F93_P_0_LEN_0,
2075   VEX_W_0F93_P_2_LEN_0,
2076   VEX_W_0F93_P_3_LEN_0,
2077   VEX_W_0F98_P_0_LEN_0,
2078   VEX_W_0F98_P_2_LEN_0,
2079   VEX_W_0F99_P_0_LEN_0,
2080   VEX_W_0F99_P_2_LEN_0,
2081   VEX_W_0FAE_R_2_M_0,
2082   VEX_W_0FAE_R_3_M_0,
2083   VEX_W_0FC2_P_0,
2084   VEX_W_0FC2_P_1,
2085   VEX_W_0FC2_P_2,
2086   VEX_W_0FC2_P_3,
2087   VEX_W_0FC4_P_2,
2088   VEX_W_0FC5_P_2,
2089   VEX_W_0FD0_P_2,
2090   VEX_W_0FD0_P_3,
2091   VEX_W_0FD1_P_2,
2092   VEX_W_0FD2_P_2,
2093   VEX_W_0FD3_P_2,
2094   VEX_W_0FD4_P_2,
2095   VEX_W_0FD5_P_2,
2096   VEX_W_0FD6_P_2,
2097   VEX_W_0FD7_P_2_M_1,
2098   VEX_W_0FD8_P_2,
2099   VEX_W_0FD9_P_2,
2100   VEX_W_0FDA_P_2,
2101   VEX_W_0FDB_P_2,
2102   VEX_W_0FDC_P_2,
2103   VEX_W_0FDD_P_2,
2104   VEX_W_0FDE_P_2,
2105   VEX_W_0FDF_P_2,
2106   VEX_W_0FE0_P_2,
2107   VEX_W_0FE1_P_2,
2108   VEX_W_0FE2_P_2,
2109   VEX_W_0FE3_P_2,
2110   VEX_W_0FE4_P_2,
2111   VEX_W_0FE5_P_2,
2112   VEX_W_0FE6_P_1,
2113   VEX_W_0FE6_P_2,
2114   VEX_W_0FE6_P_3,
2115   VEX_W_0FE7_P_2_M_0,
2116   VEX_W_0FE8_P_2,
2117   VEX_W_0FE9_P_2,
2118   VEX_W_0FEA_P_2,
2119   VEX_W_0FEB_P_2,
2120   VEX_W_0FEC_P_2,
2121   VEX_W_0FED_P_2,
2122   VEX_W_0FEE_P_2,
2123   VEX_W_0FEF_P_2,
2124   VEX_W_0FF0_P_3_M_0,
2125   VEX_W_0FF1_P_2,
2126   VEX_W_0FF2_P_2,
2127   VEX_W_0FF3_P_2,
2128   VEX_W_0FF4_P_2,
2129   VEX_W_0FF5_P_2,
2130   VEX_W_0FF6_P_2,
2131   VEX_W_0FF7_P_2,
2132   VEX_W_0FF8_P_2,
2133   VEX_W_0FF9_P_2,
2134   VEX_W_0FFA_P_2,
2135   VEX_W_0FFB_P_2,
2136   VEX_W_0FFC_P_2,
2137   VEX_W_0FFD_P_2,
2138   VEX_W_0FFE_P_2,
2139   VEX_W_0F3800_P_2,
2140   VEX_W_0F3801_P_2,
2141   VEX_W_0F3802_P_2,
2142   VEX_W_0F3803_P_2,
2143   VEX_W_0F3804_P_2,
2144   VEX_W_0F3805_P_2,
2145   VEX_W_0F3806_P_2,
2146   VEX_W_0F3807_P_2,
2147   VEX_W_0F3808_P_2,
2148   VEX_W_0F3809_P_2,
2149   VEX_W_0F380A_P_2,
2150   VEX_W_0F380B_P_2,
2151   VEX_W_0F380C_P_2,
2152   VEX_W_0F380D_P_2,
2153   VEX_W_0F380E_P_2,
2154   VEX_W_0F380F_P_2,
2155   VEX_W_0F3816_P_2,
2156   VEX_W_0F3817_P_2,
2157   VEX_W_0F3818_P_2,
2158   VEX_W_0F3819_P_2,
2159   VEX_W_0F381A_P_2_M_0,
2160   VEX_W_0F381C_P_2,
2161   VEX_W_0F381D_P_2,
2162   VEX_W_0F381E_P_2,
2163   VEX_W_0F3820_P_2,
2164   VEX_W_0F3821_P_2,
2165   VEX_W_0F3822_P_2,
2166   VEX_W_0F3823_P_2,
2167   VEX_W_0F3824_P_2,
2168   VEX_W_0F3825_P_2,
2169   VEX_W_0F3828_P_2,
2170   VEX_W_0F3829_P_2,
2171   VEX_W_0F382A_P_2_M_0,
2172   VEX_W_0F382B_P_2,
2173   VEX_W_0F382C_P_2_M_0,
2174   VEX_W_0F382D_P_2_M_0,
2175   VEX_W_0F382E_P_2_M_0,
2176   VEX_W_0F382F_P_2_M_0,
2177   VEX_W_0F3830_P_2,
2178   VEX_W_0F3831_P_2,
2179   VEX_W_0F3832_P_2,
2180   VEX_W_0F3833_P_2,
2181   VEX_W_0F3834_P_2,
2182   VEX_W_0F3835_P_2,
2183   VEX_W_0F3836_P_2,
2184   VEX_W_0F3837_P_2,
2185   VEX_W_0F3838_P_2,
2186   VEX_W_0F3839_P_2,
2187   VEX_W_0F383A_P_2,
2188   VEX_W_0F383B_P_2,
2189   VEX_W_0F383C_P_2,
2190   VEX_W_0F383D_P_2,
2191   VEX_W_0F383E_P_2,
2192   VEX_W_0F383F_P_2,
2193   VEX_W_0F3840_P_2,
2194   VEX_W_0F3841_P_2,
2195   VEX_W_0F3846_P_2,
2196   VEX_W_0F3858_P_2,
2197   VEX_W_0F3859_P_2,
2198   VEX_W_0F385A_P_2_M_0,
2199   VEX_W_0F3878_P_2,
2200   VEX_W_0F3879_P_2,
2201   VEX_W_0F38CF_P_2,
2202   VEX_W_0F38DB_P_2,
2203   VEX_W_0F3A00_P_2,
2204   VEX_W_0F3A01_P_2,
2205   VEX_W_0F3A02_P_2,
2206   VEX_W_0F3A04_P_2,
2207   VEX_W_0F3A05_P_2,
2208   VEX_W_0F3A06_P_2,
2209   VEX_W_0F3A08_P_2,
2210   VEX_W_0F3A09_P_2,
2211   VEX_W_0F3A0A_P_2,
2212   VEX_W_0F3A0B_P_2,
2213   VEX_W_0F3A0C_P_2,
2214   VEX_W_0F3A0D_P_2,
2215   VEX_W_0F3A0E_P_2,
2216   VEX_W_0F3A0F_P_2,
2217   VEX_W_0F3A14_P_2,
2218   VEX_W_0F3A15_P_2,
2219   VEX_W_0F3A18_P_2,
2220   VEX_W_0F3A19_P_2,
2221   VEX_W_0F3A20_P_2,
2222   VEX_W_0F3A21_P_2,
2223   VEX_W_0F3A30_P_2_LEN_0,
2224   VEX_W_0F3A31_P_2_LEN_0,
2225   VEX_W_0F3A32_P_2_LEN_0,
2226   VEX_W_0F3A33_P_2_LEN_0,
2227   VEX_W_0F3A38_P_2,
2228   VEX_W_0F3A39_P_2,
2229   VEX_W_0F3A40_P_2,
2230   VEX_W_0F3A41_P_2,
2231   VEX_W_0F3A42_P_2,
2232   VEX_W_0F3A46_P_2,
2233   VEX_W_0F3A48_P_2,
2234   VEX_W_0F3A49_P_2,
2235   VEX_W_0F3A4A_P_2,
2236   VEX_W_0F3A4B_P_2,
2237   VEX_W_0F3A4C_P_2,
2238   VEX_W_0F3A62_P_2,
2239   VEX_W_0F3A63_P_2,
2240   VEX_W_0F3ACE_P_2,
2241   VEX_W_0F3ACF_P_2,
2242   VEX_W_0F3ADF_P_2,
2243
2244   EVEX_W_0F10_P_0,
2245   EVEX_W_0F10_P_1_M_0,
2246   EVEX_W_0F10_P_1_M_1,
2247   EVEX_W_0F10_P_2,
2248   EVEX_W_0F10_P_3_M_0,
2249   EVEX_W_0F10_P_3_M_1,
2250   EVEX_W_0F11_P_0,
2251   EVEX_W_0F11_P_1_M_0,
2252   EVEX_W_0F11_P_1_M_1,
2253   EVEX_W_0F11_P_2,
2254   EVEX_W_0F11_P_3_M_0,
2255   EVEX_W_0F11_P_3_M_1,
2256   EVEX_W_0F12_P_0_M_0,
2257   EVEX_W_0F12_P_0_M_1,
2258   EVEX_W_0F12_P_1,
2259   EVEX_W_0F12_P_2,
2260   EVEX_W_0F12_P_3,
2261   EVEX_W_0F13_P_0,
2262   EVEX_W_0F13_P_2,
2263   EVEX_W_0F14_P_0,
2264   EVEX_W_0F14_P_2,
2265   EVEX_W_0F15_P_0,
2266   EVEX_W_0F15_P_2,
2267   EVEX_W_0F16_P_0_M_0,
2268   EVEX_W_0F16_P_0_M_1,
2269   EVEX_W_0F16_P_1,
2270   EVEX_W_0F16_P_2,
2271   EVEX_W_0F17_P_0,
2272   EVEX_W_0F17_P_2,
2273   EVEX_W_0F28_P_0,
2274   EVEX_W_0F28_P_2,
2275   EVEX_W_0F29_P_0,
2276   EVEX_W_0F29_P_2,
2277   EVEX_W_0F2A_P_1,
2278   EVEX_W_0F2A_P_3,
2279   EVEX_W_0F2B_P_0,
2280   EVEX_W_0F2B_P_2,
2281   EVEX_W_0F2E_P_0,
2282   EVEX_W_0F2E_P_2,
2283   EVEX_W_0F2F_P_0,
2284   EVEX_W_0F2F_P_2,
2285   EVEX_W_0F51_P_0,
2286   EVEX_W_0F51_P_1,
2287   EVEX_W_0F51_P_2,
2288   EVEX_W_0F51_P_3,
2289   EVEX_W_0F54_P_0,
2290   EVEX_W_0F54_P_2,
2291   EVEX_W_0F55_P_0,
2292   EVEX_W_0F55_P_2,
2293   EVEX_W_0F56_P_0,
2294   EVEX_W_0F56_P_2,
2295   EVEX_W_0F57_P_0,
2296   EVEX_W_0F57_P_2,
2297   EVEX_W_0F58_P_0,
2298   EVEX_W_0F58_P_1,
2299   EVEX_W_0F58_P_2,
2300   EVEX_W_0F58_P_3,
2301   EVEX_W_0F59_P_0,
2302   EVEX_W_0F59_P_1,
2303   EVEX_W_0F59_P_2,
2304   EVEX_W_0F59_P_3,
2305   EVEX_W_0F5A_P_0,
2306   EVEX_W_0F5A_P_1,
2307   EVEX_W_0F5A_P_2,
2308   EVEX_W_0F5A_P_3,
2309   EVEX_W_0F5B_P_0,
2310   EVEX_W_0F5B_P_1,
2311   EVEX_W_0F5B_P_2,
2312   EVEX_W_0F5C_P_0,
2313   EVEX_W_0F5C_P_1,
2314   EVEX_W_0F5C_P_2,
2315   EVEX_W_0F5C_P_3,
2316   EVEX_W_0F5D_P_0,
2317   EVEX_W_0F5D_P_1,
2318   EVEX_W_0F5D_P_2,
2319   EVEX_W_0F5D_P_3,
2320   EVEX_W_0F5E_P_0,
2321   EVEX_W_0F5E_P_1,
2322   EVEX_W_0F5E_P_2,
2323   EVEX_W_0F5E_P_3,
2324   EVEX_W_0F5F_P_0,
2325   EVEX_W_0F5F_P_1,
2326   EVEX_W_0F5F_P_2,
2327   EVEX_W_0F5F_P_3,
2328   EVEX_W_0F62_P_2,
2329   EVEX_W_0F66_P_2,
2330   EVEX_W_0F6A_P_2,
2331   EVEX_W_0F6B_P_2,
2332   EVEX_W_0F6C_P_2,
2333   EVEX_W_0F6D_P_2,
2334   EVEX_W_0F6E_P_2,
2335   EVEX_W_0F6F_P_1,
2336   EVEX_W_0F6F_P_2,
2337   EVEX_W_0F6F_P_3,
2338   EVEX_W_0F70_P_2,
2339   EVEX_W_0F72_R_2_P_2,
2340   EVEX_W_0F72_R_6_P_2,
2341   EVEX_W_0F73_R_2_P_2,
2342   EVEX_W_0F73_R_6_P_2,
2343   EVEX_W_0F76_P_2,
2344   EVEX_W_0F78_P_0,
2345   EVEX_W_0F78_P_2,
2346   EVEX_W_0F79_P_0,
2347   EVEX_W_0F79_P_2,
2348   EVEX_W_0F7A_P_1,
2349   EVEX_W_0F7A_P_2,
2350   EVEX_W_0F7A_P_3,
2351   EVEX_W_0F7B_P_1,
2352   EVEX_W_0F7B_P_2,
2353   EVEX_W_0F7B_P_3,
2354   EVEX_W_0F7E_P_1,
2355   EVEX_W_0F7E_P_2,
2356   EVEX_W_0F7F_P_1,
2357   EVEX_W_0F7F_P_2,
2358   EVEX_W_0F7F_P_3,
2359   EVEX_W_0FC2_P_0,
2360   EVEX_W_0FC2_P_1,
2361   EVEX_W_0FC2_P_2,
2362   EVEX_W_0FC2_P_3,
2363   EVEX_W_0FC6_P_0,
2364   EVEX_W_0FC6_P_2,
2365   EVEX_W_0FD2_P_2,
2366   EVEX_W_0FD3_P_2,
2367   EVEX_W_0FD4_P_2,
2368   EVEX_W_0FD6_P_2,
2369   EVEX_W_0FE6_P_1,
2370   EVEX_W_0FE6_P_2,
2371   EVEX_W_0FE6_P_3,
2372   EVEX_W_0FE7_P_2,
2373   EVEX_W_0FF2_P_2,
2374   EVEX_W_0FF3_P_2,
2375   EVEX_W_0FF4_P_2,
2376   EVEX_W_0FFA_P_2,
2377   EVEX_W_0FFB_P_2,
2378   EVEX_W_0FFE_P_2,
2379   EVEX_W_0F380C_P_2,
2380   EVEX_W_0F380D_P_2,
2381   EVEX_W_0F3810_P_1,
2382   EVEX_W_0F3810_P_2,
2383   EVEX_W_0F3811_P_1,
2384   EVEX_W_0F3811_P_2,
2385   EVEX_W_0F3812_P_1,
2386   EVEX_W_0F3812_P_2,
2387   EVEX_W_0F3813_P_1,
2388   EVEX_W_0F3813_P_2,
2389   EVEX_W_0F3814_P_1,
2390   EVEX_W_0F3815_P_1,
2391   EVEX_W_0F3818_P_2,
2392   EVEX_W_0F3819_P_2,
2393   EVEX_W_0F381A_P_2,
2394   EVEX_W_0F381B_P_2,
2395   EVEX_W_0F381E_P_2,
2396   EVEX_W_0F381F_P_2,
2397   EVEX_W_0F3820_P_1,
2398   EVEX_W_0F3821_P_1,
2399   EVEX_W_0F3822_P_1,
2400   EVEX_W_0F3823_P_1,
2401   EVEX_W_0F3824_P_1,
2402   EVEX_W_0F3825_P_1,
2403   EVEX_W_0F3825_P_2,
2404   EVEX_W_0F3826_P_1,
2405   EVEX_W_0F3826_P_2,
2406   EVEX_W_0F3828_P_1,
2407   EVEX_W_0F3828_P_2,
2408   EVEX_W_0F3829_P_1,
2409   EVEX_W_0F3829_P_2,
2410   EVEX_W_0F382A_P_1,
2411   EVEX_W_0F382A_P_2,
2412   EVEX_W_0F382B_P_2,
2413   EVEX_W_0F3830_P_1,
2414   EVEX_W_0F3831_P_1,
2415   EVEX_W_0F3832_P_1,
2416   EVEX_W_0F3833_P_1,
2417   EVEX_W_0F3834_P_1,
2418   EVEX_W_0F3835_P_1,
2419   EVEX_W_0F3835_P_2,
2420   EVEX_W_0F3837_P_2,
2421   EVEX_W_0F3838_P_1,
2422   EVEX_W_0F3839_P_1,
2423   EVEX_W_0F383A_P_1,
2424   EVEX_W_0F3840_P_2,
2425   EVEX_W_0F3854_P_2,
2426   EVEX_W_0F3855_P_2,
2427   EVEX_W_0F3858_P_2,
2428   EVEX_W_0F3859_P_2,
2429   EVEX_W_0F385A_P_2,
2430   EVEX_W_0F385B_P_2,
2431   EVEX_W_0F3862_P_2,
2432   EVEX_W_0F3863_P_2,
2433   EVEX_W_0F3866_P_2,
2434   EVEX_W_0F3870_P_2,
2435   EVEX_W_0F3871_P_2,
2436   EVEX_W_0F3872_P_2,
2437   EVEX_W_0F3873_P_2,
2438   EVEX_W_0F3875_P_2,
2439   EVEX_W_0F3878_P_2,
2440   EVEX_W_0F3879_P_2,
2441   EVEX_W_0F387A_P_2,
2442   EVEX_W_0F387B_P_2,
2443   EVEX_W_0F387D_P_2,
2444   EVEX_W_0F3883_P_2,
2445   EVEX_W_0F388D_P_2,
2446   EVEX_W_0F3891_P_2,
2447   EVEX_W_0F3893_P_2,
2448   EVEX_W_0F38A1_P_2,
2449   EVEX_W_0F38A3_P_2,
2450   EVEX_W_0F38C7_R_1_P_2,
2451   EVEX_W_0F38C7_R_2_P_2,
2452   EVEX_W_0F38C7_R_5_P_2,
2453   EVEX_W_0F38C7_R_6_P_2,
2454
2455   EVEX_W_0F3A00_P_2,
2456   EVEX_W_0F3A01_P_2,
2457   EVEX_W_0F3A04_P_2,
2458   EVEX_W_0F3A05_P_2,
2459   EVEX_W_0F3A08_P_2,
2460   EVEX_W_0F3A09_P_2,
2461   EVEX_W_0F3A0A_P_2,
2462   EVEX_W_0F3A0B_P_2,
2463   EVEX_W_0F3A16_P_2,
2464   EVEX_W_0F3A18_P_2,
2465   EVEX_W_0F3A19_P_2,
2466   EVEX_W_0F3A1A_P_2,
2467   EVEX_W_0F3A1B_P_2,
2468   EVEX_W_0F3A1D_P_2,
2469   EVEX_W_0F3A21_P_2,
2470   EVEX_W_0F3A22_P_2,
2471   EVEX_W_0F3A23_P_2,
2472   EVEX_W_0F3A38_P_2,
2473   EVEX_W_0F3A39_P_2,
2474   EVEX_W_0F3A3A_P_2,
2475   EVEX_W_0F3A3B_P_2,
2476   EVEX_W_0F3A3E_P_2,
2477   EVEX_W_0F3A3F_P_2,
2478   EVEX_W_0F3A42_P_2,
2479   EVEX_W_0F3A43_P_2,
2480   EVEX_W_0F3A50_P_2,
2481   EVEX_W_0F3A51_P_2,
2482   EVEX_W_0F3A56_P_2,
2483   EVEX_W_0F3A57_P_2,
2484   EVEX_W_0F3A66_P_2,
2485   EVEX_W_0F3A67_P_2,
2486   EVEX_W_0F3A70_P_2,
2487   EVEX_W_0F3A71_P_2,
2488   EVEX_W_0F3A72_P_2,
2489   EVEX_W_0F3A73_P_2,
2490   EVEX_W_0F3ACE_P_2,
2491   EVEX_W_0F3ACF_P_2
2492 };
2493
2494 typedef void (*op_rtn) (int bytemode, int sizeflag);
2495
2496 struct dis386 {
2497   const char *name;
2498   struct
2499     {
2500       op_rtn rtn;
2501       int bytemode;
2502     } op[MAX_OPERANDS];
2503   unsigned int prefix_requirement;
2504 };
2505
2506 /* Upper case letters in the instruction names here are macros.
2507    'A' => print 'b' if no register operands or suffix_always is true
2508    'B' => print 'b' if suffix_always is true
2509    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2510           size prefix
2511    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2512           suffix_always is true
2513    'E' => print 'e' if 32-bit form of jcxz
2514    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2515    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2516    'H' => print ",pt" or ",pn" branch hint
2517    'I' => honor following macro letter even in Intel mode (implemented only
2518           for some of the macro letters)
2519    'J' => print 'l'
2520    'K' => print 'd' or 'q' if rex prefix is present.
2521    'L' => print 'l' if suffix_always is true
2522    'M' => print 'r' if intel_mnemonic is false.
2523    'N' => print 'n' if instruction has no wait "prefix"
2524    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2525    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2526           or suffix_always is true.  print 'q' if rex prefix is present.
2527    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2528           is true
2529    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2530    'S' => print 'w', 'l' or 'q' if suffix_always is true
2531    'T' => print 'q' in 64bit mode if instruction has no operand size
2532           prefix and behave as 'P' otherwise
2533    'U' => print 'q' in 64bit mode if instruction has no operand size
2534           prefix and behave as 'Q' otherwise
2535    'V' => print 'q' in 64bit mode if instruction has no operand size
2536           prefix and behave as 'S' otherwise
2537    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2538    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2539    'Y' unused.
2540    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2541    '!' => change condition from true to false or from false to true.
2542    '%' => add 1 upper case letter to the macro.
2543    '^' => print 'w' or 'l' depending on operand size prefix or
2544           suffix_always is true (lcall/ljmp).
2545    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2546           on operand size prefix.
2547    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2548           has no operand size prefix for AMD64 ISA, behave as 'P'
2549           otherwise
2550
2551    2 upper case letter macros:
2552    "XY" => print 'x' or 'y' if suffix_always is true or no register
2553            operands and no broadcast.
2554    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2555            register operands and no broadcast.
2556    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2557    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2558            or suffix_always is true
2559    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2560    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2561    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2562    "LW" => print 'd', 'q' depending on the VEX.W bit
2563    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2564            an operand size prefix, or suffix_always is true.  print
2565            'q' if rex prefix is present.
2566
2567    Many of the above letters print nothing in Intel mode.  See "putop"
2568    for the details.
2569
2570    Braces '{' and '}', and vertical bars '|', indicate alternative
2571    mnemonic strings for AT&T and Intel.  */
2572
2573 static const struct dis386 dis386[] = {
2574   /* 00 */
2575   { "addB",             { Ebh1, Gb }, 0 },
2576   { "addS",             { Evh1, Gv }, 0 },
2577   { "addB",             { Gb, EbS }, 0 },
2578   { "addS",             { Gv, EvS }, 0 },
2579   { "addB",             { AL, Ib }, 0 },
2580   { "addS",             { eAX, Iv }, 0 },
2581   { X86_64_TABLE (X86_64_06) },
2582   { X86_64_TABLE (X86_64_07) },
2583   /* 08 */
2584   { "orB",              { Ebh1, Gb }, 0 },
2585   { "orS",              { Evh1, Gv }, 0 },
2586   { "orB",              { Gb, EbS }, 0 },
2587   { "orS",              { Gv, EvS }, 0 },
2588   { "orB",              { AL, Ib }, 0 },
2589   { "orS",              { eAX, Iv }, 0 },
2590   { X86_64_TABLE (X86_64_0D) },
2591   { Bad_Opcode },       /* 0x0f extended opcode escape */
2592   /* 10 */
2593   { "adcB",             { Ebh1, Gb }, 0 },
2594   { "adcS",             { Evh1, Gv }, 0 },
2595   { "adcB",             { Gb, EbS }, 0 },
2596   { "adcS",             { Gv, EvS }, 0 },
2597   { "adcB",             { AL, Ib }, 0 },
2598   { "adcS",             { eAX, Iv }, 0 },
2599   { X86_64_TABLE (X86_64_16) },
2600   { X86_64_TABLE (X86_64_17) },
2601   /* 18 */
2602   { "sbbB",             { Ebh1, Gb }, 0 },
2603   { "sbbS",             { Evh1, Gv }, 0 },
2604   { "sbbB",             { Gb, EbS }, 0 },
2605   { "sbbS",             { Gv, EvS }, 0 },
2606   { "sbbB",             { AL, Ib }, 0 },
2607   { "sbbS",             { eAX, Iv }, 0 },
2608   { X86_64_TABLE (X86_64_1E) },
2609   { X86_64_TABLE (X86_64_1F) },
2610   /* 20 */
2611   { "andB",             { Ebh1, Gb }, 0 },
2612   { "andS",             { Evh1, Gv }, 0 },
2613   { "andB",             { Gb, EbS }, 0 },
2614   { "andS",             { Gv, EvS }, 0 },
2615   { "andB",             { AL, Ib }, 0 },
2616   { "andS",             { eAX, Iv }, 0 },
2617   { Bad_Opcode },       /* SEG ES prefix */
2618   { X86_64_TABLE (X86_64_27) },
2619   /* 28 */
2620   { "subB",             { Ebh1, Gb }, 0 },
2621   { "subS",             { Evh1, Gv }, 0 },
2622   { "subB",             { Gb, EbS }, 0 },
2623   { "subS",             { Gv, EvS }, 0 },
2624   { "subB",             { AL, Ib }, 0 },
2625   { "subS",             { eAX, Iv }, 0 },
2626   { Bad_Opcode },       /* SEG CS prefix */
2627   { X86_64_TABLE (X86_64_2F) },
2628   /* 30 */
2629   { "xorB",             { Ebh1, Gb }, 0 },
2630   { "xorS",             { Evh1, Gv }, 0 },
2631   { "xorB",             { Gb, EbS }, 0 },
2632   { "xorS",             { Gv, EvS }, 0 },
2633   { "xorB",             { AL, Ib }, 0 },
2634   { "xorS",             { eAX, Iv }, 0 },
2635   { Bad_Opcode },       /* SEG SS prefix */
2636   { X86_64_TABLE (X86_64_37) },
2637   /* 38 */
2638   { "cmpB",             { Eb, Gb }, 0 },
2639   { "cmpS",             { Ev, Gv }, 0 },
2640   { "cmpB",             { Gb, EbS }, 0 },
2641   { "cmpS",             { Gv, EvS }, 0 },
2642   { "cmpB",             { AL, Ib }, 0 },
2643   { "cmpS",             { eAX, Iv }, 0 },
2644   { Bad_Opcode },       /* SEG DS prefix */
2645   { X86_64_TABLE (X86_64_3F) },
2646   /* 40 */
2647   { "inc{S|}",          { RMeAX }, 0 },
2648   { "inc{S|}",          { RMeCX }, 0 },
2649   { "inc{S|}",          { RMeDX }, 0 },
2650   { "inc{S|}",          { RMeBX }, 0 },
2651   { "inc{S|}",          { RMeSP }, 0 },
2652   { "inc{S|}",          { RMeBP }, 0 },
2653   { "inc{S|}",          { RMeSI }, 0 },
2654   { "inc{S|}",          { RMeDI }, 0 },
2655   /* 48 */
2656   { "dec{S|}",          { RMeAX }, 0 },
2657   { "dec{S|}",          { RMeCX }, 0 },
2658   { "dec{S|}",          { RMeDX }, 0 },
2659   { "dec{S|}",          { RMeBX }, 0 },
2660   { "dec{S|}",          { RMeSP }, 0 },
2661   { "dec{S|}",          { RMeBP }, 0 },
2662   { "dec{S|}",          { RMeSI }, 0 },
2663   { "dec{S|}",          { RMeDI }, 0 },
2664   /* 50 */
2665   { "pushV",            { RMrAX }, 0 },
2666   { "pushV",            { RMrCX }, 0 },
2667   { "pushV",            { RMrDX }, 0 },
2668   { "pushV",            { RMrBX }, 0 },
2669   { "pushV",            { RMrSP }, 0 },
2670   { "pushV",            { RMrBP }, 0 },
2671   { "pushV",            { RMrSI }, 0 },
2672   { "pushV",            { RMrDI }, 0 },
2673   /* 58 */
2674   { "popV",             { RMrAX }, 0 },
2675   { "popV",             { RMrCX }, 0 },
2676   { "popV",             { RMrDX }, 0 },
2677   { "popV",             { RMrBX }, 0 },
2678   { "popV",             { RMrSP }, 0 },
2679   { "popV",             { RMrBP }, 0 },
2680   { "popV",             { RMrSI }, 0 },
2681   { "popV",             { RMrDI }, 0 },
2682   /* 60 */
2683   { X86_64_TABLE (X86_64_60) },
2684   { X86_64_TABLE (X86_64_61) },
2685   { X86_64_TABLE (X86_64_62) },
2686   { X86_64_TABLE (X86_64_63) },
2687   { Bad_Opcode },       /* seg fs */
2688   { Bad_Opcode },       /* seg gs */
2689   { Bad_Opcode },       /* op size prefix */
2690   { Bad_Opcode },       /* adr size prefix */
2691   /* 68 */
2692   { "pushT",            { sIv }, 0 },
2693   { "imulS",            { Gv, Ev, Iv }, 0 },
2694   { "pushT",            { sIbT }, 0 },
2695   { "imulS",            { Gv, Ev, sIb }, 0 },
2696   { "ins{b|}",          { Ybr, indirDX }, 0 },
2697   { X86_64_TABLE (X86_64_6D) },
2698   { "outs{b|}",         { indirDXr, Xb }, 0 },
2699   { X86_64_TABLE (X86_64_6F) },
2700   /* 70 */
2701   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2702   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2703   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2704   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2705   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2706   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2707   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2708   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2709   /* 78 */
2710   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2711   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2712   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2713   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2714   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2715   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2716   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2717   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2718   /* 80 */
2719   { REG_TABLE (REG_80) },
2720   { REG_TABLE (REG_81) },
2721   { X86_64_TABLE (X86_64_82) },
2722   { REG_TABLE (REG_83) },
2723   { "testB",            { Eb, Gb }, 0 },
2724   { "testS",            { Ev, Gv }, 0 },
2725   { "xchgB",            { Ebh2, Gb }, 0 },
2726   { "xchgS",            { Evh2, Gv }, 0 },
2727   /* 88 */
2728   { "movB",             { Ebh3, Gb }, 0 },
2729   { "movS",             { Evh3, Gv }, 0 },
2730   { "movB",             { Gb, EbS }, 0 },
2731   { "movS",             { Gv, EvS }, 0 },
2732   { "movD",             { Sv, Sw }, 0 },
2733   { MOD_TABLE (MOD_8D) },
2734   { "movD",             { Sw, Sv }, 0 },
2735   { REG_TABLE (REG_8F) },
2736   /* 90 */
2737   { PREFIX_TABLE (PREFIX_90) },
2738   { "xchgS",            { RMeCX, eAX }, 0 },
2739   { "xchgS",            { RMeDX, eAX }, 0 },
2740   { "xchgS",            { RMeBX, eAX }, 0 },
2741   { "xchgS",            { RMeSP, eAX }, 0 },
2742   { "xchgS",            { RMeBP, eAX }, 0 },
2743   { "xchgS",            { RMeSI, eAX }, 0 },
2744   { "xchgS",            { RMeDI, eAX }, 0 },
2745   /* 98 */
2746   { "cW{t|}R",          { XX }, 0 },
2747   { "cR{t|}O",          { XX }, 0 },
2748   { X86_64_TABLE (X86_64_9A) },
2749   { Bad_Opcode },       /* fwait */
2750   { "pushfT",           { XX }, 0 },
2751   { "popfT",            { XX }, 0 },
2752   { "sahf",             { XX }, 0 },
2753   { "lahf",             { XX }, 0 },
2754   /* a0 */
2755   { "mov%LB",           { AL, Ob }, 0 },
2756   { "mov%LS",           { eAX, Ov }, 0 },
2757   { "mov%LB",           { Ob, AL }, 0 },
2758   { "mov%LS",           { Ov, eAX }, 0 },
2759   { "movs{b|}",         { Ybr, Xb }, 0 },
2760   { "movs{R|}",         { Yvr, Xv }, 0 },
2761   { "cmps{b|}",         { Xb, Yb }, 0 },
2762   { "cmps{R|}",         { Xv, Yv }, 0 },
2763   /* a8 */
2764   { "testB",            { AL, Ib }, 0 },
2765   { "testS",            { eAX, Iv }, 0 },
2766   { "stosB",            { Ybr, AL }, 0 },
2767   { "stosS",            { Yvr, eAX }, 0 },
2768   { "lodsB",            { ALr, Xb }, 0 },
2769   { "lodsS",            { eAXr, Xv }, 0 },
2770   { "scasB",            { AL, Yb }, 0 },
2771   { "scasS",            { eAX, Yv }, 0 },
2772   /* b0 */
2773   { "movB",             { RMAL, Ib }, 0 },
2774   { "movB",             { RMCL, Ib }, 0 },
2775   { "movB",             { RMDL, Ib }, 0 },
2776   { "movB",             { RMBL, Ib }, 0 },
2777   { "movB",             { RMAH, Ib }, 0 },
2778   { "movB",             { RMCH, Ib }, 0 },
2779   { "movB",             { RMDH, Ib }, 0 },
2780   { "movB",             { RMBH, Ib }, 0 },
2781   /* b8 */
2782   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2783   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2784   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2785   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2786   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2787   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2788   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2789   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2790   /* c0 */
2791   { REG_TABLE (REG_C0) },
2792   { REG_TABLE (REG_C1) },
2793   { "retT",             { Iw, BND }, 0 },
2794   { "retT",             { BND }, 0 },
2795   { X86_64_TABLE (X86_64_C4) },
2796   { X86_64_TABLE (X86_64_C5) },
2797   { REG_TABLE (REG_C6) },
2798   { REG_TABLE (REG_C7) },
2799   /* c8 */
2800   { "enterT",           { Iw, Ib }, 0 },
2801   { "leaveT",           { XX }, 0 },
2802   { "Jret{|f}P",        { Iw }, 0 },
2803   { "Jret{|f}P",        { XX }, 0 },
2804   { "int3",             { XX }, 0 },
2805   { "int",              { Ib }, 0 },
2806   { X86_64_TABLE (X86_64_CE) },
2807   { "iret%LP",          { XX }, 0 },
2808   /* d0 */
2809   { REG_TABLE (REG_D0) },
2810   { REG_TABLE (REG_D1) },
2811   { REG_TABLE (REG_D2) },
2812   { REG_TABLE (REG_D3) },
2813   { X86_64_TABLE (X86_64_D4) },
2814   { X86_64_TABLE (X86_64_D5) },
2815   { Bad_Opcode },
2816   { "xlat",             { DSBX }, 0 },
2817   /* d8 */
2818   { FLOAT },
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   { FLOAT },
2823   { FLOAT },
2824   { FLOAT },
2825   { FLOAT },
2826   /* e0 */
2827   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2828   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2829   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2830   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2831   { "inB",              { AL, Ib }, 0 },
2832   { "inG",              { zAX, Ib }, 0 },
2833   { "outB",             { Ib, AL }, 0 },
2834   { "outG",             { Ib, zAX }, 0 },
2835   /* e8 */
2836   { X86_64_TABLE (X86_64_E8) },
2837   { X86_64_TABLE (X86_64_E9) },
2838   { X86_64_TABLE (X86_64_EA) },
2839   { "jmp",              { Jb, BND }, 0 },
2840   { "inB",              { AL, indirDX }, 0 },
2841   { "inG",              { zAX, indirDX }, 0 },
2842   { "outB",             { indirDX, AL }, 0 },
2843   { "outG",             { indirDX, zAX }, 0 },
2844   /* f0 */
2845   { Bad_Opcode },       /* lock prefix */
2846   { "icebp",            { XX }, 0 },
2847   { Bad_Opcode },       /* repne */
2848   { Bad_Opcode },       /* repz */
2849   { "hlt",              { XX }, 0 },
2850   { "cmc",              { XX }, 0 },
2851   { REG_TABLE (REG_F6) },
2852   { REG_TABLE (REG_F7) },
2853   /* f8 */
2854   { "clc",              { XX }, 0 },
2855   { "stc",              { XX }, 0 },
2856   { "cli",              { XX }, 0 },
2857   { "sti",              { XX }, 0 },
2858   { "cld",              { XX }, 0 },
2859   { "std",              { XX }, 0 },
2860   { REG_TABLE (REG_FE) },
2861   { REG_TABLE (REG_FF) },
2862 };
2863
2864 static const struct dis386 dis386_twobyte[] = {
2865   /* 00 */
2866   { REG_TABLE (REG_0F00 ) },
2867   { REG_TABLE (REG_0F01 ) },
2868   { "larS",             { Gv, Ew }, 0 },
2869   { "lslS",             { Gv, Ew }, 0 },
2870   { Bad_Opcode },
2871   { "syscall",          { XX }, 0 },
2872   { "clts",             { XX }, 0 },
2873   { "sysret%LP",                { XX }, 0 },
2874   /* 08 */
2875   { "invd",             { XX }, 0 },
2876   { PREFIX_TABLE (PREFIX_0F09) },
2877   { Bad_Opcode },
2878   { "ud2",              { XX }, 0 },
2879   { Bad_Opcode },
2880   { REG_TABLE (REG_0F0D) },
2881   { "femms",            { XX }, 0 },
2882   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2883   /* 10 */
2884   { PREFIX_TABLE (PREFIX_0F10) },
2885   { PREFIX_TABLE (PREFIX_0F11) },
2886   { PREFIX_TABLE (PREFIX_0F12) },
2887   { MOD_TABLE (MOD_0F13) },
2888   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2889   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2890   { PREFIX_TABLE (PREFIX_0F16) },
2891   { MOD_TABLE (MOD_0F17) },
2892   /* 18 */
2893   { REG_TABLE (REG_0F18) },
2894   { "nopQ",             { Ev }, 0 },
2895   { PREFIX_TABLE (PREFIX_0F1A) },
2896   { PREFIX_TABLE (PREFIX_0F1B) },
2897   { "nopQ",             { Ev }, 0 },
2898   { "nopQ",             { Ev }, 0 },
2899   { PREFIX_TABLE (PREFIX_0F1E) },
2900   { "nopQ",             { Ev }, 0 },
2901   /* 20 */
2902   { "movZ",             { Rm, Cm }, 0 },
2903   { "movZ",             { Rm, Dm }, 0 },
2904   { "movZ",             { Cm, Rm }, 0 },
2905   { "movZ",             { Dm, Rm }, 0 },
2906   { MOD_TABLE (MOD_0F24) },
2907   { Bad_Opcode },
2908   { MOD_TABLE (MOD_0F26) },
2909   { Bad_Opcode },
2910   /* 28 */
2911   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2912   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2913   { PREFIX_TABLE (PREFIX_0F2A) },
2914   { PREFIX_TABLE (PREFIX_0F2B) },
2915   { PREFIX_TABLE (PREFIX_0F2C) },
2916   { PREFIX_TABLE (PREFIX_0F2D) },
2917   { PREFIX_TABLE (PREFIX_0F2E) },
2918   { PREFIX_TABLE (PREFIX_0F2F) },
2919   /* 30 */
2920   { "wrmsr",            { XX }, 0 },
2921   { "rdtsc",            { XX }, 0 },
2922   { "rdmsr",            { XX }, 0 },
2923   { "rdpmc",            { XX }, 0 },
2924   { "sysenter",         { XX }, 0 },
2925   { "sysexit",          { XX }, 0 },
2926   { Bad_Opcode },
2927   { "getsec",           { XX }, 0 },
2928   /* 38 */
2929   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2930   { Bad_Opcode },
2931   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2932   { Bad_Opcode },
2933   { Bad_Opcode },
2934   { Bad_Opcode },
2935   { Bad_Opcode },
2936   { Bad_Opcode },
2937   /* 40 */
2938   { "cmovoS",           { Gv, Ev }, 0 },
2939   { "cmovnoS",          { Gv, Ev }, 0 },
2940   { "cmovbS",           { Gv, Ev }, 0 },
2941   { "cmovaeS",          { Gv, Ev }, 0 },
2942   { "cmoveS",           { Gv, Ev }, 0 },
2943   { "cmovneS",          { Gv, Ev }, 0 },
2944   { "cmovbeS",          { Gv, Ev }, 0 },
2945   { "cmovaS",           { Gv, Ev }, 0 },
2946   /* 48 */
2947   { "cmovsS",           { Gv, Ev }, 0 },
2948   { "cmovnsS",          { Gv, Ev }, 0 },
2949   { "cmovpS",           { Gv, Ev }, 0 },
2950   { "cmovnpS",          { Gv, Ev }, 0 },
2951   { "cmovlS",           { Gv, Ev }, 0 },
2952   { "cmovgeS",          { Gv, Ev }, 0 },
2953   { "cmovleS",          { Gv, Ev }, 0 },
2954   { "cmovgS",           { Gv, Ev }, 0 },
2955   /* 50 */
2956   { MOD_TABLE (MOD_0F51) },
2957   { PREFIX_TABLE (PREFIX_0F51) },
2958   { PREFIX_TABLE (PREFIX_0F52) },
2959   { PREFIX_TABLE (PREFIX_0F53) },
2960   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2961   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2962   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2963   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2964   /* 58 */
2965   { PREFIX_TABLE (PREFIX_0F58) },
2966   { PREFIX_TABLE (PREFIX_0F59) },
2967   { PREFIX_TABLE (PREFIX_0F5A) },
2968   { PREFIX_TABLE (PREFIX_0F5B) },
2969   { PREFIX_TABLE (PREFIX_0F5C) },
2970   { PREFIX_TABLE (PREFIX_0F5D) },
2971   { PREFIX_TABLE (PREFIX_0F5E) },
2972   { PREFIX_TABLE (PREFIX_0F5F) },
2973   /* 60 */
2974   { PREFIX_TABLE (PREFIX_0F60) },
2975   { PREFIX_TABLE (PREFIX_0F61) },
2976   { PREFIX_TABLE (PREFIX_0F62) },
2977   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2978   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2979   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2980   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2981   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2982   /* 68 */
2983   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2984   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2985   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2986   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2987   { PREFIX_TABLE (PREFIX_0F6C) },
2988   { PREFIX_TABLE (PREFIX_0F6D) },
2989   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2990   { PREFIX_TABLE (PREFIX_0F6F) },
2991   /* 70 */
2992   { PREFIX_TABLE (PREFIX_0F70) },
2993   { REG_TABLE (REG_0F71) },
2994   { REG_TABLE (REG_0F72) },
2995   { REG_TABLE (REG_0F73) },
2996   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2997   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2998   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2999   { "emms",             { XX }, PREFIX_OPCODE },
3000   /* 78 */
3001   { PREFIX_TABLE (PREFIX_0F78) },
3002   { PREFIX_TABLE (PREFIX_0F79) },
3003   { Bad_Opcode },
3004   { Bad_Opcode },
3005   { PREFIX_TABLE (PREFIX_0F7C) },
3006   { PREFIX_TABLE (PREFIX_0F7D) },
3007   { PREFIX_TABLE (PREFIX_0F7E) },
3008   { PREFIX_TABLE (PREFIX_0F7F) },
3009   /* 80 */
3010   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3011   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3012   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3013   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3014   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3015   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3016   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3017   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3018   /* 88 */
3019   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3020   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3021   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3022   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3023   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3024   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3025   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3026   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3027   /* 90 */
3028   { "seto",             { Eb }, 0 },
3029   { "setno",            { Eb }, 0 },
3030   { "setb",             { Eb }, 0 },
3031   { "setae",            { Eb }, 0 },
3032   { "sete",             { Eb }, 0 },
3033   { "setne",            { Eb }, 0 },
3034   { "setbe",            { Eb }, 0 },
3035   { "seta",             { Eb }, 0 },
3036   /* 98 */
3037   { "sets",             { Eb }, 0 },
3038   { "setns",            { Eb }, 0 },
3039   { "setp",             { Eb }, 0 },
3040   { "setnp",            { Eb }, 0 },
3041   { "setl",             { Eb }, 0 },
3042   { "setge",            { Eb }, 0 },
3043   { "setle",            { Eb }, 0 },
3044   { "setg",             { Eb }, 0 },
3045   /* a0 */
3046   { "pushT",            { fs }, 0 },
3047   { "popT",             { fs }, 0 },
3048   { "cpuid",            { XX }, 0 },
3049   { "btS",              { Ev, Gv }, 0 },
3050   { "shldS",            { Ev, Gv, Ib }, 0 },
3051   { "shldS",            { Ev, Gv, CL }, 0 },
3052   { REG_TABLE (REG_0FA6) },
3053   { REG_TABLE (REG_0FA7) },
3054   /* a8 */
3055   { "pushT",            { gs }, 0 },
3056   { "popT",             { gs }, 0 },
3057   { "rsm",              { XX }, 0 },
3058   { "btsS",             { Evh1, Gv }, 0 },
3059   { "shrdS",            { Ev, Gv, Ib }, 0 },
3060   { "shrdS",            { Ev, Gv, CL }, 0 },
3061   { REG_TABLE (REG_0FAE) },
3062   { "imulS",            { Gv, Ev }, 0 },
3063   /* b0 */
3064   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3065   { "cmpxchgS",         { Evh1, Gv }, 0 },
3066   { MOD_TABLE (MOD_0FB2) },
3067   { "btrS",             { Evh1, Gv }, 0 },
3068   { MOD_TABLE (MOD_0FB4) },
3069   { MOD_TABLE (MOD_0FB5) },
3070   { "movz{bR|x}",       { Gv, Eb }, 0 },
3071   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3072   /* b8 */
3073   { PREFIX_TABLE (PREFIX_0FB8) },
3074   { "ud1S",             { Gv, Ev }, 0 },
3075   { REG_TABLE (REG_0FBA) },
3076   { "btcS",             { Evh1, Gv }, 0 },
3077   { PREFIX_TABLE (PREFIX_0FBC) },
3078   { PREFIX_TABLE (PREFIX_0FBD) },
3079   { "movs{bR|x}",       { Gv, Eb }, 0 },
3080   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3081   /* c0 */
3082   { "xaddB",            { Ebh1, Gb }, 0 },
3083   { "xaddS",            { Evh1, Gv }, 0 },
3084   { PREFIX_TABLE (PREFIX_0FC2) },
3085   { MOD_TABLE (MOD_0FC3) },
3086   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3087   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3088   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3089   { REG_TABLE (REG_0FC7) },
3090   /* c8 */
3091   { "bswap",            { RMeAX }, 0 },
3092   { "bswap",            { RMeCX }, 0 },
3093   { "bswap",            { RMeDX }, 0 },
3094   { "bswap",            { RMeBX }, 0 },
3095   { "bswap",            { RMeSP }, 0 },
3096   { "bswap",            { RMeBP }, 0 },
3097   { "bswap",            { RMeSI }, 0 },
3098   { "bswap",            { RMeDI }, 0 },
3099   /* d0 */
3100   { PREFIX_TABLE (PREFIX_0FD0) },
3101   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3102   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3103   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3104   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3105   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3106   { PREFIX_TABLE (PREFIX_0FD6) },
3107   { MOD_TABLE (MOD_0FD7) },
3108   /* d8 */
3109   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3110   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3111   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3112   { "pand",             { MX, EM }, PREFIX_OPCODE },
3113   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3114   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3115   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3116   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3117   /* e0 */
3118   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3119   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3120   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3121   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3122   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3123   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3124   { PREFIX_TABLE (PREFIX_0FE6) },
3125   { PREFIX_TABLE (PREFIX_0FE7) },
3126   /* e8 */
3127   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3128   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3129   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3130   { "por",              { MX, EM }, PREFIX_OPCODE },
3131   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3132   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3133   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3134   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3135   /* f0 */
3136   { PREFIX_TABLE (PREFIX_0FF0) },
3137   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3138   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3139   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3140   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3141   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3142   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3143   { PREFIX_TABLE (PREFIX_0FF7) },
3144   /* f8 */
3145   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3146   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3147   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3148   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3149   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3150   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3151   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3152   { "ud0S",             { Gv, Ev }, 0 },
3153 };
3154
3155 static const unsigned char onebyte_has_modrm[256] = {
3156   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3157   /*       -------------------------------        */
3158   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3159   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3160   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3161   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3162   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3163   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3164   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3165   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3166   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3167   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3168   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3169   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3170   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3171   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3172   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3173   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3174   /*       -------------------------------        */
3175   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3176 };
3177
3178 static const unsigned char twobyte_has_modrm[256] = {
3179   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3180   /*       -------------------------------        */
3181   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3182   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3183   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3184   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3185   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3186   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3187   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3188   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3189   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3190   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3191   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3192   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3193   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3194   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3195   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3196   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3197   /*       -------------------------------        */
3198   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3199 };
3200
3201 static char obuf[100];
3202 static char *obufp;
3203 static char *mnemonicendp;
3204 static char scratchbuf[100];
3205 static unsigned char *start_codep;
3206 static unsigned char *insn_codep;
3207 static unsigned char *codep;
3208 static unsigned char *end_codep;
3209 static int last_lock_prefix;
3210 static int last_repz_prefix;
3211 static int last_repnz_prefix;
3212 static int last_data_prefix;
3213 static int last_addr_prefix;
3214 static int last_rex_prefix;
3215 static int last_seg_prefix;
3216 static int fwait_prefix;
3217 /* The active segment register prefix.  */
3218 static int active_seg_prefix;
3219 #define MAX_CODE_LENGTH 15
3220 /* We can up to 14 prefixes since the maximum instruction length is
3221    15bytes.  */
3222 static int all_prefixes[MAX_CODE_LENGTH - 1];
3223 static disassemble_info *the_info;
3224 static struct
3225   {
3226     int mod;
3227     int reg;
3228     int rm;
3229   }
3230 modrm;
3231 static unsigned char need_modrm;
3232 static struct
3233   {
3234     int scale;
3235     int index;
3236     int base;
3237   }
3238 sib;
3239 static struct
3240   {
3241     int register_specifier;
3242     int length;
3243     int prefix;
3244     int w;
3245     int evex;
3246     int r;
3247     int v;
3248     int mask_register_specifier;
3249     int zeroing;
3250     int ll;
3251     int b;
3252   }
3253 vex;
3254 static unsigned char need_vex;
3255 static unsigned char need_vex_reg;
3256 static unsigned char vex_w_done;
3257
3258 struct op
3259   {
3260     const char *name;
3261     unsigned int len;
3262   };
3263
3264 /* If we are accessing mod/rm/reg without need_modrm set, then the
3265    values are stale.  Hitting this abort likely indicates that you
3266    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3267 #define MODRM_CHECK  if (!need_modrm) abort ()
3268
3269 static const char **names64;
3270 static const char **names32;
3271 static const char **names16;
3272 static const char **names8;
3273 static const char **names8rex;
3274 static const char **names_seg;
3275 static const char *index64;
3276 static const char *index32;
3277 static const char **index16;
3278 static const char **names_bnd;
3279
3280 static const char *intel_names64[] = {
3281   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3282   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3283 };
3284 static const char *intel_names32[] = {
3285   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3286   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3287 };
3288 static const char *intel_names16[] = {
3289   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3290   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3291 };
3292 static const char *intel_names8[] = {
3293   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3294 };
3295 static const char *intel_names8rex[] = {
3296   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3297   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3298 };
3299 static const char *intel_names_seg[] = {
3300   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3301 };
3302 static const char *intel_index64 = "riz";
3303 static const char *intel_index32 = "eiz";
3304 static const char *intel_index16[] = {
3305   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3306 };
3307
3308 static const char *att_names64[] = {
3309   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3310   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3311 };
3312 static const char *att_names32[] = {
3313   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3314   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3315 };
3316 static const char *att_names16[] = {
3317   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3318   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3319 };
3320 static const char *att_names8[] = {
3321   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3322 };
3323 static const char *att_names8rex[] = {
3324   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3325   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3326 };
3327 static const char *att_names_seg[] = {
3328   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3329 };
3330 static const char *att_index64 = "%riz";
3331 static const char *att_index32 = "%eiz";
3332 static const char *att_index16[] = {
3333   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3334 };
3335
3336 static const char **names_mm;
3337 static const char *intel_names_mm[] = {
3338   "mm0", "mm1", "mm2", "mm3",
3339   "mm4", "mm5", "mm6", "mm7"
3340 };
3341 static const char *att_names_mm[] = {
3342   "%mm0", "%mm1", "%mm2", "%mm3",
3343   "%mm4", "%mm5", "%mm6", "%mm7"
3344 };
3345
3346 static const char *intel_names_bnd[] = {
3347   "bnd0", "bnd1", "bnd2", "bnd3"
3348 };
3349
3350 static const char *att_names_bnd[] = {
3351   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3352 };
3353
3354 static const char **names_xmm;
3355 static const char *intel_names_xmm[] = {
3356   "xmm0", "xmm1", "xmm2", "xmm3",
3357   "xmm4", "xmm5", "xmm6", "xmm7",
3358   "xmm8", "xmm9", "xmm10", "xmm11",
3359   "xmm12", "xmm13", "xmm14", "xmm15",
3360   "xmm16", "xmm17", "xmm18", "xmm19",
3361   "xmm20", "xmm21", "xmm22", "xmm23",
3362   "xmm24", "xmm25", "xmm26", "xmm27",
3363   "xmm28", "xmm29", "xmm30", "xmm31"
3364 };
3365 static const char *att_names_xmm[] = {
3366   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3367   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3368   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3369   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3370   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3371   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3372   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3373   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3374 };
3375
3376 static const char **names_ymm;
3377 static const char *intel_names_ymm[] = {
3378   "ymm0", "ymm1", "ymm2", "ymm3",
3379   "ymm4", "ymm5", "ymm6", "ymm7",
3380   "ymm8", "ymm9", "ymm10", "ymm11",
3381   "ymm12", "ymm13", "ymm14", "ymm15",
3382   "ymm16", "ymm17", "ymm18", "ymm19",
3383   "ymm20", "ymm21", "ymm22", "ymm23",
3384   "ymm24", "ymm25", "ymm26", "ymm27",
3385   "ymm28", "ymm29", "ymm30", "ymm31"
3386 };
3387 static const char *att_names_ymm[] = {
3388   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3389   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3390   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3391   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3392   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3393   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3394   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3395   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3396 };
3397
3398 static const char **names_zmm;
3399 static const char *intel_names_zmm[] = {
3400   "zmm0", "zmm1", "zmm2", "zmm3",
3401   "zmm4", "zmm5", "zmm6", "zmm7",
3402   "zmm8", "zmm9", "zmm10", "zmm11",
3403   "zmm12", "zmm13", "zmm14", "zmm15",
3404   "zmm16", "zmm17", "zmm18", "zmm19",
3405   "zmm20", "zmm21", "zmm22", "zmm23",
3406   "zmm24", "zmm25", "zmm26", "zmm27",
3407   "zmm28", "zmm29", "zmm30", "zmm31"
3408 };
3409 static const char *att_names_zmm[] = {
3410   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3411   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3412   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3413   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3414   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3415   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3416   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3417   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3418 };
3419
3420 static const char **names_mask;
3421 static const char *intel_names_mask[] = {
3422   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3423 };
3424 static const char *att_names_mask[] = {
3425   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3426 };
3427
3428 static const char *names_rounding[] =
3429 {
3430   "{rn-sae}",
3431   "{rd-sae}",
3432   "{ru-sae}",
3433   "{rz-sae}"
3434 };
3435
3436 static const struct dis386 reg_table[][8] = {
3437   /* REG_80 */
3438   {
3439     { "addA",   { Ebh1, Ib }, 0 },
3440     { "orA",    { Ebh1, Ib }, 0 },
3441     { "adcA",   { Ebh1, Ib }, 0 },
3442     { "sbbA",   { Ebh1, Ib }, 0 },
3443     { "andA",   { Ebh1, Ib }, 0 },
3444     { "subA",   { Ebh1, Ib }, 0 },
3445     { "xorA",   { Ebh1, Ib }, 0 },
3446     { "cmpA",   { Eb, Ib }, 0 },
3447   },
3448   /* REG_81 */
3449   {
3450     { "addQ",   { Evh1, Iv }, 0 },
3451     { "orQ",    { Evh1, Iv }, 0 },
3452     { "adcQ",   { Evh1, Iv }, 0 },
3453     { "sbbQ",   { Evh1, Iv }, 0 },
3454     { "andQ",   { Evh1, Iv }, 0 },
3455     { "subQ",   { Evh1, Iv }, 0 },
3456     { "xorQ",   { Evh1, Iv }, 0 },
3457     { "cmpQ",   { Ev, Iv }, 0 },
3458   },
3459   /* REG_83 */
3460   {
3461     { "addQ",   { Evh1, sIb }, 0 },
3462     { "orQ",    { Evh1, sIb }, 0 },
3463     { "adcQ",   { Evh1, sIb }, 0 },
3464     { "sbbQ",   { Evh1, sIb }, 0 },
3465     { "andQ",   { Evh1, sIb }, 0 },
3466     { "subQ",   { Evh1, sIb }, 0 },
3467     { "xorQ",   { Evh1, sIb }, 0 },
3468     { "cmpQ",   { Ev, sIb }, 0 },
3469   },
3470   /* REG_8F */
3471   {
3472     { "popU",   { stackEv }, 0 },
3473     { XOP_8F_TABLE (XOP_09) },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { XOP_8F_TABLE (XOP_09) },
3478   },
3479   /* REG_C0 */
3480   {
3481     { "rolA",   { Eb, Ib }, 0 },
3482     { "rorA",   { Eb, Ib }, 0 },
3483     { "rclA",   { Eb, Ib }, 0 },
3484     { "rcrA",   { Eb, Ib }, 0 },
3485     { "shlA",   { Eb, Ib }, 0 },
3486     { "shrA",   { Eb, Ib }, 0 },
3487     { "shlA",   { Eb, Ib }, 0 },
3488     { "sarA",   { Eb, Ib }, 0 },
3489   },
3490   /* REG_C1 */
3491   {
3492     { "rolQ",   { Ev, Ib }, 0 },
3493     { "rorQ",   { Ev, Ib }, 0 },
3494     { "rclQ",   { Ev, Ib }, 0 },
3495     { "rcrQ",   { Ev, Ib }, 0 },
3496     { "shlQ",   { Ev, Ib }, 0 },
3497     { "shrQ",   { Ev, Ib }, 0 },
3498     { "shlQ",   { Ev, Ib }, 0 },
3499     { "sarQ",   { Ev, Ib }, 0 },
3500   },
3501   /* REG_C6 */
3502   {
3503     { "movA",   { Ebh3, Ib }, 0 },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { MOD_TABLE (MOD_C6_REG_7) },
3511   },
3512   /* REG_C7 */
3513   {
3514     { "movQ",   { Evh3, Iv }, 0 },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_C7_REG_7) },
3522   },
3523   /* REG_D0 */
3524   {
3525     { "rolA",   { Eb, I1 }, 0 },
3526     { "rorA",   { Eb, I1 }, 0 },
3527     { "rclA",   { Eb, I1 }, 0 },
3528     { "rcrA",   { Eb, I1 }, 0 },
3529     { "shlA",   { Eb, I1 }, 0 },
3530     { "shrA",   { Eb, I1 }, 0 },
3531     { "shlA",   { Eb, I1 }, 0 },
3532     { "sarA",   { Eb, I1 }, 0 },
3533   },
3534   /* REG_D1 */
3535   {
3536     { "rolQ",   { Ev, I1 }, 0 },
3537     { "rorQ",   { Ev, I1 }, 0 },
3538     { "rclQ",   { Ev, I1 }, 0 },
3539     { "rcrQ",   { Ev, I1 }, 0 },
3540     { "shlQ",   { Ev, I1 }, 0 },
3541     { "shrQ",   { Ev, I1 }, 0 },
3542     { "shlQ",   { Ev, I1 }, 0 },
3543     { "sarQ",   { Ev, I1 }, 0 },
3544   },
3545   /* REG_D2 */
3546   {
3547     { "rolA",   { Eb, CL }, 0 },
3548     { "rorA",   { Eb, CL }, 0 },
3549     { "rclA",   { Eb, CL }, 0 },
3550     { "rcrA",   { Eb, CL }, 0 },
3551     { "shlA",   { Eb, CL }, 0 },
3552     { "shrA",   { Eb, CL }, 0 },
3553     { "shlA",   { Eb, CL }, 0 },
3554     { "sarA",   { Eb, CL }, 0 },
3555   },
3556   /* REG_D3 */
3557   {
3558     { "rolQ",   { Ev, CL }, 0 },
3559     { "rorQ",   { Ev, CL }, 0 },
3560     { "rclQ",   { Ev, CL }, 0 },
3561     { "rcrQ",   { Ev, CL }, 0 },
3562     { "shlQ",   { Ev, CL }, 0 },
3563     { "shrQ",   { Ev, CL }, 0 },
3564     { "shlQ",   { Ev, CL }, 0 },
3565     { "sarQ",   { Ev, CL }, 0 },
3566   },
3567   /* REG_F6 */
3568   {
3569     { "testA",  { Eb, Ib }, 0 },
3570     { "testA",  { Eb, Ib }, 0 },
3571     { "notA",   { Ebh1 }, 0 },
3572     { "negA",   { Ebh1 }, 0 },
3573     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3574     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3575     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3576     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3577   },
3578   /* REG_F7 */
3579   {
3580     { "testQ",  { Ev, Iv }, 0 },
3581     { "testQ",  { Ev, Iv }, 0 },
3582     { "notQ",   { Evh1 }, 0 },
3583     { "negQ",   { Evh1 }, 0 },
3584     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3585     { "imulQ",  { Ev }, 0 },
3586     { "divQ",   { Ev }, 0 },
3587     { "idivQ",  { Ev }, 0 },
3588   },
3589   /* REG_FE */
3590   {
3591     { "incA",   { Ebh1 }, 0 },
3592     { "decA",   { Ebh1 }, 0 },
3593   },
3594   /* REG_FF */
3595   {
3596     { "incQ",   { Evh1 }, 0 },
3597     { "decQ",   { Evh1 }, 0 },
3598     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3599     { MOD_TABLE (MOD_FF_REG_3) },
3600     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3601     { MOD_TABLE (MOD_FF_REG_5) },
3602     { "pushU",  { stackEv }, 0 },
3603     { Bad_Opcode },
3604   },
3605   /* REG_0F00 */
3606   {
3607     { "sldtD",  { Sv }, 0 },
3608     { "strD",   { Sv }, 0 },
3609     { "lldt",   { Ew }, 0 },
3610     { "ltr",    { Ew }, 0 },
3611     { "verr",   { Ew }, 0 },
3612     { "verw",   { Ew }, 0 },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615   },
3616   /* REG_0F01 */
3617   {
3618     { MOD_TABLE (MOD_0F01_REG_0) },
3619     { MOD_TABLE (MOD_0F01_REG_1) },
3620     { MOD_TABLE (MOD_0F01_REG_2) },
3621     { MOD_TABLE (MOD_0F01_REG_3) },
3622     { "smswD",  { Sv }, 0 },
3623     { MOD_TABLE (MOD_0F01_REG_5) },
3624     { "lmsw",   { Ew }, 0 },
3625     { MOD_TABLE (MOD_0F01_REG_7) },
3626   },
3627   /* REG_0F0D */
3628   {
3629     { "prefetch",       { Mb }, 0 },
3630     { "prefetchw",      { Mb }, 0 },
3631     { "prefetchwt1",    { Mb }, 0 },
3632     { "prefetch",       { Mb }, 0 },
3633     { "prefetch",       { Mb }, 0 },
3634     { "prefetch",       { Mb }, 0 },
3635     { "prefetch",       { Mb }, 0 },
3636     { "prefetch",       { Mb }, 0 },
3637   },
3638   /* REG_0F18 */
3639   {
3640     { MOD_TABLE (MOD_0F18_REG_0) },
3641     { MOD_TABLE (MOD_0F18_REG_1) },
3642     { MOD_TABLE (MOD_0F18_REG_2) },
3643     { MOD_TABLE (MOD_0F18_REG_3) },
3644     { MOD_TABLE (MOD_0F18_REG_4) },
3645     { MOD_TABLE (MOD_0F18_REG_5) },
3646     { MOD_TABLE (MOD_0F18_REG_6) },
3647     { MOD_TABLE (MOD_0F18_REG_7) },
3648   },
3649   /* REG_0F1E_MOD_3 */
3650   {
3651     { "nopQ",           { Ev }, 0 },
3652     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3653     { "nopQ",           { Ev }, 0 },
3654     { "nopQ",           { Ev }, 0 },
3655     { "nopQ",           { Ev }, 0 },
3656     { "nopQ",           { Ev }, 0 },
3657     { "nopQ",           { Ev }, 0 },
3658     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3659   },
3660   /* REG_0F71 */
3661   {
3662     { Bad_Opcode },
3663     { Bad_Opcode },
3664     { MOD_TABLE (MOD_0F71_REG_2) },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_0F71_REG_4) },
3667     { Bad_Opcode },
3668     { MOD_TABLE (MOD_0F71_REG_6) },
3669   },
3670   /* REG_0F72 */
3671   {
3672     { Bad_Opcode },
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_0F72_REG_2) },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_0F72_REG_4) },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_0F72_REG_6) },
3679   },
3680   /* REG_0F73 */
3681   {
3682     { Bad_Opcode },
3683     { Bad_Opcode },
3684     { MOD_TABLE (MOD_0F73_REG_2) },
3685     { MOD_TABLE (MOD_0F73_REG_3) },
3686     { Bad_Opcode },
3687     { Bad_Opcode },
3688     { MOD_TABLE (MOD_0F73_REG_6) },
3689     { MOD_TABLE (MOD_0F73_REG_7) },
3690   },
3691   /* REG_0FA6 */
3692   {
3693     { "montmul",        { { OP_0f07, 0 } }, 0 },
3694     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3695     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3696   },
3697   /* REG_0FA7 */
3698   {
3699     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3700     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3701     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3702     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3703     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3704     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3705   },
3706   /* REG_0FAE */
3707   {
3708     { MOD_TABLE (MOD_0FAE_REG_0) },
3709     { MOD_TABLE (MOD_0FAE_REG_1) },
3710     { MOD_TABLE (MOD_0FAE_REG_2) },
3711     { MOD_TABLE (MOD_0FAE_REG_3) },
3712     { MOD_TABLE (MOD_0FAE_REG_4) },
3713     { MOD_TABLE (MOD_0FAE_REG_5) },
3714     { MOD_TABLE (MOD_0FAE_REG_6) },
3715     { MOD_TABLE (MOD_0FAE_REG_7) },
3716   },
3717   /* REG_0FBA */
3718   {
3719     { Bad_Opcode },
3720     { Bad_Opcode },
3721     { Bad_Opcode },
3722     { Bad_Opcode },
3723     { "btQ",    { Ev, Ib }, 0 },
3724     { "btsQ",   { Evh1, Ib }, 0 },
3725     { "btrQ",   { Evh1, Ib }, 0 },
3726     { "btcQ",   { Evh1, Ib }, 0 },
3727   },
3728   /* REG_0FC7 */
3729   {
3730     { Bad_Opcode },
3731     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3732     { Bad_Opcode },
3733     { MOD_TABLE (MOD_0FC7_REG_3) },
3734     { MOD_TABLE (MOD_0FC7_REG_4) },
3735     { MOD_TABLE (MOD_0FC7_REG_5) },
3736     { MOD_TABLE (MOD_0FC7_REG_6) },
3737     { MOD_TABLE (MOD_0FC7_REG_7) },
3738   },
3739   /* REG_VEX_0F71 */
3740   {
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3744     { Bad_Opcode },
3745     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3746     { Bad_Opcode },
3747     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3748   },
3749   /* REG_VEX_0F72 */
3750   {
3751     { Bad_Opcode },
3752     { Bad_Opcode },
3753     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3754     { Bad_Opcode },
3755     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3756     { Bad_Opcode },
3757     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3758   },
3759   /* REG_VEX_0F73 */
3760   {
3761     { Bad_Opcode },
3762     { Bad_Opcode },
3763     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3764     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3765     { Bad_Opcode },
3766     { Bad_Opcode },
3767     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3768     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3769   },
3770   /* REG_VEX_0FAE */
3771   {
3772     { Bad_Opcode },
3773     { Bad_Opcode },
3774     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3775     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3776   },
3777   /* REG_VEX_0F38F3 */
3778   {
3779     { Bad_Opcode },
3780     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3781     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3782     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3783   },
3784   /* REG_XOP_LWPCB */
3785   {
3786     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3787     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3788   },
3789   /* REG_XOP_LWP */
3790   {
3791     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3792     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3793   },
3794   /* REG_XOP_TBM_01 */
3795   {
3796     { Bad_Opcode },
3797     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3798     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3800     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3801     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3802     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3803     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3804   },
3805   /* REG_XOP_TBM_02 */
3806   {
3807     { Bad_Opcode },
3808     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3809     { Bad_Opcode },
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { Bad_Opcode },
3813     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3814   },
3815 #define NEED_REG_TABLE
3816 #include "i386-dis-evex.h"
3817 #undef NEED_REG_TABLE
3818 };
3819
3820 static const struct dis386 prefix_table[][4] = {
3821   /* PREFIX_90 */
3822   {
3823     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3824     { "pause", { XX }, 0 },
3825     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3826     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3827   },
3828
3829   /* PREFIX_MOD_0_0F01_REG_5 */
3830   {
3831     { Bad_Opcode },
3832     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3836   {
3837     { Bad_Opcode },
3838     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3842   {
3843     { Bad_Opcode },
3844     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3845   },
3846
3847   /* PREFIX_0F09 */
3848   {
3849     { "wbinvd",   { XX }, 0 },
3850     { "wbnoinvd", { XX }, 0 },
3851   },
3852
3853   /* PREFIX_0F10 */
3854   {
3855     { "movups", { XM, EXx }, PREFIX_OPCODE },
3856     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3857     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3858     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F11 */
3862   {
3863     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3864     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3865     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3866     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F12 */
3870   {
3871     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3872     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3873     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3874     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F16 */
3878   {
3879     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3880     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3881     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F1A */
3885   {
3886     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3887     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3888     { "bndmov", { Gbnd, Ebnd }, 0 },
3889     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3890   },
3891
3892   /* PREFIX_0F1B */
3893   {
3894     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3895     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3896     { "bndmov", { EbndS, Gbnd }, 0 },
3897     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3898   },
3899
3900   /* PREFIX_0F1E */
3901   {
3902     { "nopQ",   { Ev }, PREFIX_OPCODE },
3903     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3904     { "nopQ",   { Ev }, PREFIX_OPCODE },
3905     { "nopQ",   { Ev }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F2A */
3909   {
3910     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3911     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3912     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3913     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3914   },
3915
3916   /* PREFIX_0F2B */
3917   {
3918     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3919     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3920     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3921     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3922   },
3923
3924   /* PREFIX_0F2C */
3925   {
3926     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3927     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3928     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3929     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0F2D */
3933   {
3934     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3935     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3936     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3937     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0F2E */
3941   {
3942     { "ucomiss",{ XM, EXd }, 0 },
3943     { Bad_Opcode },
3944     { "ucomisd",{ XM, EXq }, 0 },
3945   },
3946
3947   /* PREFIX_0F2F */
3948   {
3949     { "comiss", { XM, EXd }, 0 },
3950     { Bad_Opcode },
3951     { "comisd", { XM, EXq }, 0 },
3952   },
3953
3954   /* PREFIX_0F51 */
3955   {
3956     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3957     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3958     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3959     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3960   },
3961
3962   /* PREFIX_0F52 */
3963   {
3964     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3965     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0F53 */
3969   {
3970     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3971     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0F58 */
3975   {
3976     { "addps", { XM, EXx }, PREFIX_OPCODE },
3977     { "addss", { XM, EXd }, PREFIX_OPCODE },
3978     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3979     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3980   },
3981
3982   /* PREFIX_0F59 */
3983   {
3984     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3985     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3986     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3987     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3988   },
3989
3990   /* PREFIX_0F5A */
3991   {
3992     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3993     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3994     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3995     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3996   },
3997
3998   /* PREFIX_0F5B */
3999   {
4000     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4001     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4002     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F5C */
4006   {
4007     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4008     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4009     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4010     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0F5D */
4014   {
4015     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4016     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4017     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4018     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0F5E */
4022   {
4023     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4024     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4025     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4026     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F5F */
4030   {
4031     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4032     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4033     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4034     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4035   },
4036
4037   /* PREFIX_0F60 */
4038   {
4039     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4040     { Bad_Opcode },
4041     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4042   },
4043
4044   /* PREFIX_0F61 */
4045   {
4046     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4047     { Bad_Opcode },
4048     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4049   },
4050
4051   /* PREFIX_0F62 */
4052   {
4053     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4054     { Bad_Opcode },
4055     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4056   },
4057
4058   /* PREFIX_0F6C */
4059   {
4060     { Bad_Opcode },
4061     { Bad_Opcode },
4062     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_0F6D */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4070   },
4071
4072   /* PREFIX_0F6F */
4073   {
4074     { "movq",   { MX, EM }, PREFIX_OPCODE },
4075     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4076     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4077   },
4078
4079   /* PREFIX_0F70 */
4080   {
4081     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4082     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4083     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4084     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4085   },
4086
4087   /* PREFIX_0F73_REG_3 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "psrldq", { XS, Ib }, 0 },
4092   },
4093
4094   /* PREFIX_0F73_REG_7 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pslldq", { XS, Ib }, 0 },
4099   },
4100
4101   /* PREFIX_0F78 */
4102   {
4103     {"vmread",  { Em, Gm }, 0 },
4104     { Bad_Opcode },
4105     {"extrq",   { XS, Ib, Ib }, 0 },
4106     {"insertq", { XM, XS, Ib, Ib }, 0 },
4107   },
4108
4109   /* PREFIX_0F79 */
4110   {
4111     {"vmwrite", { Gm, Em }, 0 },
4112     { Bad_Opcode },
4113     {"extrq",   { XM, XS }, 0 },
4114     {"insertq", { XM, XS }, 0 },
4115   },
4116
4117   /* PREFIX_0F7C */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4122     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_0F7D */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4130     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0F7E */
4134   {
4135     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4136     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4137     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F7F */
4141   {
4142     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4143     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4144     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0FAE_REG_0 */
4148   {
4149     { Bad_Opcode },
4150     { "rdfsbase", { Ev }, 0 },
4151   },
4152
4153   /* PREFIX_0FAE_REG_1 */
4154   {
4155     { Bad_Opcode },
4156     { "rdgsbase", { Ev }, 0 },
4157   },
4158
4159   /* PREFIX_0FAE_REG_2 */
4160   {
4161     { Bad_Opcode },
4162     { "wrfsbase", { Ev }, 0 },
4163   },
4164
4165   /* PREFIX_0FAE_REG_3 */
4166   {
4167     { Bad_Opcode },
4168     { "wrgsbase", { Ev }, 0 },
4169   },
4170
4171   /* PREFIX_MOD_0_0FAE_REG_4 */
4172   {
4173     { "xsave",  { FXSAVE }, 0 },
4174     { "ptwrite%LQ", { Edq }, 0 },
4175   },
4176
4177   /* PREFIX_MOD_3_0FAE_REG_4 */
4178   {
4179     { Bad_Opcode },
4180     { "ptwrite%LQ", { Edq }, 0 },
4181   },
4182
4183   /* PREFIX_MOD_0_0FAE_REG_5 */
4184   {
4185     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_MOD_3_0FAE_REG_5 */
4189   {
4190     { "lfence",         { Skip_MODRM }, 0 },
4191     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0FAE_REG_6 */
4195   {
4196     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4197     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4198     { "clwb",   { Mb }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0FAE_REG_7 */
4202   {
4203     { "clflush",        { Mb }, 0 },
4204     { Bad_Opcode },
4205     { "clflushopt",     { Mb }, 0 },
4206   },
4207
4208   /* PREFIX_0FB8 */
4209   {
4210     { Bad_Opcode },
4211     { "popcntS", { Gv, Ev }, 0 },
4212   },
4213
4214   /* PREFIX_0FBC */
4215   {
4216     { "bsfS",   { Gv, Ev }, 0 },
4217     { "tzcntS", { Gv, Ev }, 0 },
4218     { "bsfS",   { Gv, Ev }, 0 },
4219   },
4220
4221   /* PREFIX_0FBD */
4222   {
4223     { "bsrS",   { Gv, Ev }, 0 },
4224     { "lzcntS", { Gv, Ev }, 0 },
4225     { "bsrS",   { Gv, Ev }, 0 },
4226   },
4227
4228   /* PREFIX_0FC2 */
4229   {
4230     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4231     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4232     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4233     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_MOD_0_0FC3 */
4237   {
4238     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_MOD_0_0FC7_REG_6 */
4242   {
4243     { "vmptrld",{ Mq }, 0 },
4244     { "vmxon",  { Mq }, 0 },
4245     { "vmclear",{ Mq }, 0 },
4246   },
4247
4248   /* PREFIX_MOD_3_0FC7_REG_6 */
4249   {
4250     { "rdrand", { Ev }, 0 },
4251     { Bad_Opcode },
4252     { "rdrand", { Ev }, 0 }
4253   },
4254
4255   /* PREFIX_MOD_3_0FC7_REG_7 */
4256   {
4257     { "rdseed", { Ev }, 0 },
4258     { "rdpid",  { Em }, 0 },
4259     { "rdseed", { Ev }, 0 },
4260   },
4261
4262   /* PREFIX_0FD0 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "addsubpd", { XM, EXx }, 0 },
4267     { "addsubps", { XM, EXx }, 0 },
4268   },
4269
4270   /* PREFIX_0FD6 */
4271   {
4272     { Bad_Opcode },
4273     { "movq2dq",{ XM, MS }, 0 },
4274     { "movq",   { EXqS, XM }, 0 },
4275     { "movdq2q",{ MX, XS }, 0 },
4276   },
4277
4278   /* PREFIX_0FE6 */
4279   {
4280     { Bad_Opcode },
4281     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4282     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4283     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0FE7 */
4287   {
4288     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4289     { Bad_Opcode },
4290     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4291   },
4292
4293   /* PREFIX_0FF0 */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4299   },
4300
4301   /* PREFIX_0FF7 */
4302   {
4303     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4304     { Bad_Opcode },
4305     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3810 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3814 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3815 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3817 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3820 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3821 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3822 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3823 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3824 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3825 */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F3828 */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F3829 */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F382A */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4397   },
4398
4399   /* PREFIX_0F382B */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3830 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3831 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3832 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3833 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F3834 */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F3835 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3837 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3838 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3839 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F383A */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F383B */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F383C */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F383D */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F383E */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F383F */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3840 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3841 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3880 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3881 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3882 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F38C8 */
4547   {
4548     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F38C9 */
4552   {
4553     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F38CA */
4557   {
4558     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F38CB */
4562   {
4563     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F38CC */
4567   {
4568     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F38CD */
4572   {
4573     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4574   },
4575
4576   /* PREFIX_0F38CF */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4581   },
4582
4583   /* PREFIX_0F38DB */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4588   },
4589
4590   /* PREFIX_0F38DC */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4595   },
4596
4597   /* PREFIX_0F38DD */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F38DE */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4609   },
4610
4611   /* PREFIX_0F38DF */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F38F0 */
4619   {
4620     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4621     { Bad_Opcode },
4622     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4623     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F38F1 */
4627   {
4628     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4629     { Bad_Opcode },
4630     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4631     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F38F5 */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4639   },
4640
4641   /* PREFIX_0F38F6 */
4642   {
4643     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4644     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4645     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4646     { Bad_Opcode },
4647   },
4648
4649   /* PREFIX_0F3A08 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3A09 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3A0A */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3A0B */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_0F3A0C */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4682   },
4683
4684   /* PREFIX_0F3A0D */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4689   },
4690
4691   /* PREFIX_0F3A0E */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4696   },
4697
4698   /* PREFIX_0F3A14 */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4703   },
4704
4705   /* PREFIX_0F3A15 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4710   },
4711
4712   /* PREFIX_0F3A16 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4717   },
4718
4719   /* PREFIX_0F3A17 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4724   },
4725
4726   /* PREFIX_0F3A20 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4731   },
4732
4733   /* PREFIX_0F3A21 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4738   },
4739
4740   /* PREFIX_0F3A22 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4745   },
4746
4747   /* PREFIX_0F3A40 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4752   },
4753
4754   /* PREFIX_0F3A41 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4759   },
4760
4761   /* PREFIX_0F3A42 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4766   },
4767
4768   /* PREFIX_0F3A44 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4773   },
4774
4775   /* PREFIX_0F3A60 */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4780   },
4781
4782   /* PREFIX_0F3A61 */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4787   },
4788
4789   /* PREFIX_0F3A62 */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4794   },
4795
4796   /* PREFIX_0F3A63 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4801   },
4802
4803   /* PREFIX_0F3ACC */
4804   {
4805     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4806   },
4807
4808   /* PREFIX_0F3ACE */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4813   },
4814
4815   /* PREFIX_0F3ACF */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4820   },
4821
4822   /* PREFIX_0F3ADF */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4827   },
4828
4829   /* PREFIX_VEX_0F10 */
4830   {
4831     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4832     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4833     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4834     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4835   },
4836
4837   /* PREFIX_VEX_0F11 */
4838   {
4839     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4840     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4841     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4842     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4843   },
4844
4845   /* PREFIX_VEX_0F12 */
4846   {
4847     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4848     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4849     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4850     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4851   },
4852
4853   /* PREFIX_VEX_0F16 */
4854   {
4855     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4856     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4857     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0F2A */
4861   {
4862     { Bad_Opcode },
4863     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4864     { Bad_Opcode },
4865     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4866   },
4867
4868   /* PREFIX_VEX_0F2C */
4869   {
4870     { Bad_Opcode },
4871     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4872     { Bad_Opcode },
4873     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4874   },
4875
4876   /* PREFIX_VEX_0F2D */
4877   {
4878     { Bad_Opcode },
4879     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4880     { Bad_Opcode },
4881     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4882   },
4883
4884   /* PREFIX_VEX_0F2E */
4885   {
4886     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4887     { Bad_Opcode },
4888     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F2F */
4892   {
4893     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4894     { Bad_Opcode },
4895     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0F41 */
4899   {
4900     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4901     { Bad_Opcode },
4902     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F42 */
4906   {
4907     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4908     { Bad_Opcode },
4909     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F44 */
4913   {
4914     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4915     { Bad_Opcode },
4916     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F45 */
4920   {
4921     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4922     { Bad_Opcode },
4923     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F46 */
4927   {
4928     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4929     { Bad_Opcode },
4930     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F47 */
4934   {
4935     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4936     { Bad_Opcode },
4937     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F4A */
4941   {
4942     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4943     { Bad_Opcode },
4944     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F4B */
4948   {
4949     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4950     { Bad_Opcode },
4951     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F51 */
4955   {
4956     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4957     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4958     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4959     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4960   },
4961
4962   /* PREFIX_VEX_0F52 */
4963   {
4964     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4965     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4966   },
4967
4968   /* PREFIX_VEX_0F53 */
4969   {
4970     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4971     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4972   },
4973
4974   /* PREFIX_VEX_0F58 */
4975   {
4976     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4977     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4978     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4979     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4980   },
4981
4982   /* PREFIX_VEX_0F59 */
4983   {
4984     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4985     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4986     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4987     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4988   },
4989
4990   /* PREFIX_VEX_0F5A */
4991   {
4992     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4993     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4994     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4995     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4996   },
4997
4998   /* PREFIX_VEX_0F5B */
4999   {
5000     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5001     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5002     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_0F5C */
5006   {
5007     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5008     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5009     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5010     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5011   },
5012
5013   /* PREFIX_VEX_0F5D */
5014   {
5015     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5017     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5018     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5019   },
5020
5021   /* PREFIX_VEX_0F5E */
5022   {
5023     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5024     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5025     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5026     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5027   },
5028
5029   /* PREFIX_VEX_0F5F */
5030   {
5031     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5032     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5033     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5034     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5035   },
5036
5037   /* PREFIX_VEX_0F60 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0F61 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0F62 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0F63 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F64 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F65 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0F66 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F67 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F68 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F69 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F6A */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F6B */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F6C */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0F6D */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F6E */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0F6F */
5143   {
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5146     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0F70 */
5150   {
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5153     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5154     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5155   },
5156
5157   /* PREFIX_VEX_0F71_REG_2 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F71_REG_4 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0F71_REG_6 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0F72_REG_2 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0F72_REG_4 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0F72_REG_6 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F73_REG_2 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F73_REG_3 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F73_REG_6 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0F73_REG_7 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0F74 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0F75 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0F76 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0F77 */
5249   {
5250     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5251   },
5252
5253   /* PREFIX_VEX_0F7C */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5258     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5259   },
5260
5261   /* PREFIX_VEX_0F7D */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5266     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5267   },
5268
5269   /* PREFIX_VEX_0F7E */
5270   {
5271     { Bad_Opcode },
5272     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5273     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0F7F */
5277   {
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5280     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0F90 */
5284   {
5285     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5286     { Bad_Opcode },
5287     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0F91 */
5291   {
5292     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5293     { Bad_Opcode },
5294     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0F92 */
5298   {
5299     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5300     { Bad_Opcode },
5301     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5302     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5303   },
5304
5305   /* PREFIX_VEX_0F93 */
5306   {
5307     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5308     { Bad_Opcode },
5309     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5310     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5311   },
5312
5313   /* PREFIX_VEX_0F98 */
5314   {
5315     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5316     { Bad_Opcode },
5317     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5318   },
5319
5320   /* PREFIX_VEX_0F99 */
5321   {
5322     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5323     { Bad_Opcode },
5324     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5325   },
5326
5327   /* PREFIX_VEX_0FC2 */
5328   {
5329     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5330     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5331     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5332     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5333   },
5334
5335   /* PREFIX_VEX_0FC4 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FC5 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FD0 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5354     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5355   },
5356
5357   /* PREFIX_VEX_0FD1 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FD2 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5369   },
5370
5371   /* PREFIX_VEX_0FD3 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FD4 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FD5 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FD6 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FD7 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FD8 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FD9 */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FDA */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FDB */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FDC */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5439   },
5440
5441   /* PREFIX_VEX_0FDD */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FDE */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FDF */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FE0 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0FE1 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0FE2 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0FE3 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0FE4 */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0FE5 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5502   },
5503
5504   /* PREFIX_VEX_0FE6 */
5505   {
5506     { Bad_Opcode },
5507     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5508     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5509     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5510   },
5511
5512   /* PREFIX_VEX_0FE7 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5517   },
5518
5519   /* PREFIX_VEX_0FE8 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0FE9 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0FEA */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0FEB */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0FEC */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0FED */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0FEE */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0FEF */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5573   },
5574
5575   /* PREFIX_VEX_0FF0 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5581   },
5582
5583   /* PREFIX_VEX_0FF1 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0FF2 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0FF3 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0FF4 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0FF5 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0FF6 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0FF7 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0FF8 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0FF9 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0FFA */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0FFB */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5658   },
5659
5660   /* PREFIX_VEX_0FFC */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0FFD */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0FFE */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3800 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F3801 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F3802 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F3803 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F3804 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F3805 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F3806 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5728   },
5729
5730   /* PREFIX_VEX_0F3807 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F3808 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F3809 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F380A */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F380B */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F380C */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F380D */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F380E */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F380F */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3813 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5798   },
5799
5800   /* PREFIX_VEX_0F3816 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3817 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3818 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F3819 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F381A */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F381C */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F381D */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F381E */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3820 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F3821 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F3822 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F3823 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F3824 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F3825 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F3828 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F3829 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F382A */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F382B */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F382C */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F382D */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F382E */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F382F */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3830 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5959   },
5960
5961   /* PREFIX_VEX_0F3831 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3832 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F3833 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F3834 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3835 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F3836 */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F3837 */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F3838 */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6015   },
6016
6017   /* PREFIX_VEX_0F3839 */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6022   },
6023
6024   /* PREFIX_VEX_0F383A */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6029   },
6030
6031   /* PREFIX_VEX_0F383B */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6036   },
6037
6038   /* PREFIX_VEX_0F383C */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6043   },
6044
6045   /* PREFIX_VEX_0F383D */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6050   },
6051
6052   /* PREFIX_VEX_0F383E */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6057   },
6058
6059   /* PREFIX_VEX_0F383F */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6064   },
6065
6066   /* PREFIX_VEX_0F3840 */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6071   },
6072
6073   /* PREFIX_VEX_0F3841 */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6078   },
6079
6080   /* PREFIX_VEX_0F3845 */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F3846 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6092   },
6093
6094   /* PREFIX_VEX_0F3847 */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F3858 */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6106   },
6107
6108   /* PREFIX_VEX_0F3859 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6113   },
6114
6115   /* PREFIX_VEX_0F385A */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6120   },
6121
6122   /* PREFIX_VEX_0F3878 */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6127   },
6128
6129   /* PREFIX_VEX_0F3879 */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6134   },
6135
6136   /* PREFIX_VEX_0F388C */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6141   },
6142
6143   /* PREFIX_VEX_0F388E */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6148   },
6149
6150   /* PREFIX_VEX_0F3890 */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F3891 */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F3892 */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F3893 */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F3896 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F3897 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F3898 */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F3899 */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F389A */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6211   },
6212
6213   /* PREFIX_VEX_0F389B */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F389C */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F389D */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F389E */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F389F */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F38A6 */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6253     { Bad_Opcode },
6254   },
6255
6256   /* PREFIX_VEX_0F38A7 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6261   },
6262
6263   /* PREFIX_VEX_0F38A8 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6268   },
6269
6270   /* PREFIX_VEX_0F38A9 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6275   },
6276
6277   /* PREFIX_VEX_0F38AA */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6282   },
6283
6284   /* PREFIX_VEX_0F38AB */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6289   },
6290
6291   /* PREFIX_VEX_0F38AC */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6296   },
6297
6298   /* PREFIX_VEX_0F38AD */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6303   },
6304
6305   /* PREFIX_VEX_0F38AE */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6310   },
6311
6312   /* PREFIX_VEX_0F38AF */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6317   },
6318
6319   /* PREFIX_VEX_0F38B6 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6324   },
6325
6326   /* PREFIX_VEX_0F38B7 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6331   },
6332
6333   /* PREFIX_VEX_0F38B8 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6338   },
6339
6340   /* PREFIX_VEX_0F38B9 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6345   },
6346
6347   /* PREFIX_VEX_0F38BA */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6352   },
6353
6354   /* PREFIX_VEX_0F38BB */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6359   },
6360
6361   /* PREFIX_VEX_0F38BC */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F38BD */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F38BE */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6380   },
6381
6382   /* PREFIX_VEX_0F38BF */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6387   },
6388
6389   /* PREFIX_VEX_0F38CF */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6394   },
6395
6396   /* PREFIX_VEX_0F38DB */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6401   },
6402
6403   /* PREFIX_VEX_0F38DC */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { "vaesenc",        { XM, Vex, EXx }, 0 },
6408   },
6409
6410   /* PREFIX_VEX_0F38DD */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6415   },
6416
6417   /* PREFIX_VEX_0F38DE */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { "vaesdec",        { XM, Vex, EXx }, 0 },
6422   },
6423
6424   /* PREFIX_VEX_0F38DF */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6429   },
6430
6431   /* PREFIX_VEX_0F38F2 */
6432   {
6433     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6434   },
6435
6436   /* PREFIX_VEX_0F38F3_REG_1 */
6437   {
6438     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6439   },
6440
6441   /* PREFIX_VEX_0F38F3_REG_2 */
6442   {
6443     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6444   },
6445
6446   /* PREFIX_VEX_0F38F3_REG_3 */
6447   {
6448     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6449   },
6450
6451   /* PREFIX_VEX_0F38F5 */
6452   {
6453     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6454     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6457   },
6458
6459   /* PREFIX_VEX_0F38F6 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6465   },
6466
6467   /* PREFIX_VEX_0F38F7 */
6468   {
6469     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6470     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6471     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6472     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A00 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A01 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A02 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A04 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A05 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A06 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A08 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A09 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A0A */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A0B */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6543   },
6544
6545   /* PREFIX_VEX_0F3A0C */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A0D */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A0E */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A0F */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A14 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A15 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A16 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A17 */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A18 */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A19 */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A1D */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6620   },
6621
6622   /* PREFIX_VEX_0F3A20 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6627   },
6628
6629   /* PREFIX_VEX_0F3A21 */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6634   },
6635
6636   /* PREFIX_VEX_0F3A22 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6641   },
6642
6643   /* PREFIX_VEX_0F3A30 */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A31 */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A32 */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6662   },
6663
6664   /* PREFIX_VEX_0F3A33 */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6669   },
6670
6671   /* PREFIX_VEX_0F3A38 */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A39 */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6683   },
6684
6685   /* PREFIX_VEX_0F3A40 */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6690   },
6691
6692   /* PREFIX_VEX_0F3A41 */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3A42 */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3A44 */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6711   },
6712
6713   /* PREFIX_VEX_0F3A46 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6718   },
6719
6720   /* PREFIX_VEX_0F3A48 */
6721   {
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6725   },
6726
6727   /* PREFIX_VEX_0F3A49 */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6732   },
6733
6734   /* PREFIX_VEX_0F3A4A */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6739   },
6740
6741   /* PREFIX_VEX_0F3A4B */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6746   },
6747
6748   /* PREFIX_VEX_0F3A4C */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3A5C */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6760   },
6761
6762   /* PREFIX_VEX_0F3A5D */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6767   },
6768
6769   /* PREFIX_VEX_0F3A5E */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6774   },
6775
6776   /* PREFIX_VEX_0F3A5F */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6781   },
6782
6783   /* PREFIX_VEX_0F3A60 */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6788     { Bad_Opcode },
6789   },
6790
6791   /* PREFIX_VEX_0F3A61 */
6792   {
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6796   },
6797
6798   /* PREFIX_VEX_0F3A62 */
6799   {
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6803   },
6804
6805   /* PREFIX_VEX_0F3A63 */
6806   {
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6810   },
6811
6812   /* PREFIX_VEX_0F3A68 */
6813   {
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6817   },
6818
6819   /* PREFIX_VEX_0F3A69 */
6820   {
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6824   },
6825
6826   /* PREFIX_VEX_0F3A6A */
6827   {
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6831   },
6832
6833   /* PREFIX_VEX_0F3A6B */
6834   {
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6838   },
6839
6840   /* PREFIX_VEX_0F3A6C */
6841   {
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6845   },
6846
6847   /* PREFIX_VEX_0F3A6D */
6848   {
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6852   },
6853
6854   /* PREFIX_VEX_0F3A6E */
6855   {
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6859   },
6860
6861   /* PREFIX_VEX_0F3A6F */
6862   {
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6866   },
6867
6868   /* PREFIX_VEX_0F3A78 */
6869   {
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6873   },
6874
6875   /* PREFIX_VEX_0F3A79 */
6876   {
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6880   },
6881
6882   /* PREFIX_VEX_0F3A7A */
6883   {
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6887   },
6888
6889   /* PREFIX_VEX_0F3A7B */
6890   {
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6894   },
6895
6896   /* PREFIX_VEX_0F3A7C */
6897   {
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6901     { Bad_Opcode },
6902   },
6903
6904   /* PREFIX_VEX_0F3A7D */
6905   {
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6909   },
6910
6911   /* PREFIX_VEX_0F3A7E */
6912   {
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6916   },
6917
6918   /* PREFIX_VEX_0F3A7F */
6919   {
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6923   },
6924
6925   /* PREFIX_VEX_0F3ACE */
6926   {
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6930   },
6931
6932   /* PREFIX_VEX_0F3ACF */
6933   {
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6937   },
6938
6939   /* PREFIX_VEX_0F3ADF */
6940   {
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6944   },
6945
6946   /* PREFIX_VEX_0F3AF0 */
6947   {
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6952   },
6953
6954 #define NEED_PREFIX_TABLE
6955 #include "i386-dis-evex.h"
6956 #undef NEED_PREFIX_TABLE
6957 };
6958
6959 static const struct dis386 x86_64_table[][2] = {
6960   /* X86_64_06 */
6961   {
6962     { "pushP", { es }, 0 },
6963   },
6964
6965   /* X86_64_07 */
6966   {
6967     { "popP", { es }, 0 },
6968   },
6969
6970   /* X86_64_0D */
6971   {
6972     { "pushP", { cs }, 0 },
6973   },
6974
6975   /* X86_64_16 */
6976   {
6977     { "pushP", { ss }, 0 },
6978   },
6979
6980   /* X86_64_17 */
6981   {
6982     { "popP", { ss }, 0 },
6983   },
6984
6985   /* X86_64_1E */
6986   {
6987     { "pushP", { ds }, 0 },
6988   },
6989
6990   /* X86_64_1F */
6991   {
6992     { "popP", { ds }, 0 },
6993   },
6994
6995   /* X86_64_27 */
6996   {
6997     { "daa", { XX }, 0 },
6998   },
6999
7000   /* X86_64_2F */
7001   {
7002     { "das", { XX }, 0 },
7003   },
7004
7005   /* X86_64_37 */
7006   {
7007     { "aaa", { XX }, 0 },
7008   },
7009
7010   /* X86_64_3F */
7011   {
7012     { "aas", { XX }, 0 },
7013   },
7014
7015   /* X86_64_60 */
7016   {
7017     { "pushaP", { XX }, 0 },
7018   },
7019
7020   /* X86_64_61 */
7021   {
7022     { "popaP", { XX }, 0 },
7023   },
7024
7025   /* X86_64_62 */
7026   {
7027     { MOD_TABLE (MOD_62_32BIT) },
7028     { EVEX_TABLE (EVEX_0F) },
7029   },
7030
7031   /* X86_64_63 */
7032   {
7033     { "arpl", { Ew, Gw }, 0 },
7034     { "movs{lq|xd}", { Gv, Ed }, 0 },
7035   },
7036
7037   /* X86_64_6D */
7038   {
7039     { "ins{R|}", { Yzr, indirDX }, 0 },
7040     { "ins{G|}", { Yzr, indirDX }, 0 },
7041   },
7042
7043   /* X86_64_6F */
7044   {
7045     { "outs{R|}", { indirDXr, Xz }, 0 },
7046     { "outs{G|}", { indirDXr, Xz }, 0 },
7047   },
7048
7049   /* X86_64_82 */
7050   {
7051     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7052     { REG_TABLE (REG_80) },
7053   },
7054
7055   /* X86_64_9A */
7056   {
7057     { "Jcall{T|}", { Ap }, 0 },
7058   },
7059
7060   /* X86_64_C4 */
7061   {
7062     { MOD_TABLE (MOD_C4_32BIT) },
7063     { VEX_C4_TABLE (VEX_0F) },
7064   },
7065
7066   /* X86_64_C5 */
7067   {
7068     { MOD_TABLE (MOD_C5_32BIT) },
7069     { VEX_C5_TABLE (VEX_0F) },
7070   },
7071
7072   /* X86_64_CE */
7073   {
7074     { "into", { XX }, 0 },
7075   },
7076
7077   /* X86_64_D4 */
7078   {
7079     { "aam", { Ib }, 0 },
7080   },
7081
7082   /* X86_64_D5 */
7083   {
7084     { "aad", { Ib }, 0 },
7085   },
7086
7087   /* X86_64_E8 */
7088   {
7089     { "callP",          { Jv, BND }, 0 },
7090     { "call@",          { Jv, BND }, 0 }
7091   },
7092
7093   /* X86_64_E9 */
7094   {
7095     { "jmpP",           { Jv, BND }, 0 },
7096     { "jmp@",           { Jv, BND }, 0 }
7097   },
7098
7099   /* X86_64_EA */
7100   {
7101     { "Jjmp{T|}", { Ap }, 0 },
7102   },
7103
7104   /* X86_64_0F01_REG_0 */
7105   {
7106     { "sgdt{Q|IQ}", { M }, 0 },
7107     { "sgdt", { M }, 0 },
7108   },
7109
7110   /* X86_64_0F01_REG_1 */
7111   {
7112     { "sidt{Q|IQ}", { M }, 0 },
7113     { "sidt", { M }, 0 },
7114   },
7115
7116   /* X86_64_0F01_REG_2 */
7117   {
7118     { "lgdt{Q|Q}", { M }, 0 },
7119     { "lgdt", { M }, 0 },
7120   },
7121
7122   /* X86_64_0F01_REG_3 */
7123   {
7124     { "lidt{Q|Q}", { M }, 0 },
7125     { "lidt", { M }, 0 },
7126   },
7127 };
7128
7129 static const struct dis386 three_byte_table[][256] = {
7130
7131   /* THREE_BYTE_0F38 */
7132   {
7133     /* 00 */
7134     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7135     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7136     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7137     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7138     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7139     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7140     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7141     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7142     /* 08 */
7143     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7144     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7145     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7146     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* 10 */
7152     { PREFIX_TABLE (PREFIX_0F3810) },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { PREFIX_TABLE (PREFIX_0F3814) },
7157     { PREFIX_TABLE (PREFIX_0F3815) },
7158     { Bad_Opcode },
7159     { PREFIX_TABLE (PREFIX_0F3817) },
7160     /* 18 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7166     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7167     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7168     { Bad_Opcode },
7169     /* 20 */
7170     { PREFIX_TABLE (PREFIX_0F3820) },
7171     { PREFIX_TABLE (PREFIX_0F3821) },
7172     { PREFIX_TABLE (PREFIX_0F3822) },
7173     { PREFIX_TABLE (PREFIX_0F3823) },
7174     { PREFIX_TABLE (PREFIX_0F3824) },
7175     { PREFIX_TABLE (PREFIX_0F3825) },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* 28 */
7179     { PREFIX_TABLE (PREFIX_0F3828) },
7180     { PREFIX_TABLE (PREFIX_0F3829) },
7181     { PREFIX_TABLE (PREFIX_0F382A) },
7182     { PREFIX_TABLE (PREFIX_0F382B) },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* 30 */
7188     { PREFIX_TABLE (PREFIX_0F3830) },
7189     { PREFIX_TABLE (PREFIX_0F3831) },
7190     { PREFIX_TABLE (PREFIX_0F3832) },
7191     { PREFIX_TABLE (PREFIX_0F3833) },
7192     { PREFIX_TABLE (PREFIX_0F3834) },
7193     { PREFIX_TABLE (PREFIX_0F3835) },
7194     { Bad_Opcode },
7195     { PREFIX_TABLE (PREFIX_0F3837) },
7196     /* 38 */
7197     { PREFIX_TABLE (PREFIX_0F3838) },
7198     { PREFIX_TABLE (PREFIX_0F3839) },
7199     { PREFIX_TABLE (PREFIX_0F383A) },
7200     { PREFIX_TABLE (PREFIX_0F383B) },
7201     { PREFIX_TABLE (PREFIX_0F383C) },
7202     { PREFIX_TABLE (PREFIX_0F383D) },
7203     { PREFIX_TABLE (PREFIX_0F383E) },
7204     { PREFIX_TABLE (PREFIX_0F383F) },
7205     /* 40 */
7206     { PREFIX_TABLE (PREFIX_0F3840) },
7207     { PREFIX_TABLE (PREFIX_0F3841) },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* 48 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* 50 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* 58 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* 60 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* 68 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* 70 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 78 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 80 */
7278     { PREFIX_TABLE (PREFIX_0F3880) },
7279     { PREFIX_TABLE (PREFIX_0F3881) },
7280     { PREFIX_TABLE (PREFIX_0F3882) },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 88 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 90 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 98 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* a0 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* a8 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* b0 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* b8 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* c0 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* c8 */
7359     { PREFIX_TABLE (PREFIX_0F38C8) },
7360     { PREFIX_TABLE (PREFIX_0F38C9) },
7361     { PREFIX_TABLE (PREFIX_0F38CA) },
7362     { PREFIX_TABLE (PREFIX_0F38CB) },
7363     { PREFIX_TABLE (PREFIX_0F38CC) },
7364     { PREFIX_TABLE (PREFIX_0F38CD) },
7365     { Bad_Opcode },
7366     { PREFIX_TABLE (PREFIX_0F38CF) },
7367     /* d0 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* d8 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { PREFIX_TABLE (PREFIX_0F38DB) },
7381     { PREFIX_TABLE (PREFIX_0F38DC) },
7382     { PREFIX_TABLE (PREFIX_0F38DD) },
7383     { PREFIX_TABLE (PREFIX_0F38DE) },
7384     { PREFIX_TABLE (PREFIX_0F38DF) },
7385     /* e0 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* e8 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* f0 */
7404     { PREFIX_TABLE (PREFIX_0F38F0) },
7405     { PREFIX_TABLE (PREFIX_0F38F1) },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { PREFIX_TABLE (PREFIX_0F38F5) },
7410     { PREFIX_TABLE (PREFIX_0F38F6) },
7411     { Bad_Opcode },
7412     /* f8 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421   },
7422   /* THREE_BYTE_0F3A */
7423   {
7424     /* 00 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 08 */
7434     { PREFIX_TABLE (PREFIX_0F3A08) },
7435     { PREFIX_TABLE (PREFIX_0F3A09) },
7436     { PREFIX_TABLE (PREFIX_0F3A0A) },
7437     { PREFIX_TABLE (PREFIX_0F3A0B) },
7438     { PREFIX_TABLE (PREFIX_0F3A0C) },
7439     { PREFIX_TABLE (PREFIX_0F3A0D) },
7440     { PREFIX_TABLE (PREFIX_0F3A0E) },
7441     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7442     /* 10 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { PREFIX_TABLE (PREFIX_0F3A14) },
7448     { PREFIX_TABLE (PREFIX_0F3A15) },
7449     { PREFIX_TABLE (PREFIX_0F3A16) },
7450     { PREFIX_TABLE (PREFIX_0F3A17) },
7451     /* 18 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 20 */
7461     { PREFIX_TABLE (PREFIX_0F3A20) },
7462     { PREFIX_TABLE (PREFIX_0F3A21) },
7463     { PREFIX_TABLE (PREFIX_0F3A22) },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 28 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 30 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 38 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 40 */
7497     { PREFIX_TABLE (PREFIX_0F3A40) },
7498     { PREFIX_TABLE (PREFIX_0F3A41) },
7499     { PREFIX_TABLE (PREFIX_0F3A42) },
7500     { Bad_Opcode },
7501     { PREFIX_TABLE (PREFIX_0F3A44) },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 48 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 50 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 58 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 60 */
7533     { PREFIX_TABLE (PREFIX_0F3A60) },
7534     { PREFIX_TABLE (PREFIX_0F3A61) },
7535     { PREFIX_TABLE (PREFIX_0F3A62) },
7536     { PREFIX_TABLE (PREFIX_0F3A63) },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 68 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 70 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 78 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 80 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 88 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 90 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 98 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* a0 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* a8 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* b0 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* b8 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* c0 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* c8 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { PREFIX_TABLE (PREFIX_0F3ACC) },
7655     { Bad_Opcode },
7656     { PREFIX_TABLE (PREFIX_0F3ACE) },
7657     { PREFIX_TABLE (PREFIX_0F3ACF) },
7658     /* d0 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* d8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { PREFIX_TABLE (PREFIX_0F3ADF) },
7676     /* e0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* e8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* f0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* f8 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712   },
7713 };
7714
7715 static const struct dis386 xop_table[][256] = {
7716   /* XOP_08 */
7717   {
7718     /* 00 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* 08 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* 10 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* 18 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* 20 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* 28 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* 30 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* 38 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     /* 40 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* 48 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* 50 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* 58 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     /* 60 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 68 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 70 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 78 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 80 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7869     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7870     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7871     /* 88 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7879     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7880     /* 90 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7887     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7888     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7889     /* 98 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7897     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7898     /* a0 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7902     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7906     { Bad_Opcode },
7907     /* a8 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* b0 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7924     { Bad_Opcode },
7925     /* b8 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* c0 */
7935     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7936     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7937     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7938     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* c8 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7949     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7950     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7951     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7952     /* d0 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* d8 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* e0 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* e8 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7985     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7986     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7987     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7988     /* f0 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* f8 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006   },
8007   /* XOP_09 */
8008   {
8009     /* 00 */
8010     { Bad_Opcode },
8011     { REG_TABLE (REG_XOP_TBM_01) },
8012     { REG_TABLE (REG_XOP_TBM_02) },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* 08 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* 10 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { REG_TABLE (REG_XOP_LWPCB) },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* 18 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* 20 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* 28 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* 30 */
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* 38 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* 40 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* 48 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* 50 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* 58 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* 60 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* 68 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 70 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 78 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 80 */
8154     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8155     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8156     { "vfrczss",        { XM, EXd }, 0 },
8157     { "vfrczsd",        { XM, EXq }, 0 },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 88 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 90 */
8172     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8178     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8179     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8180     /* 98 */
8181     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8182     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8183     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8184     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* a0 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* a8 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* b0 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* b8 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* c0 */
8226     { Bad_Opcode },
8227     { "vphaddbw",       { XM, EXxmm }, 0 },
8228     { "vphaddbd",       { XM, EXxmm }, 0 },
8229     { "vphaddbq",       { XM, EXxmm }, 0 },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { "vphaddwd",       { XM, EXxmm }, 0 },
8233     { "vphaddwq",       { XM, EXxmm }, 0 },
8234     /* c8 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { "vphadddq",       { XM, EXxmm }, 0 },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* d0 */
8244     { Bad_Opcode },
8245     { "vphaddubw",      { XM, EXxmm }, 0 },
8246     { "vphaddubd",      { XM, EXxmm }, 0 },
8247     { "vphaddubq",      { XM, EXxmm }, 0 },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { "vphadduwd",      { XM, EXxmm }, 0 },
8251     { "vphadduwq",      { XM, EXxmm }, 0 },
8252     /* d8 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { "vphaddudq",      { XM, EXxmm }, 0 },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* e0 */
8262     { Bad_Opcode },
8263     { "vphsubbw",       { XM, EXxmm }, 0 },
8264     { "vphsubwd",       { XM, EXxmm }, 0 },
8265     { "vphsubdq",       { XM, EXxmm }, 0 },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* e8 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* f0 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* f8 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297   },
8298   /* XOP_0A */
8299   {
8300     /* 00 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 08 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 10 */
8319     { "bextr",  { Gv, Ev, Iq }, 0 },
8320     { Bad_Opcode },
8321     { REG_TABLE (REG_XOP_LWP) },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 18 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 20 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 28 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 30 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 38 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 40 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* 48 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 50 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* 58 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* 60 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* 68 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* 70 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* 78 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 80 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 88 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* 90 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 98 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* a0 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* a8 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* b0 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* b8 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* c0 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* c8 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* d0 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     /* d8 */
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     /* e0 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* e8 */
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     /* f0 */
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     /* f8 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588   },
8589 };
8590
8591 static const struct dis386 vex_table[][256] = {
8592   /* VEX_0F */
8593   {
8594     /* 00 */
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* 08 */
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* 10 */
8613     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8616     { MOD_TABLE (MOD_VEX_0F13) },
8617     { VEX_W_TABLE (VEX_W_0F14) },
8618     { VEX_W_TABLE (VEX_W_0F15) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8620     { MOD_TABLE (MOD_VEX_0F17) },
8621     /* 18 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* 20 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* 28 */
8640     { VEX_W_TABLE (VEX_W_0F28) },
8641     { VEX_W_TABLE (VEX_W_0F29) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8643     { MOD_TABLE (MOD_VEX_0F2B) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8648     /* 30 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     /* 38 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* 40 */
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8670     { Bad_Opcode },
8671     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8675     /* 48 */
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     /* 50 */
8685     { MOD_TABLE (MOD_VEX_0F50) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8689     { "vandpX",         { XM, Vex, EXx }, 0 },
8690     { "vandnpX",        { XM, Vex, EXx }, 0 },
8691     { "vorpX",          { XM, Vex, EXx }, 0 },
8692     { "vxorpX",         { XM, Vex, EXx }, 0 },
8693     /* 58 */
8694     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8702     /* 60 */
8703     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8711     /* 68 */
8712     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8720     /* 70 */
8721     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8722     { REG_TABLE (REG_VEX_0F71) },
8723     { REG_TABLE (REG_VEX_0F72) },
8724     { REG_TABLE (REG_VEX_0F73) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8729     /* 78 */
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8738     /* 80 */
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     /* 88 */
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     /* 90 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     /* 98 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     /* a0 */
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     /* a8 */
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { REG_TABLE (REG_VEX_0FAE) },
8791     { Bad_Opcode },
8792     /* b0 */
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* b8 */
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* c0 */
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8814     { Bad_Opcode },
8815     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8816     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8817     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8818     { Bad_Opcode },
8819     /* c8 */
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* d0 */
8829     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8837     /* d8 */
8838     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8846     /* e0 */
8847     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8855     /* e8 */
8856     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8864     /* f0 */
8865     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8873     /* f8 */
8874     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8881     { Bad_Opcode },
8882   },
8883   /* VEX_0F38 */
8884   {
8885     /* 00 */
8886     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8894     /* 08 */
8895     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8903     /* 10 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8912     /* 18 */
8913     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8916     { Bad_Opcode },
8917     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8920     { Bad_Opcode },
8921     /* 20 */
8922     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     /* 28 */
8931     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8939     /* 30 */
8940     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8948     /* 38 */
8949     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8957     /* 40 */
8958     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8966     /* 48 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     /* 50 */
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     /* 58 */
8985     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     /* 60 */
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     /* 68 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     /* 70 */
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     /* 78 */
9021     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* 80 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 88 */
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9044     { Bad_Opcode },
9045     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9046     { Bad_Opcode },
9047     /* 90 */
9048     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9056     /* 98 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9065     /* a0 */
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9074     /* a8 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9083     /* b0 */
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9092     /* b8 */
9093     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9101     /* c0 */
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     /* c8 */
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9119     /* d0 */
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     /* d8 */
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9137     /* e0 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* e8 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* f0 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9159     { REG_TABLE (REG_VEX_0F38F3) },
9160     { Bad_Opcode },
9161     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9164     /* f8 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173   },
9174   /* VEX_0F3A */
9175   {
9176     /* 00 */
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9180     { Bad_Opcode },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9184     { Bad_Opcode },
9185     /* 08 */
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9194     /* 10 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9203     /* 18 */
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* 20 */
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     /* 28 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     /* 30 */
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* 38 */
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     /* 40 */
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9252     { Bad_Opcode },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9254     { Bad_Opcode },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9256     { Bad_Opcode },
9257     /* 48 */
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* 50 */
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* 58 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9284     /* 60 */
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     /* 68 */
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9302     /* 70 */
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     /* 78 */
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9320     /* 80 */
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     /* 88 */
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     /* 90 */
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     /* 98 */
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     /* a0 */
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     /* a8 */
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     /* b0 */
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     /* b8 */
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     /* c0 */
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     /* c8 */
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9409     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9410     /* d0 */
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     /* d8 */
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9428     /* e0 */
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     /* e8 */
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     /* f0 */
9447     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     /* f8 */
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464   },
9465 };
9466
9467 #define NEED_OPCODE_TABLE
9468 #include "i386-dis-evex.h"
9469 #undef NEED_OPCODE_TABLE
9470 static const struct dis386 vex_len_table[][2] = {
9471   /* VEX_LEN_0F10_P_1 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9474     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9475   },
9476
9477   /* VEX_LEN_0F10_P_3 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9480     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9481   },
9482
9483   /* VEX_LEN_0F11_P_1 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9486     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9487   },
9488
9489   /* VEX_LEN_0F11_P_3 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9492     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9493   },
9494
9495   /* VEX_LEN_0F12_P_0_M_0 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9498   },
9499
9500   /* VEX_LEN_0F12_P_0_M_1 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9503   },
9504
9505   /* VEX_LEN_0F12_P_2 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9508   },
9509
9510   /* VEX_LEN_0F13_M_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9513   },
9514
9515   /* VEX_LEN_0F16_P_0_M_0 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9518   },
9519
9520   /* VEX_LEN_0F16_P_0_M_1 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9523   },
9524
9525   /* VEX_LEN_0F16_P_2 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9528   },
9529
9530   /* VEX_LEN_0F17_M_0 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9533   },
9534
9535   /* VEX_LEN_0F2A_P_1 */
9536   {
9537     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9538     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9539   },
9540
9541   /* VEX_LEN_0F2A_P_3 */
9542   {
9543     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9544     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9545   },
9546
9547   /* VEX_LEN_0F2C_P_1 */
9548   {
9549     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9550     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F2C_P_3 */
9554   {
9555     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9556     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9557   },
9558
9559   /* VEX_LEN_0F2D_P_1 */
9560   {
9561     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9562     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9563   },
9564
9565   /* VEX_LEN_0F2D_P_3 */
9566   {
9567     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9568     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F2E_P_0 */
9572   {
9573     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9574     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9575   },
9576
9577   /* VEX_LEN_0F2E_P_2 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9580     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9581   },
9582
9583   /* VEX_LEN_0F2F_P_0 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9586     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9587   },
9588
9589   /* VEX_LEN_0F2F_P_2 */
9590   {
9591     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9592     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F41_P_0 */
9596   {
9597     { Bad_Opcode },
9598     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9599   },
9600   /* VEX_LEN_0F41_P_2 */
9601   {
9602     { Bad_Opcode },
9603     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9604   },
9605   /* VEX_LEN_0F42_P_0 */
9606   {
9607     { Bad_Opcode },
9608     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9609   },
9610   /* VEX_LEN_0F42_P_2 */
9611   {
9612     { Bad_Opcode },
9613     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9614   },
9615   /* VEX_LEN_0F44_P_0 */
9616   {
9617     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9618   },
9619   /* VEX_LEN_0F44_P_2 */
9620   {
9621     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9622   },
9623   /* VEX_LEN_0F45_P_0 */
9624   {
9625     { Bad_Opcode },
9626     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9627   },
9628   /* VEX_LEN_0F45_P_2 */
9629   {
9630     { Bad_Opcode },
9631     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9632   },
9633   /* VEX_LEN_0F46_P_0 */
9634   {
9635     { Bad_Opcode },
9636     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9637   },
9638   /* VEX_LEN_0F46_P_2 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9642   },
9643   /* VEX_LEN_0F47_P_0 */
9644   {
9645     { Bad_Opcode },
9646     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9647   },
9648   /* VEX_LEN_0F47_P_2 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9652   },
9653   /* VEX_LEN_0F4A_P_0 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9657   },
9658   /* VEX_LEN_0F4A_P_2 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9662   },
9663   /* VEX_LEN_0F4B_P_0 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9667   },
9668   /* VEX_LEN_0F4B_P_2 */
9669   {
9670     { Bad_Opcode },
9671     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9672   },
9673
9674   /* VEX_LEN_0F51_P_1 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9677     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9678   },
9679
9680   /* VEX_LEN_0F51_P_3 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9683     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9684   },
9685
9686   /* VEX_LEN_0F52_P_1 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9689     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9690   },
9691
9692   /* VEX_LEN_0F53_P_1 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9695     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9696   },
9697
9698   /* VEX_LEN_0F58_P_1 */
9699   {
9700     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9701     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9702   },
9703
9704   /* VEX_LEN_0F58_P_3 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9707     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9708   },
9709
9710   /* VEX_LEN_0F59_P_1 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9713     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9714   },
9715
9716   /* VEX_LEN_0F59_P_3 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9719     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9720   },
9721
9722   /* VEX_LEN_0F5A_P_1 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9725     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9726   },
9727
9728   /* VEX_LEN_0F5A_P_3 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9731     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9732   },
9733
9734   /* VEX_LEN_0F5C_P_1 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9737     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9738   },
9739
9740   /* VEX_LEN_0F5C_P_3 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9743     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9744   },
9745
9746   /* VEX_LEN_0F5D_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F5D_P_3 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9755     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9756   },
9757
9758   /* VEX_LEN_0F5E_P_1 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9761     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9762   },
9763
9764   /* VEX_LEN_0F5E_P_3 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9767     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9768   },
9769
9770   /* VEX_LEN_0F5F_P_1 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9773     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9774   },
9775
9776   /* VEX_LEN_0F5F_P_3 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9779     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9780   },
9781
9782   /* VEX_LEN_0F6E_P_2 */
9783   {
9784     { "vmovK",          { XMScalar, Edq }, 0 },
9785     { "vmovK",          { XMScalar, Edq }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F7E_P_1 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9791     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9792   },
9793
9794   /* VEX_LEN_0F7E_P_2 */
9795   {
9796     { "vmovK",          { Edq, XMScalar }, 0 },
9797     { "vmovK",          { Edq, XMScalar }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F90_P_0 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9803   },
9804
9805   /* VEX_LEN_0F90_P_2 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9808   },
9809
9810   /* VEX_LEN_0F91_P_0 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9813   },
9814
9815   /* VEX_LEN_0F91_P_2 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9818   },
9819
9820   /* VEX_LEN_0F92_P_0 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9823   },
9824
9825   /* VEX_LEN_0F92_P_2 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9828   },
9829
9830   /* VEX_LEN_0F92_P_3 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9833   },
9834
9835   /* VEX_LEN_0F93_P_0 */
9836   {
9837     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9838   },
9839
9840   /* VEX_LEN_0F93_P_2 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9843   },
9844
9845   /* VEX_LEN_0F93_P_3 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9848   },
9849
9850   /* VEX_LEN_0F98_P_0 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9853   },
9854
9855   /* VEX_LEN_0F98_P_2 */
9856   {
9857     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9858   },
9859
9860   /* VEX_LEN_0F99_P_0 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9863   },
9864
9865   /* VEX_LEN_0F99_P_2 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9868   },
9869
9870   /* VEX_LEN_0FAE_R_2_M_0 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9873   },
9874
9875   /* VEX_LEN_0FAE_R_3_M_0 */
9876   {
9877     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9878   },
9879
9880   /* VEX_LEN_0FC2_P_1 */
9881   {
9882     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9883     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9884   },
9885
9886   /* VEX_LEN_0FC2_P_3 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9889     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9890   },
9891
9892   /* VEX_LEN_0FC4_P_2 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9895   },
9896
9897   /* VEX_LEN_0FC5_P_2 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9900   },
9901
9902   /* VEX_LEN_0FD6_P_2 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9905     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9906   },
9907
9908   /* VEX_LEN_0FF7_P_2 */
9909   {
9910     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9911   },
9912
9913   /* VEX_LEN_0F3816_P_2 */
9914   {
9915     { Bad_Opcode },
9916     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9917   },
9918
9919   /* VEX_LEN_0F3819_P_2 */
9920   {
9921     { Bad_Opcode },
9922     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9923   },
9924
9925   /* VEX_LEN_0F381A_P_2_M_0 */
9926   {
9927     { Bad_Opcode },
9928     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9929   },
9930
9931   /* VEX_LEN_0F3836_P_2 */
9932   {
9933     { Bad_Opcode },
9934     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9935   },
9936
9937   /* VEX_LEN_0F3841_P_2 */
9938   {
9939     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9940   },
9941
9942   /* VEX_LEN_0F385A_P_2_M_0 */
9943   {
9944     { Bad_Opcode },
9945     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9946   },
9947
9948   /* VEX_LEN_0F38DB_P_2 */
9949   {
9950     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F38F2_P_0 */
9954   {
9955     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9956   },
9957
9958   /* VEX_LEN_0F38F3_R_1_P_0 */
9959   {
9960     { "blsrS",          { VexGdq, Edq }, 0 },
9961   },
9962
9963   /* VEX_LEN_0F38F3_R_2_P_0 */
9964   {
9965     { "blsmskS",        { VexGdq, Edq }, 0 },
9966   },
9967
9968   /* VEX_LEN_0F38F3_R_3_P_0 */
9969   {
9970     { "blsiS",          { VexGdq, Edq }, 0 },
9971   },
9972
9973   /* VEX_LEN_0F38F5_P_0 */
9974   {
9975     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9976   },
9977
9978   /* VEX_LEN_0F38F5_P_1 */
9979   {
9980     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9981   },
9982
9983   /* VEX_LEN_0F38F5_P_3 */
9984   {
9985     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9986   },
9987
9988   /* VEX_LEN_0F38F6_P_3 */
9989   {
9990     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9991   },
9992
9993   /* VEX_LEN_0F38F7_P_0 */
9994   {
9995     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9996   },
9997
9998   /* VEX_LEN_0F38F7_P_1 */
9999   {
10000     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10001   },
10002
10003   /* VEX_LEN_0F38F7_P_2 */
10004   {
10005     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10006   },
10007
10008   /* VEX_LEN_0F38F7_P_3 */
10009   {
10010     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10011   },
10012
10013   /* VEX_LEN_0F3A00_P_2 */
10014   {
10015     { Bad_Opcode },
10016     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10017   },
10018
10019   /* VEX_LEN_0F3A01_P_2 */
10020   {
10021     { Bad_Opcode },
10022     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10023   },
10024
10025   /* VEX_LEN_0F3A06_P_2 */
10026   {
10027     { Bad_Opcode },
10028     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10029   },
10030
10031   /* VEX_LEN_0F3A0A_P_2 */
10032   {
10033     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10034     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10035   },
10036
10037   /* VEX_LEN_0F3A0B_P_2 */
10038   {
10039     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10040     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10041   },
10042
10043   /* VEX_LEN_0F3A14_P_2 */
10044   {
10045     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10046   },
10047
10048   /* VEX_LEN_0F3A15_P_2 */
10049   {
10050     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3A16_P_2  */
10054   {
10055     { "vpextrK",        { Edq, XM, Ib }, 0 },
10056   },
10057
10058   /* VEX_LEN_0F3A17_P_2 */
10059   {
10060     { "vextractps",     { Edqd, XM, Ib }, 0 },
10061   },
10062
10063   /* VEX_LEN_0F3A18_P_2 */
10064   {
10065     { Bad_Opcode },
10066     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10067   },
10068
10069   /* VEX_LEN_0F3A19_P_2 */
10070   {
10071     { Bad_Opcode },
10072     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F3A20_P_2 */
10076   {
10077     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10078   },
10079
10080   /* VEX_LEN_0F3A21_P_2 */
10081   {
10082     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A22_P_2 */
10086   {
10087     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10088   },
10089
10090   /* VEX_LEN_0F3A30_P_2 */
10091   {
10092     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10093   },
10094
10095   /* VEX_LEN_0F3A31_P_2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10098   },
10099
10100   /* VEX_LEN_0F3A32_P_2 */
10101   {
10102     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10103   },
10104
10105   /* VEX_LEN_0F3A33_P_2 */
10106   {
10107     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10108   },
10109
10110   /* VEX_LEN_0F3A38_P_2 */
10111   {
10112     { Bad_Opcode },
10113     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10114   },
10115
10116   /* VEX_LEN_0F3A39_P_2 */
10117   {
10118     { Bad_Opcode },
10119     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10120   },
10121
10122   /* VEX_LEN_0F3A41_P_2 */
10123   {
10124     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10125   },
10126
10127   /* VEX_LEN_0F3A46_P_2 */
10128   {
10129     { Bad_Opcode },
10130     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10131   },
10132
10133   /* VEX_LEN_0F3A60_P_2 */
10134   {
10135     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10136   },
10137
10138   /* VEX_LEN_0F3A61_P_2 */
10139   {
10140     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10141   },
10142
10143   /* VEX_LEN_0F3A62_P_2 */
10144   {
10145     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10146   },
10147
10148   /* VEX_LEN_0F3A63_P_2 */
10149   {
10150     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10151   },
10152
10153   /* VEX_LEN_0F3A6A_P_2 */
10154   {
10155     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10156   },
10157
10158   /* VEX_LEN_0F3A6B_P_2 */
10159   {
10160     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10161   },
10162
10163   /* VEX_LEN_0F3A6E_P_2 */
10164   {
10165     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10166   },
10167
10168   /* VEX_LEN_0F3A6F_P_2 */
10169   {
10170     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10171   },
10172
10173   /* VEX_LEN_0F3A7A_P_2 */
10174   {
10175     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10176   },
10177
10178   /* VEX_LEN_0F3A7B_P_2 */
10179   {
10180     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10181   },
10182
10183   /* VEX_LEN_0F3A7E_P_2 */
10184   {
10185     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10186   },
10187
10188   /* VEX_LEN_0F3A7F_P_2 */
10189   {
10190     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10191   },
10192
10193   /* VEX_LEN_0F3ADF_P_2 */
10194   {
10195     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10196   },
10197
10198   /* VEX_LEN_0F3AF0_P_3 */
10199   {
10200     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10201   },
10202
10203   /* VEX_LEN_0FXOP_08_CC */
10204   {
10205      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10206   },
10207
10208   /* VEX_LEN_0FXOP_08_CD */
10209   {
10210      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10211   },
10212
10213   /* VEX_LEN_0FXOP_08_CE */
10214   {
10215      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10216   },
10217
10218   /* VEX_LEN_0FXOP_08_CF */
10219   {
10220      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10221   },
10222
10223   /* VEX_LEN_0FXOP_08_EC */
10224   {
10225      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10226   },
10227
10228   /* VEX_LEN_0FXOP_08_ED */
10229   {
10230      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10231   },
10232
10233   /* VEX_LEN_0FXOP_08_EE */
10234   {
10235      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10236   },
10237
10238   /* VEX_LEN_0FXOP_08_EF */
10239   {
10240      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10241   },
10242
10243   /* VEX_LEN_0FXOP_09_80 */
10244   {
10245     { "vfrczps",        { XM, EXxmm }, 0 },
10246     { "vfrczps",        { XM, EXymmq }, 0 },
10247   },
10248
10249   /* VEX_LEN_0FXOP_09_81 */
10250   {
10251     { "vfrczpd",        { XM, EXxmm }, 0 },
10252     { "vfrczpd",        { XM, EXymmq }, 0 },
10253   },
10254 };
10255
10256 static const struct dis386 vex_w_table[][2] = {
10257   {
10258     /* VEX_W_0F10_P_0 */
10259     { "vmovups",        { XM, EXx }, 0 },
10260   },
10261   {
10262     /* VEX_W_0F10_P_1 */
10263     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10264   },
10265   {
10266     /* VEX_W_0F10_P_2 */
10267     { "vmovupd",        { XM, EXx }, 0 },
10268   },
10269   {
10270     /* VEX_W_0F10_P_3 */
10271     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10272   },
10273   {
10274     /* VEX_W_0F11_P_0 */
10275     { "vmovups",        { EXxS, XM }, 0 },
10276   },
10277   {
10278     /* VEX_W_0F11_P_1 */
10279     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10280   },
10281   {
10282     /* VEX_W_0F11_P_2 */
10283     { "vmovupd",        { EXxS, XM }, 0 },
10284   },
10285   {
10286     /* VEX_W_0F11_P_3 */
10287     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10288   },
10289   {
10290     /* VEX_W_0F12_P_0_M_0 */
10291     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10292   },
10293   {
10294     /* VEX_W_0F12_P_0_M_1 */
10295     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10296   },
10297   {
10298     /* VEX_W_0F12_P_1 */
10299     { "vmovsldup",      { XM, EXx }, 0 },
10300   },
10301   {
10302     /* VEX_W_0F12_P_2 */
10303     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10304   },
10305   {
10306     /* VEX_W_0F12_P_3 */
10307     { "vmovddup",       { XM, EXymmq }, 0 },
10308   },
10309   {
10310     /* VEX_W_0F13_M_0 */
10311     { "vmovlpX",        { EXq, XM }, 0 },
10312   },
10313   {
10314     /* VEX_W_0F14 */
10315     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10316   },
10317   {
10318     /* VEX_W_0F15 */
10319     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F16_P_0_M_0 */
10323     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F16_P_0_M_1 */
10327     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F16_P_1 */
10331     { "vmovshdup",      { XM, EXx }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F16_P_2 */
10335     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F17_M_0 */
10339     { "vmovhpX",        { EXq, XM }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F28 */
10343     { "vmovapX",        { XM, EXx }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F29 */
10347     { "vmovapX",        { EXxS, XM }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F2B_M_0 */
10351     { "vmovntpX",       { Mx, XM }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F2E_P_0 */
10355     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F2E_P_2 */
10359     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F2F_P_0 */
10363     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10364   },
10365   {
10366     /* VEX_W_0F2F_P_2 */
10367     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10368   },
10369   {
10370     /* VEX_W_0F41_P_0_LEN_1 */
10371     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10372     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10373   },
10374   {
10375     /* VEX_W_0F41_P_2_LEN_1 */
10376     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10377     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10378   },
10379   {
10380     /* VEX_W_0F42_P_0_LEN_1 */
10381     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10382     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10383   },
10384   {
10385     /* VEX_W_0F42_P_2_LEN_1 */
10386     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10387     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10388   },
10389   {
10390     /* VEX_W_0F44_P_0_LEN_0 */
10391     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10392     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10393   },
10394   {
10395     /* VEX_W_0F44_P_2_LEN_0 */
10396     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10397     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10398   },
10399   {
10400     /* VEX_W_0F45_P_0_LEN_1 */
10401     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10402     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10403   },
10404   {
10405     /* VEX_W_0F45_P_2_LEN_1 */
10406     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10407     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10408   },
10409   {
10410     /* VEX_W_0F46_P_0_LEN_1 */
10411     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10412     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10413   },
10414   {
10415     /* VEX_W_0F46_P_2_LEN_1 */
10416     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10417     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10418   },
10419   {
10420     /* VEX_W_0F47_P_0_LEN_1 */
10421     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10422     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10423   },
10424   {
10425     /* VEX_W_0F47_P_2_LEN_1 */
10426     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10427     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10428   },
10429   {
10430     /* VEX_W_0F4A_P_0_LEN_1 */
10431     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10432     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10433   },
10434   {
10435     /* VEX_W_0F4A_P_2_LEN_1 */
10436     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10437     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10438   },
10439   {
10440     /* VEX_W_0F4B_P_0_LEN_1 */
10441     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10442     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10443   },
10444   {
10445     /* VEX_W_0F4B_P_2_LEN_1 */
10446     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10447   },
10448   {
10449     /* VEX_W_0F50_M_0 */
10450     { "vmovmskpX",      { Gdq, XS }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F51_P_0 */
10454     { "vsqrtps",        { XM, EXx }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F51_P_1 */
10458     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F51_P_2  */
10462     { "vsqrtpd",        { XM, EXx }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F51_P_3 */
10466     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F52_P_0 */
10470     { "vrsqrtps",       { XM, EXx }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F52_P_1 */
10474     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F53_P_0  */
10478     { "vrcpps",         { XM, EXx }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F53_P_1  */
10482     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F58_P_0  */
10486     { "vaddps",         { XM, Vex, EXx }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F58_P_1  */
10490     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F58_P_2  */
10494     { "vaddpd",         { XM, Vex, EXx }, 0 },
10495   },
10496   {
10497     /* VEX_W_0F58_P_3  */
10498     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F59_P_0  */
10502     { "vmulps",         { XM, Vex, EXx }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F59_P_1  */
10506     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F59_P_2  */
10510     { "vmulpd",         { XM, Vex, EXx }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F59_P_3  */
10514     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F5A_P_0  */
10518     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F5A_P_1  */
10522     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F5A_P_3  */
10526     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F5B_P_0  */
10530     { "vcvtdq2ps",      { XM, EXx }, 0 },
10531   },
10532   {
10533     /* VEX_W_0F5B_P_1  */
10534     { "vcvttps2dq",     { XM, EXx }, 0 },
10535   },
10536   {
10537     /* VEX_W_0F5B_P_2  */
10538     { "vcvtps2dq",      { XM, EXx }, 0 },
10539   },
10540   {
10541     /* VEX_W_0F5C_P_0  */
10542     { "vsubps",         { XM, Vex, EXx }, 0 },
10543   },
10544   {
10545     /* VEX_W_0F5C_P_1  */
10546     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10547   },
10548   {
10549     /* VEX_W_0F5C_P_2  */
10550     { "vsubpd",         { XM, Vex, EXx }, 0 },
10551   },
10552   {
10553     /* VEX_W_0F5C_P_3  */
10554     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10555   },
10556   {
10557     /* VEX_W_0F5D_P_0  */
10558     { "vminps",         { XM, Vex, EXx }, 0 },
10559   },
10560   {
10561     /* VEX_W_0F5D_P_1  */
10562     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10563   },
10564   {
10565     /* VEX_W_0F5D_P_2  */
10566     { "vminpd",         { XM, Vex, EXx }, 0 },
10567   },
10568   {
10569     /* VEX_W_0F5D_P_3  */
10570     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10571   },
10572   {
10573     /* VEX_W_0F5E_P_0  */
10574     { "vdivps",         { XM, Vex, EXx }, 0 },
10575   },
10576   {
10577     /* VEX_W_0F5E_P_1  */
10578     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10579   },
10580   {
10581     /* VEX_W_0F5E_P_2  */
10582     { "vdivpd",         { XM, Vex, EXx }, 0 },
10583   },
10584   {
10585     /* VEX_W_0F5E_P_3  */
10586     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10587   },
10588   {
10589     /* VEX_W_0F5F_P_0  */
10590     { "vmaxps",         { XM, Vex, EXx }, 0 },
10591   },
10592   {
10593     /* VEX_W_0F5F_P_1  */
10594     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10595   },
10596   {
10597     /* VEX_W_0F5F_P_2  */
10598     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10599   },
10600   {
10601     /* VEX_W_0F5F_P_3  */
10602     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10603   },
10604   {
10605     /* VEX_W_0F60_P_2  */
10606     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10607   },
10608   {
10609     /* VEX_W_0F61_P_2  */
10610     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10611   },
10612   {
10613     /* VEX_W_0F62_P_2  */
10614     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10615   },
10616   {
10617     /* VEX_W_0F63_P_2  */
10618     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10619   },
10620   {
10621     /* VEX_W_0F64_P_2  */
10622     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10623   },
10624   {
10625     /* VEX_W_0F65_P_2  */
10626     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10627   },
10628   {
10629     /* VEX_W_0F66_P_2  */
10630     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10631   },
10632   {
10633     /* VEX_W_0F67_P_2  */
10634     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10635   },
10636   {
10637     /* VEX_W_0F68_P_2  */
10638     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10639   },
10640   {
10641     /* VEX_W_0F69_P_2  */
10642     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10643   },
10644   {
10645     /* VEX_W_0F6A_P_2  */
10646     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10647   },
10648   {
10649     /* VEX_W_0F6B_P_2  */
10650     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10651   },
10652   {
10653     /* VEX_W_0F6C_P_2  */
10654     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10655   },
10656   {
10657     /* VEX_W_0F6D_P_2  */
10658     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10659   },
10660   {
10661     /* VEX_W_0F6F_P_1  */
10662     { "vmovdqu",        { XM, EXx }, 0 },
10663   },
10664   {
10665     /* VEX_W_0F6F_P_2  */
10666     { "vmovdqa",        { XM, EXx }, 0 },
10667   },
10668   {
10669     /* VEX_W_0F70_P_1 */
10670     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10671   },
10672   {
10673     /* VEX_W_0F70_P_2 */
10674     { "vpshufd",        { XM, EXx, Ib }, 0 },
10675   },
10676   {
10677     /* VEX_W_0F70_P_3 */
10678     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10679   },
10680   {
10681     /* VEX_W_0F71_R_2_P_2  */
10682     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10683   },
10684   {
10685     /* VEX_W_0F71_R_4_P_2  */
10686     { "vpsraw",         { Vex, XS, Ib }, 0 },
10687   },
10688   {
10689     /* VEX_W_0F71_R_6_P_2  */
10690     { "vpsllw",         { Vex, XS, Ib }, 0 },
10691   },
10692   {
10693     /* VEX_W_0F72_R_2_P_2  */
10694     { "vpsrld",         { Vex, XS, Ib }, 0 },
10695   },
10696   {
10697     /* VEX_W_0F72_R_4_P_2  */
10698     { "vpsrad",         { Vex, XS, Ib }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F72_R_6_P_2  */
10702     { "vpslld",         { Vex, XS, Ib }, 0 },
10703   },
10704   {
10705     /* VEX_W_0F73_R_2_P_2  */
10706     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F73_R_3_P_2  */
10710     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10711   },
10712   {
10713     /* VEX_W_0F73_R_6_P_2  */
10714     { "vpsllq",         { Vex, XS, Ib }, 0 },
10715   },
10716   {
10717     /* VEX_W_0F73_R_7_P_2  */
10718     { "vpslldq",        { Vex, XS, Ib }, 0 },
10719   },
10720   {
10721     /* VEX_W_0F74_P_2 */
10722     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10723   },
10724   {
10725     /* VEX_W_0F75_P_2 */
10726     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F76_P_2 */
10730     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10731   },
10732   {
10733     /* VEX_W_0F77_P_0 */
10734     { "",               { VZERO }, 0 },
10735   },
10736   {
10737     /* VEX_W_0F7C_P_2 */
10738     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10739   },
10740   {
10741     /* VEX_W_0F7C_P_3 */
10742     { "vhaddps",        { XM, Vex, EXx }, 0 },
10743   },
10744   {
10745     /* VEX_W_0F7D_P_2 */
10746     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10747   },
10748   {
10749     /* VEX_W_0F7D_P_3 */
10750     { "vhsubps",        { XM, Vex, EXx }, 0 },
10751   },
10752   {
10753     /* VEX_W_0F7E_P_1 */
10754     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10755   },
10756   {
10757     /* VEX_W_0F7F_P_1 */
10758     { "vmovdqu",        { EXxS, XM }, 0 },
10759   },
10760   {
10761     /* VEX_W_0F7F_P_2 */
10762     { "vmovdqa",        { EXxS, XM }, 0 },
10763   },
10764   {
10765     /* VEX_W_0F90_P_0_LEN_0 */
10766     { "kmovw",          { MaskG, MaskE }, 0 },
10767     { "kmovq",          { MaskG, MaskE }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F90_P_2_LEN_0 */
10771     { "kmovb",          { MaskG, MaskBDE }, 0 },
10772     { "kmovd",          { MaskG, MaskBDE }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F91_P_0_LEN_0 */
10776     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10777     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10778   },
10779   {
10780     /* VEX_W_0F91_P_2_LEN_0 */
10781     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10782     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10783   },
10784   {
10785     /* VEX_W_0F92_P_0_LEN_0 */
10786     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10787   },
10788   {
10789     /* VEX_W_0F92_P_2_LEN_0 */
10790     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10791   },
10792   {
10793     /* VEX_W_0F92_P_3_LEN_0 */
10794     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10795     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10796   },
10797   {
10798     /* VEX_W_0F93_P_0_LEN_0 */
10799     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10800   },
10801   {
10802     /* VEX_W_0F93_P_2_LEN_0 */
10803     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10804   },
10805   {
10806     /* VEX_W_0F93_P_3_LEN_0 */
10807     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10808     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10809   },
10810   {
10811     /* VEX_W_0F98_P_0_LEN_0 */
10812     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10813     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10814   },
10815   {
10816     /* VEX_W_0F98_P_2_LEN_0 */
10817     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10818     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10819   },
10820   {
10821     /* VEX_W_0F99_P_0_LEN_0 */
10822     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10823     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10824   },
10825   {
10826     /* VEX_W_0F99_P_2_LEN_0 */
10827     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10828     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10829   },
10830   {
10831     /* VEX_W_0FAE_R_2_M_0 */
10832     { "vldmxcsr",       { Md }, 0 },
10833   },
10834   {
10835     /* VEX_W_0FAE_R_3_M_0 */
10836     { "vstmxcsr",       { Md }, 0 },
10837   },
10838   {
10839     /* VEX_W_0FC2_P_0 */
10840     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10841   },
10842   {
10843     /* VEX_W_0FC2_P_1 */
10844     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10845   },
10846   {
10847     /* VEX_W_0FC2_P_2 */
10848     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10849   },
10850   {
10851     /* VEX_W_0FC2_P_3 */
10852     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10853   },
10854   {
10855     /* VEX_W_0FC4_P_2 */
10856     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10857   },
10858   {
10859     /* VEX_W_0FC5_P_2 */
10860     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10861   },
10862   {
10863     /* VEX_W_0FD0_P_2 */
10864     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10865   },
10866   {
10867     /* VEX_W_0FD0_P_3 */
10868     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10869   },
10870   {
10871     /* VEX_W_0FD1_P_2 */
10872     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10873   },
10874   {
10875     /* VEX_W_0FD2_P_2 */
10876     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10877   },
10878   {
10879     /* VEX_W_0FD3_P_2 */
10880     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10881   },
10882   {
10883     /* VEX_W_0FD4_P_2 */
10884     { "vpaddq",         { XM, Vex, EXx }, 0 },
10885   },
10886   {
10887     /* VEX_W_0FD5_P_2 */
10888     { "vpmullw",        { XM, Vex, EXx }, 0 },
10889   },
10890   {
10891     /* VEX_W_0FD6_P_2 */
10892     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10893   },
10894   {
10895     /* VEX_W_0FD7_P_2_M_1 */
10896     { "vpmovmskb",      { Gdq, XS }, 0 },
10897   },
10898   {
10899     /* VEX_W_0FD8_P_2 */
10900     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10901   },
10902   {
10903     /* VEX_W_0FD9_P_2 */
10904     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10905   },
10906   {
10907     /* VEX_W_0FDA_P_2 */
10908     { "vpminub",        { XM, Vex, EXx }, 0 },
10909   },
10910   {
10911     /* VEX_W_0FDB_P_2 */
10912     { "vpand",          { XM, Vex, EXx }, 0 },
10913   },
10914   {
10915     /* VEX_W_0FDC_P_2 */
10916     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10917   },
10918   {
10919     /* VEX_W_0FDD_P_2 */
10920     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10921   },
10922   {
10923     /* VEX_W_0FDE_P_2 */
10924     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10925   },
10926   {
10927     /* VEX_W_0FDF_P_2 */
10928     { "vpandn",         { XM, Vex, EXx }, 0 },
10929   },
10930   {
10931     /* VEX_W_0FE0_P_2  */
10932     { "vpavgb",         { XM, Vex, EXx }, 0 },
10933   },
10934   {
10935     /* VEX_W_0FE1_P_2  */
10936     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10937   },
10938   {
10939     /* VEX_W_0FE2_P_2  */
10940     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10941   },
10942   {
10943     /* VEX_W_0FE3_P_2  */
10944     { "vpavgw",         { XM, Vex, EXx }, 0 },
10945   },
10946   {
10947     /* VEX_W_0FE4_P_2  */
10948     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10949   },
10950   {
10951     /* VEX_W_0FE5_P_2  */
10952     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10953   },
10954   {
10955     /* VEX_W_0FE6_P_1  */
10956     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10957   },
10958   {
10959     /* VEX_W_0FE6_P_2  */
10960     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10961   },
10962   {
10963     /* VEX_W_0FE6_P_3  */
10964     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10965   },
10966   {
10967     /* VEX_W_0FE7_P_2_M_0 */
10968     { "vmovntdq",       { Mx, XM }, 0 },
10969   },
10970   {
10971     /* VEX_W_0FE8_P_2  */
10972     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10973   },
10974   {
10975     /* VEX_W_0FE9_P_2  */
10976     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10977   },
10978   {
10979     /* VEX_W_0FEA_P_2  */
10980     { "vpminsw",        { XM, Vex, EXx }, 0 },
10981   },
10982   {
10983     /* VEX_W_0FEB_P_2  */
10984     { "vpor",           { XM, Vex, EXx }, 0 },
10985   },
10986   {
10987     /* VEX_W_0FEC_P_2  */
10988     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10989   },
10990   {
10991     /* VEX_W_0FED_P_2  */
10992     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10993   },
10994   {
10995     /* VEX_W_0FEE_P_2  */
10996     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10997   },
10998   {
10999     /* VEX_W_0FEF_P_2  */
11000     { "vpxor",          { XM, Vex, EXx }, 0 },
11001   },
11002   {
11003     /* VEX_W_0FF0_P_3_M_0 */
11004     { "vlddqu",         { XM, M }, 0 },
11005   },
11006   {
11007     /* VEX_W_0FF1_P_2 */
11008     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11009   },
11010   {
11011     /* VEX_W_0FF2_P_2 */
11012     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11013   },
11014   {
11015     /* VEX_W_0FF3_P_2 */
11016     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11017   },
11018   {
11019     /* VEX_W_0FF4_P_2 */
11020     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11021   },
11022   {
11023     /* VEX_W_0FF5_P_2 */
11024     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11025   },
11026   {
11027     /* VEX_W_0FF6_P_2 */
11028     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11029   },
11030   {
11031     /* VEX_W_0FF7_P_2 */
11032     { "vmaskmovdqu",    { XM, XS }, 0 },
11033   },
11034   {
11035     /* VEX_W_0FF8_P_2 */
11036     { "vpsubb",         { XM, Vex, EXx }, 0 },
11037   },
11038   {
11039     /* VEX_W_0FF9_P_2 */
11040     { "vpsubw",         { XM, Vex, EXx }, 0 },
11041   },
11042   {
11043     /* VEX_W_0FFA_P_2 */
11044     { "vpsubd",         { XM, Vex, EXx }, 0 },
11045   },
11046   {
11047     /* VEX_W_0FFB_P_2 */
11048     { "vpsubq",         { XM, Vex, EXx }, 0 },
11049   },
11050   {
11051     /* VEX_W_0FFC_P_2 */
11052     { "vpaddb",         { XM, Vex, EXx }, 0 },
11053   },
11054   {
11055     /* VEX_W_0FFD_P_2 */
11056     { "vpaddw",         { XM, Vex, EXx }, 0 },
11057   },
11058   {
11059     /* VEX_W_0FFE_P_2 */
11060     { "vpaddd",         { XM, Vex, EXx }, 0 },
11061   },
11062   {
11063     /* VEX_W_0F3800_P_2  */
11064     { "vpshufb",        { XM, Vex, EXx }, 0 },
11065   },
11066   {
11067     /* VEX_W_0F3801_P_2  */
11068     { "vphaddw",        { XM, Vex, EXx }, 0 },
11069   },
11070   {
11071     /* VEX_W_0F3802_P_2  */
11072     { "vphaddd",        { XM, Vex, EXx }, 0 },
11073   },
11074   {
11075     /* VEX_W_0F3803_P_2  */
11076     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11077   },
11078   {
11079     /* VEX_W_0F3804_P_2  */
11080     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11081   },
11082   {
11083     /* VEX_W_0F3805_P_2  */
11084     { "vphsubw",        { XM, Vex, EXx }, 0 },
11085   },
11086   {
11087     /* VEX_W_0F3806_P_2  */
11088     { "vphsubd",        { XM, Vex, EXx }, 0 },
11089   },
11090   {
11091     /* VEX_W_0F3807_P_2  */
11092     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11093   },
11094   {
11095     /* VEX_W_0F3808_P_2  */
11096     { "vpsignb",        { XM, Vex, EXx }, 0 },
11097   },
11098   {
11099     /* VEX_W_0F3809_P_2  */
11100     { "vpsignw",        { XM, Vex, EXx }, 0 },
11101   },
11102   {
11103     /* VEX_W_0F380A_P_2  */
11104     { "vpsignd",        { XM, Vex, EXx }, 0 },
11105   },
11106   {
11107     /* VEX_W_0F380B_P_2  */
11108     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11109   },
11110   {
11111     /* VEX_W_0F380C_P_2  */
11112     { "vpermilps",      { XM, Vex, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0F380D_P_2  */
11116     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0F380E_P_2  */
11120     { "vtestps",        { XM, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0F380F_P_2  */
11124     { "vtestpd",        { XM, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0F3816_P_2  */
11128     { "vpermps",        { XM, Vex, EXx }, 0 },
11129   },
11130   {
11131     /* VEX_W_0F3817_P_2 */
11132     { "vptest",         { XM, EXx }, 0 },
11133   },
11134   {
11135     /* VEX_W_0F3818_P_2 */
11136     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11137   },
11138   {
11139     /* VEX_W_0F3819_P_2 */
11140     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11141   },
11142   {
11143     /* VEX_W_0F381A_P_2_M_0 */
11144     { "vbroadcastf128", { XM, Mxmm }, 0 },
11145   },
11146   {
11147     /* VEX_W_0F381C_P_2 */
11148     { "vpabsb",         { XM, EXx }, 0 },
11149   },
11150   {
11151     /* VEX_W_0F381D_P_2 */
11152     { "vpabsw",         { XM, EXx }, 0 },
11153   },
11154   {
11155     /* VEX_W_0F381E_P_2 */
11156     { "vpabsd",         { XM, EXx }, 0 },
11157   },
11158   {
11159     /* VEX_W_0F3820_P_2 */
11160     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11161   },
11162   {
11163     /* VEX_W_0F3821_P_2 */
11164     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11165   },
11166   {
11167     /* VEX_W_0F3822_P_2 */
11168     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11169   },
11170   {
11171     /* VEX_W_0F3823_P_2 */
11172     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11173   },
11174   {
11175     /* VEX_W_0F3824_P_2 */
11176     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11177   },
11178   {
11179     /* VEX_W_0F3825_P_2 */
11180     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11181   },
11182   {
11183     /* VEX_W_0F3828_P_2 */
11184     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0F3829_P_2 */
11188     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0F382A_P_2_M_0 */
11192     { "vmovntdqa",      { XM, Mx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0F382B_P_2 */
11196     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11197   },
11198   {
11199     /* VEX_W_0F382C_P_2_M_0 */
11200     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11201   },
11202   {
11203     /* VEX_W_0F382D_P_2_M_0 */
11204     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11205   },
11206   {
11207     /* VEX_W_0F382E_P_2_M_0 */
11208     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11209   },
11210   {
11211     /* VEX_W_0F382F_P_2_M_0 */
11212     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11213   },
11214   {
11215     /* VEX_W_0F3830_P_2 */
11216     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11217   },
11218   {
11219     /* VEX_W_0F3831_P_2 */
11220     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11221   },
11222   {
11223     /* VEX_W_0F3832_P_2 */
11224     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11225   },
11226   {
11227     /* VEX_W_0F3833_P_2 */
11228     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11229   },
11230   {
11231     /* VEX_W_0F3834_P_2 */
11232     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11233   },
11234   {
11235     /* VEX_W_0F3835_P_2 */
11236     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11237   },
11238   {
11239     /* VEX_W_0F3836_P_2  */
11240     { "vpermd",         { XM, Vex, EXx }, 0 },
11241   },
11242   {
11243     /* VEX_W_0F3837_P_2 */
11244     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11245   },
11246   {
11247     /* VEX_W_0F3838_P_2 */
11248     { "vpminsb",        { XM, Vex, EXx }, 0 },
11249   },
11250   {
11251     /* VEX_W_0F3839_P_2 */
11252     { "vpminsd",        { XM, Vex, EXx }, 0 },
11253   },
11254   {
11255     /* VEX_W_0F383A_P_2 */
11256     { "vpminuw",        { XM, Vex, EXx }, 0 },
11257   },
11258   {
11259     /* VEX_W_0F383B_P_2 */
11260     { "vpminud",        { XM, Vex, EXx }, 0 },
11261   },
11262   {
11263     /* VEX_W_0F383C_P_2 */
11264     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F383D_P_2 */
11268     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F383E_P_2 */
11272     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F383F_P_2 */
11276     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3840_P_2 */
11280     { "vpmulld",        { XM, Vex, EXx }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3841_P_2 */
11284     { "vphminposuw",    { XM, EXx }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3846_P_2 */
11288     { "vpsravd",        { XM, Vex, EXx }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3858_P_2 */
11292     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3859_P_2 */
11296     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F385A_P_2_M_0 */
11300     { "vbroadcasti128", { XM, Mxmm }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3878_P_2 */
11304     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3879_P_2 */
11308     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F38CF_P_2 */
11312     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F38DB_P_2 */
11316     { "vaesimc",        { XM, EXx }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3A00_P_2 */
11320     { Bad_Opcode },
11321     { "vpermq",         { XM, EXx, Ib }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F3A01_P_2 */
11325     { Bad_Opcode },
11326     { "vpermpd",        { XM, EXx, Ib }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3A02_P_2 */
11330     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F3A04_P_2 */
11334     { "vpermilps",      { XM, EXx, Ib }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3A05_P_2 */
11338     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3A06_P_2 */
11342     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F3A08_P_2 */
11346     { "vroundps",       { XM, EXx, Ib }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F3A09_P_2 */
11350     { "vroundpd",       { XM, EXx, Ib }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F3A0A_P_2 */
11354     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3A0B_P_2 */
11358     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3A0C_P_2 */
11362     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3A0D_P_2 */
11366     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F3A0E_P_2 */
11370     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3A0F_P_2 */
11374     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F3A14_P_2 */
11378     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3A15_P_2 */
11382     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F3A18_P_2 */
11386     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3A19_P_2 */
11390     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F3A20_P_2 */
11394     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3A21_P_2 */
11398     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F3A30_P_2_LEN_0 */
11402     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11403     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11404   },
11405   {
11406     /* VEX_W_0F3A31_P_2_LEN_0 */
11407     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11408     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11409   },
11410   {
11411     /* VEX_W_0F3A32_P_2_LEN_0 */
11412     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11413     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11414   },
11415   {
11416     /* VEX_W_0F3A33_P_2_LEN_0 */
11417     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11418     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11419   },
11420   {
11421     /* VEX_W_0F3A38_P_2 */
11422     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3A39_P_2 */
11426     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F3A40_P_2 */
11430     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F3A41_P_2 */
11434     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3A42_P_2 */
11438     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11439   },
11440   {
11441     /* VEX_W_0F3A46_P_2 */
11442     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3A48_P_2 */
11446     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11447     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A49_P_2 */
11451     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11452     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A4A_P_2 */
11456     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3A4B_P_2 */
11460     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3A4C_P_2 */
11464     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F3A62_P_2 */
11468     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F3A63_P_2 */
11472     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3ACE_P_2 */
11476     { Bad_Opcode },
11477     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11478   },
11479   {
11480     /* VEX_W_0F3ACF_P_2 */
11481     { Bad_Opcode },
11482     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11483   },
11484   {
11485     /* VEX_W_0F3ADF_P_2 */
11486     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11487   },
11488 #define NEED_VEX_W_TABLE
11489 #include "i386-dis-evex.h"
11490 #undef NEED_VEX_W_TABLE
11491 };
11492
11493 static const struct dis386 mod_table[][2] = {
11494   {
11495     /* MOD_8D */
11496     { "leaS",           { Gv, M }, 0 },
11497   },
11498   {
11499     /* MOD_C6_REG_7 */
11500     { Bad_Opcode },
11501     { RM_TABLE (RM_C6_REG_7) },
11502   },
11503   {
11504     /* MOD_C7_REG_7 */
11505     { Bad_Opcode },
11506     { RM_TABLE (RM_C7_REG_7) },
11507   },
11508   {
11509     /* MOD_FF_REG_3 */
11510     { "Jcall^", { indirEp }, 0 },
11511   },
11512   {
11513     /* MOD_FF_REG_5 */
11514     { "Jjmp^", { indirEp }, 0 },
11515   },
11516   {
11517     /* MOD_0F01_REG_0 */
11518     { X86_64_TABLE (X86_64_0F01_REG_0) },
11519     { RM_TABLE (RM_0F01_REG_0) },
11520   },
11521   {
11522     /* MOD_0F01_REG_1 */
11523     { X86_64_TABLE (X86_64_0F01_REG_1) },
11524     { RM_TABLE (RM_0F01_REG_1) },
11525   },
11526   {
11527     /* MOD_0F01_REG_2 */
11528     { X86_64_TABLE (X86_64_0F01_REG_2) },
11529     { RM_TABLE (RM_0F01_REG_2) },
11530   },
11531   {
11532     /* MOD_0F01_REG_3 */
11533     { X86_64_TABLE (X86_64_0F01_REG_3) },
11534     { RM_TABLE (RM_0F01_REG_3) },
11535   },
11536   {
11537     /* MOD_0F01_REG_5 */
11538     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11539     { RM_TABLE (RM_0F01_REG_5) },
11540   },
11541   {
11542     /* MOD_0F01_REG_7 */
11543     { "invlpg",         { Mb }, 0 },
11544     { RM_TABLE (RM_0F01_REG_7) },
11545   },
11546   {
11547     /* MOD_0F12_PREFIX_0 */
11548     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11549     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11550   },
11551   {
11552     /* MOD_0F13 */
11553     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11554   },
11555   {
11556     /* MOD_0F16_PREFIX_0 */
11557     { "movhps",         { XM, EXq }, 0 },
11558     { "movlhps",        { XM, EXq }, 0 },
11559   },
11560   {
11561     /* MOD_0F17 */
11562     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11563   },
11564   {
11565     /* MOD_0F18_REG_0 */
11566     { "prefetchnta",    { Mb }, 0 },
11567   },
11568   {
11569     /* MOD_0F18_REG_1 */
11570     { "prefetcht0",     { Mb }, 0 },
11571   },
11572   {
11573     /* MOD_0F18_REG_2 */
11574     { "prefetcht1",     { Mb }, 0 },
11575   },
11576   {
11577     /* MOD_0F18_REG_3 */
11578     { "prefetcht2",     { Mb }, 0 },
11579   },
11580   {
11581     /* MOD_0F18_REG_4 */
11582     { "nop/reserved",   { Mb }, 0 },
11583   },
11584   {
11585     /* MOD_0F18_REG_5 */
11586     { "nop/reserved",   { Mb }, 0 },
11587   },
11588   {
11589     /* MOD_0F18_REG_6 */
11590     { "nop/reserved",   { Mb }, 0 },
11591   },
11592   {
11593     /* MOD_0F18_REG_7 */
11594     { "nop/reserved",   { Mb }, 0 },
11595   },
11596   {
11597     /* MOD_0F1A_PREFIX_0 */
11598     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11599     { "nopQ",           { Ev }, 0 },
11600   },
11601   {
11602     /* MOD_0F1B_PREFIX_0 */
11603     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11604     { "nopQ",           { Ev }, 0 },
11605   },
11606   {
11607     /* MOD_0F1B_PREFIX_1 */
11608     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11609     { "nopQ",           { Ev }, 0 },
11610   },
11611   {
11612     /* MOD_0F1E_PREFIX_1 */
11613     { "nopQ",           { Ev }, 0 },
11614     { REG_TABLE (REG_0F1E_MOD_3) },
11615   },
11616   {
11617     /* MOD_0F24 */
11618     { Bad_Opcode },
11619     { "movL",           { Rd, Td }, 0 },
11620   },
11621   {
11622     /* MOD_0F26 */
11623     { Bad_Opcode },
11624     { "movL",           { Td, Rd }, 0 },
11625   },
11626   {
11627     /* MOD_0F2B_PREFIX_0 */
11628     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11629   },
11630   {
11631     /* MOD_0F2B_PREFIX_1 */
11632     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11633   },
11634   {
11635     /* MOD_0F2B_PREFIX_2 */
11636     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11637   },
11638   {
11639     /* MOD_0F2B_PREFIX_3 */
11640     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11641   },
11642   {
11643     /* MOD_0F51 */
11644     { Bad_Opcode },
11645     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11646   },
11647   {
11648     /* MOD_0F71_REG_2 */
11649     { Bad_Opcode },
11650     { "psrlw",          { MS, Ib }, 0 },
11651   },
11652   {
11653     /* MOD_0F71_REG_4 */
11654     { Bad_Opcode },
11655     { "psraw",          { MS, Ib }, 0 },
11656   },
11657   {
11658     /* MOD_0F71_REG_6 */
11659     { Bad_Opcode },
11660     { "psllw",          { MS, Ib }, 0 },
11661   },
11662   {
11663     /* MOD_0F72_REG_2 */
11664     { Bad_Opcode },
11665     { "psrld",          { MS, Ib }, 0 },
11666   },
11667   {
11668     /* MOD_0F72_REG_4 */
11669     { Bad_Opcode },
11670     { "psrad",          { MS, Ib }, 0 },
11671   },
11672   {
11673     /* MOD_0F72_REG_6 */
11674     { Bad_Opcode },
11675     { "pslld",          { MS, Ib }, 0 },
11676   },
11677   {
11678     /* MOD_0F73_REG_2 */
11679     { Bad_Opcode },
11680     { "psrlq",          { MS, Ib }, 0 },
11681   },
11682   {
11683     /* MOD_0F73_REG_3 */
11684     { Bad_Opcode },
11685     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11686   },
11687   {
11688     /* MOD_0F73_REG_6 */
11689     { Bad_Opcode },
11690     { "psllq",          { MS, Ib }, 0 },
11691   },
11692   {
11693     /* MOD_0F73_REG_7 */
11694     { Bad_Opcode },
11695     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11696   },
11697   {
11698     /* MOD_0FAE_REG_0 */
11699     { "fxsave",         { FXSAVE }, 0 },
11700     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11701   },
11702   {
11703     /* MOD_0FAE_REG_1 */
11704     { "fxrstor",        { FXSAVE }, 0 },
11705     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11706   },
11707   {
11708     /* MOD_0FAE_REG_2 */
11709     { "ldmxcsr",        { Md }, 0 },
11710     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11711   },
11712   {
11713     /* MOD_0FAE_REG_3 */
11714     { "stmxcsr",        { Md }, 0 },
11715     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11716   },
11717   {
11718     /* MOD_0FAE_REG_4 */
11719     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11720     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11721   },
11722   {
11723     /* MOD_0FAE_REG_5 */
11724     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11725     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11726   },
11727   {
11728     /* MOD_0FAE_REG_6 */
11729     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11730     { RM_TABLE (RM_0FAE_REG_6) },
11731   },
11732   {
11733     /* MOD_0FAE_REG_7 */
11734     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11735     { RM_TABLE (RM_0FAE_REG_7) },
11736   },
11737   {
11738     /* MOD_0FB2 */
11739     { "lssS",           { Gv, Mp }, 0 },
11740   },
11741   {
11742     /* MOD_0FB4 */
11743     { "lfsS",           { Gv, Mp }, 0 },
11744   },
11745   {
11746     /* MOD_0FB5 */
11747     { "lgsS",           { Gv, Mp }, 0 },
11748   },
11749   {
11750     /* MOD_0FC3 */
11751     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11752   },
11753   {
11754     /* MOD_0FC7_REG_3 */
11755     { "xrstors",        { FXSAVE }, 0 },
11756   },
11757   {
11758     /* MOD_0FC7_REG_4 */
11759     { "xsavec",         { FXSAVE }, 0 },
11760   },
11761   {
11762     /* MOD_0FC7_REG_5 */
11763     { "xsaves",         { FXSAVE }, 0 },
11764   },
11765   {
11766     /* MOD_0FC7_REG_6 */
11767     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11768     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11769   },
11770   {
11771     /* MOD_0FC7_REG_7 */
11772     { "vmptrst",        { Mq }, 0 },
11773     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11774   },
11775   {
11776     /* MOD_0FD7 */
11777     { Bad_Opcode },
11778     { "pmovmskb",       { Gdq, MS }, 0 },
11779   },
11780   {
11781     /* MOD_0FE7_PREFIX_2 */
11782     { "movntdq",        { Mx, XM }, 0 },
11783   },
11784   {
11785     /* MOD_0FF0_PREFIX_3 */
11786     { "lddqu",          { XM, M }, 0 },
11787   },
11788   {
11789     /* MOD_0F382A_PREFIX_2 */
11790     { "movntdqa",       { XM, Mx }, 0 },
11791   },
11792   {
11793     /* MOD_0F38F5_PREFIX_2 */
11794     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11795   },
11796   {
11797     /* MOD_0F38F6_PREFIX_0 */
11798     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11799   },
11800   {
11801     /* MOD_62_32BIT */
11802     { "bound{S|}",      { Gv, Ma }, 0 },
11803     { EVEX_TABLE (EVEX_0F) },
11804   },
11805   {
11806     /* MOD_C4_32BIT */
11807     { "lesS",           { Gv, Mp }, 0 },
11808     { VEX_C4_TABLE (VEX_0F) },
11809   },
11810   {
11811     /* MOD_C5_32BIT */
11812     { "ldsS",           { Gv, Mp }, 0 },
11813     { VEX_C5_TABLE (VEX_0F) },
11814   },
11815   {
11816     /* MOD_VEX_0F12_PREFIX_0 */
11817     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11818     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11819   },
11820   {
11821     /* MOD_VEX_0F13 */
11822     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11823   },
11824   {
11825     /* MOD_VEX_0F16_PREFIX_0 */
11826     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11827     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11828   },
11829   {
11830     /* MOD_VEX_0F17 */
11831     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11832   },
11833   {
11834     /* MOD_VEX_0F2B */
11835     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11836   },
11837   {
11838     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11839     { Bad_Opcode },
11840     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11844     { Bad_Opcode },
11845     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11849     { Bad_Opcode },
11850     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11854     { Bad_Opcode },
11855     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11859     { Bad_Opcode },
11860     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11864     { Bad_Opcode },
11865     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11869     { Bad_Opcode },
11870     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11874     { Bad_Opcode },
11875     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11879     { Bad_Opcode },
11880     { "knotw",          { MaskG, MaskR }, 0 },
11881   },
11882   {
11883     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11884     { Bad_Opcode },
11885     { "knotq",          { MaskG, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11889     { Bad_Opcode },
11890     { "knotb",          { MaskG, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11894     { Bad_Opcode },
11895     { "knotd",          { MaskG, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11899     { Bad_Opcode },
11900     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11904     { Bad_Opcode },
11905     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907   {
11908     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11909     { Bad_Opcode },
11910     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11914     { Bad_Opcode },
11915     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917  {
11918     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11919     { Bad_Opcode },
11920     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11924     { Bad_Opcode },
11925     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11929     { Bad_Opcode },
11930     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11934     { Bad_Opcode },
11935     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11939     { Bad_Opcode },
11940     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11944     { Bad_Opcode },
11945     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11949     { Bad_Opcode },
11950     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11954     { Bad_Opcode },
11955     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11959     { Bad_Opcode },
11960     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11961   },
11962   {
11963     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11964     { Bad_Opcode },
11965     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11966   },
11967   {
11968     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11969     { Bad_Opcode },
11970     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11971   },
11972   {
11973     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11974     { Bad_Opcode },
11975     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11976   },
11977   {
11978     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11979     { Bad_Opcode },
11980     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11981   },
11982   {
11983     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11984     { Bad_Opcode },
11985     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11986   },
11987   {
11988     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11989     { Bad_Opcode },
11990     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11991   },
11992   {
11993     /* MOD_VEX_0F50 */
11994     { Bad_Opcode },
11995     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11996   },
11997   {
11998     /* MOD_VEX_0F71_REG_2 */
11999     { Bad_Opcode },
12000     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12001   },
12002   {
12003     /* MOD_VEX_0F71_REG_4 */
12004     { Bad_Opcode },
12005     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12006   },
12007   {
12008     /* MOD_VEX_0F71_REG_6 */
12009     { Bad_Opcode },
12010     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12011   },
12012   {
12013     /* MOD_VEX_0F72_REG_2 */
12014     { Bad_Opcode },
12015     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12016   },
12017   {
12018     /* MOD_VEX_0F72_REG_4 */
12019     { Bad_Opcode },
12020     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12021   },
12022   {
12023     /* MOD_VEX_0F72_REG_6 */
12024     { Bad_Opcode },
12025     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12026   },
12027   {
12028     /* MOD_VEX_0F73_REG_2 */
12029     { Bad_Opcode },
12030     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12031   },
12032   {
12033     /* MOD_VEX_0F73_REG_3 */
12034     { Bad_Opcode },
12035     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12036   },
12037   {
12038     /* MOD_VEX_0F73_REG_6 */
12039     { Bad_Opcode },
12040     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12041   },
12042   {
12043     /* MOD_VEX_0F73_REG_7 */
12044     { Bad_Opcode },
12045     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12049     { "kmovw",          { Ew, MaskG }, 0 },
12050     { Bad_Opcode },
12051   },
12052   {
12053     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12054     { "kmovq",          { Eq, MaskG }, 0 },
12055     { Bad_Opcode },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12059     { "kmovb",          { Eb, MaskG }, 0 },
12060     { Bad_Opcode },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12064     { "kmovd",          { Ed, MaskG }, 0 },
12065     { Bad_Opcode },
12066   },
12067   {
12068     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12069     { Bad_Opcode },
12070     { "kmovw",          { MaskG, Rdq }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12074     { Bad_Opcode },
12075     { "kmovb",          { MaskG, Rdq }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12079     { Bad_Opcode },
12080     { "kmovd",          { MaskG, Rdq }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12084     { Bad_Opcode },
12085     { "kmovq",          { MaskG, Rdq }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12089     { Bad_Opcode },
12090     { "kmovw",          { Gdq, MaskR }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12094     { Bad_Opcode },
12095     { "kmovb",          { Gdq, MaskR }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12099     { Bad_Opcode },
12100     { "kmovd",          { Gdq, MaskR }, 0 },
12101   },
12102   {
12103     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12104     { Bad_Opcode },
12105     { "kmovq",          { Gdq, MaskR }, 0 },
12106   },
12107   {
12108     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12109     { Bad_Opcode },
12110     { "kortestw", { MaskG, MaskR }, 0 },
12111   },
12112   {
12113     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12114     { Bad_Opcode },
12115     { "kortestq", { MaskG, MaskR }, 0 },
12116   },
12117   {
12118     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12119     { Bad_Opcode },
12120     { "kortestb", { MaskG, MaskR }, 0 },
12121   },
12122   {
12123     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12124     { Bad_Opcode },
12125     { "kortestd", { MaskG, MaskR }, 0 },
12126   },
12127   {
12128     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12129     { Bad_Opcode },
12130     { "ktestw", { MaskG, MaskR }, 0 },
12131   },
12132   {
12133     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12134     { Bad_Opcode },
12135     { "ktestq", { MaskG, MaskR }, 0 },
12136   },
12137   {
12138     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12139     { Bad_Opcode },
12140     { "ktestb", { MaskG, MaskR }, 0 },
12141   },
12142   {
12143     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12144     { Bad_Opcode },
12145     { "ktestd", { MaskG, MaskR }, 0 },
12146   },
12147   {
12148     /* MOD_VEX_0FAE_REG_2 */
12149     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12150   },
12151   {
12152     /* MOD_VEX_0FAE_REG_3 */
12153     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12154   },
12155   {
12156     /* MOD_VEX_0FD7_PREFIX_2 */
12157     { Bad_Opcode },
12158     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12159   },
12160   {
12161     /* MOD_VEX_0FE7_PREFIX_2 */
12162     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12163   },
12164   {
12165     /* MOD_VEX_0FF0_PREFIX_3 */
12166     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12167   },
12168   {
12169     /* MOD_VEX_0F381A_PREFIX_2 */
12170     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12171   },
12172   {
12173     /* MOD_VEX_0F382A_PREFIX_2 */
12174     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12175   },
12176   {
12177     /* MOD_VEX_0F382C_PREFIX_2 */
12178     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12179   },
12180   {
12181     /* MOD_VEX_0F382D_PREFIX_2 */
12182     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12183   },
12184   {
12185     /* MOD_VEX_0F382E_PREFIX_2 */
12186     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12187   },
12188   {
12189     /* MOD_VEX_0F382F_PREFIX_2 */
12190     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12191   },
12192   {
12193     /* MOD_VEX_0F385A_PREFIX_2 */
12194     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12195   },
12196   {
12197     /* MOD_VEX_0F388C_PREFIX_2 */
12198     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12199   },
12200   {
12201     /* MOD_VEX_0F388E_PREFIX_2 */
12202     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12208   },
12209   {
12210     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12211     { Bad_Opcode },
12212     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12213   },
12214   {
12215     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12216     { Bad_Opcode },
12217     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12218   },
12219   {
12220     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12221     { Bad_Opcode },
12222     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12223   },
12224   {
12225     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12226     { Bad_Opcode },
12227     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12228   },
12229   {
12230     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12231     { Bad_Opcode },
12232     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12233   },
12234   {
12235     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12236     { Bad_Opcode },
12237     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12238   },
12239   {
12240     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12241     { Bad_Opcode },
12242     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12243   },
12244 #define NEED_MOD_TABLE
12245 #include "i386-dis-evex.h"
12246 #undef NEED_MOD_TABLE
12247 };
12248
12249 static const struct dis386 rm_table[][8] = {
12250   {
12251     /* RM_C6_REG_7 */
12252     { "xabort",         { Skip_MODRM, Ib }, 0 },
12253   },
12254   {
12255     /* RM_C7_REG_7 */
12256     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12257   },
12258   {
12259     /* RM_0F01_REG_0 */
12260     { Bad_Opcode },
12261     { "vmcall",         { Skip_MODRM }, 0 },
12262     { "vmlaunch",       { Skip_MODRM }, 0 },
12263     { "vmresume",       { Skip_MODRM }, 0 },
12264     { "vmxoff",         { Skip_MODRM }, 0 },
12265     { "pconfig",        { Skip_MODRM }, 0 },
12266   },
12267   {
12268     /* RM_0F01_REG_1 */
12269     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12270     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12271     { "clac",           { Skip_MODRM }, 0 },
12272     { "stac",           { Skip_MODRM }, 0 },
12273     { Bad_Opcode },
12274     { Bad_Opcode },
12275     { Bad_Opcode },
12276     { "encls",          { Skip_MODRM }, 0 },
12277   },
12278   {
12279     /* RM_0F01_REG_2 */
12280     { "xgetbv",         { Skip_MODRM }, 0 },
12281     { "xsetbv",         { Skip_MODRM }, 0 },
12282     { Bad_Opcode },
12283     { Bad_Opcode },
12284     { "vmfunc",         { Skip_MODRM }, 0 },
12285     { "xend",           { Skip_MODRM }, 0 },
12286     { "xtest",          { Skip_MODRM }, 0 },
12287     { "enclu",          { Skip_MODRM }, 0 },
12288   },
12289   {
12290     /* RM_0F01_REG_3 */
12291     { "vmrun",          { Skip_MODRM }, 0 },
12292     { "vmmcall",        { Skip_MODRM }, 0 },
12293     { "vmload",         { Skip_MODRM }, 0 },
12294     { "vmsave",         { Skip_MODRM }, 0 },
12295     { "stgi",           { Skip_MODRM }, 0 },
12296     { "clgi",           { Skip_MODRM }, 0 },
12297     { "skinit",         { Skip_MODRM }, 0 },
12298     { "invlpga",        { Skip_MODRM }, 0 },
12299   },
12300   {
12301     /* RM_0F01_REG_5 */
12302     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12303     { Bad_Opcode },
12304     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12305     { Bad_Opcode },
12306     { Bad_Opcode },
12307     { Bad_Opcode },
12308     { "rdpkru",         { Skip_MODRM }, 0 },
12309     { "wrpkru",         { Skip_MODRM }, 0 },
12310   },
12311   {
12312     /* RM_0F01_REG_7 */
12313     { "swapgs",         { Skip_MODRM }, 0  },
12314     { "rdtscp",         { Skip_MODRM }, 0  },
12315     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12316     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12317     { "clzero",         { Skip_MODRM }, 0  },
12318   },
12319   {
12320     /* RM_0F1E_MOD_3_REG_7 */
12321     { "nopQ",           { Ev }, 0 },
12322     { "nopQ",           { Ev }, 0 },
12323     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12324     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12325     { "nopQ",           { Ev }, 0 },
12326     { "nopQ",           { Ev }, 0 },
12327     { "nopQ",           { Ev }, 0 },
12328     { "nopQ",           { Ev }, 0 },
12329   },
12330   {
12331     /* RM_0FAE_REG_6 */
12332     { "mfence",         { Skip_MODRM }, 0 },
12333   },
12334   {
12335     /* RM_0FAE_REG_7 */
12336     { "sfence",         { Skip_MODRM }, 0 },
12337
12338   },
12339 };
12340
12341 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12342
12343 /* We use the high bit to indicate different name for the same
12344    prefix.  */
12345 #define REP_PREFIX      (0xf3 | 0x100)
12346 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12347 #define XRELEASE_PREFIX (0xf3 | 0x400)
12348 #define BND_PREFIX      (0xf2 | 0x400)
12349 #define NOTRACK_PREFIX  (0x3e | 0x100)
12350
12351 static int
12352 ckprefix (void)
12353 {
12354   int newrex, i, length;
12355   rex = 0;
12356   rex_ignored = 0;
12357   prefixes = 0;
12358   used_prefixes = 0;
12359   rex_used = 0;
12360   last_lock_prefix = -1;
12361   last_repz_prefix = -1;
12362   last_repnz_prefix = -1;
12363   last_data_prefix = -1;
12364   last_addr_prefix = -1;
12365   last_rex_prefix = -1;
12366   last_seg_prefix = -1;
12367   fwait_prefix = -1;
12368   active_seg_prefix = 0;
12369   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12370     all_prefixes[i] = 0;
12371   i = 0;
12372   length = 0;
12373   /* The maximum instruction length is 15bytes.  */
12374   while (length < MAX_CODE_LENGTH - 1)
12375     {
12376       FETCH_DATA (the_info, codep + 1);
12377       newrex = 0;
12378       switch (*codep)
12379         {
12380         /* REX prefixes family.  */
12381         case 0x40:
12382         case 0x41:
12383         case 0x42:
12384         case 0x43:
12385         case 0x44:
12386         case 0x45:
12387         case 0x46:
12388         case 0x47:
12389         case 0x48:
12390         case 0x49:
12391         case 0x4a:
12392         case 0x4b:
12393         case 0x4c:
12394         case 0x4d:
12395         case 0x4e:
12396         case 0x4f:
12397           if (address_mode == mode_64bit)
12398             newrex = *codep;
12399           else
12400             return 1;
12401           last_rex_prefix = i;
12402           break;
12403         case 0xf3:
12404           prefixes |= PREFIX_REPZ;
12405           last_repz_prefix = i;
12406           break;
12407         case 0xf2:
12408           prefixes |= PREFIX_REPNZ;
12409           last_repnz_prefix = i;
12410           break;
12411         case 0xf0:
12412           prefixes |= PREFIX_LOCK;
12413           last_lock_prefix = i;
12414           break;
12415         case 0x2e:
12416           prefixes |= PREFIX_CS;
12417           last_seg_prefix = i;
12418           active_seg_prefix = PREFIX_CS;
12419           break;
12420         case 0x36:
12421           prefixes |= PREFIX_SS;
12422           last_seg_prefix = i;
12423           active_seg_prefix = PREFIX_SS;
12424           break;
12425         case 0x3e:
12426           prefixes |= PREFIX_DS;
12427           last_seg_prefix = i;
12428           active_seg_prefix = PREFIX_DS;
12429           break;
12430         case 0x26:
12431           prefixes |= PREFIX_ES;
12432           last_seg_prefix = i;
12433           active_seg_prefix = PREFIX_ES;
12434           break;
12435         case 0x64:
12436           prefixes |= PREFIX_FS;
12437           last_seg_prefix = i;
12438           active_seg_prefix = PREFIX_FS;
12439           break;
12440         case 0x65:
12441           prefixes |= PREFIX_GS;
12442           last_seg_prefix = i;
12443           active_seg_prefix = PREFIX_GS;
12444           break;
12445         case 0x66:
12446           prefixes |= PREFIX_DATA;
12447           last_data_prefix = i;
12448           break;
12449         case 0x67:
12450           prefixes |= PREFIX_ADDR;
12451           last_addr_prefix = i;
12452           break;
12453         case FWAIT_OPCODE:
12454           /* fwait is really an instruction.  If there are prefixes
12455              before the fwait, they belong to the fwait, *not* to the
12456              following instruction.  */
12457           fwait_prefix = i;
12458           if (prefixes || rex)
12459             {
12460               prefixes |= PREFIX_FWAIT;
12461               codep++;
12462               /* This ensures that the previous REX prefixes are noticed
12463                  as unused prefixes, as in the return case below.  */
12464               rex_used = rex;
12465               return 1;
12466             }
12467           prefixes = PREFIX_FWAIT;
12468           break;
12469         default:
12470           return 1;
12471         }
12472       /* Rex is ignored when followed by another prefix.  */
12473       if (rex)
12474         {
12475           rex_used = rex;
12476           return 1;
12477         }
12478       if (*codep != FWAIT_OPCODE)
12479         all_prefixes[i++] = *codep;
12480       rex = newrex;
12481       codep++;
12482       length++;
12483     }
12484   return 0;
12485 }
12486
12487 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12488    prefix byte.  */
12489
12490 static const char *
12491 prefix_name (int pref, int sizeflag)
12492 {
12493   static const char *rexes [16] =
12494     {
12495       "rex",            /* 0x40 */
12496       "rex.B",          /* 0x41 */
12497       "rex.X",          /* 0x42 */
12498       "rex.XB",         /* 0x43 */
12499       "rex.R",          /* 0x44 */
12500       "rex.RB",         /* 0x45 */
12501       "rex.RX",         /* 0x46 */
12502       "rex.RXB",        /* 0x47 */
12503       "rex.W",          /* 0x48 */
12504       "rex.WB",         /* 0x49 */
12505       "rex.WX",         /* 0x4a */
12506       "rex.WXB",        /* 0x4b */
12507       "rex.WR",         /* 0x4c */
12508       "rex.WRB",        /* 0x4d */
12509       "rex.WRX",        /* 0x4e */
12510       "rex.WRXB",       /* 0x4f */
12511     };
12512
12513   switch (pref)
12514     {
12515     /* REX prefixes family.  */
12516     case 0x40:
12517     case 0x41:
12518     case 0x42:
12519     case 0x43:
12520     case 0x44:
12521     case 0x45:
12522     case 0x46:
12523     case 0x47:
12524     case 0x48:
12525     case 0x49:
12526     case 0x4a:
12527     case 0x4b:
12528     case 0x4c:
12529     case 0x4d:
12530     case 0x4e:
12531     case 0x4f:
12532       return rexes [pref - 0x40];
12533     case 0xf3:
12534       return "repz";
12535     case 0xf2:
12536       return "repnz";
12537     case 0xf0:
12538       return "lock";
12539     case 0x2e:
12540       return "cs";
12541     case 0x36:
12542       return "ss";
12543     case 0x3e:
12544       return "ds";
12545     case 0x26:
12546       return "es";
12547     case 0x64:
12548       return "fs";
12549     case 0x65:
12550       return "gs";
12551     case 0x66:
12552       return (sizeflag & DFLAG) ? "data16" : "data32";
12553     case 0x67:
12554       if (address_mode == mode_64bit)
12555         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12556       else
12557         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12558     case FWAIT_OPCODE:
12559       return "fwait";
12560     case REP_PREFIX:
12561       return "rep";
12562     case XACQUIRE_PREFIX:
12563       return "xacquire";
12564     case XRELEASE_PREFIX:
12565       return "xrelease";
12566     case BND_PREFIX:
12567       return "bnd";
12568     case NOTRACK_PREFIX:
12569       return "notrack";
12570     default:
12571       return NULL;
12572     }
12573 }
12574
12575 static char op_out[MAX_OPERANDS][100];
12576 static int op_ad, op_index[MAX_OPERANDS];
12577 static int two_source_ops;
12578 static bfd_vma op_address[MAX_OPERANDS];
12579 static bfd_vma op_riprel[MAX_OPERANDS];
12580 static bfd_vma start_pc;
12581
12582 /*
12583  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12584  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12585  *   section of the "Virtual 8086 Mode" chapter.)
12586  * 'pc' should be the address of this instruction, it will
12587  *   be used to print the target address if this is a relative jump or call
12588  * The function returns the length of this instruction in bytes.
12589  */
12590
12591 static char intel_syntax;
12592 static char intel_mnemonic = !SYSV386_COMPAT;
12593 static char open_char;
12594 static char close_char;
12595 static char separator_char;
12596 static char scale_char;
12597
12598 enum x86_64_isa
12599 {
12600   amd64 = 0,
12601   intel64
12602 };
12603
12604 static enum x86_64_isa isa64;
12605
12606 /* Here for backwards compatibility.  When gdb stops using
12607    print_insn_i386_att and print_insn_i386_intel these functions can
12608    disappear, and print_insn_i386 be merged into print_insn.  */
12609 int
12610 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12611 {
12612   intel_syntax = 0;
12613
12614   return print_insn (pc, info);
12615 }
12616
12617 int
12618 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12619 {
12620   intel_syntax = 1;
12621
12622   return print_insn (pc, info);
12623 }
12624
12625 int
12626 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12627 {
12628   intel_syntax = -1;
12629
12630   return print_insn (pc, info);
12631 }
12632
12633 void
12634 print_i386_disassembler_options (FILE *stream)
12635 {
12636   fprintf (stream, _("\n\
12637 The following i386/x86-64 specific disassembler options are supported for use\n\
12638 with the -M switch (multiple options should be separated by commas):\n"));
12639
12640   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12641   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12642   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12643   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12644   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12645   fprintf (stream, _("  att-mnemonic\n"
12646                      "              Display instruction in AT&T mnemonic\n"));
12647   fprintf (stream, _("  intel-mnemonic\n"
12648                      "              Display instruction in Intel mnemonic\n"));
12649   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12650   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12651   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12652   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12653   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12654   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12655   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12656   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12657 }
12658
12659 /* Bad opcode.  */
12660 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12661
12662 /* Get a pointer to struct dis386 with a valid name.  */
12663
12664 static const struct dis386 *
12665 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12666 {
12667   int vindex, vex_table_index;
12668
12669   if (dp->name != NULL)
12670     return dp;
12671
12672   switch (dp->op[0].bytemode)
12673     {
12674     case USE_REG_TABLE:
12675       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12676       break;
12677
12678     case USE_MOD_TABLE:
12679       vindex = modrm.mod == 0x3 ? 1 : 0;
12680       dp = &mod_table[dp->op[1].bytemode][vindex];
12681       break;
12682
12683     case USE_RM_TABLE:
12684       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12685       break;
12686
12687     case USE_PREFIX_TABLE:
12688       if (need_vex)
12689         {
12690           /* The prefix in VEX is implicit.  */
12691           switch (vex.prefix)
12692             {
12693             case 0:
12694               vindex = 0;
12695               break;
12696             case REPE_PREFIX_OPCODE:
12697               vindex = 1;
12698               break;
12699             case DATA_PREFIX_OPCODE:
12700               vindex = 2;
12701               break;
12702             case REPNE_PREFIX_OPCODE:
12703               vindex = 3;
12704               break;
12705             default:
12706               abort ();
12707               break;
12708             }
12709         }
12710       else
12711         {
12712           int last_prefix = -1;
12713           int prefix = 0;
12714           vindex = 0;
12715           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12716              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12717              last one wins.  */
12718           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12719             {
12720               if (last_repz_prefix > last_repnz_prefix)
12721                 {
12722                   vindex = 1;
12723                   prefix = PREFIX_REPZ;
12724                   last_prefix = last_repz_prefix;
12725                 }
12726               else
12727                 {
12728                   vindex = 3;
12729                   prefix = PREFIX_REPNZ;
12730                   last_prefix = last_repnz_prefix;
12731                 }
12732
12733               /* Check if prefix should be ignored.  */
12734               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12735                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12736                    & prefix) != 0)
12737                 vindex = 0;
12738             }
12739
12740           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12741             {
12742               vindex = 2;
12743               prefix = PREFIX_DATA;
12744               last_prefix = last_data_prefix;
12745             }
12746
12747           if (vindex != 0)
12748             {
12749               used_prefixes |= prefix;
12750               all_prefixes[last_prefix] = 0;
12751             }
12752         }
12753       dp = &prefix_table[dp->op[1].bytemode][vindex];
12754       break;
12755
12756     case USE_X86_64_TABLE:
12757       vindex = address_mode == mode_64bit ? 1 : 0;
12758       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12759       break;
12760
12761     case USE_3BYTE_TABLE:
12762       FETCH_DATA (info, codep + 2);
12763       vindex = *codep++;
12764       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12765       end_codep = codep;
12766       modrm.mod = (*codep >> 6) & 3;
12767       modrm.reg = (*codep >> 3) & 7;
12768       modrm.rm = *codep & 7;
12769       break;
12770
12771     case USE_VEX_LEN_TABLE:
12772       if (!need_vex)
12773         abort ();
12774
12775       switch (vex.length)
12776         {
12777         case 128:
12778           vindex = 0;
12779           break;
12780         case 256:
12781           vindex = 1;
12782           break;
12783         default:
12784           abort ();
12785           break;
12786         }
12787
12788       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12789       break;
12790
12791     case USE_XOP_8F_TABLE:
12792       FETCH_DATA (info, codep + 3);
12793       /* All bits in the REX prefix are ignored.  */
12794       rex_ignored = rex;
12795       rex = ~(*codep >> 5) & 0x7;
12796
12797       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12798       switch ((*codep & 0x1f))
12799         {
12800         default:
12801           dp = &bad_opcode;
12802           return dp;
12803         case 0x8:
12804           vex_table_index = XOP_08;
12805           break;
12806         case 0x9:
12807           vex_table_index = XOP_09;
12808           break;
12809         case 0xa:
12810           vex_table_index = XOP_0A;
12811           break;
12812         }
12813       codep++;
12814       vex.w = *codep & 0x80;
12815       if (vex.w && address_mode == mode_64bit)
12816         rex |= REX_W;
12817
12818       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12819       if (address_mode != mode_64bit)
12820         {
12821           /* In 16/32-bit mode REX_B is silently ignored.  */
12822           rex &= ~REX_B;
12823         }
12824
12825       vex.length = (*codep & 0x4) ? 256 : 128;
12826       switch ((*codep & 0x3))
12827         {
12828         case 0:
12829           break;
12830         case 1:
12831           vex.prefix = DATA_PREFIX_OPCODE;
12832           break;
12833         case 2:
12834           vex.prefix = REPE_PREFIX_OPCODE;
12835           break;
12836         case 3:
12837           vex.prefix = REPNE_PREFIX_OPCODE;
12838           break;
12839         }
12840       need_vex = 1;
12841       need_vex_reg = 1;
12842       codep++;
12843       vindex = *codep++;
12844       dp = &xop_table[vex_table_index][vindex];
12845
12846       end_codep = codep;
12847       FETCH_DATA (info, codep + 1);
12848       modrm.mod = (*codep >> 6) & 3;
12849       modrm.reg = (*codep >> 3) & 7;
12850       modrm.rm = *codep & 7;
12851       break;
12852
12853     case USE_VEX_C4_TABLE:
12854       /* VEX prefix.  */
12855       FETCH_DATA (info, codep + 3);
12856       /* All bits in the REX prefix are ignored.  */
12857       rex_ignored = rex;
12858       rex = ~(*codep >> 5) & 0x7;
12859       switch ((*codep & 0x1f))
12860         {
12861         default:
12862           dp = &bad_opcode;
12863           return dp;
12864         case 0x1:
12865           vex_table_index = VEX_0F;
12866           break;
12867         case 0x2:
12868           vex_table_index = VEX_0F38;
12869           break;
12870         case 0x3:
12871           vex_table_index = VEX_0F3A;
12872           break;
12873         }
12874       codep++;
12875       vex.w = *codep & 0x80;
12876       if (address_mode == mode_64bit)
12877         {
12878           if (vex.w)
12879             rex |= REX_W;
12880         }
12881       else
12882         {
12883           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12884              is ignored, other REX bits are 0 and the highest bit in
12885              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12886           rex = 0;
12887         }
12888       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12889       vex.length = (*codep & 0x4) ? 256 : 128;
12890       switch ((*codep & 0x3))
12891         {
12892         case 0:
12893           break;
12894         case 1:
12895           vex.prefix = DATA_PREFIX_OPCODE;
12896           break;
12897         case 2:
12898           vex.prefix = REPE_PREFIX_OPCODE;
12899           break;
12900         case 3:
12901           vex.prefix = REPNE_PREFIX_OPCODE;
12902           break;
12903         }
12904       need_vex = 1;
12905       need_vex_reg = 1;
12906       codep++;
12907       vindex = *codep++;
12908       dp = &vex_table[vex_table_index][vindex];
12909       end_codep = codep;
12910       /* There is no MODRM byte for VEX0F 77.  */
12911       if (vex_table_index != VEX_0F || vindex != 0x77)
12912         {
12913           FETCH_DATA (info, codep + 1);
12914           modrm.mod = (*codep >> 6) & 3;
12915           modrm.reg = (*codep >> 3) & 7;
12916           modrm.rm = *codep & 7;
12917         }
12918       break;
12919
12920     case USE_VEX_C5_TABLE:
12921       /* VEX prefix.  */
12922       FETCH_DATA (info, codep + 2);
12923       /* All bits in the REX prefix are ignored.  */
12924       rex_ignored = rex;
12925       rex = (*codep & 0x80) ? 0 : REX_R;
12926
12927       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12928          VEX.vvvv is 1.  */
12929       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12930       vex.length = (*codep & 0x4) ? 256 : 128;
12931       switch ((*codep & 0x3))
12932         {
12933         case 0:
12934           break;
12935         case 1:
12936           vex.prefix = DATA_PREFIX_OPCODE;
12937           break;
12938         case 2:
12939           vex.prefix = REPE_PREFIX_OPCODE;
12940           break;
12941         case 3:
12942           vex.prefix = REPNE_PREFIX_OPCODE;
12943           break;
12944         }
12945       need_vex = 1;
12946       need_vex_reg = 1;
12947       codep++;
12948       vindex = *codep++;
12949       dp = &vex_table[dp->op[1].bytemode][vindex];
12950       end_codep = codep;
12951       /* There is no MODRM byte for VEX 77.  */
12952       if (vindex != 0x77)
12953         {
12954           FETCH_DATA (info, codep + 1);
12955           modrm.mod = (*codep >> 6) & 3;
12956           modrm.reg = (*codep >> 3) & 7;
12957           modrm.rm = *codep & 7;
12958         }
12959       break;
12960
12961     case USE_VEX_W_TABLE:
12962       if (!need_vex)
12963         abort ();
12964
12965       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12966       break;
12967
12968     case USE_EVEX_TABLE:
12969       two_source_ops = 0;
12970       /* EVEX prefix.  */
12971       vex.evex = 1;
12972       FETCH_DATA (info, codep + 4);
12973       /* All bits in the REX prefix are ignored.  */
12974       rex_ignored = rex;
12975       /* The first byte after 0x62.  */
12976       rex = ~(*codep >> 5) & 0x7;
12977       vex.r = *codep & 0x10;
12978       switch ((*codep & 0xf))
12979         {
12980         default:
12981           return &bad_opcode;
12982         case 0x1:
12983           vex_table_index = EVEX_0F;
12984           break;
12985         case 0x2:
12986           vex_table_index = EVEX_0F38;
12987           break;
12988         case 0x3:
12989           vex_table_index = EVEX_0F3A;
12990           break;
12991         }
12992
12993       /* The second byte after 0x62.  */
12994       codep++;
12995       vex.w = *codep & 0x80;
12996       if (vex.w && address_mode == mode_64bit)
12997         rex |= REX_W;
12998
12999       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13000
13001       /* The U bit.  */
13002       if (!(*codep & 0x4))
13003         return &bad_opcode;
13004
13005       switch ((*codep & 0x3))
13006         {
13007         case 0:
13008           break;
13009         case 1:
13010           vex.prefix = DATA_PREFIX_OPCODE;
13011           break;
13012         case 2:
13013           vex.prefix = REPE_PREFIX_OPCODE;
13014           break;
13015         case 3:
13016           vex.prefix = REPNE_PREFIX_OPCODE;
13017           break;
13018         }
13019
13020       /* The third byte after 0x62.  */
13021       codep++;
13022
13023       /* Remember the static rounding bits.  */
13024       vex.ll = (*codep >> 5) & 3;
13025       vex.b = (*codep & 0x10) != 0;
13026
13027       vex.v = *codep & 0x8;
13028       vex.mask_register_specifier = *codep & 0x7;
13029       vex.zeroing = *codep & 0x80;
13030
13031       if (address_mode != mode_64bit)
13032         {
13033           /* In 16/32-bit mode silently ignore following bits.  */
13034           rex &= ~REX_B;
13035           vex.r = 1;
13036           vex.v = 1;
13037         }
13038
13039       need_vex = 1;
13040       need_vex_reg = 1;
13041       codep++;
13042       vindex = *codep++;
13043       dp = &evex_table[vex_table_index][vindex];
13044       end_codep = codep;
13045       FETCH_DATA (info, codep + 1);
13046       modrm.mod = (*codep >> 6) & 3;
13047       modrm.reg = (*codep >> 3) & 7;
13048       modrm.rm = *codep & 7;
13049
13050       /* Set vector length.  */
13051       if (modrm.mod == 3 && vex.b)
13052         vex.length = 512;
13053       else
13054         {
13055           switch (vex.ll)
13056             {
13057             case 0x0:
13058               vex.length = 128;
13059               break;
13060             case 0x1:
13061               vex.length = 256;
13062               break;
13063             case 0x2:
13064               vex.length = 512;
13065               break;
13066             default:
13067               return &bad_opcode;
13068             }
13069         }
13070       break;
13071
13072     case 0:
13073       dp = &bad_opcode;
13074       break;
13075
13076     default:
13077       abort ();
13078     }
13079
13080   if (dp->name != NULL)
13081     return dp;
13082   else
13083     return get_valid_dis386 (dp, info);
13084 }
13085
13086 static void
13087 get_sib (disassemble_info *info, int sizeflag)
13088 {
13089   /* If modrm.mod == 3, operand must be register.  */
13090   if (need_modrm
13091       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13092       && modrm.mod != 3
13093       && modrm.rm == 4)
13094     {
13095       FETCH_DATA (info, codep + 2);
13096       sib.index = (codep [1] >> 3) & 7;
13097       sib.scale = (codep [1] >> 6) & 3;
13098       sib.base = codep [1] & 7;
13099     }
13100 }
13101
13102 static int
13103 print_insn (bfd_vma pc, disassemble_info *info)
13104 {
13105   const struct dis386 *dp;
13106   int i;
13107   char *op_txt[MAX_OPERANDS];
13108   int needcomma;
13109   int sizeflag, orig_sizeflag;
13110   const char *p;
13111   struct dis_private priv;
13112   int prefix_length;
13113
13114   priv.orig_sizeflag = AFLAG | DFLAG;
13115   if ((info->mach & bfd_mach_i386_i386) != 0)
13116     address_mode = mode_32bit;
13117   else if (info->mach == bfd_mach_i386_i8086)
13118     {
13119       address_mode = mode_16bit;
13120       priv.orig_sizeflag = 0;
13121     }
13122   else
13123     address_mode = mode_64bit;
13124
13125   if (intel_syntax == (char) -1)
13126     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13127
13128   for (p = info->disassembler_options; p != NULL; )
13129     {
13130       if (CONST_STRNEQ (p, "amd64"))
13131         isa64 = amd64;
13132       else if (CONST_STRNEQ (p, "intel64"))
13133         isa64 = intel64;
13134       else if (CONST_STRNEQ (p, "x86-64"))
13135         {
13136           address_mode = mode_64bit;
13137           priv.orig_sizeflag = AFLAG | DFLAG;
13138         }
13139       else if (CONST_STRNEQ (p, "i386"))
13140         {
13141           address_mode = mode_32bit;
13142           priv.orig_sizeflag = AFLAG | DFLAG;
13143         }
13144       else if (CONST_STRNEQ (p, "i8086"))
13145         {
13146           address_mode = mode_16bit;
13147           priv.orig_sizeflag = 0;
13148         }
13149       else if (CONST_STRNEQ (p, "intel"))
13150         {
13151           intel_syntax = 1;
13152           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13153             intel_mnemonic = 1;
13154         }
13155       else if (CONST_STRNEQ (p, "att"))
13156         {
13157           intel_syntax = 0;
13158           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13159             intel_mnemonic = 0;
13160         }
13161       else if (CONST_STRNEQ (p, "addr"))
13162         {
13163           if (address_mode == mode_64bit)
13164             {
13165               if (p[4] == '3' && p[5] == '2')
13166                 priv.orig_sizeflag &= ~AFLAG;
13167               else if (p[4] == '6' && p[5] == '4')
13168                 priv.orig_sizeflag |= AFLAG;
13169             }
13170           else
13171             {
13172               if (p[4] == '1' && p[5] == '6')
13173                 priv.orig_sizeflag &= ~AFLAG;
13174               else if (p[4] == '3' && p[5] == '2')
13175                 priv.orig_sizeflag |= AFLAG;
13176             }
13177         }
13178       else if (CONST_STRNEQ (p, "data"))
13179         {
13180           if (p[4] == '1' && p[5] == '6')
13181             priv.orig_sizeflag &= ~DFLAG;
13182           else if (p[4] == '3' && p[5] == '2')
13183             priv.orig_sizeflag |= DFLAG;
13184         }
13185       else if (CONST_STRNEQ (p, "suffix"))
13186         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13187
13188       p = strchr (p, ',');
13189       if (p != NULL)
13190         p++;
13191     }
13192
13193   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13194     {
13195       (*info->fprintf_func) (info->stream,
13196                              _("64-bit address is disabled"));
13197       return -1;
13198     }
13199
13200   if (intel_syntax)
13201     {
13202       names64 = intel_names64;
13203       names32 = intel_names32;
13204       names16 = intel_names16;
13205       names8 = intel_names8;
13206       names8rex = intel_names8rex;
13207       names_seg = intel_names_seg;
13208       names_mm = intel_names_mm;
13209       names_bnd = intel_names_bnd;
13210       names_xmm = intel_names_xmm;
13211       names_ymm = intel_names_ymm;
13212       names_zmm = intel_names_zmm;
13213       index64 = intel_index64;
13214       index32 = intel_index32;
13215       names_mask = intel_names_mask;
13216       index16 = intel_index16;
13217       open_char = '[';
13218       close_char = ']';
13219       separator_char = '+';
13220       scale_char = '*';
13221     }
13222   else
13223     {
13224       names64 = att_names64;
13225       names32 = att_names32;
13226       names16 = att_names16;
13227       names8 = att_names8;
13228       names8rex = att_names8rex;
13229       names_seg = att_names_seg;
13230       names_mm = att_names_mm;
13231       names_bnd = att_names_bnd;
13232       names_xmm = att_names_xmm;
13233       names_ymm = att_names_ymm;
13234       names_zmm = att_names_zmm;
13235       index64 = att_index64;
13236       index32 = att_index32;
13237       names_mask = att_names_mask;
13238       index16 = att_index16;
13239       open_char = '(';
13240       close_char =  ')';
13241       separator_char = ',';
13242       scale_char = ',';
13243     }
13244
13245   /* The output looks better if we put 7 bytes on a line, since that
13246      puts most long word instructions on a single line.  Use 8 bytes
13247      for Intel L1OM.  */
13248   if ((info->mach & bfd_mach_l1om) != 0)
13249     info->bytes_per_line = 8;
13250   else
13251     info->bytes_per_line = 7;
13252
13253   info->private_data = &priv;
13254   priv.max_fetched = priv.the_buffer;
13255   priv.insn_start = pc;
13256
13257   obuf[0] = 0;
13258   for (i = 0; i < MAX_OPERANDS; ++i)
13259     {
13260       op_out[i][0] = 0;
13261       op_index[i] = -1;
13262     }
13263
13264   the_info = info;
13265   start_pc = pc;
13266   start_codep = priv.the_buffer;
13267   codep = priv.the_buffer;
13268
13269   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13270     {
13271       const char *name;
13272
13273       /* Getting here means we tried for data but didn't get it.  That
13274          means we have an incomplete instruction of some sort.  Just
13275          print the first byte as a prefix or a .byte pseudo-op.  */
13276       if (codep > priv.the_buffer)
13277         {
13278           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13279           if (name != NULL)
13280             (*info->fprintf_func) (info->stream, "%s", name);
13281           else
13282             {
13283               /* Just print the first byte as a .byte instruction.  */
13284               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13285                                      (unsigned int) priv.the_buffer[0]);
13286             }
13287
13288           return 1;
13289         }
13290
13291       return -1;
13292     }
13293
13294   obufp = obuf;
13295   sizeflag = priv.orig_sizeflag;
13296
13297   if (!ckprefix () || rex_used)
13298     {
13299       /* Too many prefixes or unused REX prefixes.  */
13300       for (i = 0;
13301            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13302            i++)
13303         (*info->fprintf_func) (info->stream, "%s%s",
13304                                i == 0 ? "" : " ",
13305                                prefix_name (all_prefixes[i], sizeflag));
13306       return i;
13307     }
13308
13309   insn_codep = codep;
13310
13311   FETCH_DATA (info, codep + 1);
13312   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13313
13314   if (((prefixes & PREFIX_FWAIT)
13315        && ((*codep < 0xd8) || (*codep > 0xdf))))
13316     {
13317       /* Handle prefixes before fwait.  */
13318       for (i = 0; i < fwait_prefix && all_prefixes[i];
13319            i++)
13320         (*info->fprintf_func) (info->stream, "%s ",
13321                                prefix_name (all_prefixes[i], sizeflag));
13322       (*info->fprintf_func) (info->stream, "fwait");
13323       return i + 1;
13324     }
13325
13326   if (*codep == 0x0f)
13327     {
13328       unsigned char threebyte;
13329
13330       codep++;
13331       FETCH_DATA (info, codep + 1);
13332       threebyte = *codep;
13333       dp = &dis386_twobyte[threebyte];
13334       need_modrm = twobyte_has_modrm[*codep];
13335       codep++;
13336     }
13337   else
13338     {
13339       dp = &dis386[*codep];
13340       need_modrm = onebyte_has_modrm[*codep];
13341       codep++;
13342     }
13343
13344   /* Save sizeflag for printing the extra prefixes later before updating
13345      it for mnemonic and operand processing.  The prefix names depend
13346      only on the address mode.  */
13347   orig_sizeflag = sizeflag;
13348   if (prefixes & PREFIX_ADDR)
13349     sizeflag ^= AFLAG;
13350   if ((prefixes & PREFIX_DATA))
13351     sizeflag ^= DFLAG;
13352
13353   end_codep = codep;
13354   if (need_modrm)
13355     {
13356       FETCH_DATA (info, codep + 1);
13357       modrm.mod = (*codep >> 6) & 3;
13358       modrm.reg = (*codep >> 3) & 7;
13359       modrm.rm = *codep & 7;
13360     }
13361
13362   need_vex = 0;
13363   need_vex_reg = 0;
13364   vex_w_done = 0;
13365   memset (&vex, 0, sizeof (vex));
13366
13367   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13368     {
13369       get_sib (info, sizeflag);
13370       dofloat (sizeflag);
13371     }
13372   else
13373     {
13374       dp = get_valid_dis386 (dp, info);
13375       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13376         {
13377           get_sib (info, sizeflag);
13378           for (i = 0; i < MAX_OPERANDS; ++i)
13379             {
13380               obufp = op_out[i];
13381               op_ad = MAX_OPERANDS - 1 - i;
13382               if (dp->op[i].rtn)
13383                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13384               /* For EVEX instruction after the last operand masking
13385                  should be printed.  */
13386               if (i == 0 && vex.evex)
13387                 {
13388                   /* Don't print {%k0}.  */
13389                   if (vex.mask_register_specifier)
13390                     {
13391                       oappend ("{");
13392                       oappend (names_mask[vex.mask_register_specifier]);
13393                       oappend ("}");
13394                     }
13395                   if (vex.zeroing)
13396                     oappend ("{z}");
13397                 }
13398             }
13399         }
13400     }
13401
13402   /* Check if the REX prefix is used.  */
13403   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13404     all_prefixes[last_rex_prefix] = 0;
13405
13406   /* Check if the SEG prefix is used.  */
13407   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13408                    | PREFIX_FS | PREFIX_GS)) != 0
13409       && (used_prefixes & active_seg_prefix) != 0)
13410     all_prefixes[last_seg_prefix] = 0;
13411
13412   /* Check if the ADDR prefix is used.  */
13413   if ((prefixes & PREFIX_ADDR) != 0
13414       && (used_prefixes & PREFIX_ADDR) != 0)
13415     all_prefixes[last_addr_prefix] = 0;
13416
13417   /* Check if the DATA prefix is used.  */
13418   if ((prefixes & PREFIX_DATA) != 0
13419       && (used_prefixes & PREFIX_DATA) != 0)
13420     all_prefixes[last_data_prefix] = 0;
13421
13422   /* Print the extra prefixes.  */
13423   prefix_length = 0;
13424   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13425     if (all_prefixes[i])
13426       {
13427         const char *name;
13428         name = prefix_name (all_prefixes[i], orig_sizeflag);
13429         if (name == NULL)
13430           abort ();
13431         prefix_length += strlen (name) + 1;
13432         (*info->fprintf_func) (info->stream, "%s ", name);
13433       }
13434
13435   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13436      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13437      used by putop and MMX/SSE operand and may be overriden by the
13438      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13439      separately.  */
13440   if (dp->prefix_requirement == PREFIX_OPCODE
13441       && dp != &bad_opcode
13442       && (((prefixes
13443             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13444            && (used_prefixes
13445                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13446           || ((((prefixes
13447                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13448                 == PREFIX_DATA)
13449                && (used_prefixes & PREFIX_DATA) == 0))))
13450     {
13451       (*info->fprintf_func) (info->stream, "(bad)");
13452       return end_codep - priv.the_buffer;
13453     }
13454
13455   /* Check maximum code length.  */
13456   if ((codep - start_codep) > MAX_CODE_LENGTH)
13457     {
13458       (*info->fprintf_func) (info->stream, "(bad)");
13459       return MAX_CODE_LENGTH;
13460     }
13461
13462   obufp = mnemonicendp;
13463   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13464     oappend (" ");
13465   oappend (" ");
13466   (*info->fprintf_func) (info->stream, "%s", obuf);
13467
13468   /* The enter and bound instructions are printed with operands in the same
13469      order as the intel book; everything else is printed in reverse order.  */
13470   if (intel_syntax || two_source_ops)
13471     {
13472       bfd_vma riprel;
13473
13474       for (i = 0; i < MAX_OPERANDS; ++i)
13475         op_txt[i] = op_out[i];
13476
13477       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13478           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13479         {
13480           op_txt[2] = op_out[3];
13481           op_txt[3] = op_out[2];
13482         }
13483
13484       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13485         {
13486           op_ad = op_index[i];
13487           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13488           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13489           riprel = op_riprel[i];
13490           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13491           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13492         }
13493     }
13494   else
13495     {
13496       for (i = 0; i < MAX_OPERANDS; ++i)
13497         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13498     }
13499
13500   needcomma = 0;
13501   for (i = 0; i < MAX_OPERANDS; ++i)
13502     if (*op_txt[i])
13503       {
13504         if (needcomma)
13505           (*info->fprintf_func) (info->stream, ",");
13506         if (op_index[i] != -1 && !op_riprel[i])
13507           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13508         else
13509           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13510         needcomma = 1;
13511       }
13512
13513   for (i = 0; i < MAX_OPERANDS; i++)
13514     if (op_index[i] != -1 && op_riprel[i])
13515       {
13516         (*info->fprintf_func) (info->stream, "        # ");
13517         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13518                                                 + op_address[op_index[i]]), info);
13519         break;
13520       }
13521   return codep - priv.the_buffer;
13522 }
13523
13524 static const char *float_mem[] = {
13525   /* d8 */
13526   "fadd{s|}",
13527   "fmul{s|}",
13528   "fcom{s|}",
13529   "fcomp{s|}",
13530   "fsub{s|}",
13531   "fsubr{s|}",
13532   "fdiv{s|}",
13533   "fdivr{s|}",
13534   /* d9 */
13535   "fld{s|}",
13536   "(bad)",
13537   "fst{s|}",
13538   "fstp{s|}",
13539   "fldenvIC",
13540   "fldcw",
13541   "fNstenvIC",
13542   "fNstcw",
13543   /* da */
13544   "fiadd{l|}",
13545   "fimul{l|}",
13546   "ficom{l|}",
13547   "ficomp{l|}",
13548   "fisub{l|}",
13549   "fisubr{l|}",
13550   "fidiv{l|}",
13551   "fidivr{l|}",
13552   /* db */
13553   "fild{l|}",
13554   "fisttp{l|}",
13555   "fist{l|}",
13556   "fistp{l|}",
13557   "(bad)",
13558   "fld{t||t|}",
13559   "(bad)",
13560   "fstp{t||t|}",
13561   /* dc */
13562   "fadd{l|}",
13563   "fmul{l|}",
13564   "fcom{l|}",
13565   "fcomp{l|}",
13566   "fsub{l|}",
13567   "fsubr{l|}",
13568   "fdiv{l|}",
13569   "fdivr{l|}",
13570   /* dd */
13571   "fld{l|}",
13572   "fisttp{ll|}",
13573   "fst{l||}",
13574   "fstp{l|}",
13575   "frstorIC",
13576   "(bad)",
13577   "fNsaveIC",
13578   "fNstsw",
13579   /* de */
13580   "fiadd{s|}",
13581   "fimul{s|}",
13582   "ficom{s|}",
13583   "ficomp{s|}",
13584   "fisub{s|}",
13585   "fisubr{s|}",
13586   "fidiv{s|}",
13587   "fidivr{s|}",
13588   /* df */
13589   "fild{s|}",
13590   "fisttp{s|}",
13591   "fist{s|}",
13592   "fistp{s|}",
13593   "fbld",
13594   "fild{ll|}",
13595   "fbstp",
13596   "fistp{ll|}",
13597 };
13598
13599 static const unsigned char float_mem_mode[] = {
13600   /* d8 */
13601   d_mode,
13602   d_mode,
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   /* d9 */
13610   d_mode,
13611   0,
13612   d_mode,
13613   d_mode,
13614   0,
13615   w_mode,
13616   0,
13617   w_mode,
13618   /* da */
13619   d_mode,
13620   d_mode,
13621   d_mode,
13622   d_mode,
13623   d_mode,
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   /* db */
13628   d_mode,
13629   d_mode,
13630   d_mode,
13631   d_mode,
13632   0,
13633   t_mode,
13634   0,
13635   t_mode,
13636   /* dc */
13637   q_mode,
13638   q_mode,
13639   q_mode,
13640   q_mode,
13641   q_mode,
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   /* dd */
13646   q_mode,
13647   q_mode,
13648   q_mode,
13649   q_mode,
13650   0,
13651   0,
13652   0,
13653   w_mode,
13654   /* de */
13655   w_mode,
13656   w_mode,
13657   w_mode,
13658   w_mode,
13659   w_mode,
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   /* df */
13664   w_mode,
13665   w_mode,
13666   w_mode,
13667   w_mode,
13668   t_mode,
13669   q_mode,
13670   t_mode,
13671   q_mode
13672 };
13673
13674 #define ST { OP_ST, 0 }
13675 #define STi { OP_STi, 0 }
13676
13677 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13678 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13679 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13680 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13681 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13682 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13683 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13684 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13685 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13686
13687 static const struct dis386 float_reg[][8] = {
13688   /* d8 */
13689   {
13690     { "fadd",   { ST, STi }, 0 },
13691     { "fmul",   { ST, STi }, 0 },
13692     { "fcom",   { STi }, 0 },
13693     { "fcomp",  { STi }, 0 },
13694     { "fsub",   { ST, STi }, 0 },
13695     { "fsubr",  { ST, STi }, 0 },
13696     { "fdiv",   { ST, STi }, 0 },
13697     { "fdivr",  { ST, STi }, 0 },
13698   },
13699   /* d9 */
13700   {
13701     { "fld",    { STi }, 0 },
13702     { "fxch",   { STi }, 0 },
13703     { FGRPd9_2 },
13704     { Bad_Opcode },
13705     { FGRPd9_4 },
13706     { FGRPd9_5 },
13707     { FGRPd9_6 },
13708     { FGRPd9_7 },
13709   },
13710   /* da */
13711   {
13712     { "fcmovb", { ST, STi }, 0 },
13713     { "fcmove", { ST, STi }, 0 },
13714     { "fcmovbe",{ ST, STi }, 0 },
13715     { "fcmovu", { ST, STi }, 0 },
13716     { Bad_Opcode },
13717     { FGRPda_5 },
13718     { Bad_Opcode },
13719     { Bad_Opcode },
13720   },
13721   /* db */
13722   {
13723     { "fcmovnb",{ ST, STi }, 0 },
13724     { "fcmovne",{ ST, STi }, 0 },
13725     { "fcmovnbe",{ ST, STi }, 0 },
13726     { "fcmovnu",{ ST, STi }, 0 },
13727     { FGRPdb_4 },
13728     { "fucomi", { ST, STi }, 0 },
13729     { "fcomi",  { ST, STi }, 0 },
13730     { Bad_Opcode },
13731   },
13732   /* dc */
13733   {
13734     { "fadd",   { STi, ST }, 0 },
13735     { "fmul",   { STi, ST }, 0 },
13736     { Bad_Opcode },
13737     { Bad_Opcode },
13738     { "fsub{!M|r}",     { STi, ST }, 0 },
13739     { "fsub{M|}",       { STi, ST }, 0 },
13740     { "fdiv{!M|r}",     { STi, ST }, 0 },
13741     { "fdiv{M|}",       { STi, ST }, 0 },
13742   },
13743   /* dd */
13744   {
13745     { "ffree",  { STi }, 0 },
13746     { Bad_Opcode },
13747     { "fst",    { STi }, 0 },
13748     { "fstp",   { STi }, 0 },
13749     { "fucom",  { STi }, 0 },
13750     { "fucomp", { STi }, 0 },
13751     { Bad_Opcode },
13752     { Bad_Opcode },
13753   },
13754   /* de */
13755   {
13756     { "faddp",  { STi, ST }, 0 },
13757     { "fmulp",  { STi, ST }, 0 },
13758     { Bad_Opcode },
13759     { FGRPde_3 },
13760     { "fsub{!M|r}p",    { STi, ST }, 0 },
13761     { "fsub{M|}p",      { STi, ST }, 0 },
13762     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13763     { "fdiv{M|}p",      { STi, ST }, 0 },
13764   },
13765   /* df */
13766   {
13767     { "ffreep", { STi }, 0 },
13768     { Bad_Opcode },
13769     { Bad_Opcode },
13770     { Bad_Opcode },
13771     { FGRPdf_4 },
13772     { "fucomip", { ST, STi }, 0 },
13773     { "fcomip", { ST, STi }, 0 },
13774     { Bad_Opcode },
13775   },
13776 };
13777
13778 static char *fgrps[][8] = {
13779   /* Bad opcode 0 */
13780   {
13781     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13782   },
13783
13784   /* d9_2  1 */
13785   {
13786     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13787   },
13788
13789   /* d9_4  2 */
13790   {
13791     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13792   },
13793
13794   /* d9_5  3 */
13795   {
13796     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13797   },
13798
13799   /* d9_6  4 */
13800   {
13801     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13802   },
13803
13804   /* d9_7  5 */
13805   {
13806     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13807   },
13808
13809   /* da_5  6 */
13810   {
13811     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13812   },
13813
13814   /* db_4  7 */
13815   {
13816     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13817     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13818   },
13819
13820   /* de_3  8 */
13821   {
13822     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13823   },
13824
13825   /* df_4  9 */
13826   {
13827     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13828   },
13829 };
13830
13831 static void
13832 swap_operand (void)
13833 {
13834   mnemonicendp[0] = '.';
13835   mnemonicendp[1] = 's';
13836   mnemonicendp += 2;
13837 }
13838
13839 static void
13840 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13841                int sizeflag ATTRIBUTE_UNUSED)
13842 {
13843   /* Skip mod/rm byte.  */
13844   MODRM_CHECK;
13845   codep++;
13846 }
13847
13848 static void
13849 dofloat (int sizeflag)
13850 {
13851   const struct dis386 *dp;
13852   unsigned char floatop;
13853
13854   floatop = codep[-1];
13855
13856   if (modrm.mod != 3)
13857     {
13858       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13859
13860       putop (float_mem[fp_indx], sizeflag);
13861       obufp = op_out[0];
13862       op_ad = 2;
13863       OP_E (float_mem_mode[fp_indx], sizeflag);
13864       return;
13865     }
13866   /* Skip mod/rm byte.  */
13867   MODRM_CHECK;
13868   codep++;
13869
13870   dp = &float_reg[floatop - 0xd8][modrm.reg];
13871   if (dp->name == NULL)
13872     {
13873       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13874
13875       /* Instruction fnstsw is only one with strange arg.  */
13876       if (floatop == 0xdf && codep[-1] == 0xe0)
13877         strcpy (op_out[0], names16[0]);
13878     }
13879   else
13880     {
13881       putop (dp->name, sizeflag);
13882
13883       obufp = op_out[0];
13884       op_ad = 2;
13885       if (dp->op[0].rtn)
13886         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13887
13888       obufp = op_out[1];
13889       op_ad = 1;
13890       if (dp->op[1].rtn)
13891         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13892     }
13893 }
13894
13895 /* Like oappend (below), but S is a string starting with '%'.
13896    In Intel syntax, the '%' is elided.  */
13897 static void
13898 oappend_maybe_intel (const char *s)
13899 {
13900   oappend (s + intel_syntax);
13901 }
13902
13903 static void
13904 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13905 {
13906   oappend_maybe_intel ("%st");
13907 }
13908
13909 static void
13910 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13911 {
13912   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13913   oappend_maybe_intel (scratchbuf);
13914 }
13915
13916 /* Capital letters in template are macros.  */
13917 static int
13918 putop (const char *in_template, int sizeflag)
13919 {
13920   const char *p;
13921   int alt = 0;
13922   int cond = 1;
13923   unsigned int l = 0, len = 1;
13924   char last[4];
13925
13926 #define SAVE_LAST(c)                    \
13927   if (l < len && l < sizeof (last))     \
13928     last[l++] = c;                      \
13929   else                                  \
13930     abort ();
13931
13932   for (p = in_template; *p; p++)
13933     {
13934       switch (*p)
13935         {
13936         default:
13937           *obufp++ = *p;
13938           break;
13939         case '%':
13940           len++;
13941           break;
13942         case '!':
13943           cond = 0;
13944           break;
13945         case '{':
13946           if (intel_syntax)
13947             {
13948               while (*++p != '|')
13949                 if (*p == '}' || *p == '\0')
13950                   abort ();
13951             }
13952           /* Fall through.  */
13953         case 'I':
13954           alt = 1;
13955           continue;
13956         case '|':
13957           while (*++p != '}')
13958             {
13959               if (*p == '\0')
13960                 abort ();
13961             }
13962           break;
13963         case '}':
13964           break;
13965         case 'A':
13966           if (intel_syntax)
13967             break;
13968           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13969             *obufp++ = 'b';
13970           break;
13971         case 'B':
13972           if (l == 0 && len == 1)
13973             {
13974 case_B:
13975               if (intel_syntax)
13976                 break;
13977               if (sizeflag & SUFFIX_ALWAYS)
13978                 *obufp++ = 'b';
13979             }
13980           else
13981             {
13982               if (l != 1
13983                   || len != 2
13984                   || last[0] != 'L')
13985                 {
13986                   SAVE_LAST (*p);
13987                   break;
13988                 }
13989
13990               if (address_mode == mode_64bit
13991                   && !(prefixes & PREFIX_ADDR))
13992                 {
13993                   *obufp++ = 'a';
13994                   *obufp++ = 'b';
13995                   *obufp++ = 's';
13996                 }
13997
13998               goto case_B;
13999             }
14000           break;
14001         case 'C':
14002           if (intel_syntax && !alt)
14003             break;
14004           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14005             {
14006               if (sizeflag & DFLAG)
14007                 *obufp++ = intel_syntax ? 'd' : 'l';
14008               else
14009                 *obufp++ = intel_syntax ? 'w' : 's';
14010               used_prefixes |= (prefixes & PREFIX_DATA);
14011             }
14012           break;
14013         case 'D':
14014           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14015             break;
14016           USED_REX (REX_W);
14017           if (modrm.mod == 3)
14018             {
14019               if (rex & REX_W)
14020                 *obufp++ = 'q';
14021               else
14022                 {
14023                   if (sizeflag & DFLAG)
14024                     *obufp++ = intel_syntax ? 'd' : 'l';
14025                   else
14026                     *obufp++ = 'w';
14027                   used_prefixes |= (prefixes & PREFIX_DATA);
14028                 }
14029             }
14030           else
14031             *obufp++ = 'w';
14032           break;
14033         case 'E':               /* For jcxz/jecxz */
14034           if (address_mode == mode_64bit)
14035             {
14036               if (sizeflag & AFLAG)
14037                 *obufp++ = 'r';
14038               else
14039                 *obufp++ = 'e';
14040             }
14041           else
14042             if (sizeflag & AFLAG)
14043               *obufp++ = 'e';
14044           used_prefixes |= (prefixes & PREFIX_ADDR);
14045           break;
14046         case 'F':
14047           if (intel_syntax)
14048             break;
14049           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14050             {
14051               if (sizeflag & AFLAG)
14052                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14053               else
14054                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14055               used_prefixes |= (prefixes & PREFIX_ADDR);
14056             }
14057           break;
14058         case 'G':
14059           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14060             break;
14061           if ((rex & REX_W) || (sizeflag & DFLAG))
14062             *obufp++ = 'l';
14063           else
14064             *obufp++ = 'w';
14065           if (!(rex & REX_W))
14066             used_prefixes |= (prefixes & PREFIX_DATA);
14067           break;
14068         case 'H':
14069           if (intel_syntax)
14070             break;
14071           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14072               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14073             {
14074               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14075               *obufp++ = ',';
14076               *obufp++ = 'p';
14077               if (prefixes & PREFIX_DS)
14078                 *obufp++ = 't';
14079               else
14080                 *obufp++ = 'n';
14081             }
14082           break;
14083         case 'J':
14084           if (intel_syntax)
14085             break;
14086           *obufp++ = 'l';
14087           break;
14088         case 'K':
14089           USED_REX (REX_W);
14090           if (rex & REX_W)
14091             *obufp++ = 'q';
14092           else
14093             *obufp++ = 'd';
14094           break;
14095         case 'Z':
14096           if (l != 0 || len != 1)
14097             {
14098               if (l != 1 || len != 2 || last[0] != 'X')
14099                 {
14100                   SAVE_LAST (*p);
14101                   break;
14102                 }
14103               if (!need_vex || !vex.evex)
14104                 abort ();
14105               if (intel_syntax
14106                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14107                 break;
14108               switch (vex.length)
14109                 {
14110                 case 128:
14111                   *obufp++ = 'x';
14112                   break;
14113                 case 256:
14114                   *obufp++ = 'y';
14115                   break;
14116                 case 512:
14117                   *obufp++ = 'z';
14118                   break;
14119                 default:
14120                   abort ();
14121                 }
14122               break;
14123             }
14124           if (intel_syntax)
14125             break;
14126           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14127             {
14128               *obufp++ = 'q';
14129               break;
14130             }
14131           /* Fall through.  */
14132           goto case_L;
14133         case 'L':
14134           if (l != 0 || len != 1)
14135             {
14136               SAVE_LAST (*p);
14137               break;
14138             }
14139 case_L:
14140           if (intel_syntax)
14141             break;
14142           if (sizeflag & SUFFIX_ALWAYS)
14143             *obufp++ = 'l';
14144           break;
14145         case 'M':
14146           if (intel_mnemonic != cond)
14147             *obufp++ = 'r';
14148           break;
14149         case 'N':
14150           if ((prefixes & PREFIX_FWAIT) == 0)
14151             *obufp++ = 'n';
14152           else
14153             used_prefixes |= PREFIX_FWAIT;
14154           break;
14155         case 'O':
14156           USED_REX (REX_W);
14157           if (rex & REX_W)
14158             *obufp++ = 'o';
14159           else if (intel_syntax && (sizeflag & DFLAG))
14160             *obufp++ = 'q';
14161           else
14162             *obufp++ = 'd';
14163           if (!(rex & REX_W))
14164             used_prefixes |= (prefixes & PREFIX_DATA);
14165           break;
14166         case '&':
14167           if (!intel_syntax
14168               && address_mode == mode_64bit
14169               && isa64 == intel64)
14170             {
14171               *obufp++ = 'q';
14172               break;
14173             }
14174           /* Fall through.  */
14175         case 'T':
14176           if (!intel_syntax
14177               && address_mode == mode_64bit
14178               && ((sizeflag & DFLAG) || (rex & REX_W)))
14179             {
14180               *obufp++ = 'q';
14181               break;
14182             }
14183           /* Fall through.  */
14184           goto case_P;
14185         case 'P':
14186           if (l == 0 && len == 1)
14187             {
14188 case_P:
14189               if (intel_syntax)
14190                 {
14191                   if ((rex & REX_W) == 0
14192                       && (prefixes & PREFIX_DATA))
14193                     {
14194                       if ((sizeflag & DFLAG) == 0)
14195                         *obufp++ = 'w';
14196                       used_prefixes |= (prefixes & PREFIX_DATA);
14197                     }
14198                   break;
14199                 }
14200               if ((prefixes & PREFIX_DATA)
14201                   || (rex & REX_W)
14202                   || (sizeflag & SUFFIX_ALWAYS))
14203                 {
14204                   USED_REX (REX_W);
14205                   if (rex & REX_W)
14206                     *obufp++ = 'q';
14207                   else
14208                     {
14209                       if (sizeflag & DFLAG)
14210                         *obufp++ = 'l';
14211                       else
14212                         *obufp++ = 'w';
14213                       used_prefixes |= (prefixes & PREFIX_DATA);
14214                     }
14215                 }
14216             }
14217           else
14218             {
14219               if (l != 1 || len != 2 || last[0] != 'L')
14220                 {
14221                   SAVE_LAST (*p);
14222                   break;
14223                 }
14224
14225               if ((prefixes & PREFIX_DATA)
14226                   || (rex & REX_W)
14227                   || (sizeflag & SUFFIX_ALWAYS))
14228                 {
14229                   USED_REX (REX_W);
14230                   if (rex & REX_W)
14231                     *obufp++ = 'q';
14232                   else
14233                     {
14234                       if (sizeflag & DFLAG)
14235                         *obufp++ = intel_syntax ? 'd' : 'l';
14236                       else
14237                         *obufp++ = 'w';
14238                       used_prefixes |= (prefixes & PREFIX_DATA);
14239                     }
14240                 }
14241             }
14242           break;
14243         case 'U':
14244           if (intel_syntax)
14245             break;
14246           if (address_mode == mode_64bit
14247               && ((sizeflag & DFLAG) || (rex & REX_W)))
14248             {
14249               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14250                 *obufp++ = 'q';
14251               break;
14252             }
14253           /* Fall through.  */
14254           goto case_Q;
14255         case 'Q':
14256           if (l == 0 && len == 1)
14257             {
14258 case_Q:
14259               if (intel_syntax && !alt)
14260                 break;
14261               USED_REX (REX_W);
14262               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14263                 {
14264                   if (rex & REX_W)
14265                     *obufp++ = 'q';
14266                   else
14267                     {
14268                       if (sizeflag & DFLAG)
14269                         *obufp++ = intel_syntax ? 'd' : 'l';
14270                       else
14271                         *obufp++ = 'w';
14272                       used_prefixes |= (prefixes & PREFIX_DATA);
14273                     }
14274                 }
14275             }
14276           else
14277             {
14278               if (l != 1 || len != 2 || last[0] != 'L')
14279                 {
14280                   SAVE_LAST (*p);
14281                   break;
14282                 }
14283               if (intel_syntax
14284                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14285                 break;
14286               if ((rex & REX_W))
14287                 {
14288                   USED_REX (REX_W);
14289                   *obufp++ = 'q';
14290                 }
14291               else
14292                 *obufp++ = 'l';
14293             }
14294           break;
14295         case 'R':
14296           USED_REX (REX_W);
14297           if (rex & REX_W)
14298             *obufp++ = 'q';
14299           else if (sizeflag & DFLAG)
14300             {
14301               if (intel_syntax)
14302                   *obufp++ = 'd';
14303               else
14304                   *obufp++ = 'l';
14305             }
14306           else
14307             *obufp++ = 'w';
14308           if (intel_syntax && !p[1]
14309               && ((rex & REX_W) || (sizeflag & DFLAG)))
14310             *obufp++ = 'e';
14311           if (!(rex & REX_W))
14312             used_prefixes |= (prefixes & PREFIX_DATA);
14313           break;
14314         case 'V':
14315           if (l == 0 && len == 1)
14316             {
14317               if (intel_syntax)
14318                 break;
14319               if (address_mode == mode_64bit
14320                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14321                 {
14322                   if (sizeflag & SUFFIX_ALWAYS)
14323                     *obufp++ = 'q';
14324                   break;
14325                 }
14326             }
14327           else
14328             {
14329               if (l != 1
14330                   || len != 2
14331                   || last[0] != 'L')
14332                 {
14333                   SAVE_LAST (*p);
14334                   break;
14335                 }
14336
14337               if (rex & REX_W)
14338                 {
14339                   *obufp++ = 'a';
14340                   *obufp++ = 'b';
14341                   *obufp++ = 's';
14342                 }
14343             }
14344           /* Fall through.  */
14345           goto case_S;
14346         case 'S':
14347           if (l == 0 && len == 1)
14348             {
14349 case_S:
14350               if (intel_syntax)
14351                 break;
14352               if (sizeflag & SUFFIX_ALWAYS)
14353                 {
14354                   if (rex & REX_W)
14355                     *obufp++ = 'q';
14356                   else
14357                     {
14358                       if (sizeflag & DFLAG)
14359                         *obufp++ = 'l';
14360                       else
14361                         *obufp++ = 'w';
14362                       used_prefixes |= (prefixes & PREFIX_DATA);
14363                     }
14364                 }
14365             }
14366           else
14367             {
14368               if (l != 1
14369                   || len != 2
14370                   || last[0] != 'L')
14371                 {
14372                   SAVE_LAST (*p);
14373                   break;
14374                 }
14375
14376               if (address_mode == mode_64bit
14377                   && !(prefixes & PREFIX_ADDR))
14378                 {
14379                   *obufp++ = 'a';
14380                   *obufp++ = 'b';
14381                   *obufp++ = 's';
14382                 }
14383
14384               goto case_S;
14385             }
14386           break;
14387         case 'X':
14388           if (l != 0 || len != 1)
14389             {
14390               SAVE_LAST (*p);
14391               break;
14392             }
14393           if (need_vex && vex.prefix)
14394             {
14395               if (vex.prefix == DATA_PREFIX_OPCODE)
14396                 *obufp++ = 'd';
14397               else
14398                 *obufp++ = 's';
14399             }
14400           else
14401             {
14402               if (prefixes & PREFIX_DATA)
14403                 *obufp++ = 'd';
14404               else
14405                 *obufp++ = 's';
14406               used_prefixes |= (prefixes & PREFIX_DATA);
14407             }
14408           break;
14409         case 'Y':
14410           if (l == 0 && len == 1)
14411             abort ();
14412           else
14413             {
14414               if (l != 1 || len != 2 || last[0] != 'X')
14415                 {
14416                   SAVE_LAST (*p);
14417                   break;
14418                 }
14419               if (!need_vex)
14420                 abort ();
14421               if (intel_syntax
14422                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14423                 break;
14424               switch (vex.length)
14425                 {
14426                 case 128:
14427                   *obufp++ = 'x';
14428                   break;
14429                 case 256:
14430                   *obufp++ = 'y';
14431                   break;
14432                 case 512:
14433                   if (!vex.evex)
14434                 default:
14435                     abort ();
14436                 }
14437             }
14438           break;
14439         case 'W':
14440           if (l == 0 && len == 1)
14441             {
14442               /* operand size flag for cwtl, cbtw */
14443               USED_REX (REX_W);
14444               if (rex & REX_W)
14445                 {
14446                   if (intel_syntax)
14447                     *obufp++ = 'd';
14448                   else
14449                     *obufp++ = 'l';
14450                 }
14451               else if (sizeflag & DFLAG)
14452                 *obufp++ = 'w';
14453               else
14454                 *obufp++ = 'b';
14455               if (!(rex & REX_W))
14456                 used_prefixes |= (prefixes & PREFIX_DATA);
14457             }
14458           else
14459             {
14460               if (l != 1
14461                   || len != 2
14462                   || (last[0] != 'X'
14463                       && last[0] != 'L'))
14464                 {
14465                   SAVE_LAST (*p);
14466                   break;
14467                 }
14468               if (!need_vex)
14469                 abort ();
14470               if (last[0] == 'X')
14471                 *obufp++ = vex.w ? 'd': 's';
14472               else
14473                 *obufp++ = vex.w ? 'q': 'd';
14474             }
14475           break;
14476         case '^':
14477           if (intel_syntax)
14478             break;
14479           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14480             {
14481               if (sizeflag & DFLAG)
14482                 *obufp++ = 'l';
14483               else
14484                 *obufp++ = 'w';
14485               used_prefixes |= (prefixes & PREFIX_DATA);
14486             }
14487           break;
14488         case '@':
14489           if (intel_syntax)
14490             break;
14491           if (address_mode == mode_64bit
14492               && (isa64 == intel64
14493                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14494               *obufp++ = 'q';
14495           else if ((prefixes & PREFIX_DATA))
14496             {
14497               if (!(sizeflag & DFLAG))
14498                 *obufp++ = 'w';
14499               used_prefixes |= (prefixes & PREFIX_DATA);
14500             }
14501           break;
14502         }
14503       alt = 0;
14504     }
14505   *obufp = 0;
14506   mnemonicendp = obufp;
14507   return 0;
14508 }
14509
14510 static void
14511 oappend (const char *s)
14512 {
14513   obufp = stpcpy (obufp, s);
14514 }
14515
14516 static void
14517 append_seg (void)
14518 {
14519   /* Only print the active segment register.  */
14520   if (!active_seg_prefix)
14521     return;
14522
14523   used_prefixes |= active_seg_prefix;
14524   switch (active_seg_prefix)
14525     {
14526     case PREFIX_CS:
14527       oappend_maybe_intel ("%cs:");
14528       break;
14529     case PREFIX_DS:
14530       oappend_maybe_intel ("%ds:");
14531       break;
14532     case PREFIX_SS:
14533       oappend_maybe_intel ("%ss:");
14534       break;
14535     case PREFIX_ES:
14536       oappend_maybe_intel ("%es:");
14537       break;
14538     case PREFIX_FS:
14539       oappend_maybe_intel ("%fs:");
14540       break;
14541     case PREFIX_GS:
14542       oappend_maybe_intel ("%gs:");
14543       break;
14544     default:
14545       break;
14546     }
14547 }
14548
14549 static void
14550 OP_indirE (int bytemode, int sizeflag)
14551 {
14552   if (!intel_syntax)
14553     oappend ("*");
14554   OP_E (bytemode, sizeflag);
14555 }
14556
14557 static void
14558 print_operand_value (char *buf, int hex, bfd_vma disp)
14559 {
14560   if (address_mode == mode_64bit)
14561     {
14562       if (hex)
14563         {
14564           char tmp[30];
14565           int i;
14566           buf[0] = '0';
14567           buf[1] = 'x';
14568           sprintf_vma (tmp, disp);
14569           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14570           strcpy (buf + 2, tmp + i);
14571         }
14572       else
14573         {
14574           bfd_signed_vma v = disp;
14575           char tmp[30];
14576           int i;
14577           if (v < 0)
14578             {
14579               *(buf++) = '-';
14580               v = -disp;
14581               /* Check for possible overflow on 0x8000000000000000.  */
14582               if (v < 0)
14583                 {
14584                   strcpy (buf, "9223372036854775808");
14585                   return;
14586                 }
14587             }
14588           if (!v)
14589             {
14590               strcpy (buf, "0");
14591               return;
14592             }
14593
14594           i = 0;
14595           tmp[29] = 0;
14596           while (v)
14597             {
14598               tmp[28 - i] = (v % 10) + '0';
14599               v /= 10;
14600               i++;
14601             }
14602           strcpy (buf, tmp + 29 - i);
14603         }
14604     }
14605   else
14606     {
14607       if (hex)
14608         sprintf (buf, "0x%x", (unsigned int) disp);
14609       else
14610         sprintf (buf, "%d", (int) disp);
14611     }
14612 }
14613
14614 /* Put DISP in BUF as signed hex number.  */
14615
14616 static void
14617 print_displacement (char *buf, bfd_vma disp)
14618 {
14619   bfd_signed_vma val = disp;
14620   char tmp[30];
14621   int i, j = 0;
14622
14623   if (val < 0)
14624     {
14625       buf[j++] = '-';
14626       val = -disp;
14627
14628       /* Check for possible overflow.  */
14629       if (val < 0)
14630         {
14631           switch (address_mode)
14632             {
14633             case mode_64bit:
14634               strcpy (buf + j, "0x8000000000000000");
14635               break;
14636             case mode_32bit:
14637               strcpy (buf + j, "0x80000000");
14638               break;
14639             case mode_16bit:
14640               strcpy (buf + j, "0x8000");
14641               break;
14642             }
14643           return;
14644         }
14645     }
14646
14647   buf[j++] = '0';
14648   buf[j++] = 'x';
14649
14650   sprintf_vma (tmp, (bfd_vma) val);
14651   for (i = 0; tmp[i] == '0'; i++)
14652     continue;
14653   if (tmp[i] == '\0')
14654     i--;
14655   strcpy (buf + j, tmp + i);
14656 }
14657
14658 static void
14659 intel_operand_size (int bytemode, int sizeflag)
14660 {
14661   if (vex.evex
14662       && vex.b
14663       && (bytemode == x_mode
14664           || bytemode == evex_half_bcst_xmmq_mode))
14665     {
14666       if (vex.w)
14667         oappend ("QWORD PTR ");
14668       else
14669         oappend ("DWORD PTR ");
14670       return;
14671     }
14672   switch (bytemode)
14673     {
14674     case b_mode:
14675     case b_swap_mode:
14676     case dqb_mode:
14677     case db_mode:
14678       oappend ("BYTE PTR ");
14679       break;
14680     case w_mode:
14681     case dw_mode:
14682     case dqw_mode:
14683       oappend ("WORD PTR ");
14684       break;
14685     case indir_v_mode:
14686       if (address_mode == mode_64bit && isa64 == intel64)
14687         {
14688           oappend ("QWORD PTR ");
14689           break;
14690         }
14691       /* Fall through.  */
14692     case stack_v_mode:
14693       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14694         {
14695           oappend ("QWORD PTR ");
14696           break;
14697         }
14698       /* Fall through.  */
14699     case v_mode:
14700     case v_swap_mode:
14701     case dq_mode:
14702       USED_REX (REX_W);
14703       if (rex & REX_W)
14704         oappend ("QWORD PTR ");
14705       else
14706         {
14707           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14708             oappend ("DWORD PTR ");
14709           else
14710             oappend ("WORD PTR ");
14711           used_prefixes |= (prefixes & PREFIX_DATA);
14712         }
14713       break;
14714     case z_mode:
14715       if ((rex & REX_W) || (sizeflag & DFLAG))
14716         *obufp++ = 'D';
14717       oappend ("WORD PTR ");
14718       if (!(rex & REX_W))
14719         used_prefixes |= (prefixes & PREFIX_DATA);
14720       break;
14721     case a_mode:
14722       if (sizeflag & DFLAG)
14723         oappend ("QWORD PTR ");
14724       else
14725         oappend ("DWORD PTR ");
14726       used_prefixes |= (prefixes & PREFIX_DATA);
14727       break;
14728     case d_mode:
14729     case d_scalar_mode:
14730     case d_scalar_swap_mode:
14731     case d_swap_mode:
14732     case dqd_mode:
14733       oappend ("DWORD PTR ");
14734       break;
14735     case q_mode:
14736     case q_scalar_mode:
14737     case q_scalar_swap_mode:
14738     case q_swap_mode:
14739       oappend ("QWORD PTR ");
14740       break;
14741     case m_mode:
14742       if (address_mode == mode_64bit)
14743         oappend ("QWORD PTR ");
14744       else
14745         oappend ("DWORD PTR ");
14746       break;
14747     case f_mode:
14748       if (sizeflag & DFLAG)
14749         oappend ("FWORD PTR ");
14750       else
14751         oappend ("DWORD PTR ");
14752       used_prefixes |= (prefixes & PREFIX_DATA);
14753       break;
14754     case t_mode:
14755       oappend ("TBYTE PTR ");
14756       break;
14757     case x_mode:
14758     case x_swap_mode:
14759     case evex_x_gscat_mode:
14760     case evex_x_nobcst_mode:
14761     case b_scalar_mode:
14762     case w_scalar_mode:
14763       if (need_vex)
14764         {
14765           switch (vex.length)
14766             {
14767             case 128:
14768               oappend ("XMMWORD PTR ");
14769               break;
14770             case 256:
14771               oappend ("YMMWORD PTR ");
14772               break;
14773             case 512:
14774               oappend ("ZMMWORD PTR ");
14775               break;
14776             default:
14777               abort ();
14778             }
14779         }
14780       else
14781         oappend ("XMMWORD PTR ");
14782       break;
14783     case xmm_mode:
14784       oappend ("XMMWORD PTR ");
14785       break;
14786     case ymm_mode:
14787       oappend ("YMMWORD PTR ");
14788       break;
14789     case xmmq_mode:
14790     case evex_half_bcst_xmmq_mode:
14791       if (!need_vex)
14792         abort ();
14793
14794       switch (vex.length)
14795         {
14796         case 128:
14797           oappend ("QWORD PTR ");
14798           break;
14799         case 256:
14800           oappend ("XMMWORD PTR ");
14801           break;
14802         case 512:
14803           oappend ("YMMWORD PTR ");
14804           break;
14805         default:
14806           abort ();
14807         }
14808       break;
14809     case xmm_mb_mode:
14810       if (!need_vex)
14811         abort ();
14812
14813       switch (vex.length)
14814         {
14815         case 128:
14816         case 256:
14817         case 512:
14818           oappend ("BYTE PTR ");
14819           break;
14820         default:
14821           abort ();
14822         }
14823       break;
14824     case xmm_mw_mode:
14825       if (!need_vex)
14826         abort ();
14827
14828       switch (vex.length)
14829         {
14830         case 128:
14831         case 256:
14832         case 512:
14833           oappend ("WORD PTR ");
14834           break;
14835         default:
14836           abort ();
14837         }
14838       break;
14839     case xmm_md_mode:
14840       if (!need_vex)
14841         abort ();
14842
14843       switch (vex.length)
14844         {
14845         case 128:
14846         case 256:
14847         case 512:
14848           oappend ("DWORD PTR ");
14849           break;
14850         default:
14851           abort ();
14852         }
14853       break;
14854     case xmm_mq_mode:
14855       if (!need_vex)
14856         abort ();
14857
14858       switch (vex.length)
14859         {
14860         case 128:
14861         case 256:
14862         case 512:
14863           oappend ("QWORD PTR ");
14864           break;
14865         default:
14866           abort ();
14867         }
14868       break;
14869     case xmmdw_mode:
14870       if (!need_vex)
14871         abort ();
14872
14873       switch (vex.length)
14874         {
14875         case 128:
14876           oappend ("WORD PTR ");
14877           break;
14878         case 256:
14879           oappend ("DWORD PTR ");
14880           break;
14881         case 512:
14882           oappend ("QWORD PTR ");
14883           break;
14884         default:
14885           abort ();
14886         }
14887       break;
14888     case xmmqd_mode:
14889       if (!need_vex)
14890         abort ();
14891
14892       switch (vex.length)
14893         {
14894         case 128:
14895           oappend ("DWORD PTR ");
14896           break;
14897         case 256:
14898           oappend ("QWORD PTR ");
14899           break;
14900         case 512:
14901           oappend ("XMMWORD PTR ");
14902           break;
14903         default:
14904           abort ();
14905         }
14906       break;
14907     case ymmq_mode:
14908       if (!need_vex)
14909         abort ();
14910
14911       switch (vex.length)
14912         {
14913         case 128:
14914           oappend ("QWORD PTR ");
14915           break;
14916         case 256:
14917           oappend ("YMMWORD PTR ");
14918           break;
14919         case 512:
14920           oappend ("ZMMWORD PTR ");
14921           break;
14922         default:
14923           abort ();
14924         }
14925       break;
14926     case ymmxmm_mode:
14927       if (!need_vex)
14928         abort ();
14929
14930       switch (vex.length)
14931         {
14932         case 128:
14933         case 256:
14934           oappend ("XMMWORD PTR ");
14935           break;
14936         default:
14937           abort ();
14938         }
14939       break;
14940     case o_mode:
14941       oappend ("OWORD PTR ");
14942       break;
14943     case xmm_mdq_mode:
14944     case vex_w_dq_mode:
14945     case vex_scalar_w_dq_mode:
14946       if (!need_vex)
14947         abort ();
14948
14949       if (vex.w)
14950         oappend ("QWORD PTR ");
14951       else
14952         oappend ("DWORD PTR ");
14953       break;
14954     case vex_vsib_d_w_dq_mode:
14955     case vex_vsib_q_w_dq_mode:
14956       if (!need_vex)
14957         abort ();
14958
14959       if (!vex.evex)
14960         {
14961           if (vex.w)
14962             oappend ("QWORD PTR ");
14963           else
14964             oappend ("DWORD PTR ");
14965         }
14966       else
14967         {
14968           switch (vex.length)
14969             {
14970             case 128:
14971               oappend ("XMMWORD PTR ");
14972               break;
14973             case 256:
14974               oappend ("YMMWORD PTR ");
14975               break;
14976             case 512:
14977               oappend ("ZMMWORD PTR ");
14978               break;
14979             default:
14980               abort ();
14981             }
14982         }
14983       break;
14984     case vex_vsib_q_w_d_mode:
14985     case vex_vsib_d_w_d_mode:
14986       if (!need_vex || !vex.evex)
14987         abort ();
14988
14989       switch (vex.length)
14990         {
14991         case 128:
14992           oappend ("QWORD PTR ");
14993           break;
14994         case 256:
14995           oappend ("XMMWORD PTR ");
14996           break;
14997         case 512:
14998           oappend ("YMMWORD PTR ");
14999           break;
15000         default:
15001           abort ();
15002         }
15003
15004       break;
15005     case mask_bd_mode:
15006       if (!need_vex || vex.length != 128)
15007         abort ();
15008       if (vex.w)
15009         oappend ("DWORD PTR ");
15010       else
15011         oappend ("BYTE PTR ");
15012       break;
15013     case mask_mode:
15014       if (!need_vex)
15015         abort ();
15016       if (vex.w)
15017         oappend ("QWORD PTR ");
15018       else
15019         oappend ("WORD PTR ");
15020       break;
15021     case v_bnd_mode:
15022     default:
15023       break;
15024     }
15025 }
15026
15027 static void
15028 OP_E_register (int bytemode, int sizeflag)
15029 {
15030   int reg = modrm.rm;
15031   const char **names;
15032
15033   USED_REX (REX_B);
15034   if ((rex & REX_B))
15035     reg += 8;
15036
15037   if ((sizeflag & SUFFIX_ALWAYS)
15038       && (bytemode == b_swap_mode
15039           || bytemode == bnd_swap_mode
15040           || bytemode == v_swap_mode))
15041     swap_operand ();
15042
15043   switch (bytemode)
15044     {
15045     case b_mode:
15046     case b_swap_mode:
15047       USED_REX (0);
15048       if (rex)
15049         names = names8rex;
15050       else
15051         names = names8;
15052       break;
15053     case w_mode:
15054       names = names16;
15055       break;
15056     case d_mode:
15057     case dw_mode:
15058     case db_mode:
15059       names = names32;
15060       break;
15061     case q_mode:
15062       names = names64;
15063       break;
15064     case m_mode:
15065     case v_bnd_mode:
15066       names = address_mode == mode_64bit ? names64 : names32;
15067       break;
15068     case bnd_mode:
15069     case bnd_swap_mode:
15070       if (reg > 0x3)
15071         {
15072           oappend ("(bad)");
15073           return;
15074         }
15075       names = names_bnd;
15076       break;
15077     case indir_v_mode:
15078       if (address_mode == mode_64bit && isa64 == intel64)
15079         {
15080           names = names64;
15081           break;
15082         }
15083       /* Fall through.  */
15084     case stack_v_mode:
15085       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15086         {
15087           names = names64;
15088           break;
15089         }
15090       bytemode = v_mode;
15091       /* Fall through.  */
15092     case v_mode:
15093     case v_swap_mode:
15094     case dq_mode:
15095     case dqb_mode:
15096     case dqd_mode:
15097     case dqw_mode:
15098       USED_REX (REX_W);
15099       if (rex & REX_W)
15100         names = names64;
15101       else
15102         {
15103           if ((sizeflag & DFLAG)
15104               || (bytemode != v_mode
15105                   && bytemode != v_swap_mode))
15106             names = names32;
15107           else
15108             names = names16;
15109           used_prefixes |= (prefixes & PREFIX_DATA);
15110         }
15111       break;
15112     case mask_bd_mode:
15113     case mask_mode:
15114       if (reg > 0x7)
15115         {
15116           oappend ("(bad)");
15117           return;
15118         }
15119       names = names_mask;
15120       break;
15121     case 0:
15122       return;
15123     default:
15124       oappend (INTERNAL_DISASSEMBLER_ERROR);
15125       return;
15126     }
15127   oappend (names[reg]);
15128 }
15129
15130 static void
15131 OP_E_memory (int bytemode, int sizeflag)
15132 {
15133   bfd_vma disp = 0;
15134   int add = (rex & REX_B) ? 8 : 0;
15135   int riprel = 0;
15136   int shift;
15137
15138   if (vex.evex)
15139     {
15140       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15141       if (vex.b
15142           && bytemode != x_mode
15143           && bytemode != xmmq_mode
15144           && bytemode != evex_half_bcst_xmmq_mode)
15145         {
15146           BadOp ();
15147           return;
15148         }
15149       switch (bytemode)
15150         {
15151         case dqw_mode:
15152         case dw_mode:
15153           shift = 1;
15154           break;
15155         case dqb_mode:
15156         case db_mode:
15157           shift = 0;
15158           break;
15159         case vex_vsib_d_w_dq_mode:
15160         case vex_vsib_d_w_d_mode:
15161         case vex_vsib_q_w_dq_mode:
15162         case vex_vsib_q_w_d_mode:
15163         case evex_x_gscat_mode:
15164         case xmm_mdq_mode:
15165           shift = vex.w ? 3 : 2;
15166           break;
15167         case x_mode:
15168         case evex_half_bcst_xmmq_mode:
15169         case xmmq_mode:
15170           if (vex.b)
15171             {
15172               shift = vex.w ? 3 : 2;
15173               break;
15174             }
15175           /* Fall through.  */
15176         case xmmqd_mode:
15177         case xmmdw_mode:
15178         case ymmq_mode:
15179         case evex_x_nobcst_mode:
15180         case x_swap_mode:
15181           switch (vex.length)
15182             {
15183             case 128:
15184               shift = 4;
15185               break;
15186             case 256:
15187               shift = 5;
15188               break;
15189             case 512:
15190               shift = 6;
15191               break;
15192             default:
15193               abort ();
15194             }
15195           break;
15196         case ymm_mode:
15197           shift = 5;
15198           break;
15199         case xmm_mode:
15200           shift = 4;
15201           break;
15202         case xmm_mq_mode:
15203         case q_mode:
15204         case q_scalar_mode:
15205         case q_swap_mode:
15206         case q_scalar_swap_mode:
15207           shift = 3;
15208           break;
15209         case dqd_mode:
15210         case xmm_md_mode:
15211         case d_mode:
15212         case d_scalar_mode:
15213         case d_swap_mode:
15214         case d_scalar_swap_mode:
15215           shift = 2;
15216           break;
15217     case w_scalar_mode:
15218         case xmm_mw_mode:
15219           shift = 1;
15220           break;
15221     case b_scalar_mode:
15222         case xmm_mb_mode:
15223           shift = 0;
15224           break;
15225         default:
15226           abort ();
15227         }
15228       /* Make necessary corrections to shift for modes that need it.
15229          For these modes we currently have shift 4, 5 or 6 depending on
15230          vex.length (it corresponds to xmmword, ymmword or zmmword
15231          operand).  We might want to make it 3, 4 or 5 (e.g. for
15232          xmmq_mode).  In case of broadcast enabled the corrections
15233          aren't needed, as element size is always 32 or 64 bits.  */
15234       if (!vex.b
15235           && (bytemode == xmmq_mode
15236               || bytemode == evex_half_bcst_xmmq_mode))
15237         shift -= 1;
15238       else if (bytemode == xmmqd_mode)
15239         shift -= 2;
15240       else if (bytemode == xmmdw_mode)
15241         shift -= 3;
15242       else if (bytemode == ymmq_mode && vex.length == 128)
15243         shift -= 1;
15244     }
15245   else
15246     shift = 0;
15247
15248   USED_REX (REX_B);
15249   if (intel_syntax)
15250     intel_operand_size (bytemode, sizeflag);
15251   append_seg ();
15252
15253   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15254     {
15255       /* 32/64 bit address mode */
15256       int havedisp;
15257       int havesib;
15258       int havebase;
15259       int haveindex;
15260       int needindex;
15261       int base, rbase;
15262       int vindex = 0;
15263       int scale = 0;
15264       int addr32flag = !((sizeflag & AFLAG)
15265                          || bytemode == v_bnd_mode
15266                          || bytemode == bnd_mode
15267                          || bytemode == bnd_swap_mode);
15268       const char **indexes64 = names64;
15269       const char **indexes32 = names32;
15270
15271       havesib = 0;
15272       havebase = 1;
15273       haveindex = 0;
15274       base = modrm.rm;
15275
15276       if (base == 4)
15277         {
15278           havesib = 1;
15279           vindex = sib.index;
15280           USED_REX (REX_X);
15281           if (rex & REX_X)
15282             vindex += 8;
15283           switch (bytemode)
15284             {
15285             case vex_vsib_d_w_dq_mode:
15286             case vex_vsib_d_w_d_mode:
15287             case vex_vsib_q_w_dq_mode:
15288             case vex_vsib_q_w_d_mode:
15289               if (!need_vex)
15290                 abort ();
15291               if (vex.evex)
15292                 {
15293                   if (!vex.v)
15294                     vindex += 16;
15295                 }
15296
15297               haveindex = 1;
15298               switch (vex.length)
15299                 {
15300                 case 128:
15301                   indexes64 = indexes32 = names_xmm;
15302                   break;
15303                 case 256:
15304                   if (!vex.w
15305                       || bytemode == vex_vsib_q_w_dq_mode
15306                       || bytemode == vex_vsib_q_w_d_mode)
15307                     indexes64 = indexes32 = names_ymm;
15308                   else
15309                     indexes64 = indexes32 = names_xmm;
15310                   break;
15311                 case 512:
15312                   if (!vex.w
15313                       || bytemode == vex_vsib_q_w_dq_mode
15314                       || bytemode == vex_vsib_q_w_d_mode)
15315                     indexes64 = indexes32 = names_zmm;
15316                   else
15317                     indexes64 = indexes32 = names_ymm;
15318                   break;
15319                 default:
15320                   abort ();
15321                 }
15322               break;
15323             default:
15324               haveindex = vindex != 4;
15325               break;
15326             }
15327           scale = sib.scale;
15328           base = sib.base;
15329           codep++;
15330         }
15331       rbase = base + add;
15332
15333       switch (modrm.mod)
15334         {
15335         case 0:
15336           if (base == 5)
15337             {
15338               havebase = 0;
15339               if (address_mode == mode_64bit && !havesib)
15340                 riprel = 1;
15341               disp = get32s ();
15342             }
15343           break;
15344         case 1:
15345           FETCH_DATA (the_info, codep + 1);
15346           disp = *codep++;
15347           if ((disp & 0x80) != 0)
15348             disp -= 0x100;
15349           if (vex.evex && shift > 0)
15350             disp <<= shift;
15351           break;
15352         case 2:
15353           disp = get32s ();
15354           break;
15355         }
15356
15357       /* In 32bit mode, we need index register to tell [offset] from
15358          [eiz*1 + offset].  */
15359       needindex = (havesib
15360                    && !havebase
15361                    && !haveindex
15362                    && address_mode == mode_32bit);
15363       havedisp = (havebase
15364                   || needindex
15365                   || (havesib && (haveindex || scale != 0)));
15366
15367       if (!intel_syntax)
15368         if (modrm.mod != 0 || base == 5)
15369           {
15370             if (havedisp || riprel)
15371               print_displacement (scratchbuf, disp);
15372             else
15373               print_operand_value (scratchbuf, 1, disp);
15374             oappend (scratchbuf);
15375             if (riprel)
15376               {
15377                 set_op (disp, 1);
15378                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15379               }
15380           }
15381
15382       if ((havebase || haveindex || riprel)
15383           && (bytemode != v_bnd_mode)
15384           && (bytemode != bnd_mode)
15385           && (bytemode != bnd_swap_mode))
15386         used_prefixes |= PREFIX_ADDR;
15387
15388       if (havedisp || (intel_syntax && riprel))
15389         {
15390           *obufp++ = open_char;
15391           if (intel_syntax && riprel)
15392             {
15393               set_op (disp, 1);
15394               oappend (!addr32flag ? "rip" : "eip");
15395             }
15396           *obufp = '\0';
15397           if (havebase)
15398             oappend (address_mode == mode_64bit && !addr32flag
15399                      ? names64[rbase] : names32[rbase]);
15400           if (havesib)
15401             {
15402               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15403                  print index to tell base + index from base.  */
15404               if (scale != 0
15405                   || needindex
15406                   || haveindex
15407                   || (havebase && base != ESP_REG_NUM))
15408                 {
15409                   if (!intel_syntax || havebase)
15410                     {
15411                       *obufp++ = separator_char;
15412                       *obufp = '\0';
15413                     }
15414                   if (haveindex)
15415                     oappend (address_mode == mode_64bit && !addr32flag
15416                              ? indexes64[vindex] : indexes32[vindex]);
15417                   else
15418                     oappend (address_mode == mode_64bit && !addr32flag
15419                              ? index64 : index32);
15420
15421                   *obufp++ = scale_char;
15422                   *obufp = '\0';
15423                   sprintf (scratchbuf, "%d", 1 << scale);
15424                   oappend (scratchbuf);
15425                 }
15426             }
15427           if (intel_syntax
15428               && (disp || modrm.mod != 0 || base == 5))
15429             {
15430               if (!havedisp || (bfd_signed_vma) disp >= 0)
15431                 {
15432                   *obufp++ = '+';
15433                   *obufp = '\0';
15434                 }
15435               else if (modrm.mod != 1 && disp != -disp)
15436                 {
15437                   *obufp++ = '-';
15438                   *obufp = '\0';
15439                   disp = - (bfd_signed_vma) disp;
15440                 }
15441
15442               if (havedisp)
15443                 print_displacement (scratchbuf, disp);
15444               else
15445                 print_operand_value (scratchbuf, 1, disp);
15446               oappend (scratchbuf);
15447             }
15448
15449           *obufp++ = close_char;
15450           *obufp = '\0';
15451         }
15452       else if (intel_syntax)
15453         {
15454           if (modrm.mod != 0 || base == 5)
15455             {
15456               if (!active_seg_prefix)
15457                 {
15458                   oappend (names_seg[ds_reg - es_reg]);
15459                   oappend (":");
15460                 }
15461               print_operand_value (scratchbuf, 1, disp);
15462               oappend (scratchbuf);
15463             }
15464         }
15465     }
15466   else
15467     {
15468       /* 16 bit address mode */
15469       used_prefixes |= prefixes & PREFIX_ADDR;
15470       switch (modrm.mod)
15471         {
15472         case 0:
15473           if (modrm.rm == 6)
15474             {
15475               disp = get16 ();
15476               if ((disp & 0x8000) != 0)
15477                 disp -= 0x10000;
15478             }
15479           break;
15480         case 1:
15481           FETCH_DATA (the_info, codep + 1);
15482           disp = *codep++;
15483           if ((disp & 0x80) != 0)
15484             disp -= 0x100;
15485           if (vex.evex && shift > 0)
15486             disp <<= shift;
15487           break;
15488         case 2:
15489           disp = get16 ();
15490           if ((disp & 0x8000) != 0)
15491             disp -= 0x10000;
15492           break;
15493         }
15494
15495       if (!intel_syntax)
15496         if (modrm.mod != 0 || modrm.rm == 6)
15497           {
15498             print_displacement (scratchbuf, disp);
15499             oappend (scratchbuf);
15500           }
15501
15502       if (modrm.mod != 0 || modrm.rm != 6)
15503         {
15504           *obufp++ = open_char;
15505           *obufp = '\0';
15506           oappend (index16[modrm.rm]);
15507           if (intel_syntax
15508               && (disp || modrm.mod != 0 || modrm.rm == 6))
15509             {
15510               if ((bfd_signed_vma) disp >= 0)
15511                 {
15512                   *obufp++ = '+';
15513                   *obufp = '\0';
15514                 }
15515               else if (modrm.mod != 1)
15516                 {
15517                   *obufp++ = '-';
15518                   *obufp = '\0';
15519                   disp = - (bfd_signed_vma) disp;
15520                 }
15521
15522               print_displacement (scratchbuf, disp);
15523               oappend (scratchbuf);
15524             }
15525
15526           *obufp++ = close_char;
15527           *obufp = '\0';
15528         }
15529       else if (intel_syntax)
15530         {
15531           if (!active_seg_prefix)
15532             {
15533               oappend (names_seg[ds_reg - es_reg]);
15534               oappend (":");
15535             }
15536           print_operand_value (scratchbuf, 1, disp & 0xffff);
15537           oappend (scratchbuf);
15538         }
15539     }
15540   if (vex.evex && vex.b
15541       && (bytemode == x_mode
15542           || bytemode == xmmq_mode
15543           || bytemode == evex_half_bcst_xmmq_mode))
15544     {
15545       if (vex.w
15546           || bytemode == xmmq_mode
15547           || bytemode == evex_half_bcst_xmmq_mode)
15548         {
15549           switch (vex.length)
15550             {
15551             case 128:
15552               oappend ("{1to2}");
15553               break;
15554             case 256:
15555               oappend ("{1to4}");
15556               break;
15557             case 512:
15558               oappend ("{1to8}");
15559               break;
15560             default:
15561               abort ();
15562             }
15563         }
15564       else
15565         {
15566           switch (vex.length)
15567             {
15568             case 128:
15569               oappend ("{1to4}");
15570               break;
15571             case 256:
15572               oappend ("{1to8}");
15573               break;
15574             case 512:
15575               oappend ("{1to16}");
15576               break;
15577             default:
15578               abort ();
15579             }
15580         }
15581     }
15582 }
15583
15584 static void
15585 OP_E (int bytemode, int sizeflag)
15586 {
15587   /* Skip mod/rm byte.  */
15588   MODRM_CHECK;
15589   codep++;
15590
15591   if (modrm.mod == 3)
15592     OP_E_register (bytemode, sizeflag);
15593   else
15594     OP_E_memory (bytemode, sizeflag);
15595 }
15596
15597 static void
15598 OP_G (int bytemode, int sizeflag)
15599 {
15600   int add = 0;
15601   USED_REX (REX_R);
15602   if (rex & REX_R)
15603     add += 8;
15604   switch (bytemode)
15605     {
15606     case b_mode:
15607       USED_REX (0);
15608       if (rex)
15609         oappend (names8rex[modrm.reg + add]);
15610       else
15611         oappend (names8[modrm.reg + add]);
15612       break;
15613     case w_mode:
15614       oappend (names16[modrm.reg + add]);
15615       break;
15616     case d_mode:
15617     case db_mode:
15618     case dw_mode:
15619       oappend (names32[modrm.reg + add]);
15620       break;
15621     case q_mode:
15622       oappend (names64[modrm.reg + add]);
15623       break;
15624     case bnd_mode:
15625       if (modrm.reg > 0x3)
15626         {
15627           oappend ("(bad)");
15628           return;
15629         }
15630       oappend (names_bnd[modrm.reg]);
15631       break;
15632     case v_mode:
15633     case dq_mode:
15634     case dqb_mode:
15635     case dqd_mode:
15636     case dqw_mode:
15637       USED_REX (REX_W);
15638       if (rex & REX_W)
15639         oappend (names64[modrm.reg + add]);
15640       else
15641         {
15642           if ((sizeflag & DFLAG) || bytemode != v_mode)
15643             oappend (names32[modrm.reg + add]);
15644           else
15645             oappend (names16[modrm.reg + add]);
15646           used_prefixes |= (prefixes & PREFIX_DATA);
15647         }
15648       break;
15649     case m_mode:
15650       if (address_mode == mode_64bit)
15651         oappend (names64[modrm.reg + add]);
15652       else
15653         oappend (names32[modrm.reg + add]);
15654       break;
15655     case mask_bd_mode:
15656     case mask_mode:
15657       if ((modrm.reg + add) > 0x7)
15658         {
15659           oappend ("(bad)");
15660           return;
15661         }
15662       oappend (names_mask[modrm.reg + add]);
15663       break;
15664     default:
15665       oappend (INTERNAL_DISASSEMBLER_ERROR);
15666       break;
15667     }
15668 }
15669
15670 static bfd_vma
15671 get64 (void)
15672 {
15673   bfd_vma x;
15674 #ifdef BFD64
15675   unsigned int a;
15676   unsigned int b;
15677
15678   FETCH_DATA (the_info, codep + 8);
15679   a = *codep++ & 0xff;
15680   a |= (*codep++ & 0xff) << 8;
15681   a |= (*codep++ & 0xff) << 16;
15682   a |= (*codep++ & 0xffu) << 24;
15683   b = *codep++ & 0xff;
15684   b |= (*codep++ & 0xff) << 8;
15685   b |= (*codep++ & 0xff) << 16;
15686   b |= (*codep++ & 0xffu) << 24;
15687   x = a + ((bfd_vma) b << 32);
15688 #else
15689   abort ();
15690   x = 0;
15691 #endif
15692   return x;
15693 }
15694
15695 static bfd_signed_vma
15696 get32 (void)
15697 {
15698   bfd_signed_vma x = 0;
15699
15700   FETCH_DATA (the_info, codep + 4);
15701   x = *codep++ & (bfd_signed_vma) 0xff;
15702   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15703   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15704   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15705   return x;
15706 }
15707
15708 static bfd_signed_vma
15709 get32s (void)
15710 {
15711   bfd_signed_vma x = 0;
15712
15713   FETCH_DATA (the_info, codep + 4);
15714   x = *codep++ & (bfd_signed_vma) 0xff;
15715   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15716   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15717   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15718
15719   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15720
15721   return x;
15722 }
15723
15724 static int
15725 get16 (void)
15726 {
15727   int x = 0;
15728
15729   FETCH_DATA (the_info, codep + 2);
15730   x = *codep++ & 0xff;
15731   x |= (*codep++ & 0xff) << 8;
15732   return x;
15733 }
15734
15735 static void
15736 set_op (bfd_vma op, int riprel)
15737 {
15738   op_index[op_ad] = op_ad;
15739   if (address_mode == mode_64bit)
15740     {
15741       op_address[op_ad] = op;
15742       op_riprel[op_ad] = riprel;
15743     }
15744   else
15745     {
15746       /* Mask to get a 32-bit address.  */
15747       op_address[op_ad] = op & 0xffffffff;
15748       op_riprel[op_ad] = riprel & 0xffffffff;
15749     }
15750 }
15751
15752 static void
15753 OP_REG (int code, int sizeflag)
15754 {
15755   const char *s;
15756   int add;
15757
15758   switch (code)
15759     {
15760     case es_reg: case ss_reg: case cs_reg:
15761     case ds_reg: case fs_reg: case gs_reg:
15762       oappend (names_seg[code - es_reg]);
15763       return;
15764     }
15765
15766   USED_REX (REX_B);
15767   if (rex & REX_B)
15768     add = 8;
15769   else
15770     add = 0;
15771
15772   switch (code)
15773     {
15774     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15775     case sp_reg: case bp_reg: case si_reg: case di_reg:
15776       s = names16[code - ax_reg + add];
15777       break;
15778     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15779     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15780       USED_REX (0);
15781       if (rex)
15782         s = names8rex[code - al_reg + add];
15783       else
15784         s = names8[code - al_reg];
15785       break;
15786     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15787     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15788       if (address_mode == mode_64bit
15789           && ((sizeflag & DFLAG) || (rex & REX_W)))
15790         {
15791           s = names64[code - rAX_reg + add];
15792           break;
15793         }
15794       code += eAX_reg - rAX_reg;
15795       /* Fall through.  */
15796     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15797     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15798       USED_REX (REX_W);
15799       if (rex & REX_W)
15800         s = names64[code - eAX_reg + add];
15801       else
15802         {
15803           if (sizeflag & DFLAG)
15804             s = names32[code - eAX_reg + add];
15805           else
15806             s = names16[code - eAX_reg + add];
15807           used_prefixes |= (prefixes & PREFIX_DATA);
15808         }
15809       break;
15810     default:
15811       s = INTERNAL_DISASSEMBLER_ERROR;
15812       break;
15813     }
15814   oappend (s);
15815 }
15816
15817 static void
15818 OP_IMREG (int code, int sizeflag)
15819 {
15820   const char *s;
15821
15822   switch (code)
15823     {
15824     case indir_dx_reg:
15825       if (intel_syntax)
15826         s = "dx";
15827       else
15828         s = "(%dx)";
15829       break;
15830     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15831     case sp_reg: case bp_reg: case si_reg: case di_reg:
15832       s = names16[code - ax_reg];
15833       break;
15834     case es_reg: case ss_reg: case cs_reg:
15835     case ds_reg: case fs_reg: case gs_reg:
15836       s = names_seg[code - es_reg];
15837       break;
15838     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15839     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15840       USED_REX (0);
15841       if (rex)
15842         s = names8rex[code - al_reg];
15843       else
15844         s = names8[code - al_reg];
15845       break;
15846     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15847     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15848       USED_REX (REX_W);
15849       if (rex & REX_W)
15850         s = names64[code - eAX_reg];
15851       else
15852         {
15853           if (sizeflag & DFLAG)
15854             s = names32[code - eAX_reg];
15855           else
15856             s = names16[code - eAX_reg];
15857           used_prefixes |= (prefixes & PREFIX_DATA);
15858         }
15859       break;
15860     case z_mode_ax_reg:
15861       if ((rex & REX_W) || (sizeflag & DFLAG))
15862         s = *names32;
15863       else
15864         s = *names16;
15865       if (!(rex & REX_W))
15866         used_prefixes |= (prefixes & PREFIX_DATA);
15867       break;
15868     default:
15869       s = INTERNAL_DISASSEMBLER_ERROR;
15870       break;
15871     }
15872   oappend (s);
15873 }
15874
15875 static void
15876 OP_I (int bytemode, int sizeflag)
15877 {
15878   bfd_signed_vma op;
15879   bfd_signed_vma mask = -1;
15880
15881   switch (bytemode)
15882     {
15883     case b_mode:
15884       FETCH_DATA (the_info, codep + 1);
15885       op = *codep++;
15886       mask = 0xff;
15887       break;
15888     case q_mode:
15889       if (address_mode == mode_64bit)
15890         {
15891           op = get32s ();
15892           break;
15893         }
15894       /* Fall through.  */
15895     case v_mode:
15896       USED_REX (REX_W);
15897       if (rex & REX_W)
15898         op = get32s ();
15899       else
15900         {
15901           if (sizeflag & DFLAG)
15902             {
15903               op = get32 ();
15904               mask = 0xffffffff;
15905             }
15906           else
15907             {
15908               op = get16 ();
15909               mask = 0xfffff;
15910             }
15911           used_prefixes |= (prefixes & PREFIX_DATA);
15912         }
15913       break;
15914     case w_mode:
15915       mask = 0xfffff;
15916       op = get16 ();
15917       break;
15918     case const_1_mode:
15919       if (intel_syntax)
15920         oappend ("1");
15921       return;
15922     default:
15923       oappend (INTERNAL_DISASSEMBLER_ERROR);
15924       return;
15925     }
15926
15927   op &= mask;
15928   scratchbuf[0] = '$';
15929   print_operand_value (scratchbuf + 1, 1, op);
15930   oappend_maybe_intel (scratchbuf);
15931   scratchbuf[0] = '\0';
15932 }
15933
15934 static void
15935 OP_I64 (int bytemode, int sizeflag)
15936 {
15937   bfd_signed_vma op;
15938   bfd_signed_vma mask = -1;
15939
15940   if (address_mode != mode_64bit)
15941     {
15942       OP_I (bytemode, sizeflag);
15943       return;
15944     }
15945
15946   switch (bytemode)
15947     {
15948     case b_mode:
15949       FETCH_DATA (the_info, codep + 1);
15950       op = *codep++;
15951       mask = 0xff;
15952       break;
15953     case v_mode:
15954       USED_REX (REX_W);
15955       if (rex & REX_W)
15956         op = get64 ();
15957       else
15958         {
15959           if (sizeflag & DFLAG)
15960             {
15961               op = get32 ();
15962               mask = 0xffffffff;
15963             }
15964           else
15965             {
15966               op = get16 ();
15967               mask = 0xfffff;
15968             }
15969           used_prefixes |= (prefixes & PREFIX_DATA);
15970         }
15971       break;
15972     case w_mode:
15973       mask = 0xfffff;
15974       op = get16 ();
15975       break;
15976     default:
15977       oappend (INTERNAL_DISASSEMBLER_ERROR);
15978       return;
15979     }
15980
15981   op &= mask;
15982   scratchbuf[0] = '$';
15983   print_operand_value (scratchbuf + 1, 1, op);
15984   oappend_maybe_intel (scratchbuf);
15985   scratchbuf[0] = '\0';
15986 }
15987
15988 static void
15989 OP_sI (int bytemode, int sizeflag)
15990 {
15991   bfd_signed_vma op;
15992
15993   switch (bytemode)
15994     {
15995     case b_mode:
15996     case b_T_mode:
15997       FETCH_DATA (the_info, codep + 1);
15998       op = *codep++;
15999       if ((op & 0x80) != 0)
16000         op -= 0x100;
16001       if (bytemode == b_T_mode)
16002         {
16003           if (address_mode != mode_64bit
16004               || !((sizeflag & DFLAG) || (rex & REX_W)))
16005             {
16006               /* The operand-size prefix is overridden by a REX prefix.  */
16007               if ((sizeflag & DFLAG) || (rex & REX_W))
16008                 op &= 0xffffffff;
16009               else
16010                 op &= 0xffff;
16011           }
16012         }
16013       else
16014         {
16015           if (!(rex & REX_W))
16016             {
16017               if (sizeflag & DFLAG)
16018                 op &= 0xffffffff;
16019               else
16020                 op &= 0xffff;
16021             }
16022         }
16023       break;
16024     case v_mode:
16025       /* The operand-size prefix is overridden by a REX prefix.  */
16026       if ((sizeflag & DFLAG) || (rex & REX_W))
16027         op = get32s ();
16028       else
16029         op = get16 ();
16030       break;
16031     default:
16032       oappend (INTERNAL_DISASSEMBLER_ERROR);
16033       return;
16034     }
16035
16036   scratchbuf[0] = '$';
16037   print_operand_value (scratchbuf + 1, 1, op);
16038   oappend_maybe_intel (scratchbuf);
16039 }
16040
16041 static void
16042 OP_J (int bytemode, int sizeflag)
16043 {
16044   bfd_vma disp;
16045   bfd_vma mask = -1;
16046   bfd_vma segment = 0;
16047
16048   switch (bytemode)
16049     {
16050     case b_mode:
16051       FETCH_DATA (the_info, codep + 1);
16052       disp = *codep++;
16053       if ((disp & 0x80) != 0)
16054         disp -= 0x100;
16055       break;
16056     case v_mode:
16057       if (isa64 == amd64)
16058         USED_REX (REX_W);
16059       if ((sizeflag & DFLAG)
16060           || (address_mode == mode_64bit
16061               && (isa64 != amd64 || (rex & REX_W))))
16062         disp = get32s ();
16063       else
16064         {
16065           disp = get16 ();
16066           if ((disp & 0x8000) != 0)
16067             disp -= 0x10000;
16068           /* In 16bit mode, address is wrapped around at 64k within
16069              the same segment.  Otherwise, a data16 prefix on a jump
16070              instruction means that the pc is masked to 16 bits after
16071              the displacement is added!  */
16072           mask = 0xffff;
16073           if ((prefixes & PREFIX_DATA) == 0)
16074             segment = ((start_pc + (codep - start_codep))
16075                        & ~((bfd_vma) 0xffff));
16076         }
16077       if (address_mode != mode_64bit
16078           || (isa64 == amd64 && !(rex & REX_W)))
16079         used_prefixes |= (prefixes & PREFIX_DATA);
16080       break;
16081     default:
16082       oappend (INTERNAL_DISASSEMBLER_ERROR);
16083       return;
16084     }
16085   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16086   set_op (disp, 0);
16087   print_operand_value (scratchbuf, 1, disp);
16088   oappend (scratchbuf);
16089 }
16090
16091 static void
16092 OP_SEG (int bytemode, int sizeflag)
16093 {
16094   if (bytemode == w_mode)
16095     oappend (names_seg[modrm.reg]);
16096   else
16097     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16098 }
16099
16100 static void
16101 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16102 {
16103   int seg, offset;
16104
16105   if (sizeflag & DFLAG)
16106     {
16107       offset = get32 ();
16108       seg = get16 ();
16109     }
16110   else
16111     {
16112       offset = get16 ();
16113       seg = get16 ();
16114     }
16115   used_prefixes |= (prefixes & PREFIX_DATA);
16116   if (intel_syntax)
16117     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16118   else
16119     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16120   oappend (scratchbuf);
16121 }
16122
16123 static void
16124 OP_OFF (int bytemode, int sizeflag)
16125 {
16126   bfd_vma off;
16127
16128   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16129     intel_operand_size (bytemode, sizeflag);
16130   append_seg ();
16131
16132   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16133     off = get32 ();
16134   else
16135     off = get16 ();
16136
16137   if (intel_syntax)
16138     {
16139       if (!active_seg_prefix)
16140         {
16141           oappend (names_seg[ds_reg - es_reg]);
16142           oappend (":");
16143         }
16144     }
16145   print_operand_value (scratchbuf, 1, off);
16146   oappend (scratchbuf);
16147 }
16148
16149 static void
16150 OP_OFF64 (int bytemode, int sizeflag)
16151 {
16152   bfd_vma off;
16153
16154   if (address_mode != mode_64bit
16155       || (prefixes & PREFIX_ADDR))
16156     {
16157       OP_OFF (bytemode, sizeflag);
16158       return;
16159     }
16160
16161   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16162     intel_operand_size (bytemode, sizeflag);
16163   append_seg ();
16164
16165   off = get64 ();
16166
16167   if (intel_syntax)
16168     {
16169       if (!active_seg_prefix)
16170         {
16171           oappend (names_seg[ds_reg - es_reg]);
16172           oappend (":");
16173         }
16174     }
16175   print_operand_value (scratchbuf, 1, off);
16176   oappend (scratchbuf);
16177 }
16178
16179 static void
16180 ptr_reg (int code, int sizeflag)
16181 {
16182   const char *s;
16183
16184   *obufp++ = open_char;
16185   used_prefixes |= (prefixes & PREFIX_ADDR);
16186   if (address_mode == mode_64bit)
16187     {
16188       if (!(sizeflag & AFLAG))
16189         s = names32[code - eAX_reg];
16190       else
16191         s = names64[code - eAX_reg];
16192     }
16193   else if (sizeflag & AFLAG)
16194     s = names32[code - eAX_reg];
16195   else
16196     s = names16[code - eAX_reg];
16197   oappend (s);
16198   *obufp++ = close_char;
16199   *obufp = 0;
16200 }
16201
16202 static void
16203 OP_ESreg (int code, int sizeflag)
16204 {
16205   if (intel_syntax)
16206     {
16207       switch (codep[-1])
16208         {
16209         case 0x6d:      /* insw/insl */
16210           intel_operand_size (z_mode, sizeflag);
16211           break;
16212         case 0xa5:      /* movsw/movsl/movsq */
16213         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16214         case 0xab:      /* stosw/stosl */
16215         case 0xaf:      /* scasw/scasl */
16216           intel_operand_size (v_mode, sizeflag);
16217           break;
16218         default:
16219           intel_operand_size (b_mode, sizeflag);
16220         }
16221     }
16222   oappend_maybe_intel ("%es:");
16223   ptr_reg (code, sizeflag);
16224 }
16225
16226 static void
16227 OP_DSreg (int code, int sizeflag)
16228 {
16229   if (intel_syntax)
16230     {
16231       switch (codep[-1])
16232         {
16233         case 0x6f:      /* outsw/outsl */
16234           intel_operand_size (z_mode, sizeflag);
16235           break;
16236         case 0xa5:      /* movsw/movsl/movsq */
16237         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16238         case 0xad:      /* lodsw/lodsl/lodsq */
16239           intel_operand_size (v_mode, sizeflag);
16240           break;
16241         default:
16242           intel_operand_size (b_mode, sizeflag);
16243         }
16244     }
16245   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16246      default segment register DS is printed.  */
16247   if (!active_seg_prefix)
16248     active_seg_prefix = PREFIX_DS;
16249   append_seg ();
16250   ptr_reg (code, sizeflag);
16251 }
16252
16253 static void
16254 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16255 {
16256   int add;
16257   if (rex & REX_R)
16258     {
16259       USED_REX (REX_R);
16260       add = 8;
16261     }
16262   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16263     {
16264       all_prefixes[last_lock_prefix] = 0;
16265       used_prefixes |= PREFIX_LOCK;
16266       add = 8;
16267     }
16268   else
16269     add = 0;
16270   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16271   oappend_maybe_intel (scratchbuf);
16272 }
16273
16274 static void
16275 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16276 {
16277   int add;
16278   USED_REX (REX_R);
16279   if (rex & REX_R)
16280     add = 8;
16281   else
16282     add = 0;
16283   if (intel_syntax)
16284     sprintf (scratchbuf, "db%d", modrm.reg + add);
16285   else
16286     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16287   oappend (scratchbuf);
16288 }
16289
16290 static void
16291 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16292 {
16293   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16294   oappend_maybe_intel (scratchbuf);
16295 }
16296
16297 static void
16298 OP_R (int bytemode, int sizeflag)
16299 {
16300   /* Skip mod/rm byte.  */
16301   MODRM_CHECK;
16302   codep++;
16303   OP_E_register (bytemode, sizeflag);
16304 }
16305
16306 static void
16307 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16308 {
16309   int reg = modrm.reg;
16310   const char **names;
16311
16312   used_prefixes |= (prefixes & PREFIX_DATA);
16313   if (prefixes & PREFIX_DATA)
16314     {
16315       names = names_xmm;
16316       USED_REX (REX_R);
16317       if (rex & REX_R)
16318         reg += 8;
16319     }
16320   else
16321     names = names_mm;
16322   oappend (names[reg]);
16323 }
16324
16325 static void
16326 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16327 {
16328   int reg = modrm.reg;
16329   const char **names;
16330
16331   USED_REX (REX_R);
16332   if (rex & REX_R)
16333     reg += 8;
16334   if (vex.evex)
16335     {
16336       if (!vex.r)
16337         reg += 16;
16338     }
16339
16340   if (need_vex
16341       && bytemode != xmm_mode
16342       && bytemode != xmmq_mode
16343       && bytemode != evex_half_bcst_xmmq_mode
16344       && bytemode != ymm_mode
16345       && bytemode != scalar_mode)
16346     {
16347       switch (vex.length)
16348         {
16349         case 128:
16350           names = names_xmm;
16351           break;
16352         case 256:
16353           if (vex.w
16354               || (bytemode != vex_vsib_q_w_dq_mode
16355                   && bytemode != vex_vsib_q_w_d_mode))
16356             names = names_ymm;
16357           else
16358             names = names_xmm;
16359           break;
16360         case 512:
16361           names = names_zmm;
16362           break;
16363         default:
16364           abort ();
16365         }
16366     }
16367   else if (bytemode == xmmq_mode
16368            || bytemode == evex_half_bcst_xmmq_mode)
16369     {
16370       switch (vex.length)
16371         {
16372         case 128:
16373         case 256:
16374           names = names_xmm;
16375           break;
16376         case 512:
16377           names = names_ymm;
16378           break;
16379         default:
16380           abort ();
16381         }
16382     }
16383   else if (bytemode == ymm_mode)
16384     names = names_ymm;
16385   else
16386     names = names_xmm;
16387   oappend (names[reg]);
16388 }
16389
16390 static void
16391 OP_EM (int bytemode, int sizeflag)
16392 {
16393   int reg;
16394   const char **names;
16395
16396   if (modrm.mod != 3)
16397     {
16398       if (intel_syntax
16399           && (bytemode == v_mode || bytemode == v_swap_mode))
16400         {
16401           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16402           used_prefixes |= (prefixes & PREFIX_DATA);
16403         }
16404       OP_E (bytemode, sizeflag);
16405       return;
16406     }
16407
16408   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16409     swap_operand ();
16410
16411   /* Skip mod/rm byte.  */
16412   MODRM_CHECK;
16413   codep++;
16414   used_prefixes |= (prefixes & PREFIX_DATA);
16415   reg = modrm.rm;
16416   if (prefixes & PREFIX_DATA)
16417     {
16418       names = names_xmm;
16419       USED_REX (REX_B);
16420       if (rex & REX_B)
16421         reg += 8;
16422     }
16423   else
16424     names = names_mm;
16425   oappend (names[reg]);
16426 }
16427
16428 /* cvt* are the only instructions in sse2 which have
16429    both SSE and MMX operands and also have 0x66 prefix
16430    in their opcode. 0x66 was originally used to differentiate
16431    between SSE and MMX instruction(operands). So we have to handle the
16432    cvt* separately using OP_EMC and OP_MXC */
16433 static void
16434 OP_EMC (int bytemode, int sizeflag)
16435 {
16436   if (modrm.mod != 3)
16437     {
16438       if (intel_syntax && bytemode == v_mode)
16439         {
16440           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16441           used_prefixes |= (prefixes & PREFIX_DATA);
16442         }
16443       OP_E (bytemode, sizeflag);
16444       return;
16445     }
16446
16447   /* Skip mod/rm byte.  */
16448   MODRM_CHECK;
16449   codep++;
16450   used_prefixes |= (prefixes & PREFIX_DATA);
16451   oappend (names_mm[modrm.rm]);
16452 }
16453
16454 static void
16455 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16456 {
16457   used_prefixes |= (prefixes & PREFIX_DATA);
16458   oappend (names_mm[modrm.reg]);
16459 }
16460
16461 static void
16462 OP_EX (int bytemode, int sizeflag)
16463 {
16464   int reg;
16465   const char **names;
16466
16467   /* Skip mod/rm byte.  */
16468   MODRM_CHECK;
16469   codep++;
16470
16471   if (modrm.mod != 3)
16472     {
16473       OP_E_memory (bytemode, sizeflag);
16474       return;
16475     }
16476
16477   reg = modrm.rm;
16478   USED_REX (REX_B);
16479   if (rex & REX_B)
16480     reg += 8;
16481   if (vex.evex)
16482     {
16483       USED_REX (REX_X);
16484       if ((rex & REX_X))
16485         reg += 16;
16486     }
16487
16488   if ((sizeflag & SUFFIX_ALWAYS)
16489       && (bytemode == x_swap_mode
16490           || bytemode == d_swap_mode
16491           || bytemode == d_scalar_swap_mode
16492           || bytemode == q_swap_mode
16493           || bytemode == q_scalar_swap_mode))
16494     swap_operand ();
16495
16496   if (need_vex
16497       && bytemode != xmm_mode
16498       && bytemode != xmmdw_mode
16499       && bytemode != xmmqd_mode
16500       && bytemode != xmm_mb_mode
16501       && bytemode != xmm_mw_mode
16502       && bytemode != xmm_md_mode
16503       && bytemode != xmm_mq_mode
16504       && bytemode != xmm_mdq_mode
16505       && bytemode != xmmq_mode
16506       && bytemode != evex_half_bcst_xmmq_mode
16507       && bytemode != ymm_mode
16508       && bytemode != d_scalar_mode
16509       && bytemode != d_scalar_swap_mode
16510       && bytemode != q_scalar_mode
16511       && bytemode != q_scalar_swap_mode
16512       && bytemode != vex_scalar_w_dq_mode)
16513     {
16514       switch (vex.length)
16515         {
16516         case 128:
16517           names = names_xmm;
16518           break;
16519         case 256:
16520           names = names_ymm;
16521           break;
16522         case 512:
16523           names = names_zmm;
16524           break;
16525         default:
16526           abort ();
16527         }
16528     }
16529   else if (bytemode == xmmq_mode
16530            || bytemode == evex_half_bcst_xmmq_mode)
16531     {
16532       switch (vex.length)
16533         {
16534         case 128:
16535         case 256:
16536           names = names_xmm;
16537           break;
16538         case 512:
16539           names = names_ymm;
16540           break;
16541         default:
16542           abort ();
16543         }
16544     }
16545   else if (bytemode == ymm_mode)
16546     names = names_ymm;
16547   else
16548     names = names_xmm;
16549   oappend (names[reg]);
16550 }
16551
16552 static void
16553 OP_MS (int bytemode, int sizeflag)
16554 {
16555   if (modrm.mod == 3)
16556     OP_EM (bytemode, sizeflag);
16557   else
16558     BadOp ();
16559 }
16560
16561 static void
16562 OP_XS (int bytemode, int sizeflag)
16563 {
16564   if (modrm.mod == 3)
16565     OP_EX (bytemode, sizeflag);
16566   else
16567     BadOp ();
16568 }
16569
16570 static void
16571 OP_M (int bytemode, int sizeflag)
16572 {
16573   if (modrm.mod == 3)
16574     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16575     BadOp ();
16576   else
16577     OP_E (bytemode, sizeflag);
16578 }
16579
16580 static void
16581 OP_0f07 (int bytemode, int sizeflag)
16582 {
16583   if (modrm.mod != 3 || modrm.rm != 0)
16584     BadOp ();
16585   else
16586     OP_E (bytemode, sizeflag);
16587 }
16588
16589 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16590    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16591
16592 static void
16593 NOP_Fixup1 (int bytemode, int sizeflag)
16594 {
16595   if ((prefixes & PREFIX_DATA) != 0
16596       || (rex != 0
16597           && rex != 0x48
16598           && address_mode == mode_64bit))
16599     OP_REG (bytemode, sizeflag);
16600   else
16601     strcpy (obuf, "nop");
16602 }
16603
16604 static void
16605 NOP_Fixup2 (int bytemode, int sizeflag)
16606 {
16607   if ((prefixes & PREFIX_DATA) != 0
16608       || (rex != 0
16609           && rex != 0x48
16610           && address_mode == mode_64bit))
16611     OP_IMREG (bytemode, sizeflag);
16612 }
16613
16614 static const char *const Suffix3DNow[] = {
16615 /* 00 */        NULL,           NULL,           NULL,           NULL,
16616 /* 04 */        NULL,           NULL,           NULL,           NULL,
16617 /* 08 */        NULL,           NULL,           NULL,           NULL,
16618 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16619 /* 10 */        NULL,           NULL,           NULL,           NULL,
16620 /* 14 */        NULL,           NULL,           NULL,           NULL,
16621 /* 18 */        NULL,           NULL,           NULL,           NULL,
16622 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16623 /* 20 */        NULL,           NULL,           NULL,           NULL,
16624 /* 24 */        NULL,           NULL,           NULL,           NULL,
16625 /* 28 */        NULL,           NULL,           NULL,           NULL,
16626 /* 2C */        NULL,           NULL,           NULL,           NULL,
16627 /* 30 */        NULL,           NULL,           NULL,           NULL,
16628 /* 34 */        NULL,           NULL,           NULL,           NULL,
16629 /* 38 */        NULL,           NULL,           NULL,           NULL,
16630 /* 3C */        NULL,           NULL,           NULL,           NULL,
16631 /* 40 */        NULL,           NULL,           NULL,           NULL,
16632 /* 44 */        NULL,           NULL,           NULL,           NULL,
16633 /* 48 */        NULL,           NULL,           NULL,           NULL,
16634 /* 4C */        NULL,           NULL,           NULL,           NULL,
16635 /* 50 */        NULL,           NULL,           NULL,           NULL,
16636 /* 54 */        NULL,           NULL,           NULL,           NULL,
16637 /* 58 */        NULL,           NULL,           NULL,           NULL,
16638 /* 5C */        NULL,           NULL,           NULL,           NULL,
16639 /* 60 */        NULL,           NULL,           NULL,           NULL,
16640 /* 64 */        NULL,           NULL,           NULL,           NULL,
16641 /* 68 */        NULL,           NULL,           NULL,           NULL,
16642 /* 6C */        NULL,           NULL,           NULL,           NULL,
16643 /* 70 */        NULL,           NULL,           NULL,           NULL,
16644 /* 74 */        NULL,           NULL,           NULL,           NULL,
16645 /* 78 */        NULL,           NULL,           NULL,           NULL,
16646 /* 7C */        NULL,           NULL,           NULL,           NULL,
16647 /* 80 */        NULL,           NULL,           NULL,           NULL,
16648 /* 84 */        NULL,           NULL,           NULL,           NULL,
16649 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16650 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16651 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16652 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16653 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16654 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16655 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16656 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16657 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16658 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16659 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16660 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16661 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16662 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16663 /* C0 */        NULL,           NULL,           NULL,           NULL,
16664 /* C4 */        NULL,           NULL,           NULL,           NULL,
16665 /* C8 */        NULL,           NULL,           NULL,           NULL,
16666 /* CC */        NULL,           NULL,           NULL,           NULL,
16667 /* D0 */        NULL,           NULL,           NULL,           NULL,
16668 /* D4 */        NULL,           NULL,           NULL,           NULL,
16669 /* D8 */        NULL,           NULL,           NULL,           NULL,
16670 /* DC */        NULL,           NULL,           NULL,           NULL,
16671 /* E0 */        NULL,           NULL,           NULL,           NULL,
16672 /* E4 */        NULL,           NULL,           NULL,           NULL,
16673 /* E8 */        NULL,           NULL,           NULL,           NULL,
16674 /* EC */        NULL,           NULL,           NULL,           NULL,
16675 /* F0 */        NULL,           NULL,           NULL,           NULL,
16676 /* F4 */        NULL,           NULL,           NULL,           NULL,
16677 /* F8 */        NULL,           NULL,           NULL,           NULL,
16678 /* FC */        NULL,           NULL,           NULL,           NULL,
16679 };
16680
16681 static void
16682 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16683 {
16684   const char *mnemonic;
16685
16686   FETCH_DATA (the_info, codep + 1);
16687   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16688      place where an 8-bit immediate would normally go.  ie. the last
16689      byte of the instruction.  */
16690   obufp = mnemonicendp;
16691   mnemonic = Suffix3DNow[*codep++ & 0xff];
16692   if (mnemonic)
16693     oappend (mnemonic);
16694   else
16695     {
16696       /* Since a variable sized modrm/sib chunk is between the start
16697          of the opcode (0x0f0f) and the opcode suffix, we need to do
16698          all the modrm processing first, and don't know until now that
16699          we have a bad opcode.  This necessitates some cleaning up.  */
16700       op_out[0][0] = '\0';
16701       op_out[1][0] = '\0';
16702       BadOp ();
16703     }
16704   mnemonicendp = obufp;
16705 }
16706
16707 static struct op simd_cmp_op[] =
16708 {
16709   { STRING_COMMA_LEN ("eq") },
16710   { STRING_COMMA_LEN ("lt") },
16711   { STRING_COMMA_LEN ("le") },
16712   { STRING_COMMA_LEN ("unord") },
16713   { STRING_COMMA_LEN ("neq") },
16714   { STRING_COMMA_LEN ("nlt") },
16715   { STRING_COMMA_LEN ("nle") },
16716   { STRING_COMMA_LEN ("ord") }
16717 };
16718
16719 static void
16720 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16721 {
16722   unsigned int cmp_type;
16723
16724   FETCH_DATA (the_info, codep + 1);
16725   cmp_type = *codep++ & 0xff;
16726   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16727     {
16728       char suffix [3];
16729       char *p = mnemonicendp - 2;
16730       suffix[0] = p[0];
16731       suffix[1] = p[1];
16732       suffix[2] = '\0';
16733       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16734       mnemonicendp += simd_cmp_op[cmp_type].len;
16735     }
16736   else
16737     {
16738       /* We have a reserved extension byte.  Output it directly.  */
16739       scratchbuf[0] = '$';
16740       print_operand_value (scratchbuf + 1, 1, cmp_type);
16741       oappend_maybe_intel (scratchbuf);
16742       scratchbuf[0] = '\0';
16743     }
16744 }
16745
16746 static void
16747 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16748           int sizeflag ATTRIBUTE_UNUSED)
16749 {
16750   /* mwaitx %eax,%ecx,%ebx */
16751   if (!intel_syntax)
16752     {
16753       const char **names = (address_mode == mode_64bit
16754                             ? names64 : names32);
16755       strcpy (op_out[0], names[0]);
16756       strcpy (op_out[1], names[1]);
16757       strcpy (op_out[2], names[3]);
16758       two_source_ops = 1;
16759     }
16760   /* Skip mod/rm byte.  */
16761   MODRM_CHECK;
16762   codep++;
16763 }
16764
16765 static void
16766 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16767           int sizeflag ATTRIBUTE_UNUSED)
16768 {
16769   /* mwait %eax,%ecx  */
16770   if (!intel_syntax)
16771     {
16772       const char **names = (address_mode == mode_64bit
16773                             ? names64 : names32);
16774       strcpy (op_out[0], names[0]);
16775       strcpy (op_out[1], names[1]);
16776       two_source_ops = 1;
16777     }
16778   /* Skip mod/rm byte.  */
16779   MODRM_CHECK;
16780   codep++;
16781 }
16782
16783 static void
16784 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16785             int sizeflag ATTRIBUTE_UNUSED)
16786 {
16787   /* monitor %eax,%ecx,%edx"  */
16788   if (!intel_syntax)
16789     {
16790       const char **op1_names;
16791       const char **names = (address_mode == mode_64bit
16792                             ? names64 : names32);
16793
16794       if (!(prefixes & PREFIX_ADDR))
16795         op1_names = (address_mode == mode_16bit
16796                      ? names16 : names);
16797       else
16798         {
16799           /* Remove "addr16/addr32".  */
16800           all_prefixes[last_addr_prefix] = 0;
16801           op1_names = (address_mode != mode_32bit
16802                        ? names32 : names16);
16803           used_prefixes |= PREFIX_ADDR;
16804         }
16805       strcpy (op_out[0], op1_names[0]);
16806       strcpy (op_out[1], names[1]);
16807       strcpy (op_out[2], names[2]);
16808       two_source_ops = 1;
16809     }
16810   /* Skip mod/rm byte.  */
16811   MODRM_CHECK;
16812   codep++;
16813 }
16814
16815 static void
16816 BadOp (void)
16817 {
16818   /* Throw away prefixes and 1st. opcode byte.  */
16819   codep = insn_codep + 1;
16820   oappend ("(bad)");
16821 }
16822
16823 static void
16824 REP_Fixup (int bytemode, int sizeflag)
16825 {
16826   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16827      lods and stos.  */
16828   if (prefixes & PREFIX_REPZ)
16829     all_prefixes[last_repz_prefix] = REP_PREFIX;
16830
16831   switch (bytemode)
16832     {
16833     case al_reg:
16834     case eAX_reg:
16835     case indir_dx_reg:
16836       OP_IMREG (bytemode, sizeflag);
16837       break;
16838     case eDI_reg:
16839       OP_ESreg (bytemode, sizeflag);
16840       break;
16841     case eSI_reg:
16842       OP_DSreg (bytemode, sizeflag);
16843       break;
16844     default:
16845       abort ();
16846       break;
16847     }
16848 }
16849
16850 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16851    "bnd".  */
16852
16853 static void
16854 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16855 {
16856   if (prefixes & PREFIX_REPNZ)
16857     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16858 }
16859
16860 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16861    "notrack".  */
16862
16863 static void
16864 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16865                int sizeflag ATTRIBUTE_UNUSED)
16866 {
16867   if (active_seg_prefix == PREFIX_DS
16868       && (address_mode != mode_64bit || last_data_prefix < 0))
16869     {
16870       /* NOTRACK prefix is only valid on indirect branch instructions.
16871          NB: DATA prefix is unsupported for Intel64.  */
16872       active_seg_prefix = 0;
16873       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16874     }
16875 }
16876
16877 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16878    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16879  */
16880
16881 static void
16882 HLE_Fixup1 (int bytemode, int sizeflag)
16883 {
16884   if (modrm.mod != 3
16885       && (prefixes & PREFIX_LOCK) != 0)
16886     {
16887       if (prefixes & PREFIX_REPZ)
16888         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16889       if (prefixes & PREFIX_REPNZ)
16890         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16891     }
16892
16893   OP_E (bytemode, sizeflag);
16894 }
16895
16896 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16897    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16898  */
16899
16900 static void
16901 HLE_Fixup2 (int bytemode, int sizeflag)
16902 {
16903   if (modrm.mod != 3)
16904     {
16905       if (prefixes & PREFIX_REPZ)
16906         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16907       if (prefixes & PREFIX_REPNZ)
16908         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16909     }
16910
16911   OP_E (bytemode, sizeflag);
16912 }
16913
16914 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16915    "xrelease" for memory operand.  No check for LOCK prefix.   */
16916
16917 static void
16918 HLE_Fixup3 (int bytemode, int sizeflag)
16919 {
16920   if (modrm.mod != 3
16921       && last_repz_prefix > last_repnz_prefix
16922       && (prefixes & PREFIX_REPZ) != 0)
16923     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16924
16925   OP_E (bytemode, sizeflag);
16926 }
16927
16928 static void
16929 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16930 {
16931   USED_REX (REX_W);
16932   if (rex & REX_W)
16933     {
16934       /* Change cmpxchg8b to cmpxchg16b.  */
16935       char *p = mnemonicendp - 2;
16936       mnemonicendp = stpcpy (p, "16b");
16937       bytemode = o_mode;
16938     }
16939   else if ((prefixes & PREFIX_LOCK) != 0)
16940     {
16941       if (prefixes & PREFIX_REPZ)
16942         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16943       if (prefixes & PREFIX_REPNZ)
16944         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16945     }
16946
16947   OP_M (bytemode, sizeflag);
16948 }
16949
16950 static void
16951 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16952 {
16953   const char **names;
16954
16955   if (need_vex)
16956     {
16957       switch (vex.length)
16958         {
16959         case 128:
16960           names = names_xmm;
16961           break;
16962         case 256:
16963           names = names_ymm;
16964           break;
16965         default:
16966           abort ();
16967         }
16968     }
16969   else
16970     names = names_xmm;
16971   oappend (names[reg]);
16972 }
16973
16974 static void
16975 CRC32_Fixup (int bytemode, int sizeflag)
16976 {
16977   /* Add proper suffix to "crc32".  */
16978   char *p = mnemonicendp;
16979
16980   switch (bytemode)
16981     {
16982     case b_mode:
16983       if (intel_syntax)
16984         goto skip;
16985
16986       *p++ = 'b';
16987       break;
16988     case v_mode:
16989       if (intel_syntax)
16990         goto skip;
16991
16992       USED_REX (REX_W);
16993       if (rex & REX_W)
16994         *p++ = 'q';
16995       else
16996         {
16997           if (sizeflag & DFLAG)
16998             *p++ = 'l';
16999           else
17000             *p++ = 'w';
17001           used_prefixes |= (prefixes & PREFIX_DATA);
17002         }
17003       break;
17004     default:
17005       oappend (INTERNAL_DISASSEMBLER_ERROR);
17006       break;
17007     }
17008   mnemonicendp = p;
17009   *p = '\0';
17010
17011 skip:
17012   if (modrm.mod == 3)
17013     {
17014       int add;
17015
17016       /* Skip mod/rm byte.  */
17017       MODRM_CHECK;
17018       codep++;
17019
17020       USED_REX (REX_B);
17021       add = (rex & REX_B) ? 8 : 0;
17022       if (bytemode == b_mode)
17023         {
17024           USED_REX (0);
17025           if (rex)
17026             oappend (names8rex[modrm.rm + add]);
17027           else
17028             oappend (names8[modrm.rm + add]);
17029         }
17030       else
17031         {
17032           USED_REX (REX_W);
17033           if (rex & REX_W)
17034             oappend (names64[modrm.rm + add]);
17035           else if ((prefixes & PREFIX_DATA))
17036             oappend (names16[modrm.rm + add]);
17037           else
17038             oappend (names32[modrm.rm + add]);
17039         }
17040     }
17041   else
17042     OP_E (bytemode, sizeflag);
17043 }
17044
17045 static void
17046 FXSAVE_Fixup (int bytemode, int sizeflag)
17047 {
17048   /* Add proper suffix to "fxsave" and "fxrstor".  */
17049   USED_REX (REX_W);
17050   if (rex & REX_W)
17051     {
17052       char *p = mnemonicendp;
17053       *p++ = '6';
17054       *p++ = '4';
17055       *p = '\0';
17056       mnemonicendp = p;
17057     }
17058   OP_M (bytemode, sizeflag);
17059 }
17060
17061 static void
17062 PCMPESTR_Fixup (int bytemode, int sizeflag)
17063 {
17064   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17065   if (!intel_syntax)
17066     {
17067       char *p = mnemonicendp;
17068
17069       USED_REX (REX_W);
17070       if (rex & REX_W)
17071         *p++ = 'q';
17072       else if (sizeflag & SUFFIX_ALWAYS)
17073         *p++ = 'l';
17074
17075       *p = '\0';
17076       mnemonicendp = p;
17077     }
17078
17079   OP_EX (bytemode, sizeflag);
17080 }
17081
17082 /* Display the destination register operand for instructions with
17083    VEX. */
17084
17085 static void
17086 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17087 {
17088   int reg;
17089   const char **names;
17090
17091   if (!need_vex)
17092     abort ();
17093
17094   if (!need_vex_reg)
17095     return;
17096
17097   reg = vex.register_specifier;
17098   if (address_mode != mode_64bit)
17099     reg &= 7;
17100   else if (vex.evex && !vex.v)
17101     reg += 16;
17102
17103   if (bytemode == vex_scalar_mode)
17104     {
17105       oappend (names_xmm[reg]);
17106       return;
17107     }
17108
17109   switch (vex.length)
17110     {
17111     case 128:
17112       switch (bytemode)
17113         {
17114         case vex_mode:
17115         case vex128_mode:
17116         case vex_vsib_q_w_dq_mode:
17117         case vex_vsib_q_w_d_mode:
17118           names = names_xmm;
17119           break;
17120         case dq_mode:
17121           if (rex & REX_W)
17122             names = names64;
17123           else
17124             names = names32;
17125           break;
17126         case mask_bd_mode:
17127         case mask_mode:
17128           if (reg > 0x7)
17129             {
17130               oappend ("(bad)");
17131               return;
17132             }
17133           names = names_mask;
17134           break;
17135         default:
17136           abort ();
17137           return;
17138         }
17139       break;
17140     case 256:
17141       switch (bytemode)
17142         {
17143         case vex_mode:
17144         case vex256_mode:
17145           names = names_ymm;
17146           break;
17147         case vex_vsib_q_w_dq_mode:
17148         case vex_vsib_q_w_d_mode:
17149           names = vex.w ? names_ymm : names_xmm;
17150           break;
17151         case mask_bd_mode:
17152         case mask_mode:
17153           if (reg > 0x7)
17154             {
17155               oappend ("(bad)");
17156               return;
17157             }
17158           names = names_mask;
17159           break;
17160         default:
17161           /* See PR binutils/20893 for a reproducer.  */
17162           oappend ("(bad)");
17163           return;
17164         }
17165       break;
17166     case 512:
17167       names = names_zmm;
17168       break;
17169     default:
17170       abort ();
17171       break;
17172     }
17173   oappend (names[reg]);
17174 }
17175
17176 /* Get the VEX immediate byte without moving codep.  */
17177
17178 static unsigned char
17179 get_vex_imm8 (int sizeflag, int opnum)
17180 {
17181   int bytes_before_imm = 0;
17182
17183   if (modrm.mod != 3)
17184     {
17185       /* There are SIB/displacement bytes.  */
17186       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17187         {
17188           /* 32/64 bit address mode */
17189           int base = modrm.rm;
17190
17191           /* Check SIB byte.  */
17192           if (base == 4)
17193             {
17194               FETCH_DATA (the_info, codep + 1);
17195               base = *codep & 7;
17196               /* When decoding the third source, don't increase
17197                  bytes_before_imm as this has already been incremented
17198                  by one in OP_E_memory while decoding the second
17199                  source operand.  */
17200               if (opnum == 0)
17201                 bytes_before_imm++;
17202             }
17203
17204           /* Don't increase bytes_before_imm when decoding the third source,
17205              it has already been incremented by OP_E_memory while decoding
17206              the second source operand.  */
17207           if (opnum == 0)
17208             {
17209               switch (modrm.mod)
17210                 {
17211                   case 0:
17212                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17213                        SIB == 5, there is a 4 byte displacement.  */
17214                     if (base != 5)
17215                       /* No displacement. */
17216                       break;
17217                     /* Fall through.  */
17218                   case 2:
17219                     /* 4 byte displacement.  */
17220                     bytes_before_imm += 4;
17221                     break;
17222                   case 1:
17223                     /* 1 byte displacement.  */
17224                     bytes_before_imm++;
17225                     break;
17226                 }
17227             }
17228         }
17229       else
17230         {
17231           /* 16 bit address mode */
17232           /* Don't increase bytes_before_imm when decoding the third source,
17233              it has already been incremented by OP_E_memory while decoding
17234              the second source operand.  */
17235           if (opnum == 0)
17236             {
17237               switch (modrm.mod)
17238                 {
17239                 case 0:
17240                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17241                   if (modrm.rm != 6)
17242                     /* No displacement. */
17243                     break;
17244                   /* Fall through.  */
17245                 case 2:
17246                   /* 2 byte displacement.  */
17247                   bytes_before_imm += 2;
17248                   break;
17249                 case 1:
17250                   /* 1 byte displacement: when decoding the third source,
17251                      don't increase bytes_before_imm as this has already
17252                      been incremented by one in OP_E_memory while decoding
17253                      the second source operand.  */
17254                   if (opnum == 0)
17255                     bytes_before_imm++;
17256
17257                   break;
17258                 }
17259             }
17260         }
17261     }
17262
17263   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17264   return codep [bytes_before_imm];
17265 }
17266
17267 static void
17268 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17269 {
17270   const char **names;
17271
17272   if (reg == -1 && modrm.mod != 3)
17273     {
17274       OP_E_memory (bytemode, sizeflag);
17275       return;
17276     }
17277   else
17278     {
17279       if (reg == -1)
17280         {
17281           reg = modrm.rm;
17282           USED_REX (REX_B);
17283           if (rex & REX_B)
17284             reg += 8;
17285         }
17286       if (address_mode != mode_64bit)
17287         reg &= 7;
17288     }
17289
17290   switch (vex.length)
17291     {
17292     case 128:
17293       names = names_xmm;
17294       break;
17295     case 256:
17296       names = names_ymm;
17297       break;
17298     default:
17299       abort ();
17300     }
17301   oappend (names[reg]);
17302 }
17303
17304 static void
17305 OP_EX_VexImmW (int bytemode, int sizeflag)
17306 {
17307   int reg = -1;
17308   static unsigned char vex_imm8;
17309
17310   if (vex_w_done == 0)
17311     {
17312       vex_w_done = 1;
17313
17314       /* Skip mod/rm byte.  */
17315       MODRM_CHECK;
17316       codep++;
17317
17318       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17319
17320       if (vex.w)
17321           reg = vex_imm8 >> 4;
17322
17323       OP_EX_VexReg (bytemode, sizeflag, reg);
17324     }
17325   else if (vex_w_done == 1)
17326     {
17327       vex_w_done = 2;
17328
17329       if (!vex.w)
17330           reg = vex_imm8 >> 4;
17331
17332       OP_EX_VexReg (bytemode, sizeflag, reg);
17333     }
17334   else
17335     {
17336       /* Output the imm8 directly.  */
17337       scratchbuf[0] = '$';
17338       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17339       oappend_maybe_intel (scratchbuf);
17340       scratchbuf[0] = '\0';
17341       codep++;
17342     }
17343 }
17344
17345 static void
17346 OP_Vex_2src (int bytemode, int sizeflag)
17347 {
17348   if (modrm.mod == 3)
17349     {
17350       int reg = modrm.rm;
17351       USED_REX (REX_B);
17352       if (rex & REX_B)
17353         reg += 8;
17354       oappend (names_xmm[reg]);
17355     }
17356   else
17357     {
17358       if (intel_syntax
17359           && (bytemode == v_mode || bytemode == v_swap_mode))
17360         {
17361           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17362           used_prefixes |= (prefixes & PREFIX_DATA);
17363         }
17364       OP_E (bytemode, sizeflag);
17365     }
17366 }
17367
17368 static void
17369 OP_Vex_2src_1 (int bytemode, int sizeflag)
17370 {
17371   if (modrm.mod == 3)
17372     {
17373       /* Skip mod/rm byte.   */
17374       MODRM_CHECK;
17375       codep++;
17376     }
17377
17378   if (vex.w)
17379     {
17380       unsigned int reg = vex.register_specifier;
17381
17382       if (address_mode != mode_64bit)
17383         reg &= 7;
17384       oappend (names_xmm[reg]);
17385     }
17386   else
17387     OP_Vex_2src (bytemode, sizeflag);
17388 }
17389
17390 static void
17391 OP_Vex_2src_2 (int bytemode, int sizeflag)
17392 {
17393   if (vex.w)
17394     OP_Vex_2src (bytemode, sizeflag);
17395   else
17396     {
17397       unsigned int reg = vex.register_specifier;
17398
17399       if (address_mode != mode_64bit)
17400         reg &= 7;
17401       oappend (names_xmm[reg]);
17402     }
17403 }
17404
17405 static void
17406 OP_EX_VexW (int bytemode, int sizeflag)
17407 {
17408   int reg = -1;
17409
17410   if (!vex_w_done)
17411     {
17412       /* Skip mod/rm byte.  */
17413       MODRM_CHECK;
17414       codep++;
17415
17416       if (vex.w)
17417         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17418     }
17419   else
17420     {
17421       if (!vex.w)
17422         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17423     }
17424
17425   OP_EX_VexReg (bytemode, sizeflag, reg);
17426
17427   if (vex_w_done)
17428     codep++;
17429   vex_w_done = 1;
17430 }
17431
17432 static void
17433 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17434 {
17435   int reg;
17436   const char **names;
17437
17438   FETCH_DATA (the_info, codep + 1);
17439   reg = *codep++;
17440
17441   if (bytemode != x_mode)
17442     abort ();
17443
17444   reg >>= 4;
17445   if (address_mode != mode_64bit)
17446     reg &= 7;
17447
17448   switch (vex.length)
17449     {
17450     case 128:
17451       names = names_xmm;
17452       break;
17453     case 256:
17454       names = names_ymm;
17455       break;
17456     default:
17457       abort ();
17458     }
17459   oappend (names[reg]);
17460 }
17461
17462 static void
17463 OP_XMM_VexW (int bytemode, int sizeflag)
17464 {
17465   /* Turn off the REX.W bit since it is used for swapping operands
17466      now.  */
17467   rex &= ~REX_W;
17468   OP_XMM (bytemode, sizeflag);
17469 }
17470
17471 static void
17472 OP_EX_Vex (int bytemode, int sizeflag)
17473 {
17474   if (modrm.mod != 3)
17475     {
17476       if (vex.register_specifier != 0)
17477         BadOp ();
17478       need_vex_reg = 0;
17479     }
17480   OP_EX (bytemode, sizeflag);
17481 }
17482
17483 static void
17484 OP_XMM_Vex (int bytemode, int sizeflag)
17485 {
17486   if (modrm.mod != 3)
17487     {
17488       if (vex.register_specifier != 0)
17489         BadOp ();
17490       need_vex_reg = 0;
17491     }
17492   OP_XMM (bytemode, sizeflag);
17493 }
17494
17495 static void
17496 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17497 {
17498   switch (vex.length)
17499     {
17500     case 128:
17501       mnemonicendp = stpcpy (obuf, "vzeroupper");
17502       break;
17503     case 256:
17504       mnemonicendp = stpcpy (obuf, "vzeroall");
17505       break;
17506     default:
17507       abort ();
17508     }
17509 }
17510
17511 static struct op vex_cmp_op[] =
17512 {
17513   { STRING_COMMA_LEN ("eq") },
17514   { STRING_COMMA_LEN ("lt") },
17515   { STRING_COMMA_LEN ("le") },
17516   { STRING_COMMA_LEN ("unord") },
17517   { STRING_COMMA_LEN ("neq") },
17518   { STRING_COMMA_LEN ("nlt") },
17519   { STRING_COMMA_LEN ("nle") },
17520   { STRING_COMMA_LEN ("ord") },
17521   { STRING_COMMA_LEN ("eq_uq") },
17522   { STRING_COMMA_LEN ("nge") },
17523   { STRING_COMMA_LEN ("ngt") },
17524   { STRING_COMMA_LEN ("false") },
17525   { STRING_COMMA_LEN ("neq_oq") },
17526   { STRING_COMMA_LEN ("ge") },
17527   { STRING_COMMA_LEN ("gt") },
17528   { STRING_COMMA_LEN ("true") },
17529   { STRING_COMMA_LEN ("eq_os") },
17530   { STRING_COMMA_LEN ("lt_oq") },
17531   { STRING_COMMA_LEN ("le_oq") },
17532   { STRING_COMMA_LEN ("unord_s") },
17533   { STRING_COMMA_LEN ("neq_us") },
17534   { STRING_COMMA_LEN ("nlt_uq") },
17535   { STRING_COMMA_LEN ("nle_uq") },
17536   { STRING_COMMA_LEN ("ord_s") },
17537   { STRING_COMMA_LEN ("eq_us") },
17538   { STRING_COMMA_LEN ("nge_uq") },
17539   { STRING_COMMA_LEN ("ngt_uq") },
17540   { STRING_COMMA_LEN ("false_os") },
17541   { STRING_COMMA_LEN ("neq_os") },
17542   { STRING_COMMA_LEN ("ge_oq") },
17543   { STRING_COMMA_LEN ("gt_oq") },
17544   { STRING_COMMA_LEN ("true_us") },
17545 };
17546
17547 static void
17548 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17549 {
17550   unsigned int cmp_type;
17551
17552   FETCH_DATA (the_info, codep + 1);
17553   cmp_type = *codep++ & 0xff;
17554   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17555     {
17556       char suffix [3];
17557       char *p = mnemonicendp - 2;
17558       suffix[0] = p[0];
17559       suffix[1] = p[1];
17560       suffix[2] = '\0';
17561       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17562       mnemonicendp += vex_cmp_op[cmp_type].len;
17563     }
17564   else
17565     {
17566       /* We have a reserved extension byte.  Output it directly.  */
17567       scratchbuf[0] = '$';
17568       print_operand_value (scratchbuf + 1, 1, cmp_type);
17569       oappend_maybe_intel (scratchbuf);
17570       scratchbuf[0] = '\0';
17571     }
17572 }
17573
17574 static void
17575 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17576              int sizeflag ATTRIBUTE_UNUSED)
17577 {
17578   unsigned int cmp_type;
17579
17580   if (!vex.evex)
17581     abort ();
17582
17583   FETCH_DATA (the_info, codep + 1);
17584   cmp_type = *codep++ & 0xff;
17585   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17586      If it's the case, print suffix, otherwise - print the immediate.  */
17587   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17588       && cmp_type != 3
17589       && cmp_type != 7)
17590     {
17591       char suffix [3];
17592       char *p = mnemonicendp - 2;
17593
17594       /* vpcmp* can have both one- and two-lettered suffix.  */
17595       if (p[0] == 'p')
17596         {
17597           p++;
17598           suffix[0] = p[0];
17599           suffix[1] = '\0';
17600         }
17601       else
17602         {
17603           suffix[0] = p[0];
17604           suffix[1] = p[1];
17605           suffix[2] = '\0';
17606         }
17607
17608       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17609       mnemonicendp += simd_cmp_op[cmp_type].len;
17610     }
17611   else
17612     {
17613       /* We have a reserved extension byte.  Output it directly.  */
17614       scratchbuf[0] = '$';
17615       print_operand_value (scratchbuf + 1, 1, cmp_type);
17616       oappend_maybe_intel (scratchbuf);
17617       scratchbuf[0] = '\0';
17618     }
17619 }
17620
17621 static const struct op xop_cmp_op[] =
17622 {
17623   { STRING_COMMA_LEN ("lt") },
17624   { STRING_COMMA_LEN ("le") },
17625   { STRING_COMMA_LEN ("gt") },
17626   { STRING_COMMA_LEN ("ge") },
17627   { STRING_COMMA_LEN ("eq") },
17628   { STRING_COMMA_LEN ("neq") },
17629   { STRING_COMMA_LEN ("false") },
17630   { STRING_COMMA_LEN ("true") }
17631 };
17632
17633 static void
17634 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17635              int sizeflag ATTRIBUTE_UNUSED)
17636 {
17637   unsigned int cmp_type;
17638
17639   FETCH_DATA (the_info, codep + 1);
17640   cmp_type = *codep++ & 0xff;
17641   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17642     {
17643       char suffix[3];
17644       char *p = mnemonicendp - 2;
17645
17646       /* vpcom* can have both one- and two-lettered suffix.  */
17647       if (p[0] == 'm')
17648         {
17649           p++;
17650           suffix[0] = p[0];
17651           suffix[1] = '\0';
17652         }
17653       else
17654         {
17655           suffix[0] = p[0];
17656           suffix[1] = p[1];
17657           suffix[2] = '\0';
17658         }
17659
17660       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17661       mnemonicendp += xop_cmp_op[cmp_type].len;
17662     }
17663   else
17664     {
17665       /* We have a reserved extension byte.  Output it directly.  */
17666       scratchbuf[0] = '$';
17667       print_operand_value (scratchbuf + 1, 1, cmp_type);
17668       oappend_maybe_intel (scratchbuf);
17669       scratchbuf[0] = '\0';
17670     }
17671 }
17672
17673 static const struct op pclmul_op[] =
17674 {
17675   { STRING_COMMA_LEN ("lql") },
17676   { STRING_COMMA_LEN ("hql") },
17677   { STRING_COMMA_LEN ("lqh") },
17678   { STRING_COMMA_LEN ("hqh") }
17679 };
17680
17681 static void
17682 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17683               int sizeflag ATTRIBUTE_UNUSED)
17684 {
17685   unsigned int pclmul_type;
17686
17687   FETCH_DATA (the_info, codep + 1);
17688   pclmul_type = *codep++ & 0xff;
17689   switch (pclmul_type)
17690     {
17691     case 0x10:
17692       pclmul_type = 2;
17693       break;
17694     case 0x11:
17695       pclmul_type = 3;
17696       break;
17697     default:
17698       break;
17699     }
17700   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17701     {
17702       char suffix [4];
17703       char *p = mnemonicendp - 3;
17704       suffix[0] = p[0];
17705       suffix[1] = p[1];
17706       suffix[2] = p[2];
17707       suffix[3] = '\0';
17708       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17709       mnemonicendp += pclmul_op[pclmul_type].len;
17710     }
17711   else
17712     {
17713       /* We have a reserved extension byte.  Output it directly.  */
17714       scratchbuf[0] = '$';
17715       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17716       oappend_maybe_intel (scratchbuf);
17717       scratchbuf[0] = '\0';
17718     }
17719 }
17720
17721 static void
17722 MOVBE_Fixup (int bytemode, int sizeflag)
17723 {
17724   /* Add proper suffix to "movbe".  */
17725   char *p = mnemonicendp;
17726
17727   switch (bytemode)
17728     {
17729     case v_mode:
17730       if (intel_syntax)
17731         goto skip;
17732
17733       USED_REX (REX_W);
17734       if (sizeflag & SUFFIX_ALWAYS)
17735         {
17736           if (rex & REX_W)
17737             *p++ = 'q';
17738           else
17739             {
17740               if (sizeflag & DFLAG)
17741                 *p++ = 'l';
17742               else
17743                 *p++ = 'w';
17744               used_prefixes |= (prefixes & PREFIX_DATA);
17745             }
17746         }
17747       break;
17748     default:
17749       oappend (INTERNAL_DISASSEMBLER_ERROR);
17750       break;
17751     }
17752   mnemonicendp = p;
17753   *p = '\0';
17754
17755 skip:
17756   OP_M (bytemode, sizeflag);
17757 }
17758
17759 static void
17760 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17761 {
17762   int reg;
17763   const char **names;
17764
17765   /* Skip mod/rm byte.  */
17766   MODRM_CHECK;
17767   codep++;
17768
17769   if (rex & REX_W)
17770     names = names64;
17771   else
17772     names = names32;
17773
17774   reg = modrm.rm;
17775   USED_REX (REX_B);
17776   if (rex & REX_B)
17777     reg += 8;
17778
17779   oappend (names[reg]);
17780 }
17781
17782 static void
17783 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17784 {
17785   const char **names;
17786   unsigned int reg = vex.register_specifier;
17787
17788   if (rex & REX_W)
17789     names = names64;
17790   else
17791     names = names32;
17792
17793   if (address_mode != mode_64bit)
17794     reg &= 7;
17795   oappend (names[reg]);
17796 }
17797
17798 static void
17799 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17800 {
17801   if (!vex.evex
17802       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17803     abort ();
17804
17805   USED_REX (REX_R);
17806   if ((rex & REX_R) != 0 || !vex.r)
17807     {
17808       BadOp ();
17809       return;
17810     }
17811
17812   oappend (names_mask [modrm.reg]);
17813 }
17814
17815 static void
17816 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17817 {
17818   if (!vex.evex
17819       || (bytemode != evex_rounding_mode
17820           && bytemode != evex_sae_mode))
17821     abort ();
17822   if (modrm.mod == 3 && vex.b)
17823     switch (bytemode)
17824       {
17825       case evex_rounding_mode:
17826         oappend (names_rounding[vex.ll]);
17827         break;
17828       case evex_sae_mode:
17829         oappend ("{sae}");
17830         break;
17831       default:
17832         break;
17833       }
17834 }