opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE
 707 };
 708
 709 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 710
 711 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 712 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 713 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 714 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 715 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 716 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 717 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 718 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 719 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 720 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 721 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 722 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 723 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 724 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 725 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 726
 727 enum
 728 {
 729   REG_80 = 0,
 730   REG_81,
 731   REG_83,
 732   REG_8F,
 733   REG_C0,
 734   REG_C1,
 735   REG_C6,
 736   REG_C7,
 737   REG_D0,
 738   REG_D1,
 739   REG_D2,
 740   REG_D3,
 741   REG_F6,
 742   REG_F7,
 743   REG_FE,
 744   REG_FF,
 745   REG_0F00,
 746   REG_0F01,
 747   REG_0F0D,
 748   REG_0F18,
 749   REG_0F1C_MOD_0,
 750   REG_0F1E_MOD_3,
 751   REG_0F71,
 752   REG_0F72,
 753   REG_0F73,
 754   REG_0FA6,
 755   REG_0FA7,
 756   REG_0FAE,
 757   REG_0FBA,
 758   REG_0FC7,
 759   REG_VEX_0F71,
 760   REG_VEX_0F72,
 761   REG_VEX_0F73,
 762   REG_VEX_0FAE,
 763   REG_VEX_0F38F3,
 764   REG_XOP_LWPCB,
 765   REG_XOP_LWP,
 766   REG_XOP_TBM_01,
 767   REG_XOP_TBM_02,
 768
 769   REG_EVEX_0F71,
 770   REG_EVEX_0F72,
 771   REG_EVEX_0F73,
 772   REG_EVEX_0F38C6,
 773   REG_EVEX_0F38C7
 774 };
 775
 776 enum
 777 {
 778   MOD_8D = 0,
 779   MOD_C6_REG_7,
 780   MOD_C7_REG_7,
 781   MOD_FF_REG_3,
 782   MOD_FF_REG_5,
 783   MOD_0F01_REG_0,
 784   MOD_0F01_REG_1,
 785   MOD_0F01_REG_2,
 786   MOD_0F01_REG_3,
 787   MOD_0F01_REG_5,
 788   MOD_0F01_REG_7,
 789   MOD_0F12_PREFIX_0,
 790   MOD_0F13,
 791   MOD_0F16_PREFIX_0,
 792   MOD_0F17,
 793   MOD_0F18_REG_0,
 794   MOD_0F18_REG_1,
 795   MOD_0F18_REG_2,
 796   MOD_0F18_REG_3,
 797   MOD_0F18_REG_4,
 798   MOD_0F18_REG_5,
 799   MOD_0F18_REG_6,
 800   MOD_0F18_REG_7,
 801   MOD_0F1A_PREFIX_0,
 802   MOD_0F1B_PREFIX_0,
 803   MOD_0F1B_PREFIX_1,
 804   MOD_0F1C_PREFIX_0,
 805   MOD_0F1E_PREFIX_1,
 806   MOD_0F24,
 807   MOD_0F26,
 808   MOD_0F2B_PREFIX_0,
 809   MOD_0F2B_PREFIX_1,
 810   MOD_0F2B_PREFIX_2,
 811   MOD_0F2B_PREFIX_3,
 812   MOD_0F51,
 813   MOD_0F71_REG_2,
 814   MOD_0F71_REG_4,
 815   MOD_0F71_REG_6,
 816   MOD_0F72_REG_2,
 817   MOD_0F72_REG_4,
 818   MOD_0F72_REG_6,
 819   MOD_0F73_REG_2,
 820   MOD_0F73_REG_3,
 821   MOD_0F73_REG_6,
 822   MOD_0F73_REG_7,
 823   MOD_0FAE_REG_0,
 824   MOD_0FAE_REG_1,
 825   MOD_0FAE_REG_2,
 826   MOD_0FAE_REG_3,
 827   MOD_0FAE_REG_4,
 828   MOD_0FAE_REG_5,
 829   MOD_0FAE_REG_6,
 830   MOD_0FAE_REG_7,
 831   MOD_0FB2,
 832   MOD_0FB4,
 833   MOD_0FB5,
 834   MOD_0FC3,
 835   MOD_0FC7_REG_3,
 836   MOD_0FC7_REG_4,
 837   MOD_0FC7_REG_5,
 838   MOD_0FC7_REG_6,
 839   MOD_0FC7_REG_7,
 840   MOD_0FD7,
 841   MOD_0FE7_PREFIX_2,
 842   MOD_0FF0_PREFIX_3,
 843   MOD_0F382A_PREFIX_2,
 844   MOD_0F38F5_PREFIX_2,
 845   MOD_0F38F6_PREFIX_0,
 846   MOD_0F38F8_PREFIX_2,
 847   MOD_0F38F9_PREFIX_0,
 848   MOD_62_32BIT,
 849   MOD_C4_32BIT,
 850   MOD_C5_32BIT,
 851   MOD_VEX_0F12_PREFIX_0,
 852   MOD_VEX_0F13,
 853   MOD_VEX_0F16_PREFIX_0,
 854   MOD_VEX_0F17,
 855   MOD_VEX_0F2B,
 856   MOD_VEX_W_0_0F41_P_0_LEN_1,
 857   MOD_VEX_W_1_0F41_P_0_LEN_1,
 858   MOD_VEX_W_0_0F41_P_2_LEN_1,
 859   MOD_VEX_W_1_0F41_P_2_LEN_1,
 860   MOD_VEX_W_0_0F42_P_0_LEN_1,
 861   MOD_VEX_W_1_0F42_P_0_LEN_1,
 862   MOD_VEX_W_0_0F42_P_2_LEN_1,
 863   MOD_VEX_W_1_0F42_P_2_LEN_1,
 864   MOD_VEX_W_0_0F44_P_0_LEN_1,
 865   MOD_VEX_W_1_0F44_P_0_LEN_1,
 866   MOD_VEX_W_0_0F44_P_2_LEN_1,
 867   MOD_VEX_W_1_0F44_P_2_LEN_1,
 868   MOD_VEX_W_0_0F45_P_0_LEN_1,
 869   MOD_VEX_W_1_0F45_P_0_LEN_1,
 870   MOD_VEX_W_0_0F45_P_2_LEN_1,
 871   MOD_VEX_W_1_0F45_P_2_LEN_1,
 872   MOD_VEX_W_0_0F46_P_0_LEN_1,
 873   MOD_VEX_W_1_0F46_P_0_LEN_1,
 874   MOD_VEX_W_0_0F46_P_2_LEN_1,
 875   MOD_VEX_W_1_0F46_P_2_LEN_1,
 876   MOD_VEX_W_0_0F47_P_0_LEN_1,
 877   MOD_VEX_W_1_0F47_P_0_LEN_1,
 878   MOD_VEX_W_0_0F47_P_2_LEN_1,
 879   MOD_VEX_W_1_0F47_P_2_LEN_1,
 880   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 881   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 887   MOD_VEX_0F50,
 888   MOD_VEX_0F71_REG_2,
 889   MOD_VEX_0F71_REG_4,
 890   MOD_VEX_0F71_REG_6,
 891   MOD_VEX_0F72_REG_2,
 892   MOD_VEX_0F72_REG_4,
 893   MOD_VEX_0F72_REG_6,
 894   MOD_VEX_0F73_REG_2,
 895   MOD_VEX_0F73_REG_3,
 896   MOD_VEX_0F73_REG_6,
 897   MOD_VEX_0F73_REG_7,
 898   MOD_VEX_W_0_0F91_P_0_LEN_0,
 899   MOD_VEX_W_1_0F91_P_0_LEN_0,
 900   MOD_VEX_W_0_0F91_P_2_LEN_0,
 901   MOD_VEX_W_1_0F91_P_2_LEN_0,
 902   MOD_VEX_W_0_0F92_P_0_LEN_0,
 903   MOD_VEX_W_0_0F92_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_3_LEN_0,
 905   MOD_VEX_W_1_0F92_P_3_LEN_0,
 906   MOD_VEX_W_0_0F93_P_0_LEN_0,
 907   MOD_VEX_W_0_0F93_P_2_LEN_0,
 908   MOD_VEX_W_0_0F93_P_3_LEN_0,
 909   MOD_VEX_W_1_0F93_P_3_LEN_0,
 910   MOD_VEX_W_0_0F98_P_0_LEN_0,
 911   MOD_VEX_W_1_0F98_P_0_LEN_0,
 912   MOD_VEX_W_0_0F98_P_2_LEN_0,
 913   MOD_VEX_W_1_0F98_P_2_LEN_0,
 914   MOD_VEX_W_0_0F99_P_0_LEN_0,
 915   MOD_VEX_W_1_0F99_P_0_LEN_0,
 916   MOD_VEX_W_0_0F99_P_2_LEN_0,
 917   MOD_VEX_W_1_0F99_P_2_LEN_0,
 918   MOD_VEX_0FAE_REG_2,
 919   MOD_VEX_0FAE_REG_3,
 920   MOD_VEX_0FD7_PREFIX_2,
 921   MOD_VEX_0FE7_PREFIX_2,
 922   MOD_VEX_0FF0_PREFIX_3,
 923   MOD_VEX_0F381A_PREFIX_2,
 924   MOD_VEX_0F382A_PREFIX_2,
 925   MOD_VEX_0F382C_PREFIX_2,
 926   MOD_VEX_0F382D_PREFIX_2,
 927   MOD_VEX_0F382E_PREFIX_2,
 928   MOD_VEX_0F382F_PREFIX_2,
 929   MOD_VEX_0F385A_PREFIX_2,
 930   MOD_VEX_0F388C_PREFIX_2,
 931   MOD_VEX_0F388E_PREFIX_2,
 932   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 940
 941   MOD_EVEX_0F10_PREFIX_1,
 942   MOD_EVEX_0F10_PREFIX_3,
 943   MOD_EVEX_0F11_PREFIX_1,
 944   MOD_EVEX_0F11_PREFIX_3,
 945   MOD_EVEX_0F12_PREFIX_0,
 946   MOD_EVEX_0F16_PREFIX_0,
 947   MOD_EVEX_0F38C6_REG_1,
 948   MOD_EVEX_0F38C6_REG_2,
 949   MOD_EVEX_0F38C6_REG_5,
 950   MOD_EVEX_0F38C6_REG_6,
 951   MOD_EVEX_0F38C7_REG_1,
 952   MOD_EVEX_0F38C7_REG_2,
 953   MOD_EVEX_0F38C7_REG_5,
 954   MOD_EVEX_0F38C7_REG_6
 955 };
 956
 957 enum
 958 {
 959   RM_C6_REG_7 = 0,
 960   RM_C7_REG_7,
 961   RM_0F01_REG_0,
 962   RM_0F01_REG_1,
 963   RM_0F01_REG_2,
 964   RM_0F01_REG_3,
 965   RM_0F01_REG_5,
 966   RM_0F01_REG_7,
 967   RM_0F1E_MOD_3_REG_7,
 968   RM_0FAE_REG_6,
 969   RM_0FAE_REG_7
 970 };
 971
 972 enum
 973 {
 974   PREFIX_90 = 0,
 975   PREFIX_MOD_0_0F01_REG_5,
 976   PREFIX_MOD_3_0F01_REG_5_RM_0,
 977   PREFIX_MOD_3_0F01_REG_5_RM_2,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0,
1020   PREFIX_0FAE_REG_1,
1021   PREFIX_0FAE_REG_2,
1022   PREFIX_0FAE_REG_3,
1023   PREFIX_MOD_0_0FAE_REG_4,
1024   PREFIX_MOD_3_0FAE_REG_4,
1025   PREFIX_MOD_0_0FAE_REG_5,
1026   PREFIX_MOD_3_0FAE_REG_5,
1027   PREFIX_MOD_0_0FAE_REG_6,
1028   PREFIX_MOD_1_0FAE_REG_6,
1029   PREFIX_0FAE_REG_7,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_MOD_0_0FC3,
1035   PREFIX_MOD_0_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_6,
1037   PREFIX_MOD_3_0FC7_REG_7,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F13,
1428   PREFIX_EVEX_0F14,
1429   PREFIX_EVEX_0F15,
1430   PREFIX_EVEX_0F16,
1431   PREFIX_EVEX_0F17,
1432   PREFIX_EVEX_0F28,
1433   PREFIX_EVEX_0F29,
1434   PREFIX_EVEX_0F2A,
1435   PREFIX_EVEX_0F2B,
1436   PREFIX_EVEX_0F2C,
1437   PREFIX_EVEX_0F2D,
1438   PREFIX_EVEX_0F2E,
1439   PREFIX_EVEX_0F2F,
1440   PREFIX_EVEX_0F51,
1441   PREFIX_EVEX_0F54,
1442   PREFIX_EVEX_0F55,
1443   PREFIX_EVEX_0F56,
1444   PREFIX_EVEX_0F57,
1445   PREFIX_EVEX_0F58,
1446   PREFIX_EVEX_0F59,
1447   PREFIX_EVEX_0F5A,
1448   PREFIX_EVEX_0F5B,
1449   PREFIX_EVEX_0F5C,
1450   PREFIX_EVEX_0F5D,
1451   PREFIX_EVEX_0F5E,
1452   PREFIX_EVEX_0F5F,
1453   PREFIX_EVEX_0F60,
1454   PREFIX_EVEX_0F61,
1455   PREFIX_EVEX_0F62,
1456   PREFIX_EVEX_0F63,
1457   PREFIX_EVEX_0F64,
1458   PREFIX_EVEX_0F65,
1459   PREFIX_EVEX_0F66,
1460   PREFIX_EVEX_0F67,
1461   PREFIX_EVEX_0F68,
1462   PREFIX_EVEX_0F69,
1463   PREFIX_EVEX_0F6A,
1464   PREFIX_EVEX_0F6B,
1465   PREFIX_EVEX_0F6C,
1466   PREFIX_EVEX_0F6D,
1467   PREFIX_EVEX_0F6E,
1468   PREFIX_EVEX_0F6F,
1469   PREFIX_EVEX_0F70,
1470   PREFIX_EVEX_0F71_REG_2,
1471   PREFIX_EVEX_0F71_REG_4,
1472   PREFIX_EVEX_0F71_REG_6,
1473   PREFIX_EVEX_0F72_REG_0,
1474   PREFIX_EVEX_0F72_REG_1,
1475   PREFIX_EVEX_0F72_REG_2,
1476   PREFIX_EVEX_0F72_REG_4,
1477   PREFIX_EVEX_0F72_REG_6,
1478   PREFIX_EVEX_0F73_REG_2,
1479   PREFIX_EVEX_0F73_REG_3,
1480   PREFIX_EVEX_0F73_REG_6,
1481   PREFIX_EVEX_0F73_REG_7,
1482   PREFIX_EVEX_0F74,
1483   PREFIX_EVEX_0F75,
1484   PREFIX_EVEX_0F76,
1485   PREFIX_EVEX_0F78,
1486   PREFIX_EVEX_0F79,
1487   PREFIX_EVEX_0F7A,
1488   PREFIX_EVEX_0F7B,
1489   PREFIX_EVEX_0F7E,
1490   PREFIX_EVEX_0F7F,
1491   PREFIX_EVEX_0FC2,
1492   PREFIX_EVEX_0FC4,
1493   PREFIX_EVEX_0FC5,
1494   PREFIX_EVEX_0FC6,
1495   PREFIX_EVEX_0FD1,
1496   PREFIX_EVEX_0FD2,
1497   PREFIX_EVEX_0FD3,
1498   PREFIX_EVEX_0FD4,
1499   PREFIX_EVEX_0FD5,
1500   PREFIX_EVEX_0FD6,
1501   PREFIX_EVEX_0FD8,
1502   PREFIX_EVEX_0FD9,
1503   PREFIX_EVEX_0FDA,
1504   PREFIX_EVEX_0FDB,
1505   PREFIX_EVEX_0FDC,
1506   PREFIX_EVEX_0FDD,
1507   PREFIX_EVEX_0FDE,
1508   PREFIX_EVEX_0FDF,
1509   PREFIX_EVEX_0FE0,
1510   PREFIX_EVEX_0FE1,
1511   PREFIX_EVEX_0FE2,
1512   PREFIX_EVEX_0FE3,
1513   PREFIX_EVEX_0FE4,
1514   PREFIX_EVEX_0FE5,
1515   PREFIX_EVEX_0FE6,
1516   PREFIX_EVEX_0FE7,
1517   PREFIX_EVEX_0FE8,
1518   PREFIX_EVEX_0FE9,
1519   PREFIX_EVEX_0FEA,
1520   PREFIX_EVEX_0FEB,
1521   PREFIX_EVEX_0FEC,
1522   PREFIX_EVEX_0FED,
1523   PREFIX_EVEX_0FEE,
1524   PREFIX_EVEX_0FEF,
1525   PREFIX_EVEX_0FF1,
1526   PREFIX_EVEX_0FF2,
1527   PREFIX_EVEX_0FF3,
1528   PREFIX_EVEX_0FF4,
1529   PREFIX_EVEX_0FF5,
1530   PREFIX_EVEX_0FF6,
1531   PREFIX_EVEX_0FF8,
1532   PREFIX_EVEX_0FF9,
1533   PREFIX_EVEX_0FFA,
1534   PREFIX_EVEX_0FFB,
1535   PREFIX_EVEX_0FFC,
1536   PREFIX_EVEX_0FFD,
1537   PREFIX_EVEX_0FFE,
1538   PREFIX_EVEX_0F3800,
1539   PREFIX_EVEX_0F3804,
1540   PREFIX_EVEX_0F380B,
1541   PREFIX_EVEX_0F380C,
1542   PREFIX_EVEX_0F380D,
1543   PREFIX_EVEX_0F3810,
1544   PREFIX_EVEX_0F3811,
1545   PREFIX_EVEX_0F3812,
1546   PREFIX_EVEX_0F3813,
1547   PREFIX_EVEX_0F3814,
1548   PREFIX_EVEX_0F3815,
1549   PREFIX_EVEX_0F3816,
1550   PREFIX_EVEX_0F3818,
1551   PREFIX_EVEX_0F3819,
1552   PREFIX_EVEX_0F381A,
1553   PREFIX_EVEX_0F381B,
1554   PREFIX_EVEX_0F381C,
1555   PREFIX_EVEX_0F381D,
1556   PREFIX_EVEX_0F381E,
1557   PREFIX_EVEX_0F381F,
1558   PREFIX_EVEX_0F3820,
1559   PREFIX_EVEX_0F3821,
1560   PREFIX_EVEX_0F3822,
1561   PREFIX_EVEX_0F3823,
1562   PREFIX_EVEX_0F3824,
1563   PREFIX_EVEX_0F3825,
1564   PREFIX_EVEX_0F3826,
1565   PREFIX_EVEX_0F3827,
1566   PREFIX_EVEX_0F3828,
1567   PREFIX_EVEX_0F3829,
1568   PREFIX_EVEX_0F382A,
1569   PREFIX_EVEX_0F382B,
1570   PREFIX_EVEX_0F382C,
1571   PREFIX_EVEX_0F382D,
1572   PREFIX_EVEX_0F3830,
1573   PREFIX_EVEX_0F3831,
1574   PREFIX_EVEX_0F3832,
1575   PREFIX_EVEX_0F3833,
1576   PREFIX_EVEX_0F3834,
1577   PREFIX_EVEX_0F3835,
1578   PREFIX_EVEX_0F3836,
1579   PREFIX_EVEX_0F3837,
1580   PREFIX_EVEX_0F3838,
1581   PREFIX_EVEX_0F3839,
1582   PREFIX_EVEX_0F383A,
1583   PREFIX_EVEX_0F383B,
1584   PREFIX_EVEX_0F383C,
1585   PREFIX_EVEX_0F383D,
1586   PREFIX_EVEX_0F383E,
1587   PREFIX_EVEX_0F383F,
1588   PREFIX_EVEX_0F3840,
1589   PREFIX_EVEX_0F3842,
1590   PREFIX_EVEX_0F3843,
1591   PREFIX_EVEX_0F3844,
1592   PREFIX_EVEX_0F3845,
1593   PREFIX_EVEX_0F3846,
1594   PREFIX_EVEX_0F3847,
1595   PREFIX_EVEX_0F384C,
1596   PREFIX_EVEX_0F384D,
1597   PREFIX_EVEX_0F384E,
1598   PREFIX_EVEX_0F384F,
1599   PREFIX_EVEX_0F3850,
1600   PREFIX_EVEX_0F3851,
1601   PREFIX_EVEX_0F3852,
1602   PREFIX_EVEX_0F3853,
1603   PREFIX_EVEX_0F3854,
1604   PREFIX_EVEX_0F3855,
1605   PREFIX_EVEX_0F3858,
1606   PREFIX_EVEX_0F3859,
1607   PREFIX_EVEX_0F385A,
1608   PREFIX_EVEX_0F385B,
1609   PREFIX_EVEX_0F3862,
1610   PREFIX_EVEX_0F3863,
1611   PREFIX_EVEX_0F3864,
1612   PREFIX_EVEX_0F3865,
1613   PREFIX_EVEX_0F3866,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F2A_P_1,
1822   VEX_LEN_0F2A_P_3,
1823   VEX_LEN_0F2C_P_1,
1824   VEX_LEN_0F2C_P_3,
1825   VEX_LEN_0F2D_P_1,
1826   VEX_LEN_0F2D_P_3,
1827   VEX_LEN_0F41_P_0,
1828   VEX_LEN_0F41_P_2,
1829   VEX_LEN_0F42_P_0,
1830   VEX_LEN_0F42_P_2,
1831   VEX_LEN_0F44_P_0,
1832   VEX_LEN_0F44_P_2,
1833   VEX_LEN_0F45_P_0,
1834   VEX_LEN_0F45_P_2,
1835   VEX_LEN_0F46_P_0,
1836   VEX_LEN_0F46_P_2,
1837   VEX_LEN_0F47_P_0,
1838   VEX_LEN_0F47_P_2,
1839   VEX_LEN_0F4A_P_0,
1840   VEX_LEN_0F4A_P_2,
1841   VEX_LEN_0F4B_P_0,
1842   VEX_LEN_0F4B_P_2,
1843   VEX_LEN_0F6E_P_2,
1844   VEX_LEN_0F77_P_0,
1845   VEX_LEN_0F7E_P_1,
1846   VEX_LEN_0F7E_P_2,
1847   VEX_LEN_0F90_P_0,
1848   VEX_LEN_0F90_P_2,
1849   VEX_LEN_0F91_P_0,
1850   VEX_LEN_0F91_P_2,
1851   VEX_LEN_0F92_P_0,
1852   VEX_LEN_0F92_P_2,
1853   VEX_LEN_0F92_P_3,
1854   VEX_LEN_0F93_P_0,
1855   VEX_LEN_0F93_P_2,
1856   VEX_LEN_0F93_P_3,
1857   VEX_LEN_0F98_P_0,
1858   VEX_LEN_0F98_P_2,
1859   VEX_LEN_0F99_P_0,
1860   VEX_LEN_0F99_P_2,
1861   VEX_LEN_0FAE_R_2_M_0,
1862   VEX_LEN_0FAE_R_3_M_0,
1863   VEX_LEN_0FC4_P_2,
1864   VEX_LEN_0FC5_P_2,
1865   VEX_LEN_0FD6_P_2,
1866   VEX_LEN_0FF7_P_2,
1867   VEX_LEN_0F3816_P_2,
1868   VEX_LEN_0F3819_P_2,
1869   VEX_LEN_0F381A_P_2_M_0,
1870   VEX_LEN_0F3836_P_2,
1871   VEX_LEN_0F3841_P_2,
1872   VEX_LEN_0F385A_P_2_M_0,
1873   VEX_LEN_0F38DB_P_2,
1874   VEX_LEN_0F38F2_P_0,
1875   VEX_LEN_0F38F3_R_1_P_0,
1876   VEX_LEN_0F38F3_R_2_P_0,
1877   VEX_LEN_0F38F3_R_3_P_0,
1878   VEX_LEN_0F38F5_P_0,
1879   VEX_LEN_0F38F5_P_1,
1880   VEX_LEN_0F38F5_P_3,
1881   VEX_LEN_0F38F6_P_3,
1882   VEX_LEN_0F38F7_P_0,
1883   VEX_LEN_0F38F7_P_1,
1884   VEX_LEN_0F38F7_P_2,
1885   VEX_LEN_0F38F7_P_3,
1886   VEX_LEN_0F3A00_P_2,
1887   VEX_LEN_0F3A01_P_2,
1888   VEX_LEN_0F3A06_P_2,
1889   VEX_LEN_0F3A14_P_2,
1890   VEX_LEN_0F3A15_P_2,
1891   VEX_LEN_0F3A16_P_2,
1892   VEX_LEN_0F3A17_P_2,
1893   VEX_LEN_0F3A18_P_2,
1894   VEX_LEN_0F3A19_P_2,
1895   VEX_LEN_0F3A20_P_2,
1896   VEX_LEN_0F3A21_P_2,
1897   VEX_LEN_0F3A22_P_2,
1898   VEX_LEN_0F3A30_P_2,
1899   VEX_LEN_0F3A31_P_2,
1900   VEX_LEN_0F3A32_P_2,
1901   VEX_LEN_0F3A33_P_2,
1902   VEX_LEN_0F3A38_P_2,
1903   VEX_LEN_0F3A39_P_2,
1904   VEX_LEN_0F3A41_P_2,
1905   VEX_LEN_0F3A46_P_2,
1906   VEX_LEN_0F3A60_P_2,
1907   VEX_LEN_0F3A61_P_2,
1908   VEX_LEN_0F3A62_P_2,
1909   VEX_LEN_0F3A63_P_2,
1910   VEX_LEN_0F3A6A_P_2,
1911   VEX_LEN_0F3A6B_P_2,
1912   VEX_LEN_0F3A6E_P_2,
1913   VEX_LEN_0F3A6F_P_2,
1914   VEX_LEN_0F3A7A_P_2,
1915   VEX_LEN_0F3A7B_P_2,
1916   VEX_LEN_0F3A7E_P_2,
1917   VEX_LEN_0F3A7F_P_2,
1918   VEX_LEN_0F3ADF_P_2,
1919   VEX_LEN_0F3AF0_P_3,
1920   VEX_LEN_0FXOP_08_CC,
1921   VEX_LEN_0FXOP_08_CD,
1922   VEX_LEN_0FXOP_08_CE,
1923   VEX_LEN_0FXOP_08_CF,
1924   VEX_LEN_0FXOP_08_EC,
1925   VEX_LEN_0FXOP_08_ED,
1926   VEX_LEN_0FXOP_08_EE,
1927   VEX_LEN_0FXOP_08_EF,
1928   VEX_LEN_0FXOP_09_80,
1929   VEX_LEN_0FXOP_09_81
1930 };
1931
1932 enum
1933 {
1934   VEX_W_0F41_P_0_LEN_1 = 0,
1935   VEX_W_0F41_P_2_LEN_1,
1936   VEX_W_0F42_P_0_LEN_1,
1937   VEX_W_0F42_P_2_LEN_1,
1938   VEX_W_0F44_P_0_LEN_0,
1939   VEX_W_0F44_P_2_LEN_0,
1940   VEX_W_0F45_P_0_LEN_1,
1941   VEX_W_0F45_P_2_LEN_1,
1942   VEX_W_0F46_P_0_LEN_1,
1943   VEX_W_0F46_P_2_LEN_1,
1944   VEX_W_0F47_P_0_LEN_1,
1945   VEX_W_0F47_P_2_LEN_1,
1946   VEX_W_0F4A_P_0_LEN_1,
1947   VEX_W_0F4A_P_2_LEN_1,
1948   VEX_W_0F4B_P_0_LEN_1,
1949   VEX_W_0F4B_P_2_LEN_1,
1950   VEX_W_0F90_P_0_LEN_0,
1951   VEX_W_0F90_P_2_LEN_0,
1952   VEX_W_0F91_P_0_LEN_0,
1953   VEX_W_0F91_P_2_LEN_0,
1954   VEX_W_0F92_P_0_LEN_0,
1955   VEX_W_0F92_P_2_LEN_0,
1956   VEX_W_0F92_P_3_LEN_0,
1957   VEX_W_0F93_P_0_LEN_0,
1958   VEX_W_0F93_P_2_LEN_0,
1959   VEX_W_0F93_P_3_LEN_0,
1960   VEX_W_0F98_P_0_LEN_0,
1961   VEX_W_0F98_P_2_LEN_0,
1962   VEX_W_0F99_P_0_LEN_0,
1963   VEX_W_0F99_P_2_LEN_0,
1964   VEX_W_0FC4_P_2,
1965   VEX_W_0FC5_P_2,
1966   VEX_W_0F380C_P_2,
1967   VEX_W_0F380D_P_2,
1968   VEX_W_0F380E_P_2,
1969   VEX_W_0F380F_P_2,
1970   VEX_W_0F3816_P_2,
1971   VEX_W_0F3818_P_2,
1972   VEX_W_0F3819_P_2,
1973   VEX_W_0F381A_P_2_M_0,
1974   VEX_W_0F382C_P_2_M_0,
1975   VEX_W_0F382D_P_2_M_0,
1976   VEX_W_0F382E_P_2_M_0,
1977   VEX_W_0F382F_P_2_M_0,
1978   VEX_W_0F3836_P_2,
1979   VEX_W_0F3846_P_2,
1980   VEX_W_0F3858_P_2,
1981   VEX_W_0F3859_P_2,
1982   VEX_W_0F385A_P_2_M_0,
1983   VEX_W_0F3878_P_2,
1984   VEX_W_0F3879_P_2,
1985   VEX_W_0F38CF_P_2,
1986   VEX_W_0F3A00_P_2,
1987   VEX_W_0F3A01_P_2,
1988   VEX_W_0F3A02_P_2,
1989   VEX_W_0F3A04_P_2,
1990   VEX_W_0F3A05_P_2,
1991   VEX_W_0F3A06_P_2,
1992   VEX_W_0F3A14_P_2,
1993   VEX_W_0F3A15_P_2,
1994   VEX_W_0F3A18_P_2,
1995   VEX_W_0F3A19_P_2,
1996   VEX_W_0F3A20_P_2,
1997   VEX_W_0F3A30_P_2_LEN_0,
1998   VEX_W_0F3A31_P_2_LEN_0,
1999   VEX_W_0F3A32_P_2_LEN_0,
2000   VEX_W_0F3A33_P_2_LEN_0,
2001   VEX_W_0F3A38_P_2,
2002   VEX_W_0F3A39_P_2,
2003   VEX_W_0F3A46_P_2,
2004   VEX_W_0F3A48_P_2,
2005   VEX_W_0F3A49_P_2,
2006   VEX_W_0F3A4A_P_2,
2007   VEX_W_0F3A4B_P_2,
2008   VEX_W_0F3A4C_P_2,
2009   VEX_W_0F3ACE_P_2,
2010   VEX_W_0F3ACF_P_2,
2011
2012   EVEX_W_0F10_P_0,
2013   EVEX_W_0F10_P_1_M_0,
2014   EVEX_W_0F10_P_1_M_1,
2015   EVEX_W_0F10_P_2,
2016   EVEX_W_0F10_P_3_M_0,
2017   EVEX_W_0F10_P_3_M_1,
2018   EVEX_W_0F11_P_0,
2019   EVEX_W_0F11_P_1_M_0,
2020   EVEX_W_0F11_P_1_M_1,
2021   EVEX_W_0F11_P_2,
2022   EVEX_W_0F11_P_3_M_0,
2023   EVEX_W_0F11_P_3_M_1,
2024   EVEX_W_0F12_P_0_M_0,
2025   EVEX_W_0F12_P_0_M_1,
2026   EVEX_W_0F12_P_1,
2027   EVEX_W_0F12_P_2,
2028   EVEX_W_0F12_P_3,
2029   EVEX_W_0F13_P_0,
2030   EVEX_W_0F13_P_2,
2031   EVEX_W_0F14_P_0,
2032   EVEX_W_0F14_P_2,
2033   EVEX_W_0F15_P_0,
2034   EVEX_W_0F15_P_2,
2035   EVEX_W_0F16_P_0_M_0,
2036   EVEX_W_0F16_P_0_M_1,
2037   EVEX_W_0F16_P_1,
2038   EVEX_W_0F16_P_2,
2039   EVEX_W_0F17_P_0,
2040   EVEX_W_0F17_P_2,
2041   EVEX_W_0F28_P_0,
2042   EVEX_W_0F28_P_2,
2043   EVEX_W_0F29_P_0,
2044   EVEX_W_0F29_P_2,
2045   EVEX_W_0F2A_P_1,
2046   EVEX_W_0F2A_P_3,
2047   EVEX_W_0F2B_P_0,
2048   EVEX_W_0F2B_P_2,
2049   EVEX_W_0F2E_P_0,
2050   EVEX_W_0F2E_P_2,
2051   EVEX_W_0F2F_P_0,
2052   EVEX_W_0F2F_P_2,
2053   EVEX_W_0F51_P_0,
2054   EVEX_W_0F51_P_1,
2055   EVEX_W_0F51_P_2,
2056   EVEX_W_0F51_P_3,
2057   EVEX_W_0F54_P_0,
2058   EVEX_W_0F54_P_2,
2059   EVEX_W_0F55_P_0,
2060   EVEX_W_0F55_P_2,
2061   EVEX_W_0F56_P_0,
2062   EVEX_W_0F56_P_2,
2063   EVEX_W_0F57_P_0,
2064   EVEX_W_0F57_P_2,
2065   EVEX_W_0F58_P_0,
2066   EVEX_W_0F58_P_1,
2067   EVEX_W_0F58_P_2,
2068   EVEX_W_0F58_P_3,
2069   EVEX_W_0F59_P_0,
2070   EVEX_W_0F59_P_1,
2071   EVEX_W_0F59_P_2,
2072   EVEX_W_0F59_P_3,
2073   EVEX_W_0F5A_P_0,
2074   EVEX_W_0F5A_P_1,
2075   EVEX_W_0F5A_P_2,
2076   EVEX_W_0F5A_P_3,
2077   EVEX_W_0F5B_P_0,
2078   EVEX_W_0F5B_P_1,
2079   EVEX_W_0F5B_P_2,
2080   EVEX_W_0F5C_P_0,
2081   EVEX_W_0F5C_P_1,
2082   EVEX_W_0F5C_P_2,
2083   EVEX_W_0F5C_P_3,
2084   EVEX_W_0F5D_P_0,
2085   EVEX_W_0F5D_P_1,
2086   EVEX_W_0F5D_P_2,
2087   EVEX_W_0F5D_P_3,
2088   EVEX_W_0F5E_P_0,
2089   EVEX_W_0F5E_P_1,
2090   EVEX_W_0F5E_P_2,
2091   EVEX_W_0F5E_P_3,
2092   EVEX_W_0F5F_P_0,
2093   EVEX_W_0F5F_P_1,
2094   EVEX_W_0F5F_P_2,
2095   EVEX_W_0F5F_P_3,
2096   EVEX_W_0F62_P_2,
2097   EVEX_W_0F66_P_2,
2098   EVEX_W_0F6A_P_2,
2099   EVEX_W_0F6B_P_2,
2100   EVEX_W_0F6C_P_2,
2101   EVEX_W_0F6D_P_2,
2102   EVEX_W_0F6E_P_2,
2103   EVEX_W_0F6F_P_1,
2104   EVEX_W_0F6F_P_2,
2105   EVEX_W_0F6F_P_3,
2106   EVEX_W_0F70_P_2,
2107   EVEX_W_0F72_R_2_P_2,
2108   EVEX_W_0F72_R_6_P_2,
2109   EVEX_W_0F73_R_2_P_2,
2110   EVEX_W_0F73_R_6_P_2,
2111   EVEX_W_0F76_P_2,
2112   EVEX_W_0F78_P_0,
2113   EVEX_W_0F78_P_2,
2114   EVEX_W_0F79_P_0,
2115   EVEX_W_0F79_P_2,
2116   EVEX_W_0F7A_P_1,
2117   EVEX_W_0F7A_P_2,
2118   EVEX_W_0F7A_P_3,
2119   EVEX_W_0F7B_P_1,
2120   EVEX_W_0F7B_P_2,
2121   EVEX_W_0F7B_P_3,
2122   EVEX_W_0F7E_P_1,
2123   EVEX_W_0F7E_P_2,
2124   EVEX_W_0F7F_P_1,
2125   EVEX_W_0F7F_P_2,
2126   EVEX_W_0F7F_P_3,
2127   EVEX_W_0FC2_P_0,
2128   EVEX_W_0FC2_P_1,
2129   EVEX_W_0FC2_P_2,
2130   EVEX_W_0FC2_P_3,
2131   EVEX_W_0FC6_P_0,
2132   EVEX_W_0FC6_P_2,
2133   EVEX_W_0FD2_P_2,
2134   EVEX_W_0FD3_P_2,
2135   EVEX_W_0FD4_P_2,
2136   EVEX_W_0FD6_P_2,
2137   EVEX_W_0FE6_P_1,
2138   EVEX_W_0FE6_P_2,
2139   EVEX_W_0FE6_P_3,
2140   EVEX_W_0FE7_P_2,
2141   EVEX_W_0FF2_P_2,
2142   EVEX_W_0FF3_P_2,
2143   EVEX_W_0FF4_P_2,
2144   EVEX_W_0FFA_P_2,
2145   EVEX_W_0FFB_P_2,
2146   EVEX_W_0FFE_P_2,
2147   EVEX_W_0F380C_P_2,
2148   EVEX_W_0F380D_P_2,
2149   EVEX_W_0F3810_P_1,
2150   EVEX_W_0F3810_P_2,
2151   EVEX_W_0F3811_P_1,
2152   EVEX_W_0F3811_P_2,
2153   EVEX_W_0F3812_P_1,
2154   EVEX_W_0F3812_P_2,
2155   EVEX_W_0F3813_P_1,
2156   EVEX_W_0F3813_P_2,
2157   EVEX_W_0F3814_P_1,
2158   EVEX_W_0F3815_P_1,
2159   EVEX_W_0F3818_P_2,
2160   EVEX_W_0F3819_P_2,
2161   EVEX_W_0F381A_P_2,
2162   EVEX_W_0F381B_P_2,
2163   EVEX_W_0F381E_P_2,
2164   EVEX_W_0F381F_P_2,
2165   EVEX_W_0F3820_P_1,
2166   EVEX_W_0F3821_P_1,
2167   EVEX_W_0F3822_P_1,
2168   EVEX_W_0F3823_P_1,
2169   EVEX_W_0F3824_P_1,
2170   EVEX_W_0F3825_P_1,
2171   EVEX_W_0F3825_P_2,
2172   EVEX_W_0F3826_P_1,
2173   EVEX_W_0F3826_P_2,
2174   EVEX_W_0F3828_P_1,
2175   EVEX_W_0F3828_P_2,
2176   EVEX_W_0F3829_P_1,
2177   EVEX_W_0F3829_P_2,
2178   EVEX_W_0F382A_P_1,
2179   EVEX_W_0F382A_P_2,
2180   EVEX_W_0F382B_P_2,
2181   EVEX_W_0F3830_P_1,
2182   EVEX_W_0F3831_P_1,
2183   EVEX_W_0F3832_P_1,
2184   EVEX_W_0F3833_P_1,
2185   EVEX_W_0F3834_P_1,
2186   EVEX_W_0F3835_P_1,
2187   EVEX_W_0F3835_P_2,
2188   EVEX_W_0F3837_P_2,
2189   EVEX_W_0F3838_P_1,
2190   EVEX_W_0F3839_P_1,
2191   EVEX_W_0F383A_P_1,
2192   EVEX_W_0F3840_P_2,
2193   EVEX_W_0F3854_P_2,
2194   EVEX_W_0F3855_P_2,
2195   EVEX_W_0F3858_P_2,
2196   EVEX_W_0F3859_P_2,
2197   EVEX_W_0F385A_P_2,
2198   EVEX_W_0F385B_P_2,
2199   EVEX_W_0F3862_P_2,
2200   EVEX_W_0F3863_P_2,
2201   EVEX_W_0F3866_P_2,
2202   EVEX_W_0F3870_P_2,
2203   EVEX_W_0F3871_P_2,
2204   EVEX_W_0F3872_P_2,
2205   EVEX_W_0F3873_P_2,
2206   EVEX_W_0F3875_P_2,
2207   EVEX_W_0F3878_P_2,
2208   EVEX_W_0F3879_P_2,
2209   EVEX_W_0F387A_P_2,
2210   EVEX_W_0F387B_P_2,
2211   EVEX_W_0F387D_P_2,
2212   EVEX_W_0F3883_P_2,
2213   EVEX_W_0F388D_P_2,
2214   EVEX_W_0F3891_P_2,
2215   EVEX_W_0F3893_P_2,
2216   EVEX_W_0F38A1_P_2,
2217   EVEX_W_0F38A3_P_2,
2218   EVEX_W_0F38C7_R_1_P_2,
2219   EVEX_W_0F38C7_R_2_P_2,
2220   EVEX_W_0F38C7_R_5_P_2,
2221   EVEX_W_0F38C7_R_6_P_2,
2222
2223   EVEX_W_0F3A00_P_2,
2224   EVEX_W_0F3A01_P_2,
2225   EVEX_W_0F3A04_P_2,
2226   EVEX_W_0F3A05_P_2,
2227   EVEX_W_0F3A08_P_2,
2228   EVEX_W_0F3A09_P_2,
2229   EVEX_W_0F3A0A_P_2,
2230   EVEX_W_0F3A0B_P_2,
2231   EVEX_W_0F3A16_P_2,
2232   EVEX_W_0F3A18_P_2,
2233   EVEX_W_0F3A19_P_2,
2234   EVEX_W_0F3A1A_P_2,
2235   EVEX_W_0F3A1B_P_2,
2236   EVEX_W_0F3A1D_P_2,
2237   EVEX_W_0F3A21_P_2,
2238   EVEX_W_0F3A22_P_2,
2239   EVEX_W_0F3A23_P_2,
2240   EVEX_W_0F3A38_P_2,
2241   EVEX_W_0F3A39_P_2,
2242   EVEX_W_0F3A3A_P_2,
2243   EVEX_W_0F3A3B_P_2,
2244   EVEX_W_0F3A3E_P_2,
2245   EVEX_W_0F3A3F_P_2,
2246   EVEX_W_0F3A42_P_2,
2247   EVEX_W_0F3A43_P_2,
2248   EVEX_W_0F3A50_P_2,
2249   EVEX_W_0F3A51_P_2,
2250   EVEX_W_0F3A56_P_2,
2251   EVEX_W_0F3A57_P_2,
2252   EVEX_W_0F3A66_P_2,
2253   EVEX_W_0F3A67_P_2,
2254   EVEX_W_0F3A70_P_2,
2255   EVEX_W_0F3A71_P_2,
2256   EVEX_W_0F3A72_P_2,
2257   EVEX_W_0F3A73_P_2,
2258   EVEX_W_0F3ACE_P_2,
2259   EVEX_W_0F3ACF_P_2
2260 };
2261
2262 typedef void (*op_rtn) (int bytemode, int sizeflag);
2263
2264 struct dis386 {
2265   const char *name;
2266   struct
2267     {
2268       op_rtn rtn;
2269       int bytemode;
2270     } op[MAX_OPERANDS];
2271   unsigned int prefix_requirement;
2272 };
2273
2274 /* Upper case letters in the instruction names here are macros.
2275    'A' => print 'b' if no register operands or suffix_always is true
2276    'B' => print 'b' if suffix_always is true
2277    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2278           size prefix
2279    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2280           suffix_always is true
2281    'E' => print 'e' if 32-bit form of jcxz
2282    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2283    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2284    'H' => print ",pt" or ",pn" branch hint
2285    'I' => honor following macro letter even in Intel mode (implemented only
2286           for some of the macro letters)
2287    'J' => print 'l'
2288    'K' => print 'd' or 'q' if rex prefix is present.
2289    'L' => print 'l' if suffix_always is true
2290    'M' => print 'r' if intel_mnemonic is false.
2291    'N' => print 'n' if instruction has no wait "prefix"
2292    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2293    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2294           or suffix_always is true.  print 'q' if rex prefix is present.
2295    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2296           is true
2297    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2298    'S' => print 'w', 'l' or 'q' if suffix_always is true
2299    'T' => print 'q' in 64bit mode if instruction has no operand size
2300           prefix and behave as 'P' otherwise
2301    'U' => print 'q' in 64bit mode if instruction has no operand size
2302           prefix and behave as 'Q' otherwise
2303    'V' => print 'q' in 64bit mode if instruction has no operand size
2304           prefix and behave as 'S' otherwise
2305    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2306    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2307    'Y' unused.
2308    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2309    '!' => change condition from true to false or from false to true.
2310    '%' => add 1 upper case letter to the macro.
2311    '^' => print 'w' or 'l' depending on operand size prefix or
2312           suffix_always is true (lcall/ljmp).
2313    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2314           on operand size prefix.
2315    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2316           has no operand size prefix for AMD64 ISA, behave as 'P'
2317           otherwise
2318
2319    2 upper case letter macros:
2320    "XY" => print 'x' or 'y' if suffix_always is true or no register
2321            operands and no broadcast.
2322    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2323            register operands and no broadcast.
2324    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2325    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2326            or suffix_always is true
2327    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2328    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2329    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2330    "LW" => print 'd', 'q' depending on the VEX.W bit
2331    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2332            an operand size prefix, or suffix_always is true.  print
2333            'q' if rex prefix is present.
2334
2335    Many of the above letters print nothing in Intel mode.  See "putop"
2336    for the details.
2337
2338    Braces '{' and '}', and vertical bars '|', indicate alternative
2339    mnemonic strings for AT&T and Intel.  */
2340
2341 static const struct dis386 dis386[] = {
2342   /* 00 */
2343   { "addB",             { Ebh1, Gb }, 0 },
2344   { "addS",             { Evh1, Gv }, 0 },
2345   { "addB",             { Gb, EbS }, 0 },
2346   { "addS",             { Gv, EvS }, 0 },
2347   { "addB",             { AL, Ib }, 0 },
2348   { "addS",             { eAX, Iv }, 0 },
2349   { X86_64_TABLE (X86_64_06) },
2350   { X86_64_TABLE (X86_64_07) },
2351   /* 08 */
2352   { "orB",              { Ebh1, Gb }, 0 },
2353   { "orS",              { Evh1, Gv }, 0 },
2354   { "orB",              { Gb, EbS }, 0 },
2355   { "orS",              { Gv, EvS }, 0 },
2356   { "orB",              { AL, Ib }, 0 },
2357   { "orS",              { eAX, Iv }, 0 },
2358   { X86_64_TABLE (X86_64_0D) },
2359   { Bad_Opcode },       /* 0x0f extended opcode escape */
2360   /* 10 */
2361   { "adcB",             { Ebh1, Gb }, 0 },
2362   { "adcS",             { Evh1, Gv }, 0 },
2363   { "adcB",             { Gb, EbS }, 0 },
2364   { "adcS",             { Gv, EvS }, 0 },
2365   { "adcB",             { AL, Ib }, 0 },
2366   { "adcS",             { eAX, Iv }, 0 },
2367   { X86_64_TABLE (X86_64_16) },
2368   { X86_64_TABLE (X86_64_17) },
2369   /* 18 */
2370   { "sbbB",             { Ebh1, Gb }, 0 },
2371   { "sbbS",             { Evh1, Gv }, 0 },
2372   { "sbbB",             { Gb, EbS }, 0 },
2373   { "sbbS",             { Gv, EvS }, 0 },
2374   { "sbbB",             { AL, Ib }, 0 },
2375   { "sbbS",             { eAX, Iv }, 0 },
2376   { X86_64_TABLE (X86_64_1E) },
2377   { X86_64_TABLE (X86_64_1F) },
2378   /* 20 */
2379   { "andB",             { Ebh1, Gb }, 0 },
2380   { "andS",             { Evh1, Gv }, 0 },
2381   { "andB",             { Gb, EbS }, 0 },
2382   { "andS",             { Gv, EvS }, 0 },
2383   { "andB",             { AL, Ib }, 0 },
2384   { "andS",             { eAX, Iv }, 0 },
2385   { Bad_Opcode },       /* SEG ES prefix */
2386   { X86_64_TABLE (X86_64_27) },
2387   /* 28 */
2388   { "subB",             { Ebh1, Gb }, 0 },
2389   { "subS",             { Evh1, Gv }, 0 },
2390   { "subB",             { Gb, EbS }, 0 },
2391   { "subS",             { Gv, EvS }, 0 },
2392   { "subB",             { AL, Ib }, 0 },
2393   { "subS",             { eAX, Iv }, 0 },
2394   { Bad_Opcode },       /* SEG CS prefix */
2395   { X86_64_TABLE (X86_64_2F) },
2396   /* 30 */
2397   { "xorB",             { Ebh1, Gb }, 0 },
2398   { "xorS",             { Evh1, Gv }, 0 },
2399   { "xorB",             { Gb, EbS }, 0 },
2400   { "xorS",             { Gv, EvS }, 0 },
2401   { "xorB",             { AL, Ib }, 0 },
2402   { "xorS",             { eAX, Iv }, 0 },
2403   { Bad_Opcode },       /* SEG SS prefix */
2404   { X86_64_TABLE (X86_64_37) },
2405   /* 38 */
2406   { "cmpB",             { Eb, Gb }, 0 },
2407   { "cmpS",             { Ev, Gv }, 0 },
2408   { "cmpB",             { Gb, EbS }, 0 },
2409   { "cmpS",             { Gv, EvS }, 0 },
2410   { "cmpB",             { AL, Ib }, 0 },
2411   { "cmpS",             { eAX, Iv }, 0 },
2412   { Bad_Opcode },       /* SEG DS prefix */
2413   { X86_64_TABLE (X86_64_3F) },
2414   /* 40 */
2415   { "inc{S|}",          { RMeAX }, 0 },
2416   { "inc{S|}",          { RMeCX }, 0 },
2417   { "inc{S|}",          { RMeDX }, 0 },
2418   { "inc{S|}",          { RMeBX }, 0 },
2419   { "inc{S|}",          { RMeSP }, 0 },
2420   { "inc{S|}",          { RMeBP }, 0 },
2421   { "inc{S|}",          { RMeSI }, 0 },
2422   { "inc{S|}",          { RMeDI }, 0 },
2423   /* 48 */
2424   { "dec{S|}",          { RMeAX }, 0 },
2425   { "dec{S|}",          { RMeCX }, 0 },
2426   { "dec{S|}",          { RMeDX }, 0 },
2427   { "dec{S|}",          { RMeBX }, 0 },
2428   { "dec{S|}",          { RMeSP }, 0 },
2429   { "dec{S|}",          { RMeBP }, 0 },
2430   { "dec{S|}",          { RMeSI }, 0 },
2431   { "dec{S|}",          { RMeDI }, 0 },
2432   /* 50 */
2433   { "pushV",            { RMrAX }, 0 },
2434   { "pushV",            { RMrCX }, 0 },
2435   { "pushV",            { RMrDX }, 0 },
2436   { "pushV",            { RMrBX }, 0 },
2437   { "pushV",            { RMrSP }, 0 },
2438   { "pushV",            { RMrBP }, 0 },
2439   { "pushV",            { RMrSI }, 0 },
2440   { "pushV",            { RMrDI }, 0 },
2441   /* 58 */
2442   { "popV",             { RMrAX }, 0 },
2443   { "popV",             { RMrCX }, 0 },
2444   { "popV",             { RMrDX }, 0 },
2445   { "popV",             { RMrBX }, 0 },
2446   { "popV",             { RMrSP }, 0 },
2447   { "popV",             { RMrBP }, 0 },
2448   { "popV",             { RMrSI }, 0 },
2449   { "popV",             { RMrDI }, 0 },
2450   /* 60 */
2451   { X86_64_TABLE (X86_64_60) },
2452   { X86_64_TABLE (X86_64_61) },
2453   { X86_64_TABLE (X86_64_62) },
2454   { X86_64_TABLE (X86_64_63) },
2455   { Bad_Opcode },       /* seg fs */
2456   { Bad_Opcode },       /* seg gs */
2457   { Bad_Opcode },       /* op size prefix */
2458   { Bad_Opcode },       /* adr size prefix */
2459   /* 68 */
2460   { "pushT",            { sIv }, 0 },
2461   { "imulS",            { Gv, Ev, Iv }, 0 },
2462   { "pushT",            { sIbT }, 0 },
2463   { "imulS",            { Gv, Ev, sIb }, 0 },
2464   { "ins{b|}",          { Ybr, indirDX }, 0 },
2465   { X86_64_TABLE (X86_64_6D) },
2466   { "outs{b|}",         { indirDXr, Xb }, 0 },
2467   { X86_64_TABLE (X86_64_6F) },
2468   /* 70 */
2469   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2470   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2471   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2472   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2473   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2474   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2475   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2476   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2477   /* 78 */
2478   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2479   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2480   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2481   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2482   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2483   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2484   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2485   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2486   /* 80 */
2487   { REG_TABLE (REG_80) },
2488   { REG_TABLE (REG_81) },
2489   { X86_64_TABLE (X86_64_82) },
2490   { REG_TABLE (REG_83) },
2491   { "testB",            { Eb, Gb }, 0 },
2492   { "testS",            { Ev, Gv }, 0 },
2493   { "xchgB",            { Ebh2, Gb }, 0 },
2494   { "xchgS",            { Evh2, Gv }, 0 },
2495   /* 88 */
2496   { "movB",             { Ebh3, Gb }, 0 },
2497   { "movS",             { Evh3, Gv }, 0 },
2498   { "movB",             { Gb, EbS }, 0 },
2499   { "movS",             { Gv, EvS }, 0 },
2500   { "movD",             { Sv, Sw }, 0 },
2501   { MOD_TABLE (MOD_8D) },
2502   { "movD",             { Sw, Sv }, 0 },
2503   { REG_TABLE (REG_8F) },
2504   /* 90 */
2505   { PREFIX_TABLE (PREFIX_90) },
2506   { "xchgS",            { RMeCX, eAX }, 0 },
2507   { "xchgS",            { RMeDX, eAX }, 0 },
2508   { "xchgS",            { RMeBX, eAX }, 0 },
2509   { "xchgS",            { RMeSP, eAX }, 0 },
2510   { "xchgS",            { RMeBP, eAX }, 0 },
2511   { "xchgS",            { RMeSI, eAX }, 0 },
2512   { "xchgS",            { RMeDI, eAX }, 0 },
2513   /* 98 */
2514   { "cW{t|}R",          { XX }, 0 },
2515   { "cR{t|}O",          { XX }, 0 },
2516   { X86_64_TABLE (X86_64_9A) },
2517   { Bad_Opcode },       /* fwait */
2518   { "pushfT",           { XX }, 0 },
2519   { "popfT",            { XX }, 0 },
2520   { "sahf",             { XX }, 0 },
2521   { "lahf",             { XX }, 0 },
2522   /* a0 */
2523   { "mov%LB",           { AL, Ob }, 0 },
2524   { "mov%LS",           { eAX, Ov }, 0 },
2525   { "mov%LB",           { Ob, AL }, 0 },
2526   { "mov%LS",           { Ov, eAX }, 0 },
2527   { "movs{b|}",         { Ybr, Xb }, 0 },
2528   { "movs{R|}",         { Yvr, Xv }, 0 },
2529   { "cmps{b|}",         { Xb, Yb }, 0 },
2530   { "cmps{R|}",         { Xv, Yv }, 0 },
2531   /* a8 */
2532   { "testB",            { AL, Ib }, 0 },
2533   { "testS",            { eAX, Iv }, 0 },
2534   { "stosB",            { Ybr, AL }, 0 },
2535   { "stosS",            { Yvr, eAX }, 0 },
2536   { "lodsB",            { ALr, Xb }, 0 },
2537   { "lodsS",            { eAXr, Xv }, 0 },
2538   { "scasB",            { AL, Yb }, 0 },
2539   { "scasS",            { eAX, Yv }, 0 },
2540   /* b0 */
2541   { "movB",             { RMAL, Ib }, 0 },
2542   { "movB",             { RMCL, Ib }, 0 },
2543   { "movB",             { RMDL, Ib }, 0 },
2544   { "movB",             { RMBL, Ib }, 0 },
2545   { "movB",             { RMAH, Ib }, 0 },
2546   { "movB",             { RMCH, Ib }, 0 },
2547   { "movB",             { RMDH, Ib }, 0 },
2548   { "movB",             { RMBH, Ib }, 0 },
2549   /* b8 */
2550   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2551   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2552   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2553   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2554   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2555   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2556   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2557   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2558   /* c0 */
2559   { REG_TABLE (REG_C0) },
2560   { REG_TABLE (REG_C1) },
2561   { "retT",             { Iw, BND }, 0 },
2562   { "retT",             { BND }, 0 },
2563   { X86_64_TABLE (X86_64_C4) },
2564   { X86_64_TABLE (X86_64_C5) },
2565   { REG_TABLE (REG_C6) },
2566   { REG_TABLE (REG_C7) },
2567   /* c8 */
2568   { "enterT",           { Iw, Ib }, 0 },
2569   { "leaveT",           { XX }, 0 },
2570   { "Jret{|f}P",        { Iw }, 0 },
2571   { "Jret{|f}P",        { XX }, 0 },
2572   { "int3",             { XX }, 0 },
2573   { "int",              { Ib }, 0 },
2574   { X86_64_TABLE (X86_64_CE) },
2575   { "iret%LP",          { XX }, 0 },
2576   /* d0 */
2577   { REG_TABLE (REG_D0) },
2578   { REG_TABLE (REG_D1) },
2579   { REG_TABLE (REG_D2) },
2580   { REG_TABLE (REG_D3) },
2581   { X86_64_TABLE (X86_64_D4) },
2582   { X86_64_TABLE (X86_64_D5) },
2583   { Bad_Opcode },
2584   { "xlat",             { DSBX }, 0 },
2585   /* d8 */
2586   { FLOAT },
2587   { FLOAT },
2588   { FLOAT },
2589   { FLOAT },
2590   { FLOAT },
2591   { FLOAT },
2592   { FLOAT },
2593   { FLOAT },
2594   /* e0 */
2595   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2596   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2597   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2598   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2599   { "inB",              { AL, Ib }, 0 },
2600   { "inG",              { zAX, Ib }, 0 },
2601   { "outB",             { Ib, AL }, 0 },
2602   { "outG",             { Ib, zAX }, 0 },
2603   /* e8 */
2604   { X86_64_TABLE (X86_64_E8) },
2605   { X86_64_TABLE (X86_64_E9) },
2606   { X86_64_TABLE (X86_64_EA) },
2607   { "jmp",              { Jb, BND }, 0 },
2608   { "inB",              { AL, indirDX }, 0 },
2609   { "inG",              { zAX, indirDX }, 0 },
2610   { "outB",             { indirDX, AL }, 0 },
2611   { "outG",             { indirDX, zAX }, 0 },
2612   /* f0 */
2613   { Bad_Opcode },       /* lock prefix */
2614   { "icebp",            { XX }, 0 },
2615   { Bad_Opcode },       /* repne */
2616   { Bad_Opcode },       /* repz */
2617   { "hlt",              { XX }, 0 },
2618   { "cmc",              { XX }, 0 },
2619   { REG_TABLE (REG_F6) },
2620   { REG_TABLE (REG_F7) },
2621   /* f8 */
2622   { "clc",              { XX }, 0 },
2623   { "stc",              { XX }, 0 },
2624   { "cli",              { XX }, 0 },
2625   { "sti",              { XX }, 0 },
2626   { "cld",              { XX }, 0 },
2627   { "std",              { XX }, 0 },
2628   { REG_TABLE (REG_FE) },
2629   { REG_TABLE (REG_FF) },
2630 };
2631
2632 static const struct dis386 dis386_twobyte[] = {
2633   /* 00 */
2634   { REG_TABLE (REG_0F00 ) },
2635   { REG_TABLE (REG_0F01 ) },
2636   { "larS",             { Gv, Ew }, 0 },
2637   { "lslS",             { Gv, Ew }, 0 },
2638   { Bad_Opcode },
2639   { "syscall",          { XX }, 0 },
2640   { "clts",             { XX }, 0 },
2641   { "sysret%LP",                { XX }, 0 },
2642   /* 08 */
2643   { "invd",             { XX }, 0 },
2644   { PREFIX_TABLE (PREFIX_0F09) },
2645   { Bad_Opcode },
2646   { "ud2",              { XX }, 0 },
2647   { Bad_Opcode },
2648   { REG_TABLE (REG_0F0D) },
2649   { "femms",            { XX }, 0 },
2650   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2651   /* 10 */
2652   { PREFIX_TABLE (PREFIX_0F10) },
2653   { PREFIX_TABLE (PREFIX_0F11) },
2654   { PREFIX_TABLE (PREFIX_0F12) },
2655   { MOD_TABLE (MOD_0F13) },
2656   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2657   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2658   { PREFIX_TABLE (PREFIX_0F16) },
2659   { MOD_TABLE (MOD_0F17) },
2660   /* 18 */
2661   { REG_TABLE (REG_0F18) },
2662   { "nopQ",             { Ev }, 0 },
2663   { PREFIX_TABLE (PREFIX_0F1A) },
2664   { PREFIX_TABLE (PREFIX_0F1B) },
2665   { PREFIX_TABLE (PREFIX_0F1C) },
2666   { "nopQ",             { Ev }, 0 },
2667   { PREFIX_TABLE (PREFIX_0F1E) },
2668   { "nopQ",             { Ev }, 0 },
2669   /* 20 */
2670   { "movZ",             { Rm, Cm }, 0 },
2671   { "movZ",             { Rm, Dm }, 0 },
2672   { "movZ",             { Cm, Rm }, 0 },
2673   { "movZ",             { Dm, Rm }, 0 },
2674   { MOD_TABLE (MOD_0F24) },
2675   { Bad_Opcode },
2676   { MOD_TABLE (MOD_0F26) },
2677   { Bad_Opcode },
2678   /* 28 */
2679   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2680   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2681   { PREFIX_TABLE (PREFIX_0F2A) },
2682   { PREFIX_TABLE (PREFIX_0F2B) },
2683   { PREFIX_TABLE (PREFIX_0F2C) },
2684   { PREFIX_TABLE (PREFIX_0F2D) },
2685   { PREFIX_TABLE (PREFIX_0F2E) },
2686   { PREFIX_TABLE (PREFIX_0F2F) },
2687   /* 30 */
2688   { "wrmsr",            { XX }, 0 },
2689   { "rdtsc",            { XX }, 0 },
2690   { "rdmsr",            { XX }, 0 },
2691   { "rdpmc",            { XX }, 0 },
2692   { "sysenter",         { XX }, 0 },
2693   { "sysexit",          { XX }, 0 },
2694   { Bad_Opcode },
2695   { "getsec",           { XX }, 0 },
2696   /* 38 */
2697   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2698   { Bad_Opcode },
2699   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2700   { Bad_Opcode },
2701   { Bad_Opcode },
2702   { Bad_Opcode },
2703   { Bad_Opcode },
2704   { Bad_Opcode },
2705   /* 40 */
2706   { "cmovoS",           { Gv, Ev }, 0 },
2707   { "cmovnoS",          { Gv, Ev }, 0 },
2708   { "cmovbS",           { Gv, Ev }, 0 },
2709   { "cmovaeS",          { Gv, Ev }, 0 },
2710   { "cmoveS",           { Gv, Ev }, 0 },
2711   { "cmovneS",          { Gv, Ev }, 0 },
2712   { "cmovbeS",          { Gv, Ev }, 0 },
2713   { "cmovaS",           { Gv, Ev }, 0 },
2714   /* 48 */
2715   { "cmovsS",           { Gv, Ev }, 0 },
2716   { "cmovnsS",          { Gv, Ev }, 0 },
2717   { "cmovpS",           { Gv, Ev }, 0 },
2718   { "cmovnpS",          { Gv, Ev }, 0 },
2719   { "cmovlS",           { Gv, Ev }, 0 },
2720   { "cmovgeS",          { Gv, Ev }, 0 },
2721   { "cmovleS",          { Gv, Ev }, 0 },
2722   { "cmovgS",           { Gv, Ev }, 0 },
2723   /* 50 */
2724   { MOD_TABLE (MOD_0F51) },
2725   { PREFIX_TABLE (PREFIX_0F51) },
2726   { PREFIX_TABLE (PREFIX_0F52) },
2727   { PREFIX_TABLE (PREFIX_0F53) },
2728   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2729   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2730   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2731   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2732   /* 58 */
2733   { PREFIX_TABLE (PREFIX_0F58) },
2734   { PREFIX_TABLE (PREFIX_0F59) },
2735   { PREFIX_TABLE (PREFIX_0F5A) },
2736   { PREFIX_TABLE (PREFIX_0F5B) },
2737   { PREFIX_TABLE (PREFIX_0F5C) },
2738   { PREFIX_TABLE (PREFIX_0F5D) },
2739   { PREFIX_TABLE (PREFIX_0F5E) },
2740   { PREFIX_TABLE (PREFIX_0F5F) },
2741   /* 60 */
2742   { PREFIX_TABLE (PREFIX_0F60) },
2743   { PREFIX_TABLE (PREFIX_0F61) },
2744   { PREFIX_TABLE (PREFIX_0F62) },
2745   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2746   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2747   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2748   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2749   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2750   /* 68 */
2751   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2752   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2753   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2754   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2755   { PREFIX_TABLE (PREFIX_0F6C) },
2756   { PREFIX_TABLE (PREFIX_0F6D) },
2757   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2758   { PREFIX_TABLE (PREFIX_0F6F) },
2759   /* 70 */
2760   { PREFIX_TABLE (PREFIX_0F70) },
2761   { REG_TABLE (REG_0F71) },
2762   { REG_TABLE (REG_0F72) },
2763   { REG_TABLE (REG_0F73) },
2764   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2765   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2766   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2767   { "emms",             { XX }, PREFIX_OPCODE },
2768   /* 78 */
2769   { PREFIX_TABLE (PREFIX_0F78) },
2770   { PREFIX_TABLE (PREFIX_0F79) },
2771   { Bad_Opcode },
2772   { Bad_Opcode },
2773   { PREFIX_TABLE (PREFIX_0F7C) },
2774   { PREFIX_TABLE (PREFIX_0F7D) },
2775   { PREFIX_TABLE (PREFIX_0F7E) },
2776   { PREFIX_TABLE (PREFIX_0F7F) },
2777   /* 80 */
2778   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2779   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2780   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2781   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2782   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2783   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2784   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2785   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2786   /* 88 */
2787   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2788   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2789   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2790   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2791   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2792   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2793   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2794   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2795   /* 90 */
2796   { "seto",             { Eb }, 0 },
2797   { "setno",            { Eb }, 0 },
2798   { "setb",             { Eb }, 0 },
2799   { "setae",            { Eb }, 0 },
2800   { "sete",             { Eb }, 0 },
2801   { "setne",            { Eb }, 0 },
2802   { "setbe",            { Eb }, 0 },
2803   { "seta",             { Eb }, 0 },
2804   /* 98 */
2805   { "sets",             { Eb }, 0 },
2806   { "setns",            { Eb }, 0 },
2807   { "setp",             { Eb }, 0 },
2808   { "setnp",            { Eb }, 0 },
2809   { "setl",             { Eb }, 0 },
2810   { "setge",            { Eb }, 0 },
2811   { "setle",            { Eb }, 0 },
2812   { "setg",             { Eb }, 0 },
2813   /* a0 */
2814   { "pushT",            { fs }, 0 },
2815   { "popT",             { fs }, 0 },
2816   { "cpuid",            { XX }, 0 },
2817   { "btS",              { Ev, Gv }, 0 },
2818   { "shldS",            { Ev, Gv, Ib }, 0 },
2819   { "shldS",            { Ev, Gv, CL }, 0 },
2820   { REG_TABLE (REG_0FA6) },
2821   { REG_TABLE (REG_0FA7) },
2822   /* a8 */
2823   { "pushT",            { gs }, 0 },
2824   { "popT",             { gs }, 0 },
2825   { "rsm",              { XX }, 0 },
2826   { "btsS",             { Evh1, Gv }, 0 },
2827   { "shrdS",            { Ev, Gv, Ib }, 0 },
2828   { "shrdS",            { Ev, Gv, CL }, 0 },
2829   { REG_TABLE (REG_0FAE) },
2830   { "imulS",            { Gv, Ev }, 0 },
2831   /* b0 */
2832   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2833   { "cmpxchgS",         { Evh1, Gv }, 0 },
2834   { MOD_TABLE (MOD_0FB2) },
2835   { "btrS",             { Evh1, Gv }, 0 },
2836   { MOD_TABLE (MOD_0FB4) },
2837   { MOD_TABLE (MOD_0FB5) },
2838   { "movz{bR|x}",       { Gv, Eb }, 0 },
2839   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2840   /* b8 */
2841   { PREFIX_TABLE (PREFIX_0FB8) },
2842   { "ud1S",             { Gv, Ev }, 0 },
2843   { REG_TABLE (REG_0FBA) },
2844   { "btcS",             { Evh1, Gv }, 0 },
2845   { PREFIX_TABLE (PREFIX_0FBC) },
2846   { PREFIX_TABLE (PREFIX_0FBD) },
2847   { "movs{bR|x}",       { Gv, Eb }, 0 },
2848   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2849   /* c0 */
2850   { "xaddB",            { Ebh1, Gb }, 0 },
2851   { "xaddS",            { Evh1, Gv }, 0 },
2852   { PREFIX_TABLE (PREFIX_0FC2) },
2853   { MOD_TABLE (MOD_0FC3) },
2854   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2855   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2856   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2857   { REG_TABLE (REG_0FC7) },
2858   /* c8 */
2859   { "bswap",            { RMeAX }, 0 },
2860   { "bswap",            { RMeCX }, 0 },
2861   { "bswap",            { RMeDX }, 0 },
2862   { "bswap",            { RMeBX }, 0 },
2863   { "bswap",            { RMeSP }, 0 },
2864   { "bswap",            { RMeBP }, 0 },
2865   { "bswap",            { RMeSI }, 0 },
2866   { "bswap",            { RMeDI }, 0 },
2867   /* d0 */
2868   { PREFIX_TABLE (PREFIX_0FD0) },
2869   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2870   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2871   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2872   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2873   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2874   { PREFIX_TABLE (PREFIX_0FD6) },
2875   { MOD_TABLE (MOD_0FD7) },
2876   /* d8 */
2877   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2878   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2879   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2880   { "pand",             { MX, EM }, PREFIX_OPCODE },
2881   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2882   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2883   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2884   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2885   /* e0 */
2886   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2887   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2888   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2889   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2890   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2891   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2892   { PREFIX_TABLE (PREFIX_0FE6) },
2893   { PREFIX_TABLE (PREFIX_0FE7) },
2894   /* e8 */
2895   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2896   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2897   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2898   { "por",              { MX, EM }, PREFIX_OPCODE },
2899   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2900   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2901   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2902   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2903   /* f0 */
2904   { PREFIX_TABLE (PREFIX_0FF0) },
2905   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2906   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2907   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2908   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2909   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2910   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2911   { PREFIX_TABLE (PREFIX_0FF7) },
2912   /* f8 */
2913   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2914   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2915   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2916   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2917   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2918   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2919   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2920   { "ud0S",             { Gv, Ev }, 0 },
2921 };
2922
2923 static const unsigned char onebyte_has_modrm[256] = {
2924   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2925   /*       -------------------------------        */
2926   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2927   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2928   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2929   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2930   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2931   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2932   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2933   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2934   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2935   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2936   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2937   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2938   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2939   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2940   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2941   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2942   /*       -------------------------------        */
2943   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2944 };
2945
2946 static const unsigned char twobyte_has_modrm[256] = {
2947   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2948   /*       -------------------------------        */
2949   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2950   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2951   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2952   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2953   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2954   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2955   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2956   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2957   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2958   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2959   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2960   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2961   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2962   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2963   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2964   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2965   /*       -------------------------------        */
2966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2967 };
2968
2969 static char obuf[100];
2970 static char *obufp;
2971 static char *mnemonicendp;
2972 static char scratchbuf[100];
2973 static unsigned char *start_codep;
2974 static unsigned char *insn_codep;
2975 static unsigned char *codep;
2976 static unsigned char *end_codep;
2977 static int last_lock_prefix;
2978 static int last_repz_prefix;
2979 static int last_repnz_prefix;
2980 static int last_data_prefix;
2981 static int last_addr_prefix;
2982 static int last_rex_prefix;
2983 static int last_seg_prefix;
2984 static int fwait_prefix;
2985 /* The active segment register prefix.  */
2986 static int active_seg_prefix;
2987 #define MAX_CODE_LENGTH 15
2988 /* We can up to 14 prefixes since the maximum instruction length is
2989    15bytes.  */
2990 static int all_prefixes[MAX_CODE_LENGTH - 1];
2991 static disassemble_info *the_info;
2992 static struct
2993   {
2994     int mod;
2995     int reg;
2996     int rm;
2997   }
2998 modrm;
2999 static unsigned char need_modrm;
3000 static struct
3001   {
3002     int scale;
3003     int index;
3004     int base;
3005   }
3006 sib;
3007 static struct
3008   {
3009     int register_specifier;
3010     int length;
3011     int prefix;
3012     int w;
3013     int evex;
3014     int r;
3015     int v;
3016     int mask_register_specifier;
3017     int zeroing;
3018     int ll;
3019     int b;
3020   }
3021 vex;
3022 static unsigned char need_vex;
3023 static unsigned char need_vex_reg;
3024 static unsigned char vex_w_done;
3025
3026 struct op
3027   {
3028     const char *name;
3029     unsigned int len;
3030   };
3031
3032 /* If we are accessing mod/rm/reg without need_modrm set, then the
3033    values are stale.  Hitting this abort likely indicates that you
3034    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3035 #define MODRM_CHECK  if (!need_modrm) abort ()
3036
3037 static const char **names64;
3038 static const char **names32;
3039 static const char **names16;
3040 static const char **names8;
3041 static const char **names8rex;
3042 static const char **names_seg;
3043 static const char *index64;
3044 static const char *index32;
3045 static const char **index16;
3046 static const char **names_bnd;
3047
3048 static const char *intel_names64[] = {
3049   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3050   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3051 };
3052 static const char *intel_names32[] = {
3053   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3054   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3055 };
3056 static const char *intel_names16[] = {
3057   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3058   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3059 };
3060 static const char *intel_names8[] = {
3061   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3062 };
3063 static const char *intel_names8rex[] = {
3064   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3065   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3066 };
3067 static const char *intel_names_seg[] = {
3068   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3069 };
3070 static const char *intel_index64 = "riz";
3071 static const char *intel_index32 = "eiz";
3072 static const char *intel_index16[] = {
3073   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3074 };
3075
3076 static const char *att_names64[] = {
3077   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3078   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3079 };
3080 static const char *att_names32[] = {
3081   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3082   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3083 };
3084 static const char *att_names16[] = {
3085   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3086   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3087 };
3088 static const char *att_names8[] = {
3089   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3090 };
3091 static const char *att_names8rex[] = {
3092   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3093   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3094 };
3095 static const char *att_names_seg[] = {
3096   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3097 };
3098 static const char *att_index64 = "%riz";
3099 static const char *att_index32 = "%eiz";
3100 static const char *att_index16[] = {
3101   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3102 };
3103
3104 static const char **names_mm;
3105 static const char *intel_names_mm[] = {
3106   "mm0", "mm1", "mm2", "mm3",
3107   "mm4", "mm5", "mm6", "mm7"
3108 };
3109 static const char *att_names_mm[] = {
3110   "%mm0", "%mm1", "%mm2", "%mm3",
3111   "%mm4", "%mm5", "%mm6", "%mm7"
3112 };
3113
3114 static const char *intel_names_bnd[] = {
3115   "bnd0", "bnd1", "bnd2", "bnd3"
3116 };
3117
3118 static const char *att_names_bnd[] = {
3119   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3120 };
3121
3122 static const char **names_xmm;
3123 static const char *intel_names_xmm[] = {
3124   "xmm0", "xmm1", "xmm2", "xmm3",
3125   "xmm4", "xmm5", "xmm6", "xmm7",
3126   "xmm8", "xmm9", "xmm10", "xmm11",
3127   "xmm12", "xmm13", "xmm14", "xmm15",
3128   "xmm16", "xmm17", "xmm18", "xmm19",
3129   "xmm20", "xmm21", "xmm22", "xmm23",
3130   "xmm24", "xmm25", "xmm26", "xmm27",
3131   "xmm28", "xmm29", "xmm30", "xmm31"
3132 };
3133 static const char *att_names_xmm[] = {
3134   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3135   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3136   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3137   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3138   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3139   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3140   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3141   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3142 };
3143
3144 static const char **names_ymm;
3145 static const char *intel_names_ymm[] = {
3146   "ymm0", "ymm1", "ymm2", "ymm3",
3147   "ymm4", "ymm5", "ymm6", "ymm7",
3148   "ymm8", "ymm9", "ymm10", "ymm11",
3149   "ymm12", "ymm13", "ymm14", "ymm15",
3150   "ymm16", "ymm17", "ymm18", "ymm19",
3151   "ymm20", "ymm21", "ymm22", "ymm23",
3152   "ymm24", "ymm25", "ymm26", "ymm27",
3153   "ymm28", "ymm29", "ymm30", "ymm31"
3154 };
3155 static const char *att_names_ymm[] = {
3156   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3157   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3158   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3159   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3160   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3161   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3162   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3163   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3164 };
3165
3166 static const char **names_zmm;
3167 static const char *intel_names_zmm[] = {
3168   "zmm0", "zmm1", "zmm2", "zmm3",
3169   "zmm4", "zmm5", "zmm6", "zmm7",
3170   "zmm8", "zmm9", "zmm10", "zmm11",
3171   "zmm12", "zmm13", "zmm14", "zmm15",
3172   "zmm16", "zmm17", "zmm18", "zmm19",
3173   "zmm20", "zmm21", "zmm22", "zmm23",
3174   "zmm24", "zmm25", "zmm26", "zmm27",
3175   "zmm28", "zmm29", "zmm30", "zmm31"
3176 };
3177 static const char *att_names_zmm[] = {
3178   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3179   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3180   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3181   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3182   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3183   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3184   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3185   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3186 };
3187
3188 static const char **names_mask;
3189 static const char *intel_names_mask[] = {
3190   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3191 };
3192 static const char *att_names_mask[] = {
3193   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3194 };
3195
3196 static const char *names_rounding[] =
3197 {
3198   "{rn-sae}",
3199   "{rd-sae}",
3200   "{ru-sae}",
3201   "{rz-sae}"
3202 };
3203
3204 static const struct dis386 reg_table[][8] = {
3205   /* REG_80 */
3206   {
3207     { "addA",   { Ebh1, Ib }, 0 },
3208     { "orA",    { Ebh1, Ib }, 0 },
3209     { "adcA",   { Ebh1, Ib }, 0 },
3210     { "sbbA",   { Ebh1, Ib }, 0 },
3211     { "andA",   { Ebh1, Ib }, 0 },
3212     { "subA",   { Ebh1, Ib }, 0 },
3213     { "xorA",   { Ebh1, Ib }, 0 },
3214     { "cmpA",   { Eb, Ib }, 0 },
3215   },
3216   /* REG_81 */
3217   {
3218     { "addQ",   { Evh1, Iv }, 0 },
3219     { "orQ",    { Evh1, Iv }, 0 },
3220     { "adcQ",   { Evh1, Iv }, 0 },
3221     { "sbbQ",   { Evh1, Iv }, 0 },
3222     { "andQ",   { Evh1, Iv }, 0 },
3223     { "subQ",   { Evh1, Iv }, 0 },
3224     { "xorQ",   { Evh1, Iv }, 0 },
3225     { "cmpQ",   { Ev, Iv }, 0 },
3226   },
3227   /* REG_83 */
3228   {
3229     { "addQ",   { Evh1, sIb }, 0 },
3230     { "orQ",    { Evh1, sIb }, 0 },
3231     { "adcQ",   { Evh1, sIb }, 0 },
3232     { "sbbQ",   { Evh1, sIb }, 0 },
3233     { "andQ",   { Evh1, sIb }, 0 },
3234     { "subQ",   { Evh1, sIb }, 0 },
3235     { "xorQ",   { Evh1, sIb }, 0 },
3236     { "cmpQ",   { Ev, sIb }, 0 },
3237   },
3238   /* REG_8F */
3239   {
3240     { "popU",   { stackEv }, 0 },
3241     { XOP_8F_TABLE (XOP_09) },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { XOP_8F_TABLE (XOP_09) },
3246   },
3247   /* REG_C0 */
3248   {
3249     { "rolA",   { Eb, Ib }, 0 },
3250     { "rorA",   { Eb, Ib }, 0 },
3251     { "rclA",   { Eb, Ib }, 0 },
3252     { "rcrA",   { Eb, Ib }, 0 },
3253     { "shlA",   { Eb, Ib }, 0 },
3254     { "shrA",   { Eb, Ib }, 0 },
3255     { "shlA",   { Eb, Ib }, 0 },
3256     { "sarA",   { Eb, Ib }, 0 },
3257   },
3258   /* REG_C1 */
3259   {
3260     { "rolQ",   { Ev, Ib }, 0 },
3261     { "rorQ",   { Ev, Ib }, 0 },
3262     { "rclQ",   { Ev, Ib }, 0 },
3263     { "rcrQ",   { Ev, Ib }, 0 },
3264     { "shlQ",   { Ev, Ib }, 0 },
3265     { "shrQ",   { Ev, Ib }, 0 },
3266     { "shlQ",   { Ev, Ib }, 0 },
3267     { "sarQ",   { Ev, Ib }, 0 },
3268   },
3269   /* REG_C6 */
3270   {
3271     { "movA",   { Ebh3, Ib }, 0 },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { Bad_Opcode },
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { MOD_TABLE (MOD_C6_REG_7) },
3279   },
3280   /* REG_C7 */
3281   {
3282     { "movQ",   { Evh3, Iv }, 0 },
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { MOD_TABLE (MOD_C7_REG_7) },
3290   },
3291   /* REG_D0 */
3292   {
3293     { "rolA",   { Eb, I1 }, 0 },
3294     { "rorA",   { Eb, I1 }, 0 },
3295     { "rclA",   { Eb, I1 }, 0 },
3296     { "rcrA",   { Eb, I1 }, 0 },
3297     { "shlA",   { Eb, I1 }, 0 },
3298     { "shrA",   { Eb, I1 }, 0 },
3299     { "shlA",   { Eb, I1 }, 0 },
3300     { "sarA",   { Eb, I1 }, 0 },
3301   },
3302   /* REG_D1 */
3303   {
3304     { "rolQ",   { Ev, I1 }, 0 },
3305     { "rorQ",   { Ev, I1 }, 0 },
3306     { "rclQ",   { Ev, I1 }, 0 },
3307     { "rcrQ",   { Ev, I1 }, 0 },
3308     { "shlQ",   { Ev, I1 }, 0 },
3309     { "shrQ",   { Ev, I1 }, 0 },
3310     { "shlQ",   { Ev, I1 }, 0 },
3311     { "sarQ",   { Ev, I1 }, 0 },
3312   },
3313   /* REG_D2 */
3314   {
3315     { "rolA",   { Eb, CL }, 0 },
3316     { "rorA",   { Eb, CL }, 0 },
3317     { "rclA",   { Eb, CL }, 0 },
3318     { "rcrA",   { Eb, CL }, 0 },
3319     { "shlA",   { Eb, CL }, 0 },
3320     { "shrA",   { Eb, CL }, 0 },
3321     { "shlA",   { Eb, CL }, 0 },
3322     { "sarA",   { Eb, CL }, 0 },
3323   },
3324   /* REG_D3 */
3325   {
3326     { "rolQ",   { Ev, CL }, 0 },
3327     { "rorQ",   { Ev, CL }, 0 },
3328     { "rclQ",   { Ev, CL }, 0 },
3329     { "rcrQ",   { Ev, CL }, 0 },
3330     { "shlQ",   { Ev, CL }, 0 },
3331     { "shrQ",   { Ev, CL }, 0 },
3332     { "shlQ",   { Ev, CL }, 0 },
3333     { "sarQ",   { Ev, CL }, 0 },
3334   },
3335   /* REG_F6 */
3336   {
3337     { "testA",  { Eb, Ib }, 0 },
3338     { "testA",  { Eb, Ib }, 0 },
3339     { "notA",   { Ebh1 }, 0 },
3340     { "negA",   { Ebh1 }, 0 },
3341     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3342     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3343     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3344     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3345   },
3346   /* REG_F7 */
3347   {
3348     { "testQ",  { Ev, Iv }, 0 },
3349     { "testQ",  { Ev, Iv }, 0 },
3350     { "notQ",   { Evh1 }, 0 },
3351     { "negQ",   { Evh1 }, 0 },
3352     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3353     { "imulQ",  { Ev }, 0 },
3354     { "divQ",   { Ev }, 0 },
3355     { "idivQ",  { Ev }, 0 },
3356   },
3357   /* REG_FE */
3358   {
3359     { "incA",   { Ebh1 }, 0 },
3360     { "decA",   { Ebh1 }, 0 },
3361   },
3362   /* REG_FF */
3363   {
3364     { "incQ",   { Evh1 }, 0 },
3365     { "decQ",   { Evh1 }, 0 },
3366     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3367     { MOD_TABLE (MOD_FF_REG_3) },
3368     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3369     { MOD_TABLE (MOD_FF_REG_5) },
3370     { "pushU",  { stackEv }, 0 },
3371     { Bad_Opcode },
3372   },
3373   /* REG_0F00 */
3374   {
3375     { "sldtD",  { Sv }, 0 },
3376     { "strD",   { Sv }, 0 },
3377     { "lldt",   { Ew }, 0 },
3378     { "ltr",    { Ew }, 0 },
3379     { "verr",   { Ew }, 0 },
3380     { "verw",   { Ew }, 0 },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383   },
3384   /* REG_0F01 */
3385   {
3386     { MOD_TABLE (MOD_0F01_REG_0) },
3387     { MOD_TABLE (MOD_0F01_REG_1) },
3388     { MOD_TABLE (MOD_0F01_REG_2) },
3389     { MOD_TABLE (MOD_0F01_REG_3) },
3390     { "smswD",  { Sv }, 0 },
3391     { MOD_TABLE (MOD_0F01_REG_5) },
3392     { "lmsw",   { Ew }, 0 },
3393     { MOD_TABLE (MOD_0F01_REG_7) },
3394   },
3395   /* REG_0F0D */
3396   {
3397     { "prefetch",       { Mb }, 0 },
3398     { "prefetchw",      { Mb }, 0 },
3399     { "prefetchwt1",    { Mb }, 0 },
3400     { "prefetch",       { Mb }, 0 },
3401     { "prefetch",       { Mb }, 0 },
3402     { "prefetch",       { Mb }, 0 },
3403     { "prefetch",       { Mb }, 0 },
3404     { "prefetch",       { Mb }, 0 },
3405   },
3406   /* REG_0F18 */
3407   {
3408     { MOD_TABLE (MOD_0F18_REG_0) },
3409     { MOD_TABLE (MOD_0F18_REG_1) },
3410     { MOD_TABLE (MOD_0F18_REG_2) },
3411     { MOD_TABLE (MOD_0F18_REG_3) },
3412     { MOD_TABLE (MOD_0F18_REG_4) },
3413     { MOD_TABLE (MOD_0F18_REG_5) },
3414     { MOD_TABLE (MOD_0F18_REG_6) },
3415     { MOD_TABLE (MOD_0F18_REG_7) },
3416   },
3417   /* REG_0F1C_MOD_0 */
3418   {
3419     { "cldemote",       { Mb }, 0 },
3420     { "nopQ",           { Ev }, 0 },
3421     { "nopQ",           { Ev }, 0 },
3422     { "nopQ",           { Ev }, 0 },
3423     { "nopQ",           { Ev }, 0 },
3424     { "nopQ",           { Ev }, 0 },
3425     { "nopQ",           { Ev }, 0 },
3426     { "nopQ",           { Ev }, 0 },
3427   },
3428   /* REG_0F1E_MOD_3 */
3429   {
3430     { "nopQ",           { Ev }, 0 },
3431     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3432     { "nopQ",           { Ev }, 0 },
3433     { "nopQ",           { Ev }, 0 },
3434     { "nopQ",           { Ev }, 0 },
3435     { "nopQ",           { Ev }, 0 },
3436     { "nopQ",           { Ev }, 0 },
3437     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3438   },
3439   /* REG_0F71 */
3440   {
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { MOD_TABLE (MOD_0F71_REG_2) },
3444     { Bad_Opcode },
3445     { MOD_TABLE (MOD_0F71_REG_4) },
3446     { Bad_Opcode },
3447     { MOD_TABLE (MOD_0F71_REG_6) },
3448   },
3449   /* REG_0F72 */
3450   {
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { MOD_TABLE (MOD_0F72_REG_2) },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_0F72_REG_4) },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_0F72_REG_6) },
3458   },
3459   /* REG_0F73 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { MOD_TABLE (MOD_0F73_REG_2) },
3464     { MOD_TABLE (MOD_0F73_REG_3) },
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F73_REG_6) },
3468     { MOD_TABLE (MOD_0F73_REG_7) },
3469   },
3470   /* REG_0FA6 */
3471   {
3472     { "montmul",        { { OP_0f07, 0 } }, 0 },
3473     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3474     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3475   },
3476   /* REG_0FA7 */
3477   {
3478     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3479     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3480     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3481     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3482     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3483     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3484   },
3485   /* REG_0FAE */
3486   {
3487     { MOD_TABLE (MOD_0FAE_REG_0) },
3488     { MOD_TABLE (MOD_0FAE_REG_1) },
3489     { MOD_TABLE (MOD_0FAE_REG_2) },
3490     { MOD_TABLE (MOD_0FAE_REG_3) },
3491     { MOD_TABLE (MOD_0FAE_REG_4) },
3492     { MOD_TABLE (MOD_0FAE_REG_5) },
3493     { MOD_TABLE (MOD_0FAE_REG_6) },
3494     { MOD_TABLE (MOD_0FAE_REG_7) },
3495   },
3496   /* REG_0FBA */
3497   {
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { "btQ",    { Ev, Ib }, 0 },
3503     { "btsQ",   { Evh1, Ib }, 0 },
3504     { "btrQ",   { Evh1, Ib }, 0 },
3505     { "btcQ",   { Evh1, Ib }, 0 },
3506   },
3507   /* REG_0FC7 */
3508   {
3509     { Bad_Opcode },
3510     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_0FC7_REG_3) },
3513     { MOD_TABLE (MOD_0FC7_REG_4) },
3514     { MOD_TABLE (MOD_0FC7_REG_5) },
3515     { MOD_TABLE (MOD_0FC7_REG_6) },
3516     { MOD_TABLE (MOD_0FC7_REG_7) },
3517   },
3518   /* REG_VEX_0F71 */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3527   },
3528   /* REG_VEX_0F72 */
3529   {
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3537   },
3538   /* REG_VEX_0F73 */
3539   {
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3543     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3547     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3548   },
3549   /* REG_VEX_0FAE */
3550   {
3551     { Bad_Opcode },
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3554     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3555   },
3556   /* REG_VEX_0F38F3 */
3557   {
3558     { Bad_Opcode },
3559     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3560     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3561     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3562   },
3563   /* REG_XOP_LWPCB */
3564   {
3565     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3566     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3567   },
3568   /* REG_XOP_LWP */
3569   {
3570     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3571     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3572   },
3573   /* REG_XOP_TBM_01 */
3574   {
3575     { Bad_Opcode },
3576     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3577     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3578     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3579     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3580     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3581     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3582     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3583   },
3584   /* REG_XOP_TBM_02 */
3585   {
3586     { Bad_Opcode },
3587     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3588     { Bad_Opcode },
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { Bad_Opcode },
3592     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3593   },
3594 #define NEED_REG_TABLE
3595 #include "i386-dis-evex.h"
3596 #undef NEED_REG_TABLE
3597 };
3598
3599 static const struct dis386 prefix_table[][4] = {
3600   /* PREFIX_90 */
3601   {
3602     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3603     { "pause", { XX }, 0 },
3604     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3605     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3606   },
3607
3608   /* PREFIX_MOD_0_0F01_REG_5 */
3609   {
3610     { Bad_Opcode },
3611     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3612   },
3613
3614   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3615   {
3616     { Bad_Opcode },
3617     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3618   },
3619
3620   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3621   {
3622     { Bad_Opcode },
3623     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3624   },
3625
3626   /* PREFIX_0F09 */
3627   {
3628     { "wbinvd",   { XX }, 0 },
3629     { "wbnoinvd", { XX }, 0 },
3630   },
3631
3632   /* PREFIX_0F10 */
3633   {
3634     { "movups", { XM, EXx }, PREFIX_OPCODE },
3635     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3636     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3637     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3638   },
3639
3640   /* PREFIX_0F11 */
3641   {
3642     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3643     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3644     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3645     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F12 */
3649   {
3650     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3651     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3652     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3653     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3654   },
3655
3656   /* PREFIX_0F16 */
3657   {
3658     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3659     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3660     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3661   },
3662
3663   /* PREFIX_0F1A */
3664   {
3665     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3666     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3667     { "bndmov", { Gbnd, Ebnd }, 0 },
3668     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3669   },
3670
3671   /* PREFIX_0F1B */
3672   {
3673     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3674     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3675     { "bndmov", { EbndS, Gbnd }, 0 },
3676     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3677   },
3678
3679   /* PREFIX_0F1C */
3680   {
3681     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3682     { "nopQ",   { Ev }, PREFIX_OPCODE },
3683     { "nopQ",   { Ev }, PREFIX_OPCODE },
3684     { "nopQ",   { Ev }, PREFIX_OPCODE },
3685   },
3686
3687   /* PREFIX_0F1E */
3688   {
3689     { "nopQ",   { Ev }, PREFIX_OPCODE },
3690     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3691     { "nopQ",   { Ev }, PREFIX_OPCODE },
3692     { "nopQ",   { Ev }, PREFIX_OPCODE },
3693   },
3694
3695   /* PREFIX_0F2A */
3696   {
3697     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3698     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3699     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3700     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3701   },
3702
3703   /* PREFIX_0F2B */
3704   {
3705     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3706     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3707     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3708     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3709   },
3710
3711   /* PREFIX_0F2C */
3712   {
3713     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3714     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3715     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3716     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F2D */
3720   {
3721     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3722     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3723     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3724     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3725   },
3726
3727   /* PREFIX_0F2E */
3728   {
3729     { "ucomiss",{ XM, EXd }, 0 },
3730     { Bad_Opcode },
3731     { "ucomisd",{ XM, EXq }, 0 },
3732   },
3733
3734   /* PREFIX_0F2F */
3735   {
3736     { "comiss", { XM, EXd }, 0 },
3737     { Bad_Opcode },
3738     { "comisd", { XM, EXq }, 0 },
3739   },
3740
3741   /* PREFIX_0F51 */
3742   {
3743     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3744     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3745     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3746     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3747   },
3748
3749   /* PREFIX_0F52 */
3750   {
3751     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3752     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3753   },
3754
3755   /* PREFIX_0F53 */
3756   {
3757     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3758     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F58 */
3762   {
3763     { "addps", { XM, EXx }, PREFIX_OPCODE },
3764     { "addss", { XM, EXd }, PREFIX_OPCODE },
3765     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3766     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F59 */
3770   {
3771     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3772     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3773     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3774     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F5A */
3778   {
3779     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3780     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3781     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3782     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F5B */
3786   {
3787     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3788     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3789     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F5C */
3793   {
3794     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3795     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3796     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3797     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3798   },
3799
3800   /* PREFIX_0F5D */
3801   {
3802     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3803     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3804     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3805     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3806   },
3807
3808   /* PREFIX_0F5E */
3809   {
3810     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3811     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3812     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3813     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3814   },
3815
3816   /* PREFIX_0F5F */
3817   {
3818     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3819     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3820     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3821     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3822   },
3823
3824   /* PREFIX_0F60 */
3825   {
3826     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3827     { Bad_Opcode },
3828     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F61 */
3832   {
3833     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3834     { Bad_Opcode },
3835     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_0F62 */
3839   {
3840     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3841     { Bad_Opcode },
3842     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F6C */
3846   {
3847     { Bad_Opcode },
3848     { Bad_Opcode },
3849     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3850   },
3851
3852   /* PREFIX_0F6D */
3853   {
3854     { Bad_Opcode },
3855     { Bad_Opcode },
3856     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F6F */
3860   {
3861     { "movq",   { MX, EM }, PREFIX_OPCODE },
3862     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3863     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0F70 */
3867   {
3868     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3869     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3870     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3871     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F73_REG_3 */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { "psrldq", { XS, Ib }, 0 },
3879   },
3880
3881   /* PREFIX_0F73_REG_7 */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { "pslldq", { XS, Ib }, 0 },
3886   },
3887
3888   /* PREFIX_0F78 */
3889   {
3890     {"vmread",  { Em, Gm }, 0 },
3891     { Bad_Opcode },
3892     {"extrq",   { XS, Ib, Ib }, 0 },
3893     {"insertq", { XM, XS, Ib, Ib }, 0 },
3894   },
3895
3896   /* PREFIX_0F79 */
3897   {
3898     {"vmwrite", { Gm, Em }, 0 },
3899     { Bad_Opcode },
3900     {"extrq",   { XM, XS }, 0 },
3901     {"insertq", { XM, XS }, 0 },
3902   },
3903
3904   /* PREFIX_0F7C */
3905   {
3906     { Bad_Opcode },
3907     { Bad_Opcode },
3908     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3909     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F7D */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3917     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3918   },
3919
3920   /* PREFIX_0F7E */
3921   {
3922     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3923     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3924     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3925   },
3926
3927   /* PREFIX_0F7F */
3928   {
3929     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3930     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3931     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0FAE_REG_0 */
3935   {
3936     { Bad_Opcode },
3937     { "rdfsbase", { Ev }, 0 },
3938   },
3939
3940   /* PREFIX_0FAE_REG_1 */
3941   {
3942     { Bad_Opcode },
3943     { "rdgsbase", { Ev }, 0 },
3944   },
3945
3946   /* PREFIX_0FAE_REG_2 */
3947   {
3948     { Bad_Opcode },
3949     { "wrfsbase", { Ev }, 0 },
3950   },
3951
3952   /* PREFIX_0FAE_REG_3 */
3953   {
3954     { Bad_Opcode },
3955     { "wrgsbase", { Ev }, 0 },
3956   },
3957
3958   /* PREFIX_MOD_0_0FAE_REG_4 */
3959   {
3960     { "xsave",  { FXSAVE }, 0 },
3961     { "ptwrite%LQ", { Edq }, 0 },
3962   },
3963
3964   /* PREFIX_MOD_3_0FAE_REG_4 */
3965   {
3966     { Bad_Opcode },
3967     { "ptwrite%LQ", { Edq }, 0 },
3968   },
3969
3970   /* PREFIX_MOD_0_0FAE_REG_5 */
3971   {
3972     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3973   },
3974
3975   /* PREFIX_MOD_3_0FAE_REG_5 */
3976   {
3977     { "lfence",         { Skip_MODRM }, 0 },
3978     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3979   },
3980
3981   /* PREFIX_MOD_0_0FAE_REG_6 */
3982   {
3983     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3984     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3985     { "clwb",   { Mb }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_MOD_1_0FAE_REG_6 */
3989   {
3990     { RM_TABLE (RM_0FAE_REG_6) },
3991     { "umonitor",       { Eva }, PREFIX_OPCODE },
3992     { "tpause", { Edq }, PREFIX_OPCODE },
3993     { "umwait", { Edq }, PREFIX_OPCODE },
3994   },
3995
3996   /* PREFIX_0FAE_REG_7 */
3997   {
3998     { "clflush",        { Mb }, 0 },
3999     { Bad_Opcode },
4000     { "clflushopt",     { Mb }, 0 },
4001   },
4002
4003   /* PREFIX_0FB8 */
4004   {
4005     { Bad_Opcode },
4006     { "popcntS", { Gv, Ev }, 0 },
4007   },
4008
4009   /* PREFIX_0FBC */
4010   {
4011     { "bsfS",   { Gv, Ev }, 0 },
4012     { "tzcntS", { Gv, Ev }, 0 },
4013     { "bsfS",   { Gv, Ev }, 0 },
4014   },
4015
4016   /* PREFIX_0FBD */
4017   {
4018     { "bsrS",   { Gv, Ev }, 0 },
4019     { "lzcntS", { Gv, Ev }, 0 },
4020     { "bsrS",   { Gv, Ev }, 0 },
4021   },
4022
4023   /* PREFIX_0FC2 */
4024   {
4025     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4026     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4027     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4028     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4029   },
4030
4031   /* PREFIX_MOD_0_0FC3 */
4032   {
4033     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_MOD_0_0FC7_REG_6 */
4037   {
4038     { "vmptrld",{ Mq }, 0 },
4039     { "vmxon",  { Mq }, 0 },
4040     { "vmclear",{ Mq }, 0 },
4041   },
4042
4043   /* PREFIX_MOD_3_0FC7_REG_6 */
4044   {
4045     { "rdrand", { Ev }, 0 },
4046     { Bad_Opcode },
4047     { "rdrand", { Ev }, 0 }
4048   },
4049
4050   /* PREFIX_MOD_3_0FC7_REG_7 */
4051   {
4052     { "rdseed", { Ev }, 0 },
4053     { "rdpid",  { Em }, 0 },
4054     { "rdseed", { Ev }, 0 },
4055   },
4056
4057   /* PREFIX_0FD0 */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { "addsubpd", { XM, EXx }, 0 },
4062     { "addsubps", { XM, EXx }, 0 },
4063   },
4064
4065   /* PREFIX_0FD6 */
4066   {
4067     { Bad_Opcode },
4068     { "movq2dq",{ XM, MS }, 0 },
4069     { "movq",   { EXqS, XM }, 0 },
4070     { "movdq2q",{ MX, XS }, 0 },
4071   },
4072
4073   /* PREFIX_0FE6 */
4074   {
4075     { Bad_Opcode },
4076     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4077     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4078     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4079   },
4080
4081   /* PREFIX_0FE7 */
4082   {
4083     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4084     { Bad_Opcode },
4085     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4086   },
4087
4088   /* PREFIX_0FF0 */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { Bad_Opcode },
4093     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4094   },
4095
4096   /* PREFIX_0FF7 */
4097   {
4098     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4099     { Bad_Opcode },
4100     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4101   },
4102
4103   /* PREFIX_0F3810 */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4108   },
4109
4110   /* PREFIX_0F3814 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0F3815 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F3817 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3820 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3821 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3822 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3823 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3824 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F3825 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F3828 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F3829 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F382A */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4192   },
4193
4194   /* PREFIX_0F382B */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F3830 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F3831 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F3832 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3833 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F3834 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F3835 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F3837 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F3838 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F3839 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F383A */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F383B */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F383C */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F383D */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F383E */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F383F */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F3840 */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4311   },
4312
4313   /* PREFIX_0F3841 */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F3880 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F3881 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F3882 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F38C8 */
4342   {
4343     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F38C9 */
4347   {
4348     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38CA */
4352   {
4353     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F38CB */
4357   {
4358     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38CC */
4362   {
4363     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38CD */
4367   {
4368     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F38CF */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38DB */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38DC */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F38DD */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38DE */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F38DF */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38F0 */
4414   {
4415     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4416     { Bad_Opcode },
4417     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4418     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F38F1 */
4422   {
4423     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4424     { Bad_Opcode },
4425     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4426     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F38F5 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4434   },
4435
4436   /* PREFIX_0F38F6 */
4437   {
4438     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4439     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4440     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4441     { Bad_Opcode },
4442   },
4443
4444   /* PREFIX_0F38F8 */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4449   },
4450
4451   /* PREFIX_0F38F9 */
4452   {
4453     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4454   },
4455
4456   /* PREFIX_0F3A08 */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F3A09 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4468   },
4469
4470   /* PREFIX_0F3A0A */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4475   },
4476
4477   /* PREFIX_0F3A0B */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4482   },
4483
4484   /* PREFIX_0F3A0C */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4489   },
4490
4491   /* PREFIX_0F3A0D */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A0E */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A14 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A15 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A16 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A17 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A20 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A21 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A22 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A40 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A41 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A42 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A44 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A60 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A61 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A62 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A63 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3ACC */
4611   {
4612     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3ACE */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3ACF */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3ADF */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_VEX_0F10 */
4637   {
4638     { "vmovups",        { XM, EXx }, 0 },
4639     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4640     { "vmovupd",        { XM, EXx }, 0 },
4641     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4642   },
4643
4644   /* PREFIX_VEX_0F11 */
4645   {
4646     { "vmovups",        { EXxS, XM }, 0 },
4647     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4648     { "vmovupd",        { EXxS, XM }, 0 },
4649     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4650   },
4651
4652   /* PREFIX_VEX_0F12 */
4653   {
4654     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4655     { "vmovsldup",      { XM, EXx }, 0 },
4656     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4657     { "vmovddup",       { XM, EXymmq }, 0 },
4658   },
4659
4660   /* PREFIX_VEX_0F16 */
4661   {
4662     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4663     { "vmovshdup",      { XM, EXx }, 0 },
4664     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4665   },
4666
4667   /* PREFIX_VEX_0F2A */
4668   {
4669     { Bad_Opcode },
4670     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4673   },
4674
4675   /* PREFIX_VEX_0F2C */
4676   {
4677     { Bad_Opcode },
4678     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4679     { Bad_Opcode },
4680     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4681   },
4682
4683   /* PREFIX_VEX_0F2D */
4684   {
4685     { Bad_Opcode },
4686     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4689   },
4690
4691   /* PREFIX_VEX_0F2E */
4692   {
4693     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4694     { Bad_Opcode },
4695     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4696   },
4697
4698   /* PREFIX_VEX_0F2F */
4699   {
4700     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4701     { Bad_Opcode },
4702     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4703   },
4704
4705   /* PREFIX_VEX_0F41 */
4706   {
4707     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F42 */
4713   {
4714     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4715     { Bad_Opcode },
4716     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F44 */
4720   {
4721     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F45 */
4727   {
4728     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4729     { Bad_Opcode },
4730     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F46 */
4734   {
4735     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F47 */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F4A */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F4B */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F51 */
4762   {
4763     { "vsqrtps",        { XM, EXx }, 0 },
4764     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4765     { "vsqrtpd",        { XM, EXx }, 0 },
4766     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4767   },
4768
4769   /* PREFIX_VEX_0F52 */
4770   {
4771     { "vrsqrtps",       { XM, EXx }, 0 },
4772     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4773   },
4774
4775   /* PREFIX_VEX_0F53 */
4776   {
4777     { "vrcpps",         { XM, EXx }, 0 },
4778     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4779   },
4780
4781   /* PREFIX_VEX_0F58 */
4782   {
4783     { "vaddps",         { XM, Vex, EXx }, 0 },
4784     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4785     { "vaddpd",         { XM, Vex, EXx }, 0 },
4786     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4787   },
4788
4789   /* PREFIX_VEX_0F59 */
4790   {
4791     { "vmulps",         { XM, Vex, EXx }, 0 },
4792     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4793     { "vmulpd",         { XM, Vex, EXx }, 0 },
4794     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4795   },
4796
4797   /* PREFIX_VEX_0F5A */
4798   {
4799     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4800     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4801     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4802     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4803   },
4804
4805   /* PREFIX_VEX_0F5B */
4806   {
4807     { "vcvtdq2ps",      { XM, EXx }, 0 },
4808     { "vcvttps2dq",     { XM, EXx }, 0 },
4809     { "vcvtps2dq",      { XM, EXx }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F5C */
4813   {
4814     { "vsubps",         { XM, Vex, EXx }, 0 },
4815     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4816     { "vsubpd",         { XM, Vex, EXx }, 0 },
4817     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4818   },
4819
4820   /* PREFIX_VEX_0F5D */
4821   {
4822     { "vminps",         { XM, Vex, EXx }, 0 },
4823     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4824     { "vminpd",         { XM, Vex, EXx }, 0 },
4825     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4826   },
4827
4828   /* PREFIX_VEX_0F5E */
4829   {
4830     { "vdivps",         { XM, Vex, EXx }, 0 },
4831     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4832     { "vdivpd",         { XM, Vex, EXx }, 0 },
4833     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4834   },
4835
4836   /* PREFIX_VEX_0F5F */
4837   {
4838     { "vmaxps",         { XM, Vex, EXx }, 0 },
4839     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4840     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4841     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4842   },
4843
4844   /* PREFIX_VEX_0F60 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4849   },
4850
4851   /* PREFIX_VEX_0F61 */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F62 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F63 */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4870   },
4871
4872   /* PREFIX_VEX_0F64 */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F65 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F66 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F67 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F68 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F69 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F6A */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F6B */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F6C */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F6D */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F6E */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_0F6F */
4950   {
4951     { Bad_Opcode },
4952     { "vmovdqu",        { XM, EXx }, 0 },
4953     { "vmovdqa",        { XM, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F70 */
4957   {
4958     { Bad_Opcode },
4959     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4960     { "vpshufd",        { XM, EXx, Ib }, 0 },
4961     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4962   },
4963
4964   /* PREFIX_VEX_0F71_REG_2 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4969   },
4970
4971   /* PREFIX_VEX_0F71_REG_4 */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { "vpsraw",         { Vex, XS, Ib }, 0 },
4976   },
4977
4978   /* PREFIX_VEX_0F71_REG_6 */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { "vpsllw",         { Vex, XS, Ib }, 0 },
4983   },
4984
4985   /* PREFIX_VEX_0F72_REG_2 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { "vpsrld",         { Vex, XS, Ib }, 0 },
4990   },
4991
4992   /* PREFIX_VEX_0F72_REG_4 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { "vpsrad",         { Vex, XS, Ib }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F72_REG_6 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vpslld",         { Vex, XS, Ib }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F73_REG_2 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0F73_REG_3 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0F73_REG_6 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vpsllq",         { Vex, XS, Ib }, 0 },
5025   },
5026
5027   /* PREFIX_VEX_0F73_REG_7 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vpslldq",        { Vex, XS, Ib }, 0 },
5032   },
5033
5034   /* PREFIX_VEX_0F74 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0F75 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5046   },
5047
5048   /* PREFIX_VEX_0F76 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5053   },
5054
5055   /* PREFIX_VEX_0F77 */
5056   {
5057     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5058   },
5059
5060   /* PREFIX_VEX_0F7C */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5065     { "vhaddps",        { XM, Vex, EXx }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F7D */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5073     { "vhsubps",        { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0F7E */
5077   {
5078     { Bad_Opcode },
5079     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5080     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F7F */
5084   {
5085     { Bad_Opcode },
5086     { "vmovdqu",        { EXxS, XM }, 0 },
5087     { "vmovdqa",        { EXxS, XM }, 0 },
5088   },
5089
5090   /* PREFIX_VEX_0F90 */
5091   {
5092     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5093     { Bad_Opcode },
5094     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F91 */
5098   {
5099     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F92 */
5105   {
5106     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5107     { Bad_Opcode },
5108     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5109     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5110   },
5111
5112   /* PREFIX_VEX_0F93 */
5113   {
5114     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5117     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5118   },
5119
5120   /* PREFIX_VEX_0F98 */
5121   {
5122     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5123     { Bad_Opcode },
5124     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0F99 */
5128   {
5129     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0FC2 */
5135   {
5136     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5137     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5138     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5139     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5140   },
5141
5142   /* PREFIX_VEX_0FC4 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0FC5 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0FD0 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5161     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5162   },
5163
5164   /* PREFIX_VEX_0FD1 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5169   },
5170
5171   /* PREFIX_VEX_0FD2 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5176   },
5177
5178   /* PREFIX_VEX_0FD3 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5183   },
5184
5185   /* PREFIX_VEX_0FD4 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { "vpaddq",         { XM, Vex, EXx }, 0 },
5190   },
5191
5192   /* PREFIX_VEX_0FD5 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { "vpmullw",        { XM, Vex, EXx }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FD6 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0FD7 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5211   },
5212
5213   /* PREFIX_VEX_0FD8 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FD9 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FDA */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpminub",        { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FDB */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { "vpand",          { XM, Vex, EXx }, 0 },
5239   },
5240
5241   /* PREFIX_VEX_0FDC */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5246   },
5247
5248   /* PREFIX_VEX_0FDD */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FDE */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FDF */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpandn",         { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FE0 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpavgb",         { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FE1 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5281   },
5282
5283   /* PREFIX_VEX_0FE2 */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5288   },
5289
5290   /* PREFIX_VEX_0FE3 */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vpavgw",         { XM, Vex, EXx }, 0 },
5295   },
5296
5297   /* PREFIX_VEX_0FE4 */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE5 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE6 */
5312   {
5313     { Bad_Opcode },
5314     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5315     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5316     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5317   },
5318
5319   /* PREFIX_VEX_0FE7 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5324   },
5325
5326   /* PREFIX_VEX_0FE8 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5331   },
5332
5333   /* PREFIX_VEX_0FE9 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FEA */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { "vpminsw",        { XM, Vex, EXx }, 0 },
5345   },
5346
5347   /* PREFIX_VEX_0FEB */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { "vpor",           { XM, Vex, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FEC */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5359   },
5360
5361   /* PREFIX_VEX_0FED */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FEE */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FEF */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpxor",          { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FF0 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5388   },
5389
5390   /* PREFIX_VEX_0FF1 */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5395   },
5396
5397   /* PREFIX_VEX_0FF2 */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5402   },
5403
5404   /* PREFIX_VEX_0FF3 */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5409   },
5410
5411   /* PREFIX_VEX_0FF4 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5416   },
5417
5418   /* PREFIX_VEX_0FF5 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5423   },
5424
5425   /* PREFIX_VEX_0FF6 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0FF7 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0FF8 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vpsubb",         { XM, Vex, EXx }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0FF9 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vpsubw",         { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0FFA */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { "vpsubd",         { XM, Vex, EXx }, 0 },
5458   },
5459
5460   /* PREFIX_VEX_0FFB */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsubq",         { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0FFC */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { "vpaddb",         { XM, Vex, EXx }, 0 },
5472   },
5473
5474   /* PREFIX_VEX_0FFD */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpaddw",         { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0FFE */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpaddd",         { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0F3800 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { "vpshufb",        { XM, Vex, EXx }, 0 },
5493   },
5494
5495   /* PREFIX_VEX_0F3801 */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { "vphaddw",        { XM, Vex, EXx }, 0 },
5500   },
5501
5502   /* PREFIX_VEX_0F3802 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { "vphaddd",        { XM, Vex, EXx }, 0 },
5507   },
5508
5509   /* PREFIX_VEX_0F3803 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5514   },
5515
5516   /* PREFIX_VEX_0F3804 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5521   },
5522
5523   /* PREFIX_VEX_0F3805 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vphsubw",        { XM, Vex, EXx }, 0 },
5528   },
5529
5530   /* PREFIX_VEX_0F3806 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vphsubd",        { XM, Vex, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3807 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5542   },
5543
5544   /* PREFIX_VEX_0F3808 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { "vpsignb",        { XM, Vex, EXx }, 0 },
5549   },
5550
5551   /* PREFIX_VEX_0F3809 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vpsignw",        { XM, Vex, EXx }, 0 },
5556   },
5557
5558   /* PREFIX_VEX_0F380A */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vpsignd",        { XM, Vex, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F380B */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F380C */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F380D */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5584   },
5585
5586   /* PREFIX_VEX_0F380E */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F380F */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F3813 */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5605   },
5606
5607   /* PREFIX_VEX_0F3816 */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F3817 */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { "vptest",         { XM, EXx }, 0 },
5619   },
5620
5621   /* PREFIX_VEX_0F3818 */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F3819 */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F381A */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F381C */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { "vpabsb",         { XM, EXx }, 0 },
5647   },
5648
5649   /* PREFIX_VEX_0F381D */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { "vpabsw",         { XM, EXx }, 0 },
5654   },
5655
5656   /* PREFIX_VEX_0F381E */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { "vpabsd",         { XM, EXx }, 0 },
5661   },
5662
5663   /* PREFIX_VEX_0F3820 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5668   },
5669
5670   /* PREFIX_VEX_0F3821 */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5675   },
5676
5677   /* PREFIX_VEX_0F3822 */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F3823 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F3824 */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3825 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3828 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3829 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F382A */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F382B */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F382C */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5738   },
5739
5740   /* PREFIX_VEX_0F382D */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F382E */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5752   },
5753
5754   /* PREFIX_VEX_0F382F */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F3830 */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5766   },
5767
5768   /* PREFIX_VEX_0F3831 */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5773   },
5774
5775   /* PREFIX_VEX_0F3832 */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5780   },
5781
5782   /* PREFIX_VEX_0F3833 */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5787   },
5788
5789   /* PREFIX_VEX_0F3834 */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5794   },
5795
5796   /* PREFIX_VEX_0F3835 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5801   },
5802
5803   /* PREFIX_VEX_0F3836 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5808   },
5809
5810   /* PREFIX_VEX_0F3837 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5815   },
5816
5817   /* PREFIX_VEX_0F3838 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpminsb",        { XM, Vex, EXx }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3839 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { "vpminsd",        { XM, Vex, EXx }, 0 },
5829   },
5830
5831   /* PREFIX_VEX_0F383A */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { "vpminuw",        { XM, Vex, EXx }, 0 },
5836   },
5837
5838   /* PREFIX_VEX_0F383B */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { "vpminud",        { XM, Vex, EXx }, 0 },
5843   },
5844
5845   /* PREFIX_VEX_0F383C */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5850   },
5851
5852   /* PREFIX_VEX_0F383D */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5857   },
5858
5859   /* PREFIX_VEX_0F383E */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5864   },
5865
5866   /* PREFIX_VEX_0F383F */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F3840 */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpmulld",        { XM, Vex, EXx }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F3841 */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5885   },
5886
5887   /* PREFIX_VEX_0F3845 */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F3846 */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5899   },
5900
5901   /* PREFIX_VEX_0F3847 */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5906   },
5907
5908   /* PREFIX_VEX_0F3858 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5913   },
5914
5915   /* PREFIX_VEX_0F3859 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F385A */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5927   },
5928
5929   /* PREFIX_VEX_0F3878 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3879 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5941   },
5942
5943   /* PREFIX_VEX_0F388C */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F388E */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F3890 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F3891 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5969   },
5970
5971   /* PREFIX_VEX_0F3892 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5976   },
5977
5978   /* PREFIX_VEX_0F3893 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5983   },
5984
5985   /* PREFIX_VEX_0F3896 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F3897 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3898 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3899 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F389A */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F389B */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F389C */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F389D */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F389E */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389F */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F38A6 */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6060     { Bad_Opcode },
6061   },
6062
6063   /* PREFIX_VEX_0F38A7 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F38A8 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F38A9 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F38AA */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F38AB */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38AC */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38AD */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38AE */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AF */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38B6 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38B7 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38B8 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38B9 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38BA */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38BB */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38BC */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38BD */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38BE */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BF */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38CF */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6201   },
6202
6203   /* PREFIX_VEX_0F38DB */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6208   },
6209
6210   /* PREFIX_VEX_0F38DC */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vaesenc",        { XM, Vex, EXx }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38DD */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38DE */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vaesdec",        { XM, Vex, EXx }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38DF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38F2 */
6239   {
6240     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6241   },
6242
6243   /* PREFIX_VEX_0F38F3_REG_1 */
6244   {
6245     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6246   },
6247
6248   /* PREFIX_VEX_0F38F3_REG_2 */
6249   {
6250     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6251   },
6252
6253   /* PREFIX_VEX_0F38F3_REG_3 */
6254   {
6255     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6256   },
6257
6258   /* PREFIX_VEX_0F38F5 */
6259   {
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6264   },
6265
6266   /* PREFIX_VEX_0F38F6 */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6272   },
6273
6274   /* PREFIX_VEX_0F38F7 */
6275   {
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6280   },
6281
6282   /* PREFIX_VEX_0F3A00 */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6287   },
6288
6289   /* PREFIX_VEX_0F3A01 */
6290   {
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6294   },
6295
6296   /* PREFIX_VEX_0F3A02 */
6297   {
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6301   },
6302
6303   /* PREFIX_VEX_0F3A04 */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A05 */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A06 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A08 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { "vroundps",       { XM, EXx, Ib }, 0 },
6329   },
6330
6331   /* PREFIX_VEX_0F3A09 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { "vroundpd",       { XM, EXx, Ib }, 0 },
6336   },
6337
6338   /* PREFIX_VEX_0F3A0A */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6343   },
6344
6345   /* PREFIX_VEX_0F3A0B */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6350   },
6351
6352   /* PREFIX_VEX_0F3A0C */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6357   },
6358
6359   /* PREFIX_VEX_0F3A0D */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A0E */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0F */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A14 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A15 */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A16 */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6399   },
6400
6401   /* PREFIX_VEX_0F3A17 */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A18 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A19 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A1D */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6427   },
6428
6429   /* PREFIX_VEX_0F3A20 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A21 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A22 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A30 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A31 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A32 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A33 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A38 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A39 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A40 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6497   },
6498
6499   /* PREFIX_VEX_0F3A41 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A42 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6511   },
6512
6513   /* PREFIX_VEX_0F3A44 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6518   },
6519
6520   /* PREFIX_VEX_0F3A46 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A48 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A49 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A4A */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A4B */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A4C */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A5C */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6567   },
6568
6569   /* PREFIX_VEX_0F3A5D */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6574   },
6575
6576   /* PREFIX_VEX_0F3A5E */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6581   },
6582
6583   /* PREFIX_VEX_0F3A5F */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6588   },
6589
6590   /* PREFIX_VEX_0F3A60 */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6595     { Bad_Opcode },
6596   },
6597
6598   /* PREFIX_VEX_0F3A61 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A62 */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A63 */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A68 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6624   },
6625
6626   /* PREFIX_VEX_0F3A69 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6631   },
6632
6633   /* PREFIX_VEX_0F3A6A */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A6B */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A6C */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6652   },
6653
6654   /* PREFIX_VEX_0F3A6D */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A6E */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6F */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A78 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A79 */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A7A */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A7B */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A7C */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6708     { Bad_Opcode },
6709   },
6710
6711   /* PREFIX_VEX_0F3A7D */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6716   },
6717
6718   /* PREFIX_VEX_0F3A7E */
6719   {
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6723   },
6724
6725   /* PREFIX_VEX_0F3A7F */
6726   {
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6730   },
6731
6732   /* PREFIX_VEX_0F3ACE */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6737   },
6738
6739   /* PREFIX_VEX_0F3ACF */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6744   },
6745
6746   /* PREFIX_VEX_0F3ADF */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6751   },
6752
6753   /* PREFIX_VEX_0F3AF0 */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6759   },
6760
6761 #define NEED_PREFIX_TABLE
6762 #include "i386-dis-evex.h"
6763 #undef NEED_PREFIX_TABLE
6764 };
6765
6766 static const struct dis386 x86_64_table[][2] = {
6767   /* X86_64_06 */
6768   {
6769     { "pushP", { es }, 0 },
6770   },
6771
6772   /* X86_64_07 */
6773   {
6774     { "popP", { es }, 0 },
6775   },
6776
6777   /* X86_64_0D */
6778   {
6779     { "pushP", { cs }, 0 },
6780   },
6781
6782   /* X86_64_16 */
6783   {
6784     { "pushP", { ss }, 0 },
6785   },
6786
6787   /* X86_64_17 */
6788   {
6789     { "popP", { ss }, 0 },
6790   },
6791
6792   /* X86_64_1E */
6793   {
6794     { "pushP", { ds }, 0 },
6795   },
6796
6797   /* X86_64_1F */
6798   {
6799     { "popP", { ds }, 0 },
6800   },
6801
6802   /* X86_64_27 */
6803   {
6804     { "daa", { XX }, 0 },
6805   },
6806
6807   /* X86_64_2F */
6808   {
6809     { "das", { XX }, 0 },
6810   },
6811
6812   /* X86_64_37 */
6813   {
6814     { "aaa", { XX }, 0 },
6815   },
6816
6817   /* X86_64_3F */
6818   {
6819     { "aas", { XX }, 0 },
6820   },
6821
6822   /* X86_64_60 */
6823   {
6824     { "pushaP", { XX }, 0 },
6825   },
6826
6827   /* X86_64_61 */
6828   {
6829     { "popaP", { XX }, 0 },
6830   },
6831
6832   /* X86_64_62 */
6833   {
6834     { MOD_TABLE (MOD_62_32BIT) },
6835     { EVEX_TABLE (EVEX_0F) },
6836   },
6837
6838   /* X86_64_63 */
6839   {
6840     { "arpl", { Ew, Gw }, 0 },
6841     { "movs{lq|xd}", { Gv, Ed }, 0 },
6842   },
6843
6844   /* X86_64_6D */
6845   {
6846     { "ins{R|}", { Yzr, indirDX }, 0 },
6847     { "ins{G|}", { Yzr, indirDX }, 0 },
6848   },
6849
6850   /* X86_64_6F */
6851   {
6852     { "outs{R|}", { indirDXr, Xz }, 0 },
6853     { "outs{G|}", { indirDXr, Xz }, 0 },
6854   },
6855
6856   /* X86_64_82 */
6857   {
6858     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6859     { REG_TABLE (REG_80) },
6860   },
6861
6862   /* X86_64_9A */
6863   {
6864     { "Jcall{T|}", { Ap }, 0 },
6865   },
6866
6867   /* X86_64_C4 */
6868   {
6869     { MOD_TABLE (MOD_C4_32BIT) },
6870     { VEX_C4_TABLE (VEX_0F) },
6871   },
6872
6873   /* X86_64_C5 */
6874   {
6875     { MOD_TABLE (MOD_C5_32BIT) },
6876     { VEX_C5_TABLE (VEX_0F) },
6877   },
6878
6879   /* X86_64_CE */
6880   {
6881     { "into", { XX }, 0 },
6882   },
6883
6884   /* X86_64_D4 */
6885   {
6886     { "aam", { Ib }, 0 },
6887   },
6888
6889   /* X86_64_D5 */
6890   {
6891     { "aad", { Ib }, 0 },
6892   },
6893
6894   /* X86_64_E8 */
6895   {
6896     { "callP",          { Jv, BND }, 0 },
6897     { "call@",          { Jv, BND }, 0 }
6898   },
6899
6900   /* X86_64_E9 */
6901   {
6902     { "jmpP",           { Jv, BND }, 0 },
6903     { "jmp@",           { Jv, BND }, 0 }
6904   },
6905
6906   /* X86_64_EA */
6907   {
6908     { "Jjmp{T|}", { Ap }, 0 },
6909   },
6910
6911   /* X86_64_0F01_REG_0 */
6912   {
6913     { "sgdt{Q|IQ}", { M }, 0 },
6914     { "sgdt", { M }, 0 },
6915   },
6916
6917   /* X86_64_0F01_REG_1 */
6918   {
6919     { "sidt{Q|IQ}", { M }, 0 },
6920     { "sidt", { M }, 0 },
6921   },
6922
6923   /* X86_64_0F01_REG_2 */
6924   {
6925     { "lgdt{Q|Q}", { M }, 0 },
6926     { "lgdt", { M }, 0 },
6927   },
6928
6929   /* X86_64_0F01_REG_3 */
6930   {
6931     { "lidt{Q|Q}", { M }, 0 },
6932     { "lidt", { M }, 0 },
6933   },
6934 };
6935
6936 static const struct dis386 three_byte_table[][256] = {
6937
6938   /* THREE_BYTE_0F38 */
6939   {
6940     /* 00 */
6941     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6942     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6943     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6944     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6945     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6946     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6947     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6948     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6949     /* 08 */
6950     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6951     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6952     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6953     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     /* 10 */
6959     { PREFIX_TABLE (PREFIX_0F3810) },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { PREFIX_TABLE (PREFIX_0F3814) },
6964     { PREFIX_TABLE (PREFIX_0F3815) },
6965     { Bad_Opcode },
6966     { PREFIX_TABLE (PREFIX_0F3817) },
6967     /* 18 */
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6973     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6974     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6975     { Bad_Opcode },
6976     /* 20 */
6977     { PREFIX_TABLE (PREFIX_0F3820) },
6978     { PREFIX_TABLE (PREFIX_0F3821) },
6979     { PREFIX_TABLE (PREFIX_0F3822) },
6980     { PREFIX_TABLE (PREFIX_0F3823) },
6981     { PREFIX_TABLE (PREFIX_0F3824) },
6982     { PREFIX_TABLE (PREFIX_0F3825) },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 28 */
6986     { PREFIX_TABLE (PREFIX_0F3828) },
6987     { PREFIX_TABLE (PREFIX_0F3829) },
6988     { PREFIX_TABLE (PREFIX_0F382A) },
6989     { PREFIX_TABLE (PREFIX_0F382B) },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     /* 30 */
6995     { PREFIX_TABLE (PREFIX_0F3830) },
6996     { PREFIX_TABLE (PREFIX_0F3831) },
6997     { PREFIX_TABLE (PREFIX_0F3832) },
6998     { PREFIX_TABLE (PREFIX_0F3833) },
6999     { PREFIX_TABLE (PREFIX_0F3834) },
7000     { PREFIX_TABLE (PREFIX_0F3835) },
7001     { Bad_Opcode },
7002     { PREFIX_TABLE (PREFIX_0F3837) },
7003     /* 38 */
7004     { PREFIX_TABLE (PREFIX_0F3838) },
7005     { PREFIX_TABLE (PREFIX_0F3839) },
7006     { PREFIX_TABLE (PREFIX_0F383A) },
7007     { PREFIX_TABLE (PREFIX_0F383B) },
7008     { PREFIX_TABLE (PREFIX_0F383C) },
7009     { PREFIX_TABLE (PREFIX_0F383D) },
7010     { PREFIX_TABLE (PREFIX_0F383E) },
7011     { PREFIX_TABLE (PREFIX_0F383F) },
7012     /* 40 */
7013     { PREFIX_TABLE (PREFIX_0F3840) },
7014     { PREFIX_TABLE (PREFIX_0F3841) },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 48 */
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* 50 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 58 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 60 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 68 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 70 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 78 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 80 */
7085     { PREFIX_TABLE (PREFIX_0F3880) },
7086     { PREFIX_TABLE (PREFIX_0F3881) },
7087     { PREFIX_TABLE (PREFIX_0F3882) },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 88 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 90 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 98 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* a0 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* a8 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* b0 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* b8 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* c0 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* c8 */
7166     { PREFIX_TABLE (PREFIX_0F38C8) },
7167     { PREFIX_TABLE (PREFIX_0F38C9) },
7168     { PREFIX_TABLE (PREFIX_0F38CA) },
7169     { PREFIX_TABLE (PREFIX_0F38CB) },
7170     { PREFIX_TABLE (PREFIX_0F38CC) },
7171     { PREFIX_TABLE (PREFIX_0F38CD) },
7172     { Bad_Opcode },
7173     { PREFIX_TABLE (PREFIX_0F38CF) },
7174     /* d0 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* d8 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { PREFIX_TABLE (PREFIX_0F38DB) },
7188     { PREFIX_TABLE (PREFIX_0F38DC) },
7189     { PREFIX_TABLE (PREFIX_0F38DD) },
7190     { PREFIX_TABLE (PREFIX_0F38DE) },
7191     { PREFIX_TABLE (PREFIX_0F38DF) },
7192     /* e0 */
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     /* e8 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* f0 */
7211     { PREFIX_TABLE (PREFIX_0F38F0) },
7212     { PREFIX_TABLE (PREFIX_0F38F1) },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { PREFIX_TABLE (PREFIX_0F38F5) },
7217     { PREFIX_TABLE (PREFIX_0F38F6) },
7218     { Bad_Opcode },
7219     /* f8 */
7220     { PREFIX_TABLE (PREFIX_0F38F8) },
7221     { PREFIX_TABLE (PREFIX_0F38F9) },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228   },
7229   /* THREE_BYTE_0F3A */
7230   {
7231     /* 00 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     /* 08 */
7241     { PREFIX_TABLE (PREFIX_0F3A08) },
7242     { PREFIX_TABLE (PREFIX_0F3A09) },
7243     { PREFIX_TABLE (PREFIX_0F3A0A) },
7244     { PREFIX_TABLE (PREFIX_0F3A0B) },
7245     { PREFIX_TABLE (PREFIX_0F3A0C) },
7246     { PREFIX_TABLE (PREFIX_0F3A0D) },
7247     { PREFIX_TABLE (PREFIX_0F3A0E) },
7248     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7249     /* 10 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { PREFIX_TABLE (PREFIX_0F3A14) },
7255     { PREFIX_TABLE (PREFIX_0F3A15) },
7256     { PREFIX_TABLE (PREFIX_0F3A16) },
7257     { PREFIX_TABLE (PREFIX_0F3A17) },
7258     /* 18 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* 20 */
7268     { PREFIX_TABLE (PREFIX_0F3A20) },
7269     { PREFIX_TABLE (PREFIX_0F3A21) },
7270     { PREFIX_TABLE (PREFIX_0F3A22) },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* 28 */
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* 30 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 38 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* 40 */
7304     { PREFIX_TABLE (PREFIX_0F3A40) },
7305     { PREFIX_TABLE (PREFIX_0F3A41) },
7306     { PREFIX_TABLE (PREFIX_0F3A42) },
7307     { Bad_Opcode },
7308     { PREFIX_TABLE (PREFIX_0F3A44) },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* 48 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 50 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 58 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 60 */
7340     { PREFIX_TABLE (PREFIX_0F3A60) },
7341     { PREFIX_TABLE (PREFIX_0F3A61) },
7342     { PREFIX_TABLE (PREFIX_0F3A62) },
7343     { PREFIX_TABLE (PREFIX_0F3A63) },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* 68 */
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* 70 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* 78 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* 80 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* 88 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* 90 */
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* 98 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* a0 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     /* a8 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* b0 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* b8 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* c0 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* c8 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { PREFIX_TABLE (PREFIX_0F3ACC) },
7462     { Bad_Opcode },
7463     { PREFIX_TABLE (PREFIX_0F3ACE) },
7464     { PREFIX_TABLE (PREFIX_0F3ACF) },
7465     /* d0 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* d8 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { PREFIX_TABLE (PREFIX_0F3ADF) },
7483     /* e0 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* e8 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* f0 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* f8 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519   },
7520 };
7521
7522 static const struct dis386 xop_table[][256] = {
7523   /* XOP_08 */
7524   {
7525     /* 00 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     /* 08 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* 10 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* 18 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* 20 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     /* 28 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* 30 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 38 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 40 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 48 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 50 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 58 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 60 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* 68 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* 70 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* 78 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* 80 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7676     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7677     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7678     /* 88 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7687     /* 90 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7694     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     /* 98 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     /* a0 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     { Bad_Opcode },
7714     /* a8 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     /* b0 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     { Bad_Opcode },
7732     /* b8 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     /* c0 */
7742     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7743     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7744     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7745     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* c8 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7756     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7758     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7759     /* d0 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     /* d8 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* e0 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     /* e8 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7794     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7795     /* f0 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     /* f8 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813   },
7814   /* XOP_09 */
7815   {
7816     /* 00 */
7817     { Bad_Opcode },
7818     { REG_TABLE (REG_XOP_TBM_01) },
7819     { REG_TABLE (REG_XOP_TBM_02) },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* 08 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* 10 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { REG_TABLE (REG_XOP_LWPCB) },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* 18 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 20 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 28 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 30 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 38 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 40 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 48 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 50 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 58 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 60 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 68 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 70 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 78 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 80 */
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7962     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7963     { "vfrczss",        { XM, EXd }, 0 },
7964     { "vfrczsd",        { XM, EXq }, 0 },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 88 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 90 */
7979     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7980     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7981     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7982     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     /* 98 */
7988     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* a0 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* a8 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* b0 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* b8 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* c0 */
8033     { Bad_Opcode },
8034     { "vphaddbw",       { XM, EXxmm }, 0 },
8035     { "vphaddbd",       { XM, EXxmm }, 0 },
8036     { "vphaddbq",       { XM, EXxmm }, 0 },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { "vphaddwd",       { XM, EXxmm }, 0 },
8040     { "vphaddwq",       { XM, EXxmm }, 0 },
8041     /* c8 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { "vphadddq",       { XM, EXxmm }, 0 },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* d0 */
8051     { Bad_Opcode },
8052     { "vphaddubw",      { XM, EXxmm }, 0 },
8053     { "vphaddubd",      { XM, EXxmm }, 0 },
8054     { "vphaddubq",      { XM, EXxmm }, 0 },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { "vphadduwd",      { XM, EXxmm }, 0 },
8058     { "vphadduwq",      { XM, EXxmm }, 0 },
8059     /* d8 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { "vphaddudq",      { XM, EXxmm }, 0 },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* e0 */
8069     { Bad_Opcode },
8070     { "vphsubbw",       { XM, EXxmm }, 0 },
8071     { "vphsubwd",       { XM, EXxmm }, 0 },
8072     { "vphsubdq",       { XM, EXxmm }, 0 },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* e8 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* f0 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* f8 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104   },
8105   /* XOP_0A */
8106   {
8107     /* 00 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* 08 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* 10 */
8126     { "bextr",  { Gv, Ev, Iq }, 0 },
8127     { Bad_Opcode },
8128     { REG_TABLE (REG_XOP_LWP) },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* 18 */
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 20 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 28 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 30 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 38 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 40 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 48 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 50 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 58 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 60 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 68 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 70 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 78 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 80 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 88 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 90 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 98 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* a0 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* a8 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* b0 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* b8 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* c0 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* c8 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* d0 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* d8 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* e0 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* e8 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* f0 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* f8 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395   },
8396 };
8397
8398 static const struct dis386 vex_table[][256] = {
8399   /* VEX_0F */
8400   {
8401     /* 00 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* 08 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* 10 */
8420     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8423     { MOD_TABLE (MOD_VEX_0F13) },
8424     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8425     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8426     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8427     { MOD_TABLE (MOD_VEX_0F17) },
8428     /* 18 */
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     /* 20 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     /* 28 */
8447     { "vmovapX",        { XM, EXx }, 0 },
8448     { "vmovapX",        { EXxS, XM }, 0 },
8449     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8450     { MOD_TABLE (MOD_VEX_0F2B) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8455     /* 30 */
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     /* 38 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     /* 40 */
8474     { Bad_Opcode },
8475     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8477     { Bad_Opcode },
8478     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8482     /* 48 */
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     /* 50 */
8492     { MOD_TABLE (MOD_VEX_0F50) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8496     { "vandpX",         { XM, Vex, EXx }, 0 },
8497     { "vandnpX",        { XM, Vex, EXx }, 0 },
8498     { "vorpX",          { XM, Vex, EXx }, 0 },
8499     { "vxorpX",         { XM, Vex, EXx }, 0 },
8500     /* 58 */
8501     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8509     /* 60 */
8510     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8518     /* 68 */
8519     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8527     /* 70 */
8528     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8529     { REG_TABLE (REG_VEX_0F71) },
8530     { REG_TABLE (REG_VEX_0F72) },
8531     { REG_TABLE (REG_VEX_0F73) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8536     /* 78 */
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8545     /* 80 */
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     /* 88 */
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     /* 90 */
8564     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     /* 98 */
8573     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     /* a0 */
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     /* a8 */
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { REG_TABLE (REG_VEX_0FAE) },
8598     { Bad_Opcode },
8599     /* b0 */
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     /* b8 */
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     /* c0 */
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8621     { Bad_Opcode },
8622     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8623     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8624     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8625     { Bad_Opcode },
8626     /* c8 */
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     /* d0 */
8636     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8637     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8638     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8641     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8644     /* d8 */
8645     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8653     /* e0 */
8654     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8662     /* e8 */
8663     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8671     /* f0 */
8672     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8680     /* f8 */
8681     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8688     { Bad_Opcode },
8689   },
8690   /* VEX_0F38 */
8691   {
8692     /* 00 */
8693     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8701     /* 08 */
8702     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8710     /* 10 */
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8719     /* 18 */
8720     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8723     { Bad_Opcode },
8724     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8727     { Bad_Opcode },
8728     /* 20 */
8729     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* 28 */
8738     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8746     /* 30 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8755     /* 38 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8764     /* 40 */
8765     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8773     /* 48 */
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     /* 50 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* 58 */
8792     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     /* 60 */
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     /* 68 */
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* 70 */
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     /* 78 */
8828     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     /* 80 */
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     /* 88 */
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8851     { Bad_Opcode },
8852     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8853     { Bad_Opcode },
8854     /* 90 */
8855     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8863     /* 98 */
8864     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8872     /* a0 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8881     /* a8 */
8882     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8890     /* b0 */
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8899     /* b8 */
8900     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8908     /* c0 */
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     /* c8 */
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8926     /* d0 */
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     /* d8 */
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8944     /* e0 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     /* e8 */
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     /* f0 */
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8966     { REG_TABLE (REG_VEX_0F38F3) },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8971     /* f8 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980   },
8981   /* VEX_0F3A */
8982   {
8983     /* 00 */
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8987     { Bad_Opcode },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8991     { Bad_Opcode },
8992     /* 08 */
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9001     /* 10 */
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9010     /* 18 */
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     /* 20 */
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     /* 28 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     /* 30 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     /* 38 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* 40 */
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9059     { Bad_Opcode },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9061     { Bad_Opcode },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9063     { Bad_Opcode },
9064     /* 48 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     /* 50 */
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     /* 58 */
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9091     /* 60 */
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     /* 68 */
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9109     /* 70 */
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     /* 78 */
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9127     /* 80 */
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     /* 88 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* 90 */
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     /* 98 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* a0 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* a8 */
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     /* b0 */
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     /* b8 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     /* c0 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* c8 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9216     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9217     /* d0 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     /* d8 */
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9235     /* e0 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     /* e8 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* f0 */
9254     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     /* f8 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271   },
9272 };
9273
9274 #define NEED_OPCODE_TABLE
9275 #include "i386-dis-evex.h"
9276 #undef NEED_OPCODE_TABLE
9277 static const struct dis386 vex_len_table[][2] = {
9278   /* VEX_LEN_0F12_P_0_M_0 */
9279   {
9280     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9281   },
9282
9283   /* VEX_LEN_0F12_P_0_M_1 */
9284   {
9285     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9286   },
9287
9288   /* VEX_LEN_0F12_P_2 */
9289   {
9290     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9291   },
9292
9293   /* VEX_LEN_0F13_M_0 */
9294   {
9295     { "vmovlpX",        { EXq, XM }, 0 },
9296   },
9297
9298   /* VEX_LEN_0F16_P_0_M_0 */
9299   {
9300     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9301   },
9302
9303   /* VEX_LEN_0F16_P_0_M_1 */
9304   {
9305     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9306   },
9307
9308   /* VEX_LEN_0F16_P_2 */
9309   {
9310     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F17_M_0 */
9314   {
9315     { "vmovhpX",        { EXq, XM }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F2A_P_1 */
9319   {
9320     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9321     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9322   },
9323
9324   /* VEX_LEN_0F2A_P_3 */
9325   {
9326     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9327     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9328   },
9329
9330   /* VEX_LEN_0F2C_P_1 */
9331   {
9332     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9333     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9334   },
9335
9336   /* VEX_LEN_0F2C_P_3 */
9337   {
9338     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9339     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9340   },
9341
9342   /* VEX_LEN_0F2D_P_1 */
9343   {
9344     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9345     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9346   },
9347
9348   /* VEX_LEN_0F2D_P_3 */
9349   {
9350     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9351     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9352   },
9353
9354   /* VEX_LEN_0F41_P_0 */
9355   {
9356     { Bad_Opcode },
9357     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9358   },
9359   /* VEX_LEN_0F41_P_2 */
9360   {
9361     { Bad_Opcode },
9362     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9363   },
9364   /* VEX_LEN_0F42_P_0 */
9365   {
9366     { Bad_Opcode },
9367     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9368   },
9369   /* VEX_LEN_0F42_P_2 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9373   },
9374   /* VEX_LEN_0F44_P_0 */
9375   {
9376     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9377   },
9378   /* VEX_LEN_0F44_P_2 */
9379   {
9380     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9381   },
9382   /* VEX_LEN_0F45_P_0 */
9383   {
9384     { Bad_Opcode },
9385     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9386   },
9387   /* VEX_LEN_0F45_P_2 */
9388   {
9389     { Bad_Opcode },
9390     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9391   },
9392   /* VEX_LEN_0F46_P_0 */
9393   {
9394     { Bad_Opcode },
9395     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9396   },
9397   /* VEX_LEN_0F46_P_2 */
9398   {
9399     { Bad_Opcode },
9400     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9401   },
9402   /* VEX_LEN_0F47_P_0 */
9403   {
9404     { Bad_Opcode },
9405     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9406   },
9407   /* VEX_LEN_0F47_P_2 */
9408   {
9409     { Bad_Opcode },
9410     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9411   },
9412   /* VEX_LEN_0F4A_P_0 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9416   },
9417   /* VEX_LEN_0F4A_P_2 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9421   },
9422   /* VEX_LEN_0F4B_P_0 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9426   },
9427   /* VEX_LEN_0F4B_P_2 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9431   },
9432
9433   /* VEX_LEN_0F6E_P_2 */
9434   {
9435     { "vmovK",          { XMScalar, Edq }, 0 },
9436   },
9437
9438   /* VEX_LEN_0F77_P_1 */
9439   {
9440     { "vzeroupper",     { XX }, 0 },
9441     { "vzeroall",       { XX }, 0 },
9442   },
9443
9444   /* VEX_LEN_0F7E_P_1 */
9445   {
9446     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9447   },
9448
9449   /* VEX_LEN_0F7E_P_2 */
9450   {
9451     { "vmovK",          { Edq, XMScalar }, 0 },
9452   },
9453
9454   /* VEX_LEN_0F90_P_0 */
9455   {
9456     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9457   },
9458
9459   /* VEX_LEN_0F90_P_2 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9462   },
9463
9464   /* VEX_LEN_0F91_P_0 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9467   },
9468
9469   /* VEX_LEN_0F91_P_2 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F92_P_0 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F92_P_2 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F92_P_3 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F93_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F93_P_2 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F93_P_3 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F98_P_0 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F98_P_2 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F99_P_0 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F99_P_2 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0FAE_R_2_M_0 */
9525   {
9526     { "vldmxcsr",       { Md }, 0 },
9527   },
9528
9529   /* VEX_LEN_0FAE_R_3_M_0 */
9530   {
9531     { "vstmxcsr",       { Md }, 0 },
9532   },
9533
9534   /* VEX_LEN_0FC4_P_2 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9537   },
9538
9539   /* VEX_LEN_0FC5_P_2 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9542   },
9543
9544   /* VEX_LEN_0FD6_P_2 */
9545   {
9546     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9547   },
9548
9549   /* VEX_LEN_0FF7_P_2 */
9550   {
9551     { "vmaskmovdqu",    { XM, XS }, 0 },
9552   },
9553
9554   /* VEX_LEN_0F3816_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F3819_P_2 */
9561   {
9562     { Bad_Opcode },
9563     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9564   },
9565
9566   /* VEX_LEN_0F381A_P_2_M_0 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9570   },
9571
9572   /* VEX_LEN_0F3836_P_2 */
9573   {
9574     { Bad_Opcode },
9575     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9576   },
9577
9578   /* VEX_LEN_0F3841_P_2 */
9579   {
9580     { "vphminposuw",    { XM, EXx }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F385A_P_2_M_0 */
9584   {
9585     { Bad_Opcode },
9586     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9587   },
9588
9589   /* VEX_LEN_0F38DB_P_2 */
9590   {
9591     { "vaesimc",        { XM, EXx }, 0 },
9592   },
9593
9594   /* VEX_LEN_0F38F2_P_0 */
9595   {
9596     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F38F3_R_1_P_0 */
9600   {
9601     { "blsrS",          { VexGdq, Edq }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F38F3_R_2_P_0 */
9605   {
9606     { "blsmskS",        { VexGdq, Edq }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F38F3_R_3_P_0 */
9610   {
9611     { "blsiS",          { VexGdq, Edq }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F38F5_P_0 */
9615   {
9616     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F38F5_P_1 */
9620   {
9621     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F38F5_P_3 */
9625   {
9626     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F38F6_P_3 */
9630   {
9631     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F38F7_P_0 */
9635   {
9636     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F38F7_P_1 */
9640   {
9641     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F38F7_P_2 */
9645   {
9646     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F38F7_P_3 */
9650   {
9651     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F3A00_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9658   },
9659
9660   /* VEX_LEN_0F3A01_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9664   },
9665
9666   /* VEX_LEN_0F3A06_P_2 */
9667   {
9668     { Bad_Opcode },
9669     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9670   },
9671
9672   /* VEX_LEN_0F3A14_P_2 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9675   },
9676
9677   /* VEX_LEN_0F3A15_P_2 */
9678   {
9679     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9680   },
9681
9682   /* VEX_LEN_0F3A16_P_2  */
9683   {
9684     { "vpextrK",        { Edq, XM, Ib }, 0 },
9685   },
9686
9687   /* VEX_LEN_0F3A17_P_2 */
9688   {
9689     { "vextractps",     { Edqd, XM, Ib }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F3A18_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9696   },
9697
9698   /* VEX_LEN_0F3A19_P_2 */
9699   {
9700     { Bad_Opcode },
9701     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9702   },
9703
9704   /* VEX_LEN_0F3A20_P_2 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9707   },
9708
9709   /* VEX_LEN_0F3A21_P_2 */
9710   {
9711     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9712   },
9713
9714   /* VEX_LEN_0F3A22_P_2 */
9715   {
9716     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9717   },
9718
9719   /* VEX_LEN_0F3A30_P_2 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9722   },
9723
9724   /* VEX_LEN_0F3A31_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9727   },
9728
9729   /* VEX_LEN_0F3A32_P_2 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9732   },
9733
9734   /* VEX_LEN_0F3A33_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F3A38_P_2 */
9740   {
9741     { Bad_Opcode },
9742     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9743   },
9744
9745   /* VEX_LEN_0F3A39_P_2 */
9746   {
9747     { Bad_Opcode },
9748     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9749   },
9750
9751   /* VEX_LEN_0F3A41_P_2 */
9752   {
9753     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9754   },
9755
9756   /* VEX_LEN_0F3A46_P_2 */
9757   {
9758     { Bad_Opcode },
9759     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9760   },
9761
9762   /* VEX_LEN_0F3A60_P_2 */
9763   {
9764     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9765   },
9766
9767   /* VEX_LEN_0F3A61_P_2 */
9768   {
9769     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9770   },
9771
9772   /* VEX_LEN_0F3A62_P_2 */
9773   {
9774     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9775   },
9776
9777   /* VEX_LEN_0F3A63_P_2 */
9778   {
9779     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9780   },
9781
9782   /* VEX_LEN_0F3A6A_P_2 */
9783   {
9784     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9785   },
9786
9787   /* VEX_LEN_0F3A6B_P_2 */
9788   {
9789     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9790   },
9791
9792   /* VEX_LEN_0F3A6E_P_2 */
9793   {
9794     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F3A6F_P_2 */
9798   {
9799     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9800   },
9801
9802   /* VEX_LEN_0F3A7A_P_2 */
9803   {
9804     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9805   },
9806
9807   /* VEX_LEN_0F3A7B_P_2 */
9808   {
9809     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9810   },
9811
9812   /* VEX_LEN_0F3A7E_P_2 */
9813   {
9814     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9815   },
9816
9817   /* VEX_LEN_0F3A7F_P_2 */
9818   {
9819     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F3ADF_P_2 */
9823   {
9824     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9825   },
9826
9827   /* VEX_LEN_0F3AF0_P_3 */
9828   {
9829     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9830   },
9831
9832   /* VEX_LEN_0FXOP_08_CC */
9833   {
9834      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9835   },
9836
9837   /* VEX_LEN_0FXOP_08_CD */
9838   {
9839      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9840   },
9841
9842   /* VEX_LEN_0FXOP_08_CE */
9843   {
9844      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9845   },
9846
9847   /* VEX_LEN_0FXOP_08_CF */
9848   {
9849      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9850   },
9851
9852   /* VEX_LEN_0FXOP_08_EC */
9853   {
9854      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_ED */
9858   {
9859      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_EE */
9863   {
9864      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_EF */
9868   {
9869      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_09_80 */
9873   {
9874     { "vfrczps",        { XM, EXxmm }, 0 },
9875     { "vfrczps",        { XM, EXymmq }, 0 },
9876   },
9877
9878   /* VEX_LEN_0FXOP_09_81 */
9879   {
9880     { "vfrczpd",        { XM, EXxmm }, 0 },
9881     { "vfrczpd",        { XM, EXymmq }, 0 },
9882   },
9883 };
9884
9885 static const struct dis386 vex_w_table[][2] = {
9886   {
9887     /* VEX_W_0F41_P_0_LEN_1 */
9888     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9889     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9890   },
9891   {
9892     /* VEX_W_0F41_P_2_LEN_1 */
9893     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9894     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9895   },
9896   {
9897     /* VEX_W_0F42_P_0_LEN_1 */
9898     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9899     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9900   },
9901   {
9902     /* VEX_W_0F42_P_2_LEN_1 */
9903     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9904     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9905   },
9906   {
9907     /* VEX_W_0F44_P_0_LEN_0 */
9908     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9909     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9910   },
9911   {
9912     /* VEX_W_0F44_P_2_LEN_0 */
9913     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9914     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9915   },
9916   {
9917     /* VEX_W_0F45_P_0_LEN_1 */
9918     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9919     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9920   },
9921   {
9922     /* VEX_W_0F45_P_2_LEN_1 */
9923     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9924     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9925   },
9926   {
9927     /* VEX_W_0F46_P_0_LEN_1 */
9928     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9929     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9930   },
9931   {
9932     /* VEX_W_0F46_P_2_LEN_1 */
9933     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9934     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9935   },
9936   {
9937     /* VEX_W_0F47_P_0_LEN_1 */
9938     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9939     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9940   },
9941   {
9942     /* VEX_W_0F47_P_2_LEN_1 */
9943     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9944     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9945   },
9946   {
9947     /* VEX_W_0F4A_P_0_LEN_1 */
9948     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9949     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9950   },
9951   {
9952     /* VEX_W_0F4A_P_2_LEN_1 */
9953     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9954     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9955   },
9956   {
9957     /* VEX_W_0F4B_P_0_LEN_1 */
9958     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9959     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9960   },
9961   {
9962     /* VEX_W_0F4B_P_2_LEN_1 */
9963     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F90_P_0_LEN_0 */
9967     { "kmovw",          { MaskG, MaskE }, 0 },
9968     { "kmovq",          { MaskG, MaskE }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F90_P_2_LEN_0 */
9972     { "kmovb",          { MaskG, MaskBDE }, 0 },
9973     { "kmovd",          { MaskG, MaskBDE }, 0 },
9974   },
9975   {
9976     /* VEX_W_0F91_P_0_LEN_0 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9979   },
9980   {
9981     /* VEX_W_0F91_P_2_LEN_0 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9983     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F92_P_0_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F92_P_2_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9992   },
9993   {
9994     /* VEX_W_0F92_P_3_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
9996     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F93_P_0_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F93_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F93_P_3_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10009     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F98_P_0_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10014     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10015   },
10016   {
10017     /* VEX_W_0F98_P_2_LEN_0 */
10018     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10019     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10020   },
10021   {
10022     /* VEX_W_0F99_P_0_LEN_0 */
10023     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10024     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10025   },
10026   {
10027     /* VEX_W_0F99_P_2_LEN_0 */
10028     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10029     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10030   },
10031   {
10032     /* VEX_W_0FC4_P_2 */
10033     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10034   },
10035   {
10036     /* VEX_W_0FC5_P_2 */
10037     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10038   },
10039   {
10040     /* VEX_W_0F380C_P_2  */
10041     { "vpermilps",      { XM, Vex, EXx }, 0 },
10042   },
10043   {
10044     /* VEX_W_0F380D_P_2  */
10045     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F380E_P_2  */
10049     { "vtestps",        { XM, EXx }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F380F_P_2  */
10053     { "vtestpd",        { XM, EXx }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F3816_P_2  */
10057     { "vpermps",        { XM, Vex, EXx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F3818_P_2 */
10061     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F3819_P_2 */
10065     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F381A_P_2_M_0 */
10069     { "vbroadcastf128", { XM, Mxmm }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F382C_P_2_M_0 */
10073     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F382D_P_2_M_0 */
10077     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F382E_P_2_M_0 */
10081     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F382F_P_2_M_0 */
10085     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3836_P_2  */
10089     { "vpermd",         { XM, Vex, EXx }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3846_P_2 */
10093     { "vpsravd",        { XM, Vex, EXx }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F3858_P_2 */
10097     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3859_P_2 */
10101     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10102   },
10103   {
10104     /* VEX_W_0F385A_P_2_M_0 */
10105     { "vbroadcasti128", { XM, Mxmm }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3878_P_2 */
10109     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3879_P_2 */
10113     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F38CF_P_2 */
10117     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A00_P_2 */
10121     { Bad_Opcode },
10122     { "vpermq",         { XM, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A01_P_2 */
10126     { Bad_Opcode },
10127     { "vpermpd",        { XM, EXx, Ib }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A02_P_2 */
10131     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F3A04_P_2 */
10135     { "vpermilps",      { XM, EXx, Ib }, 0 },
10136   },
10137   {
10138     /* VEX_W_0F3A05_P_2 */
10139     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10140   },
10141   {
10142     /* VEX_W_0F3A06_P_2 */
10143     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3A14_P_2 */
10147     { "vpextrb",        { Edqb, XM, Ib }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F3A15_P_2 */
10151     { "vpextrw",        { Edqw, XM, Ib }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F3A18_P_2 */
10155     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F3A19_P_2 */
10159     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F3A20_P_2 */
10163     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A30_P_2_LEN_0 */
10167     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10168     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10169   },
10170   {
10171     /* VEX_W_0F3A31_P_2_LEN_0 */
10172     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10173     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10174   },
10175   {
10176     /* VEX_W_0F3A32_P_2_LEN_0 */
10177     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10178     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10179   },
10180   {
10181     /* VEX_W_0F3A33_P_2_LEN_0 */
10182     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10183     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10184   },
10185   {
10186     /* VEX_W_0F3A38_P_2 */
10187     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10188   },
10189   {
10190     /* VEX_W_0F3A39_P_2 */
10191     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10192   },
10193   {
10194     /* VEX_W_0F3A46_P_2 */
10195     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10196   },
10197   {
10198     /* VEX_W_0F3A48_P_2 */
10199     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10200     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10201   },
10202   {
10203     /* VEX_W_0F3A49_P_2 */
10204     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10205     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F3A4A_P_2 */
10209     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10210   },
10211   {
10212     /* VEX_W_0F3A4B_P_2 */
10213     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10214   },
10215   {
10216     /* VEX_W_0F3A4C_P_2 */
10217     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10218   },
10219   {
10220     /* VEX_W_0F3ACE_P_2 */
10221     { Bad_Opcode },
10222     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10223   },
10224   {
10225     /* VEX_W_0F3ACF_P_2 */
10226     { Bad_Opcode },
10227     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10228   },
10229 #define NEED_VEX_W_TABLE
10230 #include "i386-dis-evex.h"
10231 #undef NEED_VEX_W_TABLE
10232 };
10233
10234 static const struct dis386 mod_table[][2] = {
10235   {
10236     /* MOD_8D */
10237     { "leaS",           { Gv, M }, 0 },
10238   },
10239   {
10240     /* MOD_C6_REG_7 */
10241     { Bad_Opcode },
10242     { RM_TABLE (RM_C6_REG_7) },
10243   },
10244   {
10245     /* MOD_C7_REG_7 */
10246     { Bad_Opcode },
10247     { RM_TABLE (RM_C7_REG_7) },
10248   },
10249   {
10250     /* MOD_FF_REG_3 */
10251     { "Jcall^", { indirEp }, 0 },
10252   },
10253   {
10254     /* MOD_FF_REG_5 */
10255     { "Jjmp^", { indirEp }, 0 },
10256   },
10257   {
10258     /* MOD_0F01_REG_0 */
10259     { X86_64_TABLE (X86_64_0F01_REG_0) },
10260     { RM_TABLE (RM_0F01_REG_0) },
10261   },
10262   {
10263     /* MOD_0F01_REG_1 */
10264     { X86_64_TABLE (X86_64_0F01_REG_1) },
10265     { RM_TABLE (RM_0F01_REG_1) },
10266   },
10267   {
10268     /* MOD_0F01_REG_2 */
10269     { X86_64_TABLE (X86_64_0F01_REG_2) },
10270     { RM_TABLE (RM_0F01_REG_2) },
10271   },
10272   {
10273     /* MOD_0F01_REG_3 */
10274     { X86_64_TABLE (X86_64_0F01_REG_3) },
10275     { RM_TABLE (RM_0F01_REG_3) },
10276   },
10277   {
10278     /* MOD_0F01_REG_5 */
10279     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10280     { RM_TABLE (RM_0F01_REG_5) },
10281   },
10282   {
10283     /* MOD_0F01_REG_7 */
10284     { "invlpg",         { Mb }, 0 },
10285     { RM_TABLE (RM_0F01_REG_7) },
10286   },
10287   {
10288     /* MOD_0F12_PREFIX_0 */
10289     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10290     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10291   },
10292   {
10293     /* MOD_0F13 */
10294     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10295   },
10296   {
10297     /* MOD_0F16_PREFIX_0 */
10298     { "movhps",         { XM, EXq }, 0 },
10299     { "movlhps",        { XM, EXq }, 0 },
10300   },
10301   {
10302     /* MOD_0F17 */
10303     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10304   },
10305   {
10306     /* MOD_0F18_REG_0 */
10307     { "prefetchnta",    { Mb }, 0 },
10308   },
10309   {
10310     /* MOD_0F18_REG_1 */
10311     { "prefetcht0",     { Mb }, 0 },
10312   },
10313   {
10314     /* MOD_0F18_REG_2 */
10315     { "prefetcht1",     { Mb }, 0 },
10316   },
10317   {
10318     /* MOD_0F18_REG_3 */
10319     { "prefetcht2",     { Mb }, 0 },
10320   },
10321   {
10322     /* MOD_0F18_REG_4 */
10323     { "nop/reserved",   { Mb }, 0 },
10324   },
10325   {
10326     /* MOD_0F18_REG_5 */
10327     { "nop/reserved",   { Mb }, 0 },
10328   },
10329   {
10330     /* MOD_0F18_REG_6 */
10331     { "nop/reserved",   { Mb }, 0 },
10332   },
10333   {
10334     /* MOD_0F18_REG_7 */
10335     { "nop/reserved",   { Mb }, 0 },
10336   },
10337   {
10338     /* MOD_0F1A_PREFIX_0 */
10339     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10340     { "nopQ",           { Ev }, 0 },
10341   },
10342   {
10343     /* MOD_0F1B_PREFIX_0 */
10344     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10345     { "nopQ",           { Ev }, 0 },
10346   },
10347   {
10348     /* MOD_0F1B_PREFIX_1 */
10349     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10350     { "nopQ",           { Ev }, 0 },
10351   },
10352   {
10353     /* MOD_0F1C_PREFIX_0 */
10354     { REG_TABLE (REG_0F1C_MOD_0) },
10355     { "nopQ",           { Ev }, 0 },
10356   },
10357   {
10358     /* MOD_0F1E_PREFIX_1 */
10359     { "nopQ",           { Ev }, 0 },
10360     { REG_TABLE (REG_0F1E_MOD_3) },
10361   },
10362   {
10363     /* MOD_0F24 */
10364     { Bad_Opcode },
10365     { "movL",           { Rd, Td }, 0 },
10366   },
10367   {
10368     /* MOD_0F26 */
10369     { Bad_Opcode },
10370     { "movL",           { Td, Rd }, 0 },
10371   },
10372   {
10373     /* MOD_0F2B_PREFIX_0 */
10374     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10375   },
10376   {
10377     /* MOD_0F2B_PREFIX_1 */
10378     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10379   },
10380   {
10381     /* MOD_0F2B_PREFIX_2 */
10382     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10383   },
10384   {
10385     /* MOD_0F2B_PREFIX_3 */
10386     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10387   },
10388   {
10389     /* MOD_0F51 */
10390     { Bad_Opcode },
10391     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10392   },
10393   {
10394     /* MOD_0F71_REG_2 */
10395     { Bad_Opcode },
10396     { "psrlw",          { MS, Ib }, 0 },
10397   },
10398   {
10399     /* MOD_0F71_REG_4 */
10400     { Bad_Opcode },
10401     { "psraw",          { MS, Ib }, 0 },
10402   },
10403   {
10404     /* MOD_0F71_REG_6 */
10405     { Bad_Opcode },
10406     { "psllw",          { MS, Ib }, 0 },
10407   },
10408   {
10409     /* MOD_0F72_REG_2 */
10410     { Bad_Opcode },
10411     { "psrld",          { MS, Ib }, 0 },
10412   },
10413   {
10414     /* MOD_0F72_REG_4 */
10415     { Bad_Opcode },
10416     { "psrad",          { MS, Ib }, 0 },
10417   },
10418   {
10419     /* MOD_0F72_REG_6 */
10420     { Bad_Opcode },
10421     { "pslld",          { MS, Ib }, 0 },
10422   },
10423   {
10424     /* MOD_0F73_REG_2 */
10425     { Bad_Opcode },
10426     { "psrlq",          { MS, Ib }, 0 },
10427   },
10428   {
10429     /* MOD_0F73_REG_3 */
10430     { Bad_Opcode },
10431     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10432   },
10433   {
10434     /* MOD_0F73_REG_6 */
10435     { Bad_Opcode },
10436     { "psllq",          { MS, Ib }, 0 },
10437   },
10438   {
10439     /* MOD_0F73_REG_7 */
10440     { Bad_Opcode },
10441     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10442   },
10443   {
10444     /* MOD_0FAE_REG_0 */
10445     { "fxsave",         { FXSAVE }, 0 },
10446     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10447   },
10448   {
10449     /* MOD_0FAE_REG_1 */
10450     { "fxrstor",        { FXSAVE }, 0 },
10451     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10452   },
10453   {
10454     /* MOD_0FAE_REG_2 */
10455     { "ldmxcsr",        { Md }, 0 },
10456     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10457   },
10458   {
10459     /* MOD_0FAE_REG_3 */
10460     { "stmxcsr",        { Md }, 0 },
10461     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10462   },
10463   {
10464     /* MOD_0FAE_REG_4 */
10465     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10466     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10467   },
10468   {
10469     /* MOD_0FAE_REG_5 */
10470     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10471     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10472   },
10473   {
10474     /* MOD_0FAE_REG_6 */
10475     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10476     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10477   },
10478   {
10479     /* MOD_0FAE_REG_7 */
10480     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10481     { RM_TABLE (RM_0FAE_REG_7) },
10482   },
10483   {
10484     /* MOD_0FB2 */
10485     { "lssS",           { Gv, Mp }, 0 },
10486   },
10487   {
10488     /* MOD_0FB4 */
10489     { "lfsS",           { Gv, Mp }, 0 },
10490   },
10491   {
10492     /* MOD_0FB5 */
10493     { "lgsS",           { Gv, Mp }, 0 },
10494   },
10495   {
10496     /* MOD_0FC3 */
10497     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10498   },
10499   {
10500     /* MOD_0FC7_REG_3 */
10501     { "xrstors",        { FXSAVE }, 0 },
10502   },
10503   {
10504     /* MOD_0FC7_REG_4 */
10505     { "xsavec",         { FXSAVE }, 0 },
10506   },
10507   {
10508     /* MOD_0FC7_REG_5 */
10509     { "xsaves",         { FXSAVE }, 0 },
10510   },
10511   {
10512     /* MOD_0FC7_REG_6 */
10513     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10514     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10515   },
10516   {
10517     /* MOD_0FC7_REG_7 */
10518     { "vmptrst",        { Mq }, 0 },
10519     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10520   },
10521   {
10522     /* MOD_0FD7 */
10523     { Bad_Opcode },
10524     { "pmovmskb",       { Gdq, MS }, 0 },
10525   },
10526   {
10527     /* MOD_0FE7_PREFIX_2 */
10528     { "movntdq",        { Mx, XM }, 0 },
10529   },
10530   {
10531     /* MOD_0FF0_PREFIX_3 */
10532     { "lddqu",          { XM, M }, 0 },
10533   },
10534   {
10535     /* MOD_0F382A_PREFIX_2 */
10536     { "movntdqa",       { XM, Mx }, 0 },
10537   },
10538   {
10539     /* MOD_0F38F5_PREFIX_2 */
10540     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10541   },
10542   {
10543     /* MOD_0F38F6_PREFIX_0 */
10544     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10545   },
10546   {
10547     /* MOD_0F38F8_PREFIX_2 */
10548     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10549   },
10550   {
10551     /* MOD_0F38F9_PREFIX_0 */
10552     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10553   },
10554   {
10555     /* MOD_62_32BIT */
10556     { "bound{S|}",      { Gv, Ma }, 0 },
10557     { EVEX_TABLE (EVEX_0F) },
10558   },
10559   {
10560     /* MOD_C4_32BIT */
10561     { "lesS",           { Gv, Mp }, 0 },
10562     { VEX_C4_TABLE (VEX_0F) },
10563   },
10564   {
10565     /* MOD_C5_32BIT */
10566     { "ldsS",           { Gv, Mp }, 0 },
10567     { VEX_C5_TABLE (VEX_0F) },
10568   },
10569   {
10570     /* MOD_VEX_0F12_PREFIX_0 */
10571     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10572     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10573   },
10574   {
10575     /* MOD_VEX_0F13 */
10576     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10577   },
10578   {
10579     /* MOD_VEX_0F16_PREFIX_0 */
10580     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10581     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10582   },
10583   {
10584     /* MOD_VEX_0F17 */
10585     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10586   },
10587   {
10588     /* MOD_VEX_0F2B */
10589     { "vmovntpX",       { Mx, XM }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10608     { Bad_Opcode },
10609     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10613     { Bad_Opcode },
10614     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10618     { Bad_Opcode },
10619     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10623     { Bad_Opcode },
10624     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10628     { Bad_Opcode },
10629     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10633     { Bad_Opcode },
10634     { "knotw",          { MaskG, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10638     { Bad_Opcode },
10639     { "knotq",          { MaskG, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10643     { Bad_Opcode },
10644     { "knotb",          { MaskG, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10648     { Bad_Opcode },
10649     { "knotd",          { MaskG, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10653     { Bad_Opcode },
10654     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10658     { Bad_Opcode },
10659     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10663     { Bad_Opcode },
10664     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10668     { Bad_Opcode },
10669     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671  {
10672     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10688     { Bad_Opcode },
10689     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10693     { Bad_Opcode },
10694     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10698     { Bad_Opcode },
10699     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10703     { Bad_Opcode },
10704     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10708     { Bad_Opcode },
10709     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10713     { Bad_Opcode },
10714     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10718     { Bad_Opcode },
10719     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10723     { Bad_Opcode },
10724     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10728     { Bad_Opcode },
10729     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10733     { Bad_Opcode },
10734     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10738     { Bad_Opcode },
10739     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10743     { Bad_Opcode },
10744     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10745   },
10746   {
10747     /* MOD_VEX_0F50 */
10748     { Bad_Opcode },
10749     { "vmovmskpX",      { Gdq, XS }, 0 },
10750   },
10751   {
10752     /* MOD_VEX_0F71_REG_2 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10755   },
10756   {
10757     /* MOD_VEX_0F71_REG_4 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10760   },
10761   {
10762     /* MOD_VEX_0F71_REG_6 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10765   },
10766   {
10767     /* MOD_VEX_0F72_REG_2 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10770   },
10771   {
10772     /* MOD_VEX_0F72_REG_4 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10775   },
10776   {
10777     /* MOD_VEX_0F72_REG_6 */
10778     { Bad_Opcode },
10779     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10780   },
10781   {
10782     /* MOD_VEX_0F73_REG_2 */
10783     { Bad_Opcode },
10784     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10785   },
10786   {
10787     /* MOD_VEX_0F73_REG_3 */
10788     { Bad_Opcode },
10789     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10790   },
10791   {
10792     /* MOD_VEX_0F73_REG_6 */
10793     { Bad_Opcode },
10794     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10795   },
10796   {
10797     /* MOD_VEX_0F73_REG_7 */
10798     { Bad_Opcode },
10799     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10803     { "kmovw",          { Ew, MaskG }, 0 },
10804     { Bad_Opcode },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10808     { "kmovq",          { Eq, MaskG }, 0 },
10809     { Bad_Opcode },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10813     { "kmovb",          { Eb, MaskG }, 0 },
10814     { Bad_Opcode },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10818     { "kmovd",          { Ed, MaskG }, 0 },
10819     { Bad_Opcode },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovw",          { MaskG, Rdq }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10828     { Bad_Opcode },
10829     { "kmovb",          { MaskG, Rdq }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10833     { Bad_Opcode },
10834     { "kmovd",          { MaskG, Rdq }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10838     { Bad_Opcode },
10839     { "kmovq",          { MaskG, Rdq }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10843     { Bad_Opcode },
10844     { "kmovw",          { Gdq, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10848     { Bad_Opcode },
10849     { "kmovb",          { Gdq, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10853     { Bad_Opcode },
10854     { "kmovd",          { Gdq, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10858     { Bad_Opcode },
10859     { "kmovq",          { Gdq, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10863     { Bad_Opcode },
10864     { "kortestw", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10868     { Bad_Opcode },
10869     { "kortestq", { MaskG, MaskR }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10873     { Bad_Opcode },
10874     { "kortestb", { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10878     { Bad_Opcode },
10879     { "kortestd", { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10883     { Bad_Opcode },
10884     { "ktestw", { MaskG, MaskR }, 0 },
10885   },
10886   {
10887     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10888     { Bad_Opcode },
10889     { "ktestq", { MaskG, MaskR }, 0 },
10890   },
10891   {
10892     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10893     { Bad_Opcode },
10894     { "ktestb", { MaskG, MaskR }, 0 },
10895   },
10896   {
10897     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10898     { Bad_Opcode },
10899     { "ktestd", { MaskG, MaskR }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0FAE_REG_2 */
10903     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0FAE_REG_3 */
10907     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0FD7_PREFIX_2 */
10911     { Bad_Opcode },
10912     { "vpmovmskb",      { Gdq, XS }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_0FE7_PREFIX_2 */
10916     { "vmovntdq",       { Mx, XM }, 0 },
10917   },
10918   {
10919     /* MOD_VEX_0FF0_PREFIX_3 */
10920     { "vlddqu",         { XM, M }, 0 },
10921   },
10922   {
10923     /* MOD_VEX_0F381A_PREFIX_2 */
10924     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10925   },
10926   {
10927     /* MOD_VEX_0F382A_PREFIX_2 */
10928     { "vmovntdqa",      { XM, Mx }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_0F382C_PREFIX_2 */
10932     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10933   },
10934   {
10935     /* MOD_VEX_0F382D_PREFIX_2 */
10936     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10937   },
10938   {
10939     /* MOD_VEX_0F382E_PREFIX_2 */
10940     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10941   },
10942   {
10943     /* MOD_VEX_0F382F_PREFIX_2 */
10944     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10945   },
10946   {
10947     /* MOD_VEX_0F385A_PREFIX_2 */
10948     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10949   },
10950   {
10951     /* MOD_VEX_0F388C_PREFIX_2 */
10952     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10953   },
10954   {
10955     /* MOD_VEX_0F388E_PREFIX_2 */
10956     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10965     { Bad_Opcode },
10966     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10967   },
10968   {
10969     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10970     { Bad_Opcode },
10971     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10972   },
10973   {
10974     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10975     { Bad_Opcode },
10976     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10977   },
10978   {
10979     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10980     { Bad_Opcode },
10981     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10982   },
10983   {
10984     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10985     { Bad_Opcode },
10986     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10987   },
10988   {
10989     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10990     { Bad_Opcode },
10991     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10992   },
10993   {
10994     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10995     { Bad_Opcode },
10996     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10997   },
10998 #define NEED_MOD_TABLE
10999 #include "i386-dis-evex.h"
11000 #undef NEED_MOD_TABLE
11001 };
11002
11003 static const struct dis386 rm_table[][8] = {
11004   {
11005     /* RM_C6_REG_7 */
11006     { "xabort",         { Skip_MODRM, Ib }, 0 },
11007   },
11008   {
11009     /* RM_C7_REG_7 */
11010     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11011   },
11012   {
11013     /* RM_0F01_REG_0 */
11014     { Bad_Opcode },
11015     { "vmcall",         { Skip_MODRM }, 0 },
11016     { "vmlaunch",       { Skip_MODRM }, 0 },
11017     { "vmresume",       { Skip_MODRM }, 0 },
11018     { "vmxoff",         { Skip_MODRM }, 0 },
11019     { "pconfig",        { Skip_MODRM }, 0 },
11020   },
11021   {
11022     /* RM_0F01_REG_1 */
11023     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11024     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11025     { "clac",           { Skip_MODRM }, 0 },
11026     { "stac",           { Skip_MODRM }, 0 },
11027     { Bad_Opcode },
11028     { Bad_Opcode },
11029     { Bad_Opcode },
11030     { "encls",          { Skip_MODRM }, 0 },
11031   },
11032   {
11033     /* RM_0F01_REG_2 */
11034     { "xgetbv",         { Skip_MODRM }, 0 },
11035     { "xsetbv",         { Skip_MODRM }, 0 },
11036     { Bad_Opcode },
11037     { Bad_Opcode },
11038     { "vmfunc",         { Skip_MODRM }, 0 },
11039     { "xend",           { Skip_MODRM }, 0 },
11040     { "xtest",          { Skip_MODRM }, 0 },
11041     { "enclu",          { Skip_MODRM }, 0 },
11042   },
11043   {
11044     /* RM_0F01_REG_3 */
11045     { "vmrun",          { Skip_MODRM }, 0 },
11046     { "vmmcall",        { Skip_MODRM }, 0 },
11047     { "vmload",         { Skip_MODRM }, 0 },
11048     { "vmsave",         { Skip_MODRM }, 0 },
11049     { "stgi",           { Skip_MODRM }, 0 },
11050     { "clgi",           { Skip_MODRM }, 0 },
11051     { "skinit",         { Skip_MODRM }, 0 },
11052     { "invlpga",        { Skip_MODRM }, 0 },
11053   },
11054   {
11055     /* RM_0F01_REG_5 */
11056     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11057     { Bad_Opcode },
11058     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11059     { Bad_Opcode },
11060     { Bad_Opcode },
11061     { Bad_Opcode },
11062     { "rdpkru",         { Skip_MODRM }, 0 },
11063     { "wrpkru",         { Skip_MODRM }, 0 },
11064   },
11065   {
11066     /* RM_0F01_REG_7 */
11067     { "swapgs",         { Skip_MODRM }, 0  },
11068     { "rdtscp",         { Skip_MODRM }, 0  },
11069     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11070     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11071     { "clzero",         { Skip_MODRM }, 0  },
11072   },
11073   {
11074     /* RM_0F1E_MOD_3_REG_7 */
11075     { "nopQ",           { Ev }, 0 },
11076     { "nopQ",           { Ev }, 0 },
11077     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11078     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11079     { "nopQ",           { Ev }, 0 },
11080     { "nopQ",           { Ev }, 0 },
11081     { "nopQ",           { Ev }, 0 },
11082     { "nopQ",           { Ev }, 0 },
11083   },
11084   {
11085     /* RM_0FAE_REG_6 */
11086     { "mfence",         { Skip_MODRM }, 0 },
11087   },
11088   {
11089     /* RM_0FAE_REG_7 */
11090     { "sfence",         { Skip_MODRM }, 0 },
11091
11092   },
11093 };
11094
11095 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11096
11097 /* We use the high bit to indicate different name for the same
11098    prefix.  */
11099 #define REP_PREFIX      (0xf3 | 0x100)
11100 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11101 #define XRELEASE_PREFIX (0xf3 | 0x400)
11102 #define BND_PREFIX      (0xf2 | 0x400)
11103 #define NOTRACK_PREFIX  (0x3e | 0x100)
11104
11105 static int
11106 ckprefix (void)
11107 {
11108   int newrex, i, length;
11109   rex = 0;
11110   rex_ignored = 0;
11111   prefixes = 0;
11112   used_prefixes = 0;
11113   rex_used = 0;
11114   last_lock_prefix = -1;
11115   last_repz_prefix = -1;
11116   last_repnz_prefix = -1;
11117   last_data_prefix = -1;
11118   last_addr_prefix = -1;
11119   last_rex_prefix = -1;
11120   last_seg_prefix = -1;
11121   fwait_prefix = -1;
11122   active_seg_prefix = 0;
11123   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11124     all_prefixes[i] = 0;
11125   i = 0;
11126   length = 0;
11127   /* The maximum instruction length is 15bytes.  */
11128   while (length < MAX_CODE_LENGTH - 1)
11129     {
11130       FETCH_DATA (the_info, codep + 1);
11131       newrex = 0;
11132       switch (*codep)
11133         {
11134         /* REX prefixes family.  */
11135         case 0x40:
11136         case 0x41:
11137         case 0x42:
11138         case 0x43:
11139         case 0x44:
11140         case 0x45:
11141         case 0x46:
11142         case 0x47:
11143         case 0x48:
11144         case 0x49:
11145         case 0x4a:
11146         case 0x4b:
11147         case 0x4c:
11148         case 0x4d:
11149         case 0x4e:
11150         case 0x4f:
11151           if (address_mode == mode_64bit)
11152             newrex = *codep;
11153           else
11154             return 1;
11155           last_rex_prefix = i;
11156           break;
11157         case 0xf3:
11158           prefixes |= PREFIX_REPZ;
11159           last_repz_prefix = i;
11160           break;
11161         case 0xf2:
11162           prefixes |= PREFIX_REPNZ;
11163           last_repnz_prefix = i;
11164           break;
11165         case 0xf0:
11166           prefixes |= PREFIX_LOCK;
11167           last_lock_prefix = i;
11168           break;
11169         case 0x2e:
11170           prefixes |= PREFIX_CS;
11171           last_seg_prefix = i;
11172           active_seg_prefix = PREFIX_CS;
11173           break;
11174         case 0x36:
11175           prefixes |= PREFIX_SS;
11176           last_seg_prefix = i;
11177           active_seg_prefix = PREFIX_SS;
11178           break;
11179         case 0x3e:
11180           prefixes |= PREFIX_DS;
11181           last_seg_prefix = i;
11182           active_seg_prefix = PREFIX_DS;
11183           break;
11184         case 0x26:
11185           prefixes |= PREFIX_ES;
11186           last_seg_prefix = i;
11187           active_seg_prefix = PREFIX_ES;
11188           break;
11189         case 0x64:
11190           prefixes |= PREFIX_FS;
11191           last_seg_prefix = i;
11192           active_seg_prefix = PREFIX_FS;
11193           break;
11194         case 0x65:
11195           prefixes |= PREFIX_GS;
11196           last_seg_prefix = i;
11197           active_seg_prefix = PREFIX_GS;
11198           break;
11199         case 0x66:
11200           prefixes |= PREFIX_DATA;
11201           last_data_prefix = i;
11202           break;
11203         case 0x67:
11204           prefixes |= PREFIX_ADDR;
11205           last_addr_prefix = i;
11206           break;
11207         case FWAIT_OPCODE:
11208           /* fwait is really an instruction.  If there are prefixes
11209              before the fwait, they belong to the fwait, *not* to the
11210              following instruction.  */
11211           fwait_prefix = i;
11212           if (prefixes || rex)
11213             {
11214               prefixes |= PREFIX_FWAIT;
11215               codep++;
11216               /* This ensures that the previous REX prefixes are noticed
11217                  as unused prefixes, as in the return case below.  */
11218               rex_used = rex;
11219               return 1;
11220             }
11221           prefixes = PREFIX_FWAIT;
11222           break;
11223         default:
11224           return 1;
11225         }
11226       /* Rex is ignored when followed by another prefix.  */
11227       if (rex)
11228         {
11229           rex_used = rex;
11230           return 1;
11231         }
11232       if (*codep != FWAIT_OPCODE)
11233         all_prefixes[i++] = *codep;
11234       rex = newrex;
11235       codep++;
11236       length++;
11237     }
11238   return 0;
11239 }
11240
11241 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11242    prefix byte.  */
11243
11244 static const char *
11245 prefix_name (int pref, int sizeflag)
11246 {
11247   static const char *rexes [16] =
11248     {
11249       "rex",            /* 0x40 */
11250       "rex.B",          /* 0x41 */
11251       "rex.X",          /* 0x42 */
11252       "rex.XB",         /* 0x43 */
11253       "rex.R",          /* 0x44 */
11254       "rex.RB",         /* 0x45 */
11255       "rex.RX",         /* 0x46 */
11256       "rex.RXB",        /* 0x47 */
11257       "rex.W",          /* 0x48 */
11258       "rex.WB",         /* 0x49 */
11259       "rex.WX",         /* 0x4a */
11260       "rex.WXB",        /* 0x4b */
11261       "rex.WR",         /* 0x4c */
11262       "rex.WRB",        /* 0x4d */
11263       "rex.WRX",        /* 0x4e */
11264       "rex.WRXB",       /* 0x4f */
11265     };
11266
11267   switch (pref)
11268     {
11269     /* REX prefixes family.  */
11270     case 0x40:
11271     case 0x41:
11272     case 0x42:
11273     case 0x43:
11274     case 0x44:
11275     case 0x45:
11276     case 0x46:
11277     case 0x47:
11278     case 0x48:
11279     case 0x49:
11280     case 0x4a:
11281     case 0x4b:
11282     case 0x4c:
11283     case 0x4d:
11284     case 0x4e:
11285     case 0x4f:
11286       return rexes [pref - 0x40];
11287     case 0xf3:
11288       return "repz";
11289     case 0xf2:
11290       return "repnz";
11291     case 0xf0:
11292       return "lock";
11293     case 0x2e:
11294       return "cs";
11295     case 0x36:
11296       return "ss";
11297     case 0x3e:
11298       return "ds";
11299     case 0x26:
11300       return "es";
11301     case 0x64:
11302       return "fs";
11303     case 0x65:
11304       return "gs";
11305     case 0x66:
11306       return (sizeflag & DFLAG) ? "data16" : "data32";
11307     case 0x67:
11308       if (address_mode == mode_64bit)
11309         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11310       else
11311         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11312     case FWAIT_OPCODE:
11313       return "fwait";
11314     case REP_PREFIX:
11315       return "rep";
11316     case XACQUIRE_PREFIX:
11317       return "xacquire";
11318     case XRELEASE_PREFIX:
11319       return "xrelease";
11320     case BND_PREFIX:
11321       return "bnd";
11322     case NOTRACK_PREFIX:
11323       return "notrack";
11324     default:
11325       return NULL;
11326     }
11327 }
11328
11329 static char op_out[MAX_OPERANDS][100];
11330 static int op_ad, op_index[MAX_OPERANDS];
11331 static int two_source_ops;
11332 static bfd_vma op_address[MAX_OPERANDS];
11333 static bfd_vma op_riprel[MAX_OPERANDS];
11334 static bfd_vma start_pc;
11335
11336 /*
11337  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11338  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11339  *   section of the "Virtual 8086 Mode" chapter.)
11340  * 'pc' should be the address of this instruction, it will
11341  *   be used to print the target address if this is a relative jump or call
11342  * The function returns the length of this instruction in bytes.
11343  */
11344
11345 static char intel_syntax;
11346 static char intel_mnemonic = !SYSV386_COMPAT;
11347 static char open_char;
11348 static char close_char;
11349 static char separator_char;
11350 static char scale_char;
11351
11352 enum x86_64_isa
11353 {
11354   amd64 = 0,
11355   intel64
11356 };
11357
11358 static enum x86_64_isa isa64;
11359
11360 /* Here for backwards compatibility.  When gdb stops using
11361    print_insn_i386_att and print_insn_i386_intel these functions can
11362    disappear, and print_insn_i386 be merged into print_insn.  */
11363 int
11364 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11365 {
11366   intel_syntax = 0;
11367
11368   return print_insn (pc, info);
11369 }
11370
11371 int
11372 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11373 {
11374   intel_syntax = 1;
11375
11376   return print_insn (pc, info);
11377 }
11378
11379 int
11380 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11381 {
11382   intel_syntax = -1;
11383
11384   return print_insn (pc, info);
11385 }
11386
11387 void
11388 print_i386_disassembler_options (FILE *stream)
11389 {
11390   fprintf (stream, _("\n\
11391 The following i386/x86-64 specific disassembler options are supported for use\n\
11392 with the -M switch (multiple options should be separated by commas):\n"));
11393
11394   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11395   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11396   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11397   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11398   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11399   fprintf (stream, _("  att-mnemonic\n"
11400                      "              Display instruction in AT&T mnemonic\n"));
11401   fprintf (stream, _("  intel-mnemonic\n"
11402                      "              Display instruction in Intel mnemonic\n"));
11403   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11404   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11405   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11406   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11407   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11408   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11409   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11410   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11411 }
11412
11413 /* Bad opcode.  */
11414 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11415
11416 /* Get a pointer to struct dis386 with a valid name.  */
11417
11418 static const struct dis386 *
11419 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11420 {
11421   int vindex, vex_table_index;
11422
11423   if (dp->name != NULL)
11424     return dp;
11425
11426   switch (dp->op[0].bytemode)
11427     {
11428     case USE_REG_TABLE:
11429       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11430       break;
11431
11432     case USE_MOD_TABLE:
11433       vindex = modrm.mod == 0x3 ? 1 : 0;
11434       dp = &mod_table[dp->op[1].bytemode][vindex];
11435       break;
11436
11437     case USE_RM_TABLE:
11438       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11439       break;
11440
11441     case USE_PREFIX_TABLE:
11442       if (need_vex)
11443         {
11444           /* The prefix in VEX is implicit.  */
11445           switch (vex.prefix)
11446             {
11447             case 0:
11448               vindex = 0;
11449               break;
11450             case REPE_PREFIX_OPCODE:
11451               vindex = 1;
11452               break;
11453             case DATA_PREFIX_OPCODE:
11454               vindex = 2;
11455               break;
11456             case REPNE_PREFIX_OPCODE:
11457               vindex = 3;
11458               break;
11459             default:
11460               abort ();
11461               break;
11462             }
11463         }
11464       else
11465         {
11466           int last_prefix = -1;
11467           int prefix = 0;
11468           vindex = 0;
11469           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11470              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11471              last one wins.  */
11472           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11473             {
11474               if (last_repz_prefix > last_repnz_prefix)
11475                 {
11476                   vindex = 1;
11477                   prefix = PREFIX_REPZ;
11478                   last_prefix = last_repz_prefix;
11479                 }
11480               else
11481                 {
11482                   vindex = 3;
11483                   prefix = PREFIX_REPNZ;
11484                   last_prefix = last_repnz_prefix;
11485                 }
11486
11487               /* Check if prefix should be ignored.  */
11488               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11489                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11490                    & prefix) != 0)
11491                 vindex = 0;
11492             }
11493
11494           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11495             {
11496               vindex = 2;
11497               prefix = PREFIX_DATA;
11498               last_prefix = last_data_prefix;
11499             }
11500
11501           if (vindex != 0)
11502             {
11503               used_prefixes |= prefix;
11504               all_prefixes[last_prefix] = 0;
11505             }
11506         }
11507       dp = &prefix_table[dp->op[1].bytemode][vindex];
11508       break;
11509
11510     case USE_X86_64_TABLE:
11511       vindex = address_mode == mode_64bit ? 1 : 0;
11512       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11513       break;
11514
11515     case USE_3BYTE_TABLE:
11516       FETCH_DATA (info, codep + 2);
11517       vindex = *codep++;
11518       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11519       end_codep = codep;
11520       modrm.mod = (*codep >> 6) & 3;
11521       modrm.reg = (*codep >> 3) & 7;
11522       modrm.rm = *codep & 7;
11523       break;
11524
11525     case USE_VEX_LEN_TABLE:
11526       if (!need_vex)
11527         abort ();
11528
11529       switch (vex.length)
11530         {
11531         case 128:
11532           vindex = 0;
11533           break;
11534         case 256:
11535           vindex = 1;
11536           break;
11537         default:
11538           abort ();
11539           break;
11540         }
11541
11542       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11543       break;
11544
11545     case USE_XOP_8F_TABLE:
11546       FETCH_DATA (info, codep + 3);
11547       /* All bits in the REX prefix are ignored.  */
11548       rex_ignored = rex;
11549       rex = ~(*codep >> 5) & 0x7;
11550
11551       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11552       switch ((*codep & 0x1f))
11553         {
11554         default:
11555           dp = &bad_opcode;
11556           return dp;
11557         case 0x8:
11558           vex_table_index = XOP_08;
11559           break;
11560         case 0x9:
11561           vex_table_index = XOP_09;
11562           break;
11563         case 0xa:
11564           vex_table_index = XOP_0A;
11565           break;
11566         }
11567       codep++;
11568       vex.w = *codep & 0x80;
11569       if (vex.w && address_mode == mode_64bit)
11570         rex |= REX_W;
11571
11572       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11573       if (address_mode != mode_64bit)
11574         {
11575           /* In 16/32-bit mode REX_B is silently ignored.  */
11576           rex &= ~REX_B;
11577         }
11578
11579       vex.length = (*codep & 0x4) ? 256 : 128;
11580       switch ((*codep & 0x3))
11581         {
11582         case 0:
11583           break;
11584         case 1:
11585           vex.prefix = DATA_PREFIX_OPCODE;
11586           break;
11587         case 2:
11588           vex.prefix = REPE_PREFIX_OPCODE;
11589           break;
11590         case 3:
11591           vex.prefix = REPNE_PREFIX_OPCODE;
11592           break;
11593         }
11594       need_vex = 1;
11595       need_vex_reg = 1;
11596       codep++;
11597       vindex = *codep++;
11598       dp = &xop_table[vex_table_index][vindex];
11599
11600       end_codep = codep;
11601       FETCH_DATA (info, codep + 1);
11602       modrm.mod = (*codep >> 6) & 3;
11603       modrm.reg = (*codep >> 3) & 7;
11604       modrm.rm = *codep & 7;
11605       break;
11606
11607     case USE_VEX_C4_TABLE:
11608       /* VEX prefix.  */
11609       FETCH_DATA (info, codep + 3);
11610       /* All bits in the REX prefix are ignored.  */
11611       rex_ignored = rex;
11612       rex = ~(*codep >> 5) & 0x7;
11613       switch ((*codep & 0x1f))
11614         {
11615         default:
11616           dp = &bad_opcode;
11617           return dp;
11618         case 0x1:
11619           vex_table_index = VEX_0F;
11620           break;
11621         case 0x2:
11622           vex_table_index = VEX_0F38;
11623           break;
11624         case 0x3:
11625           vex_table_index = VEX_0F3A;
11626           break;
11627         }
11628       codep++;
11629       vex.w = *codep & 0x80;
11630       if (address_mode == mode_64bit)
11631         {
11632           if (vex.w)
11633             rex |= REX_W;
11634         }
11635       else
11636         {
11637           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11638              is ignored, other REX bits are 0 and the highest bit in
11639              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11640           rex = 0;
11641         }
11642       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11643       vex.length = (*codep & 0x4) ? 256 : 128;
11644       switch ((*codep & 0x3))
11645         {
11646         case 0:
11647           break;
11648         case 1:
11649           vex.prefix = DATA_PREFIX_OPCODE;
11650           break;
11651         case 2:
11652           vex.prefix = REPE_PREFIX_OPCODE;
11653           break;
11654         case 3:
11655           vex.prefix = REPNE_PREFIX_OPCODE;
11656           break;
11657         }
11658       need_vex = 1;
11659       need_vex_reg = 1;
11660       codep++;
11661       vindex = *codep++;
11662       dp = &vex_table[vex_table_index][vindex];
11663       end_codep = codep;
11664       /* There is no MODRM byte for VEX0F 77.  */
11665       if (vex_table_index != VEX_0F || vindex != 0x77)
11666         {
11667           FETCH_DATA (info, codep + 1);
11668           modrm.mod = (*codep >> 6) & 3;
11669           modrm.reg = (*codep >> 3) & 7;
11670           modrm.rm = *codep & 7;
11671         }
11672       break;
11673
11674     case USE_VEX_C5_TABLE:
11675       /* VEX prefix.  */
11676       FETCH_DATA (info, codep + 2);
11677       /* All bits in the REX prefix are ignored.  */
11678       rex_ignored = rex;
11679       rex = (*codep & 0x80) ? 0 : REX_R;
11680
11681       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11682          VEX.vvvv is 1.  */
11683       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11684       vex.length = (*codep & 0x4) ? 256 : 128;
11685       switch ((*codep & 0x3))
11686         {
11687         case 0:
11688           break;
11689         case 1:
11690           vex.prefix = DATA_PREFIX_OPCODE;
11691           break;
11692         case 2:
11693           vex.prefix = REPE_PREFIX_OPCODE;
11694           break;
11695         case 3:
11696           vex.prefix = REPNE_PREFIX_OPCODE;
11697           break;
11698         }
11699       need_vex = 1;
11700       need_vex_reg = 1;
11701       codep++;
11702       vindex = *codep++;
11703       dp = &vex_table[dp->op[1].bytemode][vindex];
11704       end_codep = codep;
11705       /* There is no MODRM byte for VEX 77.  */
11706       if (vindex != 0x77)
11707         {
11708           FETCH_DATA (info, codep + 1);
11709           modrm.mod = (*codep >> 6) & 3;
11710           modrm.reg = (*codep >> 3) & 7;
11711           modrm.rm = *codep & 7;
11712         }
11713       break;
11714
11715     case USE_VEX_W_TABLE:
11716       if (!need_vex)
11717         abort ();
11718
11719       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11720       break;
11721
11722     case USE_EVEX_TABLE:
11723       two_source_ops = 0;
11724       /* EVEX prefix.  */
11725       vex.evex = 1;
11726       FETCH_DATA (info, codep + 4);
11727       /* All bits in the REX prefix are ignored.  */
11728       rex_ignored = rex;
11729       /* The first byte after 0x62.  */
11730       rex = ~(*codep >> 5) & 0x7;
11731       vex.r = *codep & 0x10;
11732       switch ((*codep & 0xf))
11733         {
11734         default:
11735           return &bad_opcode;
11736         case 0x1:
11737           vex_table_index = EVEX_0F;
11738           break;
11739         case 0x2:
11740           vex_table_index = EVEX_0F38;
11741           break;
11742         case 0x3:
11743           vex_table_index = EVEX_0F3A;
11744           break;
11745         }
11746
11747       /* The second byte after 0x62.  */
11748       codep++;
11749       vex.w = *codep & 0x80;
11750       if (vex.w && address_mode == mode_64bit)
11751         rex |= REX_W;
11752
11753       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11754
11755       /* The U bit.  */
11756       if (!(*codep & 0x4))
11757         return &bad_opcode;
11758
11759       switch ((*codep & 0x3))
11760         {
11761         case 0:
11762           break;
11763         case 1:
11764           vex.prefix = DATA_PREFIX_OPCODE;
11765           break;
11766         case 2:
11767           vex.prefix = REPE_PREFIX_OPCODE;
11768           break;
11769         case 3:
11770           vex.prefix = REPNE_PREFIX_OPCODE;
11771           break;
11772         }
11773
11774       /* The third byte after 0x62.  */
11775       codep++;
11776
11777       /* Remember the static rounding bits.  */
11778       vex.ll = (*codep >> 5) & 3;
11779       vex.b = (*codep & 0x10) != 0;
11780
11781       vex.v = *codep & 0x8;
11782       vex.mask_register_specifier = *codep & 0x7;
11783       vex.zeroing = *codep & 0x80;
11784
11785       if (address_mode != mode_64bit)
11786         {
11787           /* In 16/32-bit mode silently ignore following bits.  */
11788           rex &= ~REX_B;
11789           vex.r = 1;
11790           vex.v = 1;
11791         }
11792
11793       need_vex = 1;
11794       need_vex_reg = 1;
11795       codep++;
11796       vindex = *codep++;
11797       dp = &evex_table[vex_table_index][vindex];
11798       end_codep = codep;
11799       FETCH_DATA (info, codep + 1);
11800       modrm.mod = (*codep >> 6) & 3;
11801       modrm.reg = (*codep >> 3) & 7;
11802       modrm.rm = *codep & 7;
11803
11804       /* Set vector length.  */
11805       if (modrm.mod == 3 && vex.b)
11806         vex.length = 512;
11807       else
11808         {
11809           switch (vex.ll)
11810             {
11811             case 0x0:
11812               vex.length = 128;
11813               break;
11814             case 0x1:
11815               vex.length = 256;
11816               break;
11817             case 0x2:
11818               vex.length = 512;
11819               break;
11820             default:
11821               return &bad_opcode;
11822             }
11823         }
11824       break;
11825
11826     case 0:
11827       dp = &bad_opcode;
11828       break;
11829
11830     default:
11831       abort ();
11832     }
11833
11834   if (dp->name != NULL)
11835     return dp;
11836   else
11837     return get_valid_dis386 (dp, info);
11838 }
11839
11840 static void
11841 get_sib (disassemble_info *info, int sizeflag)
11842 {
11843   /* If modrm.mod == 3, operand must be register.  */
11844   if (need_modrm
11845       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11846       && modrm.mod != 3
11847       && modrm.rm == 4)
11848     {
11849       FETCH_DATA (info, codep + 2);
11850       sib.index = (codep [1] >> 3) & 7;
11851       sib.scale = (codep [1] >> 6) & 3;
11852       sib.base = codep [1] & 7;
11853     }
11854 }
11855
11856 static int
11857 print_insn (bfd_vma pc, disassemble_info *info)
11858 {
11859   const struct dis386 *dp;
11860   int i;
11861   char *op_txt[MAX_OPERANDS];
11862   int needcomma;
11863   int sizeflag, orig_sizeflag;
11864   const char *p;
11865   struct dis_private priv;
11866   int prefix_length;
11867
11868   priv.orig_sizeflag = AFLAG | DFLAG;
11869   if ((info->mach & bfd_mach_i386_i386) != 0)
11870     address_mode = mode_32bit;
11871   else if (info->mach == bfd_mach_i386_i8086)
11872     {
11873       address_mode = mode_16bit;
11874       priv.orig_sizeflag = 0;
11875     }
11876   else
11877     address_mode = mode_64bit;
11878
11879   if (intel_syntax == (char) -1)
11880     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11881
11882   for (p = info->disassembler_options; p != NULL; )
11883     {
11884       if (CONST_STRNEQ (p, "amd64"))
11885         isa64 = amd64;
11886       else if (CONST_STRNEQ (p, "intel64"))
11887         isa64 = intel64;
11888       else if (CONST_STRNEQ (p, "x86-64"))
11889         {
11890           address_mode = mode_64bit;
11891           priv.orig_sizeflag = AFLAG | DFLAG;
11892         }
11893       else if (CONST_STRNEQ (p, "i386"))
11894         {
11895           address_mode = mode_32bit;
11896           priv.orig_sizeflag = AFLAG | DFLAG;
11897         }
11898       else if (CONST_STRNEQ (p, "i8086"))
11899         {
11900           address_mode = mode_16bit;
11901           priv.orig_sizeflag = 0;
11902         }
11903       else if (CONST_STRNEQ (p, "intel"))
11904         {
11905           intel_syntax = 1;
11906           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11907             intel_mnemonic = 1;
11908         }
11909       else if (CONST_STRNEQ (p, "att"))
11910         {
11911           intel_syntax = 0;
11912           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11913             intel_mnemonic = 0;
11914         }
11915       else if (CONST_STRNEQ (p, "addr"))
11916         {
11917           if (address_mode == mode_64bit)
11918             {
11919               if (p[4] == '3' && p[5] == '2')
11920                 priv.orig_sizeflag &= ~AFLAG;
11921               else if (p[4] == '6' && p[5] == '4')
11922                 priv.orig_sizeflag |= AFLAG;
11923             }
11924           else
11925             {
11926               if (p[4] == '1' && p[5] == '6')
11927                 priv.orig_sizeflag &= ~AFLAG;
11928               else if (p[4] == '3' && p[5] == '2')
11929                 priv.orig_sizeflag |= AFLAG;
11930             }
11931         }
11932       else if (CONST_STRNEQ (p, "data"))
11933         {
11934           if (p[4] == '1' && p[5] == '6')
11935             priv.orig_sizeflag &= ~DFLAG;
11936           else if (p[4] == '3' && p[5] == '2')
11937             priv.orig_sizeflag |= DFLAG;
11938         }
11939       else if (CONST_STRNEQ (p, "suffix"))
11940         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11941
11942       p = strchr (p, ',');
11943       if (p != NULL)
11944         p++;
11945     }
11946
11947   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11948     {
11949       (*info->fprintf_func) (info->stream,
11950                              _("64-bit address is disabled"));
11951       return -1;
11952     }
11953
11954   if (intel_syntax)
11955     {
11956       names64 = intel_names64;
11957       names32 = intel_names32;
11958       names16 = intel_names16;
11959       names8 = intel_names8;
11960       names8rex = intel_names8rex;
11961       names_seg = intel_names_seg;
11962       names_mm = intel_names_mm;
11963       names_bnd = intel_names_bnd;
11964       names_xmm = intel_names_xmm;
11965       names_ymm = intel_names_ymm;
11966       names_zmm = intel_names_zmm;
11967       index64 = intel_index64;
11968       index32 = intel_index32;
11969       names_mask = intel_names_mask;
11970       index16 = intel_index16;
11971       open_char = '[';
11972       close_char = ']';
11973       separator_char = '+';
11974       scale_char = '*';
11975     }
11976   else
11977     {
11978       names64 = att_names64;
11979       names32 = att_names32;
11980       names16 = att_names16;
11981       names8 = att_names8;
11982       names8rex = att_names8rex;
11983       names_seg = att_names_seg;
11984       names_mm = att_names_mm;
11985       names_bnd = att_names_bnd;
11986       names_xmm = att_names_xmm;
11987       names_ymm = att_names_ymm;
11988       names_zmm = att_names_zmm;
11989       index64 = att_index64;
11990       index32 = att_index32;
11991       names_mask = att_names_mask;
11992       index16 = att_index16;
11993       open_char = '(';
11994       close_char =  ')';
11995       separator_char = ',';
11996       scale_char = ',';
11997     }
11998
11999   /* The output looks better if we put 7 bytes on a line, since that
12000      puts most long word instructions on a single line.  Use 8 bytes
12001      for Intel L1OM.  */
12002   if ((info->mach & bfd_mach_l1om) != 0)
12003     info->bytes_per_line = 8;
12004   else
12005     info->bytes_per_line = 7;
12006
12007   info->private_data = &priv;
12008   priv.max_fetched = priv.the_buffer;
12009   priv.insn_start = pc;
12010
12011   obuf[0] = 0;
12012   for (i = 0; i < MAX_OPERANDS; ++i)
12013     {
12014       op_out[i][0] = 0;
12015       op_index[i] = -1;
12016     }
12017
12018   the_info = info;
12019   start_pc = pc;
12020   start_codep = priv.the_buffer;
12021   codep = priv.the_buffer;
12022
12023   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12024     {
12025       const char *name;
12026
12027       /* Getting here means we tried for data but didn't get it.  That
12028          means we have an incomplete instruction of some sort.  Just
12029          print the first byte as a prefix or a .byte pseudo-op.  */
12030       if (codep > priv.the_buffer)
12031         {
12032           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12033           if (name != NULL)
12034             (*info->fprintf_func) (info->stream, "%s", name);
12035           else
12036             {
12037               /* Just print the first byte as a .byte instruction.  */
12038               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12039                                      (unsigned int) priv.the_buffer[0]);
12040             }
12041
12042           return 1;
12043         }
12044
12045       return -1;
12046     }
12047
12048   obufp = obuf;
12049   sizeflag = priv.orig_sizeflag;
12050
12051   if (!ckprefix () || rex_used)
12052     {
12053       /* Too many prefixes or unused REX prefixes.  */
12054       for (i = 0;
12055            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12056            i++)
12057         (*info->fprintf_func) (info->stream, "%s%s",
12058                                i == 0 ? "" : " ",
12059                                prefix_name (all_prefixes[i], sizeflag));
12060       return i;
12061     }
12062
12063   insn_codep = codep;
12064
12065   FETCH_DATA (info, codep + 1);
12066   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12067
12068   if (((prefixes & PREFIX_FWAIT)
12069        && ((*codep < 0xd8) || (*codep > 0xdf))))
12070     {
12071       /* Handle prefixes before fwait.  */
12072       for (i = 0; i < fwait_prefix && all_prefixes[i];
12073            i++)
12074         (*info->fprintf_func) (info->stream, "%s ",
12075                                prefix_name (all_prefixes[i], sizeflag));
12076       (*info->fprintf_func) (info->stream, "fwait");
12077       return i + 1;
12078     }
12079
12080   if (*codep == 0x0f)
12081     {
12082       unsigned char threebyte;
12083
12084       codep++;
12085       FETCH_DATA (info, codep + 1);
12086       threebyte = *codep;
12087       dp = &dis386_twobyte[threebyte];
12088       need_modrm = twobyte_has_modrm[*codep];
12089       codep++;
12090     }
12091   else
12092     {
12093       dp = &dis386[*codep];
12094       need_modrm = onebyte_has_modrm[*codep];
12095       codep++;
12096     }
12097
12098   /* Save sizeflag for printing the extra prefixes later before updating
12099      it for mnemonic and operand processing.  The prefix names depend
12100      only on the address mode.  */
12101   orig_sizeflag = sizeflag;
12102   if (prefixes & PREFIX_ADDR)
12103     sizeflag ^= AFLAG;
12104   if ((prefixes & PREFIX_DATA))
12105     sizeflag ^= DFLAG;
12106
12107   end_codep = codep;
12108   if (need_modrm)
12109     {
12110       FETCH_DATA (info, codep + 1);
12111       modrm.mod = (*codep >> 6) & 3;
12112       modrm.reg = (*codep >> 3) & 7;
12113       modrm.rm = *codep & 7;
12114     }
12115
12116   need_vex = 0;
12117   need_vex_reg = 0;
12118   vex_w_done = 0;
12119   memset (&vex, 0, sizeof (vex));
12120
12121   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12122     {
12123       get_sib (info, sizeflag);
12124       dofloat (sizeflag);
12125     }
12126   else
12127     {
12128       dp = get_valid_dis386 (dp, info);
12129       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12130         {
12131           get_sib (info, sizeflag);
12132           for (i = 0; i < MAX_OPERANDS; ++i)
12133             {
12134               obufp = op_out[i];
12135               op_ad = MAX_OPERANDS - 1 - i;
12136               if (dp->op[i].rtn)
12137                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12138               /* For EVEX instruction after the last operand masking
12139                  should be printed.  */
12140               if (i == 0 && vex.evex)
12141                 {
12142                   /* Don't print {%k0}.  */
12143                   if (vex.mask_register_specifier)
12144                     {
12145                       oappend ("{");
12146                       oappend (names_mask[vex.mask_register_specifier]);
12147                       oappend ("}");
12148                     }
12149                   if (vex.zeroing)
12150                     oappend ("{z}");
12151                 }
12152             }
12153         }
12154     }
12155
12156   /* Check if the REX prefix is used.  */
12157   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12158     all_prefixes[last_rex_prefix] = 0;
12159
12160   /* Check if the SEG prefix is used.  */
12161   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12162                    | PREFIX_FS | PREFIX_GS)) != 0
12163       && (used_prefixes & active_seg_prefix) != 0)
12164     all_prefixes[last_seg_prefix] = 0;
12165
12166   /* Check if the ADDR prefix is used.  */
12167   if ((prefixes & PREFIX_ADDR) != 0
12168       && (used_prefixes & PREFIX_ADDR) != 0)
12169     all_prefixes[last_addr_prefix] = 0;
12170
12171   /* Check if the DATA prefix is used.  */
12172   if ((prefixes & PREFIX_DATA) != 0
12173       && (used_prefixes & PREFIX_DATA) != 0)
12174     all_prefixes[last_data_prefix] = 0;
12175
12176   /* Print the extra prefixes.  */
12177   prefix_length = 0;
12178   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12179     if (all_prefixes[i])
12180       {
12181         const char *name;
12182         name = prefix_name (all_prefixes[i], orig_sizeflag);
12183         if (name == NULL)
12184           abort ();
12185         prefix_length += strlen (name) + 1;
12186         (*info->fprintf_func) (info->stream, "%s ", name);
12187       }
12188
12189   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12190      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12191      used by putop and MMX/SSE operand and may be overriden by the
12192      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12193      separately.  */
12194   if (dp->prefix_requirement == PREFIX_OPCODE
12195       && dp != &bad_opcode
12196       && (((prefixes
12197             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12198            && (used_prefixes
12199                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12200           || ((((prefixes
12201                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12202                 == PREFIX_DATA)
12203                && (used_prefixes & PREFIX_DATA) == 0))))
12204     {
12205       (*info->fprintf_func) (info->stream, "(bad)");
12206       return end_codep - priv.the_buffer;
12207     }
12208
12209   /* Check maximum code length.  */
12210   if ((codep - start_codep) > MAX_CODE_LENGTH)
12211     {
12212       (*info->fprintf_func) (info->stream, "(bad)");
12213       return MAX_CODE_LENGTH;
12214     }
12215
12216   obufp = mnemonicendp;
12217   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12218     oappend (" ");
12219   oappend (" ");
12220   (*info->fprintf_func) (info->stream, "%s", obuf);
12221
12222   /* The enter and bound instructions are printed with operands in the same
12223      order as the intel book; everything else is printed in reverse order.  */
12224   if (intel_syntax || two_source_ops)
12225     {
12226       bfd_vma riprel;
12227
12228       for (i = 0; i < MAX_OPERANDS; ++i)
12229         op_txt[i] = op_out[i];
12230
12231       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12232           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12233         {
12234           op_txt[2] = op_out[3];
12235           op_txt[3] = op_out[2];
12236         }
12237
12238       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12239         {
12240           op_ad = op_index[i];
12241           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12242           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12243           riprel = op_riprel[i];
12244           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12245           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12246         }
12247     }
12248   else
12249     {
12250       for (i = 0; i < MAX_OPERANDS; ++i)
12251         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12252     }
12253
12254   needcomma = 0;
12255   for (i = 0; i < MAX_OPERANDS; ++i)
12256     if (*op_txt[i])
12257       {
12258         if (needcomma)
12259           (*info->fprintf_func) (info->stream, ",");
12260         if (op_index[i] != -1 && !op_riprel[i])
12261           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12262         else
12263           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12264         needcomma = 1;
12265       }
12266
12267   for (i = 0; i < MAX_OPERANDS; i++)
12268     if (op_index[i] != -1 && op_riprel[i])
12269       {
12270         (*info->fprintf_func) (info->stream, "        # ");
12271         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12272                                                 + op_address[op_index[i]]), info);
12273         break;
12274       }
12275   return codep - priv.the_buffer;
12276 }
12277
12278 static const char *float_mem[] = {
12279   /* d8 */
12280   "fadd{s|}",
12281   "fmul{s|}",
12282   "fcom{s|}",
12283   "fcomp{s|}",
12284   "fsub{s|}",
12285   "fsubr{s|}",
12286   "fdiv{s|}",
12287   "fdivr{s|}",
12288   /* d9 */
12289   "fld{s|}",
12290   "(bad)",
12291   "fst{s|}",
12292   "fstp{s|}",
12293   "fldenvIC",
12294   "fldcw",
12295   "fNstenvIC",
12296   "fNstcw",
12297   /* da */
12298   "fiadd{l|}",
12299   "fimul{l|}",
12300   "ficom{l|}",
12301   "ficomp{l|}",
12302   "fisub{l|}",
12303   "fisubr{l|}",
12304   "fidiv{l|}",
12305   "fidivr{l|}",
12306   /* db */
12307   "fild{l|}",
12308   "fisttp{l|}",
12309   "fist{l|}",
12310   "fistp{l|}",
12311   "(bad)",
12312   "fld{t||t|}",
12313   "(bad)",
12314   "fstp{t||t|}",
12315   /* dc */
12316   "fadd{l|}",
12317   "fmul{l|}",
12318   "fcom{l|}",
12319   "fcomp{l|}",
12320   "fsub{l|}",
12321   "fsubr{l|}",
12322   "fdiv{l|}",
12323   "fdivr{l|}",
12324   /* dd */
12325   "fld{l|}",
12326   "fisttp{ll|}",
12327   "fst{l||}",
12328   "fstp{l|}",
12329   "frstorIC",
12330   "(bad)",
12331   "fNsaveIC",
12332   "fNstsw",
12333   /* de */
12334   "fiadd{s|}",
12335   "fimul{s|}",
12336   "ficom{s|}",
12337   "ficomp{s|}",
12338   "fisub{s|}",
12339   "fisubr{s|}",
12340   "fidiv{s|}",
12341   "fidivr{s|}",
12342   /* df */
12343   "fild{s|}",
12344   "fisttp{s|}",
12345   "fist{s|}",
12346   "fistp{s|}",
12347   "fbld",
12348   "fild{ll|}",
12349   "fbstp",
12350   "fistp{ll|}",
12351 };
12352
12353 static const unsigned char float_mem_mode[] = {
12354   /* d8 */
12355   d_mode,
12356   d_mode,
12357   d_mode,
12358   d_mode,
12359   d_mode,
12360   d_mode,
12361   d_mode,
12362   d_mode,
12363   /* d9 */
12364   d_mode,
12365   0,
12366   d_mode,
12367   d_mode,
12368   0,
12369   w_mode,
12370   0,
12371   w_mode,
12372   /* da */
12373   d_mode,
12374   d_mode,
12375   d_mode,
12376   d_mode,
12377   d_mode,
12378   d_mode,
12379   d_mode,
12380   d_mode,
12381   /* db */
12382   d_mode,
12383   d_mode,
12384   d_mode,
12385   d_mode,
12386   0,
12387   t_mode,
12388   0,
12389   t_mode,
12390   /* dc */
12391   q_mode,
12392   q_mode,
12393   q_mode,
12394   q_mode,
12395   q_mode,
12396   q_mode,
12397   q_mode,
12398   q_mode,
12399   /* dd */
12400   q_mode,
12401   q_mode,
12402   q_mode,
12403   q_mode,
12404   0,
12405   0,
12406   0,
12407   w_mode,
12408   /* de */
12409   w_mode,
12410   w_mode,
12411   w_mode,
12412   w_mode,
12413   w_mode,
12414   w_mode,
12415   w_mode,
12416   w_mode,
12417   /* df */
12418   w_mode,
12419   w_mode,
12420   w_mode,
12421   w_mode,
12422   t_mode,
12423   q_mode,
12424   t_mode,
12425   q_mode
12426 };
12427
12428 #define ST { OP_ST, 0 }
12429 #define STi { OP_STi, 0 }
12430
12431 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12432 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12433 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12434 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12435 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12436 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12437 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12438 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12439 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12440
12441 static const struct dis386 float_reg[][8] = {
12442   /* d8 */
12443   {
12444     { "fadd",   { ST, STi }, 0 },
12445     { "fmul",   { ST, STi }, 0 },
12446     { "fcom",   { STi }, 0 },
12447     { "fcomp",  { STi }, 0 },
12448     { "fsub",   { ST, STi }, 0 },
12449     { "fsubr",  { ST, STi }, 0 },
12450     { "fdiv",   { ST, STi }, 0 },
12451     { "fdivr",  { ST, STi }, 0 },
12452   },
12453   /* d9 */
12454   {
12455     { "fld",    { STi }, 0 },
12456     { "fxch",   { STi }, 0 },
12457     { FGRPd9_2 },
12458     { Bad_Opcode },
12459     { FGRPd9_4 },
12460     { FGRPd9_5 },
12461     { FGRPd9_6 },
12462     { FGRPd9_7 },
12463   },
12464   /* da */
12465   {
12466     { "fcmovb", { ST, STi }, 0 },
12467     { "fcmove", { ST, STi }, 0 },
12468     { "fcmovbe",{ ST, STi }, 0 },
12469     { "fcmovu", { ST, STi }, 0 },
12470     { Bad_Opcode },
12471     { FGRPda_5 },
12472     { Bad_Opcode },
12473     { Bad_Opcode },
12474   },
12475   /* db */
12476   {
12477     { "fcmovnb",{ ST, STi }, 0 },
12478     { "fcmovne",{ ST, STi }, 0 },
12479     { "fcmovnbe",{ ST, STi }, 0 },
12480     { "fcmovnu",{ ST, STi }, 0 },
12481     { FGRPdb_4 },
12482     { "fucomi", { ST, STi }, 0 },
12483     { "fcomi",  { ST, STi }, 0 },
12484     { Bad_Opcode },
12485   },
12486   /* dc */
12487   {
12488     { "fadd",   { STi, ST }, 0 },
12489     { "fmul",   { STi, ST }, 0 },
12490     { Bad_Opcode },
12491     { Bad_Opcode },
12492     { "fsub{!M|r}",     { STi, ST }, 0 },
12493     { "fsub{M|}",       { STi, ST }, 0 },
12494     { "fdiv{!M|r}",     { STi, ST }, 0 },
12495     { "fdiv{M|}",       { STi, ST }, 0 },
12496   },
12497   /* dd */
12498   {
12499     { "ffree",  { STi }, 0 },
12500     { Bad_Opcode },
12501     { "fst",    { STi }, 0 },
12502     { "fstp",   { STi }, 0 },
12503     { "fucom",  { STi }, 0 },
12504     { "fucomp", { STi }, 0 },
12505     { Bad_Opcode },
12506     { Bad_Opcode },
12507   },
12508   /* de */
12509   {
12510     { "faddp",  { STi, ST }, 0 },
12511     { "fmulp",  { STi, ST }, 0 },
12512     { Bad_Opcode },
12513     { FGRPde_3 },
12514     { "fsub{!M|r}p",    { STi, ST }, 0 },
12515     { "fsub{M|}p",      { STi, ST }, 0 },
12516     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12517     { "fdiv{M|}p",      { STi, ST }, 0 },
12518   },
12519   /* df */
12520   {
12521     { "ffreep", { STi }, 0 },
12522     { Bad_Opcode },
12523     { Bad_Opcode },
12524     { Bad_Opcode },
12525     { FGRPdf_4 },
12526     { "fucomip", { ST, STi }, 0 },
12527     { "fcomip", { ST, STi }, 0 },
12528     { Bad_Opcode },
12529   },
12530 };
12531
12532 static char *fgrps[][8] = {
12533   /* Bad opcode 0 */
12534   {
12535     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12536   },
12537
12538   /* d9_2  1 */
12539   {
12540     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12541   },
12542
12543   /* d9_4  2 */
12544   {
12545     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12546   },
12547
12548   /* d9_5  3 */
12549   {
12550     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12551   },
12552
12553   /* d9_6  4 */
12554   {
12555     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12556   },
12557
12558   /* d9_7  5 */
12559   {
12560     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12561   },
12562
12563   /* da_5  6 */
12564   {
12565     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12566   },
12567
12568   /* db_4  7 */
12569   {
12570     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12571     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12572   },
12573
12574   /* de_3  8 */
12575   {
12576     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12577   },
12578
12579   /* df_4  9 */
12580   {
12581     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12582   },
12583 };
12584
12585 static void
12586 swap_operand (void)
12587 {
12588   mnemonicendp[0] = '.';
12589   mnemonicendp[1] = 's';
12590   mnemonicendp += 2;
12591 }
12592
12593 static void
12594 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12595                int sizeflag ATTRIBUTE_UNUSED)
12596 {
12597   /* Skip mod/rm byte.  */
12598   MODRM_CHECK;
12599   codep++;
12600 }
12601
12602 static void
12603 dofloat (int sizeflag)
12604 {
12605   const struct dis386 *dp;
12606   unsigned char floatop;
12607
12608   floatop = codep[-1];
12609
12610   if (modrm.mod != 3)
12611     {
12612       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12613
12614       putop (float_mem[fp_indx], sizeflag);
12615       obufp = op_out[0];
12616       op_ad = 2;
12617       OP_E (float_mem_mode[fp_indx], sizeflag);
12618       return;
12619     }
12620   /* Skip mod/rm byte.  */
12621   MODRM_CHECK;
12622   codep++;
12623
12624   dp = &float_reg[floatop - 0xd8][modrm.reg];
12625   if (dp->name == NULL)
12626     {
12627       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12628
12629       /* Instruction fnstsw is only one with strange arg.  */
12630       if (floatop == 0xdf && codep[-1] == 0xe0)
12631         strcpy (op_out[0], names16[0]);
12632     }
12633   else
12634     {
12635       putop (dp->name, sizeflag);
12636
12637       obufp = op_out[0];
12638       op_ad = 2;
12639       if (dp->op[0].rtn)
12640         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12641
12642       obufp = op_out[1];
12643       op_ad = 1;
12644       if (dp->op[1].rtn)
12645         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12646     }
12647 }
12648
12649 /* Like oappend (below), but S is a string starting with '%'.
12650    In Intel syntax, the '%' is elided.  */
12651 static void
12652 oappend_maybe_intel (const char *s)
12653 {
12654   oappend (s + intel_syntax);
12655 }
12656
12657 static void
12658 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12659 {
12660   oappend_maybe_intel ("%st");
12661 }
12662
12663 static void
12664 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12665 {
12666   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12667   oappend_maybe_intel (scratchbuf);
12668 }
12669
12670 /* Capital letters in template are macros.  */
12671 static int
12672 putop (const char *in_template, int sizeflag)
12673 {
12674   const char *p;
12675   int alt = 0;
12676   int cond = 1;
12677   unsigned int l = 0, len = 1;
12678   char last[4];
12679
12680 #define SAVE_LAST(c)                    \
12681   if (l < len && l < sizeof (last))     \
12682     last[l++] = c;                      \
12683   else                                  \
12684     abort ();
12685
12686   for (p = in_template; *p; p++)
12687     {
12688       switch (*p)
12689         {
12690         default:
12691           *obufp++ = *p;
12692           break;
12693         case '%':
12694           len++;
12695           break;
12696         case '!':
12697           cond = 0;
12698           break;
12699         case '{':
12700           if (intel_syntax)
12701             {
12702               while (*++p != '|')
12703                 if (*p == '}' || *p == '\0')
12704                   abort ();
12705             }
12706           /* Fall through.  */
12707         case 'I':
12708           alt = 1;
12709           continue;
12710         case '|':
12711           while (*++p != '}')
12712             {
12713               if (*p == '\0')
12714                 abort ();
12715             }
12716           break;
12717         case '}':
12718           break;
12719         case 'A':
12720           if (intel_syntax)
12721             break;
12722           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12723             *obufp++ = 'b';
12724           break;
12725         case 'B':
12726           if (l == 0 && len == 1)
12727             {
12728 case_B:
12729               if (intel_syntax)
12730                 break;
12731               if (sizeflag & SUFFIX_ALWAYS)
12732                 *obufp++ = 'b';
12733             }
12734           else
12735             {
12736               if (l != 1
12737                   || len != 2
12738                   || last[0] != 'L')
12739                 {
12740                   SAVE_LAST (*p);
12741                   break;
12742                 }
12743
12744               if (address_mode == mode_64bit
12745                   && !(prefixes & PREFIX_ADDR))
12746                 {
12747                   *obufp++ = 'a';
12748                   *obufp++ = 'b';
12749                   *obufp++ = 's';
12750                 }
12751
12752               goto case_B;
12753             }
12754           break;
12755         case 'C':
12756           if (intel_syntax && !alt)
12757             break;
12758           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12759             {
12760               if (sizeflag & DFLAG)
12761                 *obufp++ = intel_syntax ? 'd' : 'l';
12762               else
12763                 *obufp++ = intel_syntax ? 'w' : 's';
12764               used_prefixes |= (prefixes & PREFIX_DATA);
12765             }
12766           break;
12767         case 'D':
12768           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12769             break;
12770           USED_REX (REX_W);
12771           if (modrm.mod == 3)
12772             {
12773               if (rex & REX_W)
12774                 *obufp++ = 'q';
12775               else
12776                 {
12777                   if (sizeflag & DFLAG)
12778                     *obufp++ = intel_syntax ? 'd' : 'l';
12779                   else
12780                     *obufp++ = 'w';
12781                   used_prefixes |= (prefixes & PREFIX_DATA);
12782                 }
12783             }
12784           else
12785             *obufp++ = 'w';
12786           break;
12787         case 'E':               /* For jcxz/jecxz */
12788           if (address_mode == mode_64bit)
12789             {
12790               if (sizeflag & AFLAG)
12791                 *obufp++ = 'r';
12792               else
12793                 *obufp++ = 'e';
12794             }
12795           else
12796             if (sizeflag & AFLAG)
12797               *obufp++ = 'e';
12798           used_prefixes |= (prefixes & PREFIX_ADDR);
12799           break;
12800         case 'F':
12801           if (intel_syntax)
12802             break;
12803           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12804             {
12805               if (sizeflag & AFLAG)
12806                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12807               else
12808                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12809               used_prefixes |= (prefixes & PREFIX_ADDR);
12810             }
12811           break;
12812         case 'G':
12813           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12814             break;
12815           if ((rex & REX_W) || (sizeflag & DFLAG))
12816             *obufp++ = 'l';
12817           else
12818             *obufp++ = 'w';
12819           if (!(rex & REX_W))
12820             used_prefixes |= (prefixes & PREFIX_DATA);
12821           break;
12822         case 'H':
12823           if (intel_syntax)
12824             break;
12825           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12826               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12827             {
12828               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12829               *obufp++ = ',';
12830               *obufp++ = 'p';
12831               if (prefixes & PREFIX_DS)
12832                 *obufp++ = 't';
12833               else
12834                 *obufp++ = 'n';
12835             }
12836           break;
12837         case 'J':
12838           if (intel_syntax)
12839             break;
12840           *obufp++ = 'l';
12841           break;
12842         case 'K':
12843           USED_REX (REX_W);
12844           if (rex & REX_W)
12845             *obufp++ = 'q';
12846           else
12847             *obufp++ = 'd';
12848           break;
12849         case 'Z':
12850           if (l != 0 || len != 1)
12851             {
12852               if (l != 1 || len != 2 || last[0] != 'X')
12853                 {
12854                   SAVE_LAST (*p);
12855                   break;
12856                 }
12857               if (!need_vex || !vex.evex)
12858                 abort ();
12859               if (intel_syntax
12860                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12861                 break;
12862               switch (vex.length)
12863                 {
12864                 case 128:
12865                   *obufp++ = 'x';
12866                   break;
12867                 case 256:
12868                   *obufp++ = 'y';
12869                   break;
12870                 case 512:
12871                   *obufp++ = 'z';
12872                   break;
12873                 default:
12874                   abort ();
12875                 }
12876               break;
12877             }
12878           if (intel_syntax)
12879             break;
12880           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12881             {
12882               *obufp++ = 'q';
12883               break;
12884             }
12885           /* Fall through.  */
12886           goto case_L;
12887         case 'L':
12888           if (l != 0 || len != 1)
12889             {
12890               SAVE_LAST (*p);
12891               break;
12892             }
12893 case_L:
12894           if (intel_syntax)
12895             break;
12896           if (sizeflag & SUFFIX_ALWAYS)
12897             *obufp++ = 'l';
12898           break;
12899         case 'M':
12900           if (intel_mnemonic != cond)
12901             *obufp++ = 'r';
12902           break;
12903         case 'N':
12904           if ((prefixes & PREFIX_FWAIT) == 0)
12905             *obufp++ = 'n';
12906           else
12907             used_prefixes |= PREFIX_FWAIT;
12908           break;
12909         case 'O':
12910           USED_REX (REX_W);
12911           if (rex & REX_W)
12912             *obufp++ = 'o';
12913           else if (intel_syntax && (sizeflag & DFLAG))
12914             *obufp++ = 'q';
12915           else
12916             *obufp++ = 'd';
12917           if (!(rex & REX_W))
12918             used_prefixes |= (prefixes & PREFIX_DATA);
12919           break;
12920         case '&':
12921           if (!intel_syntax
12922               && address_mode == mode_64bit
12923               && isa64 == intel64)
12924             {
12925               *obufp++ = 'q';
12926               break;
12927             }
12928           /* Fall through.  */
12929         case 'T':
12930           if (!intel_syntax
12931               && address_mode == mode_64bit
12932               && ((sizeflag & DFLAG) || (rex & REX_W)))
12933             {
12934               *obufp++ = 'q';
12935               break;
12936             }
12937           /* Fall through.  */
12938           goto case_P;
12939         case 'P':
12940           if (l == 0 && len == 1)
12941             {
12942 case_P:
12943               if (intel_syntax)
12944                 {
12945                   if ((rex & REX_W) == 0
12946                       && (prefixes & PREFIX_DATA))
12947                     {
12948                       if ((sizeflag & DFLAG) == 0)
12949                         *obufp++ = 'w';
12950                       used_prefixes |= (prefixes & PREFIX_DATA);
12951                     }
12952                   break;
12953                 }
12954               if ((prefixes & PREFIX_DATA)
12955                   || (rex & REX_W)
12956                   || (sizeflag & SUFFIX_ALWAYS))
12957                 {
12958                   USED_REX (REX_W);
12959                   if (rex & REX_W)
12960                     *obufp++ = 'q';
12961                   else
12962                     {
12963                       if (sizeflag & DFLAG)
12964                         *obufp++ = 'l';
12965                       else
12966                         *obufp++ = 'w';
12967                       used_prefixes |= (prefixes & PREFIX_DATA);
12968                     }
12969                 }
12970             }
12971           else
12972             {
12973               if (l != 1 || len != 2 || last[0] != 'L')
12974                 {
12975                   SAVE_LAST (*p);
12976                   break;
12977                 }
12978
12979               if ((prefixes & PREFIX_DATA)
12980                   || (rex & REX_W)
12981                   || (sizeflag & SUFFIX_ALWAYS))
12982                 {
12983                   USED_REX (REX_W);
12984                   if (rex & REX_W)
12985                     *obufp++ = 'q';
12986                   else
12987                     {
12988                       if (sizeflag & DFLAG)
12989                         *obufp++ = intel_syntax ? 'd' : 'l';
12990                       else
12991                         *obufp++ = 'w';
12992                       used_prefixes |= (prefixes & PREFIX_DATA);
12993                     }
12994                 }
12995             }
12996           break;
12997         case 'U':
12998           if (intel_syntax)
12999             break;
13000           if (address_mode == mode_64bit
13001               && ((sizeflag & DFLAG) || (rex & REX_W)))
13002             {
13003               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13004                 *obufp++ = 'q';
13005               break;
13006             }
13007           /* Fall through.  */
13008           goto case_Q;
13009         case 'Q':
13010           if (l == 0 && len == 1)
13011             {
13012 case_Q:
13013               if (intel_syntax && !alt)
13014                 break;
13015               USED_REX (REX_W);
13016               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13017                 {
13018                   if (rex & REX_W)
13019                     *obufp++ = 'q';
13020                   else
13021                     {
13022                       if (sizeflag & DFLAG)
13023                         *obufp++ = intel_syntax ? 'd' : 'l';
13024                       else
13025                         *obufp++ = 'w';
13026                       used_prefixes |= (prefixes & PREFIX_DATA);
13027                     }
13028                 }
13029             }
13030           else
13031             {
13032               if (l != 1 || len != 2 || last[0] != 'L')
13033                 {
13034                   SAVE_LAST (*p);
13035                   break;
13036                 }
13037               if (intel_syntax
13038                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13039                 break;
13040               if ((rex & REX_W))
13041                 {
13042                   USED_REX (REX_W);
13043                   *obufp++ = 'q';
13044                 }
13045               else
13046                 *obufp++ = 'l';
13047             }
13048           break;
13049         case 'R':
13050           USED_REX (REX_W);
13051           if (rex & REX_W)
13052             *obufp++ = 'q';
13053           else if (sizeflag & DFLAG)
13054             {
13055               if (intel_syntax)
13056                   *obufp++ = 'd';
13057               else
13058                   *obufp++ = 'l';
13059             }
13060           else
13061             *obufp++ = 'w';
13062           if (intel_syntax && !p[1]
13063               && ((rex & REX_W) || (sizeflag & DFLAG)))
13064             *obufp++ = 'e';
13065           if (!(rex & REX_W))
13066             used_prefixes |= (prefixes & PREFIX_DATA);
13067           break;
13068         case 'V':
13069           if (l == 0 && len == 1)
13070             {
13071               if (intel_syntax)
13072                 break;
13073               if (address_mode == mode_64bit
13074                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13075                 {
13076                   if (sizeflag & SUFFIX_ALWAYS)
13077                     *obufp++ = 'q';
13078                   break;
13079                 }
13080             }
13081           else
13082             {
13083               if (l != 1
13084                   || len != 2
13085                   || last[0] != 'L')
13086                 {
13087                   SAVE_LAST (*p);
13088                   break;
13089                 }
13090
13091               if (rex & REX_W)
13092                 {
13093                   *obufp++ = 'a';
13094                   *obufp++ = 'b';
13095                   *obufp++ = 's';
13096                 }
13097             }
13098           /* Fall through.  */
13099           goto case_S;
13100         case 'S':
13101           if (l == 0 && len == 1)
13102             {
13103 case_S:
13104               if (intel_syntax)
13105                 break;
13106               if (sizeflag & SUFFIX_ALWAYS)
13107                 {
13108                   if (rex & REX_W)
13109                     *obufp++ = 'q';
13110                   else
13111                     {
13112                       if (sizeflag & DFLAG)
13113                         *obufp++ = 'l';
13114                       else
13115                         *obufp++ = 'w';
13116                       used_prefixes |= (prefixes & PREFIX_DATA);
13117                     }
13118                 }
13119             }
13120           else
13121             {
13122               if (l != 1
13123                   || len != 2
13124                   || last[0] != 'L')
13125                 {
13126                   SAVE_LAST (*p);
13127                   break;
13128                 }
13129
13130               if (address_mode == mode_64bit
13131                   && !(prefixes & PREFIX_ADDR))
13132                 {
13133                   *obufp++ = 'a';
13134                   *obufp++ = 'b';
13135                   *obufp++ = 's';
13136                 }
13137
13138               goto case_S;
13139             }
13140           break;
13141         case 'X':
13142           if (l != 0 || len != 1)
13143             {
13144               SAVE_LAST (*p);
13145               break;
13146             }
13147           if (need_vex && vex.prefix)
13148             {
13149               if (vex.prefix == DATA_PREFIX_OPCODE)
13150                 *obufp++ = 'd';
13151               else
13152                 *obufp++ = 's';
13153             }
13154           else
13155             {
13156               if (prefixes & PREFIX_DATA)
13157                 *obufp++ = 'd';
13158               else
13159                 *obufp++ = 's';
13160               used_prefixes |= (prefixes & PREFIX_DATA);
13161             }
13162           break;
13163         case 'Y':
13164           if (l == 0 && len == 1)
13165             abort ();
13166           else
13167             {
13168               if (l != 1 || len != 2 || last[0] != 'X')
13169                 {
13170                   SAVE_LAST (*p);
13171                   break;
13172                 }
13173               if (!need_vex)
13174                 abort ();
13175               if (intel_syntax
13176                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13177                 break;
13178               switch (vex.length)
13179                 {
13180                 case 128:
13181                   *obufp++ = 'x';
13182                   break;
13183                 case 256:
13184                   *obufp++ = 'y';
13185                   break;
13186                 case 512:
13187                   if (!vex.evex)
13188                 default:
13189                     abort ();
13190                 }
13191             }
13192           break;
13193         case 'W':
13194           if (l == 0 && len == 1)
13195             {
13196               /* operand size flag for cwtl, cbtw */
13197               USED_REX (REX_W);
13198               if (rex & REX_W)
13199                 {
13200                   if (intel_syntax)
13201                     *obufp++ = 'd';
13202                   else
13203                     *obufp++ = 'l';
13204                 }
13205               else if (sizeflag & DFLAG)
13206                 *obufp++ = 'w';
13207               else
13208                 *obufp++ = 'b';
13209               if (!(rex & REX_W))
13210                 used_prefixes |= (prefixes & PREFIX_DATA);
13211             }
13212           else
13213             {
13214               if (l != 1
13215                   || len != 2
13216                   || (last[0] != 'X'
13217                       && last[0] != 'L'))
13218                 {
13219                   SAVE_LAST (*p);
13220                   break;
13221                 }
13222               if (!need_vex)
13223                 abort ();
13224               if (last[0] == 'X')
13225                 *obufp++ = vex.w ? 'd': 's';
13226               else
13227                 *obufp++ = vex.w ? 'q': 'd';
13228             }
13229           break;
13230         case '^':
13231           if (intel_syntax)
13232             break;
13233           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13234             {
13235               if (sizeflag & DFLAG)
13236                 *obufp++ = 'l';
13237               else
13238                 *obufp++ = 'w';
13239               used_prefixes |= (prefixes & PREFIX_DATA);
13240             }
13241           break;
13242         case '@':
13243           if (intel_syntax)
13244             break;
13245           if (address_mode == mode_64bit
13246               && (isa64 == intel64
13247                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13248               *obufp++ = 'q';
13249           else if ((prefixes & PREFIX_DATA))
13250             {
13251               if (!(sizeflag & DFLAG))
13252                 *obufp++ = 'w';
13253               used_prefixes |= (prefixes & PREFIX_DATA);
13254             }
13255           break;
13256         }
13257       alt = 0;
13258     }
13259   *obufp = 0;
13260   mnemonicendp = obufp;
13261   return 0;
13262 }
13263
13264 static void
13265 oappend (const char *s)
13266 {
13267   obufp = stpcpy (obufp, s);
13268 }
13269
13270 static void
13271 append_seg (void)
13272 {
13273   /* Only print the active segment register.  */
13274   if (!active_seg_prefix)
13275     return;
13276
13277   used_prefixes |= active_seg_prefix;
13278   switch (active_seg_prefix)
13279     {
13280     case PREFIX_CS:
13281       oappend_maybe_intel ("%cs:");
13282       break;
13283     case PREFIX_DS:
13284       oappend_maybe_intel ("%ds:");
13285       break;
13286     case PREFIX_SS:
13287       oappend_maybe_intel ("%ss:");
13288       break;
13289     case PREFIX_ES:
13290       oappend_maybe_intel ("%es:");
13291       break;
13292     case PREFIX_FS:
13293       oappend_maybe_intel ("%fs:");
13294       break;
13295     case PREFIX_GS:
13296       oappend_maybe_intel ("%gs:");
13297       break;
13298     default:
13299       break;
13300     }
13301 }
13302
13303 static void
13304 OP_indirE (int bytemode, int sizeflag)
13305 {
13306   if (!intel_syntax)
13307     oappend ("*");
13308   OP_E (bytemode, sizeflag);
13309 }
13310
13311 static void
13312 print_operand_value (char *buf, int hex, bfd_vma disp)
13313 {
13314   if (address_mode == mode_64bit)
13315     {
13316       if (hex)
13317         {
13318           char tmp[30];
13319           int i;
13320           buf[0] = '0';
13321           buf[1] = 'x';
13322           sprintf_vma (tmp, disp);
13323           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13324           strcpy (buf + 2, tmp + i);
13325         }
13326       else
13327         {
13328           bfd_signed_vma v = disp;
13329           char tmp[30];
13330           int i;
13331           if (v < 0)
13332             {
13333               *(buf++) = '-';
13334               v = -disp;
13335               /* Check for possible overflow on 0x8000000000000000.  */
13336               if (v < 0)
13337                 {
13338                   strcpy (buf, "9223372036854775808");
13339                   return;
13340                 }
13341             }
13342           if (!v)
13343             {
13344               strcpy (buf, "0");
13345               return;
13346             }
13347
13348           i = 0;
13349           tmp[29] = 0;
13350           while (v)
13351             {
13352               tmp[28 - i] = (v % 10) + '0';
13353               v /= 10;
13354               i++;
13355             }
13356           strcpy (buf, tmp + 29 - i);
13357         }
13358     }
13359   else
13360     {
13361       if (hex)
13362         sprintf (buf, "0x%x", (unsigned int) disp);
13363       else
13364         sprintf (buf, "%d", (int) disp);
13365     }
13366 }
13367
13368 /* Put DISP in BUF as signed hex number.  */
13369
13370 static void
13371 print_displacement (char *buf, bfd_vma disp)
13372 {
13373   bfd_signed_vma val = disp;
13374   char tmp[30];
13375   int i, j = 0;
13376
13377   if (val < 0)
13378     {
13379       buf[j++] = '-';
13380       val = -disp;
13381
13382       /* Check for possible overflow.  */
13383       if (val < 0)
13384         {
13385           switch (address_mode)
13386             {
13387             case mode_64bit:
13388               strcpy (buf + j, "0x8000000000000000");
13389               break;
13390             case mode_32bit:
13391               strcpy (buf + j, "0x80000000");
13392               break;
13393             case mode_16bit:
13394               strcpy (buf + j, "0x8000");
13395               break;
13396             }
13397           return;
13398         }
13399     }
13400
13401   buf[j++] = '0';
13402   buf[j++] = 'x';
13403
13404   sprintf_vma (tmp, (bfd_vma) val);
13405   for (i = 0; tmp[i] == '0'; i++)
13406     continue;
13407   if (tmp[i] == '\0')
13408     i--;
13409   strcpy (buf + j, tmp + i);
13410 }
13411
13412 static void
13413 intel_operand_size (int bytemode, int sizeflag)
13414 {
13415   if (vex.evex
13416       && vex.b
13417       && (bytemode == x_mode
13418           || bytemode == evex_half_bcst_xmmq_mode))
13419     {
13420       if (vex.w)
13421         oappend ("QWORD PTR ");
13422       else
13423         oappend ("DWORD PTR ");
13424       return;
13425     }
13426   switch (bytemode)
13427     {
13428     case b_mode:
13429     case b_swap_mode:
13430     case dqb_mode:
13431     case db_mode:
13432       oappend ("BYTE PTR ");
13433       break;
13434     case w_mode:
13435     case dw_mode:
13436     case dqw_mode:
13437       oappend ("WORD PTR ");
13438       break;
13439     case indir_v_mode:
13440       if (address_mode == mode_64bit && isa64 == intel64)
13441         {
13442           oappend ("QWORD PTR ");
13443           break;
13444         }
13445       /* Fall through.  */
13446     case stack_v_mode:
13447       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13448         {
13449           oappend ("QWORD PTR ");
13450           break;
13451         }
13452       /* Fall through.  */
13453     case v_mode:
13454     case v_swap_mode:
13455     case dq_mode:
13456       USED_REX (REX_W);
13457       if (rex & REX_W)
13458         oappend ("QWORD PTR ");
13459       else
13460         {
13461           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13462             oappend ("DWORD PTR ");
13463           else
13464             oappend ("WORD PTR ");
13465           used_prefixes |= (prefixes & PREFIX_DATA);
13466         }
13467       break;
13468     case z_mode:
13469       if ((rex & REX_W) || (sizeflag & DFLAG))
13470         *obufp++ = 'D';
13471       oappend ("WORD PTR ");
13472       if (!(rex & REX_W))
13473         used_prefixes |= (prefixes & PREFIX_DATA);
13474       break;
13475     case a_mode:
13476       if (sizeflag & DFLAG)
13477         oappend ("QWORD PTR ");
13478       else
13479         oappend ("DWORD PTR ");
13480       used_prefixes |= (prefixes & PREFIX_DATA);
13481       break;
13482     case d_mode:
13483     case d_scalar_mode:
13484     case d_scalar_swap_mode:
13485     case d_swap_mode:
13486     case dqd_mode:
13487       oappend ("DWORD PTR ");
13488       break;
13489     case q_mode:
13490     case q_scalar_mode:
13491     case q_scalar_swap_mode:
13492     case q_swap_mode:
13493       oappend ("QWORD PTR ");
13494       break;
13495     case dqa_mode:
13496     case m_mode:
13497       if (address_mode == mode_64bit)
13498         oappend ("QWORD PTR ");
13499       else
13500         oappend ("DWORD PTR ");
13501       break;
13502     case f_mode:
13503       if (sizeflag & DFLAG)
13504         oappend ("FWORD PTR ");
13505       else
13506         oappend ("DWORD PTR ");
13507       used_prefixes |= (prefixes & PREFIX_DATA);
13508       break;
13509     case t_mode:
13510       oappend ("TBYTE PTR ");
13511       break;
13512     case x_mode:
13513     case x_swap_mode:
13514     case evex_x_gscat_mode:
13515     case evex_x_nobcst_mode:
13516     case b_scalar_mode:
13517     case w_scalar_mode:
13518       if (need_vex)
13519         {
13520           switch (vex.length)
13521             {
13522             case 128:
13523               oappend ("XMMWORD PTR ");
13524               break;
13525             case 256:
13526               oappend ("YMMWORD PTR ");
13527               break;
13528             case 512:
13529               oappend ("ZMMWORD PTR ");
13530               break;
13531             default:
13532               abort ();
13533             }
13534         }
13535       else
13536         oappend ("XMMWORD PTR ");
13537       break;
13538     case xmm_mode:
13539       oappend ("XMMWORD PTR ");
13540       break;
13541     case ymm_mode:
13542       oappend ("YMMWORD PTR ");
13543       break;
13544     case xmmq_mode:
13545     case evex_half_bcst_xmmq_mode:
13546       if (!need_vex)
13547         abort ();
13548
13549       switch (vex.length)
13550         {
13551         case 128:
13552           oappend ("QWORD PTR ");
13553           break;
13554         case 256:
13555           oappend ("XMMWORD PTR ");
13556           break;
13557         case 512:
13558           oappend ("YMMWORD PTR ");
13559           break;
13560         default:
13561           abort ();
13562         }
13563       break;
13564     case xmm_mb_mode:
13565       if (!need_vex)
13566         abort ();
13567
13568       switch (vex.length)
13569         {
13570         case 128:
13571         case 256:
13572         case 512:
13573           oappend ("BYTE PTR ");
13574           break;
13575         default:
13576           abort ();
13577         }
13578       break;
13579     case xmm_mw_mode:
13580       if (!need_vex)
13581         abort ();
13582
13583       switch (vex.length)
13584         {
13585         case 128:
13586         case 256:
13587         case 512:
13588           oappend ("WORD PTR ");
13589           break;
13590         default:
13591           abort ();
13592         }
13593       break;
13594     case xmm_md_mode:
13595       if (!need_vex)
13596         abort ();
13597
13598       switch (vex.length)
13599         {
13600         case 128:
13601         case 256:
13602         case 512:
13603           oappend ("DWORD PTR ");
13604           break;
13605         default:
13606           abort ();
13607         }
13608       break;
13609     case xmm_mq_mode:
13610       if (!need_vex)
13611         abort ();
13612
13613       switch (vex.length)
13614         {
13615         case 128:
13616         case 256:
13617         case 512:
13618           oappend ("QWORD PTR ");
13619           break;
13620         default:
13621           abort ();
13622         }
13623       break;
13624     case xmmdw_mode:
13625       if (!need_vex)
13626         abort ();
13627
13628       switch (vex.length)
13629         {
13630         case 128:
13631           oappend ("WORD PTR ");
13632           break;
13633         case 256:
13634           oappend ("DWORD PTR ");
13635           break;
13636         case 512:
13637           oappend ("QWORD PTR ");
13638           break;
13639         default:
13640           abort ();
13641         }
13642       break;
13643     case xmmqd_mode:
13644       if (!need_vex)
13645         abort ();
13646
13647       switch (vex.length)
13648         {
13649         case 128:
13650           oappend ("DWORD PTR ");
13651           break;
13652         case 256:
13653           oappend ("QWORD PTR ");
13654           break;
13655         case 512:
13656           oappend ("XMMWORD PTR ");
13657           break;
13658         default:
13659           abort ();
13660         }
13661       break;
13662     case ymmq_mode:
13663       if (!need_vex)
13664         abort ();
13665
13666       switch (vex.length)
13667         {
13668         case 128:
13669           oappend ("QWORD PTR ");
13670           break;
13671         case 256:
13672           oappend ("YMMWORD PTR ");
13673           break;
13674         case 512:
13675           oappend ("ZMMWORD PTR ");
13676           break;
13677         default:
13678           abort ();
13679         }
13680       break;
13681     case ymmxmm_mode:
13682       if (!need_vex)
13683         abort ();
13684
13685       switch (vex.length)
13686         {
13687         case 128:
13688         case 256:
13689           oappend ("XMMWORD PTR ");
13690           break;
13691         default:
13692           abort ();
13693         }
13694       break;
13695     case o_mode:
13696       oappend ("OWORD PTR ");
13697       break;
13698     case xmm_mdq_mode:
13699     case vex_w_dq_mode:
13700     case vex_scalar_w_dq_mode:
13701       if (!need_vex)
13702         abort ();
13703
13704       if (vex.w)
13705         oappend ("QWORD PTR ");
13706       else
13707         oappend ("DWORD PTR ");
13708       break;
13709     case vex_vsib_d_w_dq_mode:
13710     case vex_vsib_q_w_dq_mode:
13711       if (!need_vex)
13712         abort ();
13713
13714       if (!vex.evex)
13715         {
13716           if (vex.w)
13717             oappend ("QWORD PTR ");
13718           else
13719             oappend ("DWORD PTR ");
13720         }
13721       else
13722         {
13723           switch (vex.length)
13724             {
13725             case 128:
13726               oappend ("XMMWORD PTR ");
13727               break;
13728             case 256:
13729               oappend ("YMMWORD PTR ");
13730               break;
13731             case 512:
13732               oappend ("ZMMWORD PTR ");
13733               break;
13734             default:
13735               abort ();
13736             }
13737         }
13738       break;
13739     case vex_vsib_q_w_d_mode:
13740     case vex_vsib_d_w_d_mode:
13741       if (!need_vex || !vex.evex)
13742         abort ();
13743
13744       switch (vex.length)
13745         {
13746         case 128:
13747           oappend ("QWORD PTR ");
13748           break;
13749         case 256:
13750           oappend ("XMMWORD PTR ");
13751           break;
13752         case 512:
13753           oappend ("YMMWORD PTR ");
13754           break;
13755         default:
13756           abort ();
13757         }
13758
13759       break;
13760     case mask_bd_mode:
13761       if (!need_vex || vex.length != 128)
13762         abort ();
13763       if (vex.w)
13764         oappend ("DWORD PTR ");
13765       else
13766         oappend ("BYTE PTR ");
13767       break;
13768     case mask_mode:
13769       if (!need_vex)
13770         abort ();
13771       if (vex.w)
13772         oappend ("QWORD PTR ");
13773       else
13774         oappend ("WORD PTR ");
13775       break;
13776     case v_bnd_mode:
13777     case v_bndmk_mode:
13778     default:
13779       break;
13780     }
13781 }
13782
13783 static void
13784 OP_E_register (int bytemode, int sizeflag)
13785 {
13786   int reg = modrm.rm;
13787   const char **names;
13788
13789   USED_REX (REX_B);
13790   if ((rex & REX_B))
13791     reg += 8;
13792
13793   if ((sizeflag & SUFFIX_ALWAYS)
13794       && (bytemode == b_swap_mode
13795           || bytemode == bnd_swap_mode
13796           || bytemode == v_swap_mode))
13797     swap_operand ();
13798
13799   switch (bytemode)
13800     {
13801     case b_mode:
13802     case b_swap_mode:
13803       USED_REX (0);
13804       if (rex)
13805         names = names8rex;
13806       else
13807         names = names8;
13808       break;
13809     case w_mode:
13810       names = names16;
13811       break;
13812     case d_mode:
13813     case dw_mode:
13814     case db_mode:
13815       names = names32;
13816       break;
13817     case q_mode:
13818       names = names64;
13819       break;
13820     case m_mode:
13821     case v_bnd_mode:
13822       names = address_mode == mode_64bit ? names64 : names32;
13823       break;
13824     case bnd_mode:
13825     case bnd_swap_mode:
13826       if (reg > 0x3)
13827         {
13828           oappend ("(bad)");
13829           return;
13830         }
13831       names = names_bnd;
13832       break;
13833     case indir_v_mode:
13834       if (address_mode == mode_64bit && isa64 == intel64)
13835         {
13836           names = names64;
13837           break;
13838         }
13839       /* Fall through.  */
13840     case stack_v_mode:
13841       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13842         {
13843           names = names64;
13844           break;
13845         }
13846       bytemode = v_mode;
13847       /* Fall through.  */
13848     case v_mode:
13849     case v_swap_mode:
13850     case dq_mode:
13851     case dqb_mode:
13852     case dqd_mode:
13853     case dqw_mode:
13854     case dqa_mode:
13855       USED_REX (REX_W);
13856       if (rex & REX_W)
13857         names = names64;
13858       else
13859         {
13860           if ((sizeflag & DFLAG)
13861               || (bytemode != v_mode
13862                   && bytemode != v_swap_mode))
13863             names = names32;
13864           else
13865             names = names16;
13866           used_prefixes |= (prefixes & PREFIX_DATA);
13867         }
13868       break;
13869     case va_mode:
13870       names = (address_mode == mode_64bit
13871                ? names64 : names32);
13872       if (!(prefixes & PREFIX_ADDR))
13873         names = (address_mode == mode_16bit
13874                      ? names16 : names);
13875       else
13876         {
13877           /* Remove "addr16/addr32".  */
13878           all_prefixes[last_addr_prefix] = 0;
13879           names = (address_mode != mode_32bit
13880                        ? names32 : names16);
13881           used_prefixes |= PREFIX_ADDR;
13882         }
13883       break;
13884     case mask_bd_mode:
13885     case mask_mode:
13886       if (reg > 0x7)
13887         {
13888           oappend ("(bad)");
13889           return;
13890         }
13891       names = names_mask;
13892       break;
13893     case 0:
13894       return;
13895     default:
13896       oappend (INTERNAL_DISASSEMBLER_ERROR);
13897       return;
13898     }
13899   oappend (names[reg]);
13900 }
13901
13902 static void
13903 OP_E_memory (int bytemode, int sizeflag)
13904 {
13905   bfd_vma disp = 0;
13906   int add = (rex & REX_B) ? 8 : 0;
13907   int riprel = 0;
13908   int shift;
13909
13910   if (vex.evex)
13911     {
13912       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13913       if (vex.b
13914           && bytemode != x_mode
13915           && bytemode != xmmq_mode
13916           && bytemode != evex_half_bcst_xmmq_mode)
13917         {
13918           BadOp ();
13919           return;
13920         }
13921       switch (bytemode)
13922         {
13923         case dqw_mode:
13924         case dw_mode:
13925           shift = 1;
13926           break;
13927         case dqb_mode:
13928         case db_mode:
13929           shift = 0;
13930           break;
13931         case vex_vsib_d_w_dq_mode:
13932         case vex_vsib_d_w_d_mode:
13933         case vex_vsib_q_w_dq_mode:
13934         case vex_vsib_q_w_d_mode:
13935         case evex_x_gscat_mode:
13936         case xmm_mdq_mode:
13937           shift = vex.w ? 3 : 2;
13938           break;
13939         case x_mode:
13940         case evex_half_bcst_xmmq_mode:
13941         case xmmq_mode:
13942           if (vex.b)
13943             {
13944               shift = vex.w ? 3 : 2;
13945               break;
13946             }
13947           /* Fall through.  */
13948         case xmmqd_mode:
13949         case xmmdw_mode:
13950         case ymmq_mode:
13951         case evex_x_nobcst_mode:
13952         case x_swap_mode:
13953           switch (vex.length)
13954             {
13955             case 128:
13956               shift = 4;
13957               break;
13958             case 256:
13959               shift = 5;
13960               break;
13961             case 512:
13962               shift = 6;
13963               break;
13964             default:
13965               abort ();
13966             }
13967           break;
13968         case ymm_mode:
13969           shift = 5;
13970           break;
13971         case xmm_mode:
13972           shift = 4;
13973           break;
13974         case xmm_mq_mode:
13975         case q_mode:
13976         case q_scalar_mode:
13977         case q_swap_mode:
13978         case q_scalar_swap_mode:
13979           shift = 3;
13980           break;
13981         case dqd_mode:
13982         case xmm_md_mode:
13983         case d_mode:
13984         case d_scalar_mode:
13985         case d_swap_mode:
13986         case d_scalar_swap_mode:
13987           shift = 2;
13988           break;
13989         case w_scalar_mode:
13990         case xmm_mw_mode:
13991           shift = 1;
13992           break;
13993         case b_scalar_mode:
13994         case xmm_mb_mode:
13995           shift = 0;
13996           break;
13997         case dqa_mode:
13998           shift = address_mode == mode_64bit ? 3 : 2;
13999           break;
14000         default:
14001           abort ();
14002         }
14003       /* Make necessary corrections to shift for modes that need it.
14004          For these modes we currently have shift 4, 5 or 6 depending on
14005          vex.length (it corresponds to xmmword, ymmword or zmmword
14006          operand).  We might want to make it 3, 4 or 5 (e.g. for
14007          xmmq_mode).  In case of broadcast enabled the corrections
14008          aren't needed, as element size is always 32 or 64 bits.  */
14009       if (!vex.b
14010           && (bytemode == xmmq_mode
14011               || bytemode == evex_half_bcst_xmmq_mode))
14012         shift -= 1;
14013       else if (bytemode == xmmqd_mode)
14014         shift -= 2;
14015       else if (bytemode == xmmdw_mode)
14016         shift -= 3;
14017       else if (bytemode == ymmq_mode && vex.length == 128)
14018         shift -= 1;
14019     }
14020   else
14021     shift = 0;
14022
14023   USED_REX (REX_B);
14024   if (intel_syntax)
14025     intel_operand_size (bytemode, sizeflag);
14026   append_seg ();
14027
14028   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14029     {
14030       /* 32/64 bit address mode */
14031       int havedisp;
14032       int havesib;
14033       int havebase;
14034       int haveindex;
14035       int needindex;
14036       int needaddr32;
14037       int base, rbase;
14038       int vindex = 0;
14039       int scale = 0;
14040       int addr32flag = !((sizeflag & AFLAG)
14041                          || bytemode == v_bnd_mode
14042                          || bytemode == v_bndmk_mode
14043                          || bytemode == bnd_mode
14044                          || bytemode == bnd_swap_mode);
14045       const char **indexes64 = names64;
14046       const char **indexes32 = names32;
14047
14048       havesib = 0;
14049       havebase = 1;
14050       haveindex = 0;
14051       base = modrm.rm;
14052
14053       if (base == 4)
14054         {
14055           havesib = 1;
14056           vindex = sib.index;
14057           USED_REX (REX_X);
14058           if (rex & REX_X)
14059             vindex += 8;
14060           switch (bytemode)
14061             {
14062             case vex_vsib_d_w_dq_mode:
14063             case vex_vsib_d_w_d_mode:
14064             case vex_vsib_q_w_dq_mode:
14065             case vex_vsib_q_w_d_mode:
14066               if (!need_vex)
14067                 abort ();
14068               if (vex.evex)
14069                 {
14070                   if (!vex.v)
14071                     vindex += 16;
14072                 }
14073
14074               haveindex = 1;
14075               switch (vex.length)
14076                 {
14077                 case 128:
14078                   indexes64 = indexes32 = names_xmm;
14079                   break;
14080                 case 256:
14081                   if (!vex.w
14082                       || bytemode == vex_vsib_q_w_dq_mode
14083                       || bytemode == vex_vsib_q_w_d_mode)
14084                     indexes64 = indexes32 = names_ymm;
14085                   else
14086                     indexes64 = indexes32 = names_xmm;
14087                   break;
14088                 case 512:
14089                   if (!vex.w
14090                       || bytemode == vex_vsib_q_w_dq_mode
14091                       || bytemode == vex_vsib_q_w_d_mode)
14092                     indexes64 = indexes32 = names_zmm;
14093                   else
14094                     indexes64 = indexes32 = names_ymm;
14095                   break;
14096                 default:
14097                   abort ();
14098                 }
14099               break;
14100             default:
14101               haveindex = vindex != 4;
14102               break;
14103             }
14104           scale = sib.scale;
14105           base = sib.base;
14106           codep++;
14107         }
14108       rbase = base + add;
14109
14110       switch (modrm.mod)
14111         {
14112         case 0:
14113           if (base == 5)
14114             {
14115               havebase = 0;
14116               if (address_mode == mode_64bit && !havesib)
14117                 riprel = 1;
14118               disp = get32s ();
14119               if (riprel && bytemode == v_bndmk_mode)
14120                 {
14121                   oappend ("(bad)");
14122                   return;
14123                 }
14124             }
14125           break;
14126         case 1:
14127           FETCH_DATA (the_info, codep + 1);
14128           disp = *codep++;
14129           if ((disp & 0x80) != 0)
14130             disp -= 0x100;
14131           if (vex.evex && shift > 0)
14132             disp <<= shift;
14133           break;
14134         case 2:
14135           disp = get32s ();
14136           break;
14137         }
14138
14139       needindex = 0;
14140       needaddr32 = 0;
14141       if (havesib
14142           && !havebase
14143           && !haveindex
14144           && address_mode != mode_16bit)
14145         {
14146           if (address_mode == mode_64bit)
14147             {
14148               /* Display eiz instead of addr32.  */
14149               needindex = addr32flag;
14150               needaddr32 = 1;
14151             }
14152           else
14153             {
14154               /* In 32-bit mode, we need index register to tell [offset]
14155                  from [eiz*1 + offset].  */
14156               needindex = 1;
14157             }
14158         }
14159
14160       havedisp = (havebase
14161                   || needindex
14162                   || (havesib && (haveindex || scale != 0)));
14163
14164       if (!intel_syntax)
14165         if (modrm.mod != 0 || base == 5)
14166           {
14167             if (havedisp || riprel)
14168               print_displacement (scratchbuf, disp);
14169             else
14170               print_operand_value (scratchbuf, 1, disp);
14171             oappend (scratchbuf);
14172             if (riprel)
14173               {
14174                 set_op (disp, 1);
14175                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14176               }
14177           }
14178
14179       if ((havebase || haveindex || needaddr32 || riprel)
14180           && (bytemode != v_bnd_mode)
14181           && (bytemode != v_bndmk_mode)
14182           && (bytemode != bnd_mode)
14183           && (bytemode != bnd_swap_mode))
14184         used_prefixes |= PREFIX_ADDR;
14185
14186       if (havedisp || (intel_syntax && riprel))
14187         {
14188           *obufp++ = open_char;
14189           if (intel_syntax && riprel)
14190             {
14191               set_op (disp, 1);
14192               oappend (!addr32flag ? "rip" : "eip");
14193             }
14194           *obufp = '\0';
14195           if (havebase)
14196             oappend (address_mode == mode_64bit && !addr32flag
14197                      ? names64[rbase] : names32[rbase]);
14198           if (havesib)
14199             {
14200               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14201                  print index to tell base + index from base.  */
14202               if (scale != 0
14203                   || needindex
14204                   || haveindex
14205                   || (havebase && base != ESP_REG_NUM))
14206                 {
14207                   if (!intel_syntax || havebase)
14208                     {
14209                       *obufp++ = separator_char;
14210                       *obufp = '\0';
14211                     }
14212                   if (haveindex)
14213                     oappend (address_mode == mode_64bit && !addr32flag
14214                              ? indexes64[vindex] : indexes32[vindex]);
14215                   else
14216                     oappend (address_mode == mode_64bit && !addr32flag
14217                              ? index64 : index32);
14218
14219                   *obufp++ = scale_char;
14220                   *obufp = '\0';
14221                   sprintf (scratchbuf, "%d", 1 << scale);
14222                   oappend (scratchbuf);
14223                 }
14224             }
14225           if (intel_syntax
14226               && (disp || modrm.mod != 0 || base == 5))
14227             {
14228               if (!havedisp || (bfd_signed_vma) disp >= 0)
14229                 {
14230                   *obufp++ = '+';
14231                   *obufp = '\0';
14232                 }
14233               else if (modrm.mod != 1 && disp != -disp)
14234                 {
14235                   *obufp++ = '-';
14236                   *obufp = '\0';
14237                   disp = - (bfd_signed_vma) disp;
14238                 }
14239
14240               if (havedisp)
14241                 print_displacement (scratchbuf, disp);
14242               else
14243                 print_operand_value (scratchbuf, 1, disp);
14244               oappend (scratchbuf);
14245             }
14246
14247           *obufp++ = close_char;
14248           *obufp = '\0';
14249         }
14250       else if (intel_syntax)
14251         {
14252           if (modrm.mod != 0 || base == 5)
14253             {
14254               if (!active_seg_prefix)
14255                 {
14256                   oappend (names_seg[ds_reg - es_reg]);
14257                   oappend (":");
14258                 }
14259               print_operand_value (scratchbuf, 1, disp);
14260               oappend (scratchbuf);
14261             }
14262         }
14263     }
14264   else
14265     {
14266       /* 16 bit address mode */
14267       used_prefixes |= prefixes & PREFIX_ADDR;
14268       switch (modrm.mod)
14269         {
14270         case 0:
14271           if (modrm.rm == 6)
14272             {
14273               disp = get16 ();
14274               if ((disp & 0x8000) != 0)
14275                 disp -= 0x10000;
14276             }
14277           break;
14278         case 1:
14279           FETCH_DATA (the_info, codep + 1);
14280           disp = *codep++;
14281           if ((disp & 0x80) != 0)
14282             disp -= 0x100;
14283           if (vex.evex && shift > 0)
14284             disp <<= shift;
14285           break;
14286         case 2:
14287           disp = get16 ();
14288           if ((disp & 0x8000) != 0)
14289             disp -= 0x10000;
14290           break;
14291         }
14292
14293       if (!intel_syntax)
14294         if (modrm.mod != 0 || modrm.rm == 6)
14295           {
14296             print_displacement (scratchbuf, disp);
14297             oappend (scratchbuf);
14298           }
14299
14300       if (modrm.mod != 0 || modrm.rm != 6)
14301         {
14302           *obufp++ = open_char;
14303           *obufp = '\0';
14304           oappend (index16[modrm.rm]);
14305           if (intel_syntax
14306               && (disp || modrm.mod != 0 || modrm.rm == 6))
14307             {
14308               if ((bfd_signed_vma) disp >= 0)
14309                 {
14310                   *obufp++ = '+';
14311                   *obufp = '\0';
14312                 }
14313               else if (modrm.mod != 1)
14314                 {
14315                   *obufp++ = '-';
14316                   *obufp = '\0';
14317                   disp = - (bfd_signed_vma) disp;
14318                 }
14319
14320               print_displacement (scratchbuf, disp);
14321               oappend (scratchbuf);
14322             }
14323
14324           *obufp++ = close_char;
14325           *obufp = '\0';
14326         }
14327       else if (intel_syntax)
14328         {
14329           if (!active_seg_prefix)
14330             {
14331               oappend (names_seg[ds_reg - es_reg]);
14332               oappend (":");
14333             }
14334           print_operand_value (scratchbuf, 1, disp & 0xffff);
14335           oappend (scratchbuf);
14336         }
14337     }
14338   if (vex.evex && vex.b
14339       && (bytemode == x_mode
14340           || bytemode == xmmq_mode
14341           || bytemode == evex_half_bcst_xmmq_mode))
14342     {
14343       if (vex.w
14344           || bytemode == xmmq_mode
14345           || bytemode == evex_half_bcst_xmmq_mode)
14346         {
14347           switch (vex.length)
14348             {
14349             case 128:
14350               oappend ("{1to2}");
14351               break;
14352             case 256:
14353               oappend ("{1to4}");
14354               break;
14355             case 512:
14356               oappend ("{1to8}");
14357               break;
14358             default:
14359               abort ();
14360             }
14361         }
14362       else
14363         {
14364           switch (vex.length)
14365             {
14366             case 128:
14367               oappend ("{1to4}");
14368               break;
14369             case 256:
14370               oappend ("{1to8}");
14371               break;
14372             case 512:
14373               oappend ("{1to16}");
14374               break;
14375             default:
14376               abort ();
14377             }
14378         }
14379     }
14380 }
14381
14382 static void
14383 OP_E (int bytemode, int sizeflag)
14384 {
14385   /* Skip mod/rm byte.  */
14386   MODRM_CHECK;
14387   codep++;
14388
14389   if (modrm.mod == 3)
14390     OP_E_register (bytemode, sizeflag);
14391   else
14392     OP_E_memory (bytemode, sizeflag);
14393 }
14394
14395 static void
14396 OP_G (int bytemode, int sizeflag)
14397 {
14398   int add = 0;
14399   const char **names;
14400   USED_REX (REX_R);
14401   if (rex & REX_R)
14402     add += 8;
14403   switch (bytemode)
14404     {
14405     case b_mode:
14406       USED_REX (0);
14407       if (rex)
14408         oappend (names8rex[modrm.reg + add]);
14409       else
14410         oappend (names8[modrm.reg + add]);
14411       break;
14412     case w_mode:
14413       oappend (names16[modrm.reg + add]);
14414       break;
14415     case d_mode:
14416     case db_mode:
14417     case dw_mode:
14418       oappend (names32[modrm.reg + add]);
14419       break;
14420     case q_mode:
14421       oappend (names64[modrm.reg + add]);
14422       break;
14423     case bnd_mode:
14424       if (modrm.reg > 0x3)
14425         {
14426           oappend ("(bad)");
14427           return;
14428         }
14429       oappend (names_bnd[modrm.reg]);
14430       break;
14431     case v_mode:
14432     case dq_mode:
14433     case dqb_mode:
14434     case dqd_mode:
14435     case dqw_mode:
14436       USED_REX (REX_W);
14437       if (rex & REX_W)
14438         oappend (names64[modrm.reg + add]);
14439       else
14440         {
14441           if ((sizeflag & DFLAG) || bytemode != v_mode)
14442             oappend (names32[modrm.reg + add]);
14443           else
14444             oappend (names16[modrm.reg + add]);
14445           used_prefixes |= (prefixes & PREFIX_DATA);
14446         }
14447       break;
14448     case va_mode:
14449       names = (address_mode == mode_64bit
14450                ? names64 : names32);
14451       if (!(prefixes & PREFIX_ADDR))
14452         {
14453           if (address_mode == mode_16bit)
14454             names = names16;
14455         }
14456       else
14457         {
14458           /* Remove "addr16/addr32".  */
14459           all_prefixes[last_addr_prefix] = 0;
14460           names = (address_mode != mode_32bit
14461                        ? names32 : names16);
14462           used_prefixes |= PREFIX_ADDR;
14463         }
14464       oappend (names[modrm.reg + add]);
14465       break;
14466     case m_mode:
14467       if (address_mode == mode_64bit)
14468         oappend (names64[modrm.reg + add]);
14469       else
14470         oappend (names32[modrm.reg + add]);
14471       break;
14472     case mask_bd_mode:
14473     case mask_mode:
14474       if ((modrm.reg + add) > 0x7)
14475         {
14476           oappend ("(bad)");
14477           return;
14478         }
14479       oappend (names_mask[modrm.reg + add]);
14480       break;
14481     default:
14482       oappend (INTERNAL_DISASSEMBLER_ERROR);
14483       break;
14484     }
14485 }
14486
14487 static bfd_vma
14488 get64 (void)
14489 {
14490   bfd_vma x;
14491 #ifdef BFD64
14492   unsigned int a;
14493   unsigned int b;
14494
14495   FETCH_DATA (the_info, codep + 8);
14496   a = *codep++ & 0xff;
14497   a |= (*codep++ & 0xff) << 8;
14498   a |= (*codep++ & 0xff) << 16;
14499   a |= (*codep++ & 0xffu) << 24;
14500   b = *codep++ & 0xff;
14501   b |= (*codep++ & 0xff) << 8;
14502   b |= (*codep++ & 0xff) << 16;
14503   b |= (*codep++ & 0xffu) << 24;
14504   x = a + ((bfd_vma) b << 32);
14505 #else
14506   abort ();
14507   x = 0;
14508 #endif
14509   return x;
14510 }
14511
14512 static bfd_signed_vma
14513 get32 (void)
14514 {
14515   bfd_signed_vma x = 0;
14516
14517   FETCH_DATA (the_info, codep + 4);
14518   x = *codep++ & (bfd_signed_vma) 0xff;
14519   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14520   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14521   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14522   return x;
14523 }
14524
14525 static bfd_signed_vma
14526 get32s (void)
14527 {
14528   bfd_signed_vma x = 0;
14529
14530   FETCH_DATA (the_info, codep + 4);
14531   x = *codep++ & (bfd_signed_vma) 0xff;
14532   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14533   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14534   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14535
14536   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14537
14538   return x;
14539 }
14540
14541 static int
14542 get16 (void)
14543 {
14544   int x = 0;
14545
14546   FETCH_DATA (the_info, codep + 2);
14547   x = *codep++ & 0xff;
14548   x |= (*codep++ & 0xff) << 8;
14549   return x;
14550 }
14551
14552 static void
14553 set_op (bfd_vma op, int riprel)
14554 {
14555   op_index[op_ad] = op_ad;
14556   if (address_mode == mode_64bit)
14557     {
14558       op_address[op_ad] = op;
14559       op_riprel[op_ad] = riprel;
14560     }
14561   else
14562     {
14563       /* Mask to get a 32-bit address.  */
14564       op_address[op_ad] = op & 0xffffffff;
14565       op_riprel[op_ad] = riprel & 0xffffffff;
14566     }
14567 }
14568
14569 static void
14570 OP_REG (int code, int sizeflag)
14571 {
14572   const char *s;
14573   int add;
14574
14575   switch (code)
14576     {
14577     case es_reg: case ss_reg: case cs_reg:
14578     case ds_reg: case fs_reg: case gs_reg:
14579       oappend (names_seg[code - es_reg]);
14580       return;
14581     }
14582
14583   USED_REX (REX_B);
14584   if (rex & REX_B)
14585     add = 8;
14586   else
14587     add = 0;
14588
14589   switch (code)
14590     {
14591     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14592     case sp_reg: case bp_reg: case si_reg: case di_reg:
14593       s = names16[code - ax_reg + add];
14594       break;
14595     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14596     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14597       USED_REX (0);
14598       if (rex)
14599         s = names8rex[code - al_reg + add];
14600       else
14601         s = names8[code - al_reg];
14602       break;
14603     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14604     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14605       if (address_mode == mode_64bit
14606           && ((sizeflag & DFLAG) || (rex & REX_W)))
14607         {
14608           s = names64[code - rAX_reg + add];
14609           break;
14610         }
14611       code += eAX_reg - rAX_reg;
14612       /* Fall through.  */
14613     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14614     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14615       USED_REX (REX_W);
14616       if (rex & REX_W)
14617         s = names64[code - eAX_reg + add];
14618       else
14619         {
14620           if (sizeflag & DFLAG)
14621             s = names32[code - eAX_reg + add];
14622           else
14623             s = names16[code - eAX_reg + add];
14624           used_prefixes |= (prefixes & PREFIX_DATA);
14625         }
14626       break;
14627     default:
14628       s = INTERNAL_DISASSEMBLER_ERROR;
14629       break;
14630     }
14631   oappend (s);
14632 }
14633
14634 static void
14635 OP_IMREG (int code, int sizeflag)
14636 {
14637   const char *s;
14638
14639   switch (code)
14640     {
14641     case indir_dx_reg:
14642       if (intel_syntax)
14643         s = "dx";
14644       else
14645         s = "(%dx)";
14646       break;
14647     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14648     case sp_reg: case bp_reg: case si_reg: case di_reg:
14649       s = names16[code - ax_reg];
14650       break;
14651     case es_reg: case ss_reg: case cs_reg:
14652     case ds_reg: case fs_reg: case gs_reg:
14653       s = names_seg[code - es_reg];
14654       break;
14655     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14656     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14657       USED_REX (0);
14658       if (rex)
14659         s = names8rex[code - al_reg];
14660       else
14661         s = names8[code - al_reg];
14662       break;
14663     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14664     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14665       USED_REX (REX_W);
14666       if (rex & REX_W)
14667         s = names64[code - eAX_reg];
14668       else
14669         {
14670           if (sizeflag & DFLAG)
14671             s = names32[code - eAX_reg];
14672           else
14673             s = names16[code - eAX_reg];
14674           used_prefixes |= (prefixes & PREFIX_DATA);
14675         }
14676       break;
14677     case z_mode_ax_reg:
14678       if ((rex & REX_W) || (sizeflag & DFLAG))
14679         s = *names32;
14680       else
14681         s = *names16;
14682       if (!(rex & REX_W))
14683         used_prefixes |= (prefixes & PREFIX_DATA);
14684       break;
14685     default:
14686       s = INTERNAL_DISASSEMBLER_ERROR;
14687       break;
14688     }
14689   oappend (s);
14690 }
14691
14692 static void
14693 OP_I (int bytemode, int sizeflag)
14694 {
14695   bfd_signed_vma op;
14696   bfd_signed_vma mask = -1;
14697
14698   switch (bytemode)
14699     {
14700     case b_mode:
14701       FETCH_DATA (the_info, codep + 1);
14702       op = *codep++;
14703       mask = 0xff;
14704       break;
14705     case q_mode:
14706       if (address_mode == mode_64bit)
14707         {
14708           op = get32s ();
14709           break;
14710         }
14711       /* Fall through.  */
14712     case v_mode:
14713       USED_REX (REX_W);
14714       if (rex & REX_W)
14715         op = get32s ();
14716       else
14717         {
14718           if (sizeflag & DFLAG)
14719             {
14720               op = get32 ();
14721               mask = 0xffffffff;
14722             }
14723           else
14724             {
14725               op = get16 ();
14726               mask = 0xfffff;
14727             }
14728           used_prefixes |= (prefixes & PREFIX_DATA);
14729         }
14730       break;
14731     case w_mode:
14732       mask = 0xfffff;
14733       op = get16 ();
14734       break;
14735     case const_1_mode:
14736       if (intel_syntax)
14737         oappend ("1");
14738       return;
14739     default:
14740       oappend (INTERNAL_DISASSEMBLER_ERROR);
14741       return;
14742     }
14743
14744   op &= mask;
14745   scratchbuf[0] = '$';
14746   print_operand_value (scratchbuf + 1, 1, op);
14747   oappend_maybe_intel (scratchbuf);
14748   scratchbuf[0] = '\0';
14749 }
14750
14751 static void
14752 OP_I64 (int bytemode, int sizeflag)
14753 {
14754   bfd_signed_vma op;
14755   bfd_signed_vma mask = -1;
14756
14757   if (address_mode != mode_64bit)
14758     {
14759       OP_I (bytemode, sizeflag);
14760       return;
14761     }
14762
14763   switch (bytemode)
14764     {
14765     case b_mode:
14766       FETCH_DATA (the_info, codep + 1);
14767       op = *codep++;
14768       mask = 0xff;
14769       break;
14770     case v_mode:
14771       USED_REX (REX_W);
14772       if (rex & REX_W)
14773         op = get64 ();
14774       else
14775         {
14776           if (sizeflag & DFLAG)
14777             {
14778               op = get32 ();
14779               mask = 0xffffffff;
14780             }
14781           else
14782             {
14783               op = get16 ();
14784               mask = 0xfffff;
14785             }
14786           used_prefixes |= (prefixes & PREFIX_DATA);
14787         }
14788       break;
14789     case w_mode:
14790       mask = 0xfffff;
14791       op = get16 ();
14792       break;
14793     default:
14794       oappend (INTERNAL_DISASSEMBLER_ERROR);
14795       return;
14796     }
14797
14798   op &= mask;
14799   scratchbuf[0] = '$';
14800   print_operand_value (scratchbuf + 1, 1, op);
14801   oappend_maybe_intel (scratchbuf);
14802   scratchbuf[0] = '\0';
14803 }
14804
14805 static void
14806 OP_sI (int bytemode, int sizeflag)
14807 {
14808   bfd_signed_vma op;
14809
14810   switch (bytemode)
14811     {
14812     case b_mode:
14813     case b_T_mode:
14814       FETCH_DATA (the_info, codep + 1);
14815       op = *codep++;
14816       if ((op & 0x80) != 0)
14817         op -= 0x100;
14818       if (bytemode == b_T_mode)
14819         {
14820           if (address_mode != mode_64bit
14821               || !((sizeflag & DFLAG) || (rex & REX_W)))
14822             {
14823               /* The operand-size prefix is overridden by a REX prefix.  */
14824               if ((sizeflag & DFLAG) || (rex & REX_W))
14825                 op &= 0xffffffff;
14826               else
14827                 op &= 0xffff;
14828           }
14829         }
14830       else
14831         {
14832           if (!(rex & REX_W))
14833             {
14834               if (sizeflag & DFLAG)
14835                 op &= 0xffffffff;
14836               else
14837                 op &= 0xffff;
14838             }
14839         }
14840       break;
14841     case v_mode:
14842       /* The operand-size prefix is overridden by a REX prefix.  */
14843       if ((sizeflag & DFLAG) || (rex & REX_W))
14844         op = get32s ();
14845       else
14846         op = get16 ();
14847       break;
14848     default:
14849       oappend (INTERNAL_DISASSEMBLER_ERROR);
14850       return;
14851     }
14852
14853   scratchbuf[0] = '$';
14854   print_operand_value (scratchbuf + 1, 1, op);
14855   oappend_maybe_intel (scratchbuf);
14856 }
14857
14858 static void
14859 OP_J (int bytemode, int sizeflag)
14860 {
14861   bfd_vma disp;
14862   bfd_vma mask = -1;
14863   bfd_vma segment = 0;
14864
14865   switch (bytemode)
14866     {
14867     case b_mode:
14868       FETCH_DATA (the_info, codep + 1);
14869       disp = *codep++;
14870       if ((disp & 0x80) != 0)
14871         disp -= 0x100;
14872       break;
14873     case v_mode:
14874       if (isa64 == amd64)
14875         USED_REX (REX_W);
14876       if ((sizeflag & DFLAG)
14877           || (address_mode == mode_64bit
14878               && (isa64 != amd64 || (rex & REX_W))))
14879         disp = get32s ();
14880       else
14881         {
14882           disp = get16 ();
14883           if ((disp & 0x8000) != 0)
14884             disp -= 0x10000;
14885           /* In 16bit mode, address is wrapped around at 64k within
14886              the same segment.  Otherwise, a data16 prefix on a jump
14887              instruction means that the pc is masked to 16 bits after
14888              the displacement is added!  */
14889           mask = 0xffff;
14890           if ((prefixes & PREFIX_DATA) == 0)
14891             segment = ((start_pc + (codep - start_codep))
14892                        & ~((bfd_vma) 0xffff));
14893         }
14894       if (address_mode != mode_64bit
14895           || (isa64 == amd64 && !(rex & REX_W)))
14896         used_prefixes |= (prefixes & PREFIX_DATA);
14897       break;
14898     default:
14899       oappend (INTERNAL_DISASSEMBLER_ERROR);
14900       return;
14901     }
14902   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14903   set_op (disp, 0);
14904   print_operand_value (scratchbuf, 1, disp);
14905   oappend (scratchbuf);
14906 }
14907
14908 static void
14909 OP_SEG (int bytemode, int sizeflag)
14910 {
14911   if (bytemode == w_mode)
14912     oappend (names_seg[modrm.reg]);
14913   else
14914     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14915 }
14916
14917 static void
14918 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14919 {
14920   int seg, offset;
14921
14922   if (sizeflag & DFLAG)
14923     {
14924       offset = get32 ();
14925       seg = get16 ();
14926     }
14927   else
14928     {
14929       offset = get16 ();
14930       seg = get16 ();
14931     }
14932   used_prefixes |= (prefixes & PREFIX_DATA);
14933   if (intel_syntax)
14934     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14935   else
14936     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14937   oappend (scratchbuf);
14938 }
14939
14940 static void
14941 OP_OFF (int bytemode, int sizeflag)
14942 {
14943   bfd_vma off;
14944
14945   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14946     intel_operand_size (bytemode, sizeflag);
14947   append_seg ();
14948
14949   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14950     off = get32 ();
14951   else
14952     off = get16 ();
14953
14954   if (intel_syntax)
14955     {
14956       if (!active_seg_prefix)
14957         {
14958           oappend (names_seg[ds_reg - es_reg]);
14959           oappend (":");
14960         }
14961     }
14962   print_operand_value (scratchbuf, 1, off);
14963   oappend (scratchbuf);
14964 }
14965
14966 static void
14967 OP_OFF64 (int bytemode, int sizeflag)
14968 {
14969   bfd_vma off;
14970
14971   if (address_mode != mode_64bit
14972       || (prefixes & PREFIX_ADDR))
14973     {
14974       OP_OFF (bytemode, sizeflag);
14975       return;
14976     }
14977
14978   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14979     intel_operand_size (bytemode, sizeflag);
14980   append_seg ();
14981
14982   off = get64 ();
14983
14984   if (intel_syntax)
14985     {
14986       if (!active_seg_prefix)
14987         {
14988           oappend (names_seg[ds_reg - es_reg]);
14989           oappend (":");
14990         }
14991     }
14992   print_operand_value (scratchbuf, 1, off);
14993   oappend (scratchbuf);
14994 }
14995
14996 static void
14997 ptr_reg (int code, int sizeflag)
14998 {
14999   const char *s;
15000
15001   *obufp++ = open_char;
15002   used_prefixes |= (prefixes & PREFIX_ADDR);
15003   if (address_mode == mode_64bit)
15004     {
15005       if (!(sizeflag & AFLAG))
15006         s = names32[code - eAX_reg];
15007       else
15008         s = names64[code - eAX_reg];
15009     }
15010   else if (sizeflag & AFLAG)
15011     s = names32[code - eAX_reg];
15012   else
15013     s = names16[code - eAX_reg];
15014   oappend (s);
15015   *obufp++ = close_char;
15016   *obufp = 0;
15017 }
15018
15019 static void
15020 OP_ESreg (int code, int sizeflag)
15021 {
15022   if (intel_syntax)
15023     {
15024       switch (codep[-1])
15025         {
15026         case 0x6d:      /* insw/insl */
15027           intel_operand_size (z_mode, sizeflag);
15028           break;
15029         case 0xa5:      /* movsw/movsl/movsq */
15030         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15031         case 0xab:      /* stosw/stosl */
15032         case 0xaf:      /* scasw/scasl */
15033           intel_operand_size (v_mode, sizeflag);
15034           break;
15035         default:
15036           intel_operand_size (b_mode, sizeflag);
15037         }
15038     }
15039   oappend_maybe_intel ("%es:");
15040   ptr_reg (code, sizeflag);
15041 }
15042
15043 static void
15044 OP_DSreg (int code, int sizeflag)
15045 {
15046   if (intel_syntax)
15047     {
15048       switch (codep[-1])
15049         {
15050         case 0x6f:      /* outsw/outsl */
15051           intel_operand_size (z_mode, sizeflag);
15052           break;
15053         case 0xa5:      /* movsw/movsl/movsq */
15054         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15055         case 0xad:      /* lodsw/lodsl/lodsq */
15056           intel_operand_size (v_mode, sizeflag);
15057           break;
15058         default:
15059           intel_operand_size (b_mode, sizeflag);
15060         }
15061     }
15062   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15063      default segment register DS is printed.  */
15064   if (!active_seg_prefix)
15065     active_seg_prefix = PREFIX_DS;
15066   append_seg ();
15067   ptr_reg (code, sizeflag);
15068 }
15069
15070 static void
15071 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15072 {
15073   int add;
15074   if (rex & REX_R)
15075     {
15076       USED_REX (REX_R);
15077       add = 8;
15078     }
15079   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15080     {
15081       all_prefixes[last_lock_prefix] = 0;
15082       used_prefixes |= PREFIX_LOCK;
15083       add = 8;
15084     }
15085   else
15086     add = 0;
15087   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15088   oappend_maybe_intel (scratchbuf);
15089 }
15090
15091 static void
15092 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15093 {
15094   int add;
15095   USED_REX (REX_R);
15096   if (rex & REX_R)
15097     add = 8;
15098   else
15099     add = 0;
15100   if (intel_syntax)
15101     sprintf (scratchbuf, "db%d", modrm.reg + add);
15102   else
15103     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15104   oappend (scratchbuf);
15105 }
15106
15107 static void
15108 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15109 {
15110   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15111   oappend_maybe_intel (scratchbuf);
15112 }
15113
15114 static void
15115 OP_R (int bytemode, int sizeflag)
15116 {
15117   /* Skip mod/rm byte.  */
15118   MODRM_CHECK;
15119   codep++;
15120   OP_E_register (bytemode, sizeflag);
15121 }
15122
15123 static void
15124 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15125 {
15126   int reg = modrm.reg;
15127   const char **names;
15128
15129   used_prefixes |= (prefixes & PREFIX_DATA);
15130   if (prefixes & PREFIX_DATA)
15131     {
15132       names = names_xmm;
15133       USED_REX (REX_R);
15134       if (rex & REX_R)
15135         reg += 8;
15136     }
15137   else
15138     names = names_mm;
15139   oappend (names[reg]);
15140 }
15141
15142 static void
15143 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15144 {
15145   int reg = modrm.reg;
15146   const char **names;
15147
15148   USED_REX (REX_R);
15149   if (rex & REX_R)
15150     reg += 8;
15151   if (vex.evex)
15152     {
15153       if (!vex.r)
15154         reg += 16;
15155     }
15156
15157   if (need_vex
15158       && bytemode != xmm_mode
15159       && bytemode != xmmq_mode
15160       && bytemode != evex_half_bcst_xmmq_mode
15161       && bytemode != ymm_mode
15162       && bytemode != scalar_mode)
15163     {
15164       switch (vex.length)
15165         {
15166         case 128:
15167           names = names_xmm;
15168           break;
15169         case 256:
15170           if (vex.w
15171               || (bytemode != vex_vsib_q_w_dq_mode
15172                   && bytemode != vex_vsib_q_w_d_mode))
15173             names = names_ymm;
15174           else
15175             names = names_xmm;
15176           break;
15177         case 512:
15178           names = names_zmm;
15179           break;
15180         default:
15181           abort ();
15182         }
15183     }
15184   else if (bytemode == xmmq_mode
15185            || bytemode == evex_half_bcst_xmmq_mode)
15186     {
15187       switch (vex.length)
15188         {
15189         case 128:
15190         case 256:
15191           names = names_xmm;
15192           break;
15193         case 512:
15194           names = names_ymm;
15195           break;
15196         default:
15197           abort ();
15198         }
15199     }
15200   else if (bytemode == ymm_mode)
15201     names = names_ymm;
15202   else
15203     names = names_xmm;
15204   oappend (names[reg]);
15205 }
15206
15207 static void
15208 OP_EM (int bytemode, int sizeflag)
15209 {
15210   int reg;
15211   const char **names;
15212
15213   if (modrm.mod != 3)
15214     {
15215       if (intel_syntax
15216           && (bytemode == v_mode || bytemode == v_swap_mode))
15217         {
15218           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15219           used_prefixes |= (prefixes & PREFIX_DATA);
15220         }
15221       OP_E (bytemode, sizeflag);
15222       return;
15223     }
15224
15225   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15226     swap_operand ();
15227
15228   /* Skip mod/rm byte.  */
15229   MODRM_CHECK;
15230   codep++;
15231   used_prefixes |= (prefixes & PREFIX_DATA);
15232   reg = modrm.rm;
15233   if (prefixes & PREFIX_DATA)
15234     {
15235       names = names_xmm;
15236       USED_REX (REX_B);
15237       if (rex & REX_B)
15238         reg += 8;
15239     }
15240   else
15241     names = names_mm;
15242   oappend (names[reg]);
15243 }
15244
15245 /* cvt* are the only instructions in sse2 which have
15246    both SSE and MMX operands and also have 0x66 prefix
15247    in their opcode. 0x66 was originally used to differentiate
15248    between SSE and MMX instruction(operands). So we have to handle the
15249    cvt* separately using OP_EMC and OP_MXC */
15250 static void
15251 OP_EMC (int bytemode, int sizeflag)
15252 {
15253   if (modrm.mod != 3)
15254     {
15255       if (intel_syntax && bytemode == v_mode)
15256         {
15257           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15258           used_prefixes |= (prefixes & PREFIX_DATA);
15259         }
15260       OP_E (bytemode, sizeflag);
15261       return;
15262     }
15263
15264   /* Skip mod/rm byte.  */
15265   MODRM_CHECK;
15266   codep++;
15267   used_prefixes |= (prefixes & PREFIX_DATA);
15268   oappend (names_mm[modrm.rm]);
15269 }
15270
15271 static void
15272 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15273 {
15274   used_prefixes |= (prefixes & PREFIX_DATA);
15275   oappend (names_mm[modrm.reg]);
15276 }
15277
15278 static void
15279 OP_EX (int bytemode, int sizeflag)
15280 {
15281   int reg;
15282   const char **names;
15283
15284   /* Skip mod/rm byte.  */
15285   MODRM_CHECK;
15286   codep++;
15287
15288   if (modrm.mod != 3)
15289     {
15290       OP_E_memory (bytemode, sizeflag);
15291       return;
15292     }
15293
15294   reg = modrm.rm;
15295   USED_REX (REX_B);
15296   if (rex & REX_B)
15297     reg += 8;
15298   if (vex.evex)
15299     {
15300       USED_REX (REX_X);
15301       if ((rex & REX_X))
15302         reg += 16;
15303     }
15304
15305   if ((sizeflag & SUFFIX_ALWAYS)
15306       && (bytemode == x_swap_mode
15307           || bytemode == d_swap_mode
15308           || bytemode == d_scalar_swap_mode
15309           || bytemode == q_swap_mode
15310           || bytemode == q_scalar_swap_mode))
15311     swap_operand ();
15312
15313   if (need_vex
15314       && bytemode != xmm_mode
15315       && bytemode != xmmdw_mode
15316       && bytemode != xmmqd_mode
15317       && bytemode != xmm_mb_mode
15318       && bytemode != xmm_mw_mode
15319       && bytemode != xmm_md_mode
15320       && bytemode != xmm_mq_mode
15321       && bytemode != xmm_mdq_mode
15322       && bytemode != xmmq_mode
15323       && bytemode != evex_half_bcst_xmmq_mode
15324       && bytemode != ymm_mode
15325       && bytemode != d_scalar_mode
15326       && bytemode != d_scalar_swap_mode
15327       && bytemode != q_scalar_mode
15328       && bytemode != q_scalar_swap_mode
15329       && bytemode != vex_scalar_w_dq_mode)
15330     {
15331       switch (vex.length)
15332         {
15333         case 128:
15334           names = names_xmm;
15335           break;
15336         case 256:
15337           names = names_ymm;
15338           break;
15339         case 512:
15340           names = names_zmm;
15341           break;
15342         default:
15343           abort ();
15344         }
15345     }
15346   else if (bytemode == xmmq_mode
15347            || bytemode == evex_half_bcst_xmmq_mode)
15348     {
15349       switch (vex.length)
15350         {
15351         case 128:
15352         case 256:
15353           names = names_xmm;
15354           break;
15355         case 512:
15356           names = names_ymm;
15357           break;
15358         default:
15359           abort ();
15360         }
15361     }
15362   else if (bytemode == ymm_mode)
15363     names = names_ymm;
15364   else
15365     names = names_xmm;
15366   oappend (names[reg]);
15367 }
15368
15369 static void
15370 OP_MS (int bytemode, int sizeflag)
15371 {
15372   if (modrm.mod == 3)
15373     OP_EM (bytemode, sizeflag);
15374   else
15375     BadOp ();
15376 }
15377
15378 static void
15379 OP_XS (int bytemode, int sizeflag)
15380 {
15381   if (modrm.mod == 3)
15382     OP_EX (bytemode, sizeflag);
15383   else
15384     BadOp ();
15385 }
15386
15387 static void
15388 OP_M (int bytemode, int sizeflag)
15389 {
15390   if (modrm.mod == 3)
15391     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15392     BadOp ();
15393   else
15394     OP_E (bytemode, sizeflag);
15395 }
15396
15397 static void
15398 OP_0f07 (int bytemode, int sizeflag)
15399 {
15400   if (modrm.mod != 3 || modrm.rm != 0)
15401     BadOp ();
15402   else
15403     OP_E (bytemode, sizeflag);
15404 }
15405
15406 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15407    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15408
15409 static void
15410 NOP_Fixup1 (int bytemode, int sizeflag)
15411 {
15412   if ((prefixes & PREFIX_DATA) != 0
15413       || (rex != 0
15414           && rex != 0x48
15415           && address_mode == mode_64bit))
15416     OP_REG (bytemode, sizeflag);
15417   else
15418     strcpy (obuf, "nop");
15419 }
15420
15421 static void
15422 NOP_Fixup2 (int bytemode, int sizeflag)
15423 {
15424   if ((prefixes & PREFIX_DATA) != 0
15425       || (rex != 0
15426           && rex != 0x48
15427           && address_mode == mode_64bit))
15428     OP_IMREG (bytemode, sizeflag);
15429 }
15430
15431 static const char *const Suffix3DNow[] = {
15432 /* 00 */        NULL,           NULL,           NULL,           NULL,
15433 /* 04 */        NULL,           NULL,           NULL,           NULL,
15434 /* 08 */        NULL,           NULL,           NULL,           NULL,
15435 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15436 /* 10 */        NULL,           NULL,           NULL,           NULL,
15437 /* 14 */        NULL,           NULL,           NULL,           NULL,
15438 /* 18 */        NULL,           NULL,           NULL,           NULL,
15439 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15440 /* 20 */        NULL,           NULL,           NULL,           NULL,
15441 /* 24 */        NULL,           NULL,           NULL,           NULL,
15442 /* 28 */        NULL,           NULL,           NULL,           NULL,
15443 /* 2C */        NULL,           NULL,           NULL,           NULL,
15444 /* 30 */        NULL,           NULL,           NULL,           NULL,
15445 /* 34 */        NULL,           NULL,           NULL,           NULL,
15446 /* 38 */        NULL,           NULL,           NULL,           NULL,
15447 /* 3C */        NULL,           NULL,           NULL,           NULL,
15448 /* 40 */        NULL,           NULL,           NULL,           NULL,
15449 /* 44 */        NULL,           NULL,           NULL,           NULL,
15450 /* 48 */        NULL,           NULL,           NULL,           NULL,
15451 /* 4C */        NULL,           NULL,           NULL,           NULL,
15452 /* 50 */        NULL,           NULL,           NULL,           NULL,
15453 /* 54 */        NULL,           NULL,           NULL,           NULL,
15454 /* 58 */        NULL,           NULL,           NULL,           NULL,
15455 /* 5C */        NULL,           NULL,           NULL,           NULL,
15456 /* 60 */        NULL,           NULL,           NULL,           NULL,
15457 /* 64 */        NULL,           NULL,           NULL,           NULL,
15458 /* 68 */        NULL,           NULL,           NULL,           NULL,
15459 /* 6C */        NULL,           NULL,           NULL,           NULL,
15460 /* 70 */        NULL,           NULL,           NULL,           NULL,
15461 /* 74 */        NULL,           NULL,           NULL,           NULL,
15462 /* 78 */        NULL,           NULL,           NULL,           NULL,
15463 /* 7C */        NULL,           NULL,           NULL,           NULL,
15464 /* 80 */        NULL,           NULL,           NULL,           NULL,
15465 /* 84 */        NULL,           NULL,           NULL,           NULL,
15466 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15467 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15468 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15469 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15470 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15471 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15472 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15473 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15474 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15475 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15476 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15477 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15478 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15479 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15480 /* C0 */        NULL,           NULL,           NULL,           NULL,
15481 /* C4 */        NULL,           NULL,           NULL,           NULL,
15482 /* C8 */        NULL,           NULL,           NULL,           NULL,
15483 /* CC */        NULL,           NULL,           NULL,           NULL,
15484 /* D0 */        NULL,           NULL,           NULL,           NULL,
15485 /* D4 */        NULL,           NULL,           NULL,           NULL,
15486 /* D8 */        NULL,           NULL,           NULL,           NULL,
15487 /* DC */        NULL,           NULL,           NULL,           NULL,
15488 /* E0 */        NULL,           NULL,           NULL,           NULL,
15489 /* E4 */        NULL,           NULL,           NULL,           NULL,
15490 /* E8 */        NULL,           NULL,           NULL,           NULL,
15491 /* EC */        NULL,           NULL,           NULL,           NULL,
15492 /* F0 */        NULL,           NULL,           NULL,           NULL,
15493 /* F4 */        NULL,           NULL,           NULL,           NULL,
15494 /* F8 */        NULL,           NULL,           NULL,           NULL,
15495 /* FC */        NULL,           NULL,           NULL,           NULL,
15496 };
15497
15498 static void
15499 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15500 {
15501   const char *mnemonic;
15502
15503   FETCH_DATA (the_info, codep + 1);
15504   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15505      place where an 8-bit immediate would normally go.  ie. the last
15506      byte of the instruction.  */
15507   obufp = mnemonicendp;
15508   mnemonic = Suffix3DNow[*codep++ & 0xff];
15509   if (mnemonic)
15510     oappend (mnemonic);
15511   else
15512     {
15513       /* Since a variable sized modrm/sib chunk is between the start
15514          of the opcode (0x0f0f) and the opcode suffix, we need to do
15515          all the modrm processing first, and don't know until now that
15516          we have a bad opcode.  This necessitates some cleaning up.  */
15517       op_out[0][0] = '\0';
15518       op_out[1][0] = '\0';
15519       BadOp ();
15520     }
15521   mnemonicendp = obufp;
15522 }
15523
15524 static struct op simd_cmp_op[] =
15525 {
15526   { STRING_COMMA_LEN ("eq") },
15527   { STRING_COMMA_LEN ("lt") },
15528   { STRING_COMMA_LEN ("le") },
15529   { STRING_COMMA_LEN ("unord") },
15530   { STRING_COMMA_LEN ("neq") },
15531   { STRING_COMMA_LEN ("nlt") },
15532   { STRING_COMMA_LEN ("nle") },
15533   { STRING_COMMA_LEN ("ord") }
15534 };
15535
15536 static void
15537 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15538 {
15539   unsigned int cmp_type;
15540
15541   FETCH_DATA (the_info, codep + 1);
15542   cmp_type = *codep++ & 0xff;
15543   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15544     {
15545       char suffix [3];
15546       char *p = mnemonicendp - 2;
15547       suffix[0] = p[0];
15548       suffix[1] = p[1];
15549       suffix[2] = '\0';
15550       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15551       mnemonicendp += simd_cmp_op[cmp_type].len;
15552     }
15553   else
15554     {
15555       /* We have a reserved extension byte.  Output it directly.  */
15556       scratchbuf[0] = '$';
15557       print_operand_value (scratchbuf + 1, 1, cmp_type);
15558       oappend_maybe_intel (scratchbuf);
15559       scratchbuf[0] = '\0';
15560     }
15561 }
15562
15563 static void
15564 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15565           int sizeflag ATTRIBUTE_UNUSED)
15566 {
15567   /* mwaitx %eax,%ecx,%ebx */
15568   if (!intel_syntax)
15569     {
15570       const char **names = (address_mode == mode_64bit
15571                             ? names64 : names32);
15572       strcpy (op_out[0], names[0]);
15573       strcpy (op_out[1], names[1]);
15574       strcpy (op_out[2], names[3]);
15575       two_source_ops = 1;
15576     }
15577   /* Skip mod/rm byte.  */
15578   MODRM_CHECK;
15579   codep++;
15580 }
15581
15582 static void
15583 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15584           int sizeflag ATTRIBUTE_UNUSED)
15585 {
15586   /* mwait %eax,%ecx  */
15587   if (!intel_syntax)
15588     {
15589       const char **names = (address_mode == mode_64bit
15590                             ? names64 : names32);
15591       strcpy (op_out[0], names[0]);
15592       strcpy (op_out[1], names[1]);
15593       two_source_ops = 1;
15594     }
15595   /* Skip mod/rm byte.  */
15596   MODRM_CHECK;
15597   codep++;
15598 }
15599
15600 static void
15601 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15602             int sizeflag ATTRIBUTE_UNUSED)
15603 {
15604   /* monitor %eax,%ecx,%edx"  */
15605   if (!intel_syntax)
15606     {
15607       const char **op1_names;
15608       const char **names = (address_mode == mode_64bit
15609                             ? names64 : names32);
15610
15611       if (!(prefixes & PREFIX_ADDR))
15612         op1_names = (address_mode == mode_16bit
15613                      ? names16 : names);
15614       else
15615         {
15616           /* Remove "addr16/addr32".  */
15617           all_prefixes[last_addr_prefix] = 0;
15618           op1_names = (address_mode != mode_32bit
15619                        ? names32 : names16);
15620           used_prefixes |= PREFIX_ADDR;
15621         }
15622       strcpy (op_out[0], op1_names[0]);
15623       strcpy (op_out[1], names[1]);
15624       strcpy (op_out[2], names[2]);
15625       two_source_ops = 1;
15626     }
15627   /* Skip mod/rm byte.  */
15628   MODRM_CHECK;
15629   codep++;
15630 }
15631
15632 static void
15633 BadOp (void)
15634 {
15635   /* Throw away prefixes and 1st. opcode byte.  */
15636   codep = insn_codep + 1;
15637   oappend ("(bad)");
15638 }
15639
15640 static void
15641 REP_Fixup (int bytemode, int sizeflag)
15642 {
15643   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15644      lods and stos.  */
15645   if (prefixes & PREFIX_REPZ)
15646     all_prefixes[last_repz_prefix] = REP_PREFIX;
15647
15648   switch (bytemode)
15649     {
15650     case al_reg:
15651     case eAX_reg:
15652     case indir_dx_reg:
15653       OP_IMREG (bytemode, sizeflag);
15654       break;
15655     case eDI_reg:
15656       OP_ESreg (bytemode, sizeflag);
15657       break;
15658     case eSI_reg:
15659       OP_DSreg (bytemode, sizeflag);
15660       break;
15661     default:
15662       abort ();
15663       break;
15664     }
15665 }
15666
15667 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15668    "bnd".  */
15669
15670 static void
15671 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15672 {
15673   if (prefixes & PREFIX_REPNZ)
15674     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15675 }
15676
15677 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15678    "notrack".  */
15679
15680 static void
15681 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15682                int sizeflag ATTRIBUTE_UNUSED)
15683 {
15684   if (active_seg_prefix == PREFIX_DS
15685       && (address_mode != mode_64bit || last_data_prefix < 0))
15686     {
15687       /* NOTRACK prefix is only valid on indirect branch instructions.
15688          NB: DATA prefix is unsupported for Intel64.  */
15689       active_seg_prefix = 0;
15690       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15691     }
15692 }
15693
15694 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15695    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15696  */
15697
15698 static void
15699 HLE_Fixup1 (int bytemode, int sizeflag)
15700 {
15701   if (modrm.mod != 3
15702       && (prefixes & PREFIX_LOCK) != 0)
15703     {
15704       if (prefixes & PREFIX_REPZ)
15705         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15706       if (prefixes & PREFIX_REPNZ)
15707         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15708     }
15709
15710   OP_E (bytemode, sizeflag);
15711 }
15712
15713 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15714    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15715  */
15716
15717 static void
15718 HLE_Fixup2 (int bytemode, int sizeflag)
15719 {
15720   if (modrm.mod != 3)
15721     {
15722       if (prefixes & PREFIX_REPZ)
15723         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15724       if (prefixes & PREFIX_REPNZ)
15725         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15726     }
15727
15728   OP_E (bytemode, sizeflag);
15729 }
15730
15731 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15732    "xrelease" for memory operand.  No check for LOCK prefix.   */
15733
15734 static void
15735 HLE_Fixup3 (int bytemode, int sizeflag)
15736 {
15737   if (modrm.mod != 3
15738       && last_repz_prefix > last_repnz_prefix
15739       && (prefixes & PREFIX_REPZ) != 0)
15740     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15741
15742   OP_E (bytemode, sizeflag);
15743 }
15744
15745 static void
15746 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15747 {
15748   USED_REX (REX_W);
15749   if (rex & REX_W)
15750     {
15751       /* Change cmpxchg8b to cmpxchg16b.  */
15752       char *p = mnemonicendp - 2;
15753       mnemonicendp = stpcpy (p, "16b");
15754       bytemode = o_mode;
15755     }
15756   else if ((prefixes & PREFIX_LOCK) != 0)
15757     {
15758       if (prefixes & PREFIX_REPZ)
15759         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15760       if (prefixes & PREFIX_REPNZ)
15761         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15762     }
15763
15764   OP_M (bytemode, sizeflag);
15765 }
15766
15767 static void
15768 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15769 {
15770   const char **names;
15771
15772   if (need_vex)
15773     {
15774       switch (vex.length)
15775         {
15776         case 128:
15777           names = names_xmm;
15778           break;
15779         case 256:
15780           names = names_ymm;
15781           break;
15782         default:
15783           abort ();
15784         }
15785     }
15786   else
15787     names = names_xmm;
15788   oappend (names[reg]);
15789 }
15790
15791 static void
15792 CRC32_Fixup (int bytemode, int sizeflag)
15793 {
15794   /* Add proper suffix to "crc32".  */
15795   char *p = mnemonicendp;
15796
15797   switch (bytemode)
15798     {
15799     case b_mode:
15800       if (intel_syntax)
15801         goto skip;
15802
15803       *p++ = 'b';
15804       break;
15805     case v_mode:
15806       if (intel_syntax)
15807         goto skip;
15808
15809       USED_REX (REX_W);
15810       if (rex & REX_W)
15811         *p++ = 'q';
15812       else
15813         {
15814           if (sizeflag & DFLAG)
15815             *p++ = 'l';
15816           else
15817             *p++ = 'w';
15818           used_prefixes |= (prefixes & PREFIX_DATA);
15819         }
15820       break;
15821     default:
15822       oappend (INTERNAL_DISASSEMBLER_ERROR);
15823       break;
15824     }
15825   mnemonicendp = p;
15826   *p = '\0';
15827
15828 skip:
15829   if (modrm.mod == 3)
15830     {
15831       int add;
15832
15833       /* Skip mod/rm byte.  */
15834       MODRM_CHECK;
15835       codep++;
15836
15837       USED_REX (REX_B);
15838       add = (rex & REX_B) ? 8 : 0;
15839       if (bytemode == b_mode)
15840         {
15841           USED_REX (0);
15842           if (rex)
15843             oappend (names8rex[modrm.rm + add]);
15844           else
15845             oappend (names8[modrm.rm + add]);
15846         }
15847       else
15848         {
15849           USED_REX (REX_W);
15850           if (rex & REX_W)
15851             oappend (names64[modrm.rm + add]);
15852           else if ((prefixes & PREFIX_DATA))
15853             oappend (names16[modrm.rm + add]);
15854           else
15855             oappend (names32[modrm.rm + add]);
15856         }
15857     }
15858   else
15859     OP_E (bytemode, sizeflag);
15860 }
15861
15862 static void
15863 FXSAVE_Fixup (int bytemode, int sizeflag)
15864 {
15865   /* Add proper suffix to "fxsave" and "fxrstor".  */
15866   USED_REX (REX_W);
15867   if (rex & REX_W)
15868     {
15869       char *p = mnemonicendp;
15870       *p++ = '6';
15871       *p++ = '4';
15872       *p = '\0';
15873       mnemonicendp = p;
15874     }
15875   OP_M (bytemode, sizeflag);
15876 }
15877
15878 static void
15879 PCMPESTR_Fixup (int bytemode, int sizeflag)
15880 {
15881   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15882   if (!intel_syntax)
15883     {
15884       char *p = mnemonicendp;
15885
15886       USED_REX (REX_W);
15887       if (rex & REX_W)
15888         *p++ = 'q';
15889       else if (sizeflag & SUFFIX_ALWAYS)
15890         *p++ = 'l';
15891
15892       *p = '\0';
15893       mnemonicendp = p;
15894     }
15895
15896   OP_EX (bytemode, sizeflag);
15897 }
15898
15899 /* Display the destination register operand for instructions with
15900    VEX. */
15901
15902 static void
15903 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15904 {
15905   int reg;
15906   const char **names;
15907
15908   if (!need_vex)
15909     abort ();
15910
15911   if (!need_vex_reg)
15912     return;
15913
15914   reg = vex.register_specifier;
15915   if (address_mode != mode_64bit)
15916     reg &= 7;
15917   else if (vex.evex && !vex.v)
15918     reg += 16;
15919
15920   if (bytemode == vex_scalar_mode)
15921     {
15922       oappend (names_xmm[reg]);
15923       return;
15924     }
15925
15926   switch (vex.length)
15927     {
15928     case 128:
15929       switch (bytemode)
15930         {
15931         case vex_mode:
15932         case vex128_mode:
15933         case vex_vsib_q_w_dq_mode:
15934         case vex_vsib_q_w_d_mode:
15935           names = names_xmm;
15936           break;
15937         case dq_mode:
15938           if (rex & REX_W)
15939             names = names64;
15940           else
15941             names = names32;
15942           break;
15943         case mask_bd_mode:
15944         case mask_mode:
15945           if (reg > 0x7)
15946             {
15947               oappend ("(bad)");
15948               return;
15949             }
15950           names = names_mask;
15951           break;
15952         default:
15953           abort ();
15954           return;
15955         }
15956       break;
15957     case 256:
15958       switch (bytemode)
15959         {
15960         case vex_mode:
15961         case vex256_mode:
15962           names = names_ymm;
15963           break;
15964         case vex_vsib_q_w_dq_mode:
15965         case vex_vsib_q_w_d_mode:
15966           names = vex.w ? names_ymm : names_xmm;
15967           break;
15968         case mask_bd_mode:
15969         case mask_mode:
15970           if (reg > 0x7)
15971             {
15972               oappend ("(bad)");
15973               return;
15974             }
15975           names = names_mask;
15976           break;
15977         default:
15978           /* See PR binutils/20893 for a reproducer.  */
15979           oappend ("(bad)");
15980           return;
15981         }
15982       break;
15983     case 512:
15984       names = names_zmm;
15985       break;
15986     default:
15987       abort ();
15988       break;
15989     }
15990   oappend (names[reg]);
15991 }
15992
15993 /* Get the VEX immediate byte without moving codep.  */
15994
15995 static unsigned char
15996 get_vex_imm8 (int sizeflag, int opnum)
15997 {
15998   int bytes_before_imm = 0;
15999
16000   if (modrm.mod != 3)
16001     {
16002       /* There are SIB/displacement bytes.  */
16003       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16004         {
16005           /* 32/64 bit address mode */
16006           int base = modrm.rm;
16007
16008           /* Check SIB byte.  */
16009           if (base == 4)
16010             {
16011               FETCH_DATA (the_info, codep + 1);
16012               base = *codep & 7;
16013               /* When decoding the third source, don't increase
16014                  bytes_before_imm as this has already been incremented
16015                  by one in OP_E_memory while decoding the second
16016                  source operand.  */
16017               if (opnum == 0)
16018                 bytes_before_imm++;
16019             }
16020
16021           /* Don't increase bytes_before_imm when decoding the third source,
16022              it has already been incremented by OP_E_memory while decoding
16023              the second source operand.  */
16024           if (opnum == 0)
16025             {
16026               switch (modrm.mod)
16027                 {
16028                   case 0:
16029                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16030                        SIB == 5, there is a 4 byte displacement.  */
16031                     if (base != 5)
16032                       /* No displacement. */
16033                       break;
16034                     /* Fall through.  */
16035                   case 2:
16036                     /* 4 byte displacement.  */
16037                     bytes_before_imm += 4;
16038                     break;
16039                   case 1:
16040                     /* 1 byte displacement.  */
16041                     bytes_before_imm++;
16042                     break;
16043                 }
16044             }
16045         }
16046       else
16047         {
16048           /* 16 bit address mode */
16049           /* Don't increase bytes_before_imm when decoding the third source,
16050              it has already been incremented by OP_E_memory while decoding
16051              the second source operand.  */
16052           if (opnum == 0)
16053             {
16054               switch (modrm.mod)
16055                 {
16056                 case 0:
16057                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16058                   if (modrm.rm != 6)
16059                     /* No displacement. */
16060                     break;
16061                   /* Fall through.  */
16062                 case 2:
16063                   /* 2 byte displacement.  */
16064                   bytes_before_imm += 2;
16065                   break;
16066                 case 1:
16067                   /* 1 byte displacement: when decoding the third source,
16068                      don't increase bytes_before_imm as this has already
16069                      been incremented by one in OP_E_memory while decoding
16070                      the second source operand.  */
16071                   if (opnum == 0)
16072                     bytes_before_imm++;
16073
16074                   break;
16075                 }
16076             }
16077         }
16078     }
16079
16080   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16081   return codep [bytes_before_imm];
16082 }
16083
16084 static void
16085 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16086 {
16087   const char **names;
16088
16089   if (reg == -1 && modrm.mod != 3)
16090     {
16091       OP_E_memory (bytemode, sizeflag);
16092       return;
16093     }
16094   else
16095     {
16096       if (reg == -1)
16097         {
16098           reg = modrm.rm;
16099           USED_REX (REX_B);
16100           if (rex & REX_B)
16101             reg += 8;
16102         }
16103       if (address_mode != mode_64bit)
16104         reg &= 7;
16105     }
16106
16107   switch (vex.length)
16108     {
16109     case 128:
16110       names = names_xmm;
16111       break;
16112     case 256:
16113       names = names_ymm;
16114       break;
16115     default:
16116       abort ();
16117     }
16118   oappend (names[reg]);
16119 }
16120
16121 static void
16122 OP_EX_VexImmW (int bytemode, int sizeflag)
16123 {
16124   int reg = -1;
16125   static unsigned char vex_imm8;
16126
16127   if (vex_w_done == 0)
16128     {
16129       vex_w_done = 1;
16130
16131       /* Skip mod/rm byte.  */
16132       MODRM_CHECK;
16133       codep++;
16134
16135       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16136
16137       if (vex.w)
16138           reg = vex_imm8 >> 4;
16139
16140       OP_EX_VexReg (bytemode, sizeflag, reg);
16141     }
16142   else if (vex_w_done == 1)
16143     {
16144       vex_w_done = 2;
16145
16146       if (!vex.w)
16147           reg = vex_imm8 >> 4;
16148
16149       OP_EX_VexReg (bytemode, sizeflag, reg);
16150     }
16151   else
16152     {
16153       /* Output the imm8 directly.  */
16154       scratchbuf[0] = '$';
16155       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16156       oappend_maybe_intel (scratchbuf);
16157       scratchbuf[0] = '\0';
16158       codep++;
16159     }
16160 }
16161
16162 static void
16163 OP_Vex_2src (int bytemode, int sizeflag)
16164 {
16165   if (modrm.mod == 3)
16166     {
16167       int reg = modrm.rm;
16168       USED_REX (REX_B);
16169       if (rex & REX_B)
16170         reg += 8;
16171       oappend (names_xmm[reg]);
16172     }
16173   else
16174     {
16175       if (intel_syntax
16176           && (bytemode == v_mode || bytemode == v_swap_mode))
16177         {
16178           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16179           used_prefixes |= (prefixes & PREFIX_DATA);
16180         }
16181       OP_E (bytemode, sizeflag);
16182     }
16183 }
16184
16185 static void
16186 OP_Vex_2src_1 (int bytemode, int sizeflag)
16187 {
16188   if (modrm.mod == 3)
16189     {
16190       /* Skip mod/rm byte.   */
16191       MODRM_CHECK;
16192       codep++;
16193     }
16194
16195   if (vex.w)
16196     {
16197       unsigned int reg = vex.register_specifier;
16198
16199       if (address_mode != mode_64bit)
16200         reg &= 7;
16201       oappend (names_xmm[reg]);
16202     }
16203   else
16204     OP_Vex_2src (bytemode, sizeflag);
16205 }
16206
16207 static void
16208 OP_Vex_2src_2 (int bytemode, int sizeflag)
16209 {
16210   if (vex.w)
16211     OP_Vex_2src (bytemode, sizeflag);
16212   else
16213     {
16214       unsigned int reg = vex.register_specifier;
16215
16216       if (address_mode != mode_64bit)
16217         reg &= 7;
16218       oappend (names_xmm[reg]);
16219     }
16220 }
16221
16222 static void
16223 OP_EX_VexW (int bytemode, int sizeflag)
16224 {
16225   int reg = -1;
16226
16227   if (!vex_w_done)
16228     {
16229       /* Skip mod/rm byte.  */
16230       MODRM_CHECK;
16231       codep++;
16232
16233       if (vex.w)
16234         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16235     }
16236   else
16237     {
16238       if (!vex.w)
16239         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16240     }
16241
16242   OP_EX_VexReg (bytemode, sizeflag, reg);
16243
16244   if (vex_w_done)
16245     codep++;
16246   vex_w_done = 1;
16247 }
16248
16249 static void
16250 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16251 {
16252   int reg;
16253   const char **names;
16254
16255   FETCH_DATA (the_info, codep + 1);
16256   reg = *codep++;
16257
16258   if (bytemode != x_mode)
16259     abort ();
16260
16261   reg >>= 4;
16262   if (address_mode != mode_64bit)
16263     reg &= 7;
16264
16265   switch (vex.length)
16266     {
16267     case 128:
16268       names = names_xmm;
16269       break;
16270     case 256:
16271       names = names_ymm;
16272       break;
16273     default:
16274       abort ();
16275     }
16276   oappend (names[reg]);
16277 }
16278
16279 static void
16280 OP_XMM_VexW (int bytemode, int sizeflag)
16281 {
16282   /* Turn off the REX.W bit since it is used for swapping operands
16283      now.  */
16284   rex &= ~REX_W;
16285   OP_XMM (bytemode, sizeflag);
16286 }
16287
16288 static void
16289 OP_EX_Vex (int bytemode, int sizeflag)
16290 {
16291   if (modrm.mod != 3)
16292     {
16293       if (vex.register_specifier != 0)
16294         BadOp ();
16295       need_vex_reg = 0;
16296     }
16297   OP_EX (bytemode, sizeflag);
16298 }
16299
16300 static void
16301 OP_XMM_Vex (int bytemode, int sizeflag)
16302 {
16303   if (modrm.mod != 3)
16304     {
16305       if (vex.register_specifier != 0)
16306         BadOp ();
16307       need_vex_reg = 0;
16308     }
16309   OP_XMM (bytemode, sizeflag);
16310 }
16311
16312 static struct op vex_cmp_op[] =
16313 {
16314   { STRING_COMMA_LEN ("eq") },
16315   { STRING_COMMA_LEN ("lt") },
16316   { STRING_COMMA_LEN ("le") },
16317   { STRING_COMMA_LEN ("unord") },
16318   { STRING_COMMA_LEN ("neq") },
16319   { STRING_COMMA_LEN ("nlt") },
16320   { STRING_COMMA_LEN ("nle") },
16321   { STRING_COMMA_LEN ("ord") },
16322   { STRING_COMMA_LEN ("eq_uq") },
16323   { STRING_COMMA_LEN ("nge") },
16324   { STRING_COMMA_LEN ("ngt") },
16325   { STRING_COMMA_LEN ("false") },
16326   { STRING_COMMA_LEN ("neq_oq") },
16327   { STRING_COMMA_LEN ("ge") },
16328   { STRING_COMMA_LEN ("gt") },
16329   { STRING_COMMA_LEN ("true") },
16330   { STRING_COMMA_LEN ("eq_os") },
16331   { STRING_COMMA_LEN ("lt_oq") },
16332   { STRING_COMMA_LEN ("le_oq") },
16333   { STRING_COMMA_LEN ("unord_s") },
16334   { STRING_COMMA_LEN ("neq_us") },
16335   { STRING_COMMA_LEN ("nlt_uq") },
16336   { STRING_COMMA_LEN ("nle_uq") },
16337   { STRING_COMMA_LEN ("ord_s") },
16338   { STRING_COMMA_LEN ("eq_us") },
16339   { STRING_COMMA_LEN ("nge_uq") },
16340   { STRING_COMMA_LEN ("ngt_uq") },
16341   { STRING_COMMA_LEN ("false_os") },
16342   { STRING_COMMA_LEN ("neq_os") },
16343   { STRING_COMMA_LEN ("ge_oq") },
16344   { STRING_COMMA_LEN ("gt_oq") },
16345   { STRING_COMMA_LEN ("true_us") },
16346 };
16347
16348 static void
16349 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16350 {
16351   unsigned int cmp_type;
16352
16353   FETCH_DATA (the_info, codep + 1);
16354   cmp_type = *codep++ & 0xff;
16355   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16356     {
16357       char suffix [3];
16358       char *p = mnemonicendp - 2;
16359       suffix[0] = p[0];
16360       suffix[1] = p[1];
16361       suffix[2] = '\0';
16362       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16363       mnemonicendp += vex_cmp_op[cmp_type].len;
16364     }
16365   else
16366     {
16367       /* We have a reserved extension byte.  Output it directly.  */
16368       scratchbuf[0] = '$';
16369       print_operand_value (scratchbuf + 1, 1, cmp_type);
16370       oappend_maybe_intel (scratchbuf);
16371       scratchbuf[0] = '\0';
16372     }
16373 }
16374
16375 static void
16376 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16377              int sizeflag ATTRIBUTE_UNUSED)
16378 {
16379   unsigned int cmp_type;
16380
16381   if (!vex.evex)
16382     abort ();
16383
16384   FETCH_DATA (the_info, codep + 1);
16385   cmp_type = *codep++ & 0xff;
16386   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16387      If it's the case, print suffix, otherwise - print the immediate.  */
16388   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16389       && cmp_type != 3
16390       && cmp_type != 7)
16391     {
16392       char suffix [3];
16393       char *p = mnemonicendp - 2;
16394
16395       /* vpcmp* can have both one- and two-lettered suffix.  */
16396       if (p[0] == 'p')
16397         {
16398           p++;
16399           suffix[0] = p[0];
16400           suffix[1] = '\0';
16401         }
16402       else
16403         {
16404           suffix[0] = p[0];
16405           suffix[1] = p[1];
16406           suffix[2] = '\0';
16407         }
16408
16409       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16410       mnemonicendp += simd_cmp_op[cmp_type].len;
16411     }
16412   else
16413     {
16414       /* We have a reserved extension byte.  Output it directly.  */
16415       scratchbuf[0] = '$';
16416       print_operand_value (scratchbuf + 1, 1, cmp_type);
16417       oappend_maybe_intel (scratchbuf);
16418       scratchbuf[0] = '\0';
16419     }
16420 }
16421
16422 static const struct op xop_cmp_op[] =
16423 {
16424   { STRING_COMMA_LEN ("lt") },
16425   { STRING_COMMA_LEN ("le") },
16426   { STRING_COMMA_LEN ("gt") },
16427   { STRING_COMMA_LEN ("ge") },
16428   { STRING_COMMA_LEN ("eq") },
16429   { STRING_COMMA_LEN ("neq") },
16430   { STRING_COMMA_LEN ("false") },
16431   { STRING_COMMA_LEN ("true") }
16432 };
16433
16434 static void
16435 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16436              int sizeflag ATTRIBUTE_UNUSED)
16437 {
16438   unsigned int cmp_type;
16439
16440   FETCH_DATA (the_info, codep + 1);
16441   cmp_type = *codep++ & 0xff;
16442   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16443     {
16444       char suffix[3];
16445       char *p = mnemonicendp - 2;
16446
16447       /* vpcom* can have both one- and two-lettered suffix.  */
16448       if (p[0] == 'm')
16449         {
16450           p++;
16451           suffix[0] = p[0];
16452           suffix[1] = '\0';
16453         }
16454       else
16455         {
16456           suffix[0] = p[0];
16457           suffix[1] = p[1];
16458           suffix[2] = '\0';
16459         }
16460
16461       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16462       mnemonicendp += xop_cmp_op[cmp_type].len;
16463     }
16464   else
16465     {
16466       /* We have a reserved extension byte.  Output it directly.  */
16467       scratchbuf[0] = '$';
16468       print_operand_value (scratchbuf + 1, 1, cmp_type);
16469       oappend_maybe_intel (scratchbuf);
16470       scratchbuf[0] = '\0';
16471     }
16472 }
16473
16474 static const struct op pclmul_op[] =
16475 {
16476   { STRING_COMMA_LEN ("lql") },
16477   { STRING_COMMA_LEN ("hql") },
16478   { STRING_COMMA_LEN ("lqh") },
16479   { STRING_COMMA_LEN ("hqh") }
16480 };
16481
16482 static void
16483 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16484               int sizeflag ATTRIBUTE_UNUSED)
16485 {
16486   unsigned int pclmul_type;
16487
16488   FETCH_DATA (the_info, codep + 1);
16489   pclmul_type = *codep++ & 0xff;
16490   switch (pclmul_type)
16491     {
16492     case 0x10:
16493       pclmul_type = 2;
16494       break;
16495     case 0x11:
16496       pclmul_type = 3;
16497       break;
16498     default:
16499       break;
16500     }
16501   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16502     {
16503       char suffix [4];
16504       char *p = mnemonicendp - 3;
16505       suffix[0] = p[0];
16506       suffix[1] = p[1];
16507       suffix[2] = p[2];
16508       suffix[3] = '\0';
16509       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16510       mnemonicendp += pclmul_op[pclmul_type].len;
16511     }
16512   else
16513     {
16514       /* We have a reserved extension byte.  Output it directly.  */
16515       scratchbuf[0] = '$';
16516       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16517       oappend_maybe_intel (scratchbuf);
16518       scratchbuf[0] = '\0';
16519     }
16520 }
16521
16522 static void
16523 MOVBE_Fixup (int bytemode, int sizeflag)
16524 {
16525   /* Add proper suffix to "movbe".  */
16526   char *p = mnemonicendp;
16527
16528   switch (bytemode)
16529     {
16530     case v_mode:
16531       if (intel_syntax)
16532         goto skip;
16533
16534       USED_REX (REX_W);
16535       if (sizeflag & SUFFIX_ALWAYS)
16536         {
16537           if (rex & REX_W)
16538             *p++ = 'q';
16539           else
16540             {
16541               if (sizeflag & DFLAG)
16542                 *p++ = 'l';
16543               else
16544                 *p++ = 'w';
16545               used_prefixes |= (prefixes & PREFIX_DATA);
16546             }
16547         }
16548       break;
16549     default:
16550       oappend (INTERNAL_DISASSEMBLER_ERROR);
16551       break;
16552     }
16553   mnemonicendp = p;
16554   *p = '\0';
16555
16556 skip:
16557   OP_M (bytemode, sizeflag);
16558 }
16559
16560 static void
16561 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16562 {
16563   int reg;
16564   const char **names;
16565
16566   /* Skip mod/rm byte.  */
16567   MODRM_CHECK;
16568   codep++;
16569
16570   if (rex & REX_W)
16571     names = names64;
16572   else
16573     names = names32;
16574
16575   reg = modrm.rm;
16576   USED_REX (REX_B);
16577   if (rex & REX_B)
16578     reg += 8;
16579
16580   oappend (names[reg]);
16581 }
16582
16583 static void
16584 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16585 {
16586   const char **names;
16587   unsigned int reg = vex.register_specifier;
16588
16589   if (rex & REX_W)
16590     names = names64;
16591   else
16592     names = names32;
16593
16594   if (address_mode != mode_64bit)
16595     reg &= 7;
16596   oappend (names[reg]);
16597 }
16598
16599 static void
16600 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16601 {
16602   if (!vex.evex
16603       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16604     abort ();
16605
16606   USED_REX (REX_R);
16607   if ((rex & REX_R) != 0 || !vex.r)
16608     {
16609       BadOp ();
16610       return;
16611     }
16612
16613   oappend (names_mask [modrm.reg]);
16614 }
16615
16616 static void
16617 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16618 {
16619   if (!vex.evex
16620       || (bytemode != evex_rounding_mode
16621           && bytemode != evex_rounding_64_mode
16622           && bytemode != evex_sae_mode))
16623     abort ();
16624   if (modrm.mod == 3 && vex.b)
16625     switch (bytemode)
16626       {
16627       case evex_rounding_64_mode:
16628         if (address_mode != mode_64bit)
16629           {
16630             oappend ("(bad)");
16631             break;
16632           }
16633         /* Fall through.  */
16634       case evex_rounding_mode:
16635         oappend (names_rounding[vex.ll]);
16636         break;
16637       case evex_sae_mode:
16638         oappend ("{sae}");
16639         break;
16640       default:
16641         break;
16642       }
16643 }