opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define Edqb { OP_E, dqb_mode }
 237 #define Edqd { OP_E, dqd_mode }
 238 #define Eq { OP_E, q_mode }
 239 #define indirEv { OP_indirE, stack_v_mode }
 240 #define indirEp { OP_indirE, f_mode }
 241 #define stackEv { OP_E, stack_v_mode }
 242 #define Em { OP_E, m_mode }
 243 #define Ew { OP_E, w_mode }
 244 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 245 #define Ma { OP_M, a_mode }
 246 #define Mb { OP_M, b_mode }
 247 #define Md { OP_M, d_mode }
 248 #define Mo { OP_M, o_mode }
 249 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 250 #define Mq { OP_M, q_mode }
 251 #define Mx { OP_M, x_mode }
 252 #define Mxmm { OP_M, xmm_mode }
 253 #define Gb { OP_G, b_mode }
 254 #define Gbnd { OP_G, bnd_mode }
 255 #define Gv { OP_G, v_mode }
 256 #define Gd { OP_G, d_mode }
 257 #define Gdq { OP_G, dq_mode }
 258 #define Gm { OP_G, m_mode }
 259 #define Gw { OP_G, w_mode }
 260 #define Rd { OP_R, d_mode }
 261 #define Rdq { OP_R, dq_mode }
 262 #define Rm { OP_R, m_mode }
 263 #define Ib { OP_I, b_mode }
 264 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 266 #define Iv { OP_I, v_mode }
 267 #define sIv { OP_sI, v_mode }
 268 #define Iq { OP_I, q_mode }
 269 #define Iv64 { OP_I64, v_mode }
 270 #define Iw { OP_I, w_mode }
 271 #define I1 { OP_I, const_1_mode }
 272 #define Jb { OP_J, b_mode }
 273 #define Jv { OP_J, v_mode }
 274 #define Cm { OP_C, m_mode }
 275 #define Dm { OP_D, m_mode }
 276 #define Td { OP_T, d_mode }
 277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 278
 279 #define RMeAX { OP_REG, eAX_reg }
 280 #define RMeBX { OP_REG, eBX_reg }
 281 #define RMeCX { OP_REG, eCX_reg }
 282 #define RMeDX { OP_REG, eDX_reg }
 283 #define RMeSP { OP_REG, eSP_reg }
 284 #define RMeBP { OP_REG, eBP_reg }
 285 #define RMeSI { OP_REG, eSI_reg }
 286 #define RMeDI { OP_REG, eDI_reg }
 287 #define RMrAX { OP_REG, rAX_reg }
 288 #define RMrBX { OP_REG, rBX_reg }
 289 #define RMrCX { OP_REG, rCX_reg }
 290 #define RMrDX { OP_REG, rDX_reg }
 291 #define RMrSP { OP_REG, rSP_reg }
 292 #define RMrBP { OP_REG, rBP_reg }
 293 #define RMrSI { OP_REG, rSI_reg }
 294 #define RMrDI { OP_REG, rDI_reg }
 295 #define RMAL { OP_REG, al_reg }
 296 #define RMCL { OP_REG, cl_reg }
 297 #define RMDL { OP_REG, dl_reg }
 298 #define RMBL { OP_REG, bl_reg }
 299 #define RMAH { OP_REG, ah_reg }
 300 #define RMCH { OP_REG, ch_reg }
 301 #define RMDH { OP_REG, dh_reg }
 302 #define RMBH { OP_REG, bh_reg }
 303 #define RMAX { OP_REG, ax_reg }
 304 #define RMDX { OP_REG, dx_reg }
 305
 306 #define eAX { OP_IMREG, eAX_reg }
 307 #define eBX { OP_IMREG, eBX_reg }
 308 #define eCX { OP_IMREG, eCX_reg }
 309 #define eDX { OP_IMREG, eDX_reg }
 310 #define eSP { OP_IMREG, eSP_reg }
 311 #define eBP { OP_IMREG, eBP_reg }
 312 #define eSI { OP_IMREG, eSI_reg }
 313 #define eDI { OP_IMREG, eDI_reg }
 314 #define AL { OP_IMREG, al_reg }
 315 #define CL { OP_IMREG, cl_reg }
 316 #define DL { OP_IMREG, dl_reg }
 317 #define BL { OP_IMREG, bl_reg }
 318 #define AH { OP_IMREG, ah_reg }
 319 #define CH { OP_IMREG, ch_reg }
 320 #define DH { OP_IMREG, dh_reg }
 321 #define BH { OP_IMREG, bh_reg }
 322 #define AX { OP_IMREG, ax_reg }
 323 #define DX { OP_IMREG, dx_reg }
 324 #define zAX { OP_IMREG, z_mode_ax_reg }
 325 #define indirDX { OP_IMREG, indir_dx_reg }
 326
 327 #define Sw { OP_SEG, w_mode }
 328 #define Sv { OP_SEG, v_mode }
 329 #define Ap { OP_DIR, 0 }
 330 #define Ob { OP_OFF64, b_mode }
 331 #define Ov { OP_OFF64, v_mode }
 332 #define Xb { OP_DSreg, eSI_reg }
 333 #define Xv { OP_DSreg, eSI_reg }
 334 #define Xz { OP_DSreg, eSI_reg }
 335 #define Yb { OP_ESreg, eDI_reg }
 336 #define Yv { OP_ESreg, eDI_reg }
 337 #define DSBX { OP_DSreg, eBX_reg }
 338
 339 #define es { OP_REG, es_reg }
 340 #define ss { OP_REG, ss_reg }
 341 #define cs { OP_REG, cs_reg }
 342 #define ds { OP_REG, ds_reg }
 343 #define fs { OP_REG, fs_reg }
 344 #define gs { OP_REG, gs_reg }
 345
 346 #define MX { OP_MMX, 0 }
 347 #define XM { OP_XMM, 0 }
 348 #define XMScalar { OP_XMM, scalar_mode }
 349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 350 #define XMM { OP_XMM, xmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXw { OP_EX, w_mode }
 357 #define EXd { OP_EX, d_mode }
 358 #define EXdScalar { OP_EX, d_scalar_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 361 #define EXq { OP_EX, q_mode }
 362 #define EXqScalar { OP_EX, q_scalar_mode }
 363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 364 #define EXqS { OP_EX, q_swap_mode }
 365 #define EXx { OP_EX, x_mode }
 366 #define EXxS { OP_EX, x_swap_mode }
 367 #define EXxmm { OP_EX, xmm_mode }
 368 #define EXymm { OP_EX, ymm_mode }
 369 #define EXxmmq { OP_EX, xmmq_mode }
 370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 373 #define EXxmm_md { OP_EX, xmm_md_mode }
 374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 376 #define EXxmmdw { OP_EX, xmmdw_mode }
 377 #define EXxmmqd { OP_EX, xmmqd_mode }
 378 #define EXymmq { OP_EX, ymmq_mode }
 379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define CMP { CMP_Fixup, 0 }
 389 #define XMM0 { XMM_Fixup, 0 }
 390 #define FXSAVE { FXSAVE_Fixup, 0 }
 391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 397 #define Vex128 { OP_VEX, vex128_mode }
 398 #define Vex256 { OP_VEX, vex256_mode }
 399 #define VexGdq { OP_VEX, dq_mode }
 400 #define VexI4 { VEXI4_Fixup, 0}
 401 #define EXdVex { OP_EX_Vex, d_mode }
 402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 404 #define EXqVex { OP_EX_Vex, q_mode }
 405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 407 #define EXVexW { OP_EX_VexW, x_mode }
 408 #define EXdVexW { OP_EX_VexW, d_mode }
 409 #define EXqVexW { OP_EX_VexW, q_mode }
 410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 411 #define XMVex { OP_XMM_Vex, 0 }
 412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 413 #define XMVexW { OP_XMM_VexW, 0 }
 414 #define XMVexI4 { OP_REG_VexI4, x_mode }
 415 #define PCLMUL { PCLMUL_Fixup, 0 }
 416 #define VZERO { VZERO_Fixup, 0 }
 417 #define VCMP { VCMP_Fixup, 0 }
 418 #define VPCMP { VPCMP_Fixup, 0 }
 419
 420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 422
 423 #define XMask { OP_Mask, mask_mode }
 424 #define MaskG { OP_G, mask_mode }
 425 #define MaskE { OP_E, mask_mode }
 426 #define MaskR { OP_R, mask_mode }
 427 #define MaskVex { OP_VEX, mask_mode }
 428
 429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 562   vex_vsib_d_w_d_mode,
 563   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 564   vex_vsib_q_w_dq_mode,
 565   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 566   vex_vsib_q_w_d_mode,
 567
 568   /* scalar, ignore vector length.  */
 569   scalar_mode,
 570   /* like d_mode, ignore vector length.  */
 571   d_scalar_mode,
 572   /* like d_swap_mode, ignore vector length.  */
 573   d_scalar_swap_mode,
 574   /* like q_mode, ignore vector length.  */
 575   q_scalar_mode,
 576   /* like q_swap_mode, ignore vector length.  */
 577   q_scalar_swap_mode,
 578   /* like vex_mode, ignore vector length.  */
 579   vex_scalar_mode,
 580   /* like vex_w_dq_mode, ignore vector length.  */
 581   vex_scalar_w_dq_mode,
 582
 583   /* Static rounding.  */
 584   evex_rounding_mode,
 585   /* Supress all exceptions.  */
 586   evex_sae_mode,
 587
 588   /* Mask register operand.  */
 589   mask_mode,
 590
 591   es_reg,
 592   cs_reg,
 593   ss_reg,
 594   ds_reg,
 595   fs_reg,
 596   gs_reg,
 597
 598   eAX_reg,
 599   eCX_reg,
 600   eDX_reg,
 601   eBX_reg,
 602   eSP_reg,
 603   eBP_reg,
 604   eSI_reg,
 605   eDI_reg,
 606
 607   al_reg,
 608   cl_reg,
 609   dl_reg,
 610   bl_reg,
 611   ah_reg,
 612   ch_reg,
 613   dh_reg,
 614   bh_reg,
 615
 616   ax_reg,
 617   cx_reg,
 618   dx_reg,
 619   bx_reg,
 620   sp_reg,
 621   bp_reg,
 622   si_reg,
 623   di_reg,
 624
 625   rAX_reg,
 626   rCX_reg,
 627   rDX_reg,
 628   rBX_reg,
 629   rSP_reg,
 630   rBP_reg,
 631   rSI_reg,
 632   rDI_reg,
 633
 634   z_mode_ax_reg,
 635   indir_dx_reg
 636 };
 637
 638 enum
 639 {
 640   FLOATCODE = 1,
 641   USE_REG_TABLE,
 642   USE_MOD_TABLE,
 643   USE_RM_TABLE,
 644   USE_PREFIX_TABLE,
 645   USE_X86_64_TABLE,
 646   USE_3BYTE_TABLE,
 647   USE_XOP_8F_TABLE,
 648   USE_VEX_C4_TABLE,
 649   USE_VEX_C5_TABLE,
 650   USE_VEX_LEN_TABLE,
 651   USE_VEX_W_TABLE,
 652   USE_EVEX_TABLE
 653 };
 654
 655 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 656
 657 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 658 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 659 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 660 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 661 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 662 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 663 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 664 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 665 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 666 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 667 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 668 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 669 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 670
 671 enum
 672 {
 673   REG_80 = 0,
 674   REG_81,
 675   REG_82,
 676   REG_8F,
 677   REG_C0,
 678   REG_C1,
 679   REG_C6,
 680   REG_C7,
 681   REG_D0,
 682   REG_D1,
 683   REG_D2,
 684   REG_D3,
 685   REG_F6,
 686   REG_F7,
 687   REG_FE,
 688   REG_FF,
 689   REG_0F00,
 690   REG_0F01,
 691   REG_0F0D,
 692   REG_0F18,
 693   REG_0F71,
 694   REG_0F72,
 695   REG_0F73,
 696   REG_0FA6,
 697   REG_0FA7,
 698   REG_0FAE,
 699   REG_0FBA,
 700   REG_0FC7,
 701   REG_VEX_0F71,
 702   REG_VEX_0F72,
 703   REG_VEX_0F73,
 704   REG_VEX_0FAE,
 705   REG_VEX_0F38F3,
 706   REG_XOP_LWPCB,
 707   REG_XOP_LWP,
 708   REG_XOP_TBM_01,
 709   REG_XOP_TBM_02,
 710
 711   REG_EVEX_0F72,
 712   REG_EVEX_0F73,
 713   REG_EVEX_0F38C6,
 714   REG_EVEX_0F38C7
 715 };
 716
 717 enum
 718 {
 719   MOD_8D = 0,
 720   MOD_C6_REG_7,
 721   MOD_C7_REG_7,
 722   MOD_FF_REG_3,
 723   MOD_FF_REG_5,
 724   MOD_0F01_REG_0,
 725   MOD_0F01_REG_1,
 726   MOD_0F01_REG_2,
 727   MOD_0F01_REG_3,
 728   MOD_0F01_REG_7,
 729   MOD_0F12_PREFIX_0,
 730   MOD_0F13,
 731   MOD_0F16_PREFIX_0,
 732   MOD_0F17,
 733   MOD_0F18_REG_0,
 734   MOD_0F18_REG_1,
 735   MOD_0F18_REG_2,
 736   MOD_0F18_REG_3,
 737   MOD_0F18_REG_4,
 738   MOD_0F18_REG_5,
 739   MOD_0F18_REG_6,
 740   MOD_0F18_REG_7,
 741   MOD_0F1A_PREFIX_0,
 742   MOD_0F1B_PREFIX_0,
 743   MOD_0F1B_PREFIX_1,
 744   MOD_0F20,
 745   MOD_0F21,
 746   MOD_0F22,
 747   MOD_0F23,
 748   MOD_0F24,
 749   MOD_0F26,
 750   MOD_0F2B_PREFIX_0,
 751   MOD_0F2B_PREFIX_1,
 752   MOD_0F2B_PREFIX_2,
 753   MOD_0F2B_PREFIX_3,
 754   MOD_0F51,
 755   MOD_0F71_REG_2,
 756   MOD_0F71_REG_4,
 757   MOD_0F71_REG_6,
 758   MOD_0F72_REG_2,
 759   MOD_0F72_REG_4,
 760   MOD_0F72_REG_6,
 761   MOD_0F73_REG_2,
 762   MOD_0F73_REG_3,
 763   MOD_0F73_REG_6,
 764   MOD_0F73_REG_7,
 765   MOD_0FAE_REG_0,
 766   MOD_0FAE_REG_1,
 767   MOD_0FAE_REG_2,
 768   MOD_0FAE_REG_3,
 769   MOD_0FAE_REG_4,
 770   MOD_0FAE_REG_5,
 771   MOD_0FAE_REG_6,
 772   MOD_0FAE_REG_7,
 773   MOD_0FB2,
 774   MOD_0FB4,
 775   MOD_0FB5,
 776   MOD_0FC7_REG_3,
 777   MOD_0FC7_REG_4,
 778   MOD_0FC7_REG_5,
 779   MOD_0FC7_REG_6,
 780   MOD_0FC7_REG_7,
 781   MOD_0FD7,
 782   MOD_0FE7_PREFIX_2,
 783   MOD_0FF0_PREFIX_3,
 784   MOD_0F382A_PREFIX_2,
 785   MOD_62_32BIT,
 786   MOD_C4_32BIT,
 787   MOD_C5_32BIT,
 788   MOD_VEX_0F12_PREFIX_0,
 789   MOD_VEX_0F13,
 790   MOD_VEX_0F16_PREFIX_0,
 791   MOD_VEX_0F17,
 792   MOD_VEX_0F2B,
 793   MOD_VEX_0F50,
 794   MOD_VEX_0F71_REG_2,
 795   MOD_VEX_0F71_REG_4,
 796   MOD_VEX_0F71_REG_6,
 797   MOD_VEX_0F72_REG_2,
 798   MOD_VEX_0F72_REG_4,
 799   MOD_VEX_0F72_REG_6,
 800   MOD_VEX_0F73_REG_2,
 801   MOD_VEX_0F73_REG_3,
 802   MOD_VEX_0F73_REG_6,
 803   MOD_VEX_0F73_REG_7,
 804   MOD_VEX_0FAE_REG_2,
 805   MOD_VEX_0FAE_REG_3,
 806   MOD_VEX_0FD7_PREFIX_2,
 807   MOD_VEX_0FE7_PREFIX_2,
 808   MOD_VEX_0FF0_PREFIX_3,
 809   MOD_VEX_0F381A_PREFIX_2,
 810   MOD_VEX_0F382A_PREFIX_2,
 811   MOD_VEX_0F382C_PREFIX_2,
 812   MOD_VEX_0F382D_PREFIX_2,
 813   MOD_VEX_0F382E_PREFIX_2,
 814   MOD_VEX_0F382F_PREFIX_2,
 815   MOD_VEX_0F385A_PREFIX_2,
 816   MOD_VEX_0F388C_PREFIX_2,
 817   MOD_VEX_0F388E_PREFIX_2,
 818
 819   MOD_EVEX_0F10_PREFIX_1,
 820   MOD_EVEX_0F10_PREFIX_3,
 821   MOD_EVEX_0F11_PREFIX_1,
 822   MOD_EVEX_0F11_PREFIX_3,
 823   MOD_EVEX_0F12_PREFIX_0,
 824   MOD_EVEX_0F16_PREFIX_0,
 825   MOD_EVEX_0F38C6_REG_1,
 826   MOD_EVEX_0F38C6_REG_2,
 827   MOD_EVEX_0F38C6_REG_5,
 828   MOD_EVEX_0F38C6_REG_6,
 829   MOD_EVEX_0F38C7_REG_1,
 830   MOD_EVEX_0F38C7_REG_2,
 831   MOD_EVEX_0F38C7_REG_5,
 832   MOD_EVEX_0F38C7_REG_6
 833 };
 834
 835 enum
 836 {
 837   RM_C6_REG_7 = 0,
 838   RM_C7_REG_7,
 839   RM_0F01_REG_0,
 840   RM_0F01_REG_1,
 841   RM_0F01_REG_2,
 842   RM_0F01_REG_3,
 843   RM_0F01_REG_7,
 844   RM_0FAE_REG_5,
 845   RM_0FAE_REG_6,
 846   RM_0FAE_REG_7
 847 };
 848
 849 enum
 850 {
 851   PREFIX_90 = 0,
 852   PREFIX_0F10,
 853   PREFIX_0F11,
 854   PREFIX_0F12,
 855   PREFIX_0F16,
 856   PREFIX_0F1A,
 857   PREFIX_0F1B,
 858   PREFIX_0F2A,
 859   PREFIX_0F2B,
 860   PREFIX_0F2C,
 861   PREFIX_0F2D,
 862   PREFIX_0F2E,
 863   PREFIX_0F2F,
 864   PREFIX_0F51,
 865   PREFIX_0F52,
 866   PREFIX_0F53,
 867   PREFIX_0F58,
 868   PREFIX_0F59,
 869   PREFIX_0F5A,
 870   PREFIX_0F5B,
 871   PREFIX_0F5C,
 872   PREFIX_0F5D,
 873   PREFIX_0F5E,
 874   PREFIX_0F5F,
 875   PREFIX_0F60,
 876   PREFIX_0F61,
 877   PREFIX_0F62,
 878   PREFIX_0F6C,
 879   PREFIX_0F6D,
 880   PREFIX_0F6F,
 881   PREFIX_0F70,
 882   PREFIX_0F73_REG_3,
 883   PREFIX_0F73_REG_7,
 884   PREFIX_0F78,
 885   PREFIX_0F79,
 886   PREFIX_0F7C,
 887   PREFIX_0F7D,
 888   PREFIX_0F7E,
 889   PREFIX_0F7F,
 890   PREFIX_0FAE_REG_0,
 891   PREFIX_0FAE_REG_1,
 892   PREFIX_0FAE_REG_2,
 893   PREFIX_0FAE_REG_3,
 894   PREFIX_0FAE_REG_7,
 895   PREFIX_0FB8,
 896   PREFIX_0FBC,
 897   PREFIX_0FBD,
 898   PREFIX_0FC2,
 899   PREFIX_0FC3,
 900   PREFIX_0FC7_REG_6,
 901   PREFIX_0FD0,
 902   PREFIX_0FD6,
 903   PREFIX_0FE6,
 904   PREFIX_0FE7,
 905   PREFIX_0FF0,
 906   PREFIX_0FF7,
 907   PREFIX_0F3810,
 908   PREFIX_0F3814,
 909   PREFIX_0F3815,
 910   PREFIX_0F3817,
 911   PREFIX_0F3820,
 912   PREFIX_0F3821,
 913   PREFIX_0F3822,
 914   PREFIX_0F3823,
 915   PREFIX_0F3824,
 916   PREFIX_0F3825,
 917   PREFIX_0F3828,
 918   PREFIX_0F3829,
 919   PREFIX_0F382A,
 920   PREFIX_0F382B,
 921   PREFIX_0F3830,
 922   PREFIX_0F3831,
 923   PREFIX_0F3832,
 924   PREFIX_0F3833,
 925   PREFIX_0F3834,
 926   PREFIX_0F3835,
 927   PREFIX_0F3837,
 928   PREFIX_0F3838,
 929   PREFIX_0F3839,
 930   PREFIX_0F383A,
 931   PREFIX_0F383B,
 932   PREFIX_0F383C,
 933   PREFIX_0F383D,
 934   PREFIX_0F383E,
 935   PREFIX_0F383F,
 936   PREFIX_0F3840,
 937   PREFIX_0F3841,
 938   PREFIX_0F3880,
 939   PREFIX_0F3881,
 940   PREFIX_0F3882,
 941   PREFIX_0F38C8,
 942   PREFIX_0F38C9,
 943   PREFIX_0F38CA,
 944   PREFIX_0F38CB,
 945   PREFIX_0F38CC,
 946   PREFIX_0F38CD,
 947   PREFIX_0F38DB,
 948   PREFIX_0F38DC,
 949   PREFIX_0F38DD,
 950   PREFIX_0F38DE,
 951   PREFIX_0F38DF,
 952   PREFIX_0F38F0,
 953   PREFIX_0F38F1,
 954   PREFIX_0F38F6,
 955   PREFIX_0F3A08,
 956   PREFIX_0F3A09,
 957   PREFIX_0F3A0A,
 958   PREFIX_0F3A0B,
 959   PREFIX_0F3A0C,
 960   PREFIX_0F3A0D,
 961   PREFIX_0F3A0E,
 962   PREFIX_0F3A14,
 963   PREFIX_0F3A15,
 964   PREFIX_0F3A16,
 965   PREFIX_0F3A17,
 966   PREFIX_0F3A20,
 967   PREFIX_0F3A21,
 968   PREFIX_0F3A22,
 969   PREFIX_0F3A40,
 970   PREFIX_0F3A41,
 971   PREFIX_0F3A42,
 972   PREFIX_0F3A44,
 973   PREFIX_0F3A60,
 974   PREFIX_0F3A61,
 975   PREFIX_0F3A62,
 976   PREFIX_0F3A63,
 977   PREFIX_0F3ACC,
 978   PREFIX_0F3ADF,
 979   PREFIX_VEX_0F10,
 980   PREFIX_VEX_0F11,
 981   PREFIX_VEX_0F12,
 982   PREFIX_VEX_0F16,
 983   PREFIX_VEX_0F2A,
 984   PREFIX_VEX_0F2C,
 985   PREFIX_VEX_0F2D,
 986   PREFIX_VEX_0F2E,
 987   PREFIX_VEX_0F2F,
 988   PREFIX_VEX_0F41,
 989   PREFIX_VEX_0F42,
 990   PREFIX_VEX_0F44,
 991   PREFIX_VEX_0F45,
 992   PREFIX_VEX_0F46,
 993   PREFIX_VEX_0F47,
 994   PREFIX_VEX_0F4B,
 995   PREFIX_VEX_0F51,
 996   PREFIX_VEX_0F52,
 997   PREFIX_VEX_0F53,
 998   PREFIX_VEX_0F58,
 999   PREFIX_VEX_0F59,
1000   PREFIX_VEX_0F5A,
1001   PREFIX_VEX_0F5B,
1002   PREFIX_VEX_0F5C,
1003   PREFIX_VEX_0F5D,
1004   PREFIX_VEX_0F5E,
1005   PREFIX_VEX_0F5F,
1006   PREFIX_VEX_0F60,
1007   PREFIX_VEX_0F61,
1008   PREFIX_VEX_0F62,
1009   PREFIX_VEX_0F63,
1010   PREFIX_VEX_0F64,
1011   PREFIX_VEX_0F65,
1012   PREFIX_VEX_0F66,
1013   PREFIX_VEX_0F67,
1014   PREFIX_VEX_0F68,
1015   PREFIX_VEX_0F69,
1016   PREFIX_VEX_0F6A,
1017   PREFIX_VEX_0F6B,
1018   PREFIX_VEX_0F6C,
1019   PREFIX_VEX_0F6D,
1020   PREFIX_VEX_0F6E,
1021   PREFIX_VEX_0F6F,
1022   PREFIX_VEX_0F70,
1023   PREFIX_VEX_0F71_REG_2,
1024   PREFIX_VEX_0F71_REG_4,
1025   PREFIX_VEX_0F71_REG_6,
1026   PREFIX_VEX_0F72_REG_2,
1027   PREFIX_VEX_0F72_REG_4,
1028   PREFIX_VEX_0F72_REG_6,
1029   PREFIX_VEX_0F73_REG_2,
1030   PREFIX_VEX_0F73_REG_3,
1031   PREFIX_VEX_0F73_REG_6,
1032   PREFIX_VEX_0F73_REG_7,
1033   PREFIX_VEX_0F74,
1034   PREFIX_VEX_0F75,
1035   PREFIX_VEX_0F76,
1036   PREFIX_VEX_0F77,
1037   PREFIX_VEX_0F7C,
1038   PREFIX_VEX_0F7D,
1039   PREFIX_VEX_0F7E,
1040   PREFIX_VEX_0F7F,
1041   PREFIX_VEX_0F90,
1042   PREFIX_VEX_0F91,
1043   PREFIX_VEX_0F92,
1044   PREFIX_VEX_0F93,
1045   PREFIX_VEX_0F98,
1046   PREFIX_VEX_0FC2,
1047   PREFIX_VEX_0FC4,
1048   PREFIX_VEX_0FC5,
1049   PREFIX_VEX_0FD0,
1050   PREFIX_VEX_0FD1,
1051   PREFIX_VEX_0FD2,
1052   PREFIX_VEX_0FD3,
1053   PREFIX_VEX_0FD4,
1054   PREFIX_VEX_0FD5,
1055   PREFIX_VEX_0FD6,
1056   PREFIX_VEX_0FD7,
1057   PREFIX_VEX_0FD8,
1058   PREFIX_VEX_0FD9,
1059   PREFIX_VEX_0FDA,
1060   PREFIX_VEX_0FDB,
1061   PREFIX_VEX_0FDC,
1062   PREFIX_VEX_0FDD,
1063   PREFIX_VEX_0FDE,
1064   PREFIX_VEX_0FDF,
1065   PREFIX_VEX_0FE0,
1066   PREFIX_VEX_0FE1,
1067   PREFIX_VEX_0FE2,
1068   PREFIX_VEX_0FE3,
1069   PREFIX_VEX_0FE4,
1070   PREFIX_VEX_0FE5,
1071   PREFIX_VEX_0FE6,
1072   PREFIX_VEX_0FE7,
1073   PREFIX_VEX_0FE8,
1074   PREFIX_VEX_0FE9,
1075   PREFIX_VEX_0FEA,
1076   PREFIX_VEX_0FEB,
1077   PREFIX_VEX_0FEC,
1078   PREFIX_VEX_0FED,
1079   PREFIX_VEX_0FEE,
1080   PREFIX_VEX_0FEF,
1081   PREFIX_VEX_0FF0,
1082   PREFIX_VEX_0FF1,
1083   PREFIX_VEX_0FF2,
1084   PREFIX_VEX_0FF3,
1085   PREFIX_VEX_0FF4,
1086   PREFIX_VEX_0FF5,
1087   PREFIX_VEX_0FF6,
1088   PREFIX_VEX_0FF7,
1089   PREFIX_VEX_0FF8,
1090   PREFIX_VEX_0FF9,
1091   PREFIX_VEX_0FFA,
1092   PREFIX_VEX_0FFB,
1093   PREFIX_VEX_0FFC,
1094   PREFIX_VEX_0FFD,
1095   PREFIX_VEX_0FFE,
1096   PREFIX_VEX_0F3800,
1097   PREFIX_VEX_0F3801,
1098   PREFIX_VEX_0F3802,
1099   PREFIX_VEX_0F3803,
1100   PREFIX_VEX_0F3804,
1101   PREFIX_VEX_0F3805,
1102   PREFIX_VEX_0F3806,
1103   PREFIX_VEX_0F3807,
1104   PREFIX_VEX_0F3808,
1105   PREFIX_VEX_0F3809,
1106   PREFIX_VEX_0F380A,
1107   PREFIX_VEX_0F380B,
1108   PREFIX_VEX_0F380C,
1109   PREFIX_VEX_0F380D,
1110   PREFIX_VEX_0F380E,
1111   PREFIX_VEX_0F380F,
1112   PREFIX_VEX_0F3813,
1113   PREFIX_VEX_0F3816,
1114   PREFIX_VEX_0F3817,
1115   PREFIX_VEX_0F3818,
1116   PREFIX_VEX_0F3819,
1117   PREFIX_VEX_0F381A,
1118   PREFIX_VEX_0F381C,
1119   PREFIX_VEX_0F381D,
1120   PREFIX_VEX_0F381E,
1121   PREFIX_VEX_0F3820,
1122   PREFIX_VEX_0F3821,
1123   PREFIX_VEX_0F3822,
1124   PREFIX_VEX_0F3823,
1125   PREFIX_VEX_0F3824,
1126   PREFIX_VEX_0F3825,
1127   PREFIX_VEX_0F3828,
1128   PREFIX_VEX_0F3829,
1129   PREFIX_VEX_0F382A,
1130   PREFIX_VEX_0F382B,
1131   PREFIX_VEX_0F382C,
1132   PREFIX_VEX_0F382D,
1133   PREFIX_VEX_0F382E,
1134   PREFIX_VEX_0F382F,
1135   PREFIX_VEX_0F3830,
1136   PREFIX_VEX_0F3831,
1137   PREFIX_VEX_0F3832,
1138   PREFIX_VEX_0F3833,
1139   PREFIX_VEX_0F3834,
1140   PREFIX_VEX_0F3835,
1141   PREFIX_VEX_0F3836,
1142   PREFIX_VEX_0F3837,
1143   PREFIX_VEX_0F3838,
1144   PREFIX_VEX_0F3839,
1145   PREFIX_VEX_0F383A,
1146   PREFIX_VEX_0F383B,
1147   PREFIX_VEX_0F383C,
1148   PREFIX_VEX_0F383D,
1149   PREFIX_VEX_0F383E,
1150   PREFIX_VEX_0F383F,
1151   PREFIX_VEX_0F3840,
1152   PREFIX_VEX_0F3841,
1153   PREFIX_VEX_0F3845,
1154   PREFIX_VEX_0F3846,
1155   PREFIX_VEX_0F3847,
1156   PREFIX_VEX_0F3858,
1157   PREFIX_VEX_0F3859,
1158   PREFIX_VEX_0F385A,
1159   PREFIX_VEX_0F3878,
1160   PREFIX_VEX_0F3879,
1161   PREFIX_VEX_0F388C,
1162   PREFIX_VEX_0F388E,
1163   PREFIX_VEX_0F3890,
1164   PREFIX_VEX_0F3891,
1165   PREFIX_VEX_0F3892,
1166   PREFIX_VEX_0F3893,
1167   PREFIX_VEX_0F3896,
1168   PREFIX_VEX_0F3897,
1169   PREFIX_VEX_0F3898,
1170   PREFIX_VEX_0F3899,
1171   PREFIX_VEX_0F389A,
1172   PREFIX_VEX_0F389B,
1173   PREFIX_VEX_0F389C,
1174   PREFIX_VEX_0F389D,
1175   PREFIX_VEX_0F389E,
1176   PREFIX_VEX_0F389F,
1177   PREFIX_VEX_0F38A6,
1178   PREFIX_VEX_0F38A7,
1179   PREFIX_VEX_0F38A8,
1180   PREFIX_VEX_0F38A9,
1181   PREFIX_VEX_0F38AA,
1182   PREFIX_VEX_0F38AB,
1183   PREFIX_VEX_0F38AC,
1184   PREFIX_VEX_0F38AD,
1185   PREFIX_VEX_0F38AE,
1186   PREFIX_VEX_0F38AF,
1187   PREFIX_VEX_0F38B6,
1188   PREFIX_VEX_0F38B7,
1189   PREFIX_VEX_0F38B8,
1190   PREFIX_VEX_0F38B9,
1191   PREFIX_VEX_0F38BA,
1192   PREFIX_VEX_0F38BB,
1193   PREFIX_VEX_0F38BC,
1194   PREFIX_VEX_0F38BD,
1195   PREFIX_VEX_0F38BE,
1196   PREFIX_VEX_0F38BF,
1197   PREFIX_VEX_0F38DB,
1198   PREFIX_VEX_0F38DC,
1199   PREFIX_VEX_0F38DD,
1200   PREFIX_VEX_0F38DE,
1201   PREFIX_VEX_0F38DF,
1202   PREFIX_VEX_0F38F2,
1203   PREFIX_VEX_0F38F3_REG_1,
1204   PREFIX_VEX_0F38F3_REG_2,
1205   PREFIX_VEX_0F38F3_REG_3,
1206   PREFIX_VEX_0F38F5,
1207   PREFIX_VEX_0F38F6,
1208   PREFIX_VEX_0F38F7,
1209   PREFIX_VEX_0F3A00,
1210   PREFIX_VEX_0F3A01,
1211   PREFIX_VEX_0F3A02,
1212   PREFIX_VEX_0F3A04,
1213   PREFIX_VEX_0F3A05,
1214   PREFIX_VEX_0F3A06,
1215   PREFIX_VEX_0F3A08,
1216   PREFIX_VEX_0F3A09,
1217   PREFIX_VEX_0F3A0A,
1218   PREFIX_VEX_0F3A0B,
1219   PREFIX_VEX_0F3A0C,
1220   PREFIX_VEX_0F3A0D,
1221   PREFIX_VEX_0F3A0E,
1222   PREFIX_VEX_0F3A0F,
1223   PREFIX_VEX_0F3A14,
1224   PREFIX_VEX_0F3A15,
1225   PREFIX_VEX_0F3A16,
1226   PREFIX_VEX_0F3A17,
1227   PREFIX_VEX_0F3A18,
1228   PREFIX_VEX_0F3A19,
1229   PREFIX_VEX_0F3A1D,
1230   PREFIX_VEX_0F3A20,
1231   PREFIX_VEX_0F3A21,
1232   PREFIX_VEX_0F3A22,
1233   PREFIX_VEX_0F3A30,
1234   PREFIX_VEX_0F3A32,
1235   PREFIX_VEX_0F3A38,
1236   PREFIX_VEX_0F3A39,
1237   PREFIX_VEX_0F3A40,
1238   PREFIX_VEX_0F3A41,
1239   PREFIX_VEX_0F3A42,
1240   PREFIX_VEX_0F3A44,
1241   PREFIX_VEX_0F3A46,
1242   PREFIX_VEX_0F3A48,
1243   PREFIX_VEX_0F3A49,
1244   PREFIX_VEX_0F3A4A,
1245   PREFIX_VEX_0F3A4B,
1246   PREFIX_VEX_0F3A4C,
1247   PREFIX_VEX_0F3A5C,
1248   PREFIX_VEX_0F3A5D,
1249   PREFIX_VEX_0F3A5E,
1250   PREFIX_VEX_0F3A5F,
1251   PREFIX_VEX_0F3A60,
1252   PREFIX_VEX_0F3A61,
1253   PREFIX_VEX_0F3A62,
1254   PREFIX_VEX_0F3A63,
1255   PREFIX_VEX_0F3A68,
1256   PREFIX_VEX_0F3A69,
1257   PREFIX_VEX_0F3A6A,
1258   PREFIX_VEX_0F3A6B,
1259   PREFIX_VEX_0F3A6C,
1260   PREFIX_VEX_0F3A6D,
1261   PREFIX_VEX_0F3A6E,
1262   PREFIX_VEX_0F3A6F,
1263   PREFIX_VEX_0F3A78,
1264   PREFIX_VEX_0F3A79,
1265   PREFIX_VEX_0F3A7A,
1266   PREFIX_VEX_0F3A7B,
1267   PREFIX_VEX_0F3A7C,
1268   PREFIX_VEX_0F3A7D,
1269   PREFIX_VEX_0F3A7E,
1270   PREFIX_VEX_0F3A7F,
1271   PREFIX_VEX_0F3ADF,
1272   PREFIX_VEX_0F3AF0,
1273
1274   PREFIX_EVEX_0F10,
1275   PREFIX_EVEX_0F11,
1276   PREFIX_EVEX_0F12,
1277   PREFIX_EVEX_0F13,
1278   PREFIX_EVEX_0F14,
1279   PREFIX_EVEX_0F15,
1280   PREFIX_EVEX_0F16,
1281   PREFIX_EVEX_0F17,
1282   PREFIX_EVEX_0F28,
1283   PREFIX_EVEX_0F29,
1284   PREFIX_EVEX_0F2A,
1285   PREFIX_EVEX_0F2B,
1286   PREFIX_EVEX_0F2C,
1287   PREFIX_EVEX_0F2D,
1288   PREFIX_EVEX_0F2E,
1289   PREFIX_EVEX_0F2F,
1290   PREFIX_EVEX_0F51,
1291   PREFIX_EVEX_0F58,
1292   PREFIX_EVEX_0F59,
1293   PREFIX_EVEX_0F5A,
1294   PREFIX_EVEX_0F5B,
1295   PREFIX_EVEX_0F5C,
1296   PREFIX_EVEX_0F5D,
1297   PREFIX_EVEX_0F5E,
1298   PREFIX_EVEX_0F5F,
1299   PREFIX_EVEX_0F62,
1300   PREFIX_EVEX_0F66,
1301   PREFIX_EVEX_0F6A,
1302   PREFIX_EVEX_0F6C,
1303   PREFIX_EVEX_0F6D,
1304   PREFIX_EVEX_0F6E,
1305   PREFIX_EVEX_0F6F,
1306   PREFIX_EVEX_0F70,
1307   PREFIX_EVEX_0F72_REG_0,
1308   PREFIX_EVEX_0F72_REG_1,
1309   PREFIX_EVEX_0F72_REG_2,
1310   PREFIX_EVEX_0F72_REG_4,
1311   PREFIX_EVEX_0F72_REG_6,
1312   PREFIX_EVEX_0F73_REG_2,
1313   PREFIX_EVEX_0F73_REG_6,
1314   PREFIX_EVEX_0F76,
1315   PREFIX_EVEX_0F78,
1316   PREFIX_EVEX_0F79,
1317   PREFIX_EVEX_0F7A,
1318   PREFIX_EVEX_0F7B,
1319   PREFIX_EVEX_0F7E,
1320   PREFIX_EVEX_0F7F,
1321   PREFIX_EVEX_0FC2,
1322   PREFIX_EVEX_0FC6,
1323   PREFIX_EVEX_0FD2,
1324   PREFIX_EVEX_0FD3,
1325   PREFIX_EVEX_0FD4,
1326   PREFIX_EVEX_0FD6,
1327   PREFIX_EVEX_0FDB,
1328   PREFIX_EVEX_0FDF,
1329   PREFIX_EVEX_0FE2,
1330   PREFIX_EVEX_0FE6,
1331   PREFIX_EVEX_0FE7,
1332   PREFIX_EVEX_0FEB,
1333   PREFIX_EVEX_0FEF,
1334   PREFIX_EVEX_0FF2,
1335   PREFIX_EVEX_0FF3,
1336   PREFIX_EVEX_0FF4,
1337   PREFIX_EVEX_0FFA,
1338   PREFIX_EVEX_0FFB,
1339   PREFIX_EVEX_0FFE,
1340   PREFIX_EVEX_0F380C,
1341   PREFIX_EVEX_0F380D,
1342   PREFIX_EVEX_0F3811,
1343   PREFIX_EVEX_0F3812,
1344   PREFIX_EVEX_0F3813,
1345   PREFIX_EVEX_0F3814,
1346   PREFIX_EVEX_0F3815,
1347   PREFIX_EVEX_0F3816,
1348   PREFIX_EVEX_0F3818,
1349   PREFIX_EVEX_0F3819,
1350   PREFIX_EVEX_0F381A,
1351   PREFIX_EVEX_0F381B,
1352   PREFIX_EVEX_0F381E,
1353   PREFIX_EVEX_0F381F,
1354   PREFIX_EVEX_0F3821,
1355   PREFIX_EVEX_0F3822,
1356   PREFIX_EVEX_0F3823,
1357   PREFIX_EVEX_0F3824,
1358   PREFIX_EVEX_0F3825,
1359   PREFIX_EVEX_0F3827,
1360   PREFIX_EVEX_0F3828,
1361   PREFIX_EVEX_0F3829,
1362   PREFIX_EVEX_0F382A,
1363   PREFIX_EVEX_0F382C,
1364   PREFIX_EVEX_0F382D,
1365   PREFIX_EVEX_0F3831,
1366   PREFIX_EVEX_0F3832,
1367   PREFIX_EVEX_0F3833,
1368   PREFIX_EVEX_0F3834,
1369   PREFIX_EVEX_0F3835,
1370   PREFIX_EVEX_0F3836,
1371   PREFIX_EVEX_0F3837,
1372   PREFIX_EVEX_0F3839,
1373   PREFIX_EVEX_0F383A,
1374   PREFIX_EVEX_0F383B,
1375   PREFIX_EVEX_0F383D,
1376   PREFIX_EVEX_0F383F,
1377   PREFIX_EVEX_0F3840,
1378   PREFIX_EVEX_0F3842,
1379   PREFIX_EVEX_0F3843,
1380   PREFIX_EVEX_0F3844,
1381   PREFIX_EVEX_0F3845,
1382   PREFIX_EVEX_0F3846,
1383   PREFIX_EVEX_0F3847,
1384   PREFIX_EVEX_0F384C,
1385   PREFIX_EVEX_0F384D,
1386   PREFIX_EVEX_0F384E,
1387   PREFIX_EVEX_0F384F,
1388   PREFIX_EVEX_0F3858,
1389   PREFIX_EVEX_0F3859,
1390   PREFIX_EVEX_0F385A,
1391   PREFIX_EVEX_0F385B,
1392   PREFIX_EVEX_0F3864,
1393   PREFIX_EVEX_0F3865,
1394   PREFIX_EVEX_0F3876,
1395   PREFIX_EVEX_0F3877,
1396   PREFIX_EVEX_0F387C,
1397   PREFIX_EVEX_0F387E,
1398   PREFIX_EVEX_0F387F,
1399   PREFIX_EVEX_0F3888,
1400   PREFIX_EVEX_0F3889,
1401   PREFIX_EVEX_0F388A,
1402   PREFIX_EVEX_0F388B,
1403   PREFIX_EVEX_0F3890,
1404   PREFIX_EVEX_0F3891,
1405   PREFIX_EVEX_0F3892,
1406   PREFIX_EVEX_0F3893,
1407   PREFIX_EVEX_0F3896,
1408   PREFIX_EVEX_0F3897,
1409   PREFIX_EVEX_0F3898,
1410   PREFIX_EVEX_0F3899,
1411   PREFIX_EVEX_0F389A,
1412   PREFIX_EVEX_0F389B,
1413   PREFIX_EVEX_0F389C,
1414   PREFIX_EVEX_0F389D,
1415   PREFIX_EVEX_0F389E,
1416   PREFIX_EVEX_0F389F,
1417   PREFIX_EVEX_0F38A0,
1418   PREFIX_EVEX_0F38A1,
1419   PREFIX_EVEX_0F38A2,
1420   PREFIX_EVEX_0F38A3,
1421   PREFIX_EVEX_0F38A6,
1422   PREFIX_EVEX_0F38A7,
1423   PREFIX_EVEX_0F38A8,
1424   PREFIX_EVEX_0F38A9,
1425   PREFIX_EVEX_0F38AA,
1426   PREFIX_EVEX_0F38AB,
1427   PREFIX_EVEX_0F38AC,
1428   PREFIX_EVEX_0F38AD,
1429   PREFIX_EVEX_0F38AE,
1430   PREFIX_EVEX_0F38AF,
1431   PREFIX_EVEX_0F38B6,
1432   PREFIX_EVEX_0F38B7,
1433   PREFIX_EVEX_0F38B8,
1434   PREFIX_EVEX_0F38B9,
1435   PREFIX_EVEX_0F38BA,
1436   PREFIX_EVEX_0F38BB,
1437   PREFIX_EVEX_0F38BC,
1438   PREFIX_EVEX_0F38BD,
1439   PREFIX_EVEX_0F38BE,
1440   PREFIX_EVEX_0F38BF,
1441   PREFIX_EVEX_0F38C4,
1442   PREFIX_EVEX_0F38C6_REG_1,
1443   PREFIX_EVEX_0F38C6_REG_2,
1444   PREFIX_EVEX_0F38C6_REG_5,
1445   PREFIX_EVEX_0F38C6_REG_6,
1446   PREFIX_EVEX_0F38C7_REG_1,
1447   PREFIX_EVEX_0F38C7_REG_2,
1448   PREFIX_EVEX_0F38C7_REG_5,
1449   PREFIX_EVEX_0F38C7_REG_6,
1450   PREFIX_EVEX_0F38C8,
1451   PREFIX_EVEX_0F38CA,
1452   PREFIX_EVEX_0F38CB,
1453   PREFIX_EVEX_0F38CC,
1454   PREFIX_EVEX_0F38CD,
1455
1456   PREFIX_EVEX_0F3A00,
1457   PREFIX_EVEX_0F3A01,
1458   PREFIX_EVEX_0F3A03,
1459   PREFIX_EVEX_0F3A04,
1460   PREFIX_EVEX_0F3A05,
1461   PREFIX_EVEX_0F3A08,
1462   PREFIX_EVEX_0F3A09,
1463   PREFIX_EVEX_0F3A0A,
1464   PREFIX_EVEX_0F3A0B,
1465   PREFIX_EVEX_0F3A17,
1466   PREFIX_EVEX_0F3A18,
1467   PREFIX_EVEX_0F3A19,
1468   PREFIX_EVEX_0F3A1A,
1469   PREFIX_EVEX_0F3A1B,
1470   PREFIX_EVEX_0F3A1D,
1471   PREFIX_EVEX_0F3A1E,
1472   PREFIX_EVEX_0F3A1F,
1473   PREFIX_EVEX_0F3A21,
1474   PREFIX_EVEX_0F3A23,
1475   PREFIX_EVEX_0F3A25,
1476   PREFIX_EVEX_0F3A26,
1477   PREFIX_EVEX_0F3A27,
1478   PREFIX_EVEX_0F3A38,
1479   PREFIX_EVEX_0F3A39,
1480   PREFIX_EVEX_0F3A3A,
1481   PREFIX_EVEX_0F3A3B,
1482   PREFIX_EVEX_0F3A43,
1483   PREFIX_EVEX_0F3A54,
1484   PREFIX_EVEX_0F3A55,
1485 };
1486
1487 enum
1488 {
1489   X86_64_06 = 0,
1490   X86_64_07,
1491   X86_64_0D,
1492   X86_64_16,
1493   X86_64_17,
1494   X86_64_1E,
1495   X86_64_1F,
1496   X86_64_27,
1497   X86_64_2F,
1498   X86_64_37,
1499   X86_64_3F,
1500   X86_64_60,
1501   X86_64_61,
1502   X86_64_62,
1503   X86_64_63,
1504   X86_64_6D,
1505   X86_64_6F,
1506   X86_64_9A,
1507   X86_64_C4,
1508   X86_64_C5,
1509   X86_64_CE,
1510   X86_64_D4,
1511   X86_64_D5,
1512   X86_64_EA,
1513   X86_64_0F01_REG_0,
1514   X86_64_0F01_REG_1,
1515   X86_64_0F01_REG_2,
1516   X86_64_0F01_REG_3
1517 };
1518
1519 enum
1520 {
1521   THREE_BYTE_0F38 = 0,
1522   THREE_BYTE_0F3A,
1523   THREE_BYTE_0F7A
1524 };
1525
1526 enum
1527 {
1528   XOP_08 = 0,
1529   XOP_09,
1530   XOP_0A
1531 };
1532
1533 enum
1534 {
1535   VEX_0F = 0,
1536   VEX_0F38,
1537   VEX_0F3A
1538 };
1539
1540 enum
1541 {
1542   EVEX_0F = 0,
1543   EVEX_0F38,
1544   EVEX_0F3A
1545 };
1546
1547 enum
1548 {
1549   VEX_LEN_0F10_P_1 = 0,
1550   VEX_LEN_0F10_P_3,
1551   VEX_LEN_0F11_P_1,
1552   VEX_LEN_0F11_P_3,
1553   VEX_LEN_0F12_P_0_M_0,
1554   VEX_LEN_0F12_P_0_M_1,
1555   VEX_LEN_0F12_P_2,
1556   VEX_LEN_0F13_M_0,
1557   VEX_LEN_0F16_P_0_M_0,
1558   VEX_LEN_0F16_P_0_M_1,
1559   VEX_LEN_0F16_P_2,
1560   VEX_LEN_0F17_M_0,
1561   VEX_LEN_0F2A_P_1,
1562   VEX_LEN_0F2A_P_3,
1563   VEX_LEN_0F2C_P_1,
1564   VEX_LEN_0F2C_P_3,
1565   VEX_LEN_0F2D_P_1,
1566   VEX_LEN_0F2D_P_3,
1567   VEX_LEN_0F2E_P_0,
1568   VEX_LEN_0F2E_P_2,
1569   VEX_LEN_0F2F_P_0,
1570   VEX_LEN_0F2F_P_2,
1571   VEX_LEN_0F41_P_0,
1572   VEX_LEN_0F42_P_0,
1573   VEX_LEN_0F44_P_0,
1574   VEX_LEN_0F45_P_0,
1575   VEX_LEN_0F46_P_0,
1576   VEX_LEN_0F47_P_0,
1577   VEX_LEN_0F4B_P_2,
1578   VEX_LEN_0F51_P_1,
1579   VEX_LEN_0F51_P_3,
1580   VEX_LEN_0F52_P_1,
1581   VEX_LEN_0F53_P_1,
1582   VEX_LEN_0F58_P_1,
1583   VEX_LEN_0F58_P_3,
1584   VEX_LEN_0F59_P_1,
1585   VEX_LEN_0F59_P_3,
1586   VEX_LEN_0F5A_P_1,
1587   VEX_LEN_0F5A_P_3,
1588   VEX_LEN_0F5C_P_1,
1589   VEX_LEN_0F5C_P_3,
1590   VEX_LEN_0F5D_P_1,
1591   VEX_LEN_0F5D_P_3,
1592   VEX_LEN_0F5E_P_1,
1593   VEX_LEN_0F5E_P_3,
1594   VEX_LEN_0F5F_P_1,
1595   VEX_LEN_0F5F_P_3,
1596   VEX_LEN_0F6E_P_2,
1597   VEX_LEN_0F7E_P_1,
1598   VEX_LEN_0F7E_P_2,
1599   VEX_LEN_0F90_P_0,
1600   VEX_LEN_0F91_P_0,
1601   VEX_LEN_0F92_P_0,
1602   VEX_LEN_0F93_P_0,
1603   VEX_LEN_0F98_P_0,
1604   VEX_LEN_0FAE_R_2_M_0,
1605   VEX_LEN_0FAE_R_3_M_0,
1606   VEX_LEN_0FC2_P_1,
1607   VEX_LEN_0FC2_P_3,
1608   VEX_LEN_0FC4_P_2,
1609   VEX_LEN_0FC5_P_2,
1610   VEX_LEN_0FD6_P_2,
1611   VEX_LEN_0FF7_P_2,
1612   VEX_LEN_0F3816_P_2,
1613   VEX_LEN_0F3819_P_2,
1614   VEX_LEN_0F381A_P_2_M_0,
1615   VEX_LEN_0F3836_P_2,
1616   VEX_LEN_0F3841_P_2,
1617   VEX_LEN_0F385A_P_2_M_0,
1618   VEX_LEN_0F38DB_P_2,
1619   VEX_LEN_0F38DC_P_2,
1620   VEX_LEN_0F38DD_P_2,
1621   VEX_LEN_0F38DE_P_2,
1622   VEX_LEN_0F38DF_P_2,
1623   VEX_LEN_0F38F2_P_0,
1624   VEX_LEN_0F38F3_R_1_P_0,
1625   VEX_LEN_0F38F3_R_2_P_0,
1626   VEX_LEN_0F38F3_R_3_P_0,
1627   VEX_LEN_0F38F5_P_0,
1628   VEX_LEN_0F38F5_P_1,
1629   VEX_LEN_0F38F5_P_3,
1630   VEX_LEN_0F38F6_P_3,
1631   VEX_LEN_0F38F7_P_0,
1632   VEX_LEN_0F38F7_P_1,
1633   VEX_LEN_0F38F7_P_2,
1634   VEX_LEN_0F38F7_P_3,
1635   VEX_LEN_0F3A00_P_2,
1636   VEX_LEN_0F3A01_P_2,
1637   VEX_LEN_0F3A06_P_2,
1638   VEX_LEN_0F3A0A_P_2,
1639   VEX_LEN_0F3A0B_P_2,
1640   VEX_LEN_0F3A14_P_2,
1641   VEX_LEN_0F3A15_P_2,
1642   VEX_LEN_0F3A16_P_2,
1643   VEX_LEN_0F3A17_P_2,
1644   VEX_LEN_0F3A18_P_2,
1645   VEX_LEN_0F3A19_P_2,
1646   VEX_LEN_0F3A20_P_2,
1647   VEX_LEN_0F3A21_P_2,
1648   VEX_LEN_0F3A22_P_2,
1649   VEX_LEN_0F3A30_P_2,
1650   VEX_LEN_0F3A32_P_2,
1651   VEX_LEN_0F3A38_P_2,
1652   VEX_LEN_0F3A39_P_2,
1653   VEX_LEN_0F3A41_P_2,
1654   VEX_LEN_0F3A44_P_2,
1655   VEX_LEN_0F3A46_P_2,
1656   VEX_LEN_0F3A60_P_2,
1657   VEX_LEN_0F3A61_P_2,
1658   VEX_LEN_0F3A62_P_2,
1659   VEX_LEN_0F3A63_P_2,
1660   VEX_LEN_0F3A6A_P_2,
1661   VEX_LEN_0F3A6B_P_2,
1662   VEX_LEN_0F3A6E_P_2,
1663   VEX_LEN_0F3A6F_P_2,
1664   VEX_LEN_0F3A7A_P_2,
1665   VEX_LEN_0F3A7B_P_2,
1666   VEX_LEN_0F3A7E_P_2,
1667   VEX_LEN_0F3A7F_P_2,
1668   VEX_LEN_0F3ADF_P_2,
1669   VEX_LEN_0F3AF0_P_3,
1670   VEX_LEN_0FXOP_08_CC,
1671   VEX_LEN_0FXOP_08_CD,
1672   VEX_LEN_0FXOP_08_CE,
1673   VEX_LEN_0FXOP_08_CF,
1674   VEX_LEN_0FXOP_08_EC,
1675   VEX_LEN_0FXOP_08_ED,
1676   VEX_LEN_0FXOP_08_EE,
1677   VEX_LEN_0FXOP_08_EF,
1678   VEX_LEN_0FXOP_09_80,
1679   VEX_LEN_0FXOP_09_81
1680 };
1681
1682 enum
1683 {
1684   VEX_W_0F10_P_0 = 0,
1685   VEX_W_0F10_P_1,
1686   VEX_W_0F10_P_2,
1687   VEX_W_0F10_P_3,
1688   VEX_W_0F11_P_0,
1689   VEX_W_0F11_P_1,
1690   VEX_W_0F11_P_2,
1691   VEX_W_0F11_P_3,
1692   VEX_W_0F12_P_0_M_0,
1693   VEX_W_0F12_P_0_M_1,
1694   VEX_W_0F12_P_1,
1695   VEX_W_0F12_P_2,
1696   VEX_W_0F12_P_3,
1697   VEX_W_0F13_M_0,
1698   VEX_W_0F14,
1699   VEX_W_0F15,
1700   VEX_W_0F16_P_0_M_0,
1701   VEX_W_0F16_P_0_M_1,
1702   VEX_W_0F16_P_1,
1703   VEX_W_0F16_P_2,
1704   VEX_W_0F17_M_0,
1705   VEX_W_0F28,
1706   VEX_W_0F29,
1707   VEX_W_0F2B_M_0,
1708   VEX_W_0F2E_P_0,
1709   VEX_W_0F2E_P_2,
1710   VEX_W_0F2F_P_0,
1711   VEX_W_0F2F_P_2,
1712   VEX_W_0F41_P_0_LEN_1,
1713   VEX_W_0F42_P_0_LEN_1,
1714   VEX_W_0F44_P_0_LEN_0,
1715   VEX_W_0F45_P_0_LEN_1,
1716   VEX_W_0F46_P_0_LEN_1,
1717   VEX_W_0F47_P_0_LEN_1,
1718   VEX_W_0F4B_P_2_LEN_1,
1719   VEX_W_0F50_M_0,
1720   VEX_W_0F51_P_0,
1721   VEX_W_0F51_P_1,
1722   VEX_W_0F51_P_2,
1723   VEX_W_0F51_P_3,
1724   VEX_W_0F52_P_0,
1725   VEX_W_0F52_P_1,
1726   VEX_W_0F53_P_0,
1727   VEX_W_0F53_P_1,
1728   VEX_W_0F58_P_0,
1729   VEX_W_0F58_P_1,
1730   VEX_W_0F58_P_2,
1731   VEX_W_0F58_P_3,
1732   VEX_W_0F59_P_0,
1733   VEX_W_0F59_P_1,
1734   VEX_W_0F59_P_2,
1735   VEX_W_0F59_P_3,
1736   VEX_W_0F5A_P_0,
1737   VEX_W_0F5A_P_1,
1738   VEX_W_0F5A_P_3,
1739   VEX_W_0F5B_P_0,
1740   VEX_W_0F5B_P_1,
1741   VEX_W_0F5B_P_2,
1742   VEX_W_0F5C_P_0,
1743   VEX_W_0F5C_P_1,
1744   VEX_W_0F5C_P_2,
1745   VEX_W_0F5C_P_3,
1746   VEX_W_0F5D_P_0,
1747   VEX_W_0F5D_P_1,
1748   VEX_W_0F5D_P_2,
1749   VEX_W_0F5D_P_3,
1750   VEX_W_0F5E_P_0,
1751   VEX_W_0F5E_P_1,
1752   VEX_W_0F5E_P_2,
1753   VEX_W_0F5E_P_3,
1754   VEX_W_0F5F_P_0,
1755   VEX_W_0F5F_P_1,
1756   VEX_W_0F5F_P_2,
1757   VEX_W_0F5F_P_3,
1758   VEX_W_0F60_P_2,
1759   VEX_W_0F61_P_2,
1760   VEX_W_0F62_P_2,
1761   VEX_W_0F63_P_2,
1762   VEX_W_0F64_P_2,
1763   VEX_W_0F65_P_2,
1764   VEX_W_0F66_P_2,
1765   VEX_W_0F67_P_2,
1766   VEX_W_0F68_P_2,
1767   VEX_W_0F69_P_2,
1768   VEX_W_0F6A_P_2,
1769   VEX_W_0F6B_P_2,
1770   VEX_W_0F6C_P_2,
1771   VEX_W_0F6D_P_2,
1772   VEX_W_0F6F_P_1,
1773   VEX_W_0F6F_P_2,
1774   VEX_W_0F70_P_1,
1775   VEX_W_0F70_P_2,
1776   VEX_W_0F70_P_3,
1777   VEX_W_0F71_R_2_P_2,
1778   VEX_W_0F71_R_4_P_2,
1779   VEX_W_0F71_R_6_P_2,
1780   VEX_W_0F72_R_2_P_2,
1781   VEX_W_0F72_R_4_P_2,
1782   VEX_W_0F72_R_6_P_2,
1783   VEX_W_0F73_R_2_P_2,
1784   VEX_W_0F73_R_3_P_2,
1785   VEX_W_0F73_R_6_P_2,
1786   VEX_W_0F73_R_7_P_2,
1787   VEX_W_0F74_P_2,
1788   VEX_W_0F75_P_2,
1789   VEX_W_0F76_P_2,
1790   VEX_W_0F77_P_0,
1791   VEX_W_0F7C_P_2,
1792   VEX_W_0F7C_P_3,
1793   VEX_W_0F7D_P_2,
1794   VEX_W_0F7D_P_3,
1795   VEX_W_0F7E_P_1,
1796   VEX_W_0F7F_P_1,
1797   VEX_W_0F7F_P_2,
1798   VEX_W_0F90_P_0_LEN_0,
1799   VEX_W_0F91_P_0_LEN_0,
1800   VEX_W_0F92_P_0_LEN_0,
1801   VEX_W_0F93_P_0_LEN_0,
1802   VEX_W_0F98_P_0_LEN_0,
1803   VEX_W_0FAE_R_2_M_0,
1804   VEX_W_0FAE_R_3_M_0,
1805   VEX_W_0FC2_P_0,
1806   VEX_W_0FC2_P_1,
1807   VEX_W_0FC2_P_2,
1808   VEX_W_0FC2_P_3,
1809   VEX_W_0FC4_P_2,
1810   VEX_W_0FC5_P_2,
1811   VEX_W_0FD0_P_2,
1812   VEX_W_0FD0_P_3,
1813   VEX_W_0FD1_P_2,
1814   VEX_W_0FD2_P_2,
1815   VEX_W_0FD3_P_2,
1816   VEX_W_0FD4_P_2,
1817   VEX_W_0FD5_P_2,
1818   VEX_W_0FD6_P_2,
1819   VEX_W_0FD7_P_2_M_1,
1820   VEX_W_0FD8_P_2,
1821   VEX_W_0FD9_P_2,
1822   VEX_W_0FDA_P_2,
1823   VEX_W_0FDB_P_2,
1824   VEX_W_0FDC_P_2,
1825   VEX_W_0FDD_P_2,
1826   VEX_W_0FDE_P_2,
1827   VEX_W_0FDF_P_2,
1828   VEX_W_0FE0_P_2,
1829   VEX_W_0FE1_P_2,
1830   VEX_W_0FE2_P_2,
1831   VEX_W_0FE3_P_2,
1832   VEX_W_0FE4_P_2,
1833   VEX_W_0FE5_P_2,
1834   VEX_W_0FE6_P_1,
1835   VEX_W_0FE6_P_2,
1836   VEX_W_0FE6_P_3,
1837   VEX_W_0FE7_P_2_M_0,
1838   VEX_W_0FE8_P_2,
1839   VEX_W_0FE9_P_2,
1840   VEX_W_0FEA_P_2,
1841   VEX_W_0FEB_P_2,
1842   VEX_W_0FEC_P_2,
1843   VEX_W_0FED_P_2,
1844   VEX_W_0FEE_P_2,
1845   VEX_W_0FEF_P_2,
1846   VEX_W_0FF0_P_3_M_0,
1847   VEX_W_0FF1_P_2,
1848   VEX_W_0FF2_P_2,
1849   VEX_W_0FF3_P_2,
1850   VEX_W_0FF4_P_2,
1851   VEX_W_0FF5_P_2,
1852   VEX_W_0FF6_P_2,
1853   VEX_W_0FF7_P_2,
1854   VEX_W_0FF8_P_2,
1855   VEX_W_0FF9_P_2,
1856   VEX_W_0FFA_P_2,
1857   VEX_W_0FFB_P_2,
1858   VEX_W_0FFC_P_2,
1859   VEX_W_0FFD_P_2,
1860   VEX_W_0FFE_P_2,
1861   VEX_W_0F3800_P_2,
1862   VEX_W_0F3801_P_2,
1863   VEX_W_0F3802_P_2,
1864   VEX_W_0F3803_P_2,
1865   VEX_W_0F3804_P_2,
1866   VEX_W_0F3805_P_2,
1867   VEX_W_0F3806_P_2,
1868   VEX_W_0F3807_P_2,
1869   VEX_W_0F3808_P_2,
1870   VEX_W_0F3809_P_2,
1871   VEX_W_0F380A_P_2,
1872   VEX_W_0F380B_P_2,
1873   VEX_W_0F380C_P_2,
1874   VEX_W_0F380D_P_2,
1875   VEX_W_0F380E_P_2,
1876   VEX_W_0F380F_P_2,
1877   VEX_W_0F3816_P_2,
1878   VEX_W_0F3817_P_2,
1879   VEX_W_0F3818_P_2,
1880   VEX_W_0F3819_P_2,
1881   VEX_W_0F381A_P_2_M_0,
1882   VEX_W_0F381C_P_2,
1883   VEX_W_0F381D_P_2,
1884   VEX_W_0F381E_P_2,
1885   VEX_W_0F3820_P_2,
1886   VEX_W_0F3821_P_2,
1887   VEX_W_0F3822_P_2,
1888   VEX_W_0F3823_P_2,
1889   VEX_W_0F3824_P_2,
1890   VEX_W_0F3825_P_2,
1891   VEX_W_0F3828_P_2,
1892   VEX_W_0F3829_P_2,
1893   VEX_W_0F382A_P_2_M_0,
1894   VEX_W_0F382B_P_2,
1895   VEX_W_0F382C_P_2_M_0,
1896   VEX_W_0F382D_P_2_M_0,
1897   VEX_W_0F382E_P_2_M_0,
1898   VEX_W_0F382F_P_2_M_0,
1899   VEX_W_0F3830_P_2,
1900   VEX_W_0F3831_P_2,
1901   VEX_W_0F3832_P_2,
1902   VEX_W_0F3833_P_2,
1903   VEX_W_0F3834_P_2,
1904   VEX_W_0F3835_P_2,
1905   VEX_W_0F3836_P_2,
1906   VEX_W_0F3837_P_2,
1907   VEX_W_0F3838_P_2,
1908   VEX_W_0F3839_P_2,
1909   VEX_W_0F383A_P_2,
1910   VEX_W_0F383B_P_2,
1911   VEX_W_0F383C_P_2,
1912   VEX_W_0F383D_P_2,
1913   VEX_W_0F383E_P_2,
1914   VEX_W_0F383F_P_2,
1915   VEX_W_0F3840_P_2,
1916   VEX_W_0F3841_P_2,
1917   VEX_W_0F3846_P_2,
1918   VEX_W_0F3858_P_2,
1919   VEX_W_0F3859_P_2,
1920   VEX_W_0F385A_P_2_M_0,
1921   VEX_W_0F3878_P_2,
1922   VEX_W_0F3879_P_2,
1923   VEX_W_0F38DB_P_2,
1924   VEX_W_0F38DC_P_2,
1925   VEX_W_0F38DD_P_2,
1926   VEX_W_0F38DE_P_2,
1927   VEX_W_0F38DF_P_2,
1928   VEX_W_0F3A00_P_2,
1929   VEX_W_0F3A01_P_2,
1930   VEX_W_0F3A02_P_2,
1931   VEX_W_0F3A04_P_2,
1932   VEX_W_0F3A05_P_2,
1933   VEX_W_0F3A06_P_2,
1934   VEX_W_0F3A08_P_2,
1935   VEX_W_0F3A09_P_2,
1936   VEX_W_0F3A0A_P_2,
1937   VEX_W_0F3A0B_P_2,
1938   VEX_W_0F3A0C_P_2,
1939   VEX_W_0F3A0D_P_2,
1940   VEX_W_0F3A0E_P_2,
1941   VEX_W_0F3A0F_P_2,
1942   VEX_W_0F3A14_P_2,
1943   VEX_W_0F3A15_P_2,
1944   VEX_W_0F3A18_P_2,
1945   VEX_W_0F3A19_P_2,
1946   VEX_W_0F3A20_P_2,
1947   VEX_W_0F3A21_P_2,
1948   VEX_W_0F3A30_P_2_LEN_0,
1949   VEX_W_0F3A32_P_2_LEN_0,
1950   VEX_W_0F3A38_P_2,
1951   VEX_W_0F3A39_P_2,
1952   VEX_W_0F3A40_P_2,
1953   VEX_W_0F3A41_P_2,
1954   VEX_W_0F3A42_P_2,
1955   VEX_W_0F3A44_P_2,
1956   VEX_W_0F3A46_P_2,
1957   VEX_W_0F3A48_P_2,
1958   VEX_W_0F3A49_P_2,
1959   VEX_W_0F3A4A_P_2,
1960   VEX_W_0F3A4B_P_2,
1961   VEX_W_0F3A4C_P_2,
1962   VEX_W_0F3A60_P_2,
1963   VEX_W_0F3A61_P_2,
1964   VEX_W_0F3A62_P_2,
1965   VEX_W_0F3A63_P_2,
1966   VEX_W_0F3ADF_P_2,
1967
1968   EVEX_W_0F10_P_0,
1969   EVEX_W_0F10_P_1_M_0,
1970   EVEX_W_0F10_P_1_M_1,
1971   EVEX_W_0F10_P_2,
1972   EVEX_W_0F10_P_3_M_0,
1973   EVEX_W_0F10_P_3_M_1,
1974   EVEX_W_0F11_P_0,
1975   EVEX_W_0F11_P_1_M_0,
1976   EVEX_W_0F11_P_1_M_1,
1977   EVEX_W_0F11_P_2,
1978   EVEX_W_0F11_P_3_M_0,
1979   EVEX_W_0F11_P_3_M_1,
1980   EVEX_W_0F12_P_0_M_0,
1981   EVEX_W_0F12_P_0_M_1,
1982   EVEX_W_0F12_P_1,
1983   EVEX_W_0F12_P_2,
1984   EVEX_W_0F12_P_3,
1985   EVEX_W_0F13_P_0,
1986   EVEX_W_0F13_P_2,
1987   EVEX_W_0F14_P_0,
1988   EVEX_W_0F14_P_2,
1989   EVEX_W_0F15_P_0,
1990   EVEX_W_0F15_P_2,
1991   EVEX_W_0F16_P_0_M_0,
1992   EVEX_W_0F16_P_0_M_1,
1993   EVEX_W_0F16_P_1,
1994   EVEX_W_0F16_P_2,
1995   EVEX_W_0F17_P_0,
1996   EVEX_W_0F17_P_2,
1997   EVEX_W_0F28_P_0,
1998   EVEX_W_0F28_P_2,
1999   EVEX_W_0F29_P_0,
2000   EVEX_W_0F29_P_2,
2001   EVEX_W_0F2A_P_1,
2002   EVEX_W_0F2A_P_3,
2003   EVEX_W_0F2B_P_0,
2004   EVEX_W_0F2B_P_2,
2005   EVEX_W_0F2E_P_0,
2006   EVEX_W_0F2E_P_2,
2007   EVEX_W_0F2F_P_0,
2008   EVEX_W_0F2F_P_2,
2009   EVEX_W_0F51_P_0,
2010   EVEX_W_0F51_P_1,
2011   EVEX_W_0F51_P_2,
2012   EVEX_W_0F51_P_3,
2013   EVEX_W_0F58_P_0,
2014   EVEX_W_0F58_P_1,
2015   EVEX_W_0F58_P_2,
2016   EVEX_W_0F58_P_3,
2017   EVEX_W_0F59_P_0,
2018   EVEX_W_0F59_P_1,
2019   EVEX_W_0F59_P_2,
2020   EVEX_W_0F59_P_3,
2021   EVEX_W_0F5A_P_0,
2022   EVEX_W_0F5A_P_1,
2023   EVEX_W_0F5A_P_2,
2024   EVEX_W_0F5A_P_3,
2025   EVEX_W_0F5B_P_0,
2026   EVEX_W_0F5B_P_1,
2027   EVEX_W_0F5B_P_2,
2028   EVEX_W_0F5C_P_0,
2029   EVEX_W_0F5C_P_1,
2030   EVEX_W_0F5C_P_2,
2031   EVEX_W_0F5C_P_3,
2032   EVEX_W_0F5D_P_0,
2033   EVEX_W_0F5D_P_1,
2034   EVEX_W_0F5D_P_2,
2035   EVEX_W_0F5D_P_3,
2036   EVEX_W_0F5E_P_0,
2037   EVEX_W_0F5E_P_1,
2038   EVEX_W_0F5E_P_2,
2039   EVEX_W_0F5E_P_3,
2040   EVEX_W_0F5F_P_0,
2041   EVEX_W_0F5F_P_1,
2042   EVEX_W_0F5F_P_2,
2043   EVEX_W_0F5F_P_3,
2044   EVEX_W_0F62_P_2,
2045   EVEX_W_0F66_P_2,
2046   EVEX_W_0F6A_P_2,
2047   EVEX_W_0F6C_P_2,
2048   EVEX_W_0F6D_P_2,
2049   EVEX_W_0F6E_P_2,
2050   EVEX_W_0F6F_P_1,
2051   EVEX_W_0F6F_P_2,
2052   EVEX_W_0F70_P_2,
2053   EVEX_W_0F72_R_2_P_2,
2054   EVEX_W_0F72_R_6_P_2,
2055   EVEX_W_0F73_R_2_P_2,
2056   EVEX_W_0F73_R_6_P_2,
2057   EVEX_W_0F76_P_2,
2058   EVEX_W_0F78_P_0,
2059   EVEX_W_0F79_P_0,
2060   EVEX_W_0F7A_P_1,
2061   EVEX_W_0F7A_P_3,
2062   EVEX_W_0F7B_P_1,
2063   EVEX_W_0F7B_P_3,
2064   EVEX_W_0F7E_P_1,
2065   EVEX_W_0F7E_P_2,
2066   EVEX_W_0F7F_P_1,
2067   EVEX_W_0F7F_P_2,
2068   EVEX_W_0FC2_P_0,
2069   EVEX_W_0FC2_P_1,
2070   EVEX_W_0FC2_P_2,
2071   EVEX_W_0FC2_P_3,
2072   EVEX_W_0FC6_P_0,
2073   EVEX_W_0FC6_P_2,
2074   EVEX_W_0FD2_P_2,
2075   EVEX_W_0FD3_P_2,
2076   EVEX_W_0FD4_P_2,
2077   EVEX_W_0FD6_P_2,
2078   EVEX_W_0FE6_P_1,
2079   EVEX_W_0FE6_P_2,
2080   EVEX_W_0FE6_P_3,
2081   EVEX_W_0FE7_P_2,
2082   EVEX_W_0FF2_P_2,
2083   EVEX_W_0FF3_P_2,
2084   EVEX_W_0FF4_P_2,
2085   EVEX_W_0FFA_P_2,
2086   EVEX_W_0FFB_P_2,
2087   EVEX_W_0FFE_P_2,
2088   EVEX_W_0F380C_P_2,
2089   EVEX_W_0F380D_P_2,
2090   EVEX_W_0F3811_P_1,
2091   EVEX_W_0F3812_P_1,
2092   EVEX_W_0F3813_P_1,
2093   EVEX_W_0F3813_P_2,
2094   EVEX_W_0F3814_P_1,
2095   EVEX_W_0F3815_P_1,
2096   EVEX_W_0F3818_P_2,
2097   EVEX_W_0F3819_P_2,
2098   EVEX_W_0F381A_P_2,
2099   EVEX_W_0F381B_P_2,
2100   EVEX_W_0F381E_P_2,
2101   EVEX_W_0F381F_P_2,
2102   EVEX_W_0F3821_P_1,
2103   EVEX_W_0F3822_P_1,
2104   EVEX_W_0F3823_P_1,
2105   EVEX_W_0F3824_P_1,
2106   EVEX_W_0F3825_P_1,
2107   EVEX_W_0F3825_P_2,
2108   EVEX_W_0F3828_P_2,
2109   EVEX_W_0F3829_P_2,
2110   EVEX_W_0F382A_P_1,
2111   EVEX_W_0F382A_P_2,
2112   EVEX_W_0F3831_P_1,
2113   EVEX_W_0F3832_P_1,
2114   EVEX_W_0F3833_P_1,
2115   EVEX_W_0F3834_P_1,
2116   EVEX_W_0F3835_P_1,
2117   EVEX_W_0F3835_P_2,
2118   EVEX_W_0F3837_P_2,
2119   EVEX_W_0F383A_P_1,
2120   EVEX_W_0F3840_P_2,
2121   EVEX_W_0F3858_P_2,
2122   EVEX_W_0F3859_P_2,
2123   EVEX_W_0F385A_P_2,
2124   EVEX_W_0F385B_P_2,
2125   EVEX_W_0F3891_P_2,
2126   EVEX_W_0F3893_P_2,
2127   EVEX_W_0F38A1_P_2,
2128   EVEX_W_0F38A3_P_2,
2129   EVEX_W_0F38C7_R_1_P_2,
2130   EVEX_W_0F38C7_R_2_P_2,
2131   EVEX_W_0F38C7_R_5_P_2,
2132   EVEX_W_0F38C7_R_6_P_2,
2133
2134   EVEX_W_0F3A00_P_2,
2135   EVEX_W_0F3A01_P_2,
2136   EVEX_W_0F3A04_P_2,
2137   EVEX_W_0F3A05_P_2,
2138   EVEX_W_0F3A08_P_2,
2139   EVEX_W_0F3A09_P_2,
2140   EVEX_W_0F3A0A_P_2,
2141   EVEX_W_0F3A0B_P_2,
2142   EVEX_W_0F3A18_P_2,
2143   EVEX_W_0F3A19_P_2,
2144   EVEX_W_0F3A1A_P_2,
2145   EVEX_W_0F3A1B_P_2,
2146   EVEX_W_0F3A1D_P_2,
2147   EVEX_W_0F3A21_P_2,
2148   EVEX_W_0F3A23_P_2,
2149   EVEX_W_0F3A38_P_2,
2150   EVEX_W_0F3A39_P_2,
2151   EVEX_W_0F3A3A_P_2,
2152   EVEX_W_0F3A3B_P_2,
2153   EVEX_W_0F3A43_P_2,
2154 };
2155
2156 typedef void (*op_rtn) (int bytemode, int sizeflag);
2157
2158 struct dis386 {
2159   const char *name;
2160   struct
2161     {
2162       op_rtn rtn;
2163       int bytemode;
2164     } op[MAX_OPERANDS];
2165 };
2166
2167 /* Upper case letters in the instruction names here are macros.
2168    'A' => print 'b' if no register operands or suffix_always is true
2169    'B' => print 'b' if suffix_always is true
2170    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2171           size prefix
2172    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173           suffix_always is true
2174    'E' => print 'e' if 32-bit form of jcxz
2175    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177    'H' => print ",pt" or ",pn" branch hint
2178    'I' => honor following macro letter even in Intel mode (implemented only
2179           for some of the macro letters)
2180    'J' => print 'l'
2181    'K' => print 'd' or 'q' if rex prefix is present.
2182    'L' => print 'l' if suffix_always is true
2183    'M' => print 'r' if intel_mnemonic is false.
2184    'N' => print 'n' if instruction has no wait "prefix"
2185    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187           or suffix_always is true.  print 'q' if rex prefix is present.
2188    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2189           is true
2190    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191    'S' => print 'w', 'l' or 'q' if suffix_always is true
2192    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198           suffix_always is true.
2199    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200    '!' => change condition from true to false or from false to true.
2201    '%' => add 1 upper case letter to the macro.
2202
2203    2 upper case letter macros:
2204    "XY" => print 'x' or 'y' if no register operands or suffix_always
2205            is true.
2206    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208            or suffix_always is true
2209    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212    "LW" => print 'd', 'q' depending on the VEX.W bit
2213
2214    Many of the above letters print nothing in Intel mode.  See "putop"
2215    for the details.
2216
2217    Braces '{' and '}', and vertical bars '|', indicate alternative
2218    mnemonic strings for AT&T and Intel.  */
2219
2220 static const struct dis386 dis386[] = {
2221   /* 00 */
2222   { "addB",             { Ebh1, Gb } },
2223   { "addS",             { Evh1, Gv } },
2224   { "addB",             { Gb, EbS } },
2225   { "addS",             { Gv, EvS } },
2226   { "addB",             { AL, Ib } },
2227   { "addS",             { eAX, Iv } },
2228   { X86_64_TABLE (X86_64_06) },
2229   { X86_64_TABLE (X86_64_07) },
2230   /* 08 */
2231   { "orB",              { Ebh1, Gb } },
2232   { "orS",              { Evh1, Gv } },
2233   { "orB",              { Gb, EbS } },
2234   { "orS",              { Gv, EvS } },
2235   { "orB",              { AL, Ib } },
2236   { "orS",              { eAX, Iv } },
2237   { X86_64_TABLE (X86_64_0D) },
2238   { Bad_Opcode },       /* 0x0f extended opcode escape */
2239   /* 10 */
2240   { "adcB",             { Ebh1, Gb } },
2241   { "adcS",             { Evh1, Gv } },
2242   { "adcB",             { Gb, EbS } },
2243   { "adcS",             { Gv, EvS } },
2244   { "adcB",             { AL, Ib } },
2245   { "adcS",             { eAX, Iv } },
2246   { X86_64_TABLE (X86_64_16) },
2247   { X86_64_TABLE (X86_64_17) },
2248   /* 18 */
2249   { "sbbB",             { Ebh1, Gb } },
2250   { "sbbS",             { Evh1, Gv } },
2251   { "sbbB",             { Gb, EbS } },
2252   { "sbbS",             { Gv, EvS } },
2253   { "sbbB",             { AL, Ib } },
2254   { "sbbS",             { eAX, Iv } },
2255   { X86_64_TABLE (X86_64_1E) },
2256   { X86_64_TABLE (X86_64_1F) },
2257   /* 20 */
2258   { "andB",             { Ebh1, Gb } },
2259   { "andS",             { Evh1, Gv } },
2260   { "andB",             { Gb, EbS } },
2261   { "andS",             { Gv, EvS } },
2262   { "andB",             { AL, Ib } },
2263   { "andS",             { eAX, Iv } },
2264   { Bad_Opcode },       /* SEG ES prefix */
2265   { X86_64_TABLE (X86_64_27) },
2266   /* 28 */
2267   { "subB",             { Ebh1, Gb } },
2268   { "subS",             { Evh1, Gv } },
2269   { "subB",             { Gb, EbS } },
2270   { "subS",             { Gv, EvS } },
2271   { "subB",             { AL, Ib } },
2272   { "subS",             { eAX, Iv } },
2273   { Bad_Opcode },       /* SEG CS prefix */
2274   { X86_64_TABLE (X86_64_2F) },
2275   /* 30 */
2276   { "xorB",             { Ebh1, Gb } },
2277   { "xorS",             { Evh1, Gv } },
2278   { "xorB",             { Gb, EbS } },
2279   { "xorS",             { Gv, EvS } },
2280   { "xorB",             { AL, Ib } },
2281   { "xorS",             { eAX, Iv } },
2282   { Bad_Opcode },       /* SEG SS prefix */
2283   { X86_64_TABLE (X86_64_37) },
2284   /* 38 */
2285   { "cmpB",             { Eb, Gb } },
2286   { "cmpS",             { Ev, Gv } },
2287   { "cmpB",             { Gb, EbS } },
2288   { "cmpS",             { Gv, EvS } },
2289   { "cmpB",             { AL, Ib } },
2290   { "cmpS",             { eAX, Iv } },
2291   { Bad_Opcode },       /* SEG DS prefix */
2292   { X86_64_TABLE (X86_64_3F) },
2293   /* 40 */
2294   { "inc{S|}",          { RMeAX } },
2295   { "inc{S|}",          { RMeCX } },
2296   { "inc{S|}",          { RMeDX } },
2297   { "inc{S|}",          { RMeBX } },
2298   { "inc{S|}",          { RMeSP } },
2299   { "inc{S|}",          { RMeBP } },
2300   { "inc{S|}",          { RMeSI } },
2301   { "inc{S|}",          { RMeDI } },
2302   /* 48 */
2303   { "dec{S|}",          { RMeAX } },
2304   { "dec{S|}",          { RMeCX } },
2305   { "dec{S|}",          { RMeDX } },
2306   { "dec{S|}",          { RMeBX } },
2307   { "dec{S|}",          { RMeSP } },
2308   { "dec{S|}",          { RMeBP } },
2309   { "dec{S|}",          { RMeSI } },
2310   { "dec{S|}",          { RMeDI } },
2311   /* 50 */
2312   { "pushV",            { RMrAX } },
2313   { "pushV",            { RMrCX } },
2314   { "pushV",            { RMrDX } },
2315   { "pushV",            { RMrBX } },
2316   { "pushV",            { RMrSP } },
2317   { "pushV",            { RMrBP } },
2318   { "pushV",            { RMrSI } },
2319   { "pushV",            { RMrDI } },
2320   /* 58 */
2321   { "popV",             { RMrAX } },
2322   { "popV",             { RMrCX } },
2323   { "popV",             { RMrDX } },
2324   { "popV",             { RMrBX } },
2325   { "popV",             { RMrSP } },
2326   { "popV",             { RMrBP } },
2327   { "popV",             { RMrSI } },
2328   { "popV",             { RMrDI } },
2329   /* 60 */
2330   { X86_64_TABLE (X86_64_60) },
2331   { X86_64_TABLE (X86_64_61) },
2332   { X86_64_TABLE (X86_64_62) },
2333   { X86_64_TABLE (X86_64_63) },
2334   { Bad_Opcode },       /* seg fs */
2335   { Bad_Opcode },       /* seg gs */
2336   { Bad_Opcode },       /* op size prefix */
2337   { Bad_Opcode },       /* adr size prefix */
2338   /* 68 */
2339   { "pushT",            { sIv } },
2340   { "imulS",            { Gv, Ev, Iv } },
2341   { "pushT",            { sIbT } },
2342   { "imulS",            { Gv, Ev, sIb } },
2343   { "ins{b|}",          { Ybr, indirDX } },
2344   { X86_64_TABLE (X86_64_6D) },
2345   { "outs{b|}",         { indirDXr, Xb } },
2346   { X86_64_TABLE (X86_64_6F) },
2347   /* 70 */
2348   { "joH",              { Jb, BND, cond_jump_flag } },
2349   { "jnoH",             { Jb, BND, cond_jump_flag } },
2350   { "jbH",              { Jb, BND, cond_jump_flag } },
2351   { "jaeH",             { Jb, BND, cond_jump_flag } },
2352   { "jeH",              { Jb, BND, cond_jump_flag } },
2353   { "jneH",             { Jb, BND, cond_jump_flag } },
2354   { "jbeH",             { Jb, BND, cond_jump_flag } },
2355   { "jaH",              { Jb, BND, cond_jump_flag } },
2356   /* 78 */
2357   { "jsH",              { Jb, BND, cond_jump_flag } },
2358   { "jnsH",             { Jb, BND, cond_jump_flag } },
2359   { "jpH",              { Jb, BND, cond_jump_flag } },
2360   { "jnpH",             { Jb, BND, cond_jump_flag } },
2361   { "jlH",              { Jb, BND, cond_jump_flag } },
2362   { "jgeH",             { Jb, BND, cond_jump_flag } },
2363   { "jleH",             { Jb, BND, cond_jump_flag } },
2364   { "jgH",              { Jb, BND, cond_jump_flag } },
2365   /* 80 */
2366   { REG_TABLE (REG_80) },
2367   { REG_TABLE (REG_81) },
2368   { Bad_Opcode },
2369   { REG_TABLE (REG_82) },
2370   { "testB",            { Eb, Gb } },
2371   { "testS",            { Ev, Gv } },
2372   { "xchgB",            { Ebh2, Gb } },
2373   { "xchgS",            { Evh2, Gv } },
2374   /* 88 */
2375   { "movB",             { Ebh3, Gb } },
2376   { "movS",             { Evh3, Gv } },
2377   { "movB",             { Gb, EbS } },
2378   { "movS",             { Gv, EvS } },
2379   { "movD",             { Sv, Sw } },
2380   { MOD_TABLE (MOD_8D) },
2381   { "movD",             { Sw, Sv } },
2382   { REG_TABLE (REG_8F) },
2383   /* 90 */
2384   { PREFIX_TABLE (PREFIX_90) },
2385   { "xchgS",            { RMeCX, eAX } },
2386   { "xchgS",            { RMeDX, eAX } },
2387   { "xchgS",            { RMeBX, eAX } },
2388   { "xchgS",            { RMeSP, eAX } },
2389   { "xchgS",            { RMeBP, eAX } },
2390   { "xchgS",            { RMeSI, eAX } },
2391   { "xchgS",            { RMeDI, eAX } },
2392   /* 98 */
2393   { "cW{t|}R",          { XX } },
2394   { "cR{t|}O",          { XX } },
2395   { X86_64_TABLE (X86_64_9A) },
2396   { Bad_Opcode },       /* fwait */
2397   { "pushfT",           { XX } },
2398   { "popfT",            { XX } },
2399   { "sahf",             { XX } },
2400   { "lahf",             { XX } },
2401   /* a0 */
2402   { "mov%LB",           { AL, Ob } },
2403   { "mov%LS",           { eAX, Ov } },
2404   { "mov%LB",           { Ob, AL } },
2405   { "mov%LS",           { Ov, eAX } },
2406   { "movs{b|}",         { Ybr, Xb } },
2407   { "movs{R|}",         { Yvr, Xv } },
2408   { "cmps{b|}",         { Xb, Yb } },
2409   { "cmps{R|}",         { Xv, Yv } },
2410   /* a8 */
2411   { "testB",            { AL, Ib } },
2412   { "testS",            { eAX, Iv } },
2413   { "stosB",            { Ybr, AL } },
2414   { "stosS",            { Yvr, eAX } },
2415   { "lodsB",            { ALr, Xb } },
2416   { "lodsS",            { eAXr, Xv } },
2417   { "scasB",            { AL, Yb } },
2418   { "scasS",            { eAX, Yv } },
2419   /* b0 */
2420   { "movB",             { RMAL, Ib } },
2421   { "movB",             { RMCL, Ib } },
2422   { "movB",             { RMDL, Ib } },
2423   { "movB",             { RMBL, Ib } },
2424   { "movB",             { RMAH, Ib } },
2425   { "movB",             { RMCH, Ib } },
2426   { "movB",             { RMDH, Ib } },
2427   { "movB",             { RMBH, Ib } },
2428   /* b8 */
2429   { "mov%LV",           { RMeAX, Iv64 } },
2430   { "mov%LV",           { RMeCX, Iv64 } },
2431   { "mov%LV",           { RMeDX, Iv64 } },
2432   { "mov%LV",           { RMeBX, Iv64 } },
2433   { "mov%LV",           { RMeSP, Iv64 } },
2434   { "mov%LV",           { RMeBP, Iv64 } },
2435   { "mov%LV",           { RMeSI, Iv64 } },
2436   { "mov%LV",           { RMeDI, Iv64 } },
2437   /* c0 */
2438   { REG_TABLE (REG_C0) },
2439   { REG_TABLE (REG_C1) },
2440   { "retT",             { Iw, BND } },
2441   { "retT",             { BND } },
2442   { X86_64_TABLE (X86_64_C4) },
2443   { X86_64_TABLE (X86_64_C5) },
2444   { REG_TABLE (REG_C6) },
2445   { REG_TABLE (REG_C7) },
2446   /* c8 */
2447   { "enterT",           { Iw, Ib } },
2448   { "leaveT",           { XX } },
2449   { "Jret{|f}P",        { Iw } },
2450   { "Jret{|f}P",        { XX } },
2451   { "int3",             { XX } },
2452   { "int",              { Ib } },
2453   { X86_64_TABLE (X86_64_CE) },
2454   { "iretP",            { XX } },
2455   /* d0 */
2456   { REG_TABLE (REG_D0) },
2457   { REG_TABLE (REG_D1) },
2458   { REG_TABLE (REG_D2) },
2459   { REG_TABLE (REG_D3) },
2460   { X86_64_TABLE (X86_64_D4) },
2461   { X86_64_TABLE (X86_64_D5) },
2462   { Bad_Opcode },
2463   { "xlat",             { DSBX } },
2464   /* d8 */
2465   { FLOAT },
2466   { FLOAT },
2467   { FLOAT },
2468   { FLOAT },
2469   { FLOAT },
2470   { FLOAT },
2471   { FLOAT },
2472   { FLOAT },
2473   /* e0 */
2474   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2475   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2476   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2477   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2478   { "inB",              { AL, Ib } },
2479   { "inG",              { zAX, Ib } },
2480   { "outB",             { Ib, AL } },
2481   { "outG",             { Ib, zAX } },
2482   /* e8 */
2483   { "callT",            { Jv, BND } },
2484   { "jmpT",             { Jv, BND } },
2485   { X86_64_TABLE (X86_64_EA) },
2486   { "jmp",              { Jb, BND } },
2487   { "inB",              { AL, indirDX } },
2488   { "inG",              { zAX, indirDX } },
2489   { "outB",             { indirDX, AL } },
2490   { "outG",             { indirDX, zAX } },
2491   /* f0 */
2492   { Bad_Opcode },       /* lock prefix */
2493   { "icebp",            { XX } },
2494   { Bad_Opcode },       /* repne */
2495   { Bad_Opcode },       /* repz */
2496   { "hlt",              { XX } },
2497   { "cmc",              { XX } },
2498   { REG_TABLE (REG_F6) },
2499   { REG_TABLE (REG_F7) },
2500   /* f8 */
2501   { "clc",              { XX } },
2502   { "stc",              { XX } },
2503   { "cli",              { XX } },
2504   { "sti",              { XX } },
2505   { "cld",              { XX } },
2506   { "std",              { XX } },
2507   { REG_TABLE (REG_FE) },
2508   { REG_TABLE (REG_FF) },
2509 };
2510
2511 static const struct dis386 dis386_twobyte[] = {
2512   /* 00 */
2513   { REG_TABLE (REG_0F00 ) },
2514   { REG_TABLE (REG_0F01 ) },
2515   { "larS",             { Gv, Ew } },
2516   { "lslS",             { Gv, Ew } },
2517   { Bad_Opcode },
2518   { "syscall",          { XX } },
2519   { "clts",             { XX } },
2520   { "sysretP",          { XX } },
2521   /* 08 */
2522   { "invd",             { XX } },
2523   { "wbinvd",           { XX } },
2524   { Bad_Opcode },
2525   { "ud2",              { XX } },
2526   { Bad_Opcode },
2527   { REG_TABLE (REG_0F0D) },
2528   { "femms",            { XX } },
2529   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2530   /* 10 */
2531   { PREFIX_TABLE (PREFIX_0F10) },
2532   { PREFIX_TABLE (PREFIX_0F11) },
2533   { PREFIX_TABLE (PREFIX_0F12) },
2534   { MOD_TABLE (MOD_0F13) },
2535   { "unpcklpX",         { XM, EXx } },
2536   { "unpckhpX",         { XM, EXx } },
2537   { PREFIX_TABLE (PREFIX_0F16) },
2538   { MOD_TABLE (MOD_0F17) },
2539   /* 18 */
2540   { REG_TABLE (REG_0F18) },
2541   { "nopQ",             { Ev } },
2542   { PREFIX_TABLE (PREFIX_0F1A) },
2543   { PREFIX_TABLE (PREFIX_0F1B) },
2544   { "nopQ",             { Ev } },
2545   { "nopQ",             { Ev } },
2546   { "nopQ",             { Ev } },
2547   { "nopQ",             { Ev } },
2548   /* 20 */
2549   { MOD_TABLE (MOD_0F20) },
2550   { MOD_TABLE (MOD_0F21) },
2551   { MOD_TABLE (MOD_0F22) },
2552   { MOD_TABLE (MOD_0F23) },
2553   { MOD_TABLE (MOD_0F24) },
2554   { Bad_Opcode },
2555   { MOD_TABLE (MOD_0F26) },
2556   { Bad_Opcode },
2557   /* 28 */
2558   { "movapX",           { XM, EXx } },
2559   { "movapX",           { EXxS, XM } },
2560   { PREFIX_TABLE (PREFIX_0F2A) },
2561   { PREFIX_TABLE (PREFIX_0F2B) },
2562   { PREFIX_TABLE (PREFIX_0F2C) },
2563   { PREFIX_TABLE (PREFIX_0F2D) },
2564   { PREFIX_TABLE (PREFIX_0F2E) },
2565   { PREFIX_TABLE (PREFIX_0F2F) },
2566   /* 30 */
2567   { "wrmsr",            { XX } },
2568   { "rdtsc",            { XX } },
2569   { "rdmsr",            { XX } },
2570   { "rdpmc",            { XX } },
2571   { "sysenter",         { XX } },
2572   { "sysexit",          { XX } },
2573   { Bad_Opcode },
2574   { "getsec",           { XX } },
2575   /* 38 */
2576   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2577   { Bad_Opcode },
2578   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2579   { Bad_Opcode },
2580   { Bad_Opcode },
2581   { Bad_Opcode },
2582   { Bad_Opcode },
2583   { Bad_Opcode },
2584   /* 40 */
2585   { "cmovoS",           { Gv, Ev } },
2586   { "cmovnoS",          { Gv, Ev } },
2587   { "cmovbS",           { Gv, Ev } },
2588   { "cmovaeS",          { Gv, Ev } },
2589   { "cmoveS",           { Gv, Ev } },
2590   { "cmovneS",          { Gv, Ev } },
2591   { "cmovbeS",          { Gv, Ev } },
2592   { "cmovaS",           { Gv, Ev } },
2593   /* 48 */
2594   { "cmovsS",           { Gv, Ev } },
2595   { "cmovnsS",          { Gv, Ev } },
2596   { "cmovpS",           { Gv, Ev } },
2597   { "cmovnpS",          { Gv, Ev } },
2598   { "cmovlS",           { Gv, Ev } },
2599   { "cmovgeS",          { Gv, Ev } },
2600   { "cmovleS",          { Gv, Ev } },
2601   { "cmovgS",           { Gv, Ev } },
2602   /* 50 */
2603   { MOD_TABLE (MOD_0F51) },
2604   { PREFIX_TABLE (PREFIX_0F51) },
2605   { PREFIX_TABLE (PREFIX_0F52) },
2606   { PREFIX_TABLE (PREFIX_0F53) },
2607   { "andpX",            { XM, EXx } },
2608   { "andnpX",           { XM, EXx } },
2609   { "orpX",             { XM, EXx } },
2610   { "xorpX",            { XM, EXx } },
2611   /* 58 */
2612   { PREFIX_TABLE (PREFIX_0F58) },
2613   { PREFIX_TABLE (PREFIX_0F59) },
2614   { PREFIX_TABLE (PREFIX_0F5A) },
2615   { PREFIX_TABLE (PREFIX_0F5B) },
2616   { PREFIX_TABLE (PREFIX_0F5C) },
2617   { PREFIX_TABLE (PREFIX_0F5D) },
2618   { PREFIX_TABLE (PREFIX_0F5E) },
2619   { PREFIX_TABLE (PREFIX_0F5F) },
2620   /* 60 */
2621   { PREFIX_TABLE (PREFIX_0F60) },
2622   { PREFIX_TABLE (PREFIX_0F61) },
2623   { PREFIX_TABLE (PREFIX_0F62) },
2624   { "packsswb",         { MX, EM } },
2625   { "pcmpgtb",          { MX, EM } },
2626   { "pcmpgtw",          { MX, EM } },
2627   { "pcmpgtd",          { MX, EM } },
2628   { "packuswb",         { MX, EM } },
2629   /* 68 */
2630   { "punpckhbw",        { MX, EM } },
2631   { "punpckhwd",        { MX, EM } },
2632   { "punpckhdq",        { MX, EM } },
2633   { "packssdw",         { MX, EM } },
2634   { PREFIX_TABLE (PREFIX_0F6C) },
2635   { PREFIX_TABLE (PREFIX_0F6D) },
2636   { "movK",             { MX, Edq } },
2637   { PREFIX_TABLE (PREFIX_0F6F) },
2638   /* 70 */
2639   { PREFIX_TABLE (PREFIX_0F70) },
2640   { REG_TABLE (REG_0F71) },
2641   { REG_TABLE (REG_0F72) },
2642   { REG_TABLE (REG_0F73) },
2643   { "pcmpeqb",          { MX, EM } },
2644   { "pcmpeqw",          { MX, EM } },
2645   { "pcmpeqd",          { MX, EM } },
2646   { "emms",             { XX } },
2647   /* 78 */
2648   { PREFIX_TABLE (PREFIX_0F78) },
2649   { PREFIX_TABLE (PREFIX_0F79) },
2650   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2651   { Bad_Opcode },
2652   { PREFIX_TABLE (PREFIX_0F7C) },
2653   { PREFIX_TABLE (PREFIX_0F7D) },
2654   { PREFIX_TABLE (PREFIX_0F7E) },
2655   { PREFIX_TABLE (PREFIX_0F7F) },
2656   /* 80 */
2657   { "joH",              { Jv, BND, cond_jump_flag } },
2658   { "jnoH",             { Jv, BND, cond_jump_flag } },
2659   { "jbH",              { Jv, BND, cond_jump_flag } },
2660   { "jaeH",             { Jv, BND, cond_jump_flag } },
2661   { "jeH",              { Jv, BND, cond_jump_flag } },
2662   { "jneH",             { Jv, BND, cond_jump_flag } },
2663   { "jbeH",             { Jv, BND, cond_jump_flag } },
2664   { "jaH",              { Jv, BND, cond_jump_flag } },
2665   /* 88 */
2666   { "jsH",              { Jv, BND, cond_jump_flag } },
2667   { "jnsH",             { Jv, BND, cond_jump_flag } },
2668   { "jpH",              { Jv, BND, cond_jump_flag } },
2669   { "jnpH",             { Jv, BND, cond_jump_flag } },
2670   { "jlH",              { Jv, BND, cond_jump_flag } },
2671   { "jgeH",             { Jv, BND, cond_jump_flag } },
2672   { "jleH",             { Jv, BND, cond_jump_flag } },
2673   { "jgH",              { Jv, BND, cond_jump_flag } },
2674   /* 90 */
2675   { "seto",             { Eb } },
2676   { "setno",            { Eb } },
2677   { "setb",             { Eb } },
2678   { "setae",            { Eb } },
2679   { "sete",             { Eb } },
2680   { "setne",            { Eb } },
2681   { "setbe",            { Eb } },
2682   { "seta",             { Eb } },
2683   /* 98 */
2684   { "sets",             { Eb } },
2685   { "setns",            { Eb } },
2686   { "setp",             { Eb } },
2687   { "setnp",            { Eb } },
2688   { "setl",             { Eb } },
2689   { "setge",            { Eb } },
2690   { "setle",            { Eb } },
2691   { "setg",             { Eb } },
2692   /* a0 */
2693   { "pushT",            { fs } },
2694   { "popT",             { fs } },
2695   { "cpuid",            { XX } },
2696   { "btS",              { Ev, Gv } },
2697   { "shldS",            { Ev, Gv, Ib } },
2698   { "shldS",            { Ev, Gv, CL } },
2699   { REG_TABLE (REG_0FA6) },
2700   { REG_TABLE (REG_0FA7) },
2701   /* a8 */
2702   { "pushT",            { gs } },
2703   { "popT",             { gs } },
2704   { "rsm",              { XX } },
2705   { "btsS",             { Evh1, Gv } },
2706   { "shrdS",            { Ev, Gv, Ib } },
2707   { "shrdS",            { Ev, Gv, CL } },
2708   { REG_TABLE (REG_0FAE) },
2709   { "imulS",            { Gv, Ev } },
2710   /* b0 */
2711   { "cmpxchgB",         { Ebh1, Gb } },
2712   { "cmpxchgS",         { Evh1, Gv } },
2713   { MOD_TABLE (MOD_0FB2) },
2714   { "btrS",             { Evh1, Gv } },
2715   { MOD_TABLE (MOD_0FB4) },
2716   { MOD_TABLE (MOD_0FB5) },
2717   { "movz{bR|x}",       { Gv, Eb } },
2718   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2719   /* b8 */
2720   { PREFIX_TABLE (PREFIX_0FB8) },
2721   { "ud1",              { XX } },
2722   { REG_TABLE (REG_0FBA) },
2723   { "btcS",             { Evh1, Gv } },
2724   { PREFIX_TABLE (PREFIX_0FBC) },
2725   { PREFIX_TABLE (PREFIX_0FBD) },
2726   { "movs{bR|x}",       { Gv, Eb } },
2727   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2728   /* c0 */
2729   { "xaddB",            { Ebh1, Gb } },
2730   { "xaddS",            { Evh1, Gv } },
2731   { PREFIX_TABLE (PREFIX_0FC2) },
2732   { PREFIX_TABLE (PREFIX_0FC3) },
2733   { "pinsrw",           { MX, Edqw, Ib } },
2734   { "pextrw",           { Gdq, MS, Ib } },
2735   { "shufpX",           { XM, EXx, Ib } },
2736   { REG_TABLE (REG_0FC7) },
2737   /* c8 */
2738   { "bswap",            { RMeAX } },
2739   { "bswap",            { RMeCX } },
2740   { "bswap",            { RMeDX } },
2741   { "bswap",            { RMeBX } },
2742   { "bswap",            { RMeSP } },
2743   { "bswap",            { RMeBP } },
2744   { "bswap",            { RMeSI } },
2745   { "bswap",            { RMeDI } },
2746   /* d0 */
2747   { PREFIX_TABLE (PREFIX_0FD0) },
2748   { "psrlw",            { MX, EM } },
2749   { "psrld",            { MX, EM } },
2750   { "psrlq",            { MX, EM } },
2751   { "paddq",            { MX, EM } },
2752   { "pmullw",           { MX, EM } },
2753   { PREFIX_TABLE (PREFIX_0FD6) },
2754   { MOD_TABLE (MOD_0FD7) },
2755   /* d8 */
2756   { "psubusb",          { MX, EM } },
2757   { "psubusw",          { MX, EM } },
2758   { "pminub",           { MX, EM } },
2759   { "pand",             { MX, EM } },
2760   { "paddusb",          { MX, EM } },
2761   { "paddusw",          { MX, EM } },
2762   { "pmaxub",           { MX, EM } },
2763   { "pandn",            { MX, EM } },
2764   /* e0 */
2765   { "pavgb",            { MX, EM } },
2766   { "psraw",            { MX, EM } },
2767   { "psrad",            { MX, EM } },
2768   { "pavgw",            { MX, EM } },
2769   { "pmulhuw",          { MX, EM } },
2770   { "pmulhw",           { MX, EM } },
2771   { PREFIX_TABLE (PREFIX_0FE6) },
2772   { PREFIX_TABLE (PREFIX_0FE7) },
2773   /* e8 */
2774   { "psubsb",           { MX, EM } },
2775   { "psubsw",           { MX, EM } },
2776   { "pminsw",           { MX, EM } },
2777   { "por",              { MX, EM } },
2778   { "paddsb",           { MX, EM } },
2779   { "paddsw",           { MX, EM } },
2780   { "pmaxsw",           { MX, EM } },
2781   { "pxor",             { MX, EM } },
2782   /* f0 */
2783   { PREFIX_TABLE (PREFIX_0FF0) },
2784   { "psllw",            { MX, EM } },
2785   { "pslld",            { MX, EM } },
2786   { "psllq",            { MX, EM } },
2787   { "pmuludq",          { MX, EM } },
2788   { "pmaddwd",          { MX, EM } },
2789   { "psadbw",           { MX, EM } },
2790   { PREFIX_TABLE (PREFIX_0FF7) },
2791   /* f8 */
2792   { "psubb",            { MX, EM } },
2793   { "psubw",            { MX, EM } },
2794   { "psubd",            { MX, EM } },
2795   { "psubq",            { MX, EM } },
2796   { "paddb",            { MX, EM } },
2797   { "paddw",            { MX, EM } },
2798   { "paddd",            { MX, EM } },
2799   { Bad_Opcode },
2800 };
2801
2802 static const unsigned char onebyte_has_modrm[256] = {
2803   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2804   /*       -------------------------------        */
2805   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2821   /*       -------------------------------        */
2822   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2823 };
2824
2825 static const unsigned char twobyte_has_modrm[256] = {
2826   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2827   /*       -------------------------------        */
2828   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2844   /*       -------------------------------        */
2845   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2846 };
2847
2848 static const unsigned char twobyte_has_mandatory_prefix[256] = {
2849   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2850   /*       -------------------------------        */
2851   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
2852   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
2853   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
2854   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2855   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
2856   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2857   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2858   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
2859   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2860   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
2861   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
2862   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
2863   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
2864   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2865   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2866   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2867   /*       -------------------------------        */
2868   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2869 };
2870
2871 static char obuf[100];
2872 static char *obufp;
2873 static char *mnemonicendp;
2874 static char scratchbuf[100];
2875 static unsigned char *start_codep;
2876 static unsigned char *insn_codep;
2877 static unsigned char *codep;
2878 static unsigned char *end_codep;
2879 static int last_lock_prefix;
2880 static int last_repz_prefix;
2881 static int last_repnz_prefix;
2882 static int last_data_prefix;
2883 static int last_addr_prefix;
2884 static int last_rex_prefix;
2885 static int last_seg_prefix;
2886 static int fwait_prefix;
2887 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
2888 static int mandatory_prefix;
2889 /* The active segment register prefix.  */
2890 static int active_seg_prefix;
2891 #define MAX_CODE_LENGTH 15
2892 /* We can up to 14 prefixes since the maximum instruction length is
2893    15bytes.  */
2894 static int all_prefixes[MAX_CODE_LENGTH - 1];
2895 static disassemble_info *the_info;
2896 static struct
2897   {
2898     int mod;
2899     int reg;
2900     int rm;
2901   }
2902 modrm;
2903 static unsigned char need_modrm;
2904 static struct
2905   {
2906     int scale;
2907     int index;
2908     int base;
2909   }
2910 sib;
2911 static struct
2912   {
2913     int register_specifier;
2914     int length;
2915     int prefix;
2916     int w;
2917     int evex;
2918     int r;
2919     int v;
2920     int mask_register_specifier;
2921     int zeroing;
2922     int ll;
2923     int b;
2924   }
2925 vex;
2926 static unsigned char need_vex;
2927 static unsigned char need_vex_reg;
2928 static unsigned char vex_w_done;
2929
2930 struct op
2931   {
2932     const char *name;
2933     unsigned int len;
2934   };
2935
2936 /* If we are accessing mod/rm/reg without need_modrm set, then the
2937    values are stale.  Hitting this abort likely indicates that you
2938    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2939 #define MODRM_CHECK  if (!need_modrm) abort ()
2940
2941 static const char **names64;
2942 static const char **names32;
2943 static const char **names16;
2944 static const char **names8;
2945 static const char **names8rex;
2946 static const char **names_seg;
2947 static const char *index64;
2948 static const char *index32;
2949 static const char **index16;
2950 static const char **names_bnd;
2951
2952 static const char *intel_names64[] = {
2953   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2954   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2955 };
2956 static const char *intel_names32[] = {
2957   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2958   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2959 };
2960 static const char *intel_names16[] = {
2961   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2962   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2963 };
2964 static const char *intel_names8[] = {
2965   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2966 };
2967 static const char *intel_names8rex[] = {
2968   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2969   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2970 };
2971 static const char *intel_names_seg[] = {
2972   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2973 };
2974 static const char *intel_index64 = "riz";
2975 static const char *intel_index32 = "eiz";
2976 static const char *intel_index16[] = {
2977   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2978 };
2979
2980 static const char *att_names64[] = {
2981   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2982   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2983 };
2984 static const char *att_names32[] = {
2985   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2986   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2987 };
2988 static const char *att_names16[] = {
2989   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2990   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2991 };
2992 static const char *att_names8[] = {
2993   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2994 };
2995 static const char *att_names8rex[] = {
2996   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2997   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2998 };
2999 static const char *att_names_seg[] = {
3000   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3001 };
3002 static const char *att_index64 = "%riz";
3003 static const char *att_index32 = "%eiz";
3004 static const char *att_index16[] = {
3005   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3006 };
3007
3008 static const char **names_mm;
3009 static const char *intel_names_mm[] = {
3010   "mm0", "mm1", "mm2", "mm3",
3011   "mm4", "mm5", "mm6", "mm7"
3012 };
3013 static const char *att_names_mm[] = {
3014   "%mm0", "%mm1", "%mm2", "%mm3",
3015   "%mm4", "%mm5", "%mm6", "%mm7"
3016 };
3017
3018 static const char *intel_names_bnd[] = {
3019   "bnd0", "bnd1", "bnd2", "bnd3"
3020 };
3021
3022 static const char *att_names_bnd[] = {
3023   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3024 };
3025
3026 static const char **names_xmm;
3027 static const char *intel_names_xmm[] = {
3028   "xmm0", "xmm1", "xmm2", "xmm3",
3029   "xmm4", "xmm5", "xmm6", "xmm7",
3030   "xmm8", "xmm9", "xmm10", "xmm11",
3031   "xmm12", "xmm13", "xmm14", "xmm15",
3032   "xmm16", "xmm17", "xmm18", "xmm19",
3033   "xmm20", "xmm21", "xmm22", "xmm23",
3034   "xmm24", "xmm25", "xmm26", "xmm27",
3035   "xmm28", "xmm29", "xmm30", "xmm31"
3036 };
3037 static const char *att_names_xmm[] = {
3038   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3039   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3040   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3041   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3042   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3043   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3044   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3045   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3046 };
3047
3048 static const char **names_ymm;
3049 static const char *intel_names_ymm[] = {
3050   "ymm0", "ymm1", "ymm2", "ymm3",
3051   "ymm4", "ymm5", "ymm6", "ymm7",
3052   "ymm8", "ymm9", "ymm10", "ymm11",
3053   "ymm12", "ymm13", "ymm14", "ymm15",
3054   "ymm16", "ymm17", "ymm18", "ymm19",
3055   "ymm20", "ymm21", "ymm22", "ymm23",
3056   "ymm24", "ymm25", "ymm26", "ymm27",
3057   "ymm28", "ymm29", "ymm30", "ymm31"
3058 };
3059 static const char *att_names_ymm[] = {
3060   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3061   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3062   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3063   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3064   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3065   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3066   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3067   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3068 };
3069
3070 static const char **names_zmm;
3071 static const char *intel_names_zmm[] = {
3072   "zmm0", "zmm1", "zmm2", "zmm3",
3073   "zmm4", "zmm5", "zmm6", "zmm7",
3074   "zmm8", "zmm9", "zmm10", "zmm11",
3075   "zmm12", "zmm13", "zmm14", "zmm15",
3076   "zmm16", "zmm17", "zmm18", "zmm19",
3077   "zmm20", "zmm21", "zmm22", "zmm23",
3078   "zmm24", "zmm25", "zmm26", "zmm27",
3079   "zmm28", "zmm29", "zmm30", "zmm31"
3080 };
3081 static const char *att_names_zmm[] = {
3082   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3083   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3084   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3085   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3086   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3087   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3088   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3089   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3090 };
3091
3092 static const char **names_mask;
3093 static const char *intel_names_mask[] = {
3094   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3095 };
3096 static const char *att_names_mask[] = {
3097   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3098 };
3099
3100 static const char *names_rounding[] =
3101 {
3102   "{rn-sae}",
3103   "{rd-sae}",
3104   "{ru-sae}",
3105   "{rz-sae}"
3106 };
3107
3108 static const struct dis386 reg_table[][8] = {
3109   /* REG_80 */
3110   {
3111     { "addA",   { Ebh1, Ib } },
3112     { "orA",    { Ebh1, Ib } },
3113     { "adcA",   { Ebh1, Ib } },
3114     { "sbbA",   { Ebh1, Ib } },
3115     { "andA",   { Ebh1, Ib } },
3116     { "subA",   { Ebh1, Ib } },
3117     { "xorA",   { Ebh1, Ib } },
3118     { "cmpA",   { Eb, Ib } },
3119   },
3120   /* REG_81 */
3121   {
3122     { "addQ",   { Evh1, Iv } },
3123     { "orQ",    { Evh1, Iv } },
3124     { "adcQ",   { Evh1, Iv } },
3125     { "sbbQ",   { Evh1, Iv } },
3126     { "andQ",   { Evh1, Iv } },
3127     { "subQ",   { Evh1, Iv } },
3128     { "xorQ",   { Evh1, Iv } },
3129     { "cmpQ",   { Ev, Iv } },
3130   },
3131   /* REG_82 */
3132   {
3133     { "addQ",   { Evh1, sIb } },
3134     { "orQ",    { Evh1, sIb } },
3135     { "adcQ",   { Evh1, sIb } },
3136     { "sbbQ",   { Evh1, sIb } },
3137     { "andQ",   { Evh1, sIb } },
3138     { "subQ",   { Evh1, sIb } },
3139     { "xorQ",   { Evh1, sIb } },
3140     { "cmpQ",   { Ev, sIb } },
3141   },
3142   /* REG_8F */
3143   {
3144     { "popU",   { stackEv } },
3145     { XOP_8F_TABLE (XOP_09) },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { Bad_Opcode },
3149     { XOP_8F_TABLE (XOP_09) },
3150   },
3151   /* REG_C0 */
3152   {
3153     { "rolA",   { Eb, Ib } },
3154     { "rorA",   { Eb, Ib } },
3155     { "rclA",   { Eb, Ib } },
3156     { "rcrA",   { Eb, Ib } },
3157     { "shlA",   { Eb, Ib } },
3158     { "shrA",   { Eb, Ib } },
3159     { Bad_Opcode },
3160     { "sarA",   { Eb, Ib } },
3161   },
3162   /* REG_C1 */
3163   {
3164     { "rolQ",   { Ev, Ib } },
3165     { "rorQ",   { Ev, Ib } },
3166     { "rclQ",   { Ev, Ib } },
3167     { "rcrQ",   { Ev, Ib } },
3168     { "shlQ",   { Ev, Ib } },
3169     { "shrQ",   { Ev, Ib } },
3170     { Bad_Opcode },
3171     { "sarQ",   { Ev, Ib } },
3172   },
3173   /* REG_C6 */
3174   {
3175     { "movA",   { Ebh3, Ib } },
3176     { Bad_Opcode },
3177     { Bad_Opcode },
3178     { Bad_Opcode },
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { Bad_Opcode },
3182     { MOD_TABLE (MOD_C6_REG_7) },
3183   },
3184   /* REG_C7 */
3185   {
3186     { "movQ",   { Evh3, Iv } },
3187     { Bad_Opcode },
3188     { Bad_Opcode },
3189     { Bad_Opcode },
3190     { Bad_Opcode },
3191     { Bad_Opcode },
3192     { Bad_Opcode },
3193     { MOD_TABLE (MOD_C7_REG_7) },
3194   },
3195   /* REG_D0 */
3196   {
3197     { "rolA",   { Eb, I1 } },
3198     { "rorA",   { Eb, I1 } },
3199     { "rclA",   { Eb, I1 } },
3200     { "rcrA",   { Eb, I1 } },
3201     { "shlA",   { Eb, I1 } },
3202     { "shrA",   { Eb, I1 } },
3203     { Bad_Opcode },
3204     { "sarA",   { Eb, I1 } },
3205   },
3206   /* REG_D1 */
3207   {
3208     { "rolQ",   { Ev, I1 } },
3209     { "rorQ",   { Ev, I1 } },
3210     { "rclQ",   { Ev, I1 } },
3211     { "rcrQ",   { Ev, I1 } },
3212     { "shlQ",   { Ev, I1 } },
3213     { "shrQ",   { Ev, I1 } },
3214     { Bad_Opcode },
3215     { "sarQ",   { Ev, I1 } },
3216   },
3217   /* REG_D2 */
3218   {
3219     { "rolA",   { Eb, CL } },
3220     { "rorA",   { Eb, CL } },
3221     { "rclA",   { Eb, CL } },
3222     { "rcrA",   { Eb, CL } },
3223     { "shlA",   { Eb, CL } },
3224     { "shrA",   { Eb, CL } },
3225     { Bad_Opcode },
3226     { "sarA",   { Eb, CL } },
3227   },
3228   /* REG_D3 */
3229   {
3230     { "rolQ",   { Ev, CL } },
3231     { "rorQ",   { Ev, CL } },
3232     { "rclQ",   { Ev, CL } },
3233     { "rcrQ",   { Ev, CL } },
3234     { "shlQ",   { Ev, CL } },
3235     { "shrQ",   { Ev, CL } },
3236     { Bad_Opcode },
3237     { "sarQ",   { Ev, CL } },
3238   },
3239   /* REG_F6 */
3240   {
3241     { "testA",  { Eb, Ib } },
3242     { Bad_Opcode },
3243     { "notA",   { Ebh1 } },
3244     { "negA",   { Ebh1 } },
3245     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3246     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3247     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3248     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3249   },
3250   /* REG_F7 */
3251   {
3252     { "testQ",  { Ev, Iv } },
3253     { Bad_Opcode },
3254     { "notQ",   { Evh1 } },
3255     { "negQ",   { Evh1 } },
3256     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3257     { "imulQ",  { Ev } },
3258     { "divQ",   { Ev } },
3259     { "idivQ",  { Ev } },
3260   },
3261   /* REG_FE */
3262   {
3263     { "incA",   { Ebh1 } },
3264     { "decA",   { Ebh1 } },
3265   },
3266   /* REG_FF */
3267   {
3268     { "incQ",   { Evh1 } },
3269     { "decQ",   { Evh1 } },
3270     { "call{T|}", { indirEv, BND } },
3271     { MOD_TABLE (MOD_FF_REG_3) },
3272     { "jmp{T|}", { indirEv, BND } },
3273     { MOD_TABLE (MOD_FF_REG_5) },
3274     { "pushU",  { stackEv } },
3275     { Bad_Opcode },
3276   },
3277   /* REG_0F00 */
3278   {
3279     { "sldtD",  { Sv } },
3280     { "strD",   { Sv } },
3281     { "lldt",   { Ew } },
3282     { "ltr",    { Ew } },
3283     { "verr",   { Ew } },
3284     { "verw",   { Ew } },
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287   },
3288   /* REG_0F01 */
3289   {
3290     { MOD_TABLE (MOD_0F01_REG_0) },
3291     { MOD_TABLE (MOD_0F01_REG_1) },
3292     { MOD_TABLE (MOD_0F01_REG_2) },
3293     { MOD_TABLE (MOD_0F01_REG_3) },
3294     { "smswD",  { Sv } },
3295     { Bad_Opcode },
3296     { "lmsw",   { Ew } },
3297     { MOD_TABLE (MOD_0F01_REG_7) },
3298   },
3299   /* REG_0F0D */
3300   {
3301     { "prefetch",       { Mb } },
3302     { "prefetchw",      { Mb } },
3303     { "prefetchwt1",    { Mb } },
3304     { "prefetch",       { Mb } },
3305     { "prefetch",       { Mb } },
3306     { "prefetch",       { Mb } },
3307     { "prefetch",       { Mb } },
3308     { "prefetch",       { Mb } },
3309   },
3310   /* REG_0F18 */
3311   {
3312     { MOD_TABLE (MOD_0F18_REG_0) },
3313     { MOD_TABLE (MOD_0F18_REG_1) },
3314     { MOD_TABLE (MOD_0F18_REG_2) },
3315     { MOD_TABLE (MOD_0F18_REG_3) },
3316     { MOD_TABLE (MOD_0F18_REG_4) },
3317     { MOD_TABLE (MOD_0F18_REG_5) },
3318     { MOD_TABLE (MOD_0F18_REG_6) },
3319     { MOD_TABLE (MOD_0F18_REG_7) },
3320   },
3321   /* REG_0F71 */
3322   {
3323     { Bad_Opcode },
3324     { Bad_Opcode },
3325     { MOD_TABLE (MOD_0F71_REG_2) },
3326     { Bad_Opcode },
3327     { MOD_TABLE (MOD_0F71_REG_4) },
3328     { Bad_Opcode },
3329     { MOD_TABLE (MOD_0F71_REG_6) },
3330   },
3331   /* REG_0F72 */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { MOD_TABLE (MOD_0F72_REG_2) },
3336     { Bad_Opcode },
3337     { MOD_TABLE (MOD_0F72_REG_4) },
3338     { Bad_Opcode },
3339     { MOD_TABLE (MOD_0F72_REG_6) },
3340   },
3341   /* REG_0F73 */
3342   {
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { MOD_TABLE (MOD_0F73_REG_2) },
3346     { MOD_TABLE (MOD_0F73_REG_3) },
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { MOD_TABLE (MOD_0F73_REG_6) },
3350     { MOD_TABLE (MOD_0F73_REG_7) },
3351   },
3352   /* REG_0FA6 */
3353   {
3354     { "montmul",        { { OP_0f07, 0 } } },
3355     { "xsha1",          { { OP_0f07, 0 } } },
3356     { "xsha256",        { { OP_0f07, 0 } } },
3357   },
3358   /* REG_0FA7 */
3359   {
3360     { "xstore-rng",     { { OP_0f07, 0 } } },
3361     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3362     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3363     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3364     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3365     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3366   },
3367   /* REG_0FAE */
3368   {
3369     { MOD_TABLE (MOD_0FAE_REG_0) },
3370     { MOD_TABLE (MOD_0FAE_REG_1) },
3371     { MOD_TABLE (MOD_0FAE_REG_2) },
3372     { MOD_TABLE (MOD_0FAE_REG_3) },
3373     { MOD_TABLE (MOD_0FAE_REG_4) },
3374     { MOD_TABLE (MOD_0FAE_REG_5) },
3375     { MOD_TABLE (MOD_0FAE_REG_6) },
3376     { MOD_TABLE (MOD_0FAE_REG_7) },
3377   },
3378   /* REG_0FBA */
3379   {
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { "btQ",    { Ev, Ib } },
3385     { "btsQ",   { Evh1, Ib } },
3386     { "btrQ",   { Evh1, Ib } },
3387     { "btcQ",   { Evh1, Ib } },
3388   },
3389   /* REG_0FC7 */
3390   {
3391     { Bad_Opcode },
3392     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3393     { Bad_Opcode },
3394     { MOD_TABLE (MOD_0FC7_REG_3) },
3395     { MOD_TABLE (MOD_0FC7_REG_4) },
3396     { MOD_TABLE (MOD_0FC7_REG_5) },
3397     { MOD_TABLE (MOD_0FC7_REG_6) },
3398     { MOD_TABLE (MOD_0FC7_REG_7) },
3399   },
3400   /* REG_VEX_0F71 */
3401   {
3402     { Bad_Opcode },
3403     { Bad_Opcode },
3404     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3407     { Bad_Opcode },
3408     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3409   },
3410   /* REG_VEX_0F72 */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3415     { Bad_Opcode },
3416     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3417     { Bad_Opcode },
3418     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3419   },
3420   /* REG_VEX_0F73 */
3421   {
3422     { Bad_Opcode },
3423     { Bad_Opcode },
3424     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3425     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3429     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3430   },
3431   /* REG_VEX_0FAE */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3436     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3437   },
3438   /* REG_VEX_0F38F3 */
3439   {
3440     { Bad_Opcode },
3441     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3442     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3443     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3444   },
3445   /* REG_XOP_LWPCB */
3446   {
3447     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3448     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3449   },
3450   /* REG_XOP_LWP */
3451   {
3452     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3453     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3454   },
3455   /* REG_XOP_TBM_01 */
3456   {
3457     { Bad_Opcode },
3458     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3459     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3460     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3461     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3462     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3463     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3464     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3465   },
3466   /* REG_XOP_TBM_02 */
3467   {
3468     { Bad_Opcode },
3469     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3475   },
3476 #define NEED_REG_TABLE
3477 #include "i386-dis-evex.h"
3478 #undef NEED_REG_TABLE
3479 };
3480
3481 static const struct dis386 prefix_table[][4] = {
3482   /* PREFIX_90 */
3483   {
3484     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3485     { "pause", { XX } },
3486     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3487   },
3488
3489   /* PREFIX_0F10 */
3490   {
3491     { "movups", { XM, EXx } },
3492     { "movss",  { XM, EXd } },
3493     { "movupd", { XM, EXx } },
3494     { "movsd",  { XM, EXq } },
3495   },
3496
3497   /* PREFIX_0F11 */
3498   {
3499     { "movups", { EXxS, XM } },
3500     { "movss",  { EXdS, XM } },
3501     { "movupd", { EXxS, XM } },
3502     { "movsd",  { EXqS, XM } },
3503   },
3504
3505   /* PREFIX_0F12 */
3506   {
3507     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3508     { "movsldup", { XM, EXx } },
3509     { "movlpd", { XM, EXq } },
3510     { "movddup", { XM, EXq } },
3511   },
3512
3513   /* PREFIX_0F16 */
3514   {
3515     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3516     { "movshdup", { XM, EXx } },
3517     { "movhpd", { XM, EXq } },
3518   },
3519
3520   /* PREFIX_0F1A */
3521   {
3522     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3523     { "bndcl",  { Gbnd, Ev_bnd } },
3524     { "bndmov", { Gbnd, Ebnd } },
3525     { "bndcu",  { Gbnd, Ev_bnd } },
3526   },
3527
3528   /* PREFIX_0F1B */
3529   {
3530     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3531     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3532     { "bndmov", { Ebnd, Gbnd } },
3533     { "bndcn",  { Gbnd, Ev_bnd } },
3534   },
3535
3536   /* PREFIX_0F2A */
3537   {
3538     { "cvtpi2ps", { XM, EMCq } },
3539     { "cvtsi2ss%LQ", { XM, Ev } },
3540     { "cvtpi2pd", { XM, EMCq } },
3541     { "cvtsi2sd%LQ", { XM, Ev } },
3542   },
3543
3544   /* PREFIX_0F2B */
3545   {
3546     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3547     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3548     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3549     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3550   },
3551
3552   /* PREFIX_0F2C */
3553   {
3554     { "cvttps2pi", { MXC, EXq } },
3555     { "cvttss2siY", { Gv, EXd } },
3556     { "cvttpd2pi", { MXC, EXx } },
3557     { "cvttsd2siY", { Gv, EXq } },
3558   },
3559
3560   /* PREFIX_0F2D */
3561   {
3562     { "cvtps2pi", { MXC, EXq } },
3563     { "cvtss2siY", { Gv, EXd } },
3564     { "cvtpd2pi", { MXC, EXx } },
3565     { "cvtsd2siY", { Gv, EXq } },
3566   },
3567
3568   /* PREFIX_0F2E */
3569   {
3570     { "ucomiss",{ XM, EXd } },
3571     { Bad_Opcode },
3572     { "ucomisd",{ XM, EXq } },
3573   },
3574
3575   /* PREFIX_0F2F */
3576   {
3577     { "comiss", { XM, EXd } },
3578     { Bad_Opcode },
3579     { "comisd", { XM, EXq } },
3580   },
3581
3582   /* PREFIX_0F51 */
3583   {
3584     { "sqrtps", { XM, EXx } },
3585     { "sqrtss", { XM, EXd } },
3586     { "sqrtpd", { XM, EXx } },
3587     { "sqrtsd", { XM, EXq } },
3588   },
3589
3590   /* PREFIX_0F52 */
3591   {
3592     { "rsqrtps",{ XM, EXx } },
3593     { "rsqrtss",{ XM, EXd } },
3594   },
3595
3596   /* PREFIX_0F53 */
3597   {
3598     { "rcpps",  { XM, EXx } },
3599     { "rcpss",  { XM, EXd } },
3600   },
3601
3602   /* PREFIX_0F58 */
3603   {
3604     { "addps", { XM, EXx } },
3605     { "addss", { XM, EXd } },
3606     { "addpd", { XM, EXx } },
3607     { "addsd", { XM, EXq } },
3608   },
3609
3610   /* PREFIX_0F59 */
3611   {
3612     { "mulps",  { XM, EXx } },
3613     { "mulss",  { XM, EXd } },
3614     { "mulpd",  { XM, EXx } },
3615     { "mulsd",  { XM, EXq } },
3616   },
3617
3618   /* PREFIX_0F5A */
3619   {
3620     { "cvtps2pd", { XM, EXq } },
3621     { "cvtss2sd", { XM, EXd } },
3622     { "cvtpd2ps", { XM, EXx } },
3623     { "cvtsd2ss", { XM, EXq } },
3624   },
3625
3626   /* PREFIX_0F5B */
3627   {
3628     { "cvtdq2ps", { XM, EXx } },
3629     { "cvttps2dq", { XM, EXx } },
3630     { "cvtps2dq", { XM, EXx } },
3631   },
3632
3633   /* PREFIX_0F5C */
3634   {
3635     { "subps",  { XM, EXx } },
3636     { "subss",  { XM, EXd } },
3637     { "subpd",  { XM, EXx } },
3638     { "subsd",  { XM, EXq } },
3639   },
3640
3641   /* PREFIX_0F5D */
3642   {
3643     { "minps",  { XM, EXx } },
3644     { "minss",  { XM, EXd } },
3645     { "minpd",  { XM, EXx } },
3646     { "minsd",  { XM, EXq } },
3647   },
3648
3649   /* PREFIX_0F5E */
3650   {
3651     { "divps",  { XM, EXx } },
3652     { "divss",  { XM, EXd } },
3653     { "divpd",  { XM, EXx } },
3654     { "divsd",  { XM, EXq } },
3655   },
3656
3657   /* PREFIX_0F5F */
3658   {
3659     { "maxps",  { XM, EXx } },
3660     { "maxss",  { XM, EXd } },
3661     { "maxpd",  { XM, EXx } },
3662     { "maxsd",  { XM, EXq } },
3663   },
3664
3665   /* PREFIX_0F60 */
3666   {
3667     { "punpcklbw",{ MX, EMd } },
3668     { Bad_Opcode },
3669     { "punpcklbw",{ MX, EMx } },
3670   },
3671
3672   /* PREFIX_0F61 */
3673   {
3674     { "punpcklwd",{ MX, EMd } },
3675     { Bad_Opcode },
3676     { "punpcklwd",{ MX, EMx } },
3677   },
3678
3679   /* PREFIX_0F62 */
3680   {
3681     { "punpckldq",{ MX, EMd } },
3682     { Bad_Opcode },
3683     { "punpckldq",{ MX, EMx } },
3684   },
3685
3686   /* PREFIX_0F6C */
3687   {
3688     { Bad_Opcode },
3689     { Bad_Opcode },
3690     { "punpcklqdq", { XM, EXx } },
3691   },
3692
3693   /* PREFIX_0F6D */
3694   {
3695     { Bad_Opcode },
3696     { Bad_Opcode },
3697     { "punpckhqdq", { XM, EXx } },
3698   },
3699
3700   /* PREFIX_0F6F */
3701   {
3702     { "movq",   { MX, EM } },
3703     { "movdqu", { XM, EXx } },
3704     { "movdqa", { XM, EXx } },
3705   },
3706
3707   /* PREFIX_0F70 */
3708   {
3709     { "pshufw", { MX, EM, Ib } },
3710     { "pshufhw",{ XM, EXx, Ib } },
3711     { "pshufd", { XM, EXx, Ib } },
3712     { "pshuflw",{ XM, EXx, Ib } },
3713   },
3714
3715   /* PREFIX_0F73_REG_3 */
3716   {
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { "psrldq", { XS, Ib } },
3720   },
3721
3722   /* PREFIX_0F73_REG_7 */
3723   {
3724     { Bad_Opcode },
3725     { Bad_Opcode },
3726     { "pslldq", { XS, Ib } },
3727   },
3728
3729   /* PREFIX_0F78 */
3730   {
3731     {"vmread",  { Em, Gm } },
3732     { Bad_Opcode },
3733     {"extrq",   { XS, Ib, Ib } },
3734     {"insertq", { XM, XS, Ib, Ib } },
3735   },
3736
3737   /* PREFIX_0F79 */
3738   {
3739     {"vmwrite", { Gm, Em } },
3740     { Bad_Opcode },
3741     {"extrq",   { XM, XS } },
3742     {"insertq", { XM, XS } },
3743   },
3744
3745   /* PREFIX_0F7C */
3746   {
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { "haddpd", { XM, EXx } },
3750     { "haddps", { XM, EXx } },
3751   },
3752
3753   /* PREFIX_0F7D */
3754   {
3755     { Bad_Opcode },
3756     { Bad_Opcode },
3757     { "hsubpd", { XM, EXx } },
3758     { "hsubps", { XM, EXx } },
3759   },
3760
3761   /* PREFIX_0F7E */
3762   {
3763     { "movK",   { Edq, MX } },
3764     { "movq",   { XM, EXq } },
3765     { "movK",   { Edq, XM } },
3766   },
3767
3768   /* PREFIX_0F7F */
3769   {
3770     { "movq",   { EMS, MX } },
3771     { "movdqu", { EXxS, XM } },
3772     { "movdqa", { EXxS, XM } },
3773   },
3774
3775   /* PREFIX_0FAE_REG_0 */
3776   {
3777     { Bad_Opcode },
3778     { "rdfsbase", { Ev } },
3779   },
3780
3781   /* PREFIX_0FAE_REG_1 */
3782   {
3783     { Bad_Opcode },
3784     { "rdgsbase", { Ev } },
3785   },
3786
3787   /* PREFIX_0FAE_REG_2 */
3788   {
3789     { Bad_Opcode },
3790     { "wrfsbase", { Ev } },
3791   },
3792
3793   /* PREFIX_0FAE_REG_3 */
3794   {
3795     { Bad_Opcode },
3796     { "wrgsbase", { Ev } },
3797   },
3798
3799   /* PREFIX_0FAE_REG_7 */
3800   {
3801     { "clflush",        { Mb } },
3802     { Bad_Opcode },
3803     { "clflushopt",     { Mb } },
3804   },
3805
3806   /* PREFIX_0FB8 */
3807   {
3808     { Bad_Opcode },
3809     { "popcntS", { Gv, Ev } },
3810   },
3811
3812   /* PREFIX_0FBC */
3813   {
3814     { "bsfS",   { Gv, Ev } },
3815     { "tzcntS", { Gv, Ev } },
3816     { "bsfS",   { Gv, Ev } },
3817   },
3818
3819   /* PREFIX_0FBD */
3820   {
3821     { "bsrS",   { Gv, Ev } },
3822     { "lzcntS", { Gv, Ev } },
3823     { "bsrS",   { Gv, Ev } },
3824   },
3825
3826   /* PREFIX_0FC2 */
3827   {
3828     { "cmpps",  { XM, EXx, CMP } },
3829     { "cmpss",  { XM, EXd, CMP } },
3830     { "cmppd",  { XM, EXx, CMP } },
3831     { "cmpsd",  { XM, EXq, CMP } },
3832   },
3833
3834   /* PREFIX_0FC3 */
3835   {
3836     { "movntiS", { Ma, Gv } },
3837   },
3838
3839   /* PREFIX_0FC7_REG_6 */
3840   {
3841     { "vmptrld",{ Mq } },
3842     { "vmxon",  { Mq } },
3843     { "vmclear",{ Mq } },
3844   },
3845
3846   /* PREFIX_0FD0 */
3847   {
3848     { Bad_Opcode },
3849     { Bad_Opcode },
3850     { "addsubpd", { XM, EXx } },
3851     { "addsubps", { XM, EXx } },
3852   },
3853
3854   /* PREFIX_0FD6 */
3855   {
3856     { Bad_Opcode },
3857     { "movq2dq",{ XM, MS } },
3858     { "movq",   { EXqS, XM } },
3859     { "movdq2q",{ MX, XS } },
3860   },
3861
3862   /* PREFIX_0FE6 */
3863   {
3864     { Bad_Opcode },
3865     { "cvtdq2pd", { XM, EXq } },
3866     { "cvttpd2dq", { XM, EXx } },
3867     { "cvtpd2dq", { XM, EXx } },
3868   },
3869
3870   /* PREFIX_0FE7 */
3871   {
3872     { "movntq", { Mq, MX } },
3873     { Bad_Opcode },
3874     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3875   },
3876
3877   /* PREFIX_0FF0 */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3883   },
3884
3885   /* PREFIX_0FF7 */
3886   {
3887     { "maskmovq", { MX, MS } },
3888     { Bad_Opcode },
3889     { "maskmovdqu", { XM, XS } },
3890   },
3891
3892   /* PREFIX_0F3810 */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "pblendvb", { XM, EXx, XMM0 } },
3897   },
3898
3899   /* PREFIX_0F3814 */
3900   {
3901     { Bad_Opcode },
3902     { Bad_Opcode },
3903     { "blendvps", { XM, EXx, XMM0 } },
3904   },
3905
3906   /* PREFIX_0F3815 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "blendvpd", { XM, EXx, XMM0 } },
3911   },
3912
3913   /* PREFIX_0F3817 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { "ptest",  { XM, EXx } },
3918   },
3919
3920   /* PREFIX_0F3820 */
3921   {
3922     { Bad_Opcode },
3923     { Bad_Opcode },
3924     { "pmovsxbw", { XM, EXq } },
3925   },
3926
3927   /* PREFIX_0F3821 */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { "pmovsxbd", { XM, EXd } },
3932   },
3933
3934   /* PREFIX_0F3822 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "pmovsxbq", { XM, EXw } },
3939   },
3940
3941   /* PREFIX_0F3823 */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { "pmovsxwd", { XM, EXq } },
3946   },
3947
3948   /* PREFIX_0F3824 */
3949   {
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { "pmovsxwq", { XM, EXd } },
3953   },
3954
3955   /* PREFIX_0F3825 */
3956   {
3957     { Bad_Opcode },
3958     { Bad_Opcode },
3959     { "pmovsxdq", { XM, EXq } },
3960   },
3961
3962   /* PREFIX_0F3828 */
3963   {
3964     { Bad_Opcode },
3965     { Bad_Opcode },
3966     { "pmuldq", { XM, EXx } },
3967   },
3968
3969   /* PREFIX_0F3829 */
3970   {
3971     { Bad_Opcode },
3972     { Bad_Opcode },
3973     { "pcmpeqq", { XM, EXx } },
3974   },
3975
3976   /* PREFIX_0F382A */
3977   {
3978     { Bad_Opcode },
3979     { Bad_Opcode },
3980     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3981   },
3982
3983   /* PREFIX_0F382B */
3984   {
3985     { Bad_Opcode },
3986     { Bad_Opcode },
3987     { "packusdw", { XM, EXx } },
3988   },
3989
3990   /* PREFIX_0F3830 */
3991   {
3992     { Bad_Opcode },
3993     { Bad_Opcode },
3994     { "pmovzxbw", { XM, EXq } },
3995   },
3996
3997   /* PREFIX_0F3831 */
3998   {
3999     { Bad_Opcode },
4000     { Bad_Opcode },
4001     { "pmovzxbd", { XM, EXd } },
4002   },
4003
4004   /* PREFIX_0F3832 */
4005   {
4006     { Bad_Opcode },
4007     { Bad_Opcode },
4008     { "pmovzxbq", { XM, EXw } },
4009   },
4010
4011   /* PREFIX_0F3833 */
4012   {
4013     { Bad_Opcode },
4014     { Bad_Opcode },
4015     { "pmovzxwd", { XM, EXq } },
4016   },
4017
4018   /* PREFIX_0F3834 */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { "pmovzxwq", { XM, EXd } },
4023   },
4024
4025   /* PREFIX_0F3835 */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { "pmovzxdq", { XM, EXq } },
4030   },
4031
4032   /* PREFIX_0F3837 */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { "pcmpgtq", { XM, EXx } },
4037   },
4038
4039   /* PREFIX_0F3838 */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { "pminsb", { XM, EXx } },
4044   },
4045
4046   /* PREFIX_0F3839 */
4047   {
4048     { Bad_Opcode },
4049     { Bad_Opcode },
4050     { "pminsd", { XM, EXx } },
4051   },
4052
4053   /* PREFIX_0F383A */
4054   {
4055     { Bad_Opcode },
4056     { Bad_Opcode },
4057     { "pminuw", { XM, EXx } },
4058   },
4059
4060   /* PREFIX_0F383B */
4061   {
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { "pminud", { XM, EXx } },
4065   },
4066
4067   /* PREFIX_0F383C */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "pmaxsb", { XM, EXx } },
4072   },
4073
4074   /* PREFIX_0F383D */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { "pmaxsd", { XM, EXx } },
4079   },
4080
4081   /* PREFIX_0F383E */
4082   {
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { "pmaxuw", { XM, EXx } },
4086   },
4087
4088   /* PREFIX_0F383F */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { "pmaxud", { XM, EXx } },
4093   },
4094
4095   /* PREFIX_0F3840 */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { "pmulld", { XM, EXx } },
4100   },
4101
4102   /* PREFIX_0F3841 */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { "phminposuw", { XM, EXx } },
4107   },
4108
4109   /* PREFIX_0F3880 */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { "invept", { Gm, Mo } },
4114   },
4115
4116   /* PREFIX_0F3881 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "invvpid", { Gm, Mo } },
4121   },
4122
4123   /* PREFIX_0F3882 */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "invpcid", { Gm, M } },
4128   },
4129
4130   /* PREFIX_0F38C8 */
4131   {
4132     { "sha1nexte", { XM, EXxmm } },
4133   },
4134
4135   /* PREFIX_0F38C9 */
4136   {
4137     { "sha1msg1", { XM, EXxmm } },
4138   },
4139
4140   /* PREFIX_0F38CA */
4141   {
4142     { "sha1msg2", { XM, EXxmm } },
4143   },
4144
4145   /* PREFIX_0F38CB */
4146   {
4147     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4148   },
4149
4150   /* PREFIX_0F38CC */
4151   {
4152     { "sha256msg1", { XM, EXxmm } },
4153   },
4154
4155   /* PREFIX_0F38CD */
4156   {
4157     { "sha256msg2", { XM, EXxmm } },
4158   },
4159
4160   /* PREFIX_0F38DB */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "aesimc", { XM, EXx } },
4165   },
4166
4167   /* PREFIX_0F38DC */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "aesenc", { XM, EXx } },
4172   },
4173
4174   /* PREFIX_0F38DD */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "aesenclast", { XM, EXx } },
4179   },
4180
4181   /* PREFIX_0F38DE */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "aesdec", { XM, EXx } },
4186   },
4187
4188   /* PREFIX_0F38DF */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "aesdeclast", { XM, EXx } },
4193   },
4194
4195   /* PREFIX_0F38F0 */
4196   {
4197     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4198     { Bad_Opcode },
4199     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4200     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4201   },
4202
4203   /* PREFIX_0F38F1 */
4204   {
4205     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4206     { Bad_Opcode },
4207     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4208     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4209   },
4210
4211   /* PREFIX_0F38F6 */
4212   {
4213     { Bad_Opcode },
4214     { "adoxS",  { Gdq, Edq} },
4215     { "adcxS",  { Gdq, Edq} },
4216     { Bad_Opcode },
4217   },
4218
4219   /* PREFIX_0F3A08 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "roundps", { XM, EXx, Ib } },
4224   },
4225
4226   /* PREFIX_0F3A09 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "roundpd", { XM, EXx, Ib } },
4231   },
4232
4233   /* PREFIX_0F3A0A */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "roundss", { XM, EXd, Ib } },
4238   },
4239
4240   /* PREFIX_0F3A0B */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "roundsd", { XM, EXq, Ib } },
4245   },
4246
4247   /* PREFIX_0F3A0C */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "blendps", { XM, EXx, Ib } },
4252   },
4253
4254   /* PREFIX_0F3A0D */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "blendpd", { XM, EXx, Ib } },
4259   },
4260
4261   /* PREFIX_0F3A0E */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pblendw", { XM, EXx, Ib } },
4266   },
4267
4268   /* PREFIX_0F3A14 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pextrb", { Edqb, XM, Ib } },
4273   },
4274
4275   /* PREFIX_0F3A15 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pextrw", { Edqw, XM, Ib } },
4280   },
4281
4282   /* PREFIX_0F3A16 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pextrK", { Edq, XM, Ib } },
4287   },
4288
4289   /* PREFIX_0F3A17 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "extractps", { Edqd, XM, Ib } },
4294   },
4295
4296   /* PREFIX_0F3A20 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pinsrb", { XM, Edqb, Ib } },
4301   },
4302
4303   /* PREFIX_0F3A21 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "insertps", { XM, EXd, Ib } },
4308   },
4309
4310   /* PREFIX_0F3A22 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pinsrK", { XM, Edq, Ib } },
4315   },
4316
4317   /* PREFIX_0F3A40 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "dpps",   { XM, EXx, Ib } },
4322   },
4323
4324   /* PREFIX_0F3A41 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "dppd",   { XM, EXx, Ib } },
4329   },
4330
4331   /* PREFIX_0F3A42 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "mpsadbw", { XM, EXx, Ib } },
4336   },
4337
4338   /* PREFIX_0F3A44 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "pclmulqdq", { XM, EXx, PCLMUL } },
4343   },
4344
4345   /* PREFIX_0F3A60 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "pcmpestrm", { XM, EXx, Ib } },
4350   },
4351
4352   /* PREFIX_0F3A61 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "pcmpestri", { XM, EXx, Ib } },
4357   },
4358
4359   /* PREFIX_0F3A62 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "pcmpistrm", { XM, EXx, Ib } },
4364   },
4365
4366   /* PREFIX_0F3A63 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "pcmpistri", { XM, EXx, Ib } },
4371   },
4372
4373   /* PREFIX_0F3ACC */
4374   {
4375     { "sha1rnds4", { XM, EXxmm, Ib } },
4376   },
4377
4378   /* PREFIX_0F3ADF */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "aeskeygenassist", { XM, EXx, Ib } },
4383   },
4384
4385   /* PREFIX_VEX_0F10 */
4386   {
4387     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4388     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4389     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4390     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4391   },
4392
4393   /* PREFIX_VEX_0F11 */
4394   {
4395     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4396     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4397     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4398     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4399   },
4400
4401   /* PREFIX_VEX_0F12 */
4402   {
4403     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4404     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4405     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4406     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4407   },
4408
4409   /* PREFIX_VEX_0F16 */
4410   {
4411     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4412     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4413     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4414   },
4415
4416   /* PREFIX_VEX_0F2A */
4417   {
4418     { Bad_Opcode },
4419     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4420     { Bad_Opcode },
4421     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4422   },
4423
4424   /* PREFIX_VEX_0F2C */
4425   {
4426     { Bad_Opcode },
4427     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4428     { Bad_Opcode },
4429     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4430   },
4431
4432   /* PREFIX_VEX_0F2D */
4433   {
4434     { Bad_Opcode },
4435     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4436     { Bad_Opcode },
4437     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4438   },
4439
4440   /* PREFIX_VEX_0F2E */
4441   {
4442     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4443     { Bad_Opcode },
4444     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4445   },
4446
4447   /* PREFIX_VEX_0F2F */
4448   {
4449     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4450     { Bad_Opcode },
4451     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4452   },
4453
4454   /* PREFIX_VEX_0F41 */
4455   {
4456     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4457   },
4458
4459   /* PREFIX_VEX_0F42 */
4460   {
4461     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4462   },
4463
4464   /* PREFIX_VEX_0F44 */
4465   {
4466     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4467   },
4468
4469   /* PREFIX_VEX_0F45 */
4470   {
4471     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4472   },
4473
4474   /* PREFIX_VEX_0F46 */
4475   {
4476     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4477   },
4478
4479   /* PREFIX_VEX_0F47 */
4480   {
4481     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4482   },
4483
4484   /* PREFIX_VEX_0F4B */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4489   },
4490
4491   /* PREFIX_VEX_0F51 */
4492   {
4493     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4494     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4495     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4496     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4497   },
4498
4499   /* PREFIX_VEX_0F52 */
4500   {
4501     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4502     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4503   },
4504
4505   /* PREFIX_VEX_0F53 */
4506   {
4507     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4508     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4509   },
4510
4511   /* PREFIX_VEX_0F58 */
4512   {
4513     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4514     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4515     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4516     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4517   },
4518
4519   /* PREFIX_VEX_0F59 */
4520   {
4521     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4522     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4523     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4524     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4525   },
4526
4527   /* PREFIX_VEX_0F5A */
4528   {
4529     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4530     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4531     { "vcvtpd2ps%XY", { XMM, EXx } },
4532     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4533   },
4534
4535   /* PREFIX_VEX_0F5B */
4536   {
4537     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4538     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4539     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4540   },
4541
4542   /* PREFIX_VEX_0F5C */
4543   {
4544     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4545     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4546     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4547     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4548   },
4549
4550   /* PREFIX_VEX_0F5D */
4551   {
4552     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4553     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4554     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4555     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4556   },
4557
4558   /* PREFIX_VEX_0F5E */
4559   {
4560     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4561     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4562     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4563     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4564   },
4565
4566   /* PREFIX_VEX_0F5F */
4567   {
4568     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4569     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4570     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4571     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4572   },
4573
4574   /* PREFIX_VEX_0F60 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4579   },
4580
4581   /* PREFIX_VEX_0F61 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4586   },
4587
4588   /* PREFIX_VEX_0F62 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4593   },
4594
4595   /* PREFIX_VEX_0F63 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4600   },
4601
4602   /* PREFIX_VEX_0F64 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4607   },
4608
4609   /* PREFIX_VEX_0F65 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4614   },
4615
4616   /* PREFIX_VEX_0F66 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4621   },
4622
4623   /* PREFIX_VEX_0F67 */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4628   },
4629
4630   /* PREFIX_VEX_0F68 */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4635   },
4636
4637   /* PREFIX_VEX_0F69 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4642   },
4643
4644   /* PREFIX_VEX_0F6A */
4645   {
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4649   },
4650
4651   /* PREFIX_VEX_0F6B */
4652   {
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4656   },
4657
4658   /* PREFIX_VEX_0F6C */
4659   {
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4663   },
4664
4665   /* PREFIX_VEX_0F6D */
4666   {
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F6E */
4673   {
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F6F */
4680   {
4681     { Bad_Opcode },
4682     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4683     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F70 */
4687   {
4688     { Bad_Opcode },
4689     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4690     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4691     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4692   },
4693
4694   /* PREFIX_VEX_0F71_REG_2 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F71_REG_4 */
4702   {
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F71_REG_6 */
4709   {
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F72_REG_2 */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F72_REG_4 */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F72_REG_6 */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F73_REG_2 */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F73_REG_3 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F73_REG_6 */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F73_REG_7 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F74 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4769   },
4770
4771   /* PREFIX_VEX_0F75 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4776   },
4777
4778   /* PREFIX_VEX_0F76 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F77 */
4786   {
4787     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4788   },
4789
4790   /* PREFIX_VEX_0F7C */
4791   {
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4795     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4796   },
4797
4798   /* PREFIX_VEX_0F7D */
4799   {
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4803     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4804   },
4805
4806   /* PREFIX_VEX_0F7E */
4807   {
4808     { Bad_Opcode },
4809     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4810     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4811   },
4812
4813   /* PREFIX_VEX_0F7F */
4814   {
4815     { Bad_Opcode },
4816     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4817     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F90 */
4821   {
4822     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4823   },
4824
4825   /* PREFIX_VEX_0F91 */
4826   {
4827     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4828   },
4829
4830   /* PREFIX_VEX_0F92 */
4831   {
4832     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4833   },
4834
4835   /* PREFIX_VEX_0F93 */
4836   {
4837     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4838   },
4839
4840   /* PREFIX_VEX_0F98 */
4841   {
4842     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4843   },
4844
4845   /* PREFIX_VEX_0FC2 */
4846   {
4847     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4848     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4849     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4850     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4851   },
4852
4853   /* PREFIX_VEX_0FC4 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0FC5 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0FD0 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4872     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4873   },
4874
4875   /* PREFIX_VEX_0FD1 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4880   },
4881
4882   /* PREFIX_VEX_0FD2 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4887   },
4888
4889   /* PREFIX_VEX_0FD3 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4894   },
4895
4896   /* PREFIX_VEX_0FD4 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4901   },
4902
4903   /* PREFIX_VEX_0FD5 */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4908   },
4909
4910   /* PREFIX_VEX_0FD6 */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4915   },
4916
4917   /* PREFIX_VEX_0FD7 */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4922   },
4923
4924   /* PREFIX_VEX_0FD8 */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4929   },
4930
4931   /* PREFIX_VEX_0FD9 */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4936   },
4937
4938   /* PREFIX_VEX_0FDA */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4943   },
4944
4945   /* PREFIX_VEX_0FDB */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0FDC */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0FDD */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0FDE */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0FDF */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0FE0 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0FE1 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0FE2 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0FE3 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0FE4 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0FE5 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0FE6 */
5023   {
5024     { Bad_Opcode },
5025     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5026     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5027     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5028   },
5029
5030   /* PREFIX_VEX_0FE7 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5035   },
5036
5037   /* PREFIX_VEX_0FE8 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0FE9 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0FEA */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0FEB */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0FEC */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0FED */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0FEE */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0FEF */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0FF0 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5099   },
5100
5101   /* PREFIX_VEX_0FF1 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0FF2 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0FF3 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0FF4 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0FF5 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0FF6 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0FF7 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0FF8 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0FF9 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0FFA */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0FFB */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0FFC */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0FFD */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0FFE */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F3800 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F3801 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F3802 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0F3803 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0F3804 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0F3805 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0F3806 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0F3807 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5253   },
5254
5255   /* PREFIX_VEX_0F3808 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0F3809 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0F380A */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0F380B */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0F380C */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0F380D */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0F380E */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0F380F */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0F3813 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vcvtph2ps", { XM, EXxmmq } },
5316   },
5317
5318   /* PREFIX_VEX_0F3816 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5323   },
5324
5325   /* PREFIX_VEX_0F3817 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0F3818 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0F3819 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0F381A */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5351   },
5352
5353   /* PREFIX_VEX_0F381C */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5358   },
5359
5360   /* PREFIX_VEX_0F381D */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0F381E */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0F3820 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0F3821 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0F3822 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0F3823 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0F3824 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0F3825 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5414   },
5415
5416   /* PREFIX_VEX_0F3828 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5421   },
5422
5423   /* PREFIX_VEX_0F3829 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0F382A */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5435   },
5436
5437   /* PREFIX_VEX_0F382B */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0F382C */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5449   },
5450
5451   /* PREFIX_VEX_0F382D */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5456   },
5457
5458   /* PREFIX_VEX_0F382E */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5463   },
5464
5465   /* PREFIX_VEX_0F382F */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5470   },
5471
5472   /* PREFIX_VEX_0F3830 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0F3831 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0F3832 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0F3833 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F3834 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F3835 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F3836 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F3837 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F3838 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F3839 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F383A */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F383B */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F383C */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F383D */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F383E */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F383F */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3840 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3841 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3845 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vpsrlv%LW", { XM, Vex, EXx } },
5603   },
5604
5605   /* PREFIX_VEX_0F3846 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3847 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { "vpsllv%LW", { XM, Vex, EXx } },
5617   },
5618
5619   /* PREFIX_VEX_0F3858 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3859 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F385A */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3878 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3879 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F388C */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F388E */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3890 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5673   },
5674
5675   /* PREFIX_VEX_0F3891 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5680   },
5681
5682   /* PREFIX_VEX_0F3892 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5687   },
5688
5689   /* PREFIX_VEX_0F3893 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5694   },
5695
5696   /* PREFIX_VEX_0F3896 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5701   },
5702
5703   /* PREFIX_VEX_0F3897 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5708   },
5709
5710   /* PREFIX_VEX_0F3898 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vfmadd132p%XW", { XM, Vex, EXx } },
5715   },
5716
5717   /* PREFIX_VEX_0F3899 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5722   },
5723
5724   /* PREFIX_VEX_0F389A */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vfmsub132p%XW", { XM, Vex, EXx } },
5729   },
5730
5731   /* PREFIX_VEX_0F389B */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5736   },
5737
5738   /* PREFIX_VEX_0F389C */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5743   },
5744
5745   /* PREFIX_VEX_0F389D */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5750   },
5751
5752   /* PREFIX_VEX_0F389E */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5757   },
5758
5759   /* PREFIX_VEX_0F389F */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5764   },
5765
5766   /* PREFIX_VEX_0F38A6 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5771     { Bad_Opcode },
5772   },
5773
5774   /* PREFIX_VEX_0F38A7 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5779   },
5780
5781   /* PREFIX_VEX_0F38A8 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vfmadd213p%XW", { XM, Vex, EXx } },
5786   },
5787
5788   /* PREFIX_VEX_0F38A9 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5793   },
5794
5795   /* PREFIX_VEX_0F38AA */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vfmsub213p%XW", { XM, Vex, EXx } },
5800   },
5801
5802   /* PREFIX_VEX_0F38AB */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5807   },
5808
5809   /* PREFIX_VEX_0F38AC */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5814   },
5815
5816   /* PREFIX_VEX_0F38AD */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5821   },
5822
5823   /* PREFIX_VEX_0F38AE */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5828   },
5829
5830   /* PREFIX_VEX_0F38AF */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5835   },
5836
5837   /* PREFIX_VEX_0F38B6 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5842   },
5843
5844   /* PREFIX_VEX_0F38B7 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5849   },
5850
5851   /* PREFIX_VEX_0F38B8 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vfmadd231p%XW", { XM, Vex, EXx } },
5856   },
5857
5858   /* PREFIX_VEX_0F38B9 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5863   },
5864
5865   /* PREFIX_VEX_0F38BA */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vfmsub231p%XW", { XM, Vex, EXx } },
5870   },
5871
5872   /* PREFIX_VEX_0F38BB */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5877   },
5878
5879   /* PREFIX_VEX_0F38BC */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5884   },
5885
5886   /* PREFIX_VEX_0F38BD */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5891   },
5892
5893   /* PREFIX_VEX_0F38BE */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5898   },
5899
5900   /* PREFIX_VEX_0F38BF */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5905   },
5906
5907   /* PREFIX_VEX_0F38DB */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F38DC */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F38DD */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F38DE */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F38DF */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F38F2 */
5943   {
5944     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5945   },
5946
5947   /* PREFIX_VEX_0F38F3_REG_1 */
5948   {
5949     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5950   },
5951
5952   /* PREFIX_VEX_0F38F3_REG_2 */
5953   {
5954     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5955   },
5956
5957   /* PREFIX_VEX_0F38F3_REG_3 */
5958   {
5959     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5960   },
5961
5962   /* PREFIX_VEX_0F38F5 */
5963   {
5964     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5965     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5966     { Bad_Opcode },
5967     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5968   },
5969
5970   /* PREFIX_VEX_0F38F6 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5976   },
5977
5978   /* PREFIX_VEX_0F38F7 */
5979   {
5980     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5981     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5982     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5983     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5984   },
5985
5986   /* PREFIX_VEX_0F3A00 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F3A01 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3A02 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F3A04 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F3A05 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F3A06 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F3A08 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F3A09 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F3A0A */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F3A0B */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F3A0C */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3A0D */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3A0E */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3A0F */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6082   },
6083
6084   /* PREFIX_VEX_0F3A14 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F3A15 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6096   },
6097
6098   /* PREFIX_VEX_0F3A16 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F3A17 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F3A18 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F3A19 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F3A1D */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6131   },
6132
6133   /* PREFIX_VEX_0F3A20 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F3A21 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6145   },
6146
6147   /* PREFIX_VEX_0F3A22 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6152   },
6153
6154   /* PREFIX_VEX_0F3A30 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6159   },
6160
6161   /* PREFIX_VEX_0F3A32 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6166   },
6167
6168   /* PREFIX_VEX_0F3A38 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6173   },
6174
6175   /* PREFIX_VEX_0F3A39 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6180   },
6181
6182   /* PREFIX_VEX_0F3A40 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6187   },
6188
6189   /* PREFIX_VEX_0F3A41 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6194   },
6195
6196   /* PREFIX_VEX_0F3A42 */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6201   },
6202
6203   /* PREFIX_VEX_0F3A44 */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6208   },
6209
6210   /* PREFIX_VEX_0F3A46 */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6215   },
6216
6217   /* PREFIX_VEX_0F3A48 */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6222   },
6223
6224   /* PREFIX_VEX_0F3A49 */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6229   },
6230
6231   /* PREFIX_VEX_0F3A4A */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F3A4B */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F3A4C */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6250   },
6251
6252   /* PREFIX_VEX_0F3A5C */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6257   },
6258
6259   /* PREFIX_VEX_0F3A5D */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6264   },
6265
6266   /* PREFIX_VEX_0F3A5E */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6271   },
6272
6273   /* PREFIX_VEX_0F3A5F */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6278   },
6279
6280   /* PREFIX_VEX_0F3A60 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6285     { Bad_Opcode },
6286   },
6287
6288   /* PREFIX_VEX_0F3A61 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A62 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A63 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A68 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6314   },
6315
6316   /* PREFIX_VEX_0F3A69 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6321   },
6322
6323   /* PREFIX_VEX_0F3A6A */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A6B */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A6C */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6342   },
6343
6344   /* PREFIX_VEX_0F3A6D */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6349   },
6350
6351   /* PREFIX_VEX_0F3A6E */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A6F */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A78 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6370   },
6371
6372   /* PREFIX_VEX_0F3A79 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6377   },
6378
6379   /* PREFIX_VEX_0F3A7A */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A7B */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A7C */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6398     { Bad_Opcode },
6399   },
6400
6401   /* PREFIX_VEX_0F3A7D */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6406   },
6407
6408   /* PREFIX_VEX_0F3A7E */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A7F */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3ADF */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3AF0 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6435   },
6436
6437 #define NEED_PREFIX_TABLE
6438 #include "i386-dis-evex.h"
6439 #undef NEED_PREFIX_TABLE
6440 };
6441
6442 static const struct dis386 x86_64_table[][2] = {
6443   /* X86_64_06 */
6444   {
6445     { "pushP", { es } },
6446   },
6447
6448   /* X86_64_07 */
6449   {
6450     { "popP", { es } },
6451   },
6452
6453   /* X86_64_0D */
6454   {
6455     { "pushP", { cs } },
6456   },
6457
6458   /* X86_64_16 */
6459   {
6460     { "pushP", { ss } },
6461   },
6462
6463   /* X86_64_17 */
6464   {
6465     { "popP", { ss } },
6466   },
6467
6468   /* X86_64_1E */
6469   {
6470     { "pushP", { ds } },
6471   },
6472
6473   /* X86_64_1F */
6474   {
6475     { "popP", { ds } },
6476   },
6477
6478   /* X86_64_27 */
6479   {
6480     { "daa", { XX } },
6481   },
6482
6483   /* X86_64_2F */
6484   {
6485     { "das", { XX } },
6486   },
6487
6488   /* X86_64_37 */
6489   {
6490     { "aaa", { XX } },
6491   },
6492
6493   /* X86_64_3F */
6494   {
6495     { "aas", { XX } },
6496   },
6497
6498   /* X86_64_60 */
6499   {
6500     { "pushaP", { XX } },
6501   },
6502
6503   /* X86_64_61 */
6504   {
6505     { "popaP", { XX } },
6506   },
6507
6508   /* X86_64_62 */
6509   {
6510     { MOD_TABLE (MOD_62_32BIT) },
6511     { EVEX_TABLE (EVEX_0F) },
6512   },
6513
6514   /* X86_64_63 */
6515   {
6516     { "arpl", { Ew, Gw } },
6517     { "movs{lq|xd}", { Gv, Ed } },
6518   },
6519
6520   /* X86_64_6D */
6521   {
6522     { "ins{R|}", { Yzr, indirDX } },
6523     { "ins{G|}", { Yzr, indirDX } },
6524   },
6525
6526   /* X86_64_6F */
6527   {
6528     { "outs{R|}", { indirDXr, Xz } },
6529     { "outs{G|}", { indirDXr, Xz } },
6530   },
6531
6532   /* X86_64_9A */
6533   {
6534     { "Jcall{T|}", { Ap } },
6535   },
6536
6537   /* X86_64_C4 */
6538   {
6539     { MOD_TABLE (MOD_C4_32BIT) },
6540     { VEX_C4_TABLE (VEX_0F) },
6541   },
6542
6543   /* X86_64_C5 */
6544   {
6545     { MOD_TABLE (MOD_C5_32BIT) },
6546     { VEX_C5_TABLE (VEX_0F) },
6547   },
6548
6549   /* X86_64_CE */
6550   {
6551     { "into", { XX } },
6552   },
6553
6554   /* X86_64_D4 */
6555   {
6556     { "aam", { Ib } },
6557   },
6558
6559   /* X86_64_D5 */
6560   {
6561     { "aad", { Ib } },
6562   },
6563
6564   /* X86_64_EA */
6565   {
6566     { "Jjmp{T|}", { Ap } },
6567   },
6568
6569   /* X86_64_0F01_REG_0 */
6570   {
6571     { "sgdt{Q|IQ}", { M } },
6572     { "sgdt", { M } },
6573   },
6574
6575   /* X86_64_0F01_REG_1 */
6576   {
6577     { "sidt{Q|IQ}", { M } },
6578     { "sidt", { M } },
6579   },
6580
6581   /* X86_64_0F01_REG_2 */
6582   {
6583     { "lgdt{Q|Q}", { M } },
6584     { "lgdt", { M } },
6585   },
6586
6587   /* X86_64_0F01_REG_3 */
6588   {
6589     { "lidt{Q|Q}", { M } },
6590     { "lidt", { M } },
6591   },
6592 };
6593
6594 static const struct dis386 three_byte_table[][256] = {
6595
6596   /* THREE_BYTE_0F38 */
6597   {
6598     /* 00 */
6599     { "pshufb",         { MX, EM } },
6600     { "phaddw",         { MX, EM } },
6601     { "phaddd",         { MX, EM } },
6602     { "phaddsw",        { MX, EM } },
6603     { "pmaddubsw",      { MX, EM } },
6604     { "phsubw",         { MX, EM } },
6605     { "phsubd",         { MX, EM } },
6606     { "phsubsw",        { MX, EM } },
6607     /* 08 */
6608     { "psignb",         { MX, EM } },
6609     { "psignw",         { MX, EM } },
6610     { "psignd",         { MX, EM } },
6611     { "pmulhrsw",       { MX, EM } },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     /* 10 */
6617     { PREFIX_TABLE (PREFIX_0F3810) },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { PREFIX_TABLE (PREFIX_0F3814) },
6622     { PREFIX_TABLE (PREFIX_0F3815) },
6623     { Bad_Opcode },
6624     { PREFIX_TABLE (PREFIX_0F3817) },
6625     /* 18 */
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "pabsb",          { MX, EM } },
6631     { "pabsw",          { MX, EM } },
6632     { "pabsd",          { MX, EM } },
6633     { Bad_Opcode },
6634     /* 20 */
6635     { PREFIX_TABLE (PREFIX_0F3820) },
6636     { PREFIX_TABLE (PREFIX_0F3821) },
6637     { PREFIX_TABLE (PREFIX_0F3822) },
6638     { PREFIX_TABLE (PREFIX_0F3823) },
6639     { PREFIX_TABLE (PREFIX_0F3824) },
6640     { PREFIX_TABLE (PREFIX_0F3825) },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     /* 28 */
6644     { PREFIX_TABLE (PREFIX_0F3828) },
6645     { PREFIX_TABLE (PREFIX_0F3829) },
6646     { PREFIX_TABLE (PREFIX_0F382A) },
6647     { PREFIX_TABLE (PREFIX_0F382B) },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     /* 30 */
6653     { PREFIX_TABLE (PREFIX_0F3830) },
6654     { PREFIX_TABLE (PREFIX_0F3831) },
6655     { PREFIX_TABLE (PREFIX_0F3832) },
6656     { PREFIX_TABLE (PREFIX_0F3833) },
6657     { PREFIX_TABLE (PREFIX_0F3834) },
6658     { PREFIX_TABLE (PREFIX_0F3835) },
6659     { Bad_Opcode },
6660     { PREFIX_TABLE (PREFIX_0F3837) },
6661     /* 38 */
6662     { PREFIX_TABLE (PREFIX_0F3838) },
6663     { PREFIX_TABLE (PREFIX_0F3839) },
6664     { PREFIX_TABLE (PREFIX_0F383A) },
6665     { PREFIX_TABLE (PREFIX_0F383B) },
6666     { PREFIX_TABLE (PREFIX_0F383C) },
6667     { PREFIX_TABLE (PREFIX_0F383D) },
6668     { PREFIX_TABLE (PREFIX_0F383E) },
6669     { PREFIX_TABLE (PREFIX_0F383F) },
6670     /* 40 */
6671     { PREFIX_TABLE (PREFIX_0F3840) },
6672     { PREFIX_TABLE (PREFIX_0F3841) },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     /* 48 */
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     /* 50 */
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     /* 58 */
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     /* 60 */
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     /* 68 */
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     /* 70 */
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     /* 78 */
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     /* 80 */
6743     { PREFIX_TABLE (PREFIX_0F3880) },
6744     { PREFIX_TABLE (PREFIX_0F3881) },
6745     { PREFIX_TABLE (PREFIX_0F3882) },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     /* 88 */
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     /* 90 */
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     /* 98 */
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     /* a0 */
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     /* a8 */
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     /* b0 */
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     /* b8 */
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     /* c0 */
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     /* c8 */
6824     { PREFIX_TABLE (PREFIX_0F38C8) },
6825     { PREFIX_TABLE (PREFIX_0F38C9) },
6826     { PREFIX_TABLE (PREFIX_0F38CA) },
6827     { PREFIX_TABLE (PREFIX_0F38CB) },
6828     { PREFIX_TABLE (PREFIX_0F38CC) },
6829     { PREFIX_TABLE (PREFIX_0F38CD) },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     /* d0 */
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     /* d8 */
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { PREFIX_TABLE (PREFIX_0F38DB) },
6846     { PREFIX_TABLE (PREFIX_0F38DC) },
6847     { PREFIX_TABLE (PREFIX_0F38DD) },
6848     { PREFIX_TABLE (PREFIX_0F38DE) },
6849     { PREFIX_TABLE (PREFIX_0F38DF) },
6850     /* e0 */
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     /* e8 */
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     /* f0 */
6869     { PREFIX_TABLE (PREFIX_0F38F0) },
6870     { PREFIX_TABLE (PREFIX_0F38F1) },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { PREFIX_TABLE (PREFIX_0F38F6) },
6876     { Bad_Opcode },
6877     /* f8 */
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886   },
6887   /* THREE_BYTE_0F3A */
6888   {
6889     /* 00 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 08 */
6899     { PREFIX_TABLE (PREFIX_0F3A08) },
6900     { PREFIX_TABLE (PREFIX_0F3A09) },
6901     { PREFIX_TABLE (PREFIX_0F3A0A) },
6902     { PREFIX_TABLE (PREFIX_0F3A0B) },
6903     { PREFIX_TABLE (PREFIX_0F3A0C) },
6904     { PREFIX_TABLE (PREFIX_0F3A0D) },
6905     { PREFIX_TABLE (PREFIX_0F3A0E) },
6906     { "palignr",        { MX, EM, Ib } },
6907     /* 10 */
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { PREFIX_TABLE (PREFIX_0F3A14) },
6913     { PREFIX_TABLE (PREFIX_0F3A15) },
6914     { PREFIX_TABLE (PREFIX_0F3A16) },
6915     { PREFIX_TABLE (PREFIX_0F3A17) },
6916     /* 18 */
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 20 */
6926     { PREFIX_TABLE (PREFIX_0F3A20) },
6927     { PREFIX_TABLE (PREFIX_0F3A21) },
6928     { PREFIX_TABLE (PREFIX_0F3A22) },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 28 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 30 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 38 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 40 */
6962     { PREFIX_TABLE (PREFIX_0F3A40) },
6963     { PREFIX_TABLE (PREFIX_0F3A41) },
6964     { PREFIX_TABLE (PREFIX_0F3A42) },
6965     { Bad_Opcode },
6966     { PREFIX_TABLE (PREFIX_0F3A44) },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 48 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 50 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 58 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 60 */
6998     { PREFIX_TABLE (PREFIX_0F3A60) },
6999     { PREFIX_TABLE (PREFIX_0F3A61) },
7000     { PREFIX_TABLE (PREFIX_0F3A62) },
7001     { PREFIX_TABLE (PREFIX_0F3A63) },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 68 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 70 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 78 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 80 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 88 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 90 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* 98 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* a0 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* a8 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* b0 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* b8 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* c0 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* c8 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { PREFIX_TABLE (PREFIX_0F3ACC) },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* d0 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* d8 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { PREFIX_TABLE (PREFIX_0F3ADF) },
7141     /* e0 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* e8 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* f0 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* f8 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177   },
7178
7179   /* THREE_BYTE_0F7A */
7180   {
7181     /* 00 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 08 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* 10 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* 18 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* 20 */
7218     { "ptest",          { XX } },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* 28 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 30 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* 38 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 40 */
7254     { Bad_Opcode },
7255     { "phaddbw",        { XM, EXq } },
7256     { "phaddbd",        { XM, EXq } },
7257     { "phaddbq",        { XM, EXq } },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { "phaddwd",        { XM, EXq } },
7261     { "phaddwq",        { XM, EXq } },
7262     /* 48 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { "phadddq",        { XM, EXq } },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 50 */
7272     { Bad_Opcode },
7273     { "phaddubw",       { XM, EXq } },
7274     { "phaddubd",       { XM, EXq } },
7275     { "phaddubq",       { XM, EXq } },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { "phadduwd",       { XM, EXq } },
7279     { "phadduwq",       { XM, EXq } },
7280     /* 58 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { "phaddudq",       { XM, EXq } },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 60 */
7290     { Bad_Opcode },
7291     { "phsubbw",        { XM, EXq } },
7292     { "phsubbd",        { XM, EXq } },
7293     { "phsubbq",        { XM, EXq } },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 68 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 70 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 78 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 80 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 88 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 90 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 98 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* a0 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* a8 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* b0 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* b8 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* c0 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* c8 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* d0 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* d8 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* e0 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* e8 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* f0 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* f8 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469   },
7470 };
7471
7472 static const struct dis386 xop_table[][256] = {
7473   /* XOP_08 */
7474   {
7475     /* 00 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* 08 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 10 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* 18 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 20 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 28 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 30 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* 38 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 40 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 48 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 50 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 58 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 60 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 68 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 70 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 78 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 80 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7626     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7627     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7628     /* 88 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7636     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7637     /* 90 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7644     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7645     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7646     /* 98 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7654     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7655     /* a0 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7659     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7663     { Bad_Opcode },
7664     /* a8 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* b0 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7681     { Bad_Opcode },
7682     /* b8 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* c0 */
7692     { "vprotb",         { XM, Vex_2src_1, Ib } },
7693     { "vprotw",         { XM, Vex_2src_1, Ib } },
7694     { "vprotd",         { XM, Vex_2src_1, Ib } },
7695     { "vprotq",         { XM, Vex_2src_1, Ib } },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* c8 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7706     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7707     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7708     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7709     /* d0 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* d8 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* e0 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* e8 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7742     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7743     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7744     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7745     /* f0 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* f8 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763   },
7764   /* XOP_09 */
7765   {
7766     /* 00 */
7767     { Bad_Opcode },
7768     { REG_TABLE (REG_XOP_TBM_01) },
7769     { REG_TABLE (REG_XOP_TBM_02) },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* 08 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 10 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { REG_TABLE (REG_XOP_LWPCB) },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 18 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 20 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 28 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 30 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 38 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 40 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 48 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 50 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 58 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 60 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 68 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 70 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 78 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 80 */
7911     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7912     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7913     { "vfrczss",        { XM, EXd } },
7914     { "vfrczsd",        { XM, EXq } },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 88 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 90 */
7929     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7930     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7931     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7932     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7933     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7934     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7935     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7936     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7937     /* 98 */
7938     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7939     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7940     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7941     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* a0 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* a8 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* b0 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* b8 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* c0 */
7983     { Bad_Opcode },
7984     { "vphaddbw",       { XM, EXxmm } },
7985     { "vphaddbd",       { XM, EXxmm } },
7986     { "vphaddbq",       { XM, EXxmm } },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { "vphaddwd",       { XM, EXxmm } },
7990     { "vphaddwq",       { XM, EXxmm } },
7991     /* c8 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { "vphadddq",       { XM, EXxmm } },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* d0 */
8001     { Bad_Opcode },
8002     { "vphaddubw",      { XM, EXxmm } },
8003     { "vphaddubd",      { XM, EXxmm } },
8004     { "vphaddubq",      { XM, EXxmm } },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { "vphadduwd",      { XM, EXxmm } },
8008     { "vphadduwq",      { XM, EXxmm } },
8009     /* d8 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { "vphaddudq",      { XM, EXxmm } },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* e0 */
8019     { Bad_Opcode },
8020     { "vphsubbw",       { XM, EXxmm } },
8021     { "vphsubwd",       { XM, EXxmm } },
8022     { "vphsubdq",       { XM, EXxmm } },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* e8 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* f0 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* f8 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054   },
8055   /* XOP_0A */
8056   {
8057     /* 00 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 08 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 10 */
8076     { "bextr",  { Gv, Ev, Iq } },
8077     { Bad_Opcode },
8078     { REG_TABLE (REG_XOP_LWP) },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 18 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 20 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 28 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 30 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 38 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 40 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 48 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 50 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 58 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 60 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 68 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 70 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 78 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 80 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 88 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 90 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 98 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* a0 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* a8 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* b0 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* b8 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* c0 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* c8 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* d0 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* d8 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* e0 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* e8 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* f0 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* f8 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345   },
8346 };
8347
8348 static const struct dis386 vex_table[][256] = {
8349   /* VEX_0F */
8350   {
8351     /* 00 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* 08 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 10 */
8370     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8371     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8372     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8373     { MOD_TABLE (MOD_VEX_0F13) },
8374     { VEX_W_TABLE (VEX_W_0F14) },
8375     { VEX_W_TABLE (VEX_W_0F15) },
8376     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8377     { MOD_TABLE (MOD_VEX_0F17) },
8378     /* 18 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 20 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 28 */
8397     { VEX_W_TABLE (VEX_W_0F28) },
8398     { VEX_W_TABLE (VEX_W_0F29) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8400     { MOD_TABLE (MOD_VEX_0F2B) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8405     /* 30 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* 38 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 40 */
8424     { Bad_Opcode },
8425     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8427     { Bad_Opcode },
8428     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8432     /* 48 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 50 */
8442     { MOD_TABLE (MOD_VEX_0F50) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8444     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8445     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8446     { "vandpX",         { XM, Vex, EXx } },
8447     { "vandnpX",        { XM, Vex, EXx } },
8448     { "vorpX",          { XM, Vex, EXx } },
8449     { "vxorpX",         { XM, Vex, EXx } },
8450     /* 58 */
8451     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8458     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8459     /* 60 */
8460     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8467     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8468     /* 68 */
8469     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8477     /* 70 */
8478     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8479     { REG_TABLE (REG_VEX_0F71) },
8480     { REG_TABLE (REG_VEX_0F72) },
8481     { REG_TABLE (REG_VEX_0F73) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8486     /* 78 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8495     /* 80 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 88 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 90 */
8514     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 98 */
8523     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* a0 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* a8 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { REG_TABLE (REG_VEX_0FAE) },
8548     { Bad_Opcode },
8549     /* b0 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* b8 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* c0 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8571     { Bad_Opcode },
8572     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8574     { "vshufpX",        { XM, Vex, EXx, Ib } },
8575     { Bad_Opcode },
8576     /* c8 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* d0 */
8586     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8594     /* d8 */
8595     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8602     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8603     /* e0 */
8604     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8605     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8606     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8607     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8609     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8610     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8611     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8612     /* e8 */
8613     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8614     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8615     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8616     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8617     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8618     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8619     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8620     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8621     /* f0 */
8622     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8623     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8624     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8625     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8626     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8627     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8628     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8629     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8630     /* f8 */
8631     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8632     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8633     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8634     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8635     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8637     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8638     { Bad_Opcode },
8639   },
8640   /* VEX_0F38 */
8641   {
8642     /* 00 */
8643     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8651     /* 08 */
8652     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8660     /* 10 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8669     /* 18 */
8670     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8677     { Bad_Opcode },
8678     /* 20 */
8679     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     /* 28 */
8688     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8696     /* 30 */
8697     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8705     /* 38 */
8706     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8714     /* 40 */
8715     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8723     /* 48 */
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     /* 50 */
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     /* 58 */
8742     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     /* 60 */
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     /* 68 */
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* 70 */
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     /* 78 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     /* 80 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     /* 88 */
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8801     { Bad_Opcode },
8802     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8803     { Bad_Opcode },
8804     /* 90 */
8805     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8813     /* 98 */
8814     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8822     /* a0 */
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8831     /* a8 */
8832     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8840     /* b0 */
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8849     /* b8 */
8850     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8858     /* c0 */
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     /* c8 */
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     /* d0 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     /* d8 */
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8894     /* e0 */
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     /* e8 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     /* f0 */
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8916     { REG_TABLE (REG_VEX_0F38F3) },
8917     { Bad_Opcode },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8921     /* f8 */
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930   },
8931   /* VEX_0F3A */
8932   {
8933     /* 00 */
8934     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8941     { Bad_Opcode },
8942     /* 08 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8951     /* 10 */
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8960     /* 18 */
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     /* 20 */
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     /* 28 */
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* 30 */
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8989     { Bad_Opcode },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     /* 38 */
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     /* 40 */
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9009     { Bad_Opcode },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9011     { Bad_Opcode },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9013     { Bad_Opcode },
9014     /* 48 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     /* 50 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 58 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9041     /* 60 */
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 68 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9059     /* 70 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 78 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9077     /* 80 */
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* 88 */
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     /* 90 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     /* 98 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* a0 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     /* a8 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* b0 */
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     /* b8 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* c0 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* c8 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* d0 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* d8 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9185     /* e0 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* e8 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     /* f0 */
9204     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* f8 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221   },
9222 };
9223
9224 #define NEED_OPCODE_TABLE
9225 #include "i386-dis-evex.h"
9226 #undef NEED_OPCODE_TABLE
9227 static const struct dis386 vex_len_table[][2] = {
9228   /* VEX_LEN_0F10_P_1 */
9229   {
9230     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9231     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9232   },
9233
9234   /* VEX_LEN_0F10_P_3 */
9235   {
9236     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9237     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9238   },
9239
9240   /* VEX_LEN_0F11_P_1 */
9241   {
9242     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9243     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9244   },
9245
9246   /* VEX_LEN_0F11_P_3 */
9247   {
9248     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9249     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9250   },
9251
9252   /* VEX_LEN_0F12_P_0_M_0 */
9253   {
9254     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9255   },
9256
9257   /* VEX_LEN_0F12_P_0_M_1 */
9258   {
9259     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9260   },
9261
9262   /* VEX_LEN_0F12_P_2 */
9263   {
9264     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9265   },
9266
9267   /* VEX_LEN_0F13_M_0 */
9268   {
9269     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9270   },
9271
9272   /* VEX_LEN_0F16_P_0_M_0 */
9273   {
9274     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9275   },
9276
9277   /* VEX_LEN_0F16_P_0_M_1 */
9278   {
9279     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9280   },
9281
9282   /* VEX_LEN_0F16_P_2 */
9283   {
9284     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9285   },
9286
9287   /* VEX_LEN_0F17_M_0 */
9288   {
9289     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9290   },
9291
9292   /* VEX_LEN_0F2A_P_1 */
9293   {
9294     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9295     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9296   },
9297
9298   /* VEX_LEN_0F2A_P_3 */
9299   {
9300     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9301     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9302   },
9303
9304   /* VEX_LEN_0F2C_P_1 */
9305   {
9306     { "vcvttss2siY",    { Gv, EXdScalar } },
9307     { "vcvttss2siY",    { Gv, EXdScalar } },
9308   },
9309
9310   /* VEX_LEN_0F2C_P_3 */
9311   {
9312     { "vcvttsd2siY",    { Gv, EXqScalar } },
9313     { "vcvttsd2siY",    { Gv, EXqScalar } },
9314   },
9315
9316   /* VEX_LEN_0F2D_P_1 */
9317   {
9318     { "vcvtss2siY",     { Gv, EXdScalar } },
9319     { "vcvtss2siY",     { Gv, EXdScalar } },
9320   },
9321
9322   /* VEX_LEN_0F2D_P_3 */
9323   {
9324     { "vcvtsd2siY",     { Gv, EXqScalar } },
9325     { "vcvtsd2siY",     { Gv, EXqScalar } },
9326   },
9327
9328   /* VEX_LEN_0F2E_P_0 */
9329   {
9330     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9331     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9332   },
9333
9334   /* VEX_LEN_0F2E_P_2 */
9335   {
9336     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9337     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9338   },
9339
9340   /* VEX_LEN_0F2F_P_0 */
9341   {
9342     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9343     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9344   },
9345
9346   /* VEX_LEN_0F2F_P_2 */
9347   {
9348     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9349     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9350   },
9351
9352   /* VEX_LEN_0F41_P_0 */
9353   {
9354     { Bad_Opcode },
9355     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9356   },
9357   /* VEX_LEN_0F42_P_0 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9361   },
9362   /* VEX_LEN_0F44_P_0 */
9363   {
9364     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9365   },
9366   /* VEX_LEN_0F45_P_0 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9370   },
9371   /* VEX_LEN_0F46_P_0 */
9372   {
9373     { Bad_Opcode },
9374     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9375   },
9376   /* VEX_LEN_0F47_P_0 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9380   },
9381   /* VEX_LEN_0F4B_P_2 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9385   },
9386
9387   /* VEX_LEN_0F51_P_1 */
9388   {
9389     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9390     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9391   },
9392
9393   /* VEX_LEN_0F51_P_3 */
9394   {
9395     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9396     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9397   },
9398
9399   /* VEX_LEN_0F52_P_1 */
9400   {
9401     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9402     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9403   },
9404
9405   /* VEX_LEN_0F53_P_1 */
9406   {
9407     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9408     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9409   },
9410
9411   /* VEX_LEN_0F58_P_1 */
9412   {
9413     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9414     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9415   },
9416
9417   /* VEX_LEN_0F58_P_3 */
9418   {
9419     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9420     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9421   },
9422
9423   /* VEX_LEN_0F59_P_1 */
9424   {
9425     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9426     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9427   },
9428
9429   /* VEX_LEN_0F59_P_3 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9432     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9433   },
9434
9435   /* VEX_LEN_0F5A_P_1 */
9436   {
9437     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9438     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9439   },
9440
9441   /* VEX_LEN_0F5A_P_3 */
9442   {
9443     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9444     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9445   },
9446
9447   /* VEX_LEN_0F5C_P_1 */
9448   {
9449     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9450     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9451   },
9452
9453   /* VEX_LEN_0F5C_P_3 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9456     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9457   },
9458
9459   /* VEX_LEN_0F5D_P_1 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9462     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9463   },
9464
9465   /* VEX_LEN_0F5D_P_3 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9468     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9469   },
9470
9471   /* VEX_LEN_0F5E_P_1 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9474     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9475   },
9476
9477   /* VEX_LEN_0F5E_P_3 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9480     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9481   },
9482
9483   /* VEX_LEN_0F5F_P_1 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9486     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9487   },
9488
9489   /* VEX_LEN_0F5F_P_3 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9492     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9493   },
9494
9495   /* VEX_LEN_0F6E_P_2 */
9496   {
9497     { "vmovK",          { XMScalar, Edq } },
9498     { "vmovK",          { XMScalar, Edq } },
9499   },
9500
9501   /* VEX_LEN_0F7E_P_1 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9504     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9505   },
9506
9507   /* VEX_LEN_0F7E_P_2 */
9508   {
9509     { "vmovK",          { Edq, XMScalar } },
9510     { "vmovK",          { Edq, XMScalar } },
9511   },
9512
9513   /* VEX_LEN_0F90_P_0 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0F91_P_0 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9521   },
9522
9523   /* VEX_LEN_0F92_P_0 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9526   },
9527
9528   /* VEX_LEN_0F93_P_0 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9531   },
9532
9533   /* VEX_LEN_0F98_P_0 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9536   },
9537
9538   /* VEX_LEN_0FAE_R_2_M_0 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9541   },
9542
9543   /* VEX_LEN_0FAE_R_3_M_0 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9546   },
9547
9548   /* VEX_LEN_0FC2_P_1 */
9549   {
9550     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9551     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9552   },
9553
9554   /* VEX_LEN_0FC2_P_3 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9557     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9558   },
9559
9560   /* VEX_LEN_0FC4_P_2 */
9561   {
9562     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9563   },
9564
9565   /* VEX_LEN_0FC5_P_2 */
9566   {
9567     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9568   },
9569
9570   /* VEX_LEN_0FD6_P_2 */
9571   {
9572     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9573     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9574   },
9575
9576   /* VEX_LEN_0FF7_P_2 */
9577   {
9578     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F3816_P_2 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F3819_P_2 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9591   },
9592
9593   /* VEX_LEN_0F381A_P_2_M_0 */
9594   {
9595     { Bad_Opcode },
9596     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9597   },
9598
9599   /* VEX_LEN_0F3836_P_2 */
9600   {
9601     { Bad_Opcode },
9602     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9603   },
9604
9605   /* VEX_LEN_0F3841_P_2 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9608   },
9609
9610   /* VEX_LEN_0F385A_P_2_M_0 */
9611   {
9612     { Bad_Opcode },
9613     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9614   },
9615
9616   /* VEX_LEN_0F38DB_P_2 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9619   },
9620
9621   /* VEX_LEN_0F38DC_P_2 */
9622   {
9623     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9624   },
9625
9626   /* VEX_LEN_0F38DD_P_2 */
9627   {
9628     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9629   },
9630
9631   /* VEX_LEN_0F38DE_P_2 */
9632   {
9633     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9634   },
9635
9636   /* VEX_LEN_0F38DF_P_2 */
9637   {
9638     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9639   },
9640
9641   /* VEX_LEN_0F38F2_P_0 */
9642   {
9643     { "andnS",          { Gdq, VexGdq, Edq } },
9644   },
9645
9646   /* VEX_LEN_0F38F3_R_1_P_0 */
9647   {
9648     { "blsrS",          { VexGdq, Edq } },
9649   },
9650
9651   /* VEX_LEN_0F38F3_R_2_P_0 */
9652   {
9653     { "blsmskS",        { VexGdq, Edq } },
9654   },
9655
9656   /* VEX_LEN_0F38F3_R_3_P_0 */
9657   {
9658     { "blsiS",          { VexGdq, Edq } },
9659   },
9660
9661   /* VEX_LEN_0F38F5_P_0 */
9662   {
9663     { "bzhiS",          { Gdq, Edq, VexGdq } },
9664   },
9665
9666   /* VEX_LEN_0F38F5_P_1 */
9667   {
9668     { "pextS",          { Gdq, VexGdq, Edq } },
9669   },
9670
9671   /* VEX_LEN_0F38F5_P_3 */
9672   {
9673     { "pdepS",          { Gdq, VexGdq, Edq } },
9674   },
9675
9676   /* VEX_LEN_0F38F6_P_3 */
9677   {
9678     { "mulxS",          { Gdq, VexGdq, Edq } },
9679   },
9680
9681   /* VEX_LEN_0F38F7_P_0 */
9682   {
9683     { "bextrS",         { Gdq, Edq, VexGdq } },
9684   },
9685
9686   /* VEX_LEN_0F38F7_P_1 */
9687   {
9688     { "sarxS",          { Gdq, Edq, VexGdq } },
9689   },
9690
9691   /* VEX_LEN_0F38F7_P_2 */
9692   {
9693     { "shlxS",          { Gdq, Edq, VexGdq } },
9694   },
9695
9696   /* VEX_LEN_0F38F7_P_3 */
9697   {
9698     { "shrxS",          { Gdq, Edq, VexGdq } },
9699   },
9700
9701   /* VEX_LEN_0F3A00_P_2 */
9702   {
9703     { Bad_Opcode },
9704     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F3A01_P_2 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9711   },
9712
9713   /* VEX_LEN_0F3A06_P_2 */
9714   {
9715     { Bad_Opcode },
9716     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9717   },
9718
9719   /* VEX_LEN_0F3A0A_P_2 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9722     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9723   },
9724
9725   /* VEX_LEN_0F3A0B_P_2 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9728     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9729   },
9730
9731   /* VEX_LEN_0F3A14_P_2 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9734   },
9735
9736   /* VEX_LEN_0F3A15_P_2 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9739   },
9740
9741   /* VEX_LEN_0F3A16_P_2  */
9742   {
9743     { "vpextrK",        { Edq, XM, Ib } },
9744   },
9745
9746   /* VEX_LEN_0F3A17_P_2 */
9747   {
9748     { "vextractps",     { Edqd, XM, Ib } },
9749   },
9750
9751   /* VEX_LEN_0F3A18_P_2 */
9752   {
9753     { Bad_Opcode },
9754     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9755   },
9756
9757   /* VEX_LEN_0F3A19_P_2 */
9758   {
9759     { Bad_Opcode },
9760     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9761   },
9762
9763   /* VEX_LEN_0F3A20_P_2 */
9764   {
9765     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9766   },
9767
9768   /* VEX_LEN_0F3A21_P_2 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9771   },
9772
9773   /* VEX_LEN_0F3A22_P_2 */
9774   {
9775     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9776   },
9777
9778   /* VEX_LEN_0F3A30_P_2 */
9779   {
9780     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9781   },
9782
9783   /* VEX_LEN_0F3A32_P_2 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9786   },
9787
9788   /* VEX_LEN_0F3A38_P_2 */
9789   {
9790     { Bad_Opcode },
9791     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9792   },
9793
9794   /* VEX_LEN_0F3A39_P_2 */
9795   {
9796     { Bad_Opcode },
9797     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9798   },
9799
9800   /* VEX_LEN_0F3A41_P_2 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9803   },
9804
9805   /* VEX_LEN_0F3A44_P_2 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9808   },
9809
9810   /* VEX_LEN_0F3A46_P_2 */
9811   {
9812     { Bad_Opcode },
9813     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9814   },
9815
9816   /* VEX_LEN_0F3A60_P_2 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9819   },
9820
9821   /* VEX_LEN_0F3A61_P_2 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9824   },
9825
9826   /* VEX_LEN_0F3A62_P_2 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9829   },
9830
9831   /* VEX_LEN_0F3A63_P_2 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9834   },
9835
9836   /* VEX_LEN_0F3A6A_P_2 */
9837   {
9838     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9839   },
9840
9841   /* VEX_LEN_0F3A6B_P_2 */
9842   {
9843     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9844   },
9845
9846   /* VEX_LEN_0F3A6E_P_2 */
9847   {
9848     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9849   },
9850
9851   /* VEX_LEN_0F3A6F_P_2 */
9852   {
9853     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9854   },
9855
9856   /* VEX_LEN_0F3A7A_P_2 */
9857   {
9858     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9859   },
9860
9861   /* VEX_LEN_0F3A7B_P_2 */
9862   {
9863     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9864   },
9865
9866   /* VEX_LEN_0F3A7E_P_2 */
9867   {
9868     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9869   },
9870
9871   /* VEX_LEN_0F3A7F_P_2 */
9872   {
9873     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9874   },
9875
9876   /* VEX_LEN_0F3ADF_P_2 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9879   },
9880
9881   /* VEX_LEN_0F3AF0_P_3 */
9882   {
9883     { "rorxS",          { Gdq, Edq, Ib } },
9884   },
9885
9886   /* VEX_LEN_0FXOP_08_CC */
9887   {
9888      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9889   },
9890
9891   /* VEX_LEN_0FXOP_08_CD */
9892   {
9893      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9894   },
9895
9896   /* VEX_LEN_0FXOP_08_CE */
9897   {
9898      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9899   },
9900
9901   /* VEX_LEN_0FXOP_08_CF */
9902   {
9903      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9904   },
9905
9906   /* VEX_LEN_0FXOP_08_EC */
9907   {
9908      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9909   },
9910
9911   /* VEX_LEN_0FXOP_08_ED */
9912   {
9913      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9914   },
9915
9916   /* VEX_LEN_0FXOP_08_EE */
9917   {
9918      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9919   },
9920
9921   /* VEX_LEN_0FXOP_08_EF */
9922   {
9923      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9924   },
9925
9926   /* VEX_LEN_0FXOP_09_80 */
9927   {
9928     { "vfrczps",        { XM, EXxmm } },
9929     { "vfrczps",        { XM, EXymmq } },
9930   },
9931
9932   /* VEX_LEN_0FXOP_09_81 */
9933   {
9934     { "vfrczpd",        { XM, EXxmm } },
9935     { "vfrczpd",        { XM, EXymmq } },
9936   },
9937 };
9938
9939 static const struct dis386 vex_w_table[][2] = {
9940   {
9941     /* VEX_W_0F10_P_0 */
9942     { "vmovups",        { XM, EXx } },
9943   },
9944   {
9945     /* VEX_W_0F10_P_1 */
9946     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9947   },
9948   {
9949     /* VEX_W_0F10_P_2 */
9950     { "vmovupd",        { XM, EXx } },
9951   },
9952   {
9953     /* VEX_W_0F10_P_3 */
9954     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9955   },
9956   {
9957     /* VEX_W_0F11_P_0 */
9958     { "vmovups",        { EXxS, XM } },
9959   },
9960   {
9961     /* VEX_W_0F11_P_1 */
9962     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9963   },
9964   {
9965     /* VEX_W_0F11_P_2 */
9966     { "vmovupd",        { EXxS, XM } },
9967   },
9968   {
9969     /* VEX_W_0F11_P_3 */
9970     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9971   },
9972   {
9973     /* VEX_W_0F12_P_0_M_0 */
9974     { "vmovlps",        { XM, Vex128, EXq } },
9975   },
9976   {
9977     /* VEX_W_0F12_P_0_M_1 */
9978     { "vmovhlps",       { XM, Vex128, EXq } },
9979   },
9980   {
9981     /* VEX_W_0F12_P_1 */
9982     { "vmovsldup",      { XM, EXx } },
9983   },
9984   {
9985     /* VEX_W_0F12_P_2 */
9986     { "vmovlpd",        { XM, Vex128, EXq } },
9987   },
9988   {
9989     /* VEX_W_0F12_P_3 */
9990     { "vmovddup",       { XM, EXymmq } },
9991   },
9992   {
9993     /* VEX_W_0F13_M_0 */
9994     { "vmovlpX",        { EXq, XM } },
9995   },
9996   {
9997     /* VEX_W_0F14 */
9998     { "vunpcklpX",      { XM, Vex, EXx } },
9999   },
10000   {
10001     /* VEX_W_0F15 */
10002     { "vunpckhpX",      { XM, Vex, EXx } },
10003   },
10004   {
10005     /* VEX_W_0F16_P_0_M_0 */
10006     { "vmovhps",        { XM, Vex128, EXq } },
10007   },
10008   {
10009     /* VEX_W_0F16_P_0_M_1 */
10010     { "vmovlhps",       { XM, Vex128, EXq } },
10011   },
10012   {
10013     /* VEX_W_0F16_P_1 */
10014     { "vmovshdup",      { XM, EXx } },
10015   },
10016   {
10017     /* VEX_W_0F16_P_2 */
10018     { "vmovhpd",        { XM, Vex128, EXq } },
10019   },
10020   {
10021     /* VEX_W_0F17_M_0 */
10022     { "vmovhpX",        { EXq, XM } },
10023   },
10024   {
10025     /* VEX_W_0F28 */
10026     { "vmovapX",        { XM, EXx } },
10027   },
10028   {
10029     /* VEX_W_0F29 */
10030     { "vmovapX",        { EXxS, XM } },
10031   },
10032   {
10033     /* VEX_W_0F2B_M_0 */
10034     { "vmovntpX",       { Mx, XM } },
10035   },
10036   {
10037     /* VEX_W_0F2E_P_0 */
10038     { "vucomiss",       { XMScalar, EXdScalar } },
10039   },
10040   {
10041     /* VEX_W_0F2E_P_2 */
10042     { "vucomisd",       { XMScalar, EXqScalar } },
10043   },
10044   {
10045     /* VEX_W_0F2F_P_0 */
10046     { "vcomiss",        { XMScalar, EXdScalar } },
10047   },
10048   {
10049     /* VEX_W_0F2F_P_2 */
10050     { "vcomisd",        { XMScalar, EXqScalar } },
10051   },
10052   {
10053     /* VEX_W_0F41_P_0_LEN_1 */
10054     { "kandw",          { MaskG, MaskVex, MaskR } },
10055   },
10056   {
10057     /* VEX_W_0F42_P_0_LEN_1 */
10058     { "kandnw",         { MaskG, MaskVex, MaskR } },
10059   },
10060   {
10061     /* VEX_W_0F44_P_0_LEN_0 */
10062     { "knotw",          { MaskG, MaskR } },
10063   },
10064   {
10065     /* VEX_W_0F45_P_0_LEN_1 */
10066     { "korw",           { MaskG, MaskVex, MaskR } },
10067   },
10068   {
10069     /* VEX_W_0F46_P_0_LEN_1 */
10070     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10071   },
10072   {
10073     /* VEX_W_0F47_P_0_LEN_1 */
10074     { "kxorw",          { MaskG, MaskVex, MaskR } },
10075   },
10076   {
10077     /* VEX_W_0F4B_P_2_LEN_1 */
10078     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10079   },
10080   {
10081     /* VEX_W_0F50_M_0 */
10082     { "vmovmskpX",      { Gdq, XS } },
10083   },
10084   {
10085     /* VEX_W_0F51_P_0 */
10086     { "vsqrtps",        { XM, EXx } },
10087   },
10088   {
10089     /* VEX_W_0F51_P_1 */
10090     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10091   },
10092   {
10093     /* VEX_W_0F51_P_2  */
10094     { "vsqrtpd",        { XM, EXx } },
10095   },
10096   {
10097     /* VEX_W_0F51_P_3 */
10098     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10099   },
10100   {
10101     /* VEX_W_0F52_P_0 */
10102     { "vrsqrtps",       { XM, EXx } },
10103   },
10104   {
10105     /* VEX_W_0F52_P_1 */
10106     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10107   },
10108   {
10109     /* VEX_W_0F53_P_0  */
10110     { "vrcpps",         { XM, EXx } },
10111   },
10112   {
10113     /* VEX_W_0F53_P_1  */
10114     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10115   },
10116   {
10117     /* VEX_W_0F58_P_0  */
10118     { "vaddps",         { XM, Vex, EXx } },
10119   },
10120   {
10121     /* VEX_W_0F58_P_1  */
10122     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10123   },
10124   {
10125     /* VEX_W_0F58_P_2  */
10126     { "vaddpd",         { XM, Vex, EXx } },
10127   },
10128   {
10129     /* VEX_W_0F58_P_3  */
10130     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10131   },
10132   {
10133     /* VEX_W_0F59_P_0  */
10134     { "vmulps",         { XM, Vex, EXx } },
10135   },
10136   {
10137     /* VEX_W_0F59_P_1  */
10138     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10139   },
10140   {
10141     /* VEX_W_0F59_P_2  */
10142     { "vmulpd",         { XM, Vex, EXx } },
10143   },
10144   {
10145     /* VEX_W_0F59_P_3  */
10146     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10147   },
10148   {
10149     /* VEX_W_0F5A_P_0  */
10150     { "vcvtps2pd",      { XM, EXxmmq } },
10151   },
10152   {
10153     /* VEX_W_0F5A_P_1  */
10154     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10155   },
10156   {
10157     /* VEX_W_0F5A_P_3  */
10158     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10159   },
10160   {
10161     /* VEX_W_0F5B_P_0  */
10162     { "vcvtdq2ps",      { XM, EXx } },
10163   },
10164   {
10165     /* VEX_W_0F5B_P_1  */
10166     { "vcvttps2dq",     { XM, EXx } },
10167   },
10168   {
10169     /* VEX_W_0F5B_P_2  */
10170     { "vcvtps2dq",      { XM, EXx } },
10171   },
10172   {
10173     /* VEX_W_0F5C_P_0  */
10174     { "vsubps",         { XM, Vex, EXx } },
10175   },
10176   {
10177     /* VEX_W_0F5C_P_1  */
10178     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10179   },
10180   {
10181     /* VEX_W_0F5C_P_2  */
10182     { "vsubpd",         { XM, Vex, EXx } },
10183   },
10184   {
10185     /* VEX_W_0F5C_P_3  */
10186     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10187   },
10188   {
10189     /* VEX_W_0F5D_P_0  */
10190     { "vminps",         { XM, Vex, EXx } },
10191   },
10192   {
10193     /* VEX_W_0F5D_P_1  */
10194     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10195   },
10196   {
10197     /* VEX_W_0F5D_P_2  */
10198     { "vminpd",         { XM, Vex, EXx } },
10199   },
10200   {
10201     /* VEX_W_0F5D_P_3  */
10202     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10203   },
10204   {
10205     /* VEX_W_0F5E_P_0  */
10206     { "vdivps",         { XM, Vex, EXx } },
10207   },
10208   {
10209     /* VEX_W_0F5E_P_1  */
10210     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10211   },
10212   {
10213     /* VEX_W_0F5E_P_2  */
10214     { "vdivpd",         { XM, Vex, EXx } },
10215   },
10216   {
10217     /* VEX_W_0F5E_P_3  */
10218     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10219   },
10220   {
10221     /* VEX_W_0F5F_P_0  */
10222     { "vmaxps",         { XM, Vex, EXx } },
10223   },
10224   {
10225     /* VEX_W_0F5F_P_1  */
10226     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10227   },
10228   {
10229     /* VEX_W_0F5F_P_2  */
10230     { "vmaxpd",         { XM, Vex, EXx } },
10231   },
10232   {
10233     /* VEX_W_0F5F_P_3  */
10234     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10235   },
10236   {
10237     /* VEX_W_0F60_P_2  */
10238     { "vpunpcklbw",     { XM, Vex, EXx } },
10239   },
10240   {
10241     /* VEX_W_0F61_P_2  */
10242     { "vpunpcklwd",     { XM, Vex, EXx } },
10243   },
10244   {
10245     /* VEX_W_0F62_P_2  */
10246     { "vpunpckldq",     { XM, Vex, EXx } },
10247   },
10248   {
10249     /* VEX_W_0F63_P_2  */
10250     { "vpacksswb",      { XM, Vex, EXx } },
10251   },
10252   {
10253     /* VEX_W_0F64_P_2  */
10254     { "vpcmpgtb",       { XM, Vex, EXx } },
10255   },
10256   {
10257     /* VEX_W_0F65_P_2  */
10258     { "vpcmpgtw",       { XM, Vex, EXx } },
10259   },
10260   {
10261     /* VEX_W_0F66_P_2  */
10262     { "vpcmpgtd",       { XM, Vex, EXx } },
10263   },
10264   {
10265     /* VEX_W_0F67_P_2  */
10266     { "vpackuswb",      { XM, Vex, EXx } },
10267   },
10268   {
10269     /* VEX_W_0F68_P_2  */
10270     { "vpunpckhbw",     { XM, Vex, EXx } },
10271   },
10272   {
10273     /* VEX_W_0F69_P_2  */
10274     { "vpunpckhwd",     { XM, Vex, EXx } },
10275   },
10276   {
10277     /* VEX_W_0F6A_P_2  */
10278     { "vpunpckhdq",     { XM, Vex, EXx } },
10279   },
10280   {
10281     /* VEX_W_0F6B_P_2  */
10282     { "vpackssdw",      { XM, Vex, EXx } },
10283   },
10284   {
10285     /* VEX_W_0F6C_P_2  */
10286     { "vpunpcklqdq",    { XM, Vex, EXx } },
10287   },
10288   {
10289     /* VEX_W_0F6D_P_2  */
10290     { "vpunpckhqdq",    { XM, Vex, EXx } },
10291   },
10292   {
10293     /* VEX_W_0F6F_P_1  */
10294     { "vmovdqu",        { XM, EXx } },
10295   },
10296   {
10297     /* VEX_W_0F6F_P_2  */
10298     { "vmovdqa",        { XM, EXx } },
10299   },
10300   {
10301     /* VEX_W_0F70_P_1 */
10302     { "vpshufhw",       { XM, EXx, Ib } },
10303   },
10304   {
10305     /* VEX_W_0F70_P_2 */
10306     { "vpshufd",        { XM, EXx, Ib } },
10307   },
10308   {
10309     /* VEX_W_0F70_P_3 */
10310     { "vpshuflw",       { XM, EXx, Ib } },
10311   },
10312   {
10313     /* VEX_W_0F71_R_2_P_2  */
10314     { "vpsrlw",         { Vex, XS, Ib } },
10315   },
10316   {
10317     /* VEX_W_0F71_R_4_P_2  */
10318     { "vpsraw",         { Vex, XS, Ib } },
10319   },
10320   {
10321     /* VEX_W_0F71_R_6_P_2  */
10322     { "vpsllw",         { Vex, XS, Ib } },
10323   },
10324   {
10325     /* VEX_W_0F72_R_2_P_2  */
10326     { "vpsrld",         { Vex, XS, Ib } },
10327   },
10328   {
10329     /* VEX_W_0F72_R_4_P_2  */
10330     { "vpsrad",         { Vex, XS, Ib } },
10331   },
10332   {
10333     /* VEX_W_0F72_R_6_P_2  */
10334     { "vpslld",         { Vex, XS, Ib } },
10335   },
10336   {
10337     /* VEX_W_0F73_R_2_P_2  */
10338     { "vpsrlq",         { Vex, XS, Ib } },
10339   },
10340   {
10341     /* VEX_W_0F73_R_3_P_2  */
10342     { "vpsrldq",        { Vex, XS, Ib } },
10343   },
10344   {
10345     /* VEX_W_0F73_R_6_P_2  */
10346     { "vpsllq",         { Vex, XS, Ib } },
10347   },
10348   {
10349     /* VEX_W_0F73_R_7_P_2  */
10350     { "vpslldq",        { Vex, XS, Ib } },
10351   },
10352   {
10353     /* VEX_W_0F74_P_2 */
10354     { "vpcmpeqb",       { XM, Vex, EXx } },
10355   },
10356   {
10357     /* VEX_W_0F75_P_2 */
10358     { "vpcmpeqw",       { XM, Vex, EXx } },
10359   },
10360   {
10361     /* VEX_W_0F76_P_2 */
10362     { "vpcmpeqd",       { XM, Vex, EXx } },
10363   },
10364   {
10365     /* VEX_W_0F77_P_0 */
10366     { "",               { VZERO } },
10367   },
10368   {
10369     /* VEX_W_0F7C_P_2 */
10370     { "vhaddpd",        { XM, Vex, EXx } },
10371   },
10372   {
10373     /* VEX_W_0F7C_P_3 */
10374     { "vhaddps",        { XM, Vex, EXx } },
10375   },
10376   {
10377     /* VEX_W_0F7D_P_2 */
10378     { "vhsubpd",        { XM, Vex, EXx } },
10379   },
10380   {
10381     /* VEX_W_0F7D_P_3 */
10382     { "vhsubps",        { XM, Vex, EXx } },
10383   },
10384   {
10385     /* VEX_W_0F7E_P_1 */
10386     { "vmovq",          { XMScalar, EXqScalar } },
10387   },
10388   {
10389     /* VEX_W_0F7F_P_1 */
10390     { "vmovdqu",        { EXxS, XM } },
10391   },
10392   {
10393     /* VEX_W_0F7F_P_2 */
10394     { "vmovdqa",        { EXxS, XM } },
10395   },
10396   {
10397     /* VEX_W_0F90_P_0_LEN_0 */
10398     { "kmovw",          { MaskG, MaskE } },
10399   },
10400   {
10401     /* VEX_W_0F91_P_0_LEN_0 */
10402     { "kmovw",          { Ew, MaskG } },
10403   },
10404   {
10405     /* VEX_W_0F92_P_0_LEN_0 */
10406     { "kmovw",          { MaskG, Rdq } },
10407   },
10408   {
10409     /* VEX_W_0F93_P_0_LEN_0 */
10410     { "kmovw",          { Gdq, MaskR } },
10411   },
10412   {
10413     /* VEX_W_0F98_P_0_LEN_0 */
10414     { "kortestw",       { MaskG, MaskR } },
10415   },
10416   {
10417     /* VEX_W_0FAE_R_2_M_0 */
10418     { "vldmxcsr",       { Md } },
10419   },
10420   {
10421     /* VEX_W_0FAE_R_3_M_0 */
10422     { "vstmxcsr",       { Md } },
10423   },
10424   {
10425     /* VEX_W_0FC2_P_0 */
10426     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10427   },
10428   {
10429     /* VEX_W_0FC2_P_1 */
10430     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10431   },
10432   {
10433     /* VEX_W_0FC2_P_2 */
10434     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10435   },
10436   {
10437     /* VEX_W_0FC2_P_3 */
10438     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10439   },
10440   {
10441     /* VEX_W_0FC4_P_2 */
10442     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10443   },
10444   {
10445     /* VEX_W_0FC5_P_2 */
10446     { "vpextrw",        { Gdq, XS, Ib } },
10447   },
10448   {
10449     /* VEX_W_0FD0_P_2 */
10450     { "vaddsubpd",      { XM, Vex, EXx } },
10451   },
10452   {
10453     /* VEX_W_0FD0_P_3 */
10454     { "vaddsubps",      { XM, Vex, EXx } },
10455   },
10456   {
10457     /* VEX_W_0FD1_P_2 */
10458     { "vpsrlw",         { XM, Vex, EXxmm } },
10459   },
10460   {
10461     /* VEX_W_0FD2_P_2 */
10462     { "vpsrld",         { XM, Vex, EXxmm } },
10463   },
10464   {
10465     /* VEX_W_0FD3_P_2 */
10466     { "vpsrlq",         { XM, Vex, EXxmm } },
10467   },
10468   {
10469     /* VEX_W_0FD4_P_2 */
10470     { "vpaddq",         { XM, Vex, EXx } },
10471   },
10472   {
10473     /* VEX_W_0FD5_P_2 */
10474     { "vpmullw",        { XM, Vex, EXx } },
10475   },
10476   {
10477     /* VEX_W_0FD6_P_2 */
10478     { "vmovq",          { EXqScalarS, XMScalar } },
10479   },
10480   {
10481     /* VEX_W_0FD7_P_2_M_1 */
10482     { "vpmovmskb",      { Gdq, XS } },
10483   },
10484   {
10485     /* VEX_W_0FD8_P_2 */
10486     { "vpsubusb",       { XM, Vex, EXx } },
10487   },
10488   {
10489     /* VEX_W_0FD9_P_2 */
10490     { "vpsubusw",       { XM, Vex, EXx } },
10491   },
10492   {
10493     /* VEX_W_0FDA_P_2 */
10494     { "vpminub",        { XM, Vex, EXx } },
10495   },
10496   {
10497     /* VEX_W_0FDB_P_2 */
10498     { "vpand",          { XM, Vex, EXx } },
10499   },
10500   {
10501     /* VEX_W_0FDC_P_2 */
10502     { "vpaddusb",       { XM, Vex, EXx } },
10503   },
10504   {
10505     /* VEX_W_0FDD_P_2 */
10506     { "vpaddusw",       { XM, Vex, EXx } },
10507   },
10508   {
10509     /* VEX_W_0FDE_P_2 */
10510     { "vpmaxub",        { XM, Vex, EXx } },
10511   },
10512   {
10513     /* VEX_W_0FDF_P_2 */
10514     { "vpandn",         { XM, Vex, EXx } },
10515   },
10516   {
10517     /* VEX_W_0FE0_P_2  */
10518     { "vpavgb",         { XM, Vex, EXx } },
10519   },
10520   {
10521     /* VEX_W_0FE1_P_2  */
10522     { "vpsraw",         { XM, Vex, EXxmm } },
10523   },
10524   {
10525     /* VEX_W_0FE2_P_2  */
10526     { "vpsrad",         { XM, Vex, EXxmm } },
10527   },
10528   {
10529     /* VEX_W_0FE3_P_2  */
10530     { "vpavgw",         { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0FE4_P_2  */
10534     { "vpmulhuw",       { XM, Vex, EXx } },
10535   },
10536   {
10537     /* VEX_W_0FE5_P_2  */
10538     { "vpmulhw",        { XM, Vex, EXx } },
10539   },
10540   {
10541     /* VEX_W_0FE6_P_1  */
10542     { "vcvtdq2pd",      { XM, EXxmmq } },
10543   },
10544   {
10545     /* VEX_W_0FE6_P_2  */
10546     { "vcvttpd2dq%XY",  { XMM, EXx } },
10547   },
10548   {
10549     /* VEX_W_0FE6_P_3  */
10550     { "vcvtpd2dq%XY",   { XMM, EXx } },
10551   },
10552   {
10553     /* VEX_W_0FE7_P_2_M_0 */
10554     { "vmovntdq",       { Mx, XM } },
10555   },
10556   {
10557     /* VEX_W_0FE8_P_2  */
10558     { "vpsubsb",        { XM, Vex, EXx } },
10559   },
10560   {
10561     /* VEX_W_0FE9_P_2  */
10562     { "vpsubsw",        { XM, Vex, EXx } },
10563   },
10564   {
10565     /* VEX_W_0FEA_P_2  */
10566     { "vpminsw",        { XM, Vex, EXx } },
10567   },
10568   {
10569     /* VEX_W_0FEB_P_2  */
10570     { "vpor",           { XM, Vex, EXx } },
10571   },
10572   {
10573     /* VEX_W_0FEC_P_2  */
10574     { "vpaddsb",        { XM, Vex, EXx } },
10575   },
10576   {
10577     /* VEX_W_0FED_P_2  */
10578     { "vpaddsw",        { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0FEE_P_2  */
10582     { "vpmaxsw",        { XM, Vex, EXx } },
10583   },
10584   {
10585     /* VEX_W_0FEF_P_2  */
10586     { "vpxor",          { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0FF0_P_3_M_0 */
10590     { "vlddqu",         { XM, M } },
10591   },
10592   {
10593     /* VEX_W_0FF1_P_2 */
10594     { "vpsllw",         { XM, Vex, EXxmm } },
10595   },
10596   {
10597     /* VEX_W_0FF2_P_2 */
10598     { "vpslld",         { XM, Vex, EXxmm } },
10599   },
10600   {
10601     /* VEX_W_0FF3_P_2 */
10602     { "vpsllq",         { XM, Vex, EXxmm } },
10603   },
10604   {
10605     /* VEX_W_0FF4_P_2 */
10606     { "vpmuludq",       { XM, Vex, EXx } },
10607   },
10608   {
10609     /* VEX_W_0FF5_P_2 */
10610     { "vpmaddwd",       { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0FF6_P_2 */
10614     { "vpsadbw",        { XM, Vex, EXx } },
10615   },
10616   {
10617     /* VEX_W_0FF7_P_2 */
10618     { "vmaskmovdqu",    { XM, XS } },
10619   },
10620   {
10621     /* VEX_W_0FF8_P_2 */
10622     { "vpsubb",         { XM, Vex, EXx } },
10623   },
10624   {
10625     /* VEX_W_0FF9_P_2 */
10626     { "vpsubw",         { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0FFA_P_2 */
10630     { "vpsubd",         { XM, Vex, EXx } },
10631   },
10632   {
10633     /* VEX_W_0FFB_P_2 */
10634     { "vpsubq",         { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0FFC_P_2 */
10638     { "vpaddb",         { XM, Vex, EXx } },
10639   },
10640   {
10641     /* VEX_W_0FFD_P_2 */
10642     { "vpaddw",         { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0FFE_P_2 */
10646     { "vpaddd",         { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F3800_P_2  */
10650     { "vpshufb",        { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F3801_P_2  */
10654     { "vphaddw",        { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F3802_P_2  */
10658     { "vphaddd",        { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F3803_P_2  */
10662     { "vphaddsw",       { XM, Vex, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F3804_P_2  */
10666     { "vpmaddubsw",     { XM, Vex, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F3805_P_2  */
10670     { "vphsubw",        { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F3806_P_2  */
10674     { "vphsubd",        { XM, Vex, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F3807_P_2  */
10678     { "vphsubsw",       { XM, Vex, EXx } },
10679   },
10680   {
10681     /* VEX_W_0F3808_P_2  */
10682     { "vpsignb",        { XM, Vex, EXx } },
10683   },
10684   {
10685     /* VEX_W_0F3809_P_2  */
10686     { "vpsignw",        { XM, Vex, EXx } },
10687   },
10688   {
10689     /* VEX_W_0F380A_P_2  */
10690     { "vpsignd",        { XM, Vex, EXx } },
10691   },
10692   {
10693     /* VEX_W_0F380B_P_2  */
10694     { "vpmulhrsw",      { XM, Vex, EXx } },
10695   },
10696   {
10697     /* VEX_W_0F380C_P_2  */
10698     { "vpermilps",      { XM, Vex, EXx } },
10699   },
10700   {
10701     /* VEX_W_0F380D_P_2  */
10702     { "vpermilpd",      { XM, Vex, EXx } },
10703   },
10704   {
10705     /* VEX_W_0F380E_P_2  */
10706     { "vtestps",        { XM, EXx } },
10707   },
10708   {
10709     /* VEX_W_0F380F_P_2  */
10710     { "vtestpd",        { XM, EXx } },
10711   },
10712   {
10713     /* VEX_W_0F3816_P_2  */
10714     { "vpermps",        { XM, Vex, EXx } },
10715   },
10716   {
10717     /* VEX_W_0F3817_P_2 */
10718     { "vptest",         { XM, EXx } },
10719   },
10720   {
10721     /* VEX_W_0F3818_P_2 */
10722     { "vbroadcastss",   { XM, EXxmm_md } },
10723   },
10724   {
10725     /* VEX_W_0F3819_P_2 */
10726     { "vbroadcastsd",   { XM, EXxmm_mq } },
10727   },
10728   {
10729     /* VEX_W_0F381A_P_2_M_0 */
10730     { "vbroadcastf128", { XM, Mxmm } },
10731   },
10732   {
10733     /* VEX_W_0F381C_P_2 */
10734     { "vpabsb",         { XM, EXx } },
10735   },
10736   {
10737     /* VEX_W_0F381D_P_2 */
10738     { "vpabsw",         { XM, EXx } },
10739   },
10740   {
10741     /* VEX_W_0F381E_P_2 */
10742     { "vpabsd",         { XM, EXx } },
10743   },
10744   {
10745     /* VEX_W_0F3820_P_2 */
10746     { "vpmovsxbw",      { XM, EXxmmq } },
10747   },
10748   {
10749     /* VEX_W_0F3821_P_2 */
10750     { "vpmovsxbd",      { XM, EXxmmqd } },
10751   },
10752   {
10753     /* VEX_W_0F3822_P_2 */
10754     { "vpmovsxbq",      { XM, EXxmmdw } },
10755   },
10756   {
10757     /* VEX_W_0F3823_P_2 */
10758     { "vpmovsxwd",      { XM, EXxmmq } },
10759   },
10760   {
10761     /* VEX_W_0F3824_P_2 */
10762     { "vpmovsxwq",      { XM, EXxmmqd } },
10763   },
10764   {
10765     /* VEX_W_0F3825_P_2 */
10766     { "vpmovsxdq",      { XM, EXxmmq } },
10767   },
10768   {
10769     /* VEX_W_0F3828_P_2 */
10770     { "vpmuldq",        { XM, Vex, EXx } },
10771   },
10772   {
10773     /* VEX_W_0F3829_P_2 */
10774     { "vpcmpeqq",       { XM, Vex, EXx } },
10775   },
10776   {
10777     /* VEX_W_0F382A_P_2_M_0 */
10778     { "vmovntdqa",      { XM, Mx } },
10779   },
10780   {
10781     /* VEX_W_0F382B_P_2 */
10782     { "vpackusdw",      { XM, Vex, EXx } },
10783   },
10784   {
10785     /* VEX_W_0F382C_P_2_M_0 */
10786     { "vmaskmovps",     { XM, Vex, Mx } },
10787   },
10788   {
10789     /* VEX_W_0F382D_P_2_M_0 */
10790     { "vmaskmovpd",     { XM, Vex, Mx } },
10791   },
10792   {
10793     /* VEX_W_0F382E_P_2_M_0 */
10794     { "vmaskmovps",     { Mx, Vex, XM } },
10795   },
10796   {
10797     /* VEX_W_0F382F_P_2_M_0 */
10798     { "vmaskmovpd",     { Mx, Vex, XM } },
10799   },
10800   {
10801     /* VEX_W_0F3830_P_2 */
10802     { "vpmovzxbw",      { XM, EXxmmq } },
10803   },
10804   {
10805     /* VEX_W_0F3831_P_2 */
10806     { "vpmovzxbd",      { XM, EXxmmqd } },
10807   },
10808   {
10809     /* VEX_W_0F3832_P_2 */
10810     { "vpmovzxbq",      { XM, EXxmmdw } },
10811   },
10812   {
10813     /* VEX_W_0F3833_P_2 */
10814     { "vpmovzxwd",      { XM, EXxmmq } },
10815   },
10816   {
10817     /* VEX_W_0F3834_P_2 */
10818     { "vpmovzxwq",      { XM, EXxmmqd } },
10819   },
10820   {
10821     /* VEX_W_0F3835_P_2 */
10822     { "vpmovzxdq",      { XM, EXxmmq } },
10823   },
10824   {
10825     /* VEX_W_0F3836_P_2  */
10826     { "vpermd",         { XM, Vex, EXx } },
10827   },
10828   {
10829     /* VEX_W_0F3837_P_2 */
10830     { "vpcmpgtq",       { XM, Vex, EXx } },
10831   },
10832   {
10833     /* VEX_W_0F3838_P_2 */
10834     { "vpminsb",        { XM, Vex, EXx } },
10835   },
10836   {
10837     /* VEX_W_0F3839_P_2 */
10838     { "vpminsd",        { XM, Vex, EXx } },
10839   },
10840   {
10841     /* VEX_W_0F383A_P_2 */
10842     { "vpminuw",        { XM, Vex, EXx } },
10843   },
10844   {
10845     /* VEX_W_0F383B_P_2 */
10846     { "vpminud",        { XM, Vex, EXx } },
10847   },
10848   {
10849     /* VEX_W_0F383C_P_2 */
10850     { "vpmaxsb",        { XM, Vex, EXx } },
10851   },
10852   {
10853     /* VEX_W_0F383D_P_2 */
10854     { "vpmaxsd",        { XM, Vex, EXx } },
10855   },
10856   {
10857     /* VEX_W_0F383E_P_2 */
10858     { "vpmaxuw",        { XM, Vex, EXx } },
10859   },
10860   {
10861     /* VEX_W_0F383F_P_2 */
10862     { "vpmaxud",        { XM, Vex, EXx } },
10863   },
10864   {
10865     /* VEX_W_0F3840_P_2 */
10866     { "vpmulld",        { XM, Vex, EXx } },
10867   },
10868   {
10869     /* VEX_W_0F3841_P_2 */
10870     { "vphminposuw",    { XM, EXx } },
10871   },
10872   {
10873     /* VEX_W_0F3846_P_2 */
10874     { "vpsravd",        { XM, Vex, EXx } },
10875   },
10876   {
10877     /* VEX_W_0F3858_P_2 */
10878     { "vpbroadcastd", { XM, EXxmm_md } },
10879   },
10880   {
10881     /* VEX_W_0F3859_P_2 */
10882     { "vpbroadcastq",   { XM, EXxmm_mq } },
10883   },
10884   {
10885     /* VEX_W_0F385A_P_2_M_0 */
10886     { "vbroadcasti128", { XM, Mxmm } },
10887   },
10888   {
10889     /* VEX_W_0F3878_P_2 */
10890     { "vpbroadcastb",   { XM, EXxmm_mb } },
10891   },
10892   {
10893     /* VEX_W_0F3879_P_2 */
10894     { "vpbroadcastw",   { XM, EXxmm_mw } },
10895   },
10896   {
10897     /* VEX_W_0F38DB_P_2 */
10898     { "vaesimc",        { XM, EXx } },
10899   },
10900   {
10901     /* VEX_W_0F38DC_P_2 */
10902     { "vaesenc",        { XM, Vex128, EXx } },
10903   },
10904   {
10905     /* VEX_W_0F38DD_P_2 */
10906     { "vaesenclast",    { XM, Vex128, EXx } },
10907   },
10908   {
10909     /* VEX_W_0F38DE_P_2 */
10910     { "vaesdec",        { XM, Vex128, EXx } },
10911   },
10912   {
10913     /* VEX_W_0F38DF_P_2 */
10914     { "vaesdeclast",    { XM, Vex128, EXx } },
10915   },
10916   {
10917     /* VEX_W_0F3A00_P_2 */
10918     { Bad_Opcode },
10919     { "vpermq",         { XM, EXx, Ib } },
10920   },
10921   {
10922     /* VEX_W_0F3A01_P_2 */
10923     { Bad_Opcode },
10924     { "vpermpd",        { XM, EXx, Ib } },
10925   },
10926   {
10927     /* VEX_W_0F3A02_P_2 */
10928     { "vpblendd",       { XM, Vex, EXx, Ib } },
10929   },
10930   {
10931     /* VEX_W_0F3A04_P_2 */
10932     { "vpermilps",      { XM, EXx, Ib } },
10933   },
10934   {
10935     /* VEX_W_0F3A05_P_2 */
10936     { "vpermilpd",      { XM, EXx, Ib } },
10937   },
10938   {
10939     /* VEX_W_0F3A06_P_2 */
10940     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10941   },
10942   {
10943     /* VEX_W_0F3A08_P_2 */
10944     { "vroundps",       { XM, EXx, Ib } },
10945   },
10946   {
10947     /* VEX_W_0F3A09_P_2 */
10948     { "vroundpd",       { XM, EXx, Ib } },
10949   },
10950   {
10951     /* VEX_W_0F3A0A_P_2 */
10952     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10953   },
10954   {
10955     /* VEX_W_0F3A0B_P_2 */
10956     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10957   },
10958   {
10959     /* VEX_W_0F3A0C_P_2 */
10960     { "vblendps",       { XM, Vex, EXx, Ib } },
10961   },
10962   {
10963     /* VEX_W_0F3A0D_P_2 */
10964     { "vblendpd",       { XM, Vex, EXx, Ib } },
10965   },
10966   {
10967     /* VEX_W_0F3A0E_P_2 */
10968     { "vpblendw",       { XM, Vex, EXx, Ib } },
10969   },
10970   {
10971     /* VEX_W_0F3A0F_P_2 */
10972     { "vpalignr",       { XM, Vex, EXx, Ib } },
10973   },
10974   {
10975     /* VEX_W_0F3A14_P_2 */
10976     { "vpextrb",        { Edqb, XM, Ib } },
10977   },
10978   {
10979     /* VEX_W_0F3A15_P_2 */
10980     { "vpextrw",        { Edqw, XM, Ib } },
10981   },
10982   {
10983     /* VEX_W_0F3A18_P_2 */
10984     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10985   },
10986   {
10987     /* VEX_W_0F3A19_P_2 */
10988     { "vextractf128",   { EXxmm, XM, Ib } },
10989   },
10990   {
10991     /* VEX_W_0F3A20_P_2 */
10992     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10993   },
10994   {
10995     /* VEX_W_0F3A21_P_2 */
10996     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10997   },
10998   {
10999     /* VEX_W_0F3A30_P_2 */
11000     { Bad_Opcode },
11001     { "kshiftrw",       { MaskG, MaskR, Ib } },
11002   },
11003   {
11004     /* VEX_W_0F3A32_P_2 */
11005     { Bad_Opcode },
11006     { "kshiftlw",       { MaskG, MaskR, Ib } },
11007   },
11008   {
11009     /* VEX_W_0F3A38_P_2 */
11010     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11011   },
11012   {
11013     /* VEX_W_0F3A39_P_2 */
11014     { "vextracti128",   { EXxmm, XM, Ib } },
11015   },
11016   {
11017     /* VEX_W_0F3A40_P_2 */
11018     { "vdpps",          { XM, Vex, EXx, Ib } },
11019   },
11020   {
11021     /* VEX_W_0F3A41_P_2 */
11022     { "vdppd",          { XM, Vex128, EXx, Ib } },
11023   },
11024   {
11025     /* VEX_W_0F3A42_P_2 */
11026     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11027   },
11028   {
11029     /* VEX_W_0F3A44_P_2 */
11030     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11031   },
11032   {
11033     /* VEX_W_0F3A46_P_2 */
11034     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11035   },
11036   {
11037     /* VEX_W_0F3A48_P_2 */
11038     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11039     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11040   },
11041   {
11042     /* VEX_W_0F3A49_P_2 */
11043     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11044     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11045   },
11046   {
11047     /* VEX_W_0F3A4A_P_2 */
11048     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11049   },
11050   {
11051     /* VEX_W_0F3A4B_P_2 */
11052     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11053   },
11054   {
11055     /* VEX_W_0F3A4C_P_2 */
11056     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11057   },
11058   {
11059     /* VEX_W_0F3A60_P_2 */
11060     { "vpcmpestrm",     { XM, EXx, Ib } },
11061   },
11062   {
11063     /* VEX_W_0F3A61_P_2 */
11064     { "vpcmpestri",     { XM, EXx, Ib } },
11065   },
11066   {
11067     /* VEX_W_0F3A62_P_2 */
11068     { "vpcmpistrm",     { XM, EXx, Ib } },
11069   },
11070   {
11071     /* VEX_W_0F3A63_P_2 */
11072     { "vpcmpistri",     { XM, EXx, Ib } },
11073   },
11074   {
11075     /* VEX_W_0F3ADF_P_2 */
11076     { "vaeskeygenassist", { XM, EXx, Ib } },
11077   },
11078 #define NEED_VEX_W_TABLE
11079 #include "i386-dis-evex.h"
11080 #undef NEED_VEX_W_TABLE
11081 };
11082
11083 static const struct dis386 mod_table[][2] = {
11084   {
11085     /* MOD_8D */
11086     { "leaS",           { Gv, M } },
11087   },
11088   {
11089     /* MOD_C6_REG_7 */
11090     { Bad_Opcode },
11091     { RM_TABLE (RM_C6_REG_7) },
11092   },
11093   {
11094     /* MOD_C7_REG_7 */
11095     { Bad_Opcode },
11096     { RM_TABLE (RM_C7_REG_7) },
11097   },
11098   {
11099     /* MOD_FF_REG_3 */
11100     { "Jcall{T|}", { indirEp } },
11101   },
11102   {
11103     /* MOD_FF_REG_5 */
11104     { "Jjmp{T|}", { indirEp } },
11105   },
11106   {
11107     /* MOD_0F01_REG_0 */
11108     { X86_64_TABLE (X86_64_0F01_REG_0) },
11109     { RM_TABLE (RM_0F01_REG_0) },
11110   },
11111   {
11112     /* MOD_0F01_REG_1 */
11113     { X86_64_TABLE (X86_64_0F01_REG_1) },
11114     { RM_TABLE (RM_0F01_REG_1) },
11115   },
11116   {
11117     /* MOD_0F01_REG_2 */
11118     { X86_64_TABLE (X86_64_0F01_REG_2) },
11119     { RM_TABLE (RM_0F01_REG_2) },
11120   },
11121   {
11122     /* MOD_0F01_REG_3 */
11123     { X86_64_TABLE (X86_64_0F01_REG_3) },
11124     { RM_TABLE (RM_0F01_REG_3) },
11125   },
11126   {
11127     /* MOD_0F01_REG_7 */
11128     { "invlpg",         { Mb } },
11129     { RM_TABLE (RM_0F01_REG_7) },
11130   },
11131   {
11132     /* MOD_0F12_PREFIX_0 */
11133     { "movlps",         { XM, EXq } },
11134     { "movhlps",        { XM, EXq } },
11135   },
11136   {
11137     /* MOD_0F13 */
11138     { "movlpX",         { EXq, XM } },
11139   },
11140   {
11141     /* MOD_0F16_PREFIX_0 */
11142     { "movhps",         { XM, EXq } },
11143     { "movlhps",        { XM, EXq } },
11144   },
11145   {
11146     /* MOD_0F17 */
11147     { "movhpX",         { EXq, XM } },
11148   },
11149   {
11150     /* MOD_0F18_REG_0 */
11151     { "prefetchnta",    { Mb } },
11152   },
11153   {
11154     /* MOD_0F18_REG_1 */
11155     { "prefetcht0",     { Mb } },
11156   },
11157   {
11158     /* MOD_0F18_REG_2 */
11159     { "prefetcht1",     { Mb } },
11160   },
11161   {
11162     /* MOD_0F18_REG_3 */
11163     { "prefetcht2",     { Mb } },
11164   },
11165   {
11166     /* MOD_0F18_REG_4 */
11167     { "nop/reserved",   { Mb } },
11168   },
11169   {
11170     /* MOD_0F18_REG_5 */
11171     { "nop/reserved",   { Mb } },
11172   },
11173   {
11174     /* MOD_0F18_REG_6 */
11175     { "nop/reserved",   { Mb } },
11176   },
11177   {
11178     /* MOD_0F18_REG_7 */
11179     { "nop/reserved",   { Mb } },
11180   },
11181   {
11182     /* MOD_0F1A_PREFIX_0 */
11183     { "bndldx",         { Gbnd, Ev_bnd } },
11184     { "nopQ",           { Ev } },
11185   },
11186   {
11187     /* MOD_0F1B_PREFIX_0 */
11188     { "bndstx",         { Ev_bnd, Gbnd } },
11189     { "nopQ",           { Ev } },
11190   },
11191   {
11192     /* MOD_0F1B_PREFIX_1 */
11193     { "bndmk",          { Gbnd, Ev_bnd } },
11194     { "nopQ",           { Ev } },
11195   },
11196   {
11197     /* MOD_0F20 */
11198     { Bad_Opcode },
11199     { "movZ",           { Rm, Cm } },
11200   },
11201   {
11202     /* MOD_0F21 */
11203     { Bad_Opcode },
11204     { "movZ",           { Rm, Dm } },
11205   },
11206   {
11207     /* MOD_0F22 */
11208     { Bad_Opcode },
11209     { "movZ",           { Cm, Rm } },
11210   },
11211   {
11212     /* MOD_0F23 */
11213     { Bad_Opcode },
11214     { "movZ",           { Dm, Rm } },
11215   },
11216   {
11217     /* MOD_0F24 */
11218     { Bad_Opcode },
11219     { "movL",           { Rd, Td } },
11220   },
11221   {
11222     /* MOD_0F26 */
11223     { Bad_Opcode },
11224     { "movL",           { Td, Rd } },
11225   },
11226   {
11227     /* MOD_0F2B_PREFIX_0 */
11228     {"movntps",         { Mx, XM } },
11229   },
11230   {
11231     /* MOD_0F2B_PREFIX_1 */
11232     {"movntss",         { Md, XM } },
11233   },
11234   {
11235     /* MOD_0F2B_PREFIX_2 */
11236     {"movntpd",         { Mx, XM } },
11237   },
11238   {
11239     /* MOD_0F2B_PREFIX_3 */
11240     {"movntsd",         { Mq, XM } },
11241   },
11242   {
11243     /* MOD_0F51 */
11244     { Bad_Opcode },
11245     { "movmskpX",       { Gdq, XS } },
11246   },
11247   {
11248     /* MOD_0F71_REG_2 */
11249     { Bad_Opcode },
11250     { "psrlw",          { MS, Ib } },
11251   },
11252   {
11253     /* MOD_0F71_REG_4 */
11254     { Bad_Opcode },
11255     { "psraw",          { MS, Ib } },
11256   },
11257   {
11258     /* MOD_0F71_REG_6 */
11259     { Bad_Opcode },
11260     { "psllw",          { MS, Ib } },
11261   },
11262   {
11263     /* MOD_0F72_REG_2 */
11264     { Bad_Opcode },
11265     { "psrld",          { MS, Ib } },
11266   },
11267   {
11268     /* MOD_0F72_REG_4 */
11269     { Bad_Opcode },
11270     { "psrad",          { MS, Ib } },
11271   },
11272   {
11273     /* MOD_0F72_REG_6 */
11274     { Bad_Opcode },
11275     { "pslld",          { MS, Ib } },
11276   },
11277   {
11278     /* MOD_0F73_REG_2 */
11279     { Bad_Opcode },
11280     { "psrlq",          { MS, Ib } },
11281   },
11282   {
11283     /* MOD_0F73_REG_3 */
11284     { Bad_Opcode },
11285     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11286   },
11287   {
11288     /* MOD_0F73_REG_6 */
11289     { Bad_Opcode },
11290     { "psllq",          { MS, Ib } },
11291   },
11292   {
11293     /* MOD_0F73_REG_7 */
11294     { Bad_Opcode },
11295     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11296   },
11297   {
11298     /* MOD_0FAE_REG_0 */
11299     { "fxsave",         { FXSAVE } },
11300     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11301   },
11302   {
11303     /* MOD_0FAE_REG_1 */
11304     { "fxrstor",        { FXSAVE } },
11305     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11306   },
11307   {
11308     /* MOD_0FAE_REG_2 */
11309     { "ldmxcsr",        { Md } },
11310     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11311   },
11312   {
11313     /* MOD_0FAE_REG_3 */
11314     { "stmxcsr",        { Md } },
11315     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11316   },
11317   {
11318     /* MOD_0FAE_REG_4 */
11319     { "xsave",          { FXSAVE } },
11320   },
11321   {
11322     /* MOD_0FAE_REG_5 */
11323     { "xrstor",         { FXSAVE } },
11324     { RM_TABLE (RM_0FAE_REG_5) },
11325   },
11326   {
11327     /* MOD_0FAE_REG_6 */
11328     { "xsaveopt",       { FXSAVE } },
11329     { RM_TABLE (RM_0FAE_REG_6) },
11330   },
11331   {
11332     /* MOD_0FAE_REG_7 */
11333     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11334     { RM_TABLE (RM_0FAE_REG_7) },
11335   },
11336   {
11337     /* MOD_0FB2 */
11338     { "lssS",           { Gv, Mp } },
11339   },
11340   {
11341     /* MOD_0FB4 */
11342     { "lfsS",           { Gv, Mp } },
11343   },
11344   {
11345     /* MOD_0FB5 */
11346     { "lgsS",           { Gv, Mp } },
11347   },
11348   {
11349     /* MOD_0FC7_REG_3 */
11350     { "xrstors",                { FXSAVE } },
11351   },
11352   {
11353     /* MOD_0FC7_REG_4 */
11354     { "xsavec",         { FXSAVE } },
11355   },
11356   {
11357     /* MOD_0FC7_REG_5 */
11358     { "xsaves",         { FXSAVE } },
11359   },
11360   {
11361     /* MOD_0FC7_REG_6 */
11362     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11363     { "rdrand",         { Ev } },
11364   },
11365   {
11366     /* MOD_0FC7_REG_7 */
11367     { "vmptrst",        { Mq } },
11368     { "rdseed",         { Ev } },
11369   },
11370   {
11371     /* MOD_0FD7 */
11372     { Bad_Opcode },
11373     { "pmovmskb",       { Gdq, MS } },
11374   },
11375   {
11376     /* MOD_0FE7_PREFIX_2 */
11377     { "movntdq",        { Mx, XM } },
11378   },
11379   {
11380     /* MOD_0FF0_PREFIX_3 */
11381     { "lddqu",          { XM, M } },
11382   },
11383   {
11384     /* MOD_0F382A_PREFIX_2 */
11385     { "movntdqa",       { XM, Mx } },
11386   },
11387   {
11388     /* MOD_62_32BIT */
11389     { "bound{S|}",      { Gv, Ma } },
11390     { EVEX_TABLE (EVEX_0F) },
11391   },
11392   {
11393     /* MOD_C4_32BIT */
11394     { "lesS",           { Gv, Mp } },
11395     { VEX_C4_TABLE (VEX_0F) },
11396   },
11397   {
11398     /* MOD_C5_32BIT */
11399     { "ldsS",           { Gv, Mp } },
11400     { VEX_C5_TABLE (VEX_0F) },
11401   },
11402   {
11403     /* MOD_VEX_0F12_PREFIX_0 */
11404     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11405     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11406   },
11407   {
11408     /* MOD_VEX_0F13 */
11409     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11410   },
11411   {
11412     /* MOD_VEX_0F16_PREFIX_0 */
11413     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11414     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11415   },
11416   {
11417     /* MOD_VEX_0F17 */
11418     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11419   },
11420   {
11421     /* MOD_VEX_0F2B */
11422     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11423   },
11424   {
11425     /* MOD_VEX_0F50 */
11426     { Bad_Opcode },
11427     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11428   },
11429   {
11430     /* MOD_VEX_0F71_REG_2 */
11431     { Bad_Opcode },
11432     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11433   },
11434   {
11435     /* MOD_VEX_0F71_REG_4 */
11436     { Bad_Opcode },
11437     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11438   },
11439   {
11440     /* MOD_VEX_0F71_REG_6 */
11441     { Bad_Opcode },
11442     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11443   },
11444   {
11445     /* MOD_VEX_0F72_REG_2 */
11446     { Bad_Opcode },
11447     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11448   },
11449   {
11450     /* MOD_VEX_0F72_REG_4 */
11451     { Bad_Opcode },
11452     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11453   },
11454   {
11455     /* MOD_VEX_0F72_REG_6 */
11456     { Bad_Opcode },
11457     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11458   },
11459   {
11460     /* MOD_VEX_0F73_REG_2 */
11461     { Bad_Opcode },
11462     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11463   },
11464   {
11465     /* MOD_VEX_0F73_REG_3 */
11466     { Bad_Opcode },
11467     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11468   },
11469   {
11470     /* MOD_VEX_0F73_REG_6 */
11471     { Bad_Opcode },
11472     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11473   },
11474   {
11475     /* MOD_VEX_0F73_REG_7 */
11476     { Bad_Opcode },
11477     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11478   },
11479   {
11480     /* MOD_VEX_0FAE_REG_2 */
11481     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11482   },
11483   {
11484     /* MOD_VEX_0FAE_REG_3 */
11485     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11486   },
11487   {
11488     /* MOD_VEX_0FD7_PREFIX_2 */
11489     { Bad_Opcode },
11490     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11491   },
11492   {
11493     /* MOD_VEX_0FE7_PREFIX_2 */
11494     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11495   },
11496   {
11497     /* MOD_VEX_0FF0_PREFIX_3 */
11498     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11499   },
11500   {
11501     /* MOD_VEX_0F381A_PREFIX_2 */
11502     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11503   },
11504   {
11505     /* MOD_VEX_0F382A_PREFIX_2 */
11506     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11507   },
11508   {
11509     /* MOD_VEX_0F382C_PREFIX_2 */
11510     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11511   },
11512   {
11513     /* MOD_VEX_0F382D_PREFIX_2 */
11514     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11515   },
11516   {
11517     /* MOD_VEX_0F382E_PREFIX_2 */
11518     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11519   },
11520   {
11521     /* MOD_VEX_0F382F_PREFIX_2 */
11522     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11523   },
11524   {
11525     /* MOD_VEX_0F385A_PREFIX_2 */
11526     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11527   },
11528   {
11529     /* MOD_VEX_0F388C_PREFIX_2 */
11530     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11531   },
11532   {
11533     /* MOD_VEX_0F388E_PREFIX_2 */
11534     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11535   },
11536 #define NEED_MOD_TABLE
11537 #include "i386-dis-evex.h"
11538 #undef NEED_MOD_TABLE
11539 };
11540
11541 static const struct dis386 rm_table[][8] = {
11542   {
11543     /* RM_C6_REG_7 */
11544     { "xabort",         { Skip_MODRM, Ib } },
11545   },
11546   {
11547     /* RM_C7_REG_7 */
11548     { "xbeginT",        { Skip_MODRM, Jv } },
11549   },
11550   {
11551     /* RM_0F01_REG_0 */
11552     { Bad_Opcode },
11553     { "vmcall",         { Skip_MODRM } },
11554     { "vmlaunch",       { Skip_MODRM } },
11555     { "vmresume",       { Skip_MODRM } },
11556     { "vmxoff",         { Skip_MODRM } },
11557   },
11558   {
11559     /* RM_0F01_REG_1 */
11560     { "monitor",        { { OP_Monitor, 0 } } },
11561     { "mwait",          { { OP_Mwait, 0 } } },
11562     { "clac",           { Skip_MODRM } },
11563     { "stac",           { Skip_MODRM } },
11564     { Bad_Opcode },
11565     { Bad_Opcode },
11566     { Bad_Opcode },
11567     { "encls",          { Skip_MODRM } },
11568   },
11569   {
11570     /* RM_0F01_REG_2 */
11571     { "xgetbv",         { Skip_MODRM } },
11572     { "xsetbv",         { Skip_MODRM } },
11573     { Bad_Opcode },
11574     { Bad_Opcode },
11575     { "vmfunc",         { Skip_MODRM } },
11576     { "xend",           { Skip_MODRM } },
11577     { "xtest",          { Skip_MODRM } },
11578     { "enclu",          { Skip_MODRM } },
11579   },
11580   {
11581     /* RM_0F01_REG_3 */
11582     { "vmrun",          { Skip_MODRM } },
11583     { "vmmcall",        { Skip_MODRM } },
11584     { "vmload",         { Skip_MODRM } },
11585     { "vmsave",         { Skip_MODRM } },
11586     { "stgi",           { Skip_MODRM } },
11587     { "clgi",           { Skip_MODRM } },
11588     { "skinit",         { Skip_MODRM } },
11589     { "invlpga",        { Skip_MODRM } },
11590   },
11591   {
11592     /* RM_0F01_REG_7 */
11593     { "swapgs",         { Skip_MODRM } },
11594     { "rdtscp",         { Skip_MODRM } },
11595   },
11596   {
11597     /* RM_0FAE_REG_5 */
11598     { "lfence",         { Skip_MODRM } },
11599   },
11600   {
11601     /* RM_0FAE_REG_6 */
11602     { "mfence",         { Skip_MODRM } },
11603   },
11604   {
11605     /* RM_0FAE_REG_7 */
11606     { "sfence",         { Skip_MODRM } },
11607   },
11608 };
11609
11610 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11611
11612 /* We use the high bit to indicate different name for the same
11613    prefix.  */
11614 #define REP_PREFIX      (0xf3 | 0x100)
11615 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11616 #define XRELEASE_PREFIX (0xf3 | 0x400)
11617 #define BND_PREFIX      (0xf2 | 0x400)
11618
11619 static int
11620 ckprefix (void)
11621 {
11622   int newrex, i, length;
11623   rex = 0;
11624   rex_ignored = 0;
11625   prefixes = 0;
11626   used_prefixes = 0;
11627   rex_used = 0;
11628   last_lock_prefix = -1;
11629   last_repz_prefix = -1;
11630   last_repnz_prefix = -1;
11631   last_data_prefix = -1;
11632   last_addr_prefix = -1;
11633   last_rex_prefix = -1;
11634   last_seg_prefix = -1;
11635   fwait_prefix = -1;
11636   active_seg_prefix = 0;
11637   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11638     all_prefixes[i] = 0;
11639   i = 0;
11640   length = 0;
11641   /* The maximum instruction length is 15bytes.  */
11642   while (length < MAX_CODE_LENGTH - 1)
11643     {
11644       FETCH_DATA (the_info, codep + 1);
11645       newrex = 0;
11646       switch (*codep)
11647         {
11648         /* REX prefixes family.  */
11649         case 0x40:
11650         case 0x41:
11651         case 0x42:
11652         case 0x43:
11653         case 0x44:
11654         case 0x45:
11655         case 0x46:
11656         case 0x47:
11657         case 0x48:
11658         case 0x49:
11659         case 0x4a:
11660         case 0x4b:
11661         case 0x4c:
11662         case 0x4d:
11663         case 0x4e:
11664         case 0x4f:
11665           if (address_mode == mode_64bit)
11666             newrex = *codep;
11667           else
11668             return 1;
11669           last_rex_prefix = i;
11670           break;
11671         case 0xf3:
11672           prefixes |= PREFIX_REPZ;
11673           last_repz_prefix = i;
11674           break;
11675         case 0xf2:
11676           prefixes |= PREFIX_REPNZ;
11677           last_repnz_prefix = i;
11678           break;
11679         case 0xf0:
11680           prefixes |= PREFIX_LOCK;
11681           last_lock_prefix = i;
11682           break;
11683         case 0x2e:
11684           prefixes |= PREFIX_CS;
11685           last_seg_prefix = i;
11686           active_seg_prefix = PREFIX_CS;
11687           break;
11688         case 0x36:
11689           prefixes |= PREFIX_SS;
11690           last_seg_prefix = i;
11691           active_seg_prefix = PREFIX_SS;
11692           break;
11693         case 0x3e:
11694           prefixes |= PREFIX_DS;
11695           last_seg_prefix = i;
11696           active_seg_prefix = PREFIX_DS;
11697           break;
11698         case 0x26:
11699           prefixes |= PREFIX_ES;
11700           last_seg_prefix = i;
11701           active_seg_prefix = PREFIX_ES;
11702           break;
11703         case 0x64:
11704           prefixes |= PREFIX_FS;
11705           last_seg_prefix = i;
11706           active_seg_prefix = PREFIX_FS;
11707           break;
11708         case 0x65:
11709           prefixes |= PREFIX_GS;
11710           last_seg_prefix = i;
11711           active_seg_prefix = PREFIX_GS;
11712           break;
11713         case 0x66:
11714           prefixes |= PREFIX_DATA;
11715           last_data_prefix = i;
11716           break;
11717         case 0x67:
11718           prefixes |= PREFIX_ADDR;
11719           last_addr_prefix = i;
11720           break;
11721         case FWAIT_OPCODE:
11722           /* fwait is really an instruction.  If there are prefixes
11723              before the fwait, they belong to the fwait, *not* to the
11724              following instruction.  */
11725           fwait_prefix = i;
11726           if (prefixes || rex)
11727             {
11728               prefixes |= PREFIX_FWAIT;
11729               codep++;
11730               /* This ensures that the previous REX prefixes are noticed
11731                  as unused prefixes, as in the return case below.  */
11732               rex_used = rex;
11733               return 1;
11734             }
11735           prefixes = PREFIX_FWAIT;
11736           break;
11737         default:
11738           return 1;
11739         }
11740       /* Rex is ignored when followed by another prefix.  */
11741       if (rex)
11742         {
11743           rex_used = rex;
11744           return 1;
11745         }
11746       if (*codep != FWAIT_OPCODE)
11747         all_prefixes[i++] = *codep;
11748       rex = newrex;
11749       codep++;
11750       length++;
11751     }
11752   return 0;
11753 }
11754
11755 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11756    prefix byte.  */
11757
11758 static const char *
11759 prefix_name (int pref, int sizeflag)
11760 {
11761   static const char *rexes [16] =
11762     {
11763       "rex",            /* 0x40 */
11764       "rex.B",          /* 0x41 */
11765       "rex.X",          /* 0x42 */
11766       "rex.XB",         /* 0x43 */
11767       "rex.R",          /* 0x44 */
11768       "rex.RB",         /* 0x45 */
11769       "rex.RX",         /* 0x46 */
11770       "rex.RXB",        /* 0x47 */
11771       "rex.W",          /* 0x48 */
11772       "rex.WB",         /* 0x49 */
11773       "rex.WX",         /* 0x4a */
11774       "rex.WXB",        /* 0x4b */
11775       "rex.WR",         /* 0x4c */
11776       "rex.WRB",        /* 0x4d */
11777       "rex.WRX",        /* 0x4e */
11778       "rex.WRXB",       /* 0x4f */
11779     };
11780
11781   switch (pref)
11782     {
11783     /* REX prefixes family.  */
11784     case 0x40:
11785     case 0x41:
11786     case 0x42:
11787     case 0x43:
11788     case 0x44:
11789     case 0x45:
11790     case 0x46:
11791     case 0x47:
11792     case 0x48:
11793     case 0x49:
11794     case 0x4a:
11795     case 0x4b:
11796     case 0x4c:
11797     case 0x4d:
11798     case 0x4e:
11799     case 0x4f:
11800       return rexes [pref - 0x40];
11801     case 0xf3:
11802       return "repz";
11803     case 0xf2:
11804       return "repnz";
11805     case 0xf0:
11806       return "lock";
11807     case 0x2e:
11808       return "cs";
11809     case 0x36:
11810       return "ss";
11811     case 0x3e:
11812       return "ds";
11813     case 0x26:
11814       return "es";
11815     case 0x64:
11816       return "fs";
11817     case 0x65:
11818       return "gs";
11819     case 0x66:
11820       return (sizeflag & DFLAG) ? "data16" : "data32";
11821     case 0x67:
11822       if (address_mode == mode_64bit)
11823         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11824       else
11825         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11826     case FWAIT_OPCODE:
11827       return "fwait";
11828     case REP_PREFIX:
11829       return "rep";
11830     case XACQUIRE_PREFIX:
11831       return "xacquire";
11832     case XRELEASE_PREFIX:
11833       return "xrelease";
11834     case BND_PREFIX:
11835       return "bnd";
11836     default:
11837       return NULL;
11838     }
11839 }
11840
11841 static char op_out[MAX_OPERANDS][100];
11842 static int op_ad, op_index[MAX_OPERANDS];
11843 static int two_source_ops;
11844 static bfd_vma op_address[MAX_OPERANDS];
11845 static bfd_vma op_riprel[MAX_OPERANDS];
11846 static bfd_vma start_pc;
11847
11848 /*
11849  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11850  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11851  *   section of the "Virtual 8086 Mode" chapter.)
11852  * 'pc' should be the address of this instruction, it will
11853  *   be used to print the target address if this is a relative jump or call
11854  * The function returns the length of this instruction in bytes.
11855  */
11856
11857 static char intel_syntax;
11858 static char intel_mnemonic = !SYSV386_COMPAT;
11859 static char open_char;
11860 static char close_char;
11861 static char separator_char;
11862 static char scale_char;
11863
11864 /* Here for backwards compatibility.  When gdb stops using
11865    print_insn_i386_att and print_insn_i386_intel these functions can
11866    disappear, and print_insn_i386 be merged into print_insn.  */
11867 int
11868 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11869 {
11870   intel_syntax = 0;
11871
11872   return print_insn (pc, info);
11873 }
11874
11875 int
11876 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11877 {
11878   intel_syntax = 1;
11879
11880   return print_insn (pc, info);
11881 }
11882
11883 int
11884 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11885 {
11886   intel_syntax = -1;
11887
11888   return print_insn (pc, info);
11889 }
11890
11891 void
11892 print_i386_disassembler_options (FILE *stream)
11893 {
11894   fprintf (stream, _("\n\
11895 The following i386/x86-64 specific disassembler options are supported for use\n\
11896 with the -M switch (multiple options should be separated by commas):\n"));
11897
11898   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11899   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11900   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11901   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11902   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11903   fprintf (stream, _("  att-mnemonic\n"
11904                      "              Display instruction in AT&T mnemonic\n"));
11905   fprintf (stream, _("  intel-mnemonic\n"
11906                      "              Display instruction in Intel mnemonic\n"));
11907   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11908   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11909   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11910   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11911   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11912   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11913 }
11914
11915 /* Bad opcode.  */
11916 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11917
11918 /* Get a pointer to struct dis386 with a valid name.  */
11919
11920 static const struct dis386 *
11921 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11922 {
11923   int vindex, vex_table_index;
11924
11925   if (dp->name != NULL)
11926     return dp;
11927
11928   switch (dp->op[0].bytemode)
11929     {
11930     case USE_REG_TABLE:
11931       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11932       break;
11933
11934     case USE_MOD_TABLE:
11935       vindex = modrm.mod == 0x3 ? 1 : 0;
11936       dp = &mod_table[dp->op[1].bytemode][vindex];
11937       break;
11938
11939     case USE_RM_TABLE:
11940       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11941       break;
11942
11943     case USE_PREFIX_TABLE:
11944       if (need_vex)
11945         {
11946           /* The prefix in VEX is implicit.  */
11947           switch (vex.prefix)
11948             {
11949             case 0:
11950               vindex = 0;
11951               break;
11952             case REPE_PREFIX_OPCODE:
11953               vindex = 1;
11954               break;
11955             case DATA_PREFIX_OPCODE:
11956               vindex = 2;
11957               break;
11958             case REPNE_PREFIX_OPCODE:
11959               vindex = 3;
11960               break;
11961             default:
11962               abort ();
11963               break;
11964             }
11965         }
11966       else
11967         {
11968           int last_prefix = -1;
11969           int prefix = 0;
11970           vindex = 0;
11971           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11972              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11973              last one wins.  */
11974           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11975             {
11976               if (last_repz_prefix > last_repnz_prefix)
11977                 {
11978                   vindex = 1;
11979                   prefix = PREFIX_REPZ;
11980                   last_prefix = last_repz_prefix;
11981                 }
11982               else
11983                 {
11984                   vindex = 3;
11985                   prefix = PREFIX_REPNZ;
11986                   last_prefix = last_repnz_prefix;
11987                 }
11988
11989               /* Ignore the invalid index if it isn't mandatory.  */
11990               if (!mandatory_prefix
11991                   && (prefix_table[dp->op[1].bytemode][vindex].name
11992                       == NULL)
11993                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
11994                       == 0))
11995                 vindex = 0;
11996             }
11997
11998           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11999             {
12000               vindex = 2;
12001               prefix = PREFIX_DATA;
12002               last_prefix = last_data_prefix;
12003             }
12004
12005           if (vindex != 0)
12006             {
12007               used_prefixes |= prefix;
12008               all_prefixes[last_prefix] = 0;
12009             }
12010         }
12011       dp = &prefix_table[dp->op[1].bytemode][vindex];
12012       break;
12013
12014     case USE_X86_64_TABLE:
12015       vindex = address_mode == mode_64bit ? 1 : 0;
12016       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12017       break;
12018
12019     case USE_3BYTE_TABLE:
12020       FETCH_DATA (info, codep + 2);
12021       vindex = *codep++;
12022       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12023       end_codep = codep;
12024       modrm.mod = (*codep >> 6) & 3;
12025       modrm.reg = (*codep >> 3) & 7;
12026       modrm.rm = *codep & 7;
12027       break;
12028
12029     case USE_VEX_LEN_TABLE:
12030       if (!need_vex)
12031         abort ();
12032
12033       switch (vex.length)
12034         {
12035         case 128:
12036           vindex = 0;
12037           break;
12038         case 256:
12039           vindex = 1;
12040           break;
12041         default:
12042           abort ();
12043           break;
12044         }
12045
12046       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12047       break;
12048
12049     case USE_XOP_8F_TABLE:
12050       FETCH_DATA (info, codep + 3);
12051       /* All bits in the REX prefix are ignored.  */
12052       rex_ignored = rex;
12053       rex = ~(*codep >> 5) & 0x7;
12054
12055       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12056       switch ((*codep & 0x1f))
12057         {
12058         default:
12059           dp = &bad_opcode;
12060           return dp;
12061         case 0x8:
12062           vex_table_index = XOP_08;
12063           break;
12064         case 0x9:
12065           vex_table_index = XOP_09;
12066           break;
12067         case 0xa:
12068           vex_table_index = XOP_0A;
12069           break;
12070         }
12071       codep++;
12072       vex.w = *codep & 0x80;
12073       if (vex.w && address_mode == mode_64bit)
12074         rex |= REX_W;
12075
12076       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12077       if (address_mode != mode_64bit
12078           && vex.register_specifier > 0x7)
12079         {
12080           dp = &bad_opcode;
12081           return dp;
12082         }
12083
12084       vex.length = (*codep & 0x4) ? 256 : 128;
12085       switch ((*codep & 0x3))
12086         {
12087         case 0:
12088           vex.prefix = 0;
12089           break;
12090         case 1:
12091           vex.prefix = DATA_PREFIX_OPCODE;
12092           break;
12093         case 2:
12094           vex.prefix = REPE_PREFIX_OPCODE;
12095           break;
12096         case 3:
12097           vex.prefix = REPNE_PREFIX_OPCODE;
12098           break;
12099         }
12100       need_vex = 1;
12101       need_vex_reg = 1;
12102       codep++;
12103       vindex = *codep++;
12104       dp = &xop_table[vex_table_index][vindex];
12105
12106       end_codep = codep;
12107       FETCH_DATA (info, codep + 1);
12108       modrm.mod = (*codep >> 6) & 3;
12109       modrm.reg = (*codep >> 3) & 7;
12110       modrm.rm = *codep & 7;
12111       break;
12112
12113     case USE_VEX_C4_TABLE:
12114       /* VEX prefix.  */
12115       FETCH_DATA (info, codep + 3);
12116       /* All bits in the REX prefix are ignored.  */
12117       rex_ignored = rex;
12118       rex = ~(*codep >> 5) & 0x7;
12119       switch ((*codep & 0x1f))
12120         {
12121         default:
12122           dp = &bad_opcode;
12123           return dp;
12124         case 0x1:
12125           vex_table_index = VEX_0F;
12126           break;
12127         case 0x2:
12128           vex_table_index = VEX_0F38;
12129           break;
12130         case 0x3:
12131           vex_table_index = VEX_0F3A;
12132           break;
12133         }
12134       codep++;
12135       vex.w = *codep & 0x80;
12136       if (vex.w && address_mode == mode_64bit)
12137         rex |= REX_W;
12138
12139       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12140       if (address_mode != mode_64bit
12141           && vex.register_specifier > 0x7)
12142         {
12143           dp = &bad_opcode;
12144           return dp;
12145         }
12146
12147       vex.length = (*codep & 0x4) ? 256 : 128;
12148       switch ((*codep & 0x3))
12149         {
12150         case 0:
12151           vex.prefix = 0;
12152           break;
12153         case 1:
12154           vex.prefix = DATA_PREFIX_OPCODE;
12155           break;
12156         case 2:
12157           vex.prefix = REPE_PREFIX_OPCODE;
12158           break;
12159         case 3:
12160           vex.prefix = REPNE_PREFIX_OPCODE;
12161           break;
12162         }
12163       need_vex = 1;
12164       need_vex_reg = 1;
12165       codep++;
12166       vindex = *codep++;
12167       dp = &vex_table[vex_table_index][vindex];
12168       end_codep = codep;
12169       /* There is no MODRM byte for VEX [82|77].  */
12170       if (vindex != 0x77 && vindex != 0x82)
12171         {
12172           FETCH_DATA (info, codep + 1);
12173           modrm.mod = (*codep >> 6) & 3;
12174           modrm.reg = (*codep >> 3) & 7;
12175           modrm.rm = *codep & 7;
12176         }
12177       break;
12178
12179     case USE_VEX_C5_TABLE:
12180       /* VEX prefix.  */
12181       FETCH_DATA (info, codep + 2);
12182       /* All bits in the REX prefix are ignored.  */
12183       rex_ignored = rex;
12184       rex = (*codep & 0x80) ? 0 : REX_R;
12185
12186       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12187       if (address_mode != mode_64bit
12188           && vex.register_specifier > 0x7)
12189         {
12190           dp = &bad_opcode;
12191           return dp;
12192         }
12193
12194       vex.w = 0;
12195
12196       vex.length = (*codep & 0x4) ? 256 : 128;
12197       switch ((*codep & 0x3))
12198         {
12199         case 0:
12200           vex.prefix = 0;
12201           break;
12202         case 1:
12203           vex.prefix = DATA_PREFIX_OPCODE;
12204           break;
12205         case 2:
12206           vex.prefix = REPE_PREFIX_OPCODE;
12207           break;
12208         case 3:
12209           vex.prefix = REPNE_PREFIX_OPCODE;
12210           break;
12211         }
12212       need_vex = 1;
12213       need_vex_reg = 1;
12214       codep++;
12215       vindex = *codep++;
12216       dp = &vex_table[dp->op[1].bytemode][vindex];
12217       end_codep = codep;
12218       /* There is no MODRM byte for VEX [82|77].  */
12219       if (vindex != 0x77 && vindex != 0x82)
12220         {
12221           FETCH_DATA (info, codep + 1);
12222           modrm.mod = (*codep >> 6) & 3;
12223           modrm.reg = (*codep >> 3) & 7;
12224           modrm.rm = *codep & 7;
12225         }
12226       break;
12227
12228     case USE_VEX_W_TABLE:
12229       if (!need_vex)
12230         abort ();
12231
12232       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12233       break;
12234
12235     case USE_EVEX_TABLE:
12236       two_source_ops = 0;
12237       /* EVEX prefix.  */
12238       vex.evex = 1;
12239       FETCH_DATA (info, codep + 4);
12240       /* All bits in the REX prefix are ignored.  */
12241       rex_ignored = rex;
12242       /* The first byte after 0x62.  */
12243       rex = ~(*codep >> 5) & 0x7;
12244       vex.r = *codep & 0x10;
12245       switch ((*codep & 0xf))
12246         {
12247         default:
12248           return &bad_opcode;
12249         case 0x1:
12250           vex_table_index = EVEX_0F;
12251           break;
12252         case 0x2:
12253           vex_table_index = EVEX_0F38;
12254           break;
12255         case 0x3:
12256           vex_table_index = EVEX_0F3A;
12257           break;
12258         }
12259
12260       /* The second byte after 0x62.  */
12261       codep++;
12262       vex.w = *codep & 0x80;
12263       if (vex.w && address_mode == mode_64bit)
12264         rex |= REX_W;
12265
12266       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12267       if (address_mode != mode_64bit)
12268         {
12269           /* In 16/32-bit mode silently ignore following bits.  */
12270           rex &= ~REX_B;
12271           vex.r = 1;
12272           vex.v = 1;
12273           vex.register_specifier &= 0x7;
12274         }
12275
12276       /* The U bit.  */
12277       if (!(*codep & 0x4))
12278         return &bad_opcode;
12279
12280       switch ((*codep & 0x3))
12281         {
12282         case 0:
12283           vex.prefix = 0;
12284           break;
12285         case 1:
12286           vex.prefix = DATA_PREFIX_OPCODE;
12287           break;
12288         case 2:
12289           vex.prefix = REPE_PREFIX_OPCODE;
12290           break;
12291         case 3:
12292           vex.prefix = REPNE_PREFIX_OPCODE;
12293           break;
12294         }
12295
12296       /* The third byte after 0x62.  */
12297       codep++;
12298
12299       /* Remember the static rounding bits.  */
12300       vex.ll = (*codep >> 5) & 3;
12301       vex.b = (*codep & 0x10) != 0;
12302
12303       vex.v = *codep & 0x8;
12304       vex.mask_register_specifier = *codep & 0x7;
12305       vex.zeroing = *codep & 0x80;
12306
12307       need_vex = 1;
12308       need_vex_reg = 1;
12309       codep++;
12310       vindex = *codep++;
12311       dp = &evex_table[vex_table_index][vindex];
12312       end_codep = codep;
12313       FETCH_DATA (info, codep + 1);
12314       modrm.mod = (*codep >> 6) & 3;
12315       modrm.reg = (*codep >> 3) & 7;
12316       modrm.rm = *codep & 7;
12317
12318       /* Set vector length.  */
12319       if (modrm.mod == 3 && vex.b)
12320         vex.length = 512;
12321       else
12322         {
12323           switch (vex.ll)
12324             {
12325             case 0x0:
12326               vex.length = 128;
12327               break;
12328             case 0x1:
12329               vex.length = 256;
12330               break;
12331             case 0x2:
12332               vex.length = 512;
12333               break;
12334             default:
12335               return &bad_opcode;
12336             }
12337         }
12338       break;
12339
12340     case 0:
12341       dp = &bad_opcode;
12342       break;
12343
12344     default:
12345       abort ();
12346     }
12347
12348   if (dp->name != NULL)
12349     return dp;
12350   else
12351     return get_valid_dis386 (dp, info);
12352 }
12353
12354 static void
12355 get_sib (disassemble_info *info, int sizeflag)
12356 {
12357   /* If modrm.mod == 3, operand must be register.  */
12358   if (need_modrm
12359       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12360       && modrm.mod != 3
12361       && modrm.rm == 4)
12362     {
12363       FETCH_DATA (info, codep + 2);
12364       sib.index = (codep [1] >> 3) & 7;
12365       sib.scale = (codep [1] >> 6) & 3;
12366       sib.base = codep [1] & 7;
12367     }
12368 }
12369
12370 static int
12371 print_insn (bfd_vma pc, disassemble_info *info)
12372 {
12373   const struct dis386 *dp;
12374   int i;
12375   char *op_txt[MAX_OPERANDS];
12376   int needcomma;
12377   int sizeflag, orig_sizeflag;
12378   const char *p;
12379   struct dis_private priv;
12380   int prefix_length;
12381
12382   priv.orig_sizeflag = AFLAG | DFLAG;
12383   if ((info->mach & bfd_mach_i386_i386) != 0)
12384     address_mode = mode_32bit;
12385   else if (info->mach == bfd_mach_i386_i8086)
12386     {
12387       address_mode = mode_16bit;
12388       priv.orig_sizeflag = 0;
12389     }
12390   else
12391     address_mode = mode_64bit;
12392
12393   if (intel_syntax == (char) -1)
12394     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12395
12396   for (p = info->disassembler_options; p != NULL; )
12397     {
12398       if (CONST_STRNEQ (p, "x86-64"))
12399         {
12400           address_mode = mode_64bit;
12401           priv.orig_sizeflag = AFLAG | DFLAG;
12402         }
12403       else if (CONST_STRNEQ (p, "i386"))
12404         {
12405           address_mode = mode_32bit;
12406           priv.orig_sizeflag = AFLAG | DFLAG;
12407         }
12408       else if (CONST_STRNEQ (p, "i8086"))
12409         {
12410           address_mode = mode_16bit;
12411           priv.orig_sizeflag = 0;
12412         }
12413       else if (CONST_STRNEQ (p, "intel"))
12414         {
12415           intel_syntax = 1;
12416           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12417             intel_mnemonic = 1;
12418         }
12419       else if (CONST_STRNEQ (p, "att"))
12420         {
12421           intel_syntax = 0;
12422           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12423             intel_mnemonic = 0;
12424         }
12425       else if (CONST_STRNEQ (p, "addr"))
12426         {
12427           if (address_mode == mode_64bit)
12428             {
12429               if (p[4] == '3' && p[5] == '2')
12430                 priv.orig_sizeflag &= ~AFLAG;
12431               else if (p[4] == '6' && p[5] == '4')
12432                 priv.orig_sizeflag |= AFLAG;
12433             }
12434           else
12435             {
12436               if (p[4] == '1' && p[5] == '6')
12437                 priv.orig_sizeflag &= ~AFLAG;
12438               else if (p[4] == '3' && p[5] == '2')
12439                 priv.orig_sizeflag |= AFLAG;
12440             }
12441         }
12442       else if (CONST_STRNEQ (p, "data"))
12443         {
12444           if (p[4] == '1' && p[5] == '6')
12445             priv.orig_sizeflag &= ~DFLAG;
12446           else if (p[4] == '3' && p[5] == '2')
12447             priv.orig_sizeflag |= DFLAG;
12448         }
12449       else if (CONST_STRNEQ (p, "suffix"))
12450         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12451
12452       p = strchr (p, ',');
12453       if (p != NULL)
12454         p++;
12455     }
12456
12457   if (intel_syntax)
12458     {
12459       names64 = intel_names64;
12460       names32 = intel_names32;
12461       names16 = intel_names16;
12462       names8 = intel_names8;
12463       names8rex = intel_names8rex;
12464       names_seg = intel_names_seg;
12465       names_mm = intel_names_mm;
12466       names_bnd = intel_names_bnd;
12467       names_xmm = intel_names_xmm;
12468       names_ymm = intel_names_ymm;
12469       names_zmm = intel_names_zmm;
12470       index64 = intel_index64;
12471       index32 = intel_index32;
12472       names_mask = intel_names_mask;
12473       index16 = intel_index16;
12474       open_char = '[';
12475       close_char = ']';
12476       separator_char = '+';
12477       scale_char = '*';
12478     }
12479   else
12480     {
12481       names64 = att_names64;
12482       names32 = att_names32;
12483       names16 = att_names16;
12484       names8 = att_names8;
12485       names8rex = att_names8rex;
12486       names_seg = att_names_seg;
12487       names_mm = att_names_mm;
12488       names_bnd = att_names_bnd;
12489       names_xmm = att_names_xmm;
12490       names_ymm = att_names_ymm;
12491       names_zmm = att_names_zmm;
12492       index64 = att_index64;
12493       index32 = att_index32;
12494       names_mask = att_names_mask;
12495       index16 = att_index16;
12496       open_char = '(';
12497       close_char =  ')';
12498       separator_char = ',';
12499       scale_char = ',';
12500     }
12501
12502   /* The output looks better if we put 7 bytes on a line, since that
12503      puts most long word instructions on a single line.  Use 8 bytes
12504      for Intel L1OM.  */
12505   if ((info->mach & bfd_mach_l1om) != 0)
12506     info->bytes_per_line = 8;
12507   else
12508     info->bytes_per_line = 7;
12509
12510   info->private_data = &priv;
12511   priv.max_fetched = priv.the_buffer;
12512   priv.insn_start = pc;
12513
12514   obuf[0] = 0;
12515   for (i = 0; i < MAX_OPERANDS; ++i)
12516     {
12517       op_out[i][0] = 0;
12518       op_index[i] = -1;
12519     }
12520
12521   the_info = info;
12522   start_pc = pc;
12523   start_codep = priv.the_buffer;
12524   codep = priv.the_buffer;
12525
12526   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12527     {
12528       const char *name;
12529
12530       /* Getting here means we tried for data but didn't get it.  That
12531          means we have an incomplete instruction of some sort.  Just
12532          print the first byte as a prefix or a .byte pseudo-op.  */
12533       if (codep > priv.the_buffer)
12534         {
12535           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12536           if (name != NULL)
12537             (*info->fprintf_func) (info->stream, "%s", name);
12538           else
12539             {
12540               /* Just print the first byte as a .byte instruction.  */
12541               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12542                                      (unsigned int) priv.the_buffer[0]);
12543             }
12544
12545           return 1;
12546         }
12547
12548       return -1;
12549     }
12550
12551   obufp = obuf;
12552   sizeflag = priv.orig_sizeflag;
12553
12554   if (!ckprefix () || rex_used)
12555     {
12556       /* Too many prefixes or unused REX prefixes.  */
12557       for (i = 0;
12558            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12559            i++)
12560         (*info->fprintf_func) (info->stream, "%s%s",
12561                                i == 0 ? "" : " ",
12562                                prefix_name (all_prefixes[i], sizeflag));
12563       return i;
12564     }
12565
12566   insn_codep = codep;
12567
12568   FETCH_DATA (info, codep + 1);
12569   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12570
12571   if (((prefixes & PREFIX_FWAIT)
12572        && ((*codep < 0xd8) || (*codep > 0xdf))))
12573     {
12574       /* Handle prefixes before fwait.  */
12575       for (i = 0; i < fwait_prefix && all_prefixes[i];
12576            i++)
12577         (*info->fprintf_func) (info->stream, "%s ",
12578                                prefix_name (all_prefixes[i], sizeflag));
12579       (*info->fprintf_func) (info->stream, "fwait");
12580       return i + 1;
12581     }
12582
12583   if (*codep == 0x0f)
12584     {
12585       unsigned char threebyte;
12586       FETCH_DATA (info, codep + 2);
12587       threebyte = *++codep;
12588       dp = &dis386_twobyte[threebyte];
12589       need_modrm = twobyte_has_modrm[*codep];
12590       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
12591       codep++;
12592     }
12593   else
12594     {
12595       dp = &dis386[*codep];
12596       need_modrm = onebyte_has_modrm[*codep];
12597       mandatory_prefix = 0;
12598       codep++;
12599     }
12600
12601   /* Save sizeflag for printing the extra prefixes later before updating
12602      it for mnemonic and operand processing.  The prefix names depend
12603      only on the address mode.  */
12604   orig_sizeflag = sizeflag;
12605   if (prefixes & PREFIX_ADDR)
12606     sizeflag ^= AFLAG;
12607   if ((prefixes & PREFIX_DATA))
12608     sizeflag ^= DFLAG;
12609
12610   end_codep = codep;
12611   if (need_modrm)
12612     {
12613       FETCH_DATA (info, codep + 1);
12614       modrm.mod = (*codep >> 6) & 3;
12615       modrm.reg = (*codep >> 3) & 7;
12616       modrm.rm = *codep & 7;
12617     }
12618
12619   need_vex = 0;
12620   need_vex_reg = 0;
12621   vex_w_done = 0;
12622   vex.evex = 0;
12623
12624   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12625     {
12626       get_sib (info, sizeflag);
12627       dofloat (sizeflag);
12628     }
12629   else
12630     {
12631       dp = get_valid_dis386 (dp, info);
12632       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12633         {
12634           get_sib (info, sizeflag);
12635           for (i = 0; i < MAX_OPERANDS; ++i)
12636             {
12637               obufp = op_out[i];
12638               op_ad = MAX_OPERANDS - 1 - i;
12639               if (dp->op[i].rtn)
12640                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12641               /* For EVEX instruction after the last operand masking
12642                  should be printed.  */
12643               if (i == 0 && vex.evex)
12644                 {
12645                   /* Don't print {%k0}.  */
12646                   if (vex.mask_register_specifier)
12647                     {
12648                       oappend ("{");
12649                       oappend (names_mask[vex.mask_register_specifier]);
12650                       oappend ("}");
12651                     }
12652                   if (vex.zeroing)
12653                     oappend ("{z}");
12654                 }
12655             }
12656         }
12657     }
12658
12659   /* Check if the REX prefix is used.  */
12660   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12661     all_prefixes[last_rex_prefix] = 0;
12662
12663   /* Check if the SEG prefix is used.  */
12664   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12665                    | PREFIX_FS | PREFIX_GS)) != 0
12666       && (used_prefixes & active_seg_prefix) != 0)
12667     all_prefixes[last_seg_prefix] = 0;
12668
12669   /* Check if the ADDR prefix is used.  */
12670   if ((prefixes & PREFIX_ADDR) != 0
12671       && (used_prefixes & PREFIX_ADDR) != 0)
12672     all_prefixes[last_addr_prefix] = 0;
12673
12674   /* Check if the DATA prefix is used.  */
12675   if ((prefixes & PREFIX_DATA) != 0
12676       && (used_prefixes & PREFIX_DATA) != 0)
12677     all_prefixes[last_data_prefix] = 0;
12678
12679   /* Print the extra prefixes.  */
12680   prefix_length = 0;
12681   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12682     if (all_prefixes[i])
12683       {
12684         const char *name;
12685         name = prefix_name (all_prefixes[i], orig_sizeflag);
12686         if (name == NULL)
12687           abort ();
12688         prefix_length += strlen (name) + 1;
12689         (*info->fprintf_func) (info->stream, "%s ", name);
12690       }
12691
12692   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12693      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12694      used by putop and MMX/SSE operand and may be overriden by the
12695      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12696      separately.  */
12697   if (mandatory_prefix
12698       && dp != &bad_opcode
12699       && (((prefixes
12700             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12701            && (used_prefixes
12702                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12703           || ((((prefixes
12704                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12705                 == PREFIX_DATA)
12706                && (used_prefixes & PREFIX_DATA) == 0))))
12707     {
12708       (*info->fprintf_func) (info->stream, "(bad)");
12709       return end_codep - priv.the_buffer;
12710     }
12711
12712   /* Check maximum code length.  */
12713   if ((codep - start_codep) > MAX_CODE_LENGTH)
12714     {
12715       (*info->fprintf_func) (info->stream, "(bad)");
12716       return MAX_CODE_LENGTH;
12717     }
12718
12719   obufp = mnemonicendp;
12720   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12721     oappend (" ");
12722   oappend (" ");
12723   (*info->fprintf_func) (info->stream, "%s", obuf);
12724
12725   /* The enter and bound instructions are printed with operands in the same
12726      order as the intel book; everything else is printed in reverse order.  */
12727   if (intel_syntax || two_source_ops)
12728     {
12729       bfd_vma riprel;
12730
12731       for (i = 0; i < MAX_OPERANDS; ++i)
12732         op_txt[i] = op_out[i];
12733
12734       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12735         {
12736           op_ad = op_index[i];
12737           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12738           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12739           riprel = op_riprel[i];
12740           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12741           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12742         }
12743     }
12744   else
12745     {
12746       for (i = 0; i < MAX_OPERANDS; ++i)
12747         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12748     }
12749
12750   needcomma = 0;
12751   for (i = 0; i < MAX_OPERANDS; ++i)
12752     if (*op_txt[i])
12753       {
12754         if (needcomma)
12755           (*info->fprintf_func) (info->stream, ",");
12756         if (op_index[i] != -1 && !op_riprel[i])
12757           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12758         else
12759           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12760         needcomma = 1;
12761       }
12762
12763   for (i = 0; i < MAX_OPERANDS; i++)
12764     if (op_index[i] != -1 && op_riprel[i])
12765       {
12766         (*info->fprintf_func) (info->stream, "        # ");
12767         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12768                                                 + op_address[op_index[i]]), info);
12769         break;
12770       }
12771   return codep - priv.the_buffer;
12772 }
12773
12774 static const char *float_mem[] = {
12775   /* d8 */
12776   "fadd{s|}",
12777   "fmul{s|}",
12778   "fcom{s|}",
12779   "fcomp{s|}",
12780   "fsub{s|}",
12781   "fsubr{s|}",
12782   "fdiv{s|}",
12783   "fdivr{s|}",
12784   /* d9 */
12785   "fld{s|}",
12786   "(bad)",
12787   "fst{s|}",
12788   "fstp{s|}",
12789   "fldenvIC",
12790   "fldcw",
12791   "fNstenvIC",
12792   "fNstcw",
12793   /* da */
12794   "fiadd{l|}",
12795   "fimul{l|}",
12796   "ficom{l|}",
12797   "ficomp{l|}",
12798   "fisub{l|}",
12799   "fisubr{l|}",
12800   "fidiv{l|}",
12801   "fidivr{l|}",
12802   /* db */
12803   "fild{l|}",
12804   "fisttp{l|}",
12805   "fist{l|}",
12806   "fistp{l|}",
12807   "(bad)",
12808   "fld{t||t|}",
12809   "(bad)",
12810   "fstp{t||t|}",
12811   /* dc */
12812   "fadd{l|}",
12813   "fmul{l|}",
12814   "fcom{l|}",
12815   "fcomp{l|}",
12816   "fsub{l|}",
12817   "fsubr{l|}",
12818   "fdiv{l|}",
12819   "fdivr{l|}",
12820   /* dd */
12821   "fld{l|}",
12822   "fisttp{ll|}",
12823   "fst{l||}",
12824   "fstp{l|}",
12825   "frstorIC",
12826   "(bad)",
12827   "fNsaveIC",
12828   "fNstsw",
12829   /* de */
12830   "fiadd",
12831   "fimul",
12832   "ficom",
12833   "ficomp",
12834   "fisub",
12835   "fisubr",
12836   "fidiv",
12837   "fidivr",
12838   /* df */
12839   "fild",
12840   "fisttp",
12841   "fist",
12842   "fistp",
12843   "fbld",
12844   "fild{ll|}",
12845   "fbstp",
12846   "fistp{ll|}",
12847 };
12848
12849 static const unsigned char float_mem_mode[] = {
12850   /* d8 */
12851   d_mode,
12852   d_mode,
12853   d_mode,
12854   d_mode,
12855   d_mode,
12856   d_mode,
12857   d_mode,
12858   d_mode,
12859   /* d9 */
12860   d_mode,
12861   0,
12862   d_mode,
12863   d_mode,
12864   0,
12865   w_mode,
12866   0,
12867   w_mode,
12868   /* da */
12869   d_mode,
12870   d_mode,
12871   d_mode,
12872   d_mode,
12873   d_mode,
12874   d_mode,
12875   d_mode,
12876   d_mode,
12877   /* db */
12878   d_mode,
12879   d_mode,
12880   d_mode,
12881   d_mode,
12882   0,
12883   t_mode,
12884   0,
12885   t_mode,
12886   /* dc */
12887   q_mode,
12888   q_mode,
12889   q_mode,
12890   q_mode,
12891   q_mode,
12892   q_mode,
12893   q_mode,
12894   q_mode,
12895   /* dd */
12896   q_mode,
12897   q_mode,
12898   q_mode,
12899   q_mode,
12900   0,
12901   0,
12902   0,
12903   w_mode,
12904   /* de */
12905   w_mode,
12906   w_mode,
12907   w_mode,
12908   w_mode,
12909   w_mode,
12910   w_mode,
12911   w_mode,
12912   w_mode,
12913   /* df */
12914   w_mode,
12915   w_mode,
12916   w_mode,
12917   w_mode,
12918   t_mode,
12919   q_mode,
12920   t_mode,
12921   q_mode
12922 };
12923
12924 #define ST { OP_ST, 0 }
12925 #define STi { OP_STi, 0 }
12926
12927 #define FGRPd9_2 NULL, { { NULL, 0 } }
12928 #define FGRPd9_4 NULL, { { NULL, 1 } }
12929 #define FGRPd9_5 NULL, { { NULL, 2 } }
12930 #define FGRPd9_6 NULL, { { NULL, 3 } }
12931 #define FGRPd9_7 NULL, { { NULL, 4 } }
12932 #define FGRPda_5 NULL, { { NULL, 5 } }
12933 #define FGRPdb_4 NULL, { { NULL, 6 } }
12934 #define FGRPde_3 NULL, { { NULL, 7 } }
12935 #define FGRPdf_4 NULL, { { NULL, 8 } }
12936
12937 static const struct dis386 float_reg[][8] = {
12938   /* d8 */
12939   {
12940     { "fadd",   { ST, STi } },
12941     { "fmul",   { ST, STi } },
12942     { "fcom",   { STi } },
12943     { "fcomp",  { STi } },
12944     { "fsub",   { ST, STi } },
12945     { "fsubr",  { ST, STi } },
12946     { "fdiv",   { ST, STi } },
12947     { "fdivr",  { ST, STi } },
12948   },
12949   /* d9 */
12950   {
12951     { "fld",    { STi } },
12952     { "fxch",   { STi } },
12953     { FGRPd9_2 },
12954     { Bad_Opcode },
12955     { FGRPd9_4 },
12956     { FGRPd9_5 },
12957     { FGRPd9_6 },
12958     { FGRPd9_7 },
12959   },
12960   /* da */
12961   {
12962     { "fcmovb", { ST, STi } },
12963     { "fcmove", { ST, STi } },
12964     { "fcmovbe",{ ST, STi } },
12965     { "fcmovu", { ST, STi } },
12966     { Bad_Opcode },
12967     { FGRPda_5 },
12968     { Bad_Opcode },
12969     { Bad_Opcode },
12970   },
12971   /* db */
12972   {
12973     { "fcmovnb",{ ST, STi } },
12974     { "fcmovne",{ ST, STi } },
12975     { "fcmovnbe",{ ST, STi } },
12976     { "fcmovnu",{ ST, STi } },
12977     { FGRPdb_4 },
12978     { "fucomi", { ST, STi } },
12979     { "fcomi",  { ST, STi } },
12980     { Bad_Opcode },
12981   },
12982   /* dc */
12983   {
12984     { "fadd",   { STi, ST } },
12985     { "fmul",   { STi, ST } },
12986     { Bad_Opcode },
12987     { Bad_Opcode },
12988     { "fsub!M", { STi, ST } },
12989     { "fsubM",  { STi, ST } },
12990     { "fdiv!M", { STi, ST } },
12991     { "fdivM",  { STi, ST } },
12992   },
12993   /* dd */
12994   {
12995     { "ffree",  { STi } },
12996     { Bad_Opcode },
12997     { "fst",    { STi } },
12998     { "fstp",   { STi } },
12999     { "fucom",  { STi } },
13000     { "fucomp", { STi } },
13001     { Bad_Opcode },
13002     { Bad_Opcode },
13003   },
13004   /* de */
13005   {
13006     { "faddp",  { STi, ST } },
13007     { "fmulp",  { STi, ST } },
13008     { Bad_Opcode },
13009     { FGRPde_3 },
13010     { "fsub!Mp", { STi, ST } },
13011     { "fsubMp", { STi, ST } },
13012     { "fdiv!Mp", { STi, ST } },
13013     { "fdivMp", { STi, ST } },
13014   },
13015   /* df */
13016   {
13017     { "ffreep", { STi } },
13018     { Bad_Opcode },
13019     { Bad_Opcode },
13020     { Bad_Opcode },
13021     { FGRPdf_4 },
13022     { "fucomip", { ST, STi } },
13023     { "fcomip", { ST, STi } },
13024     { Bad_Opcode },
13025   },
13026 };
13027
13028 static char *fgrps[][8] = {
13029   /* d9_2  0 */
13030   {
13031     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13032   },
13033
13034   /* d9_4  1 */
13035   {
13036     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13037   },
13038
13039   /* d9_5  2 */
13040   {
13041     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13042   },
13043
13044   /* d9_6  3 */
13045   {
13046     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13047   },
13048
13049   /* d9_7  4 */
13050   {
13051     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13052   },
13053
13054   /* da_5  5 */
13055   {
13056     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13057   },
13058
13059   /* db_4  6 */
13060   {
13061     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13062     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13063   },
13064
13065   /* de_3  7 */
13066   {
13067     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13068   },
13069
13070   /* df_4  8 */
13071   {
13072     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13073   },
13074 };
13075
13076 static void
13077 swap_operand (void)
13078 {
13079   mnemonicendp[0] = '.';
13080   mnemonicendp[1] = 's';
13081   mnemonicendp += 2;
13082 }
13083
13084 static void
13085 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13086                int sizeflag ATTRIBUTE_UNUSED)
13087 {
13088   /* Skip mod/rm byte.  */
13089   MODRM_CHECK;
13090   codep++;
13091 }
13092
13093 static void
13094 dofloat (int sizeflag)
13095 {
13096   const struct dis386 *dp;
13097   unsigned char floatop;
13098
13099   floatop = codep[-1];
13100
13101   if (modrm.mod != 3)
13102     {
13103       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13104
13105       putop (float_mem[fp_indx], sizeflag);
13106       obufp = op_out[0];
13107       op_ad = 2;
13108       OP_E (float_mem_mode[fp_indx], sizeflag);
13109       return;
13110     }
13111   /* Skip mod/rm byte.  */
13112   MODRM_CHECK;
13113   codep++;
13114
13115   dp = &float_reg[floatop - 0xd8][modrm.reg];
13116   if (dp->name == NULL)
13117     {
13118       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13119
13120       /* Instruction fnstsw is only one with strange arg.  */
13121       if (floatop == 0xdf && codep[-1] == 0xe0)
13122         strcpy (op_out[0], names16[0]);
13123     }
13124   else
13125     {
13126       putop (dp->name, sizeflag);
13127
13128       obufp = op_out[0];
13129       op_ad = 2;
13130       if (dp->op[0].rtn)
13131         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13132
13133       obufp = op_out[1];
13134       op_ad = 1;
13135       if (dp->op[1].rtn)
13136         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13137     }
13138 }
13139
13140 /* Like oappend (below), but S is a string starting with '%'.
13141    In Intel syntax, the '%' is elided.  */
13142 static void
13143 oappend_maybe_intel (const char *s)
13144 {
13145   oappend (s + intel_syntax);
13146 }
13147
13148 static void
13149 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13150 {
13151   oappend_maybe_intel ("%st");
13152 }
13153
13154 static void
13155 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13156 {
13157   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13158   oappend_maybe_intel (scratchbuf);
13159 }
13160
13161 /* Capital letters in template are macros.  */
13162 static int
13163 putop (const char *in_template, int sizeflag)
13164 {
13165   const char *p;
13166   int alt = 0;
13167   int cond = 1;
13168   unsigned int l = 0, len = 1;
13169   char last[4];
13170
13171 #define SAVE_LAST(c)                    \
13172   if (l < len && l < sizeof (last))     \
13173     last[l++] = c;                      \
13174   else                                  \
13175     abort ();
13176
13177   for (p = in_template; *p; p++)
13178     {
13179       switch (*p)
13180         {
13181         default:
13182           *obufp++ = *p;
13183           break;
13184         case '%':
13185           len++;
13186           break;
13187         case '!':
13188           cond = 0;
13189           break;
13190         case '{':
13191           alt = 0;
13192           if (intel_syntax)
13193             {
13194               while (*++p != '|')
13195                 if (*p == '}' || *p == '\0')
13196                   abort ();
13197             }
13198           /* Fall through.  */
13199         case 'I':
13200           alt = 1;
13201           continue;
13202         case '|':
13203           while (*++p != '}')
13204             {
13205               if (*p == '\0')
13206                 abort ();
13207             }
13208           break;
13209         case '}':
13210           break;
13211         case 'A':
13212           if (intel_syntax)
13213             break;
13214           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13215             *obufp++ = 'b';
13216           break;
13217         case 'B':
13218           if (l == 0 && len == 1)
13219             {
13220 case_B:
13221               if (intel_syntax)
13222                 break;
13223               if (sizeflag & SUFFIX_ALWAYS)
13224                 *obufp++ = 'b';
13225             }
13226           else
13227             {
13228               if (l != 1
13229                   || len != 2
13230                   || last[0] != 'L')
13231                 {
13232                   SAVE_LAST (*p);
13233                   break;
13234                 }
13235
13236               if (address_mode == mode_64bit
13237                   && !(prefixes & PREFIX_ADDR))
13238                 {
13239                   *obufp++ = 'a';
13240                   *obufp++ = 'b';
13241                   *obufp++ = 's';
13242                 }
13243
13244               goto case_B;
13245             }
13246           break;
13247         case 'C':
13248           if (intel_syntax && !alt)
13249             break;
13250           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13251             {
13252               if (sizeflag & DFLAG)
13253                 *obufp++ = intel_syntax ? 'd' : 'l';
13254               else
13255                 *obufp++ = intel_syntax ? 'w' : 's';
13256               used_prefixes |= (prefixes & PREFIX_DATA);
13257             }
13258           break;
13259         case 'D':
13260           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13261             break;
13262           USED_REX (REX_W);
13263           if (modrm.mod == 3)
13264             {
13265               if (rex & REX_W)
13266                 *obufp++ = 'q';
13267               else
13268                 {
13269                   if (sizeflag & DFLAG)
13270                     *obufp++ = intel_syntax ? 'd' : 'l';
13271                   else
13272                     *obufp++ = 'w';
13273                   used_prefixes |= (prefixes & PREFIX_DATA);
13274                 }
13275             }
13276           else
13277             *obufp++ = 'w';
13278           break;
13279         case 'E':               /* For jcxz/jecxz */
13280           if (address_mode == mode_64bit)
13281             {
13282               if (sizeflag & AFLAG)
13283                 *obufp++ = 'r';
13284               else
13285                 *obufp++ = 'e';
13286             }
13287           else
13288             if (sizeflag & AFLAG)
13289               *obufp++ = 'e';
13290           used_prefixes |= (prefixes & PREFIX_ADDR);
13291           break;
13292         case 'F':
13293           if (intel_syntax)
13294             break;
13295           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13296             {
13297               if (sizeflag & AFLAG)
13298                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13299               else
13300                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13301               used_prefixes |= (prefixes & PREFIX_ADDR);
13302             }
13303           break;
13304         case 'G':
13305           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13306             break;
13307           if ((rex & REX_W) || (sizeflag & DFLAG))
13308             *obufp++ = 'l';
13309           else
13310             *obufp++ = 'w';
13311           if (!(rex & REX_W))
13312             used_prefixes |= (prefixes & PREFIX_DATA);
13313           break;
13314         case 'H':
13315           if (intel_syntax)
13316             break;
13317           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13318               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13319             {
13320               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13321               *obufp++ = ',';
13322               *obufp++ = 'p';
13323               if (prefixes & PREFIX_DS)
13324                 *obufp++ = 't';
13325               else
13326                 *obufp++ = 'n';
13327             }
13328           break;
13329         case 'J':
13330           if (intel_syntax)
13331             break;
13332           *obufp++ = 'l';
13333           break;
13334         case 'K':
13335           USED_REX (REX_W);
13336           if (rex & REX_W)
13337             *obufp++ = 'q';
13338           else
13339             *obufp++ = 'd';
13340           break;
13341         case 'Z':
13342           if (intel_syntax)
13343             break;
13344           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13345             {
13346               *obufp++ = 'q';
13347               break;
13348             }
13349           /* Fall through.  */
13350           goto case_L;
13351         case 'L':
13352           if (l != 0 || len != 1)
13353             {
13354               SAVE_LAST (*p);
13355               break;
13356             }
13357 case_L:
13358           if (intel_syntax)
13359             break;
13360           if (sizeflag & SUFFIX_ALWAYS)
13361             *obufp++ = 'l';
13362           break;
13363         case 'M':
13364           if (intel_mnemonic != cond)
13365             *obufp++ = 'r';
13366           break;
13367         case 'N':
13368           if ((prefixes & PREFIX_FWAIT) == 0)
13369             *obufp++ = 'n';
13370           else
13371             used_prefixes |= PREFIX_FWAIT;
13372           break;
13373         case 'O':
13374           USED_REX (REX_W);
13375           if (rex & REX_W)
13376             *obufp++ = 'o';
13377           else if (intel_syntax && (sizeflag & DFLAG))
13378             *obufp++ = 'q';
13379           else
13380             *obufp++ = 'd';
13381           if (!(rex & REX_W))
13382             used_prefixes |= (prefixes & PREFIX_DATA);
13383           break;
13384         case 'T':
13385           if (!intel_syntax
13386               && address_mode == mode_64bit
13387               && ((sizeflag & DFLAG) || (rex & REX_W)))
13388             {
13389               *obufp++ = 'q';
13390               break;
13391             }
13392           /* Fall through.  */
13393         case 'P':
13394           if (intel_syntax)
13395             {
13396               if ((rex & REX_W) == 0
13397                   && (prefixes & PREFIX_DATA))
13398                 {
13399                   if ((sizeflag & DFLAG) == 0)
13400                     *obufp++ = 'w';
13401                    used_prefixes |= (prefixes & PREFIX_DATA);
13402                 }
13403               break;
13404             }
13405           if ((prefixes & PREFIX_DATA)
13406               || (rex & REX_W)
13407               || (sizeflag & SUFFIX_ALWAYS))
13408             {
13409               USED_REX (REX_W);
13410               if (rex & REX_W)
13411                 *obufp++ = 'q';
13412               else
13413                 {
13414                    if (sizeflag & DFLAG)
13415                       *obufp++ = 'l';
13416                    else
13417                      *obufp++ = 'w';
13418                    used_prefixes |= (prefixes & PREFIX_DATA);
13419                 }
13420             }
13421           break;
13422         case 'U':
13423           if (intel_syntax)
13424             break;
13425           if (address_mode == mode_64bit
13426               && ((sizeflag & DFLAG) || (rex & REX_W)))
13427             {
13428               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13429                 *obufp++ = 'q';
13430               break;
13431             }
13432           /* Fall through.  */
13433           goto case_Q;
13434         case 'Q':
13435           if (l == 0 && len == 1)
13436             {
13437 case_Q:
13438               if (intel_syntax && !alt)
13439                 break;
13440               USED_REX (REX_W);
13441               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13442                 {
13443                   if (rex & REX_W)
13444                     *obufp++ = 'q';
13445                   else
13446                     {
13447                       if (sizeflag & DFLAG)
13448                         *obufp++ = intel_syntax ? 'd' : 'l';
13449                       else
13450                         *obufp++ = 'w';
13451                       used_prefixes |= (prefixes & PREFIX_DATA);
13452                     }
13453                 }
13454             }
13455           else
13456             {
13457               if (l != 1 || len != 2 || last[0] != 'L')
13458                 {
13459                   SAVE_LAST (*p);
13460                   break;
13461                 }
13462               if (intel_syntax
13463                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13464                 break;
13465               if ((rex & REX_W))
13466                 {
13467                   USED_REX (REX_W);
13468                   *obufp++ = 'q';
13469                 }
13470               else
13471                 *obufp++ = 'l';
13472             }
13473           break;
13474         case 'R':
13475           USED_REX (REX_W);
13476           if (rex & REX_W)
13477             *obufp++ = 'q';
13478           else if (sizeflag & DFLAG)
13479             {
13480               if (intel_syntax)
13481                   *obufp++ = 'd';
13482               else
13483                   *obufp++ = 'l';
13484             }
13485           else
13486             *obufp++ = 'w';
13487           if (intel_syntax && !p[1]
13488               && ((rex & REX_W) || (sizeflag & DFLAG)))
13489             *obufp++ = 'e';
13490           if (!(rex & REX_W))
13491             used_prefixes |= (prefixes & PREFIX_DATA);
13492           break;
13493         case 'V':
13494           if (l == 0 && len == 1)
13495             {
13496               if (intel_syntax)
13497                 break;
13498               if (address_mode == mode_64bit
13499                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13500                 {
13501                   if (sizeflag & SUFFIX_ALWAYS)
13502                     *obufp++ = 'q';
13503                   break;
13504                 }
13505             }
13506           else
13507             {
13508               if (l != 1
13509                   || len != 2
13510                   || last[0] != 'L')
13511                 {
13512                   SAVE_LAST (*p);
13513                   break;
13514                 }
13515
13516               if (rex & REX_W)
13517                 {
13518                   *obufp++ = 'a';
13519                   *obufp++ = 'b';
13520                   *obufp++ = 's';
13521                 }
13522             }
13523           /* Fall through.  */
13524           goto case_S;
13525         case 'S':
13526           if (l == 0 && len == 1)
13527             {
13528 case_S:
13529               if (intel_syntax)
13530                 break;
13531               if (sizeflag & SUFFIX_ALWAYS)
13532                 {
13533                   if (rex & REX_W)
13534                     *obufp++ = 'q';
13535                   else
13536                     {
13537                       if (sizeflag & DFLAG)
13538                         *obufp++ = 'l';
13539                       else
13540                         *obufp++ = 'w';
13541                       used_prefixes |= (prefixes & PREFIX_DATA);
13542                     }
13543                 }
13544             }
13545           else
13546             {
13547               if (l != 1
13548                   || len != 2
13549                   || last[0] != 'L')
13550                 {
13551                   SAVE_LAST (*p);
13552                   break;
13553                 }
13554
13555               if (address_mode == mode_64bit
13556                   && !(prefixes & PREFIX_ADDR))
13557                 {
13558                   *obufp++ = 'a';
13559                   *obufp++ = 'b';
13560                   *obufp++ = 's';
13561                 }
13562
13563               goto case_S;
13564             }
13565           break;
13566         case 'X':
13567           if (l != 0 || len != 1)
13568             {
13569               SAVE_LAST (*p);
13570               break;
13571             }
13572           if (need_vex && vex.prefix)
13573             {
13574               if (vex.prefix == DATA_PREFIX_OPCODE)
13575                 *obufp++ = 'd';
13576               else
13577                 *obufp++ = 's';
13578             }
13579           else
13580             {
13581               if (prefixes & PREFIX_DATA)
13582                 *obufp++ = 'd';
13583               else
13584                 *obufp++ = 's';
13585               used_prefixes |= (prefixes & PREFIX_DATA);
13586             }
13587           break;
13588         case 'Y':
13589           if (l == 0 && len == 1)
13590             {
13591               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13592                 break;
13593               if (rex & REX_W)
13594                 {
13595                   USED_REX (REX_W);
13596                   *obufp++ = 'q';
13597                 }
13598               break;
13599             }
13600           else
13601             {
13602               if (l != 1 || len != 2 || last[0] != 'X')
13603                 {
13604                   SAVE_LAST (*p);
13605                   break;
13606                 }
13607               if (!need_vex)
13608                 abort ();
13609               if (intel_syntax
13610                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13611                 break;
13612               switch (vex.length)
13613                 {
13614                 case 128:
13615                   *obufp++ = 'x';
13616                   break;
13617                 case 256:
13618                   *obufp++ = 'y';
13619                   break;
13620                 default:
13621                   abort ();
13622                 }
13623             }
13624           break;
13625         case 'W':
13626           if (l == 0 && len == 1)
13627             {
13628               /* operand size flag for cwtl, cbtw */
13629               USED_REX (REX_W);
13630               if (rex & REX_W)
13631                 {
13632                   if (intel_syntax)
13633                     *obufp++ = 'd';
13634                   else
13635                     *obufp++ = 'l';
13636                 }
13637               else if (sizeflag & DFLAG)
13638                 *obufp++ = 'w';
13639               else
13640                 *obufp++ = 'b';
13641               if (!(rex & REX_W))
13642                 used_prefixes |= (prefixes & PREFIX_DATA);
13643             }
13644           else
13645             {
13646               if (l != 1
13647                   || len != 2
13648                   || (last[0] != 'X'
13649                       && last[0] != 'L'))
13650                 {
13651                   SAVE_LAST (*p);
13652                   break;
13653                 }
13654               if (!need_vex)
13655                 abort ();
13656               if (last[0] == 'X')
13657                 *obufp++ = vex.w ? 'd': 's';
13658               else
13659                 *obufp++ = vex.w ? 'q': 'd';
13660             }
13661           break;
13662         }
13663       alt = 0;
13664     }
13665   *obufp = 0;
13666   mnemonicendp = obufp;
13667   return 0;
13668 }
13669
13670 static void
13671 oappend (const char *s)
13672 {
13673   obufp = stpcpy (obufp, s);
13674 }
13675
13676 static void
13677 append_seg (void)
13678 {
13679   /* Only print the active segment register.  */
13680   if (!active_seg_prefix)
13681     return;
13682
13683   used_prefixes |= active_seg_prefix;
13684   switch (active_seg_prefix)
13685     {
13686     case PREFIX_CS:
13687       oappend_maybe_intel ("%cs:");
13688       break;
13689     case PREFIX_DS:
13690       oappend_maybe_intel ("%ds:");
13691       break;
13692     case PREFIX_SS:
13693       oappend_maybe_intel ("%ss:");
13694       break;
13695     case PREFIX_ES:
13696       oappend_maybe_intel ("%es:");
13697       break;
13698     case PREFIX_FS:
13699       oappend_maybe_intel ("%fs:");
13700       break;
13701     case PREFIX_GS:
13702       oappend_maybe_intel ("%gs:");
13703       break;
13704     default:
13705       break;
13706     }
13707 }
13708
13709 static void
13710 OP_indirE (int bytemode, int sizeflag)
13711 {
13712   if (!intel_syntax)
13713     oappend ("*");
13714   OP_E (bytemode, sizeflag);
13715 }
13716
13717 static void
13718 print_operand_value (char *buf, int hex, bfd_vma disp)
13719 {
13720   if (address_mode == mode_64bit)
13721     {
13722       if (hex)
13723         {
13724           char tmp[30];
13725           int i;
13726           buf[0] = '0';
13727           buf[1] = 'x';
13728           sprintf_vma (tmp, disp);
13729           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13730           strcpy (buf + 2, tmp + i);
13731         }
13732       else
13733         {
13734           bfd_signed_vma v = disp;
13735           char tmp[30];
13736           int i;
13737           if (v < 0)
13738             {
13739               *(buf++) = '-';
13740               v = -disp;
13741               /* Check for possible overflow on 0x8000000000000000.  */
13742               if (v < 0)
13743                 {
13744                   strcpy (buf, "9223372036854775808");
13745                   return;
13746                 }
13747             }
13748           if (!v)
13749             {
13750               strcpy (buf, "0");
13751               return;
13752             }
13753
13754           i = 0;
13755           tmp[29] = 0;
13756           while (v)
13757             {
13758               tmp[28 - i] = (v % 10) + '0';
13759               v /= 10;
13760               i++;
13761             }
13762           strcpy (buf, tmp + 29 - i);
13763         }
13764     }
13765   else
13766     {
13767       if (hex)
13768         sprintf (buf, "0x%x", (unsigned int) disp);
13769       else
13770         sprintf (buf, "%d", (int) disp);
13771     }
13772 }
13773
13774 /* Put DISP in BUF as signed hex number.  */
13775
13776 static void
13777 print_displacement (char *buf, bfd_vma disp)
13778 {
13779   bfd_signed_vma val = disp;
13780   char tmp[30];
13781   int i, j = 0;
13782
13783   if (val < 0)
13784     {
13785       buf[j++] = '-';
13786       val = -disp;
13787
13788       /* Check for possible overflow.  */
13789       if (val < 0)
13790         {
13791           switch (address_mode)
13792             {
13793             case mode_64bit:
13794               strcpy (buf + j, "0x8000000000000000");
13795               break;
13796             case mode_32bit:
13797               strcpy (buf + j, "0x80000000");
13798               break;
13799             case mode_16bit:
13800               strcpy (buf + j, "0x8000");
13801               break;
13802             }
13803           return;
13804         }
13805     }
13806
13807   buf[j++] = '0';
13808   buf[j++] = 'x';
13809
13810   sprintf_vma (tmp, (bfd_vma) val);
13811   for (i = 0; tmp[i] == '0'; i++)
13812     continue;
13813   if (tmp[i] == '\0')
13814     i--;
13815   strcpy (buf + j, tmp + i);
13816 }
13817
13818 static void
13819 intel_operand_size (int bytemode, int sizeflag)
13820 {
13821   if (vex.evex
13822       && vex.b
13823       && (bytemode == x_mode
13824           || bytemode == evex_half_bcst_xmmq_mode))
13825     {
13826       if (vex.w)
13827         oappend ("QWORD PTR ");
13828       else
13829         oappend ("DWORD PTR ");
13830       return;
13831     }
13832   switch (bytemode)
13833     {
13834     case b_mode:
13835     case b_swap_mode:
13836     case dqb_mode:
13837       oappend ("BYTE PTR ");
13838       break;
13839     case w_mode:
13840     case dqw_mode:
13841       oappend ("WORD PTR ");
13842       break;
13843     case stack_v_mode:
13844       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13845         {
13846           oappend ("QWORD PTR ");
13847           break;
13848         }
13849       /* FALLTHRU */
13850     case v_mode:
13851     case v_swap_mode:
13852     case dq_mode:
13853       USED_REX (REX_W);
13854       if (rex & REX_W)
13855         oappend ("QWORD PTR ");
13856       else
13857         {
13858           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13859             oappend ("DWORD PTR ");
13860           else
13861             oappend ("WORD PTR ");
13862           used_prefixes |= (prefixes & PREFIX_DATA);
13863         }
13864       break;
13865     case z_mode:
13866       if ((rex & REX_W) || (sizeflag & DFLAG))
13867         *obufp++ = 'D';
13868       oappend ("WORD PTR ");
13869       if (!(rex & REX_W))
13870         used_prefixes |= (prefixes & PREFIX_DATA);
13871       break;
13872     case a_mode:
13873       if (sizeflag & DFLAG)
13874         oappend ("QWORD PTR ");
13875       else
13876         oappend ("DWORD PTR ");
13877       used_prefixes |= (prefixes & PREFIX_DATA);
13878       break;
13879     case d_mode:
13880     case d_scalar_mode:
13881     case d_scalar_swap_mode:
13882     case d_swap_mode:
13883     case dqd_mode:
13884       oappend ("DWORD PTR ");
13885       break;
13886     case q_mode:
13887     case q_scalar_mode:
13888     case q_scalar_swap_mode:
13889     case q_swap_mode:
13890       oappend ("QWORD PTR ");
13891       break;
13892     case m_mode:
13893       if (address_mode == mode_64bit)
13894         oappend ("QWORD PTR ");
13895       else
13896         oappend ("DWORD PTR ");
13897       break;
13898     case f_mode:
13899       if (sizeflag & DFLAG)
13900         oappend ("FWORD PTR ");
13901       else
13902         oappend ("DWORD PTR ");
13903       used_prefixes |= (prefixes & PREFIX_DATA);
13904       break;
13905     case t_mode:
13906       oappend ("TBYTE PTR ");
13907       break;
13908     case x_mode:
13909     case x_swap_mode:
13910     case evex_x_gscat_mode:
13911     case evex_x_nobcst_mode:
13912       if (need_vex)
13913         {
13914           switch (vex.length)
13915             {
13916             case 128:
13917               oappend ("XMMWORD PTR ");
13918               break;
13919             case 256:
13920               oappend ("YMMWORD PTR ");
13921               break;
13922             case 512:
13923               oappend ("ZMMWORD PTR ");
13924               break;
13925             default:
13926               abort ();
13927             }
13928         }
13929       else
13930         oappend ("XMMWORD PTR ");
13931       break;
13932     case xmm_mode:
13933       oappend ("XMMWORD PTR ");
13934       break;
13935     case ymm_mode:
13936       oappend ("YMMWORD PTR ");
13937       break;
13938     case xmmq_mode:
13939     case evex_half_bcst_xmmq_mode:
13940       if (!need_vex)
13941         abort ();
13942
13943       switch (vex.length)
13944         {
13945         case 128:
13946           oappend ("QWORD PTR ");
13947           break;
13948         case 256:
13949           oappend ("XMMWORD PTR ");
13950           break;
13951         case 512:
13952           oappend ("YMMWORD PTR ");
13953           break;
13954         default:
13955           abort ();
13956         }
13957       break;
13958     case xmm_mb_mode:
13959       if (!need_vex)
13960         abort ();
13961
13962       switch (vex.length)
13963         {
13964         case 128:
13965         case 256:
13966         case 512:
13967           oappend ("BYTE PTR ");
13968           break;
13969         default:
13970           abort ();
13971         }
13972       break;
13973     case xmm_mw_mode:
13974       if (!need_vex)
13975         abort ();
13976
13977       switch (vex.length)
13978         {
13979         case 128:
13980         case 256:
13981         case 512:
13982           oappend ("WORD PTR ");
13983           break;
13984         default:
13985           abort ();
13986         }
13987       break;
13988     case xmm_md_mode:
13989       if (!need_vex)
13990         abort ();
13991
13992       switch (vex.length)
13993         {
13994         case 128:
13995         case 256:
13996         case 512:
13997           oappend ("DWORD PTR ");
13998           break;
13999         default:
14000           abort ();
14001         }
14002       break;
14003     case xmm_mq_mode:
14004       if (!need_vex)
14005         abort ();
14006
14007       switch (vex.length)
14008         {
14009         case 128:
14010         case 256:
14011         case 512:
14012           oappend ("QWORD PTR ");
14013           break;
14014         default:
14015           abort ();
14016         }
14017       break;
14018     case xmmdw_mode:
14019       if (!need_vex)
14020         abort ();
14021
14022       switch (vex.length)
14023         {
14024         case 128:
14025           oappend ("WORD PTR ");
14026           break;
14027         case 256:
14028           oappend ("DWORD PTR ");
14029           break;
14030         case 512:
14031           oappend ("QWORD PTR ");
14032           break;
14033         default:
14034           abort ();
14035         }
14036       break;
14037     case xmmqd_mode:
14038       if (!need_vex)
14039         abort ();
14040
14041       switch (vex.length)
14042         {
14043         case 128:
14044           oappend ("DWORD PTR ");
14045           break;
14046         case 256:
14047           oappend ("QWORD PTR ");
14048           break;
14049         case 512:
14050           oappend ("XMMWORD PTR ");
14051           break;
14052         default:
14053           abort ();
14054         }
14055       break;
14056     case ymmq_mode:
14057       if (!need_vex)
14058         abort ();
14059
14060       switch (vex.length)
14061         {
14062         case 128:
14063           oappend ("QWORD PTR ");
14064           break;
14065         case 256:
14066           oappend ("YMMWORD PTR ");
14067           break;
14068         case 512:
14069           oappend ("ZMMWORD PTR ");
14070           break;
14071         default:
14072           abort ();
14073         }
14074       break;
14075     case ymmxmm_mode:
14076       if (!need_vex)
14077         abort ();
14078
14079       switch (vex.length)
14080         {
14081         case 128:
14082         case 256:
14083           oappend ("XMMWORD PTR ");
14084           break;
14085         default:
14086           abort ();
14087         }
14088       break;
14089     case o_mode:
14090       oappend ("OWORD PTR ");
14091       break;
14092     case xmm_mdq_mode:
14093     case vex_w_dq_mode:
14094     case vex_scalar_w_dq_mode:
14095       if (!need_vex)
14096         abort ();
14097
14098       if (vex.w)
14099         oappend ("QWORD PTR ");
14100       else
14101         oappend ("DWORD PTR ");
14102       break;
14103     case vex_vsib_d_w_dq_mode:
14104     case vex_vsib_q_w_dq_mode:
14105       if (!need_vex)
14106         abort ();
14107
14108       if (!vex.evex)
14109         {
14110           if (vex.w)
14111             oappend ("QWORD PTR ");
14112           else
14113             oappend ("DWORD PTR ");
14114         }
14115       else
14116         {
14117           if (vex.length != 512)
14118             abort ();
14119           oappend ("ZMMWORD PTR ");
14120         }
14121       break;
14122     case vex_vsib_q_w_d_mode:
14123     case vex_vsib_d_w_d_mode:
14124       if (!need_vex || !vex.evex || vex.length != 512)
14125         abort ();
14126
14127       oappend ("YMMWORD PTR ");
14128
14129       break;
14130     case mask_mode:
14131       if (!need_vex)
14132         abort ();
14133       /* Currently the only instructions, which allows either mask or
14134          memory operand, are AVX512's KMOVW instructions.  They need
14135          Word-sized operand.  */
14136       if (vex.w || vex.length != 128)
14137         abort ();
14138       oappend ("WORD PTR ");
14139       break;
14140     case v_bnd_mode:
14141     default:
14142       break;
14143     }
14144 }
14145
14146 static void
14147 OP_E_register (int bytemode, int sizeflag)
14148 {
14149   int reg = modrm.rm;
14150   const char **names;
14151
14152   USED_REX (REX_B);
14153   if ((rex & REX_B))
14154     reg += 8;
14155
14156   if ((sizeflag & SUFFIX_ALWAYS)
14157       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14158     swap_operand ();
14159
14160   switch (bytemode)
14161     {
14162     case b_mode:
14163     case b_swap_mode:
14164       USED_REX (0);
14165       if (rex)
14166         names = names8rex;
14167       else
14168         names = names8;
14169       break;
14170     case w_mode:
14171       names = names16;
14172       break;
14173     case d_mode:
14174       names = names32;
14175       break;
14176     case q_mode:
14177       names = names64;
14178       break;
14179     case m_mode:
14180     case v_bnd_mode:
14181       names = address_mode == mode_64bit ? names64 : names32;
14182       break;
14183     case bnd_mode:
14184       names = names_bnd;
14185       break;
14186     case stack_v_mode:
14187       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14188         {
14189           names = names64;
14190           break;
14191         }
14192       bytemode = v_mode;
14193       /* FALLTHRU */
14194     case v_mode:
14195     case v_swap_mode:
14196     case dq_mode:
14197     case dqb_mode:
14198     case dqd_mode:
14199     case dqw_mode:
14200       USED_REX (REX_W);
14201       if (rex & REX_W)
14202         names = names64;
14203       else
14204         {
14205           if ((sizeflag & DFLAG)
14206               || (bytemode != v_mode
14207                   && bytemode != v_swap_mode))
14208             names = names32;
14209           else
14210             names = names16;
14211           used_prefixes |= (prefixes & PREFIX_DATA);
14212         }
14213       break;
14214     case mask_mode:
14215       names = names_mask;
14216       break;
14217     case 0:
14218       return;
14219     default:
14220       oappend (INTERNAL_DISASSEMBLER_ERROR);
14221       return;
14222     }
14223   oappend (names[reg]);
14224 }
14225
14226 static void
14227 OP_E_memory (int bytemode, int sizeflag)
14228 {
14229   bfd_vma disp = 0;
14230   int add = (rex & REX_B) ? 8 : 0;
14231   int riprel = 0;
14232   int shift;
14233
14234   if (vex.evex)
14235     {
14236       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14237       if (vex.b
14238           && bytemode != x_mode
14239           && bytemode != evex_half_bcst_xmmq_mode)
14240         {
14241           BadOp ();
14242           return;
14243         }
14244       switch (bytemode)
14245         {
14246         case vex_vsib_d_w_dq_mode:
14247         case vex_vsib_d_w_d_mode:
14248         case vex_vsib_q_w_dq_mode:
14249         case vex_vsib_q_w_d_mode:
14250         case evex_x_gscat_mode:
14251         case xmm_mdq_mode:
14252           shift = vex.w ? 3 : 2;
14253           break;
14254         case x_mode:
14255         case evex_half_bcst_xmmq_mode:
14256           if (vex.b)
14257             {
14258               shift = vex.w ? 3 : 2;
14259               break;
14260             }
14261           /* Fall through if vex.b == 0.  */
14262         case xmmqd_mode:
14263         case xmmdw_mode:
14264         case xmmq_mode:
14265         case ymmq_mode:
14266         case evex_x_nobcst_mode:
14267         case x_swap_mode:
14268           switch (vex.length)
14269             {
14270             case 128:
14271               shift = 4;
14272               break;
14273             case 256:
14274               shift = 5;
14275               break;
14276             case 512:
14277               shift = 6;
14278               break;
14279             default:
14280               abort ();
14281             }
14282           break;
14283         case ymm_mode:
14284           shift = 5;
14285           break;
14286         case xmm_mode:
14287           shift = 4;
14288           break;
14289         case xmm_mq_mode:
14290         case q_mode:
14291         case q_scalar_mode:
14292         case q_swap_mode:
14293         case q_scalar_swap_mode:
14294           shift = 3;
14295           break;
14296         case dqd_mode:
14297         case xmm_md_mode:
14298         case d_mode:
14299         case d_scalar_mode:
14300         case d_swap_mode:
14301         case d_scalar_swap_mode:
14302           shift = 2;
14303           break;
14304         case xmm_mw_mode:
14305           shift = 1;
14306           break;
14307         case xmm_mb_mode:
14308           shift = 0;
14309           break;
14310         default:
14311           abort ();
14312         }
14313       /* Make necessary corrections to shift for modes that need it.
14314          For these modes we currently have shift 4, 5 or 6 depending on
14315          vex.length (it corresponds to xmmword, ymmword or zmmword
14316          operand).  We might want to make it 3, 4 or 5 (e.g. for
14317          xmmq_mode).  In case of broadcast enabled the corrections
14318          aren't needed, as element size is always 32 or 64 bits.  */
14319       if (bytemode == xmmq_mode
14320           || (bytemode == evex_half_bcst_xmmq_mode
14321               && !vex.b))
14322         shift -= 1;
14323       else if (bytemode == xmmqd_mode)
14324         shift -= 2;
14325       else if (bytemode == xmmdw_mode)
14326         shift -= 3;
14327     }
14328   else
14329     shift = 0;
14330
14331   USED_REX (REX_B);
14332   if (intel_syntax)
14333     intel_operand_size (bytemode, sizeflag);
14334   append_seg ();
14335
14336   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14337     {
14338       /* 32/64 bit address mode */
14339       int havedisp;
14340       int havesib;
14341       int havebase;
14342       int haveindex;
14343       int needindex;
14344       int base, rbase;
14345       int vindex = 0;
14346       int scale = 0;
14347       int addr32flag = !((sizeflag & AFLAG)
14348                          || bytemode == v_bnd_mode
14349                          || bytemode == bnd_mode);
14350       const char **indexes64 = names64;
14351       const char **indexes32 = names32;
14352
14353       havesib = 0;
14354       havebase = 1;
14355       haveindex = 0;
14356       base = modrm.rm;
14357
14358       if (base == 4)
14359         {
14360           havesib = 1;
14361           vindex = sib.index;
14362           USED_REX (REX_X);
14363           if (rex & REX_X)
14364             vindex += 8;
14365           switch (bytemode)
14366             {
14367             case vex_vsib_d_w_dq_mode:
14368             case vex_vsib_d_w_d_mode:
14369             case vex_vsib_q_w_dq_mode:
14370             case vex_vsib_q_w_d_mode:
14371               if (!need_vex)
14372                 abort ();
14373               if (vex.evex)
14374                 {
14375                   if (!vex.v)
14376                     vindex += 16;
14377                 }
14378
14379               haveindex = 1;
14380               switch (vex.length)
14381                 {
14382                 case 128:
14383                   indexes64 = indexes32 = names_xmm;
14384                   break;
14385                 case 256:
14386                   if (!vex.w
14387                       || bytemode == vex_vsib_q_w_dq_mode
14388                       || bytemode == vex_vsib_q_w_d_mode)
14389                     indexes64 = indexes32 = names_ymm;
14390                   else
14391                     indexes64 = indexes32 = names_xmm;
14392                   break;
14393                 case 512:
14394                   if (!vex.w
14395                       || bytemode == vex_vsib_q_w_dq_mode
14396                       || bytemode == vex_vsib_q_w_d_mode)
14397                     indexes64 = indexes32 = names_zmm;
14398                   else
14399                     indexes64 = indexes32 = names_ymm;
14400                   break;
14401                 default:
14402                   abort ();
14403                 }
14404               break;
14405             default:
14406               haveindex = vindex != 4;
14407               break;
14408             }
14409           scale = sib.scale;
14410           base = sib.base;
14411           codep++;
14412         }
14413       rbase = base + add;
14414
14415       switch (modrm.mod)
14416         {
14417         case 0:
14418           if (base == 5)
14419             {
14420               havebase = 0;
14421               if (address_mode == mode_64bit && !havesib)
14422                 riprel = 1;
14423               disp = get32s ();
14424             }
14425           break;
14426         case 1:
14427           FETCH_DATA (the_info, codep + 1);
14428           disp = *codep++;
14429           if ((disp & 0x80) != 0)
14430             disp -= 0x100;
14431           if (vex.evex && shift > 0)
14432             disp <<= shift;
14433           break;
14434         case 2:
14435           disp = get32s ();
14436           break;
14437         }
14438
14439       /* In 32bit mode, we need index register to tell [offset] from
14440          [eiz*1 + offset].  */
14441       needindex = (havesib
14442                    && !havebase
14443                    && !haveindex
14444                    && address_mode == mode_32bit);
14445       havedisp = (havebase
14446                   || needindex
14447                   || (havesib && (haveindex || scale != 0)));
14448
14449       if (!intel_syntax)
14450         if (modrm.mod != 0 || base == 5)
14451           {
14452             if (havedisp || riprel)
14453               print_displacement (scratchbuf, disp);
14454             else
14455               print_operand_value (scratchbuf, 1, disp);
14456             oappend (scratchbuf);
14457             if (riprel)
14458               {
14459                 set_op (disp, 1);
14460                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14461               }
14462           }
14463
14464       if ((havebase || haveindex || riprel)
14465           && (bytemode != v_bnd_mode)
14466           && (bytemode != bnd_mode))
14467         used_prefixes |= PREFIX_ADDR;
14468
14469       if (havedisp || (intel_syntax && riprel))
14470         {
14471           *obufp++ = open_char;
14472           if (intel_syntax && riprel)
14473             {
14474               set_op (disp, 1);
14475               oappend (sizeflag & AFLAG ? "rip" : "eip");
14476             }
14477           *obufp = '\0';
14478           if (havebase)
14479             oappend (address_mode == mode_64bit && !addr32flag
14480                      ? names64[rbase] : names32[rbase]);
14481           if (havesib)
14482             {
14483               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14484                  print index to tell base + index from base.  */
14485               if (scale != 0
14486                   || needindex
14487                   || haveindex
14488                   || (havebase && base != ESP_REG_NUM))
14489                 {
14490                   if (!intel_syntax || havebase)
14491                     {
14492                       *obufp++ = separator_char;
14493                       *obufp = '\0';
14494                     }
14495                   if (haveindex)
14496                     oappend (address_mode == mode_64bit && !addr32flag
14497                              ? indexes64[vindex] : indexes32[vindex]);
14498                   else
14499                     oappend (address_mode == mode_64bit && !addr32flag
14500                              ? index64 : index32);
14501
14502                   *obufp++ = scale_char;
14503                   *obufp = '\0';
14504                   sprintf (scratchbuf, "%d", 1 << scale);
14505                   oappend (scratchbuf);
14506                 }
14507             }
14508           if (intel_syntax
14509               && (disp || modrm.mod != 0 || base == 5))
14510             {
14511               if (!havedisp || (bfd_signed_vma) disp >= 0)
14512                 {
14513                   *obufp++ = '+';
14514                   *obufp = '\0';
14515                 }
14516               else if (modrm.mod != 1 && disp != -disp)
14517                 {
14518                   *obufp++ = '-';
14519                   *obufp = '\0';
14520                   disp = - (bfd_signed_vma) disp;
14521                 }
14522
14523               if (havedisp)
14524                 print_displacement (scratchbuf, disp);
14525               else
14526                 print_operand_value (scratchbuf, 1, disp);
14527               oappend (scratchbuf);
14528             }
14529
14530           *obufp++ = close_char;
14531           *obufp = '\0';
14532         }
14533       else if (intel_syntax)
14534         {
14535           if (modrm.mod != 0 || base == 5)
14536             {
14537               if (!active_seg_prefix)
14538                 {
14539                   oappend (names_seg[ds_reg - es_reg]);
14540                   oappend (":");
14541                 }
14542               print_operand_value (scratchbuf, 1, disp);
14543               oappend (scratchbuf);
14544             }
14545         }
14546     }
14547   else
14548     {
14549       /* 16 bit address mode */
14550       used_prefixes |= prefixes & PREFIX_ADDR;
14551       switch (modrm.mod)
14552         {
14553         case 0:
14554           if (modrm.rm == 6)
14555             {
14556               disp = get16 ();
14557               if ((disp & 0x8000) != 0)
14558                 disp -= 0x10000;
14559             }
14560           break;
14561         case 1:
14562           FETCH_DATA (the_info, codep + 1);
14563           disp = *codep++;
14564           if ((disp & 0x80) != 0)
14565             disp -= 0x100;
14566           break;
14567         case 2:
14568           disp = get16 ();
14569           if ((disp & 0x8000) != 0)
14570             disp -= 0x10000;
14571           break;
14572         }
14573
14574       if (!intel_syntax)
14575         if (modrm.mod != 0 || modrm.rm == 6)
14576           {
14577             print_displacement (scratchbuf, disp);
14578             oappend (scratchbuf);
14579           }
14580
14581       if (modrm.mod != 0 || modrm.rm != 6)
14582         {
14583           *obufp++ = open_char;
14584           *obufp = '\0';
14585           oappend (index16[modrm.rm]);
14586           if (intel_syntax
14587               && (disp || modrm.mod != 0 || modrm.rm == 6))
14588             {
14589               if ((bfd_signed_vma) disp >= 0)
14590                 {
14591                   *obufp++ = '+';
14592                   *obufp = '\0';
14593                 }
14594               else if (modrm.mod != 1)
14595                 {
14596                   *obufp++ = '-';
14597                   *obufp = '\0';
14598                   disp = - (bfd_signed_vma) disp;
14599                 }
14600
14601               print_displacement (scratchbuf, disp);
14602               oappend (scratchbuf);
14603             }
14604
14605           *obufp++ = close_char;
14606           *obufp = '\0';
14607         }
14608       else if (intel_syntax)
14609         {
14610           if (!active_seg_prefix)
14611             {
14612               oappend (names_seg[ds_reg - es_reg]);
14613               oappend (":");
14614             }
14615           print_operand_value (scratchbuf, 1, disp & 0xffff);
14616           oappend (scratchbuf);
14617         }
14618     }
14619   if (vex.evex && vex.b
14620       && (bytemode == x_mode
14621           || bytemode == evex_half_bcst_xmmq_mode))
14622     {
14623       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14624         oappend ("{1to8}");
14625       else
14626         oappend ("{1to16}");
14627     }
14628 }
14629
14630 static void
14631 OP_E (int bytemode, int sizeflag)
14632 {
14633   /* Skip mod/rm byte.  */
14634   MODRM_CHECK;
14635   codep++;
14636
14637   if (modrm.mod == 3)
14638     OP_E_register (bytemode, sizeflag);
14639   else
14640     OP_E_memory (bytemode, sizeflag);
14641 }
14642
14643 static void
14644 OP_G (int bytemode, int sizeflag)
14645 {
14646   int add = 0;
14647   USED_REX (REX_R);
14648   if (rex & REX_R)
14649     add += 8;
14650   switch (bytemode)
14651     {
14652     case b_mode:
14653       USED_REX (0);
14654       if (rex)
14655         oappend (names8rex[modrm.reg + add]);
14656       else
14657         oappend (names8[modrm.reg + add]);
14658       break;
14659     case w_mode:
14660       oappend (names16[modrm.reg + add]);
14661       break;
14662     case d_mode:
14663       oappend (names32[modrm.reg + add]);
14664       break;
14665     case q_mode:
14666       oappend (names64[modrm.reg + add]);
14667       break;
14668     case bnd_mode:
14669       oappend (names_bnd[modrm.reg]);
14670       break;
14671     case v_mode:
14672     case dq_mode:
14673     case dqb_mode:
14674     case dqd_mode:
14675     case dqw_mode:
14676       USED_REX (REX_W);
14677       if (rex & REX_W)
14678         oappend (names64[modrm.reg + add]);
14679       else
14680         {
14681           if ((sizeflag & DFLAG) || bytemode != v_mode)
14682             oappend (names32[modrm.reg + add]);
14683           else
14684             oappend (names16[modrm.reg + add]);
14685           used_prefixes |= (prefixes & PREFIX_DATA);
14686         }
14687       break;
14688     case m_mode:
14689       if (address_mode == mode_64bit)
14690         oappend (names64[modrm.reg + add]);
14691       else
14692         oappend (names32[modrm.reg + add]);
14693       break;
14694     case mask_mode:
14695       oappend (names_mask[modrm.reg + add]);
14696       break;
14697     default:
14698       oappend (INTERNAL_DISASSEMBLER_ERROR);
14699       break;
14700     }
14701 }
14702
14703 static bfd_vma
14704 get64 (void)
14705 {
14706   bfd_vma x;
14707 #ifdef BFD64
14708   unsigned int a;
14709   unsigned int b;
14710
14711   FETCH_DATA (the_info, codep + 8);
14712   a = *codep++ & 0xff;
14713   a |= (*codep++ & 0xff) << 8;
14714   a |= (*codep++ & 0xff) << 16;
14715   a |= (*codep++ & 0xff) << 24;
14716   b = *codep++ & 0xff;
14717   b |= (*codep++ & 0xff) << 8;
14718   b |= (*codep++ & 0xff) << 16;
14719   b |= (*codep++ & 0xff) << 24;
14720   x = a + ((bfd_vma) b << 32);
14721 #else
14722   abort ();
14723   x = 0;
14724 #endif
14725   return x;
14726 }
14727
14728 static bfd_signed_vma
14729 get32 (void)
14730 {
14731   bfd_signed_vma x = 0;
14732
14733   FETCH_DATA (the_info, codep + 4);
14734   x = *codep++ & (bfd_signed_vma) 0xff;
14735   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14736   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14737   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14738   return x;
14739 }
14740
14741 static bfd_signed_vma
14742 get32s (void)
14743 {
14744   bfd_signed_vma x = 0;
14745
14746   FETCH_DATA (the_info, codep + 4);
14747   x = *codep++ & (bfd_signed_vma) 0xff;
14748   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14749   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14750   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14751
14752   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14753
14754   return x;
14755 }
14756
14757 static int
14758 get16 (void)
14759 {
14760   int x = 0;
14761
14762   FETCH_DATA (the_info, codep + 2);
14763   x = *codep++ & 0xff;
14764   x |= (*codep++ & 0xff) << 8;
14765   return x;
14766 }
14767
14768 static void
14769 set_op (bfd_vma op, int riprel)
14770 {
14771   op_index[op_ad] = op_ad;
14772   if (address_mode == mode_64bit)
14773     {
14774       op_address[op_ad] = op;
14775       op_riprel[op_ad] = riprel;
14776     }
14777   else
14778     {
14779       /* Mask to get a 32-bit address.  */
14780       op_address[op_ad] = op & 0xffffffff;
14781       op_riprel[op_ad] = riprel & 0xffffffff;
14782     }
14783 }
14784
14785 static void
14786 OP_REG (int code, int sizeflag)
14787 {
14788   const char *s;
14789   int add;
14790
14791   switch (code)
14792     {
14793     case es_reg: case ss_reg: case cs_reg:
14794     case ds_reg: case fs_reg: case gs_reg:
14795       oappend (names_seg[code - es_reg]);
14796       return;
14797     }
14798
14799   USED_REX (REX_B);
14800   if (rex & REX_B)
14801     add = 8;
14802   else
14803     add = 0;
14804
14805   switch (code)
14806     {
14807     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14808     case sp_reg: case bp_reg: case si_reg: case di_reg:
14809       s = names16[code - ax_reg + add];
14810       break;
14811     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14812     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14813       USED_REX (0);
14814       if (rex)
14815         s = names8rex[code - al_reg + add];
14816       else
14817         s = names8[code - al_reg];
14818       break;
14819     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14820     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14821       if (address_mode == mode_64bit
14822           && ((sizeflag & DFLAG) || (rex & REX_W)))
14823         {
14824           s = names64[code - rAX_reg + add];
14825           break;
14826         }
14827       code += eAX_reg - rAX_reg;
14828       /* Fall through.  */
14829     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14830     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14831       USED_REX (REX_W);
14832       if (rex & REX_W)
14833         s = names64[code - eAX_reg + add];
14834       else
14835         {
14836           if (sizeflag & DFLAG)
14837             s = names32[code - eAX_reg + add];
14838           else
14839             s = names16[code - eAX_reg + add];
14840           used_prefixes |= (prefixes & PREFIX_DATA);
14841         }
14842       break;
14843     default:
14844       s = INTERNAL_DISASSEMBLER_ERROR;
14845       break;
14846     }
14847   oappend (s);
14848 }
14849
14850 static void
14851 OP_IMREG (int code, int sizeflag)
14852 {
14853   const char *s;
14854
14855   switch (code)
14856     {
14857     case indir_dx_reg:
14858       if (intel_syntax)
14859         s = "dx";
14860       else
14861         s = "(%dx)";
14862       break;
14863     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14864     case sp_reg: case bp_reg: case si_reg: case di_reg:
14865       s = names16[code - ax_reg];
14866       break;
14867     case es_reg: case ss_reg: case cs_reg:
14868     case ds_reg: case fs_reg: case gs_reg:
14869       s = names_seg[code - es_reg];
14870       break;
14871     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14872     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14873       USED_REX (0);
14874       if (rex)
14875         s = names8rex[code - al_reg];
14876       else
14877         s = names8[code - al_reg];
14878       break;
14879     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14880     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14881       USED_REX (REX_W);
14882       if (rex & REX_W)
14883         s = names64[code - eAX_reg];
14884       else
14885         {
14886           if (sizeflag & DFLAG)
14887             s = names32[code - eAX_reg];
14888           else
14889             s = names16[code - eAX_reg];
14890           used_prefixes |= (prefixes & PREFIX_DATA);
14891         }
14892       break;
14893     case z_mode_ax_reg:
14894       if ((rex & REX_W) || (sizeflag & DFLAG))
14895         s = *names32;
14896       else
14897         s = *names16;
14898       if (!(rex & REX_W))
14899         used_prefixes |= (prefixes & PREFIX_DATA);
14900       break;
14901     default:
14902       s = INTERNAL_DISASSEMBLER_ERROR;
14903       break;
14904     }
14905   oappend (s);
14906 }
14907
14908 static void
14909 OP_I (int bytemode, int sizeflag)
14910 {
14911   bfd_signed_vma op;
14912   bfd_signed_vma mask = -1;
14913
14914   switch (bytemode)
14915     {
14916     case b_mode:
14917       FETCH_DATA (the_info, codep + 1);
14918       op = *codep++;
14919       mask = 0xff;
14920       break;
14921     case q_mode:
14922       if (address_mode == mode_64bit)
14923         {
14924           op = get32s ();
14925           break;
14926         }
14927       /* Fall through.  */
14928     case v_mode:
14929       USED_REX (REX_W);
14930       if (rex & REX_W)
14931         op = get32s ();
14932       else
14933         {
14934           if (sizeflag & DFLAG)
14935             {
14936               op = get32 ();
14937               mask = 0xffffffff;
14938             }
14939           else
14940             {
14941               op = get16 ();
14942               mask = 0xfffff;
14943             }
14944           used_prefixes |= (prefixes & PREFIX_DATA);
14945         }
14946       break;
14947     case w_mode:
14948       mask = 0xfffff;
14949       op = get16 ();
14950       break;
14951     case const_1_mode:
14952       if (intel_syntax)
14953         oappend ("1");
14954       return;
14955     default:
14956       oappend (INTERNAL_DISASSEMBLER_ERROR);
14957       return;
14958     }
14959
14960   op &= mask;
14961   scratchbuf[0] = '$';
14962   print_operand_value (scratchbuf + 1, 1, op);
14963   oappend_maybe_intel (scratchbuf);
14964   scratchbuf[0] = '\0';
14965 }
14966
14967 static void
14968 OP_I64 (int bytemode, int sizeflag)
14969 {
14970   bfd_signed_vma op;
14971   bfd_signed_vma mask = -1;
14972
14973   if (address_mode != mode_64bit)
14974     {
14975       OP_I (bytemode, sizeflag);
14976       return;
14977     }
14978
14979   switch (bytemode)
14980     {
14981     case b_mode:
14982       FETCH_DATA (the_info, codep + 1);
14983       op = *codep++;
14984       mask = 0xff;
14985       break;
14986     case v_mode:
14987       USED_REX (REX_W);
14988       if (rex & REX_W)
14989         op = get64 ();
14990       else
14991         {
14992           if (sizeflag & DFLAG)
14993             {
14994               op = get32 ();
14995               mask = 0xffffffff;
14996             }
14997           else
14998             {
14999               op = get16 ();
15000               mask = 0xfffff;
15001             }
15002           used_prefixes |= (prefixes & PREFIX_DATA);
15003         }
15004       break;
15005     case w_mode:
15006       mask = 0xfffff;
15007       op = get16 ();
15008       break;
15009     default:
15010       oappend (INTERNAL_DISASSEMBLER_ERROR);
15011       return;
15012     }
15013
15014   op &= mask;
15015   scratchbuf[0] = '$';
15016   print_operand_value (scratchbuf + 1, 1, op);
15017   oappend_maybe_intel (scratchbuf);
15018   scratchbuf[0] = '\0';
15019 }
15020
15021 static void
15022 OP_sI (int bytemode, int sizeflag)
15023 {
15024   bfd_signed_vma op;
15025
15026   switch (bytemode)
15027     {
15028     case b_mode:
15029     case b_T_mode:
15030       FETCH_DATA (the_info, codep + 1);
15031       op = *codep++;
15032       if ((op & 0x80) != 0)
15033         op -= 0x100;
15034       if (bytemode == b_T_mode)
15035         {
15036           if (address_mode != mode_64bit
15037               || !((sizeflag & DFLAG) || (rex & REX_W)))
15038             {
15039               /* The operand-size prefix is overridden by a REX prefix.  */
15040               if ((sizeflag & DFLAG) || (rex & REX_W))
15041                 op &= 0xffffffff;
15042               else
15043                 op &= 0xffff;
15044           }
15045         }
15046       else
15047         {
15048           if (!(rex & REX_W))
15049             {
15050               if (sizeflag & DFLAG)
15051                 op &= 0xffffffff;
15052               else
15053                 op &= 0xffff;
15054             }
15055         }
15056       break;
15057     case v_mode:
15058       /* The operand-size prefix is overridden by a REX prefix.  */
15059       if ((sizeflag & DFLAG) || (rex & REX_W))
15060         op = get32s ();
15061       else
15062         op = get16 ();
15063       break;
15064     default:
15065       oappend (INTERNAL_DISASSEMBLER_ERROR);
15066       return;
15067     }
15068
15069   scratchbuf[0] = '$';
15070   print_operand_value (scratchbuf + 1, 1, op);
15071   oappend_maybe_intel (scratchbuf);
15072 }
15073
15074 static void
15075 OP_J (int bytemode, int sizeflag)
15076 {
15077   bfd_vma disp;
15078   bfd_vma mask = -1;
15079   bfd_vma segment = 0;
15080
15081   switch (bytemode)
15082     {
15083     case b_mode:
15084       FETCH_DATA (the_info, codep + 1);
15085       disp = *codep++;
15086       if ((disp & 0x80) != 0)
15087         disp -= 0x100;
15088       break;
15089     case v_mode:
15090       USED_REX (REX_W);
15091       if ((sizeflag & DFLAG) || (rex & REX_W))
15092         disp = get32s ();
15093       else
15094         {
15095           disp = get16 ();
15096           if ((disp & 0x8000) != 0)
15097             disp -= 0x10000;
15098           /* In 16bit mode, address is wrapped around at 64k within
15099              the same segment.  Otherwise, a data16 prefix on a jump
15100              instruction means that the pc is masked to 16 bits after
15101              the displacement is added!  */
15102           mask = 0xffff;
15103           if ((prefixes & PREFIX_DATA) == 0)
15104             segment = ((start_pc + codep - start_codep)
15105                        & ~((bfd_vma) 0xffff));
15106         }
15107       if (!(rex & REX_W))
15108         used_prefixes |= (prefixes & PREFIX_DATA);
15109       break;
15110     default:
15111       oappend (INTERNAL_DISASSEMBLER_ERROR);
15112       return;
15113     }
15114   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15115   set_op (disp, 0);
15116   print_operand_value (scratchbuf, 1, disp);
15117   oappend (scratchbuf);
15118 }
15119
15120 static void
15121 OP_SEG (int bytemode, int sizeflag)
15122 {
15123   if (bytemode == w_mode)
15124     oappend (names_seg[modrm.reg]);
15125   else
15126     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15127 }
15128
15129 static void
15130 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15131 {
15132   int seg, offset;
15133
15134   if (sizeflag & DFLAG)
15135     {
15136       offset = get32 ();
15137       seg = get16 ();
15138     }
15139   else
15140     {
15141       offset = get16 ();
15142       seg = get16 ();
15143     }
15144   used_prefixes |= (prefixes & PREFIX_DATA);
15145   if (intel_syntax)
15146     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15147   else
15148     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15149   oappend (scratchbuf);
15150 }
15151
15152 static void
15153 OP_OFF (int bytemode, int sizeflag)
15154 {
15155   bfd_vma off;
15156
15157   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15158     intel_operand_size (bytemode, sizeflag);
15159   append_seg ();
15160
15161   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15162     off = get32 ();
15163   else
15164     off = get16 ();
15165
15166   if (intel_syntax)
15167     {
15168       if (!active_seg_prefix)
15169         {
15170           oappend (names_seg[ds_reg - es_reg]);
15171           oappend (":");
15172         }
15173     }
15174   print_operand_value (scratchbuf, 1, off);
15175   oappend (scratchbuf);
15176 }
15177
15178 static void
15179 OP_OFF64 (int bytemode, int sizeflag)
15180 {
15181   bfd_vma off;
15182
15183   if (address_mode != mode_64bit
15184       || (prefixes & PREFIX_ADDR))
15185     {
15186       OP_OFF (bytemode, sizeflag);
15187       return;
15188     }
15189
15190   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15191     intel_operand_size (bytemode, sizeflag);
15192   append_seg ();
15193
15194   off = get64 ();
15195
15196   if (intel_syntax)
15197     {
15198       if (!active_seg_prefix)
15199         {
15200           oappend (names_seg[ds_reg - es_reg]);
15201           oappend (":");
15202         }
15203     }
15204   print_operand_value (scratchbuf, 1, off);
15205   oappend (scratchbuf);
15206 }
15207
15208 static void
15209 ptr_reg (int code, int sizeflag)
15210 {
15211   const char *s;
15212
15213   *obufp++ = open_char;
15214   used_prefixes |= (prefixes & PREFIX_ADDR);
15215   if (address_mode == mode_64bit)
15216     {
15217       if (!(sizeflag & AFLAG))
15218         s = names32[code - eAX_reg];
15219       else
15220         s = names64[code - eAX_reg];
15221     }
15222   else if (sizeflag & AFLAG)
15223     s = names32[code - eAX_reg];
15224   else
15225     s = names16[code - eAX_reg];
15226   oappend (s);
15227   *obufp++ = close_char;
15228   *obufp = 0;
15229 }
15230
15231 static void
15232 OP_ESreg (int code, int sizeflag)
15233 {
15234   if (intel_syntax)
15235     {
15236       switch (codep[-1])
15237         {
15238         case 0x6d:      /* insw/insl */
15239           intel_operand_size (z_mode, sizeflag);
15240           break;
15241         case 0xa5:      /* movsw/movsl/movsq */
15242         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15243         case 0xab:      /* stosw/stosl */
15244         case 0xaf:      /* scasw/scasl */
15245           intel_operand_size (v_mode, sizeflag);
15246           break;
15247         default:
15248           intel_operand_size (b_mode, sizeflag);
15249         }
15250     }
15251   oappend_maybe_intel ("%es:");
15252   ptr_reg (code, sizeflag);
15253 }
15254
15255 static void
15256 OP_DSreg (int code, int sizeflag)
15257 {
15258   if (intel_syntax)
15259     {
15260       switch (codep[-1])
15261         {
15262         case 0x6f:      /* outsw/outsl */
15263           intel_operand_size (z_mode, sizeflag);
15264           break;
15265         case 0xa5:      /* movsw/movsl/movsq */
15266         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15267         case 0xad:      /* lodsw/lodsl/lodsq */
15268           intel_operand_size (v_mode, sizeflag);
15269           break;
15270         default:
15271           intel_operand_size (b_mode, sizeflag);
15272         }
15273     }
15274   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15275      default segment register DS is printed.  */
15276   if (!active_seg_prefix)
15277     active_seg_prefix = PREFIX_DS;
15278   append_seg ();
15279   ptr_reg (code, sizeflag);
15280 }
15281
15282 static void
15283 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15284 {
15285   int add;
15286   if (rex & REX_R)
15287     {
15288       USED_REX (REX_R);
15289       add = 8;
15290     }
15291   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15292     {
15293       all_prefixes[last_lock_prefix] = 0;
15294       used_prefixes |= PREFIX_LOCK;
15295       add = 8;
15296     }
15297   else
15298     add = 0;
15299   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15300   oappend_maybe_intel (scratchbuf);
15301 }
15302
15303 static void
15304 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15305 {
15306   int add;
15307   USED_REX (REX_R);
15308   if (rex & REX_R)
15309     add = 8;
15310   else
15311     add = 0;
15312   if (intel_syntax)
15313     sprintf (scratchbuf, "db%d", modrm.reg + add);
15314   else
15315     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15316   oappend (scratchbuf);
15317 }
15318
15319 static void
15320 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15321 {
15322   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15323   oappend_maybe_intel (scratchbuf);
15324 }
15325
15326 static void
15327 OP_R (int bytemode, int sizeflag)
15328 {
15329   if (modrm.mod == 3)
15330     OP_E (bytemode, sizeflag);
15331   else
15332     BadOp ();
15333 }
15334
15335 static void
15336 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15337 {
15338   int reg = modrm.reg;
15339   const char **names;
15340
15341   used_prefixes |= (prefixes & PREFIX_DATA);
15342   if (prefixes & PREFIX_DATA)
15343     {
15344       names = names_xmm;
15345       USED_REX (REX_R);
15346       if (rex & REX_R)
15347         reg += 8;
15348     }
15349   else
15350     names = names_mm;
15351   oappend (names[reg]);
15352 }
15353
15354 static void
15355 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15356 {
15357   int reg = modrm.reg;
15358   const char **names;
15359
15360   USED_REX (REX_R);
15361   if (rex & REX_R)
15362     reg += 8;
15363   if (vex.evex)
15364     {
15365       if (!vex.r)
15366         reg += 16;
15367     }
15368
15369   if (need_vex
15370       && bytemode != xmm_mode
15371       && bytemode != xmmq_mode
15372       && bytemode != evex_half_bcst_xmmq_mode
15373       && bytemode != ymm_mode
15374       && bytemode != scalar_mode)
15375     {
15376       switch (vex.length)
15377         {
15378         case 128:
15379           names = names_xmm;
15380           break;
15381         case 256:
15382           if (vex.w
15383               || (bytemode != vex_vsib_q_w_dq_mode
15384                   && bytemode != vex_vsib_q_w_d_mode))
15385             names = names_ymm;
15386           else
15387             names = names_xmm;
15388           break;
15389         case 512:
15390           names = names_zmm;
15391           break;
15392         default:
15393           abort ();
15394         }
15395     }
15396   else if (bytemode == xmmq_mode
15397            || bytemode == evex_half_bcst_xmmq_mode)
15398     {
15399       switch (vex.length)
15400         {
15401         case 128:
15402         case 256:
15403           names = names_xmm;
15404           break;
15405         case 512:
15406           names = names_ymm;
15407           break;
15408         default:
15409           abort ();
15410         }
15411     }
15412   else if (bytemode == ymm_mode)
15413     names = names_ymm;
15414   else
15415     names = names_xmm;
15416   oappend (names[reg]);
15417 }
15418
15419 static void
15420 OP_EM (int bytemode, int sizeflag)
15421 {
15422   int reg;
15423   const char **names;
15424
15425   if (modrm.mod != 3)
15426     {
15427       if (intel_syntax
15428           && (bytemode == v_mode || bytemode == v_swap_mode))
15429         {
15430           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15431           used_prefixes |= (prefixes & PREFIX_DATA);
15432         }
15433       OP_E (bytemode, sizeflag);
15434       return;
15435     }
15436
15437   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15438     swap_operand ();
15439
15440   /* Skip mod/rm byte.  */
15441   MODRM_CHECK;
15442   codep++;
15443   used_prefixes |= (prefixes & PREFIX_DATA);
15444   reg = modrm.rm;
15445   if (prefixes & PREFIX_DATA)
15446     {
15447       names = names_xmm;
15448       USED_REX (REX_B);
15449       if (rex & REX_B)
15450         reg += 8;
15451     }
15452   else
15453     names = names_mm;
15454   oappend (names[reg]);
15455 }
15456
15457 /* cvt* are the only instructions in sse2 which have
15458    both SSE and MMX operands and also have 0x66 prefix
15459    in their opcode. 0x66 was originally used to differentiate
15460    between SSE and MMX instruction(operands). So we have to handle the
15461    cvt* separately using OP_EMC and OP_MXC */
15462 static void
15463 OP_EMC (int bytemode, int sizeflag)
15464 {
15465   if (modrm.mod != 3)
15466     {
15467       if (intel_syntax && bytemode == v_mode)
15468         {
15469           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15470           used_prefixes |= (prefixes & PREFIX_DATA);
15471         }
15472       OP_E (bytemode, sizeflag);
15473       return;
15474     }
15475
15476   /* Skip mod/rm byte.  */
15477   MODRM_CHECK;
15478   codep++;
15479   used_prefixes |= (prefixes & PREFIX_DATA);
15480   oappend (names_mm[modrm.rm]);
15481 }
15482
15483 static void
15484 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15485 {
15486   used_prefixes |= (prefixes & PREFIX_DATA);
15487   oappend (names_mm[modrm.reg]);
15488 }
15489
15490 static void
15491 OP_EX (int bytemode, int sizeflag)
15492 {
15493   int reg;
15494   const char **names;
15495
15496   /* Skip mod/rm byte.  */
15497   MODRM_CHECK;
15498   codep++;
15499
15500   if (modrm.mod != 3)
15501     {
15502       OP_E_memory (bytemode, sizeflag);
15503       return;
15504     }
15505
15506   reg = modrm.rm;
15507   USED_REX (REX_B);
15508   if (rex & REX_B)
15509     reg += 8;
15510   if (vex.evex)
15511     {
15512       USED_REX (REX_X);
15513       if ((rex & REX_X))
15514         reg += 16;
15515     }
15516
15517   if ((sizeflag & SUFFIX_ALWAYS)
15518       && (bytemode == x_swap_mode
15519           || bytemode == d_swap_mode
15520           || bytemode == d_scalar_swap_mode
15521           || bytemode == q_swap_mode
15522           || bytemode == q_scalar_swap_mode))
15523     swap_operand ();
15524
15525   if (need_vex
15526       && bytemode != xmm_mode
15527       && bytemode != xmmdw_mode
15528       && bytemode != xmmqd_mode
15529       && bytemode != xmm_mb_mode
15530       && bytemode != xmm_mw_mode
15531       && bytemode != xmm_md_mode
15532       && bytemode != xmm_mq_mode
15533       && bytemode != xmm_mdq_mode
15534       && bytemode != xmmq_mode
15535       && bytemode != evex_half_bcst_xmmq_mode
15536       && bytemode != ymm_mode
15537       && bytemode != d_scalar_mode
15538       && bytemode != d_scalar_swap_mode
15539       && bytemode != q_scalar_mode
15540       && bytemode != q_scalar_swap_mode
15541       && bytemode != vex_scalar_w_dq_mode)
15542     {
15543       switch (vex.length)
15544         {
15545         case 128:
15546           names = names_xmm;
15547           break;
15548         case 256:
15549           names = names_ymm;
15550           break;
15551         case 512:
15552           names = names_zmm;
15553           break;
15554         default:
15555           abort ();
15556         }
15557     }
15558   else if (bytemode == xmmq_mode
15559            || bytemode == evex_half_bcst_xmmq_mode)
15560     {
15561       switch (vex.length)
15562         {
15563         case 128:
15564         case 256:
15565           names = names_xmm;
15566           break;
15567         case 512:
15568           names = names_ymm;
15569           break;
15570         default:
15571           abort ();
15572         }
15573     }
15574   else if (bytemode == ymm_mode)
15575     names = names_ymm;
15576   else
15577     names = names_xmm;
15578   oappend (names[reg]);
15579 }
15580
15581 static void
15582 OP_MS (int bytemode, int sizeflag)
15583 {
15584   if (modrm.mod == 3)
15585     OP_EM (bytemode, sizeflag);
15586   else
15587     BadOp ();
15588 }
15589
15590 static void
15591 OP_XS (int bytemode, int sizeflag)
15592 {
15593   if (modrm.mod == 3)
15594     OP_EX (bytemode, sizeflag);
15595   else
15596     BadOp ();
15597 }
15598
15599 static void
15600 OP_M (int bytemode, int sizeflag)
15601 {
15602   if (modrm.mod == 3)
15603     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15604     BadOp ();
15605   else
15606     OP_E (bytemode, sizeflag);
15607 }
15608
15609 static void
15610 OP_0f07 (int bytemode, int sizeflag)
15611 {
15612   if (modrm.mod != 3 || modrm.rm != 0)
15613     BadOp ();
15614   else
15615     OP_E (bytemode, sizeflag);
15616 }
15617
15618 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15619    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15620
15621 static void
15622 NOP_Fixup1 (int bytemode, int sizeflag)
15623 {
15624   if ((prefixes & PREFIX_DATA) != 0
15625       || (rex != 0
15626           && rex != 0x48
15627           && address_mode == mode_64bit))
15628     OP_REG (bytemode, sizeflag);
15629   else
15630     strcpy (obuf, "nop");
15631 }
15632
15633 static void
15634 NOP_Fixup2 (int bytemode, int sizeflag)
15635 {
15636   if ((prefixes & PREFIX_DATA) != 0
15637       || (rex != 0
15638           && rex != 0x48
15639           && address_mode == mode_64bit))
15640     OP_IMREG (bytemode, sizeflag);
15641 }
15642
15643 static const char *const Suffix3DNow[] = {
15644 /* 00 */        NULL,           NULL,           NULL,           NULL,
15645 /* 04 */        NULL,           NULL,           NULL,           NULL,
15646 /* 08 */        NULL,           NULL,           NULL,           NULL,
15647 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15648 /* 10 */        NULL,           NULL,           NULL,           NULL,
15649 /* 14 */        NULL,           NULL,           NULL,           NULL,
15650 /* 18 */        NULL,           NULL,           NULL,           NULL,
15651 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15652 /* 20 */        NULL,           NULL,           NULL,           NULL,
15653 /* 24 */        NULL,           NULL,           NULL,           NULL,
15654 /* 28 */        NULL,           NULL,           NULL,           NULL,
15655 /* 2C */        NULL,           NULL,           NULL,           NULL,
15656 /* 30 */        NULL,           NULL,           NULL,           NULL,
15657 /* 34 */        NULL,           NULL,           NULL,           NULL,
15658 /* 38 */        NULL,           NULL,           NULL,           NULL,
15659 /* 3C */        NULL,           NULL,           NULL,           NULL,
15660 /* 40 */        NULL,           NULL,           NULL,           NULL,
15661 /* 44 */        NULL,           NULL,           NULL,           NULL,
15662 /* 48 */        NULL,           NULL,           NULL,           NULL,
15663 /* 4C */        NULL,           NULL,           NULL,           NULL,
15664 /* 50 */        NULL,           NULL,           NULL,           NULL,
15665 /* 54 */        NULL,           NULL,           NULL,           NULL,
15666 /* 58 */        NULL,           NULL,           NULL,           NULL,
15667 /* 5C */        NULL,           NULL,           NULL,           NULL,
15668 /* 60 */        NULL,           NULL,           NULL,           NULL,
15669 /* 64 */        NULL,           NULL,           NULL,           NULL,
15670 /* 68 */        NULL,           NULL,           NULL,           NULL,
15671 /* 6C */        NULL,           NULL,           NULL,           NULL,
15672 /* 70 */        NULL,           NULL,           NULL,           NULL,
15673 /* 74 */        NULL,           NULL,           NULL,           NULL,
15674 /* 78 */        NULL,           NULL,           NULL,           NULL,
15675 /* 7C */        NULL,           NULL,           NULL,           NULL,
15676 /* 80 */        NULL,           NULL,           NULL,           NULL,
15677 /* 84 */        NULL,           NULL,           NULL,           NULL,
15678 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15679 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15680 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15681 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15682 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15683 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15684 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15685 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15686 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15687 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15688 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15689 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15690 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15691 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15692 /* C0 */        NULL,           NULL,           NULL,           NULL,
15693 /* C4 */        NULL,           NULL,           NULL,           NULL,
15694 /* C8 */        NULL,           NULL,           NULL,           NULL,
15695 /* CC */        NULL,           NULL,           NULL,           NULL,
15696 /* D0 */        NULL,           NULL,           NULL,           NULL,
15697 /* D4 */        NULL,           NULL,           NULL,           NULL,
15698 /* D8 */        NULL,           NULL,           NULL,           NULL,
15699 /* DC */        NULL,           NULL,           NULL,           NULL,
15700 /* E0 */        NULL,           NULL,           NULL,           NULL,
15701 /* E4 */        NULL,           NULL,           NULL,           NULL,
15702 /* E8 */        NULL,           NULL,           NULL,           NULL,
15703 /* EC */        NULL,           NULL,           NULL,           NULL,
15704 /* F0 */        NULL,           NULL,           NULL,           NULL,
15705 /* F4 */        NULL,           NULL,           NULL,           NULL,
15706 /* F8 */        NULL,           NULL,           NULL,           NULL,
15707 /* FC */        NULL,           NULL,           NULL,           NULL,
15708 };
15709
15710 static void
15711 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15712 {
15713   const char *mnemonic;
15714
15715   FETCH_DATA (the_info, codep + 1);
15716   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15717      place where an 8-bit immediate would normally go.  ie. the last
15718      byte of the instruction.  */
15719   obufp = mnemonicendp;
15720   mnemonic = Suffix3DNow[*codep++ & 0xff];
15721   if (mnemonic)
15722     oappend (mnemonic);
15723   else
15724     {
15725       /* Since a variable sized modrm/sib chunk is between the start
15726          of the opcode (0x0f0f) and the opcode suffix, we need to do
15727          all the modrm processing first, and don't know until now that
15728          we have a bad opcode.  This necessitates some cleaning up.  */
15729       op_out[0][0] = '\0';
15730       op_out[1][0] = '\0';
15731       BadOp ();
15732     }
15733   mnemonicendp = obufp;
15734 }
15735
15736 static struct op simd_cmp_op[] =
15737 {
15738   { STRING_COMMA_LEN ("eq") },
15739   { STRING_COMMA_LEN ("lt") },
15740   { STRING_COMMA_LEN ("le") },
15741   { STRING_COMMA_LEN ("unord") },
15742   { STRING_COMMA_LEN ("neq") },
15743   { STRING_COMMA_LEN ("nlt") },
15744   { STRING_COMMA_LEN ("nle") },
15745   { STRING_COMMA_LEN ("ord") }
15746 };
15747
15748 static void
15749 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15750 {
15751   unsigned int cmp_type;
15752
15753   FETCH_DATA (the_info, codep + 1);
15754   cmp_type = *codep++ & 0xff;
15755   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15756     {
15757       char suffix [3];
15758       char *p = mnemonicendp - 2;
15759       suffix[0] = p[0];
15760       suffix[1] = p[1];
15761       suffix[2] = '\0';
15762       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15763       mnemonicendp += simd_cmp_op[cmp_type].len;
15764     }
15765   else
15766     {
15767       /* We have a reserved extension byte.  Output it directly.  */
15768       scratchbuf[0] = '$';
15769       print_operand_value (scratchbuf + 1, 1, cmp_type);
15770       oappend_maybe_intel (scratchbuf);
15771       scratchbuf[0] = '\0';
15772     }
15773 }
15774
15775 static void
15776 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15777           int sizeflag ATTRIBUTE_UNUSED)
15778 {
15779   /* mwait %eax,%ecx  */
15780   if (!intel_syntax)
15781     {
15782       const char **names = (address_mode == mode_64bit
15783                             ? names64 : names32);
15784       strcpy (op_out[0], names[0]);
15785       strcpy (op_out[1], names[1]);
15786       two_source_ops = 1;
15787     }
15788   /* Skip mod/rm byte.  */
15789   MODRM_CHECK;
15790   codep++;
15791 }
15792
15793 static void
15794 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15795             int sizeflag ATTRIBUTE_UNUSED)
15796 {
15797   /* monitor %eax,%ecx,%edx"  */
15798   if (!intel_syntax)
15799     {
15800       const char **op1_names;
15801       const char **names = (address_mode == mode_64bit
15802                             ? names64 : names32);
15803
15804       if (!(prefixes & PREFIX_ADDR))
15805         op1_names = (address_mode == mode_16bit
15806                      ? names16 : names);
15807       else
15808         {
15809           /* Remove "addr16/addr32".  */
15810           all_prefixes[last_addr_prefix] = 0;
15811           op1_names = (address_mode != mode_32bit
15812                        ? names32 : names16);
15813           used_prefixes |= PREFIX_ADDR;
15814         }
15815       strcpy (op_out[0], op1_names[0]);
15816       strcpy (op_out[1], names[1]);
15817       strcpy (op_out[2], names[2]);
15818       two_source_ops = 1;
15819     }
15820   /* Skip mod/rm byte.  */
15821   MODRM_CHECK;
15822   codep++;
15823 }
15824
15825 static void
15826 BadOp (void)
15827 {
15828   /* Throw away prefixes and 1st. opcode byte.  */
15829   codep = insn_codep + 1;
15830   oappend ("(bad)");
15831 }
15832
15833 static void
15834 REP_Fixup (int bytemode, int sizeflag)
15835 {
15836   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15837      lods and stos.  */
15838   if (prefixes & PREFIX_REPZ)
15839     all_prefixes[last_repz_prefix] = REP_PREFIX;
15840
15841   switch (bytemode)
15842     {
15843     case al_reg:
15844     case eAX_reg:
15845     case indir_dx_reg:
15846       OP_IMREG (bytemode, sizeflag);
15847       break;
15848     case eDI_reg:
15849       OP_ESreg (bytemode, sizeflag);
15850       break;
15851     case eSI_reg:
15852       OP_DSreg (bytemode, sizeflag);
15853       break;
15854     default:
15855       abort ();
15856       break;
15857     }
15858 }
15859
15860 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15861    "bnd".  */
15862
15863 static void
15864 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15865 {
15866   if (prefixes & PREFIX_REPNZ)
15867     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15868 }
15869
15870 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15871    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15872  */
15873
15874 static void
15875 HLE_Fixup1 (int bytemode, int sizeflag)
15876 {
15877   if (modrm.mod != 3
15878       && (prefixes & PREFIX_LOCK) != 0)
15879     {
15880       if (prefixes & PREFIX_REPZ)
15881         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15882       if (prefixes & PREFIX_REPNZ)
15883         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15884     }
15885
15886   OP_E (bytemode, sizeflag);
15887 }
15888
15889 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15890    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15891  */
15892
15893 static void
15894 HLE_Fixup2 (int bytemode, int sizeflag)
15895 {
15896   if (modrm.mod != 3)
15897     {
15898       if (prefixes & PREFIX_REPZ)
15899         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15900       if (prefixes & PREFIX_REPNZ)
15901         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15902     }
15903
15904   OP_E (bytemode, sizeflag);
15905 }
15906
15907 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15908    "xrelease" for memory operand.  No check for LOCK prefix.   */
15909
15910 static void
15911 HLE_Fixup3 (int bytemode, int sizeflag)
15912 {
15913   if (modrm.mod != 3
15914       && last_repz_prefix > last_repnz_prefix
15915       && (prefixes & PREFIX_REPZ) != 0)
15916     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15917
15918   OP_E (bytemode, sizeflag);
15919 }
15920
15921 static void
15922 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15923 {
15924   USED_REX (REX_W);
15925   if (rex & REX_W)
15926     {
15927       /* Change cmpxchg8b to cmpxchg16b.  */
15928       char *p = mnemonicendp - 2;
15929       mnemonicendp = stpcpy (p, "16b");
15930       bytemode = o_mode;
15931     }
15932   else if ((prefixes & PREFIX_LOCK) != 0)
15933     {
15934       if (prefixes & PREFIX_REPZ)
15935         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15936       if (prefixes & PREFIX_REPNZ)
15937         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15938     }
15939
15940   OP_M (bytemode, sizeflag);
15941 }
15942
15943 static void
15944 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15945 {
15946   const char **names;
15947
15948   if (need_vex)
15949     {
15950       switch (vex.length)
15951         {
15952         case 128:
15953           names = names_xmm;
15954           break;
15955         case 256:
15956           names = names_ymm;
15957           break;
15958         default:
15959           abort ();
15960         }
15961     }
15962   else
15963     names = names_xmm;
15964   oappend (names[reg]);
15965 }
15966
15967 static void
15968 CRC32_Fixup (int bytemode, int sizeflag)
15969 {
15970   /* Add proper suffix to "crc32".  */
15971   char *p = mnemonicendp;
15972
15973   switch (bytemode)
15974     {
15975     case b_mode:
15976       if (intel_syntax)
15977         goto skip;
15978
15979       *p++ = 'b';
15980       break;
15981     case v_mode:
15982       if (intel_syntax)
15983         goto skip;
15984
15985       USED_REX (REX_W);
15986       if (rex & REX_W)
15987         *p++ = 'q';
15988       else
15989         {
15990           if (sizeflag & DFLAG)
15991             *p++ = 'l';
15992           else
15993             *p++ = 'w';
15994           used_prefixes |= (prefixes & PREFIX_DATA);
15995         }
15996       break;
15997     default:
15998       oappend (INTERNAL_DISASSEMBLER_ERROR);
15999       break;
16000     }
16001   mnemonicendp = p;
16002   *p = '\0';
16003
16004 skip:
16005   if (modrm.mod == 3)
16006     {
16007       int add;
16008
16009       /* Skip mod/rm byte.  */
16010       MODRM_CHECK;
16011       codep++;
16012
16013       USED_REX (REX_B);
16014       add = (rex & REX_B) ? 8 : 0;
16015       if (bytemode == b_mode)
16016         {
16017           USED_REX (0);
16018           if (rex)
16019             oappend (names8rex[modrm.rm + add]);
16020           else
16021             oappend (names8[modrm.rm + add]);
16022         }
16023       else
16024         {
16025           USED_REX (REX_W);
16026           if (rex & REX_W)
16027             oappend (names64[modrm.rm + add]);
16028           else if ((prefixes & PREFIX_DATA))
16029             oappend (names16[modrm.rm + add]);
16030           else
16031             oappend (names32[modrm.rm + add]);
16032         }
16033     }
16034   else
16035     OP_E (bytemode, sizeflag);
16036 }
16037
16038 static void
16039 FXSAVE_Fixup (int bytemode, int sizeflag)
16040 {
16041   /* Add proper suffix to "fxsave" and "fxrstor".  */
16042   USED_REX (REX_W);
16043   if (rex & REX_W)
16044     {
16045       char *p = mnemonicendp;
16046       *p++ = '6';
16047       *p++ = '4';
16048       *p = '\0';
16049       mnemonicendp = p;
16050     }
16051   OP_M (bytemode, sizeflag);
16052 }
16053
16054 /* Display the destination register operand for instructions with
16055    VEX. */
16056
16057 static void
16058 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16059 {
16060   int reg;
16061   const char **names;
16062
16063   if (!need_vex)
16064     abort ();
16065
16066   if (!need_vex_reg)
16067     return;
16068
16069   reg = vex.register_specifier;
16070   if (vex.evex)
16071     {
16072       if (!vex.v)
16073         reg += 16;
16074     }
16075
16076   if (bytemode == vex_scalar_mode)
16077     {
16078       oappend (names_xmm[reg]);
16079       return;
16080     }
16081
16082   switch (vex.length)
16083     {
16084     case 128:
16085       switch (bytemode)
16086         {
16087         case vex_mode:
16088         case vex128_mode:
16089         case vex_vsib_q_w_dq_mode:
16090         case vex_vsib_q_w_d_mode:
16091           names = names_xmm;
16092           break;
16093         case dq_mode:
16094           if (vex.w)
16095             names = names64;
16096           else
16097             names = names32;
16098           break;
16099         case mask_mode:
16100           names = names_mask;
16101           break;
16102         default:
16103           abort ();
16104           return;
16105         }
16106       break;
16107     case 256:
16108       switch (bytemode)
16109         {
16110         case vex_mode:
16111         case vex256_mode:
16112           names = names_ymm;
16113           break;
16114         case vex_vsib_q_w_dq_mode:
16115         case vex_vsib_q_w_d_mode:
16116           names = vex.w ? names_ymm : names_xmm;
16117           break;
16118         case mask_mode:
16119           names = names_mask;
16120           break;
16121         default:
16122           abort ();
16123           return;
16124         }
16125       break;
16126     case 512:
16127       names = names_zmm;
16128       break;
16129     default:
16130       abort ();
16131       break;
16132     }
16133   oappend (names[reg]);
16134 }
16135
16136 /* Get the VEX immediate byte without moving codep.  */
16137
16138 static unsigned char
16139 get_vex_imm8 (int sizeflag, int opnum)
16140 {
16141   int bytes_before_imm = 0;
16142
16143   if (modrm.mod != 3)
16144     {
16145       /* There are SIB/displacement bytes.  */
16146       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16147         {
16148           /* 32/64 bit address mode */
16149           int base = modrm.rm;
16150
16151           /* Check SIB byte.  */
16152           if (base == 4)
16153             {
16154               FETCH_DATA (the_info, codep + 1);
16155               base = *codep & 7;
16156               /* When decoding the third source, don't increase
16157                  bytes_before_imm as this has already been incremented
16158                  by one in OP_E_memory while decoding the second
16159                  source operand.  */
16160               if (opnum == 0)
16161                 bytes_before_imm++;
16162             }
16163
16164           /* Don't increase bytes_before_imm when decoding the third source,
16165              it has already been incremented by OP_E_memory while decoding
16166              the second source operand.  */
16167           if (opnum == 0)
16168             {
16169               switch (modrm.mod)
16170                 {
16171                   case 0:
16172                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16173                        SIB == 5, there is a 4 byte displacement.  */
16174                     if (base != 5)
16175                       /* No displacement. */
16176                       break;
16177                   case 2:
16178                     /* 4 byte displacement.  */
16179                     bytes_before_imm += 4;
16180                     break;
16181                   case 1:
16182                     /* 1 byte displacement.  */
16183                     bytes_before_imm++;
16184                     break;
16185                 }
16186             }
16187         }
16188       else
16189         {
16190           /* 16 bit address mode */
16191           /* Don't increase bytes_before_imm when decoding the third source,
16192              it has already been incremented by OP_E_memory while decoding
16193              the second source operand.  */
16194           if (opnum == 0)
16195             {
16196               switch (modrm.mod)
16197                 {
16198                 case 0:
16199                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16200                   if (modrm.rm != 6)
16201                     /* No displacement. */
16202                     break;
16203                 case 2:
16204                   /* 2 byte displacement.  */
16205                   bytes_before_imm += 2;
16206                   break;
16207                 case 1:
16208                   /* 1 byte displacement: when decoding the third source,
16209                      don't increase bytes_before_imm as this has already
16210                      been incremented by one in OP_E_memory while decoding
16211                      the second source operand.  */
16212                   if (opnum == 0)
16213                     bytes_before_imm++;
16214
16215                   break;
16216                 }
16217             }
16218         }
16219     }
16220
16221   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16222   return codep [bytes_before_imm];
16223 }
16224
16225 static void
16226 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16227 {
16228   const char **names;
16229
16230   if (reg == -1 && modrm.mod != 3)
16231     {
16232       OP_E_memory (bytemode, sizeflag);
16233       return;
16234     }
16235   else
16236     {
16237       if (reg == -1)
16238         {
16239           reg = modrm.rm;
16240           USED_REX (REX_B);
16241           if (rex & REX_B)
16242             reg += 8;
16243         }
16244       else if (reg > 7 && address_mode != mode_64bit)
16245         BadOp ();
16246     }
16247
16248   switch (vex.length)
16249     {
16250     case 128:
16251       names = names_xmm;
16252       break;
16253     case 256:
16254       names = names_ymm;
16255       break;
16256     default:
16257       abort ();
16258     }
16259   oappend (names[reg]);
16260 }
16261
16262 static void
16263 OP_EX_VexImmW (int bytemode, int sizeflag)
16264 {
16265   int reg = -1;
16266   static unsigned char vex_imm8;
16267
16268   if (vex_w_done == 0)
16269     {
16270       vex_w_done = 1;
16271
16272       /* Skip mod/rm byte.  */
16273       MODRM_CHECK;
16274       codep++;
16275
16276       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16277
16278       if (vex.w)
16279           reg = vex_imm8 >> 4;
16280
16281       OP_EX_VexReg (bytemode, sizeflag, reg);
16282     }
16283   else if (vex_w_done == 1)
16284     {
16285       vex_w_done = 2;
16286
16287       if (!vex.w)
16288           reg = vex_imm8 >> 4;
16289
16290       OP_EX_VexReg (bytemode, sizeflag, reg);
16291     }
16292   else
16293     {
16294       /* Output the imm8 directly.  */
16295       scratchbuf[0] = '$';
16296       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16297       oappend_maybe_intel (scratchbuf);
16298       scratchbuf[0] = '\0';
16299       codep++;
16300     }
16301 }
16302
16303 static void
16304 OP_Vex_2src (int bytemode, int sizeflag)
16305 {
16306   if (modrm.mod == 3)
16307     {
16308       int reg = modrm.rm;
16309       USED_REX (REX_B);
16310       if (rex & REX_B)
16311         reg += 8;
16312       oappend (names_xmm[reg]);
16313     }
16314   else
16315     {
16316       if (intel_syntax
16317           && (bytemode == v_mode || bytemode == v_swap_mode))
16318         {
16319           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16320           used_prefixes |= (prefixes & PREFIX_DATA);
16321         }
16322       OP_E (bytemode, sizeflag);
16323     }
16324 }
16325
16326 static void
16327 OP_Vex_2src_1 (int bytemode, int sizeflag)
16328 {
16329   if (modrm.mod == 3)
16330     {
16331       /* Skip mod/rm byte.   */
16332       MODRM_CHECK;
16333       codep++;
16334     }
16335
16336   if (vex.w)
16337     oappend (names_xmm[vex.register_specifier]);
16338   else
16339     OP_Vex_2src (bytemode, sizeflag);
16340 }
16341
16342 static void
16343 OP_Vex_2src_2 (int bytemode, int sizeflag)
16344 {
16345   if (vex.w)
16346     OP_Vex_2src (bytemode, sizeflag);
16347   else
16348     oappend (names_xmm[vex.register_specifier]);
16349 }
16350
16351 static void
16352 OP_EX_VexW (int bytemode, int sizeflag)
16353 {
16354   int reg = -1;
16355
16356   if (!vex_w_done)
16357     {
16358       vex_w_done = 1;
16359
16360       /* Skip mod/rm byte.  */
16361       MODRM_CHECK;
16362       codep++;
16363
16364       if (vex.w)
16365         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16366     }
16367   else
16368     {
16369       if (!vex.w)
16370         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16371     }
16372
16373   OP_EX_VexReg (bytemode, sizeflag, reg);
16374 }
16375
16376 static void
16377 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16378              int sizeflag ATTRIBUTE_UNUSED)
16379 {
16380   /* Skip the immediate byte and check for invalid bits.  */
16381   FETCH_DATA (the_info, codep + 1);
16382   if (*codep++ & 0xf)
16383     BadOp ();
16384 }
16385
16386 static void
16387 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16388 {
16389   int reg;
16390   const char **names;
16391
16392   FETCH_DATA (the_info, codep + 1);
16393   reg = *codep++;
16394
16395   if (bytemode != x_mode)
16396     abort ();
16397
16398   if (reg & 0xf)
16399       BadOp ();
16400
16401   reg >>= 4;
16402   if (reg > 7 && address_mode != mode_64bit)
16403     BadOp ();
16404
16405   switch (vex.length)
16406     {
16407     case 128:
16408       names = names_xmm;
16409       break;
16410     case 256:
16411       names = names_ymm;
16412       break;
16413     default:
16414       abort ();
16415     }
16416   oappend (names[reg]);
16417 }
16418
16419 static void
16420 OP_XMM_VexW (int bytemode, int sizeflag)
16421 {
16422   /* Turn off the REX.W bit since it is used for swapping operands
16423      now.  */
16424   rex &= ~REX_W;
16425   OP_XMM (bytemode, sizeflag);
16426 }
16427
16428 static void
16429 OP_EX_Vex (int bytemode, int sizeflag)
16430 {
16431   if (modrm.mod != 3)
16432     {
16433       if (vex.register_specifier != 0)
16434         BadOp ();
16435       need_vex_reg = 0;
16436     }
16437   OP_EX (bytemode, sizeflag);
16438 }
16439
16440 static void
16441 OP_XMM_Vex (int bytemode, int sizeflag)
16442 {
16443   if (modrm.mod != 3)
16444     {
16445       if (vex.register_specifier != 0)
16446         BadOp ();
16447       need_vex_reg = 0;
16448     }
16449   OP_XMM (bytemode, sizeflag);
16450 }
16451
16452 static void
16453 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16454 {
16455   switch (vex.length)
16456     {
16457     case 128:
16458       mnemonicendp = stpcpy (obuf, "vzeroupper");
16459       break;
16460     case 256:
16461       mnemonicendp = stpcpy (obuf, "vzeroall");
16462       break;
16463     default:
16464       abort ();
16465     }
16466 }
16467
16468 static struct op vex_cmp_op[] =
16469 {
16470   { STRING_COMMA_LEN ("eq") },
16471   { STRING_COMMA_LEN ("lt") },
16472   { STRING_COMMA_LEN ("le") },
16473   { STRING_COMMA_LEN ("unord") },
16474   { STRING_COMMA_LEN ("neq") },
16475   { STRING_COMMA_LEN ("nlt") },
16476   { STRING_COMMA_LEN ("nle") },
16477   { STRING_COMMA_LEN ("ord") },
16478   { STRING_COMMA_LEN ("eq_uq") },
16479   { STRING_COMMA_LEN ("nge") },
16480   { STRING_COMMA_LEN ("ngt") },
16481   { STRING_COMMA_LEN ("false") },
16482   { STRING_COMMA_LEN ("neq_oq") },
16483   { STRING_COMMA_LEN ("ge") },
16484   { STRING_COMMA_LEN ("gt") },
16485   { STRING_COMMA_LEN ("true") },
16486   { STRING_COMMA_LEN ("eq_os") },
16487   { STRING_COMMA_LEN ("lt_oq") },
16488   { STRING_COMMA_LEN ("le_oq") },
16489   { STRING_COMMA_LEN ("unord_s") },
16490   { STRING_COMMA_LEN ("neq_us") },
16491   { STRING_COMMA_LEN ("nlt_uq") },
16492   { STRING_COMMA_LEN ("nle_uq") },
16493   { STRING_COMMA_LEN ("ord_s") },
16494   { STRING_COMMA_LEN ("eq_us") },
16495   { STRING_COMMA_LEN ("nge_uq") },
16496   { STRING_COMMA_LEN ("ngt_uq") },
16497   { STRING_COMMA_LEN ("false_os") },
16498   { STRING_COMMA_LEN ("neq_os") },
16499   { STRING_COMMA_LEN ("ge_oq") },
16500   { STRING_COMMA_LEN ("gt_oq") },
16501   { STRING_COMMA_LEN ("true_us") },
16502 };
16503
16504 static void
16505 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16506 {
16507   unsigned int cmp_type;
16508
16509   FETCH_DATA (the_info, codep + 1);
16510   cmp_type = *codep++ & 0xff;
16511   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16512     {
16513       char suffix [3];
16514       char *p = mnemonicendp - 2;
16515       suffix[0] = p[0];
16516       suffix[1] = p[1];
16517       suffix[2] = '\0';
16518       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16519       mnemonicendp += vex_cmp_op[cmp_type].len;
16520     }
16521   else
16522     {
16523       /* We have a reserved extension byte.  Output it directly.  */
16524       scratchbuf[0] = '$';
16525       print_operand_value (scratchbuf + 1, 1, cmp_type);
16526       oappend_maybe_intel (scratchbuf);
16527       scratchbuf[0] = '\0';
16528     }
16529 }
16530
16531 static void
16532 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16533              int sizeflag ATTRIBUTE_UNUSED)
16534 {
16535   unsigned int cmp_type;
16536
16537   if (!vex.evex)
16538     abort ();
16539
16540   FETCH_DATA (the_info, codep + 1);
16541   cmp_type = *codep++ & 0xff;
16542   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16543      If it's the case, print suffix, otherwise - print the immediate.  */
16544   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16545       && cmp_type != 3
16546       && cmp_type != 7)
16547     {
16548       char suffix [3];
16549       char *p = mnemonicendp - 2;
16550
16551       /* vpcmp* can have both one- and two-lettered suffix.  */
16552       if (p[0] == 'p')
16553         {
16554           p++;
16555           suffix[0] = p[0];
16556           suffix[1] = '\0';
16557         }
16558       else
16559         {
16560           suffix[0] = p[0];
16561           suffix[1] = p[1];
16562           suffix[2] = '\0';
16563         }
16564
16565       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16566       mnemonicendp += simd_cmp_op[cmp_type].len;
16567     }
16568   else
16569     {
16570       /* We have a reserved extension byte.  Output it directly.  */
16571       scratchbuf[0] = '$';
16572       print_operand_value (scratchbuf + 1, 1, cmp_type);
16573       oappend_maybe_intel (scratchbuf);
16574       scratchbuf[0] = '\0';
16575     }
16576 }
16577
16578 static const struct op pclmul_op[] =
16579 {
16580   { STRING_COMMA_LEN ("lql") },
16581   { STRING_COMMA_LEN ("hql") },
16582   { STRING_COMMA_LEN ("lqh") },
16583   { STRING_COMMA_LEN ("hqh") }
16584 };
16585
16586 static void
16587 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16588               int sizeflag ATTRIBUTE_UNUSED)
16589 {
16590   unsigned int pclmul_type;
16591
16592   FETCH_DATA (the_info, codep + 1);
16593   pclmul_type = *codep++ & 0xff;
16594   switch (pclmul_type)
16595     {
16596     case 0x10:
16597       pclmul_type = 2;
16598       break;
16599     case 0x11:
16600       pclmul_type = 3;
16601       break;
16602     default:
16603       break;
16604     }
16605   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16606     {
16607       char suffix [4];
16608       char *p = mnemonicendp - 3;
16609       suffix[0] = p[0];
16610       suffix[1] = p[1];
16611       suffix[2] = p[2];
16612       suffix[3] = '\0';
16613       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16614       mnemonicendp += pclmul_op[pclmul_type].len;
16615     }
16616   else
16617     {
16618       /* We have a reserved extension byte.  Output it directly.  */
16619       scratchbuf[0] = '$';
16620       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16621       oappend_maybe_intel (scratchbuf);
16622       scratchbuf[0] = '\0';
16623     }
16624 }
16625
16626 static void
16627 MOVBE_Fixup (int bytemode, int sizeflag)
16628 {
16629   /* Add proper suffix to "movbe".  */
16630   char *p = mnemonicendp;
16631
16632   switch (bytemode)
16633     {
16634     case v_mode:
16635       if (intel_syntax)
16636         goto skip;
16637
16638       USED_REX (REX_W);
16639       if (sizeflag & SUFFIX_ALWAYS)
16640         {
16641           if (rex & REX_W)
16642             *p++ = 'q';
16643           else
16644             {
16645               if (sizeflag & DFLAG)
16646                 *p++ = 'l';
16647               else
16648                 *p++ = 'w';
16649               used_prefixes |= (prefixes & PREFIX_DATA);
16650             }
16651         }
16652       break;
16653     default:
16654       oappend (INTERNAL_DISASSEMBLER_ERROR);
16655       break;
16656     }
16657   mnemonicendp = p;
16658   *p = '\0';
16659
16660 skip:
16661   OP_M (bytemode, sizeflag);
16662 }
16663
16664 static void
16665 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16666 {
16667   int reg;
16668   const char **names;
16669
16670   /* Skip mod/rm byte.  */
16671   MODRM_CHECK;
16672   codep++;
16673
16674   if (vex.w)
16675     names = names64;
16676   else
16677     names = names32;
16678
16679   reg = modrm.rm;
16680   USED_REX (REX_B);
16681   if (rex & REX_B)
16682     reg += 8;
16683
16684   oappend (names[reg]);
16685 }
16686
16687 static void
16688 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16689 {
16690   const char **names;
16691
16692   if (vex.w)
16693     names = names64;
16694   else
16695     names = names32;
16696
16697   oappend (names[vex.register_specifier]);
16698 }
16699
16700 static void
16701 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16702 {
16703   if (!vex.evex
16704       || bytemode != mask_mode)
16705     abort ();
16706
16707   USED_REX (REX_R);
16708   if ((rex & REX_R) != 0 || !vex.r)
16709     {
16710       BadOp ();
16711       return;
16712     }
16713
16714   oappend (names_mask [modrm.reg]);
16715 }
16716
16717 static void
16718 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16719 {
16720   if (!vex.evex
16721       || (bytemode != evex_rounding_mode
16722           && bytemode != evex_sae_mode))
16723     abort ();
16724   if (modrm.mod == 3 && vex.b)
16725     switch (bytemode)
16726       {
16727       case evex_rounding_mode:
16728         oappend (names_rounding[vex.ll]);
16729         break;
16730       case evex_sae_mode:
16731         oappend ("{sae}");
16732         break;
16733       default:
16734         break;
16735       }
16736 }