opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121
 122 static void MOVBE_Fixup (int, int);
 123 static void MOVSXD_Fixup (int, int);
 124
 125 static void OP_Mask (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   OPCODES_SIGJMP_BUF bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       OPCODES_SIGLONGJMP (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 /* Possible values for prefix requirement.  */
 222 #define PREFIX_IGNORED_SHIFT    16
 223 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 224 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 225 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 226 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 228
 229 /* Opcode prefixes.  */
 230 #define PREFIX_OPCODE           (PREFIX_REPZ \
 231                                  | PREFIX_REPNZ \
 232                                  | PREFIX_DATA)
 233
 234 /* Prefixes ignored.  */
 235 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 236                                  | PREFIX_IGNORED_REPNZ \
 237                                  | PREFIX_IGNORED_DATA)
 238
 239 #define XX { NULL, 0 }
 240 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 241
 242 #define Eb { OP_E, b_mode }
 243 #define Ebnd { OP_E, bnd_mode }
 244 #define EbS { OP_E, b_swap_mode }
 245 #define EbndS { OP_E, bnd_swap_mode }
 246 #define Ev { OP_E, v_mode }
 247 #define Eva { OP_E, va_mode }
 248 #define Ev_bnd { OP_E, v_bnd_mode }
 249 #define EvS { OP_E, v_swap_mode }
 250 #define Ed { OP_E, d_mode }
 251 #define Edq { OP_E, dq_mode }
 252 #define Edqw { OP_E, dqw_mode }
 253 #define Edqb { OP_E, dqb_mode }
 254 #define Edb { OP_E, db_mode }
 255 #define Edw { OP_E, dw_mode }
 256 #define Edqd { OP_E, dqd_mode }
 257 #define Eq { OP_E, q_mode }
 258 #define indirEv { OP_indirE, indir_v_mode }
 259 #define indirEp { OP_indirE, f_mode }
 260 #define stackEv { OP_E, stack_v_mode }
 261 #define Em { OP_E, m_mode }
 262 #define Ew { OP_E, w_mode }
 263 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 264 #define Ma { OP_M, a_mode }
 265 #define Mb { OP_M, b_mode }
 266 #define Md { OP_M, d_mode }
 267 #define Mo { OP_M, o_mode }
 268 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 269 #define Mq { OP_M, q_mode }
 270 #define Mv_bnd { OP_M, v_bndmk_mode }
 271 #define Mx { OP_M, x_mode }
 272 #define Mxmm { OP_M, xmm_mode }
 273 #define Gb { OP_G, b_mode }
 274 #define Gbnd { OP_G, bnd_mode }
 275 #define Gv { OP_G, v_mode }
 276 #define Gd { OP_G, d_mode }
 277 #define Gdq { OP_G, dq_mode }
 278 #define Gm { OP_G, m_mode }
 279 #define Gva { OP_G, va_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iv64 { OP_I64, v_mode }
 290 #define Id { OP_I, d_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Jdqw { OP_J, dqw_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define AL { OP_IMREG, al_reg }
 330 #define CL { OP_IMREG, cl_reg }
 331 #define zAX { OP_IMREG, z_mode_ax_reg }
 332 #define indirDX { OP_IMREG, indir_dx_reg }
 333
 334 #define Sw { OP_SEG, w_mode }
 335 #define Sv { OP_SEG, v_mode }
 336 #define Ap { OP_DIR, 0 }
 337 #define Ob { OP_OFF64, b_mode }
 338 #define Ov { OP_OFF64, v_mode }
 339 #define Xb { OP_DSreg, eSI_reg }
 340 #define Xv { OP_DSreg, eSI_reg }
 341 #define Xz { OP_DSreg, eSI_reg }
 342 #define Yb { OP_ESreg, eDI_reg }
 343 #define Yv { OP_ESreg, eDI_reg }
 344 #define DSBX { OP_DSreg, eBX_reg }
 345
 346 #define es { OP_REG, es_reg }
 347 #define ss { OP_REG, ss_reg }
 348 #define cs { OP_REG, cs_reg }
 349 #define ds { OP_REG, ds_reg }
 350 #define fs { OP_REG, fs_reg }
 351 #define gs { OP_REG, gs_reg }
 352
 353 #define MX { OP_MMX, 0 }
 354 #define XM { OP_XMM, 0 }
 355 #define XMScalar { OP_XMM, scalar_mode }
 356 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 357 #define XMM { OP_XMM, xmm_mode }
 358 #define TMM { OP_XMM, tmm_mode }
 359 #define XMxmmq { OP_XMM, xmmq_mode }
 360 #define EM { OP_EM, v_mode }
 361 #define EMS { OP_EM, v_swap_mode }
 362 #define EMd { OP_EM, d_mode }
 363 #define EMx { OP_EM, x_mode }
 364 #define EXbScalar { OP_EX, b_scalar_mode }
 365 #define EXw { OP_EX, w_mode }
 366 #define EXwScalar { OP_EX, w_scalar_mode }
 367 #define EXd { OP_EX, d_mode }
 368 #define EXdS { OP_EX, d_swap_mode }
 369 #define EXq { OP_EX, q_mode }
 370 #define EXqS { OP_EX, q_swap_mode }
 371 #define EXx { OP_EX, x_mode }
 372 #define EXxS { OP_EX, x_swap_mode }
 373 #define EXxmm { OP_EX, xmm_mode }
 374 #define EXymm { OP_EX, ymm_mode }
 375 #define EXtmm { OP_EX, tmm_mode }
 376 #define EXxmmq { OP_EX, xmmq_mode }
 377 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 378 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 379 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 380 #define EXxmm_md { OP_EX, xmm_md_mode }
 381 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 382 #define EXxmmdw { OP_EX, xmmdw_mode }
 383 #define EXxmmqd { OP_EX, xmmqd_mode }
 384 #define EXymmq { OP_EX, ymmq_mode }
 385 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 386 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 387 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 388 #define MS { OP_MS, v_mode }
 389 #define XS { OP_XS, v_mode }
 390 #define EMCq { OP_EMC, q_mode }
 391 #define MXC { OP_MXC, 0 }
 392 #define OPSUF { OP_3DNowSuffix, 0 }
 393 #define SEP { SEP_Fixup, 0 }
 394 #define CMP { CMP_Fixup, 0 }
 395 #define XMM0 { XMM_Fixup, 0 }
 396 #define FXSAVE { FXSAVE_Fixup, 0 }
 397
 398 #define Vex { OP_VEX, vex_mode }
 399 #define VexW { OP_VexW, vex_mode }
 400 #define VexScalar { OP_VEX, vex_scalar_mode }
 401 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 402 #define Vex128 { OP_VEX, vex128_mode }
 403 #define Vex256 { OP_VEX, vex256_mode }
 404 #define VexGdq { OP_VEX, dq_mode }
 405 #define VexTmm { OP_VEX, tmm_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 408 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 409 #define XMVexI4 { OP_REG_VexI4, x_mode }
 410 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 411 #define VexI4 { OP_VexI4, 0 }
 412 #define PCLMUL { PCLMUL_Fixup, 0 }
 413 #define VCMP { VCMP_Fixup, 0 }
 414 #define VPCMP { VPCMP_Fixup, 0 }
 415 #define VPCOM { VPCOM_Fixup, 0 }
 416
 417 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 418 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 419 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 420
 421 #define XMask { OP_Mask, mask_mode }
 422 #define MaskG { OP_G, mask_mode }
 423 #define MaskE { OP_E, mask_mode }
 424 #define MaskBDE { OP_E, mask_bd_mode }
 425 #define MaskR { OP_R, mask_mode }
 426 #define MaskVex { OP_VEX, mask_mode }
 427
 428 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 429 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 430 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 431 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 432
 433 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 434
 435 /* Used handle "rep" prefix for string instructions.  */
 436 #define Xbr { REP_Fixup, eSI_reg }
 437 #define Xvr { REP_Fixup, eSI_reg }
 438 #define Ybr { REP_Fixup, eDI_reg }
 439 #define Yvr { REP_Fixup, eDI_reg }
 440 #define Yzr { REP_Fixup, eDI_reg }
 441 #define indirDXr { REP_Fixup, indir_dx_reg }
 442 #define ALr { REP_Fixup, al_reg }
 443 #define eAXr { REP_Fixup, eAX_reg }
 444
 445 /* Used handle HLE prefix for lockable instructions.  */
 446 #define Ebh1 { HLE_Fixup1, b_mode }
 447 #define Evh1 { HLE_Fixup1, v_mode }
 448 #define Ebh2 { HLE_Fixup2, b_mode }
 449 #define Evh2 { HLE_Fixup2, v_mode }
 450 #define Ebh3 { HLE_Fixup3, b_mode }
 451 #define Evh3 { HLE_Fixup3, v_mode }
 452
 453 #define BND { BND_Fixup, 0 }
 454 #define NOTRACK { NOTRACK_Fixup, 0 }
 455
 456 #define cond_jump_flag { NULL, cond_jump_mode }
 457 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 458
 459 /* bits in sizeflag */
 460 #define SUFFIX_ALWAYS 4
 461 #define AFLAG 2
 462 #define DFLAG 1
 463
 464 enum
 465 {
 466   /* byte operand */
 467   b_mode = 1,
 468   /* byte operand with operand swapped */
 469   b_swap_mode,
 470   /* byte operand, sign extend like 'T' suffix */
 471   b_T_mode,
 472   /* operand size depends on prefixes */
 473   v_mode,
 474   /* operand size depends on prefixes with operand swapped */
 475   v_swap_mode,
 476   /* operand size depends on address prefix */
 477   va_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* 16-byte XMM, word, double word or quad word operand.  */
 517   xmmdw_mode,
 518   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 519   xmmqd_mode,
 520   /* 32-byte YMM operand */
 521   ymm_mode,
 522   /* quad word, ymmword or zmmword memory operand.  */
 523   ymmq_mode,
 524   /* 32-byte YMM or 16-byte word operand */
 525   ymmxmm_mode,
 526   /* TMM operand */
 527   tmm_mode,
 528   /* d_mode in 32bit, q_mode in 64bit mode.  */
 529   m_mode,
 530   /* pair of v_mode operands */
 531   a_mode,
 532   cond_jump_mode,
 533   loop_jcxz_mode,
 534   movsxd_mode,
 535   v_bnd_mode,
 536   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 537   v_bndmk_mode,
 538   /* operand size depends on REX prefixes.  */
 539   dq_mode,
 540   /* registers like dq_mode, memory like w_mode, displacements like
 541      v_mode without considering Intel64 ISA.  */
 542   dqw_mode,
 543   /* bounds operand */
 544   bnd_mode,
 545   /* bounds operand with operand swapped */
 546   bnd_swap_mode,
 547   /* 4- or 6-byte pointer operand */
 548   f_mode,
 549   const_1_mode,
 550   /* v_mode for indirect branch opcodes.  */
 551   indir_v_mode,
 552   /* v_mode for stack-related opcodes.  */
 553   stack_v_mode,
 554   /* non-quad operand size depends on prefixes */
 555   z_mode,
 556   /* 16-byte operand */
 557   o_mode,
 558   /* registers like dq_mode, memory like b_mode.  */
 559   dqb_mode,
 560   /* registers like d_mode, memory like b_mode.  */
 561   db_mode,
 562   /* registers like d_mode, memory like w_mode.  */
 563   dw_mode,
 564   /* registers like dq_mode, memory like d_mode.  */
 565   dqd_mode,
 566   /* normal vex mode */
 567   vex_mode,
 568   /* 128bit vex mode */
 569   vex128_mode,
 570   /* 256bit vex mode */
 571   vex256_mode,
 572
 573   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 574   vex_vsib_d_w_dq_mode,
 575   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 576   vex_vsib_d_w_d_mode,
 577   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 578   vex_vsib_q_w_dq_mode,
 579   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 580   vex_vsib_q_w_d_mode,
 581   /* mandatory non-vector SIB.  */
 582   vex_sibmem_mode,
 583
 584   /* scalar, ignore vector length.  */
 585   scalar_mode,
 586   /* like b_mode, ignore vector length.  */
 587   b_scalar_mode,
 588   /* like w_mode, ignore vector length.  */
 589   w_scalar_mode,
 590   /* like d_swap_mode, ignore vector length.  */
 591   d_scalar_swap_mode,
 592   /* like q_swap_mode, ignore vector length.  */
 593   q_scalar_swap_mode,
 594   /* like vex_mode, ignore vector length.  */
 595   vex_scalar_mode,
 596   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 597   vex_scalar_w_dq_mode,
 598
 599   /* Static rounding.  */
 600   evex_rounding_mode,
 601   /* Static rounding, 64-bit mode only.  */
 602   evex_rounding_64_mode,
 603   /* Supress all exceptions.  */
 604   evex_sae_mode,
 605
 606   /* Mask register operand.  */
 607   mask_mode,
 608   /* Mask register operand.  */
 609   mask_bd_mode,
 610
 611   es_reg,
 612   cs_reg,
 613   ss_reg,
 614   ds_reg,
 615   fs_reg,
 616   gs_reg,
 617
 618   eAX_reg,
 619   eCX_reg,
 620   eDX_reg,
 621   eBX_reg,
 622   eSP_reg,
 623   eBP_reg,
 624   eSI_reg,
 625   eDI_reg,
 626
 627   al_reg,
 628   cl_reg,
 629   dl_reg,
 630   bl_reg,
 631   ah_reg,
 632   ch_reg,
 633   dh_reg,
 634   bh_reg,
 635
 636   ax_reg,
 637   cx_reg,
 638   dx_reg,
 639   bx_reg,
 640   sp_reg,
 641   bp_reg,
 642   si_reg,
 643   di_reg,
 644
 645   rAX_reg,
 646   rCX_reg,
 647   rDX_reg,
 648   rBX_reg,
 649   rSP_reg,
 650   rBP_reg,
 651   rSI_reg,
 652   rDI_reg,
 653
 654   z_mode_ax_reg,
 655   indir_dx_reg
 656 };
 657
 658 enum
 659 {
 660   FLOATCODE = 1,
 661   USE_REG_TABLE,
 662   USE_MOD_TABLE,
 663   USE_RM_TABLE,
 664   USE_PREFIX_TABLE,
 665   USE_X86_64_TABLE,
 666   USE_3BYTE_TABLE,
 667   USE_XOP_8F_TABLE,
 668   USE_VEX_C4_TABLE,
 669   USE_VEX_C5_TABLE,
 670   USE_VEX_LEN_TABLE,
 671   USE_VEX_W_TABLE,
 672   USE_EVEX_TABLE,
 673   USE_EVEX_LEN_TABLE
 674 };
 675
 676 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 677
 678 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 679 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 680 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 681 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 682 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 683 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 684 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 685 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 686 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 687 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 688 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 689 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 690 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 691 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 692 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 693 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 694
 695 enum
 696 {
 697   REG_80 = 0,
 698   REG_81,
 699   REG_83,
 700   REG_8F,
 701   REG_C0,
 702   REG_C1,
 703   REG_C6,
 704   REG_C7,
 705   REG_D0,
 706   REG_D1,
 707   REG_D2,
 708   REG_D3,
 709   REG_F6,
 710   REG_F7,
 711   REG_FE,
 712   REG_FF,
 713   REG_0F00,
 714   REG_0F01,
 715   REG_0F0D,
 716   REG_0F18,
 717   REG_0F1C_P_0_MOD_0,
 718   REG_0F1E_P_1_MOD_3,
 719   REG_0F71,
 720   REG_0F72,
 721   REG_0F73,
 722   REG_0FA6,
 723   REG_0FA7,
 724   REG_0FAE,
 725   REG_0FBA,
 726   REG_0FC7,
 727   REG_VEX_0F71,
 728   REG_VEX_0F72,
 729   REG_VEX_0F73,
 730   REG_VEX_0FAE,
 731   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 732   REG_VEX_0F38F3,
 733
 734   REG_0FXOP_09_01_L_0,
 735   REG_0FXOP_09_02_L_0,
 736   REG_0FXOP_09_12_M_1_L_0,
 737   REG_0FXOP_0A_12_L_0,
 738
 739   REG_EVEX_0F71,
 740   REG_EVEX_0F72,
 741   REG_EVEX_0F73,
 742   REG_EVEX_0F38C6,
 743   REG_EVEX_0F38C7
 744 };
 745
 746 enum
 747 {
 748   MOD_8D = 0,
 749   MOD_C6_REG_7,
 750   MOD_C7_REG_7,
 751   MOD_FF_REG_3,
 752   MOD_FF_REG_5,
 753   MOD_0F01_REG_0,
 754   MOD_0F01_REG_1,
 755   MOD_0F01_REG_2,
 756   MOD_0F01_REG_3,
 757   MOD_0F01_REG_5,
 758   MOD_0F01_REG_7,
 759   MOD_0F12_PREFIX_0,
 760   MOD_0F12_PREFIX_2,
 761   MOD_0F13,
 762   MOD_0F16_PREFIX_0,
 763   MOD_0F16_PREFIX_2,
 764   MOD_0F17,
 765   MOD_0F18_REG_0,
 766   MOD_0F18_REG_1,
 767   MOD_0F18_REG_2,
 768   MOD_0F18_REG_3,
 769   MOD_0F18_REG_4,
 770   MOD_0F18_REG_5,
 771   MOD_0F18_REG_6,
 772   MOD_0F18_REG_7,
 773   MOD_0F1A_PREFIX_0,
 774   MOD_0F1B_PREFIX_0,
 775   MOD_0F1B_PREFIX_1,
 776   MOD_0F1C_PREFIX_0,
 777   MOD_0F1E_PREFIX_1,
 778   MOD_0F24,
 779   MOD_0F26,
 780   MOD_0F2B_PREFIX_0,
 781   MOD_0F2B_PREFIX_1,
 782   MOD_0F2B_PREFIX_2,
 783   MOD_0F2B_PREFIX_3,
 784   MOD_0F50,
 785   MOD_0F71_REG_2,
 786   MOD_0F71_REG_4,
 787   MOD_0F71_REG_6,
 788   MOD_0F72_REG_2,
 789   MOD_0F72_REG_4,
 790   MOD_0F72_REG_6,
 791   MOD_0F73_REG_2,
 792   MOD_0F73_REG_3,
 793   MOD_0F73_REG_6,
 794   MOD_0F73_REG_7,
 795   MOD_0FAE_REG_0,
 796   MOD_0FAE_REG_1,
 797   MOD_0FAE_REG_2,
 798   MOD_0FAE_REG_3,
 799   MOD_0FAE_REG_4,
 800   MOD_0FAE_REG_5,
 801   MOD_0FAE_REG_6,
 802   MOD_0FAE_REG_7,
 803   MOD_0FB2,
 804   MOD_0FB4,
 805   MOD_0FB5,
 806   MOD_0FC3,
 807   MOD_0FC7_REG_3,
 808   MOD_0FC7_REG_4,
 809   MOD_0FC7_REG_5,
 810   MOD_0FC7_REG_6,
 811   MOD_0FC7_REG_7,
 812   MOD_0FD7,
 813   MOD_0FE7_PREFIX_2,
 814   MOD_0FF0_PREFIX_3,
 815   MOD_0F382A_PREFIX_2,
 816   MOD_VEX_0F3849_X86_64_P_0_W_0,
 817   MOD_VEX_0F3849_X86_64_P_2_W_0,
 818   MOD_VEX_0F3849_X86_64_P_3_W_0,
 819   MOD_VEX_0F384B_X86_64_P_1_W_0,
 820   MOD_VEX_0F384B_X86_64_P_2_W_0,
 821   MOD_VEX_0F384B_X86_64_P_3_W_0,
 822   MOD_VEX_0F385C_X86_64_P_1_W_0,
 823   MOD_VEX_0F385E_X86_64_P_0_W_0,
 824   MOD_VEX_0F385E_X86_64_P_1_W_0,
 825   MOD_VEX_0F385E_X86_64_P_2_W_0,
 826   MOD_VEX_0F385E_X86_64_P_3_W_0,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_0F38F8_PREFIX_1,
 830   MOD_0F38F8_PREFIX_2,
 831   MOD_0F38F8_PREFIX_3,
 832   MOD_0F38F9_PREFIX_0,
 833   MOD_62_32BIT,
 834   MOD_C4_32BIT,
 835   MOD_C5_32BIT,
 836   MOD_VEX_0F12_PREFIX_0,
 837   MOD_VEX_0F12_PREFIX_2,
 838   MOD_VEX_0F13,
 839   MOD_VEX_0F16_PREFIX_0,
 840   MOD_VEX_0F16_PREFIX_2,
 841   MOD_VEX_0F17,
 842   MOD_VEX_0F2B,
 843   MOD_VEX_W_0_0F41_P_0_LEN_1,
 844   MOD_VEX_W_1_0F41_P_0_LEN_1,
 845   MOD_VEX_W_0_0F41_P_2_LEN_1,
 846   MOD_VEX_W_1_0F41_P_2_LEN_1,
 847   MOD_VEX_W_0_0F42_P_0_LEN_1,
 848   MOD_VEX_W_1_0F42_P_0_LEN_1,
 849   MOD_VEX_W_0_0F42_P_2_LEN_1,
 850   MOD_VEX_W_1_0F42_P_2_LEN_1,
 851   MOD_VEX_W_0_0F44_P_0_LEN_1,
 852   MOD_VEX_W_1_0F44_P_0_LEN_1,
 853   MOD_VEX_W_0_0F44_P_2_LEN_1,
 854   MOD_VEX_W_1_0F44_P_2_LEN_1,
 855   MOD_VEX_W_0_0F45_P_0_LEN_1,
 856   MOD_VEX_W_1_0F45_P_0_LEN_1,
 857   MOD_VEX_W_0_0F45_P_2_LEN_1,
 858   MOD_VEX_W_1_0F45_P_2_LEN_1,
 859   MOD_VEX_W_0_0F46_P_0_LEN_1,
 860   MOD_VEX_W_1_0F46_P_0_LEN_1,
 861   MOD_VEX_W_0_0F46_P_2_LEN_1,
 862   MOD_VEX_W_1_0F46_P_2_LEN_1,
 863   MOD_VEX_W_0_0F47_P_0_LEN_1,
 864   MOD_VEX_W_1_0F47_P_0_LEN_1,
 865   MOD_VEX_W_0_0F47_P_2_LEN_1,
 866   MOD_VEX_W_1_0F47_P_2_LEN_1,
 867   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 868   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 871   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 872   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 874   MOD_VEX_0F50,
 875   MOD_VEX_0F71_REG_2,
 876   MOD_VEX_0F71_REG_4,
 877   MOD_VEX_0F71_REG_6,
 878   MOD_VEX_0F72_REG_2,
 879   MOD_VEX_0F72_REG_4,
 880   MOD_VEX_0F72_REG_6,
 881   MOD_VEX_0F73_REG_2,
 882   MOD_VEX_0F73_REG_3,
 883   MOD_VEX_0F73_REG_6,
 884   MOD_VEX_0F73_REG_7,
 885   MOD_VEX_W_0_0F91_P_0_LEN_0,
 886   MOD_VEX_W_1_0F91_P_0_LEN_0,
 887   MOD_VEX_W_0_0F91_P_2_LEN_0,
 888   MOD_VEX_W_1_0F91_P_2_LEN_0,
 889   MOD_VEX_W_0_0F92_P_0_LEN_0,
 890   MOD_VEX_W_0_0F92_P_2_LEN_0,
 891   MOD_VEX_0F92_P_3_LEN_0,
 892   MOD_VEX_W_0_0F93_P_0_LEN_0,
 893   MOD_VEX_W_0_0F93_P_2_LEN_0,
 894   MOD_VEX_0F93_P_3_LEN_0,
 895   MOD_VEX_W_0_0F98_P_0_LEN_0,
 896   MOD_VEX_W_1_0F98_P_0_LEN_0,
 897   MOD_VEX_W_0_0F98_P_2_LEN_0,
 898   MOD_VEX_W_1_0F98_P_2_LEN_0,
 899   MOD_VEX_W_0_0F99_P_0_LEN_0,
 900   MOD_VEX_W_1_0F99_P_0_LEN_0,
 901   MOD_VEX_W_0_0F99_P_2_LEN_0,
 902   MOD_VEX_W_1_0F99_P_2_LEN_0,
 903   MOD_VEX_0FAE_REG_2,
 904   MOD_VEX_0FAE_REG_3,
 905   MOD_VEX_0FD7_PREFIX_2,
 906   MOD_VEX_0FE7_PREFIX_2,
 907   MOD_VEX_0FF0_PREFIX_3,
 908   MOD_VEX_0F381A_PREFIX_2,
 909   MOD_VEX_0F382A_PREFIX_2,
 910   MOD_VEX_0F382C_PREFIX_2,
 911   MOD_VEX_0F382D_PREFIX_2,
 912   MOD_VEX_0F382E_PREFIX_2,
 913   MOD_VEX_0F382F_PREFIX_2,
 914   MOD_VEX_0F385A_PREFIX_2,
 915   MOD_VEX_0F388C_PREFIX_2,
 916   MOD_VEX_0F388E_PREFIX_2,
 917   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 925
 926   MOD_VEX_0FXOP_09_12,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F381A_P_2_W_0,
 936   MOD_EVEX_0F381A_P_2_W_1,
 937   MOD_EVEX_0F381B_P_2_W_0,
 938   MOD_EVEX_0F381B_P_2_W_1,
 939   MOD_EVEX_0F385A_P_2_W_0,
 940   MOD_EVEX_0F385A_P_2_W_1,
 941   MOD_EVEX_0F385B_P_2_W_0,
 942   MOD_EVEX_0F385B_P_2_W_1,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5_MOD_3,
 962   RM_0F01_REG_7_MOD_3,
 963   RM_0F1E_P_1_MOD_3_REG_7,
 964   RM_0FAE_REG_6_MOD_3_P_0,
 965   RM_0FAE_REG_7_MOD_3,
 966   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 967 };
 968
 969 enum
 970 {
 971   PREFIX_90 = 0,
 972   PREFIX_0F01_REG_3_RM_1,
 973   PREFIX_0F01_REG_5_MOD_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_0,
 975   PREFIX_0F01_REG_5_MOD_3_RM_1,
 976   PREFIX_0F01_REG_5_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_2,
 978   PREFIX_0F01_REG_7_MOD_3_RM_3,
 979   PREFIX_0F09,
 980   PREFIX_0F10,
 981   PREFIX_0F11,
 982   PREFIX_0F12,
 983   PREFIX_0F16,
 984   PREFIX_0F1A,
 985   PREFIX_0F1B,
 986   PREFIX_0F1C,
 987   PREFIX_0F1E,
 988   PREFIX_0F2A,
 989   PREFIX_0F2B,
 990   PREFIX_0F2C,
 991   PREFIX_0F2D,
 992   PREFIX_0F2E,
 993   PREFIX_0F2F,
 994   PREFIX_0F51,
 995   PREFIX_0F52,
 996   PREFIX_0F53,
 997   PREFIX_0F58,
 998   PREFIX_0F59,
 999   PREFIX_0F5A,
1000   PREFIX_0F5B,
1001   PREFIX_0F5C,
1002   PREFIX_0F5D,
1003   PREFIX_0F5E,
1004   PREFIX_0F5F,
1005   PREFIX_0F60,
1006   PREFIX_0F61,
1007   PREFIX_0F62,
1008   PREFIX_0F6C,
1009   PREFIX_0F6D,
1010   PREFIX_0F6F,
1011   PREFIX_0F70,
1012   PREFIX_0F73_REG_3,
1013   PREFIX_0F73_REG_7,
1014   PREFIX_0F78,
1015   PREFIX_0F79,
1016   PREFIX_0F7C,
1017   PREFIX_0F7D,
1018   PREFIX_0F7E,
1019   PREFIX_0F7F,
1020   PREFIX_0FAE_REG_0_MOD_3,
1021   PREFIX_0FAE_REG_1_MOD_3,
1022   PREFIX_0FAE_REG_2_MOD_3,
1023   PREFIX_0FAE_REG_3_MOD_3,
1024   PREFIX_0FAE_REG_4_MOD_0,
1025   PREFIX_0FAE_REG_4_MOD_3,
1026   PREFIX_0FAE_REG_5_MOD_0,
1027   PREFIX_0FAE_REG_5_MOD_3,
1028   PREFIX_0FAE_REG_6_MOD_0,
1029   PREFIX_0FAE_REG_6_MOD_3,
1030   PREFIX_0FAE_REG_7_MOD_0,
1031   PREFIX_0FB8,
1032   PREFIX_0FBC,
1033   PREFIX_0FBD,
1034   PREFIX_0FC2,
1035   PREFIX_0FC3_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_0,
1037   PREFIX_0FC7_REG_6_MOD_3,
1038   PREFIX_0FC7_REG_7_MOD_3,
1039   PREFIX_0FD0,
1040   PREFIX_0FD6,
1041   PREFIX_0FE6,
1042   PREFIX_0FE7,
1043   PREFIX_0FF0,
1044   PREFIX_0FF7,
1045   PREFIX_0F3810,
1046   PREFIX_0F3814,
1047   PREFIX_0F3815,
1048   PREFIX_0F3817,
1049   PREFIX_0F3820,
1050   PREFIX_0F3821,
1051   PREFIX_0F3822,
1052   PREFIX_0F3823,
1053   PREFIX_0F3824,
1054   PREFIX_0F3825,
1055   PREFIX_0F3828,
1056   PREFIX_0F3829,
1057   PREFIX_0F382A,
1058   PREFIX_0F382B,
1059   PREFIX_0F3830,
1060   PREFIX_0F3831,
1061   PREFIX_0F3832,
1062   PREFIX_0F3833,
1063   PREFIX_0F3834,
1064   PREFIX_0F3835,
1065   PREFIX_0F3837,
1066   PREFIX_0F3838,
1067   PREFIX_0F3839,
1068   PREFIX_0F383A,
1069   PREFIX_0F383B,
1070   PREFIX_0F383C,
1071   PREFIX_0F383D,
1072   PREFIX_0F383E,
1073   PREFIX_0F383F,
1074   PREFIX_0F3840,
1075   PREFIX_0F3841,
1076   PREFIX_0F3880,
1077   PREFIX_0F3881,
1078   PREFIX_0F3882,
1079   PREFIX_0F38C8,
1080   PREFIX_0F38C9,
1081   PREFIX_0F38CA,
1082   PREFIX_0F38CB,
1083   PREFIX_0F38CC,
1084   PREFIX_0F38CD,
1085   PREFIX_0F38CF,
1086   PREFIX_0F38DB,
1087   PREFIX_0F38DC,
1088   PREFIX_0F38DD,
1089   PREFIX_0F38DE,
1090   PREFIX_0F38DF,
1091   PREFIX_0F38F0,
1092   PREFIX_0F38F1,
1093   PREFIX_0F38F5,
1094   PREFIX_0F38F6,
1095   PREFIX_0F38F8,
1096   PREFIX_0F38F9,
1097   PREFIX_0F3A08,
1098   PREFIX_0F3A09,
1099   PREFIX_0F3A0A,
1100   PREFIX_0F3A0B,
1101   PREFIX_0F3A0C,
1102   PREFIX_0F3A0D,
1103   PREFIX_0F3A0E,
1104   PREFIX_0F3A14,
1105   PREFIX_0F3A15,
1106   PREFIX_0F3A16,
1107   PREFIX_0F3A17,
1108   PREFIX_0F3A20,
1109   PREFIX_0F3A21,
1110   PREFIX_0F3A22,
1111   PREFIX_0F3A40,
1112   PREFIX_0F3A41,
1113   PREFIX_0F3A42,
1114   PREFIX_0F3A44,
1115   PREFIX_0F3A60,
1116   PREFIX_0F3A61,
1117   PREFIX_0F3A62,
1118   PREFIX_0F3A63,
1119   PREFIX_0F3ACC,
1120   PREFIX_0F3ACE,
1121   PREFIX_0F3ACF,
1122   PREFIX_0F3ADF,
1123   PREFIX_VEX_0F10,
1124   PREFIX_VEX_0F11,
1125   PREFIX_VEX_0F12,
1126   PREFIX_VEX_0F16,
1127   PREFIX_VEX_0F2A,
1128   PREFIX_VEX_0F2C,
1129   PREFIX_VEX_0F2D,
1130   PREFIX_VEX_0F2E,
1131   PREFIX_VEX_0F2F,
1132   PREFIX_VEX_0F41,
1133   PREFIX_VEX_0F42,
1134   PREFIX_VEX_0F44,
1135   PREFIX_VEX_0F45,
1136   PREFIX_VEX_0F46,
1137   PREFIX_VEX_0F47,
1138   PREFIX_VEX_0F4A,
1139   PREFIX_VEX_0F4B,
1140   PREFIX_VEX_0F51,
1141   PREFIX_VEX_0F52,
1142   PREFIX_VEX_0F53,
1143   PREFIX_VEX_0F58,
1144   PREFIX_VEX_0F59,
1145   PREFIX_VEX_0F5A,
1146   PREFIX_VEX_0F5B,
1147   PREFIX_VEX_0F5C,
1148   PREFIX_VEX_0F5D,
1149   PREFIX_VEX_0F5E,
1150   PREFIX_VEX_0F5F,
1151   PREFIX_VEX_0F60,
1152   PREFIX_VEX_0F61,
1153   PREFIX_VEX_0F62,
1154   PREFIX_VEX_0F63,
1155   PREFIX_VEX_0F64,
1156   PREFIX_VEX_0F65,
1157   PREFIX_VEX_0F66,
1158   PREFIX_VEX_0F67,
1159   PREFIX_VEX_0F68,
1160   PREFIX_VEX_0F69,
1161   PREFIX_VEX_0F6A,
1162   PREFIX_VEX_0F6B,
1163   PREFIX_VEX_0F6C,
1164   PREFIX_VEX_0F6D,
1165   PREFIX_VEX_0F6E,
1166   PREFIX_VEX_0F6F,
1167   PREFIX_VEX_0F70,
1168   PREFIX_VEX_0F71_REG_2,
1169   PREFIX_VEX_0F71_REG_4,
1170   PREFIX_VEX_0F71_REG_6,
1171   PREFIX_VEX_0F72_REG_2,
1172   PREFIX_VEX_0F72_REG_4,
1173   PREFIX_VEX_0F72_REG_6,
1174   PREFIX_VEX_0F73_REG_2,
1175   PREFIX_VEX_0F73_REG_3,
1176   PREFIX_VEX_0F73_REG_6,
1177   PREFIX_VEX_0F73_REG_7,
1178   PREFIX_VEX_0F74,
1179   PREFIX_VEX_0F75,
1180   PREFIX_VEX_0F76,
1181   PREFIX_VEX_0F77,
1182   PREFIX_VEX_0F7C,
1183   PREFIX_VEX_0F7D,
1184   PREFIX_VEX_0F7E,
1185   PREFIX_VEX_0F7F,
1186   PREFIX_VEX_0F90,
1187   PREFIX_VEX_0F91,
1188   PREFIX_VEX_0F92,
1189   PREFIX_VEX_0F93,
1190   PREFIX_VEX_0F98,
1191   PREFIX_VEX_0F99,
1192   PREFIX_VEX_0FC2,
1193   PREFIX_VEX_0FC4,
1194   PREFIX_VEX_0FC5,
1195   PREFIX_VEX_0FD0,
1196   PREFIX_VEX_0FD1,
1197   PREFIX_VEX_0FD2,
1198   PREFIX_VEX_0FD3,
1199   PREFIX_VEX_0FD4,
1200   PREFIX_VEX_0FD5,
1201   PREFIX_VEX_0FD6,
1202   PREFIX_VEX_0FD7,
1203   PREFIX_VEX_0FD8,
1204   PREFIX_VEX_0FD9,
1205   PREFIX_VEX_0FDA,
1206   PREFIX_VEX_0FDB,
1207   PREFIX_VEX_0FDC,
1208   PREFIX_VEX_0FDD,
1209   PREFIX_VEX_0FDE,
1210   PREFIX_VEX_0FDF,
1211   PREFIX_VEX_0FE0,
1212   PREFIX_VEX_0FE1,
1213   PREFIX_VEX_0FE2,
1214   PREFIX_VEX_0FE3,
1215   PREFIX_VEX_0FE4,
1216   PREFIX_VEX_0FE5,
1217   PREFIX_VEX_0FE6,
1218   PREFIX_VEX_0FE7,
1219   PREFIX_VEX_0FE8,
1220   PREFIX_VEX_0FE9,
1221   PREFIX_VEX_0FEA,
1222   PREFIX_VEX_0FEB,
1223   PREFIX_VEX_0FEC,
1224   PREFIX_VEX_0FED,
1225   PREFIX_VEX_0FEE,
1226   PREFIX_VEX_0FEF,
1227   PREFIX_VEX_0FF0,
1228   PREFIX_VEX_0FF1,
1229   PREFIX_VEX_0FF2,
1230   PREFIX_VEX_0FF3,
1231   PREFIX_VEX_0FF4,
1232   PREFIX_VEX_0FF5,
1233   PREFIX_VEX_0FF6,
1234   PREFIX_VEX_0FF7,
1235   PREFIX_VEX_0FF8,
1236   PREFIX_VEX_0FF9,
1237   PREFIX_VEX_0FFA,
1238   PREFIX_VEX_0FFB,
1239   PREFIX_VEX_0FFC,
1240   PREFIX_VEX_0FFD,
1241   PREFIX_VEX_0FFE,
1242   PREFIX_VEX_0F3800,
1243   PREFIX_VEX_0F3801,
1244   PREFIX_VEX_0F3802,
1245   PREFIX_VEX_0F3803,
1246   PREFIX_VEX_0F3804,
1247   PREFIX_VEX_0F3805,
1248   PREFIX_VEX_0F3806,
1249   PREFIX_VEX_0F3807,
1250   PREFIX_VEX_0F3808,
1251   PREFIX_VEX_0F3809,
1252   PREFIX_VEX_0F380A,
1253   PREFIX_VEX_0F380B,
1254   PREFIX_VEX_0F380C,
1255   PREFIX_VEX_0F380D,
1256   PREFIX_VEX_0F380E,
1257   PREFIX_VEX_0F380F,
1258   PREFIX_VEX_0F3813,
1259   PREFIX_VEX_0F3816,
1260   PREFIX_VEX_0F3817,
1261   PREFIX_VEX_0F3818,
1262   PREFIX_VEX_0F3819,
1263   PREFIX_VEX_0F381A,
1264   PREFIX_VEX_0F381C,
1265   PREFIX_VEX_0F381D,
1266   PREFIX_VEX_0F381E,
1267   PREFIX_VEX_0F3820,
1268   PREFIX_VEX_0F3821,
1269   PREFIX_VEX_0F3822,
1270   PREFIX_VEX_0F3823,
1271   PREFIX_VEX_0F3824,
1272   PREFIX_VEX_0F3825,
1273   PREFIX_VEX_0F3828,
1274   PREFIX_VEX_0F3829,
1275   PREFIX_VEX_0F382A,
1276   PREFIX_VEX_0F382B,
1277   PREFIX_VEX_0F382C,
1278   PREFIX_VEX_0F382D,
1279   PREFIX_VEX_0F382E,
1280   PREFIX_VEX_0F382F,
1281   PREFIX_VEX_0F3830,
1282   PREFIX_VEX_0F3831,
1283   PREFIX_VEX_0F3832,
1284   PREFIX_VEX_0F3833,
1285   PREFIX_VEX_0F3834,
1286   PREFIX_VEX_0F3835,
1287   PREFIX_VEX_0F3836,
1288   PREFIX_VEX_0F3837,
1289   PREFIX_VEX_0F3838,
1290   PREFIX_VEX_0F3839,
1291   PREFIX_VEX_0F383A,
1292   PREFIX_VEX_0F383B,
1293   PREFIX_VEX_0F383C,
1294   PREFIX_VEX_0F383D,
1295   PREFIX_VEX_0F383E,
1296   PREFIX_VEX_0F383F,
1297   PREFIX_VEX_0F3840,
1298   PREFIX_VEX_0F3841,
1299   PREFIX_VEX_0F3845,
1300   PREFIX_VEX_0F3846,
1301   PREFIX_VEX_0F3847,
1302   PREFIX_VEX_0F3849_X86_64,
1303   PREFIX_VEX_0F384B_X86_64,
1304   PREFIX_VEX_0F3858,
1305   PREFIX_VEX_0F3859,
1306   PREFIX_VEX_0F385A,
1307   PREFIX_VEX_0F385C_X86_64,
1308   PREFIX_VEX_0F385E_X86_64,
1309   PREFIX_VEX_0F3878,
1310   PREFIX_VEX_0F3879,
1311   PREFIX_VEX_0F388C,
1312   PREFIX_VEX_0F388E,
1313   PREFIX_VEX_0F3890,
1314   PREFIX_VEX_0F3891,
1315   PREFIX_VEX_0F3892,
1316   PREFIX_VEX_0F3893,
1317   PREFIX_VEX_0F3896,
1318   PREFIX_VEX_0F3897,
1319   PREFIX_VEX_0F3898,
1320   PREFIX_VEX_0F3899,
1321   PREFIX_VEX_0F389A,
1322   PREFIX_VEX_0F389B,
1323   PREFIX_VEX_0F389C,
1324   PREFIX_VEX_0F389D,
1325   PREFIX_VEX_0F389E,
1326   PREFIX_VEX_0F389F,
1327   PREFIX_VEX_0F38A6,
1328   PREFIX_VEX_0F38A7,
1329   PREFIX_VEX_0F38A8,
1330   PREFIX_VEX_0F38A9,
1331   PREFIX_VEX_0F38AA,
1332   PREFIX_VEX_0F38AB,
1333   PREFIX_VEX_0F38AC,
1334   PREFIX_VEX_0F38AD,
1335   PREFIX_VEX_0F38AE,
1336   PREFIX_VEX_0F38AF,
1337   PREFIX_VEX_0F38B6,
1338   PREFIX_VEX_0F38B7,
1339   PREFIX_VEX_0F38B8,
1340   PREFIX_VEX_0F38B9,
1341   PREFIX_VEX_0F38BA,
1342   PREFIX_VEX_0F38BB,
1343   PREFIX_VEX_0F38BC,
1344   PREFIX_VEX_0F38BD,
1345   PREFIX_VEX_0F38BE,
1346   PREFIX_VEX_0F38BF,
1347   PREFIX_VEX_0F38CF,
1348   PREFIX_VEX_0F38DB,
1349   PREFIX_VEX_0F38DC,
1350   PREFIX_VEX_0F38DD,
1351   PREFIX_VEX_0F38DE,
1352   PREFIX_VEX_0F38DF,
1353   PREFIX_VEX_0F38F2,
1354   PREFIX_VEX_0F38F3_REG_1,
1355   PREFIX_VEX_0F38F3_REG_2,
1356   PREFIX_VEX_0F38F3_REG_3,
1357   PREFIX_VEX_0F38F5,
1358   PREFIX_VEX_0F38F6,
1359   PREFIX_VEX_0F38F7,
1360   PREFIX_VEX_0F3A00,
1361   PREFIX_VEX_0F3A01,
1362   PREFIX_VEX_0F3A02,
1363   PREFIX_VEX_0F3A04,
1364   PREFIX_VEX_0F3A05,
1365   PREFIX_VEX_0F3A06,
1366   PREFIX_VEX_0F3A08,
1367   PREFIX_VEX_0F3A09,
1368   PREFIX_VEX_0F3A0A,
1369   PREFIX_VEX_0F3A0B,
1370   PREFIX_VEX_0F3A0C,
1371   PREFIX_VEX_0F3A0D,
1372   PREFIX_VEX_0F3A0E,
1373   PREFIX_VEX_0F3A0F,
1374   PREFIX_VEX_0F3A14,
1375   PREFIX_VEX_0F3A15,
1376   PREFIX_VEX_0F3A16,
1377   PREFIX_VEX_0F3A17,
1378   PREFIX_VEX_0F3A18,
1379   PREFIX_VEX_0F3A19,
1380   PREFIX_VEX_0F3A1D,
1381   PREFIX_VEX_0F3A20,
1382   PREFIX_VEX_0F3A21,
1383   PREFIX_VEX_0F3A22,
1384   PREFIX_VEX_0F3A30,
1385   PREFIX_VEX_0F3A31,
1386   PREFIX_VEX_0F3A32,
1387   PREFIX_VEX_0F3A33,
1388   PREFIX_VEX_0F3A38,
1389   PREFIX_VEX_0F3A39,
1390   PREFIX_VEX_0F3A40,
1391   PREFIX_VEX_0F3A41,
1392   PREFIX_VEX_0F3A42,
1393   PREFIX_VEX_0F3A44,
1394   PREFIX_VEX_0F3A46,
1395   PREFIX_VEX_0F3A48,
1396   PREFIX_VEX_0F3A49,
1397   PREFIX_VEX_0F3A4A,
1398   PREFIX_VEX_0F3A4B,
1399   PREFIX_VEX_0F3A4C,
1400   PREFIX_VEX_0F3A5C,
1401   PREFIX_VEX_0F3A5D,
1402   PREFIX_VEX_0F3A5E,
1403   PREFIX_VEX_0F3A5F,
1404   PREFIX_VEX_0F3A60,
1405   PREFIX_VEX_0F3A61,
1406   PREFIX_VEX_0F3A62,
1407   PREFIX_VEX_0F3A63,
1408   PREFIX_VEX_0F3A68,
1409   PREFIX_VEX_0F3A69,
1410   PREFIX_VEX_0F3A6A,
1411   PREFIX_VEX_0F3A6B,
1412   PREFIX_VEX_0F3A6C,
1413   PREFIX_VEX_0F3A6D,
1414   PREFIX_VEX_0F3A6E,
1415   PREFIX_VEX_0F3A6F,
1416   PREFIX_VEX_0F3A78,
1417   PREFIX_VEX_0F3A79,
1418   PREFIX_VEX_0F3A7A,
1419   PREFIX_VEX_0F3A7B,
1420   PREFIX_VEX_0F3A7C,
1421   PREFIX_VEX_0F3A7D,
1422   PREFIX_VEX_0F3A7E,
1423   PREFIX_VEX_0F3A7F,
1424   PREFIX_VEX_0F3ACE,
1425   PREFIX_VEX_0F3ACF,
1426   PREFIX_VEX_0F3ADF,
1427   PREFIX_VEX_0F3AF0,
1428
1429   PREFIX_EVEX_0F10,
1430   PREFIX_EVEX_0F11,
1431   PREFIX_EVEX_0F12,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F2A,
1434   PREFIX_EVEX_0F2C,
1435   PREFIX_EVEX_0F2D,
1436   PREFIX_EVEX_0F2E,
1437   PREFIX_EVEX_0F2F,
1438   PREFIX_EVEX_0F51,
1439   PREFIX_EVEX_0F58,
1440   PREFIX_EVEX_0F59,
1441   PREFIX_EVEX_0F5A,
1442   PREFIX_EVEX_0F5B,
1443   PREFIX_EVEX_0F5C,
1444   PREFIX_EVEX_0F5D,
1445   PREFIX_EVEX_0F5E,
1446   PREFIX_EVEX_0F5F,
1447   PREFIX_EVEX_0F64,
1448   PREFIX_EVEX_0F65,
1449   PREFIX_EVEX_0F66,
1450   PREFIX_EVEX_0F6E,
1451   PREFIX_EVEX_0F6F,
1452   PREFIX_EVEX_0F70,
1453   PREFIX_EVEX_0F71_REG_2,
1454   PREFIX_EVEX_0F71_REG_4,
1455   PREFIX_EVEX_0F71_REG_6,
1456   PREFIX_EVEX_0F72_REG_0,
1457   PREFIX_EVEX_0F72_REG_1,
1458   PREFIX_EVEX_0F72_REG_2,
1459   PREFIX_EVEX_0F72_REG_4,
1460   PREFIX_EVEX_0F72_REG_6,
1461   PREFIX_EVEX_0F73_REG_2,
1462   PREFIX_EVEX_0F73_REG_3,
1463   PREFIX_EVEX_0F73_REG_6,
1464   PREFIX_EVEX_0F73_REG_7,
1465   PREFIX_EVEX_0F74,
1466   PREFIX_EVEX_0F75,
1467   PREFIX_EVEX_0F76,
1468   PREFIX_EVEX_0F78,
1469   PREFIX_EVEX_0F79,
1470   PREFIX_EVEX_0F7A,
1471   PREFIX_EVEX_0F7B,
1472   PREFIX_EVEX_0F7E,
1473   PREFIX_EVEX_0F7F,
1474   PREFIX_EVEX_0FC2,
1475   PREFIX_EVEX_0FC4,
1476   PREFIX_EVEX_0FC5,
1477   PREFIX_EVEX_0FD6,
1478   PREFIX_EVEX_0FDB,
1479   PREFIX_EVEX_0FDF,
1480   PREFIX_EVEX_0FE2,
1481   PREFIX_EVEX_0FE6,
1482   PREFIX_EVEX_0FE7,
1483   PREFIX_EVEX_0FEB,
1484   PREFIX_EVEX_0FEF,
1485   PREFIX_EVEX_0F380D,
1486   PREFIX_EVEX_0F3810,
1487   PREFIX_EVEX_0F3811,
1488   PREFIX_EVEX_0F3812,
1489   PREFIX_EVEX_0F3813,
1490   PREFIX_EVEX_0F3814,
1491   PREFIX_EVEX_0F3815,
1492   PREFIX_EVEX_0F3816,
1493   PREFIX_EVEX_0F3819,
1494   PREFIX_EVEX_0F381A,
1495   PREFIX_EVEX_0F381B,
1496   PREFIX_EVEX_0F381E,
1497   PREFIX_EVEX_0F381F,
1498   PREFIX_EVEX_0F3820,
1499   PREFIX_EVEX_0F3821,
1500   PREFIX_EVEX_0F3822,
1501   PREFIX_EVEX_0F3823,
1502   PREFIX_EVEX_0F3824,
1503   PREFIX_EVEX_0F3825,
1504   PREFIX_EVEX_0F3826,
1505   PREFIX_EVEX_0F3827,
1506   PREFIX_EVEX_0F3828,
1507   PREFIX_EVEX_0F3829,
1508   PREFIX_EVEX_0F382A,
1509   PREFIX_EVEX_0F382C,
1510   PREFIX_EVEX_0F382D,
1511   PREFIX_EVEX_0F3830,
1512   PREFIX_EVEX_0F3831,
1513   PREFIX_EVEX_0F3832,
1514   PREFIX_EVEX_0F3833,
1515   PREFIX_EVEX_0F3834,
1516   PREFIX_EVEX_0F3835,
1517   PREFIX_EVEX_0F3836,
1518   PREFIX_EVEX_0F3837,
1519   PREFIX_EVEX_0F3838,
1520   PREFIX_EVEX_0F3839,
1521   PREFIX_EVEX_0F383A,
1522   PREFIX_EVEX_0F383B,
1523   PREFIX_EVEX_0F383D,
1524   PREFIX_EVEX_0F383F,
1525   PREFIX_EVEX_0F3840,
1526   PREFIX_EVEX_0F3842,
1527   PREFIX_EVEX_0F3843,
1528   PREFIX_EVEX_0F3844,
1529   PREFIX_EVEX_0F3845,
1530   PREFIX_EVEX_0F3846,
1531   PREFIX_EVEX_0F3847,
1532   PREFIX_EVEX_0F384C,
1533   PREFIX_EVEX_0F384D,
1534   PREFIX_EVEX_0F384E,
1535   PREFIX_EVEX_0F384F,
1536   PREFIX_EVEX_0F3850,
1537   PREFIX_EVEX_0F3851,
1538   PREFIX_EVEX_0F3852,
1539   PREFIX_EVEX_0F3853,
1540   PREFIX_EVEX_0F3854,
1541   PREFIX_EVEX_0F3855,
1542   PREFIX_EVEX_0F3859,
1543   PREFIX_EVEX_0F385A,
1544   PREFIX_EVEX_0F385B,
1545   PREFIX_EVEX_0F3862,
1546   PREFIX_EVEX_0F3863,
1547   PREFIX_EVEX_0F3864,
1548   PREFIX_EVEX_0F3865,
1549   PREFIX_EVEX_0F3866,
1550   PREFIX_EVEX_0F3868,
1551   PREFIX_EVEX_0F3870,
1552   PREFIX_EVEX_0F3871,
1553   PREFIX_EVEX_0F3872,
1554   PREFIX_EVEX_0F3873,
1555   PREFIX_EVEX_0F3875,
1556   PREFIX_EVEX_0F3876,
1557   PREFIX_EVEX_0F3877,
1558   PREFIX_EVEX_0F387A,
1559   PREFIX_EVEX_0F387B,
1560   PREFIX_EVEX_0F387C,
1561   PREFIX_EVEX_0F387D,
1562   PREFIX_EVEX_0F387E,
1563   PREFIX_EVEX_0F387F,
1564   PREFIX_EVEX_0F3883,
1565   PREFIX_EVEX_0F3888,
1566   PREFIX_EVEX_0F3889,
1567   PREFIX_EVEX_0F388A,
1568   PREFIX_EVEX_0F388B,
1569   PREFIX_EVEX_0F388D,
1570   PREFIX_EVEX_0F388F,
1571   PREFIX_EVEX_0F3890,
1572   PREFIX_EVEX_0F3891,
1573   PREFIX_EVEX_0F3892,
1574   PREFIX_EVEX_0F3893,
1575   PREFIX_EVEX_0F389A,
1576   PREFIX_EVEX_0F389B,
1577   PREFIX_EVEX_0F38A0,
1578   PREFIX_EVEX_0F38A1,
1579   PREFIX_EVEX_0F38A2,
1580   PREFIX_EVEX_0F38A3,
1581   PREFIX_EVEX_0F38AA,
1582   PREFIX_EVEX_0F38AB,
1583   PREFIX_EVEX_0F38B4,
1584   PREFIX_EVEX_0F38B5,
1585   PREFIX_EVEX_0F38C4,
1586   PREFIX_EVEX_0F38C6_REG_1,
1587   PREFIX_EVEX_0F38C6_REG_2,
1588   PREFIX_EVEX_0F38C6_REG_5,
1589   PREFIX_EVEX_0F38C6_REG_6,
1590   PREFIX_EVEX_0F38C7_REG_1,
1591   PREFIX_EVEX_0F38C7_REG_2,
1592   PREFIX_EVEX_0F38C7_REG_5,
1593   PREFIX_EVEX_0F38C7_REG_6,
1594   PREFIX_EVEX_0F38C8,
1595   PREFIX_EVEX_0F38CA,
1596   PREFIX_EVEX_0F38CB,
1597   PREFIX_EVEX_0F38CC,
1598   PREFIX_EVEX_0F38CD,
1599
1600   PREFIX_EVEX_0F3A00,
1601   PREFIX_EVEX_0F3A01,
1602   PREFIX_EVEX_0F3A03,
1603   PREFIX_EVEX_0F3A05,
1604   PREFIX_EVEX_0F3A08,
1605   PREFIX_EVEX_0F3A09,
1606   PREFIX_EVEX_0F3A0A,
1607   PREFIX_EVEX_0F3A0B,
1608   PREFIX_EVEX_0F3A14,
1609   PREFIX_EVEX_0F3A15,
1610   PREFIX_EVEX_0F3A16,
1611   PREFIX_EVEX_0F3A17,
1612   PREFIX_EVEX_0F3A18,
1613   PREFIX_EVEX_0F3A19,
1614   PREFIX_EVEX_0F3A1A,
1615   PREFIX_EVEX_0F3A1B,
1616   PREFIX_EVEX_0F3A1E,
1617   PREFIX_EVEX_0F3A1F,
1618   PREFIX_EVEX_0F3A20,
1619   PREFIX_EVEX_0F3A21,
1620   PREFIX_EVEX_0F3A22,
1621   PREFIX_EVEX_0F3A23,
1622   PREFIX_EVEX_0F3A25,
1623   PREFIX_EVEX_0F3A26,
1624   PREFIX_EVEX_0F3A27,
1625   PREFIX_EVEX_0F3A38,
1626   PREFIX_EVEX_0F3A39,
1627   PREFIX_EVEX_0F3A3A,
1628   PREFIX_EVEX_0F3A3B,
1629   PREFIX_EVEX_0F3A3E,
1630   PREFIX_EVEX_0F3A3F,
1631   PREFIX_EVEX_0F3A42,
1632   PREFIX_EVEX_0F3A43,
1633   PREFIX_EVEX_0F3A50,
1634   PREFIX_EVEX_0F3A51,
1635   PREFIX_EVEX_0F3A54,
1636   PREFIX_EVEX_0F3A55,
1637   PREFIX_EVEX_0F3A56,
1638   PREFIX_EVEX_0F3A57,
1639   PREFIX_EVEX_0F3A66,
1640   PREFIX_EVEX_0F3A67,
1641   PREFIX_EVEX_0F3A70,
1642   PREFIX_EVEX_0F3A71,
1643   PREFIX_EVEX_0F3A72,
1644   PREFIX_EVEX_0F3A73,
1645 };
1646
1647 enum
1648 {
1649   X86_64_06 = 0,
1650   X86_64_07,
1651   X86_64_0E,
1652   X86_64_16,
1653   X86_64_17,
1654   X86_64_1E,
1655   X86_64_1F,
1656   X86_64_27,
1657   X86_64_2F,
1658   X86_64_37,
1659   X86_64_3F,
1660   X86_64_60,
1661   X86_64_61,
1662   X86_64_62,
1663   X86_64_63,
1664   X86_64_6D,
1665   X86_64_6F,
1666   X86_64_82,
1667   X86_64_9A,
1668   X86_64_C2,
1669   X86_64_C3,
1670   X86_64_C4,
1671   X86_64_C5,
1672   X86_64_CE,
1673   X86_64_D4,
1674   X86_64_D5,
1675   X86_64_E8,
1676   X86_64_E9,
1677   X86_64_EA,
1678   X86_64_0F01_REG_0,
1679   X86_64_0F01_REG_1,
1680   X86_64_0F01_REG_2,
1681   X86_64_0F01_REG_3,
1682   X86_64_VEX_0F3849,
1683   X86_64_VEX_0F384B,
1684   X86_64_VEX_0F385C,
1685   X86_64_VEX_0F385E
1686 };
1687
1688 enum
1689 {
1690   THREE_BYTE_0F38 = 0,
1691   THREE_BYTE_0F3A
1692 };
1693
1694 enum
1695 {
1696   XOP_08 = 0,
1697   XOP_09,
1698   XOP_0A
1699 };
1700
1701 enum
1702 {
1703   VEX_0F = 0,
1704   VEX_0F38,
1705   VEX_0F3A
1706 };
1707
1708 enum
1709 {
1710   EVEX_0F = 0,
1711   EVEX_0F38,
1712   EVEX_0F3A
1713 };
1714
1715 enum
1716 {
1717   VEX_LEN_0F12_P_0_M_0 = 0,
1718   VEX_LEN_0F12_P_0_M_1,
1719 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1720   VEX_LEN_0F13_M_0,
1721   VEX_LEN_0F16_P_0_M_0,
1722   VEX_LEN_0F16_P_0_M_1,
1723 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1724   VEX_LEN_0F17_M_0,
1725   VEX_LEN_0F41_P_0,
1726   VEX_LEN_0F41_P_2,
1727   VEX_LEN_0F42_P_0,
1728   VEX_LEN_0F42_P_2,
1729   VEX_LEN_0F44_P_0,
1730   VEX_LEN_0F44_P_2,
1731   VEX_LEN_0F45_P_0,
1732   VEX_LEN_0F45_P_2,
1733   VEX_LEN_0F46_P_0,
1734   VEX_LEN_0F46_P_2,
1735   VEX_LEN_0F47_P_0,
1736   VEX_LEN_0F47_P_2,
1737   VEX_LEN_0F4A_P_0,
1738   VEX_LEN_0F4A_P_2,
1739   VEX_LEN_0F4B_P_0,
1740   VEX_LEN_0F4B_P_2,
1741   VEX_LEN_0F6E_P_2,
1742   VEX_LEN_0F77_P_0,
1743   VEX_LEN_0F7E_P_1,
1744   VEX_LEN_0F7E_P_2,
1745   VEX_LEN_0F90_P_0,
1746   VEX_LEN_0F90_P_2,
1747   VEX_LEN_0F91_P_0,
1748   VEX_LEN_0F91_P_2,
1749   VEX_LEN_0F92_P_0,
1750   VEX_LEN_0F92_P_2,
1751   VEX_LEN_0F92_P_3,
1752   VEX_LEN_0F93_P_0,
1753   VEX_LEN_0F93_P_2,
1754   VEX_LEN_0F93_P_3,
1755   VEX_LEN_0F98_P_0,
1756   VEX_LEN_0F98_P_2,
1757   VEX_LEN_0F99_P_0,
1758   VEX_LEN_0F99_P_2,
1759   VEX_LEN_0FAE_R_2_M_0,
1760   VEX_LEN_0FAE_R_3_M_0,
1761   VEX_LEN_0FC4_P_2,
1762   VEX_LEN_0FC5_P_2,
1763   VEX_LEN_0FD6_P_2,
1764   VEX_LEN_0FF7_P_2,
1765   VEX_LEN_0F3816_P_2,
1766   VEX_LEN_0F3819_P_2,
1767   VEX_LEN_0F381A_P_2_M_0,
1768   VEX_LEN_0F3836_P_2,
1769   VEX_LEN_0F3841_P_2,
1770   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1771   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1772   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1773   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1774   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1775   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1776   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1777   VEX_LEN_0F385A_P_2_M_0,
1778   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1779   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1780   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1781   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1782   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1783   VEX_LEN_0F38DB_P_2,
1784   VEX_LEN_0F38F2_P_0,
1785   VEX_LEN_0F38F3_R_1_P_0,
1786   VEX_LEN_0F38F3_R_2_P_0,
1787   VEX_LEN_0F38F3_R_3_P_0,
1788   VEX_LEN_0F38F5_P_0,
1789   VEX_LEN_0F38F5_P_1,
1790   VEX_LEN_0F38F5_P_3,
1791   VEX_LEN_0F38F6_P_3,
1792   VEX_LEN_0F38F7_P_0,
1793   VEX_LEN_0F38F7_P_1,
1794   VEX_LEN_0F38F7_P_2,
1795   VEX_LEN_0F38F7_P_3,
1796   VEX_LEN_0F3A00_P_2,
1797   VEX_LEN_0F3A01_P_2,
1798   VEX_LEN_0F3A06_P_2,
1799   VEX_LEN_0F3A14_P_2,
1800   VEX_LEN_0F3A15_P_2,
1801   VEX_LEN_0F3A16_P_2,
1802   VEX_LEN_0F3A17_P_2,
1803   VEX_LEN_0F3A18_P_2,
1804   VEX_LEN_0F3A19_P_2,
1805   VEX_LEN_0F3A20_P_2,
1806   VEX_LEN_0F3A21_P_2,
1807   VEX_LEN_0F3A22_P_2,
1808   VEX_LEN_0F3A30_P_2,
1809   VEX_LEN_0F3A31_P_2,
1810   VEX_LEN_0F3A32_P_2,
1811   VEX_LEN_0F3A33_P_2,
1812   VEX_LEN_0F3A38_P_2,
1813   VEX_LEN_0F3A39_P_2,
1814   VEX_LEN_0F3A41_P_2,
1815   VEX_LEN_0F3A46_P_2,
1816   VEX_LEN_0F3A60_P_2,
1817   VEX_LEN_0F3A61_P_2,
1818   VEX_LEN_0F3A62_P_2,
1819   VEX_LEN_0F3A63_P_2,
1820   VEX_LEN_0F3ADF_P_2,
1821   VEX_LEN_0F3AF0_P_3,
1822   VEX_LEN_0FXOP_08_85,
1823   VEX_LEN_0FXOP_08_86,
1824   VEX_LEN_0FXOP_08_87,
1825   VEX_LEN_0FXOP_08_8E,
1826   VEX_LEN_0FXOP_08_8F,
1827   VEX_LEN_0FXOP_08_95,
1828   VEX_LEN_0FXOP_08_96,
1829   VEX_LEN_0FXOP_08_97,
1830   VEX_LEN_0FXOP_08_9E,
1831   VEX_LEN_0FXOP_08_9F,
1832   VEX_LEN_0FXOP_08_A3,
1833   VEX_LEN_0FXOP_08_A6,
1834   VEX_LEN_0FXOP_08_B6,
1835   VEX_LEN_0FXOP_08_C0,
1836   VEX_LEN_0FXOP_08_C1,
1837   VEX_LEN_0FXOP_08_C2,
1838   VEX_LEN_0FXOP_08_C3,
1839   VEX_LEN_0FXOP_08_CC,
1840   VEX_LEN_0FXOP_08_CD,
1841   VEX_LEN_0FXOP_08_CE,
1842   VEX_LEN_0FXOP_08_CF,
1843   VEX_LEN_0FXOP_08_EC,
1844   VEX_LEN_0FXOP_08_ED,
1845   VEX_LEN_0FXOP_08_EE,
1846   VEX_LEN_0FXOP_08_EF,
1847   VEX_LEN_0FXOP_09_01,
1848   VEX_LEN_0FXOP_09_02,
1849   VEX_LEN_0FXOP_09_12_M_1,
1850   VEX_LEN_0FXOP_09_82_W_0,
1851   VEX_LEN_0FXOP_09_83_W_0,
1852   VEX_LEN_0FXOP_09_90,
1853   VEX_LEN_0FXOP_09_91,
1854   VEX_LEN_0FXOP_09_92,
1855   VEX_LEN_0FXOP_09_93,
1856   VEX_LEN_0FXOP_09_94,
1857   VEX_LEN_0FXOP_09_95,
1858   VEX_LEN_0FXOP_09_96,
1859   VEX_LEN_0FXOP_09_97,
1860   VEX_LEN_0FXOP_09_98,
1861   VEX_LEN_0FXOP_09_99,
1862   VEX_LEN_0FXOP_09_9A,
1863   VEX_LEN_0FXOP_09_9B,
1864   VEX_LEN_0FXOP_09_C1,
1865   VEX_LEN_0FXOP_09_C2,
1866   VEX_LEN_0FXOP_09_C3,
1867   VEX_LEN_0FXOP_09_C6,
1868   VEX_LEN_0FXOP_09_C7,
1869   VEX_LEN_0FXOP_09_CB,
1870   VEX_LEN_0FXOP_09_D1,
1871   VEX_LEN_0FXOP_09_D2,
1872   VEX_LEN_0FXOP_09_D3,
1873   VEX_LEN_0FXOP_09_D6,
1874   VEX_LEN_0FXOP_09_D7,
1875   VEX_LEN_0FXOP_09_DB,
1876   VEX_LEN_0FXOP_09_E1,
1877   VEX_LEN_0FXOP_09_E2,
1878   VEX_LEN_0FXOP_09_E3,
1879   VEX_LEN_0FXOP_0A_12,
1880 };
1881
1882 enum
1883 {
1884   EVEX_LEN_0F6E_P_2 = 0,
1885   EVEX_LEN_0F7E_P_1,
1886   EVEX_LEN_0F7E_P_2,
1887   EVEX_LEN_0FC4_P_2,
1888   EVEX_LEN_0FC5_P_2,
1889   EVEX_LEN_0FD6_P_2,
1890   EVEX_LEN_0F3816_P_2,
1891   EVEX_LEN_0F3819_P_2_W_0,
1892   EVEX_LEN_0F3819_P_2_W_1,
1893   EVEX_LEN_0F381A_P_2_W_0_M_0,
1894   EVEX_LEN_0F381A_P_2_W_1_M_0,
1895   EVEX_LEN_0F381B_P_2_W_0_M_0,
1896   EVEX_LEN_0F381B_P_2_W_1_M_0,
1897   EVEX_LEN_0F3836_P_2,
1898   EVEX_LEN_0F385A_P_2_W_0_M_0,
1899   EVEX_LEN_0F385A_P_2_W_1_M_0,
1900   EVEX_LEN_0F385B_P_2_W_0_M_0,
1901   EVEX_LEN_0F385B_P_2_W_1_M_0,
1902   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1903   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1904   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1905   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1906   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1907   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1908   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1909   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1910   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1911   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1912   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1913   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1914   EVEX_LEN_0F3A00_P_2_W_1,
1915   EVEX_LEN_0F3A01_P_2_W_1,
1916   EVEX_LEN_0F3A14_P_2,
1917   EVEX_LEN_0F3A15_P_2,
1918   EVEX_LEN_0F3A16_P_2,
1919   EVEX_LEN_0F3A17_P_2,
1920   EVEX_LEN_0F3A18_P_2_W_0,
1921   EVEX_LEN_0F3A18_P_2_W_1,
1922   EVEX_LEN_0F3A19_P_2_W_0,
1923   EVEX_LEN_0F3A19_P_2_W_1,
1924   EVEX_LEN_0F3A1A_P_2_W_0,
1925   EVEX_LEN_0F3A1A_P_2_W_1,
1926   EVEX_LEN_0F3A1B_P_2_W_0,
1927   EVEX_LEN_0F3A1B_P_2_W_1,
1928   EVEX_LEN_0F3A20_P_2,
1929   EVEX_LEN_0F3A21_P_2_W_0,
1930   EVEX_LEN_0F3A22_P_2,
1931   EVEX_LEN_0F3A23_P_2_W_0,
1932   EVEX_LEN_0F3A23_P_2_W_1,
1933   EVEX_LEN_0F3A38_P_2_W_0,
1934   EVEX_LEN_0F3A38_P_2_W_1,
1935   EVEX_LEN_0F3A39_P_2_W_0,
1936   EVEX_LEN_0F3A39_P_2_W_1,
1937   EVEX_LEN_0F3A3A_P_2_W_0,
1938   EVEX_LEN_0F3A3A_P_2_W_1,
1939   EVEX_LEN_0F3A3B_P_2_W_0,
1940   EVEX_LEN_0F3A3B_P_2_W_1,
1941   EVEX_LEN_0F3A43_P_2_W_0,
1942   EVEX_LEN_0F3A43_P_2_W_1
1943 };
1944
1945 enum
1946 {
1947   VEX_W_0F41_P_0_LEN_1 = 0,
1948   VEX_W_0F41_P_2_LEN_1,
1949   VEX_W_0F42_P_0_LEN_1,
1950   VEX_W_0F42_P_2_LEN_1,
1951   VEX_W_0F44_P_0_LEN_0,
1952   VEX_W_0F44_P_2_LEN_0,
1953   VEX_W_0F45_P_0_LEN_1,
1954   VEX_W_0F45_P_2_LEN_1,
1955   VEX_W_0F46_P_0_LEN_1,
1956   VEX_W_0F46_P_2_LEN_1,
1957   VEX_W_0F47_P_0_LEN_1,
1958   VEX_W_0F47_P_2_LEN_1,
1959   VEX_W_0F4A_P_0_LEN_1,
1960   VEX_W_0F4A_P_2_LEN_1,
1961   VEX_W_0F4B_P_0_LEN_1,
1962   VEX_W_0F4B_P_2_LEN_1,
1963   VEX_W_0F90_P_0_LEN_0,
1964   VEX_W_0F90_P_2_LEN_0,
1965   VEX_W_0F91_P_0_LEN_0,
1966   VEX_W_0F91_P_2_LEN_0,
1967   VEX_W_0F92_P_0_LEN_0,
1968   VEX_W_0F92_P_2_LEN_0,
1969   VEX_W_0F93_P_0_LEN_0,
1970   VEX_W_0F93_P_2_LEN_0,
1971   VEX_W_0F98_P_0_LEN_0,
1972   VEX_W_0F98_P_2_LEN_0,
1973   VEX_W_0F99_P_0_LEN_0,
1974   VEX_W_0F99_P_2_LEN_0,
1975   VEX_W_0F380C_P_2,
1976   VEX_W_0F380D_P_2,
1977   VEX_W_0F380E_P_2,
1978   VEX_W_0F380F_P_2,
1979   VEX_W_0F3813_P_2,
1980   VEX_W_0F3816_P_2,
1981   VEX_W_0F3818_P_2,
1982   VEX_W_0F3819_P_2,
1983   VEX_W_0F381A_P_2_M_0,
1984   VEX_W_0F382C_P_2_M_0,
1985   VEX_W_0F382D_P_2_M_0,
1986   VEX_W_0F382E_P_2_M_0,
1987   VEX_W_0F382F_P_2_M_0,
1988   VEX_W_0F3836_P_2,
1989   VEX_W_0F3846_P_2,
1990   VEX_W_0F3849_X86_64_P_0,
1991   VEX_W_0F3849_X86_64_P_2,
1992   VEX_W_0F3849_X86_64_P_3,
1993   VEX_W_0F384B_X86_64_P_1,
1994   VEX_W_0F384B_X86_64_P_2,
1995   VEX_W_0F384B_X86_64_P_3,
1996   VEX_W_0F3858_P_2,
1997   VEX_W_0F3859_P_2,
1998   VEX_W_0F385A_P_2_M_0,
1999   VEX_W_0F385C_X86_64_P_1,
2000   VEX_W_0F385E_X86_64_P_0,
2001   VEX_W_0F385E_X86_64_P_1,
2002   VEX_W_0F385E_X86_64_P_2,
2003   VEX_W_0F385E_X86_64_P_3,
2004   VEX_W_0F3878_P_2,
2005   VEX_W_0F3879_P_2,
2006   VEX_W_0F38CF_P_2,
2007   VEX_W_0F3A00_P_2,
2008   VEX_W_0F3A01_P_2,
2009   VEX_W_0F3A02_P_2,
2010   VEX_W_0F3A04_P_2,
2011   VEX_W_0F3A05_P_2,
2012   VEX_W_0F3A06_P_2,
2013   VEX_W_0F3A18_P_2,
2014   VEX_W_0F3A19_P_2,
2015   VEX_W_0F3A1D_P_2,
2016   VEX_W_0F3A30_P_2_LEN_0,
2017   VEX_W_0F3A31_P_2_LEN_0,
2018   VEX_W_0F3A32_P_2_LEN_0,
2019   VEX_W_0F3A33_P_2_LEN_0,
2020   VEX_W_0F3A38_P_2,
2021   VEX_W_0F3A39_P_2,
2022   VEX_W_0F3A46_P_2,
2023   VEX_W_0F3A4A_P_2,
2024   VEX_W_0F3A4B_P_2,
2025   VEX_W_0F3A4C_P_2,
2026   VEX_W_0F3ACE_P_2,
2027   VEX_W_0F3ACF_P_2,
2028
2029   VEX_W_0FXOP_08_85_L_0,
2030   VEX_W_0FXOP_08_86_L_0,
2031   VEX_W_0FXOP_08_87_L_0,
2032   VEX_W_0FXOP_08_8E_L_0,
2033   VEX_W_0FXOP_08_8F_L_0,
2034   VEX_W_0FXOP_08_95_L_0,
2035   VEX_W_0FXOP_08_96_L_0,
2036   VEX_W_0FXOP_08_97_L_0,
2037   VEX_W_0FXOP_08_9E_L_0,
2038   VEX_W_0FXOP_08_9F_L_0,
2039   VEX_W_0FXOP_08_A6_L_0,
2040   VEX_W_0FXOP_08_B6_L_0,
2041   VEX_W_0FXOP_08_C0_L_0,
2042   VEX_W_0FXOP_08_C1_L_0,
2043   VEX_W_0FXOP_08_C2_L_0,
2044   VEX_W_0FXOP_08_C3_L_0,
2045   VEX_W_0FXOP_08_CC_L_0,
2046   VEX_W_0FXOP_08_CD_L_0,
2047   VEX_W_0FXOP_08_CE_L_0,
2048   VEX_W_0FXOP_08_CF_L_0,
2049   VEX_W_0FXOP_08_EC_L_0,
2050   VEX_W_0FXOP_08_ED_L_0,
2051   VEX_W_0FXOP_08_EE_L_0,
2052   VEX_W_0FXOP_08_EF_L_0,
2053
2054   VEX_W_0FXOP_09_80,
2055   VEX_W_0FXOP_09_81,
2056   VEX_W_0FXOP_09_82,
2057   VEX_W_0FXOP_09_83,
2058   VEX_W_0FXOP_09_C1_L_0,
2059   VEX_W_0FXOP_09_C2_L_0,
2060   VEX_W_0FXOP_09_C3_L_0,
2061   VEX_W_0FXOP_09_C6_L_0,
2062   VEX_W_0FXOP_09_C7_L_0,
2063   VEX_W_0FXOP_09_CB_L_0,
2064   VEX_W_0FXOP_09_D1_L_0,
2065   VEX_W_0FXOP_09_D2_L_0,
2066   VEX_W_0FXOP_09_D3_L_0,
2067   VEX_W_0FXOP_09_D6_L_0,
2068   VEX_W_0FXOP_09_D7_L_0,
2069   VEX_W_0FXOP_09_DB_L_0,
2070   VEX_W_0FXOP_09_E1_L_0,
2071   VEX_W_0FXOP_09_E2_L_0,
2072   VEX_W_0FXOP_09_E3_L_0,
2073
2074   EVEX_W_0F10_P_1,
2075   EVEX_W_0F10_P_3,
2076   EVEX_W_0F11_P_1,
2077   EVEX_W_0F11_P_3,
2078   EVEX_W_0F12_P_0_M_1,
2079   EVEX_W_0F12_P_1,
2080   EVEX_W_0F12_P_3,
2081   EVEX_W_0F16_P_0_M_1,
2082   EVEX_W_0F16_P_1,
2083   EVEX_W_0F2A_P_3,
2084   EVEX_W_0F51_P_1,
2085   EVEX_W_0F51_P_3,
2086   EVEX_W_0F58_P_1,
2087   EVEX_W_0F58_P_3,
2088   EVEX_W_0F59_P_1,
2089   EVEX_W_0F59_P_3,
2090   EVEX_W_0F5A_P_0,
2091   EVEX_W_0F5A_P_1,
2092   EVEX_W_0F5A_P_2,
2093   EVEX_W_0F5A_P_3,
2094   EVEX_W_0F5B_P_0,
2095   EVEX_W_0F5B_P_1,
2096   EVEX_W_0F5B_P_2,
2097   EVEX_W_0F5C_P_1,
2098   EVEX_W_0F5C_P_3,
2099   EVEX_W_0F5D_P_1,
2100   EVEX_W_0F5D_P_3,
2101   EVEX_W_0F5E_P_1,
2102   EVEX_W_0F5E_P_3,
2103   EVEX_W_0F5F_P_1,
2104   EVEX_W_0F5F_P_3,
2105   EVEX_W_0F62,
2106   EVEX_W_0F66_P_2,
2107   EVEX_W_0F6A,
2108   EVEX_W_0F6B,
2109   EVEX_W_0F6C,
2110   EVEX_W_0F6D,
2111   EVEX_W_0F6F_P_1,
2112   EVEX_W_0F6F_P_2,
2113   EVEX_W_0F6F_P_3,
2114   EVEX_W_0F70_P_2,
2115   EVEX_W_0F72_R_2_P_2,
2116   EVEX_W_0F72_R_6_P_2,
2117   EVEX_W_0F73_R_2_P_2,
2118   EVEX_W_0F73_R_6_P_2,
2119   EVEX_W_0F76_P_2,
2120   EVEX_W_0F78_P_0,
2121   EVEX_W_0F78_P_2,
2122   EVEX_W_0F79_P_0,
2123   EVEX_W_0F79_P_2,
2124   EVEX_W_0F7A_P_1,
2125   EVEX_W_0F7A_P_2,
2126   EVEX_W_0F7A_P_3,
2127   EVEX_W_0F7B_P_2,
2128   EVEX_W_0F7B_P_3,
2129   EVEX_W_0F7E_P_1,
2130   EVEX_W_0F7F_P_1,
2131   EVEX_W_0F7F_P_2,
2132   EVEX_W_0F7F_P_3,
2133   EVEX_W_0FC2_P_1,
2134   EVEX_W_0FC2_P_3,
2135   EVEX_W_0FD2,
2136   EVEX_W_0FD3,
2137   EVEX_W_0FD4,
2138   EVEX_W_0FD6_P_2,
2139   EVEX_W_0FE6_P_1,
2140   EVEX_W_0FE6_P_2,
2141   EVEX_W_0FE6_P_3,
2142   EVEX_W_0FE7_P_2,
2143   EVEX_W_0FF2,
2144   EVEX_W_0FF3,
2145   EVEX_W_0FF4,
2146   EVEX_W_0FFA,
2147   EVEX_W_0FFB,
2148   EVEX_W_0FFE,
2149   EVEX_W_0F380D_P_2,
2150   EVEX_W_0F3810_P_1,
2151   EVEX_W_0F3810_P_2,
2152   EVEX_W_0F3811_P_1,
2153   EVEX_W_0F3811_P_2,
2154   EVEX_W_0F3812_P_1,
2155   EVEX_W_0F3812_P_2,
2156   EVEX_W_0F3813_P_1,
2157   EVEX_W_0F3813_P_2,
2158   EVEX_W_0F3814_P_1,
2159   EVEX_W_0F3815_P_1,
2160   EVEX_W_0F3819_P_2,
2161   EVEX_W_0F381A_P_2,
2162   EVEX_W_0F381B_P_2,
2163   EVEX_W_0F381E_P_2,
2164   EVEX_W_0F381F_P_2,
2165   EVEX_W_0F3820_P_1,
2166   EVEX_W_0F3821_P_1,
2167   EVEX_W_0F3822_P_1,
2168   EVEX_W_0F3823_P_1,
2169   EVEX_W_0F3824_P_1,
2170   EVEX_W_0F3825_P_1,
2171   EVEX_W_0F3825_P_2,
2172   EVEX_W_0F3828_P_2,
2173   EVEX_W_0F3829_P_2,
2174   EVEX_W_0F382A_P_1,
2175   EVEX_W_0F382A_P_2,
2176   EVEX_W_0F382B,
2177   EVEX_W_0F3830_P_1,
2178   EVEX_W_0F3831_P_1,
2179   EVEX_W_0F3832_P_1,
2180   EVEX_W_0F3833_P_1,
2181   EVEX_W_0F3834_P_1,
2182   EVEX_W_0F3835_P_1,
2183   EVEX_W_0F3835_P_2,
2184   EVEX_W_0F3837_P_2,
2185   EVEX_W_0F383A_P_1,
2186   EVEX_W_0F3852_P_1,
2187   EVEX_W_0F3859_P_2,
2188   EVEX_W_0F385A_P_2,
2189   EVEX_W_0F385B_P_2,
2190   EVEX_W_0F3862_P_2,
2191   EVEX_W_0F3863_P_2,
2192   EVEX_W_0F3870_P_2,
2193   EVEX_W_0F3872_P_1,
2194   EVEX_W_0F3872_P_2,
2195   EVEX_W_0F3872_P_3,
2196   EVEX_W_0F387A_P_2,
2197   EVEX_W_0F387B_P_2,
2198   EVEX_W_0F3883_P_2,
2199   EVEX_W_0F3891_P_2,
2200   EVEX_W_0F3893_P_2,
2201   EVEX_W_0F38A1_P_2,
2202   EVEX_W_0F38A3_P_2,
2203   EVEX_W_0F38C7_R_1_P_2,
2204   EVEX_W_0F38C7_R_2_P_2,
2205   EVEX_W_0F38C7_R_5_P_2,
2206   EVEX_W_0F38C7_R_6_P_2,
2207
2208   EVEX_W_0F3A00_P_2,
2209   EVEX_W_0F3A01_P_2,
2210   EVEX_W_0F3A05_P_2,
2211   EVEX_W_0F3A08_P_2,
2212   EVEX_W_0F3A09_P_2,
2213   EVEX_W_0F3A0A_P_2,
2214   EVEX_W_0F3A0B_P_2,
2215   EVEX_W_0F3A18_P_2,
2216   EVEX_W_0F3A19_P_2,
2217   EVEX_W_0F3A1A_P_2,
2218   EVEX_W_0F3A1B_P_2,
2219   EVEX_W_0F3A21_P_2,
2220   EVEX_W_0F3A23_P_2,
2221   EVEX_W_0F3A38_P_2,
2222   EVEX_W_0F3A39_P_2,
2223   EVEX_W_0F3A3A_P_2,
2224   EVEX_W_0F3A3B_P_2,
2225   EVEX_W_0F3A42_P_2,
2226   EVEX_W_0F3A43_P_2,
2227   EVEX_W_0F3A70_P_2,
2228   EVEX_W_0F3A72_P_2,
2229 };
2230
2231 typedef void (*op_rtn) (int bytemode, int sizeflag);
2232
2233 struct dis386 {
2234   const char *name;
2235   struct
2236     {
2237       op_rtn rtn;
2238       int bytemode;
2239     } op[MAX_OPERANDS];
2240   unsigned int prefix_requirement;
2241 };
2242
2243 /* Upper case letters in the instruction names here are macros.
2244    'A' => print 'b' if no register operands or suffix_always is true
2245    'B' => print 'b' if suffix_always is true
2246    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2247           size prefix
2248    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2249           suffix_always is true
2250    'E' => print 'e' if 32-bit form of jcxz
2251    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2252    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2253    'H' => print ",pt" or ",pn" branch hint
2254    'I' unused.
2255    'J' unused.
2256    'K' => print 'd' or 'q' if rex prefix is present.
2257    'L' => print 'l' if suffix_always is true
2258    'M' => print 'r' if intel_mnemonic is false.
2259    'N' => print 'n' if instruction has no wait "prefix"
2260    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2261    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2262           or suffix_always is true.  print 'q' if rex prefix is present.
2263    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2264           is true
2265    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2266    'S' => print 'w', 'l' or 'q' if suffix_always is true
2267    'T' => print 'q' in 64bit mode if instruction has no operand size
2268           prefix and behave as 'P' otherwise
2269    'U' => print 'q' in 64bit mode if instruction has no operand size
2270           prefix and behave as 'Q' otherwise
2271    'V' => print 'q' in 64bit mode if instruction has no operand size
2272           prefix and behave as 'S' otherwise
2273    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2274    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2275    'Y' unused.
2276    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2277    '!' => change condition from true to false or from false to true.
2278    '%' => add 1 upper case letter to the macro.
2279    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2280           prefix or suffix_always is true (lcall/ljmp).
2281    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2282           on operand size prefix.
2283    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2284           has no operand size prefix for AMD64 ISA, behave as 'P'
2285           otherwise
2286
2287    2 upper case letter macros:
2288    "XY" => print 'x' or 'y' if suffix_always is true or no register
2289            operands and no broadcast.
2290    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2291            register operands and no broadcast.
2292    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2293    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2294            operand or no operand at all in 64bit mode, or if suffix_always
2295            is true.
2296    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2297    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2298    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2299    "LW" => print 'd', 'q' depending on the VEX.W bit
2300    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2301    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2302            an operand size prefix, or suffix_always is true.  print
2303            'q' if rex prefix is present.
2304
2305    Many of the above letters print nothing in Intel mode.  See "putop"
2306    for the details.
2307
2308    Braces '{' and '}', and vertical bars '|', indicate alternative
2309    mnemonic strings for AT&T and Intel.  */
2310
2311 static const struct dis386 dis386[] = {
2312   /* 00 */
2313   { "addB",             { Ebh1, Gb }, 0 },
2314   { "addS",             { Evh1, Gv }, 0 },
2315   { "addB",             { Gb, EbS }, 0 },
2316   { "addS",             { Gv, EvS }, 0 },
2317   { "addB",             { AL, Ib }, 0 },
2318   { "addS",             { eAX, Iv }, 0 },
2319   { X86_64_TABLE (X86_64_06) },
2320   { X86_64_TABLE (X86_64_07) },
2321   /* 08 */
2322   { "orB",              { Ebh1, Gb }, 0 },
2323   { "orS",              { Evh1, Gv }, 0 },
2324   { "orB",              { Gb, EbS }, 0 },
2325   { "orS",              { Gv, EvS }, 0 },
2326   { "orB",              { AL, Ib }, 0 },
2327   { "orS",              { eAX, Iv }, 0 },
2328   { X86_64_TABLE (X86_64_0E) },
2329   { Bad_Opcode },       /* 0x0f extended opcode escape */
2330   /* 10 */
2331   { "adcB",             { Ebh1, Gb }, 0 },
2332   { "adcS",             { Evh1, Gv }, 0 },
2333   { "adcB",             { Gb, EbS }, 0 },
2334   { "adcS",             { Gv, EvS }, 0 },
2335   { "adcB",             { AL, Ib }, 0 },
2336   { "adcS",             { eAX, Iv }, 0 },
2337   { X86_64_TABLE (X86_64_16) },
2338   { X86_64_TABLE (X86_64_17) },
2339   /* 18 */
2340   { "sbbB",             { Ebh1, Gb }, 0 },
2341   { "sbbS",             { Evh1, Gv }, 0 },
2342   { "sbbB",             { Gb, EbS }, 0 },
2343   { "sbbS",             { Gv, EvS }, 0 },
2344   { "sbbB",             { AL, Ib }, 0 },
2345   { "sbbS",             { eAX, Iv }, 0 },
2346   { X86_64_TABLE (X86_64_1E) },
2347   { X86_64_TABLE (X86_64_1F) },
2348   /* 20 */
2349   { "andB",             { Ebh1, Gb }, 0 },
2350   { "andS",             { Evh1, Gv }, 0 },
2351   { "andB",             { Gb, EbS }, 0 },
2352   { "andS",             { Gv, EvS }, 0 },
2353   { "andB",             { AL, Ib }, 0 },
2354   { "andS",             { eAX, Iv }, 0 },
2355   { Bad_Opcode },       /* SEG ES prefix */
2356   { X86_64_TABLE (X86_64_27) },
2357   /* 28 */
2358   { "subB",             { Ebh1, Gb }, 0 },
2359   { "subS",             { Evh1, Gv }, 0 },
2360   { "subB",             { Gb, EbS }, 0 },
2361   { "subS",             { Gv, EvS }, 0 },
2362   { "subB",             { AL, Ib }, 0 },
2363   { "subS",             { eAX, Iv }, 0 },
2364   { Bad_Opcode },       /* SEG CS prefix */
2365   { X86_64_TABLE (X86_64_2F) },
2366   /* 30 */
2367   { "xorB",             { Ebh1, Gb }, 0 },
2368   { "xorS",             { Evh1, Gv }, 0 },
2369   { "xorB",             { Gb, EbS }, 0 },
2370   { "xorS",             { Gv, EvS }, 0 },
2371   { "xorB",             { AL, Ib }, 0 },
2372   { "xorS",             { eAX, Iv }, 0 },
2373   { Bad_Opcode },       /* SEG SS prefix */
2374   { X86_64_TABLE (X86_64_37) },
2375   /* 38 */
2376   { "cmpB",             { Eb, Gb }, 0 },
2377   { "cmpS",             { Ev, Gv }, 0 },
2378   { "cmpB",             { Gb, EbS }, 0 },
2379   { "cmpS",             { Gv, EvS }, 0 },
2380   { "cmpB",             { AL, Ib }, 0 },
2381   { "cmpS",             { eAX, Iv }, 0 },
2382   { Bad_Opcode },       /* SEG DS prefix */
2383   { X86_64_TABLE (X86_64_3F) },
2384   /* 40 */
2385   { "inc{S|}",          { RMeAX }, 0 },
2386   { "inc{S|}",          { RMeCX }, 0 },
2387   { "inc{S|}",          { RMeDX }, 0 },
2388   { "inc{S|}",          { RMeBX }, 0 },
2389   { "inc{S|}",          { RMeSP }, 0 },
2390   { "inc{S|}",          { RMeBP }, 0 },
2391   { "inc{S|}",          { RMeSI }, 0 },
2392   { "inc{S|}",          { RMeDI }, 0 },
2393   /* 48 */
2394   { "dec{S|}",          { RMeAX }, 0 },
2395   { "dec{S|}",          { RMeCX }, 0 },
2396   { "dec{S|}",          { RMeDX }, 0 },
2397   { "dec{S|}",          { RMeBX }, 0 },
2398   { "dec{S|}",          { RMeSP }, 0 },
2399   { "dec{S|}",          { RMeBP }, 0 },
2400   { "dec{S|}",          { RMeSI }, 0 },
2401   { "dec{S|}",          { RMeDI }, 0 },
2402   /* 50 */
2403   { "pushV",            { RMrAX }, 0 },
2404   { "pushV",            { RMrCX }, 0 },
2405   { "pushV",            { RMrDX }, 0 },
2406   { "pushV",            { RMrBX }, 0 },
2407   { "pushV",            { RMrSP }, 0 },
2408   { "pushV",            { RMrBP }, 0 },
2409   { "pushV",            { RMrSI }, 0 },
2410   { "pushV",            { RMrDI }, 0 },
2411   /* 58 */
2412   { "popV",             { RMrAX }, 0 },
2413   { "popV",             { RMrCX }, 0 },
2414   { "popV",             { RMrDX }, 0 },
2415   { "popV",             { RMrBX }, 0 },
2416   { "popV",             { RMrSP }, 0 },
2417   { "popV",             { RMrBP }, 0 },
2418   { "popV",             { RMrSI }, 0 },
2419   { "popV",             { RMrDI }, 0 },
2420   /* 60 */
2421   { X86_64_TABLE (X86_64_60) },
2422   { X86_64_TABLE (X86_64_61) },
2423   { X86_64_TABLE (X86_64_62) },
2424   { X86_64_TABLE (X86_64_63) },
2425   { Bad_Opcode },       /* seg fs */
2426   { Bad_Opcode },       /* seg gs */
2427   { Bad_Opcode },       /* op size prefix */
2428   { Bad_Opcode },       /* adr size prefix */
2429   /* 68 */
2430   { "pushT",            { sIv }, 0 },
2431   { "imulS",            { Gv, Ev, Iv }, 0 },
2432   { "pushT",            { sIbT }, 0 },
2433   { "imulS",            { Gv, Ev, sIb }, 0 },
2434   { "ins{b|}",          { Ybr, indirDX }, 0 },
2435   { X86_64_TABLE (X86_64_6D) },
2436   { "outs{b|}",         { indirDXr, Xb }, 0 },
2437   { X86_64_TABLE (X86_64_6F) },
2438   /* 70 */
2439   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2440   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2441   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2442   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2443   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2444   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2446   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2447   /* 78 */
2448   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2449   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2450   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2451   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2452   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2453   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2454   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2455   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2456   /* 80 */
2457   { REG_TABLE (REG_80) },
2458   { REG_TABLE (REG_81) },
2459   { X86_64_TABLE (X86_64_82) },
2460   { REG_TABLE (REG_83) },
2461   { "testB",            { Eb, Gb }, 0 },
2462   { "testS",            { Ev, Gv }, 0 },
2463   { "xchgB",            { Ebh2, Gb }, 0 },
2464   { "xchgS",            { Evh2, Gv }, 0 },
2465   /* 88 */
2466   { "movB",             { Ebh3, Gb }, 0 },
2467   { "movS",             { Evh3, Gv }, 0 },
2468   { "movB",             { Gb, EbS }, 0 },
2469   { "movS",             { Gv, EvS }, 0 },
2470   { "movD",             { Sv, Sw }, 0 },
2471   { MOD_TABLE (MOD_8D) },
2472   { "movD",             { Sw, Sv }, 0 },
2473   { REG_TABLE (REG_8F) },
2474   /* 90 */
2475   { PREFIX_TABLE (PREFIX_90) },
2476   { "xchgS",            { RMeCX, eAX }, 0 },
2477   { "xchgS",            { RMeDX, eAX }, 0 },
2478   { "xchgS",            { RMeBX, eAX }, 0 },
2479   { "xchgS",            { RMeSP, eAX }, 0 },
2480   { "xchgS",            { RMeBP, eAX }, 0 },
2481   { "xchgS",            { RMeSI, eAX }, 0 },
2482   { "xchgS",            { RMeDI, eAX }, 0 },
2483   /* 98 */
2484   { "cW{t|}R",          { XX }, 0 },
2485   { "cR{t|}O",          { XX }, 0 },
2486   { X86_64_TABLE (X86_64_9A) },
2487   { Bad_Opcode },       /* fwait */
2488   { "pushfT",           { XX }, 0 },
2489   { "popfT",            { XX }, 0 },
2490   { "sahf",             { XX }, 0 },
2491   { "lahf",             { XX }, 0 },
2492   /* a0 */
2493   { "mov%LB",           { AL, Ob }, 0 },
2494   { "mov%LS",           { eAX, Ov }, 0 },
2495   { "mov%LB",           { Ob, AL }, 0 },
2496   { "mov%LS",           { Ov, eAX }, 0 },
2497   { "movs{b|}",         { Ybr, Xb }, 0 },
2498   { "movs{R|}",         { Yvr, Xv }, 0 },
2499   { "cmps{b|}",         { Xb, Yb }, 0 },
2500   { "cmps{R|}",         { Xv, Yv }, 0 },
2501   /* a8 */
2502   { "testB",            { AL, Ib }, 0 },
2503   { "testS",            { eAX, Iv }, 0 },
2504   { "stosB",            { Ybr, AL }, 0 },
2505   { "stosS",            { Yvr, eAX }, 0 },
2506   { "lodsB",            { ALr, Xb }, 0 },
2507   { "lodsS",            { eAXr, Xv }, 0 },
2508   { "scasB",            { AL, Yb }, 0 },
2509   { "scasS",            { eAX, Yv }, 0 },
2510   /* b0 */
2511   { "movB",             { RMAL, Ib }, 0 },
2512   { "movB",             { RMCL, Ib }, 0 },
2513   { "movB",             { RMDL, Ib }, 0 },
2514   { "movB",             { RMBL, Ib }, 0 },
2515   { "movB",             { RMAH, Ib }, 0 },
2516   { "movB",             { RMCH, Ib }, 0 },
2517   { "movB",             { RMDH, Ib }, 0 },
2518   { "movB",             { RMBH, Ib }, 0 },
2519   /* b8 */
2520   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2521   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2522   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2523   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2524   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2525   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2526   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2527   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2528   /* c0 */
2529   { REG_TABLE (REG_C0) },
2530   { REG_TABLE (REG_C1) },
2531   { X86_64_TABLE (X86_64_C2) },
2532   { X86_64_TABLE (X86_64_C3) },
2533   { X86_64_TABLE (X86_64_C4) },
2534   { X86_64_TABLE (X86_64_C5) },
2535   { REG_TABLE (REG_C6) },
2536   { REG_TABLE (REG_C7) },
2537   /* c8 */
2538   { "enterT",           { Iw, Ib }, 0 },
2539   { "leaveT",           { XX }, 0 },
2540   { "{l|}ret{|f}P",     { Iw }, 0 },
2541   { "{l|}ret{|f}P",     { XX }, 0 },
2542   { "int3",             { XX }, 0 },
2543   { "int",              { Ib }, 0 },
2544   { X86_64_TABLE (X86_64_CE) },
2545   { "iret%LP",          { XX }, 0 },
2546   /* d0 */
2547   { REG_TABLE (REG_D0) },
2548   { REG_TABLE (REG_D1) },
2549   { REG_TABLE (REG_D2) },
2550   { REG_TABLE (REG_D3) },
2551   { X86_64_TABLE (X86_64_D4) },
2552   { X86_64_TABLE (X86_64_D5) },
2553   { Bad_Opcode },
2554   { "xlat",             { DSBX }, 0 },
2555   /* d8 */
2556   { FLOAT },
2557   { FLOAT },
2558   { FLOAT },
2559   { FLOAT },
2560   { FLOAT },
2561   { FLOAT },
2562   { FLOAT },
2563   { FLOAT },
2564   /* e0 */
2565   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2566   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2567   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2568   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2569   { "inB",              { AL, Ib }, 0 },
2570   { "inG",              { zAX, Ib }, 0 },
2571   { "outB",             { Ib, AL }, 0 },
2572   { "outG",             { Ib, zAX }, 0 },
2573   /* e8 */
2574   { X86_64_TABLE (X86_64_E8) },
2575   { X86_64_TABLE (X86_64_E9) },
2576   { X86_64_TABLE (X86_64_EA) },
2577   { "jmp",              { Jb, BND }, 0 },
2578   { "inB",              { AL, indirDX }, 0 },
2579   { "inG",              { zAX, indirDX }, 0 },
2580   { "outB",             { indirDX, AL }, 0 },
2581   { "outG",             { indirDX, zAX }, 0 },
2582   /* f0 */
2583   { Bad_Opcode },       /* lock prefix */
2584   { "icebp",            { XX }, 0 },
2585   { Bad_Opcode },       /* repne */
2586   { Bad_Opcode },       /* repz */
2587   { "hlt",              { XX }, 0 },
2588   { "cmc",              { XX }, 0 },
2589   { REG_TABLE (REG_F6) },
2590   { REG_TABLE (REG_F7) },
2591   /* f8 */
2592   { "clc",              { XX }, 0 },
2593   { "stc",              { XX }, 0 },
2594   { "cli",              { XX }, 0 },
2595   { "sti",              { XX }, 0 },
2596   { "cld",              { XX }, 0 },
2597   { "std",              { XX }, 0 },
2598   { REG_TABLE (REG_FE) },
2599   { REG_TABLE (REG_FF) },
2600 };
2601
2602 static const struct dis386 dis386_twobyte[] = {
2603   /* 00 */
2604   { REG_TABLE (REG_0F00 ) },
2605   { REG_TABLE (REG_0F01 ) },
2606   { "larS",             { Gv, Ew }, 0 },
2607   { "lslS",             { Gv, Ew }, 0 },
2608   { Bad_Opcode },
2609   { "syscall",          { XX }, 0 },
2610   { "clts",             { XX }, 0 },
2611   { "sysret%LQ",                { XX }, 0 },
2612   /* 08 */
2613   { "invd",             { XX }, 0 },
2614   { PREFIX_TABLE (PREFIX_0F09) },
2615   { Bad_Opcode },
2616   { "ud2",              { XX }, 0 },
2617   { Bad_Opcode },
2618   { REG_TABLE (REG_0F0D) },
2619   { "femms",            { XX }, 0 },
2620   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2621   /* 10 */
2622   { PREFIX_TABLE (PREFIX_0F10) },
2623   { PREFIX_TABLE (PREFIX_0F11) },
2624   { PREFIX_TABLE (PREFIX_0F12) },
2625   { MOD_TABLE (MOD_0F13) },
2626   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2627   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2628   { PREFIX_TABLE (PREFIX_0F16) },
2629   { MOD_TABLE (MOD_0F17) },
2630   /* 18 */
2631   { REG_TABLE (REG_0F18) },
2632   { "nopQ",             { Ev }, 0 },
2633   { PREFIX_TABLE (PREFIX_0F1A) },
2634   { PREFIX_TABLE (PREFIX_0F1B) },
2635   { PREFIX_TABLE (PREFIX_0F1C) },
2636   { "nopQ",             { Ev }, 0 },
2637   { PREFIX_TABLE (PREFIX_0F1E) },
2638   { "nopQ",             { Ev }, 0 },
2639   /* 20 */
2640   { "movZ",             { Rm, Cm }, 0 },
2641   { "movZ",             { Rm, Dm }, 0 },
2642   { "movZ",             { Cm, Rm }, 0 },
2643   { "movZ",             { Dm, Rm }, 0 },
2644   { MOD_TABLE (MOD_0F24) },
2645   { Bad_Opcode },
2646   { MOD_TABLE (MOD_0F26) },
2647   { Bad_Opcode },
2648   /* 28 */
2649   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2650   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2651   { PREFIX_TABLE (PREFIX_0F2A) },
2652   { PREFIX_TABLE (PREFIX_0F2B) },
2653   { PREFIX_TABLE (PREFIX_0F2C) },
2654   { PREFIX_TABLE (PREFIX_0F2D) },
2655   { PREFIX_TABLE (PREFIX_0F2E) },
2656   { PREFIX_TABLE (PREFIX_0F2F) },
2657   /* 30 */
2658   { "wrmsr",            { XX }, 0 },
2659   { "rdtsc",            { XX }, 0 },
2660   { "rdmsr",            { XX }, 0 },
2661   { "rdpmc",            { XX }, 0 },
2662   { "sysenter",         { SEP }, 0 },
2663   { "sysexit",          { SEP }, 0 },
2664   { Bad_Opcode },
2665   { "getsec",           { XX }, 0 },
2666   /* 38 */
2667   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2668   { Bad_Opcode },
2669   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2670   { Bad_Opcode },
2671   { Bad_Opcode },
2672   { Bad_Opcode },
2673   { Bad_Opcode },
2674   { Bad_Opcode },
2675   /* 40 */
2676   { "cmovoS",           { Gv, Ev }, 0 },
2677   { "cmovnoS",          { Gv, Ev }, 0 },
2678   { "cmovbS",           { Gv, Ev }, 0 },
2679   { "cmovaeS",          { Gv, Ev }, 0 },
2680   { "cmoveS",           { Gv, Ev }, 0 },
2681   { "cmovneS",          { Gv, Ev }, 0 },
2682   { "cmovbeS",          { Gv, Ev }, 0 },
2683   { "cmovaS",           { Gv, Ev }, 0 },
2684   /* 48 */
2685   { "cmovsS",           { Gv, Ev }, 0 },
2686   { "cmovnsS",          { Gv, Ev }, 0 },
2687   { "cmovpS",           { Gv, Ev }, 0 },
2688   { "cmovnpS",          { Gv, Ev }, 0 },
2689   { "cmovlS",           { Gv, Ev }, 0 },
2690   { "cmovgeS",          { Gv, Ev }, 0 },
2691   { "cmovleS",          { Gv, Ev }, 0 },
2692   { "cmovgS",           { Gv, Ev }, 0 },
2693   /* 50 */
2694   { MOD_TABLE (MOD_0F50) },
2695   { PREFIX_TABLE (PREFIX_0F51) },
2696   { PREFIX_TABLE (PREFIX_0F52) },
2697   { PREFIX_TABLE (PREFIX_0F53) },
2698   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2699   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2700   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2701   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2702   /* 58 */
2703   { PREFIX_TABLE (PREFIX_0F58) },
2704   { PREFIX_TABLE (PREFIX_0F59) },
2705   { PREFIX_TABLE (PREFIX_0F5A) },
2706   { PREFIX_TABLE (PREFIX_0F5B) },
2707   { PREFIX_TABLE (PREFIX_0F5C) },
2708   { PREFIX_TABLE (PREFIX_0F5D) },
2709   { PREFIX_TABLE (PREFIX_0F5E) },
2710   { PREFIX_TABLE (PREFIX_0F5F) },
2711   /* 60 */
2712   { PREFIX_TABLE (PREFIX_0F60) },
2713   { PREFIX_TABLE (PREFIX_0F61) },
2714   { PREFIX_TABLE (PREFIX_0F62) },
2715   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2716   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2717   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2718   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2719   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2720   /* 68 */
2721   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2722   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2723   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2724   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2725   { PREFIX_TABLE (PREFIX_0F6C) },
2726   { PREFIX_TABLE (PREFIX_0F6D) },
2727   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2728   { PREFIX_TABLE (PREFIX_0F6F) },
2729   /* 70 */
2730   { PREFIX_TABLE (PREFIX_0F70) },
2731   { REG_TABLE (REG_0F71) },
2732   { REG_TABLE (REG_0F72) },
2733   { REG_TABLE (REG_0F73) },
2734   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2735   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2736   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2737   { "emms",             { XX }, PREFIX_OPCODE },
2738   /* 78 */
2739   { PREFIX_TABLE (PREFIX_0F78) },
2740   { PREFIX_TABLE (PREFIX_0F79) },
2741   { Bad_Opcode },
2742   { Bad_Opcode },
2743   { PREFIX_TABLE (PREFIX_0F7C) },
2744   { PREFIX_TABLE (PREFIX_0F7D) },
2745   { PREFIX_TABLE (PREFIX_0F7E) },
2746   { PREFIX_TABLE (PREFIX_0F7F) },
2747   /* 80 */
2748   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2749   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2750   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2751   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2752   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2753   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2755   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2756   /* 88 */
2757   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2758   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2759   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2760   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2761   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2762   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2763   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2764   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2765   /* 90 */
2766   { "seto",             { Eb }, 0 },
2767   { "setno",            { Eb }, 0 },
2768   { "setb",             { Eb }, 0 },
2769   { "setae",            { Eb }, 0 },
2770   { "sete",             { Eb }, 0 },
2771   { "setne",            { Eb }, 0 },
2772   { "setbe",            { Eb }, 0 },
2773   { "seta",             { Eb }, 0 },
2774   /* 98 */
2775   { "sets",             { Eb }, 0 },
2776   { "setns",            { Eb }, 0 },
2777   { "setp",             { Eb }, 0 },
2778   { "setnp",            { Eb }, 0 },
2779   { "setl",             { Eb }, 0 },
2780   { "setge",            { Eb }, 0 },
2781   { "setle",            { Eb }, 0 },
2782   { "setg",             { Eb }, 0 },
2783   /* a0 */
2784   { "pushT",            { fs }, 0 },
2785   { "popT",             { fs }, 0 },
2786   { "cpuid",            { XX }, 0 },
2787   { "btS",              { Ev, Gv }, 0 },
2788   { "shldS",            { Ev, Gv, Ib }, 0 },
2789   { "shldS",            { Ev, Gv, CL }, 0 },
2790   { REG_TABLE (REG_0FA6) },
2791   { REG_TABLE (REG_0FA7) },
2792   /* a8 */
2793   { "pushT",            { gs }, 0 },
2794   { "popT",             { gs }, 0 },
2795   { "rsm",              { XX }, 0 },
2796   { "btsS",             { Evh1, Gv }, 0 },
2797   { "shrdS",            { Ev, Gv, Ib }, 0 },
2798   { "shrdS",            { Ev, Gv, CL }, 0 },
2799   { REG_TABLE (REG_0FAE) },
2800   { "imulS",            { Gv, Ev }, 0 },
2801   /* b0 */
2802   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2803   { "cmpxchgS",         { Evh1, Gv }, 0 },
2804   { MOD_TABLE (MOD_0FB2) },
2805   { "btrS",             { Evh1, Gv }, 0 },
2806   { MOD_TABLE (MOD_0FB4) },
2807   { MOD_TABLE (MOD_0FB5) },
2808   { "movz{bR|x}",       { Gv, Eb }, 0 },
2809   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2810   /* b8 */
2811   { PREFIX_TABLE (PREFIX_0FB8) },
2812   { "ud1S",             { Gv, Ev }, 0 },
2813   { REG_TABLE (REG_0FBA) },
2814   { "btcS",             { Evh1, Gv }, 0 },
2815   { PREFIX_TABLE (PREFIX_0FBC) },
2816   { PREFIX_TABLE (PREFIX_0FBD) },
2817   { "movs{bR|x}",       { Gv, Eb }, 0 },
2818   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2819   /* c0 */
2820   { "xaddB",            { Ebh1, Gb }, 0 },
2821   { "xaddS",            { Evh1, Gv }, 0 },
2822   { PREFIX_TABLE (PREFIX_0FC2) },
2823   { MOD_TABLE (MOD_0FC3) },
2824   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2825   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2826   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2827   { REG_TABLE (REG_0FC7) },
2828   /* c8 */
2829   { "bswap",            { RMeAX }, 0 },
2830   { "bswap",            { RMeCX }, 0 },
2831   { "bswap",            { RMeDX }, 0 },
2832   { "bswap",            { RMeBX }, 0 },
2833   { "bswap",            { RMeSP }, 0 },
2834   { "bswap",            { RMeBP }, 0 },
2835   { "bswap",            { RMeSI }, 0 },
2836   { "bswap",            { RMeDI }, 0 },
2837   /* d0 */
2838   { PREFIX_TABLE (PREFIX_0FD0) },
2839   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2840   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2841   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2842   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2843   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2844   { PREFIX_TABLE (PREFIX_0FD6) },
2845   { MOD_TABLE (MOD_0FD7) },
2846   /* d8 */
2847   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2848   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2849   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2850   { "pand",             { MX, EM }, PREFIX_OPCODE },
2851   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2852   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2853   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2854   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2855   /* e0 */
2856   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2857   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2858   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2859   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2860   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2861   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2862   { PREFIX_TABLE (PREFIX_0FE6) },
2863   { PREFIX_TABLE (PREFIX_0FE7) },
2864   /* e8 */
2865   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2866   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2867   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2868   { "por",              { MX, EM }, PREFIX_OPCODE },
2869   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2870   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2871   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2872   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2873   /* f0 */
2874   { PREFIX_TABLE (PREFIX_0FF0) },
2875   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2876   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2877   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2878   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2879   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2880   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2881   { PREFIX_TABLE (PREFIX_0FF7) },
2882   /* f8 */
2883   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2884   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2885   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2886   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2887   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2888   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2889   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2890   { "ud0S",             { Gv, Ev }, 0 },
2891 };
2892
2893 static const unsigned char onebyte_has_modrm[256] = {
2894   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2895   /*       -------------------------------        */
2896   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2897   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2898   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2899   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2900   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2901   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2902   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2903   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2904   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2905   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2906   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2907   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2908   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2909   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2910   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2911   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2912   /*       -------------------------------        */
2913   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2914 };
2915
2916 static const unsigned char twobyte_has_modrm[256] = {
2917   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2918   /*       -------------------------------        */
2919   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2920   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2921   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2922   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2923   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2924   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2925   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2926   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2927   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2928   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2929   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2930   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2931   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2932   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2933   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2934   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2935   /*       -------------------------------        */
2936   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2937 };
2938
2939 static char obuf[100];
2940 static char *obufp;
2941 static char *mnemonicendp;
2942 static char scratchbuf[100];
2943 static unsigned char *start_codep;
2944 static unsigned char *insn_codep;
2945 static unsigned char *codep;
2946 static unsigned char *end_codep;
2947 static int last_lock_prefix;
2948 static int last_repz_prefix;
2949 static int last_repnz_prefix;
2950 static int last_data_prefix;
2951 static int last_addr_prefix;
2952 static int last_rex_prefix;
2953 static int last_seg_prefix;
2954 static int fwait_prefix;
2955 /* The active segment register prefix.  */
2956 static int active_seg_prefix;
2957 #define MAX_CODE_LENGTH 15
2958 /* We can up to 14 prefixes since the maximum instruction length is
2959    15bytes.  */
2960 static int all_prefixes[MAX_CODE_LENGTH - 1];
2961 static disassemble_info *the_info;
2962 static struct
2963   {
2964     int mod;
2965     int reg;
2966     int rm;
2967   }
2968 modrm;
2969 static unsigned char need_modrm;
2970 static struct
2971   {
2972     int scale;
2973     int index;
2974     int base;
2975   }
2976 sib;
2977 static struct
2978   {
2979     int register_specifier;
2980     int length;
2981     int prefix;
2982     int w;
2983     int evex;
2984     int r;
2985     int v;
2986     int mask_register_specifier;
2987     int zeroing;
2988     int ll;
2989     int b;
2990   }
2991 vex;
2992 static unsigned char need_vex;
2993 static unsigned char need_vex_reg;
2994
2995 struct op
2996   {
2997     const char *name;
2998     unsigned int len;
2999   };
3000
3001 /* If we are accessing mod/rm/reg without need_modrm set, then the
3002    values are stale.  Hitting this abort likely indicates that you
3003    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3004 #define MODRM_CHECK  if (!need_modrm) abort ()
3005
3006 static const char **names64;
3007 static const char **names32;
3008 static const char **names16;
3009 static const char **names8;
3010 static const char **names8rex;
3011 static const char **names_seg;
3012 static const char *index64;
3013 static const char *index32;
3014 static const char **index16;
3015 static const char **names_bnd;
3016
3017 static const char *intel_names64[] = {
3018   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3019   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3020 };
3021 static const char *intel_names32[] = {
3022   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3023   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3024 };
3025 static const char *intel_names16[] = {
3026   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3027   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3028 };
3029 static const char *intel_names8[] = {
3030   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3031 };
3032 static const char *intel_names8rex[] = {
3033   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3034   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3035 };
3036 static const char *intel_names_seg[] = {
3037   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3038 };
3039 static const char *intel_index64 = "riz";
3040 static const char *intel_index32 = "eiz";
3041 static const char *intel_index16[] = {
3042   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3043 };
3044
3045 static const char *att_names64[] = {
3046   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3047   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3048 };
3049 static const char *att_names32[] = {
3050   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3051   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3052 };
3053 static const char *att_names16[] = {
3054   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3055   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3056 };
3057 static const char *att_names8[] = {
3058   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3059 };
3060 static const char *att_names8rex[] = {
3061   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3062   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3063 };
3064 static const char *att_names_seg[] = {
3065   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3066 };
3067 static const char *att_index64 = "%riz";
3068 static const char *att_index32 = "%eiz";
3069 static const char *att_index16[] = {
3070   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3071 };
3072
3073 static const char **names_mm;
3074 static const char *intel_names_mm[] = {
3075   "mm0", "mm1", "mm2", "mm3",
3076   "mm4", "mm5", "mm6", "mm7"
3077 };
3078 static const char *att_names_mm[] = {
3079   "%mm0", "%mm1", "%mm2", "%mm3",
3080   "%mm4", "%mm5", "%mm6", "%mm7"
3081 };
3082
3083 static const char *intel_names_bnd[] = {
3084   "bnd0", "bnd1", "bnd2", "bnd3"
3085 };
3086
3087 static const char *att_names_bnd[] = {
3088   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3089 };
3090
3091 static const char **names_xmm;
3092 static const char *intel_names_xmm[] = {
3093   "xmm0", "xmm1", "xmm2", "xmm3",
3094   "xmm4", "xmm5", "xmm6", "xmm7",
3095   "xmm8", "xmm9", "xmm10", "xmm11",
3096   "xmm12", "xmm13", "xmm14", "xmm15",
3097   "xmm16", "xmm17", "xmm18", "xmm19",
3098   "xmm20", "xmm21", "xmm22", "xmm23",
3099   "xmm24", "xmm25", "xmm26", "xmm27",
3100   "xmm28", "xmm29", "xmm30", "xmm31"
3101 };
3102 static const char *att_names_xmm[] = {
3103   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3104   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3105   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3106   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3107   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3108   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3109   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3110   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3111 };
3112
3113 static const char **names_ymm;
3114 static const char *intel_names_ymm[] = {
3115   "ymm0", "ymm1", "ymm2", "ymm3",
3116   "ymm4", "ymm5", "ymm6", "ymm7",
3117   "ymm8", "ymm9", "ymm10", "ymm11",
3118   "ymm12", "ymm13", "ymm14", "ymm15",
3119   "ymm16", "ymm17", "ymm18", "ymm19",
3120   "ymm20", "ymm21", "ymm22", "ymm23",
3121   "ymm24", "ymm25", "ymm26", "ymm27",
3122   "ymm28", "ymm29", "ymm30", "ymm31"
3123 };
3124 static const char *att_names_ymm[] = {
3125   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3126   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3127   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3128   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3129   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3130   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3131   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3132   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3133 };
3134
3135 static const char **names_zmm;
3136 static const char *intel_names_zmm[] = {
3137   "zmm0", "zmm1", "zmm2", "zmm3",
3138   "zmm4", "zmm5", "zmm6", "zmm7",
3139   "zmm8", "zmm9", "zmm10", "zmm11",
3140   "zmm12", "zmm13", "zmm14", "zmm15",
3141   "zmm16", "zmm17", "zmm18", "zmm19",
3142   "zmm20", "zmm21", "zmm22", "zmm23",
3143   "zmm24", "zmm25", "zmm26", "zmm27",
3144   "zmm28", "zmm29", "zmm30", "zmm31"
3145 };
3146 static const char *att_names_zmm[] = {
3147   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3148   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3149   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3150   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3151   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3152   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3153   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3154   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3155 };
3156
3157 static const char **names_tmm;
3158 static const char *intel_names_tmm[] = {
3159   "tmm0", "tmm1", "tmm2", "tmm3",
3160   "tmm4", "tmm5", "tmm6", "tmm7"
3161 };
3162 static const char *att_names_tmm[] = {
3163   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3164   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3165 };
3166
3167 static const char **names_mask;
3168 static const char *intel_names_mask[] = {
3169   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3170 };
3171 static const char *att_names_mask[] = {
3172   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3173 };
3174
3175 static const char *names_rounding[] =
3176 {
3177   "{rn-sae}",
3178   "{rd-sae}",
3179   "{ru-sae}",
3180   "{rz-sae}"
3181 };
3182
3183 static const struct dis386 reg_table[][8] = {
3184   /* REG_80 */
3185   {
3186     { "addA",   { Ebh1, Ib }, 0 },
3187     { "orA",    { Ebh1, Ib }, 0 },
3188     { "adcA",   { Ebh1, Ib }, 0 },
3189     { "sbbA",   { Ebh1, Ib }, 0 },
3190     { "andA",   { Ebh1, Ib }, 0 },
3191     { "subA",   { Ebh1, Ib }, 0 },
3192     { "xorA",   { Ebh1, Ib }, 0 },
3193     { "cmpA",   { Eb, Ib }, 0 },
3194   },
3195   /* REG_81 */
3196   {
3197     { "addQ",   { Evh1, Iv }, 0 },
3198     { "orQ",    { Evh1, Iv }, 0 },
3199     { "adcQ",   { Evh1, Iv }, 0 },
3200     { "sbbQ",   { Evh1, Iv }, 0 },
3201     { "andQ",   { Evh1, Iv }, 0 },
3202     { "subQ",   { Evh1, Iv }, 0 },
3203     { "xorQ",   { Evh1, Iv }, 0 },
3204     { "cmpQ",   { Ev, Iv }, 0 },
3205   },
3206   /* REG_83 */
3207   {
3208     { "addQ",   { Evh1, sIb }, 0 },
3209     { "orQ",    { Evh1, sIb }, 0 },
3210     { "adcQ",   { Evh1, sIb }, 0 },
3211     { "sbbQ",   { Evh1, sIb }, 0 },
3212     { "andQ",   { Evh1, sIb }, 0 },
3213     { "subQ",   { Evh1, sIb }, 0 },
3214     { "xorQ",   { Evh1, sIb }, 0 },
3215     { "cmpQ",   { Ev, sIb }, 0 },
3216   },
3217   /* REG_8F */
3218   {
3219     { "popU",   { stackEv }, 0 },
3220     { XOP_8F_TABLE (XOP_09) },
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { Bad_Opcode },
3224     { XOP_8F_TABLE (XOP_09) },
3225   },
3226   /* REG_C0 */
3227   {
3228     { "rolA",   { Eb, Ib }, 0 },
3229     { "rorA",   { Eb, Ib }, 0 },
3230     { "rclA",   { Eb, Ib }, 0 },
3231     { "rcrA",   { Eb, Ib }, 0 },
3232     { "shlA",   { Eb, Ib }, 0 },
3233     { "shrA",   { Eb, Ib }, 0 },
3234     { "shlA",   { Eb, Ib }, 0 },
3235     { "sarA",   { Eb, Ib }, 0 },
3236   },
3237   /* REG_C1 */
3238   {
3239     { "rolQ",   { Ev, Ib }, 0 },
3240     { "rorQ",   { Ev, Ib }, 0 },
3241     { "rclQ",   { Ev, Ib }, 0 },
3242     { "rcrQ",   { Ev, Ib }, 0 },
3243     { "shlQ",   { Ev, Ib }, 0 },
3244     { "shrQ",   { Ev, Ib }, 0 },
3245     { "shlQ",   { Ev, Ib }, 0 },
3246     { "sarQ",   { Ev, Ib }, 0 },
3247   },
3248   /* REG_C6 */
3249   {
3250     { "movA",   { Ebh3, Ib }, 0 },
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257     { MOD_TABLE (MOD_C6_REG_7) },
3258   },
3259   /* REG_C7 */
3260   {
3261     { "movQ",   { Evh3, Iv }, 0 },
3262     { Bad_Opcode },
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { MOD_TABLE (MOD_C7_REG_7) },
3269   },
3270   /* REG_D0 */
3271   {
3272     { "rolA",   { Eb, I1 }, 0 },
3273     { "rorA",   { Eb, I1 }, 0 },
3274     { "rclA",   { Eb, I1 }, 0 },
3275     { "rcrA",   { Eb, I1 }, 0 },
3276     { "shlA",   { Eb, I1 }, 0 },
3277     { "shrA",   { Eb, I1 }, 0 },
3278     { "shlA",   { Eb, I1 }, 0 },
3279     { "sarA",   { Eb, I1 }, 0 },
3280   },
3281   /* REG_D1 */
3282   {
3283     { "rolQ",   { Ev, I1 }, 0 },
3284     { "rorQ",   { Ev, I1 }, 0 },
3285     { "rclQ",   { Ev, I1 }, 0 },
3286     { "rcrQ",   { Ev, I1 }, 0 },
3287     { "shlQ",   { Ev, I1 }, 0 },
3288     { "shrQ",   { Ev, I1 }, 0 },
3289     { "shlQ",   { Ev, I1 }, 0 },
3290     { "sarQ",   { Ev, I1 }, 0 },
3291   },
3292   /* REG_D2 */
3293   {
3294     { "rolA",   { Eb, CL }, 0 },
3295     { "rorA",   { Eb, CL }, 0 },
3296     { "rclA",   { Eb, CL }, 0 },
3297     { "rcrA",   { Eb, CL }, 0 },
3298     { "shlA",   { Eb, CL }, 0 },
3299     { "shrA",   { Eb, CL }, 0 },
3300     { "shlA",   { Eb, CL }, 0 },
3301     { "sarA",   { Eb, CL }, 0 },
3302   },
3303   /* REG_D3 */
3304   {
3305     { "rolQ",   { Ev, CL }, 0 },
3306     { "rorQ",   { Ev, CL }, 0 },
3307     { "rclQ",   { Ev, CL }, 0 },
3308     { "rcrQ",   { Ev, CL }, 0 },
3309     { "shlQ",   { Ev, CL }, 0 },
3310     { "shrQ",   { Ev, CL }, 0 },
3311     { "shlQ",   { Ev, CL }, 0 },
3312     { "sarQ",   { Ev, CL }, 0 },
3313   },
3314   /* REG_F6 */
3315   {
3316     { "testA",  { Eb, Ib }, 0 },
3317     { "testA",  { Eb, Ib }, 0 },
3318     { "notA",   { Ebh1 }, 0 },
3319     { "negA",   { Ebh1 }, 0 },
3320     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3321     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3322     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3323     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3324   },
3325   /* REG_F7 */
3326   {
3327     { "testQ",  { Ev, Iv }, 0 },
3328     { "testQ",  { Ev, Iv }, 0 },
3329     { "notQ",   { Evh1 }, 0 },
3330     { "negQ",   { Evh1 }, 0 },
3331     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3332     { "imulQ",  { Ev }, 0 },
3333     { "divQ",   { Ev }, 0 },
3334     { "idivQ",  { Ev }, 0 },
3335   },
3336   /* REG_FE */
3337   {
3338     { "incA",   { Ebh1 }, 0 },
3339     { "decA",   { Ebh1 }, 0 },
3340   },
3341   /* REG_FF */
3342   {
3343     { "incQ",   { Evh1 }, 0 },
3344     { "decQ",   { Evh1 }, 0 },
3345     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3346     { MOD_TABLE (MOD_FF_REG_3) },
3347     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3348     { MOD_TABLE (MOD_FF_REG_5) },
3349     { "pushU",  { stackEv }, 0 },
3350     { Bad_Opcode },
3351   },
3352   /* REG_0F00 */
3353   {
3354     { "sldtD",  { Sv }, 0 },
3355     { "strD",   { Sv }, 0 },
3356     { "lldt",   { Ew }, 0 },
3357     { "ltr",    { Ew }, 0 },
3358     { "verr",   { Ew }, 0 },
3359     { "verw",   { Ew }, 0 },
3360     { Bad_Opcode },
3361     { Bad_Opcode },
3362   },
3363   /* REG_0F01 */
3364   {
3365     { MOD_TABLE (MOD_0F01_REG_0) },
3366     { MOD_TABLE (MOD_0F01_REG_1) },
3367     { MOD_TABLE (MOD_0F01_REG_2) },
3368     { MOD_TABLE (MOD_0F01_REG_3) },
3369     { "smswD",  { Sv }, 0 },
3370     { MOD_TABLE (MOD_0F01_REG_5) },
3371     { "lmsw",   { Ew }, 0 },
3372     { MOD_TABLE (MOD_0F01_REG_7) },
3373   },
3374   /* REG_0F0D */
3375   {
3376     { "prefetch",       { Mb }, 0 },
3377     { "prefetchw",      { Mb }, 0 },
3378     { "prefetchwt1",    { Mb }, 0 },
3379     { "prefetch",       { Mb }, 0 },
3380     { "prefetch",       { Mb }, 0 },
3381     { "prefetch",       { Mb }, 0 },
3382     { "prefetch",       { Mb }, 0 },
3383     { "prefetch",       { Mb }, 0 },
3384   },
3385   /* REG_0F18 */
3386   {
3387     { MOD_TABLE (MOD_0F18_REG_0) },
3388     { MOD_TABLE (MOD_0F18_REG_1) },
3389     { MOD_TABLE (MOD_0F18_REG_2) },
3390     { MOD_TABLE (MOD_0F18_REG_3) },
3391     { MOD_TABLE (MOD_0F18_REG_4) },
3392     { MOD_TABLE (MOD_0F18_REG_5) },
3393     { MOD_TABLE (MOD_0F18_REG_6) },
3394     { MOD_TABLE (MOD_0F18_REG_7) },
3395   },
3396   /* REG_0F1C_P_0_MOD_0 */
3397   {
3398     { "cldemote",       { Mb }, 0 },
3399     { "nopQ",           { Ev }, 0 },
3400     { "nopQ",           { Ev }, 0 },
3401     { "nopQ",           { Ev }, 0 },
3402     { "nopQ",           { Ev }, 0 },
3403     { "nopQ",           { Ev }, 0 },
3404     { "nopQ",           { Ev }, 0 },
3405     { "nopQ",           { Ev }, 0 },
3406   },
3407   /* REG_0F1E_P_1_MOD_3 */
3408   {
3409     { "nopQ",           { Ev }, 0 },
3410     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3411     { "nopQ",           { Ev }, 0 },
3412     { "nopQ",           { Ev }, 0 },
3413     { "nopQ",           { Ev }, 0 },
3414     { "nopQ",           { Ev }, 0 },
3415     { "nopQ",           { Ev }, 0 },
3416     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3417   },
3418   /* REG_0F71 */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { MOD_TABLE (MOD_0F71_REG_2) },
3423     { Bad_Opcode },
3424     { MOD_TABLE (MOD_0F71_REG_4) },
3425     { Bad_Opcode },
3426     { MOD_TABLE (MOD_0F71_REG_6) },
3427   },
3428   /* REG_0F72 */
3429   {
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { MOD_TABLE (MOD_0F72_REG_2) },
3433     { Bad_Opcode },
3434     { MOD_TABLE (MOD_0F72_REG_4) },
3435     { Bad_Opcode },
3436     { MOD_TABLE (MOD_0F72_REG_6) },
3437   },
3438   /* REG_0F73 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { MOD_TABLE (MOD_0F73_REG_2) },
3443     { MOD_TABLE (MOD_0F73_REG_3) },
3444     { Bad_Opcode },
3445     { Bad_Opcode },
3446     { MOD_TABLE (MOD_0F73_REG_6) },
3447     { MOD_TABLE (MOD_0F73_REG_7) },
3448   },
3449   /* REG_0FA6 */
3450   {
3451     { "montmul",        { { OP_0f07, 0 } }, 0 },
3452     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3453     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3454   },
3455   /* REG_0FA7 */
3456   {
3457     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3458     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3459     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3460     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3461     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3462     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3463   },
3464   /* REG_0FAE */
3465   {
3466     { MOD_TABLE (MOD_0FAE_REG_0) },
3467     { MOD_TABLE (MOD_0FAE_REG_1) },
3468     { MOD_TABLE (MOD_0FAE_REG_2) },
3469     { MOD_TABLE (MOD_0FAE_REG_3) },
3470     { MOD_TABLE (MOD_0FAE_REG_4) },
3471     { MOD_TABLE (MOD_0FAE_REG_5) },
3472     { MOD_TABLE (MOD_0FAE_REG_6) },
3473     { MOD_TABLE (MOD_0FAE_REG_7) },
3474   },
3475   /* REG_0FBA */
3476   {
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { Bad_Opcode },
3480     { Bad_Opcode },
3481     { "btQ",    { Ev, Ib }, 0 },
3482     { "btsQ",   { Evh1, Ib }, 0 },
3483     { "btrQ",   { Evh1, Ib }, 0 },
3484     { "btcQ",   { Evh1, Ib }, 0 },
3485   },
3486   /* REG_0FC7 */
3487   {
3488     { Bad_Opcode },
3489     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_0FC7_REG_3) },
3492     { MOD_TABLE (MOD_0FC7_REG_4) },
3493     { MOD_TABLE (MOD_0FC7_REG_5) },
3494     { MOD_TABLE (MOD_0FC7_REG_6) },
3495     { MOD_TABLE (MOD_0FC7_REG_7) },
3496   },
3497   /* REG_VEX_0F71 */
3498   {
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3502     { Bad_Opcode },
3503     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3504     { Bad_Opcode },
3505     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3506   },
3507   /* REG_VEX_0F72 */
3508   {
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3512     { Bad_Opcode },
3513     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3516   },
3517   /* REG_VEX_0F73 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3522     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3526     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3527   },
3528   /* REG_VEX_0FAE */
3529   {
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3533     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3534   },
3535   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3536   {
3537     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3538   },
3539   /* REG_VEX_0F38F3 */
3540   {
3541     { Bad_Opcode },
3542     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3543     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3544     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3545   },
3546   /* REG_0FXOP_09_01_L_0 */
3547   {
3548     { Bad_Opcode },
3549     { "blcfill",        { VexGdq, Edq }, 0 },
3550     { "blsfill",        { VexGdq, Edq }, 0 },
3551     { "blcs",   { VexGdq, Edq }, 0 },
3552     { "tzmsk",  { VexGdq, Edq }, 0 },
3553     { "blcic",  { VexGdq, Edq }, 0 },
3554     { "blsic",  { VexGdq, Edq }, 0 },
3555     { "t1mskc", { VexGdq, Edq }, 0 },
3556   },
3557   /* REG_0FXOP_09_02_L_0 */
3558   {
3559     { Bad_Opcode },
3560     { "blcmsk", { VexGdq, Edq }, 0 },
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "blci",   { VexGdq, Edq }, 0 },
3566   },
3567   /* REG_0FXOP_09_12_M_1_L_0 */
3568   {
3569     { "llwpcb", { Edq }, 0 },
3570     { "slwpcb", { Edq }, 0 },
3571   },
3572   /* REG_0FXOP_0A_12_L_0 */
3573   {
3574     { "lwpins", { VexGdq, Ed, Id }, 0 },
3575     { "lwpval", { VexGdq, Ed, Id }, 0 },
3576   },
3577
3578 #include "i386-dis-evex-reg.h"
3579 };
3580
3581 static const struct dis386 prefix_table[][4] = {
3582   /* PREFIX_90 */
3583   {
3584     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3585     { "pause", { XX }, 0 },
3586     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3587     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3588   },
3589
3590   /* PREFIX_0F01_REG_3_RM_1 */
3591   {
3592     { "vmmcall",        { Skip_MODRM }, 0 },
3593     { "vmgexit",        { Skip_MODRM }, 0 },
3594     { Bad_Opcode },
3595     { "vmgexit",        { Skip_MODRM }, 0 },
3596   },
3597
3598   /* PREFIX_0F01_REG_5_MOD_0 */
3599   {
3600     { Bad_Opcode },
3601     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3602   },
3603
3604   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3605   {
3606     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3607     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3608     { Bad_Opcode },
3609     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3610   },
3611
3612   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3613   {
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3618   },
3619
3620   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3621   {
3622     { Bad_Opcode },
3623     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3624   },
3625
3626   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3627   {
3628     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3629     { "mcommit",        { Skip_MODRM }, 0 },
3630   },
3631
3632   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3633   {
3634     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3635   },
3636
3637   /* PREFIX_0F09 */
3638   {
3639     { "wbinvd",   { XX }, 0 },
3640     { "wbnoinvd", { XX }, 0 },
3641   },
3642
3643   /* PREFIX_0F10 */
3644   {
3645     { "movups", { XM, EXx }, PREFIX_OPCODE },
3646     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3647     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3648     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3649   },
3650
3651   /* PREFIX_0F11 */
3652   {
3653     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3654     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3655     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3656     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3657   },
3658
3659   /* PREFIX_0F12 */
3660   {
3661     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3662     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3663     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3664     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3665   },
3666
3667   /* PREFIX_0F16 */
3668   {
3669     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3670     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3671     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3672   },
3673
3674   /* PREFIX_0F1A */
3675   {
3676     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3677     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3678     { "bndmov", { Gbnd, Ebnd }, 0 },
3679     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3680   },
3681
3682   /* PREFIX_0F1B */
3683   {
3684     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3685     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3686     { "bndmov", { EbndS, Gbnd }, 0 },
3687     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3688   },
3689
3690   /* PREFIX_0F1C */
3691   {
3692     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3693     { "nopQ",   { Ev }, PREFIX_OPCODE },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695     { "nopQ",   { Ev }, PREFIX_OPCODE },
3696   },
3697
3698   /* PREFIX_0F1E */
3699   {
3700     { "nopQ",   { Ev }, PREFIX_OPCODE },
3701     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3702     { "nopQ",   { Ev }, PREFIX_OPCODE },
3703     { "nopQ",   { Ev }, PREFIX_OPCODE },
3704   },
3705
3706   /* PREFIX_0F2A */
3707   {
3708     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3709     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3710     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3711     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3712   },
3713
3714   /* PREFIX_0F2B */
3715   {
3716     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3717     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3718     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3719     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3720   },
3721
3722   /* PREFIX_0F2C */
3723   {
3724     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3725     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3726     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3727     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3728   },
3729
3730   /* PREFIX_0F2D */
3731   {
3732     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3733     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3734     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3735     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3736   },
3737
3738   /* PREFIX_0F2E */
3739   {
3740     { "ucomiss",{ XM, EXd }, 0 },
3741     { Bad_Opcode },
3742     { "ucomisd",{ XM, EXq }, 0 },
3743   },
3744
3745   /* PREFIX_0F2F */
3746   {
3747     { "comiss", { XM, EXd }, 0 },
3748     { Bad_Opcode },
3749     { "comisd", { XM, EXq }, 0 },
3750   },
3751
3752   /* PREFIX_0F51 */
3753   {
3754     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3755     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3756     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3757     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F52 */
3761   {
3762     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3763     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3764   },
3765
3766   /* PREFIX_0F53 */
3767   {
3768     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3769     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3770   },
3771
3772   /* PREFIX_0F58 */
3773   {
3774     { "addps", { XM, EXx }, PREFIX_OPCODE },
3775     { "addss", { XM, EXd }, PREFIX_OPCODE },
3776     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3777     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3778   },
3779
3780   /* PREFIX_0F59 */
3781   {
3782     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3783     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3784     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3785     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F5A */
3789   {
3790     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3791     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3792     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3793     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3794   },
3795
3796   /* PREFIX_0F5B */
3797   {
3798     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3799     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3800     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F5C */
3804   {
3805     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5D */
3812   {
3813     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3814     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3815     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3816     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5E */
3820   {
3821     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3822     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3823     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3824     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F5F */
3828   {
3829     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3830     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3831     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3832     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F60 */
3836   {
3837     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3838     { Bad_Opcode },
3839     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F61 */
3843   {
3844     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3845     { Bad_Opcode },
3846     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F62 */
3850   {
3851     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3852     { Bad_Opcode },
3853     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F6C */
3857   {
3858     { Bad_Opcode },
3859     { Bad_Opcode },
3860     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F6D */
3864   {
3865     { Bad_Opcode },
3866     { Bad_Opcode },
3867     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F6F */
3871   {
3872     { "movq",   { MX, EM }, PREFIX_OPCODE },
3873     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3874     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F70 */
3878   {
3879     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3880     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3881     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3882     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F73_REG_3 */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "psrldq", { XS, Ib }, 0 },
3890   },
3891
3892   /* PREFIX_0F73_REG_7 */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "pslldq", { XS, Ib }, 0 },
3897   },
3898
3899   /* PREFIX_0F78 */
3900   {
3901     {"vmread",  { Em, Gm }, 0 },
3902     { Bad_Opcode },
3903     {"extrq",   { XS, Ib, Ib }, 0 },
3904     {"insertq", { XM, XS, Ib, Ib }, 0 },
3905   },
3906
3907   /* PREFIX_0F79 */
3908   {
3909     {"vmwrite", { Gm, Em }, 0 },
3910     { Bad_Opcode },
3911     {"extrq",   { XM, XS }, 0 },
3912     {"insertq", { XM, XS }, 0 },
3913   },
3914
3915   /* PREFIX_0F7C */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3920     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3921   },
3922
3923   /* PREFIX_0F7D */
3924   {
3925     { Bad_Opcode },
3926     { Bad_Opcode },
3927     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3928     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3929   },
3930
3931   /* PREFIX_0F7E */
3932   {
3933     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3934     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3935     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0F7F */
3939   {
3940     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3941     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3942     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3943   },
3944
3945   /* PREFIX_0FAE_REG_0_MOD_3 */
3946   {
3947     { Bad_Opcode },
3948     { "rdfsbase", { Ev }, 0 },
3949   },
3950
3951   /* PREFIX_0FAE_REG_1_MOD_3 */
3952   {
3953     { Bad_Opcode },
3954     { "rdgsbase", { Ev }, 0 },
3955   },
3956
3957   /* PREFIX_0FAE_REG_2_MOD_3 */
3958   {
3959     { Bad_Opcode },
3960     { "wrfsbase", { Ev }, 0 },
3961   },
3962
3963   /* PREFIX_0FAE_REG_3_MOD_3 */
3964   {
3965     { Bad_Opcode },
3966     { "wrgsbase", { Ev }, 0 },
3967   },
3968
3969   /* PREFIX_0FAE_REG_4_MOD_0 */
3970   {
3971     { "xsave",  { FXSAVE }, 0 },
3972     { "ptwrite%LQ", { Edq }, 0 },
3973   },
3974
3975   /* PREFIX_0FAE_REG_4_MOD_3 */
3976   {
3977     { Bad_Opcode },
3978     { "ptwrite%LQ", { Edq }, 0 },
3979   },
3980
3981   /* PREFIX_0FAE_REG_5_MOD_0 */
3982   {
3983     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0FAE_REG_5_MOD_3 */
3987   {
3988     { "lfence",         { Skip_MODRM }, 0 },
3989     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3990   },
3991
3992   /* PREFIX_0FAE_REG_6_MOD_0 */
3993   {
3994     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3995     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3996     { "clwb",   { Mb }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0FAE_REG_6_MOD_3 */
4000   {
4001     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4002     { "umonitor",       { Eva }, PREFIX_OPCODE },
4003     { "tpause", { Edq }, PREFIX_OPCODE },
4004     { "umwait", { Edq }, PREFIX_OPCODE },
4005   },
4006
4007   /* PREFIX_0FAE_REG_7_MOD_0 */
4008   {
4009     { "clflush",        { Mb }, 0 },
4010     { Bad_Opcode },
4011     { "clflushopt",     { Mb }, 0 },
4012   },
4013
4014   /* PREFIX_0FB8 */
4015   {
4016     { Bad_Opcode },
4017     { "popcntS", { Gv, Ev }, 0 },
4018   },
4019
4020   /* PREFIX_0FBC */
4021   {
4022     { "bsfS",   { Gv, Ev }, 0 },
4023     { "tzcntS", { Gv, Ev }, 0 },
4024     { "bsfS",   { Gv, Ev }, 0 },
4025   },
4026
4027   /* PREFIX_0FBD */
4028   {
4029     { "bsrS",   { Gv, Ev }, 0 },
4030     { "lzcntS", { Gv, Ev }, 0 },
4031     { "bsrS",   { Gv, Ev }, 0 },
4032   },
4033
4034   /* PREFIX_0FC2 */
4035   {
4036     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4037     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4038     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4039     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4040   },
4041
4042   /* PREFIX_0FC3_MOD_0 */
4043   {
4044     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0FC7_REG_6_MOD_0 */
4048   {
4049     { "vmptrld",{ Mq }, 0 },
4050     { "vmxon",  { Mq }, 0 },
4051     { "vmclear",{ Mq }, 0 },
4052   },
4053
4054   /* PREFIX_0FC7_REG_6_MOD_3 */
4055   {
4056     { "rdrand", { Ev }, 0 },
4057     { Bad_Opcode },
4058     { "rdrand", { Ev }, 0 }
4059   },
4060
4061   /* PREFIX_0FC7_REG_7_MOD_3 */
4062   {
4063     { "rdseed", { Ev }, 0 },
4064     { "rdpid",  { Em }, 0 },
4065     { "rdseed", { Ev }, 0 },
4066   },
4067
4068   /* PREFIX_0FD0 */
4069   {
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { "addsubpd", { XM, EXx }, 0 },
4073     { "addsubps", { XM, EXx }, 0 },
4074   },
4075
4076   /* PREFIX_0FD6 */
4077   {
4078     { Bad_Opcode },
4079     { "movq2dq",{ XM, MS }, 0 },
4080     { "movq",   { EXqS, XM }, 0 },
4081     { "movdq2q",{ MX, XS }, 0 },
4082   },
4083
4084   /* PREFIX_0FE6 */
4085   {
4086     { Bad_Opcode },
4087     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4088     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4089     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4090   },
4091
4092   /* PREFIX_0FE7 */
4093   {
4094     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4095     { Bad_Opcode },
4096     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4097   },
4098
4099   /* PREFIX_0FF0 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4105   },
4106
4107   /* PREFIX_0FF7 */
4108   {
4109     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4110     { Bad_Opcode },
4111     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0F3810 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F3814 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4126   },
4127
4128   /* PREFIX_0F3815 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3817 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3820 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3821 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3822 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3823 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3824 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3825 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F3828 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F3829 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F382A */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4203   },
4204
4205   /* PREFIX_0F382B */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3830 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3831 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3832 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3833 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3834 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3835 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3837 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3838 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3839 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F383A */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F383B */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F383C */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383D */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F383E */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F383F */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3840 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3841 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3880 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F3881 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F3882 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F38C8 */
4353   {
4354     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F38C9 */
4358   {
4359     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38CA */
4363   {
4364     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F38CB */
4368   {
4369     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F38CC */
4373   {
4374     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38CD */
4378   {
4379     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38CF */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38DB */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38DC */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38DD */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38DE */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38DF */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38F0 */
4425   {
4426     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4427     { Bad_Opcode },
4428     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4429     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38F1 */
4433   {
4434     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4435     { Bad_Opcode },
4436     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4437     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F38F5 */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4445   },
4446
4447   /* PREFIX_0F38F6 */
4448   {
4449     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4450     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4451     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4452     { Bad_Opcode },
4453   },
4454
4455   /* PREFIX_0F38F8 */
4456   {
4457     { Bad_Opcode },
4458     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4459     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4460     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4461   },
4462
4463   /* PREFIX_0F38F9 */
4464   {
4465     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4466   },
4467
4468   /* PREFIX_0F3A08 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A09 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0A */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A0B */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A0C */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A0D */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A0E */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A14 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A15 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A16 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A17 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A20 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A21 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A22 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A40 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A41 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A42 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A44 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A60 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A61 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A62 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A63 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3ACC */
4623   {
4624     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3ACE */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F3ACF */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4639   },
4640
4641   /* PREFIX_0F3ADF */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_VEX_0F10 */
4649   {
4650     { "vmovups",        { XM, EXx }, 0 },
4651     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4652     { "vmovupd",        { XM, EXx }, 0 },
4653     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4654   },
4655
4656   /* PREFIX_VEX_0F11 */
4657   {
4658     { "vmovups",        { EXxS, XM }, 0 },
4659     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4660     { "vmovupd",        { EXxS, XM }, 0 },
4661     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4662   },
4663
4664   /* PREFIX_VEX_0F12 */
4665   {
4666     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4667     { "vmovsldup",      { XM, EXx }, 0 },
4668     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4669     { "vmovddup",       { XM, EXymmq }, 0 },
4670   },
4671
4672   /* PREFIX_VEX_0F16 */
4673   {
4674     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4675     { "vmovshdup",      { XM, EXx }, 0 },
4676     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F2A */
4680   {
4681     { Bad_Opcode },
4682     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4683     { Bad_Opcode },
4684     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F2C */
4688   {
4689     { Bad_Opcode },
4690     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4691     { Bad_Opcode },
4692     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F2D */
4696   {
4697     { Bad_Opcode },
4698     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4699     { Bad_Opcode },
4700     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4701   },
4702
4703   /* PREFIX_VEX_0F2E */
4704   {
4705     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4706     { Bad_Opcode },
4707     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4708   },
4709
4710   /* PREFIX_VEX_0F2F */
4711   {
4712     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4713     { Bad_Opcode },
4714     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4715   },
4716
4717   /* PREFIX_VEX_0F41 */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F42 */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F44 */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F45 */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F46 */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F47 */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F4A */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F4B */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F51 */
4774   {
4775     { "vsqrtps",        { XM, EXx }, 0 },
4776     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4777     { "vsqrtpd",        { XM, EXx }, 0 },
4778     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4779   },
4780
4781   /* PREFIX_VEX_0F52 */
4782   {
4783     { "vrsqrtps",       { XM, EXx }, 0 },
4784     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4785   },
4786
4787   /* PREFIX_VEX_0F53 */
4788   {
4789     { "vrcpps",         { XM, EXx }, 0 },
4790     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4791   },
4792
4793   /* PREFIX_VEX_0F58 */
4794   {
4795     { "vaddps",         { XM, Vex, EXx }, 0 },
4796     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4797     { "vaddpd",         { XM, Vex, EXx }, 0 },
4798     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4799   },
4800
4801   /* PREFIX_VEX_0F59 */
4802   {
4803     { "vmulps",         { XM, Vex, EXx }, 0 },
4804     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4805     { "vmulpd",         { XM, Vex, EXx }, 0 },
4806     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F5A */
4810   {
4811     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4812     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4813     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4814     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F5B */
4818   {
4819     { "vcvtdq2ps",      { XM, EXx }, 0 },
4820     { "vcvttps2dq",     { XM, EXx }, 0 },
4821     { "vcvtps2dq",      { XM, EXx }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F5C */
4825   {
4826     { "vsubps",         { XM, Vex, EXx }, 0 },
4827     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4828     { "vsubpd",         { XM, Vex, EXx }, 0 },
4829     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F5D */
4833   {
4834     { "vminps",         { XM, Vex, EXx }, 0 },
4835     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4836     { "vminpd",         { XM, Vex, EXx }, 0 },
4837     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F5E */
4841   {
4842     { "vdivps",         { XM, Vex, EXx }, 0 },
4843     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4844     { "vdivpd",         { XM, Vex, EXx }, 0 },
4845     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4846   },
4847
4848   /* PREFIX_VEX_0F5F */
4849   {
4850     { "vmaxps",         { XM, Vex, EXx }, 0 },
4851     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4852     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4853     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F60 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F61 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F62 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F63 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F64 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F65 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F66 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F67 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F68 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F69 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F6A */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F6B */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F6C */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F6D */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F6E */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F6F */
4962   {
4963     { Bad_Opcode },
4964     { "vmovdqu",        { XM, EXx }, 0 },
4965     { "vmovdqa",        { XM, EXx }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F70 */
4969   {
4970     { Bad_Opcode },
4971     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4972     { "vpshufd",        { XM, EXx, Ib }, 0 },
4973     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F71_REG_2 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4981   },
4982
4983   /* PREFIX_VEX_0F71_REG_4 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { "vpsraw",         { Vex, XS, Ib }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F71_REG_6 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { "vpsllw",         { Vex, XS, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F72_REG_2 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpsrld",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F72_REG_4 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpsrad",         { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F72_REG_6 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpslld",         { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F73_REG_2 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F73_REG_3 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F73_REG_6 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpsllq",         { Vex, XS, Ib }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F73_REG_7 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpslldq",        { Vex, XS, Ib }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F74 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F75 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F76 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F77 */
5068   {
5069     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5070   },
5071
5072   /* PREFIX_VEX_0F7C */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5077     { "vhaddps",        { XM, Vex, EXx }, 0 },
5078   },
5079
5080   /* PREFIX_VEX_0F7D */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5085     { "vhsubps",        { XM, Vex, EXx }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0F7E */
5089   {
5090     { Bad_Opcode },
5091     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5092     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F7F */
5096   {
5097     { Bad_Opcode },
5098     { "vmovdqu",        { EXxS, XM }, 0 },
5099     { "vmovdqa",        { EXxS, XM }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0F90 */
5103   {
5104     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F91 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F92 */
5117   {
5118     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5121     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5122   },
5123
5124   /* PREFIX_VEX_0F93 */
5125   {
5126     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5129     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5130   },
5131
5132   /* PREFIX_VEX_0F98 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F99 */
5140   {
5141     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FC2 */
5147   {
5148     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5149     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5150     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5151     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5152   },
5153
5154   /* PREFIX_VEX_0FC4 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0FC5 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0FD0 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5173     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FD1 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5181   },
5182
5183   /* PREFIX_VEX_0FD2 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5188   },
5189
5190   /* PREFIX_VEX_0FD3 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FD4 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vpaddq",         { XM, Vex, EXx }, 0 },
5202   },
5203
5204   /* PREFIX_VEX_0FD5 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpmullw",        { XM, Vex, EXx }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FD6 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FD7 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FD8 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FD9 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FDA */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpminub",        { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FDB */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpand",          { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FDC */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FDD */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FDE */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FDF */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpandn",         { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FE0 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpavgb",         { XM, Vex, EXx }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FE1 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FE2 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE3 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpavgw",         { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FE4 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE5 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5321   },
5322
5323   /* PREFIX_VEX_0FE6 */
5324   {
5325     { Bad_Opcode },
5326     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5327     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5328     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FE7 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FE8 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FE9 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FEA */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpminsw",        { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FEB */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpor",           { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FEC */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FED */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FEE */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0FEF */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpxor",          { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FF0 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5400   },
5401
5402   /* PREFIX_VEX_0FF1 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FF2 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF3 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5421   },
5422
5423   /* PREFIX_VEX_0FF4 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5428   },
5429
5430   /* PREFIX_VEX_0FF5 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5435   },
5436
5437   /* PREFIX_VEX_0FF6 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5442   },
5443
5444   /* PREFIX_VEX_0FF7 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FF8 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpsubb",         { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FF9 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsubw",         { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FFA */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { "vpsubd",         { XM, Vex, EXx }, 0 },
5470   },
5471
5472   /* PREFIX_VEX_0FFB */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpsubq",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FFC */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpaddb",         { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0FFD */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vpaddw",         { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0FFE */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vpaddd",         { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0F3800 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vpshufb",        { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0F3801 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vphaddw",        { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0F3802 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vphaddd",        { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3803 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3804 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3805 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vphsubw",        { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3806 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vphsubd",        { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3807 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F3808 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vpsignb",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F3809 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vpsignw",        { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F380A */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vpsignd",        { XM, Vex, EXx }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F380B */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5582   },
5583
5584   /* PREFIX_VEX_0F380C */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F380D */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F380E */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F380F */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3813 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3816 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3817 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { "vptest",         { XM, EXx }, 0 },
5631   },
5632
5633   /* PREFIX_VEX_0F3818 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3819 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F381A */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F381C */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vpabsb",         { XM, EXx }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F381D */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vpabsw",         { XM, EXx }, 0 },
5666   },
5667
5668   /* PREFIX_VEX_0F381E */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vpabsd",         { XM, EXx }, 0 },
5673   },
5674
5675   /* PREFIX_VEX_0F3820 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F3821 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F3822 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3823 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3824 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F3825 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F3828 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F3829 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5729   },
5730
5731   /* PREFIX_VEX_0F382A */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F382B */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5743   },
5744
5745   /* PREFIX_VEX_0F382C */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F382D */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F382E */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F382F */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3830 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5778   },
5779
5780   /* PREFIX_VEX_0F3831 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5785   },
5786
5787   /* PREFIX_VEX_0F3832 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5792   },
5793
5794   /* PREFIX_VEX_0F3833 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3834 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5806   },
5807
5808   /* PREFIX_VEX_0F3835 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5813   },
5814
5815   /* PREFIX_VEX_0F3836 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3837 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F3838 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpminsb",        { XM, Vex, EXx }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F3839 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpminsd",        { XM, Vex, EXx }, 0 },
5841   },
5842
5843   /* PREFIX_VEX_0F383A */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpminuw",        { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F383B */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpminud",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F383C */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F383D */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F383E */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F383F */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F3840 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vpmulld",        { XM, Vex, EXx }, 0 },
5890   },
5891
5892   /* PREFIX_VEX_0F3841 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F3845 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5904   },
5905
5906   /* PREFIX_VEX_0F3846 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F3847 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5918   },
5919
5920   /* PREFIX_VEX_0F3849_X86_64 */
5921   {
5922     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5925     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5926   },
5927
5928   /* PREFIX_VEX_0F384B_X86_64 */
5929   {
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5932     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5933     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5934   },
5935
5936   /* PREFIX_VEX_0F3858 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5941   },
5942
5943   /* PREFIX_VEX_0F3859 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F385A */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F385C_X86_64 */
5958   {
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5961     { Bad_Opcode },
5962   },
5963
5964   /* PREFIX_VEX_0F385E_X86_64 */
5965   {
5966     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5967     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5968     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5969     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5970   },
5971
5972   /* PREFIX_VEX_0F3878 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3879 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F388C */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F388E */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3890 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6005   },
6006
6007   /* PREFIX_VEX_0F3891 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6012   },
6013
6014   /* PREFIX_VEX_0F3892 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6019   },
6020
6021   /* PREFIX_VEX_0F3893 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6026   },
6027
6028   /* PREFIX_VEX_0F3896 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6033   },
6034
6035   /* PREFIX_VEX_0F3897 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6040   },
6041
6042   /* PREFIX_VEX_0F3898 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6047   },
6048
6049   /* PREFIX_VEX_0F3899 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F389A */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6061   },
6062
6063   /* PREFIX_VEX_0F389B */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F389C */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F389D */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F389E */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F389F */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38A6 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6103     { Bad_Opcode },
6104   },
6105
6106   /* PREFIX_VEX_0F38A7 */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6111   },
6112
6113   /* PREFIX_VEX_0F38A8 */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38A9 */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38AA */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6132   },
6133
6134   /* PREFIX_VEX_0F38AB */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F38AC */
6142   {
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6146   },
6147
6148   /* PREFIX_VEX_0F38AD */
6149   {
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6153   },
6154
6155   /* PREFIX_VEX_0F38AE */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6160   },
6161
6162   /* PREFIX_VEX_0F38AF */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6167   },
6168
6169   /* PREFIX_VEX_0F38B6 */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6174   },
6175
6176   /* PREFIX_VEX_0F38B7 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6181   },
6182
6183   /* PREFIX_VEX_0F38B8 */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6188   },
6189
6190   /* PREFIX_VEX_0F38B9 */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6195   },
6196
6197   /* PREFIX_VEX_0F38BA */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6202   },
6203
6204   /* PREFIX_VEX_0F38BB */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6209   },
6210
6211   /* PREFIX_VEX_0F38BC */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F38BD */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F38BE */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F38BF */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F38CF */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6244   },
6245
6246   /* PREFIX_VEX_0F38DB */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6251   },
6252
6253   /* PREFIX_VEX_0F38DC */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vaesenc",        { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38DD */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38DE */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vaesdec",        { XM, Vex, EXx }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38DF */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38F2 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_1 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F3_REG_2 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6294   },
6295
6296   /* PREFIX_VEX_0F38F3_REG_3 */
6297   {
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F5 */
6302   {
6303     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F6 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F38F7 */
6318   {
6319     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6320     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6321     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6322     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A00 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A01 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A02 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A04 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A05 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A06 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6365   },
6366
6367   /* PREFIX_VEX_0F3A08 */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vroundps",       { XM, EXx, Ib }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F3A09 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { "vroundpd",       { XM, EXx, Ib }, 0 },
6379   },
6380
6381   /* PREFIX_VEX_0F3A0A */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6386   },
6387
6388   /* PREFIX_VEX_0F3A0B */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6393   },
6394
6395   /* PREFIX_VEX_0F3A0C */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F3A0D */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F3A0E */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6414   },
6415
6416   /* PREFIX_VEX_0F3A0F */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6421   },
6422
6423   /* PREFIX_VEX_0F3A14 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A15 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A16 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A17 */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A18 */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6456   },
6457
6458   /* PREFIX_VEX_0F3A19 */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A1D */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A20 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A21 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A22 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A30 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A31 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A32 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A33 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A38 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A39 */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A40 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6540   },
6541
6542   /* PREFIX_VEX_0F3A41 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A42 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6554   },
6555
6556   /* PREFIX_VEX_0F3A44 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6561   },
6562
6563   /* PREFIX_VEX_0F3A46 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A48 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6575   },
6576
6577   /* PREFIX_VEX_0F3A49 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6582   },
6583
6584   /* PREFIX_VEX_0F3A4A */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A4B */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A4C */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A5C */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6610   },
6611
6612   /* PREFIX_VEX_0F3A5D */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6617   },
6618
6619   /* PREFIX_VEX_0F3A5E */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6624   },
6625
6626   /* PREFIX_VEX_0F3A5F */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6631   },
6632
6633   /* PREFIX_VEX_0F3A60 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6638     { Bad_Opcode },
6639   },
6640
6641   /* PREFIX_VEX_0F3A61 */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3A62 */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6653   },
6654
6655   /* PREFIX_VEX_0F3A63 */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6660   },
6661
6662   /* PREFIX_VEX_0F3A68 */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6667   },
6668
6669   /* PREFIX_VEX_0F3A69 */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6674   },
6675
6676   /* PREFIX_VEX_0F3A6A */
6677   {
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6681   },
6682
6683   /* PREFIX_VEX_0F3A6B */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6688   },
6689
6690   /* PREFIX_VEX_0F3A6C */
6691   {
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6695   },
6696
6697   /* PREFIX_VEX_0F3A6D */
6698   {
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6702   },
6703
6704   /* PREFIX_VEX_0F3A6E */
6705   {
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6709   },
6710
6711   /* PREFIX_VEX_0F3A6F */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6716   },
6717
6718   /* PREFIX_VEX_0F3A78 */
6719   {
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6723   },
6724
6725   /* PREFIX_VEX_0F3A79 */
6726   {
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6730   },
6731
6732   /* PREFIX_VEX_0F3A7A */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6737   },
6738
6739   /* PREFIX_VEX_0F3A7B */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7C */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6751     { Bad_Opcode },
6752   },
6753
6754   /* PREFIX_VEX_0F3A7D */
6755   {
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6759   },
6760
6761   /* PREFIX_VEX_0F3A7E */
6762   {
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6766   },
6767
6768   /* PREFIX_VEX_0F3A7F */
6769   {
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6773   },
6774
6775   /* PREFIX_VEX_0F3ACE */
6776   {
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6780   },
6781
6782   /* PREFIX_VEX_0F3ACF */
6783   {
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6787   },
6788
6789   /* PREFIX_VEX_0F3ADF */
6790   {
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6794   },
6795
6796   /* PREFIX_VEX_0F3AF0 */
6797   {
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6802   },
6803
6804 #include "i386-dis-evex-prefix.h"
6805 };
6806
6807 static const struct dis386 x86_64_table[][2] = {
6808   /* X86_64_06 */
6809   {
6810     { "pushP", { es }, 0 },
6811   },
6812
6813   /* X86_64_07 */
6814   {
6815     { "popP", { es }, 0 },
6816   },
6817
6818   /* X86_64_0E */
6819   {
6820     { "pushP", { cs }, 0 },
6821   },
6822
6823   /* X86_64_16 */
6824   {
6825     { "pushP", { ss }, 0 },
6826   },
6827
6828   /* X86_64_17 */
6829   {
6830     { "popP", { ss }, 0 },
6831   },
6832
6833   /* X86_64_1E */
6834   {
6835     { "pushP", { ds }, 0 },
6836   },
6837
6838   /* X86_64_1F */
6839   {
6840     { "popP", { ds }, 0 },
6841   },
6842
6843   /* X86_64_27 */
6844   {
6845     { "daa", { XX }, 0 },
6846   },
6847
6848   /* X86_64_2F */
6849   {
6850     { "das", { XX }, 0 },
6851   },
6852
6853   /* X86_64_37 */
6854   {
6855     { "aaa", { XX }, 0 },
6856   },
6857
6858   /* X86_64_3F */
6859   {
6860     { "aas", { XX }, 0 },
6861   },
6862
6863   /* X86_64_60 */
6864   {
6865     { "pushaP", { XX }, 0 },
6866   },
6867
6868   /* X86_64_61 */
6869   {
6870     { "popaP", { XX }, 0 },
6871   },
6872
6873   /* X86_64_62 */
6874   {
6875     { MOD_TABLE (MOD_62_32BIT) },
6876     { EVEX_TABLE (EVEX_0F) },
6877   },
6878
6879   /* X86_64_63 */
6880   {
6881     { "arpl", { Ew, Gw }, 0 },
6882     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6883   },
6884
6885   /* X86_64_6D */
6886   {
6887     { "ins{R|}", { Yzr, indirDX }, 0 },
6888     { "ins{G|}", { Yzr, indirDX }, 0 },
6889   },
6890
6891   /* X86_64_6F */
6892   {
6893     { "outs{R|}", { indirDXr, Xz }, 0 },
6894     { "outs{G|}", { indirDXr, Xz }, 0 },
6895   },
6896
6897   /* X86_64_82 */
6898   {
6899     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6900     { REG_TABLE (REG_80) },
6901   },
6902
6903   /* X86_64_9A */
6904   {
6905     { "{l|}call{T|}", { Ap }, 0 },
6906   },
6907
6908   /* X86_64_C2 */
6909   {
6910     { "retP",           { Iw, BND }, 0 },
6911     { "ret@",           { Iw, BND }, 0 },
6912   },
6913
6914   /* X86_64_C3 */
6915   {
6916     { "retP",           { BND }, 0 },
6917     { "ret@",           { BND }, 0 },
6918   },
6919
6920   /* X86_64_C4 */
6921   {
6922     { MOD_TABLE (MOD_C4_32BIT) },
6923     { VEX_C4_TABLE (VEX_0F) },
6924   },
6925
6926   /* X86_64_C5 */
6927   {
6928     { MOD_TABLE (MOD_C5_32BIT) },
6929     { VEX_C5_TABLE (VEX_0F) },
6930   },
6931
6932   /* X86_64_CE */
6933   {
6934     { "into", { XX }, 0 },
6935   },
6936
6937   /* X86_64_D4 */
6938   {
6939     { "aam", { Ib }, 0 },
6940   },
6941
6942   /* X86_64_D5 */
6943   {
6944     { "aad", { Ib }, 0 },
6945   },
6946
6947   /* X86_64_E8 */
6948   {
6949     { "callP",          { Jv, BND }, 0 },
6950     { "call@",          { Jv, BND }, 0 }
6951   },
6952
6953   /* X86_64_E9 */
6954   {
6955     { "jmpP",           { Jv, BND }, 0 },
6956     { "jmp@",           { Jv, BND }, 0 }
6957   },
6958
6959   /* X86_64_EA */
6960   {
6961     { "{l|}jmp{T|}", { Ap }, 0 },
6962   },
6963
6964   /* X86_64_0F01_REG_0 */
6965   {
6966     { "sgdt{Q|Q}", { M }, 0 },
6967     { "sgdt", { M }, 0 },
6968   },
6969
6970   /* X86_64_0F01_REG_1 */
6971   {
6972     { "sidt{Q|Q}", { M }, 0 },
6973     { "sidt", { M }, 0 },
6974   },
6975
6976   /* X86_64_0F01_REG_2 */
6977   {
6978     { "lgdt{Q|Q}", { M }, 0 },
6979     { "lgdt", { M }, 0 },
6980   },
6981
6982   /* X86_64_0F01_REG_3 */
6983   {
6984     { "lidt{Q|Q}", { M }, 0 },
6985     { "lidt", { M }, 0 },
6986   },
6987
6988   /* X86_64_VEX_0F3849 */
6989   {
6990     { Bad_Opcode },
6991     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6992   },
6993
6994   /* X86_64_VEX_0F384B */
6995   {
6996     { Bad_Opcode },
6997     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6998   },
6999
7000   /* X86_64_VEX_0F385C */
7001   {
7002     { Bad_Opcode },
7003     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
7004   },
7005
7006   /* X86_64_VEX_0F385E */
7007   {
7008     { Bad_Opcode },
7009     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
7010   },
7011 };
7012
7013 static const struct dis386 three_byte_table[][256] = {
7014
7015   /* THREE_BYTE_0F38 */
7016   {
7017     /* 00 */
7018     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7019     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7020     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7021     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7022     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7023     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7024     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7025     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7026     /* 08 */
7027     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7028     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7029     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7030     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* 10 */
7036     { PREFIX_TABLE (PREFIX_0F3810) },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { PREFIX_TABLE (PREFIX_0F3814) },
7041     { PREFIX_TABLE (PREFIX_0F3815) },
7042     { Bad_Opcode },
7043     { PREFIX_TABLE (PREFIX_0F3817) },
7044     /* 18 */
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7050     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7051     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7052     { Bad_Opcode },
7053     /* 20 */
7054     { PREFIX_TABLE (PREFIX_0F3820) },
7055     { PREFIX_TABLE (PREFIX_0F3821) },
7056     { PREFIX_TABLE (PREFIX_0F3822) },
7057     { PREFIX_TABLE (PREFIX_0F3823) },
7058     { PREFIX_TABLE (PREFIX_0F3824) },
7059     { PREFIX_TABLE (PREFIX_0F3825) },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 28 */
7063     { PREFIX_TABLE (PREFIX_0F3828) },
7064     { PREFIX_TABLE (PREFIX_0F3829) },
7065     { PREFIX_TABLE (PREFIX_0F382A) },
7066     { PREFIX_TABLE (PREFIX_0F382B) },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 30 */
7072     { PREFIX_TABLE (PREFIX_0F3830) },
7073     { PREFIX_TABLE (PREFIX_0F3831) },
7074     { PREFIX_TABLE (PREFIX_0F3832) },
7075     { PREFIX_TABLE (PREFIX_0F3833) },
7076     { PREFIX_TABLE (PREFIX_0F3834) },
7077     { PREFIX_TABLE (PREFIX_0F3835) },
7078     { Bad_Opcode },
7079     { PREFIX_TABLE (PREFIX_0F3837) },
7080     /* 38 */
7081     { PREFIX_TABLE (PREFIX_0F3838) },
7082     { PREFIX_TABLE (PREFIX_0F3839) },
7083     { PREFIX_TABLE (PREFIX_0F383A) },
7084     { PREFIX_TABLE (PREFIX_0F383B) },
7085     { PREFIX_TABLE (PREFIX_0F383C) },
7086     { PREFIX_TABLE (PREFIX_0F383D) },
7087     { PREFIX_TABLE (PREFIX_0F383E) },
7088     { PREFIX_TABLE (PREFIX_0F383F) },
7089     /* 40 */
7090     { PREFIX_TABLE (PREFIX_0F3840) },
7091     { PREFIX_TABLE (PREFIX_0F3841) },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 48 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 50 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 58 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* 60 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* 68 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 70 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* 78 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* 80 */
7162     { PREFIX_TABLE (PREFIX_0F3880) },
7163     { PREFIX_TABLE (PREFIX_0F3881) },
7164     { PREFIX_TABLE (PREFIX_0F3882) },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* 88 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 90 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* 98 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* a0 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* a8 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* b0 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* b8 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* c0 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* c8 */
7243     { PREFIX_TABLE (PREFIX_0F38C8) },
7244     { PREFIX_TABLE (PREFIX_0F38C9) },
7245     { PREFIX_TABLE (PREFIX_0F38CA) },
7246     { PREFIX_TABLE (PREFIX_0F38CB) },
7247     { PREFIX_TABLE (PREFIX_0F38CC) },
7248     { PREFIX_TABLE (PREFIX_0F38CD) },
7249     { Bad_Opcode },
7250     { PREFIX_TABLE (PREFIX_0F38CF) },
7251     /* d0 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* d8 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { PREFIX_TABLE (PREFIX_0F38DB) },
7265     { PREFIX_TABLE (PREFIX_0F38DC) },
7266     { PREFIX_TABLE (PREFIX_0F38DD) },
7267     { PREFIX_TABLE (PREFIX_0F38DE) },
7268     { PREFIX_TABLE (PREFIX_0F38DF) },
7269     /* e0 */
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* e8 */
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* f0 */
7288     { PREFIX_TABLE (PREFIX_0F38F0) },
7289     { PREFIX_TABLE (PREFIX_0F38F1) },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { PREFIX_TABLE (PREFIX_0F38F5) },
7294     { PREFIX_TABLE (PREFIX_0F38F6) },
7295     { Bad_Opcode },
7296     /* f8 */
7297     { PREFIX_TABLE (PREFIX_0F38F8) },
7298     { PREFIX_TABLE (PREFIX_0F38F9) },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305   },
7306   /* THREE_BYTE_0F3A */
7307   {
7308     /* 00 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 08 */
7318     { PREFIX_TABLE (PREFIX_0F3A08) },
7319     { PREFIX_TABLE (PREFIX_0F3A09) },
7320     { PREFIX_TABLE (PREFIX_0F3A0A) },
7321     { PREFIX_TABLE (PREFIX_0F3A0B) },
7322     { PREFIX_TABLE (PREFIX_0F3A0C) },
7323     { PREFIX_TABLE (PREFIX_0F3A0D) },
7324     { PREFIX_TABLE (PREFIX_0F3A0E) },
7325     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7326     /* 10 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { PREFIX_TABLE (PREFIX_0F3A14) },
7332     { PREFIX_TABLE (PREFIX_0F3A15) },
7333     { PREFIX_TABLE (PREFIX_0F3A16) },
7334     { PREFIX_TABLE (PREFIX_0F3A17) },
7335     /* 18 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 20 */
7345     { PREFIX_TABLE (PREFIX_0F3A20) },
7346     { PREFIX_TABLE (PREFIX_0F3A21) },
7347     { PREFIX_TABLE (PREFIX_0F3A22) },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 28 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 30 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 38 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 40 */
7381     { PREFIX_TABLE (PREFIX_0F3A40) },
7382     { PREFIX_TABLE (PREFIX_0F3A41) },
7383     { PREFIX_TABLE (PREFIX_0F3A42) },
7384     { Bad_Opcode },
7385     { PREFIX_TABLE (PREFIX_0F3A44) },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 48 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 50 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 58 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* 60 */
7417     { PREFIX_TABLE (PREFIX_0F3A60) },
7418     { PREFIX_TABLE (PREFIX_0F3A61) },
7419     { PREFIX_TABLE (PREFIX_0F3A62) },
7420     { PREFIX_TABLE (PREFIX_0F3A63) },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 68 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 70 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* 78 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* 80 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 88 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 90 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* 98 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* a0 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* a8 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* b0 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* b8 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* c0 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* c8 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { PREFIX_TABLE (PREFIX_0F3ACC) },
7539     { Bad_Opcode },
7540     { PREFIX_TABLE (PREFIX_0F3ACE) },
7541     { PREFIX_TABLE (PREFIX_0F3ACF) },
7542     /* d0 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* d8 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { PREFIX_TABLE (PREFIX_0F3ADF) },
7560     /* e0 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* e8 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* f0 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* f8 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596   },
7597 };
7598
7599 static const struct dis386 xop_table[][256] = {
7600   /* XOP_08 */
7601   {
7602     /* 00 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 08 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 10 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 18 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 20 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 28 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 30 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 38 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 40 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 48 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 50 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 58 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* 60 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 68 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 70 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* 78 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* 80 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7754     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7755     /* 88 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7764     /* 90 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7771     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7772     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7773     /* 98 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7781     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7782     /* a0 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7786     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7790     { Bad_Opcode },
7791     /* a8 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* b0 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7808     { Bad_Opcode },
7809     /* b8 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* c0 */
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* c8 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7833     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7834     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7835     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7836     /* d0 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* d8 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* e0 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* e8 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7869     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7870     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7871     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7872     /* f0 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     /* f8 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890   },
7891   /* XOP_09 */
7892   {
7893     /* 00 */
7894     { Bad_Opcode },
7895     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7896     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 08 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 10 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 18 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 20 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 28 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 30 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 38 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 40 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 48 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 50 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* 58 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* 60 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 68 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* 70 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* 78 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* 80 */
8038     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8039     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8040     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8041     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 88 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* 90 */
8056     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8057     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8058     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8059     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8060     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8061     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8064     /* 98 */
8065     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8066     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8067     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8068     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* a0 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* a8 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* b0 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* b8 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* c0 */
8110     { Bad_Opcode },
8111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8117     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8118     /* c8 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* d0 */
8128     { Bad_Opcode },
8129     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8130     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8131     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8135     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8136     /* d8 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* e0 */
8146     { Bad_Opcode },
8147     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8148     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8149     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* e8 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* f0 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     /* f8 */
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181   },
8182   /* XOP_0A */
8183   {
8184     /* 00 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 08 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 10 */
8203     { "bextrS", { Gdq, Edq, Id }, 0 },
8204     { Bad_Opcode },
8205     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 18 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 20 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 28 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 30 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 38 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 40 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 48 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 50 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 58 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* 60 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 68 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 70 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 78 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 80 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* 88 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 90 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* 98 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* a0 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* a8 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* b0 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* b8 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* c0 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* c8 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* d0 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* d8 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* e0 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* e8 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* f0 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* f8 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472   },
8473 };
8474
8475 static const struct dis386 vex_table[][256] = {
8476   /* VEX_0F */
8477   {
8478     /* 00 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 08 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 10 */
8497     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8500     { MOD_TABLE (MOD_VEX_0F13) },
8501     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8502     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8503     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8504     { MOD_TABLE (MOD_VEX_0F17) },
8505     /* 18 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* 20 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 28 */
8524     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8525     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8526     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8527     { MOD_TABLE (MOD_VEX_0F2B) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8532     /* 30 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* 38 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* 40 */
8551     { Bad_Opcode },
8552     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8554     { Bad_Opcode },
8555     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8559     /* 48 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* 50 */
8569     { MOD_TABLE (MOD_VEX_0F50) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8573     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8574     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8575     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8576     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8577     /* 58 */
8578     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8586     /* 60 */
8587     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8595     /* 68 */
8596     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8604     /* 70 */
8605     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8606     { REG_TABLE (REG_VEX_0F71) },
8607     { REG_TABLE (REG_VEX_0F72) },
8608     { REG_TABLE (REG_VEX_0F73) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8613     /* 78 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8622     /* 80 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 88 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* 90 */
8641     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* 98 */
8650     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* a0 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* a8 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { REG_TABLE (REG_VEX_0FAE) },
8675     { Bad_Opcode },
8676     /* b0 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* b8 */
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     /* c0 */
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8698     { Bad_Opcode },
8699     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8701     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8702     { Bad_Opcode },
8703     /* c8 */
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     /* d0 */
8713     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8721     /* d8 */
8722     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8730     /* e0 */
8731     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8739     /* e8 */
8740     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8748     /* f0 */
8749     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8755     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8756     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8757     /* f8 */
8758     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8759     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8760     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8763     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8764     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8765     { Bad_Opcode },
8766   },
8767   /* VEX_0F38 */
8768   {
8769     /* 00 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8778     /* 08 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8787     /* 10 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8796     /* 18 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8804     { Bad_Opcode },
8805     /* 20 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* 28 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8823     /* 30 */
8824     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8832     /* 38 */
8833     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8841     /* 40 */
8842     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8850     /* 48 */
8851     { Bad_Opcode },
8852     { X86_64_TABLE (X86_64_VEX_0F3849) },
8853     { Bad_Opcode },
8854     { X86_64_TABLE (X86_64_VEX_0F384B) },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 50 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* 58 */
8869     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8872     { Bad_Opcode },
8873     { X86_64_TABLE (X86_64_VEX_0F385C) },
8874     { Bad_Opcode },
8875     { X86_64_TABLE (X86_64_VEX_0F385E) },
8876     { Bad_Opcode },
8877     /* 60 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     /* 68 */
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     /* 70 */
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     /* 78 */
8905     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     /* 80 */
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     /* 88 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8930     { Bad_Opcode },
8931     /* 90 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8940     /* 98 */
8941     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8949     /* a0 */
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8958     /* a8 */
8959     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8967     /* b0 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8976     /* b8 */
8977     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8985     /* c0 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* c8 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9003     /* d0 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     /* d8 */
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9021     /* e0 */
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* e8 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     /* f0 */
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9043     { REG_TABLE (REG_VEX_0F38F3) },
9044     { Bad_Opcode },
9045     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9048     /* f8 */
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057   },
9058   /* VEX_0F3A */
9059   {
9060     /* 00 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9064     { Bad_Opcode },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9068     { Bad_Opcode },
9069     /* 08 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9078     /* 10 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9087     /* 18 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* 20 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 28 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* 30 */
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* 38 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* 40 */
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9136     { Bad_Opcode },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9138     { Bad_Opcode },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9140     { Bad_Opcode },
9141     /* 48 */
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 50 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* 58 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9168     /* 60 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* 68 */
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9186     /* 70 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* 78 */
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9204     /* 80 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* 88 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* 90 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* 98 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* a0 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* a8 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* b0 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* b8 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* c0 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     /* c8 */
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9293     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9294     /* d0 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     /* d8 */
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9312     /* e0 */
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     /* e8 */
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     /* f0 */
9331     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     /* f8 */
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348   },
9349 };
9350
9351 #include "i386-dis-evex.h"
9352
9353 static const struct dis386 vex_len_table[][2] = {
9354   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9355   {
9356     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9357   },
9358
9359   /* VEX_LEN_0F12_P_0_M_1 */
9360   {
9361     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9362   },
9363
9364   /* VEX_LEN_0F13_M_0 */
9365   {
9366     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9367   },
9368
9369   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9370   {
9371     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9372   },
9373
9374   /* VEX_LEN_0F16_P_0_M_1 */
9375   {
9376     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9377   },
9378
9379   /* VEX_LEN_0F17_M_0 */
9380   {
9381     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9382   },
9383
9384   /* VEX_LEN_0F41_P_0 */
9385   {
9386     { Bad_Opcode },
9387     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9388   },
9389   /* VEX_LEN_0F41_P_2 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9393   },
9394   /* VEX_LEN_0F42_P_0 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9398   },
9399   /* VEX_LEN_0F42_P_2 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9403   },
9404   /* VEX_LEN_0F44_P_0 */
9405   {
9406     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9407   },
9408   /* VEX_LEN_0F44_P_2 */
9409   {
9410     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9411   },
9412   /* VEX_LEN_0F45_P_0 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9416   },
9417   /* VEX_LEN_0F45_P_2 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9421   },
9422   /* VEX_LEN_0F46_P_0 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9426   },
9427   /* VEX_LEN_0F46_P_2 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9431   },
9432   /* VEX_LEN_0F47_P_0 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9436   },
9437   /* VEX_LEN_0F47_P_2 */
9438   {
9439     { Bad_Opcode },
9440     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9441   },
9442   /* VEX_LEN_0F4A_P_0 */
9443   {
9444     { Bad_Opcode },
9445     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9446   },
9447   /* VEX_LEN_0F4A_P_2 */
9448   {
9449     { Bad_Opcode },
9450     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9451   },
9452   /* VEX_LEN_0F4B_P_0 */
9453   {
9454     { Bad_Opcode },
9455     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9456   },
9457   /* VEX_LEN_0F4B_P_2 */
9458   {
9459     { Bad_Opcode },
9460     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9461   },
9462
9463   /* VEX_LEN_0F6E_P_2 */
9464   {
9465     { "vmovK",          { XMScalar, Edq }, 0 },
9466   },
9467
9468   /* VEX_LEN_0F77_P_1 */
9469   {
9470     { "vzeroupper",     { XX }, 0 },
9471     { "vzeroall",       { XX }, 0 },
9472   },
9473
9474   /* VEX_LEN_0F7E_P_1 */
9475   {
9476     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9477   },
9478
9479   /* VEX_LEN_0F7E_P_2 */
9480   {
9481     { "vmovK",          { Edq, XMScalar }, 0 },
9482   },
9483
9484   /* VEX_LEN_0F90_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F90_P_2 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F91_P_0 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F91_P_2 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F92_P_0 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F92_P_2 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F92_P_3 */
9515   {
9516     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F93_P_0 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0F93_P_2 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9527   },
9528
9529   /* VEX_LEN_0F93_P_3 */
9530   {
9531     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9532   },
9533
9534   /* VEX_LEN_0F98_P_0 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9537   },
9538
9539   /* VEX_LEN_0F98_P_2 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9542   },
9543
9544   /* VEX_LEN_0F99_P_0 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9547   },
9548
9549   /* VEX_LEN_0F99_P_2 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9552   },
9553
9554   /* VEX_LEN_0FAE_R_2_M_0 */
9555   {
9556     { "vldmxcsr",       { Md }, 0 },
9557   },
9558
9559   /* VEX_LEN_0FAE_R_3_M_0 */
9560   {
9561     { "vstmxcsr",       { Md }, 0 },
9562   },
9563
9564   /* VEX_LEN_0FC4_P_2 */
9565   {
9566     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9567   },
9568
9569   /* VEX_LEN_0FC5_P_2 */
9570   {
9571     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9572   },
9573
9574   /* VEX_LEN_0FD6_P_2 */
9575   {
9576     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9577   },
9578
9579   /* VEX_LEN_0FF7_P_2 */
9580   {
9581     { "vmaskmovdqu",    { XM, XS }, 0 },
9582   },
9583
9584   /* VEX_LEN_0F3816_P_2 */
9585   {
9586     { Bad_Opcode },
9587     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9588   },
9589
9590   /* VEX_LEN_0F3819_P_2 */
9591   {
9592     { Bad_Opcode },
9593     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9594   },
9595
9596   /* VEX_LEN_0F381A_P_2_M_0 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9600   },
9601
9602   /* VEX_LEN_0F3836_P_2 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9606   },
9607
9608   /* VEX_LEN_0F3841_P_2 */
9609   {
9610     { "vphminposuw",    { XM, EXx }, 0 },
9611   },
9612
9613    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9614   {
9615     { "ldtilecfg", { M }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9619   {
9620     { "tilerelease", { Skip_MODRM }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9624   {
9625     { "sttilecfg", { M }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9629   {
9630     { "tilezero", { TMM, Skip_MODRM }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9634   {
9635     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9636   },
9637   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9638   {
9639     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9643   {
9644     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F385A_P_2_M_0 */
9648   {
9649     { Bad_Opcode },
9650     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9651   },
9652
9653   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9654   {
9655     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9656   },
9657
9658   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9659   {
9660     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9664   {
9665     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9669   {
9670     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9674   {
9675     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F38DB_P_2 */
9679   {
9680     { "vaesimc",        { XM, EXx }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F38F2_P_0 */
9684   {
9685     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F38F3_R_1_P_0 */
9689   {
9690     { "blsrS",          { VexGdq, Edq }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F38F3_R_2_P_0 */
9694   {
9695     { "blsmskS",        { VexGdq, Edq }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F38F3_R_3_P_0 */
9699   {
9700     { "blsiS",          { VexGdq, Edq }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F38F5_P_0 */
9704   {
9705     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F38F5_P_1 */
9709   {
9710     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F38F5_P_3 */
9714   {
9715     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F38F6_P_3 */
9719   {
9720     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9721   },
9722
9723   /* VEX_LEN_0F38F7_P_0 */
9724   {
9725     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9726   },
9727
9728   /* VEX_LEN_0F38F7_P_1 */
9729   {
9730     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9731   },
9732
9733   /* VEX_LEN_0F38F7_P_2 */
9734   {
9735     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9736   },
9737
9738   /* VEX_LEN_0F38F7_P_3 */
9739   {
9740     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9741   },
9742
9743   /* VEX_LEN_0F3A00_P_2 */
9744   {
9745     { Bad_Opcode },
9746     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9747   },
9748
9749   /* VEX_LEN_0F3A01_P_2 */
9750   {
9751     { Bad_Opcode },
9752     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9753   },
9754
9755   /* VEX_LEN_0F3A06_P_2 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A14_P_2 */
9762   {
9763     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A15_P_2 */
9767   {
9768     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A16_P_2  */
9772   {
9773     { "vpextrK",        { Edq, XM, Ib }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A17_P_2 */
9777   {
9778     { "vextractps",     { Edqd, XM, Ib }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A18_P_2 */
9782   {
9783     { Bad_Opcode },
9784     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9785   },
9786
9787   /* VEX_LEN_0F3A19_P_2 */
9788   {
9789     { Bad_Opcode },
9790     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9791   },
9792
9793   /* VEX_LEN_0F3A20_P_2 */
9794   {
9795     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A21_P_2 */
9799   {
9800     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A22_P_2 */
9804   {
9805     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A30_P_2 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9811   },
9812
9813   /* VEX_LEN_0F3A31_P_2 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9816   },
9817
9818   /* VEX_LEN_0F3A32_P_2 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9821   },
9822
9823   /* VEX_LEN_0F3A33_P_2 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9826   },
9827
9828   /* VEX_LEN_0F3A38_P_2 */
9829   {
9830     { Bad_Opcode },
9831     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9832   },
9833
9834   /* VEX_LEN_0F3A39_P_2 */
9835   {
9836     { Bad_Opcode },
9837     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9838   },
9839
9840   /* VEX_LEN_0F3A41_P_2 */
9841   {
9842     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9843   },
9844
9845   /* VEX_LEN_0F3A46_P_2 */
9846   {
9847     { Bad_Opcode },
9848     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9849   },
9850
9851   /* VEX_LEN_0F3A60_P_2 */
9852   {
9853     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9854   },
9855
9856   /* VEX_LEN_0F3A61_P_2 */
9857   {
9858     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9859   },
9860
9861   /* VEX_LEN_0F3A62_P_2 */
9862   {
9863     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9864   },
9865
9866   /* VEX_LEN_0F3A63_P_2 */
9867   {
9868     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9869   },
9870
9871   /* VEX_LEN_0F3ADF_P_2 */
9872   {
9873     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9874   },
9875
9876   /* VEX_LEN_0F3AF0_P_3 */
9877   {
9878     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9879   },
9880
9881   /* VEX_LEN_0FXOP_08_85 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9884   },
9885
9886   /* VEX_LEN_0FXOP_08_86 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9889   },
9890
9891   /* VEX_LEN_0FXOP_08_87 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9894   },
9895
9896   /* VEX_LEN_0FXOP_08_8E */
9897   {
9898     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9899   },
9900
9901   /* VEX_LEN_0FXOP_08_8F */
9902   {
9903     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9904   },
9905
9906   /* VEX_LEN_0FXOP_08_95 */
9907   {
9908     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9909   },
9910
9911   /* VEX_LEN_0FXOP_08_96 */
9912   {
9913     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9914   },
9915
9916   /* VEX_LEN_0FXOP_08_97 */
9917   {
9918     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9919   },
9920
9921   /* VEX_LEN_0FXOP_08_9E */
9922   {
9923     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9924   },
9925
9926   /* VEX_LEN_0FXOP_08_9F */
9927   {
9928     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9929   },
9930
9931   /* VEX_LEN_0FXOP_08_A3 */
9932   {
9933     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9934   },
9935
9936   /* VEX_LEN_0FXOP_08_A6 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9939   },
9940
9941   /* VEX_LEN_0FXOP_08_B6 */
9942   {
9943     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9944   },
9945
9946   /* VEX_LEN_0FXOP_08_C0 */
9947   {
9948     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9949   },
9950
9951   /* VEX_LEN_0FXOP_08_C1 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9954   },
9955
9956   /* VEX_LEN_0FXOP_08_C2 */
9957   {
9958     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9959   },
9960
9961   /* VEX_LEN_0FXOP_08_C3 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9964   },
9965
9966   /* VEX_LEN_0FXOP_08_CC */
9967   {
9968     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9969   },
9970
9971   /* VEX_LEN_0FXOP_08_CD */
9972   {
9973     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9974   },
9975
9976   /* VEX_LEN_0FXOP_08_CE */
9977   {
9978     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9979   },
9980
9981   /* VEX_LEN_0FXOP_08_CF */
9982   {
9983     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9984   },
9985
9986   /* VEX_LEN_0FXOP_08_EC */
9987   {
9988     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9989   },
9990
9991   /* VEX_LEN_0FXOP_08_ED */
9992   {
9993     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9994   },
9995
9996   /* VEX_LEN_0FXOP_08_EE */
9997   {
9998     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9999   },
10000
10001   /* VEX_LEN_0FXOP_08_EF */
10002   {
10003     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
10004   },
10005
10006   /* VEX_LEN_0FXOP_09_01 */
10007   {
10008     { REG_TABLE (REG_0FXOP_09_01_L_0) },
10009   },
10010
10011   /* VEX_LEN_0FXOP_09_02 */
10012   {
10013     { REG_TABLE (REG_0FXOP_09_02_L_0) },
10014   },
10015
10016   /* VEX_LEN_0FXOP_09_12_M_1 */
10017   {
10018     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
10019   },
10020
10021   /* VEX_LEN_0FXOP_09_82_W_0 */
10022   {
10023     { "vfrczss",        { XM, EXd }, 0 },
10024   },
10025
10026   /* VEX_LEN_0FXOP_09_83_W_0 */
10027   {
10028     { "vfrczsd",        { XM, EXq }, 0 },
10029   },
10030
10031   /* VEX_LEN_0FXOP_09_90 */
10032   {
10033     { "vprotb",         { XM, EXx, VexW }, 0 },
10034   },
10035
10036   /* VEX_LEN_0FXOP_09_91 */
10037   {
10038     { "vprotw",         { XM, EXx, VexW }, 0 },
10039   },
10040
10041   /* VEX_LEN_0FXOP_09_92 */
10042   {
10043     { "vprotd",         { XM, EXx, VexW }, 0 },
10044   },
10045
10046   /* VEX_LEN_0FXOP_09_93 */
10047   {
10048     { "vprotq",         { XM, EXx, VexW }, 0 },
10049   },
10050
10051   /* VEX_LEN_0FXOP_09_94 */
10052   {
10053     { "vpshlb",         { XM, EXx, VexW }, 0 },
10054   },
10055
10056   /* VEX_LEN_0FXOP_09_95 */
10057   {
10058     { "vpshlw",         { XM, EXx, VexW }, 0 },
10059   },
10060
10061   /* VEX_LEN_0FXOP_09_96 */
10062   {
10063     { "vpshld",         { XM, EXx, VexW }, 0 },
10064   },
10065
10066   /* VEX_LEN_0FXOP_09_97 */
10067   {
10068     { "vpshlq",         { XM, EXx, VexW }, 0 },
10069   },
10070
10071   /* VEX_LEN_0FXOP_09_98 */
10072   {
10073     { "vpshab",         { XM, EXx, VexW }, 0 },
10074   },
10075
10076   /* VEX_LEN_0FXOP_09_99 */
10077   {
10078     { "vpshaw",         { XM, EXx, VexW }, 0 },
10079   },
10080
10081   /* VEX_LEN_0FXOP_09_9A */
10082   {
10083     { "vpshad",         { XM, EXx, VexW }, 0 },
10084   },
10085
10086   /* VEX_LEN_0FXOP_09_9B */
10087   {
10088     { "vpshaq",         { XM, EXx, VexW }, 0 },
10089   },
10090
10091   /* VEX_LEN_0FXOP_09_C1 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10094   },
10095
10096   /* VEX_LEN_0FXOP_09_C2 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10099   },
10100
10101   /* VEX_LEN_0FXOP_09_C3 */
10102   {
10103     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10104   },
10105
10106   /* VEX_LEN_0FXOP_09_C6 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10109   },
10110
10111   /* VEX_LEN_0FXOP_09_C7 */
10112   {
10113     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10114   },
10115
10116   /* VEX_LEN_0FXOP_09_CB */
10117   {
10118     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10119   },
10120
10121   /* VEX_LEN_0FXOP_09_D1 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10124   },
10125
10126   /* VEX_LEN_0FXOP_09_D2 */
10127   {
10128     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10129   },
10130
10131   /* VEX_LEN_0FXOP_09_D3 */
10132   {
10133     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10134   },
10135
10136   /* VEX_LEN_0FXOP_09_D6 */
10137   {
10138     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10139   },
10140
10141   /* VEX_LEN_0FXOP_09_D7 */
10142   {
10143     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10144   },
10145
10146   /* VEX_LEN_0FXOP_09_DB */
10147   {
10148     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10149   },
10150
10151   /* VEX_LEN_0FXOP_09_E1 */
10152   {
10153     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10154   },
10155
10156   /* VEX_LEN_0FXOP_09_E2 */
10157   {
10158     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10159   },
10160
10161   /* VEX_LEN_0FXOP_09_E3 */
10162   {
10163     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10164   },
10165
10166   /* VEX_LEN_0FXOP_0A_12 */
10167   {
10168     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10169   },
10170 };
10171
10172 #include "i386-dis-evex-len.h"
10173
10174 static const struct dis386 vex_w_table[][2] = {
10175   {
10176     /* VEX_W_0F41_P_0_LEN_1 */
10177     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10178     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10179   },
10180   {
10181     /* VEX_W_0F41_P_2_LEN_1 */
10182     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10183     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10184   },
10185   {
10186     /* VEX_W_0F42_P_0_LEN_1 */
10187     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10188     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10189   },
10190   {
10191     /* VEX_W_0F42_P_2_LEN_1 */
10192     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10193     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10194   },
10195   {
10196     /* VEX_W_0F44_P_0_LEN_0 */
10197     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10198     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10199   },
10200   {
10201     /* VEX_W_0F44_P_2_LEN_0 */
10202     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10203     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10204   },
10205   {
10206     /* VEX_W_0F45_P_0_LEN_1 */
10207     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10208     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10209   },
10210   {
10211     /* VEX_W_0F45_P_2_LEN_1 */
10212     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10213     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10214   },
10215   {
10216     /* VEX_W_0F46_P_0_LEN_1 */
10217     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10218     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10219   },
10220   {
10221     /* VEX_W_0F46_P_2_LEN_1 */
10222     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10223     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10224   },
10225   {
10226     /* VEX_W_0F47_P_0_LEN_1 */
10227     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10228     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10229   },
10230   {
10231     /* VEX_W_0F47_P_2_LEN_1 */
10232     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10233     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10234   },
10235   {
10236     /* VEX_W_0F4A_P_0_LEN_1 */
10237     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10238     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10239   },
10240   {
10241     /* VEX_W_0F4A_P_2_LEN_1 */
10242     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10243     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10244   },
10245   {
10246     /* VEX_W_0F4B_P_0_LEN_1 */
10247     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10248     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10249   },
10250   {
10251     /* VEX_W_0F4B_P_2_LEN_1 */
10252     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10253   },
10254   {
10255     /* VEX_W_0F90_P_0_LEN_0 */
10256     { "kmovw",          { MaskG, MaskE }, 0 },
10257     { "kmovq",          { MaskG, MaskE }, 0 },
10258   },
10259   {
10260     /* VEX_W_0F90_P_2_LEN_0 */
10261     { "kmovb",          { MaskG, MaskBDE }, 0 },
10262     { "kmovd",          { MaskG, MaskBDE }, 0 },
10263   },
10264   {
10265     /* VEX_W_0F91_P_0_LEN_0 */
10266     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10267     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10268   },
10269   {
10270     /* VEX_W_0F91_P_2_LEN_0 */
10271     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10272     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10273   },
10274   {
10275     /* VEX_W_0F92_P_0_LEN_0 */
10276     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10277   },
10278   {
10279     /* VEX_W_0F92_P_2_LEN_0 */
10280     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10281   },
10282   {
10283     /* VEX_W_0F93_P_0_LEN_0 */
10284     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10285   },
10286   {
10287     /* VEX_W_0F93_P_2_LEN_0 */
10288     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10289   },
10290   {
10291     /* VEX_W_0F98_P_0_LEN_0 */
10292     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10293     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10294   },
10295   {
10296     /* VEX_W_0F98_P_2_LEN_0 */
10297     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10298     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10299   },
10300   {
10301     /* VEX_W_0F99_P_0_LEN_0 */
10302     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10303     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10304   },
10305   {
10306     /* VEX_W_0F99_P_2_LEN_0 */
10307     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10308     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10309   },
10310   {
10311     /* VEX_W_0F380C_P_2  */
10312     { "vpermilps",      { XM, Vex, EXx }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F380D_P_2  */
10316     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F380E_P_2  */
10320     { "vtestps",        { XM, EXx }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F380F_P_2  */
10324     { "vtestpd",        { XM, EXx }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F3813_P_2 */
10328     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F3816_P_2  */
10332     { "vpermps",        { XM, Vex, EXx }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F3818_P_2 */
10336     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F3819_P_2 */
10340     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F381A_P_2_M_0 */
10344     { "vbroadcastf128", { XM, Mxmm }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F382C_P_2_M_0 */
10348     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F382D_P_2_M_0 */
10352     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F382E_P_2_M_0 */
10356     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F382F_P_2_M_0 */
10360     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F3836_P_2  */
10364     { "vpermd",         { XM, Vex, EXx }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F3846_P_2 */
10368     { "vpsravd",        { XM, Vex, EXx }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F3849_X86_64_P_0 */
10372     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10373   },
10374   {
10375     /* VEX_W_0F3849_X86_64_P_2 */
10376     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10377   },
10378   {
10379     /* VEX_W_0F3849_X86_64_P_3 */
10380     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10381   },
10382   {
10383     /* VEX_W_0F384B_X86_64_P_1 */
10384     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10385   },
10386   {
10387     /* VEX_W_0F384B_X86_64_P_2 */
10388     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10389   },
10390   {
10391     /* VEX_W_0F384B_X86_64_P_3 */
10392     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10393   },
10394   {
10395     /* VEX_W_0F3858_P_2 */
10396     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F3859_P_2 */
10400     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F385A_P_2_M_0 */
10404     { "vbroadcasti128", { XM, Mxmm }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F385C_X86_64_P_1 */
10408     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10409   },
10410   {
10411     /* VEX_W_0F385E_X86_64_P_0 */
10412     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10413   },
10414   {
10415     /* VEX_W_0F385E_X86_64_P_1 */
10416     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10417   },
10418   {
10419     /* VEX_W_0F385E_X86_64_P_2 */
10420     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10421   },
10422   {
10423     /* VEX_W_0F385E_X86_64_P_3 */
10424     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10425   },
10426   {
10427     /* VEX_W_0F3878_P_2 */
10428     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F3879_P_2 */
10432     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F38CF_P_2 */
10436     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F3A00_P_2 */
10440     { Bad_Opcode },
10441     { "vpermq",         { XM, EXx, Ib }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F3A01_P_2 */
10445     { Bad_Opcode },
10446     { "vpermpd",        { XM, EXx, Ib }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F3A02_P_2 */
10450     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F3A04_P_2 */
10454     { "vpermilps",      { XM, EXx, Ib }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F3A05_P_2 */
10458     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F3A06_P_2 */
10462     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F3A18_P_2 */
10466     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F3A19_P_2 */
10470     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F3A1D_P_2 */
10474     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F3A30_P_2_LEN_0 */
10478     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10479     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10480   },
10481   {
10482     /* VEX_W_0F3A31_P_2_LEN_0 */
10483     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10484     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10485   },
10486   {
10487     /* VEX_W_0F3A32_P_2_LEN_0 */
10488     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10489     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10490   },
10491   {
10492     /* VEX_W_0F3A33_P_2_LEN_0 */
10493     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10494     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10495   },
10496   {
10497     /* VEX_W_0F3A38_P_2 */
10498     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F3A39_P_2 */
10502     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F3A46_P_2 */
10506     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F3A4A_P_2 */
10510     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F3A4B_P_2 */
10514     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F3A4C_P_2 */
10518     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F3ACE_P_2 */
10522     { Bad_Opcode },
10523     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F3ACF_P_2 */
10527     { Bad_Opcode },
10528     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10529   },
10530   /* VEX_W_0FXOP_08_85_L_0 */
10531   {
10532     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10533   },
10534   /* VEX_W_0FXOP_08_86_L_0 */
10535   {
10536     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10537   },
10538   /* VEX_W_0FXOP_08_87_L_0 */
10539   {
10540     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10541   },
10542   /* VEX_W_0FXOP_08_8E_L_0 */
10543   {
10544     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10545   },
10546   /* VEX_W_0FXOP_08_8F_L_0 */
10547   {
10548     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10549   },
10550   /* VEX_W_0FXOP_08_95_L_0 */
10551   {
10552     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10553   },
10554   /* VEX_W_0FXOP_08_96_L_0 */
10555   {
10556     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10557   },
10558   /* VEX_W_0FXOP_08_97_L_0 */
10559   {
10560     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10561   },
10562   /* VEX_W_0FXOP_08_9E_L_0 */
10563   {
10564     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10565   },
10566   /* VEX_W_0FXOP_08_9F_L_0 */
10567   {
10568     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10569   },
10570   /* VEX_W_0FXOP_08_A6_L_0 */
10571   {
10572     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10573   },
10574   /* VEX_W_0FXOP_08_B6_L_0 */
10575   {
10576     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10577   },
10578   /* VEX_W_0FXOP_08_C0_L_0 */
10579   {
10580     { "vprotb",         { XM, EXx, Ib }, 0 },
10581   },
10582   /* VEX_W_0FXOP_08_C1_L_0 */
10583   {
10584     { "vprotw",         { XM, EXx, Ib }, 0 },
10585   },
10586   /* VEX_W_0FXOP_08_C2_L_0 */
10587   {
10588     { "vprotd",         { XM, EXx, Ib }, 0 },
10589   },
10590   /* VEX_W_0FXOP_08_C3_L_0 */
10591   {
10592     { "vprotq",         { XM, EXx, Ib }, 0 },
10593   },
10594   /* VEX_W_0FXOP_08_CC_L_0 */
10595   {
10596      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10597   },
10598   /* VEX_W_0FXOP_08_CD_L_0 */
10599   {
10600      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10601   },
10602   /* VEX_W_0FXOP_08_CE_L_0 */
10603   {
10604      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10605   },
10606   /* VEX_W_0FXOP_08_CF_L_0 */
10607   {
10608      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10609   },
10610   /* VEX_W_0FXOP_08_EC_L_0 */
10611   {
10612      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10613   },
10614   /* VEX_W_0FXOP_08_ED_L_0 */
10615   {
10616      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10617   },
10618   /* VEX_W_0FXOP_08_EE_L_0 */
10619   {
10620      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10621   },
10622   /* VEX_W_0FXOP_08_EF_L_0 */
10623   {
10624      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10625   },
10626   /* VEX_W_0FXOP_09_80 */
10627   {
10628     { "vfrczps",        { XM, EXx }, 0 },
10629   },
10630   /* VEX_W_0FXOP_09_81 */
10631   {
10632     { "vfrczpd",        { XM, EXx }, 0 },
10633   },
10634   /* VEX_W_0FXOP_09_82 */
10635   {
10636     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10637   },
10638   /* VEX_W_0FXOP_09_83 */
10639   {
10640     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10641   },
10642   /* VEX_W_0FXOP_09_C1_L_0 */
10643   {
10644     { "vphaddbw",       { XM, EXxmm }, 0 },
10645   },
10646   /* VEX_W_0FXOP_09_C2_L_0 */
10647   {
10648     { "vphaddbd",       { XM, EXxmm }, 0 },
10649   },
10650   /* VEX_W_0FXOP_09_C3_L_0 */
10651   {
10652     { "vphaddbq",       { XM, EXxmm }, 0 },
10653   },
10654   /* VEX_W_0FXOP_09_C6_L_0 */
10655   {
10656     { "vphaddwd",       { XM, EXxmm }, 0 },
10657   },
10658   /* VEX_W_0FXOP_09_C7_L_0 */
10659   {
10660     { "vphaddwq",       { XM, EXxmm }, 0 },
10661   },
10662   /* VEX_W_0FXOP_09_CB_L_0 */
10663   {
10664     { "vphadddq",       { XM, EXxmm }, 0 },
10665   },
10666   /* VEX_W_0FXOP_09_D1_L_0 */
10667   {
10668     { "vphaddubw",      { XM, EXxmm }, 0 },
10669   },
10670   /* VEX_W_0FXOP_09_D2_L_0 */
10671   {
10672     { "vphaddubd",      { XM, EXxmm }, 0 },
10673   },
10674   /* VEX_W_0FXOP_09_D3_L_0 */
10675   {
10676     { "vphaddubq",      { XM, EXxmm }, 0 },
10677   },
10678   /* VEX_W_0FXOP_09_D6_L_0 */
10679   {
10680     { "vphadduwd",      { XM, EXxmm }, 0 },
10681   },
10682   /* VEX_W_0FXOP_09_D7_L_0 */
10683   {
10684     { "vphadduwq",      { XM, EXxmm }, 0 },
10685   },
10686   /* VEX_W_0FXOP_09_DB_L_0 */
10687   {
10688     { "vphaddudq",      { XM, EXxmm }, 0 },
10689   },
10690   /* VEX_W_0FXOP_09_E1_L_0 */
10691   {
10692     { "vphsubbw",       { XM, EXxmm }, 0 },
10693   },
10694   /* VEX_W_0FXOP_09_E2_L_0 */
10695   {
10696     { "vphsubwd",       { XM, EXxmm }, 0 },
10697   },
10698   /* VEX_W_0FXOP_09_E3_L_0 */
10699   {
10700     { "vphsubdq",       { XM, EXxmm }, 0 },
10701   },
10702
10703 #include "i386-dis-evex-w.h"
10704 };
10705
10706 static const struct dis386 mod_table[][2] = {
10707   {
10708     /* MOD_8D */
10709     { "leaS",           { Gv, M }, 0 },
10710   },
10711   {
10712     /* MOD_C6_REG_7 */
10713     { Bad_Opcode },
10714     { RM_TABLE (RM_C6_REG_7) },
10715   },
10716   {
10717     /* MOD_C7_REG_7 */
10718     { Bad_Opcode },
10719     { RM_TABLE (RM_C7_REG_7) },
10720   },
10721   {
10722     /* MOD_FF_REG_3 */
10723     { "{l|}call^", { indirEp }, 0 },
10724   },
10725   {
10726     /* MOD_FF_REG_5 */
10727     { "{l|}jmp^", { indirEp }, 0 },
10728   },
10729   {
10730     /* MOD_0F01_REG_0 */
10731     { X86_64_TABLE (X86_64_0F01_REG_0) },
10732     { RM_TABLE (RM_0F01_REG_0) },
10733   },
10734   {
10735     /* MOD_0F01_REG_1 */
10736     { X86_64_TABLE (X86_64_0F01_REG_1) },
10737     { RM_TABLE (RM_0F01_REG_1) },
10738   },
10739   {
10740     /* MOD_0F01_REG_2 */
10741     { X86_64_TABLE (X86_64_0F01_REG_2) },
10742     { RM_TABLE (RM_0F01_REG_2) },
10743   },
10744   {
10745     /* MOD_0F01_REG_3 */
10746     { X86_64_TABLE (X86_64_0F01_REG_3) },
10747     { RM_TABLE (RM_0F01_REG_3) },
10748   },
10749   {
10750     /* MOD_0F01_REG_5 */
10751     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10752     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10753   },
10754   {
10755     /* MOD_0F01_REG_7 */
10756     { "invlpg",         { Mb }, 0 },
10757     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10758   },
10759   {
10760     /* MOD_0F12_PREFIX_0 */
10761     { "movlpX",         { XM, EXq }, 0 },
10762     { "movhlps",        { XM, EXq }, 0 },
10763   },
10764   {
10765     /* MOD_0F12_PREFIX_2 */
10766     { "movlpX", { XM, EXq }, 0 },
10767   },
10768   {
10769     /* MOD_0F13 */
10770     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10771   },
10772   {
10773     /* MOD_0F16_PREFIX_0 */
10774     { "movhpX",         { XM, EXq }, 0 },
10775     { "movlhps",        { XM, EXq }, 0 },
10776   },
10777   {
10778     /* MOD_0F16_PREFIX_2 */
10779     { "movhpX", { XM, EXq }, 0 },
10780   },
10781   {
10782     /* MOD_0F17 */
10783     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10784   },
10785   {
10786     /* MOD_0F18_REG_0 */
10787     { "prefetchnta",    { Mb }, 0 },
10788   },
10789   {
10790     /* MOD_0F18_REG_1 */
10791     { "prefetcht0",     { Mb }, 0 },
10792   },
10793   {
10794     /* MOD_0F18_REG_2 */
10795     { "prefetcht1",     { Mb }, 0 },
10796   },
10797   {
10798     /* MOD_0F18_REG_3 */
10799     { "prefetcht2",     { Mb }, 0 },
10800   },
10801   {
10802     /* MOD_0F18_REG_4 */
10803     { "nop/reserved",   { Mb }, 0 },
10804   },
10805   {
10806     /* MOD_0F18_REG_5 */
10807     { "nop/reserved",   { Mb }, 0 },
10808   },
10809   {
10810     /* MOD_0F18_REG_6 */
10811     { "nop/reserved",   { Mb }, 0 },
10812   },
10813   {
10814     /* MOD_0F18_REG_7 */
10815     { "nop/reserved",   { Mb }, 0 },
10816   },
10817   {
10818     /* MOD_0F1A_PREFIX_0 */
10819     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10820     { "nopQ",           { Ev }, 0 },
10821   },
10822   {
10823     /* MOD_0F1B_PREFIX_0 */
10824     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10825     { "nopQ",           { Ev }, 0 },
10826   },
10827   {
10828     /* MOD_0F1B_PREFIX_1 */
10829     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10830     { "nopQ",           { Ev }, 0 },
10831   },
10832   {
10833     /* MOD_0F1C_PREFIX_0 */
10834     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10835     { "nopQ",           { Ev }, 0 },
10836   },
10837   {
10838     /* MOD_0F1E_PREFIX_1 */
10839     { "nopQ",           { Ev }, 0 },
10840     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10841   },
10842   {
10843     /* MOD_0F24 */
10844     { Bad_Opcode },
10845     { "movL",           { Rd, Td }, 0 },
10846   },
10847   {
10848     /* MOD_0F26 */
10849     { Bad_Opcode },
10850     { "movL",           { Td, Rd }, 0 },
10851   },
10852   {
10853     /* MOD_0F2B_PREFIX_0 */
10854     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10855   },
10856   {
10857     /* MOD_0F2B_PREFIX_1 */
10858     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10859   },
10860   {
10861     /* MOD_0F2B_PREFIX_2 */
10862     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10863   },
10864   {
10865     /* MOD_0F2B_PREFIX_3 */
10866     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10867   },
10868   {
10869     /* MOD_0F50 */
10870     { Bad_Opcode },
10871     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10872   },
10873   {
10874     /* MOD_0F71_REG_2 */
10875     { Bad_Opcode },
10876     { "psrlw",          { MS, Ib }, 0 },
10877   },
10878   {
10879     /* MOD_0F71_REG_4 */
10880     { Bad_Opcode },
10881     { "psraw",          { MS, Ib }, 0 },
10882   },
10883   {
10884     /* MOD_0F71_REG_6 */
10885     { Bad_Opcode },
10886     { "psllw",          { MS, Ib }, 0 },
10887   },
10888   {
10889     /* MOD_0F72_REG_2 */
10890     { Bad_Opcode },
10891     { "psrld",          { MS, Ib }, 0 },
10892   },
10893   {
10894     /* MOD_0F72_REG_4 */
10895     { Bad_Opcode },
10896     { "psrad",          { MS, Ib }, 0 },
10897   },
10898   {
10899     /* MOD_0F72_REG_6 */
10900     { Bad_Opcode },
10901     { "pslld",          { MS, Ib }, 0 },
10902   },
10903   {
10904     /* MOD_0F73_REG_2 */
10905     { Bad_Opcode },
10906     { "psrlq",          { MS, Ib }, 0 },
10907   },
10908   {
10909     /* MOD_0F73_REG_3 */
10910     { Bad_Opcode },
10911     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10912   },
10913   {
10914     /* MOD_0F73_REG_6 */
10915     { Bad_Opcode },
10916     { "psllq",          { MS, Ib }, 0 },
10917   },
10918   {
10919     /* MOD_0F73_REG_7 */
10920     { Bad_Opcode },
10921     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10922   },
10923   {
10924     /* MOD_0FAE_REG_0 */
10925     { "fxsave",         { FXSAVE }, 0 },
10926     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10927   },
10928   {
10929     /* MOD_0FAE_REG_1 */
10930     { "fxrstor",        { FXSAVE }, 0 },
10931     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10932   },
10933   {
10934     /* MOD_0FAE_REG_2 */
10935     { "ldmxcsr",        { Md }, 0 },
10936     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10937   },
10938   {
10939     /* MOD_0FAE_REG_3 */
10940     { "stmxcsr",        { Md }, 0 },
10941     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10942   },
10943   {
10944     /* MOD_0FAE_REG_4 */
10945     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10946     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10947   },
10948   {
10949     /* MOD_0FAE_REG_5 */
10950     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10951     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10952   },
10953   {
10954     /* MOD_0FAE_REG_6 */
10955     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10956     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10957   },
10958   {
10959     /* MOD_0FAE_REG_7 */
10960     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10961     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10962   },
10963   {
10964     /* MOD_0FB2 */
10965     { "lssS",           { Gv, Mp }, 0 },
10966   },
10967   {
10968     /* MOD_0FB4 */
10969     { "lfsS",           { Gv, Mp }, 0 },
10970   },
10971   {
10972     /* MOD_0FB5 */
10973     { "lgsS",           { Gv, Mp }, 0 },
10974   },
10975   {
10976     /* MOD_0FC3 */
10977     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10978   },
10979   {
10980     /* MOD_0FC7_REG_3 */
10981     { "xrstors",        { FXSAVE }, 0 },
10982   },
10983   {
10984     /* MOD_0FC7_REG_4 */
10985     { "xsavec",         { FXSAVE }, 0 },
10986   },
10987   {
10988     /* MOD_0FC7_REG_5 */
10989     { "xsaves",         { FXSAVE }, 0 },
10990   },
10991   {
10992     /* MOD_0FC7_REG_6 */
10993     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10994     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10995   },
10996   {
10997     /* MOD_0FC7_REG_7 */
10998     { "vmptrst",        { Mq }, 0 },
10999     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
11000   },
11001   {
11002     /* MOD_0FD7 */
11003     { Bad_Opcode },
11004     { "pmovmskb",       { Gdq, MS }, 0 },
11005   },
11006   {
11007     /* MOD_0FE7_PREFIX_2 */
11008     { "movntdq",        { Mx, XM }, 0 },
11009   },
11010   {
11011     /* MOD_0FF0_PREFIX_3 */
11012     { "lddqu",          { XM, M }, 0 },
11013   },
11014   {
11015     /* MOD_0F382A_PREFIX_2 */
11016     { "movntdqa",       { XM, Mx }, 0 },
11017   },
11018   {
11019     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11020     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
11021     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
11022   },
11023   {
11024     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11025     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
11026   },
11027   {
11028     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11029     { Bad_Opcode },
11030     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11031   },
11032   {
11033     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11034     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11035   },
11036   {
11037     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11038     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11039   },
11040   {
11041     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11042     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11043   },
11044   {
11045     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11046     { Bad_Opcode },
11047     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11048   },
11049   {
11050     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11051     { Bad_Opcode },
11052     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11053   },
11054   {
11055     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11056     { Bad_Opcode },
11057     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11058   },
11059   {
11060     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11061     { Bad_Opcode },
11062     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11063   },
11064   {
11065     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11066     { Bad_Opcode },
11067     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11068   },
11069   {
11070     /* MOD_0F38F5_PREFIX_2 */
11071     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11072   },
11073   {
11074     /* MOD_0F38F6_PREFIX_0 */
11075     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11076   },
11077   {
11078     /* MOD_0F38F8_PREFIX_1 */
11079     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11080   },
11081   {
11082     /* MOD_0F38F8_PREFIX_2 */
11083     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11084   },
11085   {
11086     /* MOD_0F38F8_PREFIX_3 */
11087     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11088   },
11089   {
11090     /* MOD_0F38F9_PREFIX_0 */
11091     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11092   },
11093   {
11094     /* MOD_62_32BIT */
11095     { "bound{S|}",      { Gv, Ma }, 0 },
11096     { EVEX_TABLE (EVEX_0F) },
11097   },
11098   {
11099     /* MOD_C4_32BIT */
11100     { "lesS",           { Gv, Mp }, 0 },
11101     { VEX_C4_TABLE (VEX_0F) },
11102   },
11103   {
11104     /* MOD_C5_32BIT */
11105     { "ldsS",           { Gv, Mp }, 0 },
11106     { VEX_C5_TABLE (VEX_0F) },
11107   },
11108   {
11109     /* MOD_VEX_0F12_PREFIX_0 */
11110     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11111     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11112   },
11113   {
11114     /* MOD_VEX_0F12_PREFIX_2 */
11115     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11116   },
11117   {
11118     /* MOD_VEX_0F13 */
11119     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11120   },
11121   {
11122     /* MOD_VEX_0F16_PREFIX_0 */
11123     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11124     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11125   },
11126   {
11127     /* MOD_VEX_0F16_PREFIX_2 */
11128     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11129   },
11130   {
11131     /* MOD_VEX_0F17 */
11132     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11133   },
11134   {
11135     /* MOD_VEX_0F2B */
11136     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11137   },
11138   {
11139     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11140     { Bad_Opcode },
11141     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11142   },
11143   {
11144     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11145     { Bad_Opcode },
11146     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11147   },
11148   {
11149     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11150     { Bad_Opcode },
11151     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11152   },
11153   {
11154     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11155     { Bad_Opcode },
11156     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11157   },
11158   {
11159     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11160     { Bad_Opcode },
11161     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11162   },
11163   {
11164     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11165     { Bad_Opcode },
11166     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11167   },
11168   {
11169     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11170     { Bad_Opcode },
11171     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11172   },
11173   {
11174     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11175     { Bad_Opcode },
11176     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11177   },
11178   {
11179     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11180     { Bad_Opcode },
11181     { "knotw",          { MaskG, MaskR }, 0 },
11182   },
11183   {
11184     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11185     { Bad_Opcode },
11186     { "knotq",          { MaskG, MaskR }, 0 },
11187   },
11188   {
11189     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11190     { Bad_Opcode },
11191     { "knotb",          { MaskG, MaskR }, 0 },
11192   },
11193   {
11194     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11195     { Bad_Opcode },
11196     { "knotd",          { MaskG, MaskR }, 0 },
11197   },
11198   {
11199     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11200     { Bad_Opcode },
11201     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11202   },
11203   {
11204     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11205     { Bad_Opcode },
11206     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11207   },
11208   {
11209     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11210     { Bad_Opcode },
11211     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11212   },
11213   {
11214     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11215     { Bad_Opcode },
11216     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11217   },
11218  {
11219     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11220     { Bad_Opcode },
11221     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11222   },
11223   {
11224     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11225     { Bad_Opcode },
11226     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11227   },
11228   {
11229     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11230     { Bad_Opcode },
11231     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11232   },
11233   {
11234     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11235     { Bad_Opcode },
11236     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11237   },
11238   {
11239     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11240     { Bad_Opcode },
11241     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11242   },
11243   {
11244     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11245     { Bad_Opcode },
11246     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11247   },
11248   {
11249     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11250     { Bad_Opcode },
11251     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11252   },
11253   {
11254     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11255     { Bad_Opcode },
11256     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11257   },
11258   {
11259     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11260     { Bad_Opcode },
11261     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11262   },
11263   {
11264     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11265     { Bad_Opcode },
11266     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11267   },
11268   {
11269     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11270     { Bad_Opcode },
11271     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11272   },
11273   {
11274     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11275     { Bad_Opcode },
11276     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11277   },
11278   {
11279     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11280     { Bad_Opcode },
11281     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11282   },
11283   {
11284     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11285     { Bad_Opcode },
11286     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11287   },
11288   {
11289     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11290     { Bad_Opcode },
11291     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11292   },
11293   {
11294     /* MOD_VEX_0F50 */
11295     { Bad_Opcode },
11296     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11297   },
11298   {
11299     /* MOD_VEX_0F71_REG_2 */
11300     { Bad_Opcode },
11301     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11302   },
11303   {
11304     /* MOD_VEX_0F71_REG_4 */
11305     { Bad_Opcode },
11306     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11307   },
11308   {
11309     /* MOD_VEX_0F71_REG_6 */
11310     { Bad_Opcode },
11311     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11312   },
11313   {
11314     /* MOD_VEX_0F72_REG_2 */
11315     { Bad_Opcode },
11316     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11317   },
11318   {
11319     /* MOD_VEX_0F72_REG_4 */
11320     { Bad_Opcode },
11321     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11322   },
11323   {
11324     /* MOD_VEX_0F72_REG_6 */
11325     { Bad_Opcode },
11326     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11327   },
11328   {
11329     /* MOD_VEX_0F73_REG_2 */
11330     { Bad_Opcode },
11331     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11332   },
11333   {
11334     /* MOD_VEX_0F73_REG_3 */
11335     { Bad_Opcode },
11336     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11337   },
11338   {
11339     /* MOD_VEX_0F73_REG_6 */
11340     { Bad_Opcode },
11341     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11342   },
11343   {
11344     /* MOD_VEX_0F73_REG_7 */
11345     { Bad_Opcode },
11346     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11347   },
11348   {
11349     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11350     { "kmovw",          { Ew, MaskG }, 0 },
11351     { Bad_Opcode },
11352   },
11353   {
11354     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11355     { "kmovq",          { Eq, MaskG }, 0 },
11356     { Bad_Opcode },
11357   },
11358   {
11359     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11360     { "kmovb",          { Eb, MaskG }, 0 },
11361     { Bad_Opcode },
11362   },
11363   {
11364     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11365     { "kmovd",          { Ed, MaskG }, 0 },
11366     { Bad_Opcode },
11367   },
11368   {
11369     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11370     { Bad_Opcode },
11371     { "kmovw",          { MaskG, Rdq }, 0 },
11372   },
11373   {
11374     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11375     { Bad_Opcode },
11376     { "kmovb",          { MaskG, Rdq }, 0 },
11377   },
11378   {
11379     /* MOD_VEX_0F92_P_3_LEN_0 */
11380     { Bad_Opcode },
11381     { "kmovK",          { MaskG, Rdq }, 0 },
11382   },
11383   {
11384     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11385     { Bad_Opcode },
11386     { "kmovw",          { Gdq, MaskR }, 0 },
11387   },
11388   {
11389     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11390     { Bad_Opcode },
11391     { "kmovb",          { Gdq, MaskR }, 0 },
11392   },
11393   {
11394     /* MOD_VEX_0F93_P_3_LEN_0 */
11395     { Bad_Opcode },
11396     { "kmovK",          { Gdq, MaskR }, 0 },
11397   },
11398   {
11399     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11400     { Bad_Opcode },
11401     { "kortestw", { MaskG, MaskR }, 0 },
11402   },
11403   {
11404     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11405     { Bad_Opcode },
11406     { "kortestq", { MaskG, MaskR }, 0 },
11407   },
11408   {
11409     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11410     { Bad_Opcode },
11411     { "kortestb", { MaskG, MaskR }, 0 },
11412   },
11413   {
11414     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11415     { Bad_Opcode },
11416     { "kortestd", { MaskG, MaskR }, 0 },
11417   },
11418   {
11419     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11420     { Bad_Opcode },
11421     { "ktestw", { MaskG, MaskR }, 0 },
11422   },
11423   {
11424     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11425     { Bad_Opcode },
11426     { "ktestq", { MaskG, MaskR }, 0 },
11427   },
11428   {
11429     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11430     { Bad_Opcode },
11431     { "ktestb", { MaskG, MaskR }, 0 },
11432   },
11433   {
11434     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11435     { Bad_Opcode },
11436     { "ktestd", { MaskG, MaskR }, 0 },
11437   },
11438   {
11439     /* MOD_VEX_0FAE_REG_2 */
11440     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11441   },
11442   {
11443     /* MOD_VEX_0FAE_REG_3 */
11444     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11445   },
11446   {
11447     /* MOD_VEX_0FD7_PREFIX_2 */
11448     { Bad_Opcode },
11449     { "vpmovmskb",      { Gdq, XS }, 0 },
11450   },
11451   {
11452     /* MOD_VEX_0FE7_PREFIX_2 */
11453     { "vmovntdq",       { Mx, XM }, 0 },
11454   },
11455   {
11456     /* MOD_VEX_0FF0_PREFIX_3 */
11457     { "vlddqu",         { XM, M }, 0 },
11458   },
11459   {
11460     /* MOD_VEX_0F381A_PREFIX_2 */
11461     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11462   },
11463   {
11464     /* MOD_VEX_0F382A_PREFIX_2 */
11465     { "vmovntdqa",      { XM, Mx }, 0 },
11466   },
11467   {
11468     /* MOD_VEX_0F382C_PREFIX_2 */
11469     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11470   },
11471   {
11472     /* MOD_VEX_0F382D_PREFIX_2 */
11473     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11474   },
11475   {
11476     /* MOD_VEX_0F382E_PREFIX_2 */
11477     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11478   },
11479   {
11480     /* MOD_VEX_0F382F_PREFIX_2 */
11481     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11482   },
11483   {
11484     /* MOD_VEX_0F385A_PREFIX_2 */
11485     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11486   },
11487   {
11488     /* MOD_VEX_0F388C_PREFIX_2 */
11489     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11490   },
11491   {
11492     /* MOD_VEX_0F388E_PREFIX_2 */
11493     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11494   },
11495   {
11496     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11497     { Bad_Opcode },
11498     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11499   },
11500   {
11501     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11502     { Bad_Opcode },
11503     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11504   },
11505   {
11506     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11507     { Bad_Opcode },
11508     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11509   },
11510   {
11511     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11512     { Bad_Opcode },
11513     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11514   },
11515   {
11516     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11517     { Bad_Opcode },
11518     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11519   },
11520   {
11521     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11522     { Bad_Opcode },
11523     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11524   },
11525   {
11526     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11527     { Bad_Opcode },
11528     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11529   },
11530   {
11531     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11532     { Bad_Opcode },
11533     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11534   },
11535   {
11536     /* MOD_VEX_0FXOP_09_12 */
11537     { Bad_Opcode },
11538     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11539   },
11540
11541 #include "i386-dis-evex-mod.h"
11542 };
11543
11544 static const struct dis386 rm_table[][8] = {
11545   {
11546     /* RM_C6_REG_7 */
11547     { "xabort",         { Skip_MODRM, Ib }, 0 },
11548   },
11549   {
11550     /* RM_C7_REG_7 */
11551     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11552   },
11553   {
11554     /* RM_0F01_REG_0 */
11555     { "enclv",          { Skip_MODRM }, 0 },
11556     { "vmcall",         { Skip_MODRM }, 0 },
11557     { "vmlaunch",       { Skip_MODRM }, 0 },
11558     { "vmresume",       { Skip_MODRM }, 0 },
11559     { "vmxoff",         { Skip_MODRM }, 0 },
11560     { "pconfig",        { Skip_MODRM }, 0 },
11561   },
11562   {
11563     /* RM_0F01_REG_1 */
11564     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11565     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11566     { "clac",           { Skip_MODRM }, 0 },
11567     { "stac",           { Skip_MODRM }, 0 },
11568     { Bad_Opcode },
11569     { Bad_Opcode },
11570     { Bad_Opcode },
11571     { "encls",          { Skip_MODRM }, 0 },
11572   },
11573   {
11574     /* RM_0F01_REG_2 */
11575     { "xgetbv",         { Skip_MODRM }, 0 },
11576     { "xsetbv",         { Skip_MODRM }, 0 },
11577     { Bad_Opcode },
11578     { Bad_Opcode },
11579     { "vmfunc",         { Skip_MODRM }, 0 },
11580     { "xend",           { Skip_MODRM }, 0 },
11581     { "xtest",          { Skip_MODRM }, 0 },
11582     { "enclu",          { Skip_MODRM }, 0 },
11583   },
11584   {
11585     /* RM_0F01_REG_3 */
11586     { "vmrun",          { Skip_MODRM }, 0 },
11587     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11588     { "vmload",         { Skip_MODRM }, 0 },
11589     { "vmsave",         { Skip_MODRM }, 0 },
11590     { "stgi",           { Skip_MODRM }, 0 },
11591     { "clgi",           { Skip_MODRM }, 0 },
11592     { "skinit",         { Skip_MODRM }, 0 },
11593     { "invlpga",        { Skip_MODRM }, 0 },
11594   },
11595   {
11596     /* RM_0F01_REG_5_MOD_3 */
11597     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11598     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11599     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11600     { Bad_Opcode },
11601     { Bad_Opcode },
11602     { Bad_Opcode },
11603     { "rdpkru",         { Skip_MODRM }, 0 },
11604     { "wrpkru",         { Skip_MODRM }, 0 },
11605   },
11606   {
11607     /* RM_0F01_REG_7_MOD_3 */
11608     { "swapgs",         { Skip_MODRM }, 0  },
11609     { "rdtscp",         { Skip_MODRM }, 0  },
11610     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11611     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11612     { "clzero",         { Skip_MODRM }, 0  },
11613     { "rdpru",          { Skip_MODRM }, 0  },
11614   },
11615   {
11616     /* RM_0F1E_P_1_MOD_3_REG_7 */
11617     { "nopQ",           { Ev }, 0 },
11618     { "nopQ",           { Ev }, 0 },
11619     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11620     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11621     { "nopQ",           { Ev }, 0 },
11622     { "nopQ",           { Ev }, 0 },
11623     { "nopQ",           { Ev }, 0 },
11624     { "nopQ",           { Ev }, 0 },
11625   },
11626   {
11627     /* RM_0FAE_REG_6_MOD_3 */
11628     { "mfence",         { Skip_MODRM }, 0 },
11629   },
11630   {
11631     /* RM_0FAE_REG_7_MOD_3 */
11632     { "sfence",         { Skip_MODRM }, 0 },
11633
11634   },
11635   {
11636     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11637     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11638   },
11639 };
11640
11641 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11642
11643 /* We use the high bit to indicate different name for the same
11644    prefix.  */
11645 #define REP_PREFIX      (0xf3 | 0x100)
11646 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11647 #define XRELEASE_PREFIX (0xf3 | 0x400)
11648 #define BND_PREFIX      (0xf2 | 0x400)
11649 #define NOTRACK_PREFIX  (0x3e | 0x100)
11650
11651 /* Remember if the current op is a jump instruction.  */
11652 static bfd_boolean op_is_jump = FALSE;
11653
11654 static int
11655 ckprefix (void)
11656 {
11657   int newrex, i, length;
11658   rex = 0;
11659   prefixes = 0;
11660   used_prefixes = 0;
11661   rex_used = 0;
11662   last_lock_prefix = -1;
11663   last_repz_prefix = -1;
11664   last_repnz_prefix = -1;
11665   last_data_prefix = -1;
11666   last_addr_prefix = -1;
11667   last_rex_prefix = -1;
11668   last_seg_prefix = -1;
11669   fwait_prefix = -1;
11670   active_seg_prefix = 0;
11671   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11672     all_prefixes[i] = 0;
11673   i = 0;
11674   length = 0;
11675   /* The maximum instruction length is 15bytes.  */
11676   while (length < MAX_CODE_LENGTH - 1)
11677     {
11678       FETCH_DATA (the_info, codep + 1);
11679       newrex = 0;
11680       switch (*codep)
11681         {
11682         /* REX prefixes family.  */
11683         case 0x40:
11684         case 0x41:
11685         case 0x42:
11686         case 0x43:
11687         case 0x44:
11688         case 0x45:
11689         case 0x46:
11690         case 0x47:
11691         case 0x48:
11692         case 0x49:
11693         case 0x4a:
11694         case 0x4b:
11695         case 0x4c:
11696         case 0x4d:
11697         case 0x4e:
11698         case 0x4f:
11699           if (address_mode == mode_64bit)
11700             newrex = *codep;
11701           else
11702             return 1;
11703           last_rex_prefix = i;
11704           break;
11705         case 0xf3:
11706           prefixes |= PREFIX_REPZ;
11707           last_repz_prefix = i;
11708           break;
11709         case 0xf2:
11710           prefixes |= PREFIX_REPNZ;
11711           last_repnz_prefix = i;
11712           break;
11713         case 0xf0:
11714           prefixes |= PREFIX_LOCK;
11715           last_lock_prefix = i;
11716           break;
11717         case 0x2e:
11718           prefixes |= PREFIX_CS;
11719           last_seg_prefix = i;
11720           active_seg_prefix = PREFIX_CS;
11721           break;
11722         case 0x36:
11723           prefixes |= PREFIX_SS;
11724           last_seg_prefix = i;
11725           active_seg_prefix = PREFIX_SS;
11726           break;
11727         case 0x3e:
11728           prefixes |= PREFIX_DS;
11729           last_seg_prefix = i;
11730           active_seg_prefix = PREFIX_DS;
11731           break;
11732         case 0x26:
11733           prefixes |= PREFIX_ES;
11734           last_seg_prefix = i;
11735           active_seg_prefix = PREFIX_ES;
11736           break;
11737         case 0x64:
11738           prefixes |= PREFIX_FS;
11739           last_seg_prefix = i;
11740           active_seg_prefix = PREFIX_FS;
11741           break;
11742         case 0x65:
11743           prefixes |= PREFIX_GS;
11744           last_seg_prefix = i;
11745           active_seg_prefix = PREFIX_GS;
11746           break;
11747         case 0x66:
11748           prefixes |= PREFIX_DATA;
11749           last_data_prefix = i;
11750           break;
11751         case 0x67:
11752           prefixes |= PREFIX_ADDR;
11753           last_addr_prefix = i;
11754           break;
11755         case FWAIT_OPCODE:
11756           /* fwait is really an instruction.  If there are prefixes
11757              before the fwait, they belong to the fwait, *not* to the
11758              following instruction.  */
11759           fwait_prefix = i;
11760           if (prefixes || rex)
11761             {
11762               prefixes |= PREFIX_FWAIT;
11763               codep++;
11764               /* This ensures that the previous REX prefixes are noticed
11765                  as unused prefixes, as in the return case below.  */
11766               rex_used = rex;
11767               return 1;
11768             }
11769           prefixes = PREFIX_FWAIT;
11770           break;
11771         default:
11772           return 1;
11773         }
11774       /* Rex is ignored when followed by another prefix.  */
11775       if (rex)
11776         {
11777           rex_used = rex;
11778           return 1;
11779         }
11780       if (*codep != FWAIT_OPCODE)
11781         all_prefixes[i++] = *codep;
11782       rex = newrex;
11783       codep++;
11784       length++;
11785     }
11786   return 0;
11787 }
11788
11789 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11790    prefix byte.  */
11791
11792 static const char *
11793 prefix_name (int pref, int sizeflag)
11794 {
11795   static const char *rexes [16] =
11796     {
11797       "rex",            /* 0x40 */
11798       "rex.B",          /* 0x41 */
11799       "rex.X",          /* 0x42 */
11800       "rex.XB",         /* 0x43 */
11801       "rex.R",          /* 0x44 */
11802       "rex.RB",         /* 0x45 */
11803       "rex.RX",         /* 0x46 */
11804       "rex.RXB",        /* 0x47 */
11805       "rex.W",          /* 0x48 */
11806       "rex.WB",         /* 0x49 */
11807       "rex.WX",         /* 0x4a */
11808       "rex.WXB",        /* 0x4b */
11809       "rex.WR",         /* 0x4c */
11810       "rex.WRB",        /* 0x4d */
11811       "rex.WRX",        /* 0x4e */
11812       "rex.WRXB",       /* 0x4f */
11813     };
11814
11815   switch (pref)
11816     {
11817     /* REX prefixes family.  */
11818     case 0x40:
11819     case 0x41:
11820     case 0x42:
11821     case 0x43:
11822     case 0x44:
11823     case 0x45:
11824     case 0x46:
11825     case 0x47:
11826     case 0x48:
11827     case 0x49:
11828     case 0x4a:
11829     case 0x4b:
11830     case 0x4c:
11831     case 0x4d:
11832     case 0x4e:
11833     case 0x4f:
11834       return rexes [pref - 0x40];
11835     case 0xf3:
11836       return "repz";
11837     case 0xf2:
11838       return "repnz";
11839     case 0xf0:
11840       return "lock";
11841     case 0x2e:
11842       return "cs";
11843     case 0x36:
11844       return "ss";
11845     case 0x3e:
11846       return "ds";
11847     case 0x26:
11848       return "es";
11849     case 0x64:
11850       return "fs";
11851     case 0x65:
11852       return "gs";
11853     case 0x66:
11854       return (sizeflag & DFLAG) ? "data16" : "data32";
11855     case 0x67:
11856       if (address_mode == mode_64bit)
11857         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11858       else
11859         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11860     case FWAIT_OPCODE:
11861       return "fwait";
11862     case REP_PREFIX:
11863       return "rep";
11864     case XACQUIRE_PREFIX:
11865       return "xacquire";
11866     case XRELEASE_PREFIX:
11867       return "xrelease";
11868     case BND_PREFIX:
11869       return "bnd";
11870     case NOTRACK_PREFIX:
11871       return "notrack";
11872     default:
11873       return NULL;
11874     }
11875 }
11876
11877 static char op_out[MAX_OPERANDS][100];
11878 static int op_ad, op_index[MAX_OPERANDS];
11879 static int two_source_ops;
11880 static bfd_vma op_address[MAX_OPERANDS];
11881 static bfd_vma op_riprel[MAX_OPERANDS];
11882 static bfd_vma start_pc;
11883
11884 /*
11885  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11886  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11887  *   section of the "Virtual 8086 Mode" chapter.)
11888  * 'pc' should be the address of this instruction, it will
11889  *   be used to print the target address if this is a relative jump or call
11890  * The function returns the length of this instruction in bytes.
11891  */
11892
11893 static char intel_syntax;
11894 static char intel_mnemonic = !SYSV386_COMPAT;
11895 static char open_char;
11896 static char close_char;
11897 static char separator_char;
11898 static char scale_char;
11899
11900 enum x86_64_isa
11901 {
11902   amd64 = 1,
11903   intel64
11904 };
11905
11906 static enum x86_64_isa isa64;
11907
11908 /* Here for backwards compatibility.  When gdb stops using
11909    print_insn_i386_att and print_insn_i386_intel these functions can
11910    disappear, and print_insn_i386 be merged into print_insn.  */
11911 int
11912 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11913 {
11914   intel_syntax = 0;
11915
11916   return print_insn (pc, info);
11917 }
11918
11919 int
11920 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11921 {
11922   intel_syntax = 1;
11923
11924   return print_insn (pc, info);
11925 }
11926
11927 int
11928 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11929 {
11930   intel_syntax = -1;
11931
11932   return print_insn (pc, info);
11933 }
11934
11935 void
11936 print_i386_disassembler_options (FILE *stream)
11937 {
11938   fprintf (stream, _("\n\
11939 The following i386/x86-64 specific disassembler options are supported for use\n\
11940 with the -M switch (multiple options should be separated by commas):\n"));
11941
11942   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11943   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11944   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11945   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11946   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11947   fprintf (stream, _("  att-mnemonic\n"
11948                      "              Display instruction in AT&T mnemonic\n"));
11949   fprintf (stream, _("  intel-mnemonic\n"
11950                      "              Display instruction in Intel mnemonic\n"));
11951   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11952   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11953   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11954   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11955   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11956   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11957   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11958   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11959 }
11960
11961 /* Bad opcode.  */
11962 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11963
11964 /* Get a pointer to struct dis386 with a valid name.  */
11965
11966 static const struct dis386 *
11967 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11968 {
11969   int vindex, vex_table_index;
11970
11971   if (dp->name != NULL)
11972     return dp;
11973
11974   switch (dp->op[0].bytemode)
11975     {
11976     case USE_REG_TABLE:
11977       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11978       break;
11979
11980     case USE_MOD_TABLE:
11981       vindex = modrm.mod == 0x3 ? 1 : 0;
11982       dp = &mod_table[dp->op[1].bytemode][vindex];
11983       break;
11984
11985     case USE_RM_TABLE:
11986       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11987       break;
11988
11989     case USE_PREFIX_TABLE:
11990       if (need_vex)
11991         {
11992           /* The prefix in VEX is implicit.  */
11993           switch (vex.prefix)
11994             {
11995             case 0:
11996               vindex = 0;
11997               break;
11998             case REPE_PREFIX_OPCODE:
11999               vindex = 1;
12000               break;
12001             case DATA_PREFIX_OPCODE:
12002               vindex = 2;
12003               break;
12004             case REPNE_PREFIX_OPCODE:
12005               vindex = 3;
12006               break;
12007             default:
12008               abort ();
12009               break;
12010             }
12011         }
12012       else
12013         {
12014           int last_prefix = -1;
12015           int prefix = 0;
12016           vindex = 0;
12017           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12018              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12019              last one wins.  */
12020           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12021             {
12022               if (last_repz_prefix > last_repnz_prefix)
12023                 {
12024                   vindex = 1;
12025                   prefix = PREFIX_REPZ;
12026                   last_prefix = last_repz_prefix;
12027                 }
12028               else
12029                 {
12030                   vindex = 3;
12031                   prefix = PREFIX_REPNZ;
12032                   last_prefix = last_repnz_prefix;
12033                 }
12034
12035               /* Check if prefix should be ignored.  */
12036               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12037                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12038                    & prefix) != 0)
12039                 vindex = 0;
12040             }
12041
12042           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12043             {
12044               vindex = 2;
12045               prefix = PREFIX_DATA;
12046               last_prefix = last_data_prefix;
12047             }
12048
12049           if (vindex != 0)
12050             {
12051               used_prefixes |= prefix;
12052               all_prefixes[last_prefix] = 0;
12053             }
12054         }
12055       dp = &prefix_table[dp->op[1].bytemode][vindex];
12056       break;
12057
12058     case USE_X86_64_TABLE:
12059       vindex = address_mode == mode_64bit ? 1 : 0;
12060       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12061       break;
12062
12063     case USE_3BYTE_TABLE:
12064       FETCH_DATA (info, codep + 2);
12065       vindex = *codep++;
12066       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12067       end_codep = codep;
12068       modrm.mod = (*codep >> 6) & 3;
12069       modrm.reg = (*codep >> 3) & 7;
12070       modrm.rm = *codep & 7;
12071       break;
12072
12073     case USE_VEX_LEN_TABLE:
12074       if (!need_vex)
12075         abort ();
12076
12077       switch (vex.length)
12078         {
12079         case 128:
12080           vindex = 0;
12081           break;
12082         case 256:
12083           vindex = 1;
12084           break;
12085         default:
12086           abort ();
12087           break;
12088         }
12089
12090       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12091       break;
12092
12093     case USE_EVEX_LEN_TABLE:
12094       if (!vex.evex)
12095         abort ();
12096
12097       switch (vex.length)
12098         {
12099         case 128:
12100           vindex = 0;
12101           break;
12102         case 256:
12103           vindex = 1;
12104           break;
12105         case 512:
12106           vindex = 2;
12107           break;
12108         default:
12109           abort ();
12110           break;
12111         }
12112
12113       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12114       break;
12115
12116     case USE_XOP_8F_TABLE:
12117       FETCH_DATA (info, codep + 3);
12118       rex = ~(*codep >> 5) & 0x7;
12119
12120       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12121       switch ((*codep & 0x1f))
12122         {
12123         default:
12124           dp = &bad_opcode;
12125           return dp;
12126         case 0x8:
12127           vex_table_index = XOP_08;
12128           break;
12129         case 0x9:
12130           vex_table_index = XOP_09;
12131           break;
12132         case 0xa:
12133           vex_table_index = XOP_0A;
12134           break;
12135         }
12136       codep++;
12137       vex.w = *codep & 0x80;
12138       if (vex.w && address_mode == mode_64bit)
12139         rex |= REX_W;
12140
12141       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12142       if (address_mode != mode_64bit)
12143         {
12144           /* In 16/32-bit mode REX_B is silently ignored.  */
12145           rex &= ~REX_B;
12146         }
12147
12148       vex.length = (*codep & 0x4) ? 256 : 128;
12149       switch ((*codep & 0x3))
12150         {
12151         case 0:
12152           break;
12153         case 1:
12154           vex.prefix = DATA_PREFIX_OPCODE;
12155           break;
12156         case 2:
12157           vex.prefix = REPE_PREFIX_OPCODE;
12158           break;
12159         case 3:
12160           vex.prefix = REPNE_PREFIX_OPCODE;
12161           break;
12162         }
12163       need_vex = 1;
12164       need_vex_reg = 1;
12165       codep++;
12166       vindex = *codep++;
12167       dp = &xop_table[vex_table_index][vindex];
12168
12169       end_codep = codep;
12170       FETCH_DATA (info, codep + 1);
12171       modrm.mod = (*codep >> 6) & 3;
12172       modrm.reg = (*codep >> 3) & 7;
12173       modrm.rm = *codep & 7;
12174
12175       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12176          having to decode the bits for every otherwise valid encoding.  */
12177       if (vex.prefix)
12178         return &bad_opcode;
12179       break;
12180
12181     case USE_VEX_C4_TABLE:
12182       /* VEX prefix.  */
12183       FETCH_DATA (info, codep + 3);
12184       rex = ~(*codep >> 5) & 0x7;
12185       switch ((*codep & 0x1f))
12186         {
12187         default:
12188           dp = &bad_opcode;
12189           return dp;
12190         case 0x1:
12191           vex_table_index = VEX_0F;
12192           break;
12193         case 0x2:
12194           vex_table_index = VEX_0F38;
12195           break;
12196         case 0x3:
12197           vex_table_index = VEX_0F3A;
12198           break;
12199         }
12200       codep++;
12201       vex.w = *codep & 0x80;
12202       if (address_mode == mode_64bit)
12203         {
12204           if (vex.w)
12205             rex |= REX_W;
12206         }
12207       else
12208         {
12209           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12210              is ignored, other REX bits are 0 and the highest bit in
12211              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12212           rex = 0;
12213         }
12214       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12215       vex.length = (*codep & 0x4) ? 256 : 128;
12216       switch ((*codep & 0x3))
12217         {
12218         case 0:
12219           break;
12220         case 1:
12221           vex.prefix = DATA_PREFIX_OPCODE;
12222           break;
12223         case 2:
12224           vex.prefix = REPE_PREFIX_OPCODE;
12225           break;
12226         case 3:
12227           vex.prefix = REPNE_PREFIX_OPCODE;
12228           break;
12229         }
12230       need_vex = 1;
12231       need_vex_reg = 1;
12232       codep++;
12233       vindex = *codep++;
12234       dp = &vex_table[vex_table_index][vindex];
12235       end_codep = codep;
12236       /* There is no MODRM byte for VEX0F 77.  */
12237       if (vex_table_index != VEX_0F || vindex != 0x77)
12238         {
12239           FETCH_DATA (info, codep + 1);
12240           modrm.mod = (*codep >> 6) & 3;
12241           modrm.reg = (*codep >> 3) & 7;
12242           modrm.rm = *codep & 7;
12243         }
12244       break;
12245
12246     case USE_VEX_C5_TABLE:
12247       /* VEX prefix.  */
12248       FETCH_DATA (info, codep + 2);
12249       rex = (*codep & 0x80) ? 0 : REX_R;
12250
12251       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12252          VEX.vvvv is 1.  */
12253       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12254       vex.length = (*codep & 0x4) ? 256 : 128;
12255       switch ((*codep & 0x3))
12256         {
12257         case 0:
12258           break;
12259         case 1:
12260           vex.prefix = DATA_PREFIX_OPCODE;
12261           break;
12262         case 2:
12263           vex.prefix = REPE_PREFIX_OPCODE;
12264           break;
12265         case 3:
12266           vex.prefix = REPNE_PREFIX_OPCODE;
12267           break;
12268         }
12269       need_vex = 1;
12270       need_vex_reg = 1;
12271       codep++;
12272       vindex = *codep++;
12273       dp = &vex_table[dp->op[1].bytemode][vindex];
12274       end_codep = codep;
12275       /* There is no MODRM byte for VEX 77.  */
12276       if (vindex != 0x77)
12277         {
12278           FETCH_DATA (info, codep + 1);
12279           modrm.mod = (*codep >> 6) & 3;
12280           modrm.reg = (*codep >> 3) & 7;
12281           modrm.rm = *codep & 7;
12282         }
12283       break;
12284
12285     case USE_VEX_W_TABLE:
12286       if (!need_vex)
12287         abort ();
12288
12289       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12290       break;
12291
12292     case USE_EVEX_TABLE:
12293       two_source_ops = 0;
12294       /* EVEX prefix.  */
12295       vex.evex = 1;
12296       FETCH_DATA (info, codep + 4);
12297       /* The first byte after 0x62.  */
12298       rex = ~(*codep >> 5) & 0x7;
12299       vex.r = *codep & 0x10;
12300       switch ((*codep & 0xf))
12301         {
12302         default:
12303           return &bad_opcode;
12304         case 0x1:
12305           vex_table_index = EVEX_0F;
12306           break;
12307         case 0x2:
12308           vex_table_index = EVEX_0F38;
12309           break;
12310         case 0x3:
12311           vex_table_index = EVEX_0F3A;
12312           break;
12313         }
12314
12315       /* The second byte after 0x62.  */
12316       codep++;
12317       vex.w = *codep & 0x80;
12318       if (vex.w && address_mode == mode_64bit)
12319         rex |= REX_W;
12320
12321       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12322
12323       /* The U bit.  */
12324       if (!(*codep & 0x4))
12325         return &bad_opcode;
12326
12327       switch ((*codep & 0x3))
12328         {
12329         case 0:
12330           break;
12331         case 1:
12332           vex.prefix = DATA_PREFIX_OPCODE;
12333           break;
12334         case 2:
12335           vex.prefix = REPE_PREFIX_OPCODE;
12336           break;
12337         case 3:
12338           vex.prefix = REPNE_PREFIX_OPCODE;
12339           break;
12340         }
12341
12342       /* The third byte after 0x62.  */
12343       codep++;
12344
12345       /* Remember the static rounding bits.  */
12346       vex.ll = (*codep >> 5) & 3;
12347       vex.b = (*codep & 0x10) != 0;
12348
12349       vex.v = *codep & 0x8;
12350       vex.mask_register_specifier = *codep & 0x7;
12351       vex.zeroing = *codep & 0x80;
12352
12353       if (address_mode != mode_64bit)
12354         {
12355           /* In 16/32-bit mode silently ignore following bits.  */
12356           rex &= ~REX_B;
12357           vex.r = 1;
12358           vex.v = 1;
12359         }
12360
12361       need_vex = 1;
12362       need_vex_reg = 1;
12363       codep++;
12364       vindex = *codep++;
12365       dp = &evex_table[vex_table_index][vindex];
12366       end_codep = codep;
12367       FETCH_DATA (info, codep + 1);
12368       modrm.mod = (*codep >> 6) & 3;
12369       modrm.reg = (*codep >> 3) & 7;
12370       modrm.rm = *codep & 7;
12371
12372       /* Set vector length.  */
12373       if (modrm.mod == 3 && vex.b)
12374         vex.length = 512;
12375       else
12376         {
12377           switch (vex.ll)
12378             {
12379             case 0x0:
12380               vex.length = 128;
12381               break;
12382             case 0x1:
12383               vex.length = 256;
12384               break;
12385             case 0x2:
12386               vex.length = 512;
12387               break;
12388             default:
12389               return &bad_opcode;
12390             }
12391         }
12392       break;
12393
12394     case 0:
12395       dp = &bad_opcode;
12396       break;
12397
12398     default:
12399       abort ();
12400     }
12401
12402   if (dp->name != NULL)
12403     return dp;
12404   else
12405     return get_valid_dis386 (dp, info);
12406 }
12407
12408 static void
12409 get_sib (disassemble_info *info, int sizeflag)
12410 {
12411   /* If modrm.mod == 3, operand must be register.  */
12412   if (need_modrm
12413       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12414       && modrm.mod != 3
12415       && modrm.rm == 4)
12416     {
12417       FETCH_DATA (info, codep + 2);
12418       sib.index = (codep [1] >> 3) & 7;
12419       sib.scale = (codep [1] >> 6) & 3;
12420       sib.base = codep [1] & 7;
12421     }
12422 }
12423
12424 static int
12425 print_insn (bfd_vma pc, disassemble_info *info)
12426 {
12427   const struct dis386 *dp;
12428   int i;
12429   char *op_txt[MAX_OPERANDS];
12430   int needcomma;
12431   int sizeflag, orig_sizeflag;
12432   const char *p;
12433   struct dis_private priv;
12434   int prefix_length;
12435
12436   priv.orig_sizeflag = AFLAG | DFLAG;
12437   if ((info->mach & bfd_mach_i386_i386) != 0)
12438     address_mode = mode_32bit;
12439   else if (info->mach == bfd_mach_i386_i8086)
12440     {
12441       address_mode = mode_16bit;
12442       priv.orig_sizeflag = 0;
12443     }
12444   else
12445     address_mode = mode_64bit;
12446
12447   if (intel_syntax == (char) -1)
12448     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12449
12450   for (p = info->disassembler_options; p != NULL; )
12451     {
12452       if (CONST_STRNEQ (p, "amd64"))
12453         isa64 = amd64;
12454       else if (CONST_STRNEQ (p, "intel64"))
12455         isa64 = intel64;
12456       else if (CONST_STRNEQ (p, "x86-64"))
12457         {
12458           address_mode = mode_64bit;
12459           priv.orig_sizeflag |= AFLAG | DFLAG;
12460         }
12461       else if (CONST_STRNEQ (p, "i386"))
12462         {
12463           address_mode = mode_32bit;
12464           priv.orig_sizeflag |= AFLAG | DFLAG;
12465         }
12466       else if (CONST_STRNEQ (p, "i8086"))
12467         {
12468           address_mode = mode_16bit;
12469           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12470         }
12471       else if (CONST_STRNEQ (p, "intel"))
12472         {
12473           intel_syntax = 1;
12474           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12475             intel_mnemonic = 1;
12476         }
12477       else if (CONST_STRNEQ (p, "att"))
12478         {
12479           intel_syntax = 0;
12480           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12481             intel_mnemonic = 0;
12482         }
12483       else if (CONST_STRNEQ (p, "addr"))
12484         {
12485           if (address_mode == mode_64bit)
12486             {
12487               if (p[4] == '3' && p[5] == '2')
12488                 priv.orig_sizeflag &= ~AFLAG;
12489               else if (p[4] == '6' && p[5] == '4')
12490                 priv.orig_sizeflag |= AFLAG;
12491             }
12492           else
12493             {
12494               if (p[4] == '1' && p[5] == '6')
12495                 priv.orig_sizeflag &= ~AFLAG;
12496               else if (p[4] == '3' && p[5] == '2')
12497                 priv.orig_sizeflag |= AFLAG;
12498             }
12499         }
12500       else if (CONST_STRNEQ (p, "data"))
12501         {
12502           if (p[4] == '1' && p[5] == '6')
12503             priv.orig_sizeflag &= ~DFLAG;
12504           else if (p[4] == '3' && p[5] == '2')
12505             priv.orig_sizeflag |= DFLAG;
12506         }
12507       else if (CONST_STRNEQ (p, "suffix"))
12508         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12509
12510       p = strchr (p, ',');
12511       if (p != NULL)
12512         p++;
12513     }
12514
12515   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12516     {
12517       (*info->fprintf_func) (info->stream,
12518                              _("64-bit address is disabled"));
12519       return -1;
12520     }
12521
12522   if (intel_syntax)
12523     {
12524       names64 = intel_names64;
12525       names32 = intel_names32;
12526       names16 = intel_names16;
12527       names8 = intel_names8;
12528       names8rex = intel_names8rex;
12529       names_seg = intel_names_seg;
12530       names_mm = intel_names_mm;
12531       names_bnd = intel_names_bnd;
12532       names_xmm = intel_names_xmm;
12533       names_ymm = intel_names_ymm;
12534       names_zmm = intel_names_zmm;
12535       names_tmm = intel_names_tmm;
12536       index64 = intel_index64;
12537       index32 = intel_index32;
12538       names_mask = intel_names_mask;
12539       index16 = intel_index16;
12540       open_char = '[';
12541       close_char = ']';
12542       separator_char = '+';
12543       scale_char = '*';
12544     }
12545   else
12546     {
12547       names64 = att_names64;
12548       names32 = att_names32;
12549       names16 = att_names16;
12550       names8 = att_names8;
12551       names8rex = att_names8rex;
12552       names_seg = att_names_seg;
12553       names_mm = att_names_mm;
12554       names_bnd = att_names_bnd;
12555       names_xmm = att_names_xmm;
12556       names_ymm = att_names_ymm;
12557       names_zmm = att_names_zmm;
12558       names_tmm = att_names_tmm;
12559       index64 = att_index64;
12560       index32 = att_index32;
12561       names_mask = att_names_mask;
12562       index16 = att_index16;
12563       open_char = '(';
12564       close_char =  ')';
12565       separator_char = ',';
12566       scale_char = ',';
12567     }
12568
12569   /* The output looks better if we put 7 bytes on a line, since that
12570      puts most long word instructions on a single line.  Use 8 bytes
12571      for Intel L1OM.  */
12572   if ((info->mach & bfd_mach_l1om) != 0)
12573     info->bytes_per_line = 8;
12574   else
12575     info->bytes_per_line = 7;
12576
12577   info->private_data = &priv;
12578   priv.max_fetched = priv.the_buffer;
12579   priv.insn_start = pc;
12580
12581   obuf[0] = 0;
12582   for (i = 0; i < MAX_OPERANDS; ++i)
12583     {
12584       op_out[i][0] = 0;
12585       op_index[i] = -1;
12586     }
12587
12588   the_info = info;
12589   start_pc = pc;
12590   start_codep = priv.the_buffer;
12591   codep = priv.the_buffer;
12592
12593   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12594     {
12595       const char *name;
12596
12597       /* Getting here means we tried for data but didn't get it.  That
12598          means we have an incomplete instruction of some sort.  Just
12599          print the first byte as a prefix or a .byte pseudo-op.  */
12600       if (codep > priv.the_buffer)
12601         {
12602           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12603           if (name != NULL)
12604             (*info->fprintf_func) (info->stream, "%s", name);
12605           else
12606             {
12607               /* Just print the first byte as a .byte instruction.  */
12608               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12609                                      (unsigned int) priv.the_buffer[0]);
12610             }
12611
12612           return 1;
12613         }
12614
12615       return -1;
12616     }
12617
12618   obufp = obuf;
12619   sizeflag = priv.orig_sizeflag;
12620
12621   if (!ckprefix () || rex_used)
12622     {
12623       /* Too many prefixes or unused REX prefixes.  */
12624       for (i = 0;
12625            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12626            i++)
12627         (*info->fprintf_func) (info->stream, "%s%s",
12628                                i == 0 ? "" : " ",
12629                                prefix_name (all_prefixes[i], sizeflag));
12630       return i;
12631     }
12632
12633   insn_codep = codep;
12634
12635   FETCH_DATA (info, codep + 1);
12636   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12637
12638   if (((prefixes & PREFIX_FWAIT)
12639        && ((*codep < 0xd8) || (*codep > 0xdf))))
12640     {
12641       /* Handle prefixes before fwait.  */
12642       for (i = 0; i < fwait_prefix && all_prefixes[i];
12643            i++)
12644         (*info->fprintf_func) (info->stream, "%s ",
12645                                prefix_name (all_prefixes[i], sizeflag));
12646       (*info->fprintf_func) (info->stream, "fwait");
12647       return i + 1;
12648     }
12649
12650   if (*codep == 0x0f)
12651     {
12652       unsigned char threebyte;
12653
12654       codep++;
12655       FETCH_DATA (info, codep + 1);
12656       threebyte = *codep;
12657       dp = &dis386_twobyte[threebyte];
12658       need_modrm = twobyte_has_modrm[*codep];
12659       codep++;
12660     }
12661   else
12662     {
12663       dp = &dis386[*codep];
12664       need_modrm = onebyte_has_modrm[*codep];
12665       codep++;
12666     }
12667
12668   /* Save sizeflag for printing the extra prefixes later before updating
12669      it for mnemonic and operand processing.  The prefix names depend
12670      only on the address mode.  */
12671   orig_sizeflag = sizeflag;
12672   if (prefixes & PREFIX_ADDR)
12673     sizeflag ^= AFLAG;
12674   if ((prefixes & PREFIX_DATA))
12675     sizeflag ^= DFLAG;
12676
12677   end_codep = codep;
12678   if (need_modrm)
12679     {
12680       FETCH_DATA (info, codep + 1);
12681       modrm.mod = (*codep >> 6) & 3;
12682       modrm.reg = (*codep >> 3) & 7;
12683       modrm.rm = *codep & 7;
12684     }
12685
12686   need_vex = 0;
12687   need_vex_reg = 0;
12688   memset (&vex, 0, sizeof (vex));
12689
12690   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12691     {
12692       get_sib (info, sizeflag);
12693       dofloat (sizeflag);
12694     }
12695   else
12696     {
12697       dp = get_valid_dis386 (dp, info);
12698       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12699         {
12700           get_sib (info, sizeflag);
12701           for (i = 0; i < MAX_OPERANDS; ++i)
12702             {
12703               obufp = op_out[i];
12704               op_ad = MAX_OPERANDS - 1 - i;
12705               if (dp->op[i].rtn)
12706                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12707               /* For EVEX instruction after the last operand masking
12708                  should be printed.  */
12709               if (i == 0 && vex.evex)
12710                 {
12711                   /* Don't print {%k0}.  */
12712                   if (vex.mask_register_specifier)
12713                     {
12714                       oappend ("{");
12715                       oappend (names_mask[vex.mask_register_specifier]);
12716                       oappend ("}");
12717                     }
12718                   if (vex.zeroing)
12719                     oappend ("{z}");
12720                 }
12721             }
12722         }
12723     }
12724
12725   /* Clear instruction information.  */
12726   if (the_info)
12727     {
12728       the_info->insn_info_valid = 0;
12729       the_info->branch_delay_insns = 0;
12730       the_info->data_size = 0;
12731       the_info->insn_type = dis_noninsn;
12732       the_info->target = 0;
12733       the_info->target2 = 0;
12734     }
12735
12736   /* Reset jump operation indicator.  */
12737   op_is_jump = FALSE;
12738
12739   {
12740     int jump_detection = 0;
12741
12742     /* Extract flags.  */
12743     for (i = 0; i < MAX_OPERANDS; ++i)
12744       {
12745         if ((dp->op[i].rtn == OP_J)
12746             || (dp->op[i].rtn == OP_indirE))
12747           jump_detection |= 1;
12748         else if ((dp->op[i].rtn == BND_Fixup)
12749                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12750           jump_detection |= 2;
12751         else if ((dp->op[i].bytemode == cond_jump_mode)
12752                  || (dp->op[i].bytemode == loop_jcxz_mode))
12753           jump_detection |= 4;
12754       }
12755
12756     /* Determine if this is a jump or branch.  */
12757     if ((jump_detection & 0x3) == 0x3)
12758       {
12759         op_is_jump = TRUE;
12760         if (jump_detection & 0x4)
12761           the_info->insn_type = dis_condbranch;
12762         else
12763           the_info->insn_type =
12764             (dp->name && !strncmp(dp->name, "call", 4))
12765             ? dis_jsr : dis_branch;
12766       }
12767   }
12768
12769   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12770      are all 0s in inverted form.  */
12771   if (need_vex && vex.register_specifier != 0)
12772     {
12773       (*info->fprintf_func) (info->stream, "(bad)");
12774       return end_codep - priv.the_buffer;
12775     }
12776
12777   /* Check if the REX prefix is used.  */
12778   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12779     all_prefixes[last_rex_prefix] = 0;
12780
12781   /* Check if the SEG prefix is used.  */
12782   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12783                    | PREFIX_FS | PREFIX_GS)) != 0
12784       && (used_prefixes & active_seg_prefix) != 0)
12785     all_prefixes[last_seg_prefix] = 0;
12786
12787   /* Check if the ADDR prefix is used.  */
12788   if ((prefixes & PREFIX_ADDR) != 0
12789       && (used_prefixes & PREFIX_ADDR) != 0)
12790     all_prefixes[last_addr_prefix] = 0;
12791
12792   /* Check if the DATA prefix is used.  */
12793   if ((prefixes & PREFIX_DATA) != 0
12794       && (used_prefixes & PREFIX_DATA) != 0
12795       && !need_vex)
12796     all_prefixes[last_data_prefix] = 0;
12797
12798   /* Print the extra prefixes.  */
12799   prefix_length = 0;
12800   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12801     if (all_prefixes[i])
12802       {
12803         const char *name;
12804         name = prefix_name (all_prefixes[i], orig_sizeflag);
12805         if (name == NULL)
12806           abort ();
12807         prefix_length += strlen (name) + 1;
12808         (*info->fprintf_func) (info->stream, "%s ", name);
12809       }
12810
12811   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12812      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12813      used by putop and MMX/SSE operand and may be overriden by the
12814      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12815      separately.  */
12816   if (dp->prefix_requirement == PREFIX_OPCODE
12817       && (((need_vex
12818             ? vex.prefix == REPE_PREFIX_OPCODE
12819               || vex.prefix == REPNE_PREFIX_OPCODE
12820             : (prefixes
12821                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12822            && (used_prefixes
12823                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12824           || (((need_vex
12825                 ? vex.prefix == DATA_PREFIX_OPCODE
12826                 : ((prefixes
12827                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12828                    == PREFIX_DATA))
12829                && (used_prefixes & PREFIX_DATA) == 0))
12830           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12831     {
12832       (*info->fprintf_func) (info->stream, "(bad)");
12833       return end_codep - priv.the_buffer;
12834     }
12835
12836   /* Check maximum code length.  */
12837   if ((codep - start_codep) > MAX_CODE_LENGTH)
12838     {
12839       (*info->fprintf_func) (info->stream, "(bad)");
12840       return MAX_CODE_LENGTH;
12841     }
12842
12843   obufp = mnemonicendp;
12844   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12845     oappend (" ");
12846   oappend (" ");
12847   (*info->fprintf_func) (info->stream, "%s", obuf);
12848
12849   /* The enter and bound instructions are printed with operands in the same
12850      order as the intel book; everything else is printed in reverse order.  */
12851   if (intel_syntax || two_source_ops)
12852     {
12853       bfd_vma riprel;
12854
12855       for (i = 0; i < MAX_OPERANDS; ++i)
12856         op_txt[i] = op_out[i];
12857
12858       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12859           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12860         {
12861           op_txt[2] = op_out[3];
12862           op_txt[3] = op_out[2];
12863         }
12864
12865       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12866         {
12867           op_ad = op_index[i];
12868           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12869           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12870           riprel = op_riprel[i];
12871           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12872           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12873         }
12874     }
12875   else
12876     {
12877       for (i = 0; i < MAX_OPERANDS; ++i)
12878         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12879     }
12880
12881   needcomma = 0;
12882   for (i = 0; i < MAX_OPERANDS; ++i)
12883     if (*op_txt[i])
12884       {
12885         if (needcomma)
12886           (*info->fprintf_func) (info->stream, ",");
12887         if (op_index[i] != -1 && !op_riprel[i])
12888           {
12889             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12890
12891             if (the_info && op_is_jump)
12892               {
12893                 the_info->insn_info_valid = 1;
12894                 the_info->branch_delay_insns = 0;
12895                 the_info->data_size = 0;
12896                 the_info->target = target;
12897                 the_info->target2 = 0;
12898               }
12899             (*info->print_address_func) (target, info);
12900           }
12901         else
12902           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12903         needcomma = 1;
12904       }
12905
12906   for (i = 0; i < MAX_OPERANDS; i++)
12907     if (op_index[i] != -1 && op_riprel[i])
12908       {
12909         (*info->fprintf_func) (info->stream, "        # ");
12910         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12911                                                 + op_address[op_index[i]]), info);
12912         break;
12913       }
12914   return codep - priv.the_buffer;
12915 }
12916
12917 static const char *float_mem[] = {
12918   /* d8 */
12919   "fadd{s|}",
12920   "fmul{s|}",
12921   "fcom{s|}",
12922   "fcomp{s|}",
12923   "fsub{s|}",
12924   "fsubr{s|}",
12925   "fdiv{s|}",
12926   "fdivr{s|}",
12927   /* d9 */
12928   "fld{s|}",
12929   "(bad)",
12930   "fst{s|}",
12931   "fstp{s|}",
12932   "fldenv{C|C}",
12933   "fldcw",
12934   "fNstenv{C|C}",
12935   "fNstcw",
12936   /* da */
12937   "fiadd{l|}",
12938   "fimul{l|}",
12939   "ficom{l|}",
12940   "ficomp{l|}",
12941   "fisub{l|}",
12942   "fisubr{l|}",
12943   "fidiv{l|}",
12944   "fidivr{l|}",
12945   /* db */
12946   "fild{l|}",
12947   "fisttp{l|}",
12948   "fist{l|}",
12949   "fistp{l|}",
12950   "(bad)",
12951   "fld{t|}",
12952   "(bad)",
12953   "fstp{t|}",
12954   /* dc */
12955   "fadd{l|}",
12956   "fmul{l|}",
12957   "fcom{l|}",
12958   "fcomp{l|}",
12959   "fsub{l|}",
12960   "fsubr{l|}",
12961   "fdiv{l|}",
12962   "fdivr{l|}",
12963   /* dd */
12964   "fld{l|}",
12965   "fisttp{ll|}",
12966   "fst{l||}",
12967   "fstp{l|}",
12968   "frstor{C|C}",
12969   "(bad)",
12970   "fNsave{C|C}",
12971   "fNstsw",
12972   /* de */
12973   "fiadd{s|}",
12974   "fimul{s|}",
12975   "ficom{s|}",
12976   "ficomp{s|}",
12977   "fisub{s|}",
12978   "fisubr{s|}",
12979   "fidiv{s|}",
12980   "fidivr{s|}",
12981   /* df */
12982   "fild{s|}",
12983   "fisttp{s|}",
12984   "fist{s|}",
12985   "fistp{s|}",
12986   "fbld",
12987   "fild{ll|}",
12988   "fbstp",
12989   "fistp{ll|}",
12990 };
12991
12992 static const unsigned char float_mem_mode[] = {
12993   /* d8 */
12994   d_mode,
12995   d_mode,
12996   d_mode,
12997   d_mode,
12998   d_mode,
12999   d_mode,
13000   d_mode,
13001   d_mode,
13002   /* d9 */
13003   d_mode,
13004   0,
13005   d_mode,
13006   d_mode,
13007   0,
13008   w_mode,
13009   0,
13010   w_mode,
13011   /* da */
13012   d_mode,
13013   d_mode,
13014   d_mode,
13015   d_mode,
13016   d_mode,
13017   d_mode,
13018   d_mode,
13019   d_mode,
13020   /* db */
13021   d_mode,
13022   d_mode,
13023   d_mode,
13024   d_mode,
13025   0,
13026   t_mode,
13027   0,
13028   t_mode,
13029   /* dc */
13030   q_mode,
13031   q_mode,
13032   q_mode,
13033   q_mode,
13034   q_mode,
13035   q_mode,
13036   q_mode,
13037   q_mode,
13038   /* dd */
13039   q_mode,
13040   q_mode,
13041   q_mode,
13042   q_mode,
13043   0,
13044   0,
13045   0,
13046   w_mode,
13047   /* de */
13048   w_mode,
13049   w_mode,
13050   w_mode,
13051   w_mode,
13052   w_mode,
13053   w_mode,
13054   w_mode,
13055   w_mode,
13056   /* df */
13057   w_mode,
13058   w_mode,
13059   w_mode,
13060   w_mode,
13061   t_mode,
13062   q_mode,
13063   t_mode,
13064   q_mode
13065 };
13066
13067 #define ST { OP_ST, 0 }
13068 #define STi { OP_STi, 0 }
13069
13070 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13071 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13072 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13073 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13074 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13075 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13076 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13077 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13078 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13079
13080 static const struct dis386 float_reg[][8] = {
13081   /* d8 */
13082   {
13083     { "fadd",   { ST, STi }, 0 },
13084     { "fmul",   { ST, STi }, 0 },
13085     { "fcom",   { STi }, 0 },
13086     { "fcomp",  { STi }, 0 },
13087     { "fsub",   { ST, STi }, 0 },
13088     { "fsubr",  { ST, STi }, 0 },
13089     { "fdiv",   { ST, STi }, 0 },
13090     { "fdivr",  { ST, STi }, 0 },
13091   },
13092   /* d9 */
13093   {
13094     { "fld",    { STi }, 0 },
13095     { "fxch",   { STi }, 0 },
13096     { FGRPd9_2 },
13097     { Bad_Opcode },
13098     { FGRPd9_4 },
13099     { FGRPd9_5 },
13100     { FGRPd9_6 },
13101     { FGRPd9_7 },
13102   },
13103   /* da */
13104   {
13105     { "fcmovb", { ST, STi }, 0 },
13106     { "fcmove", { ST, STi }, 0 },
13107     { "fcmovbe",{ ST, STi }, 0 },
13108     { "fcmovu", { ST, STi }, 0 },
13109     { Bad_Opcode },
13110     { FGRPda_5 },
13111     { Bad_Opcode },
13112     { Bad_Opcode },
13113   },
13114   /* db */
13115   {
13116     { "fcmovnb",{ ST, STi }, 0 },
13117     { "fcmovne",{ ST, STi }, 0 },
13118     { "fcmovnbe",{ ST, STi }, 0 },
13119     { "fcmovnu",{ ST, STi }, 0 },
13120     { FGRPdb_4 },
13121     { "fucomi", { ST, STi }, 0 },
13122     { "fcomi",  { ST, STi }, 0 },
13123     { Bad_Opcode },
13124   },
13125   /* dc */
13126   {
13127     { "fadd",   { STi, ST }, 0 },
13128     { "fmul",   { STi, ST }, 0 },
13129     { Bad_Opcode },
13130     { Bad_Opcode },
13131     { "fsub{!M|r}",     { STi, ST }, 0 },
13132     { "fsub{M|}",       { STi, ST }, 0 },
13133     { "fdiv{!M|r}",     { STi, ST }, 0 },
13134     { "fdiv{M|}",       { STi, ST }, 0 },
13135   },
13136   /* dd */
13137   {
13138     { "ffree",  { STi }, 0 },
13139     { Bad_Opcode },
13140     { "fst",    { STi }, 0 },
13141     { "fstp",   { STi }, 0 },
13142     { "fucom",  { STi }, 0 },
13143     { "fucomp", { STi }, 0 },
13144     { Bad_Opcode },
13145     { Bad_Opcode },
13146   },
13147   /* de */
13148   {
13149     { "faddp",  { STi, ST }, 0 },
13150     { "fmulp",  { STi, ST }, 0 },
13151     { Bad_Opcode },
13152     { FGRPde_3 },
13153     { "fsub{!M|r}p",    { STi, ST }, 0 },
13154     { "fsub{M|}p",      { STi, ST }, 0 },
13155     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13156     { "fdiv{M|}p",      { STi, ST }, 0 },
13157   },
13158   /* df */
13159   {
13160     { "ffreep", { STi }, 0 },
13161     { Bad_Opcode },
13162     { Bad_Opcode },
13163     { Bad_Opcode },
13164     { FGRPdf_4 },
13165     { "fucomip", { ST, STi }, 0 },
13166     { "fcomip", { ST, STi }, 0 },
13167     { Bad_Opcode },
13168   },
13169 };
13170
13171 static char *fgrps[][8] = {
13172   /* Bad opcode 0 */
13173   {
13174     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13175   },
13176
13177   /* d9_2  1 */
13178   {
13179     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13180   },
13181
13182   /* d9_4  2 */
13183   {
13184     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13185   },
13186
13187   /* d9_5  3 */
13188   {
13189     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13190   },
13191
13192   /* d9_6  4 */
13193   {
13194     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13195   },
13196
13197   /* d9_7  5 */
13198   {
13199     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13200   },
13201
13202   /* da_5  6 */
13203   {
13204     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13205   },
13206
13207   /* db_4  7 */
13208   {
13209     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13210     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13211   },
13212
13213   /* de_3  8 */
13214   {
13215     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13216   },
13217
13218   /* df_4  9 */
13219   {
13220     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13221   },
13222 };
13223
13224 static void
13225 swap_operand (void)
13226 {
13227   mnemonicendp[0] = '.';
13228   mnemonicendp[1] = 's';
13229   mnemonicendp += 2;
13230 }
13231
13232 static void
13233 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13234                int sizeflag ATTRIBUTE_UNUSED)
13235 {
13236   /* Skip mod/rm byte.  */
13237   MODRM_CHECK;
13238   codep++;
13239 }
13240
13241 static void
13242 dofloat (int sizeflag)
13243 {
13244   const struct dis386 *dp;
13245   unsigned char floatop;
13246
13247   floatop = codep[-1];
13248
13249   if (modrm.mod != 3)
13250     {
13251       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13252
13253       putop (float_mem[fp_indx], sizeflag);
13254       obufp = op_out[0];
13255       op_ad = 2;
13256       OP_E (float_mem_mode[fp_indx], sizeflag);
13257       return;
13258     }
13259   /* Skip mod/rm byte.  */
13260   MODRM_CHECK;
13261   codep++;
13262
13263   dp = &float_reg[floatop - 0xd8][modrm.reg];
13264   if (dp->name == NULL)
13265     {
13266       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13267
13268       /* Instruction fnstsw is only one with strange arg.  */
13269       if (floatop == 0xdf && codep[-1] == 0xe0)
13270         strcpy (op_out[0], names16[0]);
13271     }
13272   else
13273     {
13274       putop (dp->name, sizeflag);
13275
13276       obufp = op_out[0];
13277       op_ad = 2;
13278       if (dp->op[0].rtn)
13279         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13280
13281       obufp = op_out[1];
13282       op_ad = 1;
13283       if (dp->op[1].rtn)
13284         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13285     }
13286 }
13287
13288 /* Like oappend (below), but S is a string starting with '%'.
13289    In Intel syntax, the '%' is elided.  */
13290 static void
13291 oappend_maybe_intel (const char *s)
13292 {
13293   oappend (s + intel_syntax);
13294 }
13295
13296 static void
13297 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13298 {
13299   oappend_maybe_intel ("%st");
13300 }
13301
13302 static void
13303 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13304 {
13305   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13306   oappend_maybe_intel (scratchbuf);
13307 }
13308
13309 /* Capital letters in template are macros.  */
13310 static int
13311 putop (const char *in_template, int sizeflag)
13312 {
13313   const char *p;
13314   int alt = 0;
13315   int cond = 1;
13316   unsigned int l = 0, len = 0;
13317   char last[4];
13318
13319   for (p = in_template; *p; p++)
13320     {
13321       if (len > l)
13322         {
13323           if (l >= sizeof (last) || !ISUPPER (*p))
13324             abort ();
13325           last[l++] = *p;
13326           continue;
13327         }
13328       switch (*p)
13329         {
13330         default:
13331           *obufp++ = *p;
13332           break;
13333         case '%':
13334           len++;
13335           break;
13336         case '!':
13337           cond = 0;
13338           break;
13339         case '{':
13340           if (intel_syntax)
13341             {
13342               while (*++p != '|')
13343                 if (*p == '}' || *p == '\0')
13344                   abort ();
13345               alt = 1;
13346             }
13347           break;
13348         case '|':
13349           while (*++p != '}')
13350             {
13351               if (*p == '\0')
13352                 abort ();
13353             }
13354           break;
13355         case '}':
13356           alt = 0;
13357           break;
13358         case 'A':
13359           if (intel_syntax)
13360             break;
13361           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13362             *obufp++ = 'b';
13363           break;
13364         case 'B':
13365           if (l == 0)
13366             {
13367             case_B:
13368               if (intel_syntax)
13369                 break;
13370               if (sizeflag & SUFFIX_ALWAYS)
13371                 *obufp++ = 'b';
13372             }
13373           else if (l == 1 && last[0] == 'L')
13374             {
13375               if (address_mode == mode_64bit
13376                   && !(prefixes & PREFIX_ADDR))
13377                 {
13378                   *obufp++ = 'a';
13379                   *obufp++ = 'b';
13380                   *obufp++ = 's';
13381                 }
13382
13383               goto case_B;
13384             }
13385           else
13386             abort ();
13387           break;
13388         case 'C':
13389           if (intel_syntax && !alt)
13390             break;
13391           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13392             {
13393               if (sizeflag & DFLAG)
13394                 *obufp++ = intel_syntax ? 'd' : 'l';
13395               else
13396                 *obufp++ = intel_syntax ? 'w' : 's';
13397               used_prefixes |= (prefixes & PREFIX_DATA);
13398             }
13399           break;
13400         case 'D':
13401           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13402             break;
13403           USED_REX (REX_W);
13404           if (modrm.mod == 3)
13405             {
13406               if (rex & REX_W)
13407                 *obufp++ = 'q';
13408               else
13409                 {
13410                   if (sizeflag & DFLAG)
13411                     *obufp++ = intel_syntax ? 'd' : 'l';
13412                   else
13413                     *obufp++ = 'w';
13414                   used_prefixes |= (prefixes & PREFIX_DATA);
13415                 }
13416             }
13417           else
13418             *obufp++ = 'w';
13419           break;
13420         case 'E':               /* For jcxz/jecxz */
13421           if (address_mode == mode_64bit)
13422             {
13423               if (sizeflag & AFLAG)
13424                 *obufp++ = 'r';
13425               else
13426                 *obufp++ = 'e';
13427             }
13428           else
13429             if (sizeflag & AFLAG)
13430               *obufp++ = 'e';
13431           used_prefixes |= (prefixes & PREFIX_ADDR);
13432           break;
13433         case 'F':
13434           if (intel_syntax)
13435             break;
13436           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13437             {
13438               if (sizeflag & AFLAG)
13439                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13440               else
13441                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13442               used_prefixes |= (prefixes & PREFIX_ADDR);
13443             }
13444           break;
13445         case 'G':
13446           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13447             break;
13448           if ((rex & REX_W) || (sizeflag & DFLAG))
13449             *obufp++ = 'l';
13450           else
13451             *obufp++ = 'w';
13452           if (!(rex & REX_W))
13453             used_prefixes |= (prefixes & PREFIX_DATA);
13454           break;
13455         case 'H':
13456           if (intel_syntax)
13457             break;
13458           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13459               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13460             {
13461               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13462               *obufp++ = ',';
13463               *obufp++ = 'p';
13464               if (prefixes & PREFIX_DS)
13465                 *obufp++ = 't';
13466               else
13467                 *obufp++ = 'n';
13468             }
13469           break;
13470         case 'K':
13471           USED_REX (REX_W);
13472           if (rex & REX_W)
13473             *obufp++ = 'q';
13474           else
13475             *obufp++ = 'd';
13476           break;
13477         case 'Z':
13478           if (l != 0)
13479             {
13480               if (l != 1 || last[0] != 'X')
13481                 abort ();
13482               if (!need_vex || !vex.evex)
13483                 abort ();
13484               if (intel_syntax
13485                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13486                 break;
13487               switch (vex.length)
13488                 {
13489                 case 128:
13490                   *obufp++ = 'x';
13491                   break;
13492                 case 256:
13493                   *obufp++ = 'y';
13494                   break;
13495                 case 512:
13496                   *obufp++ = 'z';
13497                   break;
13498                 default:
13499                   abort ();
13500                 }
13501               break;
13502             }
13503           if (intel_syntax)
13504             break;
13505           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13506             {
13507               *obufp++ = 'q';
13508               break;
13509             }
13510           /* Fall through.  */
13511           goto case_L;
13512         case 'L':
13513           if (l != 0)
13514             abort ();
13515         case_L:
13516           if (intel_syntax)
13517             break;
13518           if (sizeflag & SUFFIX_ALWAYS)
13519             *obufp++ = 'l';
13520           break;
13521         case 'M':
13522           if (intel_mnemonic != cond)
13523             *obufp++ = 'r';
13524           break;
13525         case 'N':
13526           if ((prefixes & PREFIX_FWAIT) == 0)
13527             *obufp++ = 'n';
13528           else
13529             used_prefixes |= PREFIX_FWAIT;
13530           break;
13531         case 'O':
13532           USED_REX (REX_W);
13533           if (rex & REX_W)
13534             *obufp++ = 'o';
13535           else if (intel_syntax && (sizeflag & DFLAG))
13536             *obufp++ = 'q';
13537           else
13538             *obufp++ = 'd';
13539           if (!(rex & REX_W))
13540             used_prefixes |= (prefixes & PREFIX_DATA);
13541           break;
13542         case '&':
13543           if (!intel_syntax
13544               && address_mode == mode_64bit
13545               && isa64 == intel64)
13546             {
13547               *obufp++ = 'q';
13548               break;
13549             }
13550           /* Fall through.  */
13551         case 'T':
13552           if (!intel_syntax
13553               && address_mode == mode_64bit
13554               && ((sizeflag & DFLAG) || (rex & REX_W)))
13555             {
13556               *obufp++ = 'q';
13557               break;
13558             }
13559           /* Fall through.  */
13560           goto case_P;
13561         case 'P':
13562           if (l == 0)
13563             {
13564             case_P:
13565               if (intel_syntax)
13566                 {
13567                   if ((rex & REX_W) == 0
13568                       && (prefixes & PREFIX_DATA))
13569                     {
13570                       if ((sizeflag & DFLAG) == 0)
13571                         *obufp++ = 'w';
13572                       used_prefixes |= (prefixes & PREFIX_DATA);
13573                     }
13574                   break;
13575                 }
13576               if ((prefixes & PREFIX_DATA)
13577                   || (rex & REX_W)
13578                   || (sizeflag & SUFFIX_ALWAYS))
13579                 {
13580                   USED_REX (REX_W);
13581                   if (rex & REX_W)
13582                     *obufp++ = 'q';
13583                   else
13584                     {
13585                       if (sizeflag & DFLAG)
13586                         *obufp++ = 'l';
13587                       else
13588                         *obufp++ = 'w';
13589                       used_prefixes |= (prefixes & PREFIX_DATA);
13590                     }
13591                 }
13592             }
13593           else if (l == 1 && last[0] == 'L')
13594             {
13595               if ((prefixes & PREFIX_DATA)
13596                   || (rex & REX_W)
13597                   || (sizeflag & SUFFIX_ALWAYS))
13598                 {
13599                   USED_REX (REX_W);
13600                   if (rex & REX_W)
13601                     *obufp++ = 'q';
13602                   else
13603                     {
13604                       if (sizeflag & DFLAG)
13605                         *obufp++ = intel_syntax ? 'd' : 'l';
13606                       else
13607                         *obufp++ = 'w';
13608                       used_prefixes |= (prefixes & PREFIX_DATA);
13609                     }
13610                 }
13611             }
13612           else
13613             abort ();
13614           break;
13615         case 'U':
13616           if (intel_syntax)
13617             break;
13618           if (address_mode == mode_64bit
13619               && ((sizeflag & DFLAG) || (rex & REX_W)))
13620             {
13621               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13622                 *obufp++ = 'q';
13623               break;
13624             }
13625           /* Fall through.  */
13626           goto case_Q;
13627         case 'Q':
13628           if (l == 0)
13629             {
13630             case_Q:
13631               if (intel_syntax && !alt)
13632                 break;
13633               USED_REX (REX_W);
13634               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13635                 {
13636                   if (rex & REX_W)
13637                     *obufp++ = 'q';
13638                   else
13639                     {
13640                       if (sizeflag & DFLAG)
13641                         *obufp++ = intel_syntax ? 'd' : 'l';
13642                       else
13643                         *obufp++ = 'w';
13644                       used_prefixes |= (prefixes & PREFIX_DATA);
13645                     }
13646                 }
13647             }
13648           else if (l == 1 && last[0] == 'L')
13649             {
13650               if ((intel_syntax && need_modrm)
13651                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13652                 break;
13653               if ((rex & REX_W))
13654                 {
13655                   USED_REX (REX_W);
13656                   *obufp++ = 'q';
13657                 }
13658               else if((address_mode == mode_64bit && need_modrm)
13659                       || (sizeflag & SUFFIX_ALWAYS))
13660                 *obufp++ = intel_syntax? 'd' : 'l';
13661             }
13662           else
13663             abort ();
13664           break;
13665         case 'R':
13666           USED_REX (REX_W);
13667           if (rex & REX_W)
13668             *obufp++ = 'q';
13669           else if (sizeflag & DFLAG)
13670             {
13671               if (intel_syntax)
13672                   *obufp++ = 'd';
13673               else
13674                   *obufp++ = 'l';
13675             }
13676           else
13677             *obufp++ = 'w';
13678           if (intel_syntax && !p[1]
13679               && ((rex & REX_W) || (sizeflag & DFLAG)))
13680             *obufp++ = 'e';
13681           if (!(rex & REX_W))
13682             used_prefixes |= (prefixes & PREFIX_DATA);
13683           break;
13684         case 'V':
13685           if (l == 0)
13686             {
13687               if (intel_syntax)
13688                 break;
13689               if (address_mode == mode_64bit
13690                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13691                 {
13692                   if (sizeflag & SUFFIX_ALWAYS)
13693                     *obufp++ = 'q';
13694                   break;
13695                 }
13696             }
13697           else if (l == 1 && last[0] == 'L')
13698             {
13699               if (rex & REX_W)
13700                 {
13701                   *obufp++ = 'a';
13702                   *obufp++ = 'b';
13703                   *obufp++ = 's';
13704                 }
13705             }
13706           else
13707             abort ();
13708           /* Fall through.  */
13709           goto case_S;
13710         case 'S':
13711           if (l == 0)
13712             {
13713             case_S:
13714               if (intel_syntax)
13715                 break;
13716               if (sizeflag & SUFFIX_ALWAYS)
13717                 {
13718                   if (rex & REX_W)
13719                     *obufp++ = 'q';
13720                   else
13721                     {
13722                       if (sizeflag & DFLAG)
13723                         *obufp++ = 'l';
13724                       else
13725                         *obufp++ = 'w';
13726                       used_prefixes |= (prefixes & PREFIX_DATA);
13727                     }
13728                 }
13729             }
13730           else if (l == 1 && last[0] == 'L')
13731             {
13732               if (address_mode == mode_64bit
13733                   && !(prefixes & PREFIX_ADDR))
13734                 {
13735                   *obufp++ = 'a';
13736                   *obufp++ = 'b';
13737                   *obufp++ = 's';
13738                 }
13739
13740               goto case_S;
13741             }
13742           else
13743             abort ();
13744           break;
13745         case 'X':
13746           if (l != 0)
13747             abort ();
13748           if (need_vex
13749               ? vex.prefix == DATA_PREFIX_OPCODE
13750               : prefixes & PREFIX_DATA)
13751             {
13752               *obufp++ = 'd';
13753               used_prefixes |= PREFIX_DATA;
13754             }
13755           else
13756             *obufp++ = 's';
13757           break;
13758         case 'Y':
13759           if (l == 1 && last[0] == 'X')
13760             {
13761               if (!need_vex)
13762                 abort ();
13763               if (intel_syntax
13764                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13765                 break;
13766               switch (vex.length)
13767                 {
13768                 case 128:
13769                   *obufp++ = 'x';
13770                   break;
13771                 case 256:
13772                   *obufp++ = 'y';
13773                   break;
13774                 case 512:
13775                   if (!vex.evex)
13776                 default:
13777                     abort ();
13778                 }
13779             }
13780           else
13781             abort ();
13782           break;
13783         case 'W':
13784           if (l == 0)
13785             {
13786               /* operand size flag for cwtl, cbtw */
13787               USED_REX (REX_W);
13788               if (rex & REX_W)
13789                 {
13790                   if (intel_syntax)
13791                     *obufp++ = 'd';
13792                   else
13793                     *obufp++ = 'l';
13794                 }
13795               else if (sizeflag & DFLAG)
13796                 *obufp++ = 'w';
13797               else
13798                 *obufp++ = 'b';
13799               if (!(rex & REX_W))
13800                 used_prefixes |= (prefixes & PREFIX_DATA);
13801             }
13802           else if (l == 1)
13803             {
13804               if (!need_vex)
13805                 abort ();
13806               if (last[0] == 'X')
13807                 *obufp++ = vex.w ? 'd': 's';
13808               else if (last[0] == 'L')
13809                 *obufp++ = vex.w ? 'q': 'd';
13810               else if (last[0] == 'B')
13811                 *obufp++ = vex.w ? 'w': 'b';
13812               else
13813                 abort ();
13814             }
13815           else
13816             abort ();
13817           break;
13818         case '^':
13819           if (intel_syntax)
13820             break;
13821           if (isa64 == intel64 && (rex & REX_W))
13822             {
13823               USED_REX (REX_W);
13824               *obufp++ = 'q';
13825               break;
13826             }
13827           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13828             {
13829               if (sizeflag & DFLAG)
13830                 *obufp++ = 'l';
13831               else
13832                 *obufp++ = 'w';
13833               used_prefixes |= (prefixes & PREFIX_DATA);
13834             }
13835           break;
13836         case '@':
13837           if (intel_syntax)
13838             break;
13839           if (address_mode == mode_64bit
13840               && (isa64 == intel64
13841                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13842               *obufp++ = 'q';
13843           else if ((prefixes & PREFIX_DATA))
13844             {
13845               if (!(sizeflag & DFLAG))
13846                 *obufp++ = 'w';
13847               used_prefixes |= (prefixes & PREFIX_DATA);
13848             }
13849           break;
13850         }
13851
13852       if (len == l)
13853         len = l = 0;
13854     }
13855   *obufp = 0;
13856   mnemonicendp = obufp;
13857   return 0;
13858 }
13859
13860 static void
13861 oappend (const char *s)
13862 {
13863   obufp = stpcpy (obufp, s);
13864 }
13865
13866 static void
13867 append_seg (void)
13868 {
13869   /* Only print the active segment register.  */
13870   if (!active_seg_prefix)
13871     return;
13872
13873   used_prefixes |= active_seg_prefix;
13874   switch (active_seg_prefix)
13875     {
13876     case PREFIX_CS:
13877       oappend_maybe_intel ("%cs:");
13878       break;
13879     case PREFIX_DS:
13880       oappend_maybe_intel ("%ds:");
13881       break;
13882     case PREFIX_SS:
13883       oappend_maybe_intel ("%ss:");
13884       break;
13885     case PREFIX_ES:
13886       oappend_maybe_intel ("%es:");
13887       break;
13888     case PREFIX_FS:
13889       oappend_maybe_intel ("%fs:");
13890       break;
13891     case PREFIX_GS:
13892       oappend_maybe_intel ("%gs:");
13893       break;
13894     default:
13895       break;
13896     }
13897 }
13898
13899 static void
13900 OP_indirE (int bytemode, int sizeflag)
13901 {
13902   if (!intel_syntax)
13903     oappend ("*");
13904   OP_E (bytemode, sizeflag);
13905 }
13906
13907 static void
13908 print_operand_value (char *buf, int hex, bfd_vma disp)
13909 {
13910   if (address_mode == mode_64bit)
13911     {
13912       if (hex)
13913         {
13914           char tmp[30];
13915           int i;
13916           buf[0] = '0';
13917           buf[1] = 'x';
13918           sprintf_vma (tmp, disp);
13919           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13920           strcpy (buf + 2, tmp + i);
13921         }
13922       else
13923         {
13924           bfd_signed_vma v = disp;
13925           char tmp[30];
13926           int i;
13927           if (v < 0)
13928             {
13929               *(buf++) = '-';
13930               v = -disp;
13931               /* Check for possible overflow on 0x8000000000000000.  */
13932               if (v < 0)
13933                 {
13934                   strcpy (buf, "9223372036854775808");
13935                   return;
13936                 }
13937             }
13938           if (!v)
13939             {
13940               strcpy (buf, "0");
13941               return;
13942             }
13943
13944           i = 0;
13945           tmp[29] = 0;
13946           while (v)
13947             {
13948               tmp[28 - i] = (v % 10) + '0';
13949               v /= 10;
13950               i++;
13951             }
13952           strcpy (buf, tmp + 29 - i);
13953         }
13954     }
13955   else
13956     {
13957       if (hex)
13958         sprintf (buf, "0x%x", (unsigned int) disp);
13959       else
13960         sprintf (buf, "%d", (int) disp);
13961     }
13962 }
13963
13964 /* Put DISP in BUF as signed hex number.  */
13965
13966 static void
13967 print_displacement (char *buf, bfd_vma disp)
13968 {
13969   bfd_signed_vma val = disp;
13970   char tmp[30];
13971   int i, j = 0;
13972
13973   if (val < 0)
13974     {
13975       buf[j++] = '-';
13976       val = -disp;
13977
13978       /* Check for possible overflow.  */
13979       if (val < 0)
13980         {
13981           switch (address_mode)
13982             {
13983             case mode_64bit:
13984               strcpy (buf + j, "0x8000000000000000");
13985               break;
13986             case mode_32bit:
13987               strcpy (buf + j, "0x80000000");
13988               break;
13989             case mode_16bit:
13990               strcpy (buf + j, "0x8000");
13991               break;
13992             }
13993           return;
13994         }
13995     }
13996
13997   buf[j++] = '0';
13998   buf[j++] = 'x';
13999
14000   sprintf_vma (tmp, (bfd_vma) val);
14001   for (i = 0; tmp[i] == '0'; i++)
14002     continue;
14003   if (tmp[i] == '\0')
14004     i--;
14005   strcpy (buf + j, tmp + i);
14006 }
14007
14008 static void
14009 intel_operand_size (int bytemode, int sizeflag)
14010 {
14011   if (vex.evex
14012       && vex.b
14013       && (bytemode == x_mode
14014           || bytemode == evex_half_bcst_xmmq_mode))
14015     {
14016       if (vex.w)
14017         oappend ("QWORD PTR ");
14018       else
14019         oappend ("DWORD PTR ");
14020       return;
14021     }
14022   switch (bytemode)
14023     {
14024     case b_mode:
14025     case b_swap_mode:
14026     case dqb_mode:
14027     case db_mode:
14028       oappend ("BYTE PTR ");
14029       break;
14030     case w_mode:
14031     case dw_mode:
14032     case dqw_mode:
14033       oappend ("WORD PTR ");
14034       break;
14035     case indir_v_mode:
14036       if (address_mode == mode_64bit && isa64 == intel64)
14037         {
14038           oappend ("QWORD PTR ");
14039           break;
14040         }
14041       /* Fall through.  */
14042     case stack_v_mode:
14043       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14044         {
14045           oappend ("QWORD PTR ");
14046           break;
14047         }
14048       /* Fall through.  */
14049     case v_mode:
14050     case v_swap_mode:
14051     case dq_mode:
14052       USED_REX (REX_W);
14053       if (rex & REX_W)
14054         oappend ("QWORD PTR ");
14055       else
14056         {
14057           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14058             oappend ("DWORD PTR ");
14059           else
14060             oappend ("WORD PTR ");
14061           used_prefixes |= (prefixes & PREFIX_DATA);
14062         }
14063       break;
14064     case z_mode:
14065       if ((rex & REX_W) || (sizeflag & DFLAG))
14066         *obufp++ = 'D';
14067       oappend ("WORD PTR ");
14068       if (!(rex & REX_W))
14069         used_prefixes |= (prefixes & PREFIX_DATA);
14070       break;
14071     case a_mode:
14072       if (sizeflag & DFLAG)
14073         oappend ("QWORD PTR ");
14074       else
14075         oappend ("DWORD PTR ");
14076       used_prefixes |= (prefixes & PREFIX_DATA);
14077       break;
14078     case movsxd_mode:
14079       if (!(sizeflag & DFLAG) && isa64 == intel64)
14080         oappend ("WORD PTR ");
14081       else
14082         oappend ("DWORD PTR ");
14083       used_prefixes |= (prefixes & PREFIX_DATA);
14084       break;
14085     case d_mode:
14086     case d_scalar_swap_mode:
14087     case d_swap_mode:
14088     case dqd_mode:
14089       oappend ("DWORD PTR ");
14090       break;
14091     case q_mode:
14092     case q_scalar_swap_mode:
14093     case q_swap_mode:
14094       oappend ("QWORD PTR ");
14095       break;
14096     case m_mode:
14097       if (address_mode == mode_64bit)
14098         oappend ("QWORD PTR ");
14099       else
14100         oappend ("DWORD PTR ");
14101       break;
14102     case f_mode:
14103       if (sizeflag & DFLAG)
14104         oappend ("FWORD PTR ");
14105       else
14106         oappend ("DWORD PTR ");
14107       used_prefixes |= (prefixes & PREFIX_DATA);
14108       break;
14109     case t_mode:
14110       oappend ("TBYTE PTR ");
14111       break;
14112     case x_mode:
14113     case x_swap_mode:
14114     case evex_x_gscat_mode:
14115     case evex_x_nobcst_mode:
14116     case b_scalar_mode:
14117     case w_scalar_mode:
14118       if (need_vex)
14119         {
14120           switch (vex.length)
14121             {
14122             case 128:
14123               oappend ("XMMWORD PTR ");
14124               break;
14125             case 256:
14126               oappend ("YMMWORD PTR ");
14127               break;
14128             case 512:
14129               oappend ("ZMMWORD PTR ");
14130               break;
14131             default:
14132               abort ();
14133             }
14134         }
14135       else
14136         oappend ("XMMWORD PTR ");
14137       break;
14138     case xmm_mode:
14139       oappend ("XMMWORD PTR ");
14140       break;
14141     case ymm_mode:
14142       oappend ("YMMWORD PTR ");
14143       break;
14144     case xmmq_mode:
14145     case evex_half_bcst_xmmq_mode:
14146       if (!need_vex)
14147         abort ();
14148
14149       switch (vex.length)
14150         {
14151         case 128:
14152           oappend ("QWORD PTR ");
14153           break;
14154         case 256:
14155           oappend ("XMMWORD PTR ");
14156           break;
14157         case 512:
14158           oappend ("YMMWORD PTR ");
14159           break;
14160         default:
14161           abort ();
14162         }
14163       break;
14164     case xmm_mb_mode:
14165       if (!need_vex)
14166         abort ();
14167
14168       switch (vex.length)
14169         {
14170         case 128:
14171         case 256:
14172         case 512:
14173           oappend ("BYTE PTR ");
14174           break;
14175         default:
14176           abort ();
14177         }
14178       break;
14179     case xmm_mw_mode:
14180       if (!need_vex)
14181         abort ();
14182
14183       switch (vex.length)
14184         {
14185         case 128:
14186         case 256:
14187         case 512:
14188           oappend ("WORD PTR ");
14189           break;
14190         default:
14191           abort ();
14192         }
14193       break;
14194     case xmm_md_mode:
14195       if (!need_vex)
14196         abort ();
14197
14198       switch (vex.length)
14199         {
14200         case 128:
14201         case 256:
14202         case 512:
14203           oappend ("DWORD PTR ");
14204           break;
14205         default:
14206           abort ();
14207         }
14208       break;
14209     case xmm_mq_mode:
14210       if (!need_vex)
14211         abort ();
14212
14213       switch (vex.length)
14214         {
14215         case 128:
14216         case 256:
14217         case 512:
14218           oappend ("QWORD PTR ");
14219           break;
14220         default:
14221           abort ();
14222         }
14223       break;
14224     case xmmdw_mode:
14225       if (!need_vex)
14226         abort ();
14227
14228       switch (vex.length)
14229         {
14230         case 128:
14231           oappend ("WORD PTR ");
14232           break;
14233         case 256:
14234           oappend ("DWORD PTR ");
14235           break;
14236         case 512:
14237           oappend ("QWORD PTR ");
14238           break;
14239         default:
14240           abort ();
14241         }
14242       break;
14243     case xmmqd_mode:
14244       if (!need_vex)
14245         abort ();
14246
14247       switch (vex.length)
14248         {
14249         case 128:
14250           oappend ("DWORD PTR ");
14251           break;
14252         case 256:
14253           oappend ("QWORD PTR ");
14254           break;
14255         case 512:
14256           oappend ("XMMWORD PTR ");
14257           break;
14258         default:
14259           abort ();
14260         }
14261       break;
14262     case ymmq_mode:
14263       if (!need_vex)
14264         abort ();
14265
14266       switch (vex.length)
14267         {
14268         case 128:
14269           oappend ("QWORD PTR ");
14270           break;
14271         case 256:
14272           oappend ("YMMWORD PTR ");
14273           break;
14274         case 512:
14275           oappend ("ZMMWORD PTR ");
14276           break;
14277         default:
14278           abort ();
14279         }
14280       break;
14281     case ymmxmm_mode:
14282       if (!need_vex)
14283         abort ();
14284
14285       switch (vex.length)
14286         {
14287         case 128:
14288         case 256:
14289           oappend ("XMMWORD PTR ");
14290           break;
14291         default:
14292           abort ();
14293         }
14294       break;
14295     case o_mode:
14296       oappend ("OWORD PTR ");
14297       break;
14298     case vex_scalar_w_dq_mode:
14299       if (!need_vex)
14300         abort ();
14301
14302       if (vex.w)
14303         oappend ("QWORD PTR ");
14304       else
14305         oappend ("DWORD PTR ");
14306       break;
14307     case vex_vsib_d_w_dq_mode:
14308     case vex_vsib_q_w_dq_mode:
14309       if (!need_vex)
14310         abort ();
14311
14312       if (!vex.evex)
14313         {
14314           if (vex.w)
14315             oappend ("QWORD PTR ");
14316           else
14317             oappend ("DWORD PTR ");
14318         }
14319       else
14320         {
14321           switch (vex.length)
14322             {
14323             case 128:
14324               oappend ("XMMWORD PTR ");
14325               break;
14326             case 256:
14327               oappend ("YMMWORD PTR ");
14328               break;
14329             case 512:
14330               oappend ("ZMMWORD PTR ");
14331               break;
14332             default:
14333               abort ();
14334             }
14335         }
14336       break;
14337     case vex_vsib_q_w_d_mode:
14338     case vex_vsib_d_w_d_mode:
14339       if (!need_vex || !vex.evex)
14340         abort ();
14341
14342       switch (vex.length)
14343         {
14344         case 128:
14345           oappend ("QWORD PTR ");
14346           break;
14347         case 256:
14348           oappend ("XMMWORD PTR ");
14349           break;
14350         case 512:
14351           oappend ("YMMWORD PTR ");
14352           break;
14353         default:
14354           abort ();
14355         }
14356
14357       break;
14358     case mask_bd_mode:
14359       if (!need_vex || vex.length != 128)
14360         abort ();
14361       if (vex.w)
14362         oappend ("DWORD PTR ");
14363       else
14364         oappend ("BYTE PTR ");
14365       break;
14366     case mask_mode:
14367       if (!need_vex)
14368         abort ();
14369       if (vex.w)
14370         oappend ("QWORD PTR ");
14371       else
14372         oappend ("WORD PTR ");
14373       break;
14374     case v_bnd_mode:
14375     case v_bndmk_mode:
14376     default:
14377       break;
14378     }
14379 }
14380
14381 static void
14382 OP_E_register (int bytemode, int sizeflag)
14383 {
14384   int reg = modrm.rm;
14385   const char **names;
14386
14387   USED_REX (REX_B);
14388   if ((rex & REX_B))
14389     reg += 8;
14390
14391   if ((sizeflag & SUFFIX_ALWAYS)
14392       && (bytemode == b_swap_mode
14393           || bytemode == bnd_swap_mode
14394           || bytemode == v_swap_mode))
14395     swap_operand ();
14396
14397   switch (bytemode)
14398     {
14399     case b_mode:
14400     case b_swap_mode:
14401       USED_REX (0);
14402       if (rex)
14403         names = names8rex;
14404       else
14405         names = names8;
14406       break;
14407     case w_mode:
14408       names = names16;
14409       break;
14410     case d_mode:
14411     case dw_mode:
14412     case db_mode:
14413       names = names32;
14414       break;
14415     case q_mode:
14416       names = names64;
14417       break;
14418     case m_mode:
14419     case v_bnd_mode:
14420       names = address_mode == mode_64bit ? names64 : names32;
14421       break;
14422     case bnd_mode:
14423     case bnd_swap_mode:
14424       if (reg > 0x3)
14425         {
14426           oappend ("(bad)");
14427           return;
14428         }
14429       names = names_bnd;
14430       break;
14431     case indir_v_mode:
14432       if (address_mode == mode_64bit && isa64 == intel64)
14433         {
14434           names = names64;
14435           break;
14436         }
14437       /* Fall through.  */
14438     case stack_v_mode:
14439       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14440         {
14441           names = names64;
14442           break;
14443         }
14444       bytemode = v_mode;
14445       /* Fall through.  */
14446     case v_mode:
14447     case v_swap_mode:
14448     case dq_mode:
14449     case dqb_mode:
14450     case dqd_mode:
14451     case dqw_mode:
14452       USED_REX (REX_W);
14453       if (rex & REX_W)
14454         names = names64;
14455       else
14456         {
14457           if ((sizeflag & DFLAG)
14458               || (bytemode != v_mode
14459                   && bytemode != v_swap_mode))
14460             names = names32;
14461           else
14462             names = names16;
14463           used_prefixes |= (prefixes & PREFIX_DATA);
14464         }
14465       break;
14466     case movsxd_mode:
14467       if (!(sizeflag & DFLAG) && isa64 == intel64)
14468         names = names16;
14469       else
14470         names = names32;
14471       used_prefixes |= (prefixes & PREFIX_DATA);
14472       break;
14473     case va_mode:
14474       names = (address_mode == mode_64bit
14475                ? names64 : names32);
14476       if (!(prefixes & PREFIX_ADDR))
14477         names = (address_mode == mode_16bit
14478                      ? names16 : names);
14479       else
14480         {
14481           /* Remove "addr16/addr32".  */
14482           all_prefixes[last_addr_prefix] = 0;
14483           names = (address_mode != mode_32bit
14484                        ? names32 : names16);
14485           used_prefixes |= PREFIX_ADDR;
14486         }
14487       break;
14488     case mask_bd_mode:
14489     case mask_mode:
14490       if (reg > 0x7)
14491         {
14492           oappend ("(bad)");
14493           return;
14494         }
14495       names = names_mask;
14496       break;
14497     case 0:
14498       return;
14499     default:
14500       oappend (INTERNAL_DISASSEMBLER_ERROR);
14501       return;
14502     }
14503   oappend (names[reg]);
14504 }
14505
14506 static void
14507 OP_E_memory (int bytemode, int sizeflag)
14508 {
14509   bfd_vma disp = 0;
14510   int add = (rex & REX_B) ? 8 : 0;
14511   int riprel = 0;
14512   int shift;
14513
14514   if (vex.evex)
14515     {
14516       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14517       if (vex.b
14518           && bytemode != x_mode
14519           && bytemode != xmmq_mode
14520           && bytemode != evex_half_bcst_xmmq_mode)
14521         {
14522           BadOp ();
14523           return;
14524         }
14525       switch (bytemode)
14526         {
14527         case dqw_mode:
14528         case dw_mode:
14529           shift = 1;
14530           break;
14531         case dqb_mode:
14532         case db_mode:
14533           shift = 0;
14534           break;
14535         case dq_mode:
14536           if (address_mode != mode_64bit)
14537             {
14538               shift = 2;
14539               break;
14540             }
14541             /* fall through */
14542         case vex_scalar_w_dq_mode:
14543         case vex_vsib_d_w_dq_mode:
14544         case vex_vsib_d_w_d_mode:
14545         case vex_vsib_q_w_dq_mode:
14546         case vex_vsib_q_w_d_mode:
14547         case evex_x_gscat_mode:
14548           shift = vex.w ? 3 : 2;
14549           break;
14550         case x_mode:
14551         case evex_half_bcst_xmmq_mode:
14552         case xmmq_mode:
14553           if (vex.b)
14554             {
14555               shift = vex.w ? 3 : 2;
14556               break;
14557             }
14558           /* Fall through.  */
14559         case xmmqd_mode:
14560         case xmmdw_mode:
14561         case ymmq_mode:
14562         case evex_x_nobcst_mode:
14563         case x_swap_mode:
14564           switch (vex.length)
14565             {
14566             case 128:
14567               shift = 4;
14568               break;
14569             case 256:
14570               shift = 5;
14571               break;
14572             case 512:
14573               shift = 6;
14574               break;
14575             default:
14576               abort ();
14577             }
14578           break;
14579         case ymm_mode:
14580           shift = 5;
14581           break;
14582         case xmm_mode:
14583           shift = 4;
14584           break;
14585         case xmm_mq_mode:
14586         case q_mode:
14587         case q_swap_mode:
14588         case q_scalar_swap_mode:
14589           shift = 3;
14590           break;
14591         case dqd_mode:
14592         case xmm_md_mode:
14593         case d_mode:
14594         case d_swap_mode:
14595         case d_scalar_swap_mode:
14596           shift = 2;
14597           break;
14598         case w_scalar_mode:
14599         case xmm_mw_mode:
14600           shift = 1;
14601           break;
14602         case b_scalar_mode:
14603         case xmm_mb_mode:
14604           shift = 0;
14605           break;
14606         default:
14607           abort ();
14608         }
14609       /* Make necessary corrections to shift for modes that need it.
14610          For these modes we currently have shift 4, 5 or 6 depending on
14611          vex.length (it corresponds to xmmword, ymmword or zmmword
14612          operand).  We might want to make it 3, 4 or 5 (e.g. for
14613          xmmq_mode).  In case of broadcast enabled the corrections
14614          aren't needed, as element size is always 32 or 64 bits.  */
14615       if (!vex.b
14616           && (bytemode == xmmq_mode
14617               || bytemode == evex_half_bcst_xmmq_mode))
14618         shift -= 1;
14619       else if (bytemode == xmmqd_mode)
14620         shift -= 2;
14621       else if (bytemode == xmmdw_mode)
14622         shift -= 3;
14623       else if (bytemode == ymmq_mode && vex.length == 128)
14624         shift -= 1;
14625     }
14626   else
14627     shift = 0;
14628
14629   USED_REX (REX_B);
14630   if (intel_syntax)
14631     intel_operand_size (bytemode, sizeflag);
14632   append_seg ();
14633
14634   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14635     {
14636       /* 32/64 bit address mode */
14637       int havedisp;
14638       int havesib;
14639       int havebase;
14640       int haveindex;
14641       int needindex;
14642       int needaddr32;
14643       int base, rbase;
14644       int vindex = 0;
14645       int scale = 0;
14646       int addr32flag = !((sizeflag & AFLAG)
14647                          || bytemode == v_bnd_mode
14648                          || bytemode == v_bndmk_mode
14649                          || bytemode == bnd_mode
14650                          || bytemode == bnd_swap_mode);
14651       const char **indexes64 = names64;
14652       const char **indexes32 = names32;
14653
14654       havesib = 0;
14655       havebase = 1;
14656       haveindex = 0;
14657       base = modrm.rm;
14658
14659       if (base == 4)
14660         {
14661           havesib = 1;
14662           vindex = sib.index;
14663           USED_REX (REX_X);
14664           if (rex & REX_X)
14665             vindex += 8;
14666           switch (bytemode)
14667             {
14668             case vex_vsib_d_w_dq_mode:
14669             case vex_vsib_d_w_d_mode:
14670             case vex_vsib_q_w_dq_mode:
14671             case vex_vsib_q_w_d_mode:
14672               if (!need_vex)
14673                 abort ();
14674               if (vex.evex)
14675                 {
14676                   if (!vex.v)
14677                     vindex += 16;
14678                 }
14679
14680               haveindex = 1;
14681               switch (vex.length)
14682                 {
14683                 case 128:
14684                   indexes64 = indexes32 = names_xmm;
14685                   break;
14686                 case 256:
14687                   if (!vex.w
14688                       || bytemode == vex_vsib_q_w_dq_mode
14689                       || bytemode == vex_vsib_q_w_d_mode)
14690                     indexes64 = indexes32 = names_ymm;
14691                   else
14692                     indexes64 = indexes32 = names_xmm;
14693                   break;
14694                 case 512:
14695                   if (!vex.w
14696                       || bytemode == vex_vsib_q_w_dq_mode
14697                       || bytemode == vex_vsib_q_w_d_mode)
14698                     indexes64 = indexes32 = names_zmm;
14699                   else
14700                     indexes64 = indexes32 = names_ymm;
14701                   break;
14702                 default:
14703                   abort ();
14704                 }
14705               break;
14706             default:
14707               haveindex = vindex != 4;
14708               break;
14709             }
14710           scale = sib.scale;
14711           base = sib.base;
14712           codep++;
14713         }
14714       else
14715         {
14716           /* mandatory non-vector SIB must have sib */
14717           if (bytemode == vex_sibmem_mode)
14718             {
14719               oappend ("(bad)");
14720               return;
14721             }
14722         }
14723       rbase = base + add;
14724
14725       switch (modrm.mod)
14726         {
14727         case 0:
14728           if (base == 5)
14729             {
14730               havebase = 0;
14731               if (address_mode == mode_64bit && !havesib)
14732                 riprel = 1;
14733               disp = get32s ();
14734               if (riprel && bytemode == v_bndmk_mode)
14735                 {
14736                   oappend ("(bad)");
14737                   return;
14738                 }
14739             }
14740           break;
14741         case 1:
14742           FETCH_DATA (the_info, codep + 1);
14743           disp = *codep++;
14744           if ((disp & 0x80) != 0)
14745             disp -= 0x100;
14746           if (vex.evex && shift > 0)
14747             disp <<= shift;
14748           break;
14749         case 2:
14750           disp = get32s ();
14751           break;
14752         }
14753
14754       needindex = 0;
14755       needaddr32 = 0;
14756       if (havesib
14757           && !havebase
14758           && !haveindex
14759           && address_mode != mode_16bit)
14760         {
14761           if (address_mode == mode_64bit)
14762             {
14763               /* Display eiz instead of addr32.  */
14764               needindex = addr32flag;
14765               needaddr32 = 1;
14766             }
14767           else
14768             {
14769               /* In 32-bit mode, we need index register to tell [offset]
14770                  from [eiz*1 + offset].  */
14771               needindex = 1;
14772             }
14773         }
14774
14775       havedisp = (havebase
14776                   || needindex
14777                   || (havesib && (haveindex || scale != 0)));
14778
14779       if (!intel_syntax)
14780         if (modrm.mod != 0 || base == 5)
14781           {
14782             if (havedisp || riprel)
14783               print_displacement (scratchbuf, disp);
14784             else
14785               print_operand_value (scratchbuf, 1, disp);
14786             oappend (scratchbuf);
14787             if (riprel)
14788               {
14789                 set_op (disp, 1);
14790                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14791               }
14792           }
14793
14794       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14795           && (address_mode != mode_64bit
14796               || ((bytemode != v_bnd_mode)
14797                   && (bytemode != v_bndmk_mode)
14798                   && (bytemode != bnd_mode)
14799                   && (bytemode != bnd_swap_mode))))
14800         used_prefixes |= PREFIX_ADDR;
14801
14802       if (havedisp || (intel_syntax && riprel))
14803         {
14804           *obufp++ = open_char;
14805           if (intel_syntax && riprel)
14806             {
14807               set_op (disp, 1);
14808               oappend (!addr32flag ? "rip" : "eip");
14809             }
14810           *obufp = '\0';
14811           if (havebase)
14812             oappend (address_mode == mode_64bit && !addr32flag
14813                      ? names64[rbase] : names32[rbase]);
14814           if (havesib)
14815             {
14816               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14817                  print index to tell base + index from base.  */
14818               if (scale != 0
14819                   || needindex
14820                   || haveindex
14821                   || (havebase && base != ESP_REG_NUM))
14822                 {
14823                   if (!intel_syntax || havebase)
14824                     {
14825                       *obufp++ = separator_char;
14826                       *obufp = '\0';
14827                     }
14828                   if (haveindex)
14829                     oappend (address_mode == mode_64bit && !addr32flag
14830                              ? indexes64[vindex] : indexes32[vindex]);
14831                   else
14832                     oappend (address_mode == mode_64bit && !addr32flag
14833                              ? index64 : index32);
14834
14835                   *obufp++ = scale_char;
14836                   *obufp = '\0';
14837                   sprintf (scratchbuf, "%d", 1 << scale);
14838                   oappend (scratchbuf);
14839                 }
14840             }
14841           if (intel_syntax
14842               && (disp || modrm.mod != 0 || base == 5))
14843             {
14844               if (!havedisp || (bfd_signed_vma) disp >= 0)
14845                 {
14846                   *obufp++ = '+';
14847                   *obufp = '\0';
14848                 }
14849               else if (modrm.mod != 1 && disp != -disp)
14850                 {
14851                   *obufp++ = '-';
14852                   *obufp = '\0';
14853                   disp = - (bfd_signed_vma) disp;
14854                 }
14855
14856               if (havedisp)
14857                 print_displacement (scratchbuf, disp);
14858               else
14859                 print_operand_value (scratchbuf, 1, disp);
14860               oappend (scratchbuf);
14861             }
14862
14863           *obufp++ = close_char;
14864           *obufp = '\0';
14865         }
14866       else if (intel_syntax)
14867         {
14868           if (modrm.mod != 0 || base == 5)
14869             {
14870               if (!active_seg_prefix)
14871                 {
14872                   oappend (names_seg[ds_reg - es_reg]);
14873                   oappend (":");
14874                 }
14875               print_operand_value (scratchbuf, 1, disp);
14876               oappend (scratchbuf);
14877             }
14878         }
14879     }
14880   else if (bytemode == v_bnd_mode
14881            || bytemode == v_bndmk_mode
14882            || bytemode == bnd_mode
14883            || bytemode == bnd_swap_mode)
14884     {
14885       oappend ("(bad)");
14886       return;
14887     }
14888   else
14889     {
14890       /* 16 bit address mode */
14891       used_prefixes |= prefixes & PREFIX_ADDR;
14892       switch (modrm.mod)
14893         {
14894         case 0:
14895           if (modrm.rm == 6)
14896             {
14897               disp = get16 ();
14898               if ((disp & 0x8000) != 0)
14899                 disp -= 0x10000;
14900             }
14901           break;
14902         case 1:
14903           FETCH_DATA (the_info, codep + 1);
14904           disp = *codep++;
14905           if ((disp & 0x80) != 0)
14906             disp -= 0x100;
14907           if (vex.evex && shift > 0)
14908             disp <<= shift;
14909           break;
14910         case 2:
14911           disp = get16 ();
14912           if ((disp & 0x8000) != 0)
14913             disp -= 0x10000;
14914           break;
14915         }
14916
14917       if (!intel_syntax)
14918         if (modrm.mod != 0 || modrm.rm == 6)
14919           {
14920             print_displacement (scratchbuf, disp);
14921             oappend (scratchbuf);
14922           }
14923
14924       if (modrm.mod != 0 || modrm.rm != 6)
14925         {
14926           *obufp++ = open_char;
14927           *obufp = '\0';
14928           oappend (index16[modrm.rm]);
14929           if (intel_syntax
14930               && (disp || modrm.mod != 0 || modrm.rm == 6))
14931             {
14932               if ((bfd_signed_vma) disp >= 0)
14933                 {
14934                   *obufp++ = '+';
14935                   *obufp = '\0';
14936                 }
14937               else if (modrm.mod != 1)
14938                 {
14939                   *obufp++ = '-';
14940                   *obufp = '\0';
14941                   disp = - (bfd_signed_vma) disp;
14942                 }
14943
14944               print_displacement (scratchbuf, disp);
14945               oappend (scratchbuf);
14946             }
14947
14948           *obufp++ = close_char;
14949           *obufp = '\0';
14950         }
14951       else if (intel_syntax)
14952         {
14953           if (!active_seg_prefix)
14954             {
14955               oappend (names_seg[ds_reg - es_reg]);
14956               oappend (":");
14957             }
14958           print_operand_value (scratchbuf, 1, disp & 0xffff);
14959           oappend (scratchbuf);
14960         }
14961     }
14962   if (vex.evex && vex.b
14963       && (bytemode == x_mode
14964           || bytemode == xmmq_mode
14965           || bytemode == evex_half_bcst_xmmq_mode))
14966     {
14967       if (vex.w
14968           || bytemode == xmmq_mode
14969           || bytemode == evex_half_bcst_xmmq_mode)
14970         {
14971           switch (vex.length)
14972             {
14973             case 128:
14974               oappend ("{1to2}");
14975               break;
14976             case 256:
14977               oappend ("{1to4}");
14978               break;
14979             case 512:
14980               oappend ("{1to8}");
14981               break;
14982             default:
14983               abort ();
14984             }
14985         }
14986       else
14987         {
14988           switch (vex.length)
14989             {
14990             case 128:
14991               oappend ("{1to4}");
14992               break;
14993             case 256:
14994               oappend ("{1to8}");
14995               break;
14996             case 512:
14997               oappend ("{1to16}");
14998               break;
14999             default:
15000               abort ();
15001             }
15002         }
15003     }
15004 }
15005
15006 static void
15007 OP_E (int bytemode, int sizeflag)
15008 {
15009   /* Skip mod/rm byte.  */
15010   MODRM_CHECK;
15011   codep++;
15012
15013   if (modrm.mod == 3)
15014     OP_E_register (bytemode, sizeflag);
15015   else
15016     OP_E_memory (bytemode, sizeflag);
15017 }
15018
15019 static void
15020 OP_G (int bytemode, int sizeflag)
15021 {
15022   int add = 0;
15023   const char **names;
15024   USED_REX (REX_R);
15025   if (rex & REX_R)
15026     add += 8;
15027   switch (bytemode)
15028     {
15029     case b_mode:
15030       USED_REX (0);
15031       if (rex)
15032         oappend (names8rex[modrm.reg + add]);
15033       else
15034         oappend (names8[modrm.reg + add]);
15035       break;
15036     case w_mode:
15037       oappend (names16[modrm.reg + add]);
15038       break;
15039     case d_mode:
15040     case db_mode:
15041     case dw_mode:
15042       oappend (names32[modrm.reg + add]);
15043       break;
15044     case q_mode:
15045       oappend (names64[modrm.reg + add]);
15046       break;
15047     case bnd_mode:
15048       if (modrm.reg > 0x3)
15049         {
15050           oappend ("(bad)");
15051           return;
15052         }
15053       oappend (names_bnd[modrm.reg]);
15054       break;
15055     case v_mode:
15056     case dq_mode:
15057     case dqb_mode:
15058     case dqd_mode:
15059     case dqw_mode:
15060     case movsxd_mode:
15061       USED_REX (REX_W);
15062       if (rex & REX_W)
15063         oappend (names64[modrm.reg + add]);
15064       else
15065         {
15066           if ((sizeflag & DFLAG)
15067               || (bytemode != v_mode && bytemode != movsxd_mode))
15068             oappend (names32[modrm.reg + add]);
15069           else
15070             oappend (names16[modrm.reg + add]);
15071           used_prefixes |= (prefixes & PREFIX_DATA);
15072         }
15073       break;
15074     case va_mode:
15075       names = (address_mode == mode_64bit
15076                ? names64 : names32);
15077       if (!(prefixes & PREFIX_ADDR))
15078         {
15079           if (address_mode == mode_16bit)
15080             names = names16;
15081         }
15082       else
15083         {
15084           /* Remove "addr16/addr32".  */
15085           all_prefixes[last_addr_prefix] = 0;
15086           names = (address_mode != mode_32bit
15087                        ? names32 : names16);
15088           used_prefixes |= PREFIX_ADDR;
15089         }
15090       oappend (names[modrm.reg + add]);
15091       break;
15092     case m_mode:
15093       if (address_mode == mode_64bit)
15094         oappend (names64[modrm.reg + add]);
15095       else
15096         oappend (names32[modrm.reg + add]);
15097       break;
15098     case mask_bd_mode:
15099     case mask_mode:
15100       if ((modrm.reg + add) > 0x7)
15101         {
15102           oappend ("(bad)");
15103           return;
15104         }
15105       oappend (names_mask[modrm.reg + add]);
15106       break;
15107     default:
15108       oappend (INTERNAL_DISASSEMBLER_ERROR);
15109       break;
15110     }
15111 }
15112
15113 static bfd_vma
15114 get64 (void)
15115 {
15116   bfd_vma x;
15117 #ifdef BFD64
15118   unsigned int a;
15119   unsigned int b;
15120
15121   FETCH_DATA (the_info, codep + 8);
15122   a = *codep++ & 0xff;
15123   a |= (*codep++ & 0xff) << 8;
15124   a |= (*codep++ & 0xff) << 16;
15125   a |= (*codep++ & 0xffu) << 24;
15126   b = *codep++ & 0xff;
15127   b |= (*codep++ & 0xff) << 8;
15128   b |= (*codep++ & 0xff) << 16;
15129   b |= (*codep++ & 0xffu) << 24;
15130   x = a + ((bfd_vma) b << 32);
15131 #else
15132   abort ();
15133   x = 0;
15134 #endif
15135   return x;
15136 }
15137
15138 static bfd_signed_vma
15139 get32 (void)
15140 {
15141   bfd_signed_vma x = 0;
15142
15143   FETCH_DATA (the_info, codep + 4);
15144   x = *codep++ & (bfd_signed_vma) 0xff;
15145   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15146   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15147   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15148   return x;
15149 }
15150
15151 static bfd_signed_vma
15152 get32s (void)
15153 {
15154   bfd_signed_vma x = 0;
15155
15156   FETCH_DATA (the_info, codep + 4);
15157   x = *codep++ & (bfd_signed_vma) 0xff;
15158   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15159   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15160   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15161
15162   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15163
15164   return x;
15165 }
15166
15167 static int
15168 get16 (void)
15169 {
15170   int x = 0;
15171
15172   FETCH_DATA (the_info, codep + 2);
15173   x = *codep++ & 0xff;
15174   x |= (*codep++ & 0xff) << 8;
15175   return x;
15176 }
15177
15178 static void
15179 set_op (bfd_vma op, int riprel)
15180 {
15181   op_index[op_ad] = op_ad;
15182   if (address_mode == mode_64bit)
15183     {
15184       op_address[op_ad] = op;
15185       op_riprel[op_ad] = riprel;
15186     }
15187   else
15188     {
15189       /* Mask to get a 32-bit address.  */
15190       op_address[op_ad] = op & 0xffffffff;
15191       op_riprel[op_ad] = riprel & 0xffffffff;
15192     }
15193 }
15194
15195 static void
15196 OP_REG (int code, int sizeflag)
15197 {
15198   const char *s;
15199   int add;
15200
15201   switch (code)
15202     {
15203     case es_reg: case ss_reg: case cs_reg:
15204     case ds_reg: case fs_reg: case gs_reg:
15205       oappend (names_seg[code - es_reg]);
15206       return;
15207     }
15208
15209   USED_REX (REX_B);
15210   if (rex & REX_B)
15211     add = 8;
15212   else
15213     add = 0;
15214
15215   switch (code)
15216     {
15217     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15218     case sp_reg: case bp_reg: case si_reg: case di_reg:
15219       s = names16[code - ax_reg + add];
15220       break;
15221     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15222     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15223       USED_REX (0);
15224       if (rex)
15225         s = names8rex[code - al_reg + add];
15226       else
15227         s = names8[code - al_reg];
15228       break;
15229     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15230     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15231       if (address_mode == mode_64bit
15232           && ((sizeflag & DFLAG) || (rex & REX_W)))
15233         {
15234           s = names64[code - rAX_reg + add];
15235           break;
15236         }
15237       code += eAX_reg - rAX_reg;
15238       /* Fall through.  */
15239     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15240     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15241       USED_REX (REX_W);
15242       if (rex & REX_W)
15243         s = names64[code - eAX_reg + add];
15244       else
15245         {
15246           if (sizeflag & DFLAG)
15247             s = names32[code - eAX_reg + add];
15248           else
15249             s = names16[code - eAX_reg + add];
15250           used_prefixes |= (prefixes & PREFIX_DATA);
15251         }
15252       break;
15253     default:
15254       s = INTERNAL_DISASSEMBLER_ERROR;
15255       break;
15256     }
15257   oappend (s);
15258 }
15259
15260 static void
15261 OP_IMREG (int code, int sizeflag)
15262 {
15263   const char *s;
15264
15265   switch (code)
15266     {
15267     case indir_dx_reg:
15268       if (intel_syntax)
15269         s = "dx";
15270       else
15271         s = "(%dx)";
15272       break;
15273     case al_reg: case cl_reg:
15274       s = names8[code - al_reg];
15275       break;
15276     case eAX_reg:
15277       USED_REX (REX_W);
15278       if (rex & REX_W)
15279         {
15280           s = *names64;
15281           break;
15282         }
15283       /* Fall through.  */
15284     case z_mode_ax_reg:
15285       if ((rex & REX_W) || (sizeflag & DFLAG))
15286         s = *names32;
15287       else
15288         s = *names16;
15289       if (!(rex & REX_W))
15290         used_prefixes |= (prefixes & PREFIX_DATA);
15291       break;
15292     default:
15293       s = INTERNAL_DISASSEMBLER_ERROR;
15294       break;
15295     }
15296   oappend (s);
15297 }
15298
15299 static void
15300 OP_I (int bytemode, int sizeflag)
15301 {
15302   bfd_signed_vma op;
15303   bfd_signed_vma mask = -1;
15304
15305   switch (bytemode)
15306     {
15307     case b_mode:
15308       FETCH_DATA (the_info, codep + 1);
15309       op = *codep++;
15310       mask = 0xff;
15311       break;
15312     case v_mode:
15313       USED_REX (REX_W);
15314       if (rex & REX_W)
15315         op = get32s ();
15316       else
15317         {
15318           if (sizeflag & DFLAG)
15319             {
15320               op = get32 ();
15321               mask = 0xffffffff;
15322             }
15323           else
15324             {
15325               op = get16 ();
15326               mask = 0xfffff;
15327             }
15328           used_prefixes |= (prefixes & PREFIX_DATA);
15329         }
15330       break;
15331     case d_mode:
15332       mask = 0xffffffff;
15333       op = get32 ();
15334       break;
15335     case w_mode:
15336       mask = 0xfffff;
15337       op = get16 ();
15338       break;
15339     case const_1_mode:
15340       if (intel_syntax)
15341         oappend ("1");
15342       return;
15343     default:
15344       oappend (INTERNAL_DISASSEMBLER_ERROR);
15345       return;
15346     }
15347
15348   op &= mask;
15349   scratchbuf[0] = '$';
15350   print_operand_value (scratchbuf + 1, 1, op);
15351   oappend_maybe_intel (scratchbuf);
15352   scratchbuf[0] = '\0';
15353 }
15354
15355 static void
15356 OP_I64 (int bytemode, int sizeflag)
15357 {
15358   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15359     {
15360       OP_I (bytemode, sizeflag);
15361       return;
15362     }
15363
15364   USED_REX (REX_W);
15365
15366   scratchbuf[0] = '$';
15367   print_operand_value (scratchbuf + 1, 1, get64 ());
15368   oappend_maybe_intel (scratchbuf);
15369   scratchbuf[0] = '\0';
15370 }
15371
15372 static void
15373 OP_sI (int bytemode, int sizeflag)
15374 {
15375   bfd_signed_vma op;
15376
15377   switch (bytemode)
15378     {
15379     case b_mode:
15380     case b_T_mode:
15381       FETCH_DATA (the_info, codep + 1);
15382       op = *codep++;
15383       if ((op & 0x80) != 0)
15384         op -= 0x100;
15385       if (bytemode == b_T_mode)
15386         {
15387           if (address_mode != mode_64bit
15388               || !((sizeflag & DFLAG) || (rex & REX_W)))
15389             {
15390               /* The operand-size prefix is overridden by a REX prefix.  */
15391               if ((sizeflag & DFLAG) || (rex & REX_W))
15392                 op &= 0xffffffff;
15393               else
15394                 op &= 0xffff;
15395           }
15396         }
15397       else
15398         {
15399           if (!(rex & REX_W))
15400             {
15401               if (sizeflag & DFLAG)
15402                 op &= 0xffffffff;
15403               else
15404                 op &= 0xffff;
15405             }
15406         }
15407       break;
15408     case v_mode:
15409       /* The operand-size prefix is overridden by a REX prefix.  */
15410       if ((sizeflag & DFLAG) || (rex & REX_W))
15411         op = get32s ();
15412       else
15413         op = get16 ();
15414       break;
15415     default:
15416       oappend (INTERNAL_DISASSEMBLER_ERROR);
15417       return;
15418     }
15419
15420   scratchbuf[0] = '$';
15421   print_operand_value (scratchbuf + 1, 1, op);
15422   oappend_maybe_intel (scratchbuf);
15423 }
15424
15425 static void
15426 OP_J (int bytemode, int sizeflag)
15427 {
15428   bfd_vma disp;
15429   bfd_vma mask = -1;
15430   bfd_vma segment = 0;
15431
15432   switch (bytemode)
15433     {
15434     case b_mode:
15435       FETCH_DATA (the_info, codep + 1);
15436       disp = *codep++;
15437       if ((disp & 0x80) != 0)
15438         disp -= 0x100;
15439       break;
15440     case v_mode:
15441       if (isa64 != intel64)
15442     case dqw_mode:
15443         USED_REX (REX_W);
15444       if ((sizeflag & DFLAG)
15445           || (address_mode == mode_64bit
15446               && ((isa64 == intel64 && bytemode != dqw_mode)
15447                   || (rex & REX_W))))
15448         disp = get32s ();
15449       else
15450         {
15451           disp = get16 ();
15452           if ((disp & 0x8000) != 0)
15453             disp -= 0x10000;
15454           /* In 16bit mode, address is wrapped around at 64k within
15455              the same segment.  Otherwise, a data16 prefix on a jump
15456              instruction means that the pc is masked to 16 bits after
15457              the displacement is added!  */
15458           mask = 0xffff;
15459           if ((prefixes & PREFIX_DATA) == 0)
15460             segment = ((start_pc + (codep - start_codep))
15461                        & ~((bfd_vma) 0xffff));
15462         }
15463       if (address_mode != mode_64bit
15464           || (isa64 != intel64 && !(rex & REX_W)))
15465         used_prefixes |= (prefixes & PREFIX_DATA);
15466       break;
15467     default:
15468       oappend (INTERNAL_DISASSEMBLER_ERROR);
15469       return;
15470     }
15471   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15472   set_op (disp, 0);
15473   print_operand_value (scratchbuf, 1, disp);
15474   oappend (scratchbuf);
15475 }
15476
15477 static void
15478 OP_SEG (int bytemode, int sizeflag)
15479 {
15480   if (bytemode == w_mode)
15481     oappend (names_seg[modrm.reg]);
15482   else
15483     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15484 }
15485
15486 static void
15487 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15488 {
15489   int seg, offset;
15490
15491   if (sizeflag & DFLAG)
15492     {
15493       offset = get32 ();
15494       seg = get16 ();
15495     }
15496   else
15497     {
15498       offset = get16 ();
15499       seg = get16 ();
15500     }
15501   used_prefixes |= (prefixes & PREFIX_DATA);
15502   if (intel_syntax)
15503     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15504   else
15505     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15506   oappend (scratchbuf);
15507 }
15508
15509 static void
15510 OP_OFF (int bytemode, int sizeflag)
15511 {
15512   bfd_vma off;
15513
15514   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15515     intel_operand_size (bytemode, sizeflag);
15516   append_seg ();
15517
15518   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15519     off = get32 ();
15520   else
15521     off = get16 ();
15522
15523   if (intel_syntax)
15524     {
15525       if (!active_seg_prefix)
15526         {
15527           oappend (names_seg[ds_reg - es_reg]);
15528           oappend (":");
15529         }
15530     }
15531   print_operand_value (scratchbuf, 1, off);
15532   oappend (scratchbuf);
15533 }
15534
15535 static void
15536 OP_OFF64 (int bytemode, int sizeflag)
15537 {
15538   bfd_vma off;
15539
15540   if (address_mode != mode_64bit
15541       || (prefixes & PREFIX_ADDR))
15542     {
15543       OP_OFF (bytemode, sizeflag);
15544       return;
15545     }
15546
15547   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15548     intel_operand_size (bytemode, sizeflag);
15549   append_seg ();
15550
15551   off = get64 ();
15552
15553   if (intel_syntax)
15554     {
15555       if (!active_seg_prefix)
15556         {
15557           oappend (names_seg[ds_reg - es_reg]);
15558           oappend (":");
15559         }
15560     }
15561   print_operand_value (scratchbuf, 1, off);
15562   oappend (scratchbuf);
15563 }
15564
15565 static void
15566 ptr_reg (int code, int sizeflag)
15567 {
15568   const char *s;
15569
15570   *obufp++ = open_char;
15571   used_prefixes |= (prefixes & PREFIX_ADDR);
15572   if (address_mode == mode_64bit)
15573     {
15574       if (!(sizeflag & AFLAG))
15575         s = names32[code - eAX_reg];
15576       else
15577         s = names64[code - eAX_reg];
15578     }
15579   else if (sizeflag & AFLAG)
15580     s = names32[code - eAX_reg];
15581   else
15582     s = names16[code - eAX_reg];
15583   oappend (s);
15584   *obufp++ = close_char;
15585   *obufp = 0;
15586 }
15587
15588 static void
15589 OP_ESreg (int code, int sizeflag)
15590 {
15591   if (intel_syntax)
15592     {
15593       switch (codep[-1])
15594         {
15595         case 0x6d:      /* insw/insl */
15596           intel_operand_size (z_mode, sizeflag);
15597           break;
15598         case 0xa5:      /* movsw/movsl/movsq */
15599         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15600         case 0xab:      /* stosw/stosl */
15601         case 0xaf:      /* scasw/scasl */
15602           intel_operand_size (v_mode, sizeflag);
15603           break;
15604         default:
15605           intel_operand_size (b_mode, sizeflag);
15606         }
15607     }
15608   oappend_maybe_intel ("%es:");
15609   ptr_reg (code, sizeflag);
15610 }
15611
15612 static void
15613 OP_DSreg (int code, int sizeflag)
15614 {
15615   if (intel_syntax)
15616     {
15617       switch (codep[-1])
15618         {
15619         case 0x6f:      /* outsw/outsl */
15620           intel_operand_size (z_mode, sizeflag);
15621           break;
15622         case 0xa5:      /* movsw/movsl/movsq */
15623         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15624         case 0xad:      /* lodsw/lodsl/lodsq */
15625           intel_operand_size (v_mode, sizeflag);
15626           break;
15627         default:
15628           intel_operand_size (b_mode, sizeflag);
15629         }
15630     }
15631   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15632      default segment register DS is printed.  */
15633   if (!active_seg_prefix)
15634     active_seg_prefix = PREFIX_DS;
15635   append_seg ();
15636   ptr_reg (code, sizeflag);
15637 }
15638
15639 static void
15640 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15641 {
15642   int add;
15643   if (rex & REX_R)
15644     {
15645       USED_REX (REX_R);
15646       add = 8;
15647     }
15648   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15649     {
15650       all_prefixes[last_lock_prefix] = 0;
15651       used_prefixes |= PREFIX_LOCK;
15652       add = 8;
15653     }
15654   else
15655     add = 0;
15656   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15657   oappend_maybe_intel (scratchbuf);
15658 }
15659
15660 static void
15661 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15662 {
15663   int add;
15664   USED_REX (REX_R);
15665   if (rex & REX_R)
15666     add = 8;
15667   else
15668     add = 0;
15669   if (intel_syntax)
15670     sprintf (scratchbuf, "db%d", modrm.reg + add);
15671   else
15672     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15673   oappend (scratchbuf);
15674 }
15675
15676 static void
15677 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15678 {
15679   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15680   oappend_maybe_intel (scratchbuf);
15681 }
15682
15683 static void
15684 OP_R (int bytemode, int sizeflag)
15685 {
15686   /* Skip mod/rm byte.  */
15687   MODRM_CHECK;
15688   codep++;
15689   OP_E_register (bytemode, sizeflag);
15690 }
15691
15692 static void
15693 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15694 {
15695   int reg = modrm.reg;
15696   const char **names;
15697
15698   used_prefixes |= (prefixes & PREFIX_DATA);
15699   if (prefixes & PREFIX_DATA)
15700     {
15701       names = names_xmm;
15702       USED_REX (REX_R);
15703       if (rex & REX_R)
15704         reg += 8;
15705     }
15706   else
15707     names = names_mm;
15708   oappend (names[reg]);
15709 }
15710
15711 static void
15712 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15713 {
15714   int reg = modrm.reg;
15715   const char **names;
15716
15717   USED_REX (REX_R);
15718   if (rex & REX_R)
15719     reg += 8;
15720   if (vex.evex)
15721     {
15722       if (!vex.r)
15723         reg += 16;
15724     }
15725
15726   if (need_vex
15727       && bytemode != xmm_mode
15728       && bytemode != xmmq_mode
15729       && bytemode != evex_half_bcst_xmmq_mode
15730       && bytemode != ymm_mode
15731       && bytemode != tmm_mode
15732       && bytemode != scalar_mode)
15733     {
15734       switch (vex.length)
15735         {
15736         case 128:
15737           names = names_xmm;
15738           break;
15739         case 256:
15740           if (vex.w
15741               || (bytemode != vex_vsib_q_w_dq_mode
15742                   && bytemode != vex_vsib_q_w_d_mode))
15743             names = names_ymm;
15744           else
15745             names = names_xmm;
15746           break;
15747         case 512:
15748           names = names_zmm;
15749           break;
15750         default:
15751           abort ();
15752         }
15753     }
15754   else if (bytemode == xmmq_mode
15755            || bytemode == evex_half_bcst_xmmq_mode)
15756     {
15757       switch (vex.length)
15758         {
15759         case 128:
15760         case 256:
15761           names = names_xmm;
15762           break;
15763         case 512:
15764           names = names_ymm;
15765           break;
15766         default:
15767           abort ();
15768         }
15769     }
15770   else if (bytemode == tmm_mode)
15771     {
15772       modrm.reg = reg;
15773       if (reg >= 8)
15774         {
15775           oappend ("(bad)");
15776           return;
15777         }
15778       names = names_tmm;
15779     }
15780   else if (bytemode == ymm_mode)
15781     names = names_ymm;
15782   else
15783     names = names_xmm;
15784   oappend (names[reg]);
15785 }
15786
15787 static void
15788 OP_EM (int bytemode, int sizeflag)
15789 {
15790   int reg;
15791   const char **names;
15792
15793   if (modrm.mod != 3)
15794     {
15795       if (intel_syntax
15796           && (bytemode == v_mode || bytemode == v_swap_mode))
15797         {
15798           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15799           used_prefixes |= (prefixes & PREFIX_DATA);
15800         }
15801       OP_E (bytemode, sizeflag);
15802       return;
15803     }
15804
15805   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15806     swap_operand ();
15807
15808   /* Skip mod/rm byte.  */
15809   MODRM_CHECK;
15810   codep++;
15811   used_prefixes |= (prefixes & PREFIX_DATA);
15812   reg = modrm.rm;
15813   if (prefixes & PREFIX_DATA)
15814     {
15815       names = names_xmm;
15816       USED_REX (REX_B);
15817       if (rex & REX_B)
15818         reg += 8;
15819     }
15820   else
15821     names = names_mm;
15822   oappend (names[reg]);
15823 }
15824
15825 /* cvt* are the only instructions in sse2 which have
15826    both SSE and MMX operands and also have 0x66 prefix
15827    in their opcode. 0x66 was originally used to differentiate
15828    between SSE and MMX instruction(operands). So we have to handle the
15829    cvt* separately using OP_EMC and OP_MXC */
15830 static void
15831 OP_EMC (int bytemode, int sizeflag)
15832 {
15833   if (modrm.mod != 3)
15834     {
15835       if (intel_syntax && bytemode == v_mode)
15836         {
15837           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15838           used_prefixes |= (prefixes & PREFIX_DATA);
15839         }
15840       OP_E (bytemode, sizeflag);
15841       return;
15842     }
15843
15844   /* Skip mod/rm byte.  */
15845   MODRM_CHECK;
15846   codep++;
15847   used_prefixes |= (prefixes & PREFIX_DATA);
15848   oappend (names_mm[modrm.rm]);
15849 }
15850
15851 static void
15852 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15853 {
15854   used_prefixes |= (prefixes & PREFIX_DATA);
15855   oappend (names_mm[modrm.reg]);
15856 }
15857
15858 static void
15859 OP_EX (int bytemode, int sizeflag)
15860 {
15861   int reg;
15862   const char **names;
15863
15864   /* Skip mod/rm byte.  */
15865   MODRM_CHECK;
15866   codep++;
15867
15868   if (modrm.mod != 3)
15869     {
15870       OP_E_memory (bytemode, sizeflag);
15871       return;
15872     }
15873
15874   reg = modrm.rm;
15875   USED_REX (REX_B);
15876   if (rex & REX_B)
15877     reg += 8;
15878   if (vex.evex)
15879     {
15880       USED_REX (REX_X);
15881       if ((rex & REX_X))
15882         reg += 16;
15883     }
15884
15885   if ((sizeflag & SUFFIX_ALWAYS)
15886       && (bytemode == x_swap_mode
15887           || bytemode == d_swap_mode
15888           || bytemode == d_scalar_swap_mode
15889           || bytemode == q_swap_mode
15890           || bytemode == q_scalar_swap_mode))
15891     swap_operand ();
15892
15893   if (need_vex
15894       && bytemode != xmm_mode
15895       && bytemode != xmmdw_mode
15896       && bytemode != xmmqd_mode
15897       && bytemode != xmm_mb_mode
15898       && bytemode != xmm_mw_mode
15899       && bytemode != xmm_md_mode
15900       && bytemode != xmm_mq_mode
15901       && bytemode != xmmq_mode
15902       && bytemode != evex_half_bcst_xmmq_mode
15903       && bytemode != ymm_mode
15904       && bytemode != tmm_mode
15905       && bytemode != d_scalar_swap_mode
15906       && bytemode != q_scalar_swap_mode
15907       && bytemode != vex_scalar_w_dq_mode)
15908     {
15909       switch (vex.length)
15910         {
15911         case 128:
15912           names = names_xmm;
15913           break;
15914         case 256:
15915           names = names_ymm;
15916           break;
15917         case 512:
15918           names = names_zmm;
15919           break;
15920         default:
15921           abort ();
15922         }
15923     }
15924   else if (bytemode == xmmq_mode
15925            || bytemode == evex_half_bcst_xmmq_mode)
15926     {
15927       switch (vex.length)
15928         {
15929         case 128:
15930         case 256:
15931           names = names_xmm;
15932           break;
15933         case 512:
15934           names = names_ymm;
15935           break;
15936         default:
15937           abort ();
15938         }
15939     }
15940   else if (bytemode == tmm_mode)
15941     {
15942       modrm.rm = reg;
15943       if (reg >= 8)
15944         {
15945           oappend ("(bad)");
15946           return;
15947         }
15948       names = names_tmm;
15949     }
15950   else if (bytemode == ymm_mode)
15951     names = names_ymm;
15952   else
15953     names = names_xmm;
15954   oappend (names[reg]);
15955 }
15956
15957 static void
15958 OP_MS (int bytemode, int sizeflag)
15959 {
15960   if (modrm.mod == 3)
15961     OP_EM (bytemode, sizeflag);
15962   else
15963     BadOp ();
15964 }
15965
15966 static void
15967 OP_XS (int bytemode, int sizeflag)
15968 {
15969   if (modrm.mod == 3)
15970     OP_EX (bytemode, sizeflag);
15971   else
15972     BadOp ();
15973 }
15974
15975 static void
15976 OP_M (int bytemode, int sizeflag)
15977 {
15978   if (modrm.mod == 3)
15979     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15980     BadOp ();
15981   else
15982     OP_E (bytemode, sizeflag);
15983 }
15984
15985 static void
15986 OP_0f07 (int bytemode, int sizeflag)
15987 {
15988   if (modrm.mod != 3 || modrm.rm != 0)
15989     BadOp ();
15990   else
15991     OP_E (bytemode, sizeflag);
15992 }
15993
15994 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15995    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15996
15997 static void
15998 NOP_Fixup1 (int bytemode, int sizeflag)
15999 {
16000   if ((prefixes & PREFIX_DATA) != 0
16001       || (rex != 0
16002           && rex != 0x48
16003           && address_mode == mode_64bit))
16004     OP_REG (bytemode, sizeflag);
16005   else
16006     strcpy (obuf, "nop");
16007 }
16008
16009 static void
16010 NOP_Fixup2 (int bytemode, int sizeflag)
16011 {
16012   if ((prefixes & PREFIX_DATA) != 0
16013       || (rex != 0
16014           && rex != 0x48
16015           && address_mode == mode_64bit))
16016     OP_IMREG (bytemode, sizeflag);
16017 }
16018
16019 static const char *const Suffix3DNow[] = {
16020 /* 00 */        NULL,           NULL,           NULL,           NULL,
16021 /* 04 */        NULL,           NULL,           NULL,           NULL,
16022 /* 08 */        NULL,           NULL,           NULL,           NULL,
16023 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16024 /* 10 */        NULL,           NULL,           NULL,           NULL,
16025 /* 14 */        NULL,           NULL,           NULL,           NULL,
16026 /* 18 */        NULL,           NULL,           NULL,           NULL,
16027 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16028 /* 20 */        NULL,           NULL,           NULL,           NULL,
16029 /* 24 */        NULL,           NULL,           NULL,           NULL,
16030 /* 28 */        NULL,           NULL,           NULL,           NULL,
16031 /* 2C */        NULL,           NULL,           NULL,           NULL,
16032 /* 30 */        NULL,           NULL,           NULL,           NULL,
16033 /* 34 */        NULL,           NULL,           NULL,           NULL,
16034 /* 38 */        NULL,           NULL,           NULL,           NULL,
16035 /* 3C */        NULL,           NULL,           NULL,           NULL,
16036 /* 40 */        NULL,           NULL,           NULL,           NULL,
16037 /* 44 */        NULL,           NULL,           NULL,           NULL,
16038 /* 48 */        NULL,           NULL,           NULL,           NULL,
16039 /* 4C */        NULL,           NULL,           NULL,           NULL,
16040 /* 50 */        NULL,           NULL,           NULL,           NULL,
16041 /* 54 */        NULL,           NULL,           NULL,           NULL,
16042 /* 58 */        NULL,           NULL,           NULL,           NULL,
16043 /* 5C */        NULL,           NULL,           NULL,           NULL,
16044 /* 60 */        NULL,           NULL,           NULL,           NULL,
16045 /* 64 */        NULL,           NULL,           NULL,           NULL,
16046 /* 68 */        NULL,           NULL,           NULL,           NULL,
16047 /* 6C */        NULL,           NULL,           NULL,           NULL,
16048 /* 70 */        NULL,           NULL,           NULL,           NULL,
16049 /* 74 */        NULL,           NULL,           NULL,           NULL,
16050 /* 78 */        NULL,           NULL,           NULL,           NULL,
16051 /* 7C */        NULL,           NULL,           NULL,           NULL,
16052 /* 80 */        NULL,           NULL,           NULL,           NULL,
16053 /* 84 */        NULL,           NULL,           NULL,           NULL,
16054 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16055 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16056 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16057 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16058 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16059 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16060 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16061 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16062 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16063 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16064 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16065 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16066 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16067 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16068 /* C0 */        NULL,           NULL,           NULL,           NULL,
16069 /* C4 */        NULL,           NULL,           NULL,           NULL,
16070 /* C8 */        NULL,           NULL,           NULL,           NULL,
16071 /* CC */        NULL,           NULL,           NULL,           NULL,
16072 /* D0 */        NULL,           NULL,           NULL,           NULL,
16073 /* D4 */        NULL,           NULL,           NULL,           NULL,
16074 /* D8 */        NULL,           NULL,           NULL,           NULL,
16075 /* DC */        NULL,           NULL,           NULL,           NULL,
16076 /* E0 */        NULL,           NULL,           NULL,           NULL,
16077 /* E4 */        NULL,           NULL,           NULL,           NULL,
16078 /* E8 */        NULL,           NULL,           NULL,           NULL,
16079 /* EC */        NULL,           NULL,           NULL,           NULL,
16080 /* F0 */        NULL,           NULL,           NULL,           NULL,
16081 /* F4 */        NULL,           NULL,           NULL,           NULL,
16082 /* F8 */        NULL,           NULL,           NULL,           NULL,
16083 /* FC */        NULL,           NULL,           NULL,           NULL,
16084 };
16085
16086 static void
16087 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16088 {
16089   const char *mnemonic;
16090
16091   FETCH_DATA (the_info, codep + 1);
16092   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16093      place where an 8-bit immediate would normally go.  ie. the last
16094      byte of the instruction.  */
16095   obufp = mnemonicendp;
16096   mnemonic = Suffix3DNow[*codep++ & 0xff];
16097   if (mnemonic)
16098     oappend (mnemonic);
16099   else
16100     {
16101       /* Since a variable sized modrm/sib chunk is between the start
16102          of the opcode (0x0f0f) and the opcode suffix, we need to do
16103          all the modrm processing first, and don't know until now that
16104          we have a bad opcode.  This necessitates some cleaning up.  */
16105       op_out[0][0] = '\0';
16106       op_out[1][0] = '\0';
16107       BadOp ();
16108     }
16109   mnemonicendp = obufp;
16110 }
16111
16112 static struct op simd_cmp_op[] =
16113 {
16114   { STRING_COMMA_LEN ("eq") },
16115   { STRING_COMMA_LEN ("lt") },
16116   { STRING_COMMA_LEN ("le") },
16117   { STRING_COMMA_LEN ("unord") },
16118   { STRING_COMMA_LEN ("neq") },
16119   { STRING_COMMA_LEN ("nlt") },
16120   { STRING_COMMA_LEN ("nle") },
16121   { STRING_COMMA_LEN ("ord") }
16122 };
16123
16124 static void
16125 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16126 {
16127   unsigned int cmp_type;
16128
16129   FETCH_DATA (the_info, codep + 1);
16130   cmp_type = *codep++ & 0xff;
16131   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16132     {
16133       char suffix [3];
16134       char *p = mnemonicendp - 2;
16135       suffix[0] = p[0];
16136       suffix[1] = p[1];
16137       suffix[2] = '\0';
16138       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16139       mnemonicendp += simd_cmp_op[cmp_type].len;
16140     }
16141   else
16142     {
16143       /* We have a reserved extension byte.  Output it directly.  */
16144       scratchbuf[0] = '$';
16145       print_operand_value (scratchbuf + 1, 1, cmp_type);
16146       oappend_maybe_intel (scratchbuf);
16147       scratchbuf[0] = '\0';
16148     }
16149 }
16150
16151 static void
16152 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16153 {
16154   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16155   if (!intel_syntax)
16156     {
16157       strcpy (op_out[0], names32[0]);
16158       strcpy (op_out[1], names32[1]);
16159       if (bytemode == eBX_reg)
16160         strcpy (op_out[2], names32[3]);
16161       two_source_ops = 1;
16162     }
16163   /* Skip mod/rm byte.  */
16164   MODRM_CHECK;
16165   codep++;
16166 }
16167
16168 static void
16169 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16170             int sizeflag ATTRIBUTE_UNUSED)
16171 {
16172   /* monitor %{e,r,}ax,%ecx,%edx"  */
16173   if (!intel_syntax)
16174     {
16175       const char **names = (address_mode == mode_64bit
16176                             ? names64 : names32);
16177
16178       if (prefixes & PREFIX_ADDR)
16179         {
16180           /* Remove "addr16/addr32".  */
16181           all_prefixes[last_addr_prefix] = 0;
16182           names = (address_mode != mode_32bit
16183                    ? names32 : names16);
16184           used_prefixes |= PREFIX_ADDR;
16185         }
16186       else if (address_mode == mode_16bit)
16187         names = names16;
16188       strcpy (op_out[0], names[0]);
16189       strcpy (op_out[1], names32[1]);
16190       strcpy (op_out[2], names32[2]);
16191       two_source_ops = 1;
16192     }
16193   /* Skip mod/rm byte.  */
16194   MODRM_CHECK;
16195   codep++;
16196 }
16197
16198 static void
16199 BadOp (void)
16200 {
16201   /* Throw away prefixes and 1st. opcode byte.  */
16202   codep = insn_codep + 1;
16203   oappend ("(bad)");
16204 }
16205
16206 static void
16207 REP_Fixup (int bytemode, int sizeflag)
16208 {
16209   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16210      lods and stos.  */
16211   if (prefixes & PREFIX_REPZ)
16212     all_prefixes[last_repz_prefix] = REP_PREFIX;
16213
16214   switch (bytemode)
16215     {
16216     case al_reg:
16217     case eAX_reg:
16218     case indir_dx_reg:
16219       OP_IMREG (bytemode, sizeflag);
16220       break;
16221     case eDI_reg:
16222       OP_ESreg (bytemode, sizeflag);
16223       break;
16224     case eSI_reg:
16225       OP_DSreg (bytemode, sizeflag);
16226       break;
16227     default:
16228       abort ();
16229       break;
16230     }
16231 }
16232
16233 static void
16234 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16235 {
16236   if ( isa64 != amd64 )
16237     return;
16238
16239   obufp = obuf;
16240   BadOp ();
16241   mnemonicendp = obufp;
16242   ++codep;
16243 }
16244
16245 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16246    "bnd".  */
16247
16248 static void
16249 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16250 {
16251   if (prefixes & PREFIX_REPNZ)
16252     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16253 }
16254
16255 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16256    "notrack".  */
16257
16258 static void
16259 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16260                int sizeflag ATTRIBUTE_UNUSED)
16261 {
16262   if (active_seg_prefix == PREFIX_DS
16263       && (address_mode != mode_64bit || last_data_prefix < 0))
16264     {
16265       /* NOTRACK prefix is only valid on indirect branch instructions.
16266          NB: DATA prefix is unsupported for Intel64.  */
16267       active_seg_prefix = 0;
16268       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16269     }
16270 }
16271
16272 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16273    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16274  */
16275
16276 static void
16277 HLE_Fixup1 (int bytemode, int sizeflag)
16278 {
16279   if (modrm.mod != 3
16280       && (prefixes & PREFIX_LOCK) != 0)
16281     {
16282       if (prefixes & PREFIX_REPZ)
16283         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16284       if (prefixes & PREFIX_REPNZ)
16285         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16286     }
16287
16288   OP_E (bytemode, sizeflag);
16289 }
16290
16291 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16292    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16293  */
16294
16295 static void
16296 HLE_Fixup2 (int bytemode, int sizeflag)
16297 {
16298   if (modrm.mod != 3)
16299     {
16300       if (prefixes & PREFIX_REPZ)
16301         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16302       if (prefixes & PREFIX_REPNZ)
16303         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16304     }
16305
16306   OP_E (bytemode, sizeflag);
16307 }
16308
16309 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16310    "xrelease" for memory operand.  No check for LOCK prefix.   */
16311
16312 static void
16313 HLE_Fixup3 (int bytemode, int sizeflag)
16314 {
16315   if (modrm.mod != 3
16316       && last_repz_prefix > last_repnz_prefix
16317       && (prefixes & PREFIX_REPZ) != 0)
16318     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16319
16320   OP_E (bytemode, sizeflag);
16321 }
16322
16323 static void
16324 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16325 {
16326   USED_REX (REX_W);
16327   if (rex & REX_W)
16328     {
16329       /* Change cmpxchg8b to cmpxchg16b.  */
16330       char *p = mnemonicendp - 2;
16331       mnemonicendp = stpcpy (p, "16b");
16332       bytemode = o_mode;
16333     }
16334   else if ((prefixes & PREFIX_LOCK) != 0)
16335     {
16336       if (prefixes & PREFIX_REPZ)
16337         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16338       if (prefixes & PREFIX_REPNZ)
16339         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16340     }
16341
16342   OP_M (bytemode, sizeflag);
16343 }
16344
16345 static void
16346 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16347 {
16348   const char **names;
16349
16350   if (need_vex)
16351     {
16352       switch (vex.length)
16353         {
16354         case 128:
16355           names = names_xmm;
16356           break;
16357         case 256:
16358           names = names_ymm;
16359           break;
16360         default:
16361           abort ();
16362         }
16363     }
16364   else
16365     names = names_xmm;
16366   oappend (names[reg]);
16367 }
16368
16369 static void
16370 CRC32_Fixup (int bytemode, int sizeflag)
16371 {
16372   /* Add proper suffix to "crc32".  */
16373   char *p = mnemonicendp;
16374
16375   switch (bytemode)
16376     {
16377     case b_mode:
16378       if (intel_syntax)
16379         goto skip;
16380
16381       *p++ = 'b';
16382       break;
16383     case v_mode:
16384       if (intel_syntax)
16385         goto skip;
16386
16387       USED_REX (REX_W);
16388       if (rex & REX_W)
16389         *p++ = 'q';
16390       else
16391         {
16392           if (sizeflag & DFLAG)
16393             *p++ = 'l';
16394           else
16395             *p++ = 'w';
16396           used_prefixes |= (prefixes & PREFIX_DATA);
16397         }
16398       break;
16399     default:
16400       oappend (INTERNAL_DISASSEMBLER_ERROR);
16401       break;
16402     }
16403   mnemonicendp = p;
16404   *p = '\0';
16405
16406  skip:
16407   if (modrm.mod == 3)
16408     {
16409       int add;
16410
16411       /* Skip mod/rm byte.  */
16412       MODRM_CHECK;
16413       codep++;
16414
16415       USED_REX (REX_B);
16416       add = (rex & REX_B) ? 8 : 0;
16417       if (bytemode == b_mode)
16418         {
16419           USED_REX (0);
16420           if (rex)
16421             oappend (names8rex[modrm.rm + add]);
16422           else
16423             oappend (names8[modrm.rm + add]);
16424         }
16425       else
16426         {
16427           USED_REX (REX_W);
16428           if (rex & REX_W)
16429             oappend (names64[modrm.rm + add]);
16430           else if ((prefixes & PREFIX_DATA))
16431             oappend (names16[modrm.rm + add]);
16432           else
16433             oappend (names32[modrm.rm + add]);
16434         }
16435     }
16436   else
16437     OP_E (bytemode, sizeflag);
16438 }
16439
16440 static void
16441 FXSAVE_Fixup (int bytemode, int sizeflag)
16442 {
16443   /* Add proper suffix to "fxsave" and "fxrstor".  */
16444   USED_REX (REX_W);
16445   if (rex & REX_W)
16446     {
16447       char *p = mnemonicendp;
16448       *p++ = '6';
16449       *p++ = '4';
16450       *p = '\0';
16451       mnemonicendp = p;
16452     }
16453   OP_M (bytemode, sizeflag);
16454 }
16455
16456 static void
16457 PCMPESTR_Fixup (int bytemode, int sizeflag)
16458 {
16459   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
16460   if (!intel_syntax)
16461     {
16462       char *p = mnemonicendp;
16463
16464       USED_REX (REX_W);
16465       if (rex & REX_W)
16466         *p++ = 'q';
16467       else if (sizeflag & SUFFIX_ALWAYS)
16468         *p++ = 'l';
16469
16470       *p = '\0';
16471       mnemonicendp = p;
16472     }
16473
16474   OP_EX (bytemode, sizeflag);
16475 }
16476
16477 /* Display the destination register operand for instructions with
16478    VEX. */
16479
16480 static void
16481 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16482 {
16483   int reg;
16484   const char **names;
16485
16486   if (!need_vex)
16487     abort ();
16488
16489   if (!need_vex_reg)
16490     return;
16491
16492   reg = vex.register_specifier;
16493   vex.register_specifier = 0;
16494   if (address_mode != mode_64bit)
16495     reg &= 7;
16496   else if (vex.evex && !vex.v)
16497     reg += 16;
16498
16499   if (bytemode == vex_scalar_mode)
16500     {
16501       oappend (names_xmm[reg]);
16502       return;
16503     }
16504
16505   if (bytemode == tmm_mode)
16506     {
16507       /* All 3 TMM registers must be distinct.  */
16508       if (reg >= 8)
16509         oappend ("(bad)");
16510       else
16511         {
16512           /* This must be the 3rd operand.  */
16513           if (obufp != op_out[2])
16514             abort ();
16515           oappend (names_tmm[reg]);
16516           if (reg == modrm.reg || reg == modrm.rm)
16517             strcpy (obufp, "/(bad)");
16518         }
16519
16520       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16521         {
16522           if (modrm.reg <= 8
16523               && (modrm.reg == modrm.rm || modrm.reg == reg))
16524             strcat (op_out[0], "/(bad)");
16525           if (modrm.rm <= 8
16526               && (modrm.rm == modrm.reg || modrm.rm == reg))
16527             strcat (op_out[1], "/(bad)");
16528         }
16529
16530       return;
16531     }
16532
16533   switch (vex.length)
16534     {
16535     case 128:
16536       switch (bytemode)
16537         {
16538         case vex_mode:
16539         case vex128_mode:
16540         case vex_vsib_q_w_dq_mode:
16541         case vex_vsib_q_w_d_mode:
16542           names = names_xmm;
16543           break;
16544         case dq_mode:
16545           if (rex & REX_W)
16546             names = names64;
16547           else
16548             names = names32;
16549           break;
16550         case mask_bd_mode:
16551         case mask_mode:
16552           if (reg > 0x7)
16553             {
16554               oappend ("(bad)");
16555               return;
16556             }
16557           names = names_mask;
16558           break;
16559         default:
16560           abort ();
16561           return;
16562         }
16563       break;
16564     case 256:
16565       switch (bytemode)
16566         {
16567         case vex_mode:
16568         case vex256_mode:
16569           names = names_ymm;
16570           break;
16571         case vex_vsib_q_w_dq_mode:
16572         case vex_vsib_q_w_d_mode:
16573           names = vex.w ? names_ymm : names_xmm;
16574           break;
16575         case mask_bd_mode:
16576         case mask_mode:
16577           if (reg > 0x7)
16578             {
16579               oappend ("(bad)");
16580               return;
16581             }
16582           names = names_mask;
16583           break;
16584         default:
16585           /* See PR binutils/20893 for a reproducer.  */
16586           oappend ("(bad)");
16587           return;
16588         }
16589       break;
16590     case 512:
16591       names = names_zmm;
16592       break;
16593     default:
16594       abort ();
16595       break;
16596     }
16597   oappend (names[reg]);
16598 }
16599
16600 static void
16601 OP_VexW (int bytemode, int sizeflag)
16602 {
16603   OP_VEX (bytemode, sizeflag);
16604
16605   if (vex.w)
16606     {
16607       /* Swap 2nd and 3rd operands.  */
16608       strcpy (scratchbuf, op_out[2]);
16609       strcpy (op_out[2], op_out[1]);
16610       strcpy (op_out[1], scratchbuf);
16611     }
16612 }
16613
16614 static void
16615 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16616 {
16617   int reg;
16618   const char **names = names_xmm;
16619
16620   FETCH_DATA (the_info, codep + 1);
16621   reg = *codep++;
16622
16623   if (bytemode != x_mode && bytemode != scalar_mode)
16624     abort ();
16625
16626   reg >>= 4;
16627   if (address_mode != mode_64bit)
16628     reg &= 7;
16629
16630   if (bytemode == x_mode && vex.length == 256)
16631     names = names_ymm;
16632
16633   oappend (names[reg]);
16634
16635   if (vex.w)
16636     {
16637       /* Swap 3rd and 4th operands.  */
16638       strcpy (scratchbuf, op_out[3]);
16639       strcpy (op_out[3], op_out[2]);
16640       strcpy (op_out[2], scratchbuf);
16641     }
16642 }
16643
16644 static void
16645 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16646           int sizeflag ATTRIBUTE_UNUSED)
16647 {
16648   scratchbuf[0] = '$';
16649   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16650   oappend_maybe_intel (scratchbuf);
16651 }
16652
16653 static void
16654 OP_EX_Vex (int bytemode, int sizeflag)
16655 {
16656   if (modrm.mod != 3)
16657     need_vex_reg = 0;
16658   OP_EX (bytemode, sizeflag);
16659 }
16660
16661 static void
16662 OP_XMM_Vex (int bytemode, int sizeflag)
16663 {
16664   if (modrm.mod != 3)
16665     need_vex_reg = 0;
16666   OP_XMM (bytemode, sizeflag);
16667 }
16668
16669 static struct op vex_cmp_op[] =
16670 {
16671   { STRING_COMMA_LEN ("eq") },
16672   { STRING_COMMA_LEN ("lt") },
16673   { STRING_COMMA_LEN ("le") },
16674   { STRING_COMMA_LEN ("unord") },
16675   { STRING_COMMA_LEN ("neq") },
16676   { STRING_COMMA_LEN ("nlt") },
16677   { STRING_COMMA_LEN ("nle") },
16678   { STRING_COMMA_LEN ("ord") },
16679   { STRING_COMMA_LEN ("eq_uq") },
16680   { STRING_COMMA_LEN ("nge") },
16681   { STRING_COMMA_LEN ("ngt") },
16682   { STRING_COMMA_LEN ("false") },
16683   { STRING_COMMA_LEN ("neq_oq") },
16684   { STRING_COMMA_LEN ("ge") },
16685   { STRING_COMMA_LEN ("gt") },
16686   { STRING_COMMA_LEN ("true") },
16687   { STRING_COMMA_LEN ("eq_os") },
16688   { STRING_COMMA_LEN ("lt_oq") },
16689   { STRING_COMMA_LEN ("le_oq") },
16690   { STRING_COMMA_LEN ("unord_s") },
16691   { STRING_COMMA_LEN ("neq_us") },
16692   { STRING_COMMA_LEN ("nlt_uq") },
16693   { STRING_COMMA_LEN ("nle_uq") },
16694   { STRING_COMMA_LEN ("ord_s") },
16695   { STRING_COMMA_LEN ("eq_us") },
16696   { STRING_COMMA_LEN ("nge_uq") },
16697   { STRING_COMMA_LEN ("ngt_uq") },
16698   { STRING_COMMA_LEN ("false_os") },
16699   { STRING_COMMA_LEN ("neq_os") },
16700   { STRING_COMMA_LEN ("ge_oq") },
16701   { STRING_COMMA_LEN ("gt_oq") },
16702   { STRING_COMMA_LEN ("true_us") },
16703 };
16704
16705 static void
16706 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16707 {
16708   unsigned int cmp_type;
16709
16710   FETCH_DATA (the_info, codep + 1);
16711   cmp_type = *codep++ & 0xff;
16712   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16713     {
16714       char suffix [3];
16715       char *p = mnemonicendp - 2;
16716       suffix[0] = p[0];
16717       suffix[1] = p[1];
16718       suffix[2] = '\0';
16719       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16720       mnemonicendp += vex_cmp_op[cmp_type].len;
16721     }
16722   else
16723     {
16724       /* We have a reserved extension byte.  Output it directly.  */
16725       scratchbuf[0] = '$';
16726       print_operand_value (scratchbuf + 1, 1, cmp_type);
16727       oappend_maybe_intel (scratchbuf);
16728       scratchbuf[0] = '\0';
16729     }
16730 }
16731
16732 static void
16733 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16734              int sizeflag ATTRIBUTE_UNUSED)
16735 {
16736   unsigned int cmp_type;
16737
16738   if (!vex.evex)
16739     abort ();
16740
16741   FETCH_DATA (the_info, codep + 1);
16742   cmp_type = *codep++ & 0xff;
16743   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16744      If it's the case, print suffix, otherwise - print the immediate.  */
16745   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16746       && cmp_type != 3
16747       && cmp_type != 7)
16748     {
16749       char suffix [3];
16750       char *p = mnemonicendp - 2;
16751
16752       /* vpcmp* can have both one- and two-lettered suffix.  */
16753       if (p[0] == 'p')
16754         {
16755           p++;
16756           suffix[0] = p[0];
16757           suffix[1] = '\0';
16758         }
16759       else
16760         {
16761           suffix[0] = p[0];
16762           suffix[1] = p[1];
16763           suffix[2] = '\0';
16764         }
16765
16766       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16767       mnemonicendp += simd_cmp_op[cmp_type].len;
16768     }
16769   else
16770     {
16771       /* We have a reserved extension byte.  Output it directly.  */
16772       scratchbuf[0] = '$';
16773       print_operand_value (scratchbuf + 1, 1, cmp_type);
16774       oappend_maybe_intel (scratchbuf);
16775       scratchbuf[0] = '\0';
16776     }
16777 }
16778
16779 static const struct op xop_cmp_op[] =
16780 {
16781   { STRING_COMMA_LEN ("lt") },
16782   { STRING_COMMA_LEN ("le") },
16783   { STRING_COMMA_LEN ("gt") },
16784   { STRING_COMMA_LEN ("ge") },
16785   { STRING_COMMA_LEN ("eq") },
16786   { STRING_COMMA_LEN ("neq") },
16787   { STRING_COMMA_LEN ("false") },
16788   { STRING_COMMA_LEN ("true") }
16789 };
16790
16791 static void
16792 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16793              int sizeflag ATTRIBUTE_UNUSED)
16794 {
16795   unsigned int cmp_type;
16796
16797   FETCH_DATA (the_info, codep + 1);
16798   cmp_type = *codep++ & 0xff;
16799   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16800     {
16801       char suffix[3];
16802       char *p = mnemonicendp - 2;
16803
16804       /* vpcom* can have both one- and two-lettered suffix.  */
16805       if (p[0] == 'm')
16806         {
16807           p++;
16808           suffix[0] = p[0];
16809           suffix[1] = '\0';
16810         }
16811       else
16812         {
16813           suffix[0] = p[0];
16814           suffix[1] = p[1];
16815           suffix[2] = '\0';
16816         }
16817
16818       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16819       mnemonicendp += xop_cmp_op[cmp_type].len;
16820     }
16821   else
16822     {
16823       /* We have a reserved extension byte.  Output it directly.  */
16824       scratchbuf[0] = '$';
16825       print_operand_value (scratchbuf + 1, 1, cmp_type);
16826       oappend_maybe_intel (scratchbuf);
16827       scratchbuf[0] = '\0';
16828     }
16829 }
16830
16831 static const struct op pclmul_op[] =
16832 {
16833   { STRING_COMMA_LEN ("lql") },
16834   { STRING_COMMA_LEN ("hql") },
16835   { STRING_COMMA_LEN ("lqh") },
16836   { STRING_COMMA_LEN ("hqh") }
16837 };
16838
16839 static void
16840 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16841               int sizeflag ATTRIBUTE_UNUSED)
16842 {
16843   unsigned int pclmul_type;
16844
16845   FETCH_DATA (the_info, codep + 1);
16846   pclmul_type = *codep++ & 0xff;
16847   switch (pclmul_type)
16848     {
16849     case 0x10:
16850       pclmul_type = 2;
16851       break;
16852     case 0x11:
16853       pclmul_type = 3;
16854       break;
16855     default:
16856       break;
16857     }
16858   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16859     {
16860       char suffix [4];
16861       char *p = mnemonicendp - 3;
16862       suffix[0] = p[0];
16863       suffix[1] = p[1];
16864       suffix[2] = p[2];
16865       suffix[3] = '\0';
16866       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16867       mnemonicendp += pclmul_op[pclmul_type].len;
16868     }
16869   else
16870     {
16871       /* We have a reserved extension byte.  Output it directly.  */
16872       scratchbuf[0] = '$';
16873       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16874       oappend_maybe_intel (scratchbuf);
16875       scratchbuf[0] = '\0';
16876     }
16877 }
16878
16879 static void
16880 MOVBE_Fixup (int bytemode, int sizeflag)
16881 {
16882   /* Add proper suffix to "movbe".  */
16883   char *p = mnemonicendp;
16884
16885   switch (bytemode)
16886     {
16887     case v_mode:
16888       if (intel_syntax)
16889         goto skip;
16890
16891       USED_REX (REX_W);
16892       if (sizeflag & SUFFIX_ALWAYS)
16893         {
16894           if (rex & REX_W)
16895             *p++ = 'q';
16896           else
16897             {
16898               if (sizeflag & DFLAG)
16899                 *p++ = 'l';
16900               else
16901                 *p++ = 'w';
16902               used_prefixes |= (prefixes & PREFIX_DATA);
16903             }
16904         }
16905       break;
16906     default:
16907       oappend (INTERNAL_DISASSEMBLER_ERROR);
16908       break;
16909     }
16910   mnemonicendp = p;
16911   *p = '\0';
16912
16913  skip:
16914   OP_M (bytemode, sizeflag);
16915 }
16916
16917 static void
16918 MOVSXD_Fixup (int bytemode, int sizeflag)
16919 {
16920   /* Add proper suffix to "movsxd".  */
16921   char *p = mnemonicendp;
16922
16923   switch (bytemode)
16924     {
16925     case movsxd_mode:
16926       if (intel_syntax)
16927         {
16928           *p++ = 'x';
16929           *p++ = 'd';
16930           goto skip;
16931         }
16932
16933       USED_REX (REX_W);
16934       if (rex & REX_W)
16935         {
16936           *p++ = 'l';
16937           *p++ = 'q';
16938         }
16939       else
16940         {
16941           *p++ = 'x';
16942           *p++ = 'd';
16943         }
16944       break;
16945     default:
16946       oappend (INTERNAL_DISASSEMBLER_ERROR);
16947       break;
16948     }
16949
16950  skip:
16951   mnemonicendp = p;
16952   *p = '\0';
16953   OP_E (bytemode, sizeflag);
16954 }
16955
16956 static void
16957 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16958 {
16959   if (!vex.evex
16960       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16961     abort ();
16962
16963   USED_REX (REX_R);
16964   if ((rex & REX_R) != 0 || !vex.r)
16965     {
16966       BadOp ();
16967       return;
16968     }
16969
16970   oappend (names_mask [modrm.reg]);
16971 }
16972
16973 static void
16974 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16975 {
16976   if (modrm.mod == 3 && vex.b)
16977     switch (bytemode)
16978       {
16979       case evex_rounding_64_mode:
16980         if (address_mode != mode_64bit)
16981           {
16982             oappend ("(bad)");
16983             break;
16984           }
16985         /* Fall through.  */
16986       case evex_rounding_mode:
16987         oappend (names_rounding[vex.ll]);
16988         break;
16989       case evex_sae_mode:
16990         oappend ("{sae}");
16991         break;
16992       default:
16993         abort ();
16994         break;
16995       }
16996 }