opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_Rounding (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VEXI4_Fixup (int, int);
 101 static void VZERO_Fixup (int, int);
 102 static void VCMP_Fixup (int, int);
 103 static void VPCMP_Fixup (int, int);
 104 static void OP_0f07 (int, int);
 105 static void OP_Monitor (int, int);
 106 static void OP_Mwait (int, int);
 107 static void NOP_Fixup1 (int, int);
 108 static void NOP_Fixup2 (int, int);
 109 static void OP_3DNowSuffix (int, int);
 110 static void CMP_Fixup (int, int);
 111 static void BadOp (void);
 112 static void REP_Fixup (int, int);
 113 static void BND_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   jmp_buf bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       longjmp (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 #define XX { NULL, 0 }
 227 #define Bad_Opcode NULL, { { NULL, 0 } }
 228
 229 #define Eb { OP_E, b_mode }
 230 #define Ebnd { OP_E, bnd_mode }
 231 #define EbS { OP_E, b_swap_mode }
 232 #define Ev { OP_E, v_mode }
 233 #define Ev_bnd { OP_E, v_bnd_mode }
 234 #define EvS { OP_E, v_swap_mode }
 235 #define Ed { OP_E, d_mode }
 236 #define Edq { OP_E, dq_mode }
 237 #define Edqw { OP_E, dqw_mode }
 238 #define Edqb { OP_E, dqb_mode }
 239 #define Edqd { OP_E, dqd_mode }
 240 #define Eq { OP_E, q_mode }
 241 #define indirEv { OP_indirE, stack_v_mode }
 242 #define indirEp { OP_indirE, f_mode }
 243 #define stackEv { OP_E, stack_v_mode }
 244 #define Em { OP_E, m_mode }
 245 #define Ew { OP_E, w_mode }
 246 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 247 #define Ma { OP_M, a_mode }
 248 #define Mb { OP_M, b_mode }
 249 #define Md { OP_M, d_mode }
 250 #define Mo { OP_M, o_mode }
 251 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 252 #define Mq { OP_M, q_mode }
 253 #define Mx { OP_M, x_mode }
 254 #define Mxmm { OP_M, xmm_mode }
 255 #define Gb { OP_G, b_mode }
 256 #define Gbnd { OP_G, bnd_mode }
 257 #define Gv { OP_G, v_mode }
 258 #define Gd { OP_G, d_mode }
 259 #define Gdq { OP_G, dq_mode }
 260 #define Gm { OP_G, m_mode }
 261 #define Gw { OP_G, w_mode }
 262 #define Rd { OP_R, d_mode }
 263 #define Rdq { OP_R, dq_mode }
 264 #define Rm { OP_R, m_mode }
 265 #define Ib { OP_I, b_mode }
 266 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 268 #define Iv { OP_I, v_mode }
 269 #define sIv { OP_sI, v_mode }
 270 #define Iq { OP_I, q_mode }
 271 #define Iv64 { OP_I64, v_mode }
 272 #define Iw { OP_I, w_mode }
 273 #define I1 { OP_I, const_1_mode }
 274 #define Jb { OP_J, b_mode }
 275 #define Jv { OP_J, v_mode }
 276 #define Cm { OP_C, m_mode }
 277 #define Dm { OP_D, m_mode }
 278 #define Td { OP_T, d_mode }
 279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 280
 281 #define RMeAX { OP_REG, eAX_reg }
 282 #define RMeBX { OP_REG, eBX_reg }
 283 #define RMeCX { OP_REG, eCX_reg }
 284 #define RMeDX { OP_REG, eDX_reg }
 285 #define RMeSP { OP_REG, eSP_reg }
 286 #define RMeBP { OP_REG, eBP_reg }
 287 #define RMeSI { OP_REG, eSI_reg }
 288 #define RMeDI { OP_REG, eDI_reg }
 289 #define RMrAX { OP_REG, rAX_reg }
 290 #define RMrBX { OP_REG, rBX_reg }
 291 #define RMrCX { OP_REG, rCX_reg }
 292 #define RMrDX { OP_REG, rDX_reg }
 293 #define RMrSP { OP_REG, rSP_reg }
 294 #define RMrBP { OP_REG, rBP_reg }
 295 #define RMrSI { OP_REG, rSI_reg }
 296 #define RMrDI { OP_REG, rDI_reg }
 297 #define RMAL { OP_REG, al_reg }
 298 #define RMCL { OP_REG, cl_reg }
 299 #define RMDL { OP_REG, dl_reg }
 300 #define RMBL { OP_REG, bl_reg }
 301 #define RMAH { OP_REG, ah_reg }
 302 #define RMCH { OP_REG, ch_reg }
 303 #define RMDH { OP_REG, dh_reg }
 304 #define RMBH { OP_REG, bh_reg }
 305 #define RMAX { OP_REG, ax_reg }
 306 #define RMDX { OP_REG, dx_reg }
 307
 308 #define eAX { OP_IMREG, eAX_reg }
 309 #define eBX { OP_IMREG, eBX_reg }
 310 #define eCX { OP_IMREG, eCX_reg }
 311 #define eDX { OP_IMREG, eDX_reg }
 312 #define eSP { OP_IMREG, eSP_reg }
 313 #define eBP { OP_IMREG, eBP_reg }
 314 #define eSI { OP_IMREG, eSI_reg }
 315 #define eDI { OP_IMREG, eDI_reg }
 316 #define AL { OP_IMREG, al_reg }
 317 #define CL { OP_IMREG, cl_reg }
 318 #define DL { OP_IMREG, dl_reg }
 319 #define BL { OP_IMREG, bl_reg }
 320 #define AH { OP_IMREG, ah_reg }
 321 #define CH { OP_IMREG, ch_reg }
 322 #define DH { OP_IMREG, dh_reg }
 323 #define BH { OP_IMREG, bh_reg }
 324 #define AX { OP_IMREG, ax_reg }
 325 #define DX { OP_IMREG, dx_reg }
 326 #define zAX { OP_IMREG, z_mode_ax_reg }
 327 #define indirDX { OP_IMREG, indir_dx_reg }
 328
 329 #define Sw { OP_SEG, w_mode }
 330 #define Sv { OP_SEG, v_mode }
 331 #define Ap { OP_DIR, 0 }
 332 #define Ob { OP_OFF64, b_mode }
 333 #define Ov { OP_OFF64, v_mode }
 334 #define Xb { OP_DSreg, eSI_reg }
 335 #define Xv { OP_DSreg, eSI_reg }
 336 #define Xz { OP_DSreg, eSI_reg }
 337 #define Yb { OP_ESreg, eDI_reg }
 338 #define Yv { OP_ESreg, eDI_reg }
 339 #define DSBX { OP_DSreg, eBX_reg }
 340
 341 #define es { OP_REG, es_reg }
 342 #define ss { OP_REG, ss_reg }
 343 #define cs { OP_REG, cs_reg }
 344 #define ds { OP_REG, ds_reg }
 345 #define fs { OP_REG, fs_reg }
 346 #define gs { OP_REG, gs_reg }
 347
 348 #define MX { OP_MMX, 0 }
 349 #define XM { OP_XMM, 0 }
 350 #define XMScalar { OP_XMM, scalar_mode }
 351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define XMxmmq { OP_XMM, xmmq_mode }
 354 #define EM { OP_EM, v_mode }
 355 #define EMS { OP_EM, v_swap_mode }
 356 #define EMd { OP_EM, d_mode }
 357 #define EMx { OP_EM, x_mode }
 358 #define EXw { OP_EX, w_mode }
 359 #define EXd { OP_EX, d_mode }
 360 #define EXdScalar { OP_EX, d_scalar_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 363 #define EXq { OP_EX, q_mode }
 364 #define EXqScalar { OP_EX, q_scalar_mode }
 365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 385 #define MS { OP_MS, v_mode }
 386 #define XS { OP_XS, v_mode }
 387 #define EMCq { OP_EMC, q_mode }
 388 #define MXC { OP_MXC, 0 }
 389 #define OPSUF { OP_3DNowSuffix, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 395
 396 #define Vex { OP_VEX, vex_mode }
 397 #define VexScalar { OP_VEX, vex_scalar_mode }
 398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 399 #define Vex128 { OP_VEX, vex128_mode }
 400 #define Vex256 { OP_VEX, vex256_mode }
 401 #define VexGdq { OP_VEX, dq_mode }
 402 #define VexI4 { VEXI4_Fixup, 0}
 403 #define EXdVex { OP_EX_Vex, d_mode }
 404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 406 #define EXqVex { OP_EX_Vex, q_mode }
 407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 409 #define EXVexW { OP_EX_VexW, x_mode }
 410 #define EXdVexW { OP_EX_VexW, d_mode }
 411 #define EXqVexW { OP_EX_VexW, q_mode }
 412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 413 #define XMVex { OP_XMM_Vex, 0 }
 414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 415 #define XMVexW { OP_XMM_VexW, 0 }
 416 #define XMVexI4 { OP_REG_VexI4, x_mode }
 417 #define PCLMUL { PCLMUL_Fixup, 0 }
 418 #define VZERO { VZERO_Fixup, 0 }
 419 #define VCMP { VCMP_Fixup, 0 }
 420 #define VPCMP { VPCMP_Fixup, 0 }
 421
 422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 424
 425 #define XMask { OP_Mask, mask_mode }
 426 #define MaskG { OP_G, mask_mode }
 427 #define MaskE { OP_E, mask_mode }
 428 #define MaskR { OP_R, mask_mode }
 429 #define MaskVex { OP_VEX, mask_mode }
 430
 431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 562   vex_vsib_q_w_dq_mode,
 563
 564   /* scalar, ignore vector length.  */
 565   scalar_mode,
 566   /* like d_mode, ignore vector length.  */
 567   d_scalar_mode,
 568   /* like d_swap_mode, ignore vector length.  */
 569   d_scalar_swap_mode,
 570   /* like q_mode, ignore vector length.  */
 571   q_scalar_mode,
 572   /* like q_swap_mode, ignore vector length.  */
 573   q_scalar_swap_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* like vex_w_dq_mode, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Supress all exceptions.  */
 582   evex_sae_mode,
 583
 584   /* Mask register operand.  */
 585   mask_mode,
 586
 587   es_reg,
 588   cs_reg,
 589   ss_reg,
 590   ds_reg,
 591   fs_reg,
 592   gs_reg,
 593
 594   eAX_reg,
 595   eCX_reg,
 596   eDX_reg,
 597   eBX_reg,
 598   eSP_reg,
 599   eBP_reg,
 600   eSI_reg,
 601   eDI_reg,
 602
 603   al_reg,
 604   cl_reg,
 605   dl_reg,
 606   bl_reg,
 607   ah_reg,
 608   ch_reg,
 609   dh_reg,
 610   bh_reg,
 611
 612   ax_reg,
 613   cx_reg,
 614   dx_reg,
 615   bx_reg,
 616   sp_reg,
 617   bp_reg,
 618   si_reg,
 619   di_reg,
 620
 621   rAX_reg,
 622   rCX_reg,
 623   rDX_reg,
 624   rBX_reg,
 625   rSP_reg,
 626   rBP_reg,
 627   rSI_reg,
 628   rDI_reg,
 629
 630   z_mode_ax_reg,
 631   indir_dx_reg
 632 };
 633
 634 enum
 635 {
 636   FLOATCODE = 1,
 637   USE_REG_TABLE,
 638   USE_MOD_TABLE,
 639   USE_RM_TABLE,
 640   USE_PREFIX_TABLE,
 641   USE_X86_64_TABLE,
 642   USE_3BYTE_TABLE,
 643   USE_XOP_8F_TABLE,
 644   USE_VEX_C4_TABLE,
 645   USE_VEX_C5_TABLE,
 646   USE_VEX_LEN_TABLE,
 647   USE_VEX_W_TABLE,
 648   USE_EVEX_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 654 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 655 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 656 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 657 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 658 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 659 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 660 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 661 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 662 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 663 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 664 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 665 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 666
 667 enum
 668 {
 669   REG_80 = 0,
 670   REG_81,
 671   REG_82,
 672   REG_8F,
 673   REG_C0,
 674   REG_C1,
 675   REG_C6,
 676   REG_C7,
 677   REG_D0,
 678   REG_D1,
 679   REG_D2,
 680   REG_D3,
 681   REG_F6,
 682   REG_F7,
 683   REG_FE,
 684   REG_FF,
 685   REG_0F00,
 686   REG_0F01,
 687   REG_0F0D,
 688   REG_0F18,
 689   REG_0F71,
 690   REG_0F72,
 691   REG_0F73,
 692   REG_0FA6,
 693   REG_0FA7,
 694   REG_0FAE,
 695   REG_0FBA,
 696   REG_0FC7,
 697   REG_VEX_0F71,
 698   REG_VEX_0F72,
 699   REG_VEX_0F73,
 700   REG_VEX_0FAE,
 701   REG_VEX_0F38F3,
 702   REG_XOP_LWPCB,
 703   REG_XOP_LWP,
 704   REG_XOP_TBM_01,
 705   REG_XOP_TBM_02,
 706
 707   REG_EVEX_0F72,
 708   REG_EVEX_0F73,
 709   REG_EVEX_0F38C6,
 710   REG_EVEX_0F38C7
 711 };
 712
 713 enum
 714 {
 715   MOD_8D = 0,
 716   MOD_C6_REG_7,
 717   MOD_C7_REG_7,
 718   MOD_FF_REG_3,
 719   MOD_FF_REG_5,
 720   MOD_0F01_REG_0,
 721   MOD_0F01_REG_1,
 722   MOD_0F01_REG_2,
 723   MOD_0F01_REG_3,
 724   MOD_0F01_REG_7,
 725   MOD_0F12_PREFIX_0,
 726   MOD_0F13,
 727   MOD_0F16_PREFIX_0,
 728   MOD_0F17,
 729   MOD_0F18_REG_0,
 730   MOD_0F18_REG_1,
 731   MOD_0F18_REG_2,
 732   MOD_0F18_REG_3,
 733   MOD_0F18_REG_4,
 734   MOD_0F18_REG_5,
 735   MOD_0F18_REG_6,
 736   MOD_0F18_REG_7,
 737   MOD_0F1A_PREFIX_0,
 738   MOD_0F1B_PREFIX_0,
 739   MOD_0F1B_PREFIX_1,
 740   MOD_0F20,
 741   MOD_0F21,
 742   MOD_0F22,
 743   MOD_0F23,
 744   MOD_0F24,
 745   MOD_0F26,
 746   MOD_0F2B_PREFIX_0,
 747   MOD_0F2B_PREFIX_1,
 748   MOD_0F2B_PREFIX_2,
 749   MOD_0F2B_PREFIX_3,
 750   MOD_0F51,
 751   MOD_0F71_REG_2,
 752   MOD_0F71_REG_4,
 753   MOD_0F71_REG_6,
 754   MOD_0F72_REG_2,
 755   MOD_0F72_REG_4,
 756   MOD_0F72_REG_6,
 757   MOD_0F73_REG_2,
 758   MOD_0F73_REG_3,
 759   MOD_0F73_REG_6,
 760   MOD_0F73_REG_7,
 761   MOD_0FAE_REG_0,
 762   MOD_0FAE_REG_1,
 763   MOD_0FAE_REG_2,
 764   MOD_0FAE_REG_3,
 765   MOD_0FAE_REG_4,
 766   MOD_0FAE_REG_5,
 767   MOD_0FAE_REG_6,
 768   MOD_0FAE_REG_7,
 769   MOD_0FB2,
 770   MOD_0FB4,
 771   MOD_0FB5,
 772   MOD_0FC7_REG_6,
 773   MOD_0FC7_REG_7,
 774   MOD_0FD7,
 775   MOD_0FE7_PREFIX_2,
 776   MOD_0FF0_PREFIX_3,
 777   MOD_0F382A_PREFIX_2,
 778   MOD_62_32BIT,
 779   MOD_C4_32BIT,
 780   MOD_C5_32BIT,
 781   MOD_VEX_0F12_PREFIX_0,
 782   MOD_VEX_0F13,
 783   MOD_VEX_0F16_PREFIX_0,
 784   MOD_VEX_0F17,
 785   MOD_VEX_0F2B,
 786   MOD_VEX_0F50,
 787   MOD_VEX_0F71_REG_2,
 788   MOD_VEX_0F71_REG_4,
 789   MOD_VEX_0F71_REG_6,
 790   MOD_VEX_0F72_REG_2,
 791   MOD_VEX_0F72_REG_4,
 792   MOD_VEX_0F72_REG_6,
 793   MOD_VEX_0F73_REG_2,
 794   MOD_VEX_0F73_REG_3,
 795   MOD_VEX_0F73_REG_6,
 796   MOD_VEX_0F73_REG_7,
 797   MOD_VEX_0FAE_REG_2,
 798   MOD_VEX_0FAE_REG_3,
 799   MOD_VEX_0FD7_PREFIX_2,
 800   MOD_VEX_0FE7_PREFIX_2,
 801   MOD_VEX_0FF0_PREFIX_3,
 802   MOD_VEX_0F381A_PREFIX_2,
 803   MOD_VEX_0F382A_PREFIX_2,
 804   MOD_VEX_0F382C_PREFIX_2,
 805   MOD_VEX_0F382D_PREFIX_2,
 806   MOD_VEX_0F382E_PREFIX_2,
 807   MOD_VEX_0F382F_PREFIX_2,
 808   MOD_VEX_0F385A_PREFIX_2,
 809   MOD_VEX_0F388C_PREFIX_2,
 810   MOD_VEX_0F388E_PREFIX_2,
 811
 812   MOD_EVEX_0F10_PREFIX_1,
 813   MOD_EVEX_0F10_PREFIX_3,
 814   MOD_EVEX_0F11_PREFIX_1,
 815   MOD_EVEX_0F11_PREFIX_3,
 816   MOD_EVEX_0F12_PREFIX_0,
 817   MOD_EVEX_0F16_PREFIX_0,
 818   MOD_EVEX_0F38C6_REG_1,
 819   MOD_EVEX_0F38C6_REG_2,
 820   MOD_EVEX_0F38C6_REG_5,
 821   MOD_EVEX_0F38C6_REG_6,
 822   MOD_EVEX_0F38C7_REG_1,
 823   MOD_EVEX_0F38C7_REG_2,
 824   MOD_EVEX_0F38C7_REG_5,
 825   MOD_EVEX_0F38C7_REG_6
 826 };
 827
 828 enum
 829 {
 830   RM_C6_REG_7 = 0,
 831   RM_C7_REG_7,
 832   RM_0F01_REG_0,
 833   RM_0F01_REG_1,
 834   RM_0F01_REG_2,
 835   RM_0F01_REG_3,
 836   RM_0F01_REG_7,
 837   RM_0FAE_REG_5,
 838   RM_0FAE_REG_6,
 839   RM_0FAE_REG_7
 840 };
 841
 842 enum
 843 {
 844   PREFIX_90 = 0,
 845   PREFIX_0F10,
 846   PREFIX_0F11,
 847   PREFIX_0F12,
 848   PREFIX_0F16,
 849   PREFIX_0F1A,
 850   PREFIX_0F1B,
 851   PREFIX_0F2A,
 852   PREFIX_0F2B,
 853   PREFIX_0F2C,
 854   PREFIX_0F2D,
 855   PREFIX_0F2E,
 856   PREFIX_0F2F,
 857   PREFIX_0F51,
 858   PREFIX_0F52,
 859   PREFIX_0F53,
 860   PREFIX_0F58,
 861   PREFIX_0F59,
 862   PREFIX_0F5A,
 863   PREFIX_0F5B,
 864   PREFIX_0F5C,
 865   PREFIX_0F5D,
 866   PREFIX_0F5E,
 867   PREFIX_0F5F,
 868   PREFIX_0F60,
 869   PREFIX_0F61,
 870   PREFIX_0F62,
 871   PREFIX_0F6C,
 872   PREFIX_0F6D,
 873   PREFIX_0F6F,
 874   PREFIX_0F70,
 875   PREFIX_0F73_REG_3,
 876   PREFIX_0F73_REG_7,
 877   PREFIX_0F78,
 878   PREFIX_0F79,
 879   PREFIX_0F7C,
 880   PREFIX_0F7D,
 881   PREFIX_0F7E,
 882   PREFIX_0F7F,
 883   PREFIX_0FAE_REG_0,
 884   PREFIX_0FAE_REG_1,
 885   PREFIX_0FAE_REG_2,
 886   PREFIX_0FAE_REG_3,
 887   PREFIX_0FB8,
 888   PREFIX_0FBC,
 889   PREFIX_0FBD,
 890   PREFIX_0FC2,
 891   PREFIX_0FC3,
 892   PREFIX_0FC7_REG_6,
 893   PREFIX_0FD0,
 894   PREFIX_0FD6,
 895   PREFIX_0FE6,
 896   PREFIX_0FE7,
 897   PREFIX_0FF0,
 898   PREFIX_0FF7,
 899   PREFIX_0F3810,
 900   PREFIX_0F3814,
 901   PREFIX_0F3815,
 902   PREFIX_0F3817,
 903   PREFIX_0F3820,
 904   PREFIX_0F3821,
 905   PREFIX_0F3822,
 906   PREFIX_0F3823,
 907   PREFIX_0F3824,
 908   PREFIX_0F3825,
 909   PREFIX_0F3828,
 910   PREFIX_0F3829,
 911   PREFIX_0F382A,
 912   PREFIX_0F382B,
 913   PREFIX_0F3830,
 914   PREFIX_0F3831,
 915   PREFIX_0F3832,
 916   PREFIX_0F3833,
 917   PREFIX_0F3834,
 918   PREFIX_0F3835,
 919   PREFIX_0F3837,
 920   PREFIX_0F3838,
 921   PREFIX_0F3839,
 922   PREFIX_0F383A,
 923   PREFIX_0F383B,
 924   PREFIX_0F383C,
 925   PREFIX_0F383D,
 926   PREFIX_0F383E,
 927   PREFIX_0F383F,
 928   PREFIX_0F3840,
 929   PREFIX_0F3841,
 930   PREFIX_0F3880,
 931   PREFIX_0F3881,
 932   PREFIX_0F3882,
 933   PREFIX_0F38C8,
 934   PREFIX_0F38C9,
 935   PREFIX_0F38CA,
 936   PREFIX_0F38CB,
 937   PREFIX_0F38CC,
 938   PREFIX_0F38CD,
 939   PREFIX_0F38DB,
 940   PREFIX_0F38DC,
 941   PREFIX_0F38DD,
 942   PREFIX_0F38DE,
 943   PREFIX_0F38DF,
 944   PREFIX_0F38F0,
 945   PREFIX_0F38F1,
 946   PREFIX_0F38F6,
 947   PREFIX_0F3A08,
 948   PREFIX_0F3A09,
 949   PREFIX_0F3A0A,
 950   PREFIX_0F3A0B,
 951   PREFIX_0F3A0C,
 952   PREFIX_0F3A0D,
 953   PREFIX_0F3A0E,
 954   PREFIX_0F3A14,
 955   PREFIX_0F3A15,
 956   PREFIX_0F3A16,
 957   PREFIX_0F3A17,
 958   PREFIX_0F3A20,
 959   PREFIX_0F3A21,
 960   PREFIX_0F3A22,
 961   PREFIX_0F3A40,
 962   PREFIX_0F3A41,
 963   PREFIX_0F3A42,
 964   PREFIX_0F3A44,
 965   PREFIX_0F3A60,
 966   PREFIX_0F3A61,
 967   PREFIX_0F3A62,
 968   PREFIX_0F3A63,
 969   PREFIX_0F3ACC,
 970   PREFIX_0F3ADF,
 971   PREFIX_VEX_0F10,
 972   PREFIX_VEX_0F11,
 973   PREFIX_VEX_0F12,
 974   PREFIX_VEX_0F16,
 975   PREFIX_VEX_0F2A,
 976   PREFIX_VEX_0F2C,
 977   PREFIX_VEX_0F2D,
 978   PREFIX_VEX_0F2E,
 979   PREFIX_VEX_0F2F,
 980   PREFIX_VEX_0F41,
 981   PREFIX_VEX_0F42,
 982   PREFIX_VEX_0F44,
 983   PREFIX_VEX_0F45,
 984   PREFIX_VEX_0F46,
 985   PREFIX_VEX_0F47,
 986   PREFIX_VEX_0F4B,
 987   PREFIX_VEX_0F51,
 988   PREFIX_VEX_0F52,
 989   PREFIX_VEX_0F53,
 990   PREFIX_VEX_0F58,
 991   PREFIX_VEX_0F59,
 992   PREFIX_VEX_0F5A,
 993   PREFIX_VEX_0F5B,
 994   PREFIX_VEX_0F5C,
 995   PREFIX_VEX_0F5D,
 996   PREFIX_VEX_0F5E,
 997   PREFIX_VEX_0F5F,
 998   PREFIX_VEX_0F60,
 999   PREFIX_VEX_0F61,
1000   PREFIX_VEX_0F62,
1001   PREFIX_VEX_0F63,
1002   PREFIX_VEX_0F64,
1003   PREFIX_VEX_0F65,
1004   PREFIX_VEX_0F66,
1005   PREFIX_VEX_0F67,
1006   PREFIX_VEX_0F68,
1007   PREFIX_VEX_0F69,
1008   PREFIX_VEX_0F6A,
1009   PREFIX_VEX_0F6B,
1010   PREFIX_VEX_0F6C,
1011   PREFIX_VEX_0F6D,
1012   PREFIX_VEX_0F6E,
1013   PREFIX_VEX_0F6F,
1014   PREFIX_VEX_0F70,
1015   PREFIX_VEX_0F71_REG_2,
1016   PREFIX_VEX_0F71_REG_4,
1017   PREFIX_VEX_0F71_REG_6,
1018   PREFIX_VEX_0F72_REG_2,
1019   PREFIX_VEX_0F72_REG_4,
1020   PREFIX_VEX_0F72_REG_6,
1021   PREFIX_VEX_0F73_REG_2,
1022   PREFIX_VEX_0F73_REG_3,
1023   PREFIX_VEX_0F73_REG_6,
1024   PREFIX_VEX_0F73_REG_7,
1025   PREFIX_VEX_0F74,
1026   PREFIX_VEX_0F75,
1027   PREFIX_VEX_0F76,
1028   PREFIX_VEX_0F77,
1029   PREFIX_VEX_0F7C,
1030   PREFIX_VEX_0F7D,
1031   PREFIX_VEX_0F7E,
1032   PREFIX_VEX_0F7F,
1033   PREFIX_VEX_0F90,
1034   PREFIX_VEX_0F91,
1035   PREFIX_VEX_0F92,
1036   PREFIX_VEX_0F93,
1037   PREFIX_VEX_0F98,
1038   PREFIX_VEX_0FC2,
1039   PREFIX_VEX_0FC4,
1040   PREFIX_VEX_0FC5,
1041   PREFIX_VEX_0FD0,
1042   PREFIX_VEX_0FD1,
1043   PREFIX_VEX_0FD2,
1044   PREFIX_VEX_0FD3,
1045   PREFIX_VEX_0FD4,
1046   PREFIX_VEX_0FD5,
1047   PREFIX_VEX_0FD6,
1048   PREFIX_VEX_0FD7,
1049   PREFIX_VEX_0FD8,
1050   PREFIX_VEX_0FD9,
1051   PREFIX_VEX_0FDA,
1052   PREFIX_VEX_0FDB,
1053   PREFIX_VEX_0FDC,
1054   PREFIX_VEX_0FDD,
1055   PREFIX_VEX_0FDE,
1056   PREFIX_VEX_0FDF,
1057   PREFIX_VEX_0FE0,
1058   PREFIX_VEX_0FE1,
1059   PREFIX_VEX_0FE2,
1060   PREFIX_VEX_0FE3,
1061   PREFIX_VEX_0FE4,
1062   PREFIX_VEX_0FE5,
1063   PREFIX_VEX_0FE6,
1064   PREFIX_VEX_0FE7,
1065   PREFIX_VEX_0FE8,
1066   PREFIX_VEX_0FE9,
1067   PREFIX_VEX_0FEA,
1068   PREFIX_VEX_0FEB,
1069   PREFIX_VEX_0FEC,
1070   PREFIX_VEX_0FED,
1071   PREFIX_VEX_0FEE,
1072   PREFIX_VEX_0FEF,
1073   PREFIX_VEX_0FF0,
1074   PREFIX_VEX_0FF1,
1075   PREFIX_VEX_0FF2,
1076   PREFIX_VEX_0FF3,
1077   PREFIX_VEX_0FF4,
1078   PREFIX_VEX_0FF5,
1079   PREFIX_VEX_0FF6,
1080   PREFIX_VEX_0FF7,
1081   PREFIX_VEX_0FF8,
1082   PREFIX_VEX_0FF9,
1083   PREFIX_VEX_0FFA,
1084   PREFIX_VEX_0FFB,
1085   PREFIX_VEX_0FFC,
1086   PREFIX_VEX_0FFD,
1087   PREFIX_VEX_0FFE,
1088   PREFIX_VEX_0F3800,
1089   PREFIX_VEX_0F3801,
1090   PREFIX_VEX_0F3802,
1091   PREFIX_VEX_0F3803,
1092   PREFIX_VEX_0F3804,
1093   PREFIX_VEX_0F3805,
1094   PREFIX_VEX_0F3806,
1095   PREFIX_VEX_0F3807,
1096   PREFIX_VEX_0F3808,
1097   PREFIX_VEX_0F3809,
1098   PREFIX_VEX_0F380A,
1099   PREFIX_VEX_0F380B,
1100   PREFIX_VEX_0F380C,
1101   PREFIX_VEX_0F380D,
1102   PREFIX_VEX_0F380E,
1103   PREFIX_VEX_0F380F,
1104   PREFIX_VEX_0F3813,
1105   PREFIX_VEX_0F3816,
1106   PREFIX_VEX_0F3817,
1107   PREFIX_VEX_0F3818,
1108   PREFIX_VEX_0F3819,
1109   PREFIX_VEX_0F381A,
1110   PREFIX_VEX_0F381C,
1111   PREFIX_VEX_0F381D,
1112   PREFIX_VEX_0F381E,
1113   PREFIX_VEX_0F3820,
1114   PREFIX_VEX_0F3821,
1115   PREFIX_VEX_0F3822,
1116   PREFIX_VEX_0F3823,
1117   PREFIX_VEX_0F3824,
1118   PREFIX_VEX_0F3825,
1119   PREFIX_VEX_0F3828,
1120   PREFIX_VEX_0F3829,
1121   PREFIX_VEX_0F382A,
1122   PREFIX_VEX_0F382B,
1123   PREFIX_VEX_0F382C,
1124   PREFIX_VEX_0F382D,
1125   PREFIX_VEX_0F382E,
1126   PREFIX_VEX_0F382F,
1127   PREFIX_VEX_0F3830,
1128   PREFIX_VEX_0F3831,
1129   PREFIX_VEX_0F3832,
1130   PREFIX_VEX_0F3833,
1131   PREFIX_VEX_0F3834,
1132   PREFIX_VEX_0F3835,
1133   PREFIX_VEX_0F3836,
1134   PREFIX_VEX_0F3837,
1135   PREFIX_VEX_0F3838,
1136   PREFIX_VEX_0F3839,
1137   PREFIX_VEX_0F383A,
1138   PREFIX_VEX_0F383B,
1139   PREFIX_VEX_0F383C,
1140   PREFIX_VEX_0F383D,
1141   PREFIX_VEX_0F383E,
1142   PREFIX_VEX_0F383F,
1143   PREFIX_VEX_0F3840,
1144   PREFIX_VEX_0F3841,
1145   PREFIX_VEX_0F3845,
1146   PREFIX_VEX_0F3846,
1147   PREFIX_VEX_0F3847,
1148   PREFIX_VEX_0F3858,
1149   PREFIX_VEX_0F3859,
1150   PREFIX_VEX_0F385A,
1151   PREFIX_VEX_0F3878,
1152   PREFIX_VEX_0F3879,
1153   PREFIX_VEX_0F388C,
1154   PREFIX_VEX_0F388E,
1155   PREFIX_VEX_0F3890,
1156   PREFIX_VEX_0F3891,
1157   PREFIX_VEX_0F3892,
1158   PREFIX_VEX_0F3893,
1159   PREFIX_VEX_0F3896,
1160   PREFIX_VEX_0F3897,
1161   PREFIX_VEX_0F3898,
1162   PREFIX_VEX_0F3899,
1163   PREFIX_VEX_0F389A,
1164   PREFIX_VEX_0F389B,
1165   PREFIX_VEX_0F389C,
1166   PREFIX_VEX_0F389D,
1167   PREFIX_VEX_0F389E,
1168   PREFIX_VEX_0F389F,
1169   PREFIX_VEX_0F38A6,
1170   PREFIX_VEX_0F38A7,
1171   PREFIX_VEX_0F38A8,
1172   PREFIX_VEX_0F38A9,
1173   PREFIX_VEX_0F38AA,
1174   PREFIX_VEX_0F38AB,
1175   PREFIX_VEX_0F38AC,
1176   PREFIX_VEX_0F38AD,
1177   PREFIX_VEX_0F38AE,
1178   PREFIX_VEX_0F38AF,
1179   PREFIX_VEX_0F38B6,
1180   PREFIX_VEX_0F38B7,
1181   PREFIX_VEX_0F38B8,
1182   PREFIX_VEX_0F38B9,
1183   PREFIX_VEX_0F38BA,
1184   PREFIX_VEX_0F38BB,
1185   PREFIX_VEX_0F38BC,
1186   PREFIX_VEX_0F38BD,
1187   PREFIX_VEX_0F38BE,
1188   PREFIX_VEX_0F38BF,
1189   PREFIX_VEX_0F38DB,
1190   PREFIX_VEX_0F38DC,
1191   PREFIX_VEX_0F38DD,
1192   PREFIX_VEX_0F38DE,
1193   PREFIX_VEX_0F38DF,
1194   PREFIX_VEX_0F38F2,
1195   PREFIX_VEX_0F38F3_REG_1,
1196   PREFIX_VEX_0F38F3_REG_2,
1197   PREFIX_VEX_0F38F3_REG_3,
1198   PREFIX_VEX_0F38F5,
1199   PREFIX_VEX_0F38F6,
1200   PREFIX_VEX_0F38F7,
1201   PREFIX_VEX_0F3A00,
1202   PREFIX_VEX_0F3A01,
1203   PREFIX_VEX_0F3A02,
1204   PREFIX_VEX_0F3A04,
1205   PREFIX_VEX_0F3A05,
1206   PREFIX_VEX_0F3A06,
1207   PREFIX_VEX_0F3A08,
1208   PREFIX_VEX_0F3A09,
1209   PREFIX_VEX_0F3A0A,
1210   PREFIX_VEX_0F3A0B,
1211   PREFIX_VEX_0F3A0C,
1212   PREFIX_VEX_0F3A0D,
1213   PREFIX_VEX_0F3A0E,
1214   PREFIX_VEX_0F3A0F,
1215   PREFIX_VEX_0F3A14,
1216   PREFIX_VEX_0F3A15,
1217   PREFIX_VEX_0F3A16,
1218   PREFIX_VEX_0F3A17,
1219   PREFIX_VEX_0F3A18,
1220   PREFIX_VEX_0F3A19,
1221   PREFIX_VEX_0F3A1D,
1222   PREFIX_VEX_0F3A20,
1223   PREFIX_VEX_0F3A21,
1224   PREFIX_VEX_0F3A22,
1225   PREFIX_VEX_0F3A30,
1226   PREFIX_VEX_0F3A32,
1227   PREFIX_VEX_0F3A38,
1228   PREFIX_VEX_0F3A39,
1229   PREFIX_VEX_0F3A40,
1230   PREFIX_VEX_0F3A41,
1231   PREFIX_VEX_0F3A42,
1232   PREFIX_VEX_0F3A44,
1233   PREFIX_VEX_0F3A46,
1234   PREFIX_VEX_0F3A48,
1235   PREFIX_VEX_0F3A49,
1236   PREFIX_VEX_0F3A4A,
1237   PREFIX_VEX_0F3A4B,
1238   PREFIX_VEX_0F3A4C,
1239   PREFIX_VEX_0F3A5C,
1240   PREFIX_VEX_0F3A5D,
1241   PREFIX_VEX_0F3A5E,
1242   PREFIX_VEX_0F3A5F,
1243   PREFIX_VEX_0F3A60,
1244   PREFIX_VEX_0F3A61,
1245   PREFIX_VEX_0F3A62,
1246   PREFIX_VEX_0F3A63,
1247   PREFIX_VEX_0F3A68,
1248   PREFIX_VEX_0F3A69,
1249   PREFIX_VEX_0F3A6A,
1250   PREFIX_VEX_0F3A6B,
1251   PREFIX_VEX_0F3A6C,
1252   PREFIX_VEX_0F3A6D,
1253   PREFIX_VEX_0F3A6E,
1254   PREFIX_VEX_0F3A6F,
1255   PREFIX_VEX_0F3A78,
1256   PREFIX_VEX_0F3A79,
1257   PREFIX_VEX_0F3A7A,
1258   PREFIX_VEX_0F3A7B,
1259   PREFIX_VEX_0F3A7C,
1260   PREFIX_VEX_0F3A7D,
1261   PREFIX_VEX_0F3A7E,
1262   PREFIX_VEX_0F3A7F,
1263   PREFIX_VEX_0F3ADF,
1264   PREFIX_VEX_0F3AF0,
1265
1266   PREFIX_EVEX_0F10,
1267   PREFIX_EVEX_0F11,
1268   PREFIX_EVEX_0F12,
1269   PREFIX_EVEX_0F13,
1270   PREFIX_EVEX_0F14,
1271   PREFIX_EVEX_0F15,
1272   PREFIX_EVEX_0F16,
1273   PREFIX_EVEX_0F17,
1274   PREFIX_EVEX_0F28,
1275   PREFIX_EVEX_0F29,
1276   PREFIX_EVEX_0F2A,
1277   PREFIX_EVEX_0F2B,
1278   PREFIX_EVEX_0F2C,
1279   PREFIX_EVEX_0F2D,
1280   PREFIX_EVEX_0F2E,
1281   PREFIX_EVEX_0F2F,
1282   PREFIX_EVEX_0F51,
1283   PREFIX_EVEX_0F58,
1284   PREFIX_EVEX_0F59,
1285   PREFIX_EVEX_0F5A,
1286   PREFIX_EVEX_0F5B,
1287   PREFIX_EVEX_0F5C,
1288   PREFIX_EVEX_0F5D,
1289   PREFIX_EVEX_0F5E,
1290   PREFIX_EVEX_0F5F,
1291   PREFIX_EVEX_0F62,
1292   PREFIX_EVEX_0F66,
1293   PREFIX_EVEX_0F6A,
1294   PREFIX_EVEX_0F6C,
1295   PREFIX_EVEX_0F6D,
1296   PREFIX_EVEX_0F6E,
1297   PREFIX_EVEX_0F6F,
1298   PREFIX_EVEX_0F70,
1299   PREFIX_EVEX_0F72_REG_0,
1300   PREFIX_EVEX_0F72_REG_1,
1301   PREFIX_EVEX_0F72_REG_2,
1302   PREFIX_EVEX_0F72_REG_4,
1303   PREFIX_EVEX_0F72_REG_6,
1304   PREFIX_EVEX_0F73_REG_2,
1305   PREFIX_EVEX_0F73_REG_6,
1306   PREFIX_EVEX_0F76,
1307   PREFIX_EVEX_0F78,
1308   PREFIX_EVEX_0F79,
1309   PREFIX_EVEX_0F7A,
1310   PREFIX_EVEX_0F7B,
1311   PREFIX_EVEX_0F7E,
1312   PREFIX_EVEX_0F7F,
1313   PREFIX_EVEX_0FC2,
1314   PREFIX_EVEX_0FC6,
1315   PREFIX_EVEX_0FD2,
1316   PREFIX_EVEX_0FD3,
1317   PREFIX_EVEX_0FD4,
1318   PREFIX_EVEX_0FD6,
1319   PREFIX_EVEX_0FDB,
1320   PREFIX_EVEX_0FDF,
1321   PREFIX_EVEX_0FE2,
1322   PREFIX_EVEX_0FE6,
1323   PREFIX_EVEX_0FE7,
1324   PREFIX_EVEX_0FEB,
1325   PREFIX_EVEX_0FEF,
1326   PREFIX_EVEX_0FF2,
1327   PREFIX_EVEX_0FF3,
1328   PREFIX_EVEX_0FF4,
1329   PREFIX_EVEX_0FFA,
1330   PREFIX_EVEX_0FFB,
1331   PREFIX_EVEX_0FFE,
1332   PREFIX_EVEX_0F380C,
1333   PREFIX_EVEX_0F380D,
1334   PREFIX_EVEX_0F3811,
1335   PREFIX_EVEX_0F3812,
1336   PREFIX_EVEX_0F3813,
1337   PREFIX_EVEX_0F3814,
1338   PREFIX_EVEX_0F3815,
1339   PREFIX_EVEX_0F3816,
1340   PREFIX_EVEX_0F3818,
1341   PREFIX_EVEX_0F3819,
1342   PREFIX_EVEX_0F381A,
1343   PREFIX_EVEX_0F381B,
1344   PREFIX_EVEX_0F381E,
1345   PREFIX_EVEX_0F381F,
1346   PREFIX_EVEX_0F3821,
1347   PREFIX_EVEX_0F3822,
1348   PREFIX_EVEX_0F3823,
1349   PREFIX_EVEX_0F3824,
1350   PREFIX_EVEX_0F3825,
1351   PREFIX_EVEX_0F3827,
1352   PREFIX_EVEX_0F3828,
1353   PREFIX_EVEX_0F3829,
1354   PREFIX_EVEX_0F382A,
1355   PREFIX_EVEX_0F382C,
1356   PREFIX_EVEX_0F382D,
1357   PREFIX_EVEX_0F3831,
1358   PREFIX_EVEX_0F3832,
1359   PREFIX_EVEX_0F3833,
1360   PREFIX_EVEX_0F3834,
1361   PREFIX_EVEX_0F3835,
1362   PREFIX_EVEX_0F3836,
1363   PREFIX_EVEX_0F3837,
1364   PREFIX_EVEX_0F3839,
1365   PREFIX_EVEX_0F383A,
1366   PREFIX_EVEX_0F383B,
1367   PREFIX_EVEX_0F383D,
1368   PREFIX_EVEX_0F383F,
1369   PREFIX_EVEX_0F3840,
1370   PREFIX_EVEX_0F3842,
1371   PREFIX_EVEX_0F3843,
1372   PREFIX_EVEX_0F3844,
1373   PREFIX_EVEX_0F3845,
1374   PREFIX_EVEX_0F3846,
1375   PREFIX_EVEX_0F3847,
1376   PREFIX_EVEX_0F384C,
1377   PREFIX_EVEX_0F384D,
1378   PREFIX_EVEX_0F384E,
1379   PREFIX_EVEX_0F384F,
1380   PREFIX_EVEX_0F3858,
1381   PREFIX_EVEX_0F3859,
1382   PREFIX_EVEX_0F385A,
1383   PREFIX_EVEX_0F385B,
1384   PREFIX_EVEX_0F3864,
1385   PREFIX_EVEX_0F3865,
1386   PREFIX_EVEX_0F3876,
1387   PREFIX_EVEX_0F3877,
1388   PREFIX_EVEX_0F387C,
1389   PREFIX_EVEX_0F387E,
1390   PREFIX_EVEX_0F387F,
1391   PREFIX_EVEX_0F3888,
1392   PREFIX_EVEX_0F3889,
1393   PREFIX_EVEX_0F388A,
1394   PREFIX_EVEX_0F388B,
1395   PREFIX_EVEX_0F3890,
1396   PREFIX_EVEX_0F3891,
1397   PREFIX_EVEX_0F3892,
1398   PREFIX_EVEX_0F3893,
1399   PREFIX_EVEX_0F3896,
1400   PREFIX_EVEX_0F3897,
1401   PREFIX_EVEX_0F3898,
1402   PREFIX_EVEX_0F3899,
1403   PREFIX_EVEX_0F389A,
1404   PREFIX_EVEX_0F389B,
1405   PREFIX_EVEX_0F389C,
1406   PREFIX_EVEX_0F389D,
1407   PREFIX_EVEX_0F389E,
1408   PREFIX_EVEX_0F389F,
1409   PREFIX_EVEX_0F38A0,
1410   PREFIX_EVEX_0F38A1,
1411   PREFIX_EVEX_0F38A2,
1412   PREFIX_EVEX_0F38A3,
1413   PREFIX_EVEX_0F38A6,
1414   PREFIX_EVEX_0F38A7,
1415   PREFIX_EVEX_0F38A8,
1416   PREFIX_EVEX_0F38A9,
1417   PREFIX_EVEX_0F38AA,
1418   PREFIX_EVEX_0F38AB,
1419   PREFIX_EVEX_0F38AC,
1420   PREFIX_EVEX_0F38AD,
1421   PREFIX_EVEX_0F38AE,
1422   PREFIX_EVEX_0F38AF,
1423   PREFIX_EVEX_0F38B6,
1424   PREFIX_EVEX_0F38B7,
1425   PREFIX_EVEX_0F38B8,
1426   PREFIX_EVEX_0F38B9,
1427   PREFIX_EVEX_0F38BA,
1428   PREFIX_EVEX_0F38BB,
1429   PREFIX_EVEX_0F38BC,
1430   PREFIX_EVEX_0F38BD,
1431   PREFIX_EVEX_0F38BE,
1432   PREFIX_EVEX_0F38BF,
1433   PREFIX_EVEX_0F38C4,
1434   PREFIX_EVEX_0F38C6_REG_1,
1435   PREFIX_EVEX_0F38C6_REG_2,
1436   PREFIX_EVEX_0F38C6_REG_5,
1437   PREFIX_EVEX_0F38C6_REG_6,
1438   PREFIX_EVEX_0F38C7_REG_1,
1439   PREFIX_EVEX_0F38C7_REG_2,
1440   PREFIX_EVEX_0F38C7_REG_5,
1441   PREFIX_EVEX_0F38C7_REG_6,
1442   PREFIX_EVEX_0F38C8,
1443   PREFIX_EVEX_0F38CA,
1444   PREFIX_EVEX_0F38CB,
1445   PREFIX_EVEX_0F38CC,
1446   PREFIX_EVEX_0F38CD,
1447
1448   PREFIX_EVEX_0F3A00,
1449   PREFIX_EVEX_0F3A01,
1450   PREFIX_EVEX_0F3A03,
1451   PREFIX_EVEX_0F3A04,
1452   PREFIX_EVEX_0F3A05,
1453   PREFIX_EVEX_0F3A08,
1454   PREFIX_EVEX_0F3A09,
1455   PREFIX_EVEX_0F3A0A,
1456   PREFIX_EVEX_0F3A0B,
1457   PREFIX_EVEX_0F3A17,
1458   PREFIX_EVEX_0F3A18,
1459   PREFIX_EVEX_0F3A19,
1460   PREFIX_EVEX_0F3A1A,
1461   PREFIX_EVEX_0F3A1B,
1462   PREFIX_EVEX_0F3A1D,
1463   PREFIX_EVEX_0F3A1E,
1464   PREFIX_EVEX_0F3A1F,
1465   PREFIX_EVEX_0F3A21,
1466   PREFIX_EVEX_0F3A23,
1467   PREFIX_EVEX_0F3A25,
1468   PREFIX_EVEX_0F3A26,
1469   PREFIX_EVEX_0F3A27,
1470   PREFIX_EVEX_0F3A38,
1471   PREFIX_EVEX_0F3A39,
1472   PREFIX_EVEX_0F3A3A,
1473   PREFIX_EVEX_0F3A3B,
1474   PREFIX_EVEX_0F3A43,
1475   PREFIX_EVEX_0F3A54,
1476   PREFIX_EVEX_0F3A55,
1477 };
1478
1479 enum
1480 {
1481   X86_64_06 = 0,
1482   X86_64_07,
1483   X86_64_0D,
1484   X86_64_16,
1485   X86_64_17,
1486   X86_64_1E,
1487   X86_64_1F,
1488   X86_64_27,
1489   X86_64_2F,
1490   X86_64_37,
1491   X86_64_3F,
1492   X86_64_60,
1493   X86_64_61,
1494   X86_64_62,
1495   X86_64_63,
1496   X86_64_6D,
1497   X86_64_6F,
1498   X86_64_9A,
1499   X86_64_C4,
1500   X86_64_C5,
1501   X86_64_CE,
1502   X86_64_D4,
1503   X86_64_D5,
1504   X86_64_EA,
1505   X86_64_0F01_REG_0,
1506   X86_64_0F01_REG_1,
1507   X86_64_0F01_REG_2,
1508   X86_64_0F01_REG_3
1509 };
1510
1511 enum
1512 {
1513   THREE_BYTE_0F38 = 0,
1514   THREE_BYTE_0F3A,
1515   THREE_BYTE_0F7A
1516 };
1517
1518 enum
1519 {
1520   XOP_08 = 0,
1521   XOP_09,
1522   XOP_0A
1523 };
1524
1525 enum
1526 {
1527   VEX_0F = 0,
1528   VEX_0F38,
1529   VEX_0F3A
1530 };
1531
1532 enum
1533 {
1534   EVEX_0F = 0,
1535   EVEX_0F38,
1536   EVEX_0F3A
1537 };
1538
1539 enum
1540 {
1541   VEX_LEN_0F10_P_1 = 0,
1542   VEX_LEN_0F10_P_3,
1543   VEX_LEN_0F11_P_1,
1544   VEX_LEN_0F11_P_3,
1545   VEX_LEN_0F12_P_0_M_0,
1546   VEX_LEN_0F12_P_0_M_1,
1547   VEX_LEN_0F12_P_2,
1548   VEX_LEN_0F13_M_0,
1549   VEX_LEN_0F16_P_0_M_0,
1550   VEX_LEN_0F16_P_0_M_1,
1551   VEX_LEN_0F16_P_2,
1552   VEX_LEN_0F17_M_0,
1553   VEX_LEN_0F2A_P_1,
1554   VEX_LEN_0F2A_P_3,
1555   VEX_LEN_0F2C_P_1,
1556   VEX_LEN_0F2C_P_3,
1557   VEX_LEN_0F2D_P_1,
1558   VEX_LEN_0F2D_P_3,
1559   VEX_LEN_0F2E_P_0,
1560   VEX_LEN_0F2E_P_2,
1561   VEX_LEN_0F2F_P_0,
1562   VEX_LEN_0F2F_P_2,
1563   VEX_LEN_0F41_P_0,
1564   VEX_LEN_0F42_P_0,
1565   VEX_LEN_0F44_P_0,
1566   VEX_LEN_0F45_P_0,
1567   VEX_LEN_0F46_P_0,
1568   VEX_LEN_0F47_P_0,
1569   VEX_LEN_0F4B_P_2,
1570   VEX_LEN_0F51_P_1,
1571   VEX_LEN_0F51_P_3,
1572   VEX_LEN_0F52_P_1,
1573   VEX_LEN_0F53_P_1,
1574   VEX_LEN_0F58_P_1,
1575   VEX_LEN_0F58_P_3,
1576   VEX_LEN_0F59_P_1,
1577   VEX_LEN_0F59_P_3,
1578   VEX_LEN_0F5A_P_1,
1579   VEX_LEN_0F5A_P_3,
1580   VEX_LEN_0F5C_P_1,
1581   VEX_LEN_0F5C_P_3,
1582   VEX_LEN_0F5D_P_1,
1583   VEX_LEN_0F5D_P_3,
1584   VEX_LEN_0F5E_P_1,
1585   VEX_LEN_0F5E_P_3,
1586   VEX_LEN_0F5F_P_1,
1587   VEX_LEN_0F5F_P_3,
1588   VEX_LEN_0F6E_P_2,
1589   VEX_LEN_0F7E_P_1,
1590   VEX_LEN_0F7E_P_2,
1591   VEX_LEN_0F90_P_0,
1592   VEX_LEN_0F91_P_0,
1593   VEX_LEN_0F92_P_0,
1594   VEX_LEN_0F93_P_0,
1595   VEX_LEN_0F98_P_0,
1596   VEX_LEN_0FAE_R_2_M_0,
1597   VEX_LEN_0FAE_R_3_M_0,
1598   VEX_LEN_0FC2_P_1,
1599   VEX_LEN_0FC2_P_3,
1600   VEX_LEN_0FC4_P_2,
1601   VEX_LEN_0FC5_P_2,
1602   VEX_LEN_0FD6_P_2,
1603   VEX_LEN_0FF7_P_2,
1604   VEX_LEN_0F3816_P_2,
1605   VEX_LEN_0F3819_P_2,
1606   VEX_LEN_0F381A_P_2_M_0,
1607   VEX_LEN_0F3836_P_2,
1608   VEX_LEN_0F3841_P_2,
1609   VEX_LEN_0F385A_P_2_M_0,
1610   VEX_LEN_0F38DB_P_2,
1611   VEX_LEN_0F38DC_P_2,
1612   VEX_LEN_0F38DD_P_2,
1613   VEX_LEN_0F38DE_P_2,
1614   VEX_LEN_0F38DF_P_2,
1615   VEX_LEN_0F38F2_P_0,
1616   VEX_LEN_0F38F3_R_1_P_0,
1617   VEX_LEN_0F38F3_R_2_P_0,
1618   VEX_LEN_0F38F3_R_3_P_0,
1619   VEX_LEN_0F38F5_P_0,
1620   VEX_LEN_0F38F5_P_1,
1621   VEX_LEN_0F38F5_P_3,
1622   VEX_LEN_0F38F6_P_3,
1623   VEX_LEN_0F38F7_P_0,
1624   VEX_LEN_0F38F7_P_1,
1625   VEX_LEN_0F38F7_P_2,
1626   VEX_LEN_0F38F7_P_3,
1627   VEX_LEN_0F3A00_P_2,
1628   VEX_LEN_0F3A01_P_2,
1629   VEX_LEN_0F3A06_P_2,
1630   VEX_LEN_0F3A0A_P_2,
1631   VEX_LEN_0F3A0B_P_2,
1632   VEX_LEN_0F3A14_P_2,
1633   VEX_LEN_0F3A15_P_2,
1634   VEX_LEN_0F3A16_P_2,
1635   VEX_LEN_0F3A17_P_2,
1636   VEX_LEN_0F3A18_P_2,
1637   VEX_LEN_0F3A19_P_2,
1638   VEX_LEN_0F3A20_P_2,
1639   VEX_LEN_0F3A21_P_2,
1640   VEX_LEN_0F3A22_P_2,
1641   VEX_LEN_0F3A30_P_2,
1642   VEX_LEN_0F3A32_P_2,
1643   VEX_LEN_0F3A38_P_2,
1644   VEX_LEN_0F3A39_P_2,
1645   VEX_LEN_0F3A41_P_2,
1646   VEX_LEN_0F3A44_P_2,
1647   VEX_LEN_0F3A46_P_2,
1648   VEX_LEN_0F3A60_P_2,
1649   VEX_LEN_0F3A61_P_2,
1650   VEX_LEN_0F3A62_P_2,
1651   VEX_LEN_0F3A63_P_2,
1652   VEX_LEN_0F3A6A_P_2,
1653   VEX_LEN_0F3A6B_P_2,
1654   VEX_LEN_0F3A6E_P_2,
1655   VEX_LEN_0F3A6F_P_2,
1656   VEX_LEN_0F3A7A_P_2,
1657   VEX_LEN_0F3A7B_P_2,
1658   VEX_LEN_0F3A7E_P_2,
1659   VEX_LEN_0F3A7F_P_2,
1660   VEX_LEN_0F3ADF_P_2,
1661   VEX_LEN_0F3AF0_P_3,
1662   VEX_LEN_0FXOP_08_CC,
1663   VEX_LEN_0FXOP_08_CD,
1664   VEX_LEN_0FXOP_08_CE,
1665   VEX_LEN_0FXOP_08_CF,
1666   VEX_LEN_0FXOP_08_EC,
1667   VEX_LEN_0FXOP_08_ED,
1668   VEX_LEN_0FXOP_08_EE,
1669   VEX_LEN_0FXOP_08_EF,
1670   VEX_LEN_0FXOP_09_80,
1671   VEX_LEN_0FXOP_09_81
1672 };
1673
1674 enum
1675 {
1676   VEX_W_0F10_P_0 = 0,
1677   VEX_W_0F10_P_1,
1678   VEX_W_0F10_P_2,
1679   VEX_W_0F10_P_3,
1680   VEX_W_0F11_P_0,
1681   VEX_W_0F11_P_1,
1682   VEX_W_0F11_P_2,
1683   VEX_W_0F11_P_3,
1684   VEX_W_0F12_P_0_M_0,
1685   VEX_W_0F12_P_0_M_1,
1686   VEX_W_0F12_P_1,
1687   VEX_W_0F12_P_2,
1688   VEX_W_0F12_P_3,
1689   VEX_W_0F13_M_0,
1690   VEX_W_0F14,
1691   VEX_W_0F15,
1692   VEX_W_0F16_P_0_M_0,
1693   VEX_W_0F16_P_0_M_1,
1694   VEX_W_0F16_P_1,
1695   VEX_W_0F16_P_2,
1696   VEX_W_0F17_M_0,
1697   VEX_W_0F28,
1698   VEX_W_0F29,
1699   VEX_W_0F2B_M_0,
1700   VEX_W_0F2E_P_0,
1701   VEX_W_0F2E_P_2,
1702   VEX_W_0F2F_P_0,
1703   VEX_W_0F2F_P_2,
1704   VEX_W_0F41_P_0_LEN_1,
1705   VEX_W_0F42_P_0_LEN_1,
1706   VEX_W_0F44_P_0_LEN_0,
1707   VEX_W_0F45_P_0_LEN_1,
1708   VEX_W_0F46_P_0_LEN_1,
1709   VEX_W_0F47_P_0_LEN_1,
1710   VEX_W_0F4B_P_2_LEN_1,
1711   VEX_W_0F50_M_0,
1712   VEX_W_0F51_P_0,
1713   VEX_W_0F51_P_1,
1714   VEX_W_0F51_P_2,
1715   VEX_W_0F51_P_3,
1716   VEX_W_0F52_P_0,
1717   VEX_W_0F52_P_1,
1718   VEX_W_0F53_P_0,
1719   VEX_W_0F53_P_1,
1720   VEX_W_0F58_P_0,
1721   VEX_W_0F58_P_1,
1722   VEX_W_0F58_P_2,
1723   VEX_W_0F58_P_3,
1724   VEX_W_0F59_P_0,
1725   VEX_W_0F59_P_1,
1726   VEX_W_0F59_P_2,
1727   VEX_W_0F59_P_3,
1728   VEX_W_0F5A_P_0,
1729   VEX_W_0F5A_P_1,
1730   VEX_W_0F5A_P_3,
1731   VEX_W_0F5B_P_0,
1732   VEX_W_0F5B_P_1,
1733   VEX_W_0F5B_P_2,
1734   VEX_W_0F5C_P_0,
1735   VEX_W_0F5C_P_1,
1736   VEX_W_0F5C_P_2,
1737   VEX_W_0F5C_P_3,
1738   VEX_W_0F5D_P_0,
1739   VEX_W_0F5D_P_1,
1740   VEX_W_0F5D_P_2,
1741   VEX_W_0F5D_P_3,
1742   VEX_W_0F5E_P_0,
1743   VEX_W_0F5E_P_1,
1744   VEX_W_0F5E_P_2,
1745   VEX_W_0F5E_P_3,
1746   VEX_W_0F5F_P_0,
1747   VEX_W_0F5F_P_1,
1748   VEX_W_0F5F_P_2,
1749   VEX_W_0F5F_P_3,
1750   VEX_W_0F60_P_2,
1751   VEX_W_0F61_P_2,
1752   VEX_W_0F62_P_2,
1753   VEX_W_0F63_P_2,
1754   VEX_W_0F64_P_2,
1755   VEX_W_0F65_P_2,
1756   VEX_W_0F66_P_2,
1757   VEX_W_0F67_P_2,
1758   VEX_W_0F68_P_2,
1759   VEX_W_0F69_P_2,
1760   VEX_W_0F6A_P_2,
1761   VEX_W_0F6B_P_2,
1762   VEX_W_0F6C_P_2,
1763   VEX_W_0F6D_P_2,
1764   VEX_W_0F6F_P_1,
1765   VEX_W_0F6F_P_2,
1766   VEX_W_0F70_P_1,
1767   VEX_W_0F70_P_2,
1768   VEX_W_0F70_P_3,
1769   VEX_W_0F71_R_2_P_2,
1770   VEX_W_0F71_R_4_P_2,
1771   VEX_W_0F71_R_6_P_2,
1772   VEX_W_0F72_R_2_P_2,
1773   VEX_W_0F72_R_4_P_2,
1774   VEX_W_0F72_R_6_P_2,
1775   VEX_W_0F73_R_2_P_2,
1776   VEX_W_0F73_R_3_P_2,
1777   VEX_W_0F73_R_6_P_2,
1778   VEX_W_0F73_R_7_P_2,
1779   VEX_W_0F74_P_2,
1780   VEX_W_0F75_P_2,
1781   VEX_W_0F76_P_2,
1782   VEX_W_0F77_P_0,
1783   VEX_W_0F7C_P_2,
1784   VEX_W_0F7C_P_3,
1785   VEX_W_0F7D_P_2,
1786   VEX_W_0F7D_P_3,
1787   VEX_W_0F7E_P_1,
1788   VEX_W_0F7F_P_1,
1789   VEX_W_0F7F_P_2,
1790   VEX_W_0F90_P_0_LEN_0,
1791   VEX_W_0F91_P_0_LEN_0,
1792   VEX_W_0F92_P_0_LEN_0,
1793   VEX_W_0F93_P_0_LEN_0,
1794   VEX_W_0F98_P_0_LEN_0,
1795   VEX_W_0FAE_R_2_M_0,
1796   VEX_W_0FAE_R_3_M_0,
1797   VEX_W_0FC2_P_0,
1798   VEX_W_0FC2_P_1,
1799   VEX_W_0FC2_P_2,
1800   VEX_W_0FC2_P_3,
1801   VEX_W_0FC4_P_2,
1802   VEX_W_0FC5_P_2,
1803   VEX_W_0FD0_P_2,
1804   VEX_W_0FD0_P_3,
1805   VEX_W_0FD1_P_2,
1806   VEX_W_0FD2_P_2,
1807   VEX_W_0FD3_P_2,
1808   VEX_W_0FD4_P_2,
1809   VEX_W_0FD5_P_2,
1810   VEX_W_0FD6_P_2,
1811   VEX_W_0FD7_P_2_M_1,
1812   VEX_W_0FD8_P_2,
1813   VEX_W_0FD9_P_2,
1814   VEX_W_0FDA_P_2,
1815   VEX_W_0FDB_P_2,
1816   VEX_W_0FDC_P_2,
1817   VEX_W_0FDD_P_2,
1818   VEX_W_0FDE_P_2,
1819   VEX_W_0FDF_P_2,
1820   VEX_W_0FE0_P_2,
1821   VEX_W_0FE1_P_2,
1822   VEX_W_0FE2_P_2,
1823   VEX_W_0FE3_P_2,
1824   VEX_W_0FE4_P_2,
1825   VEX_W_0FE5_P_2,
1826   VEX_W_0FE6_P_1,
1827   VEX_W_0FE6_P_2,
1828   VEX_W_0FE6_P_3,
1829   VEX_W_0FE7_P_2_M_0,
1830   VEX_W_0FE8_P_2,
1831   VEX_W_0FE9_P_2,
1832   VEX_W_0FEA_P_2,
1833   VEX_W_0FEB_P_2,
1834   VEX_W_0FEC_P_2,
1835   VEX_W_0FED_P_2,
1836   VEX_W_0FEE_P_2,
1837   VEX_W_0FEF_P_2,
1838   VEX_W_0FF0_P_3_M_0,
1839   VEX_W_0FF1_P_2,
1840   VEX_W_0FF2_P_2,
1841   VEX_W_0FF3_P_2,
1842   VEX_W_0FF4_P_2,
1843   VEX_W_0FF5_P_2,
1844   VEX_W_0FF6_P_2,
1845   VEX_W_0FF7_P_2,
1846   VEX_W_0FF8_P_2,
1847   VEX_W_0FF9_P_2,
1848   VEX_W_0FFA_P_2,
1849   VEX_W_0FFB_P_2,
1850   VEX_W_0FFC_P_2,
1851   VEX_W_0FFD_P_2,
1852   VEX_W_0FFE_P_2,
1853   VEX_W_0F3800_P_2,
1854   VEX_W_0F3801_P_2,
1855   VEX_W_0F3802_P_2,
1856   VEX_W_0F3803_P_2,
1857   VEX_W_0F3804_P_2,
1858   VEX_W_0F3805_P_2,
1859   VEX_W_0F3806_P_2,
1860   VEX_W_0F3807_P_2,
1861   VEX_W_0F3808_P_2,
1862   VEX_W_0F3809_P_2,
1863   VEX_W_0F380A_P_2,
1864   VEX_W_0F380B_P_2,
1865   VEX_W_0F380C_P_2,
1866   VEX_W_0F380D_P_2,
1867   VEX_W_0F380E_P_2,
1868   VEX_W_0F380F_P_2,
1869   VEX_W_0F3816_P_2,
1870   VEX_W_0F3817_P_2,
1871   VEX_W_0F3818_P_2,
1872   VEX_W_0F3819_P_2,
1873   VEX_W_0F381A_P_2_M_0,
1874   VEX_W_0F381C_P_2,
1875   VEX_W_0F381D_P_2,
1876   VEX_W_0F381E_P_2,
1877   VEX_W_0F3820_P_2,
1878   VEX_W_0F3821_P_2,
1879   VEX_W_0F3822_P_2,
1880   VEX_W_0F3823_P_2,
1881   VEX_W_0F3824_P_2,
1882   VEX_W_0F3825_P_2,
1883   VEX_W_0F3828_P_2,
1884   VEX_W_0F3829_P_2,
1885   VEX_W_0F382A_P_2_M_0,
1886   VEX_W_0F382B_P_2,
1887   VEX_W_0F382C_P_2_M_0,
1888   VEX_W_0F382D_P_2_M_0,
1889   VEX_W_0F382E_P_2_M_0,
1890   VEX_W_0F382F_P_2_M_0,
1891   VEX_W_0F3830_P_2,
1892   VEX_W_0F3831_P_2,
1893   VEX_W_0F3832_P_2,
1894   VEX_W_0F3833_P_2,
1895   VEX_W_0F3834_P_2,
1896   VEX_W_0F3835_P_2,
1897   VEX_W_0F3836_P_2,
1898   VEX_W_0F3837_P_2,
1899   VEX_W_0F3838_P_2,
1900   VEX_W_0F3839_P_2,
1901   VEX_W_0F383A_P_2,
1902   VEX_W_0F383B_P_2,
1903   VEX_W_0F383C_P_2,
1904   VEX_W_0F383D_P_2,
1905   VEX_W_0F383E_P_2,
1906   VEX_W_0F383F_P_2,
1907   VEX_W_0F3840_P_2,
1908   VEX_W_0F3841_P_2,
1909   VEX_W_0F3846_P_2,
1910   VEX_W_0F3858_P_2,
1911   VEX_W_0F3859_P_2,
1912   VEX_W_0F385A_P_2_M_0,
1913   VEX_W_0F3878_P_2,
1914   VEX_W_0F3879_P_2,
1915   VEX_W_0F38DB_P_2,
1916   VEX_W_0F38DC_P_2,
1917   VEX_W_0F38DD_P_2,
1918   VEX_W_0F38DE_P_2,
1919   VEX_W_0F38DF_P_2,
1920   VEX_W_0F3A00_P_2,
1921   VEX_W_0F3A01_P_2,
1922   VEX_W_0F3A02_P_2,
1923   VEX_W_0F3A04_P_2,
1924   VEX_W_0F3A05_P_2,
1925   VEX_W_0F3A06_P_2,
1926   VEX_W_0F3A08_P_2,
1927   VEX_W_0F3A09_P_2,
1928   VEX_W_0F3A0A_P_2,
1929   VEX_W_0F3A0B_P_2,
1930   VEX_W_0F3A0C_P_2,
1931   VEX_W_0F3A0D_P_2,
1932   VEX_W_0F3A0E_P_2,
1933   VEX_W_0F3A0F_P_2,
1934   VEX_W_0F3A14_P_2,
1935   VEX_W_0F3A15_P_2,
1936   VEX_W_0F3A18_P_2,
1937   VEX_W_0F3A19_P_2,
1938   VEX_W_0F3A20_P_2,
1939   VEX_W_0F3A21_P_2,
1940   VEX_W_0F3A30_P_2_LEN_0,
1941   VEX_W_0F3A32_P_2_LEN_0,
1942   VEX_W_0F3A38_P_2,
1943   VEX_W_0F3A39_P_2,
1944   VEX_W_0F3A40_P_2,
1945   VEX_W_0F3A41_P_2,
1946   VEX_W_0F3A42_P_2,
1947   VEX_W_0F3A44_P_2,
1948   VEX_W_0F3A46_P_2,
1949   VEX_W_0F3A48_P_2,
1950   VEX_W_0F3A49_P_2,
1951   VEX_W_0F3A4A_P_2,
1952   VEX_W_0F3A4B_P_2,
1953   VEX_W_0F3A4C_P_2,
1954   VEX_W_0F3A60_P_2,
1955   VEX_W_0F3A61_P_2,
1956   VEX_W_0F3A62_P_2,
1957   VEX_W_0F3A63_P_2,
1958   VEX_W_0F3ADF_P_2,
1959
1960   EVEX_W_0F10_P_0,
1961   EVEX_W_0F10_P_1_M_0,
1962   EVEX_W_0F10_P_1_M_1,
1963   EVEX_W_0F10_P_2,
1964   EVEX_W_0F10_P_3_M_0,
1965   EVEX_W_0F10_P_3_M_1,
1966   EVEX_W_0F11_P_0,
1967   EVEX_W_0F11_P_1_M_0,
1968   EVEX_W_0F11_P_1_M_1,
1969   EVEX_W_0F11_P_2,
1970   EVEX_W_0F11_P_3_M_0,
1971   EVEX_W_0F11_P_3_M_1,
1972   EVEX_W_0F12_P_0_M_0,
1973   EVEX_W_0F12_P_0_M_1,
1974   EVEX_W_0F12_P_1,
1975   EVEX_W_0F12_P_2,
1976   EVEX_W_0F12_P_3,
1977   EVEX_W_0F13_P_0,
1978   EVEX_W_0F13_P_2,
1979   EVEX_W_0F14_P_0,
1980   EVEX_W_0F14_P_2,
1981   EVEX_W_0F15_P_0,
1982   EVEX_W_0F15_P_2,
1983   EVEX_W_0F16_P_0_M_0,
1984   EVEX_W_0F16_P_0_M_1,
1985   EVEX_W_0F16_P_1,
1986   EVEX_W_0F16_P_2,
1987   EVEX_W_0F17_P_0,
1988   EVEX_W_0F17_P_2,
1989   EVEX_W_0F28_P_0,
1990   EVEX_W_0F28_P_2,
1991   EVEX_W_0F29_P_0,
1992   EVEX_W_0F29_P_2,
1993   EVEX_W_0F2A_P_1,
1994   EVEX_W_0F2A_P_3,
1995   EVEX_W_0F2B_P_0,
1996   EVEX_W_0F2B_P_2,
1997   EVEX_W_0F2E_P_0,
1998   EVEX_W_0F2E_P_2,
1999   EVEX_W_0F2F_P_0,
2000   EVEX_W_0F2F_P_2,
2001   EVEX_W_0F51_P_0,
2002   EVEX_W_0F51_P_1,
2003   EVEX_W_0F51_P_2,
2004   EVEX_W_0F51_P_3,
2005   EVEX_W_0F58_P_0,
2006   EVEX_W_0F58_P_1,
2007   EVEX_W_0F58_P_2,
2008   EVEX_W_0F58_P_3,
2009   EVEX_W_0F59_P_0,
2010   EVEX_W_0F59_P_1,
2011   EVEX_W_0F59_P_2,
2012   EVEX_W_0F59_P_3,
2013   EVEX_W_0F5A_P_0,
2014   EVEX_W_0F5A_P_1,
2015   EVEX_W_0F5A_P_2,
2016   EVEX_W_0F5A_P_3,
2017   EVEX_W_0F5B_P_0,
2018   EVEX_W_0F5B_P_1,
2019   EVEX_W_0F5B_P_2,
2020   EVEX_W_0F5C_P_0,
2021   EVEX_W_0F5C_P_1,
2022   EVEX_W_0F5C_P_2,
2023   EVEX_W_0F5C_P_3,
2024   EVEX_W_0F5D_P_0,
2025   EVEX_W_0F5D_P_1,
2026   EVEX_W_0F5D_P_2,
2027   EVEX_W_0F5D_P_3,
2028   EVEX_W_0F5E_P_0,
2029   EVEX_W_0F5E_P_1,
2030   EVEX_W_0F5E_P_2,
2031   EVEX_W_0F5E_P_3,
2032   EVEX_W_0F5F_P_0,
2033   EVEX_W_0F5F_P_1,
2034   EVEX_W_0F5F_P_2,
2035   EVEX_W_0F5F_P_3,
2036   EVEX_W_0F62_P_2,
2037   EVEX_W_0F66_P_2,
2038   EVEX_W_0F6A_P_2,
2039   EVEX_W_0F6C_P_2,
2040   EVEX_W_0F6D_P_2,
2041   EVEX_W_0F6E_P_2,
2042   EVEX_W_0F6F_P_1,
2043   EVEX_W_0F6F_P_2,
2044   EVEX_W_0F70_P_2,
2045   EVEX_W_0F72_R_2_P_2,
2046   EVEX_W_0F72_R_6_P_2,
2047   EVEX_W_0F73_R_2_P_2,
2048   EVEX_W_0F73_R_6_P_2,
2049   EVEX_W_0F76_P_2,
2050   EVEX_W_0F78_P_0,
2051   EVEX_W_0F79_P_0,
2052   EVEX_W_0F7A_P_1,
2053   EVEX_W_0F7A_P_3,
2054   EVEX_W_0F7B_P_1,
2055   EVEX_W_0F7B_P_3,
2056   EVEX_W_0F7E_P_1,
2057   EVEX_W_0F7E_P_2,
2058   EVEX_W_0F7F_P_1,
2059   EVEX_W_0F7F_P_2,
2060   EVEX_W_0FC2_P_0,
2061   EVEX_W_0FC2_P_1,
2062   EVEX_W_0FC2_P_2,
2063   EVEX_W_0FC2_P_3,
2064   EVEX_W_0FC6_P_0,
2065   EVEX_W_0FC6_P_2,
2066   EVEX_W_0FD2_P_2,
2067   EVEX_W_0FD3_P_2,
2068   EVEX_W_0FD4_P_2,
2069   EVEX_W_0FD6_P_2,
2070   EVEX_W_0FE6_P_1,
2071   EVEX_W_0FE6_P_2,
2072   EVEX_W_0FE6_P_3,
2073   EVEX_W_0FE7_P_2,
2074   EVEX_W_0FF2_P_2,
2075   EVEX_W_0FF3_P_2,
2076   EVEX_W_0FF4_P_2,
2077   EVEX_W_0FFA_P_2,
2078   EVEX_W_0FFB_P_2,
2079   EVEX_W_0FFE_P_2,
2080   EVEX_W_0F380C_P_2,
2081   EVEX_W_0F380D_P_2,
2082   EVEX_W_0F3811_P_1,
2083   EVEX_W_0F3812_P_1,
2084   EVEX_W_0F3813_P_1,
2085   EVEX_W_0F3813_P_2,
2086   EVEX_W_0F3814_P_1,
2087   EVEX_W_0F3815_P_1,
2088   EVEX_W_0F3818_P_2,
2089   EVEX_W_0F3819_P_2,
2090   EVEX_W_0F381A_P_2,
2091   EVEX_W_0F381B_P_2,
2092   EVEX_W_0F381E_P_2,
2093   EVEX_W_0F381F_P_2,
2094   EVEX_W_0F3821_P_1,
2095   EVEX_W_0F3822_P_1,
2096   EVEX_W_0F3823_P_1,
2097   EVEX_W_0F3824_P_1,
2098   EVEX_W_0F3825_P_1,
2099   EVEX_W_0F3825_P_2,
2100   EVEX_W_0F3828_P_2,
2101   EVEX_W_0F3829_P_2,
2102   EVEX_W_0F382A_P_1,
2103   EVEX_W_0F382A_P_2,
2104   EVEX_W_0F3831_P_1,
2105   EVEX_W_0F3832_P_1,
2106   EVEX_W_0F3833_P_1,
2107   EVEX_W_0F3834_P_1,
2108   EVEX_W_0F3835_P_1,
2109   EVEX_W_0F3835_P_2,
2110   EVEX_W_0F3837_P_2,
2111   EVEX_W_0F383A_P_1,
2112   EVEX_W_0F3840_P_2,
2113   EVEX_W_0F3858_P_2,
2114   EVEX_W_0F3859_P_2,
2115   EVEX_W_0F385A_P_2,
2116   EVEX_W_0F385B_P_2,
2117   EVEX_W_0F3891_P_2,
2118   EVEX_W_0F3893_P_2,
2119   EVEX_W_0F38A1_P_2,
2120   EVEX_W_0F38A3_P_2,
2121   EVEX_W_0F38C7_R_1_P_2,
2122   EVEX_W_0F38C7_R_2_P_2,
2123   EVEX_W_0F38C7_R_5_P_2,
2124   EVEX_W_0F38C7_R_6_P_2,
2125
2126   EVEX_W_0F3A00_P_2,
2127   EVEX_W_0F3A01_P_2,
2128   EVEX_W_0F3A04_P_2,
2129   EVEX_W_0F3A05_P_2,
2130   EVEX_W_0F3A08_P_2,
2131   EVEX_W_0F3A09_P_2,
2132   EVEX_W_0F3A0A_P_2,
2133   EVEX_W_0F3A0B_P_2,
2134   EVEX_W_0F3A18_P_2,
2135   EVEX_W_0F3A19_P_2,
2136   EVEX_W_0F3A1A_P_2,
2137   EVEX_W_0F3A1B_P_2,
2138   EVEX_W_0F3A1D_P_2,
2139   EVEX_W_0F3A21_P_2,
2140   EVEX_W_0F3A23_P_2,
2141   EVEX_W_0F3A38_P_2,
2142   EVEX_W_0F3A39_P_2,
2143   EVEX_W_0F3A3A_P_2,
2144   EVEX_W_0F3A3B_P_2,
2145   EVEX_W_0F3A43_P_2,
2146 };
2147
2148 typedef void (*op_rtn) (int bytemode, int sizeflag);
2149
2150 struct dis386 {
2151   const char *name;
2152   struct
2153     {
2154       op_rtn rtn;
2155       int bytemode;
2156     } op[MAX_OPERANDS];
2157 };
2158
2159 /* Upper case letters in the instruction names here are macros.
2160    'A' => print 'b' if no register operands or suffix_always is true
2161    'B' => print 'b' if suffix_always is true
2162    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2163           size prefix
2164    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2165           suffix_always is true
2166    'E' => print 'e' if 32-bit form of jcxz
2167    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2168    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2169    'H' => print ",pt" or ",pn" branch hint
2170    'I' => honor following macro letter even in Intel mode (implemented only
2171           for some of the macro letters)
2172    'J' => print 'l'
2173    'K' => print 'd' or 'q' if rex prefix is present.
2174    'L' => print 'l' if suffix_always is true
2175    'M' => print 'r' if intel_mnemonic is false.
2176    'N' => print 'n' if instruction has no wait "prefix"
2177    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2178    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2179           or suffix_always is true.  print 'q' if rex prefix is present.
2180    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2181           is true
2182    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2183    'S' => print 'w', 'l' or 'q' if suffix_always is true
2184    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2185    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2186    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2187    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2188    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2189    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2190           suffix_always is true.
2191    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2192    '!' => change condition from true to false or from false to true.
2193    '%' => add 1 upper case letter to the macro.
2194
2195    2 upper case letter macros:
2196    "XY" => print 'x' or 'y' if no register operands or suffix_always
2197            is true.
2198    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2199    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2200            or suffix_always is true
2201    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2202    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2203    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2204    "LW" => print 'd', 'q' depending on the VEX.W bit
2205
2206    Many of the above letters print nothing in Intel mode.  See "putop"
2207    for the details.
2208
2209    Braces '{' and '}', and vertical bars '|', indicate alternative
2210    mnemonic strings for AT&T and Intel.  */
2211
2212 static const struct dis386 dis386[] = {
2213   /* 00 */
2214   { "addB",             { Ebh1, Gb } },
2215   { "addS",             { Evh1, Gv } },
2216   { "addB",             { Gb, EbS } },
2217   { "addS",             { Gv, EvS } },
2218   { "addB",             { AL, Ib } },
2219   { "addS",             { eAX, Iv } },
2220   { X86_64_TABLE (X86_64_06) },
2221   { X86_64_TABLE (X86_64_07) },
2222   /* 08 */
2223   { "orB",              { Ebh1, Gb } },
2224   { "orS",              { Evh1, Gv } },
2225   { "orB",              { Gb, EbS } },
2226   { "orS",              { Gv, EvS } },
2227   { "orB",              { AL, Ib } },
2228   { "orS",              { eAX, Iv } },
2229   { X86_64_TABLE (X86_64_0D) },
2230   { Bad_Opcode },       /* 0x0f extended opcode escape */
2231   /* 10 */
2232   { "adcB",             { Ebh1, Gb } },
2233   { "adcS",             { Evh1, Gv } },
2234   { "adcB",             { Gb, EbS } },
2235   { "adcS",             { Gv, EvS } },
2236   { "adcB",             { AL, Ib } },
2237   { "adcS",             { eAX, Iv } },
2238   { X86_64_TABLE (X86_64_16) },
2239   { X86_64_TABLE (X86_64_17) },
2240   /* 18 */
2241   { "sbbB",             { Ebh1, Gb } },
2242   { "sbbS",             { Evh1, Gv } },
2243   { "sbbB",             { Gb, EbS } },
2244   { "sbbS",             { Gv, EvS } },
2245   { "sbbB",             { AL, Ib } },
2246   { "sbbS",             { eAX, Iv } },
2247   { X86_64_TABLE (X86_64_1E) },
2248   { X86_64_TABLE (X86_64_1F) },
2249   /* 20 */
2250   { "andB",             { Ebh1, Gb } },
2251   { "andS",             { Evh1, Gv } },
2252   { "andB",             { Gb, EbS } },
2253   { "andS",             { Gv, EvS } },
2254   { "andB",             { AL, Ib } },
2255   { "andS",             { eAX, Iv } },
2256   { Bad_Opcode },       /* SEG ES prefix */
2257   { X86_64_TABLE (X86_64_27) },
2258   /* 28 */
2259   { "subB",             { Ebh1, Gb } },
2260   { "subS",             { Evh1, Gv } },
2261   { "subB",             { Gb, EbS } },
2262   { "subS",             { Gv, EvS } },
2263   { "subB",             { AL, Ib } },
2264   { "subS",             { eAX, Iv } },
2265   { Bad_Opcode },       /* SEG CS prefix */
2266   { X86_64_TABLE (X86_64_2F) },
2267   /* 30 */
2268   { "xorB",             { Ebh1, Gb } },
2269   { "xorS",             { Evh1, Gv } },
2270   { "xorB",             { Gb, EbS } },
2271   { "xorS",             { Gv, EvS } },
2272   { "xorB",             { AL, Ib } },
2273   { "xorS",             { eAX, Iv } },
2274   { Bad_Opcode },       /* SEG SS prefix */
2275   { X86_64_TABLE (X86_64_37) },
2276   /* 38 */
2277   { "cmpB",             { Eb, Gb } },
2278   { "cmpS",             { Ev, Gv } },
2279   { "cmpB",             { Gb, EbS } },
2280   { "cmpS",             { Gv, EvS } },
2281   { "cmpB",             { AL, Ib } },
2282   { "cmpS",             { eAX, Iv } },
2283   { Bad_Opcode },       /* SEG DS prefix */
2284   { X86_64_TABLE (X86_64_3F) },
2285   /* 40 */
2286   { "inc{S|}",          { RMeAX } },
2287   { "inc{S|}",          { RMeCX } },
2288   { "inc{S|}",          { RMeDX } },
2289   { "inc{S|}",          { RMeBX } },
2290   { "inc{S|}",          { RMeSP } },
2291   { "inc{S|}",          { RMeBP } },
2292   { "inc{S|}",          { RMeSI } },
2293   { "inc{S|}",          { RMeDI } },
2294   /* 48 */
2295   { "dec{S|}",          { RMeAX } },
2296   { "dec{S|}",          { RMeCX } },
2297   { "dec{S|}",          { RMeDX } },
2298   { "dec{S|}",          { RMeBX } },
2299   { "dec{S|}",          { RMeSP } },
2300   { "dec{S|}",          { RMeBP } },
2301   { "dec{S|}",          { RMeSI } },
2302   { "dec{S|}",          { RMeDI } },
2303   /* 50 */
2304   { "pushV",            { RMrAX } },
2305   { "pushV",            { RMrCX } },
2306   { "pushV",            { RMrDX } },
2307   { "pushV",            { RMrBX } },
2308   { "pushV",            { RMrSP } },
2309   { "pushV",            { RMrBP } },
2310   { "pushV",            { RMrSI } },
2311   { "pushV",            { RMrDI } },
2312   /* 58 */
2313   { "popV",             { RMrAX } },
2314   { "popV",             { RMrCX } },
2315   { "popV",             { RMrDX } },
2316   { "popV",             { RMrBX } },
2317   { "popV",             { RMrSP } },
2318   { "popV",             { RMrBP } },
2319   { "popV",             { RMrSI } },
2320   { "popV",             { RMrDI } },
2321   /* 60 */
2322   { X86_64_TABLE (X86_64_60) },
2323   { X86_64_TABLE (X86_64_61) },
2324   { X86_64_TABLE (X86_64_62) },
2325   { X86_64_TABLE (X86_64_63) },
2326   { Bad_Opcode },       /* seg fs */
2327   { Bad_Opcode },       /* seg gs */
2328   { Bad_Opcode },       /* op size prefix */
2329   { Bad_Opcode },       /* adr size prefix */
2330   /* 68 */
2331   { "pushT",            { sIv } },
2332   { "imulS",            { Gv, Ev, Iv } },
2333   { "pushT",            { sIbT } },
2334   { "imulS",            { Gv, Ev, sIb } },
2335   { "ins{b|}",          { Ybr, indirDX } },
2336   { X86_64_TABLE (X86_64_6D) },
2337   { "outs{b|}",         { indirDXr, Xb } },
2338   { X86_64_TABLE (X86_64_6F) },
2339   /* 70 */
2340   { "joH",              { Jb, BND, cond_jump_flag } },
2341   { "jnoH",             { Jb, BND, cond_jump_flag } },
2342   { "jbH",              { Jb, BND, cond_jump_flag } },
2343   { "jaeH",             { Jb, BND, cond_jump_flag } },
2344   { "jeH",              { Jb, BND, cond_jump_flag } },
2345   { "jneH",             { Jb, BND, cond_jump_flag } },
2346   { "jbeH",             { Jb, BND, cond_jump_flag } },
2347   { "jaH",              { Jb, BND, cond_jump_flag } },
2348   /* 78 */
2349   { "jsH",              { Jb, BND, cond_jump_flag } },
2350   { "jnsH",             { Jb, BND, cond_jump_flag } },
2351   { "jpH",              { Jb, BND, cond_jump_flag } },
2352   { "jnpH",             { Jb, BND, cond_jump_flag } },
2353   { "jlH",              { Jb, BND, cond_jump_flag } },
2354   { "jgeH",             { Jb, BND, cond_jump_flag } },
2355   { "jleH",             { Jb, BND, cond_jump_flag } },
2356   { "jgH",              { Jb, BND, cond_jump_flag } },
2357   /* 80 */
2358   { REG_TABLE (REG_80) },
2359   { REG_TABLE (REG_81) },
2360   { Bad_Opcode },
2361   { REG_TABLE (REG_82) },
2362   { "testB",            { Eb, Gb } },
2363   { "testS",            { Ev, Gv } },
2364   { "xchgB",            { Ebh2, Gb } },
2365   { "xchgS",            { Evh2, Gv } },
2366   /* 88 */
2367   { "movB",             { Ebh3, Gb } },
2368   { "movS",             { Evh3, Gv } },
2369   { "movB",             { Gb, EbS } },
2370   { "movS",             { Gv, EvS } },
2371   { "movD",             { Sv, Sw } },
2372   { MOD_TABLE (MOD_8D) },
2373   { "movD",             { Sw, Sv } },
2374   { REG_TABLE (REG_8F) },
2375   /* 90 */
2376   { PREFIX_TABLE (PREFIX_90) },
2377   { "xchgS",            { RMeCX, eAX } },
2378   { "xchgS",            { RMeDX, eAX } },
2379   { "xchgS",            { RMeBX, eAX } },
2380   { "xchgS",            { RMeSP, eAX } },
2381   { "xchgS",            { RMeBP, eAX } },
2382   { "xchgS",            { RMeSI, eAX } },
2383   { "xchgS",            { RMeDI, eAX } },
2384   /* 98 */
2385   { "cW{t|}R",          { XX } },
2386   { "cR{t|}O",          { XX } },
2387   { X86_64_TABLE (X86_64_9A) },
2388   { Bad_Opcode },       /* fwait */
2389   { "pushfT",           { XX } },
2390   { "popfT",            { XX } },
2391   { "sahf",             { XX } },
2392   { "lahf",             { XX } },
2393   /* a0 */
2394   { "mov%LB",           { AL, Ob } },
2395   { "mov%LS",           { eAX, Ov } },
2396   { "mov%LB",           { Ob, AL } },
2397   { "mov%LS",           { Ov, eAX } },
2398   { "movs{b|}",         { Ybr, Xb } },
2399   { "movs{R|}",         { Yvr, Xv } },
2400   { "cmps{b|}",         { Xb, Yb } },
2401   { "cmps{R|}",         { Xv, Yv } },
2402   /* a8 */
2403   { "testB",            { AL, Ib } },
2404   { "testS",            { eAX, Iv } },
2405   { "stosB",            { Ybr, AL } },
2406   { "stosS",            { Yvr, eAX } },
2407   { "lodsB",            { ALr, Xb } },
2408   { "lodsS",            { eAXr, Xv } },
2409   { "scasB",            { AL, Yb } },
2410   { "scasS",            { eAX, Yv } },
2411   /* b0 */
2412   { "movB",             { RMAL, Ib } },
2413   { "movB",             { RMCL, Ib } },
2414   { "movB",             { RMDL, Ib } },
2415   { "movB",             { RMBL, Ib } },
2416   { "movB",             { RMAH, Ib } },
2417   { "movB",             { RMCH, Ib } },
2418   { "movB",             { RMDH, Ib } },
2419   { "movB",             { RMBH, Ib } },
2420   /* b8 */
2421   { "mov%LV",           { RMeAX, Iv64 } },
2422   { "mov%LV",           { RMeCX, Iv64 } },
2423   { "mov%LV",           { RMeDX, Iv64 } },
2424   { "mov%LV",           { RMeBX, Iv64 } },
2425   { "mov%LV",           { RMeSP, Iv64 } },
2426   { "mov%LV",           { RMeBP, Iv64 } },
2427   { "mov%LV",           { RMeSI, Iv64 } },
2428   { "mov%LV",           { RMeDI, Iv64 } },
2429   /* c0 */
2430   { REG_TABLE (REG_C0) },
2431   { REG_TABLE (REG_C1) },
2432   { "retT",             { Iw, BND } },
2433   { "retT",             { BND } },
2434   { X86_64_TABLE (X86_64_C4) },
2435   { X86_64_TABLE (X86_64_C5) },
2436   { REG_TABLE (REG_C6) },
2437   { REG_TABLE (REG_C7) },
2438   /* c8 */
2439   { "enterT",           { Iw, Ib } },
2440   { "leaveT",           { XX } },
2441   { "Jret{|f}P",        { Iw } },
2442   { "Jret{|f}P",        { XX } },
2443   { "int3",             { XX } },
2444   { "int",              { Ib } },
2445   { X86_64_TABLE (X86_64_CE) },
2446   { "iretP",            { XX } },
2447   /* d0 */
2448   { REG_TABLE (REG_D0) },
2449   { REG_TABLE (REG_D1) },
2450   { REG_TABLE (REG_D2) },
2451   { REG_TABLE (REG_D3) },
2452   { X86_64_TABLE (X86_64_D4) },
2453   { X86_64_TABLE (X86_64_D5) },
2454   { Bad_Opcode },
2455   { "xlat",             { DSBX } },
2456   /* d8 */
2457   { FLOAT },
2458   { FLOAT },
2459   { FLOAT },
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   { FLOAT },
2465   /* e0 */
2466   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2467   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2468   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2469   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2470   { "inB",              { AL, Ib } },
2471   { "inG",              { zAX, Ib } },
2472   { "outB",             { Ib, AL } },
2473   { "outG",             { Ib, zAX } },
2474   /* e8 */
2475   { "callT",            { Jv, BND } },
2476   { "jmpT",             { Jv, BND } },
2477   { X86_64_TABLE (X86_64_EA) },
2478   { "jmp",              { Jb, BND } },
2479   { "inB",              { AL, indirDX } },
2480   { "inG",              { zAX, indirDX } },
2481   { "outB",             { indirDX, AL } },
2482   { "outG",             { indirDX, zAX } },
2483   /* f0 */
2484   { Bad_Opcode },       /* lock prefix */
2485   { "icebp",            { XX } },
2486   { Bad_Opcode },       /* repne */
2487   { Bad_Opcode },       /* repz */
2488   { "hlt",              { XX } },
2489   { "cmc",              { XX } },
2490   { REG_TABLE (REG_F6) },
2491   { REG_TABLE (REG_F7) },
2492   /* f8 */
2493   { "clc",              { XX } },
2494   { "stc",              { XX } },
2495   { "cli",              { XX } },
2496   { "sti",              { XX } },
2497   { "cld",              { XX } },
2498   { "std",              { XX } },
2499   { REG_TABLE (REG_FE) },
2500   { REG_TABLE (REG_FF) },
2501 };
2502
2503 static const struct dis386 dis386_twobyte[] = {
2504   /* 00 */
2505   { REG_TABLE (REG_0F00 ) },
2506   { REG_TABLE (REG_0F01 ) },
2507   { "larS",             { Gv, Ew } },
2508   { "lslS",             { Gv, Ew } },
2509   { Bad_Opcode },
2510   { "syscall",          { XX } },
2511   { "clts",             { XX } },
2512   { "sysretP",          { XX } },
2513   /* 08 */
2514   { "invd",             { XX } },
2515   { "wbinvd",           { XX } },
2516   { Bad_Opcode },
2517   { "ud2",              { XX } },
2518   { Bad_Opcode },
2519   { REG_TABLE (REG_0F0D) },
2520   { "femms",            { XX } },
2521   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2522   /* 10 */
2523   { PREFIX_TABLE (PREFIX_0F10) },
2524   { PREFIX_TABLE (PREFIX_0F11) },
2525   { PREFIX_TABLE (PREFIX_0F12) },
2526   { MOD_TABLE (MOD_0F13) },
2527   { "unpcklpX",         { XM, EXx } },
2528   { "unpckhpX",         { XM, EXx } },
2529   { PREFIX_TABLE (PREFIX_0F16) },
2530   { MOD_TABLE (MOD_0F17) },
2531   /* 18 */
2532   { REG_TABLE (REG_0F18) },
2533   { "nopQ",             { Ev } },
2534   { PREFIX_TABLE (PREFIX_0F1A) },
2535   { PREFIX_TABLE (PREFIX_0F1B) },
2536   { "nopQ",             { Ev } },
2537   { "nopQ",             { Ev } },
2538   { "nopQ",             { Ev } },
2539   { "nopQ",             { Ev } },
2540   /* 20 */
2541   { MOD_TABLE (MOD_0F20) },
2542   { MOD_TABLE (MOD_0F21) },
2543   { MOD_TABLE (MOD_0F22) },
2544   { MOD_TABLE (MOD_0F23) },
2545   { MOD_TABLE (MOD_0F24) },
2546   { Bad_Opcode },
2547   { MOD_TABLE (MOD_0F26) },
2548   { Bad_Opcode },
2549   /* 28 */
2550   { "movapX",           { XM, EXx } },
2551   { "movapX",           { EXxS, XM } },
2552   { PREFIX_TABLE (PREFIX_0F2A) },
2553   { PREFIX_TABLE (PREFIX_0F2B) },
2554   { PREFIX_TABLE (PREFIX_0F2C) },
2555   { PREFIX_TABLE (PREFIX_0F2D) },
2556   { PREFIX_TABLE (PREFIX_0F2E) },
2557   { PREFIX_TABLE (PREFIX_0F2F) },
2558   /* 30 */
2559   { "wrmsr",            { XX } },
2560   { "rdtsc",            { XX } },
2561   { "rdmsr",            { XX } },
2562   { "rdpmc",            { XX } },
2563   { "sysenter",         { XX } },
2564   { "sysexit",          { XX } },
2565   { Bad_Opcode },
2566   { "getsec",           { XX } },
2567   /* 38 */
2568   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2569   { Bad_Opcode },
2570   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2571   { Bad_Opcode },
2572   { Bad_Opcode },
2573   { Bad_Opcode },
2574   { Bad_Opcode },
2575   { Bad_Opcode },
2576   /* 40 */
2577   { "cmovoS",           { Gv, Ev } },
2578   { "cmovnoS",          { Gv, Ev } },
2579   { "cmovbS",           { Gv, Ev } },
2580   { "cmovaeS",          { Gv, Ev } },
2581   { "cmoveS",           { Gv, Ev } },
2582   { "cmovneS",          { Gv, Ev } },
2583   { "cmovbeS",          { Gv, Ev } },
2584   { "cmovaS",           { Gv, Ev } },
2585   /* 48 */
2586   { "cmovsS",           { Gv, Ev } },
2587   { "cmovnsS",          { Gv, Ev } },
2588   { "cmovpS",           { Gv, Ev } },
2589   { "cmovnpS",          { Gv, Ev } },
2590   { "cmovlS",           { Gv, Ev } },
2591   { "cmovgeS",          { Gv, Ev } },
2592   { "cmovleS",          { Gv, Ev } },
2593   { "cmovgS",           { Gv, Ev } },
2594   /* 50 */
2595   { MOD_TABLE (MOD_0F51) },
2596   { PREFIX_TABLE (PREFIX_0F51) },
2597   { PREFIX_TABLE (PREFIX_0F52) },
2598   { PREFIX_TABLE (PREFIX_0F53) },
2599   { "andpX",            { XM, EXx } },
2600   { "andnpX",           { XM, EXx } },
2601   { "orpX",             { XM, EXx } },
2602   { "xorpX",            { XM, EXx } },
2603   /* 58 */
2604   { PREFIX_TABLE (PREFIX_0F58) },
2605   { PREFIX_TABLE (PREFIX_0F59) },
2606   { PREFIX_TABLE (PREFIX_0F5A) },
2607   { PREFIX_TABLE (PREFIX_0F5B) },
2608   { PREFIX_TABLE (PREFIX_0F5C) },
2609   { PREFIX_TABLE (PREFIX_0F5D) },
2610   { PREFIX_TABLE (PREFIX_0F5E) },
2611   { PREFIX_TABLE (PREFIX_0F5F) },
2612   /* 60 */
2613   { PREFIX_TABLE (PREFIX_0F60) },
2614   { PREFIX_TABLE (PREFIX_0F61) },
2615   { PREFIX_TABLE (PREFIX_0F62) },
2616   { "packsswb",         { MX, EM } },
2617   { "pcmpgtb",          { MX, EM } },
2618   { "pcmpgtw",          { MX, EM } },
2619   { "pcmpgtd",          { MX, EM } },
2620   { "packuswb",         { MX, EM } },
2621   /* 68 */
2622   { "punpckhbw",        { MX, EM } },
2623   { "punpckhwd",        { MX, EM } },
2624   { "punpckhdq",        { MX, EM } },
2625   { "packssdw",         { MX, EM } },
2626   { PREFIX_TABLE (PREFIX_0F6C) },
2627   { PREFIX_TABLE (PREFIX_0F6D) },
2628   { "movK",             { MX, Edq } },
2629   { PREFIX_TABLE (PREFIX_0F6F) },
2630   /* 70 */
2631   { PREFIX_TABLE (PREFIX_0F70) },
2632   { REG_TABLE (REG_0F71) },
2633   { REG_TABLE (REG_0F72) },
2634   { REG_TABLE (REG_0F73) },
2635   { "pcmpeqb",          { MX, EM } },
2636   { "pcmpeqw",          { MX, EM } },
2637   { "pcmpeqd",          { MX, EM } },
2638   { "emms",             { XX } },
2639   /* 78 */
2640   { PREFIX_TABLE (PREFIX_0F78) },
2641   { PREFIX_TABLE (PREFIX_0F79) },
2642   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2643   { Bad_Opcode },
2644   { PREFIX_TABLE (PREFIX_0F7C) },
2645   { PREFIX_TABLE (PREFIX_0F7D) },
2646   { PREFIX_TABLE (PREFIX_0F7E) },
2647   { PREFIX_TABLE (PREFIX_0F7F) },
2648   /* 80 */
2649   { "joH",              { Jv, BND, cond_jump_flag } },
2650   { "jnoH",             { Jv, BND, cond_jump_flag } },
2651   { "jbH",              { Jv, BND, cond_jump_flag } },
2652   { "jaeH",             { Jv, BND, cond_jump_flag } },
2653   { "jeH",              { Jv, BND, cond_jump_flag } },
2654   { "jneH",             { Jv, BND, cond_jump_flag } },
2655   { "jbeH",             { Jv, BND, cond_jump_flag } },
2656   { "jaH",              { Jv, BND, cond_jump_flag } },
2657   /* 88 */
2658   { "jsH",              { Jv, BND, cond_jump_flag } },
2659   { "jnsH",             { Jv, BND, cond_jump_flag } },
2660   { "jpH",              { Jv, BND, cond_jump_flag } },
2661   { "jnpH",             { Jv, BND, cond_jump_flag } },
2662   { "jlH",              { Jv, BND, cond_jump_flag } },
2663   { "jgeH",             { Jv, BND, cond_jump_flag } },
2664   { "jleH",             { Jv, BND, cond_jump_flag } },
2665   { "jgH",              { Jv, BND, cond_jump_flag } },
2666   /* 90 */
2667   { "seto",             { Eb } },
2668   { "setno",            { Eb } },
2669   { "setb",             { Eb } },
2670   { "setae",            { Eb } },
2671   { "sete",             { Eb } },
2672   { "setne",            { Eb } },
2673   { "setbe",            { Eb } },
2674   { "seta",             { Eb } },
2675   /* 98 */
2676   { "sets",             { Eb } },
2677   { "setns",            { Eb } },
2678   { "setp",             { Eb } },
2679   { "setnp",            { Eb } },
2680   { "setl",             { Eb } },
2681   { "setge",            { Eb } },
2682   { "setle",            { Eb } },
2683   { "setg",             { Eb } },
2684   /* a0 */
2685   { "pushT",            { fs } },
2686   { "popT",             { fs } },
2687   { "cpuid",            { XX } },
2688   { "btS",              { Ev, Gv } },
2689   { "shldS",            { Ev, Gv, Ib } },
2690   { "shldS",            { Ev, Gv, CL } },
2691   { REG_TABLE (REG_0FA6) },
2692   { REG_TABLE (REG_0FA7) },
2693   /* a8 */
2694   { "pushT",            { gs } },
2695   { "popT",             { gs } },
2696   { "rsm",              { XX } },
2697   { "btsS",             { Evh1, Gv } },
2698   { "shrdS",            { Ev, Gv, Ib } },
2699   { "shrdS",            { Ev, Gv, CL } },
2700   { REG_TABLE (REG_0FAE) },
2701   { "imulS",            { Gv, Ev } },
2702   /* b0 */
2703   { "cmpxchgB",         { Ebh1, Gb } },
2704   { "cmpxchgS",         { Evh1, Gv } },
2705   { MOD_TABLE (MOD_0FB2) },
2706   { "btrS",             { Evh1, Gv } },
2707   { MOD_TABLE (MOD_0FB4) },
2708   { MOD_TABLE (MOD_0FB5) },
2709   { "movz{bR|x}",       { Gv, Eb } },
2710   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2711   /* b8 */
2712   { PREFIX_TABLE (PREFIX_0FB8) },
2713   { "ud1",              { XX } },
2714   { REG_TABLE (REG_0FBA) },
2715   { "btcS",             { Evh1, Gv } },
2716   { PREFIX_TABLE (PREFIX_0FBC) },
2717   { PREFIX_TABLE (PREFIX_0FBD) },
2718   { "movs{bR|x}",       { Gv, Eb } },
2719   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2720   /* c0 */
2721   { "xaddB",            { Ebh1, Gb } },
2722   { "xaddS",            { Evh1, Gv } },
2723   { PREFIX_TABLE (PREFIX_0FC2) },
2724   { PREFIX_TABLE (PREFIX_0FC3) },
2725   { "pinsrw",           { MX, Edqw, Ib } },
2726   { "pextrw",           { Gdq, MS, Ib } },
2727   { "shufpX",           { XM, EXx, Ib } },
2728   { REG_TABLE (REG_0FC7) },
2729   /* c8 */
2730   { "bswap",            { RMeAX } },
2731   { "bswap",            { RMeCX } },
2732   { "bswap",            { RMeDX } },
2733   { "bswap",            { RMeBX } },
2734   { "bswap",            { RMeSP } },
2735   { "bswap",            { RMeBP } },
2736   { "bswap",            { RMeSI } },
2737   { "bswap",            { RMeDI } },
2738   /* d0 */
2739   { PREFIX_TABLE (PREFIX_0FD0) },
2740   { "psrlw",            { MX, EM } },
2741   { "psrld",            { MX, EM } },
2742   { "psrlq",            { MX, EM } },
2743   { "paddq",            { MX, EM } },
2744   { "pmullw",           { MX, EM } },
2745   { PREFIX_TABLE (PREFIX_0FD6) },
2746   { MOD_TABLE (MOD_0FD7) },
2747   /* d8 */
2748   { "psubusb",          { MX, EM } },
2749   { "psubusw",          { MX, EM } },
2750   { "pminub",           { MX, EM } },
2751   { "pand",             { MX, EM } },
2752   { "paddusb",          { MX, EM } },
2753   { "paddusw",          { MX, EM } },
2754   { "pmaxub",           { MX, EM } },
2755   { "pandn",            { MX, EM } },
2756   /* e0 */
2757   { "pavgb",            { MX, EM } },
2758   { "psraw",            { MX, EM } },
2759   { "psrad",            { MX, EM } },
2760   { "pavgw",            { MX, EM } },
2761   { "pmulhuw",          { MX, EM } },
2762   { "pmulhw",           { MX, EM } },
2763   { PREFIX_TABLE (PREFIX_0FE6) },
2764   { PREFIX_TABLE (PREFIX_0FE7) },
2765   /* e8 */
2766   { "psubsb",           { MX, EM } },
2767   { "psubsw",           { MX, EM } },
2768   { "pminsw",           { MX, EM } },
2769   { "por",              { MX, EM } },
2770   { "paddsb",           { MX, EM } },
2771   { "paddsw",           { MX, EM } },
2772   { "pmaxsw",           { MX, EM } },
2773   { "pxor",             { MX, EM } },
2774   /* f0 */
2775   { PREFIX_TABLE (PREFIX_0FF0) },
2776   { "psllw",            { MX, EM } },
2777   { "pslld",            { MX, EM } },
2778   { "psllq",            { MX, EM } },
2779   { "pmuludq",          { MX, EM } },
2780   { "pmaddwd",          { MX, EM } },
2781   { "psadbw",           { MX, EM } },
2782   { PREFIX_TABLE (PREFIX_0FF7) },
2783   /* f8 */
2784   { "psubb",            { MX, EM } },
2785   { "psubw",            { MX, EM } },
2786   { "psubd",            { MX, EM } },
2787   { "psubq",            { MX, EM } },
2788   { "paddb",            { MX, EM } },
2789   { "paddw",            { MX, EM } },
2790   { "paddd",            { MX, EM } },
2791   { Bad_Opcode },
2792 };
2793
2794 static const unsigned char onebyte_has_modrm[256] = {
2795   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2796   /*       -------------------------------        */
2797   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2798   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2799   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2800   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2801   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2802   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2803   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2804   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2805   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2806   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2807   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2808   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2809   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2810   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2811   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2812   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2813   /*       -------------------------------        */
2814   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2815 };
2816
2817 static const unsigned char twobyte_has_modrm[256] = {
2818   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2819   /*       -------------------------------        */
2820   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2821   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2822   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2823   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2824   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2825   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2826   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2827   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2828   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2829   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2830   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2831   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2832   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2833   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2834   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2835   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2836   /*       -------------------------------        */
2837   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2838 };
2839
2840 static char obuf[100];
2841 static char *obufp;
2842 static char *mnemonicendp;
2843 static char scratchbuf[100];
2844 static unsigned char *start_codep;
2845 static unsigned char *insn_codep;
2846 static unsigned char *codep;
2847 static int last_lock_prefix;
2848 static int last_repz_prefix;
2849 static int last_repnz_prefix;
2850 static int last_data_prefix;
2851 static int last_addr_prefix;
2852 static int last_rex_prefix;
2853 static int last_seg_prefix;
2854 #define MAX_CODE_LENGTH 15
2855 /* We can up to 14 prefixes since the maximum instruction length is
2856    15bytes.  */
2857 static int all_prefixes[MAX_CODE_LENGTH - 1];
2858 static disassemble_info *the_info;
2859 static struct
2860   {
2861     int mod;
2862     int reg;
2863     int rm;
2864   }
2865 modrm;
2866 static unsigned char need_modrm;
2867 static struct
2868   {
2869     int scale;
2870     int index;
2871     int base;
2872   }
2873 sib;
2874 static struct
2875   {
2876     int register_specifier;
2877     int length;
2878     int prefix;
2879     int w;
2880     int evex;
2881     int r;
2882     int v;
2883     int mask_register_specifier;
2884     int zeroing;
2885     int ll;
2886     int b;
2887   }
2888 vex;
2889 static unsigned char need_vex;
2890 static unsigned char need_vex_reg;
2891 static unsigned char vex_w_done;
2892
2893 struct op
2894   {
2895     const char *name;
2896     unsigned int len;
2897   };
2898
2899 /* If we are accessing mod/rm/reg without need_modrm set, then the
2900    values are stale.  Hitting this abort likely indicates that you
2901    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2902 #define MODRM_CHECK  if (!need_modrm) abort ()
2903
2904 static const char **names64;
2905 static const char **names32;
2906 static const char **names16;
2907 static const char **names8;
2908 static const char **names8rex;
2909 static const char **names_seg;
2910 static const char *index64;
2911 static const char *index32;
2912 static const char **index16;
2913 static const char **names_bnd;
2914
2915 static const char *intel_names64[] = {
2916   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2917   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2918 };
2919 static const char *intel_names32[] = {
2920   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2921   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2922 };
2923 static const char *intel_names16[] = {
2924   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2925   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2926 };
2927 static const char *intel_names8[] = {
2928   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2929 };
2930 static const char *intel_names8rex[] = {
2931   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2932   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2933 };
2934 static const char *intel_names_seg[] = {
2935   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2936 };
2937 static const char *intel_index64 = "riz";
2938 static const char *intel_index32 = "eiz";
2939 static const char *intel_index16[] = {
2940   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2941 };
2942
2943 static const char *att_names64[] = {
2944   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2945   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2946 };
2947 static const char *att_names32[] = {
2948   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2949   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2950 };
2951 static const char *att_names16[] = {
2952   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2953   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2954 };
2955 static const char *att_names8[] = {
2956   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2957 };
2958 static const char *att_names8rex[] = {
2959   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2960   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2961 };
2962 static const char *att_names_seg[] = {
2963   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2964 };
2965 static const char *att_index64 = "%riz";
2966 static const char *att_index32 = "%eiz";
2967 static const char *att_index16[] = {
2968   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2969 };
2970
2971 static const char **names_mm;
2972 static const char *intel_names_mm[] = {
2973   "mm0", "mm1", "mm2", "mm3",
2974   "mm4", "mm5", "mm6", "mm7"
2975 };
2976 static const char *att_names_mm[] = {
2977   "%mm0", "%mm1", "%mm2", "%mm3",
2978   "%mm4", "%mm5", "%mm6", "%mm7"
2979 };
2980
2981 static const char *intel_names_bnd[] = {
2982   "bnd0", "bnd1", "bnd2", "bnd3"
2983 };
2984
2985 static const char *att_names_bnd[] = {
2986   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2987 };
2988
2989 static const char **names_xmm;
2990 static const char *intel_names_xmm[] = {
2991   "xmm0", "xmm1", "xmm2", "xmm3",
2992   "xmm4", "xmm5", "xmm6", "xmm7",
2993   "xmm8", "xmm9", "xmm10", "xmm11",
2994   "xmm12", "xmm13", "xmm14", "xmm15",
2995   "xmm16", "xmm17", "xmm18", "xmm19",
2996   "xmm20", "xmm21", "xmm22", "xmm23",
2997   "xmm24", "xmm25", "xmm26", "xmm27",
2998   "xmm28", "xmm29", "xmm30", "xmm31"
2999 };
3000 static const char *att_names_xmm[] = {
3001   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3002   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3003   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3004   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3005   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3006   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3007   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3008   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3009 };
3010
3011 static const char **names_ymm;
3012 static const char *intel_names_ymm[] = {
3013   "ymm0", "ymm1", "ymm2", "ymm3",
3014   "ymm4", "ymm5", "ymm6", "ymm7",
3015   "ymm8", "ymm9", "ymm10", "ymm11",
3016   "ymm12", "ymm13", "ymm14", "ymm15",
3017   "ymm16", "ymm17", "ymm18", "ymm19",
3018   "ymm20", "ymm21", "ymm22", "ymm23",
3019   "ymm24", "ymm25", "ymm26", "ymm27",
3020   "ymm28", "ymm29", "ymm30", "ymm31"
3021 };
3022 static const char *att_names_ymm[] = {
3023   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3024   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3025   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3026   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3027   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3028   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3029   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3030   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3031 };
3032
3033 static const char **names_zmm;
3034 static const char *intel_names_zmm[] = {
3035   "zmm0", "zmm1", "zmm2", "zmm3",
3036   "zmm4", "zmm5", "zmm6", "zmm7",
3037   "zmm8", "zmm9", "zmm10", "zmm11",
3038   "zmm12", "zmm13", "zmm14", "zmm15",
3039   "zmm16", "zmm17", "zmm18", "zmm19",
3040   "zmm20", "zmm21", "zmm22", "zmm23",
3041   "zmm24", "zmm25", "zmm26", "zmm27",
3042   "zmm28", "zmm29", "zmm30", "zmm31"
3043 };
3044 static const char *att_names_zmm[] = {
3045   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3046   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3047   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3048   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3049   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3050   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3051   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3052   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3053 };
3054
3055 static const char **names_mask;
3056 static const char *intel_names_mask[] = {
3057   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3058 };
3059 static const char *att_names_mask[] = {
3060   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3061 };
3062
3063 static const char *names_rounding[] =
3064 {
3065   "{rn-sae}",
3066   "{rd-sae}",
3067   "{ru-sae}",
3068   "{rz-sae}"
3069 };
3070
3071 static const struct dis386 reg_table[][8] = {
3072   /* REG_80 */
3073   {
3074     { "addA",   { Ebh1, Ib } },
3075     { "orA",    { Ebh1, Ib } },
3076     { "adcA",   { Ebh1, Ib } },
3077     { "sbbA",   { Ebh1, Ib } },
3078     { "andA",   { Ebh1, Ib } },
3079     { "subA",   { Ebh1, Ib } },
3080     { "xorA",   { Ebh1, Ib } },
3081     { "cmpA",   { Eb, Ib } },
3082   },
3083   /* REG_81 */
3084   {
3085     { "addQ",   { Evh1, Iv } },
3086     { "orQ",    { Evh1, Iv } },
3087     { "adcQ",   { Evh1, Iv } },
3088     { "sbbQ",   { Evh1, Iv } },
3089     { "andQ",   { Evh1, Iv } },
3090     { "subQ",   { Evh1, Iv } },
3091     { "xorQ",   { Evh1, Iv } },
3092     { "cmpQ",   { Ev, Iv } },
3093   },
3094   /* REG_82 */
3095   {
3096     { "addQ",   { Evh1, sIb } },
3097     { "orQ",    { Evh1, sIb } },
3098     { "adcQ",   { Evh1, sIb } },
3099     { "sbbQ",   { Evh1, sIb } },
3100     { "andQ",   { Evh1, sIb } },
3101     { "subQ",   { Evh1, sIb } },
3102     { "xorQ",   { Evh1, sIb } },
3103     { "cmpQ",   { Ev, sIb } },
3104   },
3105   /* REG_8F */
3106   {
3107     { "popU",   { stackEv } },
3108     { XOP_8F_TABLE (XOP_09) },
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { Bad_Opcode },
3112     { XOP_8F_TABLE (XOP_09) },
3113   },
3114   /* REG_C0 */
3115   {
3116     { "rolA",   { Eb, Ib } },
3117     { "rorA",   { Eb, Ib } },
3118     { "rclA",   { Eb, Ib } },
3119     { "rcrA",   { Eb, Ib } },
3120     { "shlA",   { Eb, Ib } },
3121     { "shrA",   { Eb, Ib } },
3122     { Bad_Opcode },
3123     { "sarA",   { Eb, Ib } },
3124   },
3125   /* REG_C1 */
3126   {
3127     { "rolQ",   { Ev, Ib } },
3128     { "rorQ",   { Ev, Ib } },
3129     { "rclQ",   { Ev, Ib } },
3130     { "rcrQ",   { Ev, Ib } },
3131     { "shlQ",   { Ev, Ib } },
3132     { "shrQ",   { Ev, Ib } },
3133     { Bad_Opcode },
3134     { "sarQ",   { Ev, Ib } },
3135   },
3136   /* REG_C6 */
3137   {
3138     { "movA",   { Ebh3, Ib } },
3139     { Bad_Opcode },
3140     { Bad_Opcode },
3141     { Bad_Opcode },
3142     { Bad_Opcode },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { MOD_TABLE (MOD_C6_REG_7) },
3146   },
3147   /* REG_C7 */
3148   {
3149     { "movQ",   { Evh3, Iv } },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { Bad_Opcode },
3155     { Bad_Opcode },
3156     { MOD_TABLE (MOD_C7_REG_7) },
3157   },
3158   /* REG_D0 */
3159   {
3160     { "rolA",   { Eb, I1 } },
3161     { "rorA",   { Eb, I1 } },
3162     { "rclA",   { Eb, I1 } },
3163     { "rcrA",   { Eb, I1 } },
3164     { "shlA",   { Eb, I1 } },
3165     { "shrA",   { Eb, I1 } },
3166     { Bad_Opcode },
3167     { "sarA",   { Eb, I1 } },
3168   },
3169   /* REG_D1 */
3170   {
3171     { "rolQ",   { Ev, I1 } },
3172     { "rorQ",   { Ev, I1 } },
3173     { "rclQ",   { Ev, I1 } },
3174     { "rcrQ",   { Ev, I1 } },
3175     { "shlQ",   { Ev, I1 } },
3176     { "shrQ",   { Ev, I1 } },
3177     { Bad_Opcode },
3178     { "sarQ",   { Ev, I1 } },
3179   },
3180   /* REG_D2 */
3181   {
3182     { "rolA",   { Eb, CL } },
3183     { "rorA",   { Eb, CL } },
3184     { "rclA",   { Eb, CL } },
3185     { "rcrA",   { Eb, CL } },
3186     { "shlA",   { Eb, CL } },
3187     { "shrA",   { Eb, CL } },
3188     { Bad_Opcode },
3189     { "sarA",   { Eb, CL } },
3190   },
3191   /* REG_D3 */
3192   {
3193     { "rolQ",   { Ev, CL } },
3194     { "rorQ",   { Ev, CL } },
3195     { "rclQ",   { Ev, CL } },
3196     { "rcrQ",   { Ev, CL } },
3197     { "shlQ",   { Ev, CL } },
3198     { "shrQ",   { Ev, CL } },
3199     { Bad_Opcode },
3200     { "sarQ",   { Ev, CL } },
3201   },
3202   /* REG_F6 */
3203   {
3204     { "testA",  { Eb, Ib } },
3205     { Bad_Opcode },
3206     { "notA",   { Ebh1 } },
3207     { "negA",   { Ebh1 } },
3208     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3209     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3210     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3211     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3212   },
3213   /* REG_F7 */
3214   {
3215     { "testQ",  { Ev, Iv } },
3216     { Bad_Opcode },
3217     { "notQ",   { Evh1 } },
3218     { "negQ",   { Evh1 } },
3219     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3220     { "imulQ",  { Ev } },
3221     { "divQ",   { Ev } },
3222     { "idivQ",  { Ev } },
3223   },
3224   /* REG_FE */
3225   {
3226     { "incA",   { Ebh1 } },
3227     { "decA",   { Ebh1 } },
3228   },
3229   /* REG_FF */
3230   {
3231     { "incQ",   { Evh1 } },
3232     { "decQ",   { Evh1 } },
3233     { "call{T|}", { indirEv, BND } },
3234     { MOD_TABLE (MOD_FF_REG_3) },
3235     { "jmp{T|}", { indirEv, BND } },
3236     { MOD_TABLE (MOD_FF_REG_5) },
3237     { "pushU",  { stackEv } },
3238     { Bad_Opcode },
3239   },
3240   /* REG_0F00 */
3241   {
3242     { "sldtD",  { Sv } },
3243     { "strD",   { Sv } },
3244     { "lldt",   { Ew } },
3245     { "ltr",    { Ew } },
3246     { "verr",   { Ew } },
3247     { "verw",   { Ew } },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250   },
3251   /* REG_0F01 */
3252   {
3253     { MOD_TABLE (MOD_0F01_REG_0) },
3254     { MOD_TABLE (MOD_0F01_REG_1) },
3255     { MOD_TABLE (MOD_0F01_REG_2) },
3256     { MOD_TABLE (MOD_0F01_REG_3) },
3257     { "smswD",  { Sv } },
3258     { Bad_Opcode },
3259     { "lmsw",   { Ew } },
3260     { MOD_TABLE (MOD_0F01_REG_7) },
3261   },
3262   /* REG_0F0D */
3263   {
3264     { "prefetch",       { Mb } },
3265     { "prefetchw",      { Mb } },
3266     { "prefetchwt1",    { Mb } },
3267     { "prefetch",       { Mb } },
3268     { "prefetch",       { Mb } },
3269     { "prefetch",       { Mb } },
3270     { "prefetch",       { Mb } },
3271     { "prefetch",       { Mb } },
3272   },
3273   /* REG_0F18 */
3274   {
3275     { MOD_TABLE (MOD_0F18_REG_0) },
3276     { MOD_TABLE (MOD_0F18_REG_1) },
3277     { MOD_TABLE (MOD_0F18_REG_2) },
3278     { MOD_TABLE (MOD_0F18_REG_3) },
3279     { MOD_TABLE (MOD_0F18_REG_4) },
3280     { MOD_TABLE (MOD_0F18_REG_5) },
3281     { MOD_TABLE (MOD_0F18_REG_6) },
3282     { MOD_TABLE (MOD_0F18_REG_7) },
3283   },
3284   /* REG_0F71 */
3285   {
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_0F71_REG_2) },
3289     { Bad_Opcode },
3290     { MOD_TABLE (MOD_0F71_REG_4) },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_0F71_REG_6) },
3293   },
3294   /* REG_0F72 */
3295   {
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { MOD_TABLE (MOD_0F72_REG_2) },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_0F72_REG_4) },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_0F72_REG_6) },
3303   },
3304   /* REG_0F73 */
3305   {
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_0F73_REG_2) },
3309     { MOD_TABLE (MOD_0F73_REG_3) },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_0F73_REG_6) },
3313     { MOD_TABLE (MOD_0F73_REG_7) },
3314   },
3315   /* REG_0FA6 */
3316   {
3317     { "montmul",        { { OP_0f07, 0 } } },
3318     { "xsha1",          { { OP_0f07, 0 } } },
3319     { "xsha256",        { { OP_0f07, 0 } } },
3320   },
3321   /* REG_0FA7 */
3322   {
3323     { "xstore-rng",     { { OP_0f07, 0 } } },
3324     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3325     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3326     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3327     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3328     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3329   },
3330   /* REG_0FAE */
3331   {
3332     { MOD_TABLE (MOD_0FAE_REG_0) },
3333     { MOD_TABLE (MOD_0FAE_REG_1) },
3334     { MOD_TABLE (MOD_0FAE_REG_2) },
3335     { MOD_TABLE (MOD_0FAE_REG_3) },
3336     { MOD_TABLE (MOD_0FAE_REG_4) },
3337     { MOD_TABLE (MOD_0FAE_REG_5) },
3338     { MOD_TABLE (MOD_0FAE_REG_6) },
3339     { MOD_TABLE (MOD_0FAE_REG_7) },
3340   },
3341   /* REG_0FBA */
3342   {
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347     { "btQ",    { Ev, Ib } },
3348     { "btsQ",   { Evh1, Ib } },
3349     { "btrQ",   { Evh1, Ib } },
3350     { "btcQ",   { Evh1, Ib } },
3351   },
3352   /* REG_0FC7 */
3353   {
3354     { Bad_Opcode },
3355     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { MOD_TABLE (MOD_0FC7_REG_6) },
3361     { MOD_TABLE (MOD_0FC7_REG_7) },
3362   },
3363   /* REG_VEX_0F71 */
3364   {
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3372   },
3373   /* REG_VEX_0F72 */
3374   {
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3382   },
3383   /* REG_VEX_0F73 */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3388     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3392     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3393   },
3394   /* REG_VEX_0FAE */
3395   {
3396     { Bad_Opcode },
3397     { Bad_Opcode },
3398     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3399     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3400   },
3401   /* REG_VEX_0F38F3 */
3402   {
3403     { Bad_Opcode },
3404     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3405     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3406     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3407   },
3408   /* REG_XOP_LWPCB */
3409   {
3410     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3411     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3412   },
3413   /* REG_XOP_LWP */
3414   {
3415     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3416     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3417   },
3418   /* REG_XOP_TBM_01 */
3419   {
3420     { Bad_Opcode },
3421     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3422     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3423     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3424     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3425     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3426     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3427     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3428   },
3429   /* REG_XOP_TBM_02 */
3430   {
3431     { Bad_Opcode },
3432     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3438   },
3439 #define NEED_REG_TABLE
3440 #include "i386-dis-evex.h"
3441 #undef NEED_REG_TABLE
3442 };
3443
3444 static const struct dis386 prefix_table[][4] = {
3445   /* PREFIX_90 */
3446   {
3447     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3448     { "pause", { XX } },
3449     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3450   },
3451
3452   /* PREFIX_0F10 */
3453   {
3454     { "movups", { XM, EXx } },
3455     { "movss",  { XM, EXd } },
3456     { "movupd", { XM, EXx } },
3457     { "movsd",  { XM, EXq } },
3458   },
3459
3460   /* PREFIX_0F11 */
3461   {
3462     { "movups", { EXxS, XM } },
3463     { "movss",  { EXdS, XM } },
3464     { "movupd", { EXxS, XM } },
3465     { "movsd",  { EXqS, XM } },
3466   },
3467
3468   /* PREFIX_0F12 */
3469   {
3470     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3471     { "movsldup", { XM, EXx } },
3472     { "movlpd", { XM, EXq } },
3473     { "movddup", { XM, EXq } },
3474   },
3475
3476   /* PREFIX_0F16 */
3477   {
3478     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3479     { "movshdup", { XM, EXx } },
3480     { "movhpd", { XM, EXq } },
3481   },
3482
3483   /* PREFIX_0F1A */
3484   {
3485     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3486     { "bndcl",  { Gbnd, Ev_bnd } },
3487     { "bndmov", { Gbnd, Ebnd } },
3488     { "bndcu",  { Gbnd, Ev_bnd } },
3489   },
3490
3491   /* PREFIX_0F1B */
3492   {
3493     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3494     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3495     { "bndmov", { Ebnd, Gbnd } },
3496     { "bndcn",  { Gbnd, Ev_bnd } },
3497   },
3498
3499   /* PREFIX_0F2A */
3500   {
3501     { "cvtpi2ps", { XM, EMCq } },
3502     { "cvtsi2ss%LQ", { XM, Ev } },
3503     { "cvtpi2pd", { XM, EMCq } },
3504     { "cvtsi2sd%LQ", { XM, Ev } },
3505   },
3506
3507   /* PREFIX_0F2B */
3508   {
3509     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3510     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3511     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3512     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3513   },
3514
3515   /* PREFIX_0F2C */
3516   {
3517     { "cvttps2pi", { MXC, EXq } },
3518     { "cvttss2siY", { Gv, EXd } },
3519     { "cvttpd2pi", { MXC, EXx } },
3520     { "cvttsd2siY", { Gv, EXq } },
3521   },
3522
3523   /* PREFIX_0F2D */
3524   {
3525     { "cvtps2pi", { MXC, EXq } },
3526     { "cvtss2siY", { Gv, EXd } },
3527     { "cvtpd2pi", { MXC, EXx } },
3528     { "cvtsd2siY", { Gv, EXq } },
3529   },
3530
3531   /* PREFIX_0F2E */
3532   {
3533     { "ucomiss",{ XM, EXd } },
3534     { Bad_Opcode },
3535     { "ucomisd",{ XM, EXq } },
3536   },
3537
3538   /* PREFIX_0F2F */
3539   {
3540     { "comiss", { XM, EXd } },
3541     { Bad_Opcode },
3542     { "comisd", { XM, EXq } },
3543   },
3544
3545   /* PREFIX_0F51 */
3546   {
3547     { "sqrtps", { XM, EXx } },
3548     { "sqrtss", { XM, EXd } },
3549     { "sqrtpd", { XM, EXx } },
3550     { "sqrtsd", { XM, EXq } },
3551   },
3552
3553   /* PREFIX_0F52 */
3554   {
3555     { "rsqrtps",{ XM, EXx } },
3556     { "rsqrtss",{ XM, EXd } },
3557   },
3558
3559   /* PREFIX_0F53 */
3560   {
3561     { "rcpps",  { XM, EXx } },
3562     { "rcpss",  { XM, EXd } },
3563   },
3564
3565   /* PREFIX_0F58 */
3566   {
3567     { "addps", { XM, EXx } },
3568     { "addss", { XM, EXd } },
3569     { "addpd", { XM, EXx } },
3570     { "addsd", { XM, EXq } },
3571   },
3572
3573   /* PREFIX_0F59 */
3574   {
3575     { "mulps",  { XM, EXx } },
3576     { "mulss",  { XM, EXd } },
3577     { "mulpd",  { XM, EXx } },
3578     { "mulsd",  { XM, EXq } },
3579   },
3580
3581   /* PREFIX_0F5A */
3582   {
3583     { "cvtps2pd", { XM, EXq } },
3584     { "cvtss2sd", { XM, EXd } },
3585     { "cvtpd2ps", { XM, EXx } },
3586     { "cvtsd2ss", { XM, EXq } },
3587   },
3588
3589   /* PREFIX_0F5B */
3590   {
3591     { "cvtdq2ps", { XM, EXx } },
3592     { "cvttps2dq", { XM, EXx } },
3593     { "cvtps2dq", { XM, EXx } },
3594   },
3595
3596   /* PREFIX_0F5C */
3597   {
3598     { "subps",  { XM, EXx } },
3599     { "subss",  { XM, EXd } },
3600     { "subpd",  { XM, EXx } },
3601     { "subsd",  { XM, EXq } },
3602   },
3603
3604   /* PREFIX_0F5D */
3605   {
3606     { "minps",  { XM, EXx } },
3607     { "minss",  { XM, EXd } },
3608     { "minpd",  { XM, EXx } },
3609     { "minsd",  { XM, EXq } },
3610   },
3611
3612   /* PREFIX_0F5E */
3613   {
3614     { "divps",  { XM, EXx } },
3615     { "divss",  { XM, EXd } },
3616     { "divpd",  { XM, EXx } },
3617     { "divsd",  { XM, EXq } },
3618   },
3619
3620   /* PREFIX_0F5F */
3621   {
3622     { "maxps",  { XM, EXx } },
3623     { "maxss",  { XM, EXd } },
3624     { "maxpd",  { XM, EXx } },
3625     { "maxsd",  { XM, EXq } },
3626   },
3627
3628   /* PREFIX_0F60 */
3629   {
3630     { "punpcklbw",{ MX, EMd } },
3631     { Bad_Opcode },
3632     { "punpcklbw",{ MX, EMx } },
3633   },
3634
3635   /* PREFIX_0F61 */
3636   {
3637     { "punpcklwd",{ MX, EMd } },
3638     { Bad_Opcode },
3639     { "punpcklwd",{ MX, EMx } },
3640   },
3641
3642   /* PREFIX_0F62 */
3643   {
3644     { "punpckldq",{ MX, EMd } },
3645     { Bad_Opcode },
3646     { "punpckldq",{ MX, EMx } },
3647   },
3648
3649   /* PREFIX_0F6C */
3650   {
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { "punpcklqdq", { XM, EXx } },
3654   },
3655
3656   /* PREFIX_0F6D */
3657   {
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { "punpckhqdq", { XM, EXx } },
3661   },
3662
3663   /* PREFIX_0F6F */
3664   {
3665     { "movq",   { MX, EM } },
3666     { "movdqu", { XM, EXx } },
3667     { "movdqa", { XM, EXx } },
3668   },
3669
3670   /* PREFIX_0F70 */
3671   {
3672     { "pshufw", { MX, EM, Ib } },
3673     { "pshufhw",{ XM, EXx, Ib } },
3674     { "pshufd", { XM, EXx, Ib } },
3675     { "pshuflw",{ XM, EXx, Ib } },
3676   },
3677
3678   /* PREFIX_0F73_REG_3 */
3679   {
3680     { Bad_Opcode },
3681     { Bad_Opcode },
3682     { "psrldq", { XS, Ib } },
3683   },
3684
3685   /* PREFIX_0F73_REG_7 */
3686   {
3687     { Bad_Opcode },
3688     { Bad_Opcode },
3689     { "pslldq", { XS, Ib } },
3690   },
3691
3692   /* PREFIX_0F78 */
3693   {
3694     {"vmread",  { Em, Gm } },
3695     { Bad_Opcode },
3696     {"extrq",   { XS, Ib, Ib } },
3697     {"insertq", { XM, XS, Ib, Ib } },
3698   },
3699
3700   /* PREFIX_0F79 */
3701   {
3702     {"vmwrite", { Gm, Em } },
3703     { Bad_Opcode },
3704     {"extrq",   { XM, XS } },
3705     {"insertq", { XM, XS } },
3706   },
3707
3708   /* PREFIX_0F7C */
3709   {
3710     { Bad_Opcode },
3711     { Bad_Opcode },
3712     { "haddpd", { XM, EXx } },
3713     { "haddps", { XM, EXx } },
3714   },
3715
3716   /* PREFIX_0F7D */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { "hsubpd", { XM, EXx } },
3721     { "hsubps", { XM, EXx } },
3722   },
3723
3724   /* PREFIX_0F7E */
3725   {
3726     { "movK",   { Edq, MX } },
3727     { "movq",   { XM, EXq } },
3728     { "movK",   { Edq, XM } },
3729   },
3730
3731   /* PREFIX_0F7F */
3732   {
3733     { "movq",   { EMS, MX } },
3734     { "movdqu", { EXxS, XM } },
3735     { "movdqa", { EXxS, XM } },
3736   },
3737
3738   /* PREFIX_0FAE_REG_0 */
3739   {
3740     { Bad_Opcode },
3741     { "rdfsbase", { Ev } },
3742   },
3743
3744   /* PREFIX_0FAE_REG_1 */
3745   {
3746     { Bad_Opcode },
3747     { "rdgsbase", { Ev } },
3748   },
3749
3750   /* PREFIX_0FAE_REG_2 */
3751   {
3752     { Bad_Opcode },
3753     { "wrfsbase", { Ev } },
3754   },
3755
3756   /* PREFIX_0FAE_REG_3 */
3757   {
3758     { Bad_Opcode },
3759     { "wrgsbase", { Ev } },
3760   },
3761
3762   /* PREFIX_0FB8 */
3763   {
3764     { Bad_Opcode },
3765     { "popcntS", { Gv, Ev } },
3766   },
3767
3768   /* PREFIX_0FBC */
3769   {
3770     { "bsfS",   { Gv, Ev } },
3771     { "tzcntS", { Gv, Ev } },
3772     { "bsfS",   { Gv, Ev } },
3773   },
3774
3775   /* PREFIX_0FBD */
3776   {
3777     { "bsrS",   { Gv, Ev } },
3778     { "lzcntS", { Gv, Ev } },
3779     { "bsrS",   { Gv, Ev } },
3780   },
3781
3782   /* PREFIX_0FC2 */
3783   {
3784     { "cmpps",  { XM, EXx, CMP } },
3785     { "cmpss",  { XM, EXd, CMP } },
3786     { "cmppd",  { XM, EXx, CMP } },
3787     { "cmpsd",  { XM, EXq, CMP } },
3788   },
3789
3790   /* PREFIX_0FC3 */
3791   {
3792     { "movntiS", { Ma, Gv } },
3793   },
3794
3795   /* PREFIX_0FC7_REG_6 */
3796   {
3797     { "vmptrld",{ Mq } },
3798     { "vmxon",  { Mq } },
3799     { "vmclear",{ Mq } },
3800   },
3801
3802   /* PREFIX_0FD0 */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { "addsubpd", { XM, EXx } },
3807     { "addsubps", { XM, EXx } },
3808   },
3809
3810   /* PREFIX_0FD6 */
3811   {
3812     { Bad_Opcode },
3813     { "movq2dq",{ XM, MS } },
3814     { "movq",   { EXqS, XM } },
3815     { "movdq2q",{ MX, XS } },
3816   },
3817
3818   /* PREFIX_0FE6 */
3819   {
3820     { Bad_Opcode },
3821     { "cvtdq2pd", { XM, EXq } },
3822     { "cvttpd2dq", { XM, EXx } },
3823     { "cvtpd2dq", { XM, EXx } },
3824   },
3825
3826   /* PREFIX_0FE7 */
3827   {
3828     { "movntq", { Mq, MX } },
3829     { Bad_Opcode },
3830     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3831   },
3832
3833   /* PREFIX_0FF0 */
3834   {
3835     { Bad_Opcode },
3836     { Bad_Opcode },
3837     { Bad_Opcode },
3838     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3839   },
3840
3841   /* PREFIX_0FF7 */
3842   {
3843     { "maskmovq", { MX, MS } },
3844     { Bad_Opcode },
3845     { "maskmovdqu", { XM, XS } },
3846   },
3847
3848   /* PREFIX_0F3810 */
3849   {
3850     { Bad_Opcode },
3851     { Bad_Opcode },
3852     { "pblendvb", { XM, EXx, XMM0 } },
3853   },
3854
3855   /* PREFIX_0F3814 */
3856   {
3857     { Bad_Opcode },
3858     { Bad_Opcode },
3859     { "blendvps", { XM, EXx, XMM0 } },
3860   },
3861
3862   /* PREFIX_0F3815 */
3863   {
3864     { Bad_Opcode },
3865     { Bad_Opcode },
3866     { "blendvpd", { XM, EXx, XMM0 } },
3867   },
3868
3869   /* PREFIX_0F3817 */
3870   {
3871     { Bad_Opcode },
3872     { Bad_Opcode },
3873     { "ptest",  { XM, EXx } },
3874   },
3875
3876   /* PREFIX_0F3820 */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { "pmovsxbw", { XM, EXq } },
3881   },
3882
3883   /* PREFIX_0F3821 */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "pmovsxbd", { XM, EXd } },
3888   },
3889
3890   /* PREFIX_0F3822 */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { "pmovsxbq", { XM, EXw } },
3895   },
3896
3897   /* PREFIX_0F3823 */
3898   {
3899     { Bad_Opcode },
3900     { Bad_Opcode },
3901     { "pmovsxwd", { XM, EXq } },
3902   },
3903
3904   /* PREFIX_0F3824 */
3905   {
3906     { Bad_Opcode },
3907     { Bad_Opcode },
3908     { "pmovsxwq", { XM, EXd } },
3909   },
3910
3911   /* PREFIX_0F3825 */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "pmovsxdq", { XM, EXq } },
3916   },
3917
3918   /* PREFIX_0F3828 */
3919   {
3920     { Bad_Opcode },
3921     { Bad_Opcode },
3922     { "pmuldq", { XM, EXx } },
3923   },
3924
3925   /* PREFIX_0F3829 */
3926   {
3927     { Bad_Opcode },
3928     { Bad_Opcode },
3929     { "pcmpeqq", { XM, EXx } },
3930   },
3931
3932   /* PREFIX_0F382A */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3937   },
3938
3939   /* PREFIX_0F382B */
3940   {
3941     { Bad_Opcode },
3942     { Bad_Opcode },
3943     { "packusdw", { XM, EXx } },
3944   },
3945
3946   /* PREFIX_0F3830 */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "pmovzxbw", { XM, EXq } },
3951   },
3952
3953   /* PREFIX_0F3831 */
3954   {
3955     { Bad_Opcode },
3956     { Bad_Opcode },
3957     { "pmovzxbd", { XM, EXd } },
3958   },
3959
3960   /* PREFIX_0F3832 */
3961   {
3962     { Bad_Opcode },
3963     { Bad_Opcode },
3964     { "pmovzxbq", { XM, EXw } },
3965   },
3966
3967   /* PREFIX_0F3833 */
3968   {
3969     { Bad_Opcode },
3970     { Bad_Opcode },
3971     { "pmovzxwd", { XM, EXq } },
3972   },
3973
3974   /* PREFIX_0F3834 */
3975   {
3976     { Bad_Opcode },
3977     { Bad_Opcode },
3978     { "pmovzxwq", { XM, EXd } },
3979   },
3980
3981   /* PREFIX_0F3835 */
3982   {
3983     { Bad_Opcode },
3984     { Bad_Opcode },
3985     { "pmovzxdq", { XM, EXq } },
3986   },
3987
3988   /* PREFIX_0F3837 */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { "pcmpgtq", { XM, EXx } },
3993   },
3994
3995   /* PREFIX_0F3838 */
3996   {
3997     { Bad_Opcode },
3998     { Bad_Opcode },
3999     { "pminsb", { XM, EXx } },
4000   },
4001
4002   /* PREFIX_0F3839 */
4003   {
4004     { Bad_Opcode },
4005     { Bad_Opcode },
4006     { "pminsd", { XM, EXx } },
4007   },
4008
4009   /* PREFIX_0F383A */
4010   {
4011     { Bad_Opcode },
4012     { Bad_Opcode },
4013     { "pminuw", { XM, EXx } },
4014   },
4015
4016   /* PREFIX_0F383B */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "pminud", { XM, EXx } },
4021   },
4022
4023   /* PREFIX_0F383C */
4024   {
4025     { Bad_Opcode },
4026     { Bad_Opcode },
4027     { "pmaxsb", { XM, EXx } },
4028   },
4029
4030   /* PREFIX_0F383D */
4031   {
4032     { Bad_Opcode },
4033     { Bad_Opcode },
4034     { "pmaxsd", { XM, EXx } },
4035   },
4036
4037   /* PREFIX_0F383E */
4038   {
4039     { Bad_Opcode },
4040     { Bad_Opcode },
4041     { "pmaxuw", { XM, EXx } },
4042   },
4043
4044   /* PREFIX_0F383F */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { "pmaxud", { XM, EXx } },
4049   },
4050
4051   /* PREFIX_0F3840 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { "pmulld", { XM, EXx } },
4056   },
4057
4058   /* PREFIX_0F3841 */
4059   {
4060     { Bad_Opcode },
4061     { Bad_Opcode },
4062     { "phminposuw", { XM, EXx } },
4063   },
4064
4065   /* PREFIX_0F3880 */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { "invept", { Gm, Mo } },
4070   },
4071
4072   /* PREFIX_0F3881 */
4073   {
4074     { Bad_Opcode },
4075     { Bad_Opcode },
4076     { "invvpid", { Gm, Mo } },
4077   },
4078
4079   /* PREFIX_0F3882 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "invpcid", { Gm, M } },
4084   },
4085
4086   /* PREFIX_0F38C8 */
4087   {
4088     { "sha1nexte", { XM, EXxmm } },
4089   },
4090
4091   /* PREFIX_0F38C9 */
4092   {
4093     { "sha1msg1", { XM, EXxmm } },
4094   },
4095
4096   /* PREFIX_0F38CA */
4097   {
4098     { "sha1msg2", { XM, EXxmm } },
4099   },
4100
4101   /* PREFIX_0F38CB */
4102   {
4103     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4104   },
4105
4106   /* PREFIX_0F38CC */
4107   {
4108     { "sha256msg1", { XM, EXxmm } },
4109   },
4110
4111   /* PREFIX_0F38CD */
4112   {
4113     { "sha256msg2", { XM, EXxmm } },
4114   },
4115
4116   /* PREFIX_0F38DB */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "aesimc", { XM, EXx } },
4121   },
4122
4123   /* PREFIX_0F38DC */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "aesenc", { XM, EXx } },
4128   },
4129
4130   /* PREFIX_0F38DD */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "aesenclast", { XM, EXx } },
4135   },
4136
4137   /* PREFIX_0F38DE */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "aesdec", { XM, EXx } },
4142   },
4143
4144   /* PREFIX_0F38DF */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "aesdeclast", { XM, EXx } },
4149   },
4150
4151   /* PREFIX_0F38F0 */
4152   {
4153     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4154     { Bad_Opcode },
4155     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4156     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4157   },
4158
4159   /* PREFIX_0F38F1 */
4160   {
4161     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4162     { Bad_Opcode },
4163     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4164     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4165   },
4166
4167   /* PREFIX_0F38F6 */
4168   {
4169     { Bad_Opcode },
4170     { "adoxS",  { Gdq, Edq} },
4171     { "adcxS",  { Gdq, Edq} },
4172     { Bad_Opcode },
4173   },
4174
4175   /* PREFIX_0F3A08 */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "roundps", { XM, EXx, Ib } },
4180   },
4181
4182   /* PREFIX_0F3A09 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "roundpd", { XM, EXx, Ib } },
4187   },
4188
4189   /* PREFIX_0F3A0A */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "roundss", { XM, EXd, Ib } },
4194   },
4195
4196   /* PREFIX_0F3A0B */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "roundsd", { XM, EXq, Ib } },
4201   },
4202
4203   /* PREFIX_0F3A0C */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "blendps", { XM, EXx, Ib } },
4208   },
4209
4210   /* PREFIX_0F3A0D */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "blendpd", { XM, EXx, Ib } },
4215   },
4216
4217   /* PREFIX_0F3A0E */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pblendw", { XM, EXx, Ib } },
4222   },
4223
4224   /* PREFIX_0F3A14 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pextrb", { Edqb, XM, Ib } },
4229   },
4230
4231   /* PREFIX_0F3A15 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pextrw", { Edqw, XM, Ib } },
4236   },
4237
4238   /* PREFIX_0F3A16 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pextrK", { Edq, XM, Ib } },
4243   },
4244
4245   /* PREFIX_0F3A17 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "extractps", { Edqd, XM, Ib } },
4250   },
4251
4252   /* PREFIX_0F3A20 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pinsrb", { XM, Edqb, Ib } },
4257   },
4258
4259   /* PREFIX_0F3A21 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "insertps", { XM, EXd, Ib } },
4264   },
4265
4266   /* PREFIX_0F3A22 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pinsrK", { XM, Edq, Ib } },
4271   },
4272
4273   /* PREFIX_0F3A40 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "dpps",   { XM, EXx, Ib } },
4278   },
4279
4280   /* PREFIX_0F3A41 */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "dppd",   { XM, EXx, Ib } },
4285   },
4286
4287   /* PREFIX_0F3A42 */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "mpsadbw", { XM, EXx, Ib } },
4292   },
4293
4294   /* PREFIX_0F3A44 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pclmulqdq", { XM, EXx, PCLMUL } },
4299   },
4300
4301   /* PREFIX_0F3A60 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pcmpestrm", { XM, EXx, Ib } },
4306   },
4307
4308   /* PREFIX_0F3A61 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pcmpestri", { XM, EXx, Ib } },
4313   },
4314
4315   /* PREFIX_0F3A62 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pcmpistrm", { XM, EXx, Ib } },
4320   },
4321
4322   /* PREFIX_0F3A63 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pcmpistri", { XM, EXx, Ib } },
4327   },
4328
4329   /* PREFIX_0F3ACC */
4330   {
4331     { "sha1rnds4", { XM, EXxmm, Ib } },
4332   },
4333
4334   /* PREFIX_0F3ADF */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "aeskeygenassist", { XM, EXx, Ib } },
4339   },
4340
4341   /* PREFIX_VEX_0F10 */
4342   {
4343     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4344     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4345     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4346     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4347   },
4348
4349   /* PREFIX_VEX_0F11 */
4350   {
4351     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4352     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4353     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4354     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4355   },
4356
4357   /* PREFIX_VEX_0F12 */
4358   {
4359     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4360     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4361     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4362     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4363   },
4364
4365   /* PREFIX_VEX_0F16 */
4366   {
4367     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4368     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4369     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_0F2A */
4373   {
4374     { Bad_Opcode },
4375     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4376     { Bad_Opcode },
4377     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4378   },
4379
4380   /* PREFIX_VEX_0F2C */
4381   {
4382     { Bad_Opcode },
4383     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4384     { Bad_Opcode },
4385     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4386   },
4387
4388   /* PREFIX_VEX_0F2D */
4389   {
4390     { Bad_Opcode },
4391     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4392     { Bad_Opcode },
4393     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4394   },
4395
4396   /* PREFIX_VEX_0F2E */
4397   {
4398     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4399     { Bad_Opcode },
4400     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4401   },
4402
4403   /* PREFIX_VEX_0F2F */
4404   {
4405     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4406     { Bad_Opcode },
4407     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4408   },
4409
4410   /* PREFIX_VEX_0F41 */
4411   {
4412     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4413   },
4414
4415   /* PREFIX_VEX_0F42 */
4416   {
4417     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4418   },
4419
4420   /* PREFIX_VEX_0F44 */
4421   {
4422     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4423   },
4424
4425   /* PREFIX_VEX_0F45 */
4426   {
4427     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4428   },
4429
4430   /* PREFIX_VEX_0F46 */
4431   {
4432     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4433   },
4434
4435   /* PREFIX_VEX_0F47 */
4436   {
4437     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4438   },
4439
4440   /* PREFIX_VEX_0F4B */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4445   },
4446
4447   /* PREFIX_VEX_0F51 */
4448   {
4449     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4450     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4451     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4452     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4453   },
4454
4455   /* PREFIX_VEX_0F52 */
4456   {
4457     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4458     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4459   },
4460
4461   /* PREFIX_VEX_0F53 */
4462   {
4463     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4464     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4465   },
4466
4467   /* PREFIX_VEX_0F58 */
4468   {
4469     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4470     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4471     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4472     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4473   },
4474
4475   /* PREFIX_VEX_0F59 */
4476   {
4477     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4478     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4479     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4480     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4481   },
4482
4483   /* PREFIX_VEX_0F5A */
4484   {
4485     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4486     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4487     { "vcvtpd2ps%XY", { XMM, EXx } },
4488     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4489   },
4490
4491   /* PREFIX_VEX_0F5B */
4492   {
4493     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4494     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4495     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4496   },
4497
4498   /* PREFIX_VEX_0F5C */
4499   {
4500     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4501     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4502     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4503     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4504   },
4505
4506   /* PREFIX_VEX_0F5D */
4507   {
4508     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4509     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4510     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4511     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4512   },
4513
4514   /* PREFIX_VEX_0F5E */
4515   {
4516     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4517     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4518     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4519     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4520   },
4521
4522   /* PREFIX_VEX_0F5F */
4523   {
4524     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4525     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4526     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4527     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4528   },
4529
4530   /* PREFIX_VEX_0F60 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4535   },
4536
4537   /* PREFIX_VEX_0F61 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F62 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4549   },
4550
4551   /* PREFIX_VEX_0F63 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F64 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F65 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F66 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F67 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F68 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F69 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F6A */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F6B */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F6C */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F6D */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F6E */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F6F */
4636   {
4637     { Bad_Opcode },
4638     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4639     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F70 */
4643   {
4644     { Bad_Opcode },
4645     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4646     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4647     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4648   },
4649
4650   /* PREFIX_VEX_0F71_REG_2 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F71_REG_4 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F71_REG_6 */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4669   },
4670
4671   /* PREFIX_VEX_0F72_REG_2 */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4676   },
4677
4678   /* PREFIX_VEX_0F72_REG_4 */
4679   {
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4683   },
4684
4685   /* PREFIX_VEX_0F72_REG_6 */
4686   {
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4690   },
4691
4692   /* PREFIX_VEX_0F73_REG_2 */
4693   {
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4697   },
4698
4699   /* PREFIX_VEX_0F73_REG_3 */
4700   {
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4704   },
4705
4706   /* PREFIX_VEX_0F73_REG_6 */
4707   {
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4711   },
4712
4713   /* PREFIX_VEX_0F73_REG_7 */
4714   {
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4718   },
4719
4720   /* PREFIX_VEX_0F74 */
4721   {
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4725   },
4726
4727   /* PREFIX_VEX_0F75 */
4728   {
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4732   },
4733
4734   /* PREFIX_VEX_0F76 */
4735   {
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4739   },
4740
4741   /* PREFIX_VEX_0F77 */
4742   {
4743     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4744   },
4745
4746   /* PREFIX_VEX_0F7C */
4747   {
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4751     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4752   },
4753
4754   /* PREFIX_VEX_0F7D */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4759     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4760   },
4761
4762   /* PREFIX_VEX_0F7E */
4763   {
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4767   },
4768
4769   /* PREFIX_VEX_0F7F */
4770   {
4771     { Bad_Opcode },
4772     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4773     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4774   },
4775
4776   /* PREFIX_VEX_0F90 */
4777   {
4778     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4779   },
4780
4781   /* PREFIX_VEX_0F91 */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4784   },
4785
4786   /* PREFIX_VEX_0F92 */
4787   {
4788     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4789   },
4790
4791   /* PREFIX_VEX_0F93 */
4792   {
4793     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4794   },
4795
4796   /* PREFIX_VEX_0F98 */
4797   {
4798     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4799   },
4800
4801   /* PREFIX_VEX_0FC2 */
4802   {
4803     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4804     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4805     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4806     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4807   },
4808
4809   /* PREFIX_VEX_0FC4 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4814   },
4815
4816   /* PREFIX_VEX_0FC5 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4821   },
4822
4823   /* PREFIX_VEX_0FD0 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4828     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4829   },
4830
4831   /* PREFIX_VEX_0FD1 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4836   },
4837
4838   /* PREFIX_VEX_0FD2 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4843   },
4844
4845   /* PREFIX_VEX_0FD3 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0FD4 */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4857   },
4858
4859   /* PREFIX_VEX_0FD5 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0FD6 */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4871   },
4872
4873   /* PREFIX_VEX_0FD7 */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4878   },
4879
4880   /* PREFIX_VEX_0FD8 */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4885   },
4886
4887   /* PREFIX_VEX_0FD9 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4892   },
4893
4894   /* PREFIX_VEX_0FDA */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4899   },
4900
4901   /* PREFIX_VEX_0FDB */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4906   },
4907
4908   /* PREFIX_VEX_0FDC */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4913   },
4914
4915   /* PREFIX_VEX_0FDD */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4920   },
4921
4922   /* PREFIX_VEX_0FDE */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4927   },
4928
4929   /* PREFIX_VEX_0FDF */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4934   },
4935
4936   /* PREFIX_VEX_0FE0 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4941   },
4942
4943   /* PREFIX_VEX_0FE1 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4948   },
4949
4950   /* PREFIX_VEX_0FE2 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4955   },
4956
4957   /* PREFIX_VEX_0FE3 */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4962   },
4963
4964   /* PREFIX_VEX_0FE4 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4969   },
4970
4971   /* PREFIX_VEX_0FE5 */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4976   },
4977
4978   /* PREFIX_VEX_0FE6 */
4979   {
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4982     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4983     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4984   },
4985
4986   /* PREFIX_VEX_0FE7 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4991   },
4992
4993   /* PREFIX_VEX_0FE8 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0FE9 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0FEA */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0FEB */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0FEC */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5026   },
5027
5028   /* PREFIX_VEX_0FED */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5033   },
5034
5035   /* PREFIX_VEX_0FEE */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5040   },
5041
5042   /* PREFIX_VEX_0FEF */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5047   },
5048
5049   /* PREFIX_VEX_0FF0 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5055   },
5056
5057   /* PREFIX_VEX_0FF1 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0FF2 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0FF3 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0FF4 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0FF5 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0FF6 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5097   },
5098
5099   /* PREFIX_VEX_0FF7 */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0FF8 */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0FF9 */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0FFA */
5121   {
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0FFB */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0FFC */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FFD */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FFE */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0F3800 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F3801 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0F3802 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0F3803 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0F3804 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0F3805 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0F3806 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0F3807 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0F3808 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0F3809 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0F380A */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0F380B */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0F380C */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0F380D */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0F380E */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0F380F */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0F3813 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vcvtph2ps", { XM, EXxmmq } },
5272   },
5273
5274   /* PREFIX_VEX_0F3816 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0F3817 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0F3818 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0F3819 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0F381A */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5307   },
5308
5309   /* PREFIX_VEX_0F381C */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0F381D */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0F381E */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0F3820 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0F3821 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0F3822 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0F3823 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0F3824 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0F3825 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0F3828 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0F3829 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0F382A */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5391   },
5392
5393   /* PREFIX_VEX_0F382B */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0F382C */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5405   },
5406
5407   /* PREFIX_VEX_0F382D */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5412   },
5413
5414   /* PREFIX_VEX_0F382E */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5419   },
5420
5421   /* PREFIX_VEX_0F382F */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5426   },
5427
5428   /* PREFIX_VEX_0F3830 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0F3831 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0F3832 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0F3833 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0F3834 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0F3835 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0F3836 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0F3837 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0F3838 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0F3839 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0F383A */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0F383B */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0F383C */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0F383D */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0F383E */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0F383F */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0F3840 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0F3841 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0F3845 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpsrlv%LW", { XM, Vex, EXx } },
5559   },
5560
5561   /* PREFIX_VEX_0F3846 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0F3847 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpsllv%LW", { XM, Vex, EXx } },
5573   },
5574
5575   /* PREFIX_VEX_0F3858 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F3859 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F385A */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F3878 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3879 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F388C */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F388E */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F3890 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5629   },
5630
5631   /* PREFIX_VEX_0F3891 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5636   },
5637
5638   /* PREFIX_VEX_0F3892 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5643   },
5644
5645   /* PREFIX_VEX_0F3893 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5650   },
5651
5652   /* PREFIX_VEX_0F3896 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5657   },
5658
5659   /* PREFIX_VEX_0F3897 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5664   },
5665
5666   /* PREFIX_VEX_0F3898 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vfmadd132p%XW", { XM, Vex, EXx } },
5671   },
5672
5673   /* PREFIX_VEX_0F3899 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5678   },
5679
5680   /* PREFIX_VEX_0F389A */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vfmsub132p%XW", { XM, Vex, EXx } },
5685   },
5686
5687   /* PREFIX_VEX_0F389B */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5692   },
5693
5694   /* PREFIX_VEX_0F389C */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5699   },
5700
5701   /* PREFIX_VEX_0F389D */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5706   },
5707
5708   /* PREFIX_VEX_0F389E */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5713   },
5714
5715   /* PREFIX_VEX_0F389F */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5720   },
5721
5722   /* PREFIX_VEX_0F38A6 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5727     { Bad_Opcode },
5728   },
5729
5730   /* PREFIX_VEX_0F38A7 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5735   },
5736
5737   /* PREFIX_VEX_0F38A8 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vfmadd213p%XW", { XM, Vex, EXx } },
5742   },
5743
5744   /* PREFIX_VEX_0F38A9 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5749   },
5750
5751   /* PREFIX_VEX_0F38AA */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { "vfmsub213p%XW", { XM, Vex, EXx } },
5756   },
5757
5758   /* PREFIX_VEX_0F38AB */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5763   },
5764
5765   /* PREFIX_VEX_0F38AC */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5770   },
5771
5772   /* PREFIX_VEX_0F38AD */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5777   },
5778
5779   /* PREFIX_VEX_0F38AE */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5784   },
5785
5786   /* PREFIX_VEX_0F38AF */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5791   },
5792
5793   /* PREFIX_VEX_0F38B6 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5798   },
5799
5800   /* PREFIX_VEX_0F38B7 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5805   },
5806
5807   /* PREFIX_VEX_0F38B8 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vfmadd231p%XW", { XM, Vex, EXx } },
5812   },
5813
5814   /* PREFIX_VEX_0F38B9 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5819   },
5820
5821   /* PREFIX_VEX_0F38BA */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vfmsub231p%XW", { XM, Vex, EXx } },
5826   },
5827
5828   /* PREFIX_VEX_0F38BB */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5833   },
5834
5835   /* PREFIX_VEX_0F38BC */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5840   },
5841
5842   /* PREFIX_VEX_0F38BD */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5847   },
5848
5849   /* PREFIX_VEX_0F38BE */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5854   },
5855
5856   /* PREFIX_VEX_0F38BF */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5861   },
5862
5863   /* PREFIX_VEX_0F38DB */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F38DC */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F38DD */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F38DE */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F38DF */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F38F2 */
5899   {
5900     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5901   },
5902
5903   /* PREFIX_VEX_0F38F3_REG_1 */
5904   {
5905     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5906   },
5907
5908   /* PREFIX_VEX_0F38F3_REG_2 */
5909   {
5910     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5911   },
5912
5913   /* PREFIX_VEX_0F38F3_REG_3 */
5914   {
5915     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5916   },
5917
5918   /* PREFIX_VEX_0F38F5 */
5919   {
5920     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5921     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5922     { Bad_Opcode },
5923     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5924   },
5925
5926   /* PREFIX_VEX_0F38F6 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5932   },
5933
5934   /* PREFIX_VEX_0F38F7 */
5935   {
5936     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5937     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5938     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5939     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5940   },
5941
5942   /* PREFIX_VEX_0F3A00 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3A01 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3A02 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F3A04 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3A05 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F3A06 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F3A08 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3A09 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5996   },
5997
5998   /* PREFIX_VEX_0F3A0A */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6003   },
6004
6005   /* PREFIX_VEX_0F3A0B */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6010   },
6011
6012   /* PREFIX_VEX_0F3A0C */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6017   },
6018
6019   /* PREFIX_VEX_0F3A0D */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6024   },
6025
6026   /* PREFIX_VEX_0F3A0E */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6031   },
6032
6033   /* PREFIX_VEX_0F3A0F */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6038   },
6039
6040   /* PREFIX_VEX_0F3A14 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6045   },
6046
6047   /* PREFIX_VEX_0F3A15 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6052   },
6053
6054   /* PREFIX_VEX_0F3A16 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6059   },
6060
6061   /* PREFIX_VEX_0F3A17 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6066   },
6067
6068   /* PREFIX_VEX_0F3A18 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6073   },
6074
6075   /* PREFIX_VEX_0F3A19 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6080   },
6081
6082   /* PREFIX_VEX_0F3A1D */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6087   },
6088
6089   /* PREFIX_VEX_0F3A20 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6094   },
6095
6096   /* PREFIX_VEX_0F3A21 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6101   },
6102
6103   /* PREFIX_VEX_0F3A22 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6108   },
6109
6110   /* PREFIX_VEX_0F3A30 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6115   },
6116
6117   /* PREFIX_VEX_0F3A32 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6122   },
6123
6124   /* PREFIX_VEX_0F3A38 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6129   },
6130
6131   /* PREFIX_VEX_0F3A39 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6136   },
6137
6138   /* PREFIX_VEX_0F3A40 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6143   },
6144
6145   /* PREFIX_VEX_0F3A41 */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6150   },
6151
6152   /* PREFIX_VEX_0F3A42 */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6157   },
6158
6159   /* PREFIX_VEX_0F3A44 */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6164   },
6165
6166   /* PREFIX_VEX_0F3A46 */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6171   },
6172
6173   /* PREFIX_VEX_0F3A48 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6178   },
6179
6180   /* PREFIX_VEX_0F3A49 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6185   },
6186
6187   /* PREFIX_VEX_0F3A4A */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F3A4B */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F3A4C */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F3A5C */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6213   },
6214
6215   /* PREFIX_VEX_0F3A5D */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6220   },
6221
6222   /* PREFIX_VEX_0F3A5E */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6227   },
6228
6229   /* PREFIX_VEX_0F3A5F */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6234   },
6235
6236   /* PREFIX_VEX_0F3A60 */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6241     { Bad_Opcode },
6242   },
6243
6244   /* PREFIX_VEX_0F3A61 */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6249   },
6250
6251   /* PREFIX_VEX_0F3A62 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6256   },
6257
6258   /* PREFIX_VEX_0F3A63 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F3A68 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6270   },
6271
6272   /* PREFIX_VEX_0F3A69 */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6277   },
6278
6279   /* PREFIX_VEX_0F3A6A */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A6B */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A6C */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6298   },
6299
6300   /* PREFIX_VEX_0F3A6D */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6305   },
6306
6307   /* PREFIX_VEX_0F3A6E */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A6F */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A78 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6326   },
6327
6328   /* PREFIX_VEX_0F3A79 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6333   },
6334
6335   /* PREFIX_VEX_0F3A7A */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A7B */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A7C */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6354     { Bad_Opcode },
6355   },
6356
6357   /* PREFIX_VEX_0F3A7D */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6362   },
6363
6364   /* PREFIX_VEX_0F3A7E */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A7F */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3ADF */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3AF0 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6391   },
6392
6393 #define NEED_PREFIX_TABLE
6394 #include "i386-dis-evex.h"
6395 #undef NEED_PREFIX_TABLE
6396 };
6397
6398 static const struct dis386 x86_64_table[][2] = {
6399   /* X86_64_06 */
6400   {
6401     { "pushP", { es } },
6402   },
6403
6404   /* X86_64_07 */
6405   {
6406     { "popP", { es } },
6407   },
6408
6409   /* X86_64_0D */
6410   {
6411     { "pushP", { cs } },
6412   },
6413
6414   /* X86_64_16 */
6415   {
6416     { "pushP", { ss } },
6417   },
6418
6419   /* X86_64_17 */
6420   {
6421     { "popP", { ss } },
6422   },
6423
6424   /* X86_64_1E */
6425   {
6426     { "pushP", { ds } },
6427   },
6428
6429   /* X86_64_1F */
6430   {
6431     { "popP", { ds } },
6432   },
6433
6434   /* X86_64_27 */
6435   {
6436     { "daa", { XX } },
6437   },
6438
6439   /* X86_64_2F */
6440   {
6441     { "das", { XX } },
6442   },
6443
6444   /* X86_64_37 */
6445   {
6446     { "aaa", { XX } },
6447   },
6448
6449   /* X86_64_3F */
6450   {
6451     { "aas", { XX } },
6452   },
6453
6454   /* X86_64_60 */
6455   {
6456     { "pushaP", { XX } },
6457   },
6458
6459   /* X86_64_61 */
6460   {
6461     { "popaP", { XX } },
6462   },
6463
6464   /* X86_64_62 */
6465   {
6466     { MOD_TABLE (MOD_62_32BIT) },
6467     { EVEX_TABLE (EVEX_0F) },
6468   },
6469
6470   /* X86_64_63 */
6471   {
6472     { "arpl", { Ew, Gw } },
6473     { "movs{lq|xd}", { Gv, Ed } },
6474   },
6475
6476   /* X86_64_6D */
6477   {
6478     { "ins{R|}", { Yzr, indirDX } },
6479     { "ins{G|}", { Yzr, indirDX } },
6480   },
6481
6482   /* X86_64_6F */
6483   {
6484     { "outs{R|}", { indirDXr, Xz } },
6485     { "outs{G|}", { indirDXr, Xz } },
6486   },
6487
6488   /* X86_64_9A */
6489   {
6490     { "Jcall{T|}", { Ap } },
6491   },
6492
6493   /* X86_64_C4 */
6494   {
6495     { MOD_TABLE (MOD_C4_32BIT) },
6496     { VEX_C4_TABLE (VEX_0F) },
6497   },
6498
6499   /* X86_64_C5 */
6500   {
6501     { MOD_TABLE (MOD_C5_32BIT) },
6502     { VEX_C5_TABLE (VEX_0F) },
6503   },
6504
6505   /* X86_64_CE */
6506   {
6507     { "into", { XX } },
6508   },
6509
6510   /* X86_64_D4 */
6511   {
6512     { "aam", { Ib } },
6513   },
6514
6515   /* X86_64_D5 */
6516   {
6517     { "aad", { Ib } },
6518   },
6519
6520   /* X86_64_EA */
6521   {
6522     { "Jjmp{T|}", { Ap } },
6523   },
6524
6525   /* X86_64_0F01_REG_0 */
6526   {
6527     { "sgdt{Q|IQ}", { M } },
6528     { "sgdt", { M } },
6529   },
6530
6531   /* X86_64_0F01_REG_1 */
6532   {
6533     { "sidt{Q|IQ}", { M } },
6534     { "sidt", { M } },
6535   },
6536
6537   /* X86_64_0F01_REG_2 */
6538   {
6539     { "lgdt{Q|Q}", { M } },
6540     { "lgdt", { M } },
6541   },
6542
6543   /* X86_64_0F01_REG_3 */
6544   {
6545     { "lidt{Q|Q}", { M } },
6546     { "lidt", { M } },
6547   },
6548 };
6549
6550 static const struct dis386 three_byte_table[][256] = {
6551
6552   /* THREE_BYTE_0F38 */
6553   {
6554     /* 00 */
6555     { "pshufb",         { MX, EM } },
6556     { "phaddw",         { MX, EM } },
6557     { "phaddd",         { MX, EM } },
6558     { "phaddsw",        { MX, EM } },
6559     { "pmaddubsw",      { MX, EM } },
6560     { "phsubw",         { MX, EM } },
6561     { "phsubd",         { MX, EM } },
6562     { "phsubsw",        { MX, EM } },
6563     /* 08 */
6564     { "psignb",         { MX, EM } },
6565     { "psignw",         { MX, EM } },
6566     { "psignd",         { MX, EM } },
6567     { "pmulhrsw",       { MX, EM } },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     /* 10 */
6573     { PREFIX_TABLE (PREFIX_0F3810) },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { PREFIX_TABLE (PREFIX_0F3814) },
6578     { PREFIX_TABLE (PREFIX_0F3815) },
6579     { Bad_Opcode },
6580     { PREFIX_TABLE (PREFIX_0F3817) },
6581     /* 18 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "pabsb",          { MX, EM } },
6587     { "pabsw",          { MX, EM } },
6588     { "pabsd",          { MX, EM } },
6589     { Bad_Opcode },
6590     /* 20 */
6591     { PREFIX_TABLE (PREFIX_0F3820) },
6592     { PREFIX_TABLE (PREFIX_0F3821) },
6593     { PREFIX_TABLE (PREFIX_0F3822) },
6594     { PREFIX_TABLE (PREFIX_0F3823) },
6595     { PREFIX_TABLE (PREFIX_0F3824) },
6596     { PREFIX_TABLE (PREFIX_0F3825) },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     /* 28 */
6600     { PREFIX_TABLE (PREFIX_0F3828) },
6601     { PREFIX_TABLE (PREFIX_0F3829) },
6602     { PREFIX_TABLE (PREFIX_0F382A) },
6603     { PREFIX_TABLE (PREFIX_0F382B) },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* 30 */
6609     { PREFIX_TABLE (PREFIX_0F3830) },
6610     { PREFIX_TABLE (PREFIX_0F3831) },
6611     { PREFIX_TABLE (PREFIX_0F3832) },
6612     { PREFIX_TABLE (PREFIX_0F3833) },
6613     { PREFIX_TABLE (PREFIX_0F3834) },
6614     { PREFIX_TABLE (PREFIX_0F3835) },
6615     { Bad_Opcode },
6616     { PREFIX_TABLE (PREFIX_0F3837) },
6617     /* 38 */
6618     { PREFIX_TABLE (PREFIX_0F3838) },
6619     { PREFIX_TABLE (PREFIX_0F3839) },
6620     { PREFIX_TABLE (PREFIX_0F383A) },
6621     { PREFIX_TABLE (PREFIX_0F383B) },
6622     { PREFIX_TABLE (PREFIX_0F383C) },
6623     { PREFIX_TABLE (PREFIX_0F383D) },
6624     { PREFIX_TABLE (PREFIX_0F383E) },
6625     { PREFIX_TABLE (PREFIX_0F383F) },
6626     /* 40 */
6627     { PREFIX_TABLE (PREFIX_0F3840) },
6628     { PREFIX_TABLE (PREFIX_0F3841) },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     /* 48 */
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* 50 */
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* 58 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     /* 60 */
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* 68 */
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     /* 70 */
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     /* 78 */
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 80 */
6699     { PREFIX_TABLE (PREFIX_0F3880) },
6700     { PREFIX_TABLE (PREFIX_0F3881) },
6701     { PREFIX_TABLE (PREFIX_0F3882) },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 88 */
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     /* 90 */
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 98 */
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     /* a0 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* a8 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* b0 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* b8 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* c0 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* c8 */
6780     { PREFIX_TABLE (PREFIX_0F38C8) },
6781     { PREFIX_TABLE (PREFIX_0F38C9) },
6782     { PREFIX_TABLE (PREFIX_0F38CA) },
6783     { PREFIX_TABLE (PREFIX_0F38CB) },
6784     { PREFIX_TABLE (PREFIX_0F38CC) },
6785     { PREFIX_TABLE (PREFIX_0F38CD) },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* d0 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* d8 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { PREFIX_TABLE (PREFIX_0F38DB) },
6802     { PREFIX_TABLE (PREFIX_0F38DC) },
6803     { PREFIX_TABLE (PREFIX_0F38DD) },
6804     { PREFIX_TABLE (PREFIX_0F38DE) },
6805     { PREFIX_TABLE (PREFIX_0F38DF) },
6806     /* e0 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     /* e8 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* f0 */
6825     { PREFIX_TABLE (PREFIX_0F38F0) },
6826     { PREFIX_TABLE (PREFIX_0F38F1) },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { PREFIX_TABLE (PREFIX_0F38F6) },
6832     { Bad_Opcode },
6833     /* f8 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842   },
6843   /* THREE_BYTE_0F3A */
6844   {
6845     /* 00 */
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* 08 */
6855     { PREFIX_TABLE (PREFIX_0F3A08) },
6856     { PREFIX_TABLE (PREFIX_0F3A09) },
6857     { PREFIX_TABLE (PREFIX_0F3A0A) },
6858     { PREFIX_TABLE (PREFIX_0F3A0B) },
6859     { PREFIX_TABLE (PREFIX_0F3A0C) },
6860     { PREFIX_TABLE (PREFIX_0F3A0D) },
6861     { PREFIX_TABLE (PREFIX_0F3A0E) },
6862     { "palignr",        { MX, EM, Ib } },
6863     /* 10 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { PREFIX_TABLE (PREFIX_0F3A14) },
6869     { PREFIX_TABLE (PREFIX_0F3A15) },
6870     { PREFIX_TABLE (PREFIX_0F3A16) },
6871     { PREFIX_TABLE (PREFIX_0F3A17) },
6872     /* 18 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     /* 20 */
6882     { PREFIX_TABLE (PREFIX_0F3A20) },
6883     { PREFIX_TABLE (PREFIX_0F3A21) },
6884     { PREFIX_TABLE (PREFIX_0F3A22) },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* 28 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* 30 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 38 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* 40 */
6918     { PREFIX_TABLE (PREFIX_0F3A40) },
6919     { PREFIX_TABLE (PREFIX_0F3A41) },
6920     { PREFIX_TABLE (PREFIX_0F3A42) },
6921     { Bad_Opcode },
6922     { PREFIX_TABLE (PREFIX_0F3A44) },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* 48 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 50 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 58 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 60 */
6954     { PREFIX_TABLE (PREFIX_0F3A60) },
6955     { PREFIX_TABLE (PREFIX_0F3A61) },
6956     { PREFIX_TABLE (PREFIX_0F3A62) },
6957     { PREFIX_TABLE (PREFIX_0F3A63) },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 68 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 70 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 78 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 80 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 88 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 90 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 98 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* a0 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* a8 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* b0 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* b8 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* c0 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* c8 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { PREFIX_TABLE (PREFIX_0F3ACC) },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* d0 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* d8 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { PREFIX_TABLE (PREFIX_0F3ADF) },
7097     /* e0 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* e8 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* f0 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* f8 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133   },
7134
7135   /* THREE_BYTE_0F7A */
7136   {
7137     /* 00 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 08 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 10 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 18 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 20 */
7174     { "ptest",          { XX } },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* 28 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* 30 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 38 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 40 */
7210     { Bad_Opcode },
7211     { "phaddbw",        { XM, EXq } },
7212     { "phaddbd",        { XM, EXq } },
7213     { "phaddbq",        { XM, EXq } },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { "phaddwd",        { XM, EXq } },
7217     { "phaddwq",        { XM, EXq } },
7218     /* 48 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { "phadddq",        { XM, EXq } },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* 50 */
7228     { Bad_Opcode },
7229     { "phaddubw",       { XM, EXq } },
7230     { "phaddubd",       { XM, EXq } },
7231     { "phaddubq",       { XM, EXq } },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { "phadduwd",       { XM, EXq } },
7235     { "phadduwq",       { XM, EXq } },
7236     /* 58 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { "phaddudq",       { XM, EXq } },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 60 */
7246     { Bad_Opcode },
7247     { "phsubbw",        { XM, EXq } },
7248     { "phsubbd",        { XM, EXq } },
7249     { "phsubbq",        { XM, EXq } },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 68 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 70 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 78 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 80 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 88 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 90 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 98 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* a0 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* a8 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* b0 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* b8 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* c0 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* c8 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* d0 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* d8 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* e0 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* e8 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* f0 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* f8 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425   },
7426 };
7427
7428 static const struct dis386 xop_table[][256] = {
7429   /* XOP_08 */
7430   {
7431     /* 00 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     /* 08 */
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* 10 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* 18 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 20 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 28 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 30 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 38 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 40 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 48 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 50 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 58 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 60 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 68 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 70 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 78 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 80 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7582     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7583     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7584     /* 88 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7592     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7593     /* 90 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7600     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7601     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7602     /* 98 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7610     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7611     /* a0 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7615     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7619     { Bad_Opcode },
7620     /* a8 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* b0 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7637     { Bad_Opcode },
7638     /* b8 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* c0 */
7648     { "vprotb",         { XM, Vex_2src_1, Ib } },
7649     { "vprotw",         { XM, Vex_2src_1, Ib } },
7650     { "vprotd",         { XM, Vex_2src_1, Ib } },
7651     { "vprotq",         { XM, Vex_2src_1, Ib } },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* c8 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7662     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7663     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7664     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7665     /* d0 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* d8 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* e0 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* e8 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7698     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7699     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7700     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7701     /* f0 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* f8 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719   },
7720   /* XOP_09 */
7721   {
7722     /* 00 */
7723     { Bad_Opcode },
7724     { REG_TABLE (REG_XOP_TBM_01) },
7725     { REG_TABLE (REG_XOP_TBM_02) },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 08 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 10 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { REG_TABLE (REG_XOP_LWPCB) },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 18 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 20 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 28 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 30 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 38 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 40 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 48 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 50 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 58 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 60 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 68 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 70 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 78 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 80 */
7867     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7868     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7869     { "vfrczss",        { XM, EXd } },
7870     { "vfrczsd",        { XM, EXq } },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 88 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 90 */
7885     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7886     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7887     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7888     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7889     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7890     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7891     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7892     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7893     /* 98 */
7894     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7895     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7896     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7897     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* a0 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* a8 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* b0 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* b8 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* c0 */
7939     { Bad_Opcode },
7940     { "vphaddbw",       { XM, EXxmm } },
7941     { "vphaddbd",       { XM, EXxmm } },
7942     { "vphaddbq",       { XM, EXxmm } },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { "vphaddwd",       { XM, EXxmm } },
7946     { "vphaddwq",       { XM, EXxmm } },
7947     /* c8 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { "vphadddq",       { XM, EXxmm } },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* d0 */
7957     { Bad_Opcode },
7958     { "vphaddubw",      { XM, EXxmm } },
7959     { "vphaddubd",      { XM, EXxmm } },
7960     { "vphaddubq",      { XM, EXxmm } },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { "vphadduwd",      { XM, EXxmm } },
7964     { "vphadduwq",      { XM, EXxmm } },
7965     /* d8 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { "vphaddudq",      { XM, EXxmm } },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* e0 */
7975     { Bad_Opcode },
7976     { "vphsubbw",       { XM, EXxmm } },
7977     { "vphsubwd",       { XM, EXxmm } },
7978     { "vphsubdq",       { XM, EXxmm } },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* e8 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* f0 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* f8 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010   },
8011   /* XOP_0A */
8012   {
8013     /* 00 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 08 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 10 */
8032     { "bextr",  { Gv, Ev, Iq } },
8033     { Bad_Opcode },
8034     { REG_TABLE (REG_XOP_LWP) },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 18 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 20 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 28 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 30 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 38 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 40 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 48 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 50 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 58 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 60 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 68 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 70 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 78 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 80 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 88 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 90 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 98 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* a0 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* a8 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* b0 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* b8 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* c0 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* c8 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* d0 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* d8 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* e0 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* e8 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* f0 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* f8 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301   },
8302 };
8303
8304 static const struct dis386 vex_table[][256] = {
8305   /* VEX_0F */
8306   {
8307     /* 00 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     /* 08 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* 10 */
8326     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8327     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8328     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8329     { MOD_TABLE (MOD_VEX_0F13) },
8330     { VEX_W_TABLE (VEX_W_0F14) },
8331     { VEX_W_TABLE (VEX_W_0F15) },
8332     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8333     { MOD_TABLE (MOD_VEX_0F17) },
8334     /* 18 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* 20 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 28 */
8353     { VEX_W_TABLE (VEX_W_0F28) },
8354     { VEX_W_TABLE (VEX_W_0F29) },
8355     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8356     { MOD_TABLE (MOD_VEX_0F2B) },
8357     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8358     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8359     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8360     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8361     /* 30 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* 38 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 40 */
8380     { Bad_Opcode },
8381     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8382     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8383     { Bad_Opcode },
8384     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8386     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8387     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8388     /* 48 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     /* 50 */
8398     { MOD_TABLE (MOD_VEX_0F50) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8400     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8402     { "vandpX",         { XM, Vex, EXx } },
8403     { "vandnpX",        { XM, Vex, EXx } },
8404     { "vorpX",          { XM, Vex, EXx } },
8405     { "vxorpX",         { XM, Vex, EXx } },
8406     /* 58 */
8407     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8415     /* 60 */
8416     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8424     /* 68 */
8425     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8433     /* 70 */
8434     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8435     { REG_TABLE (REG_VEX_0F71) },
8436     { REG_TABLE (REG_VEX_0F72) },
8437     { REG_TABLE (REG_VEX_0F73) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8442     /* 78 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8451     /* 80 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 88 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 90 */
8470     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 98 */
8479     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* a0 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* a8 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { REG_TABLE (REG_VEX_0FAE) },
8504     { Bad_Opcode },
8505     /* b0 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* b8 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* c0 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8527     { Bad_Opcode },
8528     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8529     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8530     { "vshufpX",        { XM, Vex, EXx, Ib } },
8531     { Bad_Opcode },
8532     /* c8 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* d0 */
8542     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8543     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8550     /* d8 */
8551     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8559     /* e0 */
8560     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8568     /* e8 */
8569     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8577     /* f0 */
8578     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8586     /* f8 */
8587     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8594     { Bad_Opcode },
8595   },
8596   /* VEX_0F38 */
8597   {
8598     /* 00 */
8599     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8607     /* 08 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8616     /* 10 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8625     /* 18 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8629     { Bad_Opcode },
8630     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8633     { Bad_Opcode },
8634     /* 20 */
8635     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* 28 */
8644     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8652     /* 30 */
8653     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8661     /* 38 */
8662     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8670     /* 40 */
8671     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8679     /* 48 */
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     /* 50 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* 58 */
8698     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     /* 60 */
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 68 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     /* 70 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 78 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 80 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 88 */
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8757     { Bad_Opcode },
8758     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8759     { Bad_Opcode },
8760     /* 90 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8769     /* 98 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8778     /* a0 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8787     /* a8 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8796     /* b0 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8805     /* b8 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8814     /* c0 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* c8 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* d0 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* d8 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8850     /* e0 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* e8 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* f0 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8872     { REG_TABLE (REG_VEX_0F38F3) },
8873     { Bad_Opcode },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8877     /* f8 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886   },
8887   /* VEX_0F3A */
8888   {
8889     /* 00 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8897     { Bad_Opcode },
8898     /* 08 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8907     /* 10 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8916     /* 18 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     /* 20 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* 28 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 30 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* 38 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* 40 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8969     { Bad_Opcode },
8970     /* 48 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* 50 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 58 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8997     /* 60 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 68 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9015     /* 70 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 78 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9033     /* 80 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 88 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 90 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 98 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* a0 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* a8 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* b0 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* b8 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* c0 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* c8 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* d0 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* d8 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9141     /* e0 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* e8 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* f0 */
9160     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* f8 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177   },
9178 };
9179
9180 #define NEED_OPCODE_TABLE
9181 #include "i386-dis-evex.h"
9182 #undef NEED_OPCODE_TABLE
9183 static const struct dis386 vex_len_table[][2] = {
9184   /* VEX_LEN_0F10_P_1 */
9185   {
9186     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9187     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9188   },
9189
9190   /* VEX_LEN_0F10_P_3 */
9191   {
9192     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9193     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9194   },
9195
9196   /* VEX_LEN_0F11_P_1 */
9197   {
9198     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9199     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9200   },
9201
9202   /* VEX_LEN_0F11_P_3 */
9203   {
9204     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9205     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9206   },
9207
9208   /* VEX_LEN_0F12_P_0_M_0 */
9209   {
9210     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9211   },
9212
9213   /* VEX_LEN_0F12_P_0_M_1 */
9214   {
9215     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9216   },
9217
9218   /* VEX_LEN_0F12_P_2 */
9219   {
9220     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9221   },
9222
9223   /* VEX_LEN_0F13_M_0 */
9224   {
9225     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9226   },
9227
9228   /* VEX_LEN_0F16_P_0_M_0 */
9229   {
9230     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9231   },
9232
9233   /* VEX_LEN_0F16_P_0_M_1 */
9234   {
9235     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9236   },
9237
9238   /* VEX_LEN_0F16_P_2 */
9239   {
9240     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9241   },
9242
9243   /* VEX_LEN_0F17_M_0 */
9244   {
9245     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9246   },
9247
9248   /* VEX_LEN_0F2A_P_1 */
9249   {
9250     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9251     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9252   },
9253
9254   /* VEX_LEN_0F2A_P_3 */
9255   {
9256     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9257     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9258   },
9259
9260   /* VEX_LEN_0F2C_P_1 */
9261   {
9262     { "vcvttss2siY",    { Gv, EXdScalar } },
9263     { "vcvttss2siY",    { Gv, EXdScalar } },
9264   },
9265
9266   /* VEX_LEN_0F2C_P_3 */
9267   {
9268     { "vcvttsd2siY",    { Gv, EXqScalar } },
9269     { "vcvttsd2siY",    { Gv, EXqScalar } },
9270   },
9271
9272   /* VEX_LEN_0F2D_P_1 */
9273   {
9274     { "vcvtss2siY",     { Gv, EXdScalar } },
9275     { "vcvtss2siY",     { Gv, EXdScalar } },
9276   },
9277
9278   /* VEX_LEN_0F2D_P_3 */
9279   {
9280     { "vcvtsd2siY",     { Gv, EXqScalar } },
9281     { "vcvtsd2siY",     { Gv, EXqScalar } },
9282   },
9283
9284   /* VEX_LEN_0F2E_P_0 */
9285   {
9286     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9287     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9288   },
9289
9290   /* VEX_LEN_0F2E_P_2 */
9291   {
9292     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9293     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9294   },
9295
9296   /* VEX_LEN_0F2F_P_0 */
9297   {
9298     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9299     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9300   },
9301
9302   /* VEX_LEN_0F2F_P_2 */
9303   {
9304     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9305     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9306   },
9307
9308   /* VEX_LEN_0F41_P_0 */
9309   {
9310     { Bad_Opcode },
9311     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9312   },
9313   /* VEX_LEN_0F42_P_0 */
9314   {
9315     { Bad_Opcode },
9316     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9317   },
9318   /* VEX_LEN_0F44_P_0 */
9319   {
9320     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9321   },
9322   /* VEX_LEN_0F45_P_0 */
9323   {
9324     { Bad_Opcode },
9325     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9326   },
9327   /* VEX_LEN_0F46_P_0 */
9328   {
9329     { Bad_Opcode },
9330     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9331   },
9332   /* VEX_LEN_0F47_P_0 */
9333   {
9334     { Bad_Opcode },
9335     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9336   },
9337   /* VEX_LEN_0F4B_P_2 */
9338   {
9339     { Bad_Opcode },
9340     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9341   },
9342
9343   /* VEX_LEN_0F51_P_1 */
9344   {
9345     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9346     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9347   },
9348
9349   /* VEX_LEN_0F51_P_3 */
9350   {
9351     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9352     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9353   },
9354
9355   /* VEX_LEN_0F52_P_1 */
9356   {
9357     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9358     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9359   },
9360
9361   /* VEX_LEN_0F53_P_1 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9364     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9365   },
9366
9367   /* VEX_LEN_0F58_P_1 */
9368   {
9369     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9370     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9371   },
9372
9373   /* VEX_LEN_0F58_P_3 */
9374   {
9375     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9376     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9377   },
9378
9379   /* VEX_LEN_0F59_P_1 */
9380   {
9381     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9382     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9383   },
9384
9385   /* VEX_LEN_0F59_P_3 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9388     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9389   },
9390
9391   /* VEX_LEN_0F5A_P_1 */
9392   {
9393     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9394     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9395   },
9396
9397   /* VEX_LEN_0F5A_P_3 */
9398   {
9399     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9400     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9401   },
9402
9403   /* VEX_LEN_0F5C_P_1 */
9404   {
9405     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9406     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9407   },
9408
9409   /* VEX_LEN_0F5C_P_3 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9412     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9413   },
9414
9415   /* VEX_LEN_0F5D_P_1 */
9416   {
9417     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9418     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9419   },
9420
9421   /* VEX_LEN_0F5D_P_3 */
9422   {
9423     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9424     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9425   },
9426
9427   /* VEX_LEN_0F5E_P_1 */
9428   {
9429     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9430     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9431   },
9432
9433   /* VEX_LEN_0F5E_P_3 */
9434   {
9435     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9436     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9437   },
9438
9439   /* VEX_LEN_0F5F_P_1 */
9440   {
9441     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9442     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9443   },
9444
9445   /* VEX_LEN_0F5F_P_3 */
9446   {
9447     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9448     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9449   },
9450
9451   /* VEX_LEN_0F6E_P_2 */
9452   {
9453     { "vmovK",          { XMScalar, Edq } },
9454     { "vmovK",          { XMScalar, Edq } },
9455   },
9456
9457   /* VEX_LEN_0F7E_P_1 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9460     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9461   },
9462
9463   /* VEX_LEN_0F7E_P_2 */
9464   {
9465     { "vmovK",          { Edq, XMScalar } },
9466     { "vmovK",          { Edq, XMScalar } },
9467   },
9468
9469   /* VEX_LEN_0F90_P_0 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F91_P_0 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F92_P_0 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F93_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F98_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0FAE_R_2_M_0 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9497   },
9498
9499   /* VEX_LEN_0FAE_R_3_M_0 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9502   },
9503
9504   /* VEX_LEN_0FC2_P_1 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9507     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9508   },
9509
9510   /* VEX_LEN_0FC2_P_3 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9513     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9514   },
9515
9516   /* VEX_LEN_0FC4_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9519   },
9520
9521   /* VEX_LEN_0FC5_P_2 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9524   },
9525
9526   /* VEX_LEN_0FD6_P_2 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9529     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9530   },
9531
9532   /* VEX_LEN_0FF7_P_2 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9535   },
9536
9537   /* VEX_LEN_0F3816_P_2 */
9538   {
9539     { Bad_Opcode },
9540     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9541   },
9542
9543   /* VEX_LEN_0F3819_P_2 */
9544   {
9545     { Bad_Opcode },
9546     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9547   },
9548
9549   /* VEX_LEN_0F381A_P_2_M_0 */
9550   {
9551     { Bad_Opcode },
9552     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9553   },
9554
9555   /* VEX_LEN_0F3836_P_2 */
9556   {
9557     { Bad_Opcode },
9558     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9559   },
9560
9561   /* VEX_LEN_0F3841_P_2 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9564   },
9565
9566   /* VEX_LEN_0F385A_P_2_M_0 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9570   },
9571
9572   /* VEX_LEN_0F38DB_P_2 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F38DC_P_2 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9580   },
9581
9582   /* VEX_LEN_0F38DD_P_2 */
9583   {
9584     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F38DE_P_2 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F38DF_P_2 */
9593   {
9594     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9595   },
9596
9597   /* VEX_LEN_0F38F2_P_0 */
9598   {
9599     { "andnS",          { Gdq, VexGdq, Edq } },
9600   },
9601
9602   /* VEX_LEN_0F38F3_R_1_P_0 */
9603   {
9604     { "blsrS",          { VexGdq, Edq } },
9605   },
9606
9607   /* VEX_LEN_0F38F3_R_2_P_0 */
9608   {
9609     { "blsmskS",        { VexGdq, Edq } },
9610   },
9611
9612   /* VEX_LEN_0F38F3_R_3_P_0 */
9613   {
9614     { "blsiS",          { VexGdq, Edq } },
9615   },
9616
9617   /* VEX_LEN_0F38F5_P_0 */
9618   {
9619     { "bzhiS",          { Gdq, Edq, VexGdq } },
9620   },
9621
9622   /* VEX_LEN_0F38F5_P_1 */
9623   {
9624     { "pextS",          { Gdq, VexGdq, Edq } },
9625   },
9626
9627   /* VEX_LEN_0F38F5_P_3 */
9628   {
9629     { "pdepS",          { Gdq, VexGdq, Edq } },
9630   },
9631
9632   /* VEX_LEN_0F38F6_P_3 */
9633   {
9634     { "mulxS",          { Gdq, VexGdq, Edq } },
9635   },
9636
9637   /* VEX_LEN_0F38F7_P_0 */
9638   {
9639     { "bextrS",         { Gdq, Edq, VexGdq } },
9640   },
9641
9642   /* VEX_LEN_0F38F7_P_1 */
9643   {
9644     { "sarxS",          { Gdq, Edq, VexGdq } },
9645   },
9646
9647   /* VEX_LEN_0F38F7_P_2 */
9648   {
9649     { "shlxS",          { Gdq, Edq, VexGdq } },
9650   },
9651
9652   /* VEX_LEN_0F38F7_P_3 */
9653   {
9654     { "shrxS",          { Gdq, Edq, VexGdq } },
9655   },
9656
9657   /* VEX_LEN_0F3A00_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F3A01_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9667   },
9668
9669   /* VEX_LEN_0F3A06_P_2 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9673   },
9674
9675   /* VEX_LEN_0F3A0A_P_2 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9678     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9679   },
9680
9681   /* VEX_LEN_0F3A0B_P_2 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9684     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9685   },
9686
9687   /* VEX_LEN_0F3A14_P_2 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A15_P_2 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F3A16_P_2  */
9698   {
9699     { "vpextrK",        { Edq, XM, Ib } },
9700   },
9701
9702   /* VEX_LEN_0F3A17_P_2 */
9703   {
9704     { "vextractps",     { Edqd, XM, Ib } },
9705   },
9706
9707   /* VEX_LEN_0F3A18_P_2 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9711   },
9712
9713   /* VEX_LEN_0F3A19_P_2 */
9714   {
9715     { Bad_Opcode },
9716     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9717   },
9718
9719   /* VEX_LEN_0F3A20_P_2 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A21_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9727   },
9728
9729   /* VEX_LEN_0F3A22_P_2 */
9730   {
9731     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9732   },
9733
9734   /* VEX_LEN_0F3A30_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F3A32_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F3A38_P_2 */
9745   {
9746     { Bad_Opcode },
9747     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9748   },
9749
9750   /* VEX_LEN_0F3A39_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A41_P_2 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A44_P_2 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9764   },
9765
9766   /* VEX_LEN_0F3A46_P_2 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A60_P_2 */
9773   {
9774     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9775   },
9776
9777   /* VEX_LEN_0F3A61_P_2 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9780   },
9781
9782   /* VEX_LEN_0F3A62_P_2 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9785   },
9786
9787   /* VEX_LEN_0F3A63_P_2 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9790   },
9791
9792   /* VEX_LEN_0F3A6A_P_2 */
9793   {
9794     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9795   },
9796
9797   /* VEX_LEN_0F3A6B_P_2 */
9798   {
9799     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9800   },
9801
9802   /* VEX_LEN_0F3A6E_P_2 */
9803   {
9804     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9805   },
9806
9807   /* VEX_LEN_0F3A6F_P_2 */
9808   {
9809     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9810   },
9811
9812   /* VEX_LEN_0F3A7A_P_2 */
9813   {
9814     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9815   },
9816
9817   /* VEX_LEN_0F3A7B_P_2 */
9818   {
9819     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9820   },
9821
9822   /* VEX_LEN_0F3A7E_P_2 */
9823   {
9824     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9825   },
9826
9827   /* VEX_LEN_0F3A7F_P_2 */
9828   {
9829     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9830   },
9831
9832   /* VEX_LEN_0F3ADF_P_2 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9835   },
9836
9837   /* VEX_LEN_0F3AF0_P_3 */
9838   {
9839     { "rorxS",          { Gdq, Edq, Ib } },
9840   },
9841
9842   /* VEX_LEN_0FXOP_08_CC */
9843   {
9844      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9845   },
9846
9847   /* VEX_LEN_0FXOP_08_CD */
9848   {
9849      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9850   },
9851
9852   /* VEX_LEN_0FXOP_08_CE */
9853   {
9854      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_CF */
9858   {
9859      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_EC */
9863   {
9864      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_ED */
9868   {
9869      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_EE */
9873   {
9874      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_EF */
9878   {
9879      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9880   },
9881
9882   /* VEX_LEN_0FXOP_09_80 */
9883   {
9884     { "vfrczps",        { XM, EXxmm } },
9885     { "vfrczps",        { XM, EXymmq } },
9886   },
9887
9888   /* VEX_LEN_0FXOP_09_81 */
9889   {
9890     { "vfrczpd",        { XM, EXxmm } },
9891     { "vfrczpd",        { XM, EXymmq } },
9892   },
9893 };
9894
9895 static const struct dis386 vex_w_table[][2] = {
9896   {
9897     /* VEX_W_0F10_P_0 */
9898     { "vmovups",        { XM, EXx } },
9899   },
9900   {
9901     /* VEX_W_0F10_P_1 */
9902     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9903   },
9904   {
9905     /* VEX_W_0F10_P_2 */
9906     { "vmovupd",        { XM, EXx } },
9907   },
9908   {
9909     /* VEX_W_0F10_P_3 */
9910     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9911   },
9912   {
9913     /* VEX_W_0F11_P_0 */
9914     { "vmovups",        { EXxS, XM } },
9915   },
9916   {
9917     /* VEX_W_0F11_P_1 */
9918     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9919   },
9920   {
9921     /* VEX_W_0F11_P_2 */
9922     { "vmovupd",        { EXxS, XM } },
9923   },
9924   {
9925     /* VEX_W_0F11_P_3 */
9926     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9927   },
9928   {
9929     /* VEX_W_0F12_P_0_M_0 */
9930     { "vmovlps",        { XM, Vex128, EXq } },
9931   },
9932   {
9933     /* VEX_W_0F12_P_0_M_1 */
9934     { "vmovhlps",       { XM, Vex128, EXq } },
9935   },
9936   {
9937     /* VEX_W_0F12_P_1 */
9938     { "vmovsldup",      { XM, EXx } },
9939   },
9940   {
9941     /* VEX_W_0F12_P_2 */
9942     { "vmovlpd",        { XM, Vex128, EXq } },
9943   },
9944   {
9945     /* VEX_W_0F12_P_3 */
9946     { "vmovddup",       { XM, EXymmq } },
9947   },
9948   {
9949     /* VEX_W_0F13_M_0 */
9950     { "vmovlpX",        { EXq, XM } },
9951   },
9952   {
9953     /* VEX_W_0F14 */
9954     { "vunpcklpX",      { XM, Vex, EXx } },
9955   },
9956   {
9957     /* VEX_W_0F15 */
9958     { "vunpckhpX",      { XM, Vex, EXx } },
9959   },
9960   {
9961     /* VEX_W_0F16_P_0_M_0 */
9962     { "vmovhps",        { XM, Vex128, EXq } },
9963   },
9964   {
9965     /* VEX_W_0F16_P_0_M_1 */
9966     { "vmovlhps",       { XM, Vex128, EXq } },
9967   },
9968   {
9969     /* VEX_W_0F16_P_1 */
9970     { "vmovshdup",      { XM, EXx } },
9971   },
9972   {
9973     /* VEX_W_0F16_P_2 */
9974     { "vmovhpd",        { XM, Vex128, EXq } },
9975   },
9976   {
9977     /* VEX_W_0F17_M_0 */
9978     { "vmovhpX",        { EXq, XM } },
9979   },
9980   {
9981     /* VEX_W_0F28 */
9982     { "vmovapX",        { XM, EXx } },
9983   },
9984   {
9985     /* VEX_W_0F29 */
9986     { "vmovapX",        { EXxS, XM } },
9987   },
9988   {
9989     /* VEX_W_0F2B_M_0 */
9990     { "vmovntpX",       { Mx, XM } },
9991   },
9992   {
9993     /* VEX_W_0F2E_P_0 */
9994     { "vucomiss",       { XMScalar, EXdScalar } },
9995   },
9996   {
9997     /* VEX_W_0F2E_P_2 */
9998     { "vucomisd",       { XMScalar, EXqScalar } },
9999   },
10000   {
10001     /* VEX_W_0F2F_P_0 */
10002     { "vcomiss",        { XMScalar, EXdScalar } },
10003   },
10004   {
10005     /* VEX_W_0F2F_P_2 */
10006     { "vcomisd",        { XMScalar, EXqScalar } },
10007   },
10008   {
10009     /* VEX_W_0F41_P_0_LEN_1 */
10010     { "kandw",          { MaskG, MaskVex, MaskR } },
10011   },
10012   {
10013     /* VEX_W_0F42_P_0_LEN_1 */
10014     { "kandnw",         { MaskG, MaskVex, MaskR } },
10015   },
10016   {
10017     /* VEX_W_0F44_P_0_LEN_0 */
10018     { "knotw",          { MaskG, MaskR } },
10019   },
10020   {
10021     /* VEX_W_0F45_P_0_LEN_1 */
10022     { "korw",           { MaskG, MaskVex, MaskR } },
10023   },
10024   {
10025     /* VEX_W_0F46_P_0_LEN_1 */
10026     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10027   },
10028   {
10029     /* VEX_W_0F47_P_0_LEN_1 */
10030     { "kxorw",          { MaskG, MaskVex, MaskR } },
10031   },
10032   {
10033     /* VEX_W_0F4B_P_2_LEN_1 */
10034     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10035   },
10036   {
10037     /* VEX_W_0F50_M_0 */
10038     { "vmovmskpX",      { Gdq, XS } },
10039   },
10040   {
10041     /* VEX_W_0F51_P_0 */
10042     { "vsqrtps",        { XM, EXx } },
10043   },
10044   {
10045     /* VEX_W_0F51_P_1 */
10046     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10047   },
10048   {
10049     /* VEX_W_0F51_P_2  */
10050     { "vsqrtpd",        { XM, EXx } },
10051   },
10052   {
10053     /* VEX_W_0F51_P_3 */
10054     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10055   },
10056   {
10057     /* VEX_W_0F52_P_0 */
10058     { "vrsqrtps",       { XM, EXx } },
10059   },
10060   {
10061     /* VEX_W_0F52_P_1 */
10062     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10063   },
10064   {
10065     /* VEX_W_0F53_P_0  */
10066     { "vrcpps",         { XM, EXx } },
10067   },
10068   {
10069     /* VEX_W_0F53_P_1  */
10070     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10071   },
10072   {
10073     /* VEX_W_0F58_P_0  */
10074     { "vaddps",         { XM, Vex, EXx } },
10075   },
10076   {
10077     /* VEX_W_0F58_P_1  */
10078     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10079   },
10080   {
10081     /* VEX_W_0F58_P_2  */
10082     { "vaddpd",         { XM, Vex, EXx } },
10083   },
10084   {
10085     /* VEX_W_0F58_P_3  */
10086     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10087   },
10088   {
10089     /* VEX_W_0F59_P_0  */
10090     { "vmulps",         { XM, Vex, EXx } },
10091   },
10092   {
10093     /* VEX_W_0F59_P_1  */
10094     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10095   },
10096   {
10097     /* VEX_W_0F59_P_2  */
10098     { "vmulpd",         { XM, Vex, EXx } },
10099   },
10100   {
10101     /* VEX_W_0F59_P_3  */
10102     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10103   },
10104   {
10105     /* VEX_W_0F5A_P_0  */
10106     { "vcvtps2pd",      { XM, EXxmmq } },
10107   },
10108   {
10109     /* VEX_W_0F5A_P_1  */
10110     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10111   },
10112   {
10113     /* VEX_W_0F5A_P_3  */
10114     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10115   },
10116   {
10117     /* VEX_W_0F5B_P_0  */
10118     { "vcvtdq2ps",      { XM, EXx } },
10119   },
10120   {
10121     /* VEX_W_0F5B_P_1  */
10122     { "vcvttps2dq",     { XM, EXx } },
10123   },
10124   {
10125     /* VEX_W_0F5B_P_2  */
10126     { "vcvtps2dq",      { XM, EXx } },
10127   },
10128   {
10129     /* VEX_W_0F5C_P_0  */
10130     { "vsubps",         { XM, Vex, EXx } },
10131   },
10132   {
10133     /* VEX_W_0F5C_P_1  */
10134     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10135   },
10136   {
10137     /* VEX_W_0F5C_P_2  */
10138     { "vsubpd",         { XM, Vex, EXx } },
10139   },
10140   {
10141     /* VEX_W_0F5C_P_3  */
10142     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10143   },
10144   {
10145     /* VEX_W_0F5D_P_0  */
10146     { "vminps",         { XM, Vex, EXx } },
10147   },
10148   {
10149     /* VEX_W_0F5D_P_1  */
10150     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10151   },
10152   {
10153     /* VEX_W_0F5D_P_2  */
10154     { "vminpd",         { XM, Vex, EXx } },
10155   },
10156   {
10157     /* VEX_W_0F5D_P_3  */
10158     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10159   },
10160   {
10161     /* VEX_W_0F5E_P_0  */
10162     { "vdivps",         { XM, Vex, EXx } },
10163   },
10164   {
10165     /* VEX_W_0F5E_P_1  */
10166     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10167   },
10168   {
10169     /* VEX_W_0F5E_P_2  */
10170     { "vdivpd",         { XM, Vex, EXx } },
10171   },
10172   {
10173     /* VEX_W_0F5E_P_3  */
10174     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10175   },
10176   {
10177     /* VEX_W_0F5F_P_0  */
10178     { "vmaxps",         { XM, Vex, EXx } },
10179   },
10180   {
10181     /* VEX_W_0F5F_P_1  */
10182     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10183   },
10184   {
10185     /* VEX_W_0F5F_P_2  */
10186     { "vmaxpd",         { XM, Vex, EXx } },
10187   },
10188   {
10189     /* VEX_W_0F5F_P_3  */
10190     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10191   },
10192   {
10193     /* VEX_W_0F60_P_2  */
10194     { "vpunpcklbw",     { XM, Vex, EXx } },
10195   },
10196   {
10197     /* VEX_W_0F61_P_2  */
10198     { "vpunpcklwd",     { XM, Vex, EXx } },
10199   },
10200   {
10201     /* VEX_W_0F62_P_2  */
10202     { "vpunpckldq",     { XM, Vex, EXx } },
10203   },
10204   {
10205     /* VEX_W_0F63_P_2  */
10206     { "vpacksswb",      { XM, Vex, EXx } },
10207   },
10208   {
10209     /* VEX_W_0F64_P_2  */
10210     { "vpcmpgtb",       { XM, Vex, EXx } },
10211   },
10212   {
10213     /* VEX_W_0F65_P_2  */
10214     { "vpcmpgtw",       { XM, Vex, EXx } },
10215   },
10216   {
10217     /* VEX_W_0F66_P_2  */
10218     { "vpcmpgtd",       { XM, Vex, EXx } },
10219   },
10220   {
10221     /* VEX_W_0F67_P_2  */
10222     { "vpackuswb",      { XM, Vex, EXx } },
10223   },
10224   {
10225     /* VEX_W_0F68_P_2  */
10226     { "vpunpckhbw",     { XM, Vex, EXx } },
10227   },
10228   {
10229     /* VEX_W_0F69_P_2  */
10230     { "vpunpckhwd",     { XM, Vex, EXx } },
10231   },
10232   {
10233     /* VEX_W_0F6A_P_2  */
10234     { "vpunpckhdq",     { XM, Vex, EXx } },
10235   },
10236   {
10237     /* VEX_W_0F6B_P_2  */
10238     { "vpackssdw",      { XM, Vex, EXx } },
10239   },
10240   {
10241     /* VEX_W_0F6C_P_2  */
10242     { "vpunpcklqdq",    { XM, Vex, EXx } },
10243   },
10244   {
10245     /* VEX_W_0F6D_P_2  */
10246     { "vpunpckhqdq",    { XM, Vex, EXx } },
10247   },
10248   {
10249     /* VEX_W_0F6F_P_1  */
10250     { "vmovdqu",        { XM, EXx } },
10251   },
10252   {
10253     /* VEX_W_0F6F_P_2  */
10254     { "vmovdqa",        { XM, EXx } },
10255   },
10256   {
10257     /* VEX_W_0F70_P_1 */
10258     { "vpshufhw",       { XM, EXx, Ib } },
10259   },
10260   {
10261     /* VEX_W_0F70_P_2 */
10262     { "vpshufd",        { XM, EXx, Ib } },
10263   },
10264   {
10265     /* VEX_W_0F70_P_3 */
10266     { "vpshuflw",       { XM, EXx, Ib } },
10267   },
10268   {
10269     /* VEX_W_0F71_R_2_P_2  */
10270     { "vpsrlw",         { Vex, XS, Ib } },
10271   },
10272   {
10273     /* VEX_W_0F71_R_4_P_2  */
10274     { "vpsraw",         { Vex, XS, Ib } },
10275   },
10276   {
10277     /* VEX_W_0F71_R_6_P_2  */
10278     { "vpsllw",         { Vex, XS, Ib } },
10279   },
10280   {
10281     /* VEX_W_0F72_R_2_P_2  */
10282     { "vpsrld",         { Vex, XS, Ib } },
10283   },
10284   {
10285     /* VEX_W_0F72_R_4_P_2  */
10286     { "vpsrad",         { Vex, XS, Ib } },
10287   },
10288   {
10289     /* VEX_W_0F72_R_6_P_2  */
10290     { "vpslld",         { Vex, XS, Ib } },
10291   },
10292   {
10293     /* VEX_W_0F73_R_2_P_2  */
10294     { "vpsrlq",         { Vex, XS, Ib } },
10295   },
10296   {
10297     /* VEX_W_0F73_R_3_P_2  */
10298     { "vpsrldq",        { Vex, XS, Ib } },
10299   },
10300   {
10301     /* VEX_W_0F73_R_6_P_2  */
10302     { "vpsllq",         { Vex, XS, Ib } },
10303   },
10304   {
10305     /* VEX_W_0F73_R_7_P_2  */
10306     { "vpslldq",        { Vex, XS, Ib } },
10307   },
10308   {
10309     /* VEX_W_0F74_P_2 */
10310     { "vpcmpeqb",       { XM, Vex, EXx } },
10311   },
10312   {
10313     /* VEX_W_0F75_P_2 */
10314     { "vpcmpeqw",       { XM, Vex, EXx } },
10315   },
10316   {
10317     /* VEX_W_0F76_P_2 */
10318     { "vpcmpeqd",       { XM, Vex, EXx } },
10319   },
10320   {
10321     /* VEX_W_0F77_P_0 */
10322     { "",               { VZERO } },
10323   },
10324   {
10325     /* VEX_W_0F7C_P_2 */
10326     { "vhaddpd",        { XM, Vex, EXx } },
10327   },
10328   {
10329     /* VEX_W_0F7C_P_3 */
10330     { "vhaddps",        { XM, Vex, EXx } },
10331   },
10332   {
10333     /* VEX_W_0F7D_P_2 */
10334     { "vhsubpd",        { XM, Vex, EXx } },
10335   },
10336   {
10337     /* VEX_W_0F7D_P_3 */
10338     { "vhsubps",        { XM, Vex, EXx } },
10339   },
10340   {
10341     /* VEX_W_0F7E_P_1 */
10342     { "vmovq",          { XMScalar, EXqScalar } },
10343   },
10344   {
10345     /* VEX_W_0F7F_P_1 */
10346     { "vmovdqu",        { EXxS, XM } },
10347   },
10348   {
10349     /* VEX_W_0F7F_P_2 */
10350     { "vmovdqa",        { EXxS, XM } },
10351   },
10352   {
10353     /* VEX_W_0F90_P_0_LEN_0 */
10354     { "kmovw",          { MaskG, MaskE } },
10355   },
10356   {
10357     /* VEX_W_0F91_P_0_LEN_0 */
10358     { "kmovw",          { Ew, MaskG } },
10359   },
10360   {
10361     /* VEX_W_0F92_P_0_LEN_0 */
10362     { "kmovw",          { MaskG, Rdq } },
10363   },
10364   {
10365     /* VEX_W_0F93_P_0_LEN_0 */
10366     { "kmovw",          { Gdq, MaskR } },
10367   },
10368   {
10369     /* VEX_W_0F98_P_0_LEN_0 */
10370     { "kortestw",       { MaskG, MaskR } },
10371   },
10372   {
10373     /* VEX_W_0FAE_R_2_M_0 */
10374     { "vldmxcsr",       { Md } },
10375   },
10376   {
10377     /* VEX_W_0FAE_R_3_M_0 */
10378     { "vstmxcsr",       { Md } },
10379   },
10380   {
10381     /* VEX_W_0FC2_P_0 */
10382     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10383   },
10384   {
10385     /* VEX_W_0FC2_P_1 */
10386     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10387   },
10388   {
10389     /* VEX_W_0FC2_P_2 */
10390     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10391   },
10392   {
10393     /* VEX_W_0FC2_P_3 */
10394     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10395   },
10396   {
10397     /* VEX_W_0FC4_P_2 */
10398     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10399   },
10400   {
10401     /* VEX_W_0FC5_P_2 */
10402     { "vpextrw",        { Gdq, XS, Ib } },
10403   },
10404   {
10405     /* VEX_W_0FD0_P_2 */
10406     { "vaddsubpd",      { XM, Vex, EXx } },
10407   },
10408   {
10409     /* VEX_W_0FD0_P_3 */
10410     { "vaddsubps",      { XM, Vex, EXx } },
10411   },
10412   {
10413     /* VEX_W_0FD1_P_2 */
10414     { "vpsrlw",         { XM, Vex, EXxmm } },
10415   },
10416   {
10417     /* VEX_W_0FD2_P_2 */
10418     { "vpsrld",         { XM, Vex, EXxmm } },
10419   },
10420   {
10421     /* VEX_W_0FD3_P_2 */
10422     { "vpsrlq",         { XM, Vex, EXxmm } },
10423   },
10424   {
10425     /* VEX_W_0FD4_P_2 */
10426     { "vpaddq",         { XM, Vex, EXx } },
10427   },
10428   {
10429     /* VEX_W_0FD5_P_2 */
10430     { "vpmullw",        { XM, Vex, EXx } },
10431   },
10432   {
10433     /* VEX_W_0FD6_P_2 */
10434     { "vmovq",          { EXqScalarS, XMScalar } },
10435   },
10436   {
10437     /* VEX_W_0FD7_P_2_M_1 */
10438     { "vpmovmskb",      { Gdq, XS } },
10439   },
10440   {
10441     /* VEX_W_0FD8_P_2 */
10442     { "vpsubusb",       { XM, Vex, EXx } },
10443   },
10444   {
10445     /* VEX_W_0FD9_P_2 */
10446     { "vpsubusw",       { XM, Vex, EXx } },
10447   },
10448   {
10449     /* VEX_W_0FDA_P_2 */
10450     { "vpminub",        { XM, Vex, EXx } },
10451   },
10452   {
10453     /* VEX_W_0FDB_P_2 */
10454     { "vpand",          { XM, Vex, EXx } },
10455   },
10456   {
10457     /* VEX_W_0FDC_P_2 */
10458     { "vpaddusb",       { XM, Vex, EXx } },
10459   },
10460   {
10461     /* VEX_W_0FDD_P_2 */
10462     { "vpaddusw",       { XM, Vex, EXx } },
10463   },
10464   {
10465     /* VEX_W_0FDE_P_2 */
10466     { "vpmaxub",        { XM, Vex, EXx } },
10467   },
10468   {
10469     /* VEX_W_0FDF_P_2 */
10470     { "vpandn",         { XM, Vex, EXx } },
10471   },
10472   {
10473     /* VEX_W_0FE0_P_2  */
10474     { "vpavgb",         { XM, Vex, EXx } },
10475   },
10476   {
10477     /* VEX_W_0FE1_P_2  */
10478     { "vpsraw",         { XM, Vex, EXxmm } },
10479   },
10480   {
10481     /* VEX_W_0FE2_P_2  */
10482     { "vpsrad",         { XM, Vex, EXxmm } },
10483   },
10484   {
10485     /* VEX_W_0FE3_P_2  */
10486     { "vpavgw",         { XM, Vex, EXx } },
10487   },
10488   {
10489     /* VEX_W_0FE4_P_2  */
10490     { "vpmulhuw",       { XM, Vex, EXx } },
10491   },
10492   {
10493     /* VEX_W_0FE5_P_2  */
10494     { "vpmulhw",        { XM, Vex, EXx } },
10495   },
10496   {
10497     /* VEX_W_0FE6_P_1  */
10498     { "vcvtdq2pd",      { XM, EXxmmq } },
10499   },
10500   {
10501     /* VEX_W_0FE6_P_2  */
10502     { "vcvttpd2dq%XY",  { XMM, EXx } },
10503   },
10504   {
10505     /* VEX_W_0FE6_P_3  */
10506     { "vcvtpd2dq%XY",   { XMM, EXx } },
10507   },
10508   {
10509     /* VEX_W_0FE7_P_2_M_0 */
10510     { "vmovntdq",       { Mx, XM } },
10511   },
10512   {
10513     /* VEX_W_0FE8_P_2  */
10514     { "vpsubsb",        { XM, Vex, EXx } },
10515   },
10516   {
10517     /* VEX_W_0FE9_P_2  */
10518     { "vpsubsw",        { XM, Vex, EXx } },
10519   },
10520   {
10521     /* VEX_W_0FEA_P_2  */
10522     { "vpminsw",        { XM, Vex, EXx } },
10523   },
10524   {
10525     /* VEX_W_0FEB_P_2  */
10526     { "vpor",           { XM, Vex, EXx } },
10527   },
10528   {
10529     /* VEX_W_0FEC_P_2  */
10530     { "vpaddsb",        { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0FED_P_2  */
10534     { "vpaddsw",        { XM, Vex, EXx } },
10535   },
10536   {
10537     /* VEX_W_0FEE_P_2  */
10538     { "vpmaxsw",        { XM, Vex, EXx } },
10539   },
10540   {
10541     /* VEX_W_0FEF_P_2  */
10542     { "vpxor",          { XM, Vex, EXx } },
10543   },
10544   {
10545     /* VEX_W_0FF0_P_3_M_0 */
10546     { "vlddqu",         { XM, M } },
10547   },
10548   {
10549     /* VEX_W_0FF1_P_2 */
10550     { "vpsllw",         { XM, Vex, EXxmm } },
10551   },
10552   {
10553     /* VEX_W_0FF2_P_2 */
10554     { "vpslld",         { XM, Vex, EXxmm } },
10555   },
10556   {
10557     /* VEX_W_0FF3_P_2 */
10558     { "vpsllq",         { XM, Vex, EXxmm } },
10559   },
10560   {
10561     /* VEX_W_0FF4_P_2 */
10562     { "vpmuludq",       { XM, Vex, EXx } },
10563   },
10564   {
10565     /* VEX_W_0FF5_P_2 */
10566     { "vpmaddwd",       { XM, Vex, EXx } },
10567   },
10568   {
10569     /* VEX_W_0FF6_P_2 */
10570     { "vpsadbw",        { XM, Vex, EXx } },
10571   },
10572   {
10573     /* VEX_W_0FF7_P_2 */
10574     { "vmaskmovdqu",    { XM, XS } },
10575   },
10576   {
10577     /* VEX_W_0FF8_P_2 */
10578     { "vpsubb",         { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0FF9_P_2 */
10582     { "vpsubw",         { XM, Vex, EXx } },
10583   },
10584   {
10585     /* VEX_W_0FFA_P_2 */
10586     { "vpsubd",         { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0FFB_P_2 */
10590     { "vpsubq",         { XM, Vex, EXx } },
10591   },
10592   {
10593     /* VEX_W_0FFC_P_2 */
10594     { "vpaddb",         { XM, Vex, EXx } },
10595   },
10596   {
10597     /* VEX_W_0FFD_P_2 */
10598     { "vpaddw",         { XM, Vex, EXx } },
10599   },
10600   {
10601     /* VEX_W_0FFE_P_2 */
10602     { "vpaddd",         { XM, Vex, EXx } },
10603   },
10604   {
10605     /* VEX_W_0F3800_P_2  */
10606     { "vpshufb",        { XM, Vex, EXx } },
10607   },
10608   {
10609     /* VEX_W_0F3801_P_2  */
10610     { "vphaddw",        { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0F3802_P_2  */
10614     { "vphaddd",        { XM, Vex, EXx } },
10615   },
10616   {
10617     /* VEX_W_0F3803_P_2  */
10618     { "vphaddsw",       { XM, Vex, EXx } },
10619   },
10620   {
10621     /* VEX_W_0F3804_P_2  */
10622     { "vpmaddubsw",     { XM, Vex, EXx } },
10623   },
10624   {
10625     /* VEX_W_0F3805_P_2  */
10626     { "vphsubw",        { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0F3806_P_2  */
10630     { "vphsubd",        { XM, Vex, EXx } },
10631   },
10632   {
10633     /* VEX_W_0F3807_P_2  */
10634     { "vphsubsw",       { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0F3808_P_2  */
10638     { "vpsignb",        { XM, Vex, EXx } },
10639   },
10640   {
10641     /* VEX_W_0F3809_P_2  */
10642     { "vpsignw",        { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0F380A_P_2  */
10646     { "vpsignd",        { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F380B_P_2  */
10650     { "vpmulhrsw",      { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F380C_P_2  */
10654     { "vpermilps",      { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F380D_P_2  */
10658     { "vpermilpd",      { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F380E_P_2  */
10662     { "vtestps",        { XM, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F380F_P_2  */
10666     { "vtestpd",        { XM, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F3816_P_2  */
10670     { "vpermps",        { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F3817_P_2 */
10674     { "vptest",         { XM, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F3818_P_2 */
10678     { "vbroadcastss",   { XM, EXxmm_md } },
10679   },
10680   {
10681     /* VEX_W_0F3819_P_2 */
10682     { "vbroadcastsd",   { XM, EXxmm_mq } },
10683   },
10684   {
10685     /* VEX_W_0F381A_P_2_M_0 */
10686     { "vbroadcastf128", { XM, Mxmm } },
10687   },
10688   {
10689     /* VEX_W_0F381C_P_2 */
10690     { "vpabsb",         { XM, EXx } },
10691   },
10692   {
10693     /* VEX_W_0F381D_P_2 */
10694     { "vpabsw",         { XM, EXx } },
10695   },
10696   {
10697     /* VEX_W_0F381E_P_2 */
10698     { "vpabsd",         { XM, EXx } },
10699   },
10700   {
10701     /* VEX_W_0F3820_P_2 */
10702     { "vpmovsxbw",      { XM, EXxmmq } },
10703   },
10704   {
10705     /* VEX_W_0F3821_P_2 */
10706     { "vpmovsxbd",      { XM, EXxmmqd } },
10707   },
10708   {
10709     /* VEX_W_0F3822_P_2 */
10710     { "vpmovsxbq",      { XM, EXxmmdw } },
10711   },
10712   {
10713     /* VEX_W_0F3823_P_2 */
10714     { "vpmovsxwd",      { XM, EXxmmq } },
10715   },
10716   {
10717     /* VEX_W_0F3824_P_2 */
10718     { "vpmovsxwq",      { XM, EXxmmqd } },
10719   },
10720   {
10721     /* VEX_W_0F3825_P_2 */
10722     { "vpmovsxdq",      { XM, EXxmmq } },
10723   },
10724   {
10725     /* VEX_W_0F3828_P_2 */
10726     { "vpmuldq",        { XM, Vex, EXx } },
10727   },
10728   {
10729     /* VEX_W_0F3829_P_2 */
10730     { "vpcmpeqq",       { XM, Vex, EXx } },
10731   },
10732   {
10733     /* VEX_W_0F382A_P_2_M_0 */
10734     { "vmovntdqa",      { XM, Mx } },
10735   },
10736   {
10737     /* VEX_W_0F382B_P_2 */
10738     { "vpackusdw",      { XM, Vex, EXx } },
10739   },
10740   {
10741     /* VEX_W_0F382C_P_2_M_0 */
10742     { "vmaskmovps",     { XM, Vex, Mx } },
10743   },
10744   {
10745     /* VEX_W_0F382D_P_2_M_0 */
10746     { "vmaskmovpd",     { XM, Vex, Mx } },
10747   },
10748   {
10749     /* VEX_W_0F382E_P_2_M_0 */
10750     { "vmaskmovps",     { Mx, Vex, XM } },
10751   },
10752   {
10753     /* VEX_W_0F382F_P_2_M_0 */
10754     { "vmaskmovpd",     { Mx, Vex, XM } },
10755   },
10756   {
10757     /* VEX_W_0F3830_P_2 */
10758     { "vpmovzxbw",      { XM, EXxmmq } },
10759   },
10760   {
10761     /* VEX_W_0F3831_P_2 */
10762     { "vpmovzxbd",      { XM, EXxmmqd } },
10763   },
10764   {
10765     /* VEX_W_0F3832_P_2 */
10766     { "vpmovzxbq",      { XM, EXxmmdw } },
10767   },
10768   {
10769     /* VEX_W_0F3833_P_2 */
10770     { "vpmovzxwd",      { XM, EXxmmq } },
10771   },
10772   {
10773     /* VEX_W_0F3834_P_2 */
10774     { "vpmovzxwq",      { XM, EXxmmqd } },
10775   },
10776   {
10777     /* VEX_W_0F3835_P_2 */
10778     { "vpmovzxdq",      { XM, EXxmmq } },
10779   },
10780   {
10781     /* VEX_W_0F3836_P_2  */
10782     { "vpermd",         { XM, Vex, EXx } },
10783   },
10784   {
10785     /* VEX_W_0F3837_P_2 */
10786     { "vpcmpgtq",       { XM, Vex, EXx } },
10787   },
10788   {
10789     /* VEX_W_0F3838_P_2 */
10790     { "vpminsb",        { XM, Vex, EXx } },
10791   },
10792   {
10793     /* VEX_W_0F3839_P_2 */
10794     { "vpminsd",        { XM, Vex, EXx } },
10795   },
10796   {
10797     /* VEX_W_0F383A_P_2 */
10798     { "vpminuw",        { XM, Vex, EXx } },
10799   },
10800   {
10801     /* VEX_W_0F383B_P_2 */
10802     { "vpminud",        { XM, Vex, EXx } },
10803   },
10804   {
10805     /* VEX_W_0F383C_P_2 */
10806     { "vpmaxsb",        { XM, Vex, EXx } },
10807   },
10808   {
10809     /* VEX_W_0F383D_P_2 */
10810     { "vpmaxsd",        { XM, Vex, EXx } },
10811   },
10812   {
10813     /* VEX_W_0F383E_P_2 */
10814     { "vpmaxuw",        { XM, Vex, EXx } },
10815   },
10816   {
10817     /* VEX_W_0F383F_P_2 */
10818     { "vpmaxud",        { XM, Vex, EXx } },
10819   },
10820   {
10821     /* VEX_W_0F3840_P_2 */
10822     { "vpmulld",        { XM, Vex, EXx } },
10823   },
10824   {
10825     /* VEX_W_0F3841_P_2 */
10826     { "vphminposuw",    { XM, EXx } },
10827   },
10828   {
10829     /* VEX_W_0F3846_P_2 */
10830     { "vpsravd",        { XM, Vex, EXx } },
10831   },
10832   {
10833     /* VEX_W_0F3858_P_2 */
10834     { "vpbroadcastd", { XM, EXxmm_md } },
10835   },
10836   {
10837     /* VEX_W_0F3859_P_2 */
10838     { "vpbroadcastq",   { XM, EXxmm_mq } },
10839   },
10840   {
10841     /* VEX_W_0F385A_P_2_M_0 */
10842     { "vbroadcasti128", { XM, Mxmm } },
10843   },
10844   {
10845     /* VEX_W_0F3878_P_2 */
10846     { "vpbroadcastb",   { XM, EXxmm_mb } },
10847   },
10848   {
10849     /* VEX_W_0F3879_P_2 */
10850     { "vpbroadcastw",   { XM, EXxmm_mw } },
10851   },
10852   {
10853     /* VEX_W_0F38DB_P_2 */
10854     { "vaesimc",        { XM, EXx } },
10855   },
10856   {
10857     /* VEX_W_0F38DC_P_2 */
10858     { "vaesenc",        { XM, Vex128, EXx } },
10859   },
10860   {
10861     /* VEX_W_0F38DD_P_2 */
10862     { "vaesenclast",    { XM, Vex128, EXx } },
10863   },
10864   {
10865     /* VEX_W_0F38DE_P_2 */
10866     { "vaesdec",        { XM, Vex128, EXx } },
10867   },
10868   {
10869     /* VEX_W_0F38DF_P_2 */
10870     { "vaesdeclast",    { XM, Vex128, EXx } },
10871   },
10872   {
10873     /* VEX_W_0F3A00_P_2 */
10874     { Bad_Opcode },
10875     { "vpermq",         { XM, EXx, Ib } },
10876   },
10877   {
10878     /* VEX_W_0F3A01_P_2 */
10879     { Bad_Opcode },
10880     { "vpermpd",        { XM, EXx, Ib } },
10881   },
10882   {
10883     /* VEX_W_0F3A02_P_2 */
10884     { "vpblendd",       { XM, Vex, EXx, Ib } },
10885   },
10886   {
10887     /* VEX_W_0F3A04_P_2 */
10888     { "vpermilps",      { XM, EXx, Ib } },
10889   },
10890   {
10891     /* VEX_W_0F3A05_P_2 */
10892     { "vpermilpd",      { XM, EXx, Ib } },
10893   },
10894   {
10895     /* VEX_W_0F3A06_P_2 */
10896     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10897   },
10898   {
10899     /* VEX_W_0F3A08_P_2 */
10900     { "vroundps",       { XM, EXx, Ib } },
10901   },
10902   {
10903     /* VEX_W_0F3A09_P_2 */
10904     { "vroundpd",       { XM, EXx, Ib } },
10905   },
10906   {
10907     /* VEX_W_0F3A0A_P_2 */
10908     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10909   },
10910   {
10911     /* VEX_W_0F3A0B_P_2 */
10912     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10913   },
10914   {
10915     /* VEX_W_0F3A0C_P_2 */
10916     { "vblendps",       { XM, Vex, EXx, Ib } },
10917   },
10918   {
10919     /* VEX_W_0F3A0D_P_2 */
10920     { "vblendpd",       { XM, Vex, EXx, Ib } },
10921   },
10922   {
10923     /* VEX_W_0F3A0E_P_2 */
10924     { "vpblendw",       { XM, Vex, EXx, Ib } },
10925   },
10926   {
10927     /* VEX_W_0F3A0F_P_2 */
10928     { "vpalignr",       { XM, Vex, EXx, Ib } },
10929   },
10930   {
10931     /* VEX_W_0F3A14_P_2 */
10932     { "vpextrb",        { Edqb, XM, Ib } },
10933   },
10934   {
10935     /* VEX_W_0F3A15_P_2 */
10936     { "vpextrw",        { Edqw, XM, Ib } },
10937   },
10938   {
10939     /* VEX_W_0F3A18_P_2 */
10940     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10941   },
10942   {
10943     /* VEX_W_0F3A19_P_2 */
10944     { "vextractf128",   { EXxmm, XM, Ib } },
10945   },
10946   {
10947     /* VEX_W_0F3A20_P_2 */
10948     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10949   },
10950   {
10951     /* VEX_W_0F3A21_P_2 */
10952     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10953   },
10954   {
10955     /* VEX_W_0F3A30_P_2 */
10956     { Bad_Opcode },
10957     { "kshiftrw",       { MaskG, MaskR, Ib } },
10958   },
10959   {
10960     /* VEX_W_0F3A32_P_2 */
10961     { Bad_Opcode },
10962     { "kshiftlw",       { MaskG, MaskR, Ib } },
10963   },
10964   {
10965     /* VEX_W_0F3A38_P_2 */
10966     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10967   },
10968   {
10969     /* VEX_W_0F3A39_P_2 */
10970     { "vextracti128",   { EXxmm, XM, Ib } },
10971   },
10972   {
10973     /* VEX_W_0F3A40_P_2 */
10974     { "vdpps",          { XM, Vex, EXx, Ib } },
10975   },
10976   {
10977     /* VEX_W_0F3A41_P_2 */
10978     { "vdppd",          { XM, Vex128, EXx, Ib } },
10979   },
10980   {
10981     /* VEX_W_0F3A42_P_2 */
10982     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10983   },
10984   {
10985     /* VEX_W_0F3A44_P_2 */
10986     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10987   },
10988   {
10989     /* VEX_W_0F3A46_P_2 */
10990     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10991   },
10992   {
10993     /* VEX_W_0F3A48_P_2 */
10994     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10995     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10996   },
10997   {
10998     /* VEX_W_0F3A49_P_2 */
10999     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11000     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11001   },
11002   {
11003     /* VEX_W_0F3A4A_P_2 */
11004     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11005   },
11006   {
11007     /* VEX_W_0F3A4B_P_2 */
11008     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11009   },
11010   {
11011     /* VEX_W_0F3A4C_P_2 */
11012     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11013   },
11014   {
11015     /* VEX_W_0F3A60_P_2 */
11016     { "vpcmpestrm",     { XM, EXx, Ib } },
11017   },
11018   {
11019     /* VEX_W_0F3A61_P_2 */
11020     { "vpcmpestri",     { XM, EXx, Ib } },
11021   },
11022   {
11023     /* VEX_W_0F3A62_P_2 */
11024     { "vpcmpistrm",     { XM, EXx, Ib } },
11025   },
11026   {
11027     /* VEX_W_0F3A63_P_2 */
11028     { "vpcmpistri",     { XM, EXx, Ib } },
11029   },
11030   {
11031     /* VEX_W_0F3ADF_P_2 */
11032     { "vaeskeygenassist", { XM, EXx, Ib } },
11033   },
11034 #define NEED_VEX_W_TABLE
11035 #include "i386-dis-evex.h"
11036 #undef NEED_VEX_W_TABLE
11037 };
11038
11039 static const struct dis386 mod_table[][2] = {
11040   {
11041     /* MOD_8D */
11042     { "leaS",           { Gv, M } },
11043   },
11044   {
11045     /* MOD_C6_REG_7 */
11046     { Bad_Opcode },
11047     { RM_TABLE (RM_C6_REG_7) },
11048   },
11049   {
11050     /* MOD_C7_REG_7 */
11051     { Bad_Opcode },
11052     { RM_TABLE (RM_C7_REG_7) },
11053   },
11054   {
11055     /* MOD_FF_REG_3 */
11056     { "Jcall{T|}", { indirEp } },
11057   },
11058   {
11059     /* MOD_FF_REG_5 */
11060     { "Jjmp{T|}", { indirEp } },
11061   },
11062   {
11063     /* MOD_0F01_REG_0 */
11064     { X86_64_TABLE (X86_64_0F01_REG_0) },
11065     { RM_TABLE (RM_0F01_REG_0) },
11066   },
11067   {
11068     /* MOD_0F01_REG_1 */
11069     { X86_64_TABLE (X86_64_0F01_REG_1) },
11070     { RM_TABLE (RM_0F01_REG_1) },
11071   },
11072   {
11073     /* MOD_0F01_REG_2 */
11074     { X86_64_TABLE (X86_64_0F01_REG_2) },
11075     { RM_TABLE (RM_0F01_REG_2) },
11076   },
11077   {
11078     /* MOD_0F01_REG_3 */
11079     { X86_64_TABLE (X86_64_0F01_REG_3) },
11080     { RM_TABLE (RM_0F01_REG_3) },
11081   },
11082   {
11083     /* MOD_0F01_REG_7 */
11084     { "invlpg",         { Mb } },
11085     { RM_TABLE (RM_0F01_REG_7) },
11086   },
11087   {
11088     /* MOD_0F12_PREFIX_0 */
11089     { "movlps",         { XM, EXq } },
11090     { "movhlps",        { XM, EXq } },
11091   },
11092   {
11093     /* MOD_0F13 */
11094     { "movlpX",         { EXq, XM } },
11095   },
11096   {
11097     /* MOD_0F16_PREFIX_0 */
11098     { "movhps",         { XM, EXq } },
11099     { "movlhps",        { XM, EXq } },
11100   },
11101   {
11102     /* MOD_0F17 */
11103     { "movhpX",         { EXq, XM } },
11104   },
11105   {
11106     /* MOD_0F18_REG_0 */
11107     { "prefetchnta",    { Mb } },
11108   },
11109   {
11110     /* MOD_0F18_REG_1 */
11111     { "prefetcht0",     { Mb } },
11112   },
11113   {
11114     /* MOD_0F18_REG_2 */
11115     { "prefetcht1",     { Mb } },
11116   },
11117   {
11118     /* MOD_0F18_REG_3 */
11119     { "prefetcht2",     { Mb } },
11120   },
11121   {
11122     /* MOD_0F18_REG_4 */
11123     { "nop/reserved",   { Mb } },
11124   },
11125   {
11126     /* MOD_0F18_REG_5 */
11127     { "nop/reserved",   { Mb } },
11128   },
11129   {
11130     /* MOD_0F18_REG_6 */
11131     { "nop/reserved",   { Mb } },
11132   },
11133   {
11134     /* MOD_0F18_REG_7 */
11135     { "nop/reserved",   { Mb } },
11136   },
11137   {
11138     /* MOD_0F1A_PREFIX_0 */
11139     { "bndldx",         { Gbnd, Ev_bnd } },
11140     { "nopQ",           { Ev } },
11141   },
11142   {
11143     /* MOD_0F1B_PREFIX_0 */
11144     { "bndstx",         { Ev_bnd, Gbnd } },
11145     { "nopQ",           { Ev } },
11146   },
11147   {
11148     /* MOD_0F1B_PREFIX_1 */
11149     { "bndmk",          { Gbnd, Ev_bnd } },
11150     { "nopQ",           { Ev } },
11151   },
11152   {
11153     /* MOD_0F20 */
11154     { Bad_Opcode },
11155     { "movZ",           { Rm, Cm } },
11156   },
11157   {
11158     /* MOD_0F21 */
11159     { Bad_Opcode },
11160     { "movZ",           { Rm, Dm } },
11161   },
11162   {
11163     /* MOD_0F22 */
11164     { Bad_Opcode },
11165     { "movZ",           { Cm, Rm } },
11166   },
11167   {
11168     /* MOD_0F23 */
11169     { Bad_Opcode },
11170     { "movZ",           { Dm, Rm } },
11171   },
11172   {
11173     /* MOD_0F24 */
11174     { Bad_Opcode },
11175     { "movL",           { Rd, Td } },
11176   },
11177   {
11178     /* MOD_0F26 */
11179     { Bad_Opcode },
11180     { "movL",           { Td, Rd } },
11181   },
11182   {
11183     /* MOD_0F2B_PREFIX_0 */
11184     {"movntps",         { Mx, XM } },
11185   },
11186   {
11187     /* MOD_0F2B_PREFIX_1 */
11188     {"movntss",         { Md, XM } },
11189   },
11190   {
11191     /* MOD_0F2B_PREFIX_2 */
11192     {"movntpd",         { Mx, XM } },
11193   },
11194   {
11195     /* MOD_0F2B_PREFIX_3 */
11196     {"movntsd",         { Mq, XM } },
11197   },
11198   {
11199     /* MOD_0F51 */
11200     { Bad_Opcode },
11201     { "movmskpX",       { Gdq, XS } },
11202   },
11203   {
11204     /* MOD_0F71_REG_2 */
11205     { Bad_Opcode },
11206     { "psrlw",          { MS, Ib } },
11207   },
11208   {
11209     /* MOD_0F71_REG_4 */
11210     { Bad_Opcode },
11211     { "psraw",          { MS, Ib } },
11212   },
11213   {
11214     /* MOD_0F71_REG_6 */
11215     { Bad_Opcode },
11216     { "psllw",          { MS, Ib } },
11217   },
11218   {
11219     /* MOD_0F72_REG_2 */
11220     { Bad_Opcode },
11221     { "psrld",          { MS, Ib } },
11222   },
11223   {
11224     /* MOD_0F72_REG_4 */
11225     { Bad_Opcode },
11226     { "psrad",          { MS, Ib } },
11227   },
11228   {
11229     /* MOD_0F72_REG_6 */
11230     { Bad_Opcode },
11231     { "pslld",          { MS, Ib } },
11232   },
11233   {
11234     /* MOD_0F73_REG_2 */
11235     { Bad_Opcode },
11236     { "psrlq",          { MS, Ib } },
11237   },
11238   {
11239     /* MOD_0F73_REG_3 */
11240     { Bad_Opcode },
11241     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11242   },
11243   {
11244     /* MOD_0F73_REG_6 */
11245     { Bad_Opcode },
11246     { "psllq",          { MS, Ib } },
11247   },
11248   {
11249     /* MOD_0F73_REG_7 */
11250     { Bad_Opcode },
11251     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11252   },
11253   {
11254     /* MOD_0FAE_REG_0 */
11255     { "fxsave",         { FXSAVE } },
11256     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11257   },
11258   {
11259     /* MOD_0FAE_REG_1 */
11260     { "fxrstor",        { FXSAVE } },
11261     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11262   },
11263   {
11264     /* MOD_0FAE_REG_2 */
11265     { "ldmxcsr",        { Md } },
11266     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11267   },
11268   {
11269     /* MOD_0FAE_REG_3 */
11270     { "stmxcsr",        { Md } },
11271     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11272   },
11273   {
11274     /* MOD_0FAE_REG_4 */
11275     { "xsave",          { FXSAVE } },
11276   },
11277   {
11278     /* MOD_0FAE_REG_5 */
11279     { "xrstor",         { FXSAVE } },
11280     { RM_TABLE (RM_0FAE_REG_5) },
11281   },
11282   {
11283     /* MOD_0FAE_REG_6 */
11284     { "xsaveopt",       { FXSAVE } },
11285     { RM_TABLE (RM_0FAE_REG_6) },
11286   },
11287   {
11288     /* MOD_0FAE_REG_7 */
11289     { "clflush",        { Mb } },
11290     { RM_TABLE (RM_0FAE_REG_7) },
11291   },
11292   {
11293     /* MOD_0FB2 */
11294     { "lssS",           { Gv, Mp } },
11295   },
11296   {
11297     /* MOD_0FB4 */
11298     { "lfsS",           { Gv, Mp } },
11299   },
11300   {
11301     /* MOD_0FB5 */
11302     { "lgsS",           { Gv, Mp } },
11303   },
11304   {
11305     /* MOD_0FC7_REG_6 */
11306     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11307     { "rdrand",         { Ev } },
11308   },
11309   {
11310     /* MOD_0FC7_REG_7 */
11311     { "vmptrst",        { Mq } },
11312     { "rdseed",         { Ev } },
11313   },
11314   {
11315     /* MOD_0FD7 */
11316     { Bad_Opcode },
11317     { "pmovmskb",       { Gdq, MS } },
11318   },
11319   {
11320     /* MOD_0FE7_PREFIX_2 */
11321     { "movntdq",        { Mx, XM } },
11322   },
11323   {
11324     /* MOD_0FF0_PREFIX_3 */
11325     { "lddqu",          { XM, M } },
11326   },
11327   {
11328     /* MOD_0F382A_PREFIX_2 */
11329     { "movntdqa",       { XM, Mx } },
11330   },
11331   {
11332     /* MOD_62_32BIT */
11333     { "bound{S|}",      { Gv, Ma } },
11334     { EVEX_TABLE (EVEX_0F) },
11335   },
11336   {
11337     /* MOD_C4_32BIT */
11338     { "lesS",           { Gv, Mp } },
11339     { VEX_C4_TABLE (VEX_0F) },
11340   },
11341   {
11342     /* MOD_C5_32BIT */
11343     { "ldsS",           { Gv, Mp } },
11344     { VEX_C5_TABLE (VEX_0F) },
11345   },
11346   {
11347     /* MOD_VEX_0F12_PREFIX_0 */
11348     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11349     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11350   },
11351   {
11352     /* MOD_VEX_0F13 */
11353     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11354   },
11355   {
11356     /* MOD_VEX_0F16_PREFIX_0 */
11357     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11358     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11359   },
11360   {
11361     /* MOD_VEX_0F17 */
11362     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11363   },
11364   {
11365     /* MOD_VEX_0F2B */
11366     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11367   },
11368   {
11369     /* MOD_VEX_0F50 */
11370     { Bad_Opcode },
11371     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11372   },
11373   {
11374     /* MOD_VEX_0F71_REG_2 */
11375     { Bad_Opcode },
11376     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11377   },
11378   {
11379     /* MOD_VEX_0F71_REG_4 */
11380     { Bad_Opcode },
11381     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11382   },
11383   {
11384     /* MOD_VEX_0F71_REG_6 */
11385     { Bad_Opcode },
11386     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11387   },
11388   {
11389     /* MOD_VEX_0F72_REG_2 */
11390     { Bad_Opcode },
11391     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11392   },
11393   {
11394     /* MOD_VEX_0F72_REG_4 */
11395     { Bad_Opcode },
11396     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11397   },
11398   {
11399     /* MOD_VEX_0F72_REG_6 */
11400     { Bad_Opcode },
11401     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11402   },
11403   {
11404     /* MOD_VEX_0F73_REG_2 */
11405     { Bad_Opcode },
11406     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11407   },
11408   {
11409     /* MOD_VEX_0F73_REG_3 */
11410     { Bad_Opcode },
11411     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11412   },
11413   {
11414     /* MOD_VEX_0F73_REG_6 */
11415     { Bad_Opcode },
11416     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11417   },
11418   {
11419     /* MOD_VEX_0F73_REG_7 */
11420     { Bad_Opcode },
11421     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11422   },
11423   {
11424     /* MOD_VEX_0FAE_REG_2 */
11425     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11426   },
11427   {
11428     /* MOD_VEX_0FAE_REG_3 */
11429     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11430   },
11431   {
11432     /* MOD_VEX_0FD7_PREFIX_2 */
11433     { Bad_Opcode },
11434     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11435   },
11436   {
11437     /* MOD_VEX_0FE7_PREFIX_2 */
11438     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11439   },
11440   {
11441     /* MOD_VEX_0FF0_PREFIX_3 */
11442     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11443   },
11444   {
11445     /* MOD_VEX_0F381A_PREFIX_2 */
11446     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0F382A_PREFIX_2 */
11450     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11451   },
11452   {
11453     /* MOD_VEX_0F382C_PREFIX_2 */
11454     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11455   },
11456   {
11457     /* MOD_VEX_0F382D_PREFIX_2 */
11458     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11459   },
11460   {
11461     /* MOD_VEX_0F382E_PREFIX_2 */
11462     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11463   },
11464   {
11465     /* MOD_VEX_0F382F_PREFIX_2 */
11466     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11467   },
11468   {
11469     /* MOD_VEX_0F385A_PREFIX_2 */
11470     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11471   },
11472   {
11473     /* MOD_VEX_0F388C_PREFIX_2 */
11474     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11475   },
11476   {
11477     /* MOD_VEX_0F388E_PREFIX_2 */
11478     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11479   },
11480 #define NEED_MOD_TABLE
11481 #include "i386-dis-evex.h"
11482 #undef NEED_MOD_TABLE
11483 };
11484
11485 static const struct dis386 rm_table[][8] = {
11486   {
11487     /* RM_C6_REG_7 */
11488     { "xabort",         { Skip_MODRM, Ib } },
11489   },
11490   {
11491     /* RM_C7_REG_7 */
11492     { "xbeginT",        { Skip_MODRM, Jv } },
11493   },
11494   {
11495     /* RM_0F01_REG_0 */
11496     { Bad_Opcode },
11497     { "vmcall",         { Skip_MODRM } },
11498     { "vmlaunch",       { Skip_MODRM } },
11499     { "vmresume",       { Skip_MODRM } },
11500     { "vmxoff",         { Skip_MODRM } },
11501   },
11502   {
11503     /* RM_0F01_REG_1 */
11504     { "monitor",        { { OP_Monitor, 0 } } },
11505     { "mwait",          { { OP_Mwait, 0 } } },
11506     { "clac",           { Skip_MODRM } },
11507     { "stac",           { Skip_MODRM } },
11508   },
11509   {
11510     /* RM_0F01_REG_2 */
11511     { "xgetbv",         { Skip_MODRM } },
11512     { "xsetbv",         { Skip_MODRM } },
11513     { Bad_Opcode },
11514     { Bad_Opcode },
11515     { "vmfunc",         { Skip_MODRM } },
11516     { "xend",           { Skip_MODRM } },
11517     { "xtest",          { Skip_MODRM } },
11518     { Bad_Opcode },
11519   },
11520   {
11521     /* RM_0F01_REG_3 */
11522     { "vmrun",          { Skip_MODRM } },
11523     { "vmmcall",        { Skip_MODRM } },
11524     { "vmload",         { Skip_MODRM } },
11525     { "vmsave",         { Skip_MODRM } },
11526     { "stgi",           { Skip_MODRM } },
11527     { "clgi",           { Skip_MODRM } },
11528     { "skinit",         { Skip_MODRM } },
11529     { "invlpga",        { Skip_MODRM } },
11530   },
11531   {
11532     /* RM_0F01_REG_7 */
11533     { "swapgs",         { Skip_MODRM } },
11534     { "rdtscp",         { Skip_MODRM } },
11535   },
11536   {
11537     /* RM_0FAE_REG_5 */
11538     { "lfence",         { Skip_MODRM } },
11539   },
11540   {
11541     /* RM_0FAE_REG_6 */
11542     { "mfence",         { Skip_MODRM } },
11543   },
11544   {
11545     /* RM_0FAE_REG_7 */
11546     { "sfence",         { Skip_MODRM } },
11547   },
11548 };
11549
11550 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11551
11552 /* We use the high bit to indicate different name for the same
11553    prefix.  */
11554 #define ADDR16_PREFIX   (0x67 | 0x100)
11555 #define ADDR32_PREFIX   (0x67 | 0x200)
11556 #define DATA16_PREFIX   (0x66 | 0x100)
11557 #define DATA32_PREFIX   (0x66 | 0x200)
11558 #define REP_PREFIX      (0xf3 | 0x100)
11559 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11560 #define XRELEASE_PREFIX (0xf3 | 0x400)
11561 #define BND_PREFIX      (0xf2 | 0x400)
11562
11563 static int
11564 ckprefix (void)
11565 {
11566   int newrex, i, length;
11567   rex = 0;
11568   rex_ignored = 0;
11569   prefixes = 0;
11570   used_prefixes = 0;
11571   rex_used = 0;
11572   last_lock_prefix = -1;
11573   last_repz_prefix = -1;
11574   last_repnz_prefix = -1;
11575   last_data_prefix = -1;
11576   last_addr_prefix = -1;
11577   last_rex_prefix = -1;
11578   last_seg_prefix = -1;
11579   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11580     all_prefixes[i] = 0;
11581   i = 0;
11582   length = 0;
11583   /* The maximum instruction length is 15bytes.  */
11584   while (length < MAX_CODE_LENGTH - 1)
11585     {
11586       FETCH_DATA (the_info, codep + 1);
11587       newrex = 0;
11588       switch (*codep)
11589         {
11590         /* REX prefixes family.  */
11591         case 0x40:
11592         case 0x41:
11593         case 0x42:
11594         case 0x43:
11595         case 0x44:
11596         case 0x45:
11597         case 0x46:
11598         case 0x47:
11599         case 0x48:
11600         case 0x49:
11601         case 0x4a:
11602         case 0x4b:
11603         case 0x4c:
11604         case 0x4d:
11605         case 0x4e:
11606         case 0x4f:
11607           if (address_mode == mode_64bit)
11608             newrex = *codep;
11609           else
11610             return 1;
11611           last_rex_prefix = i;
11612           break;
11613         case 0xf3:
11614           prefixes |= PREFIX_REPZ;
11615           last_repz_prefix = i;
11616           break;
11617         case 0xf2:
11618           prefixes |= PREFIX_REPNZ;
11619           last_repnz_prefix = i;
11620           break;
11621         case 0xf0:
11622           prefixes |= PREFIX_LOCK;
11623           last_lock_prefix = i;
11624           break;
11625         case 0x2e:
11626           prefixes |= PREFIX_CS;
11627           last_seg_prefix = i;
11628           break;
11629         case 0x36:
11630           prefixes |= PREFIX_SS;
11631           last_seg_prefix = i;
11632           break;
11633         case 0x3e:
11634           prefixes |= PREFIX_DS;
11635           last_seg_prefix = i;
11636           break;
11637         case 0x26:
11638           prefixes |= PREFIX_ES;
11639           last_seg_prefix = i;
11640           break;
11641         case 0x64:
11642           prefixes |= PREFIX_FS;
11643           last_seg_prefix = i;
11644           break;
11645         case 0x65:
11646           prefixes |= PREFIX_GS;
11647           last_seg_prefix = i;
11648           break;
11649         case 0x66:
11650           prefixes |= PREFIX_DATA;
11651           last_data_prefix = i;
11652           break;
11653         case 0x67:
11654           prefixes |= PREFIX_ADDR;
11655           last_addr_prefix = i;
11656           break;
11657         case FWAIT_OPCODE:
11658           /* fwait is really an instruction.  If there are prefixes
11659              before the fwait, they belong to the fwait, *not* to the
11660              following instruction.  */
11661           if (prefixes || rex)
11662             {
11663               prefixes |= PREFIX_FWAIT;
11664               codep++;
11665               /* This ensures that the previous REX prefixes are noticed
11666                  as unused prefixes, as in the return case below.  */
11667               rex_used = rex;
11668               return 1;
11669             }
11670           prefixes = PREFIX_FWAIT;
11671           break;
11672         default:
11673           return 1;
11674         }
11675       /* Rex is ignored when followed by another prefix.  */
11676       if (rex)
11677         {
11678           rex_used = rex;
11679           return 1;
11680         }
11681       if (*codep != FWAIT_OPCODE)
11682         all_prefixes[i++] = *codep;
11683       rex = newrex;
11684       codep++;
11685       length++;
11686     }
11687   return 0;
11688 }
11689
11690 static int
11691 seg_prefix (int pref)
11692 {
11693   switch (pref)
11694     {
11695     case 0x2e:
11696       return PREFIX_CS;
11697     case 0x36:
11698       return PREFIX_SS;
11699     case 0x3e:
11700       return PREFIX_DS;
11701     case 0x26:
11702       return PREFIX_ES;
11703     case 0x64:
11704       return PREFIX_FS;
11705     case 0x65:
11706       return PREFIX_GS;
11707     default:
11708       return 0;
11709     }
11710 }
11711
11712 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11713    prefix byte.  */
11714
11715 static const char *
11716 prefix_name (int pref, int sizeflag)
11717 {
11718   static const char *rexes [16] =
11719     {
11720       "rex",            /* 0x40 */
11721       "rex.B",          /* 0x41 */
11722       "rex.X",          /* 0x42 */
11723       "rex.XB",         /* 0x43 */
11724       "rex.R",          /* 0x44 */
11725       "rex.RB",         /* 0x45 */
11726       "rex.RX",         /* 0x46 */
11727       "rex.RXB",        /* 0x47 */
11728       "rex.W",          /* 0x48 */
11729       "rex.WB",         /* 0x49 */
11730       "rex.WX",         /* 0x4a */
11731       "rex.WXB",        /* 0x4b */
11732       "rex.WR",         /* 0x4c */
11733       "rex.WRB",        /* 0x4d */
11734       "rex.WRX",        /* 0x4e */
11735       "rex.WRXB",       /* 0x4f */
11736     };
11737
11738   switch (pref)
11739     {
11740     /* REX prefixes family.  */
11741     case 0x40:
11742     case 0x41:
11743     case 0x42:
11744     case 0x43:
11745     case 0x44:
11746     case 0x45:
11747     case 0x46:
11748     case 0x47:
11749     case 0x48:
11750     case 0x49:
11751     case 0x4a:
11752     case 0x4b:
11753     case 0x4c:
11754     case 0x4d:
11755     case 0x4e:
11756     case 0x4f:
11757       return rexes [pref - 0x40];
11758     case 0xf3:
11759       return "repz";
11760     case 0xf2:
11761       return "repnz";
11762     case 0xf0:
11763       return "lock";
11764     case 0x2e:
11765       return "cs";
11766     case 0x36:
11767       return "ss";
11768     case 0x3e:
11769       return "ds";
11770     case 0x26:
11771       return "es";
11772     case 0x64:
11773       return "fs";
11774     case 0x65:
11775       return "gs";
11776     case 0x66:
11777       return (sizeflag & DFLAG) ? "data16" : "data32";
11778     case 0x67:
11779       if (address_mode == mode_64bit)
11780         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11781       else
11782         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11783     case FWAIT_OPCODE:
11784       return "fwait";
11785     case ADDR16_PREFIX:
11786       return "addr16";
11787     case ADDR32_PREFIX:
11788       return "addr32";
11789     case DATA16_PREFIX:
11790       return "data16";
11791     case DATA32_PREFIX:
11792       return "data32";
11793     case REP_PREFIX:
11794       return "rep";
11795     case XACQUIRE_PREFIX:
11796       return "xacquire";
11797     case XRELEASE_PREFIX:
11798       return "xrelease";
11799     case BND_PREFIX:
11800       return "bnd";
11801     default:
11802       return NULL;
11803     }
11804 }
11805
11806 static char op_out[MAX_OPERANDS][100];
11807 static int op_ad, op_index[MAX_OPERANDS];
11808 static int two_source_ops;
11809 static bfd_vma op_address[MAX_OPERANDS];
11810 static bfd_vma op_riprel[MAX_OPERANDS];
11811 static bfd_vma start_pc;
11812
11813 /*
11814  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11815  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11816  *   section of the "Virtual 8086 Mode" chapter.)
11817  * 'pc' should be the address of this instruction, it will
11818  *   be used to print the target address if this is a relative jump or call
11819  * The function returns the length of this instruction in bytes.
11820  */
11821
11822 static char intel_syntax;
11823 static char intel_mnemonic = !SYSV386_COMPAT;
11824 static char open_char;
11825 static char close_char;
11826 static char separator_char;
11827 static char scale_char;
11828
11829 /* Here for backwards compatibility.  When gdb stops using
11830    print_insn_i386_att and print_insn_i386_intel these functions can
11831    disappear, and print_insn_i386 be merged into print_insn.  */
11832 int
11833 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11834 {
11835   intel_syntax = 0;
11836
11837   return print_insn (pc, info);
11838 }
11839
11840 int
11841 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11842 {
11843   intel_syntax = 1;
11844
11845   return print_insn (pc, info);
11846 }
11847
11848 int
11849 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11850 {
11851   intel_syntax = -1;
11852
11853   return print_insn (pc, info);
11854 }
11855
11856 void
11857 print_i386_disassembler_options (FILE *stream)
11858 {
11859   fprintf (stream, _("\n\
11860 The following i386/x86-64 specific disassembler options are supported for use\n\
11861 with the -M switch (multiple options should be separated by commas):\n"));
11862
11863   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11864   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11865   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11866   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11867   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11868   fprintf (stream, _("  att-mnemonic\n"
11869                      "              Display instruction in AT&T mnemonic\n"));
11870   fprintf (stream, _("  intel-mnemonic\n"
11871                      "              Display instruction in Intel mnemonic\n"));
11872   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11873   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11874   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11875   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11876   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11877   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11878 }
11879
11880 /* Bad opcode.  */
11881 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11882
11883 /* Get a pointer to struct dis386 with a valid name.  */
11884
11885 static const struct dis386 *
11886 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11887 {
11888   int vindex, vex_table_index;
11889
11890   if (dp->name != NULL)
11891     return dp;
11892
11893   switch (dp->op[0].bytemode)
11894     {
11895     case USE_REG_TABLE:
11896       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11897       break;
11898
11899     case USE_MOD_TABLE:
11900       vindex = modrm.mod == 0x3 ? 1 : 0;
11901       dp = &mod_table[dp->op[1].bytemode][vindex];
11902       break;
11903
11904     case USE_RM_TABLE:
11905       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11906       break;
11907
11908     case USE_PREFIX_TABLE:
11909       if (need_vex)
11910         {
11911           /* The prefix in VEX is implicit.  */
11912           switch (vex.prefix)
11913             {
11914             case 0:
11915               vindex = 0;
11916               break;
11917             case REPE_PREFIX_OPCODE:
11918               vindex = 1;
11919               break;
11920             case DATA_PREFIX_OPCODE:
11921               vindex = 2;
11922               break;
11923             case REPNE_PREFIX_OPCODE:
11924               vindex = 3;
11925               break;
11926             default:
11927               abort ();
11928               break;
11929             }
11930         }
11931       else
11932         {
11933           vindex = 0;
11934           used_prefixes |= (prefixes & PREFIX_REPZ);
11935           if (prefixes & PREFIX_REPZ)
11936             {
11937               vindex = 1;
11938               all_prefixes[last_repz_prefix] = 0;
11939             }
11940           else
11941             {
11942               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11943                  PREFIX_DATA.  */
11944               used_prefixes |= (prefixes & PREFIX_REPNZ);
11945               if (prefixes & PREFIX_REPNZ)
11946                 {
11947                   vindex = 3;
11948                   all_prefixes[last_repnz_prefix] = 0;
11949                 }
11950               else
11951                 {
11952                   used_prefixes |= (prefixes & PREFIX_DATA);
11953                   if (prefixes & PREFIX_DATA)
11954                     {
11955                       vindex = 2;
11956                       all_prefixes[last_data_prefix] = 0;
11957                     }
11958                 }
11959             }
11960         }
11961       dp = &prefix_table[dp->op[1].bytemode][vindex];
11962       break;
11963
11964     case USE_X86_64_TABLE:
11965       vindex = address_mode == mode_64bit ? 1 : 0;
11966       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11967       break;
11968
11969     case USE_3BYTE_TABLE:
11970       FETCH_DATA (info, codep + 2);
11971       vindex = *codep++;
11972       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11973       modrm.mod = (*codep >> 6) & 3;
11974       modrm.reg = (*codep >> 3) & 7;
11975       modrm.rm = *codep & 7;
11976       break;
11977
11978     case USE_VEX_LEN_TABLE:
11979       if (!need_vex)
11980         abort ();
11981
11982       switch (vex.length)
11983         {
11984         case 128:
11985           vindex = 0;
11986           break;
11987         case 256:
11988           vindex = 1;
11989           break;
11990         default:
11991           abort ();
11992           break;
11993         }
11994
11995       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11996       break;
11997
11998     case USE_XOP_8F_TABLE:
11999       FETCH_DATA (info, codep + 3);
12000       /* All bits in the REX prefix are ignored.  */
12001       rex_ignored = rex;
12002       rex = ~(*codep >> 5) & 0x7;
12003
12004       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12005       switch ((*codep & 0x1f))
12006         {
12007         default:
12008           dp = &bad_opcode;
12009           return dp;
12010         case 0x8:
12011           vex_table_index = XOP_08;
12012           break;
12013         case 0x9:
12014           vex_table_index = XOP_09;
12015           break;
12016         case 0xa:
12017           vex_table_index = XOP_0A;
12018           break;
12019         }
12020       codep++;
12021       vex.w = *codep & 0x80;
12022       if (vex.w && address_mode == mode_64bit)
12023         rex |= REX_W;
12024
12025       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12026       if (address_mode != mode_64bit
12027           && vex.register_specifier > 0x7)
12028         {
12029           dp = &bad_opcode;
12030           return dp;
12031         }
12032
12033       vex.length = (*codep & 0x4) ? 256 : 128;
12034       switch ((*codep & 0x3))
12035         {
12036         case 0:
12037           vex.prefix = 0;
12038           break;
12039         case 1:
12040           vex.prefix = DATA_PREFIX_OPCODE;
12041           break;
12042         case 2:
12043           vex.prefix = REPE_PREFIX_OPCODE;
12044           break;
12045         case 3:
12046           vex.prefix = REPNE_PREFIX_OPCODE;
12047           break;
12048         }
12049       need_vex = 1;
12050       need_vex_reg = 1;
12051       codep++;
12052       vindex = *codep++;
12053       dp = &xop_table[vex_table_index][vindex];
12054
12055       FETCH_DATA (info, codep + 1);
12056       modrm.mod = (*codep >> 6) & 3;
12057       modrm.reg = (*codep >> 3) & 7;
12058       modrm.rm = *codep & 7;
12059       break;
12060
12061     case USE_VEX_C4_TABLE:
12062       /* VEX prefix.  */
12063       FETCH_DATA (info, codep + 3);
12064       /* All bits in the REX prefix are ignored.  */
12065       rex_ignored = rex;
12066       rex = ~(*codep >> 5) & 0x7;
12067       switch ((*codep & 0x1f))
12068         {
12069         default:
12070           dp = &bad_opcode;
12071           return dp;
12072         case 0x1:
12073           vex_table_index = VEX_0F;
12074           break;
12075         case 0x2:
12076           vex_table_index = VEX_0F38;
12077           break;
12078         case 0x3:
12079           vex_table_index = VEX_0F3A;
12080           break;
12081         }
12082       codep++;
12083       vex.w = *codep & 0x80;
12084       if (vex.w && address_mode == mode_64bit)
12085         rex |= REX_W;
12086
12087       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12088       if (address_mode != mode_64bit
12089           && vex.register_specifier > 0x7)
12090         {
12091           dp = &bad_opcode;
12092           return dp;
12093         }
12094
12095       vex.length = (*codep & 0x4) ? 256 : 128;
12096       switch ((*codep & 0x3))
12097         {
12098         case 0:
12099           vex.prefix = 0;
12100           break;
12101         case 1:
12102           vex.prefix = DATA_PREFIX_OPCODE;
12103           break;
12104         case 2:
12105           vex.prefix = REPE_PREFIX_OPCODE;
12106           break;
12107         case 3:
12108           vex.prefix = REPNE_PREFIX_OPCODE;
12109           break;
12110         }
12111       need_vex = 1;
12112       need_vex_reg = 1;
12113       codep++;
12114       vindex = *codep++;
12115       dp = &vex_table[vex_table_index][vindex];
12116       /* There is no MODRM byte for VEX [82|77].  */
12117       if (vindex != 0x77 && vindex != 0x82)
12118         {
12119           FETCH_DATA (info, codep + 1);
12120           modrm.mod = (*codep >> 6) & 3;
12121           modrm.reg = (*codep >> 3) & 7;
12122           modrm.rm = *codep & 7;
12123         }
12124       break;
12125
12126     case USE_VEX_C5_TABLE:
12127       /* VEX prefix.  */
12128       FETCH_DATA (info, codep + 2);
12129       /* All bits in the REX prefix are ignored.  */
12130       rex_ignored = rex;
12131       rex = (*codep & 0x80) ? 0 : REX_R;
12132
12133       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12134       if (address_mode != mode_64bit
12135           && vex.register_specifier > 0x7)
12136         {
12137           dp = &bad_opcode;
12138           return dp;
12139         }
12140
12141       vex.w = 0;
12142
12143       vex.length = (*codep & 0x4) ? 256 : 128;
12144       switch ((*codep & 0x3))
12145         {
12146         case 0:
12147           vex.prefix = 0;
12148           break;
12149         case 1:
12150           vex.prefix = DATA_PREFIX_OPCODE;
12151           break;
12152         case 2:
12153           vex.prefix = REPE_PREFIX_OPCODE;
12154           break;
12155         case 3:
12156           vex.prefix = REPNE_PREFIX_OPCODE;
12157           break;
12158         }
12159       need_vex = 1;
12160       need_vex_reg = 1;
12161       codep++;
12162       vindex = *codep++;
12163       dp = &vex_table[dp->op[1].bytemode][vindex];
12164       /* There is no MODRM byte for VEX [82|77].  */
12165       if (vindex != 0x77 && vindex != 0x82)
12166         {
12167           FETCH_DATA (info, codep + 1);
12168           modrm.mod = (*codep >> 6) & 3;
12169           modrm.reg = (*codep >> 3) & 7;
12170           modrm.rm = *codep & 7;
12171         }
12172       break;
12173
12174     case USE_VEX_W_TABLE:
12175       if (!need_vex)
12176         abort ();
12177
12178       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12179       break;
12180
12181     case USE_EVEX_TABLE:
12182       two_source_ops = 0;
12183       /* EVEX prefix.  */
12184       vex.evex = 1;
12185       FETCH_DATA (info, codep + 4);
12186       /* All bits in the REX prefix are ignored.  */
12187       rex_ignored = rex;
12188       /* The first byte after 0x62.  */
12189       rex = ~(*codep >> 5) & 0x7;
12190       vex.r = *codep & 0x10;
12191       switch ((*codep & 0xf))
12192         {
12193         default:
12194           return &bad_opcode;
12195         case 0x1:
12196           vex_table_index = EVEX_0F;
12197           break;
12198         case 0x2:
12199           vex_table_index = EVEX_0F38;
12200           break;
12201         case 0x3:
12202           vex_table_index = EVEX_0F3A;
12203           break;
12204         }
12205
12206       /* The second byte after 0x62.  */
12207       codep++;
12208       vex.w = *codep & 0x80;
12209       if (vex.w && address_mode == mode_64bit)
12210         rex |= REX_W;
12211
12212       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12213       if (address_mode != mode_64bit)
12214         {
12215           /* In 16/32-bit mode silently ignore following bits.  */
12216           rex &= ~REX_B;
12217           vex.r = 1;
12218           vex.v = 1;
12219           vex.register_specifier &= 0x7;
12220         }
12221
12222       /* The U bit.  */
12223       if (!(*codep & 0x4))
12224         return &bad_opcode;
12225
12226       switch ((*codep & 0x3))
12227         {
12228         case 0:
12229           vex.prefix = 0;
12230           break;
12231         case 1:
12232           vex.prefix = DATA_PREFIX_OPCODE;
12233           break;
12234         case 2:
12235           vex.prefix = REPE_PREFIX_OPCODE;
12236           break;
12237         case 3:
12238           vex.prefix = REPNE_PREFIX_OPCODE;
12239           break;
12240         }
12241
12242       /* The third byte after 0x62.  */
12243       codep++;
12244
12245       /* Remember the static rounding bits.  */
12246       vex.ll = (*codep >> 5) & 3;
12247       vex.b = (*codep & 0x10) != 0;
12248
12249       vex.v = *codep & 0x8;
12250       vex.mask_register_specifier = *codep & 0x7;
12251       vex.zeroing = *codep & 0x80;
12252
12253       need_vex = 1;
12254       need_vex_reg = 1;
12255       codep++;
12256       vindex = *codep++;
12257       dp = &evex_table[vex_table_index][vindex];
12258       FETCH_DATA (info, codep + 1);
12259       modrm.mod = (*codep >> 6) & 3;
12260       modrm.reg = (*codep >> 3) & 7;
12261       modrm.rm = *codep & 7;
12262
12263       /* Set vector length.  */
12264       if (modrm.mod == 3 && vex.b)
12265         vex.length = 512;
12266       else
12267         {
12268           switch (vex.ll)
12269             {
12270             case 0x0:
12271               vex.length = 128;
12272               break;
12273             case 0x1:
12274               vex.length = 256;
12275               break;
12276             case 0x2:
12277               vex.length = 512;
12278               break;
12279             default:
12280               return &bad_opcode;
12281             }
12282         }
12283       break;
12284
12285     case 0:
12286       dp = &bad_opcode;
12287       break;
12288
12289     default:
12290       abort ();
12291     }
12292
12293   if (dp->name != NULL)
12294     return dp;
12295   else
12296     return get_valid_dis386 (dp, info);
12297 }
12298
12299 static void
12300 get_sib (disassemble_info *info, int sizeflag)
12301 {
12302   /* If modrm.mod == 3, operand must be register.  */
12303   if (need_modrm
12304       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12305       && modrm.mod != 3
12306       && modrm.rm == 4)
12307     {
12308       FETCH_DATA (info, codep + 2);
12309       sib.index = (codep [1] >> 3) & 7;
12310       sib.scale = (codep [1] >> 6) & 3;
12311       sib.base = codep [1] & 7;
12312     }
12313 }
12314
12315 static int
12316 print_insn (bfd_vma pc, disassemble_info *info)
12317 {
12318   const struct dis386 *dp;
12319   int i;
12320   char *op_txt[MAX_OPERANDS];
12321   int needcomma;
12322   int sizeflag;
12323   const char *p;
12324   struct dis_private priv;
12325   int prefix_length;
12326   int default_prefixes;
12327
12328   priv.orig_sizeflag = AFLAG | DFLAG;
12329   if ((info->mach & bfd_mach_i386_i386) != 0)
12330     address_mode = mode_32bit;
12331   else if (info->mach == bfd_mach_i386_i8086)
12332     {
12333       address_mode = mode_16bit;
12334       priv.orig_sizeflag = 0;
12335     }
12336   else
12337     address_mode = mode_64bit;
12338
12339   if (intel_syntax == (char) -1)
12340     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12341
12342   for (p = info->disassembler_options; p != NULL; )
12343     {
12344       if (CONST_STRNEQ (p, "x86-64"))
12345         {
12346           address_mode = mode_64bit;
12347           priv.orig_sizeflag = AFLAG | DFLAG;
12348         }
12349       else if (CONST_STRNEQ (p, "i386"))
12350         {
12351           address_mode = mode_32bit;
12352           priv.orig_sizeflag = AFLAG | DFLAG;
12353         }
12354       else if (CONST_STRNEQ (p, "i8086"))
12355         {
12356           address_mode = mode_16bit;
12357           priv.orig_sizeflag = 0;
12358         }
12359       else if (CONST_STRNEQ (p, "intel"))
12360         {
12361           intel_syntax = 1;
12362           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12363             intel_mnemonic = 1;
12364         }
12365       else if (CONST_STRNEQ (p, "att"))
12366         {
12367           intel_syntax = 0;
12368           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12369             intel_mnemonic = 0;
12370         }
12371       else if (CONST_STRNEQ (p, "addr"))
12372         {
12373           if (address_mode == mode_64bit)
12374             {
12375               if (p[4] == '3' && p[5] == '2')
12376                 priv.orig_sizeflag &= ~AFLAG;
12377               else if (p[4] == '6' && p[5] == '4')
12378                 priv.orig_sizeflag |= AFLAG;
12379             }
12380           else
12381             {
12382               if (p[4] == '1' && p[5] == '6')
12383                 priv.orig_sizeflag &= ~AFLAG;
12384               else if (p[4] == '3' && p[5] == '2')
12385                 priv.orig_sizeflag |= AFLAG;
12386             }
12387         }
12388       else if (CONST_STRNEQ (p, "data"))
12389         {
12390           if (p[4] == '1' && p[5] == '6')
12391             priv.orig_sizeflag &= ~DFLAG;
12392           else if (p[4] == '3' && p[5] == '2')
12393             priv.orig_sizeflag |= DFLAG;
12394         }
12395       else if (CONST_STRNEQ (p, "suffix"))
12396         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12397
12398       p = strchr (p, ',');
12399       if (p != NULL)
12400         p++;
12401     }
12402
12403   if (intel_syntax)
12404     {
12405       names64 = intel_names64;
12406       names32 = intel_names32;
12407       names16 = intel_names16;
12408       names8 = intel_names8;
12409       names8rex = intel_names8rex;
12410       names_seg = intel_names_seg;
12411       names_mm = intel_names_mm;
12412       names_bnd = intel_names_bnd;
12413       names_xmm = intel_names_xmm;
12414       names_ymm = intel_names_ymm;
12415       names_zmm = intel_names_zmm;
12416       index64 = intel_index64;
12417       index32 = intel_index32;
12418       names_mask = intel_names_mask;
12419       index16 = intel_index16;
12420       open_char = '[';
12421       close_char = ']';
12422       separator_char = '+';
12423       scale_char = '*';
12424     }
12425   else
12426     {
12427       names64 = att_names64;
12428       names32 = att_names32;
12429       names16 = att_names16;
12430       names8 = att_names8;
12431       names8rex = att_names8rex;
12432       names_seg = att_names_seg;
12433       names_mm = att_names_mm;
12434       names_bnd = att_names_bnd;
12435       names_xmm = att_names_xmm;
12436       names_ymm = att_names_ymm;
12437       names_zmm = att_names_zmm;
12438       index64 = att_index64;
12439       index32 = att_index32;
12440       names_mask = att_names_mask;
12441       index16 = att_index16;
12442       open_char = '(';
12443       close_char =  ')';
12444       separator_char = ',';
12445       scale_char = ',';
12446     }
12447
12448   /* The output looks better if we put 7 bytes on a line, since that
12449      puts most long word instructions on a single line.  Use 8 bytes
12450      for Intel L1OM.  */
12451   if ((info->mach & bfd_mach_l1om) != 0)
12452     info->bytes_per_line = 8;
12453   else
12454     info->bytes_per_line = 7;
12455
12456   info->private_data = &priv;
12457   priv.max_fetched = priv.the_buffer;
12458   priv.insn_start = pc;
12459
12460   obuf[0] = 0;
12461   for (i = 0; i < MAX_OPERANDS; ++i)
12462     {
12463       op_out[i][0] = 0;
12464       op_index[i] = -1;
12465     }
12466
12467   the_info = info;
12468   start_pc = pc;
12469   start_codep = priv.the_buffer;
12470   codep = priv.the_buffer;
12471
12472   if (setjmp (priv.bailout) != 0)
12473     {
12474       const char *name;
12475
12476       /* Getting here means we tried for data but didn't get it.  That
12477          means we have an incomplete instruction of some sort.  Just
12478          print the first byte as a prefix or a .byte pseudo-op.  */
12479       if (codep > priv.the_buffer)
12480         {
12481           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12482           if (name != NULL)
12483             (*info->fprintf_func) (info->stream, "%s", name);
12484           else
12485             {
12486               /* Just print the first byte as a .byte instruction.  */
12487               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12488                                      (unsigned int) priv.the_buffer[0]);
12489             }
12490
12491           return 1;
12492         }
12493
12494       return -1;
12495     }
12496
12497   obufp = obuf;
12498   sizeflag = priv.orig_sizeflag;
12499
12500   if (!ckprefix () || rex_used)
12501     {
12502       /* Too many prefixes or unused REX prefixes.  */
12503       for (i = 0;
12504            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12505            i++)
12506         (*info->fprintf_func) (info->stream, "%s%s",
12507                                i == 0 ? "" : " ",
12508                                prefix_name (all_prefixes[i], sizeflag));
12509       return i;
12510     }
12511
12512   insn_codep = codep;
12513
12514   FETCH_DATA (info, codep + 1);
12515   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12516
12517   if (((prefixes & PREFIX_FWAIT)
12518        && ((*codep < 0xd8) || (*codep > 0xdf))))
12519     {
12520       (*info->fprintf_func) (info->stream, "fwait");
12521       return 1;
12522     }
12523
12524   if (*codep == 0x0f)
12525     {
12526       unsigned char threebyte;
12527       FETCH_DATA (info, codep + 2);
12528       threebyte = *++codep;
12529       dp = &dis386_twobyte[threebyte];
12530       need_modrm = twobyte_has_modrm[*codep];
12531       codep++;
12532     }
12533   else
12534     {
12535       dp = &dis386[*codep];
12536       need_modrm = onebyte_has_modrm[*codep];
12537       codep++;
12538     }
12539
12540   if ((prefixes & PREFIX_REPZ))
12541     used_prefixes |= PREFIX_REPZ;
12542   if ((prefixes & PREFIX_REPNZ))
12543     used_prefixes |= PREFIX_REPNZ;
12544   if ((prefixes & PREFIX_LOCK))
12545     used_prefixes |= PREFIX_LOCK;
12546
12547   default_prefixes = 0;
12548   if (prefixes & PREFIX_ADDR)
12549     {
12550       sizeflag ^= AFLAG;
12551       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12552         {
12553           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12554             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12555           else
12556             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12557           default_prefixes |= PREFIX_ADDR;
12558         }
12559     }
12560
12561   if ((prefixes & PREFIX_DATA))
12562     {
12563       sizeflag ^= DFLAG;
12564       if (dp->op[2].bytemode == cond_jump_mode
12565           && dp->op[0].bytemode == v_mode
12566           && !intel_syntax)
12567         {
12568           if (sizeflag & DFLAG)
12569             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12570           else
12571             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12572           default_prefixes |= PREFIX_DATA;
12573         }
12574       else if (rex & REX_W)
12575         {
12576           /* REX_W will override PREFIX_DATA.  */
12577           default_prefixes |= PREFIX_DATA;
12578         }
12579     }
12580
12581   if (need_modrm)
12582     {
12583       FETCH_DATA (info, codep + 1);
12584       modrm.mod = (*codep >> 6) & 3;
12585       modrm.reg = (*codep >> 3) & 7;
12586       modrm.rm = *codep & 7;
12587     }
12588
12589   need_vex = 0;
12590   need_vex_reg = 0;
12591   vex_w_done = 0;
12592   vex.evex = 0;
12593
12594   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12595     {
12596       get_sib (info, sizeflag);
12597       dofloat (sizeflag);
12598     }
12599   else
12600     {
12601       dp = get_valid_dis386 (dp, info);
12602       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12603         {
12604           get_sib (info, sizeflag);
12605           for (i = 0; i < MAX_OPERANDS; ++i)
12606             {
12607               obufp = op_out[i];
12608               op_ad = MAX_OPERANDS - 1 - i;
12609               if (dp->op[i].rtn)
12610                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12611               /* For EVEX instruction after the last operand masking
12612                  should be printed.  */
12613               if (i == 0 && vex.evex)
12614                 {
12615                   /* Don't print {%k0}.  */
12616                   if (vex.mask_register_specifier)
12617                     {
12618                       oappend ("{");
12619                       oappend (names_mask[vex.mask_register_specifier]);
12620                       oappend ("}");
12621                     }
12622                   if (vex.zeroing)
12623                     oappend ("{z}");
12624                 }
12625             }
12626         }
12627     }
12628
12629   /* See if any prefixes were not used.  If so, print the first one
12630      separately.  If we don't do this, we'll wind up printing an
12631      instruction stream which does not precisely correspond to the
12632      bytes we are disassembling.  */
12633   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12634     {
12635       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12636         if (all_prefixes[i])
12637           {
12638             const char *name;
12639             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12640             if (name == NULL)
12641               name = INTERNAL_DISASSEMBLER_ERROR;
12642             (*info->fprintf_func) (info->stream, "%s", name);
12643             return 1;
12644           }
12645     }
12646
12647   /* Check if the REX prefix is used.  */
12648   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12649     all_prefixes[last_rex_prefix] = 0;
12650
12651   /* Check if the SEG prefix is used.  */
12652   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12653                    | PREFIX_FS | PREFIX_GS)) != 0
12654       && (used_prefixes
12655           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12656     all_prefixes[last_seg_prefix] = 0;
12657
12658   /* Check if the ADDR prefix is used.  */
12659   if ((prefixes & PREFIX_ADDR) != 0
12660       && (used_prefixes & PREFIX_ADDR) != 0)
12661     all_prefixes[last_addr_prefix] = 0;
12662
12663   /* Check if the DATA prefix is used.  */
12664   if ((prefixes & PREFIX_DATA) != 0
12665       && (used_prefixes & PREFIX_DATA) != 0)
12666     all_prefixes[last_data_prefix] = 0;
12667
12668   prefix_length = 0;
12669   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12670     if (all_prefixes[i])
12671       {
12672         const char *name;
12673         name = prefix_name (all_prefixes[i], sizeflag);
12674         if (name == NULL)
12675           abort ();
12676         prefix_length += strlen (name) + 1;
12677         (*info->fprintf_func) (info->stream, "%s ", name);
12678       }
12679
12680   /* Check maximum code length.  */
12681   if ((codep - start_codep) > MAX_CODE_LENGTH)
12682     {
12683       (*info->fprintf_func) (info->stream, "(bad)");
12684       return MAX_CODE_LENGTH;
12685     }
12686
12687   obufp = mnemonicendp;
12688   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12689     oappend (" ");
12690   oappend (" ");
12691   (*info->fprintf_func) (info->stream, "%s", obuf);
12692
12693   /* The enter and bound instructions are printed with operands in the same
12694      order as the intel book; everything else is printed in reverse order.  */
12695   if (intel_syntax || two_source_ops)
12696     {
12697       bfd_vma riprel;
12698
12699       for (i = 0; i < MAX_OPERANDS; ++i)
12700         op_txt[i] = op_out[i];
12701
12702       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12703         {
12704           op_ad = op_index[i];
12705           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12706           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12707           riprel = op_riprel[i];
12708           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12709           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12710         }
12711     }
12712   else
12713     {
12714       for (i = 0; i < MAX_OPERANDS; ++i)
12715         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12716     }
12717
12718   needcomma = 0;
12719   for (i = 0; i < MAX_OPERANDS; ++i)
12720     if (*op_txt[i])
12721       {
12722         if (needcomma)
12723           (*info->fprintf_func) (info->stream, ",");
12724         if (op_index[i] != -1 && !op_riprel[i])
12725           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12726         else
12727           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12728         needcomma = 1;
12729       }
12730
12731   for (i = 0; i < MAX_OPERANDS; i++)
12732     if (op_index[i] != -1 && op_riprel[i])
12733       {
12734         (*info->fprintf_func) (info->stream, "        # ");
12735         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12736                                                 + op_address[op_index[i]]), info);
12737         break;
12738       }
12739   return codep - priv.the_buffer;
12740 }
12741
12742 static const char *float_mem[] = {
12743   /* d8 */
12744   "fadd{s|}",
12745   "fmul{s|}",
12746   "fcom{s|}",
12747   "fcomp{s|}",
12748   "fsub{s|}",
12749   "fsubr{s|}",
12750   "fdiv{s|}",
12751   "fdivr{s|}",
12752   /* d9 */
12753   "fld{s|}",
12754   "(bad)",
12755   "fst{s|}",
12756   "fstp{s|}",
12757   "fldenvIC",
12758   "fldcw",
12759   "fNstenvIC",
12760   "fNstcw",
12761   /* da */
12762   "fiadd{l|}",
12763   "fimul{l|}",
12764   "ficom{l|}",
12765   "ficomp{l|}",
12766   "fisub{l|}",
12767   "fisubr{l|}",
12768   "fidiv{l|}",
12769   "fidivr{l|}",
12770   /* db */
12771   "fild{l|}",
12772   "fisttp{l|}",
12773   "fist{l|}",
12774   "fistp{l|}",
12775   "(bad)",
12776   "fld{t||t|}",
12777   "(bad)",
12778   "fstp{t||t|}",
12779   /* dc */
12780   "fadd{l|}",
12781   "fmul{l|}",
12782   "fcom{l|}",
12783   "fcomp{l|}",
12784   "fsub{l|}",
12785   "fsubr{l|}",
12786   "fdiv{l|}",
12787   "fdivr{l|}",
12788   /* dd */
12789   "fld{l|}",
12790   "fisttp{ll|}",
12791   "fst{l||}",
12792   "fstp{l|}",
12793   "frstorIC",
12794   "(bad)",
12795   "fNsaveIC",
12796   "fNstsw",
12797   /* de */
12798   "fiadd",
12799   "fimul",
12800   "ficom",
12801   "ficomp",
12802   "fisub",
12803   "fisubr",
12804   "fidiv",
12805   "fidivr",
12806   /* df */
12807   "fild",
12808   "fisttp",
12809   "fist",
12810   "fistp",
12811   "fbld",
12812   "fild{ll|}",
12813   "fbstp",
12814   "fistp{ll|}",
12815 };
12816
12817 static const unsigned char float_mem_mode[] = {
12818   /* d8 */
12819   d_mode,
12820   d_mode,
12821   d_mode,
12822   d_mode,
12823   d_mode,
12824   d_mode,
12825   d_mode,
12826   d_mode,
12827   /* d9 */
12828   d_mode,
12829   0,
12830   d_mode,
12831   d_mode,
12832   0,
12833   w_mode,
12834   0,
12835   w_mode,
12836   /* da */
12837   d_mode,
12838   d_mode,
12839   d_mode,
12840   d_mode,
12841   d_mode,
12842   d_mode,
12843   d_mode,
12844   d_mode,
12845   /* db */
12846   d_mode,
12847   d_mode,
12848   d_mode,
12849   d_mode,
12850   0,
12851   t_mode,
12852   0,
12853   t_mode,
12854   /* dc */
12855   q_mode,
12856   q_mode,
12857   q_mode,
12858   q_mode,
12859   q_mode,
12860   q_mode,
12861   q_mode,
12862   q_mode,
12863   /* dd */
12864   q_mode,
12865   q_mode,
12866   q_mode,
12867   q_mode,
12868   0,
12869   0,
12870   0,
12871   w_mode,
12872   /* de */
12873   w_mode,
12874   w_mode,
12875   w_mode,
12876   w_mode,
12877   w_mode,
12878   w_mode,
12879   w_mode,
12880   w_mode,
12881   /* df */
12882   w_mode,
12883   w_mode,
12884   w_mode,
12885   w_mode,
12886   t_mode,
12887   q_mode,
12888   t_mode,
12889   q_mode
12890 };
12891
12892 #define ST { OP_ST, 0 }
12893 #define STi { OP_STi, 0 }
12894
12895 #define FGRPd9_2 NULL, { { NULL, 0 } }
12896 #define FGRPd9_4 NULL, { { NULL, 1 } }
12897 #define FGRPd9_5 NULL, { { NULL, 2 } }
12898 #define FGRPd9_6 NULL, { { NULL, 3 } }
12899 #define FGRPd9_7 NULL, { { NULL, 4 } }
12900 #define FGRPda_5 NULL, { { NULL, 5 } }
12901 #define FGRPdb_4 NULL, { { NULL, 6 } }
12902 #define FGRPde_3 NULL, { { NULL, 7 } }
12903 #define FGRPdf_4 NULL, { { NULL, 8 } }
12904
12905 static const struct dis386 float_reg[][8] = {
12906   /* d8 */
12907   {
12908     { "fadd",   { ST, STi } },
12909     { "fmul",   { ST, STi } },
12910     { "fcom",   { STi } },
12911     { "fcomp",  { STi } },
12912     { "fsub",   { ST, STi } },
12913     { "fsubr",  { ST, STi } },
12914     { "fdiv",   { ST, STi } },
12915     { "fdivr",  { ST, STi } },
12916   },
12917   /* d9 */
12918   {
12919     { "fld",    { STi } },
12920     { "fxch",   { STi } },
12921     { FGRPd9_2 },
12922     { Bad_Opcode },
12923     { FGRPd9_4 },
12924     { FGRPd9_5 },
12925     { FGRPd9_6 },
12926     { FGRPd9_7 },
12927   },
12928   /* da */
12929   {
12930     { "fcmovb", { ST, STi } },
12931     { "fcmove", { ST, STi } },
12932     { "fcmovbe",{ ST, STi } },
12933     { "fcmovu", { ST, STi } },
12934     { Bad_Opcode },
12935     { FGRPda_5 },
12936     { Bad_Opcode },
12937     { Bad_Opcode },
12938   },
12939   /* db */
12940   {
12941     { "fcmovnb",{ ST, STi } },
12942     { "fcmovne",{ ST, STi } },
12943     { "fcmovnbe",{ ST, STi } },
12944     { "fcmovnu",{ ST, STi } },
12945     { FGRPdb_4 },
12946     { "fucomi", { ST, STi } },
12947     { "fcomi",  { ST, STi } },
12948     { Bad_Opcode },
12949   },
12950   /* dc */
12951   {
12952     { "fadd",   { STi, ST } },
12953     { "fmul",   { STi, ST } },
12954     { Bad_Opcode },
12955     { Bad_Opcode },
12956     { "fsub!M", { STi, ST } },
12957     { "fsubM",  { STi, ST } },
12958     { "fdiv!M", { STi, ST } },
12959     { "fdivM",  { STi, ST } },
12960   },
12961   /* dd */
12962   {
12963     { "ffree",  { STi } },
12964     { Bad_Opcode },
12965     { "fst",    { STi } },
12966     { "fstp",   { STi } },
12967     { "fucom",  { STi } },
12968     { "fucomp", { STi } },
12969     { Bad_Opcode },
12970     { Bad_Opcode },
12971   },
12972   /* de */
12973   {
12974     { "faddp",  { STi, ST } },
12975     { "fmulp",  { STi, ST } },
12976     { Bad_Opcode },
12977     { FGRPde_3 },
12978     { "fsub!Mp", { STi, ST } },
12979     { "fsubMp", { STi, ST } },
12980     { "fdiv!Mp", { STi, ST } },
12981     { "fdivMp", { STi, ST } },
12982   },
12983   /* df */
12984   {
12985     { "ffreep", { STi } },
12986     { Bad_Opcode },
12987     { Bad_Opcode },
12988     { Bad_Opcode },
12989     { FGRPdf_4 },
12990     { "fucomip", { ST, STi } },
12991     { "fcomip", { ST, STi } },
12992     { Bad_Opcode },
12993   },
12994 };
12995
12996 static char *fgrps[][8] = {
12997   /* d9_2  0 */
12998   {
12999     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13000   },
13001
13002   /* d9_4  1 */
13003   {
13004     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13005   },
13006
13007   /* d9_5  2 */
13008   {
13009     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13010   },
13011
13012   /* d9_6  3 */
13013   {
13014     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13015   },
13016
13017   /* d9_7  4 */
13018   {
13019     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13020   },
13021
13022   /* da_5  5 */
13023   {
13024     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13025   },
13026
13027   /* db_4  6 */
13028   {
13029     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13030     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13031   },
13032
13033   /* de_3  7 */
13034   {
13035     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13036   },
13037
13038   /* df_4  8 */
13039   {
13040     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13041   },
13042 };
13043
13044 static void
13045 swap_operand (void)
13046 {
13047   mnemonicendp[0] = '.';
13048   mnemonicendp[1] = 's';
13049   mnemonicendp += 2;
13050 }
13051
13052 static void
13053 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13054                int sizeflag ATTRIBUTE_UNUSED)
13055 {
13056   /* Skip mod/rm byte.  */
13057   MODRM_CHECK;
13058   codep++;
13059 }
13060
13061 static void
13062 dofloat (int sizeflag)
13063 {
13064   const struct dis386 *dp;
13065   unsigned char floatop;
13066
13067   floatop = codep[-1];
13068
13069   if (modrm.mod != 3)
13070     {
13071       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13072
13073       putop (float_mem[fp_indx], sizeflag);
13074       obufp = op_out[0];
13075       op_ad = 2;
13076       OP_E (float_mem_mode[fp_indx], sizeflag);
13077       return;
13078     }
13079   /* Skip mod/rm byte.  */
13080   MODRM_CHECK;
13081   codep++;
13082
13083   dp = &float_reg[floatop - 0xd8][modrm.reg];
13084   if (dp->name == NULL)
13085     {
13086       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13087
13088       /* Instruction fnstsw is only one with strange arg.  */
13089       if (floatop == 0xdf && codep[-1] == 0xe0)
13090         strcpy (op_out[0], names16[0]);
13091     }
13092   else
13093     {
13094       putop (dp->name, sizeflag);
13095
13096       obufp = op_out[0];
13097       op_ad = 2;
13098       if (dp->op[0].rtn)
13099         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13100
13101       obufp = op_out[1];
13102       op_ad = 1;
13103       if (dp->op[1].rtn)
13104         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13105     }
13106 }
13107
13108 /* Like oappend (below), but S is a string starting with '%'.
13109    In Intel syntax, the '%' is elided.  */
13110 static void
13111 oappend_maybe_intel (const char *s)
13112 {
13113   oappend (s + intel_syntax);
13114 }
13115
13116 static void
13117 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13118 {
13119   oappend_maybe_intel ("%st");
13120 }
13121
13122 static void
13123 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13124 {
13125   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13126   oappend_maybe_intel (scratchbuf);
13127 }
13128
13129 /* Capital letters in template are macros.  */
13130 static int
13131 putop (const char *in_template, int sizeflag)
13132 {
13133   const char *p;
13134   int alt = 0;
13135   int cond = 1;
13136   unsigned int l = 0, len = 1;
13137   char last[4];
13138
13139 #define SAVE_LAST(c)                    \
13140   if (l < len && l < sizeof (last))     \
13141     last[l++] = c;                      \
13142   else                                  \
13143     abort ();
13144
13145   for (p = in_template; *p; p++)
13146     {
13147       switch (*p)
13148         {
13149         default:
13150           *obufp++ = *p;
13151           break;
13152         case '%':
13153           len++;
13154           break;
13155         case '!':
13156           cond = 0;
13157           break;
13158         case '{':
13159           alt = 0;
13160           if (intel_syntax)
13161             {
13162               while (*++p != '|')
13163                 if (*p == '}' || *p == '\0')
13164                   abort ();
13165             }
13166           /* Fall through.  */
13167         case 'I':
13168           alt = 1;
13169           continue;
13170         case '|':
13171           while (*++p != '}')
13172             {
13173               if (*p == '\0')
13174                 abort ();
13175             }
13176           break;
13177         case '}':
13178           break;
13179         case 'A':
13180           if (intel_syntax)
13181             break;
13182           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13183             *obufp++ = 'b';
13184           break;
13185         case 'B':
13186           if (l == 0 && len == 1)
13187             {
13188 case_B:
13189               if (intel_syntax)
13190                 break;
13191               if (sizeflag & SUFFIX_ALWAYS)
13192                 *obufp++ = 'b';
13193             }
13194           else
13195             {
13196               if (l != 1
13197                   || len != 2
13198                   || last[0] != 'L')
13199                 {
13200                   SAVE_LAST (*p);
13201                   break;
13202                 }
13203
13204               if (address_mode == mode_64bit
13205                   && !(prefixes & PREFIX_ADDR))
13206                 {
13207                   *obufp++ = 'a';
13208                   *obufp++ = 'b';
13209                   *obufp++ = 's';
13210                 }
13211
13212               goto case_B;
13213             }
13214           break;
13215         case 'C':
13216           if (intel_syntax && !alt)
13217             break;
13218           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13219             {
13220               if (sizeflag & DFLAG)
13221                 *obufp++ = intel_syntax ? 'd' : 'l';
13222               else
13223                 *obufp++ = intel_syntax ? 'w' : 's';
13224               used_prefixes |= (prefixes & PREFIX_DATA);
13225             }
13226           break;
13227         case 'D':
13228           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13229             break;
13230           USED_REX (REX_W);
13231           if (modrm.mod == 3)
13232             {
13233               if (rex & REX_W)
13234                 *obufp++ = 'q';
13235               else
13236                 {
13237                   if (sizeflag & DFLAG)
13238                     *obufp++ = intel_syntax ? 'd' : 'l';
13239                   else
13240                     *obufp++ = 'w';
13241                   used_prefixes |= (prefixes & PREFIX_DATA);
13242                 }
13243             }
13244           else
13245             *obufp++ = 'w';
13246           break;
13247         case 'E':               /* For jcxz/jecxz */
13248           if (address_mode == mode_64bit)
13249             {
13250               if (sizeflag & AFLAG)
13251                 *obufp++ = 'r';
13252               else
13253                 *obufp++ = 'e';
13254             }
13255           else
13256             if (sizeflag & AFLAG)
13257               *obufp++ = 'e';
13258           used_prefixes |= (prefixes & PREFIX_ADDR);
13259           break;
13260         case 'F':
13261           if (intel_syntax)
13262             break;
13263           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13264             {
13265               if (sizeflag & AFLAG)
13266                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13267               else
13268                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13269               used_prefixes |= (prefixes & PREFIX_ADDR);
13270             }
13271           break;
13272         case 'G':
13273           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13274             break;
13275           if ((rex & REX_W) || (sizeflag & DFLAG))
13276             *obufp++ = 'l';
13277           else
13278             *obufp++ = 'w';
13279           if (!(rex & REX_W))
13280             used_prefixes |= (prefixes & PREFIX_DATA);
13281           break;
13282         case 'H':
13283           if (intel_syntax)
13284             break;
13285           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13286               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13287             {
13288               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13289               *obufp++ = ',';
13290               *obufp++ = 'p';
13291               if (prefixes & PREFIX_DS)
13292                 *obufp++ = 't';
13293               else
13294                 *obufp++ = 'n';
13295             }
13296           break;
13297         case 'J':
13298           if (intel_syntax)
13299             break;
13300           *obufp++ = 'l';
13301           break;
13302         case 'K':
13303           USED_REX (REX_W);
13304           if (rex & REX_W)
13305             *obufp++ = 'q';
13306           else
13307             *obufp++ = 'd';
13308           break;
13309         case 'Z':
13310           if (intel_syntax)
13311             break;
13312           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13313             {
13314               *obufp++ = 'q';
13315               break;
13316             }
13317           /* Fall through.  */
13318           goto case_L;
13319         case 'L':
13320           if (l != 0 || len != 1)
13321             {
13322               SAVE_LAST (*p);
13323               break;
13324             }
13325 case_L:
13326           if (intel_syntax)
13327             break;
13328           if (sizeflag & SUFFIX_ALWAYS)
13329             *obufp++ = 'l';
13330           break;
13331         case 'M':
13332           if (intel_mnemonic != cond)
13333             *obufp++ = 'r';
13334           break;
13335         case 'N':
13336           if ((prefixes & PREFIX_FWAIT) == 0)
13337             *obufp++ = 'n';
13338           else
13339             used_prefixes |= PREFIX_FWAIT;
13340           break;
13341         case 'O':
13342           USED_REX (REX_W);
13343           if (rex & REX_W)
13344             *obufp++ = 'o';
13345           else if (intel_syntax && (sizeflag & DFLAG))
13346             *obufp++ = 'q';
13347           else
13348             *obufp++ = 'd';
13349           if (!(rex & REX_W))
13350             used_prefixes |= (prefixes & PREFIX_DATA);
13351           break;
13352         case 'T':
13353           if (!intel_syntax
13354               && address_mode == mode_64bit
13355               && ((sizeflag & DFLAG) || (rex & REX_W)))
13356             {
13357               *obufp++ = 'q';
13358               break;
13359             }
13360           /* Fall through.  */
13361         case 'P':
13362           if (intel_syntax)
13363             {
13364               if ((rex & REX_W) == 0
13365                   && (prefixes & PREFIX_DATA))
13366                 {
13367                   if ((sizeflag & DFLAG) == 0)
13368                     *obufp++ = 'w';
13369                    used_prefixes |= (prefixes & PREFIX_DATA);
13370                 }
13371               break;
13372             }
13373           if ((prefixes & PREFIX_DATA)
13374               || (rex & REX_W)
13375               || (sizeflag & SUFFIX_ALWAYS))
13376             {
13377               USED_REX (REX_W);
13378               if (rex & REX_W)
13379                 *obufp++ = 'q';
13380               else
13381                 {
13382                    if (sizeflag & DFLAG)
13383                       *obufp++ = 'l';
13384                    else
13385                      *obufp++ = 'w';
13386                    used_prefixes |= (prefixes & PREFIX_DATA);
13387                 }
13388             }
13389           break;
13390         case 'U':
13391           if (intel_syntax)
13392             break;
13393           if (address_mode == mode_64bit
13394               && ((sizeflag & DFLAG) || (rex & REX_W)))
13395             {
13396               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13397                 *obufp++ = 'q';
13398               break;
13399             }
13400           /* Fall through.  */
13401           goto case_Q;
13402         case 'Q':
13403           if (l == 0 && len == 1)
13404             {
13405 case_Q:
13406               if (intel_syntax && !alt)
13407                 break;
13408               USED_REX (REX_W);
13409               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13410                 {
13411                   if (rex & REX_W)
13412                     *obufp++ = 'q';
13413                   else
13414                     {
13415                       if (sizeflag & DFLAG)
13416                         *obufp++ = intel_syntax ? 'd' : 'l';
13417                       else
13418                         *obufp++ = 'w';
13419                       used_prefixes |= (prefixes & PREFIX_DATA);
13420                     }
13421                 }
13422             }
13423           else
13424             {
13425               if (l != 1 || len != 2 || last[0] != 'L')
13426                 {
13427                   SAVE_LAST (*p);
13428                   break;
13429                 }
13430               if (intel_syntax
13431                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13432                 break;
13433               if ((rex & REX_W))
13434                 {
13435                   USED_REX (REX_W);
13436                   *obufp++ = 'q';
13437                 }
13438               else
13439                 *obufp++ = 'l';
13440             }
13441           break;
13442         case 'R':
13443           USED_REX (REX_W);
13444           if (rex & REX_W)
13445             *obufp++ = 'q';
13446           else if (sizeflag & DFLAG)
13447             {
13448               if (intel_syntax)
13449                   *obufp++ = 'd';
13450               else
13451                   *obufp++ = 'l';
13452             }
13453           else
13454             *obufp++ = 'w';
13455           if (intel_syntax && !p[1]
13456               && ((rex & REX_W) || (sizeflag & DFLAG)))
13457             *obufp++ = 'e';
13458           if (!(rex & REX_W))
13459             used_prefixes |= (prefixes & PREFIX_DATA);
13460           break;
13461         case 'V':
13462           if (l == 0 && len == 1)
13463             {
13464               if (intel_syntax)
13465                 break;
13466               if (address_mode == mode_64bit
13467                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13468                 {
13469                   if (sizeflag & SUFFIX_ALWAYS)
13470                     *obufp++ = 'q';
13471                   break;
13472                 }
13473             }
13474           else
13475             {
13476               if (l != 1
13477                   || len != 2
13478                   || last[0] != 'L')
13479                 {
13480                   SAVE_LAST (*p);
13481                   break;
13482                 }
13483
13484               if (rex & REX_W)
13485                 {
13486                   *obufp++ = 'a';
13487                   *obufp++ = 'b';
13488                   *obufp++ = 's';
13489                 }
13490             }
13491           /* Fall through.  */
13492           goto case_S;
13493         case 'S':
13494           if (l == 0 && len == 1)
13495             {
13496 case_S:
13497               if (intel_syntax)
13498                 break;
13499               if (sizeflag & SUFFIX_ALWAYS)
13500                 {
13501                   if (rex & REX_W)
13502                     *obufp++ = 'q';
13503                   else
13504                     {
13505                       if (sizeflag & DFLAG)
13506                         *obufp++ = 'l';
13507                       else
13508                         *obufp++ = 'w';
13509                       used_prefixes |= (prefixes & PREFIX_DATA);
13510                     }
13511                 }
13512             }
13513           else
13514             {
13515               if (l != 1
13516                   || len != 2
13517                   || last[0] != 'L')
13518                 {
13519                   SAVE_LAST (*p);
13520                   break;
13521                 }
13522
13523               if (address_mode == mode_64bit
13524                   && !(prefixes & PREFIX_ADDR))
13525                 {
13526                   *obufp++ = 'a';
13527                   *obufp++ = 'b';
13528                   *obufp++ = 's';
13529                 }
13530
13531               goto case_S;
13532             }
13533           break;
13534         case 'X':
13535           if (l != 0 || len != 1)
13536             {
13537               SAVE_LAST (*p);
13538               break;
13539             }
13540           if (need_vex && vex.prefix)
13541             {
13542               if (vex.prefix == DATA_PREFIX_OPCODE)
13543                 *obufp++ = 'd';
13544               else
13545                 *obufp++ = 's';
13546             }
13547           else
13548             {
13549               if (prefixes & PREFIX_DATA)
13550                 *obufp++ = 'd';
13551               else
13552                 *obufp++ = 's';
13553               used_prefixes |= (prefixes & PREFIX_DATA);
13554             }
13555           break;
13556         case 'Y':
13557           if (l == 0 && len == 1)
13558             {
13559               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13560                 break;
13561               if (rex & REX_W)
13562                 {
13563                   USED_REX (REX_W);
13564                   *obufp++ = 'q';
13565                 }
13566               break;
13567             }
13568           else
13569             {
13570               if (l != 1 || len != 2 || last[0] != 'X')
13571                 {
13572                   SAVE_LAST (*p);
13573                   break;
13574                 }
13575               if (!need_vex)
13576                 abort ();
13577               if (intel_syntax
13578                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13579                 break;
13580               switch (vex.length)
13581                 {
13582                 case 128:
13583                   *obufp++ = 'x';
13584                   break;
13585                 case 256:
13586                   *obufp++ = 'y';
13587                   break;
13588                 default:
13589                   abort ();
13590                 }
13591             }
13592           break;
13593         case 'W':
13594           if (l == 0 && len == 1)
13595             {
13596               /* operand size flag for cwtl, cbtw */
13597               USED_REX (REX_W);
13598               if (rex & REX_W)
13599                 {
13600                   if (intel_syntax)
13601                     *obufp++ = 'd';
13602                   else
13603                     *obufp++ = 'l';
13604                 }
13605               else if (sizeflag & DFLAG)
13606                 *obufp++ = 'w';
13607               else
13608                 *obufp++ = 'b';
13609               if (!(rex & REX_W))
13610                 used_prefixes |= (prefixes & PREFIX_DATA);
13611             }
13612           else
13613             {
13614               if (l != 1
13615                   || len != 2
13616                   || (last[0] != 'X'
13617                       && last[0] != 'L'))
13618                 {
13619                   SAVE_LAST (*p);
13620                   break;
13621                 }
13622               if (!need_vex)
13623                 abort ();
13624               if (last[0] == 'X')
13625                 *obufp++ = vex.w ? 'd': 's';
13626               else
13627                 *obufp++ = vex.w ? 'q': 'd';
13628             }
13629           break;
13630         }
13631       alt = 0;
13632     }
13633   *obufp = 0;
13634   mnemonicendp = obufp;
13635   return 0;
13636 }
13637
13638 static void
13639 oappend (const char *s)
13640 {
13641   obufp = stpcpy (obufp, s);
13642 }
13643
13644 static void
13645 append_seg (void)
13646 {
13647   if (prefixes & PREFIX_CS)
13648     {
13649       used_prefixes |= PREFIX_CS;
13650       oappend_maybe_intel ("%cs:");
13651     }
13652   if (prefixes & PREFIX_DS)
13653     {
13654       used_prefixes |= PREFIX_DS;
13655       oappend_maybe_intel ("%ds:");
13656     }
13657   if (prefixes & PREFIX_SS)
13658     {
13659       used_prefixes |= PREFIX_SS;
13660       oappend_maybe_intel ("%ss:");
13661     }
13662   if (prefixes & PREFIX_ES)
13663     {
13664       used_prefixes |= PREFIX_ES;
13665       oappend_maybe_intel ("%es:");
13666     }
13667   if (prefixes & PREFIX_FS)
13668     {
13669       used_prefixes |= PREFIX_FS;
13670       oappend_maybe_intel ("%fs:");
13671     }
13672   if (prefixes & PREFIX_GS)
13673     {
13674       used_prefixes |= PREFIX_GS;
13675       oappend_maybe_intel ("%gs:");
13676     }
13677 }
13678
13679 static void
13680 OP_indirE (int bytemode, int sizeflag)
13681 {
13682   if (!intel_syntax)
13683     oappend ("*");
13684   OP_E (bytemode, sizeflag);
13685 }
13686
13687 static void
13688 print_operand_value (char *buf, int hex, bfd_vma disp)
13689 {
13690   if (address_mode == mode_64bit)
13691     {
13692       if (hex)
13693         {
13694           char tmp[30];
13695           int i;
13696           buf[0] = '0';
13697           buf[1] = 'x';
13698           sprintf_vma (tmp, disp);
13699           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13700           strcpy (buf + 2, tmp + i);
13701         }
13702       else
13703         {
13704           bfd_signed_vma v = disp;
13705           char tmp[30];
13706           int i;
13707           if (v < 0)
13708             {
13709               *(buf++) = '-';
13710               v = -disp;
13711               /* Check for possible overflow on 0x8000000000000000.  */
13712               if (v < 0)
13713                 {
13714                   strcpy (buf, "9223372036854775808");
13715                   return;
13716                 }
13717             }
13718           if (!v)
13719             {
13720               strcpy (buf, "0");
13721               return;
13722             }
13723
13724           i = 0;
13725           tmp[29] = 0;
13726           while (v)
13727             {
13728               tmp[28 - i] = (v % 10) + '0';
13729               v /= 10;
13730               i++;
13731             }
13732           strcpy (buf, tmp + 29 - i);
13733         }
13734     }
13735   else
13736     {
13737       if (hex)
13738         sprintf (buf, "0x%x", (unsigned int) disp);
13739       else
13740         sprintf (buf, "%d", (int) disp);
13741     }
13742 }
13743
13744 /* Put DISP in BUF as signed hex number.  */
13745
13746 static void
13747 print_displacement (char *buf, bfd_vma disp)
13748 {
13749   bfd_signed_vma val = disp;
13750   char tmp[30];
13751   int i, j = 0;
13752
13753   if (val < 0)
13754     {
13755       buf[j++] = '-';
13756       val = -disp;
13757
13758       /* Check for possible overflow.  */
13759       if (val < 0)
13760         {
13761           switch (address_mode)
13762             {
13763             case mode_64bit:
13764               strcpy (buf + j, "0x8000000000000000");
13765               break;
13766             case mode_32bit:
13767               strcpy (buf + j, "0x80000000");
13768               break;
13769             case mode_16bit:
13770               strcpy (buf + j, "0x8000");
13771               break;
13772             }
13773           return;
13774         }
13775     }
13776
13777   buf[j++] = '0';
13778   buf[j++] = 'x';
13779
13780   sprintf_vma (tmp, (bfd_vma) val);
13781   for (i = 0; tmp[i] == '0'; i++)
13782     continue;
13783   if (tmp[i] == '\0')
13784     i--;
13785   strcpy (buf + j, tmp + i);
13786 }
13787
13788 static void
13789 intel_operand_size (int bytemode, int sizeflag)
13790 {
13791   if (vex.evex
13792       && vex.b
13793       && (bytemode == x_mode
13794           || bytemode == evex_half_bcst_xmmq_mode))
13795     {
13796       if (vex.w)
13797         oappend ("QWORD PTR ");
13798       else
13799         oappend ("DWORD PTR ");
13800       return;
13801     }
13802   switch (bytemode)
13803     {
13804     case b_mode:
13805     case b_swap_mode:
13806     case dqb_mode:
13807       oappend ("BYTE PTR ");
13808       break;
13809     case w_mode:
13810     case dqw_mode:
13811       oappend ("WORD PTR ");
13812       break;
13813     case stack_v_mode:
13814       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13815         {
13816           oappend ("QWORD PTR ");
13817           break;
13818         }
13819       /* FALLTHRU */
13820     case v_mode:
13821     case v_swap_mode:
13822     case dq_mode:
13823       USED_REX (REX_W);
13824       if (rex & REX_W)
13825         oappend ("QWORD PTR ");
13826       else
13827         {
13828           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13829             oappend ("DWORD PTR ");
13830           else
13831             oappend ("WORD PTR ");
13832           used_prefixes |= (prefixes & PREFIX_DATA);
13833         }
13834       break;
13835     case z_mode:
13836       if ((rex & REX_W) || (sizeflag & DFLAG))
13837         *obufp++ = 'D';
13838       oappend ("WORD PTR ");
13839       if (!(rex & REX_W))
13840         used_prefixes |= (prefixes & PREFIX_DATA);
13841       break;
13842     case a_mode:
13843       if (sizeflag & DFLAG)
13844         oappend ("QWORD PTR ");
13845       else
13846         oappend ("DWORD PTR ");
13847       used_prefixes |= (prefixes & PREFIX_DATA);
13848       break;
13849     case d_mode:
13850     case d_scalar_mode:
13851     case d_scalar_swap_mode:
13852     case d_swap_mode:
13853     case dqd_mode:
13854       oappend ("DWORD PTR ");
13855       break;
13856     case q_mode:
13857     case q_scalar_mode:
13858     case q_scalar_swap_mode:
13859     case q_swap_mode:
13860       oappend ("QWORD PTR ");
13861       break;
13862     case m_mode:
13863       if (address_mode == mode_64bit)
13864         oappend ("QWORD PTR ");
13865       else
13866         oappend ("DWORD PTR ");
13867       break;
13868     case f_mode:
13869       if (sizeflag & DFLAG)
13870         oappend ("FWORD PTR ");
13871       else
13872         oappend ("DWORD PTR ");
13873       used_prefixes |= (prefixes & PREFIX_DATA);
13874       break;
13875     case t_mode:
13876       oappend ("TBYTE PTR ");
13877       break;
13878     case x_mode:
13879     case x_swap_mode:
13880     case evex_x_gscat_mode:
13881     case evex_x_nobcst_mode:
13882       if (need_vex)
13883         {
13884           switch (vex.length)
13885             {
13886             case 128:
13887               oappend ("XMMWORD PTR ");
13888               break;
13889             case 256:
13890               oappend ("YMMWORD PTR ");
13891               break;
13892             case 512:
13893               oappend ("ZMMWORD PTR ");
13894               break;
13895             default:
13896               abort ();
13897             }
13898         }
13899       else
13900         oappend ("XMMWORD PTR ");
13901       break;
13902     case xmm_mode:
13903       oappend ("XMMWORD PTR ");
13904       break;
13905     case ymm_mode:
13906       oappend ("YMMWORD PTR ");
13907       break;
13908     case xmmq_mode:
13909     case evex_half_bcst_xmmq_mode:
13910       if (!need_vex)
13911         abort ();
13912
13913       switch (vex.length)
13914         {
13915         case 128:
13916           oappend ("QWORD PTR ");
13917           break;
13918         case 256:
13919           oappend ("XMMWORD PTR ");
13920           break;
13921         case 512:
13922           oappend ("YMMWORD PTR ");
13923           break;
13924         default:
13925           abort ();
13926         }
13927       break;
13928     case xmm_mb_mode:
13929       if (!need_vex)
13930         abort ();
13931
13932       switch (vex.length)
13933         {
13934         case 128:
13935         case 256:
13936         case 512:
13937           oappend ("BYTE PTR ");
13938           break;
13939         default:
13940           abort ();
13941         }
13942       break;
13943     case xmm_mw_mode:
13944       if (!need_vex)
13945         abort ();
13946
13947       switch (vex.length)
13948         {
13949         case 128:
13950         case 256:
13951         case 512:
13952           oappend ("WORD PTR ");
13953           break;
13954         default:
13955           abort ();
13956         }
13957       break;
13958     case xmm_md_mode:
13959       if (!need_vex)
13960         abort ();
13961
13962       switch (vex.length)
13963         {
13964         case 128:
13965         case 256:
13966         case 512:
13967           oappend ("DWORD PTR ");
13968           break;
13969         default:
13970           abort ();
13971         }
13972       break;
13973     case xmm_mq_mode:
13974       if (!need_vex)
13975         abort ();
13976
13977       switch (vex.length)
13978         {
13979         case 128:
13980         case 256:
13981         case 512:
13982           oappend ("QWORD PTR ");
13983           break;
13984         default:
13985           abort ();
13986         }
13987       break;
13988     case xmmdw_mode:
13989       if (!need_vex)
13990         abort ();
13991
13992       switch (vex.length)
13993         {
13994         case 128:
13995           oappend ("WORD PTR ");
13996           break;
13997         case 256:
13998           oappend ("DWORD PTR ");
13999           break;
14000         case 512:
14001           oappend ("QWORD PTR ");
14002           break;
14003         default:
14004           abort ();
14005         }
14006       break;
14007     case xmmqd_mode:
14008       if (!need_vex)
14009         abort ();
14010
14011       switch (vex.length)
14012         {
14013         case 128:
14014           oappend ("DWORD PTR ");
14015           break;
14016         case 256:
14017           oappend ("QWORD PTR ");
14018           break;
14019         case 512:
14020           oappend ("XMMWORD PTR ");
14021           break;
14022         default:
14023           abort ();
14024         }
14025       break;
14026     case ymmq_mode:
14027       if (!need_vex)
14028         abort ();
14029
14030       switch (vex.length)
14031         {
14032         case 128:
14033           oappend ("QWORD PTR ");
14034           break;
14035         case 256:
14036           oappend ("YMMWORD PTR ");
14037           break;
14038         case 512:
14039           oappend ("ZMMWORD PTR ");
14040           break;
14041         default:
14042           abort ();
14043         }
14044       break;
14045     case ymmxmm_mode:
14046       if (!need_vex)
14047         abort ();
14048
14049       switch (vex.length)
14050         {
14051         case 128:
14052         case 256:
14053           oappend ("XMMWORD PTR ");
14054           break;
14055         default:
14056           abort ();
14057         }
14058       break;
14059     case o_mode:
14060       oappend ("OWORD PTR ");
14061       break;
14062     case xmm_mdq_mode:
14063     case vex_w_dq_mode:
14064     case vex_scalar_w_dq_mode:
14065       if (!need_vex)
14066         abort ();
14067
14068       if (vex.w)
14069         oappend ("QWORD PTR ");
14070       else
14071         oappend ("DWORD PTR ");
14072       break;
14073     case vex_vsib_d_w_dq_mode:
14074     case vex_vsib_q_w_dq_mode:
14075       if (!need_vex)
14076         abort ();
14077
14078       if (!vex.evex)
14079         {
14080           if (vex.w)
14081             oappend ("QWORD PTR ");
14082           else
14083             oappend ("DWORD PTR ");
14084         }
14085       else
14086         {
14087           if (vex.length != 512)
14088             abort ();
14089           oappend ("ZMMWORD PTR ");
14090         }
14091       break;
14092     case mask_mode:
14093       if (!need_vex)
14094         abort ();
14095       /* Currently the only instructions, which allows either mask or
14096          memory operand, are AVX512's KMOVW instructions.  They need
14097          Word-sized operand.  */
14098       if (vex.w || vex.length != 128)
14099         abort ();
14100       oappend ("WORD PTR ");
14101       break;
14102     case v_bnd_mode:
14103     default:
14104       break;
14105     }
14106 }
14107
14108 static void
14109 OP_E_register (int bytemode, int sizeflag)
14110 {
14111   int reg = modrm.rm;
14112   const char **names;
14113
14114   USED_REX (REX_B);
14115   if ((rex & REX_B))
14116     reg += 8;
14117
14118   if ((sizeflag & SUFFIX_ALWAYS)
14119       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14120     swap_operand ();
14121
14122   switch (bytemode)
14123     {
14124     case b_mode:
14125     case b_swap_mode:
14126       USED_REX (0);
14127       if (rex)
14128         names = names8rex;
14129       else
14130         names = names8;
14131       break;
14132     case w_mode:
14133       names = names16;
14134       break;
14135     case d_mode:
14136       names = names32;
14137       break;
14138     case q_mode:
14139       names = names64;
14140       break;
14141     case m_mode:
14142     case v_bnd_mode:
14143       names = address_mode == mode_64bit ? names64 : names32;
14144       break;
14145     case bnd_mode:
14146       names = names_bnd;
14147       break;
14148     case stack_v_mode:
14149       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14150         {
14151           names = names64;
14152           break;
14153         }
14154       bytemode = v_mode;
14155       /* FALLTHRU */
14156     case v_mode:
14157     case v_swap_mode:
14158     case dq_mode:
14159     case dqb_mode:
14160     case dqd_mode:
14161     case dqw_mode:
14162       USED_REX (REX_W);
14163       if (rex & REX_W)
14164         names = names64;
14165       else
14166         {
14167           if ((sizeflag & DFLAG)
14168               || (bytemode != v_mode
14169                   && bytemode != v_swap_mode))
14170             names = names32;
14171           else
14172             names = names16;
14173           used_prefixes |= (prefixes & PREFIX_DATA);
14174         }
14175       break;
14176     case mask_mode:
14177       names = names_mask;
14178       break;
14179     case 0:
14180       return;
14181     default:
14182       oappend (INTERNAL_DISASSEMBLER_ERROR);
14183       return;
14184     }
14185   oappend (names[reg]);
14186 }
14187
14188 static void
14189 OP_E_memory (int bytemode, int sizeflag)
14190 {
14191   bfd_vma disp = 0;
14192   int add = (rex & REX_B) ? 8 : 0;
14193   int riprel = 0;
14194   int shift;
14195
14196   if (vex.evex)
14197     {
14198       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14199       if (vex.b
14200           && bytemode != x_mode
14201           && bytemode != evex_half_bcst_xmmq_mode)
14202         {
14203           BadOp ();
14204           return;
14205         }
14206       switch (bytemode)
14207         {
14208         case vex_vsib_d_w_dq_mode:
14209         case vex_vsib_q_w_dq_mode:
14210         case evex_x_gscat_mode:
14211         case xmm_mdq_mode:
14212           shift = vex.w ? 3 : 2;
14213           break;
14214         case x_mode:
14215         case evex_half_bcst_xmmq_mode:
14216           if (vex.b)
14217             {
14218               shift = vex.w ? 3 : 2;
14219               break;
14220             }
14221           /* Fall through if vex.b == 0.  */
14222         case xmmqd_mode:
14223         case xmmdw_mode:
14224         case xmmq_mode:
14225         case ymmq_mode:
14226         case evex_x_nobcst_mode:
14227         case x_swap_mode:
14228           switch (vex.length)
14229             {
14230             case 128:
14231               shift = 4;
14232               break;
14233             case 256:
14234               shift = 5;
14235               break;
14236             case 512:
14237               shift = 6;
14238               break;
14239             default:
14240               abort ();
14241             }
14242           break;
14243         case ymm_mode:
14244           shift = 5;
14245           break;
14246         case xmm_mode:
14247           shift = 4;
14248           break;
14249         case xmm_mq_mode:
14250         case q_mode:
14251         case q_scalar_mode:
14252         case q_swap_mode:
14253         case q_scalar_swap_mode:
14254           shift = 3;
14255           break;
14256         case dqd_mode:
14257         case xmm_md_mode:
14258         case d_mode:
14259         case d_scalar_mode:
14260         case d_swap_mode:
14261         case d_scalar_swap_mode:
14262           shift = 2;
14263           break;
14264         case xmm_mw_mode:
14265           shift = 1;
14266           break;
14267         case xmm_mb_mode:
14268           shift = 0;
14269           break;
14270         default:
14271           abort ();
14272         }
14273       /* Make necessary corrections to shift for modes that need it.
14274          For these modes we currently have shift 4, 5 or 6 depending on
14275          vex.length (it corresponds to xmmword, ymmword or zmmword
14276          operand).  We might want to make it 3, 4 or 5 (e.g. for
14277          xmmq_mode).  In case of broadcast enabled the corrections
14278          aren't needed, as element size is always 32 or 64 bits.  */
14279       if (bytemode == xmmq_mode
14280           || (bytemode == evex_half_bcst_xmmq_mode
14281               && !vex.b))
14282         shift -= 1;
14283       else if (bytemode == xmmqd_mode)
14284         shift -= 2;
14285       else if (bytemode == xmmdw_mode)
14286         shift -= 3;
14287     }
14288   else
14289     shift = 0;
14290
14291   USED_REX (REX_B);
14292   if (intel_syntax)
14293     intel_operand_size (bytemode, sizeflag);
14294   append_seg ();
14295
14296   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14297     {
14298       /* 32/64 bit address mode */
14299       int havedisp;
14300       int havesib;
14301       int havebase;
14302       int haveindex;
14303       int needindex;
14304       int base, rbase;
14305       int vindex = 0;
14306       int scale = 0;
14307       int addr32flag = !((sizeflag & AFLAG)
14308                          || bytemode == v_bnd_mode
14309                          || bytemode == bnd_mode);
14310       const char **indexes64 = names64;
14311       const char **indexes32 = names32;
14312
14313       havesib = 0;
14314       havebase = 1;
14315       haveindex = 0;
14316       base = modrm.rm;
14317
14318       if (base == 4)
14319         {
14320           havesib = 1;
14321           vindex = sib.index;
14322           USED_REX (REX_X);
14323           if (rex & REX_X)
14324             vindex += 8;
14325           switch (bytemode)
14326             {
14327             case vex_vsib_d_w_dq_mode:
14328             case vex_vsib_q_w_dq_mode:
14329               if (!need_vex)
14330                 abort ();
14331               if (vex.evex)
14332                 {
14333                   if (!vex.v)
14334                     vindex += 16;
14335                 }
14336
14337               haveindex = 1;
14338               switch (vex.length)
14339                 {
14340                 case 128:
14341                   indexes64 = indexes32 = names_xmm;
14342                   break;
14343                 case 256:
14344                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14345                     indexes64 = indexes32 = names_ymm;
14346                   else
14347                     indexes64 = indexes32 = names_xmm;
14348                   break;
14349                 case 512:
14350                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14351                     indexes64 = indexes32 = names_zmm;
14352                   else
14353                     indexes64 = indexes32 = names_ymm;
14354                   break;
14355                 default:
14356                   abort ();
14357                 }
14358               break;
14359             default:
14360               haveindex = vindex != 4;
14361               break;
14362             }
14363           scale = sib.scale;
14364           base = sib.base;
14365           codep++;
14366         }
14367       rbase = base + add;
14368
14369       switch (modrm.mod)
14370         {
14371         case 0:
14372           if (base == 5)
14373             {
14374               havebase = 0;
14375               if (address_mode == mode_64bit && !havesib)
14376                 riprel = 1;
14377               disp = get32s ();
14378             }
14379           break;
14380         case 1:
14381           FETCH_DATA (the_info, codep + 1);
14382           disp = *codep++;
14383           if ((disp & 0x80) != 0)
14384             disp -= 0x100;
14385           if (vex.evex && shift > 0)
14386             disp <<= shift;
14387           break;
14388         case 2:
14389           disp = get32s ();
14390           break;
14391         }
14392
14393       /* In 32bit mode, we need index register to tell [offset] from
14394          [eiz*1 + offset].  */
14395       needindex = (havesib
14396                    && !havebase
14397                    && !haveindex
14398                    && address_mode == mode_32bit);
14399       havedisp = (havebase
14400                   || needindex
14401                   || (havesib && (haveindex || scale != 0)));
14402
14403       if (!intel_syntax)
14404         if (modrm.mod != 0 || base == 5)
14405           {
14406             if (havedisp || riprel)
14407               print_displacement (scratchbuf, disp);
14408             else
14409               print_operand_value (scratchbuf, 1, disp);
14410             oappend (scratchbuf);
14411             if (riprel)
14412               {
14413                 set_op (disp, 1);
14414                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14415               }
14416           }
14417
14418       if ((havebase || haveindex || riprel)
14419           && (bytemode != v_bnd_mode)
14420           && (bytemode != bnd_mode))
14421         used_prefixes |= PREFIX_ADDR;
14422
14423       if (havedisp || (intel_syntax && riprel))
14424         {
14425           *obufp++ = open_char;
14426           if (intel_syntax && riprel)
14427             {
14428               set_op (disp, 1);
14429               oappend (sizeflag & AFLAG ? "rip" : "eip");
14430             }
14431           *obufp = '\0';
14432           if (havebase)
14433             oappend (address_mode == mode_64bit && !addr32flag
14434                      ? names64[rbase] : names32[rbase]);
14435           if (havesib)
14436             {
14437               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14438                  print index to tell base + index from base.  */
14439               if (scale != 0
14440                   || needindex
14441                   || haveindex
14442                   || (havebase && base != ESP_REG_NUM))
14443                 {
14444                   if (!intel_syntax || havebase)
14445                     {
14446                       *obufp++ = separator_char;
14447                       *obufp = '\0';
14448                     }
14449                   if (haveindex)
14450                     oappend (address_mode == mode_64bit && !addr32flag
14451                              ? indexes64[vindex] : indexes32[vindex]);
14452                   else
14453                     oappend (address_mode == mode_64bit && !addr32flag
14454                              ? index64 : index32);
14455
14456                   *obufp++ = scale_char;
14457                   *obufp = '\0';
14458                   sprintf (scratchbuf, "%d", 1 << scale);
14459                   oappend (scratchbuf);
14460                 }
14461             }
14462           if (intel_syntax
14463               && (disp || modrm.mod != 0 || base == 5))
14464             {
14465               if (!havedisp || (bfd_signed_vma) disp >= 0)
14466                 {
14467                   *obufp++ = '+';
14468                   *obufp = '\0';
14469                 }
14470               else if (modrm.mod != 1 && disp != -disp)
14471                 {
14472                   *obufp++ = '-';
14473                   *obufp = '\0';
14474                   disp = - (bfd_signed_vma) disp;
14475                 }
14476
14477               if (havedisp)
14478                 print_displacement (scratchbuf, disp);
14479               else
14480                 print_operand_value (scratchbuf, 1, disp);
14481               oappend (scratchbuf);
14482             }
14483
14484           *obufp++ = close_char;
14485           *obufp = '\0';
14486         }
14487       else if (intel_syntax)
14488         {
14489           if (modrm.mod != 0 || base == 5)
14490             {
14491               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14492                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14493                 ;
14494               else
14495                 {
14496                   oappend (names_seg[ds_reg - es_reg]);
14497                   oappend (":");
14498                 }
14499               print_operand_value (scratchbuf, 1, disp);
14500               oappend (scratchbuf);
14501             }
14502         }
14503     }
14504   else
14505     {
14506       /* 16 bit address mode */
14507       used_prefixes |= prefixes & PREFIX_ADDR;
14508       switch (modrm.mod)
14509         {
14510         case 0:
14511           if (modrm.rm == 6)
14512             {
14513               disp = get16 ();
14514               if ((disp & 0x8000) != 0)
14515                 disp -= 0x10000;
14516             }
14517           break;
14518         case 1:
14519           FETCH_DATA (the_info, codep + 1);
14520           disp = *codep++;
14521           if ((disp & 0x80) != 0)
14522             disp -= 0x100;
14523           break;
14524         case 2:
14525           disp = get16 ();
14526           if ((disp & 0x8000) != 0)
14527             disp -= 0x10000;
14528           break;
14529         }
14530
14531       if (!intel_syntax)
14532         if (modrm.mod != 0 || modrm.rm == 6)
14533           {
14534             print_displacement (scratchbuf, disp);
14535             oappend (scratchbuf);
14536           }
14537
14538       if (modrm.mod != 0 || modrm.rm != 6)
14539         {
14540           *obufp++ = open_char;
14541           *obufp = '\0';
14542           oappend (index16[modrm.rm]);
14543           if (intel_syntax
14544               && (disp || modrm.mod != 0 || modrm.rm == 6))
14545             {
14546               if ((bfd_signed_vma) disp >= 0)
14547                 {
14548                   *obufp++ = '+';
14549                   *obufp = '\0';
14550                 }
14551               else if (modrm.mod != 1)
14552                 {
14553                   *obufp++ = '-';
14554                   *obufp = '\0';
14555                   disp = - (bfd_signed_vma) disp;
14556                 }
14557
14558               print_displacement (scratchbuf, disp);
14559               oappend (scratchbuf);
14560             }
14561
14562           *obufp++ = close_char;
14563           *obufp = '\0';
14564         }
14565       else if (intel_syntax)
14566         {
14567           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14568                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14569             ;
14570           else
14571             {
14572               oappend (names_seg[ds_reg - es_reg]);
14573               oappend (":");
14574             }
14575           print_operand_value (scratchbuf, 1, disp & 0xffff);
14576           oappend (scratchbuf);
14577         }
14578     }
14579   if (vex.evex && vex.b
14580       && (bytemode == x_mode
14581           || bytemode == evex_half_bcst_xmmq_mode))
14582     {
14583       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14584         oappend ("{1to8}");
14585       else
14586         oappend ("{1to16}");
14587     }
14588 }
14589
14590 static void
14591 OP_E (int bytemode, int sizeflag)
14592 {
14593   /* Skip mod/rm byte.  */
14594   MODRM_CHECK;
14595   codep++;
14596
14597   if (modrm.mod == 3)
14598     OP_E_register (bytemode, sizeflag);
14599   else
14600     OP_E_memory (bytemode, sizeflag);
14601 }
14602
14603 static void
14604 OP_G (int bytemode, int sizeflag)
14605 {
14606   int add = 0;
14607   USED_REX (REX_R);
14608   if (rex & REX_R)
14609     add += 8;
14610   switch (bytemode)
14611     {
14612     case b_mode:
14613       USED_REX (0);
14614       if (rex)
14615         oappend (names8rex[modrm.reg + add]);
14616       else
14617         oappend (names8[modrm.reg + add]);
14618       break;
14619     case w_mode:
14620       oappend (names16[modrm.reg + add]);
14621       break;
14622     case d_mode:
14623       oappend (names32[modrm.reg + add]);
14624       break;
14625     case q_mode:
14626       oappend (names64[modrm.reg + add]);
14627       break;
14628     case bnd_mode:
14629       oappend (names_bnd[modrm.reg]);
14630       break;
14631     case v_mode:
14632     case dq_mode:
14633     case dqb_mode:
14634     case dqd_mode:
14635     case dqw_mode:
14636       USED_REX (REX_W);
14637       if (rex & REX_W)
14638         oappend (names64[modrm.reg + add]);
14639       else
14640         {
14641           if ((sizeflag & DFLAG) || bytemode != v_mode)
14642             oappend (names32[modrm.reg + add]);
14643           else
14644             oappend (names16[modrm.reg + add]);
14645           used_prefixes |= (prefixes & PREFIX_DATA);
14646         }
14647       break;
14648     case m_mode:
14649       if (address_mode == mode_64bit)
14650         oappend (names64[modrm.reg + add]);
14651       else
14652         oappend (names32[modrm.reg + add]);
14653       break;
14654     case mask_mode:
14655       oappend (names_mask[modrm.reg + add]);
14656       break;
14657     default:
14658       oappend (INTERNAL_DISASSEMBLER_ERROR);
14659       break;
14660     }
14661 }
14662
14663 static bfd_vma
14664 get64 (void)
14665 {
14666   bfd_vma x;
14667 #ifdef BFD64
14668   unsigned int a;
14669   unsigned int b;
14670
14671   FETCH_DATA (the_info, codep + 8);
14672   a = *codep++ & 0xff;
14673   a |= (*codep++ & 0xff) << 8;
14674   a |= (*codep++ & 0xff) << 16;
14675   a |= (*codep++ & 0xff) << 24;
14676   b = *codep++ & 0xff;
14677   b |= (*codep++ & 0xff) << 8;
14678   b |= (*codep++ & 0xff) << 16;
14679   b |= (*codep++ & 0xff) << 24;
14680   x = a + ((bfd_vma) b << 32);
14681 #else
14682   abort ();
14683   x = 0;
14684 #endif
14685   return x;
14686 }
14687
14688 static bfd_signed_vma
14689 get32 (void)
14690 {
14691   bfd_signed_vma x = 0;
14692
14693   FETCH_DATA (the_info, codep + 4);
14694   x = *codep++ & (bfd_signed_vma) 0xff;
14695   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14696   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14697   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14698   return x;
14699 }
14700
14701 static bfd_signed_vma
14702 get32s (void)
14703 {
14704   bfd_signed_vma x = 0;
14705
14706   FETCH_DATA (the_info, codep + 4);
14707   x = *codep++ & (bfd_signed_vma) 0xff;
14708   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14709   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14710   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14711
14712   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14713
14714   return x;
14715 }
14716
14717 static int
14718 get16 (void)
14719 {
14720   int x = 0;
14721
14722   FETCH_DATA (the_info, codep + 2);
14723   x = *codep++ & 0xff;
14724   x |= (*codep++ & 0xff) << 8;
14725   return x;
14726 }
14727
14728 static void
14729 set_op (bfd_vma op, int riprel)
14730 {
14731   op_index[op_ad] = op_ad;
14732   if (address_mode == mode_64bit)
14733     {
14734       op_address[op_ad] = op;
14735       op_riprel[op_ad] = riprel;
14736     }
14737   else
14738     {
14739       /* Mask to get a 32-bit address.  */
14740       op_address[op_ad] = op & 0xffffffff;
14741       op_riprel[op_ad] = riprel & 0xffffffff;
14742     }
14743 }
14744
14745 static void
14746 OP_REG (int code, int sizeflag)
14747 {
14748   const char *s;
14749   int add;
14750
14751   switch (code)
14752     {
14753     case es_reg: case ss_reg: case cs_reg:
14754     case ds_reg: case fs_reg: case gs_reg:
14755       oappend (names_seg[code - es_reg]);
14756       return;
14757     }
14758
14759   USED_REX (REX_B);
14760   if (rex & REX_B)
14761     add = 8;
14762   else
14763     add = 0;
14764
14765   switch (code)
14766     {
14767     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14768     case sp_reg: case bp_reg: case si_reg: case di_reg:
14769       s = names16[code - ax_reg + add];
14770       break;
14771     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14772     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14773       USED_REX (0);
14774       if (rex)
14775         s = names8rex[code - al_reg + add];
14776       else
14777         s = names8[code - al_reg];
14778       break;
14779     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14780     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14781       if (address_mode == mode_64bit
14782           && ((sizeflag & DFLAG) || (rex & REX_W)))
14783         {
14784           s = names64[code - rAX_reg + add];
14785           break;
14786         }
14787       code += eAX_reg - rAX_reg;
14788       /* Fall through.  */
14789     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14790     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14791       USED_REX (REX_W);
14792       if (rex & REX_W)
14793         s = names64[code - eAX_reg + add];
14794       else
14795         {
14796           if (sizeflag & DFLAG)
14797             s = names32[code - eAX_reg + add];
14798           else
14799             s = names16[code - eAX_reg + add];
14800           used_prefixes |= (prefixes & PREFIX_DATA);
14801         }
14802       break;
14803     default:
14804       s = INTERNAL_DISASSEMBLER_ERROR;
14805       break;
14806     }
14807   oappend (s);
14808 }
14809
14810 static void
14811 OP_IMREG (int code, int sizeflag)
14812 {
14813   const char *s;
14814
14815   switch (code)
14816     {
14817     case indir_dx_reg:
14818       if (intel_syntax)
14819         s = "dx";
14820       else
14821         s = "(%dx)";
14822       break;
14823     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14824     case sp_reg: case bp_reg: case si_reg: case di_reg:
14825       s = names16[code - ax_reg];
14826       break;
14827     case es_reg: case ss_reg: case cs_reg:
14828     case ds_reg: case fs_reg: case gs_reg:
14829       s = names_seg[code - es_reg];
14830       break;
14831     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14832     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14833       USED_REX (0);
14834       if (rex)
14835         s = names8rex[code - al_reg];
14836       else
14837         s = names8[code - al_reg];
14838       break;
14839     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14840     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14841       USED_REX (REX_W);
14842       if (rex & REX_W)
14843         s = names64[code - eAX_reg];
14844       else
14845         {
14846           if (sizeflag & DFLAG)
14847             s = names32[code - eAX_reg];
14848           else
14849             s = names16[code - eAX_reg];
14850           used_prefixes |= (prefixes & PREFIX_DATA);
14851         }
14852       break;
14853     case z_mode_ax_reg:
14854       if ((rex & REX_W) || (sizeflag & DFLAG))
14855         s = *names32;
14856       else
14857         s = *names16;
14858       if (!(rex & REX_W))
14859         used_prefixes |= (prefixes & PREFIX_DATA);
14860       break;
14861     default:
14862       s = INTERNAL_DISASSEMBLER_ERROR;
14863       break;
14864     }
14865   oappend (s);
14866 }
14867
14868 static void
14869 OP_I (int bytemode, int sizeflag)
14870 {
14871   bfd_signed_vma op;
14872   bfd_signed_vma mask = -1;
14873
14874   switch (bytemode)
14875     {
14876     case b_mode:
14877       FETCH_DATA (the_info, codep + 1);
14878       op = *codep++;
14879       mask = 0xff;
14880       break;
14881     case q_mode:
14882       if (address_mode == mode_64bit)
14883         {
14884           op = get32s ();
14885           break;
14886         }
14887       /* Fall through.  */
14888     case v_mode:
14889       USED_REX (REX_W);
14890       if (rex & REX_W)
14891         op = get32s ();
14892       else
14893         {
14894           if (sizeflag & DFLAG)
14895             {
14896               op = get32 ();
14897               mask = 0xffffffff;
14898             }
14899           else
14900             {
14901               op = get16 ();
14902               mask = 0xfffff;
14903             }
14904           used_prefixes |= (prefixes & PREFIX_DATA);
14905         }
14906       break;
14907     case w_mode:
14908       mask = 0xfffff;
14909       op = get16 ();
14910       break;
14911     case const_1_mode:
14912       if (intel_syntax)
14913         oappend ("1");
14914       return;
14915     default:
14916       oappend (INTERNAL_DISASSEMBLER_ERROR);
14917       return;
14918     }
14919
14920   op &= mask;
14921   scratchbuf[0] = '$';
14922   print_operand_value (scratchbuf + 1, 1, op);
14923   oappend_maybe_intel (scratchbuf);
14924   scratchbuf[0] = '\0';
14925 }
14926
14927 static void
14928 OP_I64 (int bytemode, int sizeflag)
14929 {
14930   bfd_signed_vma op;
14931   bfd_signed_vma mask = -1;
14932
14933   if (address_mode != mode_64bit)
14934     {
14935       OP_I (bytemode, sizeflag);
14936       return;
14937     }
14938
14939   switch (bytemode)
14940     {
14941     case b_mode:
14942       FETCH_DATA (the_info, codep + 1);
14943       op = *codep++;
14944       mask = 0xff;
14945       break;
14946     case v_mode:
14947       USED_REX (REX_W);
14948       if (rex & REX_W)
14949         op = get64 ();
14950       else
14951         {
14952           if (sizeflag & DFLAG)
14953             {
14954               op = get32 ();
14955               mask = 0xffffffff;
14956             }
14957           else
14958             {
14959               op = get16 ();
14960               mask = 0xfffff;
14961             }
14962           used_prefixes |= (prefixes & PREFIX_DATA);
14963         }
14964       break;
14965     case w_mode:
14966       mask = 0xfffff;
14967       op = get16 ();
14968       break;
14969     default:
14970       oappend (INTERNAL_DISASSEMBLER_ERROR);
14971       return;
14972     }
14973
14974   op &= mask;
14975   scratchbuf[0] = '$';
14976   print_operand_value (scratchbuf + 1, 1, op);
14977   oappend_maybe_intel (scratchbuf);
14978   scratchbuf[0] = '\0';
14979 }
14980
14981 static void
14982 OP_sI (int bytemode, int sizeflag)
14983 {
14984   bfd_signed_vma op;
14985
14986   switch (bytemode)
14987     {
14988     case b_mode:
14989     case b_T_mode:
14990       FETCH_DATA (the_info, codep + 1);
14991       op = *codep++;
14992       if ((op & 0x80) != 0)
14993         op -= 0x100;
14994       if (bytemode == b_T_mode)
14995         {
14996           if (address_mode != mode_64bit
14997               || !((sizeflag & DFLAG) || (rex & REX_W)))
14998             {
14999               /* The operand-size prefix is overridden by a REX prefix.  */
15000               if ((sizeflag & DFLAG) || (rex & REX_W))
15001                 op &= 0xffffffff;
15002               else
15003                 op &= 0xffff;
15004           }
15005         }
15006       else
15007         {
15008           if (!(rex & REX_W))
15009             {
15010               if (sizeflag & DFLAG)
15011                 op &= 0xffffffff;
15012               else
15013                 op &= 0xffff;
15014             }
15015         }
15016       break;
15017     case v_mode:
15018       /* The operand-size prefix is overridden by a REX prefix.  */
15019       if ((sizeflag & DFLAG) || (rex & REX_W))
15020         op = get32s ();
15021       else
15022         op = get16 ();
15023       break;
15024     default:
15025       oappend (INTERNAL_DISASSEMBLER_ERROR);
15026       return;
15027     }
15028
15029   scratchbuf[0] = '$';
15030   print_operand_value (scratchbuf + 1, 1, op);
15031   oappend_maybe_intel (scratchbuf);
15032 }
15033
15034 static void
15035 OP_J (int bytemode, int sizeflag)
15036 {
15037   bfd_vma disp;
15038   bfd_vma mask = -1;
15039   bfd_vma segment = 0;
15040
15041   switch (bytemode)
15042     {
15043     case b_mode:
15044       FETCH_DATA (the_info, codep + 1);
15045       disp = *codep++;
15046       if ((disp & 0x80) != 0)
15047         disp -= 0x100;
15048       break;
15049     case v_mode:
15050       USED_REX (REX_W);
15051       if ((sizeflag & DFLAG) || (rex & REX_W))
15052         disp = get32s ();
15053       else
15054         {
15055           disp = get16 ();
15056           if ((disp & 0x8000) != 0)
15057             disp -= 0x10000;
15058           /* In 16bit mode, address is wrapped around at 64k within
15059              the same segment.  Otherwise, a data16 prefix on a jump
15060              instruction means that the pc is masked to 16 bits after
15061              the displacement is added!  */
15062           mask = 0xffff;
15063           if ((prefixes & PREFIX_DATA) == 0)
15064             segment = ((start_pc + codep - start_codep)
15065                        & ~((bfd_vma) 0xffff));
15066         }
15067       if (!(rex & REX_W))
15068         used_prefixes |= (prefixes & PREFIX_DATA);
15069       break;
15070     default:
15071       oappend (INTERNAL_DISASSEMBLER_ERROR);
15072       return;
15073     }
15074   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15075   set_op (disp, 0);
15076   print_operand_value (scratchbuf, 1, disp);
15077   oappend (scratchbuf);
15078 }
15079
15080 static void
15081 OP_SEG (int bytemode, int sizeflag)
15082 {
15083   if (bytemode == w_mode)
15084     oappend (names_seg[modrm.reg]);
15085   else
15086     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15087 }
15088
15089 static void
15090 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15091 {
15092   int seg, offset;
15093
15094   if (sizeflag & DFLAG)
15095     {
15096       offset = get32 ();
15097       seg = get16 ();
15098     }
15099   else
15100     {
15101       offset = get16 ();
15102       seg = get16 ();
15103     }
15104   used_prefixes |= (prefixes & PREFIX_DATA);
15105   if (intel_syntax)
15106     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15107   else
15108     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15109   oappend (scratchbuf);
15110 }
15111
15112 static void
15113 OP_OFF (int bytemode, int sizeflag)
15114 {
15115   bfd_vma off;
15116
15117   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15118     intel_operand_size (bytemode, sizeflag);
15119   append_seg ();
15120
15121   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15122     off = get32 ();
15123   else
15124     off = get16 ();
15125
15126   if (intel_syntax)
15127     {
15128       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15129                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15130         {
15131           oappend (names_seg[ds_reg - es_reg]);
15132           oappend (":");
15133         }
15134     }
15135   print_operand_value (scratchbuf, 1, off);
15136   oappend (scratchbuf);
15137 }
15138
15139 static void
15140 OP_OFF64 (int bytemode, int sizeflag)
15141 {
15142   bfd_vma off;
15143
15144   if (address_mode != mode_64bit
15145       || (prefixes & PREFIX_ADDR))
15146     {
15147       OP_OFF (bytemode, sizeflag);
15148       return;
15149     }
15150
15151   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15152     intel_operand_size (bytemode, sizeflag);
15153   append_seg ();
15154
15155   off = get64 ();
15156
15157   if (intel_syntax)
15158     {
15159       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15160                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15161         {
15162           oappend (names_seg[ds_reg - es_reg]);
15163           oappend (":");
15164         }
15165     }
15166   print_operand_value (scratchbuf, 1, off);
15167   oappend (scratchbuf);
15168 }
15169
15170 static void
15171 ptr_reg (int code, int sizeflag)
15172 {
15173   const char *s;
15174
15175   *obufp++ = open_char;
15176   used_prefixes |= (prefixes & PREFIX_ADDR);
15177   if (address_mode == mode_64bit)
15178     {
15179       if (!(sizeflag & AFLAG))
15180         s = names32[code - eAX_reg];
15181       else
15182         s = names64[code - eAX_reg];
15183     }
15184   else if (sizeflag & AFLAG)
15185     s = names32[code - eAX_reg];
15186   else
15187     s = names16[code - eAX_reg];
15188   oappend (s);
15189   *obufp++ = close_char;
15190   *obufp = 0;
15191 }
15192
15193 static void
15194 OP_ESreg (int code, int sizeflag)
15195 {
15196   if (intel_syntax)
15197     {
15198       switch (codep[-1])
15199         {
15200         case 0x6d:      /* insw/insl */
15201           intel_operand_size (z_mode, sizeflag);
15202           break;
15203         case 0xa5:      /* movsw/movsl/movsq */
15204         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15205         case 0xab:      /* stosw/stosl */
15206         case 0xaf:      /* scasw/scasl */
15207           intel_operand_size (v_mode, sizeflag);
15208           break;
15209         default:
15210           intel_operand_size (b_mode, sizeflag);
15211         }
15212     }
15213   oappend_maybe_intel ("%es:");
15214   ptr_reg (code, sizeflag);
15215 }
15216
15217 static void
15218 OP_DSreg (int code, int sizeflag)
15219 {
15220   if (intel_syntax)
15221     {
15222       switch (codep[-1])
15223         {
15224         case 0x6f:      /* outsw/outsl */
15225           intel_operand_size (z_mode, sizeflag);
15226           break;
15227         case 0xa5:      /* movsw/movsl/movsq */
15228         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15229         case 0xad:      /* lodsw/lodsl/lodsq */
15230           intel_operand_size (v_mode, sizeflag);
15231           break;
15232         default:
15233           intel_operand_size (b_mode, sizeflag);
15234         }
15235     }
15236   if ((prefixes
15237        & (PREFIX_CS
15238           | PREFIX_DS
15239           | PREFIX_SS
15240           | PREFIX_ES
15241           | PREFIX_FS
15242           | PREFIX_GS)) == 0)
15243     prefixes |= PREFIX_DS;
15244   append_seg ();
15245   ptr_reg (code, sizeflag);
15246 }
15247
15248 static void
15249 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15250 {
15251   int add;
15252   if (rex & REX_R)
15253     {
15254       USED_REX (REX_R);
15255       add = 8;
15256     }
15257   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15258     {
15259       all_prefixes[last_lock_prefix] = 0;
15260       used_prefixes |= PREFIX_LOCK;
15261       add = 8;
15262     }
15263   else
15264     add = 0;
15265   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15266   oappend_maybe_intel (scratchbuf);
15267 }
15268
15269 static void
15270 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15271 {
15272   int add;
15273   USED_REX (REX_R);
15274   if (rex & REX_R)
15275     add = 8;
15276   else
15277     add = 0;
15278   if (intel_syntax)
15279     sprintf (scratchbuf, "db%d", modrm.reg + add);
15280   else
15281     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15282   oappend (scratchbuf);
15283 }
15284
15285 static void
15286 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15287 {
15288   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15289   oappend_maybe_intel (scratchbuf);
15290 }
15291
15292 static void
15293 OP_R (int bytemode, int sizeflag)
15294 {
15295   if (modrm.mod == 3)
15296     OP_E (bytemode, sizeflag);
15297   else
15298     BadOp ();
15299 }
15300
15301 static void
15302 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15303 {
15304   int reg = modrm.reg;
15305   const char **names;
15306
15307   used_prefixes |= (prefixes & PREFIX_DATA);
15308   if (prefixes & PREFIX_DATA)
15309     {
15310       names = names_xmm;
15311       USED_REX (REX_R);
15312       if (rex & REX_R)
15313         reg += 8;
15314     }
15315   else
15316     names = names_mm;
15317   oappend (names[reg]);
15318 }
15319
15320 static void
15321 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15322 {
15323   int reg = modrm.reg;
15324   const char **names;
15325
15326   USED_REX (REX_R);
15327   if (rex & REX_R)
15328     reg += 8;
15329   if (vex.evex)
15330     {
15331       if (!vex.r)
15332         reg += 16;
15333     }
15334
15335   if (need_vex
15336       && bytemode != xmm_mode
15337       && bytemode != xmmq_mode
15338       && bytemode != evex_half_bcst_xmmq_mode
15339       && bytemode != ymm_mode
15340       && bytemode != scalar_mode)
15341     {
15342       switch (vex.length)
15343         {
15344         case 128:
15345           names = names_xmm;
15346           break;
15347         case 256:
15348           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15349             names = names_ymm;
15350           else
15351             names = names_xmm;
15352           break;
15353         case 512:
15354           names = names_zmm;
15355           break;
15356         default:
15357           abort ();
15358         }
15359     }
15360   else if (bytemode == xmmq_mode
15361            || bytemode == evex_half_bcst_xmmq_mode)
15362     {
15363       switch (vex.length)
15364         {
15365         case 128:
15366         case 256:
15367           names = names_xmm;
15368           break;
15369         case 512:
15370           names = names_ymm;
15371           break;
15372         default:
15373           abort ();
15374         }
15375     }
15376   else if (bytemode == ymm_mode)
15377     names = names_ymm;
15378   else
15379     names = names_xmm;
15380   oappend (names[reg]);
15381 }
15382
15383 static void
15384 OP_EM (int bytemode, int sizeflag)
15385 {
15386   int reg;
15387   const char **names;
15388
15389   if (modrm.mod != 3)
15390     {
15391       if (intel_syntax
15392           && (bytemode == v_mode || bytemode == v_swap_mode))
15393         {
15394           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15395           used_prefixes |= (prefixes & PREFIX_DATA);
15396         }
15397       OP_E (bytemode, sizeflag);
15398       return;
15399     }
15400
15401   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15402     swap_operand ();
15403
15404   /* Skip mod/rm byte.  */
15405   MODRM_CHECK;
15406   codep++;
15407   used_prefixes |= (prefixes & PREFIX_DATA);
15408   reg = modrm.rm;
15409   if (prefixes & PREFIX_DATA)
15410     {
15411       names = names_xmm;
15412       USED_REX (REX_B);
15413       if (rex & REX_B)
15414         reg += 8;
15415     }
15416   else
15417     names = names_mm;
15418   oappend (names[reg]);
15419 }
15420
15421 /* cvt* are the only instructions in sse2 which have
15422    both SSE and MMX operands and also have 0x66 prefix
15423    in their opcode. 0x66 was originally used to differentiate
15424    between SSE and MMX instruction(operands). So we have to handle the
15425    cvt* separately using OP_EMC and OP_MXC */
15426 static void
15427 OP_EMC (int bytemode, int sizeflag)
15428 {
15429   if (modrm.mod != 3)
15430     {
15431       if (intel_syntax && bytemode == v_mode)
15432         {
15433           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15434           used_prefixes |= (prefixes & PREFIX_DATA);
15435         }
15436       OP_E (bytemode, sizeflag);
15437       return;
15438     }
15439
15440   /* Skip mod/rm byte.  */
15441   MODRM_CHECK;
15442   codep++;
15443   used_prefixes |= (prefixes & PREFIX_DATA);
15444   oappend (names_mm[modrm.rm]);
15445 }
15446
15447 static void
15448 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15449 {
15450   used_prefixes |= (prefixes & PREFIX_DATA);
15451   oappend (names_mm[modrm.reg]);
15452 }
15453
15454 static void
15455 OP_EX (int bytemode, int sizeflag)
15456 {
15457   int reg;
15458   const char **names;
15459
15460   /* Skip mod/rm byte.  */
15461   MODRM_CHECK;
15462   codep++;
15463
15464   if (modrm.mod != 3)
15465     {
15466       OP_E_memory (bytemode, sizeflag);
15467       return;
15468     }
15469
15470   reg = modrm.rm;
15471   USED_REX (REX_B);
15472   if (rex & REX_B)
15473     reg += 8;
15474   if (vex.evex)
15475     {
15476       USED_REX (REX_X);
15477       if ((rex & REX_X))
15478         reg += 16;
15479     }
15480
15481   if ((sizeflag & SUFFIX_ALWAYS)
15482       && (bytemode == x_swap_mode
15483           || bytemode == d_swap_mode
15484           || bytemode == d_scalar_swap_mode
15485           || bytemode == q_swap_mode
15486           || bytemode == q_scalar_swap_mode))
15487     swap_operand ();
15488
15489   if (need_vex
15490       && bytemode != xmm_mode
15491       && bytemode != xmmdw_mode
15492       && bytemode != xmmqd_mode
15493       && bytemode != xmm_mb_mode
15494       && bytemode != xmm_mw_mode
15495       && bytemode != xmm_md_mode
15496       && bytemode != xmm_mq_mode
15497       && bytemode != xmm_mdq_mode
15498       && bytemode != xmmq_mode
15499       && bytemode != evex_half_bcst_xmmq_mode
15500       && bytemode != ymm_mode
15501       && bytemode != d_scalar_mode
15502       && bytemode != d_scalar_swap_mode
15503       && bytemode != q_scalar_mode
15504       && bytemode != q_scalar_swap_mode
15505       && bytemode != vex_scalar_w_dq_mode)
15506     {
15507       switch (vex.length)
15508         {
15509         case 128:
15510           names = names_xmm;
15511           break;
15512         case 256:
15513           names = names_ymm;
15514           break;
15515         case 512:
15516           names = names_zmm;
15517           break;
15518         default:
15519           abort ();
15520         }
15521     }
15522   else if (bytemode == xmmq_mode
15523            || bytemode == evex_half_bcst_xmmq_mode)
15524     {
15525       switch (vex.length)
15526         {
15527         case 128:
15528         case 256:
15529           names = names_xmm;
15530           break;
15531         case 512:
15532           names = names_ymm;
15533           break;
15534         default:
15535           abort ();
15536         }
15537     }
15538   else if (bytemode == ymm_mode)
15539     names = names_ymm;
15540   else
15541     names = names_xmm;
15542   oappend (names[reg]);
15543 }
15544
15545 static void
15546 OP_MS (int bytemode, int sizeflag)
15547 {
15548   if (modrm.mod == 3)
15549     OP_EM (bytemode, sizeflag);
15550   else
15551     BadOp ();
15552 }
15553
15554 static void
15555 OP_XS (int bytemode, int sizeflag)
15556 {
15557   if (modrm.mod == 3)
15558     OP_EX (bytemode, sizeflag);
15559   else
15560     BadOp ();
15561 }
15562
15563 static void
15564 OP_M (int bytemode, int sizeflag)
15565 {
15566   if (modrm.mod == 3)
15567     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15568     BadOp ();
15569   else
15570     OP_E (bytemode, sizeflag);
15571 }
15572
15573 static void
15574 OP_0f07 (int bytemode, int sizeflag)
15575 {
15576   if (modrm.mod != 3 || modrm.rm != 0)
15577     BadOp ();
15578   else
15579     OP_E (bytemode, sizeflag);
15580 }
15581
15582 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15583    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15584
15585 static void
15586 NOP_Fixup1 (int bytemode, int sizeflag)
15587 {
15588   if ((prefixes & PREFIX_DATA) != 0
15589       || (rex != 0
15590           && rex != 0x48
15591           && address_mode == mode_64bit))
15592     OP_REG (bytemode, sizeflag);
15593   else
15594     strcpy (obuf, "nop");
15595 }
15596
15597 static void
15598 NOP_Fixup2 (int bytemode, int sizeflag)
15599 {
15600   if ((prefixes & PREFIX_DATA) != 0
15601       || (rex != 0
15602           && rex != 0x48
15603           && address_mode == mode_64bit))
15604     OP_IMREG (bytemode, sizeflag);
15605 }
15606
15607 static const char *const Suffix3DNow[] = {
15608 /* 00 */        NULL,           NULL,           NULL,           NULL,
15609 /* 04 */        NULL,           NULL,           NULL,           NULL,
15610 /* 08 */        NULL,           NULL,           NULL,           NULL,
15611 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15612 /* 10 */        NULL,           NULL,           NULL,           NULL,
15613 /* 14 */        NULL,           NULL,           NULL,           NULL,
15614 /* 18 */        NULL,           NULL,           NULL,           NULL,
15615 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15616 /* 20 */        NULL,           NULL,           NULL,           NULL,
15617 /* 24 */        NULL,           NULL,           NULL,           NULL,
15618 /* 28 */        NULL,           NULL,           NULL,           NULL,
15619 /* 2C */        NULL,           NULL,           NULL,           NULL,
15620 /* 30 */        NULL,           NULL,           NULL,           NULL,
15621 /* 34 */        NULL,           NULL,           NULL,           NULL,
15622 /* 38 */        NULL,           NULL,           NULL,           NULL,
15623 /* 3C */        NULL,           NULL,           NULL,           NULL,
15624 /* 40 */        NULL,           NULL,           NULL,           NULL,
15625 /* 44 */        NULL,           NULL,           NULL,           NULL,
15626 /* 48 */        NULL,           NULL,           NULL,           NULL,
15627 /* 4C */        NULL,           NULL,           NULL,           NULL,
15628 /* 50 */        NULL,           NULL,           NULL,           NULL,
15629 /* 54 */        NULL,           NULL,           NULL,           NULL,
15630 /* 58 */        NULL,           NULL,           NULL,           NULL,
15631 /* 5C */        NULL,           NULL,           NULL,           NULL,
15632 /* 60 */        NULL,           NULL,           NULL,           NULL,
15633 /* 64 */        NULL,           NULL,           NULL,           NULL,
15634 /* 68 */        NULL,           NULL,           NULL,           NULL,
15635 /* 6C */        NULL,           NULL,           NULL,           NULL,
15636 /* 70 */        NULL,           NULL,           NULL,           NULL,
15637 /* 74 */        NULL,           NULL,           NULL,           NULL,
15638 /* 78 */        NULL,           NULL,           NULL,           NULL,
15639 /* 7C */        NULL,           NULL,           NULL,           NULL,
15640 /* 80 */        NULL,           NULL,           NULL,           NULL,
15641 /* 84 */        NULL,           NULL,           NULL,           NULL,
15642 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15643 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15644 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15645 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15646 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15647 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15648 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15649 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15650 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15651 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15652 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15653 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15654 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15655 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15656 /* C0 */        NULL,           NULL,           NULL,           NULL,
15657 /* C4 */        NULL,           NULL,           NULL,           NULL,
15658 /* C8 */        NULL,           NULL,           NULL,           NULL,
15659 /* CC */        NULL,           NULL,           NULL,           NULL,
15660 /* D0 */        NULL,           NULL,           NULL,           NULL,
15661 /* D4 */        NULL,           NULL,           NULL,           NULL,
15662 /* D8 */        NULL,           NULL,           NULL,           NULL,
15663 /* DC */        NULL,           NULL,           NULL,           NULL,
15664 /* E0 */        NULL,           NULL,           NULL,           NULL,
15665 /* E4 */        NULL,           NULL,           NULL,           NULL,
15666 /* E8 */        NULL,           NULL,           NULL,           NULL,
15667 /* EC */        NULL,           NULL,           NULL,           NULL,
15668 /* F0 */        NULL,           NULL,           NULL,           NULL,
15669 /* F4 */        NULL,           NULL,           NULL,           NULL,
15670 /* F8 */        NULL,           NULL,           NULL,           NULL,
15671 /* FC */        NULL,           NULL,           NULL,           NULL,
15672 };
15673
15674 static void
15675 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15676 {
15677   const char *mnemonic;
15678
15679   FETCH_DATA (the_info, codep + 1);
15680   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15681      place where an 8-bit immediate would normally go.  ie. the last
15682      byte of the instruction.  */
15683   obufp = mnemonicendp;
15684   mnemonic = Suffix3DNow[*codep++ & 0xff];
15685   if (mnemonic)
15686     oappend (mnemonic);
15687   else
15688     {
15689       /* Since a variable sized modrm/sib chunk is between the start
15690          of the opcode (0x0f0f) and the opcode suffix, we need to do
15691          all the modrm processing first, and don't know until now that
15692          we have a bad opcode.  This necessitates some cleaning up.  */
15693       op_out[0][0] = '\0';
15694       op_out[1][0] = '\0';
15695       BadOp ();
15696     }
15697   mnemonicendp = obufp;
15698 }
15699
15700 static struct op simd_cmp_op[] =
15701 {
15702   { STRING_COMMA_LEN ("eq") },
15703   { STRING_COMMA_LEN ("lt") },
15704   { STRING_COMMA_LEN ("le") },
15705   { STRING_COMMA_LEN ("unord") },
15706   { STRING_COMMA_LEN ("neq") },
15707   { STRING_COMMA_LEN ("nlt") },
15708   { STRING_COMMA_LEN ("nle") },
15709   { STRING_COMMA_LEN ("ord") }
15710 };
15711
15712 static void
15713 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15714 {
15715   unsigned int cmp_type;
15716
15717   FETCH_DATA (the_info, codep + 1);
15718   cmp_type = *codep++ & 0xff;
15719   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15720     {
15721       char suffix [3];
15722       char *p = mnemonicendp - 2;
15723       suffix[0] = p[0];
15724       suffix[1] = p[1];
15725       suffix[2] = '\0';
15726       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15727       mnemonicendp += simd_cmp_op[cmp_type].len;
15728     }
15729   else
15730     {
15731       /* We have a reserved extension byte.  Output it directly.  */
15732       scratchbuf[0] = '$';
15733       print_operand_value (scratchbuf + 1, 1, cmp_type);
15734       oappend_maybe_intel (scratchbuf);
15735       scratchbuf[0] = '\0';
15736     }
15737 }
15738
15739 static void
15740 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15741           int sizeflag ATTRIBUTE_UNUSED)
15742 {
15743   /* mwait %eax,%ecx  */
15744   if (!intel_syntax)
15745     {
15746       const char **names = (address_mode == mode_64bit
15747                             ? names64 : names32);
15748       strcpy (op_out[0], names[0]);
15749       strcpy (op_out[1], names[1]);
15750       two_source_ops = 1;
15751     }
15752   /* Skip mod/rm byte.  */
15753   MODRM_CHECK;
15754   codep++;
15755 }
15756
15757 static void
15758 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15759             int sizeflag ATTRIBUTE_UNUSED)
15760 {
15761   /* monitor %eax,%ecx,%edx"  */
15762   if (!intel_syntax)
15763     {
15764       const char **op1_names;
15765       const char **names = (address_mode == mode_64bit
15766                             ? names64 : names32);
15767
15768       if (!(prefixes & PREFIX_ADDR))
15769         op1_names = (address_mode == mode_16bit
15770                      ? names16 : names);
15771       else
15772         {
15773           /* Remove "addr16/addr32".  */
15774           all_prefixes[last_addr_prefix] = 0;
15775           op1_names = (address_mode != mode_32bit
15776                        ? names32 : names16);
15777           used_prefixes |= PREFIX_ADDR;
15778         }
15779       strcpy (op_out[0], op1_names[0]);
15780       strcpy (op_out[1], names[1]);
15781       strcpy (op_out[2], names[2]);
15782       two_source_ops = 1;
15783     }
15784   /* Skip mod/rm byte.  */
15785   MODRM_CHECK;
15786   codep++;
15787 }
15788
15789 static void
15790 BadOp (void)
15791 {
15792   /* Throw away prefixes and 1st. opcode byte.  */
15793   codep = insn_codep + 1;
15794   oappend ("(bad)");
15795 }
15796
15797 static void
15798 REP_Fixup (int bytemode, int sizeflag)
15799 {
15800   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15801      lods and stos.  */
15802   if (prefixes & PREFIX_REPZ)
15803     all_prefixes[last_repz_prefix] = REP_PREFIX;
15804
15805   switch (bytemode)
15806     {
15807     case al_reg:
15808     case eAX_reg:
15809     case indir_dx_reg:
15810       OP_IMREG (bytemode, sizeflag);
15811       break;
15812     case eDI_reg:
15813       OP_ESreg (bytemode, sizeflag);
15814       break;
15815     case eSI_reg:
15816       OP_DSreg (bytemode, sizeflag);
15817       break;
15818     default:
15819       abort ();
15820       break;
15821     }
15822 }
15823
15824 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15825    "bnd".  */
15826
15827 static void
15828 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15829 {
15830   if (prefixes & PREFIX_REPNZ)
15831     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15832 }
15833
15834 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15835    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15836  */
15837
15838 static void
15839 HLE_Fixup1 (int bytemode, int sizeflag)
15840 {
15841   if (modrm.mod != 3
15842       && (prefixes & PREFIX_LOCK) != 0)
15843     {
15844       if (prefixes & PREFIX_REPZ)
15845         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15846       if (prefixes & PREFIX_REPNZ)
15847         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15848     }
15849
15850   OP_E (bytemode, sizeflag);
15851 }
15852
15853 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15854    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15855  */
15856
15857 static void
15858 HLE_Fixup2 (int bytemode, int sizeflag)
15859 {
15860   if (modrm.mod != 3)
15861     {
15862       if (prefixes & PREFIX_REPZ)
15863         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15864       if (prefixes & PREFIX_REPNZ)
15865         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15866     }
15867
15868   OP_E (bytemode, sizeflag);
15869 }
15870
15871 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15872    "xrelease" for memory operand.  No check for LOCK prefix.   */
15873
15874 static void
15875 HLE_Fixup3 (int bytemode, int sizeflag)
15876 {
15877   if (modrm.mod != 3
15878       && last_repz_prefix > last_repnz_prefix
15879       && (prefixes & PREFIX_REPZ) != 0)
15880     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15881
15882   OP_E (bytemode, sizeflag);
15883 }
15884
15885 static void
15886 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15887 {
15888   USED_REX (REX_W);
15889   if (rex & REX_W)
15890     {
15891       /* Change cmpxchg8b to cmpxchg16b.  */
15892       char *p = mnemonicendp - 2;
15893       mnemonicendp = stpcpy (p, "16b");
15894       bytemode = o_mode;
15895     }
15896   else if ((prefixes & PREFIX_LOCK) != 0)
15897     {
15898       if (prefixes & PREFIX_REPZ)
15899         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15900       if (prefixes & PREFIX_REPNZ)
15901         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15902     }
15903
15904   OP_M (bytemode, sizeflag);
15905 }
15906
15907 static void
15908 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15909 {
15910   const char **names;
15911
15912   if (need_vex)
15913     {
15914       switch (vex.length)
15915         {
15916         case 128:
15917           names = names_xmm;
15918           break;
15919         case 256:
15920           names = names_ymm;
15921           break;
15922         default:
15923           abort ();
15924         }
15925     }
15926   else
15927     names = names_xmm;
15928   oappend (names[reg]);
15929 }
15930
15931 static void
15932 CRC32_Fixup (int bytemode, int sizeflag)
15933 {
15934   /* Add proper suffix to "crc32".  */
15935   char *p = mnemonicendp;
15936
15937   switch (bytemode)
15938     {
15939     case b_mode:
15940       if (intel_syntax)
15941         goto skip;
15942
15943       *p++ = 'b';
15944       break;
15945     case v_mode:
15946       if (intel_syntax)
15947         goto skip;
15948
15949       USED_REX (REX_W);
15950       if (rex & REX_W)
15951         *p++ = 'q';
15952       else
15953         {
15954           if (sizeflag & DFLAG)
15955             *p++ = 'l';
15956           else
15957             *p++ = 'w';
15958           used_prefixes |= (prefixes & PREFIX_DATA);
15959         }
15960       break;
15961     default:
15962       oappend (INTERNAL_DISASSEMBLER_ERROR);
15963       break;
15964     }
15965   mnemonicendp = p;
15966   *p = '\0';
15967
15968 skip:
15969   if (modrm.mod == 3)
15970     {
15971       int add;
15972
15973       /* Skip mod/rm byte.  */
15974       MODRM_CHECK;
15975       codep++;
15976
15977       USED_REX (REX_B);
15978       add = (rex & REX_B) ? 8 : 0;
15979       if (bytemode == b_mode)
15980         {
15981           USED_REX (0);
15982           if (rex)
15983             oappend (names8rex[modrm.rm + add]);
15984           else
15985             oappend (names8[modrm.rm + add]);
15986         }
15987       else
15988         {
15989           USED_REX (REX_W);
15990           if (rex & REX_W)
15991             oappend (names64[modrm.rm + add]);
15992           else if ((prefixes & PREFIX_DATA))
15993             oappend (names16[modrm.rm + add]);
15994           else
15995             oappend (names32[modrm.rm + add]);
15996         }
15997     }
15998   else
15999     OP_E (bytemode, sizeflag);
16000 }
16001
16002 static void
16003 FXSAVE_Fixup (int bytemode, int sizeflag)
16004 {
16005   /* Add proper suffix to "fxsave" and "fxrstor".  */
16006   USED_REX (REX_W);
16007   if (rex & REX_W)
16008     {
16009       char *p = mnemonicendp;
16010       *p++ = '6';
16011       *p++ = '4';
16012       *p = '\0';
16013       mnemonicendp = p;
16014     }
16015   OP_M (bytemode, sizeflag);
16016 }
16017
16018 /* Display the destination register operand for instructions with
16019    VEX. */
16020
16021 static void
16022 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16023 {
16024   int reg;
16025   const char **names;
16026
16027   if (!need_vex)
16028     abort ();
16029
16030   if (!need_vex_reg)
16031     return;
16032
16033   reg = vex.register_specifier;
16034   if (vex.evex)
16035     {
16036       if (!vex.v)
16037         reg += 16;
16038     }
16039
16040   if (bytemode == vex_scalar_mode)
16041     {
16042       oappend (names_xmm[reg]);
16043       return;
16044     }
16045
16046   switch (vex.length)
16047     {
16048     case 128:
16049       switch (bytemode)
16050         {
16051         case vex_mode:
16052         case vex128_mode:
16053         case vex_vsib_q_w_dq_mode:
16054           names = names_xmm;
16055           break;
16056         case dq_mode:
16057           if (vex.w)
16058             names = names64;
16059           else
16060             names = names32;
16061           break;
16062         case mask_mode:
16063           names = names_mask;
16064           break;
16065         default:
16066           abort ();
16067           return;
16068         }
16069       break;
16070     case 256:
16071       switch (bytemode)
16072         {
16073         case vex_mode:
16074         case vex256_mode:
16075           names = names_ymm;
16076           break;
16077         case vex_vsib_q_w_dq_mode:
16078           names = vex.w ? names_ymm : names_xmm;
16079           break;
16080         case mask_mode:
16081           names = names_mask;
16082           break;
16083         default:
16084           abort ();
16085           return;
16086         }
16087       break;
16088     case 512:
16089       names = names_zmm;
16090       break;
16091     default:
16092       abort ();
16093       break;
16094     }
16095   oappend (names[reg]);
16096 }
16097
16098 /* Get the VEX immediate byte without moving codep.  */
16099
16100 static unsigned char
16101 get_vex_imm8 (int sizeflag, int opnum)
16102 {
16103   int bytes_before_imm = 0;
16104
16105   if (modrm.mod != 3)
16106     {
16107       /* There are SIB/displacement bytes.  */
16108       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16109         {
16110           /* 32/64 bit address mode */
16111           int base = modrm.rm;
16112
16113           /* Check SIB byte.  */
16114           if (base == 4)
16115             {
16116               FETCH_DATA (the_info, codep + 1);
16117               base = *codep & 7;
16118               /* When decoding the third source, don't increase
16119                  bytes_before_imm as this has already been incremented
16120                  by one in OP_E_memory while decoding the second
16121                  source operand.  */
16122               if (opnum == 0)
16123                 bytes_before_imm++;
16124             }
16125
16126           /* Don't increase bytes_before_imm when decoding the third source,
16127              it has already been incremented by OP_E_memory while decoding
16128              the second source operand.  */
16129           if (opnum == 0)
16130             {
16131               switch (modrm.mod)
16132                 {
16133                   case 0:
16134                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16135                        SIB == 5, there is a 4 byte displacement.  */
16136                     if (base != 5)
16137                       /* No displacement. */
16138                       break;
16139                   case 2:
16140                     /* 4 byte displacement.  */
16141                     bytes_before_imm += 4;
16142                     break;
16143                   case 1:
16144                     /* 1 byte displacement.  */
16145                     bytes_before_imm++;
16146                     break;
16147                 }
16148             }
16149         }
16150       else
16151         {
16152           /* 16 bit address mode */
16153           /* Don't increase bytes_before_imm when decoding the third source,
16154              it has already been incremented by OP_E_memory while decoding
16155              the second source operand.  */
16156           if (opnum == 0)
16157             {
16158               switch (modrm.mod)
16159                 {
16160                 case 0:
16161                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16162                   if (modrm.rm != 6)
16163                     /* No displacement. */
16164                     break;
16165                 case 2:
16166                   /* 2 byte displacement.  */
16167                   bytes_before_imm += 2;
16168                   break;
16169                 case 1:
16170                   /* 1 byte displacement: when decoding the third source,
16171                      don't increase bytes_before_imm as this has already
16172                      been incremented by one in OP_E_memory while decoding
16173                      the second source operand.  */
16174                   if (opnum == 0)
16175                     bytes_before_imm++;
16176
16177                   break;
16178                 }
16179             }
16180         }
16181     }
16182
16183   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16184   return codep [bytes_before_imm];
16185 }
16186
16187 static void
16188 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16189 {
16190   const char **names;
16191
16192   if (reg == -1 && modrm.mod != 3)
16193     {
16194       OP_E_memory (bytemode, sizeflag);
16195       return;
16196     }
16197   else
16198     {
16199       if (reg == -1)
16200         {
16201           reg = modrm.rm;
16202           USED_REX (REX_B);
16203           if (rex & REX_B)
16204             reg += 8;
16205         }
16206       else if (reg > 7 && address_mode != mode_64bit)
16207         BadOp ();
16208     }
16209
16210   switch (vex.length)
16211     {
16212     case 128:
16213       names = names_xmm;
16214       break;
16215     case 256:
16216       names = names_ymm;
16217       break;
16218     default:
16219       abort ();
16220     }
16221   oappend (names[reg]);
16222 }
16223
16224 static void
16225 OP_EX_VexImmW (int bytemode, int sizeflag)
16226 {
16227   int reg = -1;
16228   static unsigned char vex_imm8;
16229
16230   if (vex_w_done == 0)
16231     {
16232       vex_w_done = 1;
16233
16234       /* Skip mod/rm byte.  */
16235       MODRM_CHECK;
16236       codep++;
16237
16238       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16239
16240       if (vex.w)
16241           reg = vex_imm8 >> 4;
16242
16243       OP_EX_VexReg (bytemode, sizeflag, reg);
16244     }
16245   else if (vex_w_done == 1)
16246     {
16247       vex_w_done = 2;
16248
16249       if (!vex.w)
16250           reg = vex_imm8 >> 4;
16251
16252       OP_EX_VexReg (bytemode, sizeflag, reg);
16253     }
16254   else
16255     {
16256       /* Output the imm8 directly.  */
16257       scratchbuf[0] = '$';
16258       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16259       oappend_maybe_intel (scratchbuf);
16260       scratchbuf[0] = '\0';
16261       codep++;
16262     }
16263 }
16264
16265 static void
16266 OP_Vex_2src (int bytemode, int sizeflag)
16267 {
16268   if (modrm.mod == 3)
16269     {
16270       int reg = modrm.rm;
16271       USED_REX (REX_B);
16272       if (rex & REX_B)
16273         reg += 8;
16274       oappend (names_xmm[reg]);
16275     }
16276   else
16277     {
16278       if (intel_syntax
16279           && (bytemode == v_mode || bytemode == v_swap_mode))
16280         {
16281           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16282           used_prefixes |= (prefixes & PREFIX_DATA);
16283         }
16284       OP_E (bytemode, sizeflag);
16285     }
16286 }
16287
16288 static void
16289 OP_Vex_2src_1 (int bytemode, int sizeflag)
16290 {
16291   if (modrm.mod == 3)
16292     {
16293       /* Skip mod/rm byte.   */
16294       MODRM_CHECK;
16295       codep++;
16296     }
16297
16298   if (vex.w)
16299     oappend (names_xmm[vex.register_specifier]);
16300   else
16301     OP_Vex_2src (bytemode, sizeflag);
16302 }
16303
16304 static void
16305 OP_Vex_2src_2 (int bytemode, int sizeflag)
16306 {
16307   if (vex.w)
16308     OP_Vex_2src (bytemode, sizeflag);
16309   else
16310     oappend (names_xmm[vex.register_specifier]);
16311 }
16312
16313 static void
16314 OP_EX_VexW (int bytemode, int sizeflag)
16315 {
16316   int reg = -1;
16317
16318   if (!vex_w_done)
16319     {
16320       vex_w_done = 1;
16321
16322       /* Skip mod/rm byte.  */
16323       MODRM_CHECK;
16324       codep++;
16325
16326       if (vex.w)
16327         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16328     }
16329   else
16330     {
16331       if (!vex.w)
16332         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16333     }
16334
16335   OP_EX_VexReg (bytemode, sizeflag, reg);
16336 }
16337
16338 static void
16339 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16340              int sizeflag ATTRIBUTE_UNUSED)
16341 {
16342   /* Skip the immediate byte and check for invalid bits.  */
16343   FETCH_DATA (the_info, codep + 1);
16344   if (*codep++ & 0xf)
16345     BadOp ();
16346 }
16347
16348 static void
16349 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16350 {
16351   int reg;
16352   const char **names;
16353
16354   FETCH_DATA (the_info, codep + 1);
16355   reg = *codep++;
16356
16357   if (bytemode != x_mode)
16358     abort ();
16359
16360   if (reg & 0xf)
16361       BadOp ();
16362
16363   reg >>= 4;
16364   if (reg > 7 && address_mode != mode_64bit)
16365     BadOp ();
16366
16367   switch (vex.length)
16368     {
16369     case 128:
16370       names = names_xmm;
16371       break;
16372     case 256:
16373       names = names_ymm;
16374       break;
16375     default:
16376       abort ();
16377     }
16378   oappend (names[reg]);
16379 }
16380
16381 static void
16382 OP_XMM_VexW (int bytemode, int sizeflag)
16383 {
16384   /* Turn off the REX.W bit since it is used for swapping operands
16385      now.  */
16386   rex &= ~REX_W;
16387   OP_XMM (bytemode, sizeflag);
16388 }
16389
16390 static void
16391 OP_EX_Vex (int bytemode, int sizeflag)
16392 {
16393   if (modrm.mod != 3)
16394     {
16395       if (vex.register_specifier != 0)
16396         BadOp ();
16397       need_vex_reg = 0;
16398     }
16399   OP_EX (bytemode, sizeflag);
16400 }
16401
16402 static void
16403 OP_XMM_Vex (int bytemode, int sizeflag)
16404 {
16405   if (modrm.mod != 3)
16406     {
16407       if (vex.register_specifier != 0)
16408         BadOp ();
16409       need_vex_reg = 0;
16410     }
16411   OP_XMM (bytemode, sizeflag);
16412 }
16413
16414 static void
16415 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16416 {
16417   switch (vex.length)
16418     {
16419     case 128:
16420       mnemonicendp = stpcpy (obuf, "vzeroupper");
16421       break;
16422     case 256:
16423       mnemonicendp = stpcpy (obuf, "vzeroall");
16424       break;
16425     default:
16426       abort ();
16427     }
16428 }
16429
16430 static struct op vex_cmp_op[] =
16431 {
16432   { STRING_COMMA_LEN ("eq") },
16433   { STRING_COMMA_LEN ("lt") },
16434   { STRING_COMMA_LEN ("le") },
16435   { STRING_COMMA_LEN ("unord") },
16436   { STRING_COMMA_LEN ("neq") },
16437   { STRING_COMMA_LEN ("nlt") },
16438   { STRING_COMMA_LEN ("nle") },
16439   { STRING_COMMA_LEN ("ord") },
16440   { STRING_COMMA_LEN ("eq_uq") },
16441   { STRING_COMMA_LEN ("nge") },
16442   { STRING_COMMA_LEN ("ngt") },
16443   { STRING_COMMA_LEN ("false") },
16444   { STRING_COMMA_LEN ("neq_oq") },
16445   { STRING_COMMA_LEN ("ge") },
16446   { STRING_COMMA_LEN ("gt") },
16447   { STRING_COMMA_LEN ("true") },
16448   { STRING_COMMA_LEN ("eq_os") },
16449   { STRING_COMMA_LEN ("lt_oq") },
16450   { STRING_COMMA_LEN ("le_oq") },
16451   { STRING_COMMA_LEN ("unord_s") },
16452   { STRING_COMMA_LEN ("neq_us") },
16453   { STRING_COMMA_LEN ("nlt_uq") },
16454   { STRING_COMMA_LEN ("nle_uq") },
16455   { STRING_COMMA_LEN ("ord_s") },
16456   { STRING_COMMA_LEN ("eq_us") },
16457   { STRING_COMMA_LEN ("nge_uq") },
16458   { STRING_COMMA_LEN ("ngt_uq") },
16459   { STRING_COMMA_LEN ("false_os") },
16460   { STRING_COMMA_LEN ("neq_os") },
16461   { STRING_COMMA_LEN ("ge_oq") },
16462   { STRING_COMMA_LEN ("gt_oq") },
16463   { STRING_COMMA_LEN ("true_us") },
16464 };
16465
16466 static void
16467 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16468 {
16469   unsigned int cmp_type;
16470
16471   FETCH_DATA (the_info, codep + 1);
16472   cmp_type = *codep++ & 0xff;
16473   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16474     {
16475       char suffix [3];
16476       char *p = mnemonicendp - 2;
16477       suffix[0] = p[0];
16478       suffix[1] = p[1];
16479       suffix[2] = '\0';
16480       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16481       mnemonicendp += vex_cmp_op[cmp_type].len;
16482     }
16483   else
16484     {
16485       /* We have a reserved extension byte.  Output it directly.  */
16486       scratchbuf[0] = '$';
16487       print_operand_value (scratchbuf + 1, 1, cmp_type);
16488       oappend_maybe_intel (scratchbuf);
16489       scratchbuf[0] = '\0';
16490     }
16491 }
16492
16493 static void
16494 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16495              int sizeflag ATTRIBUTE_UNUSED)
16496 {
16497   unsigned int cmp_type;
16498
16499   if (!vex.evex)
16500     abort ();
16501
16502   FETCH_DATA (the_info, codep + 1);
16503   cmp_type = *codep++ & 0xff;
16504   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16505      If it's the case, print suffix, otherwise - print the immediate.  */
16506   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16507       && cmp_type != 3
16508       && cmp_type != 7)
16509     {
16510       char suffix [3];
16511       char *p = mnemonicendp - 2;
16512
16513       /* vpcmp* can have both one- and two-lettered suffix.  */
16514       if (p[0] == 'p')
16515         {
16516           p++;
16517           suffix[0] = p[0];
16518           suffix[1] = '\0';
16519         }
16520       else
16521         {
16522           suffix[0] = p[0];
16523           suffix[1] = p[1];
16524           suffix[2] = '\0';
16525         }
16526
16527       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16528       mnemonicendp += simd_cmp_op[cmp_type].len;
16529     }
16530   else
16531     {
16532       /* We have a reserved extension byte.  Output it directly.  */
16533       scratchbuf[0] = '$';
16534       print_operand_value (scratchbuf + 1, 1, cmp_type);
16535       oappend_maybe_intel (scratchbuf);
16536       scratchbuf[0] = '\0';
16537     }
16538 }
16539
16540 static const struct op pclmul_op[] =
16541 {
16542   { STRING_COMMA_LEN ("lql") },
16543   { STRING_COMMA_LEN ("hql") },
16544   { STRING_COMMA_LEN ("lqh") },
16545   { STRING_COMMA_LEN ("hqh") }
16546 };
16547
16548 static void
16549 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16550               int sizeflag ATTRIBUTE_UNUSED)
16551 {
16552   unsigned int pclmul_type;
16553
16554   FETCH_DATA (the_info, codep + 1);
16555   pclmul_type = *codep++ & 0xff;
16556   switch (pclmul_type)
16557     {
16558     case 0x10:
16559       pclmul_type = 2;
16560       break;
16561     case 0x11:
16562       pclmul_type = 3;
16563       break;
16564     default:
16565       break;
16566     }
16567   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16568     {
16569       char suffix [4];
16570       char *p = mnemonicendp - 3;
16571       suffix[0] = p[0];
16572       suffix[1] = p[1];
16573       suffix[2] = p[2];
16574       suffix[3] = '\0';
16575       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16576       mnemonicendp += pclmul_op[pclmul_type].len;
16577     }
16578   else
16579     {
16580       /* We have a reserved extension byte.  Output it directly.  */
16581       scratchbuf[0] = '$';
16582       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16583       oappend_maybe_intel (scratchbuf);
16584       scratchbuf[0] = '\0';
16585     }
16586 }
16587
16588 static void
16589 MOVBE_Fixup (int bytemode, int sizeflag)
16590 {
16591   /* Add proper suffix to "movbe".  */
16592   char *p = mnemonicendp;
16593
16594   switch (bytemode)
16595     {
16596     case v_mode:
16597       if (intel_syntax)
16598         goto skip;
16599
16600       USED_REX (REX_W);
16601       if (sizeflag & SUFFIX_ALWAYS)
16602         {
16603           if (rex & REX_W)
16604             *p++ = 'q';
16605           else
16606             {
16607               if (sizeflag & DFLAG)
16608                 *p++ = 'l';
16609               else
16610                 *p++ = 'w';
16611               used_prefixes |= (prefixes & PREFIX_DATA);
16612             }
16613         }
16614       break;
16615     default:
16616       oappend (INTERNAL_DISASSEMBLER_ERROR);
16617       break;
16618     }
16619   mnemonicendp = p;
16620   *p = '\0';
16621
16622 skip:
16623   OP_M (bytemode, sizeflag);
16624 }
16625
16626 static void
16627 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16628 {
16629   int reg;
16630   const char **names;
16631
16632   /* Skip mod/rm byte.  */
16633   MODRM_CHECK;
16634   codep++;
16635
16636   if (vex.w)
16637     names = names64;
16638   else
16639     names = names32;
16640
16641   reg = modrm.rm;
16642   USED_REX (REX_B);
16643   if (rex & REX_B)
16644     reg += 8;
16645
16646   oappend (names[reg]);
16647 }
16648
16649 static void
16650 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16651 {
16652   const char **names;
16653
16654   if (vex.w)
16655     names = names64;
16656   else
16657     names = names32;
16658
16659   oappend (names[vex.register_specifier]);
16660 }
16661
16662 static void
16663 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16664 {
16665   if (!vex.evex
16666       || bytemode != mask_mode)
16667     abort ();
16668
16669   USED_REX (REX_R);
16670   if ((rex & REX_R) != 0 || !vex.r)
16671     {
16672       BadOp ();
16673       return;
16674     }
16675
16676   oappend (names_mask [modrm.reg]);
16677 }
16678
16679 static void
16680 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16681 {
16682   if (!vex.evex
16683       || (bytemode != evex_rounding_mode
16684           && bytemode != evex_sae_mode))
16685     abort ();
16686   if (modrm.mod == 3 && vex.b)
16687     switch (bytemode)
16688       {
16689       case evex_rounding_mode:
16690         oappend (names_rounding[vex.ll]);
16691         break;
16692       case evex_sae_mode:
16693         oappend ("{sae}");
16694         break;
16695       default:
16696         break;
16697       }
16698 }