opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_UD_SHIFT         8
 226 #define PREFIX_UD_REPZ          (PREFIX_REPZ << PREFIX_UD_SHIFT)
 227 #define PREFIX_UD_REPNZ         (PREFIX_REPNZ << PREFIX_UD_SHIFT)
 228 #define PREFIX_UD_DATA          (PREFIX_DATA << PREFIX_UD_SHIFT)
 229 #define PREFIX_UD_ADDR          (PREFIX_ADDR << PREFIX_UD_SHIFT)
 230 #define PREFIX_UD_LOCK          (PREFIX_LOCK << PREFIX_UD_SHIFT)
 231 #define PREFIX_IGNORED_SHIFT    16
 232 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 234 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 235 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 236 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 237
 238 /* Opcode prefixes.  */
 239 #define PREFIX_OPCODE           (PREFIX_REPZ \
 240                                  | PREFIX_REPNZ \
 241                                  | PREFIX_DATA)
 242
 243 /* Prefixes ignored.  */
 244 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 245                                  | PREFIX_IGNORED_REPNZ \
 246                                  | PREFIX_IGNORED_DATA)
 247
 248 #define XX { NULL, 0 }
 249 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 250
 251 #define Eb { OP_E, b_mode }
 252 #define Ebnd { OP_E, bnd_mode }
 253 #define EbS { OP_E, b_swap_mode }
 254 #define Ev { OP_E, v_mode }
 255 #define Ev_bnd { OP_E, v_bnd_mode }
 256 #define EvS { OP_E, v_swap_mode }
 257 #define Ed { OP_E, d_mode }
 258 #define Edq { OP_E, dq_mode }
 259 #define Edqw { OP_E, dqw_mode }
 260 #define EdqwS { OP_E, dqw_swap_mode }
 261 #define Edqb { OP_E, dqb_mode }
 262 #define Edb { OP_E, db_mode }
 263 #define Edw { OP_E, dw_mode }
 264 #define Edqd { OP_E, dqd_mode }
 265 #define Eq { OP_E, q_mode }
 266 #define indirEv { OP_indirE, stack_v_mode }
 267 #define indirEp { OP_indirE, f_mode }
 268 #define stackEv { OP_E, stack_v_mode }
 269 #define Em { OP_E, m_mode }
 270 #define Ew { OP_E, w_mode }
 271 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 272 #define Ma { OP_M, a_mode }
 273 #define Mb { OP_M, b_mode }
 274 #define Md { OP_M, d_mode }
 275 #define Mo { OP_M, o_mode }
 276 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 277 #define Mq { OP_M, q_mode }
 278 #define Mx { OP_M, x_mode }
 279 #define Mxmm { OP_M, xmm_mode }
 280 #define Gb { OP_G, b_mode }
 281 #define Gbnd { OP_G, bnd_mode }
 282 #define Gv { OP_G, v_mode }
 283 #define Gd { OP_G, d_mode }
 284 #define Gdq { OP_G, dq_mode }
 285 #define Gm { OP_G, m_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdScalar { OP_EX, d_scalar_mode }
 386 #define EXdS { OP_EX, d_swap_mode }
 387 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define VexI4 { VEXI4_Fixup, 0}
 428 #define EXdVex { OP_EX_Vex, d_mode }
 429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVex { OP_EX_Vex, q_mode }
 432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 434 #define EXVexW { OP_EX_VexW, x_mode }
 435 #define EXdVexW { OP_EX_VexW, d_mode }
 436 #define EXqVexW { OP_EX_VexW, q_mode }
 437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 438 #define XMVex { OP_XMM_Vex, 0 }
 439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 440 #define XMVexW { OP_XMM_VexW, 0 }
 441 #define XMVexI4 { OP_REG_VexI4, x_mode }
 442 #define PCLMUL { PCLMUL_Fixup, 0 }
 443 #define VZERO { VZERO_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 449
 450 #define XMask { OP_Mask, mask_mode }
 451 #define MaskG { OP_G, mask_mode }
 452 #define MaskE { OP_E, mask_mode }
 453 #define MaskBDE { OP_E, mask_bd_mode }
 454 #define MaskR { OP_R, mask_mode }
 455 #define MaskVex { OP_VEX, mask_mode }
 456
 457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 461
 462 /* Used handle "rep" prefix for string instructions.  */
 463 #define Xbr { REP_Fixup, eSI_reg }
 464 #define Xvr { REP_Fixup, eSI_reg }
 465 #define Ybr { REP_Fixup, eDI_reg }
 466 #define Yvr { REP_Fixup, eDI_reg }
 467 #define Yzr { REP_Fixup, eDI_reg }
 468 #define indirDXr { REP_Fixup, indir_dx_reg }
 469 #define ALr { REP_Fixup, al_reg }
 470 #define eAXr { REP_Fixup, eAX_reg }
 471
 472 /* Used handle HLE prefix for lockable instructions.  */
 473 #define Ebh1 { HLE_Fixup1, b_mode }
 474 #define Evh1 { HLE_Fixup1, v_mode }
 475 #define Ebh2 { HLE_Fixup2, b_mode }
 476 #define Evh2 { HLE_Fixup2, v_mode }
 477 #define Ebh3 { HLE_Fixup3, b_mode }
 478 #define Evh3 { HLE_Fixup3, v_mode }
 479
 480 #define BND { BND_Fixup, 0 }
 481
 482 #define cond_jump_flag { NULL, cond_jump_mode }
 483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 484
 485 /* bits in sizeflag */
 486 #define SUFFIX_ALWAYS 4
 487 #define AFLAG 2
 488 #define DFLAG 1
 489
 490 enum
 491 {
 492   /* byte operand */
 493   b_mode = 1,
 494   /* byte operand with operand swapped */
 495   b_swap_mode,
 496   /* byte operand, sign extend like 'T' suffix */
 497   b_T_mode,
 498   /* operand size depends on prefixes */
 499   v_mode,
 500   /* operand size depends on prefixes with operand swapped */
 501   v_swap_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   v_bnd_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   dqw_swap_mode,
 565   bnd_mode,
 566   /* 4- or 6-byte pointer operand */
 567   f_mode,
 568   const_1_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like d_mode, ignore vector length.  */
 604   d_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_mode, ignore vector length.  */
 608   q_scalar_mode,
 609   /* like q_swap_mode, ignore vector length.  */
 610   q_scalar_swap_mode,
 611   /* like vex_mode, ignore vector length.  */
 612   vex_scalar_mode,
 613   /* like vex_w_dq_mode, ignore vector length.  */
 614   vex_scalar_w_dq_mode,
 615
 616   /* Static rounding.  */
 617   evex_rounding_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE
 688 };
 689
 690 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 691
 692 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 693 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 694 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 695 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 696 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 697 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 698 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 699 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 700 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 701 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 702 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 703 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 704 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 705 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 706 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 707
 708 enum
 709 {
 710   REG_80 = 0,
 711   REG_81,
 712   REG_82,
 713   REG_8F,
 714   REG_C0,
 715   REG_C1,
 716   REG_C6,
 717   REG_C7,
 718   REG_D0,
 719   REG_D1,
 720   REG_D2,
 721   REG_D3,
 722   REG_F6,
 723   REG_F7,
 724   REG_FE,
 725   REG_FF,
 726   REG_0F00,
 727   REG_0F01,
 728   REG_0F0D,
 729   REG_0F18,
 730   REG_0F71,
 731   REG_0F72,
 732   REG_0F73,
 733   REG_0FA6,
 734   REG_0FA7,
 735   REG_0FAE,
 736   REG_0FBA,
 737   REG_0FC7,
 738   REG_VEX_0F71,
 739   REG_VEX_0F72,
 740   REG_VEX_0F73,
 741   REG_VEX_0FAE,
 742   REG_VEX_0F38F3,
 743   REG_XOP_LWPCB,
 744   REG_XOP_LWP,
 745   REG_XOP_TBM_01,
 746   REG_XOP_TBM_02,
 747
 748   REG_EVEX_0F71,
 749   REG_EVEX_0F72,
 750   REG_EVEX_0F73,
 751   REG_EVEX_0F38C6,
 752   REG_EVEX_0F38C7
 753 };
 754
 755 enum
 756 {
 757   MOD_8D = 0,
 758   MOD_C6_REG_7,
 759   MOD_C7_REG_7,
 760   MOD_FF_REG_3,
 761   MOD_FF_REG_5,
 762   MOD_0F01_REG_0,
 763   MOD_0F01_REG_1,
 764   MOD_0F01_REG_2,
 765   MOD_0F01_REG_3,
 766   MOD_0F01_REG_7,
 767   MOD_0F12_PREFIX_0,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F24,
 783   MOD_0F26,
 784   MOD_0F2B_PREFIX_0,
 785   MOD_0F2B_PREFIX_1,
 786   MOD_0F2B_PREFIX_2,
 787   MOD_0F2B_PREFIX_3,
 788   MOD_0F51,
 789   MOD_0F71_REG_2,
 790   MOD_0F71_REG_4,
 791   MOD_0F71_REG_6,
 792   MOD_0F72_REG_2,
 793   MOD_0F72_REG_4,
 794   MOD_0F72_REG_6,
 795   MOD_0F73_REG_2,
 796   MOD_0F73_REG_3,
 797   MOD_0F73_REG_6,
 798   MOD_0F73_REG_7,
 799   MOD_0FAE_REG_0,
 800   MOD_0FAE_REG_1,
 801   MOD_0FAE_REG_2,
 802   MOD_0FAE_REG_3,
 803   MOD_0FAE_REG_4,
 804   MOD_0FAE_REG_5,
 805   MOD_0FAE_REG_6,
 806   MOD_0FAE_REG_7,
 807   MOD_0FB2,
 808   MOD_0FB4,
 809   MOD_0FB5,
 810   MOD_0FC7_REG_3,
 811   MOD_0FC7_REG_4,
 812   MOD_0FC7_REG_5,
 813   MOD_0FC7_REG_6,
 814   MOD_0FC7_REG_7,
 815   MOD_0FD7,
 816   MOD_0FE7_PREFIX_2,
 817   MOD_0FF0_PREFIX_3,
 818   MOD_0F382A_PREFIX_2,
 819   MOD_62_32BIT,
 820   MOD_C4_32BIT,
 821   MOD_C5_32BIT,
 822   MOD_VEX_0F12_PREFIX_0,
 823   MOD_VEX_0F13,
 824   MOD_VEX_0F16_PREFIX_0,
 825   MOD_VEX_0F17,
 826   MOD_VEX_0F2B,
 827   MOD_VEX_0F50,
 828   MOD_VEX_0F71_REG_2,
 829   MOD_VEX_0F71_REG_4,
 830   MOD_VEX_0F71_REG_6,
 831   MOD_VEX_0F72_REG_2,
 832   MOD_VEX_0F72_REG_4,
 833   MOD_VEX_0F72_REG_6,
 834   MOD_VEX_0F73_REG_2,
 835   MOD_VEX_0F73_REG_3,
 836   MOD_VEX_0F73_REG_6,
 837   MOD_VEX_0F73_REG_7,
 838   MOD_VEX_0FAE_REG_2,
 839   MOD_VEX_0FAE_REG_3,
 840   MOD_VEX_0FD7_PREFIX_2,
 841   MOD_VEX_0FE7_PREFIX_2,
 842   MOD_VEX_0FF0_PREFIX_3,
 843   MOD_VEX_0F381A_PREFIX_2,
 844   MOD_VEX_0F382A_PREFIX_2,
 845   MOD_VEX_0F382C_PREFIX_2,
 846   MOD_VEX_0F382D_PREFIX_2,
 847   MOD_VEX_0F382E_PREFIX_2,
 848   MOD_VEX_0F382F_PREFIX_2,
 849   MOD_VEX_0F385A_PREFIX_2,
 850   MOD_VEX_0F388C_PREFIX_2,
 851   MOD_VEX_0F388E_PREFIX_2,
 852
 853   MOD_EVEX_0F10_PREFIX_1,
 854   MOD_EVEX_0F10_PREFIX_3,
 855   MOD_EVEX_0F11_PREFIX_1,
 856   MOD_EVEX_0F11_PREFIX_3,
 857   MOD_EVEX_0F12_PREFIX_0,
 858   MOD_EVEX_0F16_PREFIX_0,
 859   MOD_EVEX_0F38C6_REG_1,
 860   MOD_EVEX_0F38C6_REG_2,
 861   MOD_EVEX_0F38C6_REG_5,
 862   MOD_EVEX_0F38C6_REG_6,
 863   MOD_EVEX_0F38C7_REG_1,
 864   MOD_EVEX_0F38C7_REG_2,
 865   MOD_EVEX_0F38C7_REG_5,
 866   MOD_EVEX_0F38C7_REG_6
 867 };
 868
 869 enum
 870 {
 871   RM_C6_REG_7 = 0,
 872   RM_C7_REG_7,
 873   RM_0F01_REG_0,
 874   RM_0F01_REG_1,
 875   RM_0F01_REG_2,
 876   RM_0F01_REG_3,
 877   RM_0F01_REG_7,
 878   RM_0FAE_REG_5,
 879   RM_0FAE_REG_6,
 880   RM_0FAE_REG_7
 881 };
 882
 883 enum
 884 {
 885   PREFIX_90 = 0,
 886   PREFIX_0F10,
 887   PREFIX_0F11,
 888   PREFIX_0F12,
 889   PREFIX_0F16,
 890   PREFIX_0F1A,
 891   PREFIX_0F1B,
 892   PREFIX_0F2A,
 893   PREFIX_0F2B,
 894   PREFIX_0F2C,
 895   PREFIX_0F2D,
 896   PREFIX_0F2E,
 897   PREFIX_0F2F,
 898   PREFIX_0F51,
 899   PREFIX_0F52,
 900   PREFIX_0F53,
 901   PREFIX_0F58,
 902   PREFIX_0F59,
 903   PREFIX_0F5A,
 904   PREFIX_0F5B,
 905   PREFIX_0F5C,
 906   PREFIX_0F5D,
 907   PREFIX_0F5E,
 908   PREFIX_0F5F,
 909   PREFIX_0F60,
 910   PREFIX_0F61,
 911   PREFIX_0F62,
 912   PREFIX_0F6C,
 913   PREFIX_0F6D,
 914   PREFIX_0F6F,
 915   PREFIX_0F70,
 916   PREFIX_0F73_REG_3,
 917   PREFIX_0F73_REG_7,
 918   PREFIX_0F78,
 919   PREFIX_0F79,
 920   PREFIX_0F7C,
 921   PREFIX_0F7D,
 922   PREFIX_0F7E,
 923   PREFIX_0F7F,
 924   PREFIX_0FAE_REG_0,
 925   PREFIX_0FAE_REG_1,
 926   PREFIX_0FAE_REG_2,
 927   PREFIX_0FAE_REG_3,
 928   PREFIX_0FAE_REG_6,
 929   PREFIX_0FAE_REG_7,
 930   PREFIX_RM_0_0FAE_REG_7,
 931   PREFIX_0FB8,
 932   PREFIX_0FBC,
 933   PREFIX_0FBD,
 934   PREFIX_0FC2,
 935   PREFIX_0FC3,
 936   PREFIX_MOD_0_0FC7_REG_6,
 937   PREFIX_MOD_3_0FC7_REG_6,
 938   PREFIX_MOD_3_0FC7_REG_7,
 939   PREFIX_0FD0,
 940   PREFIX_0FD6,
 941   PREFIX_0FE6,
 942   PREFIX_0FE7,
 943   PREFIX_0FF0,
 944   PREFIX_0FF7,
 945   PREFIX_0F3810,
 946   PREFIX_0F3814,
 947   PREFIX_0F3815,
 948   PREFIX_0F3817,
 949   PREFIX_0F3820,
 950   PREFIX_0F3821,
 951   PREFIX_0F3822,
 952   PREFIX_0F3823,
 953   PREFIX_0F3824,
 954   PREFIX_0F3825,
 955   PREFIX_0F3828,
 956   PREFIX_0F3829,
 957   PREFIX_0F382A,
 958   PREFIX_0F382B,
 959   PREFIX_0F3830,
 960   PREFIX_0F3831,
 961   PREFIX_0F3832,
 962   PREFIX_0F3833,
 963   PREFIX_0F3834,
 964   PREFIX_0F3835,
 965   PREFIX_0F3837,
 966   PREFIX_0F3838,
 967   PREFIX_0F3839,
 968   PREFIX_0F383A,
 969   PREFIX_0F383B,
 970   PREFIX_0F383C,
 971   PREFIX_0F383D,
 972   PREFIX_0F383E,
 973   PREFIX_0F383F,
 974   PREFIX_0F3840,
 975   PREFIX_0F3841,
 976   PREFIX_0F3880,
 977   PREFIX_0F3881,
 978   PREFIX_0F3882,
 979   PREFIX_0F38C8,
 980   PREFIX_0F38C9,
 981   PREFIX_0F38CA,
 982   PREFIX_0F38CB,
 983   PREFIX_0F38CC,
 984   PREFIX_0F38CD,
 985   PREFIX_0F38DB,
 986   PREFIX_0F38DC,
 987   PREFIX_0F38DD,
 988   PREFIX_0F38DE,
 989   PREFIX_0F38DF,
 990   PREFIX_0F38F0,
 991   PREFIX_0F38F1,
 992   PREFIX_0F38F6,
 993   PREFIX_0F3A08,
 994   PREFIX_0F3A09,
 995   PREFIX_0F3A0A,
 996   PREFIX_0F3A0B,
 997   PREFIX_0F3A0C,
 998   PREFIX_0F3A0D,
 999   PREFIX_0F3A0E,
1000   PREFIX_0F3A14,
1001   PREFIX_0F3A15,
1002   PREFIX_0F3A16,
1003   PREFIX_0F3A17,
1004   PREFIX_0F3A20,
1005   PREFIX_0F3A21,
1006   PREFIX_0F3A22,
1007   PREFIX_0F3A40,
1008   PREFIX_0F3A41,
1009   PREFIX_0F3A42,
1010   PREFIX_0F3A44,
1011   PREFIX_0F3A60,
1012   PREFIX_0F3A61,
1013   PREFIX_0F3A62,
1014   PREFIX_0F3A63,
1015   PREFIX_0F3ACC,
1016   PREFIX_0F3ADF,
1017   PREFIX_VEX_0F10,
1018   PREFIX_VEX_0F11,
1019   PREFIX_VEX_0F12,
1020   PREFIX_VEX_0F16,
1021   PREFIX_VEX_0F2A,
1022   PREFIX_VEX_0F2C,
1023   PREFIX_VEX_0F2D,
1024   PREFIX_VEX_0F2E,
1025   PREFIX_VEX_0F2F,
1026   PREFIX_VEX_0F41,
1027   PREFIX_VEX_0F42,
1028   PREFIX_VEX_0F44,
1029   PREFIX_VEX_0F45,
1030   PREFIX_VEX_0F46,
1031   PREFIX_VEX_0F47,
1032   PREFIX_VEX_0F4A,
1033   PREFIX_VEX_0F4B,
1034   PREFIX_VEX_0F51,
1035   PREFIX_VEX_0F52,
1036   PREFIX_VEX_0F53,
1037   PREFIX_VEX_0F58,
1038   PREFIX_VEX_0F59,
1039   PREFIX_VEX_0F5A,
1040   PREFIX_VEX_0F5B,
1041   PREFIX_VEX_0F5C,
1042   PREFIX_VEX_0F5D,
1043   PREFIX_VEX_0F5E,
1044   PREFIX_VEX_0F5F,
1045   PREFIX_VEX_0F60,
1046   PREFIX_VEX_0F61,
1047   PREFIX_VEX_0F62,
1048   PREFIX_VEX_0F63,
1049   PREFIX_VEX_0F64,
1050   PREFIX_VEX_0F65,
1051   PREFIX_VEX_0F66,
1052   PREFIX_VEX_0F67,
1053   PREFIX_VEX_0F68,
1054   PREFIX_VEX_0F69,
1055   PREFIX_VEX_0F6A,
1056   PREFIX_VEX_0F6B,
1057   PREFIX_VEX_0F6C,
1058   PREFIX_VEX_0F6D,
1059   PREFIX_VEX_0F6E,
1060   PREFIX_VEX_0F6F,
1061   PREFIX_VEX_0F70,
1062   PREFIX_VEX_0F71_REG_2,
1063   PREFIX_VEX_0F71_REG_4,
1064   PREFIX_VEX_0F71_REG_6,
1065   PREFIX_VEX_0F72_REG_2,
1066   PREFIX_VEX_0F72_REG_4,
1067   PREFIX_VEX_0F72_REG_6,
1068   PREFIX_VEX_0F73_REG_2,
1069   PREFIX_VEX_0F73_REG_3,
1070   PREFIX_VEX_0F73_REG_6,
1071   PREFIX_VEX_0F73_REG_7,
1072   PREFIX_VEX_0F74,
1073   PREFIX_VEX_0F75,
1074   PREFIX_VEX_0F76,
1075   PREFIX_VEX_0F77,
1076   PREFIX_VEX_0F7C,
1077   PREFIX_VEX_0F7D,
1078   PREFIX_VEX_0F7E,
1079   PREFIX_VEX_0F7F,
1080   PREFIX_VEX_0F90,
1081   PREFIX_VEX_0F91,
1082   PREFIX_VEX_0F92,
1083   PREFIX_VEX_0F93,
1084   PREFIX_VEX_0F98,
1085   PREFIX_VEX_0F99,
1086   PREFIX_VEX_0FC2,
1087   PREFIX_VEX_0FC4,
1088   PREFIX_VEX_0FC5,
1089   PREFIX_VEX_0FD0,
1090   PREFIX_VEX_0FD1,
1091   PREFIX_VEX_0FD2,
1092   PREFIX_VEX_0FD3,
1093   PREFIX_VEX_0FD4,
1094   PREFIX_VEX_0FD5,
1095   PREFIX_VEX_0FD6,
1096   PREFIX_VEX_0FD7,
1097   PREFIX_VEX_0FD8,
1098   PREFIX_VEX_0FD9,
1099   PREFIX_VEX_0FDA,
1100   PREFIX_VEX_0FDB,
1101   PREFIX_VEX_0FDC,
1102   PREFIX_VEX_0FDD,
1103   PREFIX_VEX_0FDE,
1104   PREFIX_VEX_0FDF,
1105   PREFIX_VEX_0FE0,
1106   PREFIX_VEX_0FE1,
1107   PREFIX_VEX_0FE2,
1108   PREFIX_VEX_0FE3,
1109   PREFIX_VEX_0FE4,
1110   PREFIX_VEX_0FE5,
1111   PREFIX_VEX_0FE6,
1112   PREFIX_VEX_0FE7,
1113   PREFIX_VEX_0FE8,
1114   PREFIX_VEX_0FE9,
1115   PREFIX_VEX_0FEA,
1116   PREFIX_VEX_0FEB,
1117   PREFIX_VEX_0FEC,
1118   PREFIX_VEX_0FED,
1119   PREFIX_VEX_0FEE,
1120   PREFIX_VEX_0FEF,
1121   PREFIX_VEX_0FF0,
1122   PREFIX_VEX_0FF1,
1123   PREFIX_VEX_0FF2,
1124   PREFIX_VEX_0FF3,
1125   PREFIX_VEX_0FF4,
1126   PREFIX_VEX_0FF5,
1127   PREFIX_VEX_0FF6,
1128   PREFIX_VEX_0FF7,
1129   PREFIX_VEX_0FF8,
1130   PREFIX_VEX_0FF9,
1131   PREFIX_VEX_0FFA,
1132   PREFIX_VEX_0FFB,
1133   PREFIX_VEX_0FFC,
1134   PREFIX_VEX_0FFD,
1135   PREFIX_VEX_0FFE,
1136   PREFIX_VEX_0F3800,
1137   PREFIX_VEX_0F3801,
1138   PREFIX_VEX_0F3802,
1139   PREFIX_VEX_0F3803,
1140   PREFIX_VEX_0F3804,
1141   PREFIX_VEX_0F3805,
1142   PREFIX_VEX_0F3806,
1143   PREFIX_VEX_0F3807,
1144   PREFIX_VEX_0F3808,
1145   PREFIX_VEX_0F3809,
1146   PREFIX_VEX_0F380A,
1147   PREFIX_VEX_0F380B,
1148   PREFIX_VEX_0F380C,
1149   PREFIX_VEX_0F380D,
1150   PREFIX_VEX_0F380E,
1151   PREFIX_VEX_0F380F,
1152   PREFIX_VEX_0F3813,
1153   PREFIX_VEX_0F3816,
1154   PREFIX_VEX_0F3817,
1155   PREFIX_VEX_0F3818,
1156   PREFIX_VEX_0F3819,
1157   PREFIX_VEX_0F381A,
1158   PREFIX_VEX_0F381C,
1159   PREFIX_VEX_0F381D,
1160   PREFIX_VEX_0F381E,
1161   PREFIX_VEX_0F3820,
1162   PREFIX_VEX_0F3821,
1163   PREFIX_VEX_0F3822,
1164   PREFIX_VEX_0F3823,
1165   PREFIX_VEX_0F3824,
1166   PREFIX_VEX_0F3825,
1167   PREFIX_VEX_0F3828,
1168   PREFIX_VEX_0F3829,
1169   PREFIX_VEX_0F382A,
1170   PREFIX_VEX_0F382B,
1171   PREFIX_VEX_0F382C,
1172   PREFIX_VEX_0F382D,
1173   PREFIX_VEX_0F382E,
1174   PREFIX_VEX_0F382F,
1175   PREFIX_VEX_0F3830,
1176   PREFIX_VEX_0F3831,
1177   PREFIX_VEX_0F3832,
1178   PREFIX_VEX_0F3833,
1179   PREFIX_VEX_0F3834,
1180   PREFIX_VEX_0F3835,
1181   PREFIX_VEX_0F3836,
1182   PREFIX_VEX_0F3837,
1183   PREFIX_VEX_0F3838,
1184   PREFIX_VEX_0F3839,
1185   PREFIX_VEX_0F383A,
1186   PREFIX_VEX_0F383B,
1187   PREFIX_VEX_0F383C,
1188   PREFIX_VEX_0F383D,
1189   PREFIX_VEX_0F383E,
1190   PREFIX_VEX_0F383F,
1191   PREFIX_VEX_0F3840,
1192   PREFIX_VEX_0F3841,
1193   PREFIX_VEX_0F3845,
1194   PREFIX_VEX_0F3846,
1195   PREFIX_VEX_0F3847,
1196   PREFIX_VEX_0F3858,
1197   PREFIX_VEX_0F3859,
1198   PREFIX_VEX_0F385A,
1199   PREFIX_VEX_0F3878,
1200   PREFIX_VEX_0F3879,
1201   PREFIX_VEX_0F388C,
1202   PREFIX_VEX_0F388E,
1203   PREFIX_VEX_0F3890,
1204   PREFIX_VEX_0F3891,
1205   PREFIX_VEX_0F3892,
1206   PREFIX_VEX_0F3893,
1207   PREFIX_VEX_0F3896,
1208   PREFIX_VEX_0F3897,
1209   PREFIX_VEX_0F3898,
1210   PREFIX_VEX_0F3899,
1211   PREFIX_VEX_0F389A,
1212   PREFIX_VEX_0F389B,
1213   PREFIX_VEX_0F389C,
1214   PREFIX_VEX_0F389D,
1215   PREFIX_VEX_0F389E,
1216   PREFIX_VEX_0F389F,
1217   PREFIX_VEX_0F38A6,
1218   PREFIX_VEX_0F38A7,
1219   PREFIX_VEX_0F38A8,
1220   PREFIX_VEX_0F38A9,
1221   PREFIX_VEX_0F38AA,
1222   PREFIX_VEX_0F38AB,
1223   PREFIX_VEX_0F38AC,
1224   PREFIX_VEX_0F38AD,
1225   PREFIX_VEX_0F38AE,
1226   PREFIX_VEX_0F38AF,
1227   PREFIX_VEX_0F38B6,
1228   PREFIX_VEX_0F38B7,
1229   PREFIX_VEX_0F38B8,
1230   PREFIX_VEX_0F38B9,
1231   PREFIX_VEX_0F38BA,
1232   PREFIX_VEX_0F38BB,
1233   PREFIX_VEX_0F38BC,
1234   PREFIX_VEX_0F38BD,
1235   PREFIX_VEX_0F38BE,
1236   PREFIX_VEX_0F38BF,
1237   PREFIX_VEX_0F38DB,
1238   PREFIX_VEX_0F38DC,
1239   PREFIX_VEX_0F38DD,
1240   PREFIX_VEX_0F38DE,
1241   PREFIX_VEX_0F38DF,
1242   PREFIX_VEX_0F38F2,
1243   PREFIX_VEX_0F38F3_REG_1,
1244   PREFIX_VEX_0F38F3_REG_2,
1245   PREFIX_VEX_0F38F3_REG_3,
1246   PREFIX_VEX_0F38F5,
1247   PREFIX_VEX_0F38F6,
1248   PREFIX_VEX_0F38F7,
1249   PREFIX_VEX_0F3A00,
1250   PREFIX_VEX_0F3A01,
1251   PREFIX_VEX_0F3A02,
1252   PREFIX_VEX_0F3A04,
1253   PREFIX_VEX_0F3A05,
1254   PREFIX_VEX_0F3A06,
1255   PREFIX_VEX_0F3A08,
1256   PREFIX_VEX_0F3A09,
1257   PREFIX_VEX_0F3A0A,
1258   PREFIX_VEX_0F3A0B,
1259   PREFIX_VEX_0F3A0C,
1260   PREFIX_VEX_0F3A0D,
1261   PREFIX_VEX_0F3A0E,
1262   PREFIX_VEX_0F3A0F,
1263   PREFIX_VEX_0F3A14,
1264   PREFIX_VEX_0F3A15,
1265   PREFIX_VEX_0F3A16,
1266   PREFIX_VEX_0F3A17,
1267   PREFIX_VEX_0F3A18,
1268   PREFIX_VEX_0F3A19,
1269   PREFIX_VEX_0F3A1D,
1270   PREFIX_VEX_0F3A20,
1271   PREFIX_VEX_0F3A21,
1272   PREFIX_VEX_0F3A22,
1273   PREFIX_VEX_0F3A30,
1274   PREFIX_VEX_0F3A31,
1275   PREFIX_VEX_0F3A32,
1276   PREFIX_VEX_0F3A33,
1277   PREFIX_VEX_0F3A38,
1278   PREFIX_VEX_0F3A39,
1279   PREFIX_VEX_0F3A40,
1280   PREFIX_VEX_0F3A41,
1281   PREFIX_VEX_0F3A42,
1282   PREFIX_VEX_0F3A44,
1283   PREFIX_VEX_0F3A46,
1284   PREFIX_VEX_0F3A48,
1285   PREFIX_VEX_0F3A49,
1286   PREFIX_VEX_0F3A4A,
1287   PREFIX_VEX_0F3A4B,
1288   PREFIX_VEX_0F3A4C,
1289   PREFIX_VEX_0F3A5C,
1290   PREFIX_VEX_0F3A5D,
1291   PREFIX_VEX_0F3A5E,
1292   PREFIX_VEX_0F3A5F,
1293   PREFIX_VEX_0F3A60,
1294   PREFIX_VEX_0F3A61,
1295   PREFIX_VEX_0F3A62,
1296   PREFIX_VEX_0F3A63,
1297   PREFIX_VEX_0F3A68,
1298   PREFIX_VEX_0F3A69,
1299   PREFIX_VEX_0F3A6A,
1300   PREFIX_VEX_0F3A6B,
1301   PREFIX_VEX_0F3A6C,
1302   PREFIX_VEX_0F3A6D,
1303   PREFIX_VEX_0F3A6E,
1304   PREFIX_VEX_0F3A6F,
1305   PREFIX_VEX_0F3A78,
1306   PREFIX_VEX_0F3A79,
1307   PREFIX_VEX_0F3A7A,
1308   PREFIX_VEX_0F3A7B,
1309   PREFIX_VEX_0F3A7C,
1310   PREFIX_VEX_0F3A7D,
1311   PREFIX_VEX_0F3A7E,
1312   PREFIX_VEX_0F3A7F,
1313   PREFIX_VEX_0F3ADF,
1314   PREFIX_VEX_0F3AF0,
1315
1316   PREFIX_EVEX_0F10,
1317   PREFIX_EVEX_0F11,
1318   PREFIX_EVEX_0F12,
1319   PREFIX_EVEX_0F13,
1320   PREFIX_EVEX_0F14,
1321   PREFIX_EVEX_0F15,
1322   PREFIX_EVEX_0F16,
1323   PREFIX_EVEX_0F17,
1324   PREFIX_EVEX_0F28,
1325   PREFIX_EVEX_0F29,
1326   PREFIX_EVEX_0F2A,
1327   PREFIX_EVEX_0F2B,
1328   PREFIX_EVEX_0F2C,
1329   PREFIX_EVEX_0F2D,
1330   PREFIX_EVEX_0F2E,
1331   PREFIX_EVEX_0F2F,
1332   PREFIX_EVEX_0F51,
1333   PREFIX_EVEX_0F54,
1334   PREFIX_EVEX_0F55,
1335   PREFIX_EVEX_0F56,
1336   PREFIX_EVEX_0F57,
1337   PREFIX_EVEX_0F58,
1338   PREFIX_EVEX_0F59,
1339   PREFIX_EVEX_0F5A,
1340   PREFIX_EVEX_0F5B,
1341   PREFIX_EVEX_0F5C,
1342   PREFIX_EVEX_0F5D,
1343   PREFIX_EVEX_0F5E,
1344   PREFIX_EVEX_0F5F,
1345   PREFIX_EVEX_0F60,
1346   PREFIX_EVEX_0F61,
1347   PREFIX_EVEX_0F62,
1348   PREFIX_EVEX_0F63,
1349   PREFIX_EVEX_0F64,
1350   PREFIX_EVEX_0F65,
1351   PREFIX_EVEX_0F66,
1352   PREFIX_EVEX_0F67,
1353   PREFIX_EVEX_0F68,
1354   PREFIX_EVEX_0F69,
1355   PREFIX_EVEX_0F6A,
1356   PREFIX_EVEX_0F6B,
1357   PREFIX_EVEX_0F6C,
1358   PREFIX_EVEX_0F6D,
1359   PREFIX_EVEX_0F6E,
1360   PREFIX_EVEX_0F6F,
1361   PREFIX_EVEX_0F70,
1362   PREFIX_EVEX_0F71_REG_2,
1363   PREFIX_EVEX_0F71_REG_4,
1364   PREFIX_EVEX_0F71_REG_6,
1365   PREFIX_EVEX_0F72_REG_0,
1366   PREFIX_EVEX_0F72_REG_1,
1367   PREFIX_EVEX_0F72_REG_2,
1368   PREFIX_EVEX_0F72_REG_4,
1369   PREFIX_EVEX_0F72_REG_6,
1370   PREFIX_EVEX_0F73_REG_2,
1371   PREFIX_EVEX_0F73_REG_3,
1372   PREFIX_EVEX_0F73_REG_6,
1373   PREFIX_EVEX_0F73_REG_7,
1374   PREFIX_EVEX_0F74,
1375   PREFIX_EVEX_0F75,
1376   PREFIX_EVEX_0F76,
1377   PREFIX_EVEX_0F78,
1378   PREFIX_EVEX_0F79,
1379   PREFIX_EVEX_0F7A,
1380   PREFIX_EVEX_0F7B,
1381   PREFIX_EVEX_0F7E,
1382   PREFIX_EVEX_0F7F,
1383   PREFIX_EVEX_0FC2,
1384   PREFIX_EVEX_0FC4,
1385   PREFIX_EVEX_0FC5,
1386   PREFIX_EVEX_0FC6,
1387   PREFIX_EVEX_0FD1,
1388   PREFIX_EVEX_0FD2,
1389   PREFIX_EVEX_0FD3,
1390   PREFIX_EVEX_0FD4,
1391   PREFIX_EVEX_0FD5,
1392   PREFIX_EVEX_0FD6,
1393   PREFIX_EVEX_0FD8,
1394   PREFIX_EVEX_0FD9,
1395   PREFIX_EVEX_0FDA,
1396   PREFIX_EVEX_0FDB,
1397   PREFIX_EVEX_0FDC,
1398   PREFIX_EVEX_0FDD,
1399   PREFIX_EVEX_0FDE,
1400   PREFIX_EVEX_0FDF,
1401   PREFIX_EVEX_0FE0,
1402   PREFIX_EVEX_0FE1,
1403   PREFIX_EVEX_0FE2,
1404   PREFIX_EVEX_0FE3,
1405   PREFIX_EVEX_0FE4,
1406   PREFIX_EVEX_0FE5,
1407   PREFIX_EVEX_0FE6,
1408   PREFIX_EVEX_0FE7,
1409   PREFIX_EVEX_0FE8,
1410   PREFIX_EVEX_0FE9,
1411   PREFIX_EVEX_0FEA,
1412   PREFIX_EVEX_0FEB,
1413   PREFIX_EVEX_0FEC,
1414   PREFIX_EVEX_0FED,
1415   PREFIX_EVEX_0FEE,
1416   PREFIX_EVEX_0FEF,
1417   PREFIX_EVEX_0FF1,
1418   PREFIX_EVEX_0FF2,
1419   PREFIX_EVEX_0FF3,
1420   PREFIX_EVEX_0FF4,
1421   PREFIX_EVEX_0FF5,
1422   PREFIX_EVEX_0FF6,
1423   PREFIX_EVEX_0FF8,
1424   PREFIX_EVEX_0FF9,
1425   PREFIX_EVEX_0FFA,
1426   PREFIX_EVEX_0FFB,
1427   PREFIX_EVEX_0FFC,
1428   PREFIX_EVEX_0FFD,
1429   PREFIX_EVEX_0FFE,
1430   PREFIX_EVEX_0F3800,
1431   PREFIX_EVEX_0F3804,
1432   PREFIX_EVEX_0F380B,
1433   PREFIX_EVEX_0F380C,
1434   PREFIX_EVEX_0F380D,
1435   PREFIX_EVEX_0F3810,
1436   PREFIX_EVEX_0F3811,
1437   PREFIX_EVEX_0F3812,
1438   PREFIX_EVEX_0F3813,
1439   PREFIX_EVEX_0F3814,
1440   PREFIX_EVEX_0F3815,
1441   PREFIX_EVEX_0F3816,
1442   PREFIX_EVEX_0F3818,
1443   PREFIX_EVEX_0F3819,
1444   PREFIX_EVEX_0F381A,
1445   PREFIX_EVEX_0F381B,
1446   PREFIX_EVEX_0F381C,
1447   PREFIX_EVEX_0F381D,
1448   PREFIX_EVEX_0F381E,
1449   PREFIX_EVEX_0F381F,
1450   PREFIX_EVEX_0F3820,
1451   PREFIX_EVEX_0F3821,
1452   PREFIX_EVEX_0F3822,
1453   PREFIX_EVEX_0F3823,
1454   PREFIX_EVEX_0F3824,
1455   PREFIX_EVEX_0F3825,
1456   PREFIX_EVEX_0F3826,
1457   PREFIX_EVEX_0F3827,
1458   PREFIX_EVEX_0F3828,
1459   PREFIX_EVEX_0F3829,
1460   PREFIX_EVEX_0F382A,
1461   PREFIX_EVEX_0F382B,
1462   PREFIX_EVEX_0F382C,
1463   PREFIX_EVEX_0F382D,
1464   PREFIX_EVEX_0F3830,
1465   PREFIX_EVEX_0F3831,
1466   PREFIX_EVEX_0F3832,
1467   PREFIX_EVEX_0F3833,
1468   PREFIX_EVEX_0F3834,
1469   PREFIX_EVEX_0F3835,
1470   PREFIX_EVEX_0F3836,
1471   PREFIX_EVEX_0F3837,
1472   PREFIX_EVEX_0F3838,
1473   PREFIX_EVEX_0F3839,
1474   PREFIX_EVEX_0F383A,
1475   PREFIX_EVEX_0F383B,
1476   PREFIX_EVEX_0F383C,
1477   PREFIX_EVEX_0F383D,
1478   PREFIX_EVEX_0F383E,
1479   PREFIX_EVEX_0F383F,
1480   PREFIX_EVEX_0F3840,
1481   PREFIX_EVEX_0F3842,
1482   PREFIX_EVEX_0F3843,
1483   PREFIX_EVEX_0F3844,
1484   PREFIX_EVEX_0F3845,
1485   PREFIX_EVEX_0F3846,
1486   PREFIX_EVEX_0F3847,
1487   PREFIX_EVEX_0F384C,
1488   PREFIX_EVEX_0F384D,
1489   PREFIX_EVEX_0F384E,
1490   PREFIX_EVEX_0F384F,
1491   PREFIX_EVEX_0F3858,
1492   PREFIX_EVEX_0F3859,
1493   PREFIX_EVEX_0F385A,
1494   PREFIX_EVEX_0F385B,
1495   PREFIX_EVEX_0F3864,
1496   PREFIX_EVEX_0F3865,
1497   PREFIX_EVEX_0F3866,
1498   PREFIX_EVEX_0F3875,
1499   PREFIX_EVEX_0F3876,
1500   PREFIX_EVEX_0F3877,
1501   PREFIX_EVEX_0F3878,
1502   PREFIX_EVEX_0F3879,
1503   PREFIX_EVEX_0F387A,
1504   PREFIX_EVEX_0F387B,
1505   PREFIX_EVEX_0F387C,
1506   PREFIX_EVEX_0F387D,
1507   PREFIX_EVEX_0F387E,
1508   PREFIX_EVEX_0F387F,
1509   PREFIX_EVEX_0F3883,
1510   PREFIX_EVEX_0F3888,
1511   PREFIX_EVEX_0F3889,
1512   PREFIX_EVEX_0F388A,
1513   PREFIX_EVEX_0F388B,
1514   PREFIX_EVEX_0F388D,
1515   PREFIX_EVEX_0F3890,
1516   PREFIX_EVEX_0F3891,
1517   PREFIX_EVEX_0F3892,
1518   PREFIX_EVEX_0F3893,
1519   PREFIX_EVEX_0F3896,
1520   PREFIX_EVEX_0F3897,
1521   PREFIX_EVEX_0F3898,
1522   PREFIX_EVEX_0F3899,
1523   PREFIX_EVEX_0F389A,
1524   PREFIX_EVEX_0F389B,
1525   PREFIX_EVEX_0F389C,
1526   PREFIX_EVEX_0F389D,
1527   PREFIX_EVEX_0F389E,
1528   PREFIX_EVEX_0F389F,
1529   PREFIX_EVEX_0F38A0,
1530   PREFIX_EVEX_0F38A1,
1531   PREFIX_EVEX_0F38A2,
1532   PREFIX_EVEX_0F38A3,
1533   PREFIX_EVEX_0F38A6,
1534   PREFIX_EVEX_0F38A7,
1535   PREFIX_EVEX_0F38A8,
1536   PREFIX_EVEX_0F38A9,
1537   PREFIX_EVEX_0F38AA,
1538   PREFIX_EVEX_0F38AB,
1539   PREFIX_EVEX_0F38AC,
1540   PREFIX_EVEX_0F38AD,
1541   PREFIX_EVEX_0F38AE,
1542   PREFIX_EVEX_0F38AF,
1543   PREFIX_EVEX_0F38B4,
1544   PREFIX_EVEX_0F38B5,
1545   PREFIX_EVEX_0F38B6,
1546   PREFIX_EVEX_0F38B7,
1547   PREFIX_EVEX_0F38B8,
1548   PREFIX_EVEX_0F38B9,
1549   PREFIX_EVEX_0F38BA,
1550   PREFIX_EVEX_0F38BB,
1551   PREFIX_EVEX_0F38BC,
1552   PREFIX_EVEX_0F38BD,
1553   PREFIX_EVEX_0F38BE,
1554   PREFIX_EVEX_0F38BF,
1555   PREFIX_EVEX_0F38C4,
1556   PREFIX_EVEX_0F38C6_REG_1,
1557   PREFIX_EVEX_0F38C6_REG_2,
1558   PREFIX_EVEX_0F38C6_REG_5,
1559   PREFIX_EVEX_0F38C6_REG_6,
1560   PREFIX_EVEX_0F38C7_REG_1,
1561   PREFIX_EVEX_0F38C7_REG_2,
1562   PREFIX_EVEX_0F38C7_REG_5,
1563   PREFIX_EVEX_0F38C7_REG_6,
1564   PREFIX_EVEX_0F38C8,
1565   PREFIX_EVEX_0F38CA,
1566   PREFIX_EVEX_0F38CB,
1567   PREFIX_EVEX_0F38CC,
1568   PREFIX_EVEX_0F38CD,
1569
1570   PREFIX_EVEX_0F3A00,
1571   PREFIX_EVEX_0F3A01,
1572   PREFIX_EVEX_0F3A03,
1573   PREFIX_EVEX_0F3A04,
1574   PREFIX_EVEX_0F3A05,
1575   PREFIX_EVEX_0F3A08,
1576   PREFIX_EVEX_0F3A09,
1577   PREFIX_EVEX_0F3A0A,
1578   PREFIX_EVEX_0F3A0B,
1579   PREFIX_EVEX_0F3A0F,
1580   PREFIX_EVEX_0F3A14,
1581   PREFIX_EVEX_0F3A15,
1582   PREFIX_EVEX_0F3A16,
1583   PREFIX_EVEX_0F3A17,
1584   PREFIX_EVEX_0F3A18,
1585   PREFIX_EVEX_0F3A19,
1586   PREFIX_EVEX_0F3A1A,
1587   PREFIX_EVEX_0F3A1B,
1588   PREFIX_EVEX_0F3A1D,
1589   PREFIX_EVEX_0F3A1E,
1590   PREFIX_EVEX_0F3A1F,
1591   PREFIX_EVEX_0F3A20,
1592   PREFIX_EVEX_0F3A21,
1593   PREFIX_EVEX_0F3A22,
1594   PREFIX_EVEX_0F3A23,
1595   PREFIX_EVEX_0F3A25,
1596   PREFIX_EVEX_0F3A26,
1597   PREFIX_EVEX_0F3A27,
1598   PREFIX_EVEX_0F3A38,
1599   PREFIX_EVEX_0F3A39,
1600   PREFIX_EVEX_0F3A3A,
1601   PREFIX_EVEX_0F3A3B,
1602   PREFIX_EVEX_0F3A3E,
1603   PREFIX_EVEX_0F3A3F,
1604   PREFIX_EVEX_0F3A42,
1605   PREFIX_EVEX_0F3A43,
1606   PREFIX_EVEX_0F3A50,
1607   PREFIX_EVEX_0F3A51,
1608   PREFIX_EVEX_0F3A54,
1609   PREFIX_EVEX_0F3A55,
1610   PREFIX_EVEX_0F3A56,
1611   PREFIX_EVEX_0F3A57,
1612   PREFIX_EVEX_0F3A66,
1613   PREFIX_EVEX_0F3A67
1614 };
1615
1616 enum
1617 {
1618   X86_64_06 = 0,
1619   X86_64_07,
1620   X86_64_0D,
1621   X86_64_16,
1622   X86_64_17,
1623   X86_64_1E,
1624   X86_64_1F,
1625   X86_64_27,
1626   X86_64_2F,
1627   X86_64_37,
1628   X86_64_3F,
1629   X86_64_60,
1630   X86_64_61,
1631   X86_64_62,
1632   X86_64_63,
1633   X86_64_6D,
1634   X86_64_6F,
1635   X86_64_9A,
1636   X86_64_C4,
1637   X86_64_C5,
1638   X86_64_CE,
1639   X86_64_D4,
1640   X86_64_D5,
1641   X86_64_EA,
1642   X86_64_0F01_REG_0,
1643   X86_64_0F01_REG_1,
1644   X86_64_0F01_REG_2,
1645   X86_64_0F01_REG_3
1646 };
1647
1648 enum
1649 {
1650   THREE_BYTE_0F38 = 0,
1651   THREE_BYTE_0F3A,
1652   THREE_BYTE_0F7A
1653 };
1654
1655 enum
1656 {
1657   XOP_08 = 0,
1658   XOP_09,
1659   XOP_0A
1660 };
1661
1662 enum
1663 {
1664   VEX_0F = 0,
1665   VEX_0F38,
1666   VEX_0F3A
1667 };
1668
1669 enum
1670 {
1671   EVEX_0F = 0,
1672   EVEX_0F38,
1673   EVEX_0F3A
1674 };
1675
1676 enum
1677 {
1678   VEX_LEN_0F10_P_1 = 0,
1679   VEX_LEN_0F10_P_3,
1680   VEX_LEN_0F11_P_1,
1681   VEX_LEN_0F11_P_3,
1682   VEX_LEN_0F12_P_0_M_0,
1683   VEX_LEN_0F12_P_0_M_1,
1684   VEX_LEN_0F12_P_2,
1685   VEX_LEN_0F13_M_0,
1686   VEX_LEN_0F16_P_0_M_0,
1687   VEX_LEN_0F16_P_0_M_1,
1688   VEX_LEN_0F16_P_2,
1689   VEX_LEN_0F17_M_0,
1690   VEX_LEN_0F2A_P_1,
1691   VEX_LEN_0F2A_P_3,
1692   VEX_LEN_0F2C_P_1,
1693   VEX_LEN_0F2C_P_3,
1694   VEX_LEN_0F2D_P_1,
1695   VEX_LEN_0F2D_P_3,
1696   VEX_LEN_0F2E_P_0,
1697   VEX_LEN_0F2E_P_2,
1698   VEX_LEN_0F2F_P_0,
1699   VEX_LEN_0F2F_P_2,
1700   VEX_LEN_0F41_P_0,
1701   VEX_LEN_0F41_P_2,
1702   VEX_LEN_0F42_P_0,
1703   VEX_LEN_0F42_P_2,
1704   VEX_LEN_0F44_P_0,
1705   VEX_LEN_0F44_P_2,
1706   VEX_LEN_0F45_P_0,
1707   VEX_LEN_0F45_P_2,
1708   VEX_LEN_0F46_P_0,
1709   VEX_LEN_0F46_P_2,
1710   VEX_LEN_0F47_P_0,
1711   VEX_LEN_0F47_P_2,
1712   VEX_LEN_0F4A_P_0,
1713   VEX_LEN_0F4A_P_2,
1714   VEX_LEN_0F4B_P_0,
1715   VEX_LEN_0F4B_P_2,
1716   VEX_LEN_0F51_P_1,
1717   VEX_LEN_0F51_P_3,
1718   VEX_LEN_0F52_P_1,
1719   VEX_LEN_0F53_P_1,
1720   VEX_LEN_0F58_P_1,
1721   VEX_LEN_0F58_P_3,
1722   VEX_LEN_0F59_P_1,
1723   VEX_LEN_0F59_P_3,
1724   VEX_LEN_0F5A_P_1,
1725   VEX_LEN_0F5A_P_3,
1726   VEX_LEN_0F5C_P_1,
1727   VEX_LEN_0F5C_P_3,
1728   VEX_LEN_0F5D_P_1,
1729   VEX_LEN_0F5D_P_3,
1730   VEX_LEN_0F5E_P_1,
1731   VEX_LEN_0F5E_P_3,
1732   VEX_LEN_0F5F_P_1,
1733   VEX_LEN_0F5F_P_3,
1734   VEX_LEN_0F6E_P_2,
1735   VEX_LEN_0F7E_P_1,
1736   VEX_LEN_0F7E_P_2,
1737   VEX_LEN_0F90_P_0,
1738   VEX_LEN_0F90_P_2,
1739   VEX_LEN_0F91_P_0,
1740   VEX_LEN_0F91_P_2,
1741   VEX_LEN_0F92_P_0,
1742   VEX_LEN_0F92_P_2,
1743   VEX_LEN_0F92_P_3,
1744   VEX_LEN_0F93_P_0,
1745   VEX_LEN_0F93_P_2,
1746   VEX_LEN_0F93_P_3,
1747   VEX_LEN_0F98_P_0,
1748   VEX_LEN_0F98_P_2,
1749   VEX_LEN_0F99_P_0,
1750   VEX_LEN_0F99_P_2,
1751   VEX_LEN_0FAE_R_2_M_0,
1752   VEX_LEN_0FAE_R_3_M_0,
1753   VEX_LEN_0FC2_P_1,
1754   VEX_LEN_0FC2_P_3,
1755   VEX_LEN_0FC4_P_2,
1756   VEX_LEN_0FC5_P_2,
1757   VEX_LEN_0FD6_P_2,
1758   VEX_LEN_0FF7_P_2,
1759   VEX_LEN_0F3816_P_2,
1760   VEX_LEN_0F3819_P_2,
1761   VEX_LEN_0F381A_P_2_M_0,
1762   VEX_LEN_0F3836_P_2,
1763   VEX_LEN_0F3841_P_2,
1764   VEX_LEN_0F385A_P_2_M_0,
1765   VEX_LEN_0F38DB_P_2,
1766   VEX_LEN_0F38DC_P_2,
1767   VEX_LEN_0F38DD_P_2,
1768   VEX_LEN_0F38DE_P_2,
1769   VEX_LEN_0F38DF_P_2,
1770   VEX_LEN_0F38F2_P_0,
1771   VEX_LEN_0F38F3_R_1_P_0,
1772   VEX_LEN_0F38F3_R_2_P_0,
1773   VEX_LEN_0F38F3_R_3_P_0,
1774   VEX_LEN_0F38F5_P_0,
1775   VEX_LEN_0F38F5_P_1,
1776   VEX_LEN_0F38F5_P_3,
1777   VEX_LEN_0F38F6_P_3,
1778   VEX_LEN_0F38F7_P_0,
1779   VEX_LEN_0F38F7_P_1,
1780   VEX_LEN_0F38F7_P_2,
1781   VEX_LEN_0F38F7_P_3,
1782   VEX_LEN_0F3A00_P_2,
1783   VEX_LEN_0F3A01_P_2,
1784   VEX_LEN_0F3A06_P_2,
1785   VEX_LEN_0F3A0A_P_2,
1786   VEX_LEN_0F3A0B_P_2,
1787   VEX_LEN_0F3A14_P_2,
1788   VEX_LEN_0F3A15_P_2,
1789   VEX_LEN_0F3A16_P_2,
1790   VEX_LEN_0F3A17_P_2,
1791   VEX_LEN_0F3A18_P_2,
1792   VEX_LEN_0F3A19_P_2,
1793   VEX_LEN_0F3A20_P_2,
1794   VEX_LEN_0F3A21_P_2,
1795   VEX_LEN_0F3A22_P_2,
1796   VEX_LEN_0F3A30_P_2,
1797   VEX_LEN_0F3A31_P_2,
1798   VEX_LEN_0F3A32_P_2,
1799   VEX_LEN_0F3A33_P_2,
1800   VEX_LEN_0F3A38_P_2,
1801   VEX_LEN_0F3A39_P_2,
1802   VEX_LEN_0F3A41_P_2,
1803   VEX_LEN_0F3A44_P_2,
1804   VEX_LEN_0F3A46_P_2,
1805   VEX_LEN_0F3A60_P_2,
1806   VEX_LEN_0F3A61_P_2,
1807   VEX_LEN_0F3A62_P_2,
1808   VEX_LEN_0F3A63_P_2,
1809   VEX_LEN_0F3A6A_P_2,
1810   VEX_LEN_0F3A6B_P_2,
1811   VEX_LEN_0F3A6E_P_2,
1812   VEX_LEN_0F3A6F_P_2,
1813   VEX_LEN_0F3A7A_P_2,
1814   VEX_LEN_0F3A7B_P_2,
1815   VEX_LEN_0F3A7E_P_2,
1816   VEX_LEN_0F3A7F_P_2,
1817   VEX_LEN_0F3ADF_P_2,
1818   VEX_LEN_0F3AF0_P_3,
1819   VEX_LEN_0FXOP_08_CC,
1820   VEX_LEN_0FXOP_08_CD,
1821   VEX_LEN_0FXOP_08_CE,
1822   VEX_LEN_0FXOP_08_CF,
1823   VEX_LEN_0FXOP_08_EC,
1824   VEX_LEN_0FXOP_08_ED,
1825   VEX_LEN_0FXOP_08_EE,
1826   VEX_LEN_0FXOP_08_EF,
1827   VEX_LEN_0FXOP_09_80,
1828   VEX_LEN_0FXOP_09_81
1829 };
1830
1831 enum
1832 {
1833   VEX_W_0F10_P_0 = 0,
1834   VEX_W_0F10_P_1,
1835   VEX_W_0F10_P_2,
1836   VEX_W_0F10_P_3,
1837   VEX_W_0F11_P_0,
1838   VEX_W_0F11_P_1,
1839   VEX_W_0F11_P_2,
1840   VEX_W_0F11_P_3,
1841   VEX_W_0F12_P_0_M_0,
1842   VEX_W_0F12_P_0_M_1,
1843   VEX_W_0F12_P_1,
1844   VEX_W_0F12_P_2,
1845   VEX_W_0F12_P_3,
1846   VEX_W_0F13_M_0,
1847   VEX_W_0F14,
1848   VEX_W_0F15,
1849   VEX_W_0F16_P_0_M_0,
1850   VEX_W_0F16_P_0_M_1,
1851   VEX_W_0F16_P_1,
1852   VEX_W_0F16_P_2,
1853   VEX_W_0F17_M_0,
1854   VEX_W_0F28,
1855   VEX_W_0F29,
1856   VEX_W_0F2B_M_0,
1857   VEX_W_0F2E_P_0,
1858   VEX_W_0F2E_P_2,
1859   VEX_W_0F2F_P_0,
1860   VEX_W_0F2F_P_2,
1861   VEX_W_0F41_P_0_LEN_1,
1862   VEX_W_0F41_P_2_LEN_1,
1863   VEX_W_0F42_P_0_LEN_1,
1864   VEX_W_0F42_P_2_LEN_1,
1865   VEX_W_0F44_P_0_LEN_0,
1866   VEX_W_0F44_P_2_LEN_0,
1867   VEX_W_0F45_P_0_LEN_1,
1868   VEX_W_0F45_P_2_LEN_1,
1869   VEX_W_0F46_P_0_LEN_1,
1870   VEX_W_0F46_P_2_LEN_1,
1871   VEX_W_0F47_P_0_LEN_1,
1872   VEX_W_0F47_P_2_LEN_1,
1873   VEX_W_0F4A_P_0_LEN_1,
1874   VEX_W_0F4A_P_2_LEN_1,
1875   VEX_W_0F4B_P_0_LEN_1,
1876   VEX_W_0F4B_P_2_LEN_1,
1877   VEX_W_0F50_M_0,
1878   VEX_W_0F51_P_0,
1879   VEX_W_0F51_P_1,
1880   VEX_W_0F51_P_2,
1881   VEX_W_0F51_P_3,
1882   VEX_W_0F52_P_0,
1883   VEX_W_0F52_P_1,
1884   VEX_W_0F53_P_0,
1885   VEX_W_0F53_P_1,
1886   VEX_W_0F58_P_0,
1887   VEX_W_0F58_P_1,
1888   VEX_W_0F58_P_2,
1889   VEX_W_0F58_P_3,
1890   VEX_W_0F59_P_0,
1891   VEX_W_0F59_P_1,
1892   VEX_W_0F59_P_2,
1893   VEX_W_0F59_P_3,
1894   VEX_W_0F5A_P_0,
1895   VEX_W_0F5A_P_1,
1896   VEX_W_0F5A_P_3,
1897   VEX_W_0F5B_P_0,
1898   VEX_W_0F5B_P_1,
1899   VEX_W_0F5B_P_2,
1900   VEX_W_0F5C_P_0,
1901   VEX_W_0F5C_P_1,
1902   VEX_W_0F5C_P_2,
1903   VEX_W_0F5C_P_3,
1904   VEX_W_0F5D_P_0,
1905   VEX_W_0F5D_P_1,
1906   VEX_W_0F5D_P_2,
1907   VEX_W_0F5D_P_3,
1908   VEX_W_0F5E_P_0,
1909   VEX_W_0F5E_P_1,
1910   VEX_W_0F5E_P_2,
1911   VEX_W_0F5E_P_3,
1912   VEX_W_0F5F_P_0,
1913   VEX_W_0F5F_P_1,
1914   VEX_W_0F5F_P_2,
1915   VEX_W_0F5F_P_3,
1916   VEX_W_0F60_P_2,
1917   VEX_W_0F61_P_2,
1918   VEX_W_0F62_P_2,
1919   VEX_W_0F63_P_2,
1920   VEX_W_0F64_P_2,
1921   VEX_W_0F65_P_2,
1922   VEX_W_0F66_P_2,
1923   VEX_W_0F67_P_2,
1924   VEX_W_0F68_P_2,
1925   VEX_W_0F69_P_2,
1926   VEX_W_0F6A_P_2,
1927   VEX_W_0F6B_P_2,
1928   VEX_W_0F6C_P_2,
1929   VEX_W_0F6D_P_2,
1930   VEX_W_0F6F_P_1,
1931   VEX_W_0F6F_P_2,
1932   VEX_W_0F70_P_1,
1933   VEX_W_0F70_P_2,
1934   VEX_W_0F70_P_3,
1935   VEX_W_0F71_R_2_P_2,
1936   VEX_W_0F71_R_4_P_2,
1937   VEX_W_0F71_R_6_P_2,
1938   VEX_W_0F72_R_2_P_2,
1939   VEX_W_0F72_R_4_P_2,
1940   VEX_W_0F72_R_6_P_2,
1941   VEX_W_0F73_R_2_P_2,
1942   VEX_W_0F73_R_3_P_2,
1943   VEX_W_0F73_R_6_P_2,
1944   VEX_W_0F73_R_7_P_2,
1945   VEX_W_0F74_P_2,
1946   VEX_W_0F75_P_2,
1947   VEX_W_0F76_P_2,
1948   VEX_W_0F77_P_0,
1949   VEX_W_0F7C_P_2,
1950   VEX_W_0F7C_P_3,
1951   VEX_W_0F7D_P_2,
1952   VEX_W_0F7D_P_3,
1953   VEX_W_0F7E_P_1,
1954   VEX_W_0F7F_P_1,
1955   VEX_W_0F7F_P_2,
1956   VEX_W_0F90_P_0_LEN_0,
1957   VEX_W_0F90_P_2_LEN_0,
1958   VEX_W_0F91_P_0_LEN_0,
1959   VEX_W_0F91_P_2_LEN_0,
1960   VEX_W_0F92_P_0_LEN_0,
1961   VEX_W_0F92_P_2_LEN_0,
1962   VEX_W_0F92_P_3_LEN_0,
1963   VEX_W_0F93_P_0_LEN_0,
1964   VEX_W_0F93_P_2_LEN_0,
1965   VEX_W_0F93_P_3_LEN_0,
1966   VEX_W_0F98_P_0_LEN_0,
1967   VEX_W_0F98_P_2_LEN_0,
1968   VEX_W_0F99_P_0_LEN_0,
1969   VEX_W_0F99_P_2_LEN_0,
1970   VEX_W_0FAE_R_2_M_0,
1971   VEX_W_0FAE_R_3_M_0,
1972   VEX_W_0FC2_P_0,
1973   VEX_W_0FC2_P_1,
1974   VEX_W_0FC2_P_2,
1975   VEX_W_0FC2_P_3,
1976   VEX_W_0FC4_P_2,
1977   VEX_W_0FC5_P_2,
1978   VEX_W_0FD0_P_2,
1979   VEX_W_0FD0_P_3,
1980   VEX_W_0FD1_P_2,
1981   VEX_W_0FD2_P_2,
1982   VEX_W_0FD3_P_2,
1983   VEX_W_0FD4_P_2,
1984   VEX_W_0FD5_P_2,
1985   VEX_W_0FD6_P_2,
1986   VEX_W_0FD7_P_2_M_1,
1987   VEX_W_0FD8_P_2,
1988   VEX_W_0FD9_P_2,
1989   VEX_W_0FDA_P_2,
1990   VEX_W_0FDB_P_2,
1991   VEX_W_0FDC_P_2,
1992   VEX_W_0FDD_P_2,
1993   VEX_W_0FDE_P_2,
1994   VEX_W_0FDF_P_2,
1995   VEX_W_0FE0_P_2,
1996   VEX_W_0FE1_P_2,
1997   VEX_W_0FE2_P_2,
1998   VEX_W_0FE3_P_2,
1999   VEX_W_0FE4_P_2,
2000   VEX_W_0FE5_P_2,
2001   VEX_W_0FE6_P_1,
2002   VEX_W_0FE6_P_2,
2003   VEX_W_0FE6_P_3,
2004   VEX_W_0FE7_P_2_M_0,
2005   VEX_W_0FE8_P_2,
2006   VEX_W_0FE9_P_2,
2007   VEX_W_0FEA_P_2,
2008   VEX_W_0FEB_P_2,
2009   VEX_W_0FEC_P_2,
2010   VEX_W_0FED_P_2,
2011   VEX_W_0FEE_P_2,
2012   VEX_W_0FEF_P_2,
2013   VEX_W_0FF0_P_3_M_0,
2014   VEX_W_0FF1_P_2,
2015   VEX_W_0FF2_P_2,
2016   VEX_W_0FF3_P_2,
2017   VEX_W_0FF4_P_2,
2018   VEX_W_0FF5_P_2,
2019   VEX_W_0FF6_P_2,
2020   VEX_W_0FF7_P_2,
2021   VEX_W_0FF8_P_2,
2022   VEX_W_0FF9_P_2,
2023   VEX_W_0FFA_P_2,
2024   VEX_W_0FFB_P_2,
2025   VEX_W_0FFC_P_2,
2026   VEX_W_0FFD_P_2,
2027   VEX_W_0FFE_P_2,
2028   VEX_W_0F3800_P_2,
2029   VEX_W_0F3801_P_2,
2030   VEX_W_0F3802_P_2,
2031   VEX_W_0F3803_P_2,
2032   VEX_W_0F3804_P_2,
2033   VEX_W_0F3805_P_2,
2034   VEX_W_0F3806_P_2,
2035   VEX_W_0F3807_P_2,
2036   VEX_W_0F3808_P_2,
2037   VEX_W_0F3809_P_2,
2038   VEX_W_0F380A_P_2,
2039   VEX_W_0F380B_P_2,
2040   VEX_W_0F380C_P_2,
2041   VEX_W_0F380D_P_2,
2042   VEX_W_0F380E_P_2,
2043   VEX_W_0F380F_P_2,
2044   VEX_W_0F3816_P_2,
2045   VEX_W_0F3817_P_2,
2046   VEX_W_0F3818_P_2,
2047   VEX_W_0F3819_P_2,
2048   VEX_W_0F381A_P_2_M_0,
2049   VEX_W_0F381C_P_2,
2050   VEX_W_0F381D_P_2,
2051   VEX_W_0F381E_P_2,
2052   VEX_W_0F3820_P_2,
2053   VEX_W_0F3821_P_2,
2054   VEX_W_0F3822_P_2,
2055   VEX_W_0F3823_P_2,
2056   VEX_W_0F3824_P_2,
2057   VEX_W_0F3825_P_2,
2058   VEX_W_0F3828_P_2,
2059   VEX_W_0F3829_P_2,
2060   VEX_W_0F382A_P_2_M_0,
2061   VEX_W_0F382B_P_2,
2062   VEX_W_0F382C_P_2_M_0,
2063   VEX_W_0F382D_P_2_M_0,
2064   VEX_W_0F382E_P_2_M_0,
2065   VEX_W_0F382F_P_2_M_0,
2066   VEX_W_0F3830_P_2,
2067   VEX_W_0F3831_P_2,
2068   VEX_W_0F3832_P_2,
2069   VEX_W_0F3833_P_2,
2070   VEX_W_0F3834_P_2,
2071   VEX_W_0F3835_P_2,
2072   VEX_W_0F3836_P_2,
2073   VEX_W_0F3837_P_2,
2074   VEX_W_0F3838_P_2,
2075   VEX_W_0F3839_P_2,
2076   VEX_W_0F383A_P_2,
2077   VEX_W_0F383B_P_2,
2078   VEX_W_0F383C_P_2,
2079   VEX_W_0F383D_P_2,
2080   VEX_W_0F383E_P_2,
2081   VEX_W_0F383F_P_2,
2082   VEX_W_0F3840_P_2,
2083   VEX_W_0F3841_P_2,
2084   VEX_W_0F3846_P_2,
2085   VEX_W_0F3858_P_2,
2086   VEX_W_0F3859_P_2,
2087   VEX_W_0F385A_P_2_M_0,
2088   VEX_W_0F3878_P_2,
2089   VEX_W_0F3879_P_2,
2090   VEX_W_0F38DB_P_2,
2091   VEX_W_0F38DC_P_2,
2092   VEX_W_0F38DD_P_2,
2093   VEX_W_0F38DE_P_2,
2094   VEX_W_0F38DF_P_2,
2095   VEX_W_0F3A00_P_2,
2096   VEX_W_0F3A01_P_2,
2097   VEX_W_0F3A02_P_2,
2098   VEX_W_0F3A04_P_2,
2099   VEX_W_0F3A05_P_2,
2100   VEX_W_0F3A06_P_2,
2101   VEX_W_0F3A08_P_2,
2102   VEX_W_0F3A09_P_2,
2103   VEX_W_0F3A0A_P_2,
2104   VEX_W_0F3A0B_P_2,
2105   VEX_W_0F3A0C_P_2,
2106   VEX_W_0F3A0D_P_2,
2107   VEX_W_0F3A0E_P_2,
2108   VEX_W_0F3A0F_P_2,
2109   VEX_W_0F3A14_P_2,
2110   VEX_W_0F3A15_P_2,
2111   VEX_W_0F3A18_P_2,
2112   VEX_W_0F3A19_P_2,
2113   VEX_W_0F3A20_P_2,
2114   VEX_W_0F3A21_P_2,
2115   VEX_W_0F3A30_P_2_LEN_0,
2116   VEX_W_0F3A31_P_2_LEN_0,
2117   VEX_W_0F3A32_P_2_LEN_0,
2118   VEX_W_0F3A33_P_2_LEN_0,
2119   VEX_W_0F3A38_P_2,
2120   VEX_W_0F3A39_P_2,
2121   VEX_W_0F3A40_P_2,
2122   VEX_W_0F3A41_P_2,
2123   VEX_W_0F3A42_P_2,
2124   VEX_W_0F3A44_P_2,
2125   VEX_W_0F3A46_P_2,
2126   VEX_W_0F3A48_P_2,
2127   VEX_W_0F3A49_P_2,
2128   VEX_W_0F3A4A_P_2,
2129   VEX_W_0F3A4B_P_2,
2130   VEX_W_0F3A4C_P_2,
2131   VEX_W_0F3A60_P_2,
2132   VEX_W_0F3A61_P_2,
2133   VEX_W_0F3A62_P_2,
2134   VEX_W_0F3A63_P_2,
2135   VEX_W_0F3ADF_P_2,
2136
2137   EVEX_W_0F10_P_0,
2138   EVEX_W_0F10_P_1_M_0,
2139   EVEX_W_0F10_P_1_M_1,
2140   EVEX_W_0F10_P_2,
2141   EVEX_W_0F10_P_3_M_0,
2142   EVEX_W_0F10_P_3_M_1,
2143   EVEX_W_0F11_P_0,
2144   EVEX_W_0F11_P_1_M_0,
2145   EVEX_W_0F11_P_1_M_1,
2146   EVEX_W_0F11_P_2,
2147   EVEX_W_0F11_P_3_M_0,
2148   EVEX_W_0F11_P_3_M_1,
2149   EVEX_W_0F12_P_0_M_0,
2150   EVEX_W_0F12_P_0_M_1,
2151   EVEX_W_0F12_P_1,
2152   EVEX_W_0F12_P_2,
2153   EVEX_W_0F12_P_3,
2154   EVEX_W_0F13_P_0,
2155   EVEX_W_0F13_P_2,
2156   EVEX_W_0F14_P_0,
2157   EVEX_W_0F14_P_2,
2158   EVEX_W_0F15_P_0,
2159   EVEX_W_0F15_P_2,
2160   EVEX_W_0F16_P_0_M_0,
2161   EVEX_W_0F16_P_0_M_1,
2162   EVEX_W_0F16_P_1,
2163   EVEX_W_0F16_P_2,
2164   EVEX_W_0F17_P_0,
2165   EVEX_W_0F17_P_2,
2166   EVEX_W_0F28_P_0,
2167   EVEX_W_0F28_P_2,
2168   EVEX_W_0F29_P_0,
2169   EVEX_W_0F29_P_2,
2170   EVEX_W_0F2A_P_1,
2171   EVEX_W_0F2A_P_3,
2172   EVEX_W_0F2B_P_0,
2173   EVEX_W_0F2B_P_2,
2174   EVEX_W_0F2E_P_0,
2175   EVEX_W_0F2E_P_2,
2176   EVEX_W_0F2F_P_0,
2177   EVEX_W_0F2F_P_2,
2178   EVEX_W_0F51_P_0,
2179   EVEX_W_0F51_P_1,
2180   EVEX_W_0F51_P_2,
2181   EVEX_W_0F51_P_3,
2182   EVEX_W_0F54_P_0,
2183   EVEX_W_0F54_P_2,
2184   EVEX_W_0F55_P_0,
2185   EVEX_W_0F55_P_2,
2186   EVEX_W_0F56_P_0,
2187   EVEX_W_0F56_P_2,
2188   EVEX_W_0F57_P_0,
2189   EVEX_W_0F57_P_2,
2190   EVEX_W_0F58_P_0,
2191   EVEX_W_0F58_P_1,
2192   EVEX_W_0F58_P_2,
2193   EVEX_W_0F58_P_3,
2194   EVEX_W_0F59_P_0,
2195   EVEX_W_0F59_P_1,
2196   EVEX_W_0F59_P_2,
2197   EVEX_W_0F59_P_3,
2198   EVEX_W_0F5A_P_0,
2199   EVEX_W_0F5A_P_1,
2200   EVEX_W_0F5A_P_2,
2201   EVEX_W_0F5A_P_3,
2202   EVEX_W_0F5B_P_0,
2203   EVEX_W_0F5B_P_1,
2204   EVEX_W_0F5B_P_2,
2205   EVEX_W_0F5C_P_0,
2206   EVEX_W_0F5C_P_1,
2207   EVEX_W_0F5C_P_2,
2208   EVEX_W_0F5C_P_3,
2209   EVEX_W_0F5D_P_0,
2210   EVEX_W_0F5D_P_1,
2211   EVEX_W_0F5D_P_2,
2212   EVEX_W_0F5D_P_3,
2213   EVEX_W_0F5E_P_0,
2214   EVEX_W_0F5E_P_1,
2215   EVEX_W_0F5E_P_2,
2216   EVEX_W_0F5E_P_3,
2217   EVEX_W_0F5F_P_0,
2218   EVEX_W_0F5F_P_1,
2219   EVEX_W_0F5F_P_2,
2220   EVEX_W_0F5F_P_3,
2221   EVEX_W_0F62_P_2,
2222   EVEX_W_0F66_P_2,
2223   EVEX_W_0F6A_P_2,
2224   EVEX_W_0F6B_P_2,
2225   EVEX_W_0F6C_P_2,
2226   EVEX_W_0F6D_P_2,
2227   EVEX_W_0F6E_P_2,
2228   EVEX_W_0F6F_P_1,
2229   EVEX_W_0F6F_P_2,
2230   EVEX_W_0F6F_P_3,
2231   EVEX_W_0F70_P_2,
2232   EVEX_W_0F72_R_2_P_2,
2233   EVEX_W_0F72_R_6_P_2,
2234   EVEX_W_0F73_R_2_P_2,
2235   EVEX_W_0F73_R_6_P_2,
2236   EVEX_W_0F76_P_2,
2237   EVEX_W_0F78_P_0,
2238   EVEX_W_0F78_P_2,
2239   EVEX_W_0F79_P_0,
2240   EVEX_W_0F79_P_2,
2241   EVEX_W_0F7A_P_1,
2242   EVEX_W_0F7A_P_2,
2243   EVEX_W_0F7A_P_3,
2244   EVEX_W_0F7B_P_1,
2245   EVEX_W_0F7B_P_2,
2246   EVEX_W_0F7B_P_3,
2247   EVEX_W_0F7E_P_1,
2248   EVEX_W_0F7E_P_2,
2249   EVEX_W_0F7F_P_1,
2250   EVEX_W_0F7F_P_2,
2251   EVEX_W_0F7F_P_3,
2252   EVEX_W_0FC2_P_0,
2253   EVEX_W_0FC2_P_1,
2254   EVEX_W_0FC2_P_2,
2255   EVEX_W_0FC2_P_3,
2256   EVEX_W_0FC6_P_0,
2257   EVEX_W_0FC6_P_2,
2258   EVEX_W_0FD2_P_2,
2259   EVEX_W_0FD3_P_2,
2260   EVEX_W_0FD4_P_2,
2261   EVEX_W_0FD6_P_2,
2262   EVEX_W_0FE6_P_1,
2263   EVEX_W_0FE6_P_2,
2264   EVEX_W_0FE6_P_3,
2265   EVEX_W_0FE7_P_2,
2266   EVEX_W_0FF2_P_2,
2267   EVEX_W_0FF3_P_2,
2268   EVEX_W_0FF4_P_2,
2269   EVEX_W_0FFA_P_2,
2270   EVEX_W_0FFB_P_2,
2271   EVEX_W_0FFE_P_2,
2272   EVEX_W_0F380C_P_2,
2273   EVEX_W_0F380D_P_2,
2274   EVEX_W_0F3810_P_1,
2275   EVEX_W_0F3810_P_2,
2276   EVEX_W_0F3811_P_1,
2277   EVEX_W_0F3811_P_2,
2278   EVEX_W_0F3812_P_1,
2279   EVEX_W_0F3812_P_2,
2280   EVEX_W_0F3813_P_1,
2281   EVEX_W_0F3813_P_2,
2282   EVEX_W_0F3814_P_1,
2283   EVEX_W_0F3815_P_1,
2284   EVEX_W_0F3818_P_2,
2285   EVEX_W_0F3819_P_2,
2286   EVEX_W_0F381A_P_2,
2287   EVEX_W_0F381B_P_2,
2288   EVEX_W_0F381E_P_2,
2289   EVEX_W_0F381F_P_2,
2290   EVEX_W_0F3820_P_1,
2291   EVEX_W_0F3821_P_1,
2292   EVEX_W_0F3822_P_1,
2293   EVEX_W_0F3823_P_1,
2294   EVEX_W_0F3824_P_1,
2295   EVEX_W_0F3825_P_1,
2296   EVEX_W_0F3825_P_2,
2297   EVEX_W_0F3826_P_1,
2298   EVEX_W_0F3826_P_2,
2299   EVEX_W_0F3828_P_1,
2300   EVEX_W_0F3828_P_2,
2301   EVEX_W_0F3829_P_1,
2302   EVEX_W_0F3829_P_2,
2303   EVEX_W_0F382A_P_1,
2304   EVEX_W_0F382A_P_2,
2305   EVEX_W_0F382B_P_2,
2306   EVEX_W_0F3830_P_1,
2307   EVEX_W_0F3831_P_1,
2308   EVEX_W_0F3832_P_1,
2309   EVEX_W_0F3833_P_1,
2310   EVEX_W_0F3834_P_1,
2311   EVEX_W_0F3835_P_1,
2312   EVEX_W_0F3835_P_2,
2313   EVEX_W_0F3837_P_2,
2314   EVEX_W_0F3838_P_1,
2315   EVEX_W_0F3839_P_1,
2316   EVEX_W_0F383A_P_1,
2317   EVEX_W_0F3840_P_2,
2318   EVEX_W_0F3858_P_2,
2319   EVEX_W_0F3859_P_2,
2320   EVEX_W_0F385A_P_2,
2321   EVEX_W_0F385B_P_2,
2322   EVEX_W_0F3866_P_2,
2323   EVEX_W_0F3875_P_2,
2324   EVEX_W_0F3878_P_2,
2325   EVEX_W_0F3879_P_2,
2326   EVEX_W_0F387A_P_2,
2327   EVEX_W_0F387B_P_2,
2328   EVEX_W_0F387D_P_2,
2329   EVEX_W_0F3883_P_2,
2330   EVEX_W_0F388D_P_2,
2331   EVEX_W_0F3891_P_2,
2332   EVEX_W_0F3893_P_2,
2333   EVEX_W_0F38A1_P_2,
2334   EVEX_W_0F38A3_P_2,
2335   EVEX_W_0F38C7_R_1_P_2,
2336   EVEX_W_0F38C7_R_2_P_2,
2337   EVEX_W_0F38C7_R_5_P_2,
2338   EVEX_W_0F38C7_R_6_P_2,
2339
2340   EVEX_W_0F3A00_P_2,
2341   EVEX_W_0F3A01_P_2,
2342   EVEX_W_0F3A04_P_2,
2343   EVEX_W_0F3A05_P_2,
2344   EVEX_W_0F3A08_P_2,
2345   EVEX_W_0F3A09_P_2,
2346   EVEX_W_0F3A0A_P_2,
2347   EVEX_W_0F3A0B_P_2,
2348   EVEX_W_0F3A16_P_2,
2349   EVEX_W_0F3A18_P_2,
2350   EVEX_W_0F3A19_P_2,
2351   EVEX_W_0F3A1A_P_2,
2352   EVEX_W_0F3A1B_P_2,
2353   EVEX_W_0F3A1D_P_2,
2354   EVEX_W_0F3A21_P_2,
2355   EVEX_W_0F3A22_P_2,
2356   EVEX_W_0F3A23_P_2,
2357   EVEX_W_0F3A38_P_2,
2358   EVEX_W_0F3A39_P_2,
2359   EVEX_W_0F3A3A_P_2,
2360   EVEX_W_0F3A3B_P_2,
2361   EVEX_W_0F3A3E_P_2,
2362   EVEX_W_0F3A3F_P_2,
2363   EVEX_W_0F3A42_P_2,
2364   EVEX_W_0F3A43_P_2,
2365   EVEX_W_0F3A50_P_2,
2366   EVEX_W_0F3A51_P_2,
2367   EVEX_W_0F3A56_P_2,
2368   EVEX_W_0F3A57_P_2,
2369   EVEX_W_0F3A66_P_2,
2370   EVEX_W_0F3A67_P_2
2371 };
2372
2373 typedef void (*op_rtn) (int bytemode, int sizeflag);
2374
2375 struct dis386 {
2376   const char *name;
2377   struct
2378     {
2379       op_rtn rtn;
2380       int bytemode;
2381     } op[MAX_OPERANDS];
2382   unsigned int prefix_requirement;
2383 };
2384
2385 /* Upper case letters in the instruction names here are macros.
2386    'A' => print 'b' if no register operands or suffix_always is true
2387    'B' => print 'b' if suffix_always is true
2388    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2389           size prefix
2390    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2391           suffix_always is true
2392    'E' => print 'e' if 32-bit form of jcxz
2393    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2394    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2395    'H' => print ",pt" or ",pn" branch hint
2396    'I' => honor following macro letter even in Intel mode (implemented only
2397           for some of the macro letters)
2398    'J' => print 'l'
2399    'K' => print 'd' or 'q' if rex prefix is present.
2400    'L' => print 'l' if suffix_always is true
2401    'M' => print 'r' if intel_mnemonic is false.
2402    'N' => print 'n' if instruction has no wait "prefix"
2403    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2404    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2405           or suffix_always is true.  print 'q' if rex prefix is present.
2406    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2407           is true
2408    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2409    'S' => print 'w', 'l' or 'q' if suffix_always is true
2410    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2411    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2412    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2413    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2414    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2415    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2416           suffix_always is true.
2417    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2418    '!' => change condition from true to false or from false to true.
2419    '%' => add 1 upper case letter to the macro.
2420
2421    2 upper case letter macros:
2422    "XY" => print 'x' or 'y' if no register operands or suffix_always
2423            is true.
2424    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2425    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2426            or suffix_always is true
2427    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2428    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2429    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2430    "LW" => print 'd', 'q' depending on the VEX.W bit
2431    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2432            an operand size prefix, or suffix_always is true.  print
2433            'q' if rex prefix is present.
2434
2435    Many of the above letters print nothing in Intel mode.  See "putop"
2436    for the details.
2437
2438    Braces '{' and '}', and vertical bars '|', indicate alternative
2439    mnemonic strings for AT&T and Intel.  */
2440
2441 static const struct dis386 dis386[] = {
2442   /* 00 */
2443   { "addB",             { Ebh1, Gb }, 0 },
2444   { "addS",             { Evh1, Gv }, 0 },
2445   { "addB",             { Gb, EbS }, 0 },
2446   { "addS",             { Gv, EvS }, 0 },
2447   { "addB",             { AL, Ib }, 0 },
2448   { "addS",             { eAX, Iv }, 0 },
2449   { X86_64_TABLE (X86_64_06) },
2450   { X86_64_TABLE (X86_64_07) },
2451   /* 08 */
2452   { "orB",              { Ebh1, Gb }, 0 },
2453   { "orS",              { Evh1, Gv }, 0 },
2454   { "orB",              { Gb, EbS }, 0 },
2455   { "orS",              { Gv, EvS }, 0 },
2456   { "orB",              { AL, Ib }, 0 },
2457   { "orS",              { eAX, Iv }, 0 },
2458   { X86_64_TABLE (X86_64_0D) },
2459   { Bad_Opcode },       /* 0x0f extended opcode escape */
2460   /* 10 */
2461   { "adcB",             { Ebh1, Gb }, 0 },
2462   { "adcS",             { Evh1, Gv }, 0 },
2463   { "adcB",             { Gb, EbS }, 0 },
2464   { "adcS",             { Gv, EvS }, 0 },
2465   { "adcB",             { AL, Ib }, 0 },
2466   { "adcS",             { eAX, Iv }, 0 },
2467   { X86_64_TABLE (X86_64_16) },
2468   { X86_64_TABLE (X86_64_17) },
2469   /* 18 */
2470   { "sbbB",             { Ebh1, Gb }, 0 },
2471   { "sbbS",             { Evh1, Gv }, 0 },
2472   { "sbbB",             { Gb, EbS }, 0 },
2473   { "sbbS",             { Gv, EvS }, 0 },
2474   { "sbbB",             { AL, Ib }, 0 },
2475   { "sbbS",             { eAX, Iv }, 0 },
2476   { X86_64_TABLE (X86_64_1E) },
2477   { X86_64_TABLE (X86_64_1F) },
2478   /* 20 */
2479   { "andB",             { Ebh1, Gb }, 0 },
2480   { "andS",             { Evh1, Gv }, 0 },
2481   { "andB",             { Gb, EbS }, 0 },
2482   { "andS",             { Gv, EvS }, 0 },
2483   { "andB",             { AL, Ib }, 0 },
2484   { "andS",             { eAX, Iv }, 0 },
2485   { Bad_Opcode },       /* SEG ES prefix */
2486   { X86_64_TABLE (X86_64_27) },
2487   /* 28 */
2488   { "subB",             { Ebh1, Gb }, 0 },
2489   { "subS",             { Evh1, Gv }, 0 },
2490   { "subB",             { Gb, EbS }, 0 },
2491   { "subS",             { Gv, EvS }, 0 },
2492   { "subB",             { AL, Ib }, 0 },
2493   { "subS",             { eAX, Iv }, 0 },
2494   { Bad_Opcode },       /* SEG CS prefix */
2495   { X86_64_TABLE (X86_64_2F) },
2496   /* 30 */
2497   { "xorB",             { Ebh1, Gb }, 0 },
2498   { "xorS",             { Evh1, Gv }, 0 },
2499   { "xorB",             { Gb, EbS }, 0 },
2500   { "xorS",             { Gv, EvS }, 0 },
2501   { "xorB",             { AL, Ib }, 0 },
2502   { "xorS",             { eAX, Iv }, 0 },
2503   { Bad_Opcode },       /* SEG SS prefix */
2504   { X86_64_TABLE (X86_64_37) },
2505   /* 38 */
2506   { "cmpB",             { Eb, Gb }, 0 },
2507   { "cmpS",             { Ev, Gv }, 0 },
2508   { "cmpB",             { Gb, EbS }, 0 },
2509   { "cmpS",             { Gv, EvS }, 0 },
2510   { "cmpB",             { AL, Ib }, 0 },
2511   { "cmpS",             { eAX, Iv }, 0 },
2512   { Bad_Opcode },       /* SEG DS prefix */
2513   { X86_64_TABLE (X86_64_3F) },
2514   /* 40 */
2515   { "inc{S|}",          { RMeAX }, 0 },
2516   { "inc{S|}",          { RMeCX }, 0 },
2517   { "inc{S|}",          { RMeDX }, 0 },
2518   { "inc{S|}",          { RMeBX }, 0 },
2519   { "inc{S|}",          { RMeSP }, 0 },
2520   { "inc{S|}",          { RMeBP }, 0 },
2521   { "inc{S|}",          { RMeSI }, 0 },
2522   { "inc{S|}",          { RMeDI }, 0 },
2523   /* 48 */
2524   { "dec{S|}",          { RMeAX }, 0 },
2525   { "dec{S|}",          { RMeCX }, 0 },
2526   { "dec{S|}",          { RMeDX }, 0 },
2527   { "dec{S|}",          { RMeBX }, 0 },
2528   { "dec{S|}",          { RMeSP }, 0 },
2529   { "dec{S|}",          { RMeBP }, 0 },
2530   { "dec{S|}",          { RMeSI }, 0 },
2531   { "dec{S|}",          { RMeDI }, 0 },
2532   /* 50 */
2533   { "pushV",            { RMrAX }, 0 },
2534   { "pushV",            { RMrCX }, 0 },
2535   { "pushV",            { RMrDX }, 0 },
2536   { "pushV",            { RMrBX }, 0 },
2537   { "pushV",            { RMrSP }, 0 },
2538   { "pushV",            { RMrBP }, 0 },
2539   { "pushV",            { RMrSI }, 0 },
2540   { "pushV",            { RMrDI }, 0 },
2541   /* 58 */
2542   { "popV",             { RMrAX }, 0 },
2543   { "popV",             { RMrCX }, 0 },
2544   { "popV",             { RMrDX }, 0 },
2545   { "popV",             { RMrBX }, 0 },
2546   { "popV",             { RMrSP }, 0 },
2547   { "popV",             { RMrBP }, 0 },
2548   { "popV",             { RMrSI }, 0 },
2549   { "popV",             { RMrDI }, 0 },
2550   /* 60 */
2551   { X86_64_TABLE (X86_64_60) },
2552   { X86_64_TABLE (X86_64_61) },
2553   { X86_64_TABLE (X86_64_62) },
2554   { X86_64_TABLE (X86_64_63) },
2555   { Bad_Opcode },       /* seg fs */
2556   { Bad_Opcode },       /* seg gs */
2557   { Bad_Opcode },       /* op size prefix */
2558   { Bad_Opcode },       /* adr size prefix */
2559   /* 68 */
2560   { "pushT",            { sIv }, 0 },
2561   { "imulS",            { Gv, Ev, Iv }, 0 },
2562   { "pushT",            { sIbT }, 0 },
2563   { "imulS",            { Gv, Ev, sIb }, 0 },
2564   { "ins{b|}",          { Ybr, indirDX }, 0 },
2565   { X86_64_TABLE (X86_64_6D) },
2566   { "outs{b|}",         { indirDXr, Xb }, 0 },
2567   { X86_64_TABLE (X86_64_6F) },
2568   /* 70 */
2569   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2570   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2571   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2572   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2573   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2574   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2575   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2577   /* 78 */
2578   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2579   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2580   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2581   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2582   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2583   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2584   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2585   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2586   /* 80 */
2587   { REG_TABLE (REG_80) },
2588   { REG_TABLE (REG_81) },
2589   { Bad_Opcode },
2590   { REG_TABLE (REG_82) },
2591   { "testB",            { Eb, Gb }, 0 },
2592   { "testS",            { Ev, Gv }, 0 },
2593   { "xchgB",            { Ebh2, Gb }, 0 },
2594   { "xchgS",            { Evh2, Gv }, 0 },
2595   /* 88 */
2596   { "movB",             { Ebh3, Gb }, 0 },
2597   { "movS",             { Evh3, Gv }, 0 },
2598   { "movB",             { Gb, EbS }, 0 },
2599   { "movS",             { Gv, EvS }, 0 },
2600   { "movD",             { Sv, Sw }, 0 },
2601   { MOD_TABLE (MOD_8D) },
2602   { "movD",             { Sw, Sv }, 0 },
2603   { REG_TABLE (REG_8F) },
2604   /* 90 */
2605   { PREFIX_TABLE (PREFIX_90) },
2606   { "xchgS",            { RMeCX, eAX }, 0 },
2607   { "xchgS",            { RMeDX, eAX }, 0 },
2608   { "xchgS",            { RMeBX, eAX }, 0 },
2609   { "xchgS",            { RMeSP, eAX }, 0 },
2610   { "xchgS",            { RMeBP, eAX }, 0 },
2611   { "xchgS",            { RMeSI, eAX }, 0 },
2612   { "xchgS",            { RMeDI, eAX }, 0 },
2613   /* 98 */
2614   { "cW{t|}R",          { XX }, 0 },
2615   { "cR{t|}O",          { XX }, 0 },
2616   { X86_64_TABLE (X86_64_9A) },
2617   { Bad_Opcode },       /* fwait */
2618   { "pushfT",           { XX }, 0 },
2619   { "popfT",            { XX }, 0 },
2620   { "sahf",             { XX }, 0 },
2621   { "lahf",             { XX }, 0 },
2622   /* a0 */
2623   { "mov%LB",           { AL, Ob }, 0 },
2624   { "mov%LS",           { eAX, Ov }, 0 },
2625   { "mov%LB",           { Ob, AL }, 0 },
2626   { "mov%LS",           { Ov, eAX }, 0 },
2627   { "movs{b|}",         { Ybr, Xb }, 0 },
2628   { "movs{R|}",         { Yvr, Xv }, 0 },
2629   { "cmps{b|}",         { Xb, Yb }, 0 },
2630   { "cmps{R|}",         { Xv, Yv }, 0 },
2631   /* a8 */
2632   { "testB",            { AL, Ib }, 0 },
2633   { "testS",            { eAX, Iv }, 0 },
2634   { "stosB",            { Ybr, AL }, 0 },
2635   { "stosS",            { Yvr, eAX }, 0 },
2636   { "lodsB",            { ALr, Xb }, 0 },
2637   { "lodsS",            { eAXr, Xv }, 0 },
2638   { "scasB",            { AL, Yb }, 0 },
2639   { "scasS",            { eAX, Yv }, 0 },
2640   /* b0 */
2641   { "movB",             { RMAL, Ib }, 0 },
2642   { "movB",             { RMCL, Ib }, 0 },
2643   { "movB",             { RMDL, Ib }, 0 },
2644   { "movB",             { RMBL, Ib }, 0 },
2645   { "movB",             { RMAH, Ib }, 0 },
2646   { "movB",             { RMCH, Ib }, 0 },
2647   { "movB",             { RMDH, Ib }, 0 },
2648   { "movB",             { RMBH, Ib }, 0 },
2649   /* b8 */
2650   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2651   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2652   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2653   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2654   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2655   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2656   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2657   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2658   /* c0 */
2659   { REG_TABLE (REG_C0) },
2660   { REG_TABLE (REG_C1) },
2661   { "retT",             { Iw, BND }, 0 },
2662   { "retT",             { BND }, 0 },
2663   { X86_64_TABLE (X86_64_C4) },
2664   { X86_64_TABLE (X86_64_C5) },
2665   { REG_TABLE (REG_C6) },
2666   { REG_TABLE (REG_C7) },
2667   /* c8 */
2668   { "enterT",           { Iw, Ib }, 0 },
2669   { "leaveT",           { XX }, 0 },
2670   { "Jret{|f}P",        { Iw }, 0 },
2671   { "Jret{|f}P",        { XX }, 0 },
2672   { "int3",             { XX }, 0 },
2673   { "int",              { Ib }, 0 },
2674   { X86_64_TABLE (X86_64_CE) },
2675   { "iret%LP",          { XX }, 0 },
2676   /* d0 */
2677   { REG_TABLE (REG_D0) },
2678   { REG_TABLE (REG_D1) },
2679   { REG_TABLE (REG_D2) },
2680   { REG_TABLE (REG_D3) },
2681   { X86_64_TABLE (X86_64_D4) },
2682   { X86_64_TABLE (X86_64_D5) },
2683   { Bad_Opcode },
2684   { "xlat",             { DSBX }, 0 },
2685   /* d8 */
2686   { FLOAT },
2687   { FLOAT },
2688   { FLOAT },
2689   { FLOAT },
2690   { FLOAT },
2691   { FLOAT },
2692   { FLOAT },
2693   { FLOAT },
2694   /* e0 */
2695   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2696   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2697   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2698   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2699   { "inB",              { AL, Ib }, 0 },
2700   { "inG",              { zAX, Ib }, 0 },
2701   { "outB",             { Ib, AL }, 0 },
2702   { "outG",             { Ib, zAX }, 0 },
2703   /* e8 */
2704   { "callT",            { Jv, BND }, 0 },
2705   { "jmpT",             { Jv, BND }, 0 },
2706   { X86_64_TABLE (X86_64_EA) },
2707   { "jmp",              { Jb, BND }, 0 },
2708   { "inB",              { AL, indirDX }, 0 },
2709   { "inG",              { zAX, indirDX }, 0 },
2710   { "outB",             { indirDX, AL }, 0 },
2711   { "outG",             { indirDX, zAX }, 0 },
2712   /* f0 */
2713   { Bad_Opcode },       /* lock prefix */
2714   { "icebp",            { XX }, 0 },
2715   { Bad_Opcode },       /* repne */
2716   { Bad_Opcode },       /* repz */
2717   { "hlt",              { XX }, 0 },
2718   { "cmc",              { XX }, 0 },
2719   { REG_TABLE (REG_F6) },
2720   { REG_TABLE (REG_F7) },
2721   /* f8 */
2722   { "clc",              { XX }, 0 },
2723   { "stc",              { XX }, 0 },
2724   { "cli",              { XX }, 0 },
2725   { "sti",              { XX }, 0 },
2726   { "cld",              { XX }, 0 },
2727   { "std",              { XX }, 0 },
2728   { REG_TABLE (REG_FE) },
2729   { REG_TABLE (REG_FF) },
2730 };
2731
2732 static const struct dis386 dis386_twobyte[] = {
2733   /* 00 */
2734   { REG_TABLE (REG_0F00 ) },
2735   { REG_TABLE (REG_0F01 ) },
2736   { "larS",             { Gv, Ew }, 0 },
2737   { "lslS",             { Gv, Ew }, 0 },
2738   { Bad_Opcode },
2739   { "syscall",          { XX }, 0 },
2740   { "clts",             { XX }, 0 },
2741   { "sysret%LP",                { XX }, 0 },
2742   /* 08 */
2743   { "invd",             { XX }, 0 },
2744   { "wbinvd",           { XX }, 0 },
2745   { Bad_Opcode },
2746   { "ud2",              { XX }, 0 },
2747   { Bad_Opcode },
2748   { REG_TABLE (REG_0F0D) },
2749   { "femms",            { XX }, 0 },
2750   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2751   /* 10 */
2752   { PREFIX_TABLE (PREFIX_0F10) },
2753   { PREFIX_TABLE (PREFIX_0F11) },
2754   { PREFIX_TABLE (PREFIX_0F12) },
2755   { MOD_TABLE (MOD_0F13) },
2756   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2757   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2758   { PREFIX_TABLE (PREFIX_0F16) },
2759   { MOD_TABLE (MOD_0F17) },
2760   /* 18 */
2761   { REG_TABLE (REG_0F18) },
2762   { "nopQ",             { Ev }, 0 },
2763   { PREFIX_TABLE (PREFIX_0F1A) },
2764   { PREFIX_TABLE (PREFIX_0F1B) },
2765   { "nopQ",             { Ev }, 0 },
2766   { "nopQ",             { Ev }, 0 },
2767   { "nopQ",             { Ev }, 0 },
2768   { "nopQ",             { Ev }, 0 },
2769   /* 20 */
2770   { "movZ",             { Rm, Cm }, 0 },
2771   { "movZ",             { Rm, Dm }, 0 },
2772   { "movZ",             { Cm, Rm }, 0 },
2773   { "movZ",             { Dm, Rm }, 0 },
2774   { MOD_TABLE (MOD_0F24) },
2775   { Bad_Opcode },
2776   { MOD_TABLE (MOD_0F26) },
2777   { Bad_Opcode },
2778   /* 28 */
2779   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2780   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F2A) },
2782   { PREFIX_TABLE (PREFIX_0F2B) },
2783   { PREFIX_TABLE (PREFIX_0F2C) },
2784   { PREFIX_TABLE (PREFIX_0F2D) },
2785   { PREFIX_TABLE (PREFIX_0F2E) },
2786   { PREFIX_TABLE (PREFIX_0F2F) },
2787   /* 30 */
2788   { "wrmsr",            { XX }, 0 },
2789   { "rdtsc",            { XX }, 0 },
2790   { "rdmsr",            { XX }, 0 },
2791   { "rdpmc",            { XX }, 0 },
2792   { "sysenter",         { XX }, 0 },
2793   { "sysexit",          { XX }, 0 },
2794   { Bad_Opcode },
2795   { "getsec",           { XX }, 0 },
2796   /* 38 */
2797   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2798   { Bad_Opcode },
2799   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2800   { Bad_Opcode },
2801   { Bad_Opcode },
2802   { Bad_Opcode },
2803   { Bad_Opcode },
2804   { Bad_Opcode },
2805   /* 40 */
2806   { "cmovoS",           { Gv, Ev }, 0 },
2807   { "cmovnoS",          { Gv, Ev }, 0 },
2808   { "cmovbS",           { Gv, Ev }, 0 },
2809   { "cmovaeS",          { Gv, Ev }, 0 },
2810   { "cmoveS",           { Gv, Ev }, 0 },
2811   { "cmovneS",          { Gv, Ev }, 0 },
2812   { "cmovbeS",          { Gv, Ev }, 0 },
2813   { "cmovaS",           { Gv, Ev }, 0 },
2814   /* 48 */
2815   { "cmovsS",           { Gv, Ev }, 0 },
2816   { "cmovnsS",          { Gv, Ev }, 0 },
2817   { "cmovpS",           { Gv, Ev }, 0 },
2818   { "cmovnpS",          { Gv, Ev }, 0 },
2819   { "cmovlS",           { Gv, Ev }, 0 },
2820   { "cmovgeS",          { Gv, Ev }, 0 },
2821   { "cmovleS",          { Gv, Ev }, 0 },
2822   { "cmovgS",           { Gv, Ev }, 0 },
2823   /* 50 */
2824   { MOD_TABLE (MOD_0F51) },
2825   { PREFIX_TABLE (PREFIX_0F51) },
2826   { PREFIX_TABLE (PREFIX_0F52) },
2827   { PREFIX_TABLE (PREFIX_0F53) },
2828   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2829   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2830   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2831   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2832   /* 58 */
2833   { PREFIX_TABLE (PREFIX_0F58) },
2834   { PREFIX_TABLE (PREFIX_0F59) },
2835   { PREFIX_TABLE (PREFIX_0F5A) },
2836   { PREFIX_TABLE (PREFIX_0F5B) },
2837   { PREFIX_TABLE (PREFIX_0F5C) },
2838   { PREFIX_TABLE (PREFIX_0F5D) },
2839   { PREFIX_TABLE (PREFIX_0F5E) },
2840   { PREFIX_TABLE (PREFIX_0F5F) },
2841   /* 60 */
2842   { PREFIX_TABLE (PREFIX_0F60) },
2843   { PREFIX_TABLE (PREFIX_0F61) },
2844   { PREFIX_TABLE (PREFIX_0F62) },
2845   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2846   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2847   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2848   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2849   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2850   /* 68 */
2851   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2852   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2853   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2854   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0F6C) },
2856   { PREFIX_TABLE (PREFIX_0F6D) },
2857   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2858   { PREFIX_TABLE (PREFIX_0F6F) },
2859   /* 70 */
2860   { PREFIX_TABLE (PREFIX_0F70) },
2861   { REG_TABLE (REG_0F71) },
2862   { REG_TABLE (REG_0F72) },
2863   { REG_TABLE (REG_0F73) },
2864   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2865   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2866   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2867   { "emms",             { XX }, PREFIX_OPCODE },
2868   /* 78 */
2869   { PREFIX_TABLE (PREFIX_0F78) },
2870   { PREFIX_TABLE (PREFIX_0F79) },
2871   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2872   { Bad_Opcode },
2873   { PREFIX_TABLE (PREFIX_0F7C) },
2874   { PREFIX_TABLE (PREFIX_0F7D) },
2875   { PREFIX_TABLE (PREFIX_0F7E) },
2876   { PREFIX_TABLE (PREFIX_0F7F) },
2877   /* 80 */
2878   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2879   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2880   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2881   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2882   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2883   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2884   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2886   /* 88 */
2887   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2888   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2889   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2890   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2891   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2892   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2893   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2894   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2895   /* 90 */
2896   { "seto",             { Eb }, 0 },
2897   { "setno",            { Eb }, 0 },
2898   { "setb",             { Eb }, 0 },
2899   { "setae",            { Eb }, 0 },
2900   { "sete",             { Eb }, 0 },
2901   { "setne",            { Eb }, 0 },
2902   { "setbe",            { Eb }, 0 },
2903   { "seta",             { Eb }, 0 },
2904   /* 98 */
2905   { "sets",             { Eb }, 0 },
2906   { "setns",            { Eb }, 0 },
2907   { "setp",             { Eb }, 0 },
2908   { "setnp",            { Eb }, 0 },
2909   { "setl",             { Eb }, 0 },
2910   { "setge",            { Eb }, 0 },
2911   { "setle",            { Eb }, 0 },
2912   { "setg",             { Eb }, 0 },
2913   /* a0 */
2914   { "pushT",            { fs }, 0 },
2915   { "popT",             { fs }, 0 },
2916   { "cpuid",            { XX }, 0 },
2917   { "btS",              { Ev, Gv }, 0 },
2918   { "shldS",            { Ev, Gv, Ib }, 0 },
2919   { "shldS",            { Ev, Gv, CL }, 0 },
2920   { REG_TABLE (REG_0FA6) },
2921   { REG_TABLE (REG_0FA7) },
2922   /* a8 */
2923   { "pushT",            { gs }, 0 },
2924   { "popT",             { gs }, 0 },
2925   { "rsm",              { XX }, 0 },
2926   { "btsS",             { Evh1, Gv }, 0 },
2927   { "shrdS",            { Ev, Gv, Ib }, 0 },
2928   { "shrdS",            { Ev, Gv, CL }, 0 },
2929   { REG_TABLE (REG_0FAE) },
2930   { "imulS",            { Gv, Ev }, 0 },
2931   /* b0 */
2932   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2933   { "cmpxchgS",         { Evh1, Gv }, 0 },
2934   { MOD_TABLE (MOD_0FB2) },
2935   { "btrS",             { Evh1, Gv }, 0 },
2936   { MOD_TABLE (MOD_0FB4) },
2937   { MOD_TABLE (MOD_0FB5) },
2938   { "movz{bR|x}",       { Gv, Eb }, 0 },
2939   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2940   /* b8 */
2941   { PREFIX_TABLE (PREFIX_0FB8) },
2942   { "ud1",              { XX }, 0 },
2943   { REG_TABLE (REG_0FBA) },
2944   { "btcS",             { Evh1, Gv }, 0 },
2945   { PREFIX_TABLE (PREFIX_0FBC) },
2946   { PREFIX_TABLE (PREFIX_0FBD) },
2947   { "movs{bR|x}",       { Gv, Eb }, 0 },
2948   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2949   /* c0 */
2950   { "xaddB",            { Ebh1, Gb }, 0 },
2951   { "xaddS",            { Evh1, Gv }, 0 },
2952   { PREFIX_TABLE (PREFIX_0FC2) },
2953   { PREFIX_TABLE (PREFIX_0FC3) },
2954   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2955   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2956   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2957   { REG_TABLE (REG_0FC7) },
2958   /* c8 */
2959   { "bswap",            { RMeAX }, 0 },
2960   { "bswap",            { RMeCX }, 0 },
2961   { "bswap",            { RMeDX }, 0 },
2962   { "bswap",            { RMeBX }, 0 },
2963   { "bswap",            { RMeSP }, 0 },
2964   { "bswap",            { RMeBP }, 0 },
2965   { "bswap",            { RMeSI }, 0 },
2966   { "bswap",            { RMeDI }, 0 },
2967   /* d0 */
2968   { PREFIX_TABLE (PREFIX_0FD0) },
2969   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2970   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2971   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2972   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2973   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2974   { PREFIX_TABLE (PREFIX_0FD6) },
2975   { MOD_TABLE (MOD_0FD7) },
2976   /* d8 */
2977   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2978   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2979   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2980   { "pand",             { MX, EM }, PREFIX_OPCODE },
2981   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2982   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2983   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2984   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2985   /* e0 */
2986   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2987   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2988   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2989   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2990   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2991   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2992   { PREFIX_TABLE (PREFIX_0FE6) },
2993   { PREFIX_TABLE (PREFIX_0FE7) },
2994   /* e8 */
2995   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2996   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2997   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2998   { "por",              { MX, EM }, PREFIX_OPCODE },
2999   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3000   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3001   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3002   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3003   /* f0 */
3004   { PREFIX_TABLE (PREFIX_0FF0) },
3005   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3006   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3007   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3008   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3009   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3010   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3011   { PREFIX_TABLE (PREFIX_0FF7) },
3012   /* f8 */
3013   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3014   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3015   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3016   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3017   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3018   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3019   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3020   { Bad_Opcode },
3021 };
3022
3023 static const unsigned char onebyte_has_modrm[256] = {
3024   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3025   /*       -------------------------------        */
3026   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3027   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3028   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3029   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3030   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3031   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3032   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3033   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3034   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3035   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3036   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3037   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3038   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3039   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3040   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3041   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3042   /*       -------------------------------        */
3043   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3044 };
3045
3046 static const unsigned char twobyte_has_modrm[256] = {
3047   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3048   /*       -------------------------------        */
3049   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3050   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3051   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3052   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3053   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3054   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3055   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3056   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3057   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3058   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3059   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3060   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3061   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3062   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3063   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3064   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3065   /*       -------------------------------        */
3066   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3067 };
3068
3069 static char obuf[100];
3070 static char *obufp;
3071 static char *mnemonicendp;
3072 static char scratchbuf[100];
3073 static unsigned char *start_codep;
3074 static unsigned char *insn_codep;
3075 static unsigned char *codep;
3076 static unsigned char *end_codep;
3077 static int last_lock_prefix;
3078 static int last_repz_prefix;
3079 static int last_repnz_prefix;
3080 static int last_data_prefix;
3081 static int last_addr_prefix;
3082 static int last_rex_prefix;
3083 static int last_seg_prefix;
3084 static int fwait_prefix;
3085 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3086 static int prefix_requirement;
3087 /* The active segment register prefix.  */
3088 static int active_seg_prefix;
3089 #define MAX_CODE_LENGTH 15
3090 /* We can up to 14 prefixes since the maximum instruction length is
3091    15bytes.  */
3092 static int all_prefixes[MAX_CODE_LENGTH - 1];
3093 static disassemble_info *the_info;
3094 static struct
3095   {
3096     int mod;
3097     int reg;
3098     int rm;
3099   }
3100 modrm;
3101 static unsigned char need_modrm;
3102 static struct
3103   {
3104     int scale;
3105     int index;
3106     int base;
3107   }
3108 sib;
3109 static struct
3110   {
3111     int register_specifier;
3112     int length;
3113     int prefix;
3114     int w;
3115     int evex;
3116     int r;
3117     int v;
3118     int mask_register_specifier;
3119     int zeroing;
3120     int ll;
3121     int b;
3122   }
3123 vex;
3124 static unsigned char need_vex;
3125 static unsigned char need_vex_reg;
3126 static unsigned char vex_w_done;
3127
3128 struct op
3129   {
3130     const char *name;
3131     unsigned int len;
3132   };
3133
3134 /* If we are accessing mod/rm/reg without need_modrm set, then the
3135    values are stale.  Hitting this abort likely indicates that you
3136    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3137 #define MODRM_CHECK  if (!need_modrm) abort ()
3138
3139 static const char **names64;
3140 static const char **names32;
3141 static const char **names16;
3142 static const char **names8;
3143 static const char **names8rex;
3144 static const char **names_seg;
3145 static const char *index64;
3146 static const char *index32;
3147 static const char **index16;
3148 static const char **names_bnd;
3149
3150 static const char *intel_names64[] = {
3151   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3152   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3153 };
3154 static const char *intel_names32[] = {
3155   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3156   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3157 };
3158 static const char *intel_names16[] = {
3159   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3160   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3161 };
3162 static const char *intel_names8[] = {
3163   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3164 };
3165 static const char *intel_names8rex[] = {
3166   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3167   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3168 };
3169 static const char *intel_names_seg[] = {
3170   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3171 };
3172 static const char *intel_index64 = "riz";
3173 static const char *intel_index32 = "eiz";
3174 static const char *intel_index16[] = {
3175   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3176 };
3177
3178 static const char *att_names64[] = {
3179   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3180   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3181 };
3182 static const char *att_names32[] = {
3183   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3184   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3185 };
3186 static const char *att_names16[] = {
3187   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3188   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3189 };
3190 static const char *att_names8[] = {
3191   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3192 };
3193 static const char *att_names8rex[] = {
3194   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3195   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3196 };
3197 static const char *att_names_seg[] = {
3198   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3199 };
3200 static const char *att_index64 = "%riz";
3201 static const char *att_index32 = "%eiz";
3202 static const char *att_index16[] = {
3203   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3204 };
3205
3206 static const char **names_mm;
3207 static const char *intel_names_mm[] = {
3208   "mm0", "mm1", "mm2", "mm3",
3209   "mm4", "mm5", "mm6", "mm7"
3210 };
3211 static const char *att_names_mm[] = {
3212   "%mm0", "%mm1", "%mm2", "%mm3",
3213   "%mm4", "%mm5", "%mm6", "%mm7"
3214 };
3215
3216 static const char *intel_names_bnd[] = {
3217   "bnd0", "bnd1", "bnd2", "bnd3"
3218 };
3219
3220 static const char *att_names_bnd[] = {
3221   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3222 };
3223
3224 static const char **names_xmm;
3225 static const char *intel_names_xmm[] = {
3226   "xmm0", "xmm1", "xmm2", "xmm3",
3227   "xmm4", "xmm5", "xmm6", "xmm7",
3228   "xmm8", "xmm9", "xmm10", "xmm11",
3229   "xmm12", "xmm13", "xmm14", "xmm15",
3230   "xmm16", "xmm17", "xmm18", "xmm19",
3231   "xmm20", "xmm21", "xmm22", "xmm23",
3232   "xmm24", "xmm25", "xmm26", "xmm27",
3233   "xmm28", "xmm29", "xmm30", "xmm31"
3234 };
3235 static const char *att_names_xmm[] = {
3236   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3237   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3238   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3239   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3240   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3241   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3242   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3243   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3244 };
3245
3246 static const char **names_ymm;
3247 static const char *intel_names_ymm[] = {
3248   "ymm0", "ymm1", "ymm2", "ymm3",
3249   "ymm4", "ymm5", "ymm6", "ymm7",
3250   "ymm8", "ymm9", "ymm10", "ymm11",
3251   "ymm12", "ymm13", "ymm14", "ymm15",
3252   "ymm16", "ymm17", "ymm18", "ymm19",
3253   "ymm20", "ymm21", "ymm22", "ymm23",
3254   "ymm24", "ymm25", "ymm26", "ymm27",
3255   "ymm28", "ymm29", "ymm30", "ymm31"
3256 };
3257 static const char *att_names_ymm[] = {
3258   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3259   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3260   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3261   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3262   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3263   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3264   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3265   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3266 };
3267
3268 static const char **names_zmm;
3269 static const char *intel_names_zmm[] = {
3270   "zmm0", "zmm1", "zmm2", "zmm3",
3271   "zmm4", "zmm5", "zmm6", "zmm7",
3272   "zmm8", "zmm9", "zmm10", "zmm11",
3273   "zmm12", "zmm13", "zmm14", "zmm15",
3274   "zmm16", "zmm17", "zmm18", "zmm19",
3275   "zmm20", "zmm21", "zmm22", "zmm23",
3276   "zmm24", "zmm25", "zmm26", "zmm27",
3277   "zmm28", "zmm29", "zmm30", "zmm31"
3278 };
3279 static const char *att_names_zmm[] = {
3280   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3281   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3282   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3283   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3284   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3285   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3286   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3287   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3288 };
3289
3290 static const char **names_mask;
3291 static const char *intel_names_mask[] = {
3292   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3293 };
3294 static const char *att_names_mask[] = {
3295   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3296 };
3297
3298 static const char *names_rounding[] =
3299 {
3300   "{rn-sae}",
3301   "{rd-sae}",
3302   "{ru-sae}",
3303   "{rz-sae}"
3304 };
3305
3306 static const struct dis386 reg_table[][8] = {
3307   /* REG_80 */
3308   {
3309     { "addA",   { Ebh1, Ib }, 0 },
3310     { "orA",    { Ebh1, Ib }, 0 },
3311     { "adcA",   { Ebh1, Ib }, 0 },
3312     { "sbbA",   { Ebh1, Ib }, 0 },
3313     { "andA",   { Ebh1, Ib }, 0 },
3314     { "subA",   { Ebh1, Ib }, 0 },
3315     { "xorA",   { Ebh1, Ib }, 0 },
3316     { "cmpA",   { Eb, Ib }, 0 },
3317   },
3318   /* REG_81 */
3319   {
3320     { "addQ",   { Evh1, Iv }, 0 },
3321     { "orQ",    { Evh1, Iv }, 0 },
3322     { "adcQ",   { Evh1, Iv }, 0 },
3323     { "sbbQ",   { Evh1, Iv }, 0 },
3324     { "andQ",   { Evh1, Iv }, 0 },
3325     { "subQ",   { Evh1, Iv }, 0 },
3326     { "xorQ",   { Evh1, Iv }, 0 },
3327     { "cmpQ",   { Ev, Iv }, 0 },
3328   },
3329   /* REG_82 */
3330   {
3331     { "addQ",   { Evh1, sIb }, 0 },
3332     { "orQ",    { Evh1, sIb }, 0 },
3333     { "adcQ",   { Evh1, sIb }, 0 },
3334     { "sbbQ",   { Evh1, sIb }, 0 },
3335     { "andQ",   { Evh1, sIb }, 0 },
3336     { "subQ",   { Evh1, sIb }, 0 },
3337     { "xorQ",   { Evh1, sIb }, 0 },
3338     { "cmpQ",   { Ev, sIb }, 0 },
3339   },
3340   /* REG_8F */
3341   {
3342     { "popU",   { stackEv }, 0 },
3343     { XOP_8F_TABLE (XOP_09) },
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347     { XOP_8F_TABLE (XOP_09) },
3348   },
3349   /* REG_C0 */
3350   {
3351     { "rolA",   { Eb, Ib }, 0 },
3352     { "rorA",   { Eb, Ib }, 0 },
3353     { "rclA",   { Eb, Ib }, 0 },
3354     { "rcrA",   { Eb, Ib }, 0 },
3355     { "shlA",   { Eb, Ib }, 0 },
3356     { "shrA",   { Eb, Ib }, 0 },
3357     { Bad_Opcode },
3358     { "sarA",   { Eb, Ib }, 0 },
3359   },
3360   /* REG_C1 */
3361   {
3362     { "rolQ",   { Ev, Ib }, 0 },
3363     { "rorQ",   { Ev, Ib }, 0 },
3364     { "rclQ",   { Ev, Ib }, 0 },
3365     { "rcrQ",   { Ev, Ib }, 0 },
3366     { "shlQ",   { Ev, Ib }, 0 },
3367     { "shrQ",   { Ev, Ib }, 0 },
3368     { Bad_Opcode },
3369     { "sarQ",   { Ev, Ib }, 0 },
3370   },
3371   /* REG_C6 */
3372   {
3373     { "movA",   { Ebh3, Ib }, 0 },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { MOD_TABLE (MOD_C6_REG_7) },
3381   },
3382   /* REG_C7 */
3383   {
3384     { "movQ",   { Evh3, Iv }, 0 },
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_C7_REG_7) },
3392   },
3393   /* REG_D0 */
3394   {
3395     { "rolA",   { Eb, I1 }, 0 },
3396     { "rorA",   { Eb, I1 }, 0 },
3397     { "rclA",   { Eb, I1 }, 0 },
3398     { "rcrA",   { Eb, I1 }, 0 },
3399     { "shlA",   { Eb, I1 }, 0 },
3400     { "shrA",   { Eb, I1 }, 0 },
3401     { Bad_Opcode },
3402     { "sarA",   { Eb, I1 }, 0 },
3403   },
3404   /* REG_D1 */
3405   {
3406     { "rolQ",   { Ev, I1 }, 0 },
3407     { "rorQ",   { Ev, I1 }, 0 },
3408     { "rclQ",   { Ev, I1 }, 0 },
3409     { "rcrQ",   { Ev, I1 }, 0 },
3410     { "shlQ",   { Ev, I1 }, 0 },
3411     { "shrQ",   { Ev, I1 }, 0 },
3412     { Bad_Opcode },
3413     { "sarQ",   { Ev, I1 }, 0 },
3414   },
3415   /* REG_D2 */
3416   {
3417     { "rolA",   { Eb, CL }, 0 },
3418     { "rorA",   { Eb, CL }, 0 },
3419     { "rclA",   { Eb, CL }, 0 },
3420     { "rcrA",   { Eb, CL }, 0 },
3421     { "shlA",   { Eb, CL }, 0 },
3422     { "shrA",   { Eb, CL }, 0 },
3423     { Bad_Opcode },
3424     { "sarA",   { Eb, CL }, 0 },
3425   },
3426   /* REG_D3 */
3427   {
3428     { "rolQ",   { Ev, CL }, 0 },
3429     { "rorQ",   { Ev, CL }, 0 },
3430     { "rclQ",   { Ev, CL }, 0 },
3431     { "rcrQ",   { Ev, CL }, 0 },
3432     { "shlQ",   { Ev, CL }, 0 },
3433     { "shrQ",   { Ev, CL }, 0 },
3434     { Bad_Opcode },
3435     { "sarQ",   { Ev, CL }, 0 },
3436   },
3437   /* REG_F6 */
3438   {
3439     { "testA",  { Eb, Ib }, 0 },
3440     { Bad_Opcode },
3441     { "notA",   { Ebh1 }, 0 },
3442     { "negA",   { Ebh1 }, 0 },
3443     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3444     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3445     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3446     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3447   },
3448   /* REG_F7 */
3449   {
3450     { "testQ",  { Ev, Iv }, 0 },
3451     { Bad_Opcode },
3452     { "notQ",   { Evh1 }, 0 },
3453     { "negQ",   { Evh1 }, 0 },
3454     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3455     { "imulQ",  { Ev }, 0 },
3456     { "divQ",   { Ev }, 0 },
3457     { "idivQ",  { Ev }, 0 },
3458   },
3459   /* REG_FE */
3460   {
3461     { "incA",   { Ebh1 }, 0 },
3462     { "decA",   { Ebh1 }, 0 },
3463   },
3464   /* REG_FF */
3465   {
3466     { "incQ",   { Evh1 }, 0 },
3467     { "decQ",   { Evh1 }, 0 },
3468     { "call{T|}", { indirEv, BND }, 0 },
3469     { MOD_TABLE (MOD_FF_REG_3) },
3470     { "jmp{T|}", { indirEv, BND }, 0 },
3471     { MOD_TABLE (MOD_FF_REG_5) },
3472     { "pushU",  { stackEv }, 0 },
3473     { Bad_Opcode },
3474   },
3475   /* REG_0F00 */
3476   {
3477     { "sldtD",  { Sv }, 0 },
3478     { "strD",   { Sv }, 0 },
3479     { "lldt",   { Ew }, 0 },
3480     { "ltr",    { Ew }, 0 },
3481     { "verr",   { Ew }, 0 },
3482     { "verw",   { Ew }, 0 },
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485   },
3486   /* REG_0F01 */
3487   {
3488     { MOD_TABLE (MOD_0F01_REG_0) },
3489     { MOD_TABLE (MOD_0F01_REG_1) },
3490     { MOD_TABLE (MOD_0F01_REG_2) },
3491     { MOD_TABLE (MOD_0F01_REG_3) },
3492     { "smswD",  { Sv }, 0 },
3493     { Bad_Opcode },
3494     { "lmsw",   { Ew }, 0 },
3495     { MOD_TABLE (MOD_0F01_REG_7) },
3496   },
3497   /* REG_0F0D */
3498   {
3499     { "prefetch",       { Mb }, 0 },
3500     { "prefetchw",      { Mb }, 0 },
3501     { "prefetchwt1",    { Mb }, 0 },
3502     { "prefetch",       { Mb }, 0 },
3503     { "prefetch",       { Mb }, 0 },
3504     { "prefetch",       { Mb }, 0 },
3505     { "prefetch",       { Mb }, 0 },
3506     { "prefetch",       { Mb }, 0 },
3507   },
3508   /* REG_0F18 */
3509   {
3510     { MOD_TABLE (MOD_0F18_REG_0) },
3511     { MOD_TABLE (MOD_0F18_REG_1) },
3512     { MOD_TABLE (MOD_0F18_REG_2) },
3513     { MOD_TABLE (MOD_0F18_REG_3) },
3514     { MOD_TABLE (MOD_0F18_REG_4) },
3515     { MOD_TABLE (MOD_0F18_REG_5) },
3516     { MOD_TABLE (MOD_0F18_REG_6) },
3517     { MOD_TABLE (MOD_0F18_REG_7) },
3518   },
3519   /* REG_0F71 */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_0F71_REG_2) },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F71_REG_4) },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0F71_REG_6) },
3528   },
3529   /* REG_0F72 */
3530   {
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_0F72_REG_2) },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F72_REG_4) },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_0F72_REG_6) },
3538   },
3539   /* REG_0F73 */
3540   {
3541     { Bad_Opcode },
3542     { Bad_Opcode },
3543     { MOD_TABLE (MOD_0F73_REG_2) },
3544     { MOD_TABLE (MOD_0F73_REG_3) },
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0F73_REG_6) },
3548     { MOD_TABLE (MOD_0F73_REG_7) },
3549   },
3550   /* REG_0FA6 */
3551   {
3552     { "montmul",        { { OP_0f07, 0 } }, 0 },
3553     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3554     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3555   },
3556   /* REG_0FA7 */
3557   {
3558     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3559     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3560     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3561     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3562     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3563     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3564   },
3565   /* REG_0FAE */
3566   {
3567     { MOD_TABLE (MOD_0FAE_REG_0) },
3568     { MOD_TABLE (MOD_0FAE_REG_1) },
3569     { MOD_TABLE (MOD_0FAE_REG_2) },
3570     { MOD_TABLE (MOD_0FAE_REG_3) },
3571     { MOD_TABLE (MOD_0FAE_REG_4) },
3572     { MOD_TABLE (MOD_0FAE_REG_5) },
3573     { MOD_TABLE (MOD_0FAE_REG_6) },
3574     { MOD_TABLE (MOD_0FAE_REG_7) },
3575   },
3576   /* REG_0FBA */
3577   {
3578     { Bad_Opcode },
3579     { Bad_Opcode },
3580     { Bad_Opcode },
3581     { Bad_Opcode },
3582     { "btQ",    { Ev, Ib }, 0 },
3583     { "btsQ",   { Evh1, Ib }, 0 },
3584     { "btrQ",   { Evh1, Ib }, 0 },
3585     { "btcQ",   { Evh1, Ib }, 0 },
3586   },
3587   /* REG_0FC7 */
3588   {
3589     { Bad_Opcode },
3590     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3591     { Bad_Opcode },
3592     { MOD_TABLE (MOD_0FC7_REG_3) },
3593     { MOD_TABLE (MOD_0FC7_REG_4) },
3594     { MOD_TABLE (MOD_0FC7_REG_5) },
3595     { MOD_TABLE (MOD_0FC7_REG_6) },
3596     { MOD_TABLE (MOD_0FC7_REG_7) },
3597   },
3598   /* REG_VEX_0F71 */
3599   {
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3607   },
3608   /* REG_VEX_0F72 */
3609   {
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3617   },
3618   /* REG_VEX_0F73 */
3619   {
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3623     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3624     { Bad_Opcode },
3625     { Bad_Opcode },
3626     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3627     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3628   },
3629   /* REG_VEX_0FAE */
3630   {
3631     { Bad_Opcode },
3632     { Bad_Opcode },
3633     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3634     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3635   },
3636   /* REG_VEX_0F38F3 */
3637   {
3638     { Bad_Opcode },
3639     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3640     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3641     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3642   },
3643   /* REG_XOP_LWPCB */
3644   {
3645     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3646     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3647   },
3648   /* REG_XOP_LWP */
3649   {
3650     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3651     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3652   },
3653   /* REG_XOP_TBM_01 */
3654   {
3655     { Bad_Opcode },
3656     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3657     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3658     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3659     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3660     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3661     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3662     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3663   },
3664   /* REG_XOP_TBM_02 */
3665   {
3666     { Bad_Opcode },
3667     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3668     { Bad_Opcode },
3669     { Bad_Opcode },
3670     { Bad_Opcode },
3671     { Bad_Opcode },
3672     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3673   },
3674 #define NEED_REG_TABLE
3675 #include "i386-dis-evex.h"
3676 #undef NEED_REG_TABLE
3677 };
3678
3679 static const struct dis386 prefix_table[][4] = {
3680   /* PREFIX_90 */
3681   {
3682     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3683     { "pause", { XX }, 0 },
3684     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3685     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3686   },
3687
3688   /* PREFIX_0F10 */
3689   {
3690     { "movups", { XM, EXx }, PREFIX_OPCODE },
3691     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3692     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3693     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F11 */
3697   {
3698     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3699     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3700     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3701     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3702   },
3703
3704   /* PREFIX_0F12 */
3705   {
3706     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3707     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3708     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3709     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3710   },
3711
3712   /* PREFIX_0F16 */
3713   {
3714     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3715     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3716     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F1A */
3720   {
3721     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3722     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3723     { "bndmov", { Gbnd, Ebnd }, 0 },
3724     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3725   },
3726
3727   /* PREFIX_0F1B */
3728   {
3729     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3730     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3731     { "bndmov", { Ebnd, Gbnd }, 0 },
3732     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3733   },
3734
3735   /* PREFIX_0F2A */
3736   {
3737     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3738     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3739     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3740     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3741   },
3742
3743   /* PREFIX_0F2B */
3744   {
3745     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3746     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3747     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3748     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3749   },
3750
3751   /* PREFIX_0F2C */
3752   {
3753     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3755     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F2D */
3760   {
3761     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3762     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3763     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3764     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F2E */
3768   {
3769     { "ucomiss",{ XM, EXd }, 0 },
3770     { Bad_Opcode },
3771     { "ucomisd",{ XM, EXq }, 0 },
3772   },
3773
3774   /* PREFIX_0F2F */
3775   {
3776     { "comiss", { XM, EXd }, 0 },
3777     { Bad_Opcode },
3778     { "comisd", { XM, EXq }, 0 },
3779   },
3780
3781   /* PREFIX_0F51 */
3782   {
3783     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3784     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3785     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3786     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F52 */
3790   {
3791     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3792     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F53 */
3796   {
3797     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3798     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F58 */
3802   {
3803     { "addps", { XM, EXx }, PREFIX_OPCODE },
3804     { "addss", { XM, EXd }, PREFIX_OPCODE },
3805     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3806     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F59 */
3810   {
3811     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3812     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3813     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3814     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F5A */
3818   {
3819     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3820     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3821     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F5B */
3826   {
3827     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3828     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3829     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F5C */
3833   {
3834     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3835     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3836     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3837     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F5D */
3841   {
3842     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3843     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3844     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3845     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F5E */
3849   {
3850     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3851     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3852     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3853     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F5F */
3857   {
3858     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3859     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3860     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3861     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F60 */
3865   {
3866     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3867     { Bad_Opcode },
3868     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F61 */
3872   {
3873     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3874     { Bad_Opcode },
3875     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F62 */
3879   {
3880     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3881     { Bad_Opcode },
3882     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F6C */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0F6D */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0F6F */
3900   {
3901     { "movq",   { MX, EM }, PREFIX_OPCODE },
3902     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3903     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F70 */
3907   {
3908     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3909     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3910     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3911     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3912   },
3913
3914   /* PREFIX_0F73_REG_3 */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "psrldq", { XS, Ib }, 0 },
3919   },
3920
3921   /* PREFIX_0F73_REG_7 */
3922   {
3923     { Bad_Opcode },
3924     { Bad_Opcode },
3925     { "pslldq", { XS, Ib }, 0 },
3926   },
3927
3928   /* PREFIX_0F78 */
3929   {
3930     {"vmread",  { Em, Gm }, 0 },
3931     { Bad_Opcode },
3932     {"extrq",   { XS, Ib, Ib }, 0 },
3933     {"insertq", { XM, XS, Ib, Ib }, 0 },
3934   },
3935
3936   /* PREFIX_0F79 */
3937   {
3938     {"vmwrite", { Gm, Em }, 0 },
3939     { Bad_Opcode },
3940     {"extrq",   { XM, XS }, 0 },
3941     {"insertq", { XM, XS }, 0 },
3942   },
3943
3944   /* PREFIX_0F7C */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F7D */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3957     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F7E */
3961   {
3962     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3963     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3964     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3965   },
3966
3967   /* PREFIX_0F7F */
3968   {
3969     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3970     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3971     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0FAE_REG_0 */
3975   {
3976     { Bad_Opcode },
3977     { "rdfsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_1 */
3981   {
3982     { Bad_Opcode },
3983     { "rdgsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_2 */
3987   {
3988     { Bad_Opcode },
3989     { "wrfsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_0FAE_REG_3 */
3993   {
3994     { Bad_Opcode },
3995     { "wrgsbase", { Ev }, 0 },
3996   },
3997
3998   /* PREFIX_0FAE_REG_6 */
3999   {
4000     { "xsaveopt",      { FXSAVE }, 0 },
4001     { Bad_Opcode },
4002     { "clwb",   { Mb }, 0 },
4003   },
4004
4005   /* PREFIX_0FAE_REG_7 */
4006   {
4007     { "clflush",        { Mb }, 0 },
4008     { Bad_Opcode },
4009     { "clflushopt",     { Mb }, 0 },
4010   },
4011
4012   /* PREFIX_RM_0_0FAE_REG_7 */
4013   {
4014     { "sfence",         { Skip_MODRM }, 0 },
4015     { Bad_Opcode },
4016     { "pcommit",                { Skip_MODRM }, 0 },
4017   },
4018
4019   /* PREFIX_0FB8 */
4020   {
4021     { Bad_Opcode },
4022     { "popcntS", { Gv, Ev }, 0 },
4023   },
4024
4025   /* PREFIX_0FBC */
4026   {
4027     { "bsfS",   { Gv, Ev }, 0 },
4028     { "tzcntS", { Gv, Ev }, 0 },
4029     { "bsfS",   { Gv, Ev }, 0 },
4030   },
4031
4032   /* PREFIX_0FBD */
4033   {
4034     { "bsrS",   { Gv, Ev }, 0 },
4035     { "lzcntS", { Gv, Ev }, 0 },
4036     { "bsrS",   { Gv, Ev }, 0 },
4037   },
4038
4039   /* PREFIX_0FC2 */
4040   {
4041     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4042     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4043     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4044     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0FC3 */
4048   {
4049     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4050   },
4051
4052   /* PREFIX_MOD_0_0FC7_REG_6 */
4053   {
4054     { "vmptrld",{ Mq }, 0 },
4055     { "vmxon",  { Mq }, 0 },
4056     { "vmclear",{ Mq }, 0 },
4057   },
4058
4059   /* PREFIX_MOD_3_0FC7_REG_6 */
4060   {
4061     { "rdrand", { Ev }, 0 },
4062     { Bad_Opcode },
4063     { "rdrand", { Ev }, 0 }
4064   },
4065
4066   /* PREFIX_MOD_3_0FC7_REG_7 */
4067   {
4068     { "rdseed", { Ev }, 0 },
4069     { Bad_Opcode },
4070     { "rdseed", { Ev }, 0 },
4071   },
4072
4073   /* PREFIX_0FD0 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "addsubpd", { XM, EXx }, 0 },
4078     { "addsubps", { XM, EXx }, 0 },
4079   },
4080
4081   /* PREFIX_0FD6 */
4082   {
4083     { Bad_Opcode },
4084     { "movq2dq",{ XM, MS }, 0 },
4085     { "movq",   { EXqS, XM }, 0 },
4086     { "movdq2q",{ MX, XS }, 0 },
4087   },
4088
4089   /* PREFIX_0FE6 */
4090   {
4091     { Bad_Opcode },
4092     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4093     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4094     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4095   },
4096
4097   /* PREFIX_0FE7 */
4098   {
4099     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4100     { Bad_Opcode },
4101     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4102   },
4103
4104   /* PREFIX_0FF0 */
4105   {
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4110   },
4111
4112   /* PREFIX_0FF7 */
4113   {
4114     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4115     { Bad_Opcode },
4116     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F3810 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F3814 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0F3815 */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F3817 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0F3820 */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4152   },
4153
4154   /* PREFIX_0F3821 */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0F3822 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4166   },
4167
4168   /* PREFIX_0F3823 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0F3824 */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_0F3825 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_0F3828 */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F3829 */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F382A */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4208   },
4209
4210   /* PREFIX_0F382B */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3830 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3831 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3832 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3833 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3834 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F3835 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3837 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F3838 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F3839 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F383A */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F383B */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F383C */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F383D */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F383E */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F383F */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3840 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3841 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3880 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3881 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3882 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F38C8 */
4358   {
4359     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38C9 */
4363   {
4364     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F38CA */
4368   {
4369     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F38CB */
4373   {
4374     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38CC */
4378   {
4379     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38CD */
4383   {
4384     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38DB */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38DC */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F38DD */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F38DE */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F38DF */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F38F0 */
4423   {
4424     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4425     { Bad_Opcode },
4426     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4427     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F38F1 */
4431   {
4432     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4433     { Bad_Opcode },
4434     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4435     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F38F6 */
4439   {
4440     { Bad_Opcode },
4441     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4442     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4443     { Bad_Opcode },
4444   },
4445
4446   /* PREFIX_0F3A08 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F3A09 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A0A */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A0B */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A0C */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A0D */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3A0E */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A14 */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A15 */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3A16 */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3A17 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3A20 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A21 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A22 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A40 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A41 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A42 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A44 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A60 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A61 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A62 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A63 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3ACC */
4601   {
4602     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F3ADF */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_VEX_0F10 */
4613   {
4614     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4615     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4616     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4617     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4618   },
4619
4620   /* PREFIX_VEX_0F11 */
4621   {
4622     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4623     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4624     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4625     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4626   },
4627
4628   /* PREFIX_VEX_0F12 */
4629   {
4630     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4631     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4632     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4633     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4634   },
4635
4636   /* PREFIX_VEX_0F16 */
4637   {
4638     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4639     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4640     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4641   },
4642
4643   /* PREFIX_VEX_0F2A */
4644   {
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4647     { Bad_Opcode },
4648     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4649   },
4650
4651   /* PREFIX_VEX_0F2C */
4652   {
4653     { Bad_Opcode },
4654     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4657   },
4658
4659   /* PREFIX_VEX_0F2D */
4660   {
4661     { Bad_Opcode },
4662     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4663     { Bad_Opcode },
4664     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4665   },
4666
4667   /* PREFIX_VEX_0F2E */
4668   {
4669     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4670     { Bad_Opcode },
4671     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4672   },
4673
4674   /* PREFIX_VEX_0F2F */
4675   {
4676     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4677     { Bad_Opcode },
4678     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4679   },
4680
4681   /* PREFIX_VEX_0F41 */
4682   {
4683     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4686   },
4687
4688   /* PREFIX_VEX_0F42 */
4689   {
4690     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4691     { Bad_Opcode },
4692     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4693   },
4694
4695   /* PREFIX_VEX_0F44 */
4696   {
4697     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4698     { Bad_Opcode },
4699     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4700   },
4701
4702   /* PREFIX_VEX_0F45 */
4703   {
4704     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4705     { Bad_Opcode },
4706     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4707   },
4708
4709   /* PREFIX_VEX_0F46 */
4710   {
4711     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4712     { Bad_Opcode },
4713     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4714   },
4715
4716   /* PREFIX_VEX_0F47 */
4717   {
4718     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4721   },
4722
4723   /* PREFIX_VEX_0F4A */
4724   {
4725     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4726     { Bad_Opcode },
4727     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4728   },
4729
4730   /* PREFIX_VEX_0F4B */
4731   {
4732     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4735   },
4736
4737   /* PREFIX_VEX_0F51 */
4738   {
4739     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4740     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4741     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4742     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4743   },
4744
4745   /* PREFIX_VEX_0F52 */
4746   {
4747     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4748     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4749   },
4750
4751   /* PREFIX_VEX_0F53 */
4752   {
4753     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4754     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4755   },
4756
4757   /* PREFIX_VEX_0F58 */
4758   {
4759     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4760     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4761     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4762     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4763   },
4764
4765   /* PREFIX_VEX_0F59 */
4766   {
4767     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4769     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4770     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4771   },
4772
4773   /* PREFIX_VEX_0F5A */
4774   {
4775     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4777     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4778     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4779   },
4780
4781   /* PREFIX_VEX_0F5B */
4782   {
4783     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4784     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4785     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F5C */
4789   {
4790     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4791     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4792     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4793     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4794   },
4795
4796   /* PREFIX_VEX_0F5D */
4797   {
4798     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4799     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4800     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4801     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4802   },
4803
4804   /* PREFIX_VEX_0F5E */
4805   {
4806     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4807     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4808     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4809     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4810   },
4811
4812   /* PREFIX_VEX_0F5F */
4813   {
4814     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4815     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4816     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4817     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4818   },
4819
4820   /* PREFIX_VEX_0F60 */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F61 */
4828   {
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4832   },
4833
4834   /* PREFIX_VEX_0F62 */
4835   {
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4839   },
4840
4841   /* PREFIX_VEX_0F63 */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4846   },
4847
4848   /* PREFIX_VEX_0F64 */
4849   {
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4853   },
4854
4855   /* PREFIX_VEX_0F65 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4860   },
4861
4862   /* PREFIX_VEX_0F66 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4867   },
4868
4869   /* PREFIX_VEX_0F67 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4874   },
4875
4876   /* PREFIX_VEX_0F68 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4881   },
4882
4883   /* PREFIX_VEX_0F69 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4888   },
4889
4890   /* PREFIX_VEX_0F6A */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4895   },
4896
4897   /* PREFIX_VEX_0F6B */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F6C */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F6D */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F6E */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F6F */
4926   {
4927     { Bad_Opcode },
4928     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4929     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F70 */
4933   {
4934     { Bad_Opcode },
4935     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4936     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4937     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4938   },
4939
4940   /* PREFIX_VEX_0F71_REG_2 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F71_REG_4 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F71_REG_6 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F72_REG_2 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F72_REG_4 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F72_REG_6 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F73_REG_2 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0F73_REG_3 */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F73_REG_6 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F73_REG_7 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5008   },
5009
5010   /* PREFIX_VEX_0F74 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5015   },
5016
5017   /* PREFIX_VEX_0F75 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5022   },
5023
5024   /* PREFIX_VEX_0F76 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5029   },
5030
5031   /* PREFIX_VEX_0F77 */
5032   {
5033     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5034   },
5035
5036   /* PREFIX_VEX_0F7C */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5041     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5042   },
5043
5044   /* PREFIX_VEX_0F7D */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5049     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5050   },
5051
5052   /* PREFIX_VEX_0F7E */
5053   {
5054     { Bad_Opcode },
5055     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5056     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0F7F */
5060   {
5061     { Bad_Opcode },
5062     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5063     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5064   },
5065
5066   /* PREFIX_VEX_0F90 */
5067   {
5068     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5069     { Bad_Opcode },
5070     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_0F91 */
5074   {
5075     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5076     { Bad_Opcode },
5077     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F92 */
5081   {
5082     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5085     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5086   },
5087
5088   /* PREFIX_VEX_0F93 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5093     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5094   },
5095
5096   /* PREFIX_VEX_0F98 */
5097   {
5098     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0F99 */
5104   {
5105     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5106     { Bad_Opcode },
5107     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_0FC2 */
5111   {
5112     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5113     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5114     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5115     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5116   },
5117
5118   /* PREFIX_VEX_0FC4 */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0FC5 */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0FD0 */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5137     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5138   },
5139
5140   /* PREFIX_VEX_0FD1 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0FD2 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0FD3 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0FD4 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0FD5 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0FD6 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0FD7 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5187   },
5188
5189   /* PREFIX_VEX_0FD8 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0FD9 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0FDA */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FDB */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0FDC */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FDD */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0FDE */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FDF */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0FE0 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0FE1 */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5257   },
5258
5259   /* PREFIX_VEX_0FE2 */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5264   },
5265
5266   /* PREFIX_VEX_0FE3 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0FE4 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0FE5 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0FE6 */
5288   {
5289     { Bad_Opcode },
5290     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5291     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5292     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5293   },
5294
5295   /* PREFIX_VEX_0FE7 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FE8 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FE9 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FEA */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FEB */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FEC */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FED */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FEE */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FEF */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FF0 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5364   },
5365
5366   /* PREFIX_VEX_0FF1 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0FF2 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0FF3 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FF4 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0FF5 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FF6 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FF7 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FF8 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FF9 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0FFA */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FFB */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0FFC */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0FFD */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0FFE */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F3800 */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F3801 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F3802 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F3803 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F3804 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3805 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3806 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F3807 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0F3808 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0F3809 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0F380A */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F380B */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0F380C */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F380D */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F380E */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0F380F */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F3813 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F3816 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F3817 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3818 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F3819 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F381A */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F381C */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F381D */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F381E */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3820 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F3821 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F3822 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5658   },
5659
5660   /* PREFIX_VEX_0F3823 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3824 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F3825 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3828 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F3829 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F382A */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F382B */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F382C */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F382D */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F382E */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5728   },
5729
5730   /* PREFIX_VEX_0F382F */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F3830 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F3831 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F3832 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3833 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F3834 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F3835 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F3836 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F3837 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3838 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F3839 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F383A */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F383B */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F383C */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F383D */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F383E */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F383F */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F3840 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3841 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F3845 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3846 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F3847 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F3858 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F3859 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F385A */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F3878 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F3879 */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F388C */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F388E */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3890 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5938   },
5939
5940   /* PREFIX_VEX_0F3891 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5945   },
5946
5947   /* PREFIX_VEX_0F3892 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5952   },
5953
5954   /* PREFIX_VEX_0F3893 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5959   },
5960
5961   /* PREFIX_VEX_0F3896 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5966   },
5967
5968   /* PREFIX_VEX_0F3897 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5973   },
5974
5975   /* PREFIX_VEX_0F3898 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5980   },
5981
5982   /* PREFIX_VEX_0F3899 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5987   },
5988
5989   /* PREFIX_VEX_0F389A */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5994   },
5995
5996   /* PREFIX_VEX_0F389B */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6001   },
6002
6003   /* PREFIX_VEX_0F389C */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6008   },
6009
6010   /* PREFIX_VEX_0F389D */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F389E */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F389F */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F38A6 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6036     { Bad_Opcode },
6037   },
6038
6039   /* PREFIX_VEX_0F38A7 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F38A8 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F38A9 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F38AA */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F38AB */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F38AC */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F38AD */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38AE */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38AF */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F38B6 */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38B7 */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38B8 */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38B9 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38BA */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38BB */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F38BC */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6149   },
6150
6151   /* PREFIX_VEX_0F38BD */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F38BE */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F38BF */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F38DB */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6177   },
6178
6179   /* PREFIX_VEX_0F38DC */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6184   },
6185
6186   /* PREFIX_VEX_0F38DD */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6191   },
6192
6193   /* PREFIX_VEX_0F38DE */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6198   },
6199
6200   /* PREFIX_VEX_0F38DF */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6205   },
6206
6207   /* PREFIX_VEX_0F38F2 */
6208   {
6209     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6210   },
6211
6212   /* PREFIX_VEX_0F38F3_REG_1 */
6213   {
6214     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6215   },
6216
6217   /* PREFIX_VEX_0F38F3_REG_2 */
6218   {
6219     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6220   },
6221
6222   /* PREFIX_VEX_0F38F3_REG_3 */
6223   {
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6225   },
6226
6227   /* PREFIX_VEX_0F38F5 */
6228   {
6229     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6230     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6231     { Bad_Opcode },
6232     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6233   },
6234
6235   /* PREFIX_VEX_0F38F6 */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6241   },
6242
6243   /* PREFIX_VEX_0F38F7 */
6244   {
6245     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6246     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6247     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6248     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6249   },
6250
6251   /* PREFIX_VEX_0F3A00 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6256   },
6257
6258   /* PREFIX_VEX_0F3A01 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F3A02 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6270   },
6271
6272   /* PREFIX_VEX_0F3A04 */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6277   },
6278
6279   /* PREFIX_VEX_0F3A05 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A06 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A08 */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6298   },
6299
6300   /* PREFIX_VEX_0F3A09 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6305   },
6306
6307   /* PREFIX_VEX_0F3A0A */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A0B */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A0C */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A0D */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A0E */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A0F */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A14 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A15 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A16 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6368   },
6369
6370   /* PREFIX_VEX_0F3A17 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6375   },
6376
6377   /* PREFIX_VEX_0F3A18 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A19 */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6389   },
6390
6391   /* PREFIX_VEX_0F3A1D */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6396   },
6397
6398   /* PREFIX_VEX_0F3A20 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A21 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6410   },
6411
6412   /* PREFIX_VEX_0F3A22 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A30 */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A31 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A32 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A33 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A38 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A39 */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A40 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A41 */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A42 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A44 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A46 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A48 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A49 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A4A */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A4B */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A4C */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A5C */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6536   },
6537
6538   /* PREFIX_VEX_0F3A5D */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6543   },
6544
6545   /* PREFIX_VEX_0F3A5E */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6550   },
6551
6552   /* PREFIX_VEX_0F3A5F */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6557   },
6558
6559   /* PREFIX_VEX_0F3A60 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6564     { Bad_Opcode },
6565   },
6566
6567   /* PREFIX_VEX_0F3A61 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A62 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A63 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A68 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6593   },
6594
6595   /* PREFIX_VEX_0F3A69 */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6600   },
6601
6602   /* PREFIX_VEX_0F3A6A */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A6B */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A6C */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A6D */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A6E */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A6F */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3A78 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6649   },
6650
6651   /* PREFIX_VEX_0F3A79 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6656   },
6657
6658   /* PREFIX_VEX_0F3A7A */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A7B */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6670   },
6671
6672   /* PREFIX_VEX_0F3A7C */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6677     { Bad_Opcode },
6678   },
6679
6680   /* PREFIX_VEX_0F3A7D */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A7E */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A7F */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3ADF */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3AF0 */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6714   },
6715
6716 #define NEED_PREFIX_TABLE
6717 #include "i386-dis-evex.h"
6718 #undef NEED_PREFIX_TABLE
6719 };
6720
6721 static const struct dis386 x86_64_table[][2] = {
6722   /* X86_64_06 */
6723   {
6724     { "pushP", { es }, 0 },
6725   },
6726
6727   /* X86_64_07 */
6728   {
6729     { "popP", { es }, 0 },
6730   },
6731
6732   /* X86_64_0D */
6733   {
6734     { "pushP", { cs }, 0 },
6735   },
6736
6737   /* X86_64_16 */
6738   {
6739     { "pushP", { ss }, 0 },
6740   },
6741
6742   /* X86_64_17 */
6743   {
6744     { "popP", { ss }, 0 },
6745   },
6746
6747   /* X86_64_1E */
6748   {
6749     { "pushP", { ds }, 0 },
6750   },
6751
6752   /* X86_64_1F */
6753   {
6754     { "popP", { ds }, 0 },
6755   },
6756
6757   /* X86_64_27 */
6758   {
6759     { "daa", { XX }, 0 },
6760   },
6761
6762   /* X86_64_2F */
6763   {
6764     { "das", { XX }, 0 },
6765   },
6766
6767   /* X86_64_37 */
6768   {
6769     { "aaa", { XX }, 0 },
6770   },
6771
6772   /* X86_64_3F */
6773   {
6774     { "aas", { XX }, 0 },
6775   },
6776
6777   /* X86_64_60 */
6778   {
6779     { "pushaP", { XX }, 0 },
6780   },
6781
6782   /* X86_64_61 */
6783   {
6784     { "popaP", { XX }, 0 },
6785   },
6786
6787   /* X86_64_62 */
6788   {
6789     { MOD_TABLE (MOD_62_32BIT) },
6790     { EVEX_TABLE (EVEX_0F) },
6791   },
6792
6793   /* X86_64_63 */
6794   {
6795     { "arpl", { Ew, Gw }, 0 },
6796     { "movs{lq|xd}", { Gv, Ed }, 0 },
6797   },
6798
6799   /* X86_64_6D */
6800   {
6801     { "ins{R|}", { Yzr, indirDX }, 0 },
6802     { "ins{G|}", { Yzr, indirDX }, 0 },
6803   },
6804
6805   /* X86_64_6F */
6806   {
6807     { "outs{R|}", { indirDXr, Xz }, 0 },
6808     { "outs{G|}", { indirDXr, Xz }, 0 },
6809   },
6810
6811   /* X86_64_9A */
6812   {
6813     { "Jcall{T|}", { Ap }, 0 },
6814   },
6815
6816   /* X86_64_C4 */
6817   {
6818     { MOD_TABLE (MOD_C4_32BIT) },
6819     { VEX_C4_TABLE (VEX_0F) },
6820   },
6821
6822   /* X86_64_C5 */
6823   {
6824     { MOD_TABLE (MOD_C5_32BIT) },
6825     { VEX_C5_TABLE (VEX_0F) },
6826   },
6827
6828   /* X86_64_CE */
6829   {
6830     { "into", { XX }, 0 },
6831   },
6832
6833   /* X86_64_D4 */
6834   {
6835     { "aam", { Ib }, 0 },
6836   },
6837
6838   /* X86_64_D5 */
6839   {
6840     { "aad", { Ib }, 0 },
6841   },
6842
6843   /* X86_64_EA */
6844   {
6845     { "Jjmp{T|}", { Ap }, 0 },
6846   },
6847
6848   /* X86_64_0F01_REG_0 */
6849   {
6850     { "sgdt{Q|IQ}", { M }, 0 },
6851     { "sgdt", { M }, 0 },
6852   },
6853
6854   /* X86_64_0F01_REG_1 */
6855   {
6856     { "sidt{Q|IQ}", { M }, 0 },
6857     { "sidt", { M }, 0 },
6858   },
6859
6860   /* X86_64_0F01_REG_2 */
6861   {
6862     { "lgdt{Q|Q}", { M }, 0 },
6863     { "lgdt", { M }, 0 },
6864   },
6865
6866   /* X86_64_0F01_REG_3 */
6867   {
6868     { "lidt{Q|Q}", { M }, 0 },
6869     { "lidt", { M }, 0 },
6870   },
6871 };
6872
6873 static const struct dis386 three_byte_table[][256] = {
6874
6875   /* THREE_BYTE_0F38 */
6876   {
6877     /* 00 */
6878     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6879     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6880     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6881     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6882     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6883     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6884     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6885     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6886     /* 08 */
6887     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6888     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6889     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6890     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     /* 10 */
6896     { PREFIX_TABLE (PREFIX_0F3810) },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { PREFIX_TABLE (PREFIX_0F3814) },
6901     { PREFIX_TABLE (PREFIX_0F3815) },
6902     { Bad_Opcode },
6903     { PREFIX_TABLE (PREFIX_0F3817) },
6904     /* 18 */
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6910     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6911     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6912     { Bad_Opcode },
6913     /* 20 */
6914     { PREFIX_TABLE (PREFIX_0F3820) },
6915     { PREFIX_TABLE (PREFIX_0F3821) },
6916     { PREFIX_TABLE (PREFIX_0F3822) },
6917     { PREFIX_TABLE (PREFIX_0F3823) },
6918     { PREFIX_TABLE (PREFIX_0F3824) },
6919     { PREFIX_TABLE (PREFIX_0F3825) },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     /* 28 */
6923     { PREFIX_TABLE (PREFIX_0F3828) },
6924     { PREFIX_TABLE (PREFIX_0F3829) },
6925     { PREFIX_TABLE (PREFIX_0F382A) },
6926     { PREFIX_TABLE (PREFIX_0F382B) },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     /* 30 */
6932     { PREFIX_TABLE (PREFIX_0F3830) },
6933     { PREFIX_TABLE (PREFIX_0F3831) },
6934     { PREFIX_TABLE (PREFIX_0F3832) },
6935     { PREFIX_TABLE (PREFIX_0F3833) },
6936     { PREFIX_TABLE (PREFIX_0F3834) },
6937     { PREFIX_TABLE (PREFIX_0F3835) },
6938     { Bad_Opcode },
6939     { PREFIX_TABLE (PREFIX_0F3837) },
6940     /* 38 */
6941     { PREFIX_TABLE (PREFIX_0F3838) },
6942     { PREFIX_TABLE (PREFIX_0F3839) },
6943     { PREFIX_TABLE (PREFIX_0F383A) },
6944     { PREFIX_TABLE (PREFIX_0F383B) },
6945     { PREFIX_TABLE (PREFIX_0F383C) },
6946     { PREFIX_TABLE (PREFIX_0F383D) },
6947     { PREFIX_TABLE (PREFIX_0F383E) },
6948     { PREFIX_TABLE (PREFIX_0F383F) },
6949     /* 40 */
6950     { PREFIX_TABLE (PREFIX_0F3840) },
6951     { PREFIX_TABLE (PREFIX_0F3841) },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     /* 48 */
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     /* 50 */
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     /* 58 */
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 60 */
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     /* 68 */
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     /* 70 */
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 78 */
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 80 */
7022     { PREFIX_TABLE (PREFIX_0F3880) },
7023     { PREFIX_TABLE (PREFIX_0F3881) },
7024     { PREFIX_TABLE (PREFIX_0F3882) },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* 88 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 90 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 98 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* a0 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* a8 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* b0 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* b8 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* c0 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* c8 */
7103     { PREFIX_TABLE (PREFIX_0F38C8) },
7104     { PREFIX_TABLE (PREFIX_0F38C9) },
7105     { PREFIX_TABLE (PREFIX_0F38CA) },
7106     { PREFIX_TABLE (PREFIX_0F38CB) },
7107     { PREFIX_TABLE (PREFIX_0F38CC) },
7108     { PREFIX_TABLE (PREFIX_0F38CD) },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* d0 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* d8 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { PREFIX_TABLE (PREFIX_0F38DB) },
7125     { PREFIX_TABLE (PREFIX_0F38DC) },
7126     { PREFIX_TABLE (PREFIX_0F38DD) },
7127     { PREFIX_TABLE (PREFIX_0F38DE) },
7128     { PREFIX_TABLE (PREFIX_0F38DF) },
7129     /* e0 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* e8 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* f0 */
7148     { PREFIX_TABLE (PREFIX_0F38F0) },
7149     { PREFIX_TABLE (PREFIX_0F38F1) },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { PREFIX_TABLE (PREFIX_0F38F6) },
7155     { Bad_Opcode },
7156     /* f8 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165   },
7166   /* THREE_BYTE_0F3A */
7167   {
7168     /* 00 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* 08 */
7178     { PREFIX_TABLE (PREFIX_0F3A08) },
7179     { PREFIX_TABLE (PREFIX_0F3A09) },
7180     { PREFIX_TABLE (PREFIX_0F3A0A) },
7181     { PREFIX_TABLE (PREFIX_0F3A0B) },
7182     { PREFIX_TABLE (PREFIX_0F3A0C) },
7183     { PREFIX_TABLE (PREFIX_0F3A0D) },
7184     { PREFIX_TABLE (PREFIX_0F3A0E) },
7185     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7186     /* 10 */
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { PREFIX_TABLE (PREFIX_0F3A14) },
7192     { PREFIX_TABLE (PREFIX_0F3A15) },
7193     { PREFIX_TABLE (PREFIX_0F3A16) },
7194     { PREFIX_TABLE (PREFIX_0F3A17) },
7195     /* 18 */
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* 20 */
7205     { PREFIX_TABLE (PREFIX_0F3A20) },
7206     { PREFIX_TABLE (PREFIX_0F3A21) },
7207     { PREFIX_TABLE (PREFIX_0F3A22) },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* 28 */
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     /* 30 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* 38 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     /* 40 */
7241     { PREFIX_TABLE (PREFIX_0F3A40) },
7242     { PREFIX_TABLE (PREFIX_0F3A41) },
7243     { PREFIX_TABLE (PREFIX_0F3A42) },
7244     { Bad_Opcode },
7245     { PREFIX_TABLE (PREFIX_0F3A44) },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     /* 48 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     /* 50 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* 58 */
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* 60 */
7277     { PREFIX_TABLE (PREFIX_0F3A60) },
7278     { PREFIX_TABLE (PREFIX_0F3A61) },
7279     { PREFIX_TABLE (PREFIX_0F3A62) },
7280     { PREFIX_TABLE (PREFIX_0F3A63) },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* 68 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 70 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* 78 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* 80 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 88 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 90 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 98 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* a0 */
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* a8 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* b0 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* b8 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* c0 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* c8 */
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { PREFIX_TABLE (PREFIX_0F3ACC) },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* d0 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* d8 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { PREFIX_TABLE (PREFIX_0F3ADF) },
7420     /* e0 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* e8 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* f0 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* f8 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456   },
7457
7458   /* THREE_BYTE_0F7A */
7459   {
7460     /* 00 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 08 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 10 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 18 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 20 */
7497     { "ptest",          { XX }, PREFIX_OPCODE },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 28 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 30 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 38 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 40 */
7533     { Bad_Opcode },
7534     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7535     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7536     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7540     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7541     /* 48 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 50 */
7551     { Bad_Opcode },
7552     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7553     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7554     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7558     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7559     /* 58 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 60 */
7569     { Bad_Opcode },
7570     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7571     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7572     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 68 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 70 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 78 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* 80 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* 88 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* 90 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* 98 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* a0 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* a8 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* b0 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* b8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* c0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* c8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* d0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* d8 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* e0 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* e8 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     /* f0 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* f8 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748   },
7749 };
7750
7751 static const struct dis386 xop_table[][256] = {
7752   /* XOP_08 */
7753   {
7754     /* 00 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* 08 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* 10 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* 18 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     /* 20 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* 28 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* 30 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* 38 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     /* 40 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 48 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 50 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 58 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 60 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 68 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 70 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 78 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 80 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7905     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7906     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7907     /* 88 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7915     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7916     /* 90 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7923     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7924     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7925     /* 98 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7933     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7934     /* a0 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7938     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7942     { Bad_Opcode },
7943     /* a8 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* b0 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7960     { Bad_Opcode },
7961     /* b8 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* c0 */
7971     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7972     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7973     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7974     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* c8 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7985     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7986     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7987     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7988     /* d0 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* d8 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* e0 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* e8 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8021     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8022     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8023     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8024     /* f0 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* f8 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042   },
8043   /* XOP_09 */
8044   {
8045     /* 00 */
8046     { Bad_Opcode },
8047     { REG_TABLE (REG_XOP_TBM_01) },
8048     { REG_TABLE (REG_XOP_TBM_02) },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* 08 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* 10 */
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { REG_TABLE (REG_XOP_LWPCB) },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* 18 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* 20 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* 28 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* 30 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* 38 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* 40 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* 48 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 50 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 58 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 60 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 68 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 70 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 78 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 80 */
8190     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8191     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8192     { "vfrczss",        { XM, EXd }, 0 },
8193     { "vfrczsd",        { XM, EXq }, 0 },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 88 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 90 */
8208     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8209     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8211     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8213     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8214     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8215     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8216     /* 98 */
8217     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8218     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8219     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8220     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* a0 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* a8 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* b0 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* b8 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* c0 */
8262     { Bad_Opcode },
8263     { "vphaddbw",       { XM, EXxmm }, 0 },
8264     { "vphaddbd",       { XM, EXxmm }, 0 },
8265     { "vphaddbq",       { XM, EXxmm }, 0 },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { "vphaddwd",       { XM, EXxmm }, 0 },
8269     { "vphaddwq",       { XM, EXxmm }, 0 },
8270     /* c8 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { "vphadddq",       { XM, EXxmm }, 0 },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* d0 */
8280     { Bad_Opcode },
8281     { "vphaddubw",      { XM, EXxmm }, 0 },
8282     { "vphaddubd",      { XM, EXxmm }, 0 },
8283     { "vphaddubq",      { XM, EXxmm }, 0 },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { "vphadduwd",      { XM, EXxmm }, 0 },
8287     { "vphadduwq",      { XM, EXxmm }, 0 },
8288     /* d8 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { "vphaddudq",      { XM, EXxmm }, 0 },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* e0 */
8298     { Bad_Opcode },
8299     { "vphsubbw",       { XM, EXxmm }, 0 },
8300     { "vphsubwd",       { XM, EXxmm }, 0 },
8301     { "vphsubdq",       { XM, EXxmm }, 0 },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* e8 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* f0 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* f8 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333   },
8334   /* XOP_0A */
8335   {
8336     /* 00 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 08 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 10 */
8355     { "bextr",  { Gv, Ev, Iq }, 0 },
8356     { Bad_Opcode },
8357     { REG_TABLE (REG_XOP_LWP) },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 18 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 20 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* 28 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 30 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* 38 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* 40 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* 48 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* 50 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* 58 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 60 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 68 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* 70 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 78 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* 80 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* 88 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* 90 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* 98 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* a0 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* a8 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* b0 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     /* b8 */
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     /* c0 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* c8 */
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     /* d0 */
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     /* d8 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     /* e0 */
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     /* e8 */
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     /* f0 */
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* f8 */
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624   },
8625 };
8626
8627 static const struct dis386 vex_table[][256] = {
8628   /* VEX_0F */
8629   {
8630     /* 00 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* 08 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* 10 */
8649     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8652     { MOD_TABLE (MOD_VEX_0F13) },
8653     { VEX_W_TABLE (VEX_W_0F14) },
8654     { VEX_W_TABLE (VEX_W_0F15) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8656     { MOD_TABLE (MOD_VEX_0F17) },
8657     /* 18 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* 20 */
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     /* 28 */
8676     { VEX_W_TABLE (VEX_W_0F28) },
8677     { VEX_W_TABLE (VEX_W_0F29) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8679     { MOD_TABLE (MOD_VEX_0F2B) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8684     /* 30 */
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     /* 38 */
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     /* 40 */
8703     { Bad_Opcode },
8704     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8706     { Bad_Opcode },
8707     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8711     /* 48 */
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     /* 50 */
8721     { MOD_TABLE (MOD_VEX_0F50) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8725     { "vandpX",         { XM, Vex, EXx }, 0 },
8726     { "vandnpX",        { XM, Vex, EXx }, 0 },
8727     { "vorpX",          { XM, Vex, EXx }, 0 },
8728     { "vxorpX",         { XM, Vex, EXx }, 0 },
8729     /* 58 */
8730     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8738     /* 60 */
8739     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8747     /* 68 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8756     /* 70 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8758     { REG_TABLE (REG_VEX_0F71) },
8759     { REG_TABLE (REG_VEX_0F72) },
8760     { REG_TABLE (REG_VEX_0F73) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8765     /* 78 */
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8774     /* 80 */
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     /* 88 */
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     /* 90 */
8793     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 98 */
8802     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* a0 */
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* a8 */
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { REG_TABLE (REG_VEX_0FAE) },
8827     { Bad_Opcode },
8828     /* b0 */
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* b8 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* c0 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8850     { Bad_Opcode },
8851     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8853     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8854     { Bad_Opcode },
8855     /* c8 */
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* d0 */
8865     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8873     /* d8 */
8874     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8882     /* e0 */
8883     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8891     /* e8 */
8892     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8900     /* f0 */
8901     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8909     /* f8 */
8910     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8915     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8916     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8917     { Bad_Opcode },
8918   },
8919   /* VEX_0F38 */
8920   {
8921     /* 00 */
8922     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8930     /* 08 */
8931     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8939     /* 10 */
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8948     /* 18 */
8949     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8952     { Bad_Opcode },
8953     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8956     { Bad_Opcode },
8957     /* 20 */
8958     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     /* 28 */
8967     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8975     /* 30 */
8976     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8984     /* 38 */
8985     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8993     /* 40 */
8994     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9002     /* 48 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     /* 50 */
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     /* 58 */
9021     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* 60 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 68 */
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 70 */
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 78 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     /* 80 */
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     /* 88 */
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9080     { Bad_Opcode },
9081     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9082     { Bad_Opcode },
9083     /* 90 */
9084     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9092     /* 98 */
9093     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9101     /* a0 */
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9110     /* a8 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9119     /* b0 */
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9128     /* b8 */
9129     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9137     /* c0 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* c8 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* d0 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* d8 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9173     /* e0 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* e8 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     /* f0 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9195     { REG_TABLE (REG_VEX_0F38F3) },
9196     { Bad_Opcode },
9197     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9200     /* f8 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209   },
9210   /* VEX_0F3A */
9211   {
9212     /* 00 */
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9216     { Bad_Opcode },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9220     { Bad_Opcode },
9221     /* 08 */
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9230     /* 10 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9239     /* 18 */
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     /* 20 */
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* 28 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* 30 */
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* 38 */
9276     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* 40 */
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9288     { Bad_Opcode },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9290     { Bad_Opcode },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9292     { Bad_Opcode },
9293     /* 48 */
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     /* 50 */
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     /* 58 */
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9320     /* 60 */
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     /* 68 */
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9338     /* 70 */
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     /* 78 */
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9355     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9356     /* 80 */
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     /* 88 */
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     /* 90 */
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     /* 98 */
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     /* a0 */
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     /* a8 */
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     /* b0 */
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     /* b8 */
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     /* c0 */
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     /* c8 */
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     /* d0 */
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     /* d8 */
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9464     /* e0 */
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     /* e8 */
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     /* f0 */
9483     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     /* f8 */
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500   },
9501 };
9502
9503 #define NEED_OPCODE_TABLE
9504 #include "i386-dis-evex.h"
9505 #undef NEED_OPCODE_TABLE
9506 static const struct dis386 vex_len_table[][2] = {
9507   /* VEX_LEN_0F10_P_1 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9510     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9511   },
9512
9513   /* VEX_LEN_0F10_P_3 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9516     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9517   },
9518
9519   /* VEX_LEN_0F11_P_1 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9522     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9523   },
9524
9525   /* VEX_LEN_0F11_P_3 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9528     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9529   },
9530
9531   /* VEX_LEN_0F12_P_0_M_0 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9534   },
9535
9536   /* VEX_LEN_0F12_P_0_M_1 */
9537   {
9538     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9539   },
9540
9541   /* VEX_LEN_0F12_P_2 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9544   },
9545
9546   /* VEX_LEN_0F13_M_0 */
9547   {
9548     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9549   },
9550
9551   /* VEX_LEN_0F16_P_0_M_0 */
9552   {
9553     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9554   },
9555
9556   /* VEX_LEN_0F16_P_0_M_1 */
9557   {
9558     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9559   },
9560
9561   /* VEX_LEN_0F16_P_2 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9564   },
9565
9566   /* VEX_LEN_0F17_M_0 */
9567   {
9568     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9569   },
9570
9571   /* VEX_LEN_0F2A_P_1 */
9572   {
9573     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9574     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F2A_P_3 */
9578   {
9579     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9580     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F2C_P_1 */
9584   {
9585     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9586     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9587   },
9588
9589   /* VEX_LEN_0F2C_P_3 */
9590   {
9591     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9592     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F2D_P_1 */
9596   {
9597     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9598     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F2D_P_3 */
9602   {
9603     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9604     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F2E_P_0 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9610     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9611   },
9612
9613   /* VEX_LEN_0F2E_P_2 */
9614   {
9615     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9616     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9617   },
9618
9619   /* VEX_LEN_0F2F_P_0 */
9620   {
9621     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9622     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9623   },
9624
9625   /* VEX_LEN_0F2F_P_2 */
9626   {
9627     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9628     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9629   },
9630
9631   /* VEX_LEN_0F41_P_0 */
9632   {
9633     { Bad_Opcode },
9634     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9635   },
9636   /* VEX_LEN_0F41_P_2 */
9637   {
9638     { Bad_Opcode },
9639     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9640   },
9641   /* VEX_LEN_0F42_P_0 */
9642   {
9643     { Bad_Opcode },
9644     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9645   },
9646   /* VEX_LEN_0F42_P_2 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9650   },
9651   /* VEX_LEN_0F44_P_0 */
9652   {
9653     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9654   },
9655   /* VEX_LEN_0F44_P_2 */
9656   {
9657     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9658   },
9659   /* VEX_LEN_0F45_P_0 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9663   },
9664   /* VEX_LEN_0F45_P_2 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9668   },
9669   /* VEX_LEN_0F46_P_0 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9673   },
9674   /* VEX_LEN_0F46_P_2 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9678   },
9679   /* VEX_LEN_0F47_P_0 */
9680   {
9681     { Bad_Opcode },
9682     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9683   },
9684   /* VEX_LEN_0F47_P_2 */
9685   {
9686     { Bad_Opcode },
9687     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9688   },
9689   /* VEX_LEN_0F4A_P_0 */
9690   {
9691     { Bad_Opcode },
9692     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9693   },
9694   /* VEX_LEN_0F4A_P_2 */
9695   {
9696     { Bad_Opcode },
9697     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9698   },
9699   /* VEX_LEN_0F4B_P_0 */
9700   {
9701     { Bad_Opcode },
9702     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9703   },
9704   /* VEX_LEN_0F4B_P_2 */
9705   {
9706     { Bad_Opcode },
9707     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9708   },
9709
9710   /* VEX_LEN_0F51_P_1 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9713     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9714   },
9715
9716   /* VEX_LEN_0F51_P_3 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9719     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9720   },
9721
9722   /* VEX_LEN_0F52_P_1 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9725     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9726   },
9727
9728   /* VEX_LEN_0F53_P_1 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9731     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9732   },
9733
9734   /* VEX_LEN_0F58_P_1 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9737     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9738   },
9739
9740   /* VEX_LEN_0F58_P_3 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9743     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9744   },
9745
9746   /* VEX_LEN_0F59_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F59_P_3 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9755     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9756   },
9757
9758   /* VEX_LEN_0F5A_P_1 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9761     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9762   },
9763
9764   /* VEX_LEN_0F5A_P_3 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9767     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9768   },
9769
9770   /* VEX_LEN_0F5C_P_1 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9773     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9774   },
9775
9776   /* VEX_LEN_0F5C_P_3 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9779     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9780   },
9781
9782   /* VEX_LEN_0F5D_P_1 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9785     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9786   },
9787
9788   /* VEX_LEN_0F5D_P_3 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9791     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9792   },
9793
9794   /* VEX_LEN_0F5E_P_1 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9797     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9798   },
9799
9800   /* VEX_LEN_0F5E_P_3 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9803     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9804   },
9805
9806   /* VEX_LEN_0F5F_P_1 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9809     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9810   },
9811
9812   /* VEX_LEN_0F5F_P_3 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9815     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9816   },
9817
9818   /* VEX_LEN_0F6E_P_2 */
9819   {
9820     { "vmovK",          { XMScalar, Edq }, 0 },
9821     { "vmovK",          { XMScalar, Edq }, 0 },
9822   },
9823
9824   /* VEX_LEN_0F7E_P_1 */
9825   {
9826     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9827     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9828   },
9829
9830   /* VEX_LEN_0F7E_P_2 */
9831   {
9832     { "vmovK",          { Edq, XMScalar }, 0 },
9833     { "vmovK",          { Edq, XMScalar }, 0 },
9834   },
9835
9836   /* VEX_LEN_0F90_P_0 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9839   },
9840
9841   /* VEX_LEN_0F90_P_2 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9844   },
9845
9846   /* VEX_LEN_0F91_P_0 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9849   },
9850
9851   /* VEX_LEN_0F91_P_2 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0F92_P_0 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9859   },
9860
9861   /* VEX_LEN_0F92_P_2 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9864   },
9865
9866   /* VEX_LEN_0F92_P_3 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9869   },
9870
9871   /* VEX_LEN_0F93_P_0 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9874   },
9875
9876   /* VEX_LEN_0F93_P_2 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9879   },
9880
9881   /* VEX_LEN_0F93_P_3 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9884   },
9885
9886   /* VEX_LEN_0F98_P_0 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9889   },
9890
9891   /* VEX_LEN_0F98_P_2 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9894   },
9895
9896   /* VEX_LEN_0F99_P_0 */
9897   {
9898     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9899   },
9900
9901   /* VEX_LEN_0F99_P_2 */
9902   {
9903     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9904   },
9905
9906   /* VEX_LEN_0FAE_R_2_M_0 */
9907   {
9908     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9909   },
9910
9911   /* VEX_LEN_0FAE_R_3_M_0 */
9912   {
9913     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9914   },
9915
9916   /* VEX_LEN_0FC2_P_1 */
9917   {
9918     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9919     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9920   },
9921
9922   /* VEX_LEN_0FC2_P_3 */
9923   {
9924     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9925     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9926   },
9927
9928   /* VEX_LEN_0FC4_P_2 */
9929   {
9930     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9931   },
9932
9933   /* VEX_LEN_0FC5_P_2 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9936   },
9937
9938   /* VEX_LEN_0FD6_P_2 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9941     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9942   },
9943
9944   /* VEX_LEN_0FF7_P_2 */
9945   {
9946     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9947   },
9948
9949   /* VEX_LEN_0F3816_P_2 */
9950   {
9951     { Bad_Opcode },
9952     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9953   },
9954
9955   /* VEX_LEN_0F3819_P_2 */
9956   {
9957     { Bad_Opcode },
9958     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9959   },
9960
9961   /* VEX_LEN_0F381A_P_2_M_0 */
9962   {
9963     { Bad_Opcode },
9964     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9965   },
9966
9967   /* VEX_LEN_0F3836_P_2 */
9968   {
9969     { Bad_Opcode },
9970     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9971   },
9972
9973   /* VEX_LEN_0F3841_P_2 */
9974   {
9975     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9976   },
9977
9978   /* VEX_LEN_0F385A_P_2_M_0 */
9979   {
9980     { Bad_Opcode },
9981     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9982   },
9983
9984   /* VEX_LEN_0F38DB_P_2 */
9985   {
9986     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9987   },
9988
9989   /* VEX_LEN_0F38DC_P_2 */
9990   {
9991     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9992   },
9993
9994   /* VEX_LEN_0F38DD_P_2 */
9995   {
9996     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9997   },
9998
9999   /* VEX_LEN_0F38DE_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10002   },
10003
10004   /* VEX_LEN_0F38DF_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F38F2_P_0 */
10010   {
10011     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10012   },
10013
10014   /* VEX_LEN_0F38F3_R_1_P_0 */
10015   {
10016     { "blsrS",          { VexGdq, Edq }, 0 },
10017   },
10018
10019   /* VEX_LEN_0F38F3_R_2_P_0 */
10020   {
10021     { "blsmskS",        { VexGdq, Edq }, 0 },
10022   },
10023
10024   /* VEX_LEN_0F38F3_R_3_P_0 */
10025   {
10026     { "blsiS",          { VexGdq, Edq }, 0 },
10027   },
10028
10029   /* VEX_LEN_0F38F5_P_0 */
10030   {
10031     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10032   },
10033
10034   /* VEX_LEN_0F38F5_P_1 */
10035   {
10036     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10037   },
10038
10039   /* VEX_LEN_0F38F5_P_3 */
10040   {
10041     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10042   },
10043
10044   /* VEX_LEN_0F38F6_P_3 */
10045   {
10046     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10047   },
10048
10049   /* VEX_LEN_0F38F7_P_0 */
10050   {
10051     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10052   },
10053
10054   /* VEX_LEN_0F38F7_P_1 */
10055   {
10056     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10057   },
10058
10059   /* VEX_LEN_0F38F7_P_2 */
10060   {
10061     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10062   },
10063
10064   /* VEX_LEN_0F38F7_P_3 */
10065   {
10066     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10067   },
10068
10069   /* VEX_LEN_0F3A00_P_2 */
10070   {
10071     { Bad_Opcode },
10072     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F3A01_P_2 */
10076   {
10077     { Bad_Opcode },
10078     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A06_P_2 */
10082   {
10083     { Bad_Opcode },
10084     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F3A0A_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10090     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10091   },
10092
10093   /* VEX_LEN_0F3A0B_P_2 */
10094   {
10095     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10096     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10097   },
10098
10099   /* VEX_LEN_0F3A14_P_2 */
10100   {
10101     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10102   },
10103
10104   /* VEX_LEN_0F3A15_P_2 */
10105   {
10106     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10107   },
10108
10109   /* VEX_LEN_0F3A16_P_2  */
10110   {
10111     { "vpextrK",        { Edq, XM, Ib }, 0 },
10112   },
10113
10114   /* VEX_LEN_0F3A17_P_2 */
10115   {
10116     { "vextractps",     { Edqd, XM, Ib }, 0 },
10117   },
10118
10119   /* VEX_LEN_0F3A18_P_2 */
10120   {
10121     { Bad_Opcode },
10122     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10123   },
10124
10125   /* VEX_LEN_0F3A19_P_2 */
10126   {
10127     { Bad_Opcode },
10128     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10129   },
10130
10131   /* VEX_LEN_0F3A20_P_2 */
10132   {
10133     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10134   },
10135
10136   /* VEX_LEN_0F3A21_P_2 */
10137   {
10138     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10139   },
10140
10141   /* VEX_LEN_0F3A22_P_2 */
10142   {
10143     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10144   },
10145
10146   /* VEX_LEN_0F3A30_P_2 */
10147   {
10148     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10149   },
10150
10151   /* VEX_LEN_0F3A31_P_2 */
10152   {
10153     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10154   },
10155
10156   /* VEX_LEN_0F3A32_P_2 */
10157   {
10158     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10159   },
10160
10161   /* VEX_LEN_0F3A33_P_2 */
10162   {
10163     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10164   },
10165
10166   /* VEX_LEN_0F3A38_P_2 */
10167   {
10168     { Bad_Opcode },
10169     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10170   },
10171
10172   /* VEX_LEN_0F3A39_P_2 */
10173   {
10174     { Bad_Opcode },
10175     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10176   },
10177
10178   /* VEX_LEN_0F3A41_P_2 */
10179   {
10180     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10181   },
10182
10183   /* VEX_LEN_0F3A44_P_2 */
10184   {
10185     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10186   },
10187
10188   /* VEX_LEN_0F3A46_P_2 */
10189   {
10190     { Bad_Opcode },
10191     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10192   },
10193
10194   /* VEX_LEN_0F3A60_P_2 */
10195   {
10196     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10197   },
10198
10199   /* VEX_LEN_0F3A61_P_2 */
10200   {
10201     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10202   },
10203
10204   /* VEX_LEN_0F3A62_P_2 */
10205   {
10206     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10207   },
10208
10209   /* VEX_LEN_0F3A63_P_2 */
10210   {
10211     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10212   },
10213
10214   /* VEX_LEN_0F3A6A_P_2 */
10215   {
10216     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10217   },
10218
10219   /* VEX_LEN_0F3A6B_P_2 */
10220   {
10221     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10222   },
10223
10224   /* VEX_LEN_0F3A6E_P_2 */
10225   {
10226     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10227   },
10228
10229   /* VEX_LEN_0F3A6F_P_2 */
10230   {
10231     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10232   },
10233
10234   /* VEX_LEN_0F3A7A_P_2 */
10235   {
10236     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10237   },
10238
10239   /* VEX_LEN_0F3A7B_P_2 */
10240   {
10241     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10242   },
10243
10244   /* VEX_LEN_0F3A7E_P_2 */
10245   {
10246     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10247   },
10248
10249   /* VEX_LEN_0F3A7F_P_2 */
10250   {
10251     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10252   },
10253
10254   /* VEX_LEN_0F3ADF_P_2 */
10255   {
10256     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10257   },
10258
10259   /* VEX_LEN_0F3AF0_P_3 */
10260   {
10261     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10262   },
10263
10264   /* VEX_LEN_0FXOP_08_CC */
10265   {
10266      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10267   },
10268
10269   /* VEX_LEN_0FXOP_08_CD */
10270   {
10271      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10272   },
10273
10274   /* VEX_LEN_0FXOP_08_CE */
10275   {
10276      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10277   },
10278
10279   /* VEX_LEN_0FXOP_08_CF */
10280   {
10281      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10282   },
10283
10284   /* VEX_LEN_0FXOP_08_EC */
10285   {
10286      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10287   },
10288
10289   /* VEX_LEN_0FXOP_08_ED */
10290   {
10291      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10292   },
10293
10294   /* VEX_LEN_0FXOP_08_EE */
10295   {
10296      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10297   },
10298
10299   /* VEX_LEN_0FXOP_08_EF */
10300   {
10301      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10302   },
10303
10304   /* VEX_LEN_0FXOP_09_80 */
10305   {
10306     { "vfrczps",        { XM, EXxmm }, 0 },
10307     { "vfrczps",        { XM, EXymmq }, 0 },
10308   },
10309
10310   /* VEX_LEN_0FXOP_09_81 */
10311   {
10312     { "vfrczpd",        { XM, EXxmm }, 0 },
10313     { "vfrczpd",        { XM, EXymmq }, 0 },
10314   },
10315 };
10316
10317 static const struct dis386 vex_w_table[][2] = {
10318   {
10319     /* VEX_W_0F10_P_0 */
10320     { "vmovups",        { XM, EXx }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F10_P_1 */
10324     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F10_P_2 */
10328     { "vmovupd",        { XM, EXx }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F10_P_3 */
10332     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F11_P_0 */
10336     { "vmovups",        { EXxS, XM }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F11_P_1 */
10340     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F11_P_2 */
10344     { "vmovupd",        { EXxS, XM }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F11_P_3 */
10348     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F12_P_0_M_0 */
10352     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F12_P_0_M_1 */
10356     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F12_P_1 */
10360     { "vmovsldup",      { XM, EXx }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F12_P_2 */
10364     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F12_P_3 */
10368     { "vmovddup",       { XM, EXymmq }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F13_M_0 */
10372     { "vmovlpX",        { EXq, XM }, 0 },
10373   },
10374   {
10375     /* VEX_W_0F14 */
10376     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F15 */
10380     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F16_P_0_M_0 */
10384     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F16_P_0_M_1 */
10388     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F16_P_1 */
10392     { "vmovshdup",      { XM, EXx }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F16_P_2 */
10396     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F17_M_0 */
10400     { "vmovhpX",        { EXq, XM }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F28 */
10404     { "vmovapX",        { XM, EXx }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F29 */
10408     { "vmovapX",        { EXxS, XM }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F2B_M_0 */
10412     { "vmovntpX",       { Mx, XM }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F2E_P_0 */
10416     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F2E_P_2 */
10420     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F2F_P_0 */
10424     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F2F_P_2 */
10428     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F41_P_0_LEN_1 */
10432     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10433     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F41_P_2_LEN_1 */
10437     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10438     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10439   },
10440   {
10441     /* VEX_W_0F42_P_0_LEN_1 */
10442     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10443     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F42_P_2_LEN_1 */
10447     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10448     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F44_P_0_LEN_0 */
10452     { "knotw",          { MaskG, MaskR }, 0 },
10453     { "knotq",          { MaskG, MaskR }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F44_P_2_LEN_0 */
10457     { "knotb",          { MaskG, MaskR }, 0 },
10458     { "knotd",          { MaskG, MaskR }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F45_P_0_LEN_1 */
10462     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10463     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F45_P_2_LEN_1 */
10467     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10468     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F46_P_0_LEN_1 */
10472     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10473     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F46_P_2_LEN_1 */
10477     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10478     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F47_P_0_LEN_1 */
10482     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10483     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F47_P_2_LEN_1 */
10487     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10488     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F4A_P_0_LEN_1 */
10492     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10493     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F4A_P_2_LEN_1 */
10497     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10498     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F4B_P_0_LEN_1 */
10502     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10503     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F4B_P_2_LEN_1 */
10507     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F50_M_0 */
10511     { "vmovmskpX",      { Gdq, XS }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F51_P_0 */
10515     { "vsqrtps",        { XM, EXx }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F51_P_1 */
10519     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F51_P_2  */
10523     { "vsqrtpd",        { XM, EXx }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F51_P_3 */
10527     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F52_P_0 */
10531     { "vrsqrtps",       { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F52_P_1 */
10535     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F53_P_0  */
10539     { "vrcpps",         { XM, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F53_P_1  */
10543     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F58_P_0  */
10547     { "vaddps",         { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F58_P_1  */
10551     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F58_P_2  */
10555     { "vaddpd",         { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F58_P_3  */
10559     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F59_P_0  */
10563     { "vmulps",         { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F59_P_1  */
10567     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F59_P_2  */
10571     { "vmulpd",         { XM, Vex, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F59_P_3  */
10575     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5A_P_0  */
10579     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5A_P_1  */
10583     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5A_P_3  */
10587     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5B_P_0  */
10591     { "vcvtdq2ps",      { XM, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5B_P_1  */
10595     { "vcvttps2dq",     { XM, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5B_P_2  */
10599     { "vcvtps2dq",      { XM, EXx }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F5C_P_0  */
10603     { "vsubps",         { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F5C_P_1  */
10607     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F5C_P_2  */
10611     { "vsubpd",         { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F5C_P_3  */
10615     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F5D_P_0  */
10619     { "vminps",         { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F5D_P_1  */
10623     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F5D_P_2  */
10627     { "vminpd",         { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F5D_P_3  */
10631     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F5E_P_0  */
10635     { "vdivps",         { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F5E_P_1  */
10639     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F5E_P_2  */
10643     { "vdivpd",         { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F5E_P_3  */
10647     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F5F_P_0  */
10651     { "vmaxps",         { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F5F_P_1  */
10655     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F5F_P_2  */
10659     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F5F_P_3  */
10663     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F60_P_2  */
10667     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F61_P_2  */
10671     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F62_P_2  */
10675     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F63_P_2  */
10679     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F64_P_2  */
10683     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F65_P_2  */
10687     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F66_P_2  */
10691     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F67_P_2  */
10695     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F68_P_2  */
10699     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F69_P_2  */
10703     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F6A_P_2  */
10707     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F6B_P_2  */
10711     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F6C_P_2  */
10715     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F6D_P_2  */
10719     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F6F_P_1  */
10723     { "vmovdqu",        { XM, EXx }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F6F_P_2  */
10727     { "vmovdqa",        { XM, EXx }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F70_P_1 */
10731     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F70_P_2 */
10735     { "vpshufd",        { XM, EXx, Ib }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F70_P_3 */
10739     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F71_R_2_P_2  */
10743     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F71_R_4_P_2  */
10747     { "vpsraw",         { Vex, XS, Ib }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F71_R_6_P_2  */
10751     { "vpsllw",         { Vex, XS, Ib }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F72_R_2_P_2  */
10755     { "vpsrld",         { Vex, XS, Ib }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F72_R_4_P_2  */
10759     { "vpsrad",         { Vex, XS, Ib }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F72_R_6_P_2  */
10763     { "vpslld",         { Vex, XS, Ib }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F73_R_2_P_2  */
10767     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F73_R_3_P_2  */
10771     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10772   },
10773   {
10774     /* VEX_W_0F73_R_6_P_2  */
10775     { "vpsllq",         { Vex, XS, Ib }, 0 },
10776   },
10777   {
10778     /* VEX_W_0F73_R_7_P_2  */
10779     { "vpslldq",        { Vex, XS, Ib }, 0 },
10780   },
10781   {
10782     /* VEX_W_0F74_P_2 */
10783     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10784   },
10785   {
10786     /* VEX_W_0F75_P_2 */
10787     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10788   },
10789   {
10790     /* VEX_W_0F76_P_2 */
10791     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10792   },
10793   {
10794     /* VEX_W_0F77_P_0 */
10795     { "",               { VZERO }, 0 },
10796   },
10797   {
10798     /* VEX_W_0F7C_P_2 */
10799     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10800   },
10801   {
10802     /* VEX_W_0F7C_P_3 */
10803     { "vhaddps",        { XM, Vex, EXx }, 0 },
10804   },
10805   {
10806     /* VEX_W_0F7D_P_2 */
10807     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10808   },
10809   {
10810     /* VEX_W_0F7D_P_3 */
10811     { "vhsubps",        { XM, Vex, EXx }, 0 },
10812   },
10813   {
10814     /* VEX_W_0F7E_P_1 */
10815     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10816   },
10817   {
10818     /* VEX_W_0F7F_P_1 */
10819     { "vmovdqu",        { EXxS, XM }, 0 },
10820   },
10821   {
10822     /* VEX_W_0F7F_P_2 */
10823     { "vmovdqa",        { EXxS, XM }, 0 },
10824   },
10825   {
10826     /* VEX_W_0F90_P_0_LEN_0 */
10827     { "kmovw",          { MaskG, MaskE }, 0 },
10828     { "kmovq",          { MaskG, MaskE }, 0 },
10829   },
10830   {
10831     /* VEX_W_0F90_P_2_LEN_0 */
10832     { "kmovb",          { MaskG, MaskBDE }, 0 },
10833     { "kmovd",          { MaskG, MaskBDE }, 0 },
10834   },
10835   {
10836     /* VEX_W_0F91_P_0_LEN_0 */
10837     { "kmovw",          { Ew, MaskG }, 0 },
10838     { "kmovq",          { Eq, MaskG }, 0 },
10839   },
10840   {
10841     /* VEX_W_0F91_P_2_LEN_0 */
10842     { "kmovb",          { Eb, MaskG }, 0 },
10843     { "kmovd",          { Ed, MaskG }, 0 },
10844   },
10845   {
10846     /* VEX_W_0F92_P_0_LEN_0 */
10847     { "kmovw",          { MaskG, Rdq }, 0 },
10848   },
10849   {
10850     /* VEX_W_0F92_P_2_LEN_0 */
10851     { "kmovb",          { MaskG, Rdq }, 0 },
10852   },
10853   {
10854     /* VEX_W_0F92_P_3_LEN_0 */
10855     { "kmovd",          { MaskG, Rdq }, 0 },
10856     { "kmovq",          { MaskG, Rdq }, 0 },
10857   },
10858   {
10859     /* VEX_W_0F93_P_0_LEN_0 */
10860     { "kmovw",          { Gdq, MaskR }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F93_P_2_LEN_0 */
10864     { "kmovb",          { Gdq, MaskR }, 0 },
10865   },
10866   {
10867     /* VEX_W_0F93_P_3_LEN_0 */
10868     { "kmovd",          { Gdq, MaskR }, 0 },
10869     { "kmovq",          { Gdq, MaskR }, 0 },
10870   },
10871   {
10872     /* VEX_W_0F98_P_0_LEN_0 */
10873     { "kortestw",       { MaskG, MaskR }, 0 },
10874     { "kortestq",       { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* VEX_W_0F98_P_2_LEN_0 */
10878     { "kortestb",       { MaskG, MaskR }, 0 },
10879     { "kortestd",       { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* VEX_W_0F99_P_0_LEN_0 */
10883     { "ktestw", { MaskG, MaskR }, 0 },
10884     { "ktestq", { MaskG, MaskR }, 0 },
10885   },
10886   {
10887     /* VEX_W_0F99_P_2_LEN_0 */
10888     { "ktestb", { MaskG, MaskR }, 0 },
10889     { "ktestd", { MaskG, MaskR }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FAE_R_2_M_0 */
10893     { "vldmxcsr",       { Md }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FAE_R_3_M_0 */
10897     { "vstmxcsr",       { Md }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FC2_P_0 */
10901     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FC2_P_1 */
10905     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FC2_P_2 */
10909     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FC2_P_3 */
10913     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FC4_P_2 */
10917     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FC5_P_2 */
10921     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FD0_P_2 */
10925     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FD0_P_3 */
10929     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FD1_P_2 */
10933     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FD2_P_2 */
10937     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FD3_P_2 */
10941     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FD4_P_2 */
10945     { "vpaddq",         { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FD5_P_2 */
10949     { "vpmullw",        { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FD6_P_2 */
10953     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FD7_P_2_M_1 */
10957     { "vpmovmskb",      { Gdq, XS }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FD8_P_2 */
10961     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FD9_P_2 */
10965     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FDA_P_2 */
10969     { "vpminub",        { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FDB_P_2 */
10973     { "vpand",          { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FDC_P_2 */
10977     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FDD_P_2 */
10981     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FDE_P_2 */
10985     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FDF_P_2 */
10989     { "vpandn",         { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FE0_P_2  */
10993     { "vpavgb",         { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FE1_P_2  */
10997     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FE2_P_2  */
11001     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FE3_P_2  */
11005     { "vpavgw",         { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FE4_P_2  */
11009     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FE5_P_2  */
11013     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FE6_P_1  */
11017     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FE6_P_2  */
11021     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FE6_P_3  */
11025     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FE7_P_2_M_0 */
11029     { "vmovntdq",       { Mx, XM }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FE8_P_2  */
11033     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FE9_P_2  */
11037     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FEA_P_2  */
11041     { "vpminsw",        { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FEB_P_2  */
11045     { "vpor",           { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FEC_P_2  */
11049     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FED_P_2  */
11053     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FEE_P_2  */
11057     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FEF_P_2  */
11061     { "vpxor",          { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0FF0_P_3_M_0 */
11065     { "vlddqu",         { XM, M }, 0 },
11066   },
11067   {
11068     /* VEX_W_0FF1_P_2 */
11069     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11070   },
11071   {
11072     /* VEX_W_0FF2_P_2 */
11073     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11074   },
11075   {
11076     /* VEX_W_0FF3_P_2 */
11077     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11078   },
11079   {
11080     /* VEX_W_0FF4_P_2 */
11081     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0FF5_P_2 */
11085     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0FF6_P_2 */
11089     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0FF7_P_2 */
11093     { "vmaskmovdqu",    { XM, XS }, 0 },
11094   },
11095   {
11096     /* VEX_W_0FF8_P_2 */
11097     { "vpsubb",         { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0FF9_P_2 */
11101     { "vpsubw",         { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0FFA_P_2 */
11105     { "vpsubd",         { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0FFB_P_2 */
11109     { "vpsubq",         { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0FFC_P_2 */
11113     { "vpaddb",         { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0FFD_P_2 */
11117     { "vpaddw",         { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0FFE_P_2 */
11121     { "vpaddd",         { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3800_P_2  */
11125     { "vpshufb",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3801_P_2  */
11129     { "vphaddw",        { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3802_P_2  */
11133     { "vphaddd",        { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3803_P_2  */
11137     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F3804_P_2  */
11141     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F3805_P_2  */
11145     { "vphsubw",        { XM, Vex, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3806_P_2  */
11149     { "vphsubd",        { XM, Vex, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3807_P_2  */
11153     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3808_P_2  */
11157     { "vpsignb",        { XM, Vex, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3809_P_2  */
11161     { "vpsignw",        { XM, Vex, EXx }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F380A_P_2  */
11165     { "vpsignd",        { XM, Vex, EXx }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F380B_P_2  */
11169     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F380C_P_2  */
11173     { "vpermilps",      { XM, Vex, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F380D_P_2  */
11177     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F380E_P_2  */
11181     { "vtestps",        { XM, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F380F_P_2  */
11185     { "vtestpd",        { XM, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F3816_P_2  */
11189     { "vpermps",        { XM, Vex, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F3817_P_2 */
11193     { "vptest",         { XM, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F3818_P_2 */
11197     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F3819_P_2 */
11201     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F381A_P_2_M_0 */
11205     { "vbroadcastf128", { XM, Mxmm }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F381C_P_2 */
11209     { "vpabsb",         { XM, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F381D_P_2 */
11213     { "vpabsw",         { XM, EXx }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F381E_P_2 */
11217     { "vpabsd",         { XM, EXx }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3820_P_2 */
11221     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3821_P_2 */
11225     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3822_P_2 */
11229     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3823_P_2 */
11233     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3824_P_2 */
11237     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3825_P_2 */
11241     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F3828_P_2 */
11245     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F3829_P_2 */
11249     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F382A_P_2_M_0 */
11253     { "vmovntdqa",      { XM, Mx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F382B_P_2 */
11257     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F382C_P_2_M_0 */
11261     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F382D_P_2_M_0 */
11265     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F382E_P_2_M_0 */
11269     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F382F_P_2_M_0 */
11273     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3830_P_2 */
11277     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3831_P_2 */
11281     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3832_P_2 */
11285     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3833_P_2 */
11289     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3834_P_2 */
11293     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F3835_P_2 */
11297     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3836_P_2  */
11301     { "vpermd",         { XM, Vex, EXx }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3837_P_2 */
11305     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F3838_P_2 */
11309     { "vpminsb",        { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F3839_P_2 */
11313     { "vpminsd",        { XM, Vex, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F383A_P_2 */
11317     { "vpminuw",        { XM, Vex, EXx }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F383B_P_2 */
11321     { "vpminud",        { XM, Vex, EXx }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F383C_P_2 */
11325     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F383D_P_2 */
11329     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F383E_P_2 */
11333     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F383F_P_2 */
11337     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3840_P_2 */
11341     { "vpmulld",        { XM, Vex, EXx }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3841_P_2 */
11345     { "vphminposuw",    { XM, EXx }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3846_P_2 */
11349     { "vpsravd",        { XM, Vex, EXx }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3858_P_2 */
11353     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3859_P_2 */
11357     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F385A_P_2_M_0 */
11361     { "vbroadcasti128", { XM, Mxmm }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F3878_P_2 */
11365     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F3879_P_2 */
11369     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F38DB_P_2 */
11373     { "vaesimc",        { XM, EXx }, 0 },
11374   },
11375   {
11376     /* VEX_W_0F38DC_P_2 */
11377     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11378   },
11379   {
11380     /* VEX_W_0F38DD_P_2 */
11381     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11382   },
11383   {
11384     /* VEX_W_0F38DE_P_2 */
11385     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11386   },
11387   {
11388     /* VEX_W_0F38DF_P_2 */
11389     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11390   },
11391   {
11392     /* VEX_W_0F3A00_P_2 */
11393     { Bad_Opcode },
11394     { "vpermq",         { XM, EXx, Ib }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3A01_P_2 */
11398     { Bad_Opcode },
11399     { "vpermpd",        { XM, EXx, Ib }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3A02_P_2 */
11403     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F3A04_P_2 */
11407     { "vpermilps",      { XM, EXx, Ib }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3A05_P_2 */
11411     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F3A06_P_2 */
11415     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F3A08_P_2 */
11419     { "vroundps",       { XM, EXx, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A09_P_2 */
11423     { "vroundpd",       { XM, EXx, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A0A_P_2 */
11427     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A0B_P_2 */
11431     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A0C_P_2 */
11435     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A0D_P_2 */
11439     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A0E_P_2 */
11443     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A0F_P_2 */
11447     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A14_P_2 */
11451     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F3A15_P_2 */
11455     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F3A18_P_2 */
11459     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11460   },
11461   {
11462     /* VEX_W_0F3A19_P_2 */
11463     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11464   },
11465   {
11466     /* VEX_W_0F3A20_P_2 */
11467     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F3A21_P_2 */
11471     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11472   },
11473   {
11474     /* VEX_W_0F3A30_P_2_LEN_0 */
11475     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11476     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F3A31_P_2_LEN_0 */
11480     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11481     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11482   },
11483   {
11484     /* VEX_W_0F3A32_P_2_LEN_0 */
11485     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11486     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11487   },
11488   {
11489     /* VEX_W_0F3A33_P_2_LEN_0 */
11490     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11491     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A38_P_2 */
11495     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11496   },
11497   {
11498     /* VEX_W_0F3A39_P_2 */
11499     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11500   },
11501   {
11502     /* VEX_W_0F3A40_P_2 */
11503     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11504   },
11505   {
11506     /* VEX_W_0F3A41_P_2 */
11507     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11508   },
11509   {
11510     /* VEX_W_0F3A42_P_2 */
11511     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11512   },
11513   {
11514     /* VEX_W_0F3A44_P_2 */
11515     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11516   },
11517   {
11518     /* VEX_W_0F3A46_P_2 */
11519     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11520   },
11521   {
11522     /* VEX_W_0F3A48_P_2 */
11523     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11524     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A49_P_2 */
11528     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11529     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3A4A_P_2 */
11533     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11534   },
11535   {
11536     /* VEX_W_0F3A4B_P_2 */
11537     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3A4C_P_2 */
11541     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11542   },
11543   {
11544     /* VEX_W_0F3A60_P_2 */
11545     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11546   },
11547   {
11548     /* VEX_W_0F3A61_P_2 */
11549     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11550   },
11551   {
11552     /* VEX_W_0F3A62_P_2 */
11553     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11554   },
11555   {
11556     /* VEX_W_0F3A63_P_2 */
11557     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11558   },
11559   {
11560     /* VEX_W_0F3ADF_P_2 */
11561     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11562   },
11563 #define NEED_VEX_W_TABLE
11564 #include "i386-dis-evex.h"
11565 #undef NEED_VEX_W_TABLE
11566 };
11567
11568 static const struct dis386 mod_table[][2] = {
11569   {
11570     /* MOD_8D */
11571     { "leaS",           { Gv, M }, 0 },
11572   },
11573   {
11574     /* MOD_C6_REG_7 */
11575     { Bad_Opcode },
11576     { RM_TABLE (RM_C6_REG_7) },
11577   },
11578   {
11579     /* MOD_C7_REG_7 */
11580     { Bad_Opcode },
11581     { RM_TABLE (RM_C7_REG_7) },
11582   },
11583   {
11584     /* MOD_FF_REG_3 */
11585     { "Jcall{T|}", { indirEp }, 0 },
11586   },
11587   {
11588     /* MOD_FF_REG_5 */
11589     { "Jjmp{T|}", { indirEp }, 0 },
11590   },
11591   {
11592     /* MOD_0F01_REG_0 */
11593     { X86_64_TABLE (X86_64_0F01_REG_0) },
11594     { RM_TABLE (RM_0F01_REG_0) },
11595   },
11596   {
11597     /* MOD_0F01_REG_1 */
11598     { X86_64_TABLE (X86_64_0F01_REG_1) },
11599     { RM_TABLE (RM_0F01_REG_1) },
11600   },
11601   {
11602     /* MOD_0F01_REG_2 */
11603     { X86_64_TABLE (X86_64_0F01_REG_2) },
11604     { RM_TABLE (RM_0F01_REG_2) },
11605   },
11606   {
11607     /* MOD_0F01_REG_3 */
11608     { X86_64_TABLE (X86_64_0F01_REG_3) },
11609     { RM_TABLE (RM_0F01_REG_3) },
11610   },
11611   {
11612     /* MOD_0F01_REG_7 */
11613     { "invlpg",         { Mb }, 0 },
11614     { RM_TABLE (RM_0F01_REG_7) },
11615   },
11616   {
11617     /* MOD_0F12_PREFIX_0 */
11618     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11619     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11620   },
11621   {
11622     /* MOD_0F13 */
11623     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11624   },
11625   {
11626     /* MOD_0F16_PREFIX_0 */
11627     { "movhps",         { XM, EXq }, 0 },
11628     { "movlhps",        { XM, EXq }, 0 },
11629   },
11630   {
11631     /* MOD_0F17 */
11632     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11633   },
11634   {
11635     /* MOD_0F18_REG_0 */
11636     { "prefetchnta",    { Mb }, 0 },
11637   },
11638   {
11639     /* MOD_0F18_REG_1 */
11640     { "prefetcht0",     { Mb }, 0 },
11641   },
11642   {
11643     /* MOD_0F18_REG_2 */
11644     { "prefetcht1",     { Mb }, 0 },
11645   },
11646   {
11647     /* MOD_0F18_REG_3 */
11648     { "prefetcht2",     { Mb }, 0 },
11649   },
11650   {
11651     /* MOD_0F18_REG_4 */
11652     { "nop/reserved",   { Mb }, 0 },
11653   },
11654   {
11655     /* MOD_0F18_REG_5 */
11656     { "nop/reserved",   { Mb }, 0 },
11657   },
11658   {
11659     /* MOD_0F18_REG_6 */
11660     { "nop/reserved",   { Mb }, 0 },
11661   },
11662   {
11663     /* MOD_0F18_REG_7 */
11664     { "nop/reserved",   { Mb }, 0 },
11665   },
11666   {
11667     /* MOD_0F1A_PREFIX_0 */
11668     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11669     { "nopQ",           { Ev }, 0 },
11670   },
11671   {
11672     /* MOD_0F1B_PREFIX_0 */
11673     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11674     { "nopQ",           { Ev }, 0 },
11675   },
11676   {
11677     /* MOD_0F1B_PREFIX_1 */
11678     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11679     { "nopQ",           { Ev }, 0 },
11680   },
11681   {
11682     /* MOD_0F24 */
11683     { Bad_Opcode },
11684     { "movL",           { Rd, Td }, 0 },
11685   },
11686   {
11687     /* MOD_0F26 */
11688     { Bad_Opcode },
11689     { "movL",           { Td, Rd }, 0 },
11690   },
11691   {
11692     /* MOD_0F2B_PREFIX_0 */
11693     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11694   },
11695   {
11696     /* MOD_0F2B_PREFIX_1 */
11697     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11698   },
11699   {
11700     /* MOD_0F2B_PREFIX_2 */
11701     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11702   },
11703   {
11704     /* MOD_0F2B_PREFIX_3 */
11705     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11706   },
11707   {
11708     /* MOD_0F51 */
11709     { Bad_Opcode },
11710     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11711   },
11712   {
11713     /* MOD_0F71_REG_2 */
11714     { Bad_Opcode },
11715     { "psrlw",          { MS, Ib }, 0 },
11716   },
11717   {
11718     /* MOD_0F71_REG_4 */
11719     { Bad_Opcode },
11720     { "psraw",          { MS, Ib }, 0 },
11721   },
11722   {
11723     /* MOD_0F71_REG_6 */
11724     { Bad_Opcode },
11725     { "psllw",          { MS, Ib }, 0 },
11726   },
11727   {
11728     /* MOD_0F72_REG_2 */
11729     { Bad_Opcode },
11730     { "psrld",          { MS, Ib }, 0 },
11731   },
11732   {
11733     /* MOD_0F72_REG_4 */
11734     { Bad_Opcode },
11735     { "psrad",          { MS, Ib }, 0 },
11736   },
11737   {
11738     /* MOD_0F72_REG_6 */
11739     { Bad_Opcode },
11740     { "pslld",          { MS, Ib }, 0 },
11741   },
11742   {
11743     /* MOD_0F73_REG_2 */
11744     { Bad_Opcode },
11745     { "psrlq",          { MS, Ib }, 0 },
11746   },
11747   {
11748     /* MOD_0F73_REG_3 */
11749     { Bad_Opcode },
11750     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11751   },
11752   {
11753     /* MOD_0F73_REG_6 */
11754     { Bad_Opcode },
11755     { "psllq",          { MS, Ib }, 0 },
11756   },
11757   {
11758     /* MOD_0F73_REG_7 */
11759     { Bad_Opcode },
11760     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11761   },
11762   {
11763     /* MOD_0FAE_REG_0 */
11764     { "fxsave",         { FXSAVE }, 0 },
11765     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11766   },
11767   {
11768     /* MOD_0FAE_REG_1 */
11769     { "fxrstor",        { FXSAVE }, 0 },
11770     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11771   },
11772   {
11773     /* MOD_0FAE_REG_2 */
11774     { "ldmxcsr",        { Md }, 0 },
11775     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11776   },
11777   {
11778     /* MOD_0FAE_REG_3 */
11779     { "stmxcsr",        { Md }, 0 },
11780     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11781   },
11782   {
11783     /* MOD_0FAE_REG_4 */
11784     { "xsave",          { FXSAVE }, 0 },
11785   },
11786   {
11787     /* MOD_0FAE_REG_5 */
11788     { "xrstor",         { FXSAVE }, 0 },
11789     { RM_TABLE (RM_0FAE_REG_5) },
11790   },
11791   {
11792     /* MOD_0FAE_REG_6 */
11793     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11794     { RM_TABLE (RM_0FAE_REG_6) },
11795   },
11796   {
11797     /* MOD_0FAE_REG_7 */
11798     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11799     { RM_TABLE (RM_0FAE_REG_7) },
11800   },
11801   {
11802     /* MOD_0FB2 */
11803     { "lssS",           { Gv, Mp }, 0 },
11804   },
11805   {
11806     /* MOD_0FB4 */
11807     { "lfsS",           { Gv, Mp }, 0 },
11808   },
11809   {
11810     /* MOD_0FB5 */
11811     { "lgsS",           { Gv, Mp }, 0 },
11812   },
11813   {
11814     /* MOD_0FC7_REG_3 */
11815     { "xrstors",                { FXSAVE }, 0 },
11816   },
11817   {
11818     /* MOD_0FC7_REG_4 */
11819     { "xsavec",         { FXSAVE }, 0 },
11820   },
11821   {
11822     /* MOD_0FC7_REG_5 */
11823     { "xsaves",         { FXSAVE }, 0 },
11824   },
11825   {
11826     /* MOD_0FC7_REG_6 */
11827     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11828     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11829   },
11830   {
11831     /* MOD_0FC7_REG_7 */
11832     { "vmptrst",        { Mq }, 0 },
11833     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11834   },
11835   {
11836     /* MOD_0FD7 */
11837     { Bad_Opcode },
11838     { "pmovmskb",       { Gdq, MS }, 0 },
11839   },
11840   {
11841     /* MOD_0FE7_PREFIX_2 */
11842     { "movntdq",        { Mx, XM }, 0 },
11843   },
11844   {
11845     /* MOD_0FF0_PREFIX_3 */
11846     { "lddqu",          { XM, M }, 0 },
11847   },
11848   {
11849     /* MOD_0F382A_PREFIX_2 */
11850     { "movntdqa",       { XM, Mx }, 0 },
11851   },
11852   {
11853     /* MOD_62_32BIT */
11854     { "bound{S|}",      { Gv, Ma }, 0 },
11855     { EVEX_TABLE (EVEX_0F) },
11856   },
11857   {
11858     /* MOD_C4_32BIT */
11859     { "lesS",           { Gv, Mp }, 0 },
11860     { VEX_C4_TABLE (VEX_0F) },
11861   },
11862   {
11863     /* MOD_C5_32BIT */
11864     { "ldsS",           { Gv, Mp }, 0 },
11865     { VEX_C5_TABLE (VEX_0F) },
11866   },
11867   {
11868     /* MOD_VEX_0F12_PREFIX_0 */
11869     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11870     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11871   },
11872   {
11873     /* MOD_VEX_0F13 */
11874     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11875   },
11876   {
11877     /* MOD_VEX_0F16_PREFIX_0 */
11878     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11879     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11880   },
11881   {
11882     /* MOD_VEX_0F17 */
11883     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11884   },
11885   {
11886     /* MOD_VEX_0F2B */
11887     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11888   },
11889   {
11890     /* MOD_VEX_0F50 */
11891     { Bad_Opcode },
11892     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11893   },
11894   {
11895     /* MOD_VEX_0F71_REG_2 */
11896     { Bad_Opcode },
11897     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11898   },
11899   {
11900     /* MOD_VEX_0F71_REG_4 */
11901     { Bad_Opcode },
11902     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11903   },
11904   {
11905     /* MOD_VEX_0F71_REG_6 */
11906     { Bad_Opcode },
11907     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11908   },
11909   {
11910     /* MOD_VEX_0F72_REG_2 */
11911     { Bad_Opcode },
11912     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11913   },
11914   {
11915     /* MOD_VEX_0F72_REG_4 */
11916     { Bad_Opcode },
11917     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11918   },
11919   {
11920     /* MOD_VEX_0F72_REG_6 */
11921     { Bad_Opcode },
11922     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11923   },
11924   {
11925     /* MOD_VEX_0F73_REG_2 */
11926     { Bad_Opcode },
11927     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11928   },
11929   {
11930     /* MOD_VEX_0F73_REG_3 */
11931     { Bad_Opcode },
11932     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11933   },
11934   {
11935     /* MOD_VEX_0F73_REG_6 */
11936     { Bad_Opcode },
11937     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11938   },
11939   {
11940     /* MOD_VEX_0F73_REG_7 */
11941     { Bad_Opcode },
11942     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11943   },
11944   {
11945     /* MOD_VEX_0FAE_REG_2 */
11946     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11947   },
11948   {
11949     /* MOD_VEX_0FAE_REG_3 */
11950     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11951   },
11952   {
11953     /* MOD_VEX_0FD7_PREFIX_2 */
11954     { Bad_Opcode },
11955     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11956   },
11957   {
11958     /* MOD_VEX_0FE7_PREFIX_2 */
11959     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11960   },
11961   {
11962     /* MOD_VEX_0FF0_PREFIX_3 */
11963     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0F381A_PREFIX_2 */
11967     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_0F382A_PREFIX_2 */
11971     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11972   },
11973   {
11974     /* MOD_VEX_0F382C_PREFIX_2 */
11975     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11976   },
11977   {
11978     /* MOD_VEX_0F382D_PREFIX_2 */
11979     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11980   },
11981   {
11982     /* MOD_VEX_0F382E_PREFIX_2 */
11983     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11984   },
11985   {
11986     /* MOD_VEX_0F382F_PREFIX_2 */
11987     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11988   },
11989   {
11990     /* MOD_VEX_0F385A_PREFIX_2 */
11991     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11992   },
11993   {
11994     /* MOD_VEX_0F388C_PREFIX_2 */
11995     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11996   },
11997   {
11998     /* MOD_VEX_0F388E_PREFIX_2 */
11999     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12000   },
12001 #define NEED_MOD_TABLE
12002 #include "i386-dis-evex.h"
12003 #undef NEED_MOD_TABLE
12004 };
12005
12006 static const struct dis386 rm_table[][8] = {
12007   {
12008     /* RM_C6_REG_7 */
12009     { "xabort",         { Skip_MODRM, Ib }, 0 },
12010   },
12011   {
12012     /* RM_C7_REG_7 */
12013     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12014   },
12015   {
12016     /* RM_0F01_REG_0 */
12017     { Bad_Opcode },
12018     { "vmcall",         { Skip_MODRM }, 0 },
12019     { "vmlaunch",       { Skip_MODRM }, 0 },
12020     { "vmresume",       { Skip_MODRM }, 0 },
12021     { "vmxoff",         { Skip_MODRM }, 0 },
12022   },
12023   {
12024     /* RM_0F01_REG_1 */
12025     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12026     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12027     { "clac",           { Skip_MODRM }, 0 },
12028     { "stac",           { Skip_MODRM }, 0 },
12029     { Bad_Opcode },
12030     { Bad_Opcode },
12031     { Bad_Opcode },
12032     { "encls",          { Skip_MODRM }, 0 },
12033   },
12034   {
12035     /* RM_0F01_REG_2 */
12036     { "xgetbv",         { Skip_MODRM }, 0 },
12037     { "xsetbv",         { Skip_MODRM }, 0 },
12038     { Bad_Opcode },
12039     { Bad_Opcode },
12040     { "vmfunc",         { Skip_MODRM }, 0 },
12041     { "xend",           { Skip_MODRM }, 0 },
12042     { "xtest",          { Skip_MODRM }, 0 },
12043     { "enclu",          { Skip_MODRM }, 0 },
12044   },
12045   {
12046     /* RM_0F01_REG_3 */
12047     { "vmrun",          { Skip_MODRM }, 0 },
12048     { "vmmcall",        { Skip_MODRM }, 0 },
12049     { "vmload",         { Skip_MODRM }, 0 },
12050     { "vmsave",         { Skip_MODRM }, 0 },
12051     { "stgi",           { Skip_MODRM }, 0 },
12052     { "clgi",           { Skip_MODRM }, 0 },
12053     { "skinit",         { Skip_MODRM }, 0 },
12054     { "invlpga",        { Skip_MODRM }, 0 },
12055   },
12056   {
12057     /* RM_0F01_REG_7 */
12058     { "swapgs",         { Skip_MODRM }, 0  },
12059     { "rdtscp",         { Skip_MODRM }, 0  },
12060     { Bad_Opcode },
12061     { Bad_Opcode },
12062     { "clzero",         { Skip_MODRM }, 0  },
12063   },
12064   {
12065     /* RM_0FAE_REG_5 */
12066     { "lfence",         { Skip_MODRM }, 0 },
12067   },
12068   {
12069     /* RM_0FAE_REG_6 */
12070     { "mfence",         { Skip_MODRM }, 0 },
12071   },
12072   {
12073     /* RM_0FAE_REG_7 */
12074     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12075   },
12076 };
12077
12078 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12079
12080 /* We use the high bit to indicate different name for the same
12081    prefix.  */
12082 #define REP_PREFIX      (0xf3 | 0x100)
12083 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12084 #define XRELEASE_PREFIX (0xf3 | 0x400)
12085 #define BND_PREFIX      (0xf2 | 0x400)
12086
12087 static int
12088 ckprefix (void)
12089 {
12090   int newrex, i, length;
12091   rex = 0;
12092   rex_ignored = 0;
12093   prefixes = 0;
12094   used_prefixes = 0;
12095   rex_used = 0;
12096   last_lock_prefix = -1;
12097   last_repz_prefix = -1;
12098   last_repnz_prefix = -1;
12099   last_data_prefix = -1;
12100   last_addr_prefix = -1;
12101   last_rex_prefix = -1;
12102   last_seg_prefix = -1;
12103   fwait_prefix = -1;
12104   active_seg_prefix = 0;
12105   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12106     all_prefixes[i] = 0;
12107   i = 0;
12108   length = 0;
12109   /* The maximum instruction length is 15bytes.  */
12110   while (length < MAX_CODE_LENGTH - 1)
12111     {
12112       FETCH_DATA (the_info, codep + 1);
12113       newrex = 0;
12114       switch (*codep)
12115         {
12116         /* REX prefixes family.  */
12117         case 0x40:
12118         case 0x41:
12119         case 0x42:
12120         case 0x43:
12121         case 0x44:
12122         case 0x45:
12123         case 0x46:
12124         case 0x47:
12125         case 0x48:
12126         case 0x49:
12127         case 0x4a:
12128         case 0x4b:
12129         case 0x4c:
12130         case 0x4d:
12131         case 0x4e:
12132         case 0x4f:
12133           if (address_mode == mode_64bit)
12134             newrex = *codep;
12135           else
12136             return 1;
12137           last_rex_prefix = i;
12138           break;
12139         case 0xf3:
12140           prefixes |= PREFIX_REPZ;
12141           last_repz_prefix = i;
12142           break;
12143         case 0xf2:
12144           prefixes |= PREFIX_REPNZ;
12145           last_repnz_prefix = i;
12146           break;
12147         case 0xf0:
12148           prefixes |= PREFIX_LOCK;
12149           last_lock_prefix = i;
12150           break;
12151         case 0x2e:
12152           prefixes |= PREFIX_CS;
12153           last_seg_prefix = i;
12154           active_seg_prefix = PREFIX_CS;
12155           break;
12156         case 0x36:
12157           prefixes |= PREFIX_SS;
12158           last_seg_prefix = i;
12159           active_seg_prefix = PREFIX_SS;
12160           break;
12161         case 0x3e:
12162           prefixes |= PREFIX_DS;
12163           last_seg_prefix = i;
12164           active_seg_prefix = PREFIX_DS;
12165           break;
12166         case 0x26:
12167           prefixes |= PREFIX_ES;
12168           last_seg_prefix = i;
12169           active_seg_prefix = PREFIX_ES;
12170           break;
12171         case 0x64:
12172           prefixes |= PREFIX_FS;
12173           last_seg_prefix = i;
12174           active_seg_prefix = PREFIX_FS;
12175           break;
12176         case 0x65:
12177           prefixes |= PREFIX_GS;
12178           last_seg_prefix = i;
12179           active_seg_prefix = PREFIX_GS;
12180           break;
12181         case 0x66:
12182           prefixes |= PREFIX_DATA;
12183           last_data_prefix = i;
12184           break;
12185         case 0x67:
12186           prefixes |= PREFIX_ADDR;
12187           last_addr_prefix = i;
12188           break;
12189         case FWAIT_OPCODE:
12190           /* fwait is really an instruction.  If there are prefixes
12191              before the fwait, they belong to the fwait, *not* to the
12192              following instruction.  */
12193           fwait_prefix = i;
12194           if (prefixes || rex)
12195             {
12196               prefixes |= PREFIX_FWAIT;
12197               codep++;
12198               /* This ensures that the previous REX prefixes are noticed
12199                  as unused prefixes, as in the return case below.  */
12200               rex_used = rex;
12201               return 1;
12202             }
12203           prefixes = PREFIX_FWAIT;
12204           break;
12205         default:
12206           return 1;
12207         }
12208       /* Rex is ignored when followed by another prefix.  */
12209       if (rex)
12210         {
12211           rex_used = rex;
12212           return 1;
12213         }
12214       if (*codep != FWAIT_OPCODE)
12215         all_prefixes[i++] = *codep;
12216       rex = newrex;
12217       codep++;
12218       length++;
12219     }
12220   return 0;
12221 }
12222
12223 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12224    prefix byte.  */
12225
12226 static const char *
12227 prefix_name (int pref, int sizeflag)
12228 {
12229   static const char *rexes [16] =
12230     {
12231       "rex",            /* 0x40 */
12232       "rex.B",          /* 0x41 */
12233       "rex.X",          /* 0x42 */
12234       "rex.XB",         /* 0x43 */
12235       "rex.R",          /* 0x44 */
12236       "rex.RB",         /* 0x45 */
12237       "rex.RX",         /* 0x46 */
12238       "rex.RXB",        /* 0x47 */
12239       "rex.W",          /* 0x48 */
12240       "rex.WB",         /* 0x49 */
12241       "rex.WX",         /* 0x4a */
12242       "rex.WXB",        /* 0x4b */
12243       "rex.WR",         /* 0x4c */
12244       "rex.WRB",        /* 0x4d */
12245       "rex.WRX",        /* 0x4e */
12246       "rex.WRXB",       /* 0x4f */
12247     };
12248
12249   switch (pref)
12250     {
12251     /* REX prefixes family.  */
12252     case 0x40:
12253     case 0x41:
12254     case 0x42:
12255     case 0x43:
12256     case 0x44:
12257     case 0x45:
12258     case 0x46:
12259     case 0x47:
12260     case 0x48:
12261     case 0x49:
12262     case 0x4a:
12263     case 0x4b:
12264     case 0x4c:
12265     case 0x4d:
12266     case 0x4e:
12267     case 0x4f:
12268       return rexes [pref - 0x40];
12269     case 0xf3:
12270       return "repz";
12271     case 0xf2:
12272       return "repnz";
12273     case 0xf0:
12274       return "lock";
12275     case 0x2e:
12276       return "cs";
12277     case 0x36:
12278       return "ss";
12279     case 0x3e:
12280       return "ds";
12281     case 0x26:
12282       return "es";
12283     case 0x64:
12284       return "fs";
12285     case 0x65:
12286       return "gs";
12287     case 0x66:
12288       return (sizeflag & DFLAG) ? "data16" : "data32";
12289     case 0x67:
12290       if (address_mode == mode_64bit)
12291         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12292       else
12293         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12294     case FWAIT_OPCODE:
12295       return "fwait";
12296     case REP_PREFIX:
12297       return "rep";
12298     case XACQUIRE_PREFIX:
12299       return "xacquire";
12300     case XRELEASE_PREFIX:
12301       return "xrelease";
12302     case BND_PREFIX:
12303       return "bnd";
12304     default:
12305       return NULL;
12306     }
12307 }
12308
12309 static char op_out[MAX_OPERANDS][100];
12310 static int op_ad, op_index[MAX_OPERANDS];
12311 static int two_source_ops;
12312 static bfd_vma op_address[MAX_OPERANDS];
12313 static bfd_vma op_riprel[MAX_OPERANDS];
12314 static bfd_vma start_pc;
12315
12316 /*
12317  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12318  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12319  *   section of the "Virtual 8086 Mode" chapter.)
12320  * 'pc' should be the address of this instruction, it will
12321  *   be used to print the target address if this is a relative jump or call
12322  * The function returns the length of this instruction in bytes.
12323  */
12324
12325 static char intel_syntax;
12326 static char intel_mnemonic = !SYSV386_COMPAT;
12327 static char open_char;
12328 static char close_char;
12329 static char separator_char;
12330 static char scale_char;
12331
12332 /* Here for backwards compatibility.  When gdb stops using
12333    print_insn_i386_att and print_insn_i386_intel these functions can
12334    disappear, and print_insn_i386 be merged into print_insn.  */
12335 int
12336 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12337 {
12338   intel_syntax = 0;
12339
12340   return print_insn (pc, info);
12341 }
12342
12343 int
12344 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12345 {
12346   intel_syntax = 1;
12347
12348   return print_insn (pc, info);
12349 }
12350
12351 int
12352 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12353 {
12354   intel_syntax = -1;
12355
12356   return print_insn (pc, info);
12357 }
12358
12359 void
12360 print_i386_disassembler_options (FILE *stream)
12361 {
12362   fprintf (stream, _("\n\
12363 The following i386/x86-64 specific disassembler options are supported for use\n\
12364 with the -M switch (multiple options should be separated by commas):\n"));
12365
12366   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12367   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12368   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12369   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12370   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12371   fprintf (stream, _("  att-mnemonic\n"
12372                      "              Display instruction in AT&T mnemonic\n"));
12373   fprintf (stream, _("  intel-mnemonic\n"
12374                      "              Display instruction in Intel mnemonic\n"));
12375   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12376   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12377   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12378   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12379   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12380   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12381 }
12382
12383 /* Bad opcode.  */
12384 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12385
12386 /* Get a pointer to struct dis386 with a valid name.  */
12387
12388 static const struct dis386 *
12389 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12390 {
12391   int vindex, vex_table_index;
12392
12393   if (dp->name != NULL)
12394     return dp;
12395
12396   switch (dp->op[0].bytemode)
12397     {
12398     case USE_REG_TABLE:
12399       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12400       break;
12401
12402     case USE_MOD_TABLE:
12403       vindex = modrm.mod == 0x3 ? 1 : 0;
12404       dp = &mod_table[dp->op[1].bytemode][vindex];
12405       break;
12406
12407     case USE_RM_TABLE:
12408       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12409       break;
12410
12411     case USE_PREFIX_TABLE:
12412       if (need_vex)
12413         {
12414           /* The prefix in VEX is implicit.  */
12415           switch (vex.prefix)
12416             {
12417             case 0:
12418               vindex = 0;
12419               break;
12420             case REPE_PREFIX_OPCODE:
12421               vindex = 1;
12422               break;
12423             case DATA_PREFIX_OPCODE:
12424               vindex = 2;
12425               break;
12426             case REPNE_PREFIX_OPCODE:
12427               vindex = 3;
12428               break;
12429             default:
12430               abort ();
12431               break;
12432             }
12433         }
12434       else
12435         {
12436           int last_prefix = -1;
12437           int prefix = 0;
12438           vindex = 0;
12439           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12440              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12441              last one wins.  */
12442           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12443             {
12444               if (last_repz_prefix > last_repnz_prefix)
12445                 {
12446                   vindex = 1;
12447                   prefix = PREFIX_REPZ;
12448                   last_prefix = last_repz_prefix;
12449                 }
12450               else
12451                 {
12452                   vindex = 3;
12453                   prefix = PREFIX_REPNZ;
12454                   last_prefix = last_repnz_prefix;
12455                 }
12456
12457               /* Check if prefix should be ignored.  */
12458               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12459                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12460                    & prefix) != 0)
12461                 vindex = 0;
12462             }
12463
12464           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12465             {
12466               vindex = 2;
12467               prefix = PREFIX_DATA;
12468               last_prefix = last_data_prefix;
12469             }
12470
12471           if (vindex != 0)
12472             {
12473               used_prefixes |= prefix;
12474               all_prefixes[last_prefix] = 0;
12475             }
12476         }
12477       dp = &prefix_table[dp->op[1].bytemode][vindex];
12478       break;
12479
12480     case USE_X86_64_TABLE:
12481       vindex = address_mode == mode_64bit ? 1 : 0;
12482       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12483       break;
12484
12485     case USE_3BYTE_TABLE:
12486       FETCH_DATA (info, codep + 2);
12487       vindex = *codep++;
12488       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12489       end_codep = codep;
12490       modrm.mod = (*codep >> 6) & 3;
12491       modrm.reg = (*codep >> 3) & 7;
12492       modrm.rm = *codep & 7;
12493       break;
12494
12495     case USE_VEX_LEN_TABLE:
12496       if (!need_vex)
12497         abort ();
12498
12499       switch (vex.length)
12500         {
12501         case 128:
12502           vindex = 0;
12503           break;
12504         case 256:
12505           vindex = 1;
12506           break;
12507         default:
12508           abort ();
12509           break;
12510         }
12511
12512       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12513       break;
12514
12515     case USE_XOP_8F_TABLE:
12516       FETCH_DATA (info, codep + 3);
12517       /* All bits in the REX prefix are ignored.  */
12518       rex_ignored = rex;
12519       rex = ~(*codep >> 5) & 0x7;
12520
12521       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12522       switch ((*codep & 0x1f))
12523         {
12524         default:
12525           dp = &bad_opcode;
12526           return dp;
12527         case 0x8:
12528           vex_table_index = XOP_08;
12529           break;
12530         case 0x9:
12531           vex_table_index = XOP_09;
12532           break;
12533         case 0xa:
12534           vex_table_index = XOP_0A;
12535           break;
12536         }
12537       codep++;
12538       vex.w = *codep & 0x80;
12539       if (vex.w && address_mode == mode_64bit)
12540         rex |= REX_W;
12541
12542       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12543       if (address_mode != mode_64bit
12544           && vex.register_specifier > 0x7)
12545         {
12546           dp = &bad_opcode;
12547           return dp;
12548         }
12549
12550       vex.length = (*codep & 0x4) ? 256 : 128;
12551       switch ((*codep & 0x3))
12552         {
12553         case 0:
12554           vex.prefix = 0;
12555           break;
12556         case 1:
12557           vex.prefix = DATA_PREFIX_OPCODE;
12558           break;
12559         case 2:
12560           vex.prefix = REPE_PREFIX_OPCODE;
12561           break;
12562         case 3:
12563           vex.prefix = REPNE_PREFIX_OPCODE;
12564           break;
12565         }
12566       need_vex = 1;
12567       need_vex_reg = 1;
12568       codep++;
12569       vindex = *codep++;
12570       dp = &xop_table[vex_table_index][vindex];
12571
12572       end_codep = codep;
12573       FETCH_DATA (info, codep + 1);
12574       modrm.mod = (*codep >> 6) & 3;
12575       modrm.reg = (*codep >> 3) & 7;
12576       modrm.rm = *codep & 7;
12577       break;
12578
12579     case USE_VEX_C4_TABLE:
12580       /* VEX prefix.  */
12581       FETCH_DATA (info, codep + 3);
12582       /* All bits in the REX prefix are ignored.  */
12583       rex_ignored = rex;
12584       rex = ~(*codep >> 5) & 0x7;
12585       switch ((*codep & 0x1f))
12586         {
12587         default:
12588           dp = &bad_opcode;
12589           return dp;
12590         case 0x1:
12591           vex_table_index = VEX_0F;
12592           break;
12593         case 0x2:
12594           vex_table_index = VEX_0F38;
12595           break;
12596         case 0x3:
12597           vex_table_index = VEX_0F3A;
12598           break;
12599         }
12600       codep++;
12601       vex.w = *codep & 0x80;
12602       if (vex.w && address_mode == mode_64bit)
12603         rex |= REX_W;
12604
12605       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12606       if (address_mode != mode_64bit
12607           && vex.register_specifier > 0x7)
12608         {
12609           dp = &bad_opcode;
12610           return dp;
12611         }
12612
12613       vex.length = (*codep & 0x4) ? 256 : 128;
12614       switch ((*codep & 0x3))
12615         {
12616         case 0:
12617           vex.prefix = 0;
12618           break;
12619         case 1:
12620           vex.prefix = DATA_PREFIX_OPCODE;
12621           break;
12622         case 2:
12623           vex.prefix = REPE_PREFIX_OPCODE;
12624           break;
12625         case 3:
12626           vex.prefix = REPNE_PREFIX_OPCODE;
12627           break;
12628         }
12629       need_vex = 1;
12630       need_vex_reg = 1;
12631       codep++;
12632       vindex = *codep++;
12633       dp = &vex_table[vex_table_index][vindex];
12634       end_codep = codep;
12635       /* There is no MODRM byte for VEX [82|77].  */
12636       if (vindex != 0x77 && vindex != 0x82)
12637         {
12638           FETCH_DATA (info, codep + 1);
12639           modrm.mod = (*codep >> 6) & 3;
12640           modrm.reg = (*codep >> 3) & 7;
12641           modrm.rm = *codep & 7;
12642         }
12643       break;
12644
12645     case USE_VEX_C5_TABLE:
12646       /* VEX prefix.  */
12647       FETCH_DATA (info, codep + 2);
12648       /* All bits in the REX prefix are ignored.  */
12649       rex_ignored = rex;
12650       rex = (*codep & 0x80) ? 0 : REX_R;
12651
12652       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12653       if (address_mode != mode_64bit
12654           && vex.register_specifier > 0x7)
12655         {
12656           dp = &bad_opcode;
12657           return dp;
12658         }
12659
12660       vex.w = 0;
12661
12662       vex.length = (*codep & 0x4) ? 256 : 128;
12663       switch ((*codep & 0x3))
12664         {
12665         case 0:
12666           vex.prefix = 0;
12667           break;
12668         case 1:
12669           vex.prefix = DATA_PREFIX_OPCODE;
12670           break;
12671         case 2:
12672           vex.prefix = REPE_PREFIX_OPCODE;
12673           break;
12674         case 3:
12675           vex.prefix = REPNE_PREFIX_OPCODE;
12676           break;
12677         }
12678       need_vex = 1;
12679       need_vex_reg = 1;
12680       codep++;
12681       vindex = *codep++;
12682       dp = &vex_table[dp->op[1].bytemode][vindex];
12683       end_codep = codep;
12684       /* There is no MODRM byte for VEX [82|77].  */
12685       if (vindex != 0x77 && vindex != 0x82)
12686         {
12687           FETCH_DATA (info, codep + 1);
12688           modrm.mod = (*codep >> 6) & 3;
12689           modrm.reg = (*codep >> 3) & 7;
12690           modrm.rm = *codep & 7;
12691         }
12692       break;
12693
12694     case USE_VEX_W_TABLE:
12695       if (!need_vex)
12696         abort ();
12697
12698       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12699       break;
12700
12701     case USE_EVEX_TABLE:
12702       two_source_ops = 0;
12703       /* EVEX prefix.  */
12704       vex.evex = 1;
12705       FETCH_DATA (info, codep + 4);
12706       /* All bits in the REX prefix are ignored.  */
12707       rex_ignored = rex;
12708       /* The first byte after 0x62.  */
12709       rex = ~(*codep >> 5) & 0x7;
12710       vex.r = *codep & 0x10;
12711       switch ((*codep & 0xf))
12712         {
12713         default:
12714           return &bad_opcode;
12715         case 0x1:
12716           vex_table_index = EVEX_0F;
12717           break;
12718         case 0x2:
12719           vex_table_index = EVEX_0F38;
12720           break;
12721         case 0x3:
12722           vex_table_index = EVEX_0F3A;
12723           break;
12724         }
12725
12726       /* The second byte after 0x62.  */
12727       codep++;
12728       vex.w = *codep & 0x80;
12729       if (vex.w && address_mode == mode_64bit)
12730         rex |= REX_W;
12731
12732       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12733       if (address_mode != mode_64bit)
12734         {
12735           /* In 16/32-bit mode silently ignore following bits.  */
12736           rex &= ~REX_B;
12737           vex.r = 1;
12738           vex.v = 1;
12739           vex.register_specifier &= 0x7;
12740         }
12741
12742       /* The U bit.  */
12743       if (!(*codep & 0x4))
12744         return &bad_opcode;
12745
12746       switch ((*codep & 0x3))
12747         {
12748         case 0:
12749           vex.prefix = 0;
12750           break;
12751         case 1:
12752           vex.prefix = DATA_PREFIX_OPCODE;
12753           break;
12754         case 2:
12755           vex.prefix = REPE_PREFIX_OPCODE;
12756           break;
12757         case 3:
12758           vex.prefix = REPNE_PREFIX_OPCODE;
12759           break;
12760         }
12761
12762       /* The third byte after 0x62.  */
12763       codep++;
12764
12765       /* Remember the static rounding bits.  */
12766       vex.ll = (*codep >> 5) & 3;
12767       vex.b = (*codep & 0x10) != 0;
12768
12769       vex.v = *codep & 0x8;
12770       vex.mask_register_specifier = *codep & 0x7;
12771       vex.zeroing = *codep & 0x80;
12772
12773       need_vex = 1;
12774       need_vex_reg = 1;
12775       codep++;
12776       vindex = *codep++;
12777       dp = &evex_table[vex_table_index][vindex];
12778       end_codep = codep;
12779       FETCH_DATA (info, codep + 1);
12780       modrm.mod = (*codep >> 6) & 3;
12781       modrm.reg = (*codep >> 3) & 7;
12782       modrm.rm = *codep & 7;
12783
12784       /* Set vector length.  */
12785       if (modrm.mod == 3 && vex.b)
12786         vex.length = 512;
12787       else
12788         {
12789           switch (vex.ll)
12790             {
12791             case 0x0:
12792               vex.length = 128;
12793               break;
12794             case 0x1:
12795               vex.length = 256;
12796               break;
12797             case 0x2:
12798               vex.length = 512;
12799               break;
12800             default:
12801               return &bad_opcode;
12802             }
12803         }
12804       break;
12805
12806     case 0:
12807       dp = &bad_opcode;
12808       break;
12809
12810     default:
12811       abort ();
12812     }
12813
12814   if (dp->name != NULL)
12815     return dp;
12816   else
12817     return get_valid_dis386 (dp, info);
12818 }
12819
12820 static void
12821 get_sib (disassemble_info *info, int sizeflag)
12822 {
12823   /* If modrm.mod == 3, operand must be register.  */
12824   if (need_modrm
12825       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12826       && modrm.mod != 3
12827       && modrm.rm == 4)
12828     {
12829       FETCH_DATA (info, codep + 2);
12830       sib.index = (codep [1] >> 3) & 7;
12831       sib.scale = (codep [1] >> 6) & 3;
12832       sib.base = codep [1] & 7;
12833     }
12834 }
12835
12836 static int
12837 print_insn (bfd_vma pc, disassemble_info *info)
12838 {
12839   const struct dis386 *dp;
12840   int i;
12841   char *op_txt[MAX_OPERANDS];
12842   int needcomma;
12843   int sizeflag, orig_sizeflag;
12844   const char *p;
12845   struct dis_private priv;
12846   int prefix_length;
12847
12848   priv.orig_sizeflag = AFLAG | DFLAG;
12849   if ((info->mach & bfd_mach_i386_i386) != 0)
12850     address_mode = mode_32bit;
12851   else if (info->mach == bfd_mach_i386_i8086)
12852     {
12853       address_mode = mode_16bit;
12854       priv.orig_sizeflag = 0;
12855     }
12856   else
12857     address_mode = mode_64bit;
12858
12859   if (intel_syntax == (char) -1)
12860     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12861
12862   for (p = info->disassembler_options; p != NULL; )
12863     {
12864       if (CONST_STRNEQ (p, "x86-64"))
12865         {
12866           address_mode = mode_64bit;
12867           priv.orig_sizeflag = AFLAG | DFLAG;
12868         }
12869       else if (CONST_STRNEQ (p, "i386"))
12870         {
12871           address_mode = mode_32bit;
12872           priv.orig_sizeflag = AFLAG | DFLAG;
12873         }
12874       else if (CONST_STRNEQ (p, "i8086"))
12875         {
12876           address_mode = mode_16bit;
12877           priv.orig_sizeflag = 0;
12878         }
12879       else if (CONST_STRNEQ (p, "intel"))
12880         {
12881           intel_syntax = 1;
12882           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12883             intel_mnemonic = 1;
12884         }
12885       else if (CONST_STRNEQ (p, "att"))
12886         {
12887           intel_syntax = 0;
12888           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12889             intel_mnemonic = 0;
12890         }
12891       else if (CONST_STRNEQ (p, "addr"))
12892         {
12893           if (address_mode == mode_64bit)
12894             {
12895               if (p[4] == '3' && p[5] == '2')
12896                 priv.orig_sizeflag &= ~AFLAG;
12897               else if (p[4] == '6' && p[5] == '4')
12898                 priv.orig_sizeflag |= AFLAG;
12899             }
12900           else
12901             {
12902               if (p[4] == '1' && p[5] == '6')
12903                 priv.orig_sizeflag &= ~AFLAG;
12904               else if (p[4] == '3' && p[5] == '2')
12905                 priv.orig_sizeflag |= AFLAG;
12906             }
12907         }
12908       else if (CONST_STRNEQ (p, "data"))
12909         {
12910           if (p[4] == '1' && p[5] == '6')
12911             priv.orig_sizeflag &= ~DFLAG;
12912           else if (p[4] == '3' && p[5] == '2')
12913             priv.orig_sizeflag |= DFLAG;
12914         }
12915       else if (CONST_STRNEQ (p, "suffix"))
12916         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12917
12918       p = strchr (p, ',');
12919       if (p != NULL)
12920         p++;
12921     }
12922
12923   if (intel_syntax)
12924     {
12925       names64 = intel_names64;
12926       names32 = intel_names32;
12927       names16 = intel_names16;
12928       names8 = intel_names8;
12929       names8rex = intel_names8rex;
12930       names_seg = intel_names_seg;
12931       names_mm = intel_names_mm;
12932       names_bnd = intel_names_bnd;
12933       names_xmm = intel_names_xmm;
12934       names_ymm = intel_names_ymm;
12935       names_zmm = intel_names_zmm;
12936       index64 = intel_index64;
12937       index32 = intel_index32;
12938       names_mask = intel_names_mask;
12939       index16 = intel_index16;
12940       open_char = '[';
12941       close_char = ']';
12942       separator_char = '+';
12943       scale_char = '*';
12944     }
12945   else
12946     {
12947       names64 = att_names64;
12948       names32 = att_names32;
12949       names16 = att_names16;
12950       names8 = att_names8;
12951       names8rex = att_names8rex;
12952       names_seg = att_names_seg;
12953       names_mm = att_names_mm;
12954       names_bnd = att_names_bnd;
12955       names_xmm = att_names_xmm;
12956       names_ymm = att_names_ymm;
12957       names_zmm = att_names_zmm;
12958       index64 = att_index64;
12959       index32 = att_index32;
12960       names_mask = att_names_mask;
12961       index16 = att_index16;
12962       open_char = '(';
12963       close_char =  ')';
12964       separator_char = ',';
12965       scale_char = ',';
12966     }
12967
12968   /* The output looks better if we put 7 bytes on a line, since that
12969      puts most long word instructions on a single line.  Use 8 bytes
12970      for Intel L1OM.  */
12971   if ((info->mach & bfd_mach_l1om) != 0)
12972     info->bytes_per_line = 8;
12973   else
12974     info->bytes_per_line = 7;
12975
12976   info->private_data = &priv;
12977   priv.max_fetched = priv.the_buffer;
12978   priv.insn_start = pc;
12979
12980   obuf[0] = 0;
12981   for (i = 0; i < MAX_OPERANDS; ++i)
12982     {
12983       op_out[i][0] = 0;
12984       op_index[i] = -1;
12985     }
12986
12987   the_info = info;
12988   start_pc = pc;
12989   start_codep = priv.the_buffer;
12990   codep = priv.the_buffer;
12991
12992   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12993     {
12994       const char *name;
12995
12996       /* Getting here means we tried for data but didn't get it.  That
12997          means we have an incomplete instruction of some sort.  Just
12998          print the first byte as a prefix or a .byte pseudo-op.  */
12999       if (codep > priv.the_buffer)
13000         {
13001           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13002           if (name != NULL)
13003             (*info->fprintf_func) (info->stream, "%s", name);
13004           else
13005             {
13006               /* Just print the first byte as a .byte instruction.  */
13007               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13008                                      (unsigned int) priv.the_buffer[0]);
13009             }
13010
13011           return 1;
13012         }
13013
13014       return -1;
13015     }
13016
13017   obufp = obuf;
13018   sizeflag = priv.orig_sizeflag;
13019
13020   if (!ckprefix () || rex_used)
13021     {
13022       /* Too many prefixes or unused REX prefixes.  */
13023       for (i = 0;
13024            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13025            i++)
13026         (*info->fprintf_func) (info->stream, "%s%s",
13027                                i == 0 ? "" : " ",
13028                                prefix_name (all_prefixes[i], sizeflag));
13029       return i;
13030     }
13031
13032   insn_codep = codep;
13033
13034   FETCH_DATA (info, codep + 1);
13035   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13036
13037   if (((prefixes & PREFIX_FWAIT)
13038        && ((*codep < 0xd8) || (*codep > 0xdf))))
13039     {
13040       /* Handle prefixes before fwait.  */
13041       for (i = 0; i < fwait_prefix && all_prefixes[i];
13042            i++)
13043         (*info->fprintf_func) (info->stream, "%s ",
13044                                prefix_name (all_prefixes[i], sizeflag));
13045       (*info->fprintf_func) (info->stream, "fwait");
13046       return i + 1;
13047     }
13048
13049   if (*codep == 0x0f)
13050     {
13051       unsigned char threebyte;
13052       FETCH_DATA (info, codep + 2);
13053       threebyte = *++codep;
13054       dp = &dis386_twobyte[threebyte];
13055       need_modrm = twobyte_has_modrm[*codep];
13056       prefix_requirement = dp->prefix_requirement;
13057       codep++;
13058     }
13059   else
13060     {
13061       dp = &dis386[*codep];
13062       need_modrm = onebyte_has_modrm[*codep];
13063       prefix_requirement = 0;
13064       codep++;
13065     }
13066
13067   /* Save sizeflag for printing the extra prefixes later before updating
13068      it for mnemonic and operand processing.  The prefix names depend
13069      only on the address mode.  */
13070   orig_sizeflag = sizeflag;
13071   if (prefixes & PREFIX_ADDR)
13072     sizeflag ^= AFLAG;
13073   if ((prefixes & PREFIX_DATA))
13074     sizeflag ^= DFLAG;
13075
13076   end_codep = codep;
13077   if (need_modrm)
13078     {
13079       FETCH_DATA (info, codep + 1);
13080       modrm.mod = (*codep >> 6) & 3;
13081       modrm.reg = (*codep >> 3) & 7;
13082       modrm.rm = *codep & 7;
13083     }
13084
13085   need_vex = 0;
13086   need_vex_reg = 0;
13087   vex_w_done = 0;
13088   vex.evex = 0;
13089
13090   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13091     {
13092       get_sib (info, sizeflag);
13093       dofloat (sizeflag);
13094     }
13095   else
13096     {
13097       dp = get_valid_dis386 (dp, info);
13098       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13099         {
13100           get_sib (info, sizeflag);
13101           for (i = 0; i < MAX_OPERANDS; ++i)
13102             {
13103               obufp = op_out[i];
13104               op_ad = MAX_OPERANDS - 1 - i;
13105               if (dp->op[i].rtn)
13106                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13107               /* For EVEX instruction after the last operand masking
13108                  should be printed.  */
13109               if (i == 0 && vex.evex)
13110                 {
13111                   /* Don't print {%k0}.  */
13112                   if (vex.mask_register_specifier)
13113                     {
13114                       oappend ("{");
13115                       oappend (names_mask[vex.mask_register_specifier]);
13116                       oappend ("}");
13117                     }
13118                   if (vex.zeroing)
13119                     oappend ("{z}");
13120                 }
13121             }
13122         }
13123     }
13124
13125   /* Check if the REX prefix is used.  */
13126   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13127     all_prefixes[last_rex_prefix] = 0;
13128
13129   /* Check if the SEG prefix is used.  */
13130   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13131                    | PREFIX_FS | PREFIX_GS)) != 0
13132       && (used_prefixes & active_seg_prefix) != 0)
13133     all_prefixes[last_seg_prefix] = 0;
13134
13135   /* Check if the ADDR prefix is used.  */
13136   if ((prefixes & PREFIX_ADDR) != 0
13137       && (used_prefixes & PREFIX_ADDR) != 0)
13138     all_prefixes[last_addr_prefix] = 0;
13139
13140   /* Check if the DATA prefix is used.  */
13141   if ((prefixes & PREFIX_DATA) != 0
13142       && (used_prefixes & PREFIX_DATA) != 0)
13143     all_prefixes[last_data_prefix] = 0;
13144
13145   /* Print the extra prefixes.  */
13146   prefix_length = 0;
13147   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13148     if (all_prefixes[i])
13149       {
13150         const char *name;
13151         name = prefix_name (all_prefixes[i], orig_sizeflag);
13152         if (name == NULL)
13153           abort ();
13154         prefix_length += strlen (name) + 1;
13155         (*info->fprintf_func) (info->stream, "%s ", name);
13156       }
13157
13158   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13159      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13160      used by putop and MMX/SSE operand and may be overriden by the
13161      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13162      separately.  */
13163   if (prefix_requirement == PREFIX_OPCODE
13164       && dp != &bad_opcode
13165       && (((prefixes
13166             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13167            && (used_prefixes
13168                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13169           || ((((prefixes
13170                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13171                 == PREFIX_DATA)
13172                && (used_prefixes & PREFIX_DATA) == 0))))
13173     {
13174       (*info->fprintf_func) (info->stream, "(bad)");
13175       return end_codep - priv.the_buffer;
13176     }
13177
13178   /* Check maximum code length.  */
13179   if ((codep - start_codep) > MAX_CODE_LENGTH)
13180     {
13181       (*info->fprintf_func) (info->stream, "(bad)");
13182       return MAX_CODE_LENGTH;
13183     }
13184
13185   obufp = mnemonicendp;
13186   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13187     oappend (" ");
13188   oappend (" ");
13189   (*info->fprintf_func) (info->stream, "%s", obuf);
13190
13191   /* The enter and bound instructions are printed with operands in the same
13192      order as the intel book; everything else is printed in reverse order.  */
13193   if (intel_syntax || two_source_ops)
13194     {
13195       bfd_vma riprel;
13196
13197       for (i = 0; i < MAX_OPERANDS; ++i)
13198         op_txt[i] = op_out[i];
13199
13200       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13201         {
13202           op_ad = op_index[i];
13203           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13204           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13205           riprel = op_riprel[i];
13206           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13207           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13208         }
13209     }
13210   else
13211     {
13212       for (i = 0; i < MAX_OPERANDS; ++i)
13213         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13214     }
13215
13216   needcomma = 0;
13217   for (i = 0; i < MAX_OPERANDS; ++i)
13218     if (*op_txt[i])
13219       {
13220         if (needcomma)
13221           (*info->fprintf_func) (info->stream, ",");
13222         if (op_index[i] != -1 && !op_riprel[i])
13223           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13224         else
13225           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13226         needcomma = 1;
13227       }
13228
13229   for (i = 0; i < MAX_OPERANDS; i++)
13230     if (op_index[i] != -1 && op_riprel[i])
13231       {
13232         (*info->fprintf_func) (info->stream, "        # ");
13233         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13234                                                 + op_address[op_index[i]]), info);
13235         break;
13236       }
13237   return codep - priv.the_buffer;
13238 }
13239
13240 static const char *float_mem[] = {
13241   /* d8 */
13242   "fadd{s|}",
13243   "fmul{s|}",
13244   "fcom{s|}",
13245   "fcomp{s|}",
13246   "fsub{s|}",
13247   "fsubr{s|}",
13248   "fdiv{s|}",
13249   "fdivr{s|}",
13250   /* d9 */
13251   "fld{s|}",
13252   "(bad)",
13253   "fst{s|}",
13254   "fstp{s|}",
13255   "fldenvIC",
13256   "fldcw",
13257   "fNstenvIC",
13258   "fNstcw",
13259   /* da */
13260   "fiadd{l|}",
13261   "fimul{l|}",
13262   "ficom{l|}",
13263   "ficomp{l|}",
13264   "fisub{l|}",
13265   "fisubr{l|}",
13266   "fidiv{l|}",
13267   "fidivr{l|}",
13268   /* db */
13269   "fild{l|}",
13270   "fisttp{l|}",
13271   "fist{l|}",
13272   "fistp{l|}",
13273   "(bad)",
13274   "fld{t||t|}",
13275   "(bad)",
13276   "fstp{t||t|}",
13277   /* dc */
13278   "fadd{l|}",
13279   "fmul{l|}",
13280   "fcom{l|}",
13281   "fcomp{l|}",
13282   "fsub{l|}",
13283   "fsubr{l|}",
13284   "fdiv{l|}",
13285   "fdivr{l|}",
13286   /* dd */
13287   "fld{l|}",
13288   "fisttp{ll|}",
13289   "fst{l||}",
13290   "fstp{l|}",
13291   "frstorIC",
13292   "(bad)",
13293   "fNsaveIC",
13294   "fNstsw",
13295   /* de */
13296   "fiadd",
13297   "fimul",
13298   "ficom",
13299   "ficomp",
13300   "fisub",
13301   "fisubr",
13302   "fidiv",
13303   "fidivr",
13304   /* df */
13305   "fild",
13306   "fisttp",
13307   "fist",
13308   "fistp",
13309   "fbld",
13310   "fild{ll|}",
13311   "fbstp",
13312   "fistp{ll|}",
13313 };
13314
13315 static const unsigned char float_mem_mode[] = {
13316   /* d8 */
13317   d_mode,
13318   d_mode,
13319   d_mode,
13320   d_mode,
13321   d_mode,
13322   d_mode,
13323   d_mode,
13324   d_mode,
13325   /* d9 */
13326   d_mode,
13327   0,
13328   d_mode,
13329   d_mode,
13330   0,
13331   w_mode,
13332   0,
13333   w_mode,
13334   /* da */
13335   d_mode,
13336   d_mode,
13337   d_mode,
13338   d_mode,
13339   d_mode,
13340   d_mode,
13341   d_mode,
13342   d_mode,
13343   /* db */
13344   d_mode,
13345   d_mode,
13346   d_mode,
13347   d_mode,
13348   0,
13349   t_mode,
13350   0,
13351   t_mode,
13352   /* dc */
13353   q_mode,
13354   q_mode,
13355   q_mode,
13356   q_mode,
13357   q_mode,
13358   q_mode,
13359   q_mode,
13360   q_mode,
13361   /* dd */
13362   q_mode,
13363   q_mode,
13364   q_mode,
13365   q_mode,
13366   0,
13367   0,
13368   0,
13369   w_mode,
13370   /* de */
13371   w_mode,
13372   w_mode,
13373   w_mode,
13374   w_mode,
13375   w_mode,
13376   w_mode,
13377   w_mode,
13378   w_mode,
13379   /* df */
13380   w_mode,
13381   w_mode,
13382   w_mode,
13383   w_mode,
13384   t_mode,
13385   q_mode,
13386   t_mode,
13387   q_mode
13388 };
13389
13390 #define ST { OP_ST, 0 }
13391 #define STi { OP_STi, 0 }
13392
13393 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13394 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13395 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13396 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13397 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13398 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13399 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13400 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13401 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13402
13403 static const struct dis386 float_reg[][8] = {
13404   /* d8 */
13405   {
13406     { "fadd",   { ST, STi }, 0 },
13407     { "fmul",   { ST, STi }, 0 },
13408     { "fcom",   { STi }, 0 },
13409     { "fcomp",  { STi }, 0 },
13410     { "fsub",   { ST, STi }, 0 },
13411     { "fsubr",  { ST, STi }, 0 },
13412     { "fdiv",   { ST, STi }, 0 },
13413     { "fdivr",  { ST, STi }, 0 },
13414   },
13415   /* d9 */
13416   {
13417     { "fld",    { STi }, 0 },
13418     { "fxch",   { STi }, 0 },
13419     { FGRPd9_2 },
13420     { Bad_Opcode },
13421     { FGRPd9_4 },
13422     { FGRPd9_5 },
13423     { FGRPd9_6 },
13424     { FGRPd9_7 },
13425   },
13426   /* da */
13427   {
13428     { "fcmovb", { ST, STi }, 0 },
13429     { "fcmove", { ST, STi }, 0 },
13430     { "fcmovbe",{ ST, STi }, 0 },
13431     { "fcmovu", { ST, STi }, 0 },
13432     { Bad_Opcode },
13433     { FGRPda_5 },
13434     { Bad_Opcode },
13435     { Bad_Opcode },
13436   },
13437   /* db */
13438   {
13439     { "fcmovnb",{ ST, STi }, 0 },
13440     { "fcmovne",{ ST, STi }, 0 },
13441     { "fcmovnbe",{ ST, STi }, 0 },
13442     { "fcmovnu",{ ST, STi }, 0 },
13443     { FGRPdb_4 },
13444     { "fucomi", { ST, STi }, 0 },
13445     { "fcomi",  { ST, STi }, 0 },
13446     { Bad_Opcode },
13447   },
13448   /* dc */
13449   {
13450     { "fadd",   { STi, ST }, 0 },
13451     { "fmul",   { STi, ST }, 0 },
13452     { Bad_Opcode },
13453     { Bad_Opcode },
13454     { "fsub!M", { STi, ST }, 0 },
13455     { "fsubM",  { STi, ST }, 0 },
13456     { "fdiv!M", { STi, ST }, 0 },
13457     { "fdivM",  { STi, ST }, 0 },
13458   },
13459   /* dd */
13460   {
13461     { "ffree",  { STi }, 0 },
13462     { Bad_Opcode },
13463     { "fst",    { STi }, 0 },
13464     { "fstp",   { STi }, 0 },
13465     { "fucom",  { STi }, 0 },
13466     { "fucomp", { STi }, 0 },
13467     { Bad_Opcode },
13468     { Bad_Opcode },
13469   },
13470   /* de */
13471   {
13472     { "faddp",  { STi, ST }, 0 },
13473     { "fmulp",  { STi, ST }, 0 },
13474     { Bad_Opcode },
13475     { FGRPde_3 },
13476     { "fsub!Mp", { STi, ST }, 0 },
13477     { "fsubMp", { STi, ST }, 0 },
13478     { "fdiv!Mp", { STi, ST }, 0 },
13479     { "fdivMp", { STi, ST }, 0 },
13480   },
13481   /* df */
13482   {
13483     { "ffreep", { STi }, 0 },
13484     { Bad_Opcode },
13485     { Bad_Opcode },
13486     { Bad_Opcode },
13487     { FGRPdf_4 },
13488     { "fucomip", { ST, STi }, 0 },
13489     { "fcomip", { ST, STi }, 0 },
13490     { Bad_Opcode },
13491   },
13492 };
13493
13494 static char *fgrps[][8] = {
13495   /* d9_2  0 */
13496   {
13497     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13498   },
13499
13500   /* d9_4  1 */
13501   {
13502     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13503   },
13504
13505   /* d9_5  2 */
13506   {
13507     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13508   },
13509
13510   /* d9_6  3 */
13511   {
13512     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13513   },
13514
13515   /* d9_7  4 */
13516   {
13517     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13518   },
13519
13520   /* da_5  5 */
13521   {
13522     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13523   },
13524
13525   /* db_4  6 */
13526   {
13527     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13528     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13529   },
13530
13531   /* de_3  7 */
13532   {
13533     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13534   },
13535
13536   /* df_4  8 */
13537   {
13538     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13539   },
13540 };
13541
13542 static void
13543 swap_operand (void)
13544 {
13545   mnemonicendp[0] = '.';
13546   mnemonicendp[1] = 's';
13547   mnemonicendp += 2;
13548 }
13549
13550 static void
13551 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13552                int sizeflag ATTRIBUTE_UNUSED)
13553 {
13554   /* Skip mod/rm byte.  */
13555   MODRM_CHECK;
13556   codep++;
13557 }
13558
13559 static void
13560 dofloat (int sizeflag)
13561 {
13562   const struct dis386 *dp;
13563   unsigned char floatop;
13564
13565   floatop = codep[-1];
13566
13567   if (modrm.mod != 3)
13568     {
13569       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13570
13571       putop (float_mem[fp_indx], sizeflag);
13572       obufp = op_out[0];
13573       op_ad = 2;
13574       OP_E (float_mem_mode[fp_indx], sizeflag);
13575       return;
13576     }
13577   /* Skip mod/rm byte.  */
13578   MODRM_CHECK;
13579   codep++;
13580
13581   dp = &float_reg[floatop - 0xd8][modrm.reg];
13582   if (dp->name == NULL)
13583     {
13584       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13585
13586       /* Instruction fnstsw is only one with strange arg.  */
13587       if (floatop == 0xdf && codep[-1] == 0xe0)
13588         strcpy (op_out[0], names16[0]);
13589     }
13590   else
13591     {
13592       putop (dp->name, sizeflag);
13593
13594       obufp = op_out[0];
13595       op_ad = 2;
13596       if (dp->op[0].rtn)
13597         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13598
13599       obufp = op_out[1];
13600       op_ad = 1;
13601       if (dp->op[1].rtn)
13602         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13603     }
13604 }
13605
13606 /* Like oappend (below), but S is a string starting with '%'.
13607    In Intel syntax, the '%' is elided.  */
13608 static void
13609 oappend_maybe_intel (const char *s)
13610 {
13611   oappend (s + intel_syntax);
13612 }
13613
13614 static void
13615 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13616 {
13617   oappend_maybe_intel ("%st");
13618 }
13619
13620 static void
13621 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13622 {
13623   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13624   oappend_maybe_intel (scratchbuf);
13625 }
13626
13627 /* Capital letters in template are macros.  */
13628 static int
13629 putop (const char *in_template, int sizeflag)
13630 {
13631   const char *p;
13632   int alt = 0;
13633   int cond = 1;
13634   unsigned int l = 0, len = 1;
13635   char last[4];
13636
13637 #define SAVE_LAST(c)                    \
13638   if (l < len && l < sizeof (last))     \
13639     last[l++] = c;                      \
13640   else                                  \
13641     abort ();
13642
13643   for (p = in_template; *p; p++)
13644     {
13645       switch (*p)
13646         {
13647         default:
13648           *obufp++ = *p;
13649           break;
13650         case '%':
13651           len++;
13652           break;
13653         case '!':
13654           cond = 0;
13655           break;
13656         case '{':
13657           alt = 0;
13658           if (intel_syntax)
13659             {
13660               while (*++p != '|')
13661                 if (*p == '}' || *p == '\0')
13662                   abort ();
13663             }
13664           /* Fall through.  */
13665         case 'I':
13666           alt = 1;
13667           continue;
13668         case '|':
13669           while (*++p != '}')
13670             {
13671               if (*p == '\0')
13672                 abort ();
13673             }
13674           break;
13675         case '}':
13676           break;
13677         case 'A':
13678           if (intel_syntax)
13679             break;
13680           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13681             *obufp++ = 'b';
13682           break;
13683         case 'B':
13684           if (l == 0 && len == 1)
13685             {
13686 case_B:
13687               if (intel_syntax)
13688                 break;
13689               if (sizeflag & SUFFIX_ALWAYS)
13690                 *obufp++ = 'b';
13691             }
13692           else
13693             {
13694               if (l != 1
13695                   || len != 2
13696                   || last[0] != 'L')
13697                 {
13698                   SAVE_LAST (*p);
13699                   break;
13700                 }
13701
13702               if (address_mode == mode_64bit
13703                   && !(prefixes & PREFIX_ADDR))
13704                 {
13705                   *obufp++ = 'a';
13706                   *obufp++ = 'b';
13707                   *obufp++ = 's';
13708                 }
13709
13710               goto case_B;
13711             }
13712           break;
13713         case 'C':
13714           if (intel_syntax && !alt)
13715             break;
13716           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13717             {
13718               if (sizeflag & DFLAG)
13719                 *obufp++ = intel_syntax ? 'd' : 'l';
13720               else
13721                 *obufp++ = intel_syntax ? 'w' : 's';
13722               used_prefixes |= (prefixes & PREFIX_DATA);
13723             }
13724           break;
13725         case 'D':
13726           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13727             break;
13728           USED_REX (REX_W);
13729           if (modrm.mod == 3)
13730             {
13731               if (rex & REX_W)
13732                 *obufp++ = 'q';
13733               else
13734                 {
13735                   if (sizeflag & DFLAG)
13736                     *obufp++ = intel_syntax ? 'd' : 'l';
13737                   else
13738                     *obufp++ = 'w';
13739                   used_prefixes |= (prefixes & PREFIX_DATA);
13740                 }
13741             }
13742           else
13743             *obufp++ = 'w';
13744           break;
13745         case 'E':               /* For jcxz/jecxz */
13746           if (address_mode == mode_64bit)
13747             {
13748               if (sizeflag & AFLAG)
13749                 *obufp++ = 'r';
13750               else
13751                 *obufp++ = 'e';
13752             }
13753           else
13754             if (sizeflag & AFLAG)
13755               *obufp++ = 'e';
13756           used_prefixes |= (prefixes & PREFIX_ADDR);
13757           break;
13758         case 'F':
13759           if (intel_syntax)
13760             break;
13761           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13762             {
13763               if (sizeflag & AFLAG)
13764                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13765               else
13766                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13767               used_prefixes |= (prefixes & PREFIX_ADDR);
13768             }
13769           break;
13770         case 'G':
13771           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13772             break;
13773           if ((rex & REX_W) || (sizeflag & DFLAG))
13774             *obufp++ = 'l';
13775           else
13776             *obufp++ = 'w';
13777           if (!(rex & REX_W))
13778             used_prefixes |= (prefixes & PREFIX_DATA);
13779           break;
13780         case 'H':
13781           if (intel_syntax)
13782             break;
13783           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13784               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13785             {
13786               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13787               *obufp++ = ',';
13788               *obufp++ = 'p';
13789               if (prefixes & PREFIX_DS)
13790                 *obufp++ = 't';
13791               else
13792                 *obufp++ = 'n';
13793             }
13794           break;
13795         case 'J':
13796           if (intel_syntax)
13797             break;
13798           *obufp++ = 'l';
13799           break;
13800         case 'K':
13801           USED_REX (REX_W);
13802           if (rex & REX_W)
13803             *obufp++ = 'q';
13804           else
13805             *obufp++ = 'd';
13806           break;
13807         case 'Z':
13808           if (intel_syntax)
13809             break;
13810           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13811             {
13812               *obufp++ = 'q';
13813               break;
13814             }
13815           /* Fall through.  */
13816           goto case_L;
13817         case 'L':
13818           if (l != 0 || len != 1)
13819             {
13820               SAVE_LAST (*p);
13821               break;
13822             }
13823 case_L:
13824           if (intel_syntax)
13825             break;
13826           if (sizeflag & SUFFIX_ALWAYS)
13827             *obufp++ = 'l';
13828           break;
13829         case 'M':
13830           if (intel_mnemonic != cond)
13831             *obufp++ = 'r';
13832           break;
13833         case 'N':
13834           if ((prefixes & PREFIX_FWAIT) == 0)
13835             *obufp++ = 'n';
13836           else
13837             used_prefixes |= PREFIX_FWAIT;
13838           break;
13839         case 'O':
13840           USED_REX (REX_W);
13841           if (rex & REX_W)
13842             *obufp++ = 'o';
13843           else if (intel_syntax && (sizeflag & DFLAG))
13844             *obufp++ = 'q';
13845           else
13846             *obufp++ = 'd';
13847           if (!(rex & REX_W))
13848             used_prefixes |= (prefixes & PREFIX_DATA);
13849           break;
13850         case 'T':
13851           if (!intel_syntax
13852               && address_mode == mode_64bit
13853               && ((sizeflag & DFLAG) || (rex & REX_W)))
13854             {
13855               *obufp++ = 'q';
13856               break;
13857             }
13858           /* Fall through.  */
13859           goto case_P;
13860         case 'P':
13861           if (l == 0 && len == 1)
13862             {
13863 case_P:
13864               if (intel_syntax)
13865                 {
13866                   if ((rex & REX_W) == 0
13867                       && (prefixes & PREFIX_DATA))
13868                     {
13869                       if ((sizeflag & DFLAG) == 0)
13870                         *obufp++ = 'w';
13871                       used_prefixes |= (prefixes & PREFIX_DATA);
13872                     }
13873                   break;
13874                 }
13875               if ((prefixes & PREFIX_DATA)
13876                   || (rex & REX_W)
13877                   || (sizeflag & SUFFIX_ALWAYS))
13878                 {
13879                   USED_REX (REX_W);
13880                   if (rex & REX_W)
13881                     *obufp++ = 'q';
13882                   else
13883                     {
13884                       if (sizeflag & DFLAG)
13885                         *obufp++ = 'l';
13886                       else
13887                         *obufp++ = 'w';
13888                       used_prefixes |= (prefixes & PREFIX_DATA);
13889                     }
13890                 }
13891             }
13892           else
13893             {
13894               if (l != 1 || len != 2 || last[0] != 'L')
13895                 {
13896                   SAVE_LAST (*p);
13897                   break;
13898                 }
13899
13900               if ((prefixes & PREFIX_DATA)
13901                   || (rex & REX_W)
13902                   || (sizeflag & SUFFIX_ALWAYS))
13903                 {
13904                   USED_REX (REX_W);
13905                   if (rex & REX_W)
13906                     *obufp++ = 'q';
13907                   else
13908                     {
13909                       if (sizeflag & DFLAG)
13910                         *obufp++ = intel_syntax ? 'd' : 'l';
13911                       else
13912                         *obufp++ = 'w';
13913                       used_prefixes |= (prefixes & PREFIX_DATA);
13914                     }
13915                 }
13916             }
13917           break;
13918         case 'U':
13919           if (intel_syntax)
13920             break;
13921           if (address_mode == mode_64bit
13922               && ((sizeflag & DFLAG) || (rex & REX_W)))
13923             {
13924               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13925                 *obufp++ = 'q';
13926               break;
13927             }
13928           /* Fall through.  */
13929           goto case_Q;
13930         case 'Q':
13931           if (l == 0 && len == 1)
13932             {
13933 case_Q:
13934               if (intel_syntax && !alt)
13935                 break;
13936               USED_REX (REX_W);
13937               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13938                 {
13939                   if (rex & REX_W)
13940                     *obufp++ = 'q';
13941                   else
13942                     {
13943                       if (sizeflag & DFLAG)
13944                         *obufp++ = intel_syntax ? 'd' : 'l';
13945                       else
13946                         *obufp++ = 'w';
13947                       used_prefixes |= (prefixes & PREFIX_DATA);
13948                     }
13949                 }
13950             }
13951           else
13952             {
13953               if (l != 1 || len != 2 || last[0] != 'L')
13954                 {
13955                   SAVE_LAST (*p);
13956                   break;
13957                 }
13958               if (intel_syntax
13959                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13960                 break;
13961               if ((rex & REX_W))
13962                 {
13963                   USED_REX (REX_W);
13964                   *obufp++ = 'q';
13965                 }
13966               else
13967                 *obufp++ = 'l';
13968             }
13969           break;
13970         case 'R':
13971           USED_REX (REX_W);
13972           if (rex & REX_W)
13973             *obufp++ = 'q';
13974           else if (sizeflag & DFLAG)
13975             {
13976               if (intel_syntax)
13977                   *obufp++ = 'd';
13978               else
13979                   *obufp++ = 'l';
13980             }
13981           else
13982             *obufp++ = 'w';
13983           if (intel_syntax && !p[1]
13984               && ((rex & REX_W) || (sizeflag & DFLAG)))
13985             *obufp++ = 'e';
13986           if (!(rex & REX_W))
13987             used_prefixes |= (prefixes & PREFIX_DATA);
13988           break;
13989         case 'V':
13990           if (l == 0 && len == 1)
13991             {
13992               if (intel_syntax)
13993                 break;
13994               if (address_mode == mode_64bit
13995                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13996                 {
13997                   if (sizeflag & SUFFIX_ALWAYS)
13998                     *obufp++ = 'q';
13999                   break;
14000                 }
14001             }
14002           else
14003             {
14004               if (l != 1
14005                   || len != 2
14006                   || last[0] != 'L')
14007                 {
14008                   SAVE_LAST (*p);
14009                   break;
14010                 }
14011
14012               if (rex & REX_W)
14013                 {
14014                   *obufp++ = 'a';
14015                   *obufp++ = 'b';
14016                   *obufp++ = 's';
14017                 }
14018             }
14019           /* Fall through.  */
14020           goto case_S;
14021         case 'S':
14022           if (l == 0 && len == 1)
14023             {
14024 case_S:
14025               if (intel_syntax)
14026                 break;
14027               if (sizeflag & SUFFIX_ALWAYS)
14028                 {
14029                   if (rex & REX_W)
14030                     *obufp++ = 'q';
14031                   else
14032                     {
14033                       if (sizeflag & DFLAG)
14034                         *obufp++ = 'l';
14035                       else
14036                         *obufp++ = 'w';
14037                       used_prefixes |= (prefixes & PREFIX_DATA);
14038                     }
14039                 }
14040             }
14041           else
14042             {
14043               if (l != 1
14044                   || len != 2
14045                   || last[0] != 'L')
14046                 {
14047                   SAVE_LAST (*p);
14048                   break;
14049                 }
14050
14051               if (address_mode == mode_64bit
14052                   && !(prefixes & PREFIX_ADDR))
14053                 {
14054                   *obufp++ = 'a';
14055                   *obufp++ = 'b';
14056                   *obufp++ = 's';
14057                 }
14058
14059               goto case_S;
14060             }
14061           break;
14062         case 'X':
14063           if (l != 0 || len != 1)
14064             {
14065               SAVE_LAST (*p);
14066               break;
14067             }
14068           if (need_vex && vex.prefix)
14069             {
14070               if (vex.prefix == DATA_PREFIX_OPCODE)
14071                 *obufp++ = 'd';
14072               else
14073                 *obufp++ = 's';
14074             }
14075           else
14076             {
14077               if (prefixes & PREFIX_DATA)
14078                 *obufp++ = 'd';
14079               else
14080                 *obufp++ = 's';
14081               used_prefixes |= (prefixes & PREFIX_DATA);
14082             }
14083           break;
14084         case 'Y':
14085           if (l == 0 && len == 1)
14086             {
14087               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14088                 break;
14089               if (rex & REX_W)
14090                 {
14091                   USED_REX (REX_W);
14092                   *obufp++ = 'q';
14093                 }
14094               break;
14095             }
14096           else
14097             {
14098               if (l != 1 || len != 2 || last[0] != 'X')
14099                 {
14100                   SAVE_LAST (*p);
14101                   break;
14102                 }
14103               if (!need_vex)
14104                 abort ();
14105               if (intel_syntax
14106                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14107                 break;
14108               switch (vex.length)
14109                 {
14110                 case 128:
14111                   *obufp++ = 'x';
14112                   break;
14113                 case 256:
14114                   *obufp++ = 'y';
14115                   break;
14116                 default:
14117                   abort ();
14118                 }
14119             }
14120           break;
14121         case 'W':
14122           if (l == 0 && len == 1)
14123             {
14124               /* operand size flag for cwtl, cbtw */
14125               USED_REX (REX_W);
14126               if (rex & REX_W)
14127                 {
14128                   if (intel_syntax)
14129                     *obufp++ = 'd';
14130                   else
14131                     *obufp++ = 'l';
14132                 }
14133               else if (sizeflag & DFLAG)
14134                 *obufp++ = 'w';
14135               else
14136                 *obufp++ = 'b';
14137               if (!(rex & REX_W))
14138                 used_prefixes |= (prefixes & PREFIX_DATA);
14139             }
14140           else
14141             {
14142               if (l != 1
14143                   || len != 2
14144                   || (last[0] != 'X'
14145                       && last[0] != 'L'))
14146                 {
14147                   SAVE_LAST (*p);
14148                   break;
14149                 }
14150               if (!need_vex)
14151                 abort ();
14152               if (last[0] == 'X')
14153                 *obufp++ = vex.w ? 'd': 's';
14154               else
14155                 *obufp++ = vex.w ? 'q': 'd';
14156             }
14157           break;
14158         }
14159       alt = 0;
14160     }
14161   *obufp = 0;
14162   mnemonicendp = obufp;
14163   return 0;
14164 }
14165
14166 static void
14167 oappend (const char *s)
14168 {
14169   obufp = stpcpy (obufp, s);
14170 }
14171
14172 static void
14173 append_seg (void)
14174 {
14175   /* Only print the active segment register.  */
14176   if (!active_seg_prefix)
14177     return;
14178
14179   used_prefixes |= active_seg_prefix;
14180   switch (active_seg_prefix)
14181     {
14182     case PREFIX_CS:
14183       oappend_maybe_intel ("%cs:");
14184       break;
14185     case PREFIX_DS:
14186       oappend_maybe_intel ("%ds:");
14187       break;
14188     case PREFIX_SS:
14189       oappend_maybe_intel ("%ss:");
14190       break;
14191     case PREFIX_ES:
14192       oappend_maybe_intel ("%es:");
14193       break;
14194     case PREFIX_FS:
14195       oappend_maybe_intel ("%fs:");
14196       break;
14197     case PREFIX_GS:
14198       oappend_maybe_intel ("%gs:");
14199       break;
14200     default:
14201       break;
14202     }
14203 }
14204
14205 static void
14206 OP_indirE (int bytemode, int sizeflag)
14207 {
14208   if (!intel_syntax)
14209     oappend ("*");
14210   OP_E (bytemode, sizeflag);
14211 }
14212
14213 static void
14214 print_operand_value (char *buf, int hex, bfd_vma disp)
14215 {
14216   if (address_mode == mode_64bit)
14217     {
14218       if (hex)
14219         {
14220           char tmp[30];
14221           int i;
14222           buf[0] = '0';
14223           buf[1] = 'x';
14224           sprintf_vma (tmp, disp);
14225           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14226           strcpy (buf + 2, tmp + i);
14227         }
14228       else
14229         {
14230           bfd_signed_vma v = disp;
14231           char tmp[30];
14232           int i;
14233           if (v < 0)
14234             {
14235               *(buf++) = '-';
14236               v = -disp;
14237               /* Check for possible overflow on 0x8000000000000000.  */
14238               if (v < 0)
14239                 {
14240                   strcpy (buf, "9223372036854775808");
14241                   return;
14242                 }
14243             }
14244           if (!v)
14245             {
14246               strcpy (buf, "0");
14247               return;
14248             }
14249
14250           i = 0;
14251           tmp[29] = 0;
14252           while (v)
14253             {
14254               tmp[28 - i] = (v % 10) + '0';
14255               v /= 10;
14256               i++;
14257             }
14258           strcpy (buf, tmp + 29 - i);
14259         }
14260     }
14261   else
14262     {
14263       if (hex)
14264         sprintf (buf, "0x%x", (unsigned int) disp);
14265       else
14266         sprintf (buf, "%d", (int) disp);
14267     }
14268 }
14269
14270 /* Put DISP in BUF as signed hex number.  */
14271
14272 static void
14273 print_displacement (char *buf, bfd_vma disp)
14274 {
14275   bfd_signed_vma val = disp;
14276   char tmp[30];
14277   int i, j = 0;
14278
14279   if (val < 0)
14280     {
14281       buf[j++] = '-';
14282       val = -disp;
14283
14284       /* Check for possible overflow.  */
14285       if (val < 0)
14286         {
14287           switch (address_mode)
14288             {
14289             case mode_64bit:
14290               strcpy (buf + j, "0x8000000000000000");
14291               break;
14292             case mode_32bit:
14293               strcpy (buf + j, "0x80000000");
14294               break;
14295             case mode_16bit:
14296               strcpy (buf + j, "0x8000");
14297               break;
14298             }
14299           return;
14300         }
14301     }
14302
14303   buf[j++] = '0';
14304   buf[j++] = 'x';
14305
14306   sprintf_vma (tmp, (bfd_vma) val);
14307   for (i = 0; tmp[i] == '0'; i++)
14308     continue;
14309   if (tmp[i] == '\0')
14310     i--;
14311   strcpy (buf + j, tmp + i);
14312 }
14313
14314 static void
14315 intel_operand_size (int bytemode, int sizeflag)
14316 {
14317   if (vex.evex
14318       && vex.b
14319       && (bytemode == x_mode
14320           || bytemode == evex_half_bcst_xmmq_mode))
14321     {
14322       if (vex.w)
14323         oappend ("QWORD PTR ");
14324       else
14325         oappend ("DWORD PTR ");
14326       return;
14327     }
14328   switch (bytemode)
14329     {
14330     case b_mode:
14331     case b_swap_mode:
14332     case dqb_mode:
14333     case db_mode:
14334       oappend ("BYTE PTR ");
14335       break;
14336     case w_mode:
14337     case dw_mode:
14338     case dqw_mode:
14339     case dqw_swap_mode:
14340       oappend ("WORD PTR ");
14341       break;
14342     case stack_v_mode:
14343       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14344         {
14345           oappend ("QWORD PTR ");
14346           break;
14347         }
14348       /* FALLTHRU */
14349     case v_mode:
14350     case v_swap_mode:
14351     case dq_mode:
14352       USED_REX (REX_W);
14353       if (rex & REX_W)
14354         oappend ("QWORD PTR ");
14355       else
14356         {
14357           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14358             oappend ("DWORD PTR ");
14359           else
14360             oappend ("WORD PTR ");
14361           used_prefixes |= (prefixes & PREFIX_DATA);
14362         }
14363       break;
14364     case z_mode:
14365       if ((rex & REX_W) || (sizeflag & DFLAG))
14366         *obufp++ = 'D';
14367       oappend ("WORD PTR ");
14368       if (!(rex & REX_W))
14369         used_prefixes |= (prefixes & PREFIX_DATA);
14370       break;
14371     case a_mode:
14372       if (sizeflag & DFLAG)
14373         oappend ("QWORD PTR ");
14374       else
14375         oappend ("DWORD PTR ");
14376       used_prefixes |= (prefixes & PREFIX_DATA);
14377       break;
14378     case d_mode:
14379     case d_scalar_mode:
14380     case d_scalar_swap_mode:
14381     case d_swap_mode:
14382     case dqd_mode:
14383       oappend ("DWORD PTR ");
14384       break;
14385     case q_mode:
14386     case q_scalar_mode:
14387     case q_scalar_swap_mode:
14388     case q_swap_mode:
14389       oappend ("QWORD PTR ");
14390       break;
14391     case m_mode:
14392       if (address_mode == mode_64bit)
14393         oappend ("QWORD PTR ");
14394       else
14395         oappend ("DWORD PTR ");
14396       break;
14397     case f_mode:
14398       if (sizeflag & DFLAG)
14399         oappend ("FWORD PTR ");
14400       else
14401         oappend ("DWORD PTR ");
14402       used_prefixes |= (prefixes & PREFIX_DATA);
14403       break;
14404     case t_mode:
14405       oappend ("TBYTE PTR ");
14406       break;
14407     case x_mode:
14408     case x_swap_mode:
14409     case evex_x_gscat_mode:
14410     case evex_x_nobcst_mode:
14411       if (need_vex)
14412         {
14413           switch (vex.length)
14414             {
14415             case 128:
14416               oappend ("XMMWORD PTR ");
14417               break;
14418             case 256:
14419               oappend ("YMMWORD PTR ");
14420               break;
14421             case 512:
14422               oappend ("ZMMWORD PTR ");
14423               break;
14424             default:
14425               abort ();
14426             }
14427         }
14428       else
14429         oappend ("XMMWORD PTR ");
14430       break;
14431     case xmm_mode:
14432       oappend ("XMMWORD PTR ");
14433       break;
14434     case ymm_mode:
14435       oappend ("YMMWORD PTR ");
14436       break;
14437     case xmmq_mode:
14438     case evex_half_bcst_xmmq_mode:
14439       if (!need_vex)
14440         abort ();
14441
14442       switch (vex.length)
14443         {
14444         case 128:
14445           oappend ("QWORD PTR ");
14446           break;
14447         case 256:
14448           oappend ("XMMWORD PTR ");
14449           break;
14450         case 512:
14451           oappend ("YMMWORD PTR ");
14452           break;
14453         default:
14454           abort ();
14455         }
14456       break;
14457     case xmm_mb_mode:
14458       if (!need_vex)
14459         abort ();
14460
14461       switch (vex.length)
14462         {
14463         case 128:
14464         case 256:
14465         case 512:
14466           oappend ("BYTE PTR ");
14467           break;
14468         default:
14469           abort ();
14470         }
14471       break;
14472     case xmm_mw_mode:
14473       if (!need_vex)
14474         abort ();
14475
14476       switch (vex.length)
14477         {
14478         case 128:
14479         case 256:
14480         case 512:
14481           oappend ("WORD PTR ");
14482           break;
14483         default:
14484           abort ();
14485         }
14486       break;
14487     case xmm_md_mode:
14488       if (!need_vex)
14489         abort ();
14490
14491       switch (vex.length)
14492         {
14493         case 128:
14494         case 256:
14495         case 512:
14496           oappend ("DWORD PTR ");
14497           break;
14498         default:
14499           abort ();
14500         }
14501       break;
14502     case xmm_mq_mode:
14503       if (!need_vex)
14504         abort ();
14505
14506       switch (vex.length)
14507         {
14508         case 128:
14509         case 256:
14510         case 512:
14511           oappend ("QWORD PTR ");
14512           break;
14513         default:
14514           abort ();
14515         }
14516       break;
14517     case xmmdw_mode:
14518       if (!need_vex)
14519         abort ();
14520
14521       switch (vex.length)
14522         {
14523         case 128:
14524           oappend ("WORD PTR ");
14525           break;
14526         case 256:
14527           oappend ("DWORD PTR ");
14528           break;
14529         case 512:
14530           oappend ("QWORD PTR ");
14531           break;
14532         default:
14533           abort ();
14534         }
14535       break;
14536     case xmmqd_mode:
14537       if (!need_vex)
14538         abort ();
14539
14540       switch (vex.length)
14541         {
14542         case 128:
14543           oappend ("DWORD PTR ");
14544           break;
14545         case 256:
14546           oappend ("QWORD PTR ");
14547           break;
14548         case 512:
14549           oappend ("XMMWORD PTR ");
14550           break;
14551         default:
14552           abort ();
14553         }
14554       break;
14555     case ymmq_mode:
14556       if (!need_vex)
14557         abort ();
14558
14559       switch (vex.length)
14560         {
14561         case 128:
14562           oappend ("QWORD PTR ");
14563           break;
14564         case 256:
14565           oappend ("YMMWORD PTR ");
14566           break;
14567         case 512:
14568           oappend ("ZMMWORD PTR ");
14569           break;
14570         default:
14571           abort ();
14572         }
14573       break;
14574     case ymmxmm_mode:
14575       if (!need_vex)
14576         abort ();
14577
14578       switch (vex.length)
14579         {
14580         case 128:
14581         case 256:
14582           oappend ("XMMWORD PTR ");
14583           break;
14584         default:
14585           abort ();
14586         }
14587       break;
14588     case o_mode:
14589       oappend ("OWORD PTR ");
14590       break;
14591     case xmm_mdq_mode:
14592     case vex_w_dq_mode:
14593     case vex_scalar_w_dq_mode:
14594       if (!need_vex)
14595         abort ();
14596
14597       if (vex.w)
14598         oappend ("QWORD PTR ");
14599       else
14600         oappend ("DWORD PTR ");
14601       break;
14602     case vex_vsib_d_w_dq_mode:
14603     case vex_vsib_q_w_dq_mode:
14604       if (!need_vex)
14605         abort ();
14606
14607       if (!vex.evex)
14608         {
14609           if (vex.w)
14610             oappend ("QWORD PTR ");
14611           else
14612             oappend ("DWORD PTR ");
14613         }
14614       else
14615         {
14616           switch (vex.length)
14617             {
14618             case 128:
14619               oappend ("XMMWORD PTR ");
14620               break;
14621             case 256:
14622               oappend ("YMMWORD PTR ");
14623               break;
14624             case 512:
14625               oappend ("ZMMWORD PTR ");
14626               break;
14627             default:
14628               abort ();
14629             }
14630         }
14631       break;
14632     case vex_vsib_q_w_d_mode:
14633     case vex_vsib_d_w_d_mode:
14634       if (!need_vex || !vex.evex)
14635         abort ();
14636
14637       switch (vex.length)
14638         {
14639         case 128:
14640           oappend ("QWORD PTR ");
14641           break;
14642         case 256:
14643           oappend ("XMMWORD PTR ");
14644           break;
14645         case 512:
14646           oappend ("YMMWORD PTR ");
14647           break;
14648         default:
14649           abort ();
14650         }
14651
14652       break;
14653     case mask_bd_mode:
14654       if (!need_vex || vex.length != 128)
14655         abort ();
14656       if (vex.w)
14657         oappend ("DWORD PTR ");
14658       else
14659         oappend ("BYTE PTR ");
14660       break;
14661     case mask_mode:
14662       if (!need_vex)
14663         abort ();
14664       if (vex.w)
14665         oappend ("QWORD PTR ");
14666       else
14667         oappend ("WORD PTR ");
14668       break;
14669     case v_bnd_mode:
14670     default:
14671       break;
14672     }
14673 }
14674
14675 static void
14676 OP_E_register (int bytemode, int sizeflag)
14677 {
14678   int reg = modrm.rm;
14679   const char **names;
14680
14681   USED_REX (REX_B);
14682   if ((rex & REX_B))
14683     reg += 8;
14684
14685   if ((sizeflag & SUFFIX_ALWAYS)
14686       && (bytemode == b_swap_mode
14687           || bytemode == v_swap_mode
14688           || bytemode == dqw_swap_mode))
14689     swap_operand ();
14690
14691   switch (bytemode)
14692     {
14693     case b_mode:
14694     case b_swap_mode:
14695       USED_REX (0);
14696       if (rex)
14697         names = names8rex;
14698       else
14699         names = names8;
14700       break;
14701     case w_mode:
14702       names = names16;
14703       break;
14704     case d_mode:
14705     case dw_mode:
14706     case db_mode:
14707       names = names32;
14708       break;
14709     case q_mode:
14710       names = names64;
14711       break;
14712     case m_mode:
14713     case v_bnd_mode:
14714       names = address_mode == mode_64bit ? names64 : names32;
14715       break;
14716     case bnd_mode:
14717       names = names_bnd;
14718       break;
14719     case stack_v_mode:
14720       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14721         {
14722           names = names64;
14723           break;
14724         }
14725       bytemode = v_mode;
14726       /* FALLTHRU */
14727     case v_mode:
14728     case v_swap_mode:
14729     case dq_mode:
14730     case dqb_mode:
14731     case dqd_mode:
14732     case dqw_mode:
14733     case dqw_swap_mode:
14734       USED_REX (REX_W);
14735       if (rex & REX_W)
14736         names = names64;
14737       else
14738         {
14739           if ((sizeflag & DFLAG)
14740               || (bytemode != v_mode
14741                   && bytemode != v_swap_mode))
14742             names = names32;
14743           else
14744             names = names16;
14745           used_prefixes |= (prefixes & PREFIX_DATA);
14746         }
14747       break;
14748     case mask_bd_mode:
14749     case mask_mode:
14750       names = names_mask;
14751       break;
14752     case 0:
14753       return;
14754     default:
14755       oappend (INTERNAL_DISASSEMBLER_ERROR);
14756       return;
14757     }
14758   oappend (names[reg]);
14759 }
14760
14761 static void
14762 OP_E_memory (int bytemode, int sizeflag)
14763 {
14764   bfd_vma disp = 0;
14765   int add = (rex & REX_B) ? 8 : 0;
14766   int riprel = 0;
14767   int shift;
14768
14769   if (vex.evex)
14770     {
14771       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14772       if (vex.b
14773           && bytemode != x_mode
14774           && bytemode != xmmq_mode
14775           && bytemode != evex_half_bcst_xmmq_mode)
14776         {
14777           BadOp ();
14778           return;
14779         }
14780       switch (bytemode)
14781         {
14782         case dqw_mode:
14783         case dw_mode:
14784         case dqw_swap_mode:
14785           shift = 1;
14786           break;
14787         case dqb_mode:
14788         case db_mode:
14789           shift = 0;
14790           break;
14791         case vex_vsib_d_w_dq_mode:
14792         case vex_vsib_d_w_d_mode:
14793         case vex_vsib_q_w_dq_mode:
14794         case vex_vsib_q_w_d_mode:
14795         case evex_x_gscat_mode:
14796         case xmm_mdq_mode:
14797           shift = vex.w ? 3 : 2;
14798           break;
14799         case x_mode:
14800         case evex_half_bcst_xmmq_mode:
14801         case xmmq_mode:
14802           if (vex.b)
14803             {
14804               shift = vex.w ? 3 : 2;
14805               break;
14806             }
14807           /* Fall through if vex.b == 0.  */
14808         case xmmqd_mode:
14809         case xmmdw_mode:
14810         case ymmq_mode:
14811         case evex_x_nobcst_mode:
14812         case x_swap_mode:
14813           switch (vex.length)
14814             {
14815             case 128:
14816               shift = 4;
14817               break;
14818             case 256:
14819               shift = 5;
14820               break;
14821             case 512:
14822               shift = 6;
14823               break;
14824             default:
14825               abort ();
14826             }
14827           break;
14828         case ymm_mode:
14829           shift = 5;
14830           break;
14831         case xmm_mode:
14832           shift = 4;
14833           break;
14834         case xmm_mq_mode:
14835         case q_mode:
14836         case q_scalar_mode:
14837         case q_swap_mode:
14838         case q_scalar_swap_mode:
14839           shift = 3;
14840           break;
14841         case dqd_mode:
14842         case xmm_md_mode:
14843         case d_mode:
14844         case d_scalar_mode:
14845         case d_swap_mode:
14846         case d_scalar_swap_mode:
14847           shift = 2;
14848           break;
14849         case xmm_mw_mode:
14850           shift = 1;
14851           break;
14852         case xmm_mb_mode:
14853           shift = 0;
14854           break;
14855         default:
14856           abort ();
14857         }
14858       /* Make necessary corrections to shift for modes that need it.
14859          For these modes we currently have shift 4, 5 or 6 depending on
14860          vex.length (it corresponds to xmmword, ymmword or zmmword
14861          operand).  We might want to make it 3, 4 or 5 (e.g. for
14862          xmmq_mode).  In case of broadcast enabled the corrections
14863          aren't needed, as element size is always 32 or 64 bits.  */
14864       if (!vex.b
14865           && (bytemode == xmmq_mode
14866               || bytemode == evex_half_bcst_xmmq_mode))
14867         shift -= 1;
14868       else if (bytemode == xmmqd_mode)
14869         shift -= 2;
14870       else if (bytemode == xmmdw_mode)
14871         shift -= 3;
14872       else if (bytemode == ymmq_mode && vex.length == 128)
14873         shift -= 1;
14874     }
14875   else
14876     shift = 0;
14877
14878   USED_REX (REX_B);
14879   if (intel_syntax)
14880     intel_operand_size (bytemode, sizeflag);
14881   append_seg ();
14882
14883   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14884     {
14885       /* 32/64 bit address mode */
14886       int havedisp;
14887       int havesib;
14888       int havebase;
14889       int haveindex;
14890       int needindex;
14891       int base, rbase;
14892       int vindex = 0;
14893       int scale = 0;
14894       int addr32flag = !((sizeflag & AFLAG)
14895                          || bytemode == v_bnd_mode
14896                          || bytemode == bnd_mode);
14897       const char **indexes64 = names64;
14898       const char **indexes32 = names32;
14899
14900       havesib = 0;
14901       havebase = 1;
14902       haveindex = 0;
14903       base = modrm.rm;
14904
14905       if (base == 4)
14906         {
14907           havesib = 1;
14908           vindex = sib.index;
14909           USED_REX (REX_X);
14910           if (rex & REX_X)
14911             vindex += 8;
14912           switch (bytemode)
14913             {
14914             case vex_vsib_d_w_dq_mode:
14915             case vex_vsib_d_w_d_mode:
14916             case vex_vsib_q_w_dq_mode:
14917             case vex_vsib_q_w_d_mode:
14918               if (!need_vex)
14919                 abort ();
14920               if (vex.evex)
14921                 {
14922                   if (!vex.v)
14923                     vindex += 16;
14924                 }
14925
14926               haveindex = 1;
14927               switch (vex.length)
14928                 {
14929                 case 128:
14930                   indexes64 = indexes32 = names_xmm;
14931                   break;
14932                 case 256:
14933                   if (!vex.w
14934                       || bytemode == vex_vsib_q_w_dq_mode
14935                       || bytemode == vex_vsib_q_w_d_mode)
14936                     indexes64 = indexes32 = names_ymm;
14937                   else
14938                     indexes64 = indexes32 = names_xmm;
14939                   break;
14940                 case 512:
14941                   if (!vex.w
14942                       || bytemode == vex_vsib_q_w_dq_mode
14943                       || bytemode == vex_vsib_q_w_d_mode)
14944                     indexes64 = indexes32 = names_zmm;
14945                   else
14946                     indexes64 = indexes32 = names_ymm;
14947                   break;
14948                 default:
14949                   abort ();
14950                 }
14951               break;
14952             default:
14953               haveindex = vindex != 4;
14954               break;
14955             }
14956           scale = sib.scale;
14957           base = sib.base;
14958           codep++;
14959         }
14960       rbase = base + add;
14961
14962       switch (modrm.mod)
14963         {
14964         case 0:
14965           if (base == 5)
14966             {
14967               havebase = 0;
14968               if (address_mode == mode_64bit && !havesib)
14969                 riprel = 1;
14970               disp = get32s ();
14971             }
14972           break;
14973         case 1:
14974           FETCH_DATA (the_info, codep + 1);
14975           disp = *codep++;
14976           if ((disp & 0x80) != 0)
14977             disp -= 0x100;
14978           if (vex.evex && shift > 0)
14979             disp <<= shift;
14980           break;
14981         case 2:
14982           disp = get32s ();
14983           break;
14984         }
14985
14986       /* In 32bit mode, we need index register to tell [offset] from
14987          [eiz*1 + offset].  */
14988       needindex = (havesib
14989                    && !havebase
14990                    && !haveindex
14991                    && address_mode == mode_32bit);
14992       havedisp = (havebase
14993                   || needindex
14994                   || (havesib && (haveindex || scale != 0)));
14995
14996       if (!intel_syntax)
14997         if (modrm.mod != 0 || base == 5)
14998           {
14999             if (havedisp || riprel)
15000               print_displacement (scratchbuf, disp);
15001             else
15002               print_operand_value (scratchbuf, 1, disp);
15003             oappend (scratchbuf);
15004             if (riprel)
15005               {
15006                 set_op (disp, 1);
15007                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15008               }
15009           }
15010
15011       if ((havebase || haveindex || riprel)
15012           && (bytemode != v_bnd_mode)
15013           && (bytemode != bnd_mode))
15014         used_prefixes |= PREFIX_ADDR;
15015
15016       if (havedisp || (intel_syntax && riprel))
15017         {
15018           *obufp++ = open_char;
15019           if (intel_syntax && riprel)
15020             {
15021               set_op (disp, 1);
15022               oappend (sizeflag & AFLAG ? "rip" : "eip");
15023             }
15024           *obufp = '\0';
15025           if (havebase)
15026             oappend (address_mode == mode_64bit && !addr32flag
15027                      ? names64[rbase] : names32[rbase]);
15028           if (havesib)
15029             {
15030               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15031                  print index to tell base + index from base.  */
15032               if (scale != 0
15033                   || needindex
15034                   || haveindex
15035                   || (havebase && base != ESP_REG_NUM))
15036                 {
15037                   if (!intel_syntax || havebase)
15038                     {
15039                       *obufp++ = separator_char;
15040                       *obufp = '\0';
15041                     }
15042                   if (haveindex)
15043                     oappend (address_mode == mode_64bit && !addr32flag
15044                              ? indexes64[vindex] : indexes32[vindex]);
15045                   else
15046                     oappend (address_mode == mode_64bit && !addr32flag
15047                              ? index64 : index32);
15048
15049                   *obufp++ = scale_char;
15050                   *obufp = '\0';
15051                   sprintf (scratchbuf, "%d", 1 << scale);
15052                   oappend (scratchbuf);
15053                 }
15054             }
15055           if (intel_syntax
15056               && (disp || modrm.mod != 0 || base == 5))
15057             {
15058               if (!havedisp || (bfd_signed_vma) disp >= 0)
15059                 {
15060                   *obufp++ = '+';
15061                   *obufp = '\0';
15062                 }
15063               else if (modrm.mod != 1 && disp != -disp)
15064                 {
15065                   *obufp++ = '-';
15066                   *obufp = '\0';
15067                   disp = - (bfd_signed_vma) disp;
15068                 }
15069
15070               if (havedisp)
15071                 print_displacement (scratchbuf, disp);
15072               else
15073                 print_operand_value (scratchbuf, 1, disp);
15074               oappend (scratchbuf);
15075             }
15076
15077           *obufp++ = close_char;
15078           *obufp = '\0';
15079         }
15080       else if (intel_syntax)
15081         {
15082           if (modrm.mod != 0 || base == 5)
15083             {
15084               if (!active_seg_prefix)
15085                 {
15086                   oappend (names_seg[ds_reg - es_reg]);
15087                   oappend (":");
15088                 }
15089               print_operand_value (scratchbuf, 1, disp);
15090               oappend (scratchbuf);
15091             }
15092         }
15093     }
15094   else
15095     {
15096       /* 16 bit address mode */
15097       used_prefixes |= prefixes & PREFIX_ADDR;
15098       switch (modrm.mod)
15099         {
15100         case 0:
15101           if (modrm.rm == 6)
15102             {
15103               disp = get16 ();
15104               if ((disp & 0x8000) != 0)
15105                 disp -= 0x10000;
15106             }
15107           break;
15108         case 1:
15109           FETCH_DATA (the_info, codep + 1);
15110           disp = *codep++;
15111           if ((disp & 0x80) != 0)
15112             disp -= 0x100;
15113           break;
15114         case 2:
15115           disp = get16 ();
15116           if ((disp & 0x8000) != 0)
15117             disp -= 0x10000;
15118           break;
15119         }
15120
15121       if (!intel_syntax)
15122         if (modrm.mod != 0 || modrm.rm == 6)
15123           {
15124             print_displacement (scratchbuf, disp);
15125             oappend (scratchbuf);
15126           }
15127
15128       if (modrm.mod != 0 || modrm.rm != 6)
15129         {
15130           *obufp++ = open_char;
15131           *obufp = '\0';
15132           oappend (index16[modrm.rm]);
15133           if (intel_syntax
15134               && (disp || modrm.mod != 0 || modrm.rm == 6))
15135             {
15136               if ((bfd_signed_vma) disp >= 0)
15137                 {
15138                   *obufp++ = '+';
15139                   *obufp = '\0';
15140                 }
15141               else if (modrm.mod != 1)
15142                 {
15143                   *obufp++ = '-';
15144                   *obufp = '\0';
15145                   disp = - (bfd_signed_vma) disp;
15146                 }
15147
15148               print_displacement (scratchbuf, disp);
15149               oappend (scratchbuf);
15150             }
15151
15152           *obufp++ = close_char;
15153           *obufp = '\0';
15154         }
15155       else if (intel_syntax)
15156         {
15157           if (!active_seg_prefix)
15158             {
15159               oappend (names_seg[ds_reg - es_reg]);
15160               oappend (":");
15161             }
15162           print_operand_value (scratchbuf, 1, disp & 0xffff);
15163           oappend (scratchbuf);
15164         }
15165     }
15166   if (vex.evex && vex.b
15167       && (bytemode == x_mode
15168           || bytemode == xmmq_mode
15169           || bytemode == evex_half_bcst_xmmq_mode))
15170     {
15171       if (vex.w
15172           || bytemode == xmmq_mode
15173           || bytemode == evex_half_bcst_xmmq_mode)
15174         {
15175           switch (vex.length)
15176             {
15177             case 128:
15178               oappend ("{1to2}");
15179               break;
15180             case 256:
15181               oappend ("{1to4}");
15182               break;
15183             case 512:
15184               oappend ("{1to8}");
15185               break;
15186             default:
15187               abort ();
15188             }
15189         }
15190       else
15191         {
15192           switch (vex.length)
15193             {
15194             case 128:
15195               oappend ("{1to4}");
15196               break;
15197             case 256:
15198               oappend ("{1to8}");
15199               break;
15200             case 512:
15201               oappend ("{1to16}");
15202               break;
15203             default:
15204               abort ();
15205             }
15206         }
15207     }
15208 }
15209
15210 static void
15211 OP_E (int bytemode, int sizeflag)
15212 {
15213   /* Skip mod/rm byte.  */
15214   MODRM_CHECK;
15215   codep++;
15216
15217   if (modrm.mod == 3)
15218     OP_E_register (bytemode, sizeflag);
15219   else
15220     OP_E_memory (bytemode, sizeflag);
15221 }
15222
15223 static void
15224 OP_G (int bytemode, int sizeflag)
15225 {
15226   int add = 0;
15227   USED_REX (REX_R);
15228   if (rex & REX_R)
15229     add += 8;
15230   switch (bytemode)
15231     {
15232     case b_mode:
15233       USED_REX (0);
15234       if (rex)
15235         oappend (names8rex[modrm.reg + add]);
15236       else
15237         oappend (names8[modrm.reg + add]);
15238       break;
15239     case w_mode:
15240       oappend (names16[modrm.reg + add]);
15241       break;
15242     case d_mode:
15243     case db_mode:
15244     case dw_mode:
15245       oappend (names32[modrm.reg + add]);
15246       break;
15247     case q_mode:
15248       oappend (names64[modrm.reg + add]);
15249       break;
15250     case bnd_mode:
15251       oappend (names_bnd[modrm.reg]);
15252       break;
15253     case v_mode:
15254     case dq_mode:
15255     case dqb_mode:
15256     case dqd_mode:
15257     case dqw_mode:
15258     case dqw_swap_mode:
15259       USED_REX (REX_W);
15260       if (rex & REX_W)
15261         oappend (names64[modrm.reg + add]);
15262       else
15263         {
15264           if ((sizeflag & DFLAG) || bytemode != v_mode)
15265             oappend (names32[modrm.reg + add]);
15266           else
15267             oappend (names16[modrm.reg + add]);
15268           used_prefixes |= (prefixes & PREFIX_DATA);
15269         }
15270       break;
15271     case m_mode:
15272       if (address_mode == mode_64bit)
15273         oappend (names64[modrm.reg + add]);
15274       else
15275         oappend (names32[modrm.reg + add]);
15276       break;
15277     case mask_bd_mode:
15278     case mask_mode:
15279       oappend (names_mask[modrm.reg + add]);
15280       break;
15281     default:
15282       oappend (INTERNAL_DISASSEMBLER_ERROR);
15283       break;
15284     }
15285 }
15286
15287 static bfd_vma
15288 get64 (void)
15289 {
15290   bfd_vma x;
15291 #ifdef BFD64
15292   unsigned int a;
15293   unsigned int b;
15294
15295   FETCH_DATA (the_info, codep + 8);
15296   a = *codep++ & 0xff;
15297   a |= (*codep++ & 0xff) << 8;
15298   a |= (*codep++ & 0xff) << 16;
15299   a |= (*codep++ & 0xff) << 24;
15300   b = *codep++ & 0xff;
15301   b |= (*codep++ & 0xff) << 8;
15302   b |= (*codep++ & 0xff) << 16;
15303   b |= (*codep++ & 0xff) << 24;
15304   x = a + ((bfd_vma) b << 32);
15305 #else
15306   abort ();
15307   x = 0;
15308 #endif
15309   return x;
15310 }
15311
15312 static bfd_signed_vma
15313 get32 (void)
15314 {
15315   bfd_signed_vma x = 0;
15316
15317   FETCH_DATA (the_info, codep + 4);
15318   x = *codep++ & (bfd_signed_vma) 0xff;
15319   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15320   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15321   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15322   return x;
15323 }
15324
15325 static bfd_signed_vma
15326 get32s (void)
15327 {
15328   bfd_signed_vma x = 0;
15329
15330   FETCH_DATA (the_info, codep + 4);
15331   x = *codep++ & (bfd_signed_vma) 0xff;
15332   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15333   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15334   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15335
15336   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15337
15338   return x;
15339 }
15340
15341 static int
15342 get16 (void)
15343 {
15344   int x = 0;
15345
15346   FETCH_DATA (the_info, codep + 2);
15347   x = *codep++ & 0xff;
15348   x |= (*codep++ & 0xff) << 8;
15349   return x;
15350 }
15351
15352 static void
15353 set_op (bfd_vma op, int riprel)
15354 {
15355   op_index[op_ad] = op_ad;
15356   if (address_mode == mode_64bit)
15357     {
15358       op_address[op_ad] = op;
15359       op_riprel[op_ad] = riprel;
15360     }
15361   else
15362     {
15363       /* Mask to get a 32-bit address.  */
15364       op_address[op_ad] = op & 0xffffffff;
15365       op_riprel[op_ad] = riprel & 0xffffffff;
15366     }
15367 }
15368
15369 static void
15370 OP_REG (int code, int sizeflag)
15371 {
15372   const char *s;
15373   int add;
15374
15375   switch (code)
15376     {
15377     case es_reg: case ss_reg: case cs_reg:
15378     case ds_reg: case fs_reg: case gs_reg:
15379       oappend (names_seg[code - es_reg]);
15380       return;
15381     }
15382
15383   USED_REX (REX_B);
15384   if (rex & REX_B)
15385     add = 8;
15386   else
15387     add = 0;
15388
15389   switch (code)
15390     {
15391     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15392     case sp_reg: case bp_reg: case si_reg: case di_reg:
15393       s = names16[code - ax_reg + add];
15394       break;
15395     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15396     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15397       USED_REX (0);
15398       if (rex)
15399         s = names8rex[code - al_reg + add];
15400       else
15401         s = names8[code - al_reg];
15402       break;
15403     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15404     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15405       if (address_mode == mode_64bit
15406           && ((sizeflag & DFLAG) || (rex & REX_W)))
15407         {
15408           s = names64[code - rAX_reg + add];
15409           break;
15410         }
15411       code += eAX_reg - rAX_reg;
15412       /* Fall through.  */
15413     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15414     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15415       USED_REX (REX_W);
15416       if (rex & REX_W)
15417         s = names64[code - eAX_reg + add];
15418       else
15419         {
15420           if (sizeflag & DFLAG)
15421             s = names32[code - eAX_reg + add];
15422           else
15423             s = names16[code - eAX_reg + add];
15424           used_prefixes |= (prefixes & PREFIX_DATA);
15425         }
15426       break;
15427     default:
15428       s = INTERNAL_DISASSEMBLER_ERROR;
15429       break;
15430     }
15431   oappend (s);
15432 }
15433
15434 static void
15435 OP_IMREG (int code, int sizeflag)
15436 {
15437   const char *s;
15438
15439   switch (code)
15440     {
15441     case indir_dx_reg:
15442       if (intel_syntax)
15443         s = "dx";
15444       else
15445         s = "(%dx)";
15446       break;
15447     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15448     case sp_reg: case bp_reg: case si_reg: case di_reg:
15449       s = names16[code - ax_reg];
15450       break;
15451     case es_reg: case ss_reg: case cs_reg:
15452     case ds_reg: case fs_reg: case gs_reg:
15453       s = names_seg[code - es_reg];
15454       break;
15455     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15456     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15457       USED_REX (0);
15458       if (rex)
15459         s = names8rex[code - al_reg];
15460       else
15461         s = names8[code - al_reg];
15462       break;
15463     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15464     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15465       USED_REX (REX_W);
15466       if (rex & REX_W)
15467         s = names64[code - eAX_reg];
15468       else
15469         {
15470           if (sizeflag & DFLAG)
15471             s = names32[code - eAX_reg];
15472           else
15473             s = names16[code - eAX_reg];
15474           used_prefixes |= (prefixes & PREFIX_DATA);
15475         }
15476       break;
15477     case z_mode_ax_reg:
15478       if ((rex & REX_W) || (sizeflag & DFLAG))
15479         s = *names32;
15480       else
15481         s = *names16;
15482       if (!(rex & REX_W))
15483         used_prefixes |= (prefixes & PREFIX_DATA);
15484       break;
15485     default:
15486       s = INTERNAL_DISASSEMBLER_ERROR;
15487       break;
15488     }
15489   oappend (s);
15490 }
15491
15492 static void
15493 OP_I (int bytemode, int sizeflag)
15494 {
15495   bfd_signed_vma op;
15496   bfd_signed_vma mask = -1;
15497
15498   switch (bytemode)
15499     {
15500     case b_mode:
15501       FETCH_DATA (the_info, codep + 1);
15502       op = *codep++;
15503       mask = 0xff;
15504       break;
15505     case q_mode:
15506       if (address_mode == mode_64bit)
15507         {
15508           op = get32s ();
15509           break;
15510         }
15511       /* Fall through.  */
15512     case v_mode:
15513       USED_REX (REX_W);
15514       if (rex & REX_W)
15515         op = get32s ();
15516       else
15517         {
15518           if (sizeflag & DFLAG)
15519             {
15520               op = get32 ();
15521               mask = 0xffffffff;
15522             }
15523           else
15524             {
15525               op = get16 ();
15526               mask = 0xfffff;
15527             }
15528           used_prefixes |= (prefixes & PREFIX_DATA);
15529         }
15530       break;
15531     case w_mode:
15532       mask = 0xfffff;
15533       op = get16 ();
15534       break;
15535     case const_1_mode:
15536       if (intel_syntax)
15537         oappend ("1");
15538       return;
15539     default:
15540       oappend (INTERNAL_DISASSEMBLER_ERROR);
15541       return;
15542     }
15543
15544   op &= mask;
15545   scratchbuf[0] = '$';
15546   print_operand_value (scratchbuf + 1, 1, op);
15547   oappend_maybe_intel (scratchbuf);
15548   scratchbuf[0] = '\0';
15549 }
15550
15551 static void
15552 OP_I64 (int bytemode, int sizeflag)
15553 {
15554   bfd_signed_vma op;
15555   bfd_signed_vma mask = -1;
15556
15557   if (address_mode != mode_64bit)
15558     {
15559       OP_I (bytemode, sizeflag);
15560       return;
15561     }
15562
15563   switch (bytemode)
15564     {
15565     case b_mode:
15566       FETCH_DATA (the_info, codep + 1);
15567       op = *codep++;
15568       mask = 0xff;
15569       break;
15570     case v_mode:
15571       USED_REX (REX_W);
15572       if (rex & REX_W)
15573         op = get64 ();
15574       else
15575         {
15576           if (sizeflag & DFLAG)
15577             {
15578               op = get32 ();
15579               mask = 0xffffffff;
15580             }
15581           else
15582             {
15583               op = get16 ();
15584               mask = 0xfffff;
15585             }
15586           used_prefixes |= (prefixes & PREFIX_DATA);
15587         }
15588       break;
15589     case w_mode:
15590       mask = 0xfffff;
15591       op = get16 ();
15592       break;
15593     default:
15594       oappend (INTERNAL_DISASSEMBLER_ERROR);
15595       return;
15596     }
15597
15598   op &= mask;
15599   scratchbuf[0] = '$';
15600   print_operand_value (scratchbuf + 1, 1, op);
15601   oappend_maybe_intel (scratchbuf);
15602   scratchbuf[0] = '\0';
15603 }
15604
15605 static void
15606 OP_sI (int bytemode, int sizeflag)
15607 {
15608   bfd_signed_vma op;
15609
15610   switch (bytemode)
15611     {
15612     case b_mode:
15613     case b_T_mode:
15614       FETCH_DATA (the_info, codep + 1);
15615       op = *codep++;
15616       if ((op & 0x80) != 0)
15617         op -= 0x100;
15618       if (bytemode == b_T_mode)
15619         {
15620           if (address_mode != mode_64bit
15621               || !((sizeflag & DFLAG) || (rex & REX_W)))
15622             {
15623               /* The operand-size prefix is overridden by a REX prefix.  */
15624               if ((sizeflag & DFLAG) || (rex & REX_W))
15625                 op &= 0xffffffff;
15626               else
15627                 op &= 0xffff;
15628           }
15629         }
15630       else
15631         {
15632           if (!(rex & REX_W))
15633             {
15634               if (sizeflag & DFLAG)
15635                 op &= 0xffffffff;
15636               else
15637                 op &= 0xffff;
15638             }
15639         }
15640       break;
15641     case v_mode:
15642       /* The operand-size prefix is overridden by a REX prefix.  */
15643       if ((sizeflag & DFLAG) || (rex & REX_W))
15644         op = get32s ();
15645       else
15646         op = get16 ();
15647       break;
15648     default:
15649       oappend (INTERNAL_DISASSEMBLER_ERROR);
15650       return;
15651     }
15652
15653   scratchbuf[0] = '$';
15654   print_operand_value (scratchbuf + 1, 1, op);
15655   oappend_maybe_intel (scratchbuf);
15656 }
15657
15658 static void
15659 OP_J (int bytemode, int sizeflag)
15660 {
15661   bfd_vma disp;
15662   bfd_vma mask = -1;
15663   bfd_vma segment = 0;
15664
15665   switch (bytemode)
15666     {
15667     case b_mode:
15668       FETCH_DATA (the_info, codep + 1);
15669       disp = *codep++;
15670       if ((disp & 0x80) != 0)
15671         disp -= 0x100;
15672       break;
15673     case v_mode:
15674       USED_REX (REX_W);
15675       if ((sizeflag & DFLAG) || (rex & REX_W))
15676         disp = get32s ();
15677       else
15678         {
15679           disp = get16 ();
15680           if ((disp & 0x8000) != 0)
15681             disp -= 0x10000;
15682           /* In 16bit mode, address is wrapped around at 64k within
15683              the same segment.  Otherwise, a data16 prefix on a jump
15684              instruction means that the pc is masked to 16 bits after
15685              the displacement is added!  */
15686           mask = 0xffff;
15687           if ((prefixes & PREFIX_DATA) == 0)
15688             segment = ((start_pc + codep - start_codep)
15689                        & ~((bfd_vma) 0xffff));
15690         }
15691       if (!(rex & REX_W))
15692         used_prefixes |= (prefixes & PREFIX_DATA);
15693       break;
15694     default:
15695       oappend (INTERNAL_DISASSEMBLER_ERROR);
15696       return;
15697     }
15698   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15699   set_op (disp, 0);
15700   print_operand_value (scratchbuf, 1, disp);
15701   oappend (scratchbuf);
15702 }
15703
15704 static void
15705 OP_SEG (int bytemode, int sizeflag)
15706 {
15707   if (bytemode == w_mode)
15708     oappend (names_seg[modrm.reg]);
15709   else
15710     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15711 }
15712
15713 static void
15714 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15715 {
15716   int seg, offset;
15717
15718   if (sizeflag & DFLAG)
15719     {
15720       offset = get32 ();
15721       seg = get16 ();
15722     }
15723   else
15724     {
15725       offset = get16 ();
15726       seg = get16 ();
15727     }
15728   used_prefixes |= (prefixes & PREFIX_DATA);
15729   if (intel_syntax)
15730     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15731   else
15732     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15733   oappend (scratchbuf);
15734 }
15735
15736 static void
15737 OP_OFF (int bytemode, int sizeflag)
15738 {
15739   bfd_vma off;
15740
15741   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15742     intel_operand_size (bytemode, sizeflag);
15743   append_seg ();
15744
15745   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15746     off = get32 ();
15747   else
15748     off = get16 ();
15749
15750   if (intel_syntax)
15751     {
15752       if (!active_seg_prefix)
15753         {
15754           oappend (names_seg[ds_reg - es_reg]);
15755           oappend (":");
15756         }
15757     }
15758   print_operand_value (scratchbuf, 1, off);
15759   oappend (scratchbuf);
15760 }
15761
15762 static void
15763 OP_OFF64 (int bytemode, int sizeflag)
15764 {
15765   bfd_vma off;
15766
15767   if (address_mode != mode_64bit
15768       || (prefixes & PREFIX_ADDR))
15769     {
15770       OP_OFF (bytemode, sizeflag);
15771       return;
15772     }
15773
15774   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15775     intel_operand_size (bytemode, sizeflag);
15776   append_seg ();
15777
15778   off = get64 ();
15779
15780   if (intel_syntax)
15781     {
15782       if (!active_seg_prefix)
15783         {
15784           oappend (names_seg[ds_reg - es_reg]);
15785           oappend (":");
15786         }
15787     }
15788   print_operand_value (scratchbuf, 1, off);
15789   oappend (scratchbuf);
15790 }
15791
15792 static void
15793 ptr_reg (int code, int sizeflag)
15794 {
15795   const char *s;
15796
15797   *obufp++ = open_char;
15798   used_prefixes |= (prefixes & PREFIX_ADDR);
15799   if (address_mode == mode_64bit)
15800     {
15801       if (!(sizeflag & AFLAG))
15802         s = names32[code - eAX_reg];
15803       else
15804         s = names64[code - eAX_reg];
15805     }
15806   else if (sizeflag & AFLAG)
15807     s = names32[code - eAX_reg];
15808   else
15809     s = names16[code - eAX_reg];
15810   oappend (s);
15811   *obufp++ = close_char;
15812   *obufp = 0;
15813 }
15814
15815 static void
15816 OP_ESreg (int code, int sizeflag)
15817 {
15818   if (intel_syntax)
15819     {
15820       switch (codep[-1])
15821         {
15822         case 0x6d:      /* insw/insl */
15823           intel_operand_size (z_mode, sizeflag);
15824           break;
15825         case 0xa5:      /* movsw/movsl/movsq */
15826         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15827         case 0xab:      /* stosw/stosl */
15828         case 0xaf:      /* scasw/scasl */
15829           intel_operand_size (v_mode, sizeflag);
15830           break;
15831         default:
15832           intel_operand_size (b_mode, sizeflag);
15833         }
15834     }
15835   oappend_maybe_intel ("%es:");
15836   ptr_reg (code, sizeflag);
15837 }
15838
15839 static void
15840 OP_DSreg (int code, int sizeflag)
15841 {
15842   if (intel_syntax)
15843     {
15844       switch (codep[-1])
15845         {
15846         case 0x6f:      /* outsw/outsl */
15847           intel_operand_size (z_mode, sizeflag);
15848           break;
15849         case 0xa5:      /* movsw/movsl/movsq */
15850         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15851         case 0xad:      /* lodsw/lodsl/lodsq */
15852           intel_operand_size (v_mode, sizeflag);
15853           break;
15854         default:
15855           intel_operand_size (b_mode, sizeflag);
15856         }
15857     }
15858   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15859      default segment register DS is printed.  */
15860   if (!active_seg_prefix)
15861     active_seg_prefix = PREFIX_DS;
15862   append_seg ();
15863   ptr_reg (code, sizeflag);
15864 }
15865
15866 static void
15867 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15868 {
15869   int add;
15870   if (rex & REX_R)
15871     {
15872       USED_REX (REX_R);
15873       add = 8;
15874     }
15875   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15876     {
15877       all_prefixes[last_lock_prefix] = 0;
15878       used_prefixes |= PREFIX_LOCK;
15879       add = 8;
15880     }
15881   else
15882     add = 0;
15883   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15884   oappend_maybe_intel (scratchbuf);
15885 }
15886
15887 static void
15888 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15889 {
15890   int add;
15891   USED_REX (REX_R);
15892   if (rex & REX_R)
15893     add = 8;
15894   else
15895     add = 0;
15896   if (intel_syntax)
15897     sprintf (scratchbuf, "db%d", modrm.reg + add);
15898   else
15899     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15900   oappend (scratchbuf);
15901 }
15902
15903 static void
15904 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15905 {
15906   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15907   oappend_maybe_intel (scratchbuf);
15908 }
15909
15910 static void
15911 OP_R (int bytemode, int sizeflag)
15912 {
15913   /* Skip mod/rm byte.  */
15914   MODRM_CHECK;
15915   codep++;
15916   OP_E_register (bytemode, sizeflag);
15917 }
15918
15919 static void
15920 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15921 {
15922   int reg = modrm.reg;
15923   const char **names;
15924
15925   used_prefixes |= (prefixes & PREFIX_DATA);
15926   if (prefixes & PREFIX_DATA)
15927     {
15928       names = names_xmm;
15929       USED_REX (REX_R);
15930       if (rex & REX_R)
15931         reg += 8;
15932     }
15933   else
15934     names = names_mm;
15935   oappend (names[reg]);
15936 }
15937
15938 static void
15939 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15940 {
15941   int reg = modrm.reg;
15942   const char **names;
15943
15944   USED_REX (REX_R);
15945   if (rex & REX_R)
15946     reg += 8;
15947   if (vex.evex)
15948     {
15949       if (!vex.r)
15950         reg += 16;
15951     }
15952
15953   if (need_vex
15954       && bytemode != xmm_mode
15955       && bytemode != xmmq_mode
15956       && bytemode != evex_half_bcst_xmmq_mode
15957       && bytemode != ymm_mode
15958       && bytemode != scalar_mode)
15959     {
15960       switch (vex.length)
15961         {
15962         case 128:
15963           names = names_xmm;
15964           break;
15965         case 256:
15966           if (vex.w
15967               || (bytemode != vex_vsib_q_w_dq_mode
15968                   && bytemode != vex_vsib_q_w_d_mode))
15969             names = names_ymm;
15970           else
15971             names = names_xmm;
15972           break;
15973         case 512:
15974           names = names_zmm;
15975           break;
15976         default:
15977           abort ();
15978         }
15979     }
15980   else if (bytemode == xmmq_mode
15981            || bytemode == evex_half_bcst_xmmq_mode)
15982     {
15983       switch (vex.length)
15984         {
15985         case 128:
15986         case 256:
15987           names = names_xmm;
15988           break;
15989         case 512:
15990           names = names_ymm;
15991           break;
15992         default:
15993           abort ();
15994         }
15995     }
15996   else if (bytemode == ymm_mode)
15997     names = names_ymm;
15998   else
15999     names = names_xmm;
16000   oappend (names[reg]);
16001 }
16002
16003 static void
16004 OP_EM (int bytemode, int sizeflag)
16005 {
16006   int reg;
16007   const char **names;
16008
16009   if (modrm.mod != 3)
16010     {
16011       if (intel_syntax
16012           && (bytemode == v_mode || bytemode == v_swap_mode))
16013         {
16014           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16015           used_prefixes |= (prefixes & PREFIX_DATA);
16016         }
16017       OP_E (bytemode, sizeflag);
16018       return;
16019     }
16020
16021   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16022     swap_operand ();
16023
16024   /* Skip mod/rm byte.  */
16025   MODRM_CHECK;
16026   codep++;
16027   used_prefixes |= (prefixes & PREFIX_DATA);
16028   reg = modrm.rm;
16029   if (prefixes & PREFIX_DATA)
16030     {
16031       names = names_xmm;
16032       USED_REX (REX_B);
16033       if (rex & REX_B)
16034         reg += 8;
16035     }
16036   else
16037     names = names_mm;
16038   oappend (names[reg]);
16039 }
16040
16041 /* cvt* are the only instructions in sse2 which have
16042    both SSE and MMX operands and also have 0x66 prefix
16043    in their opcode. 0x66 was originally used to differentiate
16044    between SSE and MMX instruction(operands). So we have to handle the
16045    cvt* separately using OP_EMC and OP_MXC */
16046 static void
16047 OP_EMC (int bytemode, int sizeflag)
16048 {
16049   if (modrm.mod != 3)
16050     {
16051       if (intel_syntax && bytemode == v_mode)
16052         {
16053           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16054           used_prefixes |= (prefixes & PREFIX_DATA);
16055         }
16056       OP_E (bytemode, sizeflag);
16057       return;
16058     }
16059
16060   /* Skip mod/rm byte.  */
16061   MODRM_CHECK;
16062   codep++;
16063   used_prefixes |= (prefixes & PREFIX_DATA);
16064   oappend (names_mm[modrm.rm]);
16065 }
16066
16067 static void
16068 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16069 {
16070   used_prefixes |= (prefixes & PREFIX_DATA);
16071   oappend (names_mm[modrm.reg]);
16072 }
16073
16074 static void
16075 OP_EX (int bytemode, int sizeflag)
16076 {
16077   int reg;
16078   const char **names;
16079
16080   /* Skip mod/rm byte.  */
16081   MODRM_CHECK;
16082   codep++;
16083
16084   if (modrm.mod != 3)
16085     {
16086       OP_E_memory (bytemode, sizeflag);
16087       return;
16088     }
16089
16090   reg = modrm.rm;
16091   USED_REX (REX_B);
16092   if (rex & REX_B)
16093     reg += 8;
16094   if (vex.evex)
16095     {
16096       USED_REX (REX_X);
16097       if ((rex & REX_X))
16098         reg += 16;
16099     }
16100
16101   if ((sizeflag & SUFFIX_ALWAYS)
16102       && (bytemode == x_swap_mode
16103           || bytemode == d_swap_mode
16104           || bytemode == dqw_swap_mode
16105           || bytemode == d_scalar_swap_mode
16106           || bytemode == q_swap_mode
16107           || bytemode == q_scalar_swap_mode))
16108     swap_operand ();
16109
16110   if (need_vex
16111       && bytemode != xmm_mode
16112       && bytemode != xmmdw_mode
16113       && bytemode != xmmqd_mode
16114       && bytemode != xmm_mb_mode
16115       && bytemode != xmm_mw_mode
16116       && bytemode != xmm_md_mode
16117       && bytemode != xmm_mq_mode
16118       && bytemode != xmm_mdq_mode
16119       && bytemode != xmmq_mode
16120       && bytemode != evex_half_bcst_xmmq_mode
16121       && bytemode != ymm_mode
16122       && bytemode != d_scalar_mode
16123       && bytemode != d_scalar_swap_mode
16124       && bytemode != q_scalar_mode
16125       && bytemode != q_scalar_swap_mode
16126       && bytemode != vex_scalar_w_dq_mode)
16127     {
16128       switch (vex.length)
16129         {
16130         case 128:
16131           names = names_xmm;
16132           break;
16133         case 256:
16134           names = names_ymm;
16135           break;
16136         case 512:
16137           names = names_zmm;
16138           break;
16139         default:
16140           abort ();
16141         }
16142     }
16143   else if (bytemode == xmmq_mode
16144            || bytemode == evex_half_bcst_xmmq_mode)
16145     {
16146       switch (vex.length)
16147         {
16148         case 128:
16149         case 256:
16150           names = names_xmm;
16151           break;
16152         case 512:
16153           names = names_ymm;
16154           break;
16155         default:
16156           abort ();
16157         }
16158     }
16159   else if (bytemode == ymm_mode)
16160     names = names_ymm;
16161   else
16162     names = names_xmm;
16163   oappend (names[reg]);
16164 }
16165
16166 static void
16167 OP_MS (int bytemode, int sizeflag)
16168 {
16169   if (modrm.mod == 3)
16170     OP_EM (bytemode, sizeflag);
16171   else
16172     BadOp ();
16173 }
16174
16175 static void
16176 OP_XS (int bytemode, int sizeflag)
16177 {
16178   if (modrm.mod == 3)
16179     OP_EX (bytemode, sizeflag);
16180   else
16181     BadOp ();
16182 }
16183
16184 static void
16185 OP_M (int bytemode, int sizeflag)
16186 {
16187   if (modrm.mod == 3)
16188     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16189     BadOp ();
16190   else
16191     OP_E (bytemode, sizeflag);
16192 }
16193
16194 static void
16195 OP_0f07 (int bytemode, int sizeflag)
16196 {
16197   if (modrm.mod != 3 || modrm.rm != 0)
16198     BadOp ();
16199   else
16200     OP_E (bytemode, sizeflag);
16201 }
16202
16203 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16204    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16205
16206 static void
16207 NOP_Fixup1 (int bytemode, int sizeflag)
16208 {
16209   if ((prefixes & PREFIX_DATA) != 0
16210       || (rex != 0
16211           && rex != 0x48
16212           && address_mode == mode_64bit))
16213     OP_REG (bytemode, sizeflag);
16214   else
16215     strcpy (obuf, "nop");
16216 }
16217
16218 static void
16219 NOP_Fixup2 (int bytemode, int sizeflag)
16220 {
16221   if ((prefixes & PREFIX_DATA) != 0
16222       || (rex != 0
16223           && rex != 0x48
16224           && address_mode == mode_64bit))
16225     OP_IMREG (bytemode, sizeflag);
16226 }
16227
16228 static const char *const Suffix3DNow[] = {
16229 /* 00 */        NULL,           NULL,           NULL,           NULL,
16230 /* 04 */        NULL,           NULL,           NULL,           NULL,
16231 /* 08 */        NULL,           NULL,           NULL,           NULL,
16232 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16233 /* 10 */        NULL,           NULL,           NULL,           NULL,
16234 /* 14 */        NULL,           NULL,           NULL,           NULL,
16235 /* 18 */        NULL,           NULL,           NULL,           NULL,
16236 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16237 /* 20 */        NULL,           NULL,           NULL,           NULL,
16238 /* 24 */        NULL,           NULL,           NULL,           NULL,
16239 /* 28 */        NULL,           NULL,           NULL,           NULL,
16240 /* 2C */        NULL,           NULL,           NULL,           NULL,
16241 /* 30 */        NULL,           NULL,           NULL,           NULL,
16242 /* 34 */        NULL,           NULL,           NULL,           NULL,
16243 /* 38 */        NULL,           NULL,           NULL,           NULL,
16244 /* 3C */        NULL,           NULL,           NULL,           NULL,
16245 /* 40 */        NULL,           NULL,           NULL,           NULL,
16246 /* 44 */        NULL,           NULL,           NULL,           NULL,
16247 /* 48 */        NULL,           NULL,           NULL,           NULL,
16248 /* 4C */        NULL,           NULL,           NULL,           NULL,
16249 /* 50 */        NULL,           NULL,           NULL,           NULL,
16250 /* 54 */        NULL,           NULL,           NULL,           NULL,
16251 /* 58 */        NULL,           NULL,           NULL,           NULL,
16252 /* 5C */        NULL,           NULL,           NULL,           NULL,
16253 /* 60 */        NULL,           NULL,           NULL,           NULL,
16254 /* 64 */        NULL,           NULL,           NULL,           NULL,
16255 /* 68 */        NULL,           NULL,           NULL,           NULL,
16256 /* 6C */        NULL,           NULL,           NULL,           NULL,
16257 /* 70 */        NULL,           NULL,           NULL,           NULL,
16258 /* 74 */        NULL,           NULL,           NULL,           NULL,
16259 /* 78 */        NULL,           NULL,           NULL,           NULL,
16260 /* 7C */        NULL,           NULL,           NULL,           NULL,
16261 /* 80 */        NULL,           NULL,           NULL,           NULL,
16262 /* 84 */        NULL,           NULL,           NULL,           NULL,
16263 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16264 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16265 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16266 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16267 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16268 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16269 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16270 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16271 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16272 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16273 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16274 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16275 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16276 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16277 /* C0 */        NULL,           NULL,           NULL,           NULL,
16278 /* C4 */        NULL,           NULL,           NULL,           NULL,
16279 /* C8 */        NULL,           NULL,           NULL,           NULL,
16280 /* CC */        NULL,           NULL,           NULL,           NULL,
16281 /* D0 */        NULL,           NULL,           NULL,           NULL,
16282 /* D4 */        NULL,           NULL,           NULL,           NULL,
16283 /* D8 */        NULL,           NULL,           NULL,           NULL,
16284 /* DC */        NULL,           NULL,           NULL,           NULL,
16285 /* E0 */        NULL,           NULL,           NULL,           NULL,
16286 /* E4 */        NULL,           NULL,           NULL,           NULL,
16287 /* E8 */        NULL,           NULL,           NULL,           NULL,
16288 /* EC */        NULL,           NULL,           NULL,           NULL,
16289 /* F0 */        NULL,           NULL,           NULL,           NULL,
16290 /* F4 */        NULL,           NULL,           NULL,           NULL,
16291 /* F8 */        NULL,           NULL,           NULL,           NULL,
16292 /* FC */        NULL,           NULL,           NULL,           NULL,
16293 };
16294
16295 static void
16296 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16297 {
16298   const char *mnemonic;
16299
16300   FETCH_DATA (the_info, codep + 1);
16301   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16302      place where an 8-bit immediate would normally go.  ie. the last
16303      byte of the instruction.  */
16304   obufp = mnemonicendp;
16305   mnemonic = Suffix3DNow[*codep++ & 0xff];
16306   if (mnemonic)
16307     oappend (mnemonic);
16308   else
16309     {
16310       /* Since a variable sized modrm/sib chunk is between the start
16311          of the opcode (0x0f0f) and the opcode suffix, we need to do
16312          all the modrm processing first, and don't know until now that
16313          we have a bad opcode.  This necessitates some cleaning up.  */
16314       op_out[0][0] = '\0';
16315       op_out[1][0] = '\0';
16316       BadOp ();
16317     }
16318   mnemonicendp = obufp;
16319 }
16320
16321 static struct op simd_cmp_op[] =
16322 {
16323   { STRING_COMMA_LEN ("eq") },
16324   { STRING_COMMA_LEN ("lt") },
16325   { STRING_COMMA_LEN ("le") },
16326   { STRING_COMMA_LEN ("unord") },
16327   { STRING_COMMA_LEN ("neq") },
16328   { STRING_COMMA_LEN ("nlt") },
16329   { STRING_COMMA_LEN ("nle") },
16330   { STRING_COMMA_LEN ("ord") }
16331 };
16332
16333 static void
16334 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16335 {
16336   unsigned int cmp_type;
16337
16338   FETCH_DATA (the_info, codep + 1);
16339   cmp_type = *codep++ & 0xff;
16340   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16341     {
16342       char suffix [3];
16343       char *p = mnemonicendp - 2;
16344       suffix[0] = p[0];
16345       suffix[1] = p[1];
16346       suffix[2] = '\0';
16347       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16348       mnemonicendp += simd_cmp_op[cmp_type].len;
16349     }
16350   else
16351     {
16352       /* We have a reserved extension byte.  Output it directly.  */
16353       scratchbuf[0] = '$';
16354       print_operand_value (scratchbuf + 1, 1, cmp_type);
16355       oappend_maybe_intel (scratchbuf);
16356       scratchbuf[0] = '\0';
16357     }
16358 }
16359
16360 static void
16361 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16362           int sizeflag ATTRIBUTE_UNUSED)
16363 {
16364   /* mwait %eax,%ecx  */
16365   if (!intel_syntax)
16366     {
16367       const char **names = (address_mode == mode_64bit
16368                             ? names64 : names32);
16369       strcpy (op_out[0], names[0]);
16370       strcpy (op_out[1], names[1]);
16371       two_source_ops = 1;
16372     }
16373   /* Skip mod/rm byte.  */
16374   MODRM_CHECK;
16375   codep++;
16376 }
16377
16378 static void
16379 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16380             int sizeflag ATTRIBUTE_UNUSED)
16381 {
16382   /* monitor %eax,%ecx,%edx"  */
16383   if (!intel_syntax)
16384     {
16385       const char **op1_names;
16386       const char **names = (address_mode == mode_64bit
16387                             ? names64 : names32);
16388
16389       if (!(prefixes & PREFIX_ADDR))
16390         op1_names = (address_mode == mode_16bit
16391                      ? names16 : names);
16392       else
16393         {
16394           /* Remove "addr16/addr32".  */
16395           all_prefixes[last_addr_prefix] = 0;
16396           op1_names = (address_mode != mode_32bit
16397                        ? names32 : names16);
16398           used_prefixes |= PREFIX_ADDR;
16399         }
16400       strcpy (op_out[0], op1_names[0]);
16401       strcpy (op_out[1], names[1]);
16402       strcpy (op_out[2], names[2]);
16403       two_source_ops = 1;
16404     }
16405   /* Skip mod/rm byte.  */
16406   MODRM_CHECK;
16407   codep++;
16408 }
16409
16410 static void
16411 BadOp (void)
16412 {
16413   /* Throw away prefixes and 1st. opcode byte.  */
16414   codep = insn_codep + 1;
16415   oappend ("(bad)");
16416 }
16417
16418 static void
16419 REP_Fixup (int bytemode, int sizeflag)
16420 {
16421   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16422      lods and stos.  */
16423   if (prefixes & PREFIX_REPZ)
16424     all_prefixes[last_repz_prefix] = REP_PREFIX;
16425
16426   switch (bytemode)
16427     {
16428     case al_reg:
16429     case eAX_reg:
16430     case indir_dx_reg:
16431       OP_IMREG (bytemode, sizeflag);
16432       break;
16433     case eDI_reg:
16434       OP_ESreg (bytemode, sizeflag);
16435       break;
16436     case eSI_reg:
16437       OP_DSreg (bytemode, sizeflag);
16438       break;
16439     default:
16440       abort ();
16441       break;
16442     }
16443 }
16444
16445 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16446    "bnd".  */
16447
16448 static void
16449 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16450 {
16451   if (prefixes & PREFIX_REPNZ)
16452     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16453 }
16454
16455 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16456    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16457  */
16458
16459 static void
16460 HLE_Fixup1 (int bytemode, int sizeflag)
16461 {
16462   if (modrm.mod != 3
16463       && (prefixes & PREFIX_LOCK) != 0)
16464     {
16465       if (prefixes & PREFIX_REPZ)
16466         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16467       if (prefixes & PREFIX_REPNZ)
16468         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16469     }
16470
16471   OP_E (bytemode, sizeflag);
16472 }
16473
16474 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16475    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16476  */
16477
16478 static void
16479 HLE_Fixup2 (int bytemode, int sizeflag)
16480 {
16481   if (modrm.mod != 3)
16482     {
16483       if (prefixes & PREFIX_REPZ)
16484         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16485       if (prefixes & PREFIX_REPNZ)
16486         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16487     }
16488
16489   OP_E (bytemode, sizeflag);
16490 }
16491
16492 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16493    "xrelease" for memory operand.  No check for LOCK prefix.   */
16494
16495 static void
16496 HLE_Fixup3 (int bytemode, int sizeflag)
16497 {
16498   if (modrm.mod != 3
16499       && last_repz_prefix > last_repnz_prefix
16500       && (prefixes & PREFIX_REPZ) != 0)
16501     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16502
16503   OP_E (bytemode, sizeflag);
16504 }
16505
16506 static void
16507 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16508 {
16509   USED_REX (REX_W);
16510   if (rex & REX_W)
16511     {
16512       /* Change cmpxchg8b to cmpxchg16b.  */
16513       char *p = mnemonicendp - 2;
16514       mnemonicendp = stpcpy (p, "16b");
16515       bytemode = o_mode;
16516     }
16517   else if ((prefixes & PREFIX_LOCK) != 0)
16518     {
16519       if (prefixes & PREFIX_REPZ)
16520         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16521       if (prefixes & PREFIX_REPNZ)
16522         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16523     }
16524
16525   OP_M (bytemode, sizeflag);
16526 }
16527
16528 static void
16529 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16530 {
16531   const char **names;
16532
16533   if (need_vex)
16534     {
16535       switch (vex.length)
16536         {
16537         case 128:
16538           names = names_xmm;
16539           break;
16540         case 256:
16541           names = names_ymm;
16542           break;
16543         default:
16544           abort ();
16545         }
16546     }
16547   else
16548     names = names_xmm;
16549   oappend (names[reg]);
16550 }
16551
16552 static void
16553 CRC32_Fixup (int bytemode, int sizeflag)
16554 {
16555   /* Add proper suffix to "crc32".  */
16556   char *p = mnemonicendp;
16557
16558   switch (bytemode)
16559     {
16560     case b_mode:
16561       if (intel_syntax)
16562         goto skip;
16563
16564       *p++ = 'b';
16565       break;
16566     case v_mode:
16567       if (intel_syntax)
16568         goto skip;
16569
16570       USED_REX (REX_W);
16571       if (rex & REX_W)
16572         *p++ = 'q';
16573       else
16574         {
16575           if (sizeflag & DFLAG)
16576             *p++ = 'l';
16577           else
16578             *p++ = 'w';
16579           used_prefixes |= (prefixes & PREFIX_DATA);
16580         }
16581       break;
16582     default:
16583       oappend (INTERNAL_DISASSEMBLER_ERROR);
16584       break;
16585     }
16586   mnemonicendp = p;
16587   *p = '\0';
16588
16589 skip:
16590   if (modrm.mod == 3)
16591     {
16592       int add;
16593
16594       /* Skip mod/rm byte.  */
16595       MODRM_CHECK;
16596       codep++;
16597
16598       USED_REX (REX_B);
16599       add = (rex & REX_B) ? 8 : 0;
16600       if (bytemode == b_mode)
16601         {
16602           USED_REX (0);
16603           if (rex)
16604             oappend (names8rex[modrm.rm + add]);
16605           else
16606             oappend (names8[modrm.rm + add]);
16607         }
16608       else
16609         {
16610           USED_REX (REX_W);
16611           if (rex & REX_W)
16612             oappend (names64[modrm.rm + add]);
16613           else if ((prefixes & PREFIX_DATA))
16614             oappend (names16[modrm.rm + add]);
16615           else
16616             oappend (names32[modrm.rm + add]);
16617         }
16618     }
16619   else
16620     OP_E (bytemode, sizeflag);
16621 }
16622
16623 static void
16624 FXSAVE_Fixup (int bytemode, int sizeflag)
16625 {
16626   /* Add proper suffix to "fxsave" and "fxrstor".  */
16627   USED_REX (REX_W);
16628   if (rex & REX_W)
16629     {
16630       char *p = mnemonicendp;
16631       *p++ = '6';
16632       *p++ = '4';
16633       *p = '\0';
16634       mnemonicendp = p;
16635     }
16636   OP_M (bytemode, sizeflag);
16637 }
16638
16639 /* Display the destination register operand for instructions with
16640    VEX. */
16641
16642 static void
16643 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16644 {
16645   int reg;
16646   const char **names;
16647
16648   if (!need_vex)
16649     abort ();
16650
16651   if (!need_vex_reg)
16652     return;
16653
16654   reg = vex.register_specifier;
16655   if (vex.evex)
16656     {
16657       if (!vex.v)
16658         reg += 16;
16659     }
16660
16661   if (bytemode == vex_scalar_mode)
16662     {
16663       oappend (names_xmm[reg]);
16664       return;
16665     }
16666
16667   switch (vex.length)
16668     {
16669     case 128:
16670       switch (bytemode)
16671         {
16672         case vex_mode:
16673         case vex128_mode:
16674         case vex_vsib_q_w_dq_mode:
16675         case vex_vsib_q_w_d_mode:
16676           names = names_xmm;
16677           break;
16678         case dq_mode:
16679           if (vex.w)
16680             names = names64;
16681           else
16682             names = names32;
16683           break;
16684         case mask_bd_mode:
16685         case mask_mode:
16686           names = names_mask;
16687           break;
16688         default:
16689           abort ();
16690           return;
16691         }
16692       break;
16693     case 256:
16694       switch (bytemode)
16695         {
16696         case vex_mode:
16697         case vex256_mode:
16698           names = names_ymm;
16699           break;
16700         case vex_vsib_q_w_dq_mode:
16701         case vex_vsib_q_w_d_mode:
16702           names = vex.w ? names_ymm : names_xmm;
16703           break;
16704         case mask_bd_mode:
16705         case mask_mode:
16706           names = names_mask;
16707           break;
16708         default:
16709           abort ();
16710           return;
16711         }
16712       break;
16713     case 512:
16714       names = names_zmm;
16715       break;
16716     default:
16717       abort ();
16718       break;
16719     }
16720   oappend (names[reg]);
16721 }
16722
16723 /* Get the VEX immediate byte without moving codep.  */
16724
16725 static unsigned char
16726 get_vex_imm8 (int sizeflag, int opnum)
16727 {
16728   int bytes_before_imm = 0;
16729
16730   if (modrm.mod != 3)
16731     {
16732       /* There are SIB/displacement bytes.  */
16733       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16734         {
16735           /* 32/64 bit address mode */
16736           int base = modrm.rm;
16737
16738           /* Check SIB byte.  */
16739           if (base == 4)
16740             {
16741               FETCH_DATA (the_info, codep + 1);
16742               base = *codep & 7;
16743               /* When decoding the third source, don't increase
16744                  bytes_before_imm as this has already been incremented
16745                  by one in OP_E_memory while decoding the second
16746                  source operand.  */
16747               if (opnum == 0)
16748                 bytes_before_imm++;
16749             }
16750
16751           /* Don't increase bytes_before_imm when decoding the third source,
16752              it has already been incremented by OP_E_memory while decoding
16753              the second source operand.  */
16754           if (opnum == 0)
16755             {
16756               switch (modrm.mod)
16757                 {
16758                   case 0:
16759                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16760                        SIB == 5, there is a 4 byte displacement.  */
16761                     if (base != 5)
16762                       /* No displacement. */
16763                       break;
16764                   case 2:
16765                     /* 4 byte displacement.  */
16766                     bytes_before_imm += 4;
16767                     break;
16768                   case 1:
16769                     /* 1 byte displacement.  */
16770                     bytes_before_imm++;
16771                     break;
16772                 }
16773             }
16774         }
16775       else
16776         {
16777           /* 16 bit address mode */
16778           /* Don't increase bytes_before_imm when decoding the third source,
16779              it has already been incremented by OP_E_memory while decoding
16780              the second source operand.  */
16781           if (opnum == 0)
16782             {
16783               switch (modrm.mod)
16784                 {
16785                 case 0:
16786                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16787                   if (modrm.rm != 6)
16788                     /* No displacement. */
16789                     break;
16790                 case 2:
16791                   /* 2 byte displacement.  */
16792                   bytes_before_imm += 2;
16793                   break;
16794                 case 1:
16795                   /* 1 byte displacement: when decoding the third source,
16796                      don't increase bytes_before_imm as this has already
16797                      been incremented by one in OP_E_memory while decoding
16798                      the second source operand.  */
16799                   if (opnum == 0)
16800                     bytes_before_imm++;
16801
16802                   break;
16803                 }
16804             }
16805         }
16806     }
16807
16808   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16809   return codep [bytes_before_imm];
16810 }
16811
16812 static void
16813 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16814 {
16815   const char **names;
16816
16817   if (reg == -1 && modrm.mod != 3)
16818     {
16819       OP_E_memory (bytemode, sizeflag);
16820       return;
16821     }
16822   else
16823     {
16824       if (reg == -1)
16825         {
16826           reg = modrm.rm;
16827           USED_REX (REX_B);
16828           if (rex & REX_B)
16829             reg += 8;
16830         }
16831       else if (reg > 7 && address_mode != mode_64bit)
16832         BadOp ();
16833     }
16834
16835   switch (vex.length)
16836     {
16837     case 128:
16838       names = names_xmm;
16839       break;
16840     case 256:
16841       names = names_ymm;
16842       break;
16843     default:
16844       abort ();
16845     }
16846   oappend (names[reg]);
16847 }
16848
16849 static void
16850 OP_EX_VexImmW (int bytemode, int sizeflag)
16851 {
16852   int reg = -1;
16853   static unsigned char vex_imm8;
16854
16855   if (vex_w_done == 0)
16856     {
16857       vex_w_done = 1;
16858
16859       /* Skip mod/rm byte.  */
16860       MODRM_CHECK;
16861       codep++;
16862
16863       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16864
16865       if (vex.w)
16866           reg = vex_imm8 >> 4;
16867
16868       OP_EX_VexReg (bytemode, sizeflag, reg);
16869     }
16870   else if (vex_w_done == 1)
16871     {
16872       vex_w_done = 2;
16873
16874       if (!vex.w)
16875           reg = vex_imm8 >> 4;
16876
16877       OP_EX_VexReg (bytemode, sizeflag, reg);
16878     }
16879   else
16880     {
16881       /* Output the imm8 directly.  */
16882       scratchbuf[0] = '$';
16883       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16884       oappend_maybe_intel (scratchbuf);
16885       scratchbuf[0] = '\0';
16886       codep++;
16887     }
16888 }
16889
16890 static void
16891 OP_Vex_2src (int bytemode, int sizeflag)
16892 {
16893   if (modrm.mod == 3)
16894     {
16895       int reg = modrm.rm;
16896       USED_REX (REX_B);
16897       if (rex & REX_B)
16898         reg += 8;
16899       oappend (names_xmm[reg]);
16900     }
16901   else
16902     {
16903       if (intel_syntax
16904           && (bytemode == v_mode || bytemode == v_swap_mode))
16905         {
16906           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16907           used_prefixes |= (prefixes & PREFIX_DATA);
16908         }
16909       OP_E (bytemode, sizeflag);
16910     }
16911 }
16912
16913 static void
16914 OP_Vex_2src_1 (int bytemode, int sizeflag)
16915 {
16916   if (modrm.mod == 3)
16917     {
16918       /* Skip mod/rm byte.   */
16919       MODRM_CHECK;
16920       codep++;
16921     }
16922
16923   if (vex.w)
16924     oappend (names_xmm[vex.register_specifier]);
16925   else
16926     OP_Vex_2src (bytemode, sizeflag);
16927 }
16928
16929 static void
16930 OP_Vex_2src_2 (int bytemode, int sizeflag)
16931 {
16932   if (vex.w)
16933     OP_Vex_2src (bytemode, sizeflag);
16934   else
16935     oappend (names_xmm[vex.register_specifier]);
16936 }
16937
16938 static void
16939 OP_EX_VexW (int bytemode, int sizeflag)
16940 {
16941   int reg = -1;
16942
16943   if (!vex_w_done)
16944     {
16945       vex_w_done = 1;
16946
16947       /* Skip mod/rm byte.  */
16948       MODRM_CHECK;
16949       codep++;
16950
16951       if (vex.w)
16952         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16953     }
16954   else
16955     {
16956       if (!vex.w)
16957         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16958     }
16959
16960   OP_EX_VexReg (bytemode, sizeflag, reg);
16961 }
16962
16963 static void
16964 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16965              int sizeflag ATTRIBUTE_UNUSED)
16966 {
16967   /* Skip the immediate byte and check for invalid bits.  */
16968   FETCH_DATA (the_info, codep + 1);
16969   if (*codep++ & 0xf)
16970     BadOp ();
16971 }
16972
16973 static void
16974 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16975 {
16976   int reg;
16977   const char **names;
16978
16979   FETCH_DATA (the_info, codep + 1);
16980   reg = *codep++;
16981
16982   if (bytemode != x_mode)
16983     abort ();
16984
16985   if (reg & 0xf)
16986       BadOp ();
16987
16988   reg >>= 4;
16989   if (reg > 7 && address_mode != mode_64bit)
16990     BadOp ();
16991
16992   switch (vex.length)
16993     {
16994     case 128:
16995       names = names_xmm;
16996       break;
16997     case 256:
16998       names = names_ymm;
16999       break;
17000     default:
17001       abort ();
17002     }
17003   oappend (names[reg]);
17004 }
17005
17006 static void
17007 OP_XMM_VexW (int bytemode, int sizeflag)
17008 {
17009   /* Turn off the REX.W bit since it is used for swapping operands
17010      now.  */
17011   rex &= ~REX_W;
17012   OP_XMM (bytemode, sizeflag);
17013 }
17014
17015 static void
17016 OP_EX_Vex (int bytemode, int sizeflag)
17017 {
17018   if (modrm.mod != 3)
17019     {
17020       if (vex.register_specifier != 0)
17021         BadOp ();
17022       need_vex_reg = 0;
17023     }
17024   OP_EX (bytemode, sizeflag);
17025 }
17026
17027 static void
17028 OP_XMM_Vex (int bytemode, int sizeflag)
17029 {
17030   if (modrm.mod != 3)
17031     {
17032       if (vex.register_specifier != 0)
17033         BadOp ();
17034       need_vex_reg = 0;
17035     }
17036   OP_XMM (bytemode, sizeflag);
17037 }
17038
17039 static void
17040 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17041 {
17042   switch (vex.length)
17043     {
17044     case 128:
17045       mnemonicendp = stpcpy (obuf, "vzeroupper");
17046       break;
17047     case 256:
17048       mnemonicendp = stpcpy (obuf, "vzeroall");
17049       break;
17050     default:
17051       abort ();
17052     }
17053 }
17054
17055 static struct op vex_cmp_op[] =
17056 {
17057   { STRING_COMMA_LEN ("eq") },
17058   { STRING_COMMA_LEN ("lt") },
17059   { STRING_COMMA_LEN ("le") },
17060   { STRING_COMMA_LEN ("unord") },
17061   { STRING_COMMA_LEN ("neq") },
17062   { STRING_COMMA_LEN ("nlt") },
17063   { STRING_COMMA_LEN ("nle") },
17064   { STRING_COMMA_LEN ("ord") },
17065   { STRING_COMMA_LEN ("eq_uq") },
17066   { STRING_COMMA_LEN ("nge") },
17067   { STRING_COMMA_LEN ("ngt") },
17068   { STRING_COMMA_LEN ("false") },
17069   { STRING_COMMA_LEN ("neq_oq") },
17070   { STRING_COMMA_LEN ("ge") },
17071   { STRING_COMMA_LEN ("gt") },
17072   { STRING_COMMA_LEN ("true") },
17073   { STRING_COMMA_LEN ("eq_os") },
17074   { STRING_COMMA_LEN ("lt_oq") },
17075   { STRING_COMMA_LEN ("le_oq") },
17076   { STRING_COMMA_LEN ("unord_s") },
17077   { STRING_COMMA_LEN ("neq_us") },
17078   { STRING_COMMA_LEN ("nlt_uq") },
17079   { STRING_COMMA_LEN ("nle_uq") },
17080   { STRING_COMMA_LEN ("ord_s") },
17081   { STRING_COMMA_LEN ("eq_us") },
17082   { STRING_COMMA_LEN ("nge_uq") },
17083   { STRING_COMMA_LEN ("ngt_uq") },
17084   { STRING_COMMA_LEN ("false_os") },
17085   { STRING_COMMA_LEN ("neq_os") },
17086   { STRING_COMMA_LEN ("ge_oq") },
17087   { STRING_COMMA_LEN ("gt_oq") },
17088   { STRING_COMMA_LEN ("true_us") },
17089 };
17090
17091 static void
17092 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17093 {
17094   unsigned int cmp_type;
17095
17096   FETCH_DATA (the_info, codep + 1);
17097   cmp_type = *codep++ & 0xff;
17098   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17099     {
17100       char suffix [3];
17101       char *p = mnemonicendp - 2;
17102       suffix[0] = p[0];
17103       suffix[1] = p[1];
17104       suffix[2] = '\0';
17105       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17106       mnemonicendp += vex_cmp_op[cmp_type].len;
17107     }
17108   else
17109     {
17110       /* We have a reserved extension byte.  Output it directly.  */
17111       scratchbuf[0] = '$';
17112       print_operand_value (scratchbuf + 1, 1, cmp_type);
17113       oappend_maybe_intel (scratchbuf);
17114       scratchbuf[0] = '\0';
17115     }
17116 }
17117
17118 static void
17119 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17120              int sizeflag ATTRIBUTE_UNUSED)
17121 {
17122   unsigned int cmp_type;
17123
17124   if (!vex.evex)
17125     abort ();
17126
17127   FETCH_DATA (the_info, codep + 1);
17128   cmp_type = *codep++ & 0xff;
17129   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17130      If it's the case, print suffix, otherwise - print the immediate.  */
17131   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17132       && cmp_type != 3
17133       && cmp_type != 7)
17134     {
17135       char suffix [3];
17136       char *p = mnemonicendp - 2;
17137
17138       /* vpcmp* can have both one- and two-lettered suffix.  */
17139       if (p[0] == 'p')
17140         {
17141           p++;
17142           suffix[0] = p[0];
17143           suffix[1] = '\0';
17144         }
17145       else
17146         {
17147           suffix[0] = p[0];
17148           suffix[1] = p[1];
17149           suffix[2] = '\0';
17150         }
17151
17152       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17153       mnemonicendp += simd_cmp_op[cmp_type].len;
17154     }
17155   else
17156     {
17157       /* We have a reserved extension byte.  Output it directly.  */
17158       scratchbuf[0] = '$';
17159       print_operand_value (scratchbuf + 1, 1, cmp_type);
17160       oappend_maybe_intel (scratchbuf);
17161       scratchbuf[0] = '\0';
17162     }
17163 }
17164
17165 static const struct op pclmul_op[] =
17166 {
17167   { STRING_COMMA_LEN ("lql") },
17168   { STRING_COMMA_LEN ("hql") },
17169   { STRING_COMMA_LEN ("lqh") },
17170   { STRING_COMMA_LEN ("hqh") }
17171 };
17172
17173 static void
17174 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17175               int sizeflag ATTRIBUTE_UNUSED)
17176 {
17177   unsigned int pclmul_type;
17178
17179   FETCH_DATA (the_info, codep + 1);
17180   pclmul_type = *codep++ & 0xff;
17181   switch (pclmul_type)
17182     {
17183     case 0x10:
17184       pclmul_type = 2;
17185       break;
17186     case 0x11:
17187       pclmul_type = 3;
17188       break;
17189     default:
17190       break;
17191     }
17192   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17193     {
17194       char suffix [4];
17195       char *p = mnemonicendp - 3;
17196       suffix[0] = p[0];
17197       suffix[1] = p[1];
17198       suffix[2] = p[2];
17199       suffix[3] = '\0';
17200       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17201       mnemonicendp += pclmul_op[pclmul_type].len;
17202     }
17203   else
17204     {
17205       /* We have a reserved extension byte.  Output it directly.  */
17206       scratchbuf[0] = '$';
17207       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17208       oappend_maybe_intel (scratchbuf);
17209       scratchbuf[0] = '\0';
17210     }
17211 }
17212
17213 static void
17214 MOVBE_Fixup (int bytemode, int sizeflag)
17215 {
17216   /* Add proper suffix to "movbe".  */
17217   char *p = mnemonicendp;
17218
17219   switch (bytemode)
17220     {
17221     case v_mode:
17222       if (intel_syntax)
17223         goto skip;
17224
17225       USED_REX (REX_W);
17226       if (sizeflag & SUFFIX_ALWAYS)
17227         {
17228           if (rex & REX_W)
17229             *p++ = 'q';
17230           else
17231             {
17232               if (sizeflag & DFLAG)
17233                 *p++ = 'l';
17234               else
17235                 *p++ = 'w';
17236               used_prefixes |= (prefixes & PREFIX_DATA);
17237             }
17238         }
17239       break;
17240     default:
17241       oappend (INTERNAL_DISASSEMBLER_ERROR);
17242       break;
17243     }
17244   mnemonicendp = p;
17245   *p = '\0';
17246
17247 skip:
17248   OP_M (bytemode, sizeflag);
17249 }
17250
17251 static void
17252 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17253 {
17254   int reg;
17255   const char **names;
17256
17257   /* Skip mod/rm byte.  */
17258   MODRM_CHECK;
17259   codep++;
17260
17261   if (vex.w)
17262     names = names64;
17263   else
17264     names = names32;
17265
17266   reg = modrm.rm;
17267   USED_REX (REX_B);
17268   if (rex & REX_B)
17269     reg += 8;
17270
17271   oappend (names[reg]);
17272 }
17273
17274 static void
17275 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17276 {
17277   const char **names;
17278
17279   if (vex.w)
17280     names = names64;
17281   else
17282     names = names32;
17283
17284   oappend (names[vex.register_specifier]);
17285 }
17286
17287 static void
17288 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17289 {
17290   if (!vex.evex
17291       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17292     abort ();
17293
17294   USED_REX (REX_R);
17295   if ((rex & REX_R) != 0 || !vex.r)
17296     {
17297       BadOp ();
17298       return;
17299     }
17300
17301   oappend (names_mask [modrm.reg]);
17302 }
17303
17304 static void
17305 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17306 {
17307   if (!vex.evex
17308       || (bytemode != evex_rounding_mode
17309           && bytemode != evex_sae_mode))
17310     abort ();
17311   if (modrm.mod == 3 && vex.b)
17312     switch (bytemode)
17313       {
17314       case evex_rounding_mode:
17315         oappend (names_rounding[vex.ll]);
17316         break;
17317       case evex_sae_mode:
17318         oappend ("{sae}");
17319         break;
17320       default:
17321         break;
17322       }
17323 }