opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* mwaitx instruction required */
 202   CpuMWAITX,
 203   /* Clzero instruction required */
 204   CpuCLZERO,
 205   /* OSPKE instruction required */
 206   CpuOSPKE,
 207   /* RDPID instruction required */
 208   CpuRDPID,
 209   /* PTWRITE instruction required */
 210   CpuPTWRITE,
 211   /* MMX register support required */
 212   CpuRegMMX,
 213   /* XMM register support required */
 214   CpuRegXMM,
 215   /* YMM register support required */
 216   CpuRegYMM,
 217   /* ZMM register support required */
 218   CpuRegZMM,
 219   /* Mask register support required */
 220   CpuRegMask,
 221   /* 64bit support required  */
 222   Cpu64,
 223   /* Not supported in the 64bit mode  */
 224   CpuNo64,
 225   /* The last bitfield in i386_cpu_flags.  */
 226   CpuMax = CpuNo64
 227 };
 228
 229 #define CpuNumOfUints \
 230   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 231 #define CpuNumOfBits \
 232   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 233
 234 /* If you get a compiler error for zero width of the unused field,
 235    comment it out.  */
 236 #define CpuUnused       (CpuMax + 1)
 237
 238 /* We can check if an instruction is available with array instead
 239    of bitfield. */
 240 typedef union i386_cpu_flags
 241 {
 242   struct
 243     {
 244       unsigned int cpui186:1;
 245       unsigned int cpui286:1;
 246       unsigned int cpui386:1;
 247       unsigned int cpui486:1;
 248       unsigned int cpui586:1;
 249       unsigned int cpui686:1;
 250       unsigned int cpuclflush:1;
 251       unsigned int cpunop:1;
 252       unsigned int cpusyscall:1;
 253       unsigned int cpu8087:1;
 254       unsigned int cpu287:1;
 255       unsigned int cpu387:1;
 256       unsigned int cpu687:1;
 257       unsigned int cpufisttp:1;
 258       unsigned int cpummx:1;
 259       unsigned int cpusse:1;
 260       unsigned int cpusse2:1;
 261       unsigned int cpua3dnow:1;
 262       unsigned int cpua3dnowa:1;
 263       unsigned int cpusse3:1;
 264       unsigned int cpupadlock:1;
 265       unsigned int cpusvme:1;
 266       unsigned int cpuvmx:1;
 267       unsigned int cpusmx:1;
 268       unsigned int cpussse3:1;
 269       unsigned int cpusse4a:1;
 270       unsigned int cpuabm:1;
 271       unsigned int cpusse4_1:1;
 272       unsigned int cpusse4_2:1;
 273       unsigned int cpuavx:1;
 274       unsigned int cpuavx2:1;
 275       unsigned int cpuavx512f:1;
 276       unsigned int cpuavx512cd:1;
 277       unsigned int cpuavx512er:1;
 278       unsigned int cpuavx512pf:1;
 279       unsigned int cpuavx512vl:1;
 280       unsigned int cpuavx512dq:1;
 281       unsigned int cpuavx512bw:1;
 282       unsigned int cpul1om:1;
 283       unsigned int cpuk1om:1;
 284       unsigned int cpuiamcu:1;
 285       unsigned int cpuxsave:1;
 286       unsigned int cpuxsaveopt:1;
 287       unsigned int cpuaes:1;
 288       unsigned int cpupclmul:1;
 289       unsigned int cpufma:1;
 290       unsigned int cpufma4:1;
 291       unsigned int cpuxop:1;
 292       unsigned int cpulwp:1;
 293       unsigned int cpubmi:1;
 294       unsigned int cputbm:1;
 295       unsigned int cpumovbe:1;
 296       unsigned int cpucx16:1;
 297       unsigned int cpuept:1;
 298       unsigned int cpurdtscp:1;
 299       unsigned int cpufsgsbase:1;
 300       unsigned int cpurdrnd:1;
 301       unsigned int cpuf16c:1;
 302       unsigned int cpubmi2:1;
 303       unsigned int cpulzcnt:1;
 304       unsigned int cpuhle:1;
 305       unsigned int cpurtm:1;
 306       unsigned int cpuinvpcid:1;
 307       unsigned int cpuvmfunc:1;
 308       unsigned int cpumpx:1;
 309       unsigned int cpulm:1;
 310       unsigned int cpurdseed:1;
 311       unsigned int cpuadx:1;
 312       unsigned int cpuprfchw:1;
 313       unsigned int cpusmap:1;
 314       unsigned int cpusha:1;
 315       unsigned int cpuvrex:1;
 316       unsigned int cpuclflushopt:1;
 317       unsigned int cpuxsaves:1;
 318       unsigned int cpuxsavec:1;
 319       unsigned int cpuprefetchwt1:1;
 320       unsigned int cpuse1:1;
 321       unsigned int cpuclwb:1;
 322       unsigned int cpuavx512ifma:1;
 323       unsigned int cpuavx512vbmi:1;
 324       unsigned int cpuavx512_4fmaps:1;
 325       unsigned int cpuavx512_4vnniw:1;
 326       unsigned int cpuavx512_vpopcntdq:1;
 327       unsigned int cpumwaitx:1;
 328       unsigned int cpuclzero:1;
 329       unsigned int cpuospke:1;
 330       unsigned int cpurdpid:1;
 331       unsigned int cpuptwrite:1;
 332       unsigned int cpuregmmx:1;
 333       unsigned int cpuregxmm:1;
 334       unsigned int cpuregymm:1;
 335       unsigned int cpuregzmm:1;
 336       unsigned int cpuregmask:1;
 337       unsigned int cpu64:1;
 338       unsigned int cpuno64:1;
 339 #ifdef CpuUnused
 340       unsigned int unused:(CpuNumOfBits - CpuUnused);
 341 #endif
 342     } bitfield;
 343   unsigned int array[CpuNumOfUints];
 344 } i386_cpu_flags;
 345
 346 /* Position of opcode_modifier bits.  */
 347
 348 enum
 349 {
 350   /* has direction bit. */
 351   D = 0,
 352   /* set if operands can be words or dwords encoded the canonical way */
 353   W,
 354   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 355      operand in encoding.  */
 356   S,
 357   /* insn has a modrm byte. */
 358   Modrm,
 359   /* register is in low 3 bits of opcode */
 360   ShortForm,
 361   /* special case for jump insns.  */
 362   Jump,
 363   /* call and jump */
 364   JumpDword,
 365   /* loop and jecxz */
 366   JumpByte,
 367   /* special case for intersegment leaps/calls */
 368   JumpInterSegment,
 369   /* FP insn memory format bit, sized by 0x4 */
 370   FloatMF,
 371   /* src/dest swap for floats. */
 372   FloatR,
 373   /* has float insn direction bit. */
 374   FloatD,
 375   /* needs size prefix if in 32-bit mode */
 376   Size16,
 377   /* needs size prefix if in 16-bit mode */
 378   Size32,
 379   /* needs size prefix if in 64-bit mode */
 380   Size64,
 381   /* check register size.  */
 382   CheckRegSize,
 383   /* instruction ignores operand size prefix and in Intel mode ignores
 384      mnemonic size suffix check.  */
 385   IgnoreSize,
 386   /* default insn size depends on mode */
 387   DefaultSize,
 388   /* b suffix on instruction illegal */
 389   No_bSuf,
 390   /* w suffix on instruction illegal */
 391   No_wSuf,
 392   /* l suffix on instruction illegal */
 393   No_lSuf,
 394   /* s suffix on instruction illegal */
 395   No_sSuf,
 396   /* q suffix on instruction illegal */
 397   No_qSuf,
 398   /* long double suffix on instruction illegal */
 399   No_ldSuf,
 400   /* instruction needs FWAIT */
 401   FWait,
 402   /* quick test for string instructions */
 403   IsString,
 404   /* quick test if branch instruction is MPX supported */
 405   BNDPrefixOk,
 406   /* quick test for lockable instructions */
 407   IsLockable,
 408   /* fake an extra reg operand for clr, imul and special register
 409      processing for some instructions.  */
 410   RegKludge,
 411   /* The first operand must be xmm0 */
 412   FirstXmm0,
 413   /* An implicit xmm0 as the first operand */
 414   Implicit1stXmm0,
 415   /* The HLE prefix is OK:
 416      1. With a LOCK prefix.
 417      2. With or without a LOCK prefix.
 418      3. With a RELEASE (0xf3) prefix.
 419    */
 420 #define HLEPrefixNone           0
 421 #define HLEPrefixLock           1
 422 #define HLEPrefixAny            2
 423 #define HLEPrefixRelease        3
 424   HLEPrefixOk,
 425   /* An instruction on which a "rep" prefix is acceptable.  */
 426   RepPrefixOk,
 427   /* Convert to DWORD */
 428   ToDword,
 429   /* Convert to QWORD */
 430   ToQword,
 431   /* Address prefix changes operand 0 */
 432   AddrPrefixOp0,
 433   /* opcode is a prefix */
 434   IsPrefix,
 435   /* instruction has extension in 8 bit imm */
 436   ImmExt,
 437   /* instruction don't need Rex64 prefix.  */
 438   NoRex64,
 439   /* instruction require Rex64 prefix.  */
 440   Rex64,
 441   /* deprecated fp insn, gets a warning */
 442   Ugh,
 443   /* insn has VEX prefix:
 444         1: 128bit VEX prefix.
 445         2: 256bit VEX prefix.
 446         3: Scalar VEX prefix.
 447    */
 448 #define VEX128          1
 449 #define VEX256          2
 450 #define VEXScalar       3
 451   Vex,
 452   /* How to encode VEX.vvvv:
 453      0: VEX.vvvv must be 1111b.
 454      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 455         the content of source registers will be preserved.
 456         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 457         where the content of first source register will be overwritten
 458         by the result.
 459         VEX.NDD2.  The second destination register operand is encoded in
 460         VEX.vvvv for instructions with 2 destination register operands.
 461         For assembler, there are no difference between VEX.NDS, VEX.DDS
 462         and VEX.NDD2.
 463      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 464      instructions with 1 destination register operand.
 465      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 466         of the operands can access a memory location.
 467    */
 468 #define VEXXDS  1
 469 #define VEXNDD  2
 470 #define VEXLWP  3
 471   VexVVVV,
 472   /* How the VEX.W bit is used:
 473      0: Set by the REX.W bit.
 474      1: VEX.W0.  Should always be 0.
 475      2: VEX.W1.  Should always be 1.
 476    */
 477 #define VEXW0   1
 478 #define VEXW1   2
 479   VexW,
 480   /* VEX opcode prefix:
 481      0: VEX 0x0F opcode prefix.
 482      1: VEX 0x0F38 opcode prefix.
 483      2: VEX 0x0F3A opcode prefix
 484      3: XOP 0x08 opcode prefix.
 485      4: XOP 0x09 opcode prefix
 486      5: XOP 0x0A opcode prefix.
 487    */
 488 #define VEX0F           0
 489 #define VEX0F38         1
 490 #define VEX0F3A         2
 491 #define XOP08           3
 492 #define XOP09           4
 493 #define XOP0A           5
 494   VexOpcode,
 495   /* number of VEX source operands:
 496      0: <= 2 source operands.
 497      1: 2 XOP source operands.
 498      2: 3 source operands.
 499    */
 500 #define XOP2SOURCES     1
 501 #define VEX3SOURCES     2
 502   VexSources,
 503   /* instruction has VEX 8 bit imm */
 504   VexImmExt,
 505   /* Instruction with vector SIB byte:
 506         1: 128bit vector register.
 507         2: 256bit vector register.
 508         3: 512bit vector register.
 509    */
 510 #define VecSIB128       1
 511 #define VecSIB256       2
 512 #define VecSIB512       3
 513   VecSIB,
 514   /* SSE to AVX support required */
 515   SSE2AVX,
 516   /* No AVX equivalent */
 517   NoAVX,
 518
 519   /* insn has EVEX prefix:
 520         1: 512bit EVEX prefix.
 521         2: 128bit EVEX prefix.
 522         3: 256bit EVEX prefix.
 523         4: Length-ignored (LIG) EVEX prefix.
 524    */
 525 #define EVEX512                1
 526 #define EVEX128                2
 527 #define EVEX256                3
 528 #define EVEXLIG                4
 529   EVex,
 530
 531   /* AVX512 masking support:
 532         1: Zeroing-masking.
 533         2: Merging-masking.
 534         3: Both zeroing and merging masking.
 535    */
 536 #define ZEROING_MASKING 1
 537 #define MERGING_MASKING 2
 538 #define BOTH_MASKING    3
 539   Masking,
 540
 541   /* Input element size of vector insn:
 542         0: 32bit.
 543         1: 64bit.
 544    */
 545   VecESize,
 546
 547   /* Broadcast factor.
 548         0: No broadcast.
 549         1: 1to16 broadcast.
 550         2: 1to8 broadcast.
 551    */
 552 #define NO_BROADCAST    0
 553 #define BROADCAST_1TO16 1
 554 #define BROADCAST_1TO8  2
 555 #define BROADCAST_1TO4  3
 556 #define BROADCAST_1TO2  4
 557   Broadcast,
 558
 559   /* Static rounding control is supported.  */
 560   StaticRounding,
 561
 562   /* Supress All Exceptions is supported.  */
 563   SAE,
 564
 565   /* Copressed Disp8*N attribute.  */
 566   Disp8MemShift,
 567
 568   /* Default mask isn't allowed.  */
 569   NoDefMask,
 570
 571   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 572      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 573    */
 574   ImplicitQuadGroup,
 575
 576   /* Compatible with old (<= 2.8.1) versions of gcc  */
 577   OldGcc,
 578   /* AT&T mnemonic.  */
 579   ATTMnemonic,
 580   /* AT&T syntax.  */
 581   ATTSyntax,
 582   /* Intel syntax.  */
 583   IntelSyntax,
 584   /* AMD64.  */
 585   AMD64,
 586   /* Intel64.  */
 587   Intel64,
 588   /* The last bitfield in i386_opcode_modifier.  */
 589   Opcode_Modifier_Max
 590 };
 591
 592 typedef struct i386_opcode_modifier
 593 {
 594   unsigned int d:1;
 595   unsigned int w:1;
 596   unsigned int s:1;
 597   unsigned int modrm:1;
 598   unsigned int shortform:1;
 599   unsigned int jump:1;
 600   unsigned int jumpdword:1;
 601   unsigned int jumpbyte:1;
 602   unsigned int jumpintersegment:1;
 603   unsigned int floatmf:1;
 604   unsigned int floatr:1;
 605   unsigned int floatd:1;
 606   unsigned int size16:1;
 607   unsigned int size32:1;
 608   unsigned int size64:1;
 609   unsigned int checkregsize:1;
 610   unsigned int ignoresize:1;
 611   unsigned int defaultsize:1;
 612   unsigned int no_bsuf:1;
 613   unsigned int no_wsuf:1;
 614   unsigned int no_lsuf:1;
 615   unsigned int no_ssuf:1;
 616   unsigned int no_qsuf:1;
 617   unsigned int no_ldsuf:1;
 618   unsigned int fwait:1;
 619   unsigned int isstring:1;
 620   unsigned int bndprefixok:1;
 621   unsigned int islockable:1;
 622   unsigned int regkludge:1;
 623   unsigned int firstxmm0:1;
 624   unsigned int implicit1stxmm0:1;
 625   unsigned int hleprefixok:2;
 626   unsigned int repprefixok:1;
 627   unsigned int todword:1;
 628   unsigned int toqword:1;
 629   unsigned int addrprefixop0:1;
 630   unsigned int isprefix:1;
 631   unsigned int immext:1;
 632   unsigned int norex64:1;
 633   unsigned int rex64:1;
 634   unsigned int ugh:1;
 635   unsigned int vex:2;
 636   unsigned int vexvvvv:2;
 637   unsigned int vexw:2;
 638   unsigned int vexopcode:3;
 639   unsigned int vexsources:2;
 640   unsigned int veximmext:1;
 641   unsigned int vecsib:2;
 642   unsigned int sse2avx:1;
 643   unsigned int noavx:1;
 644   unsigned int evex:3;
 645   unsigned int masking:2;
 646   unsigned int vecesize:1;
 647   unsigned int broadcast:3;
 648   unsigned int staticrounding:1;
 649   unsigned int sae:1;
 650   unsigned int disp8memshift:3;
 651   unsigned int nodefmask:1;
 652   unsigned int implicitquadgroup:1;
 653   unsigned int oldgcc:1;
 654   unsigned int attmnemonic:1;
 655   unsigned int attsyntax:1;
 656   unsigned int intelsyntax:1;
 657   unsigned int amd64:1;
 658   unsigned int intel64:1;
 659 } i386_opcode_modifier;
 660
 661 /* Position of operand_type bits.  */
 662
 663 enum
 664 {
 665   /* 8bit register */
 666   Reg8 = 0,
 667   /* 16bit register */
 668   Reg16,
 669   /* 32bit register */
 670   Reg32,
 671   /* 64bit register */
 672   Reg64,
 673   /* Floating pointer stack register */
 674   FloatReg,
 675   /* MMX register */
 676   RegMMX,
 677   /* SSE register */
 678   RegXMM,
 679   /* AVX registers */
 680   RegYMM,
 681   /* AVX512 registers */
 682   RegZMM,
 683   /* Vector Mask registers */
 684   RegMask,
 685   /* Control register */
 686   Control,
 687   /* Debug register */
 688   Debug,
 689   /* Test register */
 690   Test,
 691   /* 2 bit segment register */
 692   SReg2,
 693   /* 3 bit segment register */
 694   SReg3,
 695   /* 1 bit immediate */
 696   Imm1,
 697   /* 8 bit immediate */
 698   Imm8,
 699   /* 8 bit immediate sign extended */
 700   Imm8S,
 701   /* 16 bit immediate */
 702   Imm16,
 703   /* 32 bit immediate */
 704   Imm32,
 705   /* 32 bit immediate sign extended */
 706   Imm32S,
 707   /* 64 bit immediate */
 708   Imm64,
 709   /* 8bit/16bit/32bit displacements are used in different ways,
 710      depending on the instruction.  For jumps, they specify the
 711      size of the PC relative displacement, for instructions with
 712      memory operand, they specify the size of the offset relative
 713      to the base register, and for instructions with memory offset
 714      such as `mov 1234,%al' they specify the size of the offset
 715      relative to the segment base.  */
 716   /* 8 bit displacement */
 717   Disp8,
 718   /* 16 bit displacement */
 719   Disp16,
 720   /* 32 bit displacement */
 721   Disp32,
 722   /* 32 bit signed displacement */
 723   Disp32S,
 724   /* 64 bit displacement */
 725   Disp64,
 726   /* Accumulator %al/%ax/%eax/%rax */
 727   Acc,
 728   /* Floating pointer top stack register %st(0) */
 729   FloatAcc,
 730   /* Register which can be used for base or index in memory operand.  */
 731   BaseIndex,
 732   /* Register to hold in/out port addr = dx */
 733   InOutPortReg,
 734   /* Register to hold shift count = cl */
 735   ShiftCount,
 736   /* Absolute address for jump.  */
 737   JumpAbsolute,
 738   /* String insn operand with fixed es segment */
 739   EsSeg,
 740   /* RegMem is for instructions with a modrm byte where the register
 741      destination operand should be encoded in the mod and regmem fields.
 742      Normally, it will be encoded in the reg field. We add a RegMem
 743      flag to the destination register operand to indicate that it should
 744      be encoded in the regmem field.  */
 745   RegMem,
 746   /* Memory.  */
 747   Mem,
 748   /* BYTE memory. */
 749   Byte,
 750   /* WORD memory. 2 byte */
 751   Word,
 752   /* DWORD memory. 4 byte */
 753   Dword,
 754   /* FWORD memory. 6 byte */
 755   Fword,
 756   /* QWORD memory. 8 byte */
 757   Qword,
 758   /* TBYTE memory. 10 byte */
 759   Tbyte,
 760   /* XMMWORD memory. */
 761   Xmmword,
 762   /* YMMWORD memory. */
 763   Ymmword,
 764   /* ZMMWORD memory.  */
 765   Zmmword,
 766   /* Unspecified memory size.  */
 767   Unspecified,
 768   /* Any memory size.  */
 769   Anysize,
 770
 771   /* Vector 4 bit immediate.  */
 772   Vec_Imm4,
 773
 774   /* Bound register.  */
 775   RegBND,
 776
 777   /* Vector 8bit displacement */
 778   Vec_Disp8,
 779
 780   /* The last bitfield in i386_operand_type.  */
 781   OTMax
 782 };
 783
 784 #define OTNumOfUints \
 785   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 786 #define OTNumOfBits \
 787   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 788
 789 /* If you get a compiler error for zero width of the unused field,
 790    comment it out.  */
 791 #define OTUnused                (OTMax + 1)
 792
 793 typedef union i386_operand_type
 794 {
 795   struct
 796     {
 797       unsigned int reg8:1;
 798       unsigned int reg16:1;
 799       unsigned int reg32:1;
 800       unsigned int reg64:1;
 801       unsigned int floatreg:1;
 802       unsigned int regmmx:1;
 803       unsigned int regxmm:1;
 804       unsigned int regymm:1;
 805       unsigned int regzmm:1;
 806       unsigned int regmask:1;
 807       unsigned int control:1;
 808       unsigned int debug:1;
 809       unsigned int test:1;
 810       unsigned int sreg2:1;
 811       unsigned int sreg3:1;
 812       unsigned int imm1:1;
 813       unsigned int imm8:1;
 814       unsigned int imm8s:1;
 815       unsigned int imm16:1;
 816       unsigned int imm32:1;
 817       unsigned int imm32s:1;
 818       unsigned int imm64:1;
 819       unsigned int disp8:1;
 820       unsigned int disp16:1;
 821       unsigned int disp32:1;
 822       unsigned int disp32s:1;
 823       unsigned int disp64:1;
 824       unsigned int acc:1;
 825       unsigned int floatacc:1;
 826       unsigned int baseindex:1;
 827       unsigned int inoutportreg:1;
 828       unsigned int shiftcount:1;
 829       unsigned int jumpabsolute:1;
 830       unsigned int esseg:1;
 831       unsigned int regmem:1;
 832       unsigned int mem:1;
 833       unsigned int byte:1;
 834       unsigned int word:1;
 835       unsigned int dword:1;
 836       unsigned int fword:1;
 837       unsigned int qword:1;
 838       unsigned int tbyte:1;
 839       unsigned int xmmword:1;
 840       unsigned int ymmword:1;
 841       unsigned int zmmword:1;
 842       unsigned int unspecified:1;
 843       unsigned int anysize:1;
 844       unsigned int vec_imm4:1;
 845       unsigned int regbnd:1;
 846       unsigned int vec_disp8:1;
 847 #ifdef OTUnused
 848       unsigned int unused:(OTNumOfBits - OTUnused);
 849 #endif
 850     } bitfield;
 851   unsigned int array[OTNumOfUints];
 852 } i386_operand_type;
 853
 854 typedef struct insn_template
 855 {
 856   /* instruction name sans width suffix ("mov" for movl insns) */
 857   char *name;
 858
 859   /* how many operands */
 860   unsigned int operands;
 861
 862   /* base_opcode is the fundamental opcode byte without optional
 863      prefix(es).  */
 864   unsigned int base_opcode;
 865 #define Opcode_D        0x2 /* Direction bit:
 866                                set if Reg --> Regmem;
 867                                unset if Regmem --> Reg. */
 868 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 869 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 870
 871   /* extension_opcode is the 3 bit extension for group <n> insns.
 872      This field is also used to store the 8-bit opcode suffix for the
 873      AMD 3DNow! instructions.
 874      If this template has no extension opcode (the usual case) use None
 875      Instructions */
 876   unsigned int extension_opcode;
 877 #define None 0xffff             /* If no extension_opcode is possible.  */
 878
 879   /* Opcode length.  */
 880   unsigned char opcode_length;
 881
 882   /* cpu feature flags */
 883   i386_cpu_flags cpu_flags;
 884
 885   /* the bits in opcode_modifier are used to generate the final opcode from
 886      the base_opcode.  These bits also are used to detect alternate forms of
 887      the same instruction */
 888   i386_opcode_modifier opcode_modifier;
 889
 890   /* operand_types[i] describes the type of operand i.  This is made
 891      by OR'ing together all of the possible type masks.  (e.g.
 892      'operand_types[i] = Reg|Imm' specifies that operand i can be
 893      either a register or an immediate operand.  */
 894   i386_operand_type operand_types[MAX_OPERANDS];
 895 }
 896 insn_template;
 897
 898 extern const insn_template i386_optab[];
 899
 900 /* these are for register name --> number & type hash lookup */
 901 typedef struct
 902 {
 903   char *reg_name;
 904   i386_operand_type reg_type;
 905   unsigned char reg_flags;
 906 #define RegRex      0x1  /* Extended register.  */
 907 #define RegRex64    0x2  /* Extended 8 bit register.  */
 908 #define RegVRex     0x4  /* Extended vector register.  */
 909   unsigned char reg_num;
 910 #define RegRip  ((unsigned char ) ~0)
 911 #define RegEip  (RegRip - 1)
 912 /* EIZ and RIZ are fake index registers.  */
 913 #define RegEiz  (RegEip - 1)
 914 #define RegRiz  (RegEiz - 1)
 915 /* FLAT is a fake segment register (Intel mode).  */
 916 #define RegFlat     ((unsigned char) ~0)
 917   signed char dw2_regnum[2];
 918 #define Dw2Inval (-1)
 919 }
 920 reg_entry;
 921
 922 /* Entries in i386_regtab.  */
 923 #define REGNAM_AL 1
 924 #define REGNAM_AX 25
 925 #define REGNAM_EAX 41
 926
 927 extern const reg_entry i386_regtab[];
 928 extern const unsigned int i386_regtab_size;
 929
 930 typedef struct
 931 {
 932   char *seg_name;
 933   unsigned int seg_prefix;
 934 }
 935 seg_entry;
 936
 937 extern const seg_entry cs;
 938 extern const seg_entry ds;
 939 extern const seg_entry ss;
 940 extern const seg_entry es;
 941 extern const seg_entry fs;
 942 extern const seg_entry gs;