opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* WAITPKG instructions required */
 231   CpuWAITPKG,
 232   /* CLDEMOTE instruction required */
 233   CpuCLDEMOTE,
 234   /* 64bit support required  */
 235   Cpu64,
 236   /* Not supported in the 64bit mode  */
 237   CpuNo64,
 238   /* The last bitfield in i386_cpu_flags.  */
 239   CpuMax = CpuNo64
 240 };
 241
 242 #define CpuNumOfUints \
 243   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 244 #define CpuNumOfBits \
 245   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 246
 247 /* If you get a compiler error for zero width of the unused field,
 248    comment it out.  */
 249 #define CpuUnused       (CpuMax + 1)
 250
 251 /* We can check if an instruction is available with array instead
 252    of bitfield. */
 253 typedef union i386_cpu_flags
 254 {
 255   struct
 256     {
 257       unsigned int cpui186:1;
 258       unsigned int cpui286:1;
 259       unsigned int cpui386:1;
 260       unsigned int cpui486:1;
 261       unsigned int cpui586:1;
 262       unsigned int cpui686:1;
 263       unsigned int cpuclflush:1;
 264       unsigned int cpunop:1;
 265       unsigned int cpusyscall:1;
 266       unsigned int cpu8087:1;
 267       unsigned int cpu287:1;
 268       unsigned int cpu387:1;
 269       unsigned int cpu687:1;
 270       unsigned int cpufisttp:1;
 271       unsigned int cpummx:1;
 272       unsigned int cpusse:1;
 273       unsigned int cpusse2:1;
 274       unsigned int cpua3dnow:1;
 275       unsigned int cpua3dnowa:1;
 276       unsigned int cpusse3:1;
 277       unsigned int cpupadlock:1;
 278       unsigned int cpusvme:1;
 279       unsigned int cpuvmx:1;
 280       unsigned int cpusmx:1;
 281       unsigned int cpussse3:1;
 282       unsigned int cpusse4a:1;
 283       unsigned int cpuabm:1;
 284       unsigned int cpusse4_1:1;
 285       unsigned int cpusse4_2:1;
 286       unsigned int cpuavx:1;
 287       unsigned int cpuavx2:1;
 288       unsigned int cpuavx512f:1;
 289       unsigned int cpuavx512cd:1;
 290       unsigned int cpuavx512er:1;
 291       unsigned int cpuavx512pf:1;
 292       unsigned int cpuavx512vl:1;
 293       unsigned int cpuavx512dq:1;
 294       unsigned int cpuavx512bw:1;
 295       unsigned int cpul1om:1;
 296       unsigned int cpuk1om:1;
 297       unsigned int cpuiamcu:1;
 298       unsigned int cpuxsave:1;
 299       unsigned int cpuxsaveopt:1;
 300       unsigned int cpuaes:1;
 301       unsigned int cpupclmul:1;
 302       unsigned int cpufma:1;
 303       unsigned int cpufma4:1;
 304       unsigned int cpuxop:1;
 305       unsigned int cpulwp:1;
 306       unsigned int cpubmi:1;
 307       unsigned int cputbm:1;
 308       unsigned int cpumovbe:1;
 309       unsigned int cpucx16:1;
 310       unsigned int cpuept:1;
 311       unsigned int cpurdtscp:1;
 312       unsigned int cpufsgsbase:1;
 313       unsigned int cpurdrnd:1;
 314       unsigned int cpuf16c:1;
 315       unsigned int cpubmi2:1;
 316       unsigned int cpulzcnt:1;
 317       unsigned int cpuhle:1;
 318       unsigned int cpurtm:1;
 319       unsigned int cpuinvpcid:1;
 320       unsigned int cpuvmfunc:1;
 321       unsigned int cpumpx:1;
 322       unsigned int cpulm:1;
 323       unsigned int cpurdseed:1;
 324       unsigned int cpuadx:1;
 325       unsigned int cpuprfchw:1;
 326       unsigned int cpusmap:1;
 327       unsigned int cpusha:1;
 328       unsigned int cpuvrex:1;
 329       unsigned int cpuclflushopt:1;
 330       unsigned int cpuxsaves:1;
 331       unsigned int cpuxsavec:1;
 332       unsigned int cpuprefetchwt1:1;
 333       unsigned int cpuse1:1;
 334       unsigned int cpuclwb:1;
 335       unsigned int cpuavx512ifma:1;
 336       unsigned int cpuavx512vbmi:1;
 337       unsigned int cpuavx512_4fmaps:1;
 338       unsigned int cpuavx512_4vnniw:1;
 339       unsigned int cpuavx512_vpopcntdq:1;
 340       unsigned int cpuavx512_vbmi2:1;
 341       unsigned int cpuavx512_vnni:1;
 342       unsigned int cpuavx512_bitalg:1;
 343       unsigned int cpumwaitx:1;
 344       unsigned int cpuclzero:1;
 345       unsigned int cpuospke:1;
 346       unsigned int cpurdpid:1;
 347       unsigned int cpuptwrite:1;
 348       unsigned int cpuibt:1;
 349       unsigned int cpushstk:1;
 350       unsigned int cpugfni:1;
 351       unsigned int cpuvaes:1;
 352       unsigned int cpuvpclmulqdq:1;
 353       unsigned int cpuwbnoinvd:1;
 354       unsigned int cpupconfig:1;
 355       unsigned int cpuwaitpkg:1;
 356       unsigned int cpucldemote:1;
 357       unsigned int cpu64:1;
 358       unsigned int cpuno64:1;
 359 #ifdef CpuUnused
 360       unsigned int unused:(CpuNumOfBits - CpuUnused);
 361 #endif
 362     } bitfield;
 363   unsigned int array[CpuNumOfUints];
 364 } i386_cpu_flags;
 365
 366 /* Position of opcode_modifier bits.  */
 367
 368 enum
 369 {
 370   /* has direction bit. */
 371   D = 0,
 372   /* set if operands can be words or dwords encoded the canonical way */
 373   W,
 374   /* load form instruction. Must be placed before store form.  */
 375   Load,
 376   /* insn has a modrm byte. */
 377   Modrm,
 378   /* register is in low 3 bits of opcode */
 379   ShortForm,
 380   /* special case for jump insns.  */
 381   Jump,
 382   /* call and jump */
 383   JumpDword,
 384   /* loop and jecxz */
 385   JumpByte,
 386   /* special case for intersegment leaps/calls */
 387   JumpInterSegment,
 388   /* FP insn memory format bit, sized by 0x4 */
 389   FloatMF,
 390   /* src/dest swap for floats. */
 391   FloatR,
 392   /* needs size prefix if in 32-bit mode */
 393   Size16,
 394   /* needs size prefix if in 16-bit mode */
 395   Size32,
 396   /* needs size prefix if in 64-bit mode */
 397   Size64,
 398   /* check register size.  */
 399   CheckRegSize,
 400   /* instruction ignores operand size prefix and in Intel mode ignores
 401      mnemonic size suffix check.  */
 402   IgnoreSize,
 403   /* default insn size depends on mode */
 404   DefaultSize,
 405   /* b suffix on instruction illegal */
 406   No_bSuf,
 407   /* w suffix on instruction illegal */
 408   No_wSuf,
 409   /* l suffix on instruction illegal */
 410   No_lSuf,
 411   /* s suffix on instruction illegal */
 412   No_sSuf,
 413   /* q suffix on instruction illegal */
 414   No_qSuf,
 415   /* long double suffix on instruction illegal */
 416   No_ldSuf,
 417   /* instruction needs FWAIT */
 418   FWait,
 419   /* quick test for string instructions */
 420   IsString,
 421   /* quick test if branch instruction is MPX supported */
 422   BNDPrefixOk,
 423   /* quick test if NOTRACK prefix is supported */
 424   NoTrackPrefixOk,
 425   /* quick test for lockable instructions */
 426   IsLockable,
 427   /* fake an extra reg operand for clr, imul and special register
 428      processing for some instructions.  */
 429   RegKludge,
 430   /* An implicit xmm0 as the first operand */
 431   Implicit1stXmm0,
 432   /* The HLE prefix is OK:
 433      1. With a LOCK prefix.
 434      2. With or without a LOCK prefix.
 435      3. With a RELEASE (0xf3) prefix.
 436    */
 437 #define HLEPrefixNone           0
 438 #define HLEPrefixLock           1
 439 #define HLEPrefixAny            2
 440 #define HLEPrefixRelease        3
 441   HLEPrefixOk,
 442   /* An instruction on which a "rep" prefix is acceptable.  */
 443   RepPrefixOk,
 444   /* Convert to DWORD */
 445   ToDword,
 446   /* Convert to QWORD */
 447   ToQword,
 448   /* Address prefix changes register operand */
 449   AddrPrefixOpReg,
 450   /* opcode is a prefix */
 451   IsPrefix,
 452   /* instruction has extension in 8 bit imm */
 453   ImmExt,
 454   /* instruction don't need Rex64 prefix.  */
 455   NoRex64,
 456   /* instruction require Rex64 prefix.  */
 457   Rex64,
 458   /* deprecated fp insn, gets a warning */
 459   Ugh,
 460   /* insn has VEX prefix:
 461         1: 128bit VEX prefix (or operand dependent).
 462         2: 256bit VEX prefix.
 463         3: Scalar VEX prefix.
 464    */
 465 #define VEX128          1
 466 #define VEX256          2
 467 #define VEXScalar       3
 468   Vex,
 469   /* How to encode VEX.vvvv:
 470      0: VEX.vvvv must be 1111b.
 471      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 472         the content of source registers will be preserved.
 473         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 474         where the content of first source register will be overwritten
 475         by the result.
 476         VEX.NDD2.  The second destination register operand is encoded in
 477         VEX.vvvv for instructions with 2 destination register operands.
 478         For assembler, there are no difference between VEX.NDS, VEX.DDS
 479         and VEX.NDD2.
 480      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 481      instructions with 1 destination register operand.
 482      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 483         of the operands can access a memory location.
 484    */
 485 #define VEXXDS  1
 486 #define VEXNDD  2
 487 #define VEXLWP  3
 488   VexVVVV,
 489   /* How the VEX.W bit is used:
 490      0: Set by the REX.W bit.
 491      1: VEX.W0.  Should always be 0.
 492      2: VEX.W1.  Should always be 1.
 493    */
 494 #define VEXW0   1
 495 #define VEXW1   2
 496   VexW,
 497   /* VEX opcode prefix:
 498      0: VEX 0x0F opcode prefix.
 499      1: VEX 0x0F38 opcode prefix.
 500      2: VEX 0x0F3A opcode prefix
 501      3: XOP 0x08 opcode prefix.
 502      4: XOP 0x09 opcode prefix
 503      5: XOP 0x0A opcode prefix.
 504    */
 505 #define VEX0F           0
 506 #define VEX0F38         1
 507 #define VEX0F3A         2
 508 #define XOP08           3
 509 #define XOP09           4
 510 #define XOP0A           5
 511   VexOpcode,
 512   /* number of VEX source operands:
 513      0: <= 2 source operands.
 514      1: 2 XOP source operands.
 515      2: 3 source operands.
 516    */
 517 #define XOP2SOURCES     1
 518 #define VEX3SOURCES     2
 519   VexSources,
 520   /* Instruction with vector SIB byte:
 521         1: 128bit vector register.
 522         2: 256bit vector register.
 523         3: 512bit vector register.
 524    */
 525 #define VecSIB128       1
 526 #define VecSIB256       2
 527 #define VecSIB512       3
 528   VecSIB,
 529   /* SSE to AVX support required */
 530   SSE2AVX,
 531   /* No AVX equivalent */
 532   NoAVX,
 533
 534   /* insn has EVEX prefix:
 535         1: 512bit EVEX prefix.
 536         2: 128bit EVEX prefix.
 537         3: 256bit EVEX prefix.
 538         4: Length-ignored (LIG) EVEX prefix.
 539         5: Length determined from actual operands.
 540    */
 541 #define EVEX512                1
 542 #define EVEX128                2
 543 #define EVEX256                3
 544 #define EVEXLIG                4
 545 #define EVEXDYN                5
 546   EVex,
 547
 548   /* AVX512 masking support:
 549         1: Zeroing-masking.
 550         2: Merging-masking.
 551         3: Both zeroing and merging masking.
 552    */
 553 #define ZEROING_MASKING 1
 554 #define MERGING_MASKING 2
 555 #define BOTH_MASKING    3
 556   Masking,
 557
 558   Broadcast,
 559
 560   /* Static rounding control is supported.  */
 561   StaticRounding,
 562
 563   /* Supress All Exceptions is supported.  */
 564   SAE,
 565
 566   /* Copressed Disp8*N attribute.  */
 567   Disp8MemShift,
 568
 569   /* Default mask isn't allowed.  */
 570   NoDefMask,
 571
 572   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 573      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 574    */
 575   ImplicitQuadGroup,
 576
 577   /* Support encoding optimization.  */
 578   Optimize,
 579
 580   /* AT&T mnemonic.  */
 581   ATTMnemonic,
 582   /* AT&T syntax.  */
 583   ATTSyntax,
 584   /* Intel syntax.  */
 585   IntelSyntax,
 586   /* AMD64.  */
 587   AMD64,
 588   /* Intel64.  */
 589   Intel64,
 590   /* The last bitfield in i386_opcode_modifier.  */
 591   Opcode_Modifier_Max
 592 };
 593
 594 typedef struct i386_opcode_modifier
 595 {
 596   unsigned int d:1;
 597   unsigned int w:1;
 598   unsigned int load:1;
 599   unsigned int modrm:1;
 600   unsigned int shortform:1;
 601   unsigned int jump:1;
 602   unsigned int jumpdword:1;
 603   unsigned int jumpbyte:1;
 604   unsigned int jumpintersegment:1;
 605   unsigned int floatmf:1;
 606   unsigned int floatr:1;
 607   unsigned int size16:1;
 608   unsigned int size32:1;
 609   unsigned int size64:1;
 610   unsigned int checkregsize:1;
 611   unsigned int ignoresize:1;
 612   unsigned int defaultsize:1;
 613   unsigned int no_bsuf:1;
 614   unsigned int no_wsuf:1;
 615   unsigned int no_lsuf:1;
 616   unsigned int no_ssuf:1;
 617   unsigned int no_qsuf:1;
 618   unsigned int no_ldsuf:1;
 619   unsigned int fwait:1;
 620   unsigned int isstring:1;
 621   unsigned int bndprefixok:1;
 622   unsigned int notrackprefixok:1;
 623   unsigned int islockable:1;
 624   unsigned int regkludge:1;
 625   unsigned int implicit1stxmm0:1;
 626   unsigned int hleprefixok:2;
 627   unsigned int repprefixok:1;
 628   unsigned int todword:1;
 629   unsigned int toqword:1;
 630   unsigned int addrprefixopreg:1;
 631   unsigned int isprefix:1;
 632   unsigned int immext:1;
 633   unsigned int norex64:1;
 634   unsigned int rex64:1;
 635   unsigned int ugh:1;
 636   unsigned int vex:2;
 637   unsigned int vexvvvv:2;
 638   unsigned int vexw:2;
 639   unsigned int vexopcode:3;
 640   unsigned int vexsources:2;
 641   unsigned int vecsib:2;
 642   unsigned int sse2avx:1;
 643   unsigned int noavx:1;
 644   unsigned int evex:3;
 645   unsigned int masking:2;
 646   unsigned int broadcast:1;
 647   unsigned int staticrounding:1;
 648   unsigned int sae:1;
 649   unsigned int disp8memshift:3;
 650   unsigned int nodefmask:1;
 651   unsigned int implicitquadgroup:1;
 652   unsigned int optimize:1;
 653   unsigned int attmnemonic:1;
 654   unsigned int attsyntax:1;
 655   unsigned int intelsyntax:1;
 656   unsigned int amd64:1;
 657   unsigned int intel64:1;
 658 } i386_opcode_modifier;
 659
 660 /* Position of operand_type bits.  */
 661
 662 enum
 663 {
 664   /* Register (qualified by Byte, Word, etc) */
 665   Reg = 0,
 666   /* MMX register */
 667   RegMMX,
 668   /* Vector registers */
 669   RegSIMD,
 670   /* Vector Mask registers */
 671   RegMask,
 672   /* Control register */
 673   Control,
 674   /* Debug register */
 675   Debug,
 676   /* Test register */
 677   Test,
 678   /* 2 bit segment register */
 679   SReg2,
 680   /* 3 bit segment register */
 681   SReg3,
 682   /* 1 bit immediate */
 683   Imm1,
 684   /* 8 bit immediate */
 685   Imm8,
 686   /* 8 bit immediate sign extended */
 687   Imm8S,
 688   /* 16 bit immediate */
 689   Imm16,
 690   /* 32 bit immediate */
 691   Imm32,
 692   /* 32 bit immediate sign extended */
 693   Imm32S,
 694   /* 64 bit immediate */
 695   Imm64,
 696   /* 8bit/16bit/32bit displacements are used in different ways,
 697      depending on the instruction.  For jumps, they specify the
 698      size of the PC relative displacement, for instructions with
 699      memory operand, they specify the size of the offset relative
 700      to the base register, and for instructions with memory offset
 701      such as `mov 1234,%al' they specify the size of the offset
 702      relative to the segment base.  */
 703   /* 8 bit displacement */
 704   Disp8,
 705   /* 16 bit displacement */
 706   Disp16,
 707   /* 32 bit displacement */
 708   Disp32,
 709   /* 32 bit signed displacement */
 710   Disp32S,
 711   /* 64 bit displacement */
 712   Disp64,
 713   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 714   Acc,
 715   /* Register which can be used for base or index in memory operand.  */
 716   BaseIndex,
 717   /* Register to hold in/out port addr = dx */
 718   InOutPortReg,
 719   /* Register to hold shift count = cl */
 720   ShiftCount,
 721   /* Absolute address for jump.  */
 722   JumpAbsolute,
 723   /* String insn operand with fixed es segment */
 724   EsSeg,
 725   /* RegMem is for instructions with a modrm byte where the register
 726      destination operand should be encoded in the mod and regmem fields.
 727      Normally, it will be encoded in the reg field. We add a RegMem
 728      flag to the destination register operand to indicate that it should
 729      be encoded in the regmem field.  */
 730   RegMem,
 731   /* Memory.  */
 732   Mem,
 733   /* BYTE memory. */
 734   Byte,
 735   /* WORD memory. 2 byte */
 736   Word,
 737   /* DWORD memory. 4 byte */
 738   Dword,
 739   /* FWORD memory. 6 byte */
 740   Fword,
 741   /* QWORD memory. 8 byte */
 742   Qword,
 743   /* TBYTE memory. 10 byte */
 744   Tbyte,
 745   /* XMMWORD memory. */
 746   Xmmword,
 747   /* YMMWORD memory. */
 748   Ymmword,
 749   /* ZMMWORD memory.  */
 750   Zmmword,
 751   /* Unspecified memory size.  */
 752   Unspecified,
 753   /* Any memory size.  */
 754   Anysize,
 755
 756   /* Vector 4 bit immediate.  */
 757   Vec_Imm4,
 758
 759   /* Bound register.  */
 760   RegBND,
 761
 762   /* The last bitfield in i386_operand_type.  */
 763   OTMax
 764 };
 765
 766 #define OTNumOfUints \
 767   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 768 #define OTNumOfBits \
 769   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 770
 771 /* If you get a compiler error for zero width of the unused field,
 772    comment it out.  */
 773 #define OTUnused                (OTMax + 1)
 774
 775 typedef union i386_operand_type
 776 {
 777   struct
 778     {
 779       unsigned int reg:1;
 780       unsigned int regmmx:1;
 781       unsigned int regsimd:1;
 782       unsigned int regmask:1;
 783       unsigned int control:1;
 784       unsigned int debug:1;
 785       unsigned int test:1;
 786       unsigned int sreg2:1;
 787       unsigned int sreg3:1;
 788       unsigned int imm1:1;
 789       unsigned int imm8:1;
 790       unsigned int imm8s:1;
 791       unsigned int imm16:1;
 792       unsigned int imm32:1;
 793       unsigned int imm32s:1;
 794       unsigned int imm64:1;
 795       unsigned int disp8:1;
 796       unsigned int disp16:1;
 797       unsigned int disp32:1;
 798       unsigned int disp32s:1;
 799       unsigned int disp64:1;
 800       unsigned int acc:1;
 801       unsigned int baseindex:1;
 802       unsigned int inoutportreg:1;
 803       unsigned int shiftcount:1;
 804       unsigned int jumpabsolute:1;
 805       unsigned int esseg:1;
 806       unsigned int regmem:1;
 807       unsigned int mem:1;
 808       unsigned int byte:1;
 809       unsigned int word:1;
 810       unsigned int dword:1;
 811       unsigned int fword:1;
 812       unsigned int qword:1;
 813       unsigned int tbyte:1;
 814       unsigned int xmmword:1;
 815       unsigned int ymmword:1;
 816       unsigned int zmmword:1;
 817       unsigned int unspecified:1;
 818       unsigned int anysize:1;
 819       unsigned int vec_imm4:1;
 820       unsigned int regbnd:1;
 821 #ifdef OTUnused
 822       unsigned int unused:(OTNumOfBits - OTUnused);
 823 #endif
 824     } bitfield;
 825   unsigned int array[OTNumOfUints];
 826 } i386_operand_type;
 827
 828 typedef struct insn_template
 829 {
 830   /* instruction name sans width suffix ("mov" for movl insns) */
 831   char *name;
 832
 833   /* how many operands */
 834   unsigned int operands;
 835
 836   /* base_opcode is the fundamental opcode byte without optional
 837      prefix(es).  */
 838   unsigned int base_opcode;
 839 #define Opcode_D        0x2 /* Direction bit:
 840                                set if Reg --> Regmem;
 841                                unset if Regmem --> Reg. */
 842 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 843 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 844
 845   /* extension_opcode is the 3 bit extension for group <n> insns.
 846      This field is also used to store the 8-bit opcode suffix for the
 847      AMD 3DNow! instructions.
 848      If this template has no extension opcode (the usual case) use None
 849      Instructions */
 850   unsigned int extension_opcode;
 851 #define None 0xffff             /* If no extension_opcode is possible.  */
 852
 853   /* Opcode length.  */
 854   unsigned char opcode_length;
 855
 856   /* cpu feature flags */
 857   i386_cpu_flags cpu_flags;
 858
 859   /* the bits in opcode_modifier are used to generate the final opcode from
 860      the base_opcode.  These bits also are used to detect alternate forms of
 861      the same instruction */
 862   i386_opcode_modifier opcode_modifier;
 863
 864   /* operand_types[i] describes the type of operand i.  This is made
 865      by OR'ing together all of the possible type masks.  (e.g.
 866      'operand_types[i] = Reg|Imm' specifies that operand i can be
 867      either a register or an immediate operand.  */
 868   i386_operand_type operand_types[MAX_OPERANDS];
 869 }
 870 insn_template;
 871
 872 extern const insn_template i386_optab[];
 873
 874 /* these are for register name --> number & type hash lookup */
 875 typedef struct
 876 {
 877   char *reg_name;
 878   i386_operand_type reg_type;
 879   unsigned char reg_flags;
 880 #define RegRex      0x1  /* Extended register.  */
 881 #define RegRex64    0x2  /* Extended 8 bit register.  */
 882 #define RegVRex     0x4  /* Extended vector register.  */
 883   unsigned char reg_num;
 884 #define RegRip  ((unsigned char ) ~0)
 885 #define RegEip  (RegRip - 1)
 886 /* EIZ and RIZ are fake index registers.  */
 887 #define RegEiz  (RegEip - 1)
 888 #define RegRiz  (RegEiz - 1)
 889 /* FLAT is a fake segment register (Intel mode).  */
 890 #define RegFlat     ((unsigned char) ~0)
 891   signed char dw2_regnum[2];
 892 #define Dw2Inval (-1)
 893 }
 894 reg_entry;
 895
 896 /* Entries in i386_regtab.  */
 897 #define REGNAM_AL 1
 898 #define REGNAM_AX 25
 899 #define REGNAM_EAX 41
 900
 901 extern const reg_entry i386_regtab[];
 902 extern const unsigned int i386_regtab_size;
 903
 904 typedef struct
 905 {
 906   char *seg_name;
 907   unsigned int seg_prefix;
 908 }
 909 seg_entry;
 910
 911 extern const seg_entry cs;
 912 extern const seg_entry ds;
 913 extern const seg_entry ss;
 914 extern const seg_entry es;
 915 extern const seg_entry fs;
 916 extern const seg_entry gs;