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[thirdparty/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23 #include "sysdep.h"
24 #include "dis-asm.h"
25 #include "libiberty.h"
26 #include "opcode/mips.h"
27 #include "opintl.h"
28
29 /* FIXME: These are needed to figure out if the code is mips16 or
30 not. The low bit of the address is often a good indicator. No
31 symbol table is available when this code runs out in an embedded
32 system as when it is used for disassembler support in a monitor. */
33
34 #if !defined(EMBEDDED_ENV)
35 #define SYMTAB_AVAILABLE 1
36 #include "elf-bfd.h"
37 #include "elf/mips.h"
38 #endif
39
40 /* Mips instructions are at maximum this many bytes long. */
41 #define INSNLEN 4
42
43 static void set_default_mips_dis_options
44 PARAMS ((struct disassemble_info *));
45 static void parse_mips_dis_option
46 PARAMS ((const char *, unsigned int));
47 static void parse_mips_dis_options
48 PARAMS ((const char *));
49 static int _print_insn_mips
50 PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
51 static int print_insn_mips
52 PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
53 static void print_insn_args
54 PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
55 static int print_insn_mips16
56 PARAMS ((bfd_vma, struct disassemble_info *));
57 static int is_newabi
58 PARAMS ((Elf_Internal_Ehdr *));
59 static void print_mips16_insn_arg
60 PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
61 struct disassemble_info *));
62 \f
63 /* FIXME: These should be shared with gdb somehow. */
64
65 struct mips_cp0sel_name {
66 unsigned int cp0reg;
67 unsigned int sel;
68 const char * const name;
69 };
70
71 /* The mips16 register names. */
72 static const char * const mips16_reg_names[] = {
73 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
74 };
75
76 static const char * const mips_gpr_names_numeric[32] = {
77 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
78 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
79 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
80 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
81 };
82
83 static const char * const mips_gpr_names_oldabi[32] = {
84 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
85 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
86 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
87 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
88 };
89
90 static const char * const mips_gpr_names_newabi[32] = {
91 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
92 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
93 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
94 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
95 };
96
97 static const char * const mips_fpr_names_numeric[32] = {
98 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
99 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
100 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
101 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
102 };
103
104 static const char * const mips_fpr_names_32[32] = {
105 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
106 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
107 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
108 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
109 };
110
111 static const char * const mips_fpr_names_n32[32] = {
112 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
113 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
114 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
115 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
116 };
117
118 static const char * const mips_fpr_names_64[32] = {
119 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
120 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
121 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
122 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
123 };
124
125 static const char * const mips_cp0_names_numeric[32] = {
126 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
127 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
128 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
129 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
130 };
131
132 static const char * const mips_cp0_names_mips3264[32] = {
133 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
134 "c0_context", "c0_pagemask", "c0_wired", "$7",
135 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
136 "c0_status", "c0_cause", "c0_epc", "c0_prid",
137 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
138 "c0_xcontext", "$21", "$22", "c0_debug",
139 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
140 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
141 };
142
143 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
144 { 16, 1, "c0_config1" },
145 { 16, 2, "c0_config2" },
146 { 16, 3, "c0_config3" },
147 { 18, 1, "c0_watchlo,1" },
148 { 18, 2, "c0_watchlo,2" },
149 { 18, 3, "c0_watchlo,3" },
150 { 18, 4, "c0_watchlo,4" },
151 { 18, 5, "c0_watchlo,5" },
152 { 18, 6, "c0_watchlo,6" },
153 { 18, 7, "c0_watchlo,7" },
154 { 19, 1, "c0_watchhi,1" },
155 { 19, 2, "c0_watchhi,2" },
156 { 19, 3, "c0_watchhi,3" },
157 { 19, 4, "c0_watchhi,4" },
158 { 19, 5, "c0_watchhi,5" },
159 { 19, 6, "c0_watchhi,6" },
160 { 19, 7, "c0_watchhi,7" },
161 { 25, 1, "c0_perfcnt,1" },
162 { 25, 2, "c0_perfcnt,2" },
163 { 25, 3, "c0_perfcnt,3" },
164 { 25, 4, "c0_perfcnt,4" },
165 { 25, 5, "c0_perfcnt,5" },
166 { 25, 6, "c0_perfcnt,6" },
167 { 25, 7, "c0_perfcnt,7" },
168 { 27, 1, "c0_cacheerr,1" },
169 { 27, 2, "c0_cacheerr,2" },
170 { 27, 3, "c0_cacheerr,3" },
171 { 28, 1, "c0_datalo" },
172 { 29, 1, "c0_datahi" }
173 };
174
175 static const char * const mips_cp0_names_mips3264r2[32] = {
176 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
177 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
178 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
179 "c0_status", "c0_cause", "c0_epc", "c0_prid",
180 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
181 "c0_xcontext", "$21", "$22", "c0_debug",
182 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
183 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
184 };
185
186 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
187 { 4, 1, "c0_contextconfig" },
188 { 5, 1, "c0_pagegrain" },
189 { 12, 1, "c0_intctl" },
190 { 12, 2, "c0_srsctl" },
191 { 12, 3, "c0_srsmap" },
192 { 15, 1, "c0_ebase" },
193 { 16, 1, "c0_config1" },
194 { 16, 2, "c0_config2" },
195 { 16, 3, "c0_config3" },
196 { 18, 1, "c0_watchlo,1" },
197 { 18, 2, "c0_watchlo,2" },
198 { 18, 3, "c0_watchlo,3" },
199 { 18, 4, "c0_watchlo,4" },
200 { 18, 5, "c0_watchlo,5" },
201 { 18, 6, "c0_watchlo,6" },
202 { 18, 7, "c0_watchlo,7" },
203 { 19, 1, "c0_watchhi,1" },
204 { 19, 2, "c0_watchhi,2" },
205 { 19, 3, "c0_watchhi,3" },
206 { 19, 4, "c0_watchhi,4" },
207 { 19, 5, "c0_watchhi,5" },
208 { 19, 6, "c0_watchhi,6" },
209 { 19, 7, "c0_watchhi,7" },
210 { 23, 1, "c0_tracecontrol" },
211 { 23, 2, "c0_tracecontrol2" },
212 { 23, 3, "c0_usertracedata" },
213 { 23, 4, "c0_tracebpc" },
214 { 25, 1, "c0_perfcnt,1" },
215 { 25, 2, "c0_perfcnt,2" },
216 { 25, 3, "c0_perfcnt,3" },
217 { 25, 4, "c0_perfcnt,4" },
218 { 25, 5, "c0_perfcnt,5" },
219 { 25, 6, "c0_perfcnt,6" },
220 { 25, 7, "c0_perfcnt,7" },
221 { 27, 1, "c0_cacheerr,1" },
222 { 27, 2, "c0_cacheerr,2" },
223 { 27, 3, "c0_cacheerr,3" },
224 { 28, 1, "c0_datalo" },
225 { 28, 2, "c0_taglo1" },
226 { 28, 3, "c0_datalo1" },
227 { 28, 4, "c0_taglo2" },
228 { 28, 5, "c0_datalo2" },
229 { 28, 6, "c0_taglo3" },
230 { 28, 7, "c0_datalo3" },
231 { 29, 1, "c0_datahi" },
232 { 29, 2, "c0_taghi1" },
233 { 29, 3, "c0_datahi1" },
234 { 29, 4, "c0_taghi2" },
235 { 29, 5, "c0_datahi2" },
236 { 29, 6, "c0_taghi3" },
237 { 29, 7, "c0_datahi3" },
238 };
239
240 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
241 static const char * const mips_cp0_names_sb1[32] = {
242 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
243 "c0_context", "c0_pagemask", "c0_wired", "$7",
244 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
245 "c0_status", "c0_cause", "c0_epc", "c0_prid",
246 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
247 "c0_xcontext", "$21", "$22", "c0_debug",
248 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
249 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
250 };
251
252 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
253 { 16, 1, "c0_config1" },
254 { 18, 1, "c0_watchlo,1" },
255 { 19, 1, "c0_watchhi,1" },
256 { 22, 0, "c0_perftrace" },
257 { 23, 3, "c0_edebug" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 26, 1, "c0_buserr_pa" },
266 { 27, 1, "c0_cacheerr_d" },
267 { 27, 3, "c0_cacheerr_d_pa" },
268 { 28, 1, "c0_datalo_i" },
269 { 28, 2, "c0_taglo_d" },
270 { 28, 3, "c0_datalo_d" },
271 { 29, 1, "c0_datahi_i" },
272 { 29, 2, "c0_taghi_d" },
273 { 29, 3, "c0_datahi_d" },
274 };
275
276 static const char * const mips_hwr_names_numeric[32] = {
277 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
278 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
279 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
280 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
281 };
282
283 static const char * const mips_hwr_names_mips3264r2[32] = {
284 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
285 "$4", "$5", "$6", "$7",
286 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
287 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
288 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
289 };
290
291 struct mips_abi_choice {
292 const char *name;
293 const char * const *gpr_names;
294 const char * const *fpr_names;
295 };
296
297 struct mips_abi_choice mips_abi_choices[] = {
298 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
299 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
300 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
301 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
302 };
303
304 struct mips_arch_choice {
305 const char *name;
306 int bfd_mach_valid;
307 unsigned long bfd_mach;
308 int processor;
309 int isa;
310 const char * const *cp0_names;
311 const struct mips_cp0sel_name *cp0sel_names;
312 unsigned int cp0sel_names_len;
313 const char * const *hwr_names;
314 };
315
316 const struct mips_arch_choice mips_arch_choices[] = {
317 { "numeric", 0, 0, 0, 0,
318 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
319
320 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
321 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
322 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
323 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
324 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
326 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
327 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
328 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
329 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
330 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
331 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
332 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
333 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
334 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
335 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
336 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
337 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
338 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
339 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
340 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
341 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
342 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
343 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
344 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
345 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
346 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
347 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
348 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362
363 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
364 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
365 _MIPS32 Architecture For Programmers Volume I: Introduction to the
366 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
367 page 1. */
368 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
369 ISA_MIPS32 | INSN_MIPS16,
370 mips_cp0_names_mips3264,
371 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
372 mips_hwr_names_numeric },
373
374 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
375 ISA_MIPS32R2 | INSN_MIPS16,
376 mips_cp0_names_mips3264r2,
377 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
378 mips_hwr_names_mips3264r2 },
379
380 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
381 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
382 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
383 mips_cp0_names_mips3264,
384 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
385 mips_hwr_names_numeric },
386
387 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
388 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
389 mips_cp0_names_sb1,
390 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
391 mips_hwr_names_numeric },
392
393 /* This entry, mips16, is here only for ISA/processor selection; do
394 not print its name. */
395 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
396 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
397 };
398
399 /* ISA and processor type to disassemble for, and register names to use.
400 set_default_mips_dis_options and parse_mips_dis_options fill in these
401 values. */
402 static int mips_processor;
403 static int mips_isa;
404 static const char * const *mips_gpr_names;
405 static const char * const *mips_fpr_names;
406 static const char * const *mips_cp0_names;
407 static const struct mips_cp0sel_name *mips_cp0sel_names;
408 static int mips_cp0sel_names_len;
409 static const char * const *mips_hwr_names;
410
411 static const struct mips_abi_choice *choose_abi_by_name
412 PARAMS ((const char *, unsigned int));
413 static const struct mips_arch_choice *choose_arch_by_name
414 PARAMS ((const char *, unsigned int));
415 static const struct mips_arch_choice *choose_arch_by_number
416 PARAMS ((unsigned long));
417 static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
418 PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
419 unsigned int));
420 \f
421 static const struct mips_abi_choice *
422 choose_abi_by_name (name, namelen)
423 const char *name;
424 unsigned int namelen;
425 {
426 const struct mips_abi_choice *c;
427 unsigned int i;
428
429 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
430 {
431 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
432 && strlen (mips_abi_choices[i].name) == namelen)
433 c = &mips_abi_choices[i];
434 }
435 return c;
436 }
437
438 static const struct mips_arch_choice *
439 choose_arch_by_name (name, namelen)
440 const char *name;
441 unsigned int namelen;
442 {
443 const struct mips_arch_choice *c = NULL;
444 unsigned int i;
445
446 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
447 {
448 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
449 && strlen (mips_arch_choices[i].name) == namelen)
450 c = &mips_arch_choices[i];
451 }
452 return c;
453 }
454
455 static const struct mips_arch_choice *
456 choose_arch_by_number (mach)
457 unsigned long mach;
458 {
459 static unsigned long hint_bfd_mach;
460 static const struct mips_arch_choice *hint_arch_choice;
461 const struct mips_arch_choice *c;
462 unsigned int i;
463
464 /* We optimize this because even if the user specifies no
465 flags, this will be done for every instruction! */
466 if (hint_bfd_mach == mach
467 && hint_arch_choice != NULL
468 && hint_arch_choice->bfd_mach == hint_bfd_mach)
469 return hint_arch_choice;
470
471 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
472 {
473 if (mips_arch_choices[i].bfd_mach_valid
474 && mips_arch_choices[i].bfd_mach == mach)
475 {
476 c = &mips_arch_choices[i];
477 hint_bfd_mach = mach;
478 hint_arch_choice = c;
479 }
480 }
481 return c;
482 }
483
484 void
485 set_default_mips_dis_options (info)
486 struct disassemble_info *info;
487 {
488 const struct mips_arch_choice *chosen_arch;
489
490 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
491 and numeric FPR, CP0 register, and HWR names. */
492 mips_isa = ISA_MIPS3;
493 mips_processor = CPU_R3000;
494 mips_gpr_names = mips_gpr_names_oldabi;
495 mips_fpr_names = mips_fpr_names_numeric;
496 mips_cp0_names = mips_cp0_names_numeric;
497 mips_cp0sel_names = NULL;
498 mips_cp0sel_names_len = 0;
499 mips_hwr_names = mips_hwr_names_numeric;
500
501 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
502 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
503 {
504 Elf_Internal_Ehdr *header;
505
506 header = elf_elfheader (info->section->owner);
507 if (is_newabi (header))
508 mips_gpr_names = mips_gpr_names_newabi;
509 }
510
511 /* Set ISA, architecture, and cp0 register names as best we can. */
512 #if ! SYMTAB_AVAILABLE
513 /* This is running out on a target machine, not in a host tool.
514 FIXME: Where does mips_target_info come from? */
515 target_processor = mips_target_info.processor;
516 mips_isa = mips_target_info.isa;
517 #else
518 chosen_arch = choose_arch_by_number (info->mach);
519 if (chosen_arch != NULL)
520 {
521 mips_processor = chosen_arch->processor;
522 mips_isa = chosen_arch->isa;
523 mips_cp0_names = chosen_arch->cp0_names;
524 mips_cp0sel_names = chosen_arch->cp0sel_names;
525 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
526 mips_hwr_names = chosen_arch->hwr_names;
527 }
528 #endif
529 }
530
531 void
532 parse_mips_dis_option (option, len)
533 const char *option;
534 unsigned int len;
535 {
536 unsigned int i, optionlen, vallen;
537 const char *val;
538 const struct mips_abi_choice *chosen_abi;
539 const struct mips_arch_choice *chosen_arch;
540
541 /* Look for the = that delimits the end of the option name. */
542 for (i = 0; i < len; i++)
543 {
544 if (option[i] == '=')
545 break;
546 }
547 if (i == 0) /* Invalid option: no name before '='. */
548 return;
549 if (i == len) /* Invalid option: no '='. */
550 return;
551 if (i == (len - 1)) /* Invalid option: no value after '='. */
552 return;
553
554 optionlen = i;
555 val = option + (optionlen + 1);
556 vallen = len - (optionlen + 1);
557
558 if (strncmp("gpr-names", option, optionlen) == 0
559 && strlen("gpr-names") == optionlen)
560 {
561 chosen_abi = choose_abi_by_name (val, vallen);
562 if (chosen_abi != NULL)
563 mips_gpr_names = chosen_abi->gpr_names;
564 return;
565 }
566
567 if (strncmp("fpr-names", option, optionlen) == 0
568 && strlen("fpr-names") == optionlen)
569 {
570 chosen_abi = choose_abi_by_name (val, vallen);
571 if (chosen_abi != NULL)
572 mips_fpr_names = chosen_abi->fpr_names;
573 return;
574 }
575
576 if (strncmp("cp0-names", option, optionlen) == 0
577 && strlen("cp0-names") == optionlen)
578 {
579 chosen_arch = choose_arch_by_name (val, vallen);
580 if (chosen_arch != NULL)
581 {
582 mips_cp0_names = chosen_arch->cp0_names;
583 mips_cp0sel_names = chosen_arch->cp0sel_names;
584 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
585 }
586 return;
587 }
588
589 if (strncmp("hwr-names", option, optionlen) == 0
590 && strlen("hwr-names") == optionlen)
591 {
592 chosen_arch = choose_arch_by_name (val, vallen);
593 if (chosen_arch != NULL)
594 mips_hwr_names = chosen_arch->hwr_names;
595 return;
596 }
597
598 if (strncmp("reg-names", option, optionlen) == 0
599 && strlen("reg-names") == optionlen)
600 {
601 /* We check both ABI and ARCH here unconditionally, so
602 that "numeric" will do the desirable thing: select
603 numeric register names for all registers. Other than
604 that, a given name probably won't match both. */
605 chosen_abi = choose_abi_by_name (val, vallen);
606 if (chosen_abi != NULL)
607 {
608 mips_gpr_names = chosen_abi->gpr_names;
609 mips_fpr_names = chosen_abi->fpr_names;
610 }
611 chosen_arch = choose_arch_by_name (val, vallen);
612 if (chosen_arch != NULL)
613 {
614 mips_cp0_names = chosen_arch->cp0_names;
615 mips_cp0sel_names = chosen_arch->cp0sel_names;
616 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
617 mips_hwr_names = chosen_arch->hwr_names;
618 }
619 return;
620 }
621
622 /* Invalid option. */
623 }
624
625 void
626 parse_mips_dis_options (options)
627 const char *options;
628 {
629 const char *option_end;
630
631 if (options == NULL)
632 return;
633
634 while (*options != '\0')
635 {
636 /* Skip empty options. */
637 if (*options == ',')
638 {
639 options++;
640 continue;
641 }
642
643 /* We know that *options is neither NUL or a comma. */
644 option_end = options + 1;
645 while (*option_end != ',' && *option_end != '\0')
646 option_end++;
647
648 parse_mips_dis_option (options, option_end - options);
649
650 /* Go on to the next one. If option_end points to a comma, it
651 will be skipped above. */
652 options = option_end;
653 }
654 }
655
656 static const struct mips_cp0sel_name *
657 lookup_mips_cp0sel_name(names, len, cp0reg, sel)
658 const struct mips_cp0sel_name *names;
659 unsigned int len, cp0reg, sel;
660 {
661 unsigned int i;
662
663 for (i = 0; i < len; i++)
664 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
665 return &names[i];
666 return NULL;
667 }
668 \f
669 /* Print insn arguments for 32/64-bit code. */
670
671 static void
672 print_insn_args (d, l, pc, info)
673 const char *d;
674 register unsigned long int l;
675 bfd_vma pc;
676 struct disassemble_info *info;
677 {
678 int op, delta;
679 unsigned int lsb, msb, msbd;
680
681 lsb = 0;
682
683 for (; *d != '\0'; d++)
684 {
685 switch (*d)
686 {
687 case ',':
688 case '(':
689 case ')':
690 case '[':
691 case ']':
692 (*info->fprintf_func) (info->stream, "%c", *d);
693 break;
694
695 case '+':
696 /* Extension character; switch for second char. */
697 d++;
698 switch (*d)
699 {
700 case '\0':
701 /* xgettext:c-format */
702 (*info->fprintf_func) (info->stream,
703 _("# internal error, incomplete extension sequence (+)"));
704 return;
705
706 case 'A':
707 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
708 (*info->fprintf_func) (info->stream, "0x%x", lsb);
709 break;
710
711 case 'B':
712 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
713 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
714 break;
715
716 case 'C':
717 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
718 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
719 break;
720
721 case 'D':
722 {
723 const struct mips_cp0sel_name *n;
724 unsigned int cp0reg, sel;
725
726 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
727 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
728
729 /* CP0 register including 'sel' code for mtcN (et al.), to be
730 printed textually if known. If not known, print both
731 CP0 register name and sel numerically since CP0 register
732 with sel 0 may have a name unrelated to register being
733 printed. */
734 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
735 mips_cp0sel_names_len, cp0reg, sel);
736 if (n != NULL)
737 (*info->fprintf_func) (info->stream, "%s", n->name);
738 else
739 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
740 break;
741 }
742
743 default:
744 /* xgettext:c-format */
745 (*info->fprintf_func) (info->stream,
746 _("# internal error, undefined extension sequence (+%c)"),
747 *d);
748 return;
749 }
750 break;
751
752 case 's':
753 case 'b':
754 case 'r':
755 case 'v':
756 (*info->fprintf_func) (info->stream, "%s",
757 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
758 break;
759
760 case 't':
761 case 'w':
762 (*info->fprintf_func) (info->stream, "%s",
763 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
764 break;
765
766 case 'i':
767 case 'u':
768 (*info->fprintf_func) (info->stream, "0x%x",
769 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
770 break;
771
772 case 'j': /* Same as i, but sign-extended. */
773 case 'o':
774 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
775 if (delta & 0x8000)
776 delta |= ~0xffff;
777 (*info->fprintf_func) (info->stream, "%d",
778 delta);
779 break;
780
781 case 'h':
782 (*info->fprintf_func) (info->stream, "0x%x",
783 (unsigned int) ((l >> OP_SH_PREFX)
784 & OP_MASK_PREFX));
785 break;
786
787 case 'k':
788 (*info->fprintf_func) (info->stream, "0x%x",
789 (unsigned int) ((l >> OP_SH_CACHE)
790 & OP_MASK_CACHE));
791 break;
792
793 case 'a':
794 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
795 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
796 (*info->print_address_func) (info->target, info);
797 break;
798
799 case 'p':
800 /* Sign extend the displacement. */
801 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
802 if (delta & 0x8000)
803 delta |= ~0xffff;
804 info->target = (delta << 2) + pc + INSNLEN;
805 (*info->print_address_func) (info->target, info);
806 break;
807
808 case 'd':
809 (*info->fprintf_func) (info->stream, "%s",
810 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
811 break;
812
813 case 'U':
814 {
815 /* First check for both rd and rt being equal. */
816 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
817 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
818 (*info->fprintf_func) (info->stream, "%s",
819 mips_gpr_names[reg]);
820 else
821 {
822 /* If one is zero use the other. */
823 if (reg == 0)
824 (*info->fprintf_func) (info->stream, "%s",
825 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
826 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
827 (*info->fprintf_func) (info->stream, "%s",
828 mips_gpr_names[reg]);
829 else /* Bogus, result depends on processor. */
830 (*info->fprintf_func) (info->stream, "%s or %s",
831 mips_gpr_names[reg],
832 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
833 }
834 }
835 break;
836
837 case 'z':
838 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
839 break;
840
841 case '<':
842 (*info->fprintf_func) (info->stream, "0x%x",
843 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
844 break;
845
846 case 'c':
847 (*info->fprintf_func) (info->stream, "0x%x",
848 (l >> OP_SH_CODE) & OP_MASK_CODE);
849 break;
850
851 case 'q':
852 (*info->fprintf_func) (info->stream, "0x%x",
853 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
854 break;
855
856 case 'C':
857 (*info->fprintf_func) (info->stream, "0x%x",
858 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
859 break;
860
861 case 'B':
862 (*info->fprintf_func) (info->stream, "0x%x",
863 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
864 break;
865
866 case 'J':
867 (*info->fprintf_func) (info->stream, "0x%x",
868 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
869 break;
870
871 case 'S':
872 case 'V':
873 (*info->fprintf_func) (info->stream, "%s",
874 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
875 break;
876
877 case 'T':
878 case 'W':
879 (*info->fprintf_func) (info->stream, "%s",
880 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
881 break;
882
883 case 'D':
884 (*info->fprintf_func) (info->stream, "%s",
885 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
886 break;
887
888 case 'R':
889 (*info->fprintf_func) (info->stream, "%s",
890 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
891 break;
892
893 case 'E':
894 /* Coprocessor register for lwcN instructions, et al.
895
896 Note that there is no load/store cp0 instructions, and
897 that FPU (cp1) instructions disassemble this field using
898 'T' format. Therefore, until we gain understanding of
899 cp2 register names, we can simply print the register
900 numbers. */
901 (*info->fprintf_func) (info->stream, "$%d",
902 (l >> OP_SH_RT) & OP_MASK_RT);
903 break;
904
905 case 'G':
906 /* Coprocessor register for mtcN instructions, et al. Note
907 that FPU (cp1) instructions disassemble this field using
908 'S' format. Therefore, we only need to worry about cp0,
909 cp2, and cp3. */
910 op = (l >> OP_SH_OP) & OP_MASK_OP;
911 if (op == OP_OP_COP0)
912 (*info->fprintf_func) (info->stream, "%s",
913 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
914 else
915 (*info->fprintf_func) (info->stream, "$%d",
916 (l >> OP_SH_RD) & OP_MASK_RD);
917 break;
918
919 case 'K':
920 (*info->fprintf_func) (info->stream, "%s",
921 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
922 break;
923
924 case 'N':
925 (*info->fprintf_func) (info->stream, "$fcc%d",
926 (l >> OP_SH_BCC) & OP_MASK_BCC);
927 break;
928
929 case 'M':
930 (*info->fprintf_func) (info->stream, "$fcc%d",
931 (l >> OP_SH_CCC) & OP_MASK_CCC);
932 break;
933
934 case 'P':
935 (*info->fprintf_func) (info->stream, "%d",
936 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
937 break;
938
939 case 'e':
940 (*info->fprintf_func) (info->stream, "%d",
941 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
942 break;
943
944 case '%':
945 (*info->fprintf_func) (info->stream, "%d",
946 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
947 break;
948
949 case 'H':
950 (*info->fprintf_func) (info->stream, "%d",
951 (l >> OP_SH_SEL) & OP_MASK_SEL);
952 break;
953
954 case 'O':
955 (*info->fprintf_func) (info->stream, "%d",
956 (l >> OP_SH_ALN) & OP_MASK_ALN);
957 break;
958
959 case 'Q':
960 {
961 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
962 if ((vsel & 0x10) == 0)
963 {
964 int fmt;
965 vsel &= 0x0f;
966 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
967 if ((vsel & 1) == 0)
968 break;
969 (*info->fprintf_func) (info->stream, "$v%d[%d]",
970 (l >> OP_SH_FT) & OP_MASK_FT,
971 vsel >> 1);
972 }
973 else if ((vsel & 0x08) == 0)
974 {
975 (*info->fprintf_func) (info->stream, "$v%d",
976 (l >> OP_SH_FT) & OP_MASK_FT);
977 }
978 else
979 {
980 (*info->fprintf_func) (info->stream, "0x%x",
981 (l >> OP_SH_FT) & OP_MASK_FT);
982 }
983 }
984 break;
985
986 case 'X':
987 (*info->fprintf_func) (info->stream, "$v%d",
988 (l >> OP_SH_FD) & OP_MASK_FD);
989 break;
990
991 case 'Y':
992 (*info->fprintf_func) (info->stream, "$v%d",
993 (l >> OP_SH_FS) & OP_MASK_FS);
994 break;
995
996 case 'Z':
997 (*info->fprintf_func) (info->stream, "$v%d",
998 (l >> OP_SH_FT) & OP_MASK_FT);
999 break;
1000
1001 default:
1002 /* xgettext:c-format */
1003 (*info->fprintf_func) (info->stream,
1004 _("# internal error, undefined modifier(%c)"),
1005 *d);
1006 return;
1007 }
1008 }
1009 }
1010 \f
1011 /* Check if the object uses NewABI conventions. */
1012
1013 static int
1014 is_newabi (header)
1015 Elf_Internal_Ehdr *header;
1016 {
1017 /* There are no old-style ABIs which use 64-bit ELF. */
1018 if (header->e_ident[EI_CLASS] == ELFCLASS64)
1019 return 1;
1020
1021 /* If a 32-bit ELF file, n32 is a new-style ABI. */
1022 if ((header->e_flags & EF_MIPS_ABI2) != 0)
1023 return 1;
1024
1025 return 0;
1026 }
1027 \f
1028 /* Print the mips instruction at address MEMADDR in debugged memory,
1029 on using INFO. Returns length of the instruction, in bytes, which is
1030 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1031 this is little-endian code. */
1032
1033 static int
1034 print_insn_mips (memaddr, word, info)
1035 bfd_vma memaddr;
1036 unsigned long int word;
1037 struct disassemble_info *info;
1038 {
1039 register const struct mips_opcode *op;
1040 static bfd_boolean init = 0;
1041 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1042
1043 /* Build a hash table to shorten the search time. */
1044 if (! init)
1045 {
1046 unsigned int i;
1047
1048 for (i = 0; i <= OP_MASK_OP; i++)
1049 {
1050 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1051 {
1052 if (op->pinfo == INSN_MACRO)
1053 continue;
1054 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1055 {
1056 mips_hash[i] = op;
1057 break;
1058 }
1059 }
1060 }
1061
1062 init = 1;
1063 }
1064
1065 info->bytes_per_chunk = INSNLEN;
1066 info->display_endian = info->endian;
1067 info->insn_info_valid = 1;
1068 info->branch_delay_insns = 0;
1069 info->data_size = 0;
1070 info->insn_type = dis_nonbranch;
1071 info->target = 0;
1072 info->target2 = 0;
1073
1074 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1075 if (op != NULL)
1076 {
1077 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1078 {
1079 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
1080 {
1081 register const char *d;
1082
1083 /* We always allow to disassemble the jalx instruction. */
1084 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1085 && strcmp (op->name, "jalx"))
1086 continue;
1087
1088 /* Figure out instruction type and branch delay information. */
1089 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1090 {
1091 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1092 info->insn_type = dis_jsr;
1093 else
1094 info->insn_type = dis_branch;
1095 info->branch_delay_insns = 1;
1096 }
1097 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1098 | INSN_COND_BRANCH_LIKELY)) != 0)
1099 {
1100 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1101 info->insn_type = dis_condjsr;
1102 else
1103 info->insn_type = dis_condbranch;
1104 info->branch_delay_insns = 1;
1105 }
1106 else if ((op->pinfo & (INSN_STORE_MEMORY
1107 | INSN_LOAD_MEMORY_DELAY)) != 0)
1108 info->insn_type = dis_dref;
1109
1110 (*info->fprintf_func) (info->stream, "%s", op->name);
1111
1112 d = op->args;
1113 if (d != NULL && *d != '\0')
1114 {
1115 (*info->fprintf_func) (info->stream, "\t");
1116 print_insn_args (d, word, memaddr, info);
1117 }
1118
1119 return INSNLEN;
1120 }
1121 }
1122 }
1123
1124 /* Handle undefined instructions. */
1125 info->insn_type = dis_noninsn;
1126 (*info->fprintf_func) (info->stream, "0x%x", word);
1127 return INSNLEN;
1128 }
1129 \f
1130 /* In an environment where we do not know the symbol type of the
1131 instruction we are forced to assume that the low order bit of the
1132 instructions' address may mark it as a mips16 instruction. If we
1133 are single stepping, or the pc is within the disassembled function,
1134 this works. Otherwise, we need a clue. Sometimes. */
1135
1136 static int
1137 _print_insn_mips (memaddr, info, endianness)
1138 bfd_vma memaddr;
1139 struct disassemble_info *info;
1140 enum bfd_endian endianness;
1141 {
1142 bfd_byte buffer[INSNLEN];
1143 int status;
1144
1145 set_default_mips_dis_options (info);
1146 parse_mips_dis_options (info->disassembler_options);
1147
1148 #if 1
1149 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1150 /* Only a few tools will work this way. */
1151 if (memaddr & 0x01)
1152 return print_insn_mips16 (memaddr, info);
1153 #endif
1154
1155 #if SYMTAB_AVAILABLE
1156 if (info->mach == bfd_mach_mips16
1157 || (info->flavour == bfd_target_elf_flavour
1158 && info->symbols != NULL
1159 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1160 == STO_MIPS16)))
1161 return print_insn_mips16 (memaddr, info);
1162 #endif
1163
1164 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1165 if (status == 0)
1166 {
1167 unsigned long insn;
1168
1169 if (endianness == BFD_ENDIAN_BIG)
1170 insn = (unsigned long) bfd_getb32 (buffer);
1171 else
1172 insn = (unsigned long) bfd_getl32 (buffer);
1173
1174 return print_insn_mips (memaddr, insn, info);
1175 }
1176 else
1177 {
1178 (*info->memory_error_func) (status, memaddr, info);
1179 return -1;
1180 }
1181 }
1182
1183 int
1184 print_insn_big_mips (memaddr, info)
1185 bfd_vma memaddr;
1186 struct disassemble_info *info;
1187 {
1188 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1189 }
1190
1191 int
1192 print_insn_little_mips (memaddr, info)
1193 bfd_vma memaddr;
1194 struct disassemble_info *info;
1195 {
1196 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
1197 }
1198 \f
1199 /* Disassemble mips16 instructions. */
1200
1201 static int
1202 print_insn_mips16 (memaddr, info)
1203 bfd_vma memaddr;
1204 struct disassemble_info *info;
1205 {
1206 int status;
1207 bfd_byte buffer[2];
1208 int length;
1209 int insn;
1210 bfd_boolean use_extend;
1211 int extend = 0;
1212 const struct mips_opcode *op, *opend;
1213
1214 info->bytes_per_chunk = 2;
1215 info->display_endian = info->endian;
1216 info->insn_info_valid = 1;
1217 info->branch_delay_insns = 0;
1218 info->data_size = 0;
1219 info->insn_type = dis_nonbranch;
1220 info->target = 0;
1221 info->target2 = 0;
1222
1223 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1224 if (status != 0)
1225 {
1226 (*info->memory_error_func) (status, memaddr, info);
1227 return -1;
1228 }
1229
1230 length = 2;
1231
1232 if (info->endian == BFD_ENDIAN_BIG)
1233 insn = bfd_getb16 (buffer);
1234 else
1235 insn = bfd_getl16 (buffer);
1236
1237 /* Handle the extend opcode specially. */
1238 use_extend = FALSE;
1239 if ((insn & 0xf800) == 0xf000)
1240 {
1241 use_extend = TRUE;
1242 extend = insn & 0x7ff;
1243
1244 memaddr += 2;
1245
1246 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1247 if (status != 0)
1248 {
1249 (*info->fprintf_func) (info->stream, "extend 0x%x",
1250 (unsigned int) extend);
1251 (*info->memory_error_func) (status, memaddr, info);
1252 return -1;
1253 }
1254
1255 if (info->endian == BFD_ENDIAN_BIG)
1256 insn = bfd_getb16 (buffer);
1257 else
1258 insn = bfd_getl16 (buffer);
1259
1260 /* Check for an extend opcode followed by an extend opcode. */
1261 if ((insn & 0xf800) == 0xf000)
1262 {
1263 (*info->fprintf_func) (info->stream, "extend 0x%x",
1264 (unsigned int) extend);
1265 info->insn_type = dis_noninsn;
1266 return length;
1267 }
1268
1269 length += 2;
1270 }
1271
1272 /* FIXME: Should probably use a hash table on the major opcode here. */
1273
1274 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1275 for (op = mips16_opcodes; op < opend; op++)
1276 {
1277 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
1278 {
1279 const char *s;
1280
1281 if (strchr (op->args, 'a') != NULL)
1282 {
1283 if (use_extend)
1284 {
1285 (*info->fprintf_func) (info->stream, "extend 0x%x",
1286 (unsigned int) extend);
1287 info->insn_type = dis_noninsn;
1288 return length - 2;
1289 }
1290
1291 use_extend = FALSE;
1292
1293 memaddr += 2;
1294
1295 status = (*info->read_memory_func) (memaddr, buffer, 2,
1296 info);
1297 if (status == 0)
1298 {
1299 use_extend = TRUE;
1300 if (info->endian == BFD_ENDIAN_BIG)
1301 extend = bfd_getb16 (buffer);
1302 else
1303 extend = bfd_getl16 (buffer);
1304 length += 2;
1305 }
1306 }
1307
1308 (*info->fprintf_func) (info->stream, "%s", op->name);
1309 if (op->args[0] != '\0')
1310 (*info->fprintf_func) (info->stream, "\t");
1311
1312 for (s = op->args; *s != '\0'; s++)
1313 {
1314 if (*s == ','
1315 && s[1] == 'w'
1316 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1317 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1318 {
1319 /* Skip the register and the comma. */
1320 ++s;
1321 continue;
1322 }
1323 if (*s == ','
1324 && s[1] == 'v'
1325 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1326 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1327 {
1328 /* Skip the register and the comma. */
1329 ++s;
1330 continue;
1331 }
1332 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1333 info);
1334 }
1335
1336 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1337 {
1338 info->branch_delay_insns = 1;
1339 if (info->insn_type != dis_jsr)
1340 info->insn_type = dis_branch;
1341 }
1342
1343 return length;
1344 }
1345 }
1346
1347 if (use_extend)
1348 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1349 (*info->fprintf_func) (info->stream, "0x%x", insn);
1350 info->insn_type = dis_noninsn;
1351
1352 return length;
1353 }
1354
1355 /* Disassemble an operand for a mips16 instruction. */
1356
1357 static void
1358 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
1359 char type;
1360 const struct mips_opcode *op;
1361 int l;
1362 bfd_boolean use_extend;
1363 int extend;
1364 bfd_vma memaddr;
1365 struct disassemble_info *info;
1366 {
1367 switch (type)
1368 {
1369 case ',':
1370 case '(':
1371 case ')':
1372 (*info->fprintf_func) (info->stream, "%c", type);
1373 break;
1374
1375 case 'y':
1376 case 'w':
1377 (*info->fprintf_func) (info->stream, "%s",
1378 mips16_reg_names[((l >> MIPS16OP_SH_RY)
1379 & MIPS16OP_MASK_RY)]);
1380 break;
1381
1382 case 'x':
1383 case 'v':
1384 (*info->fprintf_func) (info->stream, "%s",
1385 mips16_reg_names[((l >> MIPS16OP_SH_RX)
1386 & MIPS16OP_MASK_RX)]);
1387 break;
1388
1389 case 'z':
1390 (*info->fprintf_func) (info->stream, "%s",
1391 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
1392 & MIPS16OP_MASK_RZ)]);
1393 break;
1394
1395 case 'Z':
1396 (*info->fprintf_func) (info->stream, "%s",
1397 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
1398 & MIPS16OP_MASK_MOVE32Z)]);
1399 break;
1400
1401 case '0':
1402 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1403 break;
1404
1405 case 'S':
1406 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1407 break;
1408
1409 case 'P':
1410 (*info->fprintf_func) (info->stream, "$pc");
1411 break;
1412
1413 case 'R':
1414 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1415 break;
1416
1417 case 'X':
1418 (*info->fprintf_func) (info->stream, "%s",
1419 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1420 & MIPS16OP_MASK_REGR32)]);
1421 break;
1422
1423 case 'Y':
1424 (*info->fprintf_func) (info->stream, "%s",
1425 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1426 break;
1427
1428 case '<':
1429 case '>':
1430 case '[':
1431 case ']':
1432 case '4':
1433 case '5':
1434 case 'H':
1435 case 'W':
1436 case 'D':
1437 case 'j':
1438 case '6':
1439 case '8':
1440 case 'V':
1441 case 'C':
1442 case 'U':
1443 case 'k':
1444 case 'K':
1445 case 'p':
1446 case 'q':
1447 case 'A':
1448 case 'B':
1449 case 'E':
1450 {
1451 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1452
1453 shift = 0;
1454 signedp = 0;
1455 extbits = 16;
1456 pcrel = 0;
1457 extu = 0;
1458 branch = 0;
1459 switch (type)
1460 {
1461 case '<':
1462 nbits = 3;
1463 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1464 extbits = 5;
1465 extu = 1;
1466 break;
1467 case '>':
1468 nbits = 3;
1469 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1470 extbits = 5;
1471 extu = 1;
1472 break;
1473 case '[':
1474 nbits = 3;
1475 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1476 extbits = 6;
1477 extu = 1;
1478 break;
1479 case ']':
1480 nbits = 3;
1481 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1482 extbits = 6;
1483 extu = 1;
1484 break;
1485 case '4':
1486 nbits = 4;
1487 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1488 signedp = 1;
1489 extbits = 15;
1490 break;
1491 case '5':
1492 nbits = 5;
1493 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1494 info->insn_type = dis_dref;
1495 info->data_size = 1;
1496 break;
1497 case 'H':
1498 nbits = 5;
1499 shift = 1;
1500 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1501 info->insn_type = dis_dref;
1502 info->data_size = 2;
1503 break;
1504 case 'W':
1505 nbits = 5;
1506 shift = 2;
1507 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1508 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1509 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1510 {
1511 info->insn_type = dis_dref;
1512 info->data_size = 4;
1513 }
1514 break;
1515 case 'D':
1516 nbits = 5;
1517 shift = 3;
1518 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1519 info->insn_type = dis_dref;
1520 info->data_size = 8;
1521 break;
1522 case 'j':
1523 nbits = 5;
1524 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1525 signedp = 1;
1526 break;
1527 case '6':
1528 nbits = 6;
1529 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1530 break;
1531 case '8':
1532 nbits = 8;
1533 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1534 break;
1535 case 'V':
1536 nbits = 8;
1537 shift = 2;
1538 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1539 /* FIXME: This might be lw, or it might be addiu to $sp or
1540 $pc. We assume it's load. */
1541 info->insn_type = dis_dref;
1542 info->data_size = 4;
1543 break;
1544 case 'C':
1545 nbits = 8;
1546 shift = 3;
1547 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1548 info->insn_type = dis_dref;
1549 info->data_size = 8;
1550 break;
1551 case 'U':
1552 nbits = 8;
1553 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1554 extu = 1;
1555 break;
1556 case 'k':
1557 nbits = 8;
1558 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1559 signedp = 1;
1560 break;
1561 case 'K':
1562 nbits = 8;
1563 shift = 3;
1564 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1565 signedp = 1;
1566 break;
1567 case 'p':
1568 nbits = 8;
1569 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1570 signedp = 1;
1571 pcrel = 1;
1572 branch = 1;
1573 info->insn_type = dis_condbranch;
1574 break;
1575 case 'q':
1576 nbits = 11;
1577 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1578 signedp = 1;
1579 pcrel = 1;
1580 branch = 1;
1581 info->insn_type = dis_branch;
1582 break;
1583 case 'A':
1584 nbits = 8;
1585 shift = 2;
1586 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1587 pcrel = 1;
1588 /* FIXME: This can be lw or la. We assume it is lw. */
1589 info->insn_type = dis_dref;
1590 info->data_size = 4;
1591 break;
1592 case 'B':
1593 nbits = 5;
1594 shift = 3;
1595 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1596 pcrel = 1;
1597 info->insn_type = dis_dref;
1598 info->data_size = 8;
1599 break;
1600 case 'E':
1601 nbits = 5;
1602 shift = 2;
1603 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1604 pcrel = 1;
1605 break;
1606 default:
1607 abort ();
1608 }
1609
1610 if (! use_extend)
1611 {
1612 if (signedp && immed >= (1 << (nbits - 1)))
1613 immed -= 1 << nbits;
1614 immed <<= shift;
1615 if ((type == '<' || type == '>' || type == '[' || type == ']')
1616 && immed == 0)
1617 immed = 8;
1618 }
1619 else
1620 {
1621 if (extbits == 16)
1622 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1623 else if (extbits == 15)
1624 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1625 else
1626 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1627 immed &= (1 << extbits) - 1;
1628 if (! extu && immed >= (1 << (extbits - 1)))
1629 immed -= 1 << extbits;
1630 }
1631
1632 if (! pcrel)
1633 (*info->fprintf_func) (info->stream, "%d", immed);
1634 else
1635 {
1636 bfd_vma baseaddr;
1637
1638 if (branch)
1639 {
1640 immed *= 2;
1641 baseaddr = memaddr + 2;
1642 }
1643 else if (use_extend)
1644 baseaddr = memaddr - 2;
1645 else
1646 {
1647 int status;
1648 bfd_byte buffer[2];
1649
1650 baseaddr = memaddr;
1651
1652 /* If this instruction is in the delay slot of a jr
1653 instruction, the base address is the address of the
1654 jr instruction. If it is in the delay slot of jalr
1655 instruction, the base address is the address of the
1656 jalr instruction. This test is unreliable: we have
1657 no way of knowing whether the previous word is
1658 instruction or data. */
1659 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1660 info);
1661 if (status == 0
1662 && (((info->endian == BFD_ENDIAN_BIG
1663 ? bfd_getb16 (buffer)
1664 : bfd_getl16 (buffer))
1665 & 0xf800) == 0x1800))
1666 baseaddr = memaddr - 4;
1667 else
1668 {
1669 status = (*info->read_memory_func) (memaddr - 2, buffer,
1670 2, info);
1671 if (status == 0
1672 && (((info->endian == BFD_ENDIAN_BIG
1673 ? bfd_getb16 (buffer)
1674 : bfd_getl16 (buffer))
1675 & 0xf81f) == 0xe800))
1676 baseaddr = memaddr - 2;
1677 }
1678 }
1679 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1680 (*info->print_address_func) (info->target, info);
1681 }
1682 }
1683 break;
1684
1685 case 'a':
1686 if (! use_extend)
1687 extend = 0;
1688 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1689 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1690 (*info->print_address_func) (info->target, info);
1691 info->insn_type = dis_jsr;
1692 info->branch_delay_insns = 1;
1693 break;
1694
1695 case 'l':
1696 case 'L':
1697 {
1698 int need_comma, amask, smask;
1699
1700 need_comma = 0;
1701
1702 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1703
1704 amask = (l >> 3) & 7;
1705
1706 if (amask > 0 && amask < 5)
1707 {
1708 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1709 if (amask > 1)
1710 (*info->fprintf_func) (info->stream, "-%s",
1711 mips_gpr_names[amask + 3]);
1712 need_comma = 1;
1713 }
1714
1715 smask = (l >> 1) & 3;
1716 if (smask == 3)
1717 {
1718 (*info->fprintf_func) (info->stream, "%s??",
1719 need_comma ? "," : "");
1720 need_comma = 1;
1721 }
1722 else if (smask > 0)
1723 {
1724 (*info->fprintf_func) (info->stream, "%s%s",
1725 need_comma ? "," : "",
1726 mips_gpr_names[16]);
1727 if (smask > 1)
1728 (*info->fprintf_func) (info->stream, "-%s",
1729 mips_gpr_names[smask + 15]);
1730 need_comma = 1;
1731 }
1732
1733 if (l & 1)
1734 {
1735 (*info->fprintf_func) (info->stream, "%s%s",
1736 need_comma ? "," : "",
1737 mips_gpr_names[31]);
1738 need_comma = 1;
1739 }
1740
1741 if (amask == 5 || amask == 6)
1742 {
1743 (*info->fprintf_func) (info->stream, "%s$f0",
1744 need_comma ? "," : "");
1745 if (amask == 6)
1746 (*info->fprintf_func) (info->stream, "-$f1");
1747 }
1748 }
1749 break;
1750
1751 default:
1752 /* xgettext:c-format */
1753 (*info->fprintf_func)
1754 (info->stream,
1755 _("# internal disassembler error, unrecognised modifier (%c)"),
1756 type);
1757 abort ();
1758 }
1759 }
1760
1761 void
1762 print_mips_disassembler_options (stream)
1763 FILE *stream;
1764 {
1765 unsigned int i;
1766
1767 fprintf (stream, _("\n\
1768 The following MIPS specific disassembler options are supported for use\n\
1769 with the -M switch (multiple options should be separated by commas):\n"));
1770
1771 fprintf (stream, _("\n\
1772 gpr-names=ABI Print GPR names according to specified ABI.\n\
1773 Default: based on binary being disassembled.\n"));
1774
1775 fprintf (stream, _("\n\
1776 fpr-names=ABI Print FPR names according to specified ABI.\n\
1777 Default: numeric.\n"));
1778
1779 fprintf (stream, _("\n\
1780 cp0-names=ARCH Print CP0 register names according to\n\
1781 specified architecture.\n\
1782 Default: based on binary being disassembled.\n"));
1783
1784 fprintf (stream, _("\n\
1785 hwr-names=ARCH Print HWR names according to specified \n\
1786 architecture.\n\
1787 Default: based on binary being disassembled.\n"));
1788
1789 fprintf (stream, _("\n\
1790 reg-names=ABI Print GPR and FPR names according to\n\
1791 specified ABI.\n"));
1792
1793 fprintf (stream, _("\n\
1794 reg-names=ARCH Print CP0 register and HWR names according to\n\
1795 specified architecture.\n"));
1796
1797 fprintf (stream, _("\n\
1798 For the options above, the following values are supported for \"ABI\":\n\
1799 "));
1800 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
1801 fprintf (stream, " %s", mips_abi_choices[i].name);
1802 fprintf (stream, _("\n"));
1803
1804 fprintf (stream, _("\n\
1805 For the options above, The following values are supported for \"ARCH\":\n\
1806 "));
1807 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
1808 if (*mips_arch_choices[i].name != '\0')
1809 fprintf (stream, " %s", mips_arch_choices[i].name);
1810 fprintf (stream, _("\n"));
1811
1812 fprintf (stream, _("\n"));
1813 }
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