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include/opcode/
[thirdparty/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 static const char * const mips_gpr_names_numeric[32] =
55 {
56 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
57 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
58 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
59 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
60 };
61
62 static const char * const mips_gpr_names_oldabi[32] =
63 {
64 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
65 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
66 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
67 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
68 };
69
70 static const char * const mips_gpr_names_newabi[32] =
71 {
72 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
73 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
74 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
75 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
76 };
77
78 static const char * const mips_fpr_names_numeric[32] =
79 {
80 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
81 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
82 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
83 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
84 };
85
86 static const char * const mips_fpr_names_32[32] =
87 {
88 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
89 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
90 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
91 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
92 };
93
94 static const char * const mips_fpr_names_n32[32] =
95 {
96 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
97 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
98 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
99 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
100 };
101
102 static const char * const mips_fpr_names_64[32] =
103 {
104 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
105 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
106 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
107 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
108 };
109
110 static const char * const mips_cp0_names_numeric[32] =
111 {
112 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
113 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
114 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
115 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
116 };
117
118 static const char * const mips_cp0_names_r3000[32] =
119 {
120 "c0_index", "c0_random", "c0_entrylo", "$3",
121 "c0_context", "$5", "$6", "$7",
122 "c0_badvaddr", "$9", "c0_entryhi", "$11",
123 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
124 "$16", "$17", "$18", "$19",
125 "$20", "$21", "$22", "$23",
126 "$24", "$25", "$26", "$27",
127 "$28", "$29", "$30", "$31",
128 };
129
130 static const char * const mips_cp0_names_r4000[32] =
131 {
132 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
133 "c0_context", "c0_pagemask", "c0_wired", "$7",
134 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
135 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
136 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
137 "c0_xcontext", "$21", "$22", "$23",
138 "$24", "$25", "c0_ecc", "c0_cacheerr",
139 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
140 };
141
142 static const char * const mips_cp0_names_r5900[32] =
143 {
144 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
145 "c0_context", "c0_pagemask", "c0_wired", "$7",
146 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
147 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
148 "c0_config", "$17", "$18", "$19",
149 "$20", "$21", "$22", "c0_badpaddr",
150 "c0_depc", "c0_perfcnt", "$26", "$27",
151 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
152 };
153
154 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
155 {
156 { 24, 2, "c0_iab" },
157 { 24, 3, "c0_iabm" },
158 { 24, 4, "c0_dab" },
159 { 24, 5, "c0_dabm" },
160 { 24, 6, "c0_dvb" },
161 { 24, 7, "c0_dvbm" },
162 { 25, 1, "c0_perfcnt,1" },
163 { 25, 2, "c0_perfcnt,2" }
164 };
165
166 static const char * const mips_cp0_names_mips3264[32] =
167 {
168 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
169 "c0_context", "c0_pagemask", "c0_wired", "$7",
170 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
171 "c0_status", "c0_cause", "c0_epc", "c0_prid",
172 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
173 "c0_xcontext", "$21", "$22", "c0_debug",
174 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
175 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
176 };
177
178 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
179 {
180 { 16, 1, "c0_config1" },
181 { 16, 2, "c0_config2" },
182 { 16, 3, "c0_config3" },
183 { 18, 1, "c0_watchlo,1" },
184 { 18, 2, "c0_watchlo,2" },
185 { 18, 3, "c0_watchlo,3" },
186 { 18, 4, "c0_watchlo,4" },
187 { 18, 5, "c0_watchlo,5" },
188 { 18, 6, "c0_watchlo,6" },
189 { 18, 7, "c0_watchlo,7" },
190 { 19, 1, "c0_watchhi,1" },
191 { 19, 2, "c0_watchhi,2" },
192 { 19, 3, "c0_watchhi,3" },
193 { 19, 4, "c0_watchhi,4" },
194 { 19, 5, "c0_watchhi,5" },
195 { 19, 6, "c0_watchhi,6" },
196 { 19, 7, "c0_watchhi,7" },
197 { 25, 1, "c0_perfcnt,1" },
198 { 25, 2, "c0_perfcnt,2" },
199 { 25, 3, "c0_perfcnt,3" },
200 { 25, 4, "c0_perfcnt,4" },
201 { 25, 5, "c0_perfcnt,5" },
202 { 25, 6, "c0_perfcnt,6" },
203 { 25, 7, "c0_perfcnt,7" },
204 { 27, 1, "c0_cacheerr,1" },
205 { 27, 2, "c0_cacheerr,2" },
206 { 27, 3, "c0_cacheerr,3" },
207 { 28, 1, "c0_datalo" },
208 { 29, 1, "c0_datahi" }
209 };
210
211 static const char * const mips_cp0_names_mips3264r2[32] =
212 {
213 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
214 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
215 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
216 "c0_status", "c0_cause", "c0_epc", "c0_prid",
217 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
218 "c0_xcontext", "$21", "$22", "c0_debug",
219 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
220 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
221 };
222
223 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
224 {
225 { 4, 1, "c0_contextconfig" },
226 { 0, 1, "c0_mvpcontrol" },
227 { 0, 2, "c0_mvpconf0" },
228 { 0, 3, "c0_mvpconf1" },
229 { 1, 1, "c0_vpecontrol" },
230 { 1, 2, "c0_vpeconf0" },
231 { 1, 3, "c0_vpeconf1" },
232 { 1, 4, "c0_yqmask" },
233 { 1, 5, "c0_vpeschedule" },
234 { 1, 6, "c0_vpeschefback" },
235 { 2, 1, "c0_tcstatus" },
236 { 2, 2, "c0_tcbind" },
237 { 2, 3, "c0_tcrestart" },
238 { 2, 4, "c0_tchalt" },
239 { 2, 5, "c0_tccontext" },
240 { 2, 6, "c0_tcschedule" },
241 { 2, 7, "c0_tcschefback" },
242 { 5, 1, "c0_pagegrain" },
243 { 6, 1, "c0_srsconf0" },
244 { 6, 2, "c0_srsconf1" },
245 { 6, 3, "c0_srsconf2" },
246 { 6, 4, "c0_srsconf3" },
247 { 6, 5, "c0_srsconf4" },
248 { 12, 1, "c0_intctl" },
249 { 12, 2, "c0_srsctl" },
250 { 12, 3, "c0_srsmap" },
251 { 15, 1, "c0_ebase" },
252 { 16, 1, "c0_config1" },
253 { 16, 2, "c0_config2" },
254 { 16, 3, "c0_config3" },
255 { 18, 1, "c0_watchlo,1" },
256 { 18, 2, "c0_watchlo,2" },
257 { 18, 3, "c0_watchlo,3" },
258 { 18, 4, "c0_watchlo,4" },
259 { 18, 5, "c0_watchlo,5" },
260 { 18, 6, "c0_watchlo,6" },
261 { 18, 7, "c0_watchlo,7" },
262 { 19, 1, "c0_watchhi,1" },
263 { 19, 2, "c0_watchhi,2" },
264 { 19, 3, "c0_watchhi,3" },
265 { 19, 4, "c0_watchhi,4" },
266 { 19, 5, "c0_watchhi,5" },
267 { 19, 6, "c0_watchhi,6" },
268 { 19, 7, "c0_watchhi,7" },
269 { 23, 1, "c0_tracecontrol" },
270 { 23, 2, "c0_tracecontrol2" },
271 { 23, 3, "c0_usertracedata" },
272 { 23, 4, "c0_tracebpc" },
273 { 25, 1, "c0_perfcnt,1" },
274 { 25, 2, "c0_perfcnt,2" },
275 { 25, 3, "c0_perfcnt,3" },
276 { 25, 4, "c0_perfcnt,4" },
277 { 25, 5, "c0_perfcnt,5" },
278 { 25, 6, "c0_perfcnt,6" },
279 { 25, 7, "c0_perfcnt,7" },
280 { 27, 1, "c0_cacheerr,1" },
281 { 27, 2, "c0_cacheerr,2" },
282 { 27, 3, "c0_cacheerr,3" },
283 { 28, 1, "c0_datalo" },
284 { 28, 2, "c0_taglo1" },
285 { 28, 3, "c0_datalo1" },
286 { 28, 4, "c0_taglo2" },
287 { 28, 5, "c0_datalo2" },
288 { 28, 6, "c0_taglo3" },
289 { 28, 7, "c0_datalo3" },
290 { 29, 1, "c0_datahi" },
291 { 29, 2, "c0_taghi1" },
292 { 29, 3, "c0_datahi1" },
293 { 29, 4, "c0_taghi2" },
294 { 29, 5, "c0_datahi2" },
295 { 29, 6, "c0_taghi3" },
296 { 29, 7, "c0_datahi3" },
297 };
298
299 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
300 static const char * const mips_cp0_names_sb1[32] =
301 {
302 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
303 "c0_context", "c0_pagemask", "c0_wired", "$7",
304 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
305 "c0_status", "c0_cause", "c0_epc", "c0_prid",
306 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
307 "c0_xcontext", "$21", "$22", "c0_debug",
308 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
309 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
310 };
311
312 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
313 {
314 { 16, 1, "c0_config1" },
315 { 18, 1, "c0_watchlo,1" },
316 { 19, 1, "c0_watchhi,1" },
317 { 22, 0, "c0_perftrace" },
318 { 23, 3, "c0_edebug" },
319 { 25, 1, "c0_perfcnt,1" },
320 { 25, 2, "c0_perfcnt,2" },
321 { 25, 3, "c0_perfcnt,3" },
322 { 25, 4, "c0_perfcnt,4" },
323 { 25, 5, "c0_perfcnt,5" },
324 { 25, 6, "c0_perfcnt,6" },
325 { 25, 7, "c0_perfcnt,7" },
326 { 26, 1, "c0_buserr_pa" },
327 { 27, 1, "c0_cacheerr_d" },
328 { 27, 3, "c0_cacheerr_d_pa" },
329 { 28, 1, "c0_datalo_i" },
330 { 28, 2, "c0_taglo_d" },
331 { 28, 3, "c0_datalo_d" },
332 { 29, 1, "c0_datahi_i" },
333 { 29, 2, "c0_taghi_d" },
334 { 29, 3, "c0_datahi_d" },
335 };
336
337 /* Xlr cop0 register names. */
338 static const char * const mips_cp0_names_xlr[32] = {
339 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
340 "c0_context", "c0_pagemask", "c0_wired", "$7",
341 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
342 "c0_status", "c0_cause", "c0_epc", "c0_prid",
343 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
344 "c0_xcontext", "$21", "$22", "c0_debug",
345 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
346 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
347 };
348
349 /* XLR's CP0 Select Registers. */
350
351 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
352 { 9, 6, "c0_extintreq" },
353 { 9, 7, "c0_extintmask" },
354 { 15, 1, "c0_ebase" },
355 { 16, 1, "c0_config1" },
356 { 16, 2, "c0_config2" },
357 { 16, 3, "c0_config3" },
358 { 16, 7, "c0_procid2" },
359 { 18, 1, "c0_watchlo,1" },
360 { 18, 2, "c0_watchlo,2" },
361 { 18, 3, "c0_watchlo,3" },
362 { 18, 4, "c0_watchlo,4" },
363 { 18, 5, "c0_watchlo,5" },
364 { 18, 6, "c0_watchlo,6" },
365 { 18, 7, "c0_watchlo,7" },
366 { 19, 1, "c0_watchhi,1" },
367 { 19, 2, "c0_watchhi,2" },
368 { 19, 3, "c0_watchhi,3" },
369 { 19, 4, "c0_watchhi,4" },
370 { 19, 5, "c0_watchhi,5" },
371 { 19, 6, "c0_watchhi,6" },
372 { 19, 7, "c0_watchhi,7" },
373 { 25, 1, "c0_perfcnt,1" },
374 { 25, 2, "c0_perfcnt,2" },
375 { 25, 3, "c0_perfcnt,3" },
376 { 25, 4, "c0_perfcnt,4" },
377 { 25, 5, "c0_perfcnt,5" },
378 { 25, 6, "c0_perfcnt,6" },
379 { 25, 7, "c0_perfcnt,7" },
380 { 27, 1, "c0_cacheerr,1" },
381 { 27, 2, "c0_cacheerr,2" },
382 { 27, 3, "c0_cacheerr,3" },
383 { 28, 1, "c0_datalo" },
384 { 29, 1, "c0_datahi" }
385 };
386
387 static const char * const mips_hwr_names_numeric[32] =
388 {
389 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
390 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
391 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
392 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
393 };
394
395 static const char * const mips_hwr_names_mips3264r2[32] =
396 {
397 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
398 "$4", "$5", "$6", "$7",
399 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
400 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
401 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
402 };
403
404 struct mips_abi_choice
405 {
406 const char * name;
407 const char * const *gpr_names;
408 const char * const *fpr_names;
409 };
410
411 struct mips_abi_choice mips_abi_choices[] =
412 {
413 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
414 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
415 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
416 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
417 };
418
419 struct mips_arch_choice
420 {
421 const char *name;
422 int bfd_mach_valid;
423 unsigned long bfd_mach;
424 int processor;
425 int isa;
426 int ase;
427 const char * const *cp0_names;
428 const struct mips_cp0sel_name *cp0sel_names;
429 unsigned int cp0sel_names_len;
430 const char * const *hwr_names;
431 };
432
433 const struct mips_arch_choice mips_arch_choices[] =
434 {
435 { "numeric", 0, 0, 0, 0, 0,
436 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
437
438 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
439 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
440 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
441 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
443 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
444 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
445 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
447 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
449 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
451 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
453 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
455 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
456 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
457 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
459 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
461 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
463 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
465 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
467 mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
468 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
469 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
470 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
471 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
472 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
473 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
474 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
475 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
476 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
477 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
478 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
479 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
480 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
481 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
482 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
483 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
484 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
485 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
486
487 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
488 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
489 _MIPS32 Architecture For Programmers Volume I: Introduction to the
490 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
491 page 1. */
492 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
493 ISA_MIPS32, ASE_SMARTMIPS,
494 mips_cp0_names_mips3264,
495 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
496 mips_hwr_names_numeric },
497
498 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
499 ISA_MIPS32R2,
500 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
501 | ASE_MT | ASE_MCU | ASE_VIRT),
502 mips_cp0_names_mips3264r2,
503 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
504 mips_hwr_names_mips3264r2 },
505
506 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
507 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
508 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
509 mips_cp0_names_mips3264,
510 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
511 mips_hwr_names_numeric },
512
513 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
514 ISA_MIPS64R2,
515 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
516 | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64),
517 mips_cp0_names_mips3264r2,
518 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
519 mips_hwr_names_mips3264r2 },
520
521 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
522 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
523 mips_cp0_names_sb1,
524 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
525 mips_hwr_names_numeric },
526
527 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
528 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
529 NULL, 0, mips_hwr_names_numeric },
530
531 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
532 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
533 NULL, 0, mips_hwr_names_numeric },
534
535 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
536 ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
537 NULL, 0, mips_hwr_names_numeric },
538
539 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
540 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
541 mips_hwr_names_numeric },
542
543 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
544 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
545 NULL, 0, mips_hwr_names_numeric },
546
547 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
548 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
549 NULL, 0, mips_hwr_names_numeric },
550
551 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
552 ISA_MIPS64 | INSN_XLR, 0,
553 mips_cp0_names_xlr,
554 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
555 mips_hwr_names_numeric },
556
557 /* XLP is mostly like XLR, with the prominent exception it is being
558 MIPS64R2. */
559 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
560 ISA_MIPS64R2 | INSN_XLR, 0,
561 mips_cp0_names_xlr,
562 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
563 mips_hwr_names_numeric },
564
565 /* This entry, mips16, is here only for ISA/processor selection; do
566 not print its name. */
567 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
568 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
569 };
570
571 /* ISA and processor type to disassemble for, and register names to use.
572 set_default_mips_dis_options and parse_mips_dis_options fill in these
573 values. */
574 static int mips_processor;
575 static int mips_isa;
576 static int mips_ase;
577 static int micromips_ase;
578 static const char * const *mips_gpr_names;
579 static const char * const *mips_fpr_names;
580 static const char * const *mips_cp0_names;
581 static const struct mips_cp0sel_name *mips_cp0sel_names;
582 static int mips_cp0sel_names_len;
583 static const char * const *mips_hwr_names;
584
585 /* Other options */
586 static int no_aliases; /* If set disassemble as most general inst. */
587 \f
588 static const struct mips_abi_choice *
589 choose_abi_by_name (const char *name, unsigned int namelen)
590 {
591 const struct mips_abi_choice *c;
592 unsigned int i;
593
594 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
595 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
596 && strlen (mips_abi_choices[i].name) == namelen)
597 c = &mips_abi_choices[i];
598
599 return c;
600 }
601
602 static const struct mips_arch_choice *
603 choose_arch_by_name (const char *name, unsigned int namelen)
604 {
605 const struct mips_arch_choice *c = NULL;
606 unsigned int i;
607
608 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
609 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
610 && strlen (mips_arch_choices[i].name) == namelen)
611 c = &mips_arch_choices[i];
612
613 return c;
614 }
615
616 static const struct mips_arch_choice *
617 choose_arch_by_number (unsigned long mach)
618 {
619 static unsigned long hint_bfd_mach;
620 static const struct mips_arch_choice *hint_arch_choice;
621 const struct mips_arch_choice *c;
622 unsigned int i;
623
624 /* We optimize this because even if the user specifies no
625 flags, this will be done for every instruction! */
626 if (hint_bfd_mach == mach
627 && hint_arch_choice != NULL
628 && hint_arch_choice->bfd_mach == hint_bfd_mach)
629 return hint_arch_choice;
630
631 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
632 {
633 if (mips_arch_choices[i].bfd_mach_valid
634 && mips_arch_choices[i].bfd_mach == mach)
635 {
636 c = &mips_arch_choices[i];
637 hint_bfd_mach = mach;
638 hint_arch_choice = c;
639 }
640 }
641 return c;
642 }
643
644 /* Check if the object uses NewABI conventions. */
645
646 static int
647 is_newabi (Elf_Internal_Ehdr *header)
648 {
649 /* There are no old-style ABIs which use 64-bit ELF. */
650 if (header->e_ident[EI_CLASS] == ELFCLASS64)
651 return 1;
652
653 /* If a 32-bit ELF file, n32 is a new-style ABI. */
654 if ((header->e_flags & EF_MIPS_ABI2) != 0)
655 return 1;
656
657 return 0;
658 }
659
660 /* Check if the object has microMIPS ASE code. */
661
662 static int
663 is_micromips (Elf_Internal_Ehdr *header)
664 {
665 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
666 return 1;
667
668 return 0;
669 }
670
671 static void
672 set_default_mips_dis_options (struct disassemble_info *info)
673 {
674 const struct mips_arch_choice *chosen_arch;
675
676 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
677 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
678 CP0 register, and HWR names. */
679 mips_isa = ISA_MIPS3;
680 mips_processor = CPU_R3000;
681 micromips_ase = 0;
682 mips_ase = 0;
683 mips_gpr_names = mips_gpr_names_oldabi;
684 mips_fpr_names = mips_fpr_names_numeric;
685 mips_cp0_names = mips_cp0_names_numeric;
686 mips_cp0sel_names = NULL;
687 mips_cp0sel_names_len = 0;
688 mips_hwr_names = mips_hwr_names_numeric;
689 no_aliases = 0;
690
691 /* Update settings according to the ELF file header flags. */
692 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
693 {
694 Elf_Internal_Ehdr *header;
695
696 header = elf_elfheader (info->section->owner);
697 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
698 if (is_newabi (header))
699 mips_gpr_names = mips_gpr_names_newabi;
700 /* If a microMIPS binary, then don't use MIPS16 bindings. */
701 micromips_ase = is_micromips (header);
702 }
703
704 /* Set ISA, architecture, and cp0 register names as best we can. */
705 #if ! SYMTAB_AVAILABLE
706 /* This is running out on a target machine, not in a host tool.
707 FIXME: Where does mips_target_info come from? */
708 target_processor = mips_target_info.processor;
709 mips_isa = mips_target_info.isa;
710 mips_ase = mips_target_info.ase;
711 #else
712 chosen_arch = choose_arch_by_number (info->mach);
713 if (chosen_arch != NULL)
714 {
715 mips_processor = chosen_arch->processor;
716 mips_isa = chosen_arch->isa;
717 mips_ase = chosen_arch->ase;
718 mips_cp0_names = chosen_arch->cp0_names;
719 mips_cp0sel_names = chosen_arch->cp0sel_names;
720 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
721 mips_hwr_names = chosen_arch->hwr_names;
722 }
723 #endif
724 }
725
726 static void
727 parse_mips_dis_option (const char *option, unsigned int len)
728 {
729 unsigned int i, optionlen, vallen;
730 const char *val;
731 const struct mips_abi_choice *chosen_abi;
732 const struct mips_arch_choice *chosen_arch;
733
734 /* Try to match options that are simple flags */
735 if (CONST_STRNEQ (option, "no-aliases"))
736 {
737 no_aliases = 1;
738 return;
739 }
740
741 if (CONST_STRNEQ (option, "virt"))
742 {
743 mips_ase |= ASE_VIRT;
744 if (mips_isa & ISA_MIPS64R2)
745 mips_ase |= ASE_VIRT64;
746 return;
747 }
748
749 /* Look for the = that delimits the end of the option name. */
750 for (i = 0; i < len; i++)
751 if (option[i] == '=')
752 break;
753
754 if (i == 0) /* Invalid option: no name before '='. */
755 return;
756 if (i == len) /* Invalid option: no '='. */
757 return;
758 if (i == (len - 1)) /* Invalid option: no value after '='. */
759 return;
760
761 optionlen = i;
762 val = option + (optionlen + 1);
763 vallen = len - (optionlen + 1);
764
765 if (strncmp ("gpr-names", option, optionlen) == 0
766 && strlen ("gpr-names") == optionlen)
767 {
768 chosen_abi = choose_abi_by_name (val, vallen);
769 if (chosen_abi != NULL)
770 mips_gpr_names = chosen_abi->gpr_names;
771 return;
772 }
773
774 if (strncmp ("fpr-names", option, optionlen) == 0
775 && strlen ("fpr-names") == optionlen)
776 {
777 chosen_abi = choose_abi_by_name (val, vallen);
778 if (chosen_abi != NULL)
779 mips_fpr_names = chosen_abi->fpr_names;
780 return;
781 }
782
783 if (strncmp ("cp0-names", option, optionlen) == 0
784 && strlen ("cp0-names") == optionlen)
785 {
786 chosen_arch = choose_arch_by_name (val, vallen);
787 if (chosen_arch != NULL)
788 {
789 mips_cp0_names = chosen_arch->cp0_names;
790 mips_cp0sel_names = chosen_arch->cp0sel_names;
791 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
792 }
793 return;
794 }
795
796 if (strncmp ("hwr-names", option, optionlen) == 0
797 && strlen ("hwr-names") == optionlen)
798 {
799 chosen_arch = choose_arch_by_name (val, vallen);
800 if (chosen_arch != NULL)
801 mips_hwr_names = chosen_arch->hwr_names;
802 return;
803 }
804
805 if (strncmp ("reg-names", option, optionlen) == 0
806 && strlen ("reg-names") == optionlen)
807 {
808 /* We check both ABI and ARCH here unconditionally, so
809 that "numeric" will do the desirable thing: select
810 numeric register names for all registers. Other than
811 that, a given name probably won't match both. */
812 chosen_abi = choose_abi_by_name (val, vallen);
813 if (chosen_abi != NULL)
814 {
815 mips_gpr_names = chosen_abi->gpr_names;
816 mips_fpr_names = chosen_abi->fpr_names;
817 }
818 chosen_arch = choose_arch_by_name (val, vallen);
819 if (chosen_arch != NULL)
820 {
821 mips_cp0_names = chosen_arch->cp0_names;
822 mips_cp0sel_names = chosen_arch->cp0sel_names;
823 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
824 mips_hwr_names = chosen_arch->hwr_names;
825 }
826 return;
827 }
828
829 /* Invalid option. */
830 }
831
832 static void
833 parse_mips_dis_options (const char *options)
834 {
835 const char *option_end;
836
837 if (options == NULL)
838 return;
839
840 while (*options != '\0')
841 {
842 /* Skip empty options. */
843 if (*options == ',')
844 {
845 options++;
846 continue;
847 }
848
849 /* We know that *options is neither NUL or a comma. */
850 option_end = options + 1;
851 while (*option_end != ',' && *option_end != '\0')
852 option_end++;
853
854 parse_mips_dis_option (options, option_end - options);
855
856 /* Go on to the next one. If option_end points to a comma, it
857 will be skipped above. */
858 options = option_end;
859 }
860 }
861
862 static const struct mips_cp0sel_name *
863 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
864 unsigned int len,
865 unsigned int cp0reg,
866 unsigned int sel)
867 {
868 unsigned int i;
869
870 for (i = 0; i < len; i++)
871 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
872 return &names[i];
873 return NULL;
874 }
875
876 /* Print register REGNO, of type TYPE, for instruction OPCODE. */
877
878 static void
879 print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
880 enum mips_reg_operand_type type, int regno)
881 {
882 switch (type)
883 {
884 case OP_REG_GP:
885 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]);
886 break;
887
888 case OP_REG_FP:
889 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]);
890 break;
891
892 case OP_REG_CCC:
893 if (opcode->pinfo & (FP_D | FP_S))
894 info->fprintf_func (info->stream, "$fcc%d", regno);
895 else
896 info->fprintf_func (info->stream, "$cc%d", regno);
897 break;
898
899 case OP_REG_VEC:
900 if (opcode->membership & INSN_5400)
901 info->fprintf_func (info->stream, "$f%d", regno);
902 else
903 info->fprintf_func (info->stream, "$v%d", regno);
904 break;
905
906 case OP_REG_ACC:
907 info->fprintf_func (info->stream, "$ac%d", regno);
908 break;
909
910 case OP_REG_COPRO:
911 if (opcode->name[strlen (opcode->name) - 1] == '0')
912 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
913 else
914 info->fprintf_func (info->stream, "$%d", regno);
915 break;
916
917 case OP_REG_HW:
918 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]);
919 break;
920 }
921 }
922 \f
923 /* Used to track the state carried over from previous operands in
924 an instruction. */
925 struct mips_print_arg_state {
926 /* The value of the last OP_INT seen. We only use this for OP_MSB,
927 where the value is known to be unsigned and small. */
928 unsigned int last_int;
929
930 /* The type and number of the last OP_REG seen. We only use this for
931 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */
932 enum mips_reg_operand_type last_reg_type;
933 unsigned int last_regno;
934 };
935
936 /* Initialize STATE for the start of an instruction. */
937
938 static inline void
939 init_print_arg_state (struct mips_print_arg_state *state)
940 {
941 memset (state, 0, sizeof (*state));
942 }
943
944 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
945 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
946 the base address for OP_PCREL operands. */
947
948 static void
949 print_insn_arg (struct disassemble_info *info,
950 struct mips_print_arg_state *state,
951 const struct mips_opcode *opcode,
952 const struct mips_operand *operand,
953 bfd_vma base_pc,
954 unsigned int uval)
955 {
956 const fprintf_ftype infprintf = info->fprintf_func;
957 void *is = info->stream;
958
959 switch (operand->type)
960 {
961 case OP_INT:
962 {
963 const struct mips_int_operand *int_op;
964
965 int_op = (const struct mips_int_operand *) operand;
966 uval = mips_decode_int_operand (int_op, uval);
967 state->last_int = uval;
968 if (int_op->print_hex)
969 infprintf (is, "0x%x", uval);
970 else
971 infprintf (is, "%d", uval);
972 }
973 break;
974
975 case OP_MAPPED_INT:
976 {
977 const struct mips_mapped_int_operand *mint_op;
978
979 mint_op = (const struct mips_mapped_int_operand *) operand;
980 uval = mint_op->int_map[uval];
981 state->last_int = uval;
982 if (mint_op->print_hex)
983 infprintf (is, "0x%x", uval);
984 else
985 infprintf (is, "%d", uval);
986 }
987 break;
988
989 case OP_MSB:
990 {
991 const struct mips_msb_operand *msb_op;
992
993 msb_op = (const struct mips_msb_operand *) operand;
994 uval += msb_op->bias;
995 if (msb_op->add_lsb)
996 uval -= state->last_int;
997 infprintf (is, "0x%x", uval);
998 }
999 break;
1000
1001 case OP_REG:
1002 {
1003 const struct mips_reg_operand *reg_op;
1004
1005 reg_op = (const struct mips_reg_operand *) operand;
1006 if (reg_op->reg_map)
1007 uval = reg_op->reg_map[uval];
1008 print_reg (info, opcode, reg_op->reg_type, uval);
1009
1010 state->last_reg_type = reg_op->reg_type;
1011 state->last_regno = uval;
1012 }
1013 break;
1014
1015 case OP_REG_PAIR:
1016 {
1017 const struct mips_reg_pair_operand *pair_op;
1018
1019 pair_op = (const struct mips_reg_pair_operand *) operand;
1020 print_reg (info, opcode, pair_op->reg_type,
1021 pair_op->reg1_map[uval]);
1022 infprintf (is, ",");
1023 print_reg (info, opcode, pair_op->reg_type,
1024 pair_op->reg2_map[uval]);
1025 }
1026 break;
1027
1028 case OP_PCREL:
1029 {
1030 const struct mips_pcrel_operand *pcrel_op;
1031
1032 pcrel_op = (const struct mips_pcrel_operand *) operand;
1033 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval);
1034
1035 /* Preserve the ISA bit for the GDB disassembler,
1036 otherwise clear it. */
1037 if (info->flavour != bfd_target_unknown_flavour)
1038 info->target &= -2;
1039
1040 (*info->print_address_func) (info->target, info);
1041 }
1042 break;
1043
1044 case OP_PERF_REG:
1045 infprintf (is, "%d", uval);
1046 break;
1047
1048 case OP_ADDIUSP_INT:
1049 {
1050 int sval;
1051
1052 sval = mips_signed_operand (operand, uval) * 4;
1053 if (sval >= -8 && sval < 8)
1054 sval ^= 0x400;
1055 infprintf (is, "%d", sval);
1056 break;
1057 }
1058
1059 case OP_CLO_CLZ_DEST:
1060 {
1061 unsigned int reg1, reg2;
1062
1063 reg1 = uval & 31;
1064 reg2 = uval >> 5;
1065 /* If one is zero use the other. */
1066 if (reg1 == reg2 || reg2 == 0)
1067 infprintf (is, "%s", mips_gpr_names[reg1]);
1068 else if (reg1 == 0)
1069 infprintf (is, "%s", mips_gpr_names[reg2]);
1070 else
1071 /* Bogus, result depends on processor. */
1072 infprintf (is, "%s or %s", mips_gpr_names[reg1],
1073 mips_gpr_names[reg2]);
1074 }
1075 break;
1076
1077 case OP_LWM_SWM_LIST:
1078 if (operand->size == 2)
1079 {
1080 if (uval == 0)
1081 infprintf (is, "%s,%s",
1082 mips_gpr_names[16],
1083 mips_gpr_names[31]);
1084 else
1085 infprintf (is, "%s-%s,%s",
1086 mips_gpr_names[16],
1087 mips_gpr_names[16 + uval],
1088 mips_gpr_names[31]);
1089 }
1090 else
1091 {
1092 int s_reg_encode;
1093
1094 s_reg_encode = uval & 0xf;
1095 if (s_reg_encode != 0)
1096 {
1097 if (s_reg_encode == 1)
1098 infprintf (is, "%s", mips_gpr_names[16]);
1099 else if (s_reg_encode < 9)
1100 infprintf (is, "%s-%s",
1101 mips_gpr_names[16],
1102 mips_gpr_names[15 + s_reg_encode]);
1103 else if (s_reg_encode == 9)
1104 infprintf (is, "%s-%s,%s",
1105 mips_gpr_names[16],
1106 mips_gpr_names[23],
1107 mips_gpr_names[30]);
1108 else
1109 infprintf (is, "UNKNOWN");
1110 }
1111
1112 if (uval & 0x10) /* For ra. */
1113 {
1114 if (s_reg_encode == 0)
1115 infprintf (is, "%s", mips_gpr_names[31]);
1116 else
1117 infprintf (is, ",%s", mips_gpr_names[31]);
1118 }
1119 }
1120 break;
1121
1122 case OP_ENTRY_EXIT_LIST:
1123 {
1124 const char *sep;
1125 unsigned int amask, smask;
1126
1127 sep = "";
1128 amask = (uval >> 3) & 7;
1129 if (amask > 0 && amask < 5)
1130 {
1131 infprintf (is, "%s", mips_gpr_names[4]);
1132 if (amask > 1)
1133 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1134 sep = ",";
1135 }
1136
1137 smask = (uval >> 1) & 3;
1138 if (smask == 3)
1139 {
1140 infprintf (is, "%s??", sep);
1141 sep = ",";
1142 }
1143 else if (smask > 0)
1144 {
1145 infprintf (is, "%s%s", sep, mips_gpr_names[16]);
1146 if (smask > 1)
1147 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1148 sep = ",";
1149 }
1150
1151 if (uval & 1)
1152 {
1153 infprintf (is, "%s%s", sep, mips_gpr_names[31]);
1154 sep = ",";
1155 }
1156
1157 if (amask == 5 || amask == 6)
1158 {
1159 infprintf (is, "%s%s", sep, mips_fpr_names[0]);
1160 if (amask == 6)
1161 infprintf (is, "-%s", mips_fpr_names[1]);
1162 }
1163 }
1164 break;
1165
1166 case OP_SAVE_RESTORE_LIST:
1167 /* Should be handled by the caller due to extend behavior. */
1168 abort ();
1169
1170 case OP_MDMX_IMM_REG:
1171 {
1172 unsigned int vsel;
1173
1174 vsel = uval >> 5;
1175 uval &= 31;
1176 if ((vsel & 0x10) == 0)
1177 {
1178 int fmt;
1179
1180 vsel &= 0x0f;
1181 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1182 if ((vsel & 1) == 0)
1183 break;
1184 print_reg (info, opcode, OP_REG_VEC, uval);
1185 infprintf (is, "[%d]", vsel >> 1);
1186 }
1187 else if ((vsel & 0x08) == 0)
1188 print_reg (info, opcode, OP_REG_VEC, uval);
1189 else
1190 infprintf (is, "0x%x", uval);
1191 }
1192 break;
1193
1194 case OP_REPEAT_PREV_REG:
1195 print_reg (info, opcode, state->last_reg_type, state->last_regno);
1196 break;
1197
1198 case OP_REPEAT_DEST_REG:
1199 /* Should always match OP_REPEAT_PREV_REG first. */
1200 abort ();
1201
1202 case OP_PC:
1203 infprintf (is, "$pc");
1204 break;
1205 }
1206 }
1207
1208 /* Print the arguments for INSN, which is described by OPCODE.
1209 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC
1210 as the base of OP_PCREL operands. */
1211
1212 static void
1213 print_insn_args (struct disassemble_info *info,
1214 const struct mips_opcode *opcode,
1215 const struct mips_operand *(*decode_operand) (const char *),
1216 unsigned int insn, bfd_vma base_pc)
1217 {
1218 const fprintf_ftype infprintf = info->fprintf_func;
1219 void *is = info->stream;
1220 struct mips_print_arg_state state;
1221 const struct mips_operand *operand;
1222 const char *s;
1223
1224 init_print_arg_state (&state);
1225 for (s = opcode->args; *s; ++s)
1226 {
1227 switch (*s)
1228 {
1229 case ',':
1230 case '(':
1231 case ')':
1232 infprintf (is, "%c", *s);
1233 break;
1234
1235 default:
1236 operand = decode_operand (s);
1237 if (!operand)
1238 {
1239 /* xgettext:c-format */
1240 infprintf (is,
1241 _("# internal error, undefined operand in `%s %s'"),
1242 opcode->name, opcode->args);
1243 return;
1244 }
1245 if (operand->type == OP_REG
1246 && s[1] == ','
1247 && s[2] == 'H'
1248 && opcode->name[strlen (opcode->name) - 1] == '0')
1249 {
1250 /* Coprocessor register 0 with sel field (MT ASE). */
1251 const struct mips_cp0sel_name *n;
1252 unsigned int reg, sel;
1253
1254 reg = mips_extract_operand (operand, insn);
1255 s += 2;
1256 operand = decode_operand (s);
1257 sel = mips_extract_operand (operand, insn);
1258
1259 /* CP0 register including 'sel' code for mftc0, to be
1260 printed textually if known. If not known, print both
1261 CP0 register name and sel numerically since CP0 register
1262 with sel 0 may have a name unrelated to register being
1263 printed. */
1264 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
1265 mips_cp0sel_names_len,
1266 reg, sel);
1267 if (n != NULL)
1268 infprintf (is, "%s", n->name);
1269 else
1270 infprintf (is, "$%d,%d", reg, sel);
1271 }
1272 else
1273 print_insn_arg (info, &state, opcode, operand, base_pc,
1274 mips_extract_operand (operand, insn));
1275 if (*s == 'm' || *s == '+')
1276 ++s;
1277 break;
1278 }
1279 }
1280 }
1281 \f
1282 /* Print the mips instruction at address MEMADDR in debugged memory,
1283 on using INFO. Returns length of the instruction, in bytes, which is
1284 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1285 this is little-endian code. */
1286
1287 static int
1288 print_insn_mips (bfd_vma memaddr,
1289 int word,
1290 struct disassemble_info *info)
1291 {
1292 #define GET_OP(insn, field) \
1293 (((insn) >> OP_SH_##field) & OP_MASK_##field)
1294 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1295 const fprintf_ftype infprintf = info->fprintf_func;
1296 const struct mips_opcode *op;
1297 static bfd_boolean init = 0;
1298 void *is = info->stream;
1299
1300 /* Build a hash table to shorten the search time. */
1301 if (! init)
1302 {
1303 unsigned int i;
1304
1305 for (i = 0; i <= OP_MASK_OP; i++)
1306 {
1307 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1308 {
1309 if (op->pinfo == INSN_MACRO
1310 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1311 continue;
1312 if (i == GET_OP (op->match, OP))
1313 {
1314 mips_hash[i] = op;
1315 break;
1316 }
1317 }
1318 }
1319
1320 init = 1;
1321 }
1322
1323 info->bytes_per_chunk = INSNLEN;
1324 info->display_endian = info->endian;
1325 info->insn_info_valid = 1;
1326 info->branch_delay_insns = 0;
1327 info->data_size = 0;
1328 info->insn_type = dis_nonbranch;
1329 info->target = 0;
1330 info->target2 = 0;
1331
1332 op = mips_hash[GET_OP (word, OP)];
1333 if (op != NULL)
1334 {
1335 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1336 {
1337 if (op->pinfo != INSN_MACRO
1338 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1339 && (word & op->mask) == op->match)
1340 {
1341 /* We always allow to disassemble the jalx instruction. */
1342 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
1343 && strcmp (op->name, "jalx"))
1344 continue;
1345
1346 /* Figure out instruction type and branch delay information. */
1347 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1348 {
1349 if ((op->pinfo & (INSN_WRITE_GPR_31
1350 | INSN_WRITE_GPR_D)) != 0)
1351 info->insn_type = dis_jsr;
1352 else
1353 info->insn_type = dis_branch;
1354 info->branch_delay_insns = 1;
1355 }
1356 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1357 | INSN_COND_BRANCH_LIKELY)) != 0)
1358 {
1359 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1360 info->insn_type = dis_condjsr;
1361 else
1362 info->insn_type = dis_condbranch;
1363 info->branch_delay_insns = 1;
1364 }
1365 else if ((op->pinfo & (INSN_STORE_MEMORY
1366 | INSN_LOAD_MEMORY_DELAY)) != 0)
1367 info->insn_type = dis_dref;
1368
1369 infprintf (is, "%s", op->name);
1370
1371 if (op->args[0])
1372 {
1373 infprintf (is, "\t");
1374 print_insn_args (info, op, decode_mips_operand, word,
1375 memaddr + 4);
1376 }
1377
1378 return INSNLEN;
1379 }
1380 }
1381 }
1382 #undef GET_OP
1383
1384 /* Handle undefined instructions. */
1385 info->insn_type = dis_noninsn;
1386 infprintf (is, "0x%x", word);
1387 return INSNLEN;
1388 }
1389 \f
1390 /* Disassemble an operand for a mips16 instruction. */
1391
1392 static void
1393 print_mips16_insn_arg (struct disassemble_info *info,
1394 struct mips_print_arg_state *state,
1395 const struct mips_opcode *opcode,
1396 char type, bfd_vma memaddr,
1397 unsigned insn, bfd_boolean use_extend,
1398 unsigned extend, bfd_boolean is_offset)
1399 {
1400 const fprintf_ftype infprintf = info->fprintf_func;
1401 void *is = info->stream;
1402 const struct mips_operand *operand, *ext_operand;
1403 unsigned int uval;
1404 bfd_vma baseaddr;
1405
1406 if (!use_extend)
1407 extend = 0;
1408
1409 switch (type)
1410 {
1411 case ',':
1412 case '(':
1413 case ')':
1414 infprintf (is, "%c", type);
1415 break;
1416
1417 default:
1418 operand = decode_mips16_operand (type, FALSE);
1419 if (!operand)
1420 {
1421 /* xgettext:c-format */
1422 infprintf (is, _("# internal error, undefined operand in `%s %s'"),
1423 opcode->name, opcode->args);
1424 return;
1425 }
1426
1427 if (operand->type == OP_SAVE_RESTORE_LIST)
1428 {
1429 /* Handle this case here because of the complex interation
1430 with the EXTEND opcode. */
1431 unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j;
1432 const char *sep;
1433
1434 amask = extend & 0xf;
1435 if (amask == MIPS16_ALL_ARGS)
1436 {
1437 nargs = 4;
1438 nstatics = 0;
1439 }
1440 else if (amask == MIPS16_ALL_STATICS)
1441 {
1442 nargs = 0;
1443 nstatics = 4;
1444 }
1445 else
1446 {
1447 nargs = amask >> 2;
1448 nstatics = amask & 3;
1449 }
1450
1451 sep = "";
1452 if (nargs > 0)
1453 {
1454 infprintf (is, "%s", mips_gpr_names[4]);
1455 if (nargs > 1)
1456 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
1457 sep = ",";
1458 }
1459
1460 frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
1461 if (frame_size == 0 && !use_extend)
1462 frame_size = 128;
1463 infprintf (is, "%s%d", sep, frame_size);
1464
1465 if (insn & 0x40) /* $ra */
1466 infprintf (is, ",%s", mips_gpr_names[31]);
1467
1468 nsreg = (extend >> 8) & 0x7;
1469 smask = 0;
1470 if (insn & 0x20) /* $s0 */
1471 smask |= 1 << 0;
1472 if (insn & 0x10) /* $s1 */
1473 smask |= 1 << 1;
1474 if (nsreg > 0) /* $s2-$s8 */
1475 smask |= ((1 << nsreg) - 1) << 2;
1476
1477 for (i = 0; i < 9; i++)
1478 if (smask & (1 << i))
1479 {
1480 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1481 /* Skip over string of set bits. */
1482 for (j = i; smask & (2 << j); j++)
1483 continue;
1484 if (j > i)
1485 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1486 i = j + 1;
1487 }
1488 /* Statics $ax - $a3. */
1489 if (nstatics == 1)
1490 infprintf (is, ",%s", mips_gpr_names[7]);
1491 else if (nstatics > 0)
1492 infprintf (is, ",%s-%s",
1493 mips_gpr_names[7 - nstatics + 1],
1494 mips_gpr_names[7]);
1495 break;
1496 }
1497
1498 if (is_offset && operand->type == OP_INT)
1499 {
1500 const struct mips_int_operand *int_op;
1501
1502 int_op = (const struct mips_int_operand *) operand;
1503 info->insn_type = dis_dref;
1504 info->data_size = 1 << int_op->shift;
1505 }
1506
1507 if (operand->size == 26)
1508 /* In this case INSN is the first two bytes of the instruction
1509 and EXTEND is the second two bytes. */
1510 uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend;
1511 else
1512 {
1513 /* Calculate the full field value. */
1514 uval = mips_extract_operand (operand, insn);
1515 if (use_extend)
1516 {
1517 ext_operand = decode_mips16_operand (type, TRUE);
1518 if (ext_operand != operand)
1519 {
1520 operand = ext_operand;
1521 if (operand->size == 16)
1522 uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1523 else if (operand->size == 15)
1524 uval |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1525 else
1526 uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
1527 }
1528 }
1529 }
1530
1531 baseaddr = memaddr + 2;
1532 if (operand->type == OP_PCREL)
1533 {
1534 const struct mips_pcrel_operand *pcrel_op;
1535
1536 pcrel_op = (const struct mips_pcrel_operand *) operand;
1537 if (!pcrel_op->include_isa_bit && use_extend)
1538 baseaddr = memaddr - 2;
1539 else if (!pcrel_op->include_isa_bit)
1540 {
1541 bfd_byte buffer[2];
1542
1543 /* If this instruction is in the delay slot of a JR
1544 instruction, the base address is the address of the
1545 JR instruction. If it is in the delay slot of a JALR
1546 instruction, the base address is the address of the
1547 JALR instruction. This test is unreliable: we have
1548 no way of knowing whether the previous word is
1549 instruction or data. */
1550 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
1551 && (((info->endian == BFD_ENDIAN_BIG
1552 ? bfd_getb16 (buffer)
1553 : bfd_getl16 (buffer))
1554 & 0xf800) == 0x1800))
1555 baseaddr = memaddr - 4;
1556 else if (info->read_memory_func (memaddr - 2, buffer, 2,
1557 info) == 0
1558 && (((info->endian == BFD_ENDIAN_BIG
1559 ? bfd_getb16 (buffer)
1560 : bfd_getl16 (buffer))
1561 & 0xf81f) == 0xe800))
1562 baseaddr = memaddr - 2;
1563 else
1564 baseaddr = memaddr;
1565 }
1566 }
1567
1568 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);
1569 break;
1570 }
1571 }
1572
1573
1574 /* Check if the given address is the last word of a MIPS16 PLT entry.
1575 This word is data and depending on the value it may interfere with
1576 disassembly of further PLT entries. We make use of the fact PLT
1577 symbols are marked BSF_SYNTHETIC. */
1578 static bfd_boolean
1579 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
1580 {
1581 if (info->symbols
1582 && info->symbols[0]
1583 && (info->symbols[0]->flags & BSF_SYNTHETIC)
1584 && addr == bfd_asymbol_value (info->symbols[0]) + 12)
1585 return TRUE;
1586
1587 return FALSE;
1588 }
1589
1590 /* Disassemble mips16 instructions. */
1591
1592 static int
1593 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1594 {
1595 const fprintf_ftype infprintf = info->fprintf_func;
1596 int status;
1597 bfd_byte buffer[4];
1598 int length;
1599 int insn;
1600 bfd_boolean use_extend;
1601 int extend = 0;
1602 const struct mips_opcode *op, *opend;
1603 struct mips_print_arg_state state;
1604 void *is = info->stream;
1605
1606 info->bytes_per_chunk = 2;
1607 info->display_endian = info->endian;
1608 info->insn_info_valid = 1;
1609 info->branch_delay_insns = 0;
1610 info->data_size = 0;
1611 info->target = 0;
1612 info->target2 = 0;
1613
1614 #define GET_OP(insn, field) \
1615 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1616 /* Decode PLT entry's GOT slot address word. */
1617 if (is_mips16_plt_tail (info, memaddr))
1618 {
1619 info->insn_type = dis_noninsn;
1620 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1621 if (status == 0)
1622 {
1623 unsigned int gotslot;
1624
1625 if (info->endian == BFD_ENDIAN_BIG)
1626 gotslot = bfd_getb32 (buffer);
1627 else
1628 gotslot = bfd_getl32 (buffer);
1629 infprintf (is, ".word\t0x%x", gotslot);
1630
1631 return 4;
1632 }
1633 }
1634 else
1635 {
1636 info->insn_type = dis_nonbranch;
1637 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1638 }
1639 if (status != 0)
1640 {
1641 (*info->memory_error_func) (status, memaddr, info);
1642 return -1;
1643 }
1644
1645 length = 2;
1646
1647 if (info->endian == BFD_ENDIAN_BIG)
1648 insn = bfd_getb16 (buffer);
1649 else
1650 insn = bfd_getl16 (buffer);
1651
1652 /* Handle the extend opcode specially. */
1653 use_extend = FALSE;
1654 if ((insn & 0xf800) == 0xf000)
1655 {
1656 use_extend = TRUE;
1657 extend = insn & 0x7ff;
1658
1659 memaddr += 2;
1660
1661 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1662 if (status != 0)
1663 {
1664 infprintf (is, "extend 0x%x", (unsigned int) extend);
1665 (*info->memory_error_func) (status, memaddr, info);
1666 return -1;
1667 }
1668
1669 if (info->endian == BFD_ENDIAN_BIG)
1670 insn = bfd_getb16 (buffer);
1671 else
1672 insn = bfd_getl16 (buffer);
1673
1674 /* Check for an extend opcode followed by an extend opcode. */
1675 if ((insn & 0xf800) == 0xf000)
1676 {
1677 infprintf (is, "extend 0x%x", (unsigned int) extend);
1678 info->insn_type = dis_noninsn;
1679 return length;
1680 }
1681
1682 length += 2;
1683 }
1684
1685 /* FIXME: Should probably use a hash table on the major opcode here. */
1686
1687 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1688 for (op = mips16_opcodes; op < opend; op++)
1689 {
1690 if (op->pinfo != INSN_MACRO
1691 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1692 && (insn & op->mask) == op->match)
1693 {
1694 const char *s;
1695
1696 if (op->args[0] == 'a' || op->args[0] == 'i')
1697 {
1698 if (use_extend)
1699 {
1700 infprintf (is, "extend 0x%x", (unsigned int) extend);
1701 info->insn_type = dis_noninsn;
1702 return length - 2;
1703 }
1704
1705 use_extend = FALSE;
1706
1707 memaddr += 2;
1708
1709 status = (*info->read_memory_func) (memaddr, buffer, 2,
1710 info);
1711 if (status == 0)
1712 {
1713 use_extend = TRUE;
1714 if (info->endian == BFD_ENDIAN_BIG)
1715 extend = bfd_getb16 (buffer);
1716 else
1717 extend = bfd_getl16 (buffer);
1718 length += 2;
1719 }
1720 }
1721
1722 infprintf (is, "%s", op->name);
1723 if (op->args[0] != '\0')
1724 infprintf (is, "\t");
1725
1726 init_print_arg_state (&state);
1727 for (s = op->args; *s != '\0'; s++)
1728 {
1729 if (*s == ','
1730 && s[1] == 'w'
1731 && GET_OP (insn, RX) == GET_OP (insn, RY))
1732 {
1733 /* Skip the register and the comma. */
1734 ++s;
1735 continue;
1736 }
1737 if (*s == ','
1738 && s[1] == 'v'
1739 && GET_OP (insn, RZ) == GET_OP (insn, RX))
1740 {
1741 /* Skip the register and the comma. */
1742 ++s;
1743 continue;
1744 }
1745 print_mips16_insn_arg (info, &state, op, *s, memaddr, insn,
1746 use_extend, extend, s[1] == '(');
1747 }
1748
1749 /* Figure out branch instruction type and delay slot information. */
1750 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1751 info->branch_delay_insns = 1;
1752 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
1753 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
1754 {
1755 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1756 info->insn_type = dis_jsr;
1757 else
1758 info->insn_type = dis_branch;
1759 }
1760 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
1761 info->insn_type = dis_condbranch;
1762
1763 return length;
1764 }
1765 }
1766 #undef GET_OP
1767
1768 if (use_extend)
1769 infprintf (is, "0x%x", extend | 0xf000);
1770 infprintf (is, "0x%x", insn);
1771 info->insn_type = dis_noninsn;
1772
1773 return length;
1774 }
1775
1776 /* Disassemble microMIPS instructions. */
1777
1778 static int
1779 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
1780 {
1781 const fprintf_ftype infprintf = info->fprintf_func;
1782 const struct mips_opcode *op, *opend;
1783 void *is = info->stream;
1784 bfd_byte buffer[2];
1785 unsigned int higher;
1786 unsigned int length;
1787 int status;
1788 unsigned int insn;
1789
1790 info->bytes_per_chunk = 2;
1791 info->display_endian = info->endian;
1792 info->insn_info_valid = 1;
1793 info->branch_delay_insns = 0;
1794 info->data_size = 0;
1795 info->insn_type = dis_nonbranch;
1796 info->target = 0;
1797 info->target2 = 0;
1798
1799 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1800 if (status != 0)
1801 {
1802 (*info->memory_error_func) (status, memaddr, info);
1803 return -1;
1804 }
1805
1806 length = 2;
1807
1808 if (info->endian == BFD_ENDIAN_BIG)
1809 insn = bfd_getb16 (buffer);
1810 else
1811 insn = bfd_getl16 (buffer);
1812
1813 if ((insn & 0xfc00) == 0x7c00)
1814 {
1815 /* This is a 48-bit microMIPS instruction. */
1816 higher = insn;
1817
1818 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
1819 if (status != 0)
1820 {
1821 infprintf (is, "micromips 0x%x", higher);
1822 (*info->memory_error_func) (status, memaddr + 2, info);
1823 return -1;
1824 }
1825 if (info->endian == BFD_ENDIAN_BIG)
1826 insn = bfd_getb16 (buffer);
1827 else
1828 insn = bfd_getl16 (buffer);
1829 higher = (higher << 16) | insn;
1830
1831 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
1832 if (status != 0)
1833 {
1834 infprintf (is, "micromips 0x%x", higher);
1835 (*info->memory_error_func) (status, memaddr + 4, info);
1836 return -1;
1837 }
1838 if (info->endian == BFD_ENDIAN_BIG)
1839 insn = bfd_getb16 (buffer);
1840 else
1841 insn = bfd_getl16 (buffer);
1842 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
1843
1844 info->insn_type = dis_noninsn;
1845 return 6;
1846 }
1847 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
1848 {
1849 /* This is a 32-bit microMIPS instruction. */
1850 higher = insn;
1851
1852 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
1853 if (status != 0)
1854 {
1855 infprintf (is, "micromips 0x%x", higher);
1856 (*info->memory_error_func) (status, memaddr + 2, info);
1857 return -1;
1858 }
1859
1860 if (info->endian == BFD_ENDIAN_BIG)
1861 insn = bfd_getb16 (buffer);
1862 else
1863 insn = bfd_getl16 (buffer);
1864
1865 insn = insn | (higher << 16);
1866
1867 length += 2;
1868 }
1869
1870 /* FIXME: Should probably use a hash table on the major opcode here. */
1871
1872 opend = micromips_opcodes + bfd_micromips_num_opcodes;
1873 for (op = micromips_opcodes; op < opend; op++)
1874 {
1875 if (op->pinfo != INSN_MACRO
1876 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1877 && (insn & op->mask) == op->match
1878 && ((length == 2 && (op->mask & 0xffff0000) == 0)
1879 || (length == 4 && (op->mask & 0xffff0000) != 0)))
1880 {
1881 infprintf (is, "%s", op->name);
1882
1883 if (op->args[0])
1884 {
1885 infprintf (is, "\t");
1886 print_insn_args (info, op, decode_micromips_operand, insn,
1887 memaddr + length + 1);
1888 }
1889
1890 /* Figure out instruction type and branch delay information. */
1891 if ((op->pinfo
1892 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
1893 info->branch_delay_insns = 1;
1894 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
1895 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
1896 {
1897 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
1898 info->insn_type = dis_jsr;
1899 else
1900 info->insn_type = dis_branch;
1901 }
1902 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
1903 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
1904 {
1905 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1906 info->insn_type = dis_condjsr;
1907 else
1908 info->insn_type = dis_condbranch;
1909 }
1910 else if ((op->pinfo
1911 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
1912 info->insn_type = dis_dref;
1913
1914 return length;
1915 }
1916 }
1917
1918 infprintf (is, "0x%x", insn);
1919 info->insn_type = dis_noninsn;
1920
1921 return length;
1922 }
1923
1924 /* Return 1 if a symbol associated with the location being disassembled
1925 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
1926 all the symbols at the address being considered assuming if at least
1927 one of them indicates code compression, then such code has been
1928 genuinely produced here (other symbols could have been derived from
1929 function symbols defined elsewhere or could define data). Otherwise,
1930 return 0. */
1931
1932 static bfd_boolean
1933 is_compressed_mode_p (struct disassemble_info *info)
1934 {
1935 int i;
1936 int l;
1937
1938 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
1939 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
1940 && ((!micromips_ase
1941 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
1942 || (micromips_ase
1943 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
1944 return 1;
1945 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
1946 && info->symtab[i]->section == info->section)
1947 {
1948 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
1949 if ((!micromips_ase
1950 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
1951 || (micromips_ase
1952 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
1953 return 1;
1954 }
1955
1956 return 0;
1957 }
1958
1959 /* In an environment where we do not know the symbol type of the
1960 instruction we are forced to assume that the low order bit of the
1961 instructions' address may mark it as a mips16 instruction. If we
1962 are single stepping, or the pc is within the disassembled function,
1963 this works. Otherwise, we need a clue. Sometimes. */
1964
1965 static int
1966 _print_insn_mips (bfd_vma memaddr,
1967 struct disassemble_info *info,
1968 enum bfd_endian endianness)
1969 {
1970 int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
1971 bfd_byte buffer[INSNLEN];
1972 int status;
1973
1974 set_default_mips_dis_options (info);
1975 parse_mips_dis_options (info->disassembler_options);
1976
1977 if (info->mach == bfd_mach_mips16)
1978 return print_insn_mips16 (memaddr, info);
1979 if (info->mach == bfd_mach_mips_micromips)
1980 return print_insn_micromips (memaddr, info);
1981
1982 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
1983
1984 #if 1
1985 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
1986 /* Only a few tools will work this way. */
1987 if (memaddr & 0x01)
1988 return print_insn_compr (memaddr, info);
1989 #endif
1990
1991 #if SYMTAB_AVAILABLE
1992 if (is_compressed_mode_p (info))
1993 return print_insn_compr (memaddr, info);
1994 #endif
1995
1996 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1997 if (status == 0)
1998 {
1999 int insn;
2000
2001 if (endianness == BFD_ENDIAN_BIG)
2002 insn = bfd_getb32 (buffer);
2003 else
2004 insn = bfd_getl32 (buffer);
2005
2006 return print_insn_mips (memaddr, insn, info);
2007 }
2008 else
2009 {
2010 (*info->memory_error_func) (status, memaddr, info);
2011 return -1;
2012 }
2013 }
2014
2015 int
2016 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2017 {
2018 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2019 }
2020
2021 int
2022 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2023 {
2024 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2025 }
2026 \f
2027 void
2028 print_mips_disassembler_options (FILE *stream)
2029 {
2030 unsigned int i;
2031
2032 fprintf (stream, _("\n\
2033 The following MIPS specific disassembler options are supported for use\n\
2034 with the -M switch (multiple options should be separated by commas):\n"));
2035
2036 fprintf (stream, _("\n\
2037 virt Recognize the virtualization ASE instructions.\n"));
2038
2039 fprintf (stream, _("\n\
2040 gpr-names=ABI Print GPR names according to specified ABI.\n\
2041 Default: based on binary being disassembled.\n"));
2042
2043 fprintf (stream, _("\n\
2044 fpr-names=ABI Print FPR names according to specified ABI.\n\
2045 Default: numeric.\n"));
2046
2047 fprintf (stream, _("\n\
2048 cp0-names=ARCH Print CP0 register names according to\n\
2049 specified architecture.\n\
2050 Default: based on binary being disassembled.\n"));
2051
2052 fprintf (stream, _("\n\
2053 hwr-names=ARCH Print HWR names according to specified \n\
2054 architecture.\n\
2055 Default: based on binary being disassembled.\n"));
2056
2057 fprintf (stream, _("\n\
2058 reg-names=ABI Print GPR and FPR names according to\n\
2059 specified ABI.\n"));
2060
2061 fprintf (stream, _("\n\
2062 reg-names=ARCH Print CP0 register and HWR names according to\n\
2063 specified architecture.\n"));
2064
2065 fprintf (stream, _("\n\
2066 For the options above, the following values are supported for \"ABI\":\n\
2067 "));
2068 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2069 fprintf (stream, " %s", mips_abi_choices[i].name);
2070 fprintf (stream, _("\n"));
2071
2072 fprintf (stream, _("\n\
2073 For the options above, The following values are supported for \"ARCH\":\n\
2074 "));
2075 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2076 if (*mips_arch_choices[i].name != '\0')
2077 fprintf (stream, " %s", mips_arch_choices[i].name);
2078 fprintf (stream, _("\n"));
2079
2080 fprintf (stream, _("\n"));
2081 }
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