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1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 /* Xlr cop0 register names. */
323 static const char * const mips_cp0_names_xlr[32] = {
324 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
325 "c0_context", "c0_pagemask", "c0_wired", "$7",
326 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
327 "c0_status", "c0_cause", "c0_epc", "c0_prid",
328 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
329 "c0_xcontext", "$21", "$22", "c0_debug",
330 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
331 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
332 };
333
334 /* XLR's CP0 Select Registers. */
335
336 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
337 { 9, 6, "c0_extintreq" },
338 { 9, 7, "c0_extintmask" },
339 { 15, 1, "c0_ebase" },
340 { 16, 1, "c0_config1" },
341 { 16, 2, "c0_config2" },
342 { 16, 3, "c0_config3" },
343 { 16, 7, "c0_procid2" },
344 { 18, 1, "c0_watchlo,1" },
345 { 18, 2, "c0_watchlo,2" },
346 { 18, 3, "c0_watchlo,3" },
347 { 18, 4, "c0_watchlo,4" },
348 { 18, 5, "c0_watchlo,5" },
349 { 18, 6, "c0_watchlo,6" },
350 { 18, 7, "c0_watchlo,7" },
351 { 19, 1, "c0_watchhi,1" },
352 { 19, 2, "c0_watchhi,2" },
353 { 19, 3, "c0_watchhi,3" },
354 { 19, 4, "c0_watchhi,4" },
355 { 19, 5, "c0_watchhi,5" },
356 { 19, 6, "c0_watchhi,6" },
357 { 19, 7, "c0_watchhi,7" },
358 { 25, 1, "c0_perfcnt,1" },
359 { 25, 2, "c0_perfcnt,2" },
360 { 25, 3, "c0_perfcnt,3" },
361 { 25, 4, "c0_perfcnt,4" },
362 { 25, 5, "c0_perfcnt,5" },
363 { 25, 6, "c0_perfcnt,6" },
364 { 25, 7, "c0_perfcnt,7" },
365 { 27, 1, "c0_cacheerr,1" },
366 { 27, 2, "c0_cacheerr,2" },
367 { 27, 3, "c0_cacheerr,3" },
368 { 28, 1, "c0_datalo" },
369 { 29, 1, "c0_datahi" }
370 };
371
372 static const char * const mips_hwr_names_numeric[32] =
373 {
374 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
375 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
376 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
377 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
378 };
379
380 static const char * const mips_hwr_names_mips3264r2[32] =
381 {
382 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
383 "$4", "$5", "$6", "$7",
384 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
385 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
386 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
387 };
388
389 struct mips_abi_choice
390 {
391 const char * name;
392 const char * const *gpr_names;
393 const char * const *fpr_names;
394 };
395
396 struct mips_abi_choice mips_abi_choices[] =
397 {
398 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
399 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
400 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
401 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
402 };
403
404 struct mips_arch_choice
405 {
406 const char *name;
407 int bfd_mach_valid;
408 unsigned long bfd_mach;
409 int processor;
410 int isa;
411 const char * const *cp0_names;
412 const struct mips_cp0sel_name *cp0sel_names;
413 unsigned int cp0sel_names_len;
414 const char * const *hwr_names;
415 };
416
417 const struct mips_arch_choice mips_arch_choices[] =
418 {
419 { "numeric", 0, 0, 0, 0,
420 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
421
422 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
423 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
424 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
425 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
426 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
427 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
428 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
429 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
430 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
431 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
432 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
433 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
434 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
435 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
436 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
437 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
438 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
439 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
440 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
441 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
443 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
444 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
445 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
447 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
449 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
451 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
453 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
455 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
456 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
457 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
459 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
461 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
463 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
465 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
467 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
468
469 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
470 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
471 _MIPS32 Architecture For Programmers Volume I: Introduction to the
472 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
473 page 1. */
474 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
475 ISA_MIPS32 | INSN_SMARTMIPS,
476 mips_cp0_names_mips3264,
477 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
478 mips_hwr_names_numeric },
479
480 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
481 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
482 | INSN_MIPS3D | INSN_MT),
483 mips_cp0_names_mips3264r2,
484 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
485 mips_hwr_names_mips3264r2 },
486
487 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
488 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
489 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
490 mips_cp0_names_mips3264,
491 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
492 mips_hwr_names_numeric },
493
494 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
495 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
496 | INSN_DSP64 | INSN_MT | INSN_MDMX),
497 mips_cp0_names_mips3264r2,
498 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
499 mips_hwr_names_mips3264r2 },
500
501 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
502 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
503 mips_cp0_names_sb1,
504 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
505 mips_hwr_names_numeric },
506
507 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
508 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
509 NULL, 0, mips_hwr_names_numeric },
510
511 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
512 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
513 NULL, 0, mips_hwr_names_numeric },
514
515 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
516 ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
517 NULL, 0, mips_hwr_names_numeric },
518
519 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
520 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
521 mips_hwr_names_numeric },
522
523 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
524 ISA_MIPS64 | INSN_XLR,
525 mips_cp0_names_xlr,
526 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
527 mips_hwr_names_numeric },
528
529 /* This entry, mips16, is here only for ISA/processor selection; do
530 not print its name. */
531 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
532 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
533 };
534
535 /* ISA and processor type to disassemble for, and register names to use.
536 set_default_mips_dis_options and parse_mips_dis_options fill in these
537 values. */
538 static int mips_processor;
539 static int mips_isa;
540 static const char * const *mips_gpr_names;
541 static const char * const *mips_fpr_names;
542 static const char * const *mips_cp0_names;
543 static const struct mips_cp0sel_name *mips_cp0sel_names;
544 static int mips_cp0sel_names_len;
545 static const char * const *mips_hwr_names;
546
547 /* Other options */
548 static int no_aliases; /* If set disassemble as most general inst. */
549 \f
550 static const struct mips_abi_choice *
551 choose_abi_by_name (const char *name, unsigned int namelen)
552 {
553 const struct mips_abi_choice *c;
554 unsigned int i;
555
556 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
557 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
558 && strlen (mips_abi_choices[i].name) == namelen)
559 c = &mips_abi_choices[i];
560
561 return c;
562 }
563
564 static const struct mips_arch_choice *
565 choose_arch_by_name (const char *name, unsigned int namelen)
566 {
567 const struct mips_arch_choice *c = NULL;
568 unsigned int i;
569
570 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
571 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
572 && strlen (mips_arch_choices[i].name) == namelen)
573 c = &mips_arch_choices[i];
574
575 return c;
576 }
577
578 static const struct mips_arch_choice *
579 choose_arch_by_number (unsigned long mach)
580 {
581 static unsigned long hint_bfd_mach;
582 static const struct mips_arch_choice *hint_arch_choice;
583 const struct mips_arch_choice *c;
584 unsigned int i;
585
586 /* We optimize this because even if the user specifies no
587 flags, this will be done for every instruction! */
588 if (hint_bfd_mach == mach
589 && hint_arch_choice != NULL
590 && hint_arch_choice->bfd_mach == hint_bfd_mach)
591 return hint_arch_choice;
592
593 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
594 {
595 if (mips_arch_choices[i].bfd_mach_valid
596 && mips_arch_choices[i].bfd_mach == mach)
597 {
598 c = &mips_arch_choices[i];
599 hint_bfd_mach = mach;
600 hint_arch_choice = c;
601 }
602 }
603 return c;
604 }
605
606 /* Check if the object uses NewABI conventions. */
607
608 static int
609 is_newabi (Elf_Internal_Ehdr *header)
610 {
611 /* There are no old-style ABIs which use 64-bit ELF. */
612 if (header->e_ident[EI_CLASS] == ELFCLASS64)
613 return 1;
614
615 /* If a 32-bit ELF file, n32 is a new-style ABI. */
616 if ((header->e_flags & EF_MIPS_ABI2) != 0)
617 return 1;
618
619 return 0;
620 }
621
622 static void
623 set_default_mips_dis_options (struct disassemble_info *info)
624 {
625 const struct mips_arch_choice *chosen_arch;
626
627 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
628 and numeric FPR, CP0 register, and HWR names. */
629 mips_isa = ISA_MIPS3;
630 mips_processor = CPU_R3000;
631 mips_gpr_names = mips_gpr_names_oldabi;
632 mips_fpr_names = mips_fpr_names_numeric;
633 mips_cp0_names = mips_cp0_names_numeric;
634 mips_cp0sel_names = NULL;
635 mips_cp0sel_names_len = 0;
636 mips_hwr_names = mips_hwr_names_numeric;
637 no_aliases = 0;
638
639 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
640 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
641 {
642 Elf_Internal_Ehdr *header;
643
644 header = elf_elfheader (info->section->owner);
645 if (is_newabi (header))
646 mips_gpr_names = mips_gpr_names_newabi;
647 }
648
649 /* Set ISA, architecture, and cp0 register names as best we can. */
650 #if ! SYMTAB_AVAILABLE
651 /* This is running out on a target machine, not in a host tool.
652 FIXME: Where does mips_target_info come from? */
653 target_processor = mips_target_info.processor;
654 mips_isa = mips_target_info.isa;
655 #else
656 chosen_arch = choose_arch_by_number (info->mach);
657 if (chosen_arch != NULL)
658 {
659 mips_processor = chosen_arch->processor;
660 mips_isa = chosen_arch->isa;
661 mips_cp0_names = chosen_arch->cp0_names;
662 mips_cp0sel_names = chosen_arch->cp0sel_names;
663 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
664 mips_hwr_names = chosen_arch->hwr_names;
665 }
666 #endif
667 }
668
669 static void
670 parse_mips_dis_option (const char *option, unsigned int len)
671 {
672 unsigned int i, optionlen, vallen;
673 const char *val;
674 const struct mips_abi_choice *chosen_abi;
675 const struct mips_arch_choice *chosen_arch;
676
677 /* Try to match options that are simple flags */
678 if (CONST_STRNEQ (option, "no-aliases"))
679 {
680 no_aliases = 1;
681 return;
682 }
683
684 /* Look for the = that delimits the end of the option name. */
685 for (i = 0; i < len; i++)
686 if (option[i] == '=')
687 break;
688
689 if (i == 0) /* Invalid option: no name before '='. */
690 return;
691 if (i == len) /* Invalid option: no '='. */
692 return;
693 if (i == (len - 1)) /* Invalid option: no value after '='. */
694 return;
695
696 optionlen = i;
697 val = option + (optionlen + 1);
698 vallen = len - (optionlen + 1);
699
700 if (strncmp ("gpr-names", option, optionlen) == 0
701 && strlen ("gpr-names") == optionlen)
702 {
703 chosen_abi = choose_abi_by_name (val, vallen);
704 if (chosen_abi != NULL)
705 mips_gpr_names = chosen_abi->gpr_names;
706 return;
707 }
708
709 if (strncmp ("fpr-names", option, optionlen) == 0
710 && strlen ("fpr-names") == optionlen)
711 {
712 chosen_abi = choose_abi_by_name (val, vallen);
713 if (chosen_abi != NULL)
714 mips_fpr_names = chosen_abi->fpr_names;
715 return;
716 }
717
718 if (strncmp ("cp0-names", option, optionlen) == 0
719 && strlen ("cp0-names") == optionlen)
720 {
721 chosen_arch = choose_arch_by_name (val, vallen);
722 if (chosen_arch != NULL)
723 {
724 mips_cp0_names = chosen_arch->cp0_names;
725 mips_cp0sel_names = chosen_arch->cp0sel_names;
726 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
727 }
728 return;
729 }
730
731 if (strncmp ("hwr-names", option, optionlen) == 0
732 && strlen ("hwr-names") == optionlen)
733 {
734 chosen_arch = choose_arch_by_name (val, vallen);
735 if (chosen_arch != NULL)
736 mips_hwr_names = chosen_arch->hwr_names;
737 return;
738 }
739
740 if (strncmp ("reg-names", option, optionlen) == 0
741 && strlen ("reg-names") == optionlen)
742 {
743 /* We check both ABI and ARCH here unconditionally, so
744 that "numeric" will do the desirable thing: select
745 numeric register names for all registers. Other than
746 that, a given name probably won't match both. */
747 chosen_abi = choose_abi_by_name (val, vallen);
748 if (chosen_abi != NULL)
749 {
750 mips_gpr_names = chosen_abi->gpr_names;
751 mips_fpr_names = chosen_abi->fpr_names;
752 }
753 chosen_arch = choose_arch_by_name (val, vallen);
754 if (chosen_arch != NULL)
755 {
756 mips_cp0_names = chosen_arch->cp0_names;
757 mips_cp0sel_names = chosen_arch->cp0sel_names;
758 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
759 mips_hwr_names = chosen_arch->hwr_names;
760 }
761 return;
762 }
763
764 /* Invalid option. */
765 }
766
767 static void
768 parse_mips_dis_options (const char *options)
769 {
770 const char *option_end;
771
772 if (options == NULL)
773 return;
774
775 while (*options != '\0')
776 {
777 /* Skip empty options. */
778 if (*options == ',')
779 {
780 options++;
781 continue;
782 }
783
784 /* We know that *options is neither NUL or a comma. */
785 option_end = options + 1;
786 while (*option_end != ',' && *option_end != '\0')
787 option_end++;
788
789 parse_mips_dis_option (options, option_end - options);
790
791 /* Go on to the next one. If option_end points to a comma, it
792 will be skipped above. */
793 options = option_end;
794 }
795 }
796
797 static const struct mips_cp0sel_name *
798 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
799 unsigned int len,
800 unsigned int cp0reg,
801 unsigned int sel)
802 {
803 unsigned int i;
804
805 for (i = 0; i < len; i++)
806 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
807 return &names[i];
808 return NULL;
809 }
810 \f
811 /* Print insn arguments for 32/64-bit code. */
812
813 static void
814 print_insn_args (const char *d,
815 register unsigned long int l,
816 bfd_vma pc,
817 struct disassemble_info *info,
818 const struct mips_opcode *opp)
819 {
820 int op, delta;
821 unsigned int lsb, msb, msbd;
822
823 lsb = 0;
824
825 for (; *d != '\0'; d++)
826 {
827 switch (*d)
828 {
829 case ',':
830 case '(':
831 case ')':
832 case '[':
833 case ']':
834 (*info->fprintf_func) (info->stream, "%c", *d);
835 break;
836
837 case '+':
838 /* Extension character; switch for second char. */
839 d++;
840 switch (*d)
841 {
842 case '\0':
843 /* xgettext:c-format */
844 (*info->fprintf_func) (info->stream,
845 _("# internal error, incomplete extension sequence (+)"));
846 return;
847
848 case 'A':
849 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
850 (*info->fprintf_func) (info->stream, "0x%x", lsb);
851 break;
852
853 case 'B':
854 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
855 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
856 break;
857
858 case '1':
859 (*info->fprintf_func) (info->stream, "0x%lx",
860 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
861 break;
862
863 case '2':
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
866 break;
867
868 case '3':
869 (*info->fprintf_func) (info->stream, "0x%lx",
870 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
871 break;
872
873 case '4':
874 (*info->fprintf_func) (info->stream, "0x%lx",
875 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
876 break;
877
878 case 'C':
879 case 'H':
880 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
881 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
882 break;
883
884 case 'D':
885 {
886 const struct mips_cp0sel_name *n;
887 unsigned int cp0reg, sel;
888
889 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
890 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
891
892 /* CP0 register including 'sel' code for mtcN (et al.), to be
893 printed textually if known. If not known, print both
894 CP0 register name and sel numerically since CP0 register
895 with sel 0 may have a name unrelated to register being
896 printed. */
897 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
898 mips_cp0sel_names_len, cp0reg, sel);
899 if (n != NULL)
900 (*info->fprintf_func) (info->stream, "%s", n->name);
901 else
902 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
903 break;
904 }
905
906 case 'E':
907 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
908 (*info->fprintf_func) (info->stream, "0x%x", lsb);
909 break;
910
911 case 'F':
912 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
913 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
914 break;
915
916 case 'G':
917 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
918 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
919 break;
920
921 case 't': /* Coprocessor 0 reg name */
922 (*info->fprintf_func) (info->stream, "%s",
923 mips_cp0_names[(l >> OP_SH_RT) &
924 OP_MASK_RT]);
925 break;
926
927 case 'T': /* Coprocessor 0 reg name */
928 {
929 const struct mips_cp0sel_name *n;
930 unsigned int cp0reg, sel;
931
932 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
933 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
934
935 /* CP0 register including 'sel' code for mftc0, to be
936 printed textually if known. If not known, print both
937 CP0 register name and sel numerically since CP0 register
938 with sel 0 may have a name unrelated to register being
939 printed. */
940 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
941 mips_cp0sel_names_len, cp0reg, sel);
942 if (n != NULL)
943 (*info->fprintf_func) (info->stream, "%s", n->name);
944 else
945 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
946 break;
947 }
948
949 case 'x': /* bbit bit index */
950 (*info->fprintf_func) (info->stream, "0x%lx",
951 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
952 break;
953
954 case 'p': /* cins, cins32, exts and exts32 position */
955 (*info->fprintf_func) (info->stream, "0x%lx",
956 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
957 break;
958
959 case 's': /* cins and exts length-minus-one */
960 (*info->fprintf_func) (info->stream, "0x%lx",
961 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
962 break;
963
964 case 'S': /* cins32 and exts32 length-minus-one field */
965 (*info->fprintf_func) (info->stream, "0x%lx",
966 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
967 break;
968
969 case 'Q': /* seqi/snei immediate field */
970 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
971 /* Sign-extend it. */
972 op = (op ^ 512) - 512;
973 (*info->fprintf_func) (info->stream, "%d", op);
974 break;
975
976 default:
977 /* xgettext:c-format */
978 (*info->fprintf_func) (info->stream,
979 _("# internal error, undefined extension sequence (+%c)"),
980 *d);
981 return;
982 }
983 break;
984
985 case '2':
986 (*info->fprintf_func) (info->stream, "0x%lx",
987 (l >> OP_SH_BP) & OP_MASK_BP);
988 break;
989
990 case '3':
991 (*info->fprintf_func) (info->stream, "0x%lx",
992 (l >> OP_SH_SA3) & OP_MASK_SA3);
993 break;
994
995 case '4':
996 (*info->fprintf_func) (info->stream, "0x%lx",
997 (l >> OP_SH_SA4) & OP_MASK_SA4);
998 break;
999
1000 case '5':
1001 (*info->fprintf_func) (info->stream, "0x%lx",
1002 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
1003 break;
1004
1005 case '6':
1006 (*info->fprintf_func) (info->stream, "0x%lx",
1007 (l >> OP_SH_RS) & OP_MASK_RS);
1008 break;
1009
1010 case '7':
1011 (*info->fprintf_func) (info->stream, "$ac%ld",
1012 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
1013 break;
1014
1015 case '8':
1016 (*info->fprintf_func) (info->stream, "0x%lx",
1017 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
1018 break;
1019
1020 case '9':
1021 (*info->fprintf_func) (info->stream, "$ac%ld",
1022 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
1023 break;
1024
1025 case '0': /* dsp 6-bit signed immediate in bit 20 */
1026 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
1027 if (delta & 0x20) /* test sign bit */
1028 delta |= ~OP_MASK_DSPSFT;
1029 (*info->fprintf_func) (info->stream, "%d", delta);
1030 break;
1031
1032 case ':': /* dsp 7-bit signed immediate in bit 19 */
1033 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
1034 if (delta & 0x40) /* test sign bit */
1035 delta |= ~OP_MASK_DSPSFT_7;
1036 (*info->fprintf_func) (info->stream, "%d", delta);
1037 break;
1038
1039 case '\'':
1040 (*info->fprintf_func) (info->stream, "0x%lx",
1041 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
1042 break;
1043
1044 case '@': /* dsp 10-bit signed immediate in bit 16 */
1045 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
1046 if (delta & 0x200) /* test sign bit */
1047 delta |= ~OP_MASK_IMM10;
1048 (*info->fprintf_func) (info->stream, "%d", delta);
1049 break;
1050
1051 case '!':
1052 (*info->fprintf_func) (info->stream, "%ld",
1053 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
1054 break;
1055
1056 case '$':
1057 (*info->fprintf_func) (info->stream, "%ld",
1058 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
1059 break;
1060
1061 case '*':
1062 (*info->fprintf_func) (info->stream, "$ac%ld",
1063 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1064 break;
1065
1066 case '&':
1067 (*info->fprintf_func) (info->stream, "$ac%ld",
1068 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1069 break;
1070
1071 case 'g':
1072 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1073 (*info->fprintf_func) (info->stream, "$%ld",
1074 (l >> OP_SH_RD) & OP_MASK_RD);
1075 break;
1076
1077 case 's':
1078 case 'b':
1079 case 'r':
1080 case 'v':
1081 (*info->fprintf_func) (info->stream, "%s",
1082 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1083 break;
1084
1085 case 't':
1086 case 'w':
1087 (*info->fprintf_func) (info->stream, "%s",
1088 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1089 break;
1090
1091 case 'i':
1092 case 'u':
1093 (*info->fprintf_func) (info->stream, "0x%lx",
1094 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1095 break;
1096
1097 case 'j': /* Same as i, but sign-extended. */
1098 case 'o':
1099 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1100 if (delta & 0x8000)
1101 delta |= ~0xffff;
1102 (*info->fprintf_func) (info->stream, "%d",
1103 delta);
1104 break;
1105
1106 case 'h':
1107 (*info->fprintf_func) (info->stream, "0x%x",
1108 (unsigned int) ((l >> OP_SH_PREFX)
1109 & OP_MASK_PREFX));
1110 break;
1111
1112 case 'k':
1113 (*info->fprintf_func) (info->stream, "0x%x",
1114 (unsigned int) ((l >> OP_SH_CACHE)
1115 & OP_MASK_CACHE));
1116 break;
1117
1118 case 'a':
1119 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1120 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1121 /* For gdb disassembler, force odd address on jalx. */
1122 if (info->flavour == bfd_target_unknown_flavour
1123 && strcmp (opp->name, "jalx") == 0)
1124 info->target |= 1;
1125 (*info->print_address_func) (info->target, info);
1126 break;
1127
1128 case 'p':
1129 /* Sign extend the displacement. */
1130 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1131 if (delta & 0x8000)
1132 delta |= ~0xffff;
1133 info->target = (delta << 2) + pc + INSNLEN;
1134 (*info->print_address_func) (info->target, info);
1135 break;
1136
1137 case 'd':
1138 (*info->fprintf_func) (info->stream, "%s",
1139 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1140 break;
1141
1142 case 'U':
1143 {
1144 /* First check for both rd and rt being equal. */
1145 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1146 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1147 (*info->fprintf_func) (info->stream, "%s",
1148 mips_gpr_names[reg]);
1149 else
1150 {
1151 /* If one is zero use the other. */
1152 if (reg == 0)
1153 (*info->fprintf_func) (info->stream, "%s",
1154 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1155 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1156 (*info->fprintf_func) (info->stream, "%s",
1157 mips_gpr_names[reg]);
1158 else /* Bogus, result depends on processor. */
1159 (*info->fprintf_func) (info->stream, "%s or %s",
1160 mips_gpr_names[reg],
1161 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1162 }
1163 }
1164 break;
1165
1166 case 'z':
1167 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1168 break;
1169
1170 case '<':
1171 case '1':
1172 (*info->fprintf_func) (info->stream, "0x%lx",
1173 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1174 break;
1175
1176 case 'c':
1177 (*info->fprintf_func) (info->stream, "0x%lx",
1178 (l >> OP_SH_CODE) & OP_MASK_CODE);
1179 break;
1180
1181 case 'q':
1182 (*info->fprintf_func) (info->stream, "0x%lx",
1183 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1184 break;
1185
1186 case 'C':
1187 (*info->fprintf_func) (info->stream, "0x%lx",
1188 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1189 break;
1190
1191 case 'B':
1192 (*info->fprintf_func) (info->stream, "0x%lx",
1193
1194 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1195 break;
1196
1197 case 'J':
1198 (*info->fprintf_func) (info->stream, "0x%lx",
1199 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1200 break;
1201
1202 case 'S':
1203 case 'V':
1204 (*info->fprintf_func) (info->stream, "%s",
1205 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1206 break;
1207
1208 case 'T':
1209 case 'W':
1210 (*info->fprintf_func) (info->stream, "%s",
1211 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1212 break;
1213
1214 case 'D':
1215 (*info->fprintf_func) (info->stream, "%s",
1216 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1217 break;
1218
1219 case 'R':
1220 (*info->fprintf_func) (info->stream, "%s",
1221 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1222 break;
1223
1224 case 'E':
1225 /* Coprocessor register for lwcN instructions, et al.
1226
1227 Note that there is no load/store cp0 instructions, and
1228 that FPU (cp1) instructions disassemble this field using
1229 'T' format. Therefore, until we gain understanding of
1230 cp2 register names, we can simply print the register
1231 numbers. */
1232 (*info->fprintf_func) (info->stream, "$%ld",
1233 (l >> OP_SH_RT) & OP_MASK_RT);
1234 break;
1235
1236 case 'G':
1237 /* Coprocessor register for mtcN instructions, et al. Note
1238 that FPU (cp1) instructions disassemble this field using
1239 'S' format. Therefore, we only need to worry about cp0,
1240 cp2, and cp3. */
1241 op = (l >> OP_SH_OP) & OP_MASK_OP;
1242 if (op == OP_OP_COP0)
1243 (*info->fprintf_func) (info->stream, "%s",
1244 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1245 else
1246 (*info->fprintf_func) (info->stream, "$%ld",
1247 (l >> OP_SH_RD) & OP_MASK_RD);
1248 break;
1249
1250 case 'K':
1251 (*info->fprintf_func) (info->stream, "%s",
1252 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1253 break;
1254
1255 case 'N':
1256 (*info->fprintf_func) (info->stream,
1257 ((opp->pinfo & (FP_D | FP_S)) != 0
1258 ? "$fcc%ld" : "$cc%ld"),
1259 (l >> OP_SH_BCC) & OP_MASK_BCC);
1260 break;
1261
1262 case 'M':
1263 (*info->fprintf_func) (info->stream, "$fcc%ld",
1264 (l >> OP_SH_CCC) & OP_MASK_CCC);
1265 break;
1266
1267 case 'P':
1268 (*info->fprintf_func) (info->stream, "%ld",
1269 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1270 break;
1271
1272 case 'e':
1273 (*info->fprintf_func) (info->stream, "%ld",
1274 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1275 break;
1276
1277 case '%':
1278 (*info->fprintf_func) (info->stream, "%ld",
1279 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1280 break;
1281
1282 case 'H':
1283 (*info->fprintf_func) (info->stream, "%ld",
1284 (l >> OP_SH_SEL) & OP_MASK_SEL);
1285 break;
1286
1287 case 'O':
1288 (*info->fprintf_func) (info->stream, "%ld",
1289 (l >> OP_SH_ALN) & OP_MASK_ALN);
1290 break;
1291
1292 case 'Q':
1293 {
1294 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1295
1296 if ((vsel & 0x10) == 0)
1297 {
1298 int fmt;
1299
1300 vsel &= 0x0f;
1301 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1302 if ((vsel & 1) == 0)
1303 break;
1304 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1305 (l >> OP_SH_FT) & OP_MASK_FT,
1306 vsel >> 1);
1307 }
1308 else if ((vsel & 0x08) == 0)
1309 {
1310 (*info->fprintf_func) (info->stream, "$v%ld",
1311 (l >> OP_SH_FT) & OP_MASK_FT);
1312 }
1313 else
1314 {
1315 (*info->fprintf_func) (info->stream, "0x%lx",
1316 (l >> OP_SH_FT) & OP_MASK_FT);
1317 }
1318 }
1319 break;
1320
1321 case 'X':
1322 (*info->fprintf_func) (info->stream, "$v%ld",
1323 (l >> OP_SH_FD) & OP_MASK_FD);
1324 break;
1325
1326 case 'Y':
1327 (*info->fprintf_func) (info->stream, "$v%ld",
1328 (l >> OP_SH_FS) & OP_MASK_FS);
1329 break;
1330
1331 case 'Z':
1332 (*info->fprintf_func) (info->stream, "$v%ld",
1333 (l >> OP_SH_FT) & OP_MASK_FT);
1334 break;
1335
1336 default:
1337 /* xgettext:c-format */
1338 (*info->fprintf_func) (info->stream,
1339 _("# internal error, undefined modifier (%c)"),
1340 *d);
1341 return;
1342 }
1343 }
1344 }
1345 \f
1346 /* Print the mips instruction at address MEMADDR in debugged memory,
1347 on using INFO. Returns length of the instruction, in bytes, which is
1348 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1349 this is little-endian code. */
1350
1351 static int
1352 print_insn_mips (bfd_vma memaddr,
1353 unsigned long int word,
1354 struct disassemble_info *info)
1355 {
1356 const struct mips_opcode *op;
1357 static bfd_boolean init = 0;
1358 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1359
1360 /* Build a hash table to shorten the search time. */
1361 if (! init)
1362 {
1363 unsigned int i;
1364
1365 for (i = 0; i <= OP_MASK_OP; i++)
1366 {
1367 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1368 {
1369 if (op->pinfo == INSN_MACRO
1370 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1371 continue;
1372 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1373 {
1374 mips_hash[i] = op;
1375 break;
1376 }
1377 }
1378 }
1379
1380 init = 1;
1381 }
1382
1383 info->bytes_per_chunk = INSNLEN;
1384 info->display_endian = info->endian;
1385 info->insn_info_valid = 1;
1386 info->branch_delay_insns = 0;
1387 info->data_size = 0;
1388 info->insn_type = dis_nonbranch;
1389 info->target = 0;
1390 info->target2 = 0;
1391
1392 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1393 if (op != NULL)
1394 {
1395 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1396 {
1397 if (op->pinfo != INSN_MACRO
1398 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1399 && (word & op->mask) == op->match)
1400 {
1401 const char *d;
1402
1403 /* We always allow to disassemble the jalx instruction. */
1404 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1405 && strcmp (op->name, "jalx"))
1406 continue;
1407
1408 /* Figure out instruction type and branch delay information. */
1409 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1410 {
1411 if ((op->pinfo & (INSN_WRITE_GPR_31
1412 | INSN_WRITE_GPR_D)) != 0)
1413 info->insn_type = dis_jsr;
1414 else
1415 info->insn_type = dis_branch;
1416 info->branch_delay_insns = 1;
1417 }
1418 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1419 | INSN_COND_BRANCH_LIKELY)) != 0)
1420 {
1421 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1422 info->insn_type = dis_condjsr;
1423 else
1424 info->insn_type = dis_condbranch;
1425 info->branch_delay_insns = 1;
1426 }
1427 else if ((op->pinfo & (INSN_STORE_MEMORY
1428 | INSN_LOAD_MEMORY_DELAY)) != 0)
1429 info->insn_type = dis_dref;
1430
1431 (*info->fprintf_func) (info->stream, "%s", op->name);
1432
1433 d = op->args;
1434 if (d != NULL && *d != '\0')
1435 {
1436 (*info->fprintf_func) (info->stream, "\t");
1437 print_insn_args (d, word, memaddr, info, op);
1438 }
1439
1440 return INSNLEN;
1441 }
1442 }
1443 }
1444
1445 /* Handle undefined instructions. */
1446 info->insn_type = dis_noninsn;
1447 (*info->fprintf_func) (info->stream, "0x%lx", word);
1448 return INSNLEN;
1449 }
1450 \f
1451 /* Disassemble an operand for a mips16 instruction. */
1452
1453 static void
1454 print_mips16_insn_arg (char type,
1455 const struct mips_opcode *op,
1456 int l,
1457 bfd_boolean use_extend,
1458 int extend,
1459 bfd_vma memaddr,
1460 struct disassemble_info *info)
1461 {
1462 switch (type)
1463 {
1464 case ',':
1465 case '(':
1466 case ')':
1467 (*info->fprintf_func) (info->stream, "%c", type);
1468 break;
1469
1470 case 'y':
1471 case 'w':
1472 (*info->fprintf_func) (info->stream, "%s",
1473 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1474 & MIPS16OP_MASK_RY)));
1475 break;
1476
1477 case 'x':
1478 case 'v':
1479 (*info->fprintf_func) (info->stream, "%s",
1480 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1481 & MIPS16OP_MASK_RX)));
1482 break;
1483
1484 case 'z':
1485 (*info->fprintf_func) (info->stream, "%s",
1486 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1487 & MIPS16OP_MASK_RZ)));
1488 break;
1489
1490 case 'Z':
1491 (*info->fprintf_func) (info->stream, "%s",
1492 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1493 & MIPS16OP_MASK_MOVE32Z)));
1494 break;
1495
1496 case '0':
1497 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1498 break;
1499
1500 case 'S':
1501 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1502 break;
1503
1504 case 'P':
1505 (*info->fprintf_func) (info->stream, "$pc");
1506 break;
1507
1508 case 'R':
1509 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1510 break;
1511
1512 case 'X':
1513 (*info->fprintf_func) (info->stream, "%s",
1514 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1515 & MIPS16OP_MASK_REGR32)]);
1516 break;
1517
1518 case 'Y':
1519 (*info->fprintf_func) (info->stream, "%s",
1520 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1521 break;
1522
1523 case '<':
1524 case '>':
1525 case '[':
1526 case ']':
1527 case '4':
1528 case '5':
1529 case 'H':
1530 case 'W':
1531 case 'D':
1532 case 'j':
1533 case '6':
1534 case '8':
1535 case 'V':
1536 case 'C':
1537 case 'U':
1538 case 'k':
1539 case 'K':
1540 case 'p':
1541 case 'q':
1542 case 'A':
1543 case 'B':
1544 case 'E':
1545 {
1546 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1547
1548 shift = 0;
1549 signedp = 0;
1550 extbits = 16;
1551 pcrel = 0;
1552 extu = 0;
1553 branch = 0;
1554 switch (type)
1555 {
1556 case '<':
1557 nbits = 3;
1558 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1559 extbits = 5;
1560 extu = 1;
1561 break;
1562 case '>':
1563 nbits = 3;
1564 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1565 extbits = 5;
1566 extu = 1;
1567 break;
1568 case '[':
1569 nbits = 3;
1570 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1571 extbits = 6;
1572 extu = 1;
1573 break;
1574 case ']':
1575 nbits = 3;
1576 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1577 extbits = 6;
1578 extu = 1;
1579 break;
1580 case '4':
1581 nbits = 4;
1582 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1583 signedp = 1;
1584 extbits = 15;
1585 break;
1586 case '5':
1587 nbits = 5;
1588 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1589 info->insn_type = dis_dref;
1590 info->data_size = 1;
1591 break;
1592 case 'H':
1593 nbits = 5;
1594 shift = 1;
1595 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1596 info->insn_type = dis_dref;
1597 info->data_size = 2;
1598 break;
1599 case 'W':
1600 nbits = 5;
1601 shift = 2;
1602 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1603 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1604 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1605 {
1606 info->insn_type = dis_dref;
1607 info->data_size = 4;
1608 }
1609 break;
1610 case 'D':
1611 nbits = 5;
1612 shift = 3;
1613 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1614 info->insn_type = dis_dref;
1615 info->data_size = 8;
1616 break;
1617 case 'j':
1618 nbits = 5;
1619 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1620 signedp = 1;
1621 break;
1622 case '6':
1623 nbits = 6;
1624 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1625 break;
1626 case '8':
1627 nbits = 8;
1628 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1629 break;
1630 case 'V':
1631 nbits = 8;
1632 shift = 2;
1633 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1634 /* FIXME: This might be lw, or it might be addiu to $sp or
1635 $pc. We assume it's load. */
1636 info->insn_type = dis_dref;
1637 info->data_size = 4;
1638 break;
1639 case 'C':
1640 nbits = 8;
1641 shift = 3;
1642 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1643 info->insn_type = dis_dref;
1644 info->data_size = 8;
1645 break;
1646 case 'U':
1647 nbits = 8;
1648 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1649 extu = 1;
1650 break;
1651 case 'k':
1652 nbits = 8;
1653 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1654 signedp = 1;
1655 break;
1656 case 'K':
1657 nbits = 8;
1658 shift = 3;
1659 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1660 signedp = 1;
1661 break;
1662 case 'p':
1663 nbits = 8;
1664 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1665 signedp = 1;
1666 pcrel = 1;
1667 branch = 1;
1668 break;
1669 case 'q':
1670 nbits = 11;
1671 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1672 signedp = 1;
1673 pcrel = 1;
1674 branch = 1;
1675 break;
1676 case 'A':
1677 nbits = 8;
1678 shift = 2;
1679 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1680 pcrel = 1;
1681 /* FIXME: This can be lw or la. We assume it is lw. */
1682 info->insn_type = dis_dref;
1683 info->data_size = 4;
1684 break;
1685 case 'B':
1686 nbits = 5;
1687 shift = 3;
1688 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1689 pcrel = 1;
1690 info->insn_type = dis_dref;
1691 info->data_size = 8;
1692 break;
1693 case 'E':
1694 nbits = 5;
1695 shift = 2;
1696 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1697 pcrel = 1;
1698 break;
1699 default:
1700 abort ();
1701 }
1702
1703 if (! use_extend)
1704 {
1705 if (signedp && immed >= (1 << (nbits - 1)))
1706 immed -= 1 << nbits;
1707 immed <<= shift;
1708 if ((type == '<' || type == '>' || type == '[' || type == ']')
1709 && immed == 0)
1710 immed = 8;
1711 }
1712 else
1713 {
1714 if (extbits == 16)
1715 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1716 else if (extbits == 15)
1717 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1718 else
1719 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1720 immed &= (1 << extbits) - 1;
1721 if (! extu && immed >= (1 << (extbits - 1)))
1722 immed -= 1 << extbits;
1723 }
1724
1725 if (! pcrel)
1726 (*info->fprintf_func) (info->stream, "%d", immed);
1727 else
1728 {
1729 bfd_vma baseaddr;
1730
1731 if (branch)
1732 {
1733 immed *= 2;
1734 baseaddr = memaddr + 2;
1735 }
1736 else if (use_extend)
1737 baseaddr = memaddr - 2;
1738 else
1739 {
1740 int status;
1741 bfd_byte buffer[2];
1742
1743 baseaddr = memaddr;
1744
1745 /* If this instruction is in the delay slot of a jr
1746 instruction, the base address is the address of the
1747 jr instruction. If it is in the delay slot of jalr
1748 instruction, the base address is the address of the
1749 jalr instruction. This test is unreliable: we have
1750 no way of knowing whether the previous word is
1751 instruction or data. */
1752 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1753 info);
1754 if (status == 0
1755 && (((info->endian == BFD_ENDIAN_BIG
1756 ? bfd_getb16 (buffer)
1757 : bfd_getl16 (buffer))
1758 & 0xf800) == 0x1800))
1759 baseaddr = memaddr - 4;
1760 else
1761 {
1762 status = (*info->read_memory_func) (memaddr - 2, buffer,
1763 2, info);
1764 if (status == 0
1765 && (((info->endian == BFD_ENDIAN_BIG
1766 ? bfd_getb16 (buffer)
1767 : bfd_getl16 (buffer))
1768 & 0xf81f) == 0xe800))
1769 baseaddr = memaddr - 2;
1770 }
1771 }
1772 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1773 if (pcrel && branch
1774 && info->flavour == bfd_target_unknown_flavour)
1775 /* For gdb disassembler, maintain odd address. */
1776 info->target |= 1;
1777 (*info->print_address_func) (info->target, info);
1778 }
1779 }
1780 break;
1781
1782 case 'a':
1783 {
1784 int jalx = l & 0x400;
1785
1786 if (! use_extend)
1787 extend = 0;
1788 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1789 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1790 /* For gdb disassembler, maintain odd address. */
1791 l |= 1;
1792 }
1793 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1794 (*info->print_address_func) (info->target, info);
1795 break;
1796
1797 case 'l':
1798 case 'L':
1799 {
1800 int need_comma, amask, smask;
1801
1802 need_comma = 0;
1803
1804 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1805
1806 amask = (l >> 3) & 7;
1807
1808 if (amask > 0 && amask < 5)
1809 {
1810 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1811 if (amask > 1)
1812 (*info->fprintf_func) (info->stream, "-%s",
1813 mips_gpr_names[amask + 3]);
1814 need_comma = 1;
1815 }
1816
1817 smask = (l >> 1) & 3;
1818 if (smask == 3)
1819 {
1820 (*info->fprintf_func) (info->stream, "%s??",
1821 need_comma ? "," : "");
1822 need_comma = 1;
1823 }
1824 else if (smask > 0)
1825 {
1826 (*info->fprintf_func) (info->stream, "%s%s",
1827 need_comma ? "," : "",
1828 mips_gpr_names[16]);
1829 if (smask > 1)
1830 (*info->fprintf_func) (info->stream, "-%s",
1831 mips_gpr_names[smask + 15]);
1832 need_comma = 1;
1833 }
1834
1835 if (l & 1)
1836 {
1837 (*info->fprintf_func) (info->stream, "%s%s",
1838 need_comma ? "," : "",
1839 mips_gpr_names[31]);
1840 need_comma = 1;
1841 }
1842
1843 if (amask == 5 || amask == 6)
1844 {
1845 (*info->fprintf_func) (info->stream, "%s$f0",
1846 need_comma ? "," : "");
1847 if (amask == 6)
1848 (*info->fprintf_func) (info->stream, "-$f1");
1849 }
1850 }
1851 break;
1852
1853 case 'm':
1854 case 'M':
1855 /* MIPS16e save/restore. */
1856 {
1857 int need_comma = 0;
1858 int amask, args, statics;
1859 int nsreg, smask;
1860 int framesz;
1861 int i, j;
1862
1863 l = l & 0x7f;
1864 if (use_extend)
1865 l |= extend << 16;
1866
1867 amask = (l >> 16) & 0xf;
1868 if (amask == MIPS16_ALL_ARGS)
1869 {
1870 args = 4;
1871 statics = 0;
1872 }
1873 else if (amask == MIPS16_ALL_STATICS)
1874 {
1875 args = 0;
1876 statics = 4;
1877 }
1878 else
1879 {
1880 args = amask >> 2;
1881 statics = amask & 3;
1882 }
1883
1884 if (args > 0) {
1885 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1886 if (args > 1)
1887 (*info->fprintf_func) (info->stream, "-%s",
1888 mips_gpr_names[4 + args - 1]);
1889 need_comma = 1;
1890 }
1891
1892 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1893 if (framesz == 0 && !use_extend)
1894 framesz = 128;
1895
1896 (*info->fprintf_func) (info->stream, "%s%d",
1897 need_comma ? "," : "",
1898 framesz);
1899
1900 if (l & 0x40) /* $ra */
1901 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1902
1903 nsreg = (l >> 24) & 0x7;
1904 smask = 0;
1905 if (l & 0x20) /* $s0 */
1906 smask |= 1 << 0;
1907 if (l & 0x10) /* $s1 */
1908 smask |= 1 << 1;
1909 if (nsreg > 0) /* $s2-$s8 */
1910 smask |= ((1 << nsreg) - 1) << 2;
1911
1912 /* Find first set static reg bit. */
1913 for (i = 0; i < 9; i++)
1914 {
1915 if (smask & (1 << i))
1916 {
1917 (*info->fprintf_func) (info->stream, ",%s",
1918 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1919 /* Skip over string of set bits. */
1920 for (j = i; smask & (2 << j); j++)
1921 continue;
1922 if (j > i)
1923 (*info->fprintf_func) (info->stream, "-%s",
1924 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1925 i = j + 1;
1926 }
1927 }
1928
1929 /* Statics $ax - $a3. */
1930 if (statics == 1)
1931 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1932 else if (statics > 0)
1933 (*info->fprintf_func) (info->stream, ",%s-%s",
1934 mips_gpr_names[7 - statics + 1],
1935 mips_gpr_names[7]);
1936 }
1937 break;
1938
1939 default:
1940 /* xgettext:c-format */
1941 (*info->fprintf_func)
1942 (info->stream,
1943 _("# internal disassembler error, unrecognised modifier (%c)"),
1944 type);
1945 abort ();
1946 }
1947 }
1948
1949 /* Disassemble mips16 instructions. */
1950
1951 static int
1952 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1953 {
1954 int status;
1955 bfd_byte buffer[2];
1956 int length;
1957 int insn;
1958 bfd_boolean use_extend;
1959 int extend = 0;
1960 const struct mips_opcode *op, *opend;
1961
1962 info->bytes_per_chunk = 2;
1963 info->display_endian = info->endian;
1964 info->insn_info_valid = 1;
1965 info->branch_delay_insns = 0;
1966 info->data_size = 0;
1967 info->insn_type = dis_nonbranch;
1968 info->target = 0;
1969 info->target2 = 0;
1970
1971 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1972 if (status != 0)
1973 {
1974 (*info->memory_error_func) (status, memaddr, info);
1975 return -1;
1976 }
1977
1978 length = 2;
1979
1980 if (info->endian == BFD_ENDIAN_BIG)
1981 insn = bfd_getb16 (buffer);
1982 else
1983 insn = bfd_getl16 (buffer);
1984
1985 /* Handle the extend opcode specially. */
1986 use_extend = FALSE;
1987 if ((insn & 0xf800) == 0xf000)
1988 {
1989 use_extend = TRUE;
1990 extend = insn & 0x7ff;
1991
1992 memaddr += 2;
1993
1994 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1995 if (status != 0)
1996 {
1997 (*info->fprintf_func) (info->stream, "extend 0x%x",
1998 (unsigned int) extend);
1999 (*info->memory_error_func) (status, memaddr, info);
2000 return -1;
2001 }
2002
2003 if (info->endian == BFD_ENDIAN_BIG)
2004 insn = bfd_getb16 (buffer);
2005 else
2006 insn = bfd_getl16 (buffer);
2007
2008 /* Check for an extend opcode followed by an extend opcode. */
2009 if ((insn & 0xf800) == 0xf000)
2010 {
2011 (*info->fprintf_func) (info->stream, "extend 0x%x",
2012 (unsigned int) extend);
2013 info->insn_type = dis_noninsn;
2014 return length;
2015 }
2016
2017 length += 2;
2018 }
2019
2020 /* FIXME: Should probably use a hash table on the major opcode here. */
2021
2022 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2023 for (op = mips16_opcodes; op < opend; op++)
2024 {
2025 if (op->pinfo != INSN_MACRO
2026 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2027 && (insn & op->mask) == op->match)
2028 {
2029 const char *s;
2030
2031 if (strchr (op->args, 'a') != NULL)
2032 {
2033 if (use_extend)
2034 {
2035 (*info->fprintf_func) (info->stream, "extend 0x%x",
2036 (unsigned int) extend);
2037 info->insn_type = dis_noninsn;
2038 return length - 2;
2039 }
2040
2041 use_extend = FALSE;
2042
2043 memaddr += 2;
2044
2045 status = (*info->read_memory_func) (memaddr, buffer, 2,
2046 info);
2047 if (status == 0)
2048 {
2049 use_extend = TRUE;
2050 if (info->endian == BFD_ENDIAN_BIG)
2051 extend = bfd_getb16 (buffer);
2052 else
2053 extend = bfd_getl16 (buffer);
2054 length += 2;
2055 }
2056 }
2057
2058 (*info->fprintf_func) (info->stream, "%s", op->name);
2059 if (op->args[0] != '\0')
2060 (*info->fprintf_func) (info->stream, "\t");
2061
2062 for (s = op->args; *s != '\0'; s++)
2063 {
2064 if (*s == ','
2065 && s[1] == 'w'
2066 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2067 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2068 {
2069 /* Skip the register and the comma. */
2070 ++s;
2071 continue;
2072 }
2073 if (*s == ','
2074 && s[1] == 'v'
2075 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2076 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2077 {
2078 /* Skip the register and the comma. */
2079 ++s;
2080 continue;
2081 }
2082 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2083 info);
2084 }
2085
2086 /* Figure out branch instruction type and delay slot information. */
2087 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2088 info->branch_delay_insns = 1;
2089 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2090 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2091 {
2092 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2093 info->insn_type = dis_jsr;
2094 else
2095 info->insn_type = dis_branch;
2096 }
2097 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2098 info->insn_type = dis_condbranch;
2099
2100 return length;
2101 }
2102 }
2103
2104 if (use_extend)
2105 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2106 (*info->fprintf_func) (info->stream, "0x%x", insn);
2107 info->insn_type = dis_noninsn;
2108
2109 return length;
2110 }
2111
2112 /* In an environment where we do not know the symbol type of the
2113 instruction we are forced to assume that the low order bit of the
2114 instructions' address may mark it as a mips16 instruction. If we
2115 are single stepping, or the pc is within the disassembled function,
2116 this works. Otherwise, we need a clue. Sometimes. */
2117
2118 static int
2119 _print_insn_mips (bfd_vma memaddr,
2120 struct disassemble_info *info,
2121 enum bfd_endian endianness)
2122 {
2123 bfd_byte buffer[INSNLEN];
2124 int status;
2125
2126 set_default_mips_dis_options (info);
2127 parse_mips_dis_options (info->disassembler_options);
2128
2129 #if 1
2130 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2131 /* Only a few tools will work this way. */
2132 if (memaddr & 0x01)
2133 return print_insn_mips16 (memaddr, info);
2134 #endif
2135
2136 #if SYMTAB_AVAILABLE
2137 if (info->mach == bfd_mach_mips16
2138 || (info->symbols != NULL
2139 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2140 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2141 ->internal_elf_sym.st_other)))
2142 return print_insn_mips16 (memaddr, info);
2143 #endif
2144
2145 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2146 if (status == 0)
2147 {
2148 unsigned long insn;
2149
2150 if (endianness == BFD_ENDIAN_BIG)
2151 insn = (unsigned long) bfd_getb32 (buffer);
2152 else
2153 insn = (unsigned long) bfd_getl32 (buffer);
2154
2155 return print_insn_mips (memaddr, insn, info);
2156 }
2157 else
2158 {
2159 (*info->memory_error_func) (status, memaddr, info);
2160 return -1;
2161 }
2162 }
2163
2164 int
2165 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2166 {
2167 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2168 }
2169
2170 int
2171 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2172 {
2173 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2174 }
2175 \f
2176 void
2177 print_mips_disassembler_options (FILE *stream)
2178 {
2179 unsigned int i;
2180
2181 fprintf (stream, _("\n\
2182 The following MIPS specific disassembler options are supported for use\n\
2183 with the -M switch (multiple options should be separated by commas):\n"));
2184
2185 fprintf (stream, _("\n\
2186 gpr-names=ABI Print GPR names according to specified ABI.\n\
2187 Default: based on binary being disassembled.\n"));
2188
2189 fprintf (stream, _("\n\
2190 fpr-names=ABI Print FPR names according to specified ABI.\n\
2191 Default: numeric.\n"));
2192
2193 fprintf (stream, _("\n\
2194 cp0-names=ARCH Print CP0 register names according to\n\
2195 specified architecture.\n\
2196 Default: based on binary being disassembled.\n"));
2197
2198 fprintf (stream, _("\n\
2199 hwr-names=ARCH Print HWR names according to specified \n\
2200 architecture.\n\
2201 Default: based on binary being disassembled.\n"));
2202
2203 fprintf (stream, _("\n\
2204 reg-names=ABI Print GPR and FPR names according to\n\
2205 specified ABI.\n"));
2206
2207 fprintf (stream, _("\n\
2208 reg-names=ARCH Print CP0 register and HWR names according to\n\
2209 specified architecture.\n"));
2210
2211 fprintf (stream, _("\n\
2212 For the options above, the following values are supported for \"ABI\":\n\
2213 "));
2214 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2215 fprintf (stream, " %s", mips_abi_choices[i].name);
2216 fprintf (stream, _("\n"));
2217
2218 fprintf (stream, _("\n\
2219 For the options above, The following values are supported for \"ARCH\":\n\
2220 "));
2221 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2222 if (*mips_arch_choices[i].name != '\0')
2223 fprintf (stream, " %s", mips_arch_choices[i].name);
2224 fprintf (stream, _("\n"));
2225
2226 fprintf (stream, _("\n"));
2227 }
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