opcodes/or32-opc.c

   1 /* Table of opcodes for the OpenRISC 1000 ISA.
   2    Copyright 2002 Free Software Foundation, Inc.
   3    Contributed by Damjan Lampret (lampret@opencores.org).
   4
   5    This file is part of gen_or1k_isa, or1k, GDB and GAS.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 /* We treat all letters the same in encode/decode routines so
  22    we need to assign some characteristics to them like signess etc.  */
  23 #include <string.h>
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "safe-ctype.h"
  27 #include "ansidecl.h"
  28 #ifdef HAVE_CONFIG_H
  29 # include "config.h"
  30 #endif
  31 #include "opcode/or32.h"
  32
  33 static unsigned long           insn_extract         PARAMS ((char, char *));
  34 static unsigned long *         cover_insn           PARAMS ((unsigned long *, int, unsigned int));
  35 static int                     num_ones             PARAMS ((unsigned long));
  36 static struct insn_op_struct * parse_params         PARAMS ((const struct or32_opcode *, struct insn_op_struct *));
  37 static unsigned long           or32_extract         PARAMS ((char, char *, unsigned long));
  38 static void                    or32_print_register  PARAMS ((char, char *, unsigned long));
  39 static void                    or32_print_immediate PARAMS ((char, char *, unsigned long));
  40 static unsigned long           extend_imm           PARAMS ((unsigned long, char));
  41
  42 const struct or32_letter or32_letters[] =
  43   {
  44     { 'A', NUM_UNSIGNED },
  45     { 'B', NUM_UNSIGNED },
  46     { 'D', NUM_UNSIGNED },
  47     { 'I', NUM_SIGNED },
  48     { 'K', NUM_UNSIGNED },
  49     { 'L', NUM_UNSIGNED },
  50     { 'N', NUM_SIGNED },
  51     { '0', NUM_UNSIGNED },
  52     { '\0', 0 }     /* Dummy entry.  */
  53   };
  54
  55 /* Opcode encoding:
  56    machine[31:30]: first two bits of opcode
  57                    00 - neither of source operands is GPR
  58                    01 - second source operand is GPR (rB)
  59                    10 - first source operand is GPR (rA)
  60                    11 - both source operands are GPRs (rA and rB)
  61    machine[29:26]: next four bits of opcode
  62    machine[25:00]: instruction operands (specific to individual instruction)
  63
  64   Recommendation: irrelevant instruction bits should be set with a value of
  65   bits in same positions of instruction preceding current instruction in the
  66   code (when assembling).  */
  67
  68 #define EFN &l_none
  69
  70 #ifdef HAS_EXECUTION
  71 #define EF(func) &(func)
  72 #define EFI &l_invalid
  73 #else  /* HAS_EXECUTION */
  74 #define EF(func) EFN
  75 #define EFI EFN
  76 #endif /* HAS_EXECUTION */
  77
  78 const struct or32_opcode or32_opcodes[] =
  79   {
  80     { "l.j",       "N",            "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
  81     { "l.jal",     "N",            "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
  82     { "l.bnf",     "N",            "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
  83     { "l.bf",      "N",            "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
  84     { "l.nop",     "K",            "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
  85     { "l.movhi",   "rD,K",         "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
  86     { "l.macrc",   "rD",           "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
  87
  88     { "l.sys",     "K",            "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
  89     { "l.trap",    "K",            "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
  90     { "l.msync",   "",             "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0 },
  91     { "l.psync",   "",             "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0 },
  92     { "l.csync",   "",             "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0 },
  93     { "l.rfe",     "",             "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
  94
  95     { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
  96     { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
  97     { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
  98     { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
  99     { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
 100     { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
 101     { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
 102     { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
 103     { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
 104     { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
 105     { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
 106     { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
 107     { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
 108     { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
 109     { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
 110     { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
 111     { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
 112     { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
 113     { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
 114     { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
 115     { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
 116     { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
 117     { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
 118     { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
 119     { "lv.add.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
 120     { "lv.add.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
 121     { "lv.adds.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
 122     { "lv.adds.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
 123     { "lv.addu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
 124     { "lv.addu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
 125     { "lv.addus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
 126     { "lv.addus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
 127     { "lv.and",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
 128     { "lv.avg.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
 129     { "lv.avg.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
 130     { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
 131     { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
 132     { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
 133     { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
 134     { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
 135     { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
 136     { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
 137     { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
 138     { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
 139     { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
 140     { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
 141     { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
 142     { "lv.madds.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
 143     { "lv.max.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
 144     { "lv.max.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
 145     { "lv.merge.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
 146     { "lv.merge.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
 147     { "lv.min.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
 148     { "lv.min.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
 149     { "lv.msubs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
 150     { "lv.muls.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
 151     { "lv.nand",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
 152     { "lv.nor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
 153     { "lv.or",     "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
 154     { "lv.pack.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
 155     { "lv.pack.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
 156     { "lv.packs.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
 157     { "lv.packs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
 158     { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
 159     { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
 160     { "lv.perm.n", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
 161     { "lv.rl.b",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
 162     { "lv.rl.h",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
 163     { "lv.sll.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
 164     { "lv.sll.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
 165     { "lv.sll",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
 166     { "lv.srl.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
 167     { "lv.srl.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
 168     { "lv.sra.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
 169     { "lv.sra.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
 170     { "lv.srl",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
 171     { "lv.sub.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
 172     { "lv.sub.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
 173     { "lv.subs.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
 174     { "lv.subs.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
 175     { "lv.subu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
 176     { "lv.subu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
 177     { "lv.subus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
 178     { "lv.subus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
 179     { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
 180     { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
 181     { "lv.xor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
 182     { "lv.cust1",  "",         "00 0xA  ----- ----- ---- ---- 0xC ----", EFI, 0 },
 183     { "lv.cust2",  "",         "00 0xA  ----- ----- ---- ---- 0xD ----", EFI, 0 },
 184     { "lv.cust3",  "",         "00 0xA  ----- ----- ---- ---- 0xE ----", EFI, 0 },
 185     { "lv.cust4",  "",         "00 0xA  ----- ----- ---- ---- 0xF ----", EFI, 0 },
 186
 187     { "lf.add.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
 188     { "lf.sub.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
 189     { "lf.mul.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
 190     { "lf.div.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
 191     { "lf.itof.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
 192     { "lf.ftoi.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
 193     { "lf.rem.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
 194     { "lf.madd.s",  "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
 195     { "lf.sfeq.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
 196     { "lf.sfne.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
 197     { "lf.sfgt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
 198     { "lf.sfge.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
 199     { "lf.sflt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
 200     { "lf.sfle.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
 201     { "lf.cust1.s", "",        "00 0xB  ----- ----- ---- ---- 0xE ----", EFI, 0 },
 202
 203     { "lf.add.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
 204     { "lf.sub.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
 205     { "lf.mul.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
 206     { "lf.div.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
 207     { "lf.itof.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
 208     { "lf.ftoi.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
 209     { "lf.rem.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
 210     { "lf.madd.d",  "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
 211     { "lf.sfeq.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
 212     { "lf.sfne.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
 213     { "lf.sfgt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
 214     { "lf.sfge.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
 215     { "lf.sflt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
 216     { "lf.sfle.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
 217     { "lf.cust1.d", "",        "00 0xC  ----- ----- ---- ---- 0xE ----", EFI, 0 },
 218
 219     { "lvf.ld",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
 220     { "lvf.lw",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
 221     { "lvf.sd",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
 222     { "lvf.sw",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
 223
 224     { "l.jr",      "rB",           "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
 225     { "l.jalr",    "rB",           "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
 226     { "l.maci",    "rB,I",         "01 0x3  IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
 227     { "l.cust1",   "",         "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
 228     { "l.cust2",   "",         "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
 229     { "l.cust3",   "",         "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
 230     { "l.cust4",   "",         "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
 231
 232     { "l.ld",      "rD,I(rA)",     "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
 233     { "l.lwz",     "rD,I(rA)",     "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
 234     { "l.lws",     "rD,I(rA)",     "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
 235     { "l.lbz",     "rD,I(rA)",     "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
 236     { "l.lbs",     "rD,I(rA)",     "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
 237     { "l.lhz",     "rD,I(rA)",     "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
 238     { "l.lhs",     "rD,I(rA)",     "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
 239
 240     { "l.addi",    "rD,rA,I",      "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
 241     { "l.addic",   "rD,rA,I",      "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
 242     { "l.andi",    "rD,rA,K",      "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
 243     { "l.ori",     "rD,rA,K",      "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0  },
 244     { "l.xori",    "rD,rA,I",      "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
 245     { "l.muli",    "rD,rA,I",      "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
 246     { "l.mfspr",   "rD,rA,K",      "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
 247     { "l.slli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
 248     { "l.srli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
 249     { "l.srai",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
 250     { "l.rori",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
 251
 252     { "l.sfeqi",   "rA,I",         "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
 253     { "l.sfnei",   "rA,I",         "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
 254     { "l.sfgtui",  "rA,I",         "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
 255     { "l.sfgeui",  "rA,I",         "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
 256     { "l.sfltui",  "rA,I",         "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
 257     { "l.sfleui",  "rA,I",         "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
 258     { "l.sfgtsi",  "rA,I",         "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
 259     { "l.sfgesi",  "rA,I",         "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
 260     { "l.sfltsi",  "rA,I",         "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
 261     { "l.sflesi",  "rA,I",         "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
 262
 263     { "l.mtspr",   "rA,rB,K",      "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
 264     { "l.mac",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
 265     { "l.msb",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
 266
 267     { "l.sd",      "I(rA),rB",     "11 0x4  IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
 268     { "l.sw",      "I(rA),rB",     "11 0x5  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
 269     { "l.sb",      "I(rA),rB",     "11 0x6  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
 270     { "l.sh",      "I(rA),rB",     "11 0x7  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
 271
 272     { "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
 273     { "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
 274     { "l.sub",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
 275     { "l.and",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
 276     { "l.or",      "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
 277     { "l.xor",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
 278     { "l.mul",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
 279
 280     { "l.sll",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
 281     { "l.srl",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
 282     { "l.sra",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
 283     { "l.ror",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
 284     { "l.div",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
 285     { "l.divu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
 286     { "l.mulu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
 287     { "l.exths",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
 288     { "l.extbs",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
 289     { "l.exthz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
 290     { "l.extbz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
 291     { "l.extws",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
 292     { "l.extwz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
 293     { "l.cmov",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
 294     { "l.ff1",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
 295
 296     { "l.sfeq",    "rA,rB",        "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
 297     { "l.sfne",    "rA,rB",        "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
 298     { "l.sfgtu",   "rA,rB",        "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
 299     { "l.sfgeu",   "rA,rB",        "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
 300     { "l.sfltu",   "rA,rB",        "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
 301     { "l.sfleu",   "rA,rB",        "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
 302     { "l.sfgts",   "rA,rB",        "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
 303     { "l.sfges",   "rA,rB",        "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
 304     { "l.sflts",   "rA,rB",        "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
 305     { "l.sfles",   "rA,rB",        "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
 306
 307     { "l.cust5",   "",         "11 0xC  ----- ----- ---- ---- ---- ----", EFI, 0 },
 308     { "l.cust6",   "",         "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0 },
 309     { "l.cust7",   "",         "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0 },
 310     { "l.cust8",   "",         "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0 },
 311
 312     /* This section should not be defined in or1ksim, since it contains duplicates,
 313        which would cause machine builder to complain.  */
 314 #ifdef HAS_CUST
 315     { "l.cust5_1",   "rD",             "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
 316     { "l.cust5_2",   "rD,rA"   ,   "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
 317     { "l.cust5_3",   "rD,rA,rB",   "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 318
 319     { "l.cust6_1",   "rD",             "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
 320     { "l.cust6_2",   "rD,rA"   ,   "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
 321     { "l.cust6_3",   "rD,rA,rB",   "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 322
 323     { "l.cust7_1",   "rD",             "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
 324     { "l.cust7_2",   "rD,rA"   ,   "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
 325     { "l.cust7_3",   "rD,rA,rB",   "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 326
 327     { "l.cust8_1",   "rD",             "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
 328     { "l.cust8_2",   "rD,rA"   ,   "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
 329     { "l.cust8_3",   "rD,rA,rB",   "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 330 #endif
 331
 332     /* Dummy entry, not included in num_opcodes.  This
 333        lets code examine entry i+1 without checking
 334        if we've run off the end of the table.  */
 335     { "", "", "", EFI, 0 }
 336 };
 337
 338 #undef EFI
 339 #undef EFN
 340 #undef EF
 341
 342 /* Define dummy, if debug is not defined.  */
 343
 344 #if !defined HAS_DEBUG
 345 static void debug PARAMS ((int, const char *, ...));
 346
 347 static void
 348 debug (int level, const char *format, ...)
 349 {
 350   /* Just to get rid of warnings.  */
 351   format = level = 0;
 352 }
 353 #endif
 354
 355 const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
 356
 357 /* Calculates instruction length in bytes. Always 4 for OR32.  */
 358
 359 int
 360 insn_len (insn_index)
 361      int insn_index ATTRIBUTE_UNUSED;
 362 {
 363   return 4;
 364 }
 365
 366 /* Is individual insn's operand signed or unsigned?  */
 367
 368 int
 369 letter_signed (l)
 370      char l;
 371 {
 372   const struct or32_letter *pletter;
 373
 374   for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
 375     if (pletter->letter == l)
 376       return pletter->sign;
 377
 378   printf ("letter_signed(%c): Unknown letter.\n", l);
 379   return 0;
 380 }
 381
 382 /* Number of letters in the individual lettered operand.  */
 383
 384 int
 385 letter_range (l)
 386      char l;
 387 {
 388   const struct or32_opcode *pinsn;
 389   char *enc;
 390   int range = 0;
 391
 392   for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
 393     {
 394       if (strchr (pinsn->encoding,l))
 395         {
 396           for (enc = pinsn->encoding; *enc != '\0'; enc++)
 397             if ((*enc == '0') && (*(enc+1) == 'x'))
 398               enc += 2;
 399             else if (*enc == l)
 400               range++;
 401           return range;
 402         }
 403     }
 404
 405   printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
 406   exit (1);
 407 }
 408
 409 /* MM: Returns index of given instruction name.  */
 410
 411 int
 412 insn_index (char *insn)
 413 {
 414   int i, found = -1;
 415
 416   for (i = 0; i < or32_num_opcodes; i++)
 417     if (!strcmp (or32_opcodes[i].name, insn))
 418       {
 419         found = i;
 420         break;
 421       }
 422   return found;
 423 }
 424
 425 const char *
 426 insn_name (index)
 427      int index;
 428 {
 429   if (index >= 0 && index < or32_num_opcodes)
 430     return or32_opcodes[index].name;
 431   else
 432     return "???";
 433 }
 434
 435 void
 436 l_none ()
 437 {
 438 }
 439
 440 /* Finite automata for instruction decoding building code.  */
 441
 442 /* Find simbols in encoding.  */
 443 static unsigned long
 444 insn_extract (param_ch, enc_initial)
 445      char param_ch;
 446      char *enc_initial;
 447 {
 448   char *enc;
 449   unsigned long ret = 0;
 450   unsigned opc_pos = 32;
 451
 452   for (enc = enc_initial; *enc != '\0'; )
 453     if ((*enc == '0') && (*(enc + 1) == 'x'))
 454       {
 455         unsigned long tmp = strtol (enc+2, NULL, 16);
 456
 457         opc_pos -= 4;
 458         if (param_ch == '0' || param_ch == '1')
 459           {
 460             if (param_ch == '0')
 461               tmp = 15 - tmp;
 462             ret |= tmp << opc_pos;
 463           }
 464         enc += 3;
 465       }
 466     else
 467       {
 468         if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
 469           {
 470             opc_pos--;
 471             if (param_ch == *enc)
 472               ret |= 1 << opc_pos;
 473           }
 474         enc++;
 475       }
 476   return ret;
 477 }
 478
 479 #define MAX_AUTOMATA_SIZE (1200)
 480 #define MAX_OP_TABLE_SIZE (1200)
 481 #define LEAF_FLAG         (0x80000000)
 482 #define MAX_LEN           (8)
 483
 484 #ifndef MIN
 485 # define MIN(x,y)          ((x) < (y) ? (x) : (y))
 486 #endif
 487
 488 unsigned long *automata;
 489 int nuncovered;
 490 int curpass = 0;
 491
 492 /* MM: Struct that hold runtime build information about instructions.  */
 493 struct temp_insn_struct
 494 {
 495   unsigned long insn;
 496   unsigned long insn_mask;
 497   int in_pass;
 498 } *ti;
 499
 500 struct insn_op_struct *op_data, **op_start;
 501
 502 /* Recursive utility function used to find best match and to build automata.  */
 503
 504 static unsigned long *
 505 cover_insn (cur, pass, mask)
 506      unsigned long * cur;
 507      int pass;
 508      unsigned int mask;
 509 {
 510   int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
 511   unsigned long cur_mask = mask;
 512   unsigned long *next;
 513
 514   for (i = 0; i < or32_num_opcodes; i++)
 515     if (ti[i].in_pass == pass)
 516       {
 517         cur_mask &= ti[i].insn_mask;
 518         ninstr++;
 519         last_match = i;
 520       }
 521
 522   debug (8, "%08X %08X\n", mask, cur_mask);
 523
 524   if (ninstr == 0)
 525     return 0;
 526
 527   if (ninstr == 1)
 528     {
 529       /* Leaf holds instruction index.  */
 530       debug (8, "%i>I%i %s\n",
 531              cur - automata, last_match, or32_opcodes[last_match].name);
 532
 533       *cur = LEAF_FLAG | last_match;
 534       cur++;
 535       nuncovered--;
 536     }
 537   else
 538     {
 539       /* Find longest match.  */
 540       for (i = 0; i < 32; i++)
 541         {
 542           int len;
 543
 544           for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
 545             {
 546               unsigned long m = (1UL << ((unsigned long)len)) - 1;
 547
 548               debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
 549                      len,m, cur_mask, i, (cur_mask >> (unsigned)i),
 550                      (cur_mask >> (unsigned)i) & m);
 551
 552               if ((m & (cur_mask >> (unsigned)i)) == m)
 553                 {
 554                   best_len = len;
 555                   best_first = i;
 556                   debug (9, "!");
 557                 }
 558               else
 559                 break;
 560             }
 561         }
 562
 563       debug (9, "\n");
 564
 565       if (!best_len)
 566         {
 567           fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
 568
 569           for (i = 0; i < or32_num_opcodes; i++)
 570             if (ti[i].in_pass == pass)
 571               fprintf (stderr, "%s ", or32_opcodes[i].name);
 572
 573           fprintf (stderr, "\n");
 574           exit (1);
 575         }
 576
 577       debug (8, "%i> #### %i << %i (%i) ####\n",
 578              cur - automata, best_len, best_first, ninstr);
 579
 580       *cur = best_first;
 581       cur++;
 582       *cur = (1 << best_len) - 1;
 583       cur++;
 584       next = cur;
 585
 586       /* Allocate space for pointers.  */
 587       cur += 1 << best_len;
 588       cur_mask = (1 << (unsigned long)best_len) - 1;
 589
 590       for (i = 0; i < (1 << (unsigned long)best_len); i++)
 591         {
 592           int j;
 593           unsigned long *c;
 594
 595           curpass++;
 596           for (j = 0; j < or32_num_opcodes; j++)
 597             if (ti[j].in_pass == pass
 598                 && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
 599                 && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
 600               ti[j].in_pass = curpass;
 601
 602           debug (9, "%08X %08X %i\n", mask, cur_mask, best_first);
 603           c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
 604           if (c)
 605             {
 606               debug (8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
 607               *next = cur - automata;
 608               cur = c;
 609             }
 610           else
 611             {
 612               debug (8, "%i> N/A\n", next - automata);
 613               *next = 0;
 614             }
 615           next++;
 616         }
 617     }
 618   return cur;
 619 }
 620
 621 /* Returns number of nonzero bits.  */
 622
 623 static int
 624 num_ones (value)
 625      unsigned long value;
 626 {
 627   int c = 0;
 628
 629   while (value)
 630     {
 631       if (value & 1)
 632         c++;
 633       value >>= 1;
 634     }
 635   return c;
 636 }
 637
 638 /* Utility function, which converts parameters from or32_opcode format to more binary form.
 639    Parameters are stored in ti struct.  */
 640
 641 static struct insn_op_struct *
 642 parse_params (opcode, cur)
 643      const struct or32_opcode * opcode;
 644      struct insn_op_struct * cur;
 645 {
 646   char *args = opcode->args;
 647   int i, type;
 648
 649   i = 0;
 650   type = 0;
 651   /* In case we don't have any parameters, we add dummy read from r0.  */
 652
 653   if (!(*args))
 654     {
 655       cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
 656       cur->data = 0;
 657       debug (9, "#%08X %08X\n", cur->type, cur->data);
 658       cur++;
 659       return cur;
 660   }
 661
 662   while (*args != '\0')
 663     {
 664       if (*args == 'r')
 665         {
 666           args++;
 667           type |= OPTYPE_REG;
 668         }
 669       else if (ISALPHA (*args))
 670         {
 671           unsigned long arg;
 672
 673           arg = insn_extract (*args, opcode->encoding);
 674           debug (9, "%s : %08X ------\n", opcode->name, arg);
 675           if (letter_signed (*args))
 676             {
 677               type |= OPTYPE_SIG;
 678               type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
 679             }
 680
 681           /* Split argument to sequences of consecutive ones.  */
 682           while (arg)
 683             {
 684               int shr = 0;
 685               unsigned long tmp = arg, mask = 0;
 686
 687               while ((tmp & 1) == 0)
 688                 {
 689                   shr++;
 690                   tmp >>= 1;
 691                 }
 692               while (tmp & 1)
 693                 {
 694                   mask++;
 695                   tmp >>= 1;
 696                 }
 697               cur->type = type | shr;
 698               cur->data = mask;
 699               arg &= ~(((1 << mask) - 1) << shr);
 700               debug (6, "|%08X %08X\n", cur->type, cur->data);
 701               cur++;
 702             }
 703           args++;
 704         }
 705       else if (*args == '(')
 706         {
 707           /* Next param is displacement.  Later we will treat them as one operand.  */
 708           cur--;
 709           cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
 710           debug (9, ">%08X %08X\n", cur->type, cur->data);
 711           cur++;
 712           type = 0;
 713           i++;
 714           args++;
 715         }
 716       else if (*args == OPERAND_DELIM)
 717         {
 718           cur--;
 719           cur->type = type | cur->type | OPTYPE_OP;
 720           debug (9, ">%08X %08X\n", cur->type, cur->data);
 721           cur++;
 722           type = 0;
 723           i++;
 724           args++;
 725         }
 726       else if (*args == '0')
 727         {
 728           cur->type = type;
 729           cur->data = 0;
 730           debug (9, ">%08X %08X\n", cur->type, cur->data);
 731           cur++;
 732           type = 0;
 733           i++;
 734           args++;
 735         }
 736       else if (*args == ')')
 737         args++;
 738       else
 739         {
 740           fprintf (stderr, "%s : parse error in args.\n", opcode->name);
 741           exit (1);
 742         }
 743     }
 744
 745   cur--;
 746   cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
 747   debug (9, "#%08X %08X\n", cur->type, cur->data);
 748   cur++;
 749
 750   return cur;
 751 }
 752
 753 /* Constructs new automata based on or32_opcodes array.  */
 754
 755 void
 756 build_automata ()
 757 {
 758   int i;
 759   unsigned long *end;
 760   struct insn_op_struct *cur;
 761
 762   automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
 763   ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
 764
 765   nuncovered = or32_num_opcodes;
 766   printf ("Building automata... ");
 767   /* Build temporary information about instructions.  */
 768   for (i = 0; i < or32_num_opcodes; i++)
 769     {
 770       unsigned long ones, zeros;
 771       char *encoding = or32_opcodes[i].encoding;
 772
 773       ones  = insn_extract('1', encoding);
 774       zeros = insn_extract('0', encoding);
 775
 776       ti[i].insn_mask = ones | zeros;
 777       ti[i].insn = ones;
 778       ti[i].in_pass = curpass = 0;
 779
 780       /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
 781         or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
 782     }
 783
 784   /* Until all are covered search for best criteria to separate them.  */
 785   end = cover_insn (automata, curpass, 0xFFFFFFFF);
 786
 787   if (end - automata > MAX_AUTOMATA_SIZE)
 788     {
 789       fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
 790       exit (1);
 791     }
 792
 793   printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
 794   printf ("Parsing operands data... ");
 795
 796   op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
 797   op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
 798   cur = op_data;
 799
 800   for (i = 0; i < or32_num_opcodes; i++)
 801     {
 802       op_start[i] = cur;
 803       cur = parse_params (&or32_opcodes[i], cur);
 804
 805       if (cur - op_data > MAX_OP_TABLE_SIZE)
 806         {
 807           fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
 808           exit (1);
 809         }
 810     }
 811   printf ("done.\n");
 812 }
 813
 814 void
 815 destruct_automata ()
 816 {
 817   free (ti);
 818   free (automata);
 819   free (op_data);
 820   free (op_start);
 821 }
 822
 823 /* Decodes instruction and returns instruction index.  */
 824
 825 int
 826 insn_decode (insn)
 827      unsigned int insn;
 828 {
 829   unsigned long *a = automata;
 830   int i;
 831
 832   while (!(*a & LEAF_FLAG))
 833     {
 834       unsigned int first = *a;
 835
 836       debug (9, "%i ", a - automata);
 837
 838       a++;
 839       i = (insn >> first) & *a;
 840       a++;
 841       if (!*(a + i))
 842         {
 843           /* Invalid instruction found?  */
 844           debug (9, "XXX\n", i);
 845           return -1;
 846         }
 847       a = automata + *(a + i);
 848     }
 849
 850   i = *a & ~LEAF_FLAG;
 851
 852   debug (9, "%i\n", i);
 853
 854   /* Final check - do we have direct match?
 855      (based on or32_opcodes this should be the only possibility,
 856      but in case of invalid/missing instruction we must perform a check)  */
 857   if ((ti[i].insn_mask & insn) == ti[i].insn)
 858     return i;
 859   else
 860     return -1;
 861 }
 862
 863 static char disassembled_str[50];
 864 char *disassembled = &disassembled_str[0];
 865
 866 /* Automagically does zero- or sign- extension and also finds correct
 867    sign bit position if sign extension is correct extension. Which extension
 868    is proper is figured out from letter description.  */
 869
 870 static unsigned long
 871 extend_imm (imm, l)
 872      unsigned long imm;
 873      char l;
 874 {
 875   unsigned long mask;
 876   int letter_bits;
 877
 878   /* First truncate all bits above valid range for this letter
 879      in case it is zero extend.  */
 880   letter_bits = letter_range (l);
 881   mask = (1 << letter_bits) - 1;
 882   imm &= mask;
 883
 884   /* Do sign extend if this is the right one.  */
 885   if (letter_signed(l) && (imm >> (letter_bits - 1)))
 886     imm |= (~mask);
 887
 888   return imm;
 889 }
 890
 891 static unsigned long
 892 or32_extract (param_ch, enc_initial, insn)
 893      char param_ch;
 894      char *enc_initial;
 895      unsigned long insn;
 896 {
 897   char *enc;
 898   unsigned long ret = 0;
 899   int opc_pos = 0;
 900   int param_pos = 0;
 901
 902   for (enc = enc_initial; *enc != '\0'; enc++)
 903     if (*enc == param_ch)
 904       {
 905         if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
 906           continue;
 907         else
 908           param_pos++;
 909       }
 910
 911 #if DEBUG
 912   printf ("or32_extract: %x ", param_pos);
 913 #endif
 914   opc_pos = 32;
 915
 916   for (enc = enc_initial; *enc != '\0'; )
 917     if ((*enc == '0') && (*(enc + 1) == 'x'))
 918       {
 919         opc_pos -= 4;
 920         if ((param_ch == '0') || (param_ch == '1'))
 921           {
 922             unsigned long tmp = strtol (enc, NULL, 16);
 923 #if DEBUG
 924             printf (" enc=%s, tmp=%x ", enc, tmp);
 925 #endif
 926             if (param_ch == '0')
 927               tmp = 15 - tmp;
 928             ret |= tmp << opc_pos;
 929           }
 930         enc += 3;
 931       }
 932     else if ((*enc == '0') || (*enc == '1'))
 933       {
 934         opc_pos--;
 935         if (param_ch == *enc)
 936           ret |= 1 << opc_pos;
 937         enc++;
 938       }
 939     else if (*enc == param_ch)
 940       {
 941         opc_pos--;
 942         param_pos--;
 943 #if DEBUG
 944         printf ("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
 945 #endif
 946         if (ISLOWER (param_ch))
 947           ret -= ((insn >> opc_pos) & 0x1) << param_pos;
 948         else
 949           ret += ((insn >> opc_pos) & 0x1) << param_pos;
 950         enc++;
 951       }
 952     else if (ISALPHA (*enc))
 953       {
 954         opc_pos--;
 955         enc++;
 956       }
 957     else if (*enc == '-')
 958       {
 959         opc_pos--;
 960         enc++;
 961       }
 962     else
 963       enc++;
 964
 965 #if DEBUG
 966   printf ("ret=%x\n", ret);
 967 #endif
 968   return ret;
 969 }
 970
 971 /* Print register. Used only by print_insn.  */
 972
 973 static void
 974 or32_print_register (param_ch, encoding, insn)
 975      char param_ch;
 976      char *encoding;
 977      unsigned long insn;
 978 {
 979   int regnum = or32_extract(param_ch, encoding, insn);
 980
 981   sprintf (disassembled, "%sr%d", disassembled, regnum);
 982 }
 983
 984 /* Print immediate. Used only by print_insn.  */
 985
 986 static void
 987 or32_print_immediate (param_ch, encoding, insn)
 988      char param_ch;
 989      char *encoding;
 990      unsigned long insn;
 991 {
 992   int imm = or32_extract (param_ch, encoding, insn);
 993
 994   imm = extend_imm (imm, param_ch);
 995
 996   if (letter_signed (param_ch))
 997     {
 998       if (imm < 0)
 999         sprintf (disassembled, "%s%d", disassembled, imm);
1000       else
1001         sprintf (disassembled, "%s0x%x", disassembled, imm);
1002     }
1003   else
1004     sprintf (disassembled, "%s%#x", disassembled, imm);
1005 }
1006
1007 /* Disassemble one instruction from insn to disassemble.
1008    Return the size of the instruction.  */
1009
1010 int
1011 disassemble_insn (insn)
1012      unsigned long insn;
1013 {
1014   int index;
1015   index = insn_decode (insn);
1016
1017   if (index >= 0)
1018     {
1019       struct or32_opcode const *opcode = &or32_opcodes[index];
1020       char *s;
1021
1022       sprintf (disassembled, "%s ", opcode->name);
1023       for (s = opcode->args; *s != '\0'; ++s)
1024         {
1025           switch (*s)
1026             {
1027             case '\0':
1028               return 4;
1029
1030             case 'r':
1031               or32_print_register (*++s, opcode->encoding, insn);
1032               break;
1033
1034             default:
1035               if (strchr (opcode->encoding, *s))
1036                 or32_print_immediate (*s, opcode->encoding, insn);
1037               else
1038                 sprintf (disassembled, "%s%c", disassembled, *s);
1039             }
1040         }
1041     }
1042   else
1043     {
1044       /* This used to be %8x for binutils.  */
1045       sprintf (disassembled, "%s.word 0x%08lx", disassembled, insn);
1046     }
1047
1048   return insn_len (insn);
1049 }